diff --git a/.editorconfig b/.editorconfig
deleted file mode 100644
index 2a9c5c8c5..000000000
--- a/.editorconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-root = true
-
-[src/**.sv]
-indent_style = space
-indent_size = 2
\ No newline at end of file
diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 000000000..3848b3e2a
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+pipelined/busybear_boot/* filter=lfs diff=lfs merge=lfs -text
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
deleted file mode 100644
index fe7eab6c8..000000000
--- a/.github/dependabot.yml
+++ /dev/null
@@ -1,21 +0,0 @@
-# To get started with Dependabot version updates, you'll need to specify which
-# package ecosystems to update and where the package manifests are located.
-# Please see the documentation for all configuration options:
-# https://docs.github.com/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file
-
-version: 2
-updates:
-  # Update git submodules to latest version
-  - package-ecosystem: "gitsubmodule"
-    directory: "/"
-    schedule:
-      interval: "weekly"
-    ignore:
-      - dependency-name: "addins/coremark"
-      - dependency-name: "addins/embench-iot"
-      - dependency-name: "addins/verilog-ethernet"
-  # Update actions in the GitHub Actions workflow files
-  - package-ecosystem: "github-actions"
-    directory: "/"
-    schedule:
-      interval: "weekly"
diff --git a/.github/scripts/cli-space-cleanup.sh b/.github/scripts/cli-space-cleanup.sh
deleted file mode 100755
index 0f8de1619..000000000
--- a/.github/scripts/cli-space-cleanup.sh
+++ /dev/null
@@ -1,65 +0,0 @@
-#!/bin/bash
-###########################################
-## GitHub runner space cleanup
-##
-## Written: Jordan Carlin, jcarlin@hmc.edu
-## Created: 30 June 2024
-## Modified:
-##
-## Purpose: Remove unnecessary packages/directories from GitHub Actions runner
-
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-# Remove unnecessary packages
-removePacks=( '^llvm-.*' 'php.*' '^mongodb-.*' '^mysql-.*' '^dotnet-sdk-.*' 'azure-cli' 'google-cloud-cli' 'google-chrome-stable' 'firefox' '^powershell*' 'microsoft-edge-stable' 'mono-devel' 'hhvm' )
-for pack in "${removePacks[@]}"; do
-  sudo apt-get purge -y "$pack" || true
-done
-sudo apt-get autoremove -y || true
-sudo apt-get clean || true
-
-# Remove unnecessary directories
-sudo rm -rf /usr/local/lib/android
-sudo rm -rf /usr/share/dotnet
-sudo rm -rf /usr/share/swift
-sudo rm -rf /usr/share/miniconda
-sudo rm -rf /usr/share/az*
-sudo rm -rf /usr/share/gradle-*
-sudo rm -rf /usr/share/sbt
-sudo rm -rf /opt/ghc
-sudo rm -rf /usr/local/.ghcup
-sudo rm -rf /usr/local/share/powershell
-sudo rm -rf /usr/local/lib/node_modules
-sudo rm -rf /usr/local/julia*
-sudo rm -rf /usr/local/share/chromium
-sudo rm -rf /usr/local/share/vcpkg
-sudo rm -rf /usr/local/games
-sudo rm -rf /usr/local/sqlpackage
-sudo rm -rf /usr/lib/google-cloud-sdk
-sudo rm -rf /usr/lib/jvm
-sudo rm -rf /usr/lib/mono
-sudo rm -rf /usr/lib/R
-sudo rm -rf /usr/lib/postgresql
-sudo rm -rf /usr/lib/heroku
-sudo rm -rf /usr/lib/firefox
-sudo rm -rf /opt/hostedtoolcache
-
-# Clean up docker images
-sudo docker image prune --all --force
diff --git a/.github/workflows/install.yml b/.github/workflows/install.yml
deleted file mode 100644
index 922d894c5..000000000
--- a/.github/workflows/install.yml
+++ /dev/null
@@ -1,183 +0,0 @@
-##################################
-# install.yml
-# jcarlin@hmc.edu October 2024
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# GitHub Action to test the wally-tool-chain-install.sh script for all supported linux distributions
-# and configurations. Runs weekly and on pull requests that modify the installation scripts.
-##################################
-
-name: Installation
-
-# Run on PR that modifies the installation scripts, weekly, or manually
-on:
-  workflow_dispatch:
-  pull_request:
-    branches:
-      - main
-    paths:
-      - 'bin/wally-tool-chain-install.sh'
-      - 'bin/wally-distro-check.sh'
-      - 'bin/wally-package-install.sh'
-      - '.github/workflows/install.yml'
-  schedule:
-    - cron: "0 7 * * 3" # Run at 12:00 AM Pacific Time on Wednesdays
-
-# Use bash shell with extra GitHub Actions options for all jobs
-defaults:
-  run:
-    shell: bash
-
-jobs:
-  installation_test:
-    name: Test installation for ${{ matrix.name }}
-    strategy:
-      fail-fast: false
-      matrix:
-        include:
-          # Ubuntu Installations
-          - name: ubuntu-20.04
-            image: ubuntu:20.04
-            imageFamily: debian
-            regressionFail: true
-          - name: ubuntu-22.04
-            image: ubuntu:22.04
-            imageFamily: debian
-          - name: ubuntu-24.04
-            image: ubuntu:24.04
-            imageFamily: debian
-          # Debian Installations
-          - name: debian-12
-            image: debian:12
-            imageFamily: debian
-          - name: debian-11
-            image: debian:11
-            imageFamily: debian
-          # Red Hat Installations
-          - name: rocky-8
-            image: rockylinux:8
-            imageFamily: redhat
-            regressionFail: true
-          - name: rocky-9
-            image: rockylinux:9
-            imageFamily: redhat
-          - name: almalinux-8
-            image: almalinux:8
-            imageFamily: redhat
-            regressionFail: true
-          - name: almalinux-9
-            image: almalinux:9
-            imageFamily: redhat
-          # SUSE Installations
-          - name: opensuse-15.6
-            image: opensuse/leap:15.6
-            imageFamily: suse
-          # User level installation
-          - name: user-install
-            image: null
-            user: true
-          # Custom location installation
-          - name: custom-install
-            image: null
-            riscv_path: /home/riscv
-          # Custom location user level installation
-          - name: custom-user-install
-            image: null
-            user: true
-            riscv_path: $HOME/riscv-toolchain
-
-    # run on selected version of ubuntu or on ubuntu-latest with docker image
-    runs-on: ubuntu-latest
-    container:
-      image: ${{ matrix.image }}
-      options: --privileged --mount type=bind,source=/,target=/host --pid=host --entrypoint /bin/bash # Allow for connection with host
-
-    steps:
-      # Docker images need git installed or the checkout action fails
-      - name: Install Dependencies for Container Image
-        if: ${{ matrix.image != null }}
-        run: |
-            if [ ${{ matrix.imageFamily }} == "debian" ]; then
-              apt-get update
-              apt-get install -y git
-            elif [ ${{ matrix.imageFamily }} == "redhat" ]; then
-              dnf install -y git
-              dnf install curl -y --allowerasing || true
-            elif [ ${{ matrix.imageFamily }} == "suse" ]; then
-              zypper install -y git
-            fi
-      # Only clone submodules needed for standard tests/regression to save space
-      - uses: actions/checkout@v4
-      - name: Clone Necessary Submodules
-        run: |
-              git config --global --add safe.directory '*'
-              git submodule update --init addins/riscv-arch-test addins/verilog-ethernet
-      # Free up space on the host machine, either from the container or the host
-      - name: Free Up Storage
-        run: |
-              df -h
-              if [ -z ${{ matrix.image }} ]; then
-                ./.github/scripts/cli-space-cleanup.sh
-              else
-                nsenter -t 1 -m -u -n -i bash -c "$(cat .github/scripts/cli-space-cleanup.sh)"
-              fi
-              df -h
-      # Run main tool chain installation script, either as a user or system wide
-      - name: Install
-        run: |
-              if [ ! -z ${{ matrix.image }} ]; then
-                ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }}
-              elif [ -z ${{ matrix.user }} ]; then
-                sudo ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }}
-              else
-                sudo ./bin/wally-package-install.sh
-                ./bin/wally-tool-chain-install.sh --clean ${{ matrix.riscv_path }}
-              fi
-      # Set environment variables for the rest of the job
-      - name: Set Environment Variables
-        if: always()
-        run: |
-              if [ ! -z ${{ matrix.riscv_path }} ]; then
-                sed -i 's,exit 1,export RISCV=${{ matrix.riscv_path }},g' setup.sh
-              fi
-              source setup.sh
-              echo "RISCV=$RISCV" >> "$GITHUB_ENV"
-      # Upload installation logs for debugging
-      - name: Upload Installation Logs
-        uses: actions/upload-artifact@v4
-        if: always()
-        with:
-          name: installation-logs-${{ matrix.name }}
-          path: ${{ env.RISCV }}/logs/
-      # Only the linux-testvectors are needed, so remove the rest of the buildroot to save space
-      # Logs have already been uploaded so they can be removed
-      - name: Clean up installation
-        run: |
-            rm -rf $RISCV/buildroot/ || sudo rm -rf $RISCV/buildroot/
-            rm -rf $RISCV/logs || sudo rm -rf $RISCV/logs
-            df -h
-      # Make riscof and zsbl only as that is the only testsuite used by standard regression
-      - name: make tests
-        run: |
-              source setup.sh
-              make riscof zsbl --jobs $(nproc --ignore 1)
-      # Run standard regression, skipping distros that are known to be broken with Verilator
-      - name: Regression
-        if: ${{ matrix.regressionFail != true }}
-        run: |
-              source setup.sh
-              regression-wally
-      - name: Lint + wsim Test Only (for distros with broken Verilator sim)
-        if: ${{ matrix.regressionFail == true }}
-        run: |
-              source setup.sh
-              mkdir -p $WALLY/sim/verilator/logs/
-              lint-wally
-              wsim rv32i arch32i --sim verilator | tee $WALLY/sim/verilator/logs/rv32i_arch32i.log
-      # Upload regression logs for debugging
-      - name: Upload regression logs
-        uses: actions/upload-artifact@v4
-        if: always()
-        with:
-          name: regression-logs-${{ matrix.name }}
-          path: ${{ github.workspace }}/sim/verilator/logs/
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
deleted file mode 100644
index f4c7501d5..000000000
--- a/.github/workflows/lint.yml
+++ /dev/null
@@ -1,35 +0,0 @@
-name: Lint
-
-on:
-  push:
-    paths:
-      - '**/*.py'
-      - 'bin/*'
-      - 'sim/vcs/run_vcs'
-      - '.ruff.toml'
-      - '!addins/*'
-  pull_request:
-    paths:
-      - '**/*.py'
-      - 'bin/*'
-      - 'sim/vcs/run_vcs'
-      - '.ruff.toml'
-      - '!addins/*'
-
-jobs:
-  lint:
-    name: Lint (Python ${{matrix.version}})
-    strategy:
-      matrix:
-        version: [39, 312] # Test on oldest and newest verions used in wally-package-install.sh
-    runs-on: ubuntu-latest
-
-    steps:
-    - name: Checkout code
-      uses: actions/checkout@v4
-
-    - name: Set Python version
-      run: sed -i '/^target-version/c\target-version = "py${{matrix.version}}"' .ruff.toml
-
-    - name: Ensure pre-commit checks pass
-      run: python3 -m pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always
diff --git a/.gitignore b/.gitignore
index 11acaf0b1..587fc73a5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,44 +1,65 @@
-# General file extensions to ignore
+**/work*
+**/wally_*.log
+
 .nfs*
-*.objdump*
+
+__pycache__/
+.vscode/
+
+#External repos
+addins/riscv-arch-test/Makefile.include
+addins/riscv-tests/target
+addins/TestFloat-3e/build/Linux-x86_64-GCC/*
+benchmarks/embench/wally*.json
+
+#vsim work files to ignore
+transcript
+vsim.wlf
+pipelined/wlft*
+wlft*
+/imperas-riscv-tests/FunctionRadix_32.addr
+/imperas-riscv-tests/FunctionRadix_64.addr
+/imperas-riscv-tests/FunctionRadix.addr
+/imperas-riscv-tests/ProgramMap.txt
+/imperas-riscv-tests/logs
 *.o
 *.d
-*.a
 *.vstf
-*.vcd
-*.signature.output
-*.dtb
-*.log
-*.map
-*.elf*
-*.list
-*.memfile
-
-# General directories to ignore
-.vscode/
-__pycache__/
-**/work*
-!.github/*
-/**/obj_dir*
-/**/gmon*
-
-# Tests
+testsBP/*/*/*.elf*
+testsBP/*/OBJ/*
+testsBP/*/*.a
+tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
+tests/riscof/riscof_work/
 tests/riscof/config32.ini
 tests/riscof/config32e.ini
 tests/riscof/config64.ini
-tests/riscof/riscof_work/
-tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
-tests/fp/vectors/*.tv
-tests/fp/vectors/sed*
-tests/fp/combined_IF_vectors/IF_vectors/*.tv
-tests/custom/*/*/
-tests/custom/*/*/*.memfile
-sim/tests/riscvdv
-testbench/trek_files/uvm_output
-
-# Linux
-linux/buildroot
-linux/testvector-generation/boottrace.S
+tests/linux-testgen/linux-testvectors/*
+!tests/linux-testgen/linux-testvectors/tvCopier.py
+!tests/linux-testgen/linux-testvectors/tvLinker.sh
+!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
+tests/linux-testgen/buildroot
+tests/linux-testgen/buildroot-image-output
+tests/linux-testgen/buildroot-config-src/main.config.old
+tests/linux-testgen/buildroot-config-src/linux.config.old
+tests/linux-testgen/buildroot-config-src/busybox.config.old
+pipelined/regression/slack-notifier/slack-webhook-url.txt
+pipelined/regression/logs
+fpga/generator/IP
+fpga/generator/vivado.*
+fpga/generator/.Xil/*
+fpga/generator/WallyFPGA*
+fpga/generator/reports/
+fpga/generator/*.log
+fpga/generator/*.jou
+*.objdump*
+*.signature.output
+examples/asm/sumtest/sumtest
+examples/asm/example/example
+examples/C/sum/sum
+examples/C/fir/fir
+examples/fp/softfloat_demo/softfloat_demo
+examples/fp/fpcalc/fpcalc
+pipelined/src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
 linux/testvector-generation/genCheckpoint.gdb
@@ -46,131 +67,64 @@ linux/testvector-generation/silencePipe
 linux/testvector-generation/silencePipe.control
 linux/testvector-generation/fixBinMem
 linux/testvector-generation/qemu-serial
-
-# FPGA
-fpga/generator/IP
-fpga/generator/vivado.*
-fpga/generator/.Xil/*
-fpga/generator/WallyFPGA*
-fpga/generator/reports/
-fpga/generator/*.jou
-fpga/src/sdc/*
-fpga/src/sdc.tar.gz
-fpga/src/CopiedFiles_do_not_add_to_repo/*
-fpga/generator/sim/imp-funcsim.v
-fpga/generator/sim/imp-timesim.sdf
-fpga/generator/sim/imp-timesim.v
-fpga/generator/sim/syn-funcsim.v
-fpga/rvvidaemon/rvvidaemon
-fpga/zsbl/OBJ/*
-fpga/zsbl/bin/*
-fpga/src/boot.mem
-fpga/src/data.mem
-
-# Synthesis
+*.dtb
 synthDC/WORK
 synthDC/alib-52
+synthDC/*.log
 synthDC/*.svf
 synthDC/runs/
 synthDC/newRuns
 synthDC/ppa/PPAruns
 synthDC/ppa/plots
-synthDC/wallyplots/
+synthDC/plots/
 synthDC/runArchive
 synthDC/hdl
+/pipelined/regression/power.saif
+tests/fp/vectors/*.tv
+# Temporary configs produced for synthesis
+pipelined/config/rv32e_FPUoff
+pipelined/config/rv32e_PMP0
+pipelined/config/rv32e_PMP16
+pipelined/config/rv32e_noMulDiv
+pipelined/config/rv32e_noPriv
+pipelined/config/rv32e_orig
+pipelined/config/rv32gc_FPUoff
+pipelined/config/rv32gc_PMP0
+pipelined/config/rv32gc_PMP16
+pipelined/config/rv32gc_noMulDiv
+pipelined/config/rv32gc_noPriv
+pipelined/config/rv32gc_orig
+pipelined/config/rv32ic_FPUoff
+pipelined/config/rv32ic_PMP0
+pipelined/config/rv32ic_PMP16
+pipelined/config/rv32ic_noMulDiv
+pipelined/config/rv32ic_noPriv
+pipelined/config/rv32ic_orig
+pipelined/config/rv64gc_FPUoff
+pipelined/config/rv64gc_PMP0
+pipelined/config/rv64gc_PMP16
+pipelined/config/rv64gc_noMulDiv
+pipelined/config/rv64gc_noPriv
+pipelined/config/rv64gc_orig
+pipelined/config/rv64ic_FPUoff
+pipelined/config/rv64ic_PMP0
+pipelined/config/rv64ic_PMP16
+pipelined/config/rv64ic_noMulDiv
+pipelined/config/rv64ic_noPriv
+pipelined/config/rv64ic_orig
 synthDC/Summary.csv
-
-# Benchmarks
-benchmarks/embench/wally*.json
-benchmarks/embench/run*
-benchmarks/coremark/coremark_results.csv
-
-# Simulation
-sim/*.svg
-sim/power.saif
-sim/results
-sim/results-error/
-sim/test1.rep
-sim/branch
-sim/branch-march14.tar.gz
-sim/gshareforward-no-class
-sim/local16.txt
-sim/localhistory_m6k10_results_april24.txt
-sim/cfi/*
-sim/branch/*
-sim/covhtmlreport/
-sim/*/*Cache.log
-
-# Questa
-sim/questa/logs
-sim/questa/wkdir
-sim/questa/ucdb
-sim/questa/cov
-sim/questa/fcov
-sim/questa/fcov_logs
-sim/questa/fcov_ucdb
-sim/questa/riscv.ucdb
-transcript
-vsim.wlf
-wlft*
-
-# VCS
-sim/vcs/logs
-sim/vcs/wkdir
-sim/vcs/ucdb
-sim/vcs/csrc
-sim/vcs/profileReport*
-sim/vcs/program.out
-sim/vcs/sim_out*
-sim/vcs/simprofile_dir
-sim/vcs/ucli.key
-sim/vcs/verdi_config_file
-sim/vcs/vcdplus.vpd
-sim/vcs/simprofile*
-
-# Verilator
-sim/verilator/logs
-sim/verilator/wkdir
-
-# Examples
-examples/verilog/fulladder/csrc/
-examples/verilog/fulladder/profileReport.html
-examples/verilog/fulladder/profileReport.json
-examples/verilog/fulladder/profileReport.txt
-examples/verilog/fulladder/profileReport/
-examples/verilog/fulladder/simprofile_dir/
-examples/verilog/fulladder/simv.daidir/
-examples/verilog/fulladder/ucli.key
-examples/verilog/fulladder/verdi_config_file
-examples/fp/softfloat_demo/softfloat_demo
-examples/fp/softfloat_demo/softfloat_demoDP
-examples/fp/softfloat_demo/softfloat_demoQP
-examples/fp/softfloat_demo/softfloat_demoSP
-examples/fp/fpcalc/fpcalc
-examples/fp/sqrttest/sqrttest
-examples/crypto/gfmul/gfmul
-examples/C/fir/fir
-examples/C/inline/inline
-examples/C/mcmodel/mcmodel_medany
-examples/C/mcmodel/mcmodel_medlow
-examples/C/sum/sum
-examples/C/sum_mixed/sum_mixed
-examples/C/hello/hello
-examples/C/gpio/gpio
-examples/asm/sumtest/sumtest
-examples/asm/example/example
-examples/asm/trap/trap
-examples/asm/etc/pause
-examples/C/fmul
-examples/exercises/fma16/fma16.sv
-examples/exercises/fma16/fma16_testgen
-examples/exercises/fma16/sol 
-examples/exercises/riscvsoc_solutions
-
-
-# Other
-external
-config/deriv
-sim/slack-notifier/slack-webhook-url.txt
-docs/docker/buildroot-config-src
-docs/docker/testvector-generation
+pipelined/srt/exptestgen
+pipelined/srt/testgen
+pipelined/srt/qslc_r4a2
+pipelined/srt/qslc_r4a2.sv
+pipelined/srt/testvectors
+pipelined/regression/wkdir
+tests/custom/work
+tests/custom/*/*/*.list
+tests/custom/*/*/*.elf
+tests/custom/*/*/*.map
+tests/custom/*/*/*.memfile
+tests/custom/crt0/*.a
+/pipelined/regression/sd_model.log
+fpga/src/sdc/*
+fpga/src/sdc.tar.gz
diff --git a/.gitmodules b/.gitmodules
index 672ec445f..ab45d3f96 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,16 @@
+[submodule "sky130/sky130_osu_sc_t12"]
+	path = sky130/sky130_osu_sc_t12
+	url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/
+[submodule "addins/riscv-arch-test"]
+	path = addins/riscv-arch-test
+	url = https://github.com/riscv-non-isa/riscv-arch-test
+	ignore = dirty
+[submodule "addins/imperas-riscv-tests"]
+	path = addins/imperas-riscv-tests
+	url = https://github.com/riscv-ovpsim/imperas-riscv-tests
+[submodule "addins/riscv-tests"]
+	path = addins/riscv-tests
+	url = https://github.com/riscv-software-src/riscv-tests
 [submodule "addins/riscv-dv"]
 	path = addins/riscv-dv
 	url = https://github.com/google/riscv-dv
@@ -8,28 +21,3 @@
 [submodule "addins/coremark"]
 	path = addins/coremark
 	url = https://github.com/eembc/coremark
-[submodule "addins/vivado-boards"]
-	path = addins/vivado-boards
-	url = https://github.com/Digilent/vivado-boards/
-[submodule "addins/riscv-arch-test"]
-	path = addins/riscv-arch-test
-	url = https://github.com/riscv-non-isa/riscv-arch-test
-	branch = dev
-[submodule "addins/branch-predictor-simulator"]
-	path = addins/branch-predictor-simulator
-	url = https://github.com/rosethompson/branch-predictor-simulator
-[submodule "addins/verilog-ethernet"]
-	sparseCheckout = true
-	path = addins/verilog-ethernet
-	url = https://github.com/rosethompson/verilog-ethernet.git
-[submodule "addins/cvw-arch-verif"]
-	path = addins/cvw-arch-verif
-	url = https://github.com/openhwgroup/cvw-arch-verif
-	ignore = dirty
-[submodule "addins/berkeley-softfloat-3"]
-	path = addins/berkeley-softfloat-3
-	url = https://github.com/ucb-bar/berkeley-softfloat-3.git
-[submodule "addins/berkeley-testfloat-3"]
-	path = addins/berkeley-testfloat-3
-	url = https://github.com/ucb-bar/berkeley-testfloat-3
-	ignore = untracked
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
deleted file mode 100644
index 1ac8e720e..000000000
--- a/.pre-commit-config.yaml
+++ /dev/null
@@ -1,41 +0,0 @@
-# .pre-commit-config.yaml
-# jcarlin@hmc.edu 8 April 2025
-# Pre-commit hook configuration file for CVW
-
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# See https://pre-commit.com for more information
-# See https://pre-commit.com/hooks.html for more hooks
-exclude: addins/
-minimum_pre_commit_version: "4.0.0"
-repos:
-  # Standard pre-commit hooks
-  - repo: https://github.com/pre-commit/pre-commit-hooks
-    rev: v5.0.0
-    hooks:
-      - id: check-added-large-files
-      - id: check-case-conflict
-      - id: check-docstring-first
-      # - id: check-executables-have-shebangs
-      # - id: check-shebang-scripts-are-executable
-      - id: check-symlinks
-        exclude: bin/sim_bp # symlink to compiled executable
-      - id: requirements-txt-fixer
-        files: requirements.txt
-      # - id: end-of-file-fixer
-      # - id: trailing-whitespace
-      #   args: [--markdown-linebreak-ext=md]
-      - id: check-merge-conflict
-        args: ["--assume-in-merge"]
-        exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise
-      - id: check-json
-      - id: check-toml
-      - id: check-yaml
-
-  # Ruff python linter
-  - repo: https://github.com/astral-sh/ruff-pre-commit
-    rev: v0.11.4
-    hooks:
-      # Run the linter.
-      - id: ruff
-        args: [ --fix ]
diff --git a/.ruff.toml b/.ruff.toml
deleted file mode 100644
index 50efc7fb0..000000000
--- a/.ruff.toml
+++ /dev/null
@@ -1,34 +0,0 @@
-# Lint all .py files and extra python scripts without extensions
-exclude = ["addins/*"]
-
-# Target oldest version of Python used (Python 3.9 for Ubuntu 20.04 LTS)
-target-version = "py39"
-
-line-length=250
-
-[lint]
-select = [
-  "F",    # various basic rules (pyflakes)
-  "E",    # errors (pycodestyle)
-  "W",    # warnings (pycodestyle)
-  "I",    # Import related rules (isort)
-  "UP",   # Upgraded version available in newer Python
-  "B",    # bugbear rules
-  "A",    # shadow builtins
-  "EXE",  # Executable file shebangs
-  "Q003", # Avoidable escaped quotes
-  "Q004", # Unnecessary esacpe character
-  "RUF",  # Ruff specific rules
-]
-
-ignore = [
-  "E501",           # line too long
-  "E701", "E702",   # multiple statements on one line
-  "E722",           # do not use bare 'except'
-  "E741",           # ambiguous variable name
-  "W291",           # trailing whitespace
-  "W293",           # blank line contains whitespace
-  "B007",           # loop control variable not used
-  "B9",             # overly opinionated rules
-  "RUF005",         # iterable unpacking in list
-]
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
deleted file mode 100644
index d9919d464..000000000
--- a/CONTRIBUTING.md
+++ /dev/null
@@ -1,24 +0,0 @@
-<!---
-SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
---->
-# Contributing
-New Contributors are always welcome.
-
-## Contributor Agreement
-Most Contributors are [members](https://www.openhwgroup.org/membership/) of the
-OpenHW Group and participate in one or more [Technical Task Groups](https://www.openhwgroup.org/working-groups/).
-Membership is strongly encouraged, but not required.  Contributors must be
-covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
-(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
-(for employees of Member companies). The ECA/MCCA provides a legal
-framework for a Contributor's technical contributions to the OpenHW Group,
-including provisions for grant of copyright license and a Developer
-Certificate of Origin on contributions merged into OpenHW Group repositories.
-
-## The Mechanics
-1. [Fork](https://help.github.com/articles/fork-a-repo/) the [cvw](https://github.com/openhwgroup/cvw) repository
-2. Clone repository: `git clone https://github.com/[your_github_username]/cvw`
-3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name.  See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
-5. Commit your changes: `git commit -m 'Add some feature'`
-6. Push feature branch: `git push origin <my_branch>`
-7. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).
diff --git a/Install b/Install
new file mode 100644
index 000000000..28ef1b846
--- /dev/null
+++ b/Install
@@ -0,0 +1,468 @@
+Complete Wally Installation guide
+Formally RISC-V System on Chip Design Appendix D
+
+Sections:
+1. RISC-V Tool Installation (Sys Admin)
+2. Core-v-wally Repo Installation
+3. Build and Run Regression Tests
+
+Section 1 tool install should be done once by a system admin with root access.  The specific details may need to be 
+adjusted as some tools may already be present on the system.  This guide assumes all compiled from source tools are
+installed at base diretory $RISCV.
+
+* Tool-chain Installation (Sys Admin)
+
+** TL;DR Open Source Tool-chain Installation
+
+   The installing details are involved.  The following script assumes installation occurs in RISCV=/opt/riscv
+   This install script does NOT install buildroot or commercial EDA tools; Questa, Design Compiler, or Innovus.
+   It must be run as root or with sudo.
+   This script only works for Ubuntu.
+
+   wally-tool-chain-install.sh
+
+** TL;DR install summery
+
+*** Environement setup
+    1. export RISCV=/opt/riscv
+    2. sudo mkdir $RISCV
+    3. sudo chown cad $RISCV
+    4. sudo su cad  (or root, if you don’t have a cad account)
+    5. export RISCV=/opt/riscv
+    6. chmod 755 $RISCV
+    7. mask 0002
+    8. cd $RISCV
+
+*** Install dependencies
+
+**** Ubuntu
+    1. sudo apt update
+    2. sudo apt upgrade
+    3. sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog 
+
+**** Red Hat / Fedora *** TODO
+
+*** Install RISC-V GCC Cross-Compiler
+    1. git clone https://github.com/riscv/riscv-gnu-toolchain
+    2. cd riscv-gnu-toolchain
+    3. git checkout 2022.09.21
+    4. ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+    5. make --jobs
+
+*** Install elf2hex
+    1. cd $RISCV
+    2. export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+    3. git clone https://github.com/sifive/elf2hex.git
+    4. cd elf2hex
+    5. autoreconf -i
+    6. ./configure --target=riscv64-unknown-elf --prefix=$RISCV
+    7. make
+    8. make install 
+
+*** Install RISC-V Spike Simulator
+    1. cd $RISCV
+    2. git clone https://github.com/riscv-software-src/riscv-isa-sim
+    3. mkdir riscv-isa-sim/build
+    4. cd riscv-isa-sim/build
+    5. ../configure --prefix=$RISCV --enable-commitlog
+    6. make --jobs
+    7. make install
+    8. cd ../arch_test_target/spike/device
+    9. sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
+    10. sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include 
+
+*** Install Sail Simulator
+
+**** Ubuntu
+     1. sudo apt install opam  build-essential libgmp-dev z3 pkg-config zlib1g-dev
+
+**** Red Hat / Fedora
+     # Parallel make (--jobs) will massively speed up installation; however it requires significant system RAM.  Recomemded to have 64GB
+     1. sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)"
+	When prompted, put it in /usr/bin 
+     2. sudo yum groupinstall 'Development Tools'
+     3. sudo yum -y install gmp-devel
+     4. sudo yum -y install zlib-devel
+     5. git clone https://github.com/Z3Prover/z3.git
+     6. cd z3
+     7. python scripts/mk_make.py
+     8. cd build
+     9. make 
+     10. sudo make install
+     11. cd ../..
+     12. sudo pip3 install chardet==3.0.4
+     13. sudo pip3 install urllib3==1.22
+
+**** Complete Sail Install with OCaml
+     # Parallel make (--jobs) will massively speed up installation; however it requires significant system RAM.  Recomemded to have 64GB
+     1. sudo su cad
+     2. opam init -y --disable-sandboxing
+     3. opam switch create ocaml-base-compiler.4.06.1
+     4. opam install sail -y
+     5. eval $(opam config env)
+     6. cd $RISCV
+     7. git clone https://github.com/riscv/sail-riscv.git
+     8. cd sail-riscv
+     9. make
+     10. ARCH=RV32 make
+     11. ARCH=RV64 make
+     12. exit
+     13. sudo su
+     14. export RISCV=/opt/riscv
+     15. ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
+     16. ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
+     17. exit
+
+*** Install riscof
+    1. sudo pip3 install testresources
+    2. sudo pip3 install riscof --ignore-installed PyYAML
+
+*** Install Verilator
+
+**** Ubuntu
+     sudo apt install verilator 
+
+**** Red Hat / Fedora *** TODO
+
+*** Install QEMU Simulator (Only required for linux simulation)
+     1. cd $RISCV
+     2. git clone --recurse-submodules https://github.com/qemu/qemu
+     3. cd qemu
+     4. git checkout v6.2.0    # last version tested; newer versions might be ok
+     5. ./configure --target-list=riscv64-softmmu --prefix=$RISCV
+     6. make --jobs
+     7. make install
+
+*** Cross-Compile Buildroot Linux (Only required for linux simulation)
+#May wish to install in another location
+    1. cd $RISCV
+    2. export WALLY=~/riscv-wally  # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
+    3. git clone https://github.com/buildroot/buildroot.git
+    4. cd buildroot
+    5. git checkout 2021.05 # last tested working version
+    6. cp -r $WALLY/linux/buildroot-config-src/wally ./board
+    7. cp ./board/wally/main.config .config
+    8. make --jobs
+
+**** Generate disassembly files
+     1. source ~/riscv-wally/setup.sh
+     2. cd $WALLY/linux/buildroot-scripts
+     3. make all
+
+*** Download Synthesis Libraries
+    1. cd $RISCV
+    2. mkdir cad
+    3. mkdir cad/lib
+    4. cd cad/lib
+    5. git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
+
+
+** Detailed Tool-chain Instal Guide
+   Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server.  This appendix describes how the system administrator installs RISC-V tools.  Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman.  
+
+*** Open Source Software Installation
+
+Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools:
+
+1.	The GCC cross-compiler
+2.	A RISC-V simulator such as Spike, Sail, and/or QEMU
+3.      Spike is easy to use but doesn’t support peripherals to boot Linux
+4.	QEMU is faster and can boot Linux
+5.	Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal
+
+This setup needs to be done once by the administrator
+
+Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer.
+
+Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. 
+
+*** Create the $RISCV Directory
+
+First, set up a directory for riscv software in some place such as /opt/riscv.  We will call this shared directory $RISCV.
+
+$ export RISCV=/opt/riscv
+$ sudo mkdir $RISCV
+$ sudo chown cad $RISCV
+$ sudo su cad  (or root, if you don’t have a cad account)
+$ export RISCV=/opt/riscv
+$ chmod 755 $RISCV
+$ umask 0002
+$ cd $RISCV
+
+*** Update Tools
+
+Ubuntu users may need to install and update various tools.
+
+$ sudo apt update
+$ sudo apt upgrade
+$ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog 
+
+*** Install RISC-V GCC Cross-Compiler
+
+To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V.   This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. 
+
+$ git clone https://github.com/riscv/riscv-gnu-toolchain 
+$ cd riscv-gnu-toolchain 
+$ git checkout 2022.09.21 
+$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+$ make --jobs
+
+Note: make --jobs will reduce compile time by compiling in parallel.  However, adding this option could dramatically increase the memory utilization of your local machine.
+
+*** Install elf2hex
+
+We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with:
+
+$ cd $RISCV
+$ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+$ git clone https://github.com/sifive/elf2hex.git
+$ cd elf2hex
+$ autoreconf -i
+$ ./configure --target=riscv64-unknown-elf --prefix=$RISCV
+$ make 
+$ make install 
+
+Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly.  Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly.
+
+*** Install RISC-V Spike Simulator
+
+Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation.  After the build, we need to change two Makefiles to support atomic instructions .
+
+$ cd $RISCV
+$ git clone https://github.com/riscv-software-src/riscv-isa-sim
+$ mkdir riscv-isa-sim/build
+$ cd riscv-isa-sim/build
+$ ../configure --prefix=$RISCV --enable-commitlog 
+$ make --jobs
+$ make install 
+$ cd ../arch_test_target/spike/device
+$ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
+$ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include 
+
+*** Install Sail Simulator
+
+Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification.  OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install.
+
+On Ubuntu, apt-get makes opam installation fairly simple.
+
+$ sudo apt-get install opam  build-essential libgmp-dev z3 pkg-config zlib1g-dev
+
+If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source.
+
+$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)"
+	When prompted, put it in /usr/bin
+$ sudo yum groupinstall 'Development Tools'
+$ sudo yum -y install gmp-devel
+$ sudo yum -y install zlib-devel
+$ git clone https://github.com/Z3Prover/z3.git 
+$ cd z3
+$ python scripts/mk_make.py
+$ cd build
+$ make
+$ sudo make install
+$ cd ../..
+$ sudo pip3 install chardet==3.0.4
+$ sudo pip3 install urllib3==1.22
+
+Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail.  Run as the cad user because you will be installing Sail in $RISCV.
+
+$ sudo su cad
+$ opam init -y --disable-sandboxing
+$ opam switch create ocaml-base-compiler.4.06.1
+$ opam install sail -y
+
+Now you can clone and compile Sail-RISCV.  This will take a while.
+
+$ eval $(opam config env)
+$ cd $RISCV
+$ git clone https://github.com/riscv/sail-riscv.git
+$ cd sail-riscv
+$ make
+$ ARCH=RV32 make
+$ ARCH=RV64 make
+$ exit
+$ sudo su
+$ export RISCV=/opt/riscv
+$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
+$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
+$ exit
+
+*** Install riscof
+
+riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite.  
+
+It is most convenient if the sysadmin installs riscof into the server’s Python libraries:
+
+$ sudo pip3 install testresources
+$ sudo pip3 install riscof --ignore-installed PyYAML
+
+However, riscof can also be installed and run locally by individual users.
+
+*** Install Verilator
+
+Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code.  It is needed to run regression.
+$ sudo apt install verilator 
+
+*** Install QEMU Simulator
+
+QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. 
+
+<SIDEBAR>
+The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF).
+</END>
+
+$ cd $RISCV
+$ git clone --recurse-submodules https://github.com/qemu/qemu
+$ cd qemu
+$ git checkout v6.2.0    # last version tested; newer versions might be ok
+$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV
+$ make --jobs
+$ make install
+
+*** Cross-Compile Buildroot Linux
+
+Building Linux is only necessary for exploring the boot process in Chapter 17.  Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details.
+
+Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2.  However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot.
+
+To configure and build Buildroot:
+
+$ cd $RISCV
+$ export WALLY=~/riscv-wally  # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
+$ git clone https://github.com/buildroot/buildroot.git
+$ cd buildroot
+$ git checkout 2021.05 # last tested working version
+$ cp -r $WALLY/linux/buildroot-config-src/wally ./board
+$ cp ./board/wally/main.config .config
+$ make --jobs
+
+To generate disassembly files and the device tree, run another make script.  Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
+
+$ source ~/riscv-wally/setup.sh
+$ cd $WALLY/linux/buildroot-scripts
+$ make all
+
+Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images.
+
+*** Download Synthesis Libraries
+
+For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library.  Clone the OSU 12-track cell library for the Skywater 130 nm process:
+
+$ cd $RISCV
+$ mkdir cad
+$ mkdir cad/lib
+$ cd cad/lib
+$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
+
+** Installing EDA Tools
+
+Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs.   Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text.  The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally.  It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
+
+Siemens Quest is the primary tool utilized for simulating and validating Wally.    For logic synthesis, you will need Synopsys Design Compiler.  Questa and Design Compiler are commercial tools that require an educational or commercial license.  
+
+Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server.  Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file.  Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license.
+
+Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors.  Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration.  Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels.  
+
+Siemens Questa
+
+Siemens Questa simulates behavioral, RTL and gate-level HDL.  To install Siemens Questa first go to a web browser and navigate to 
+https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/.  Click Sign In and log in with your credentials and the product can easily be downloaded and installed.  Some  Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.  
+
+Synopsys Design Compiler (DC)
+
+Many commercial synthesis and place and route tools require a common installer.  These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer.  To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL).  Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet.  First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files.  Then, install the Installer
+
+$ firefox &
+Navigate to https://solvnet.synopsys.com
+Log in with your institution’s username and password
+Click on Downloads, then scroll down to Synopsys Installer
+Select the latest version (currently 5.4).  Click Download Here, agree,
+Click on SynopsysInstaller_v5.4.run
+Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
+	Click on all parts and the .spf file, then click Download Files near the top
+move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, 
+move other files into /cad/synopsys/downloads and work as user cad from here on
+$ cd /cad/synopsys/installer_5.4
+$ ./SynopsysInstaller_v5.4.run
+Accept default installation directory
+$ ./installer
+Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys
+When prompted, enter your site ID
+Follow prompts
+
+Installer can be utilized in graphical or text-based modes.  It is far easier to use the text-based installation tool.  To install DC, navigate to the location where your downloaded DC files are and type installer.  You should be prompted with questions related to where you wish to have your files installed.  
+
+The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation:
+
+/import/programs/synopsys/syn/S-2021.06-SP1
+
+Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. 
+
+The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. 
+
+If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. 
+
+Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection.
+
+
+* Core-v-wally Repo Installation
+** TL;DR Repo Install
+cd
+git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
+cd riscv-wally
+source ./setup.sh        # may require some modification for your system. Always run once after opening a new terminal.
+
+** Detailed Repo Install Guide
+
+1. cd
+   Return to home directory.  The home directory is sufficent a location for students.
+   However more advanced users may choose to clone wally into another directory.
+
+2. git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
+   Clone the wally repository and all dependent submodules into subdirectory riscv-wally.
+
+3. cd riscv-wally
+   Change directory to the wally repos riscv-wally. 
+
+4. source ./setup.sh
+   setup.sh is s configuration script which creates several environment variables.
+   WALLY: Absolute directory path to this repo clone.
+   MGLS_LICENSE_FILE: Siemens license server for questa sim (modelsim). If your computer
+                      is already configured for questa remove variable.
+   SNPSLMD_LICENSE_FILE: Synopsys license server.  If remove if already setup.
+   PATH: PATH is extended to include the installation directories for Siemens questa and
+         Synopsys design compiler.  Remove if already setup.
+	 Adds riscv-gnu-toolchain and spike to PATH.  Adjust if installed in another location.
+	 Or remove if already in the PATH variable.
+	 Adds path to wally repo specific tools.  (Must include.)
+	 Adds path to verilator.  Remove if already in path.
+   RISCV: This is the location of the riscv tool chain and other wally requirements.
+          See the Sys Admin section for details.
+
+   If using ubuntu 22.04 setup.sh can be reduced to 
+
+   echo "Executing Wally setup.sh"
+
+   # Path to Wally repository
+   #!/bin/bash
+
+   WALLY=$(dirname ${BASH_SOURCE[0]:-$0})
+   export WALLY=$(cd "$WALLY" && pwd)
+   echo \$WALLY set to ${WALLY}
+
+   # Path to RISC-V Tools
+   export RISCV=/opt/riscv   # change this if you installed the tools in a different location
+
+   # utility functions in Wally repository
+   export PATH=$PATH:$RISCV/bin
+   export PATH=$WALLY/bin:$PATH    
+
+* Build and Run Regression Tests
+  Ensure the system tools are installed.
+
+  cd <to location of repo clone>
+  make
+  cd pipelined/regression
+  ./regression-wally       #(depends on having Questa installed)
+
diff --git a/LICENSE b/LICENSE
index 173f17332..21432e098 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,14 +1,22 @@
-// Copyright (C) 2021-25 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
+MIT License
+
+Copyright (c) 2021 Harvey Mudd College & Oklahoma State University
+Contact: Prof. David Harris  David_Harris@hmc.edu
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/Makefile b/Makefile
index d50c761b8..b3a054e49 100644
--- a/Makefile
+++ b/Makefile
@@ -1,46 +1,22 @@
-# David_Harris@hmc.edu 2023
-# Top-level Makefile for CORE-V-Wally
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+all:
+	make install
+	make regression
 
-MAKEFLAGS += --output-sync --no-print-directory
+# install copies over the Makefile.include from riscv-isa-sim
+# And corrects the TARGETDIR path and the RISCV_PREFIX
 
-SIM = ${WALLY}/sim
+install:
+	# *** 1/15/23 dh: check if any of this is still needed
+	#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
+	#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
+	#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
+	##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
+	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
-.PHONY: all riscof testfloat combined_IF_vectors zsbl coverage cvw-arch-verif sim_bp clean
-
-all: riscof	testfloat combined_IF_vectors zsbl coverage sim_bp # cvw-arch-verif
-
-# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
-riscof:
-	$(MAKE) -C sim
-
-testfloat:
-	$(MAKE) -C ${WALLY}/tests/fp vectors
-
-combined_IF_vectors: testfloat riscof
-	$(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors
-
-zsbl:
-	$(MAKE) -C ${WALLY}/fpga/zsbl
-
-coverage:
-	$(MAKE) -C tests/coverage
-
-cvw-arch-verif:
-	$(MAKE) -C ${WALLY}/addins/cvw-arch-verif
-
-sim_bp: ${WALLY}/addins/branch-predictor-simulator/src/sim_bp
-
-${WALLY}/addins/branch-predictor-simulator/src/sim_bp:
-	$(MAKE) -C ${WALLY}/addins/branch-predictor-simulator/src
-
-# Requires a license for the Breker tool. See tests/breker/README.md for details
-breker:
-	$(MAKE) -C ${WALLY}/testbench/trek_files
-	$(MAKE) -C ${WALLY}/tests/breker
+regression:
+	make -C pipelined/regression
 
 clean:
-	$(MAKE) clean -C sim
-	$(MAKE) clean -C ${WALLY}/tests/fp
-	$(MAKE) clean -C ${WALLY}/tests/coverage
-	$(MAKE) clean -C ${WALLY}/addins/cvw-arch-verif
+	make clean -C pipelined/regression
+
diff --git a/README.md b/README.md
index b700df728..433eb442a 100644
--- a/README.md
+++ b/README.md
@@ -1,285 +1,31 @@
-[![Installation CI](https://github.com/openhwgroup/cvw/actions/workflows/install.yml/badge.svg?branch=main)](https://github.com/openhwgroup/cvw/actions/workflows/install.yml)
-
 # core-v-wally
+Configurable RISC-V Processor
 
-Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO).   Wally is written in SystemVerilog.  It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA.  Configurations range from a minimal RV32E core to a fully featured RV64GC application processor with all of the RVA22S64 profile extensions. Wally is part of the OpenHWGroup family of robust open RISC-V cores.
+Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.
 
-![Wally block diagram](wallyriscvTopAll.png)
-
-Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
-
-# Verification
-
-Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplans/testplan.md) for details.
-
-# New User Setup
+Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris.  See Appendix D for directions installing the RISC-V tool chain needed to use Wally.
 
 New users may wish to do the following setup to access the server via a GUI and use a text editor.
 
-- Git started with Git configuration and authentication: C.1  (replace with your name and email)
-	```bash
-	$ git config --global user.name "Ben Bitdiddle"
-	$ git config --global user.email "ben_bitdiddle@wally.edu"
-	$ git config --global pull.rebase false
-	```
-- Optional: Download and install x2go - B.1.1
-- Optional: Download and install VSCode - B.4.2
-- Optional: Make sure you can log into your server via x2go and via a terminal
-	- Terminal on Mac, cmd on Windows, xterm on Linux
-	- See B.1 about ssh -Y login from a terminal
+	Download and install x2go - A.1.1
+	Download and install VSCode - A.4.2
+	Make sure you can log into Tera acceptly via x2go and via a terminal
+		Terminal on Mac, cmd on Windows, xterm on Linux
+		See A.1 about ssh -Y login from a terminal
+	Git started with Git configuration and authentication: B.1
 
-Then fork and clone the repo, source setup, make the tests and run regression
+Then follow Section 2.2 to clone the repo, source setup,  make the tests and run regression
 
-1. If you don't already have a Github account, create one
-2. In a web browser, visit https://github.com/openhwgroup/cvw
-3. In the upper right part of the screen, click on Fork
-4. Create a fork, choosing the owner as your github account and the repository as cvw.
-5. On the Linux computer where you will be working, log in.
-6. Clone your fork of the repo. Change `<yourgithubid>` to your github id.
-	```bash
-	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
-	$ cd cvw
-	$ git remote add upstream https://github.com/openhwgroup/cvw
-	```
-
-> [!NOTE]
-> If you are installing on a new system without any tools installed, please jump to the next section, [Toolchain Installation](#toolchain-installation-and-configuration-sys-admin), then come back here.
-
-7. Run the setup script to update your `PATH` and activate the python virtual environment.
-
-	```bash
+	$ cd
+	$ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
+	$ cd riscv-wally
 	$ source ./setup.sh
-	```
-
-8. Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in.
-
-	```bash
-	if [ -f ~/cvw/setup.sh ]; then
-		source ~/cvw/setup.sh
-	fi
-	```
-
-9. Try compiling the HelloWally program and simulating it on the SystemVerilog with Verilator and on the Spike simulator.
-	```
-	$ cd examples/C/hello
 	$ make
-	$ wsim --sim verilator rv64gc --elf hello
-	Hello Wally!
-	0 1 2 3 4 5 6 7 8 9 
-	$ spike hello
-	Hello Wally!
-	0 1 2 3 4 5 6 7 8 9 
-	```
+	$ cd pipelined/regression
+	$ ./regression-wally       (depends on having Questa installed)
 
-10. Build the tests and run a regression simulation to prove everything is installed.  Building tests may take a while.
+Add the following lines to your .bashrc or .bash_profile
 
-	```bash
-	$ make --jobs
-	$ regression-wally
-	```
-
-# Toolchain Installation and Configuration (Sys Admin)
-
-> This section describes the open source toolchain installation.
-
-### Compatibility
-The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS), Debian (versions 11 and 12), Red Hat/Rocky/AlmaLinux (versions 8 and 9),
-and SUSE version 15.6. Only the latest minor release of each major version is tested.
-
-> [!WARNING]
-> - Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler.
-> - Verilator currently fails to simulate correctly on Ubuntu 20.04 LTS and Red Hat/Rocky/AlmaLinux 8.
-
-### Overview
-The toolchain installation script installs the following tools:
-- [RISC-V GNU Toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain): GCC and accompanying compiler tools
-- [elf2hex](https://github.com/sifive/elf2hex): executable file to hexadecimal converter
-- [QEMU](https://www.qemu.org/docs/master/system/target-riscv.html): emulator
-- [Spike](https://github.com/riscv-software-src/riscv-isa-sim): functional RISC-V model
-- [Verilator](https://github.com/verilator/verilator): open-source Verilog simulator
-- [RISC-V Sail Model](https://github.com/riscv/sail-riscv): golden reference model for RISC-V
-- [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library
-- [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework
-
-Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details. This can be skipped using the `--no-buildroot` flag.
-
-### Installation
-
-The tools can be installed by running
-
-```bash
-$ $WALLY/bin/wally-tool-chain-install.sh
-```
-If this script is run as root or using `sudo`, it will also install all of the prerequisite packages using the system package manager. The default installation directory when run in this manner is `/opt/riscv`.
-
-If a user-level installation is desired, the script can instead be run by any user without `sudo` and the installation directory will be `~/riscv`. In this case, the prerequisite packages must first be installed by running
-
-```bash
-$ sudo $WALLY/bin/wally-package-install.sh
-```
-
-In either case, the installation directory can be overridden by passing the desired directory as the last argument to the installation script. For example,
-
-```bash
-$ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv
-```
-
-See `wally-tool-chain-install.sh` for a detailed description of each component, or to issue the commands one at a time to install on the command line.
-
-> [!NOTE]
-> The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed to the installation script then the final consumed space is only ~26 GB, but upgrading the tools will reinstall everything from scratch.
-
-### Configuration
-`$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path.
-
-`$RISCV/site-setup.sh` allows for customization of the site specific information such as commercial licenses and PATH variables. It is automatically copied into your `$RISCV` folder when the installation script is run.
-
-Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler and VCS installations and license servers.  If you only have Questa or VCS, you can still simulate but cannot run logic synthesis.  If Questa, VSC, or Design Compiler are already setup on this system then don't set these variables.
-
-```bash
-export MGLS_LICENSE_FILE=..         # Change this to your Siemens license server
-export SNPSLMD_LICENSE_FILE=..      # Change this to your Synopsys license server
-export QUESTA_HOME=..               # Change this for your path to Questa
-export DC_HOME=..                   # Change this for your path to Synopsys Design Compiler
-export VCS_HOME=..                  # Change this for your path to Synopsys VCS
-```
-
-# Installing EDA Tools
-
-Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs.   Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text.  The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally.  It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
-
-Verilator is an open-source Verilog simulator.  It is fast and free.  Run Wally on the riscv-arch-test suite using Verilator with:
-
-```
-regression-wally
-```
-
-Running code or functional coverage simulations or lock-step presently require commercial tools.  Siemens Questa is the primary tool utilized for simulating and validating Wally. Synopsys VCS also can run regression-wally and lock-step simulation.  For logic synthesis, you will need Synopsys Design Compiler.  Questa and Design Compiler are commercial tools that require an educational or commercial license.
-
-Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server.  Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file.  Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license.
-
-Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors.  Red Hat Enterprise Linux (and its free Rocky clone) and SUSE Linux products  typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration.  
-
-### Siemens Questa
-
-Siemens Questa simulates behavioral, RTL and gate-level HDL.  To install Siemens Questa first go to a web browser and navigate to https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/.  Click Sign In and log in with your credentials and the product can easily be downloaded and installed.  Some  Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.
-
-### Synopsys Design Compiler (DC)
-
-Many commercial synthesis and place and route tools require a common installer.  These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer.  To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL).  Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet.  First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files.  Then, install the Installer.
-
-```bash
-$ firefox &
-```
-
-- Navigate to https://solvnet.synopsys.com
-- Log in with your institution’s username and password
-- Click on Downloads, then scroll down to Synopsys Installer
-- Select the latest version (currently 5.4).  Click Download Here, agree,
-- Click on SynopsysInstaller_v5.4.run
-- Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
-- Click on all parts and the .spf file, then click Download Files near the top
-- Move the SynopsysInstaller into `/cad/synopsys/Installer_5.4` with 755 permission for cad,
-- move other files into `/cad/synopsys/downloads` and work as user cad from here on
-
-```bash
-$ cd /cad/synopsys/installer_5.4
-$ ./SynopsysInstaller_v5.4.run
-```
-- Accept default installation directory
-```bash
-$ ./installer
-```
-- Enter source path as `/cad/synopsys/downloads`, and installation path as `/cad/synopsys`
-- When prompted, enter your site ID
-- Follow prompts
-
-Installer can be utilized in graphical or text-based modes.  It is far easier to use the text-based installation tool.  To install DC, navigate to the location where your downloaded DC files are and type installer.  You should be prompted with questions related to where you wish to have your files installed.
-
-The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify `/import/programs/synopsys` as the target directory, your installation directory structure might look like this after installation:
-
-```bash
-/import/programs/synopsys/syn/S-2021.06-SP1
-```
-
-> [!Note]
-> Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2024, the Synopsys CAD tools for SoC design are only supported on Red Hat Enterprise Linux (or AlmaLinux/Rocky) 8.4+ or 9.1+ or SUSE Linux Enterprise Server (SLES) 15.
-
-The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year.
-
-If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips.
-
-Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection.
-
-
-# Adding Cron Job for nightly builds
-
-If you want to add a cronjob you can do the following:
-1) Set up the email client `mutt` to send emails through the command line
-2) Enter `crontab -e` into a terminal
-3) add this code to test cloning CVW, making CVW's tests, then running `regression-wally --nightly --buildroot` every day at 21:30 in your local time
-```bash
-30 21 * * * curl -L https://raw.githubusercontent.com/openhwgroup/cvw/refs/heads/main/bin/nightly_build.py | python - --path {PATH_FOR_NIGHTLY_RUNS} --target all --tests all --send_email harris@hmc.edu,rose@rosethompson.net
-```
-This utility will take up approximately 100 GB on your hard drive. You can also run the script directly from `bin/nightly_build.py`.
-
-# Example wsim commands
-
-wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
-The general syntax is
-`wsim <config> <suite or elf file> [--options]`
-
-Parameters and options:
-
-```
--h, --help                                                   show this help message and exit
---elf ELF, -e ELF                                            ELF File name; use if name does not end in .elf
---sim {questa,verilator,vcs}, -s {questa,verilator,vcs}      Simulator
---tb {testbench,testbench_fp}, -t {testbench,testbench_fp}   Testbench
---gui, -g                                                    Simulate with GUI
---ccov, -c                                                   Code Coverage
---fcov, -f                                                   Functional Coverage with cvw-arch-verif, implies lockstep
---args ARGS, -a ARGS                                         Optional arguments passed to simulator via $value$plusargs
---params PARAMS, -p PARAMS            			 								 Optional top-level parameter overrides of the form param=value
---define DEFINE, -d DEFINE            											 Optional define macros passed to simulator
---vcd, -v                                                    Generate testbench.vcd
---lockstep, -l                                               Run ImperasDV lock, step, and compare.
---lockstepverbose, -lv                                       Run ImperasDV lock, step, and compare with tracing enabled
---rvvi, -r                                                   Simulate rvvi hardware interface and ethernet.
-```
-
-Run basic test with Questa
-
-```bash
-wsim rv64gc arch64i
-```
-
-Run Questa with gui
-
-```bash
-wsim rv64gc wally64priv --gui
-```
-
-Run basic test with Verilator
-
-```bash
-wsim rv32i arch32i --sim verilator
-```
-
-Run lockstep against ImperasDV with a single elf file in the gui. Lockstep requires single elf.
-
-```bash
-wsim rv64gc $WALLY/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
-```
-
-Run lockstep against ImperasDV with a single elf file. Collect functional coverage.
-
-```bash
-wsim rv64gc $WALLY/addins/cvw-arch-verif/tests/rv64/Zicsr/WALLY-COV-ALL.elf --fcov
-```
-
-Run Linux boot simulation in lock step between Wally and ImperasDV
-
-```bash
-wsim buildroot buildroot --args +INSTR_LIMIT=600000000 --lockstep
-```
+	if [ -f ~/riscv-wally/setup.sh ]; then
+		source ~/riscv-wally/setup.sh
+	fi
diff --git a/addins/README.md b/addins/README.md
deleted file mode 100644
index ba04e05eb..000000000
--- a/addins/README.md
+++ /dev/null
@@ -1,3 +0,0 @@
-verilog-ethernet contains many ethernet devices.  Wally's synthesizable RVVI interface only requires a small subset of these files.
-To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info
-This will make the working directory only contain the necessary files.
diff --git a/addins/SoftFloat-3e/COPYING.txt b/addins/SoftFloat-3e/COPYING.txt
new file mode 100644
index 000000000..9c05d49ca
--- /dev/null
+++ b/addins/SoftFloat-3e/COPYING.txt
@@ -0,0 +1,37 @@
+
+License for Berkeley SoftFloat Release 3e
+
+John R. Hauser
+2018 January 20
+
+The following applies to the whole of SoftFloat Release 3e as well as to
+each source file individually.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions, and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors
+    may be used to endorse or promote products derived from this software
+    without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/addins/SoftFloat-3e/README.html b/addins/SoftFloat-3e/README.html
new file mode 100644
index 000000000..7989e0c26
--- /dev/null
+++ b/addins/SoftFloat-3e/README.html
@@ -0,0 +1,49 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley SoftFloat Package Overview</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+<P>
+Berkeley SoftFloat is a software implementation of binary floating-point that
+conforms to the IEEE Standard for Floating-Point Arithmetic.
+SoftFloat is distributed in the form of C source code.
+Building the SoftFloat sources generates a library file (typically
+<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
+floating-point subroutines.
+</P>
+
+<P>
+The SoftFloat package is documented in the following files in the
+<CODE>doc</CODE> subdirectory:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
+<TD>Documentation for using the SoftFloat functions.</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
+<TD>Documentation for building SoftFloat.</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></NOBR></TD>
+<TD>History of the major changes to SoftFloat.</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+Other files in the package comprise the source code for SoftFloat.
+</P>
+
+</BODY>
+
diff --git a/addins/SoftFloat-3e/README.txt b/addins/SoftFloat-3e/README.txt
new file mode 100644
index 000000000..f819baa5c
--- /dev/null
+++ b/addins/SoftFloat-3e/README.txt
@@ -0,0 +1,21 @@
+
+Package Overview for Berkeley SoftFloat Release 3e
+
+John R. Hauser
+2018 January 20
+
+Berkeley SoftFloat is a software implementation of binary floating-point
+that conforms to the IEEE Standard for Floating-Point Arithmetic.  SoftFloat
+is distributed in the form of C source code.  Building the SoftFloat sources
+generates a library file (typically "softfloat.a" or "libsoftfloat.a")
+containing the floating-point subroutines.
+
+The SoftFloat package is documented in the following files in the "doc"
+subdirectory:
+
+    SoftFloat.html          Documentation for using the SoftFloat functions.
+    SoftFloat-source.html   Documentation for building SoftFloat.
+    SoftFloat-history.html  History of the major changes to SoftFloat.
+
+Other files in the package comprise the source code for SoftFloat.
+
diff --git a/addins/SoftFloat-3e/build/Linux-386-GCC/Makefile b/addins/SoftFloat-3e/build/Linux-386-GCC/Makefile
new file mode 100644
index 000000000..418160051
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-386-GCC/Makefile
@@ -0,0 +1,325 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Linux-386-GCC/platform.h b/addins/SoftFloat-3e/build/Linux-386-GCC/platform.h
new file mode 100644
index 000000000..420aa4e04
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-386-GCC/platform.h
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile b/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile
new file mode 100644
index 000000000..1cf6f5e1a
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile
@@ -0,0 +1,325 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086-SSE
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/platform.h b/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/platform.h
new file mode 100644
index 000000000..420aa4e04
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-386-SSE2-GCC/platform.h
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile b/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile
new file mode 100644
index 000000000..2565fe56c
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile
@@ -0,0 +1,323 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= ARM-VFPv2
+
+SOFTFLOAT_OPTS ?= -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h b/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h
new file mode 100644
index 000000000..420aa4e04
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile
new file mode 100644
index 000000000..570337825
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile
@@ -0,0 +1,390 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086-SSE
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration -DSOFTFLOAT_FAST_INT64 \
+    $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_eq128$(OBJ) \
+  s_le128$(OBJ) \
+  s_lt128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_add128$(OBJ) \
+  s_add256M$(OBJ) \
+  s_sub128$(OBJ) \
+  s_sub256M$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64To128$(OBJ) \
+  s_mul128By32$(OBJ) \
+  s_mul128To256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
+  s_roundPackToF128$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80_to_ui32$(OBJ) \
+  extF80_to_ui64$(OBJ) \
+  extF80_to_i32$(OBJ) \
+  extF80_to_i64$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_to_f16$(OBJ) \
+  extF80_to_f32$(OBJ) \
+  extF80_to_f64$(OBJ) \
+  extF80_to_f128$(OBJ) \
+  extF80_roundToInt$(OBJ) \
+  extF80_add$(OBJ) \
+  extF80_sub$(OBJ) \
+  extF80_mul$(OBJ) \
+  extF80_div$(OBJ) \
+  extF80_rem$(OBJ) \
+  extF80_sqrt$(OBJ) \
+  extF80_eq$(OBJ) \
+  extF80_le$(OBJ) \
+  extF80_lt$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
+  extF80_le_quiet$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128_to_ui32$(OBJ) \
+  f128_to_ui64$(OBJ) \
+  f128_to_i32$(OBJ) \
+  f128_to_i64$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
+  f128_to_f16$(OBJ) \
+  f128_to_f32$(OBJ) \
+  f128_to_extF80$(OBJ) \
+  f128_to_f64$(OBJ) \
+  f128_roundToInt$(OBJ) \
+  f128_add$(OBJ) \
+  f128_sub$(OBJ) \
+  f128_mul$(OBJ) \
+  f128_mulAdd$(OBJ) \
+  f128_div$(OBJ) \
+  f128_rem$(OBJ) \
+  f128_sqrt$(OBJ) \
+  f128_eq$(OBJ) \
+  f128_le$(OBJ) \
+  f128_lt$(OBJ) \
+  f128_eq_signaling$(OBJ) \
+  f128_le_quiet$(OBJ) \
+  f128_lt_quiet$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/platform.h b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/platform.h
new file mode 100644
index 000000000..2fccb6c09
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/platform.h
@@ -0,0 +1,54 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_INTRINSIC_INT128 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
new file mode 100644
index 000000000..69cd932a8
Binary files /dev/null and b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a differ
diff --git a/addins/SoftFloat-3e/build/Win32-MinGW/Makefile b/addins/SoftFloat-3e/build/Win32-MinGW/Makefile
new file mode 100644
index 000000000..418160051
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win32-MinGW/Makefile
@@ -0,0 +1,325 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Win32-MinGW/platform.h b/addins/SoftFloat-3e/build/Win32-MinGW/platform.h
new file mode 100644
index 000000000..420aa4e04
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win32-MinGW/platform.h
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile b/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile
new file mode 100644
index 000000000..1cf6f5e1a
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile
@@ -0,0 +1,325 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086-SSE
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(SOFTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+MAKELIB = ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/platform.h b/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/platform.h
new file mode 100644
index 000000000..420aa4e04
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win32-SSE2-MinGW/platform.h
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/Win64-MinGW-w64/Makefile b/addins/SoftFloat-3e/build/Win64-MinGW-w64/Makefile
new file mode 100644
index 000000000..05bbf5bb5
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win64-MinGW-w64/Makefile
@@ -0,0 +1,390 @@
+
+#=============================================================================
+#
+# This Makefile is part of the SoftFloat IEEE Floating-Point Arithmetic
+# Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SPECIALIZE_TYPE ?= 8086-SSE
+
+SOFTFLOAT_OPTS ?= \
+  -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+  -DSOFTFLOAT_FAST_DIV64TO32
+
+DELETE = rm -f
+C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+COMPILE_C = \
+  x86_64-w64-mingw32-gcc -c -Werror-implicit-function-declaration \
+    -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+MAKELIB = x86_64-w64-mingw32-ar crs $@
+
+OBJ = .o
+LIB = .a
+
+OTHER_HEADERS = $(SOURCE_DIR)/include/opts-GCC.h
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_eq128$(OBJ) \
+  s_le128$(OBJ) \
+  s_lt128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_add128$(OBJ) \
+  s_add256M$(OBJ) \
+  s_sub128$(OBJ) \
+  s_sub256M$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64To128$(OBJ) \
+  s_mul128By32$(OBJ) \
+  s_mul128To256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
+  s_roundPackToF128$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80_to_ui32$(OBJ) \
+  extF80_to_ui64$(OBJ) \
+  extF80_to_i32$(OBJ) \
+  extF80_to_i64$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_to_f16$(OBJ) \
+  extF80_to_f32$(OBJ) \
+  extF80_to_f64$(OBJ) \
+  extF80_to_f128$(OBJ) \
+  extF80_roundToInt$(OBJ) \
+  extF80_add$(OBJ) \
+  extF80_sub$(OBJ) \
+  extF80_mul$(OBJ) \
+  extF80_div$(OBJ) \
+  extF80_rem$(OBJ) \
+  extF80_sqrt$(OBJ) \
+  extF80_eq$(OBJ) \
+  extF80_le$(OBJ) \
+  extF80_lt$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
+  extF80_le_quiet$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128_to_ui32$(OBJ) \
+  f128_to_ui64$(OBJ) \
+  f128_to_i32$(OBJ) \
+  f128_to_i64$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
+  f128_to_f16$(OBJ) \
+  f128_to_f32$(OBJ) \
+  f128_to_extF80$(OBJ) \
+  f128_to_f64$(OBJ) \
+  f128_roundToInt$(OBJ) \
+  f128_add$(OBJ) \
+  f128_sub$(OBJ) \
+  f128_mul$(OBJ) \
+  f128_mulAdd$(OBJ) \
+  f128_div$(OBJ) \
+  f128_rem$(OBJ) \
+  f128_sqrt$(OBJ) \
+  f128_eq$(OBJ) \
+  f128_le$(OBJ) \
+  f128_lt$(OBJ) \
+  f128_eq_signaling$(OBJ) \
+  f128_le_quiet$(OBJ) \
+  f128_lt_quiet$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/Win64-MinGW-w64/platform.h b/addins/SoftFloat-3e/build/Win64-MinGW-w64/platform.h
new file mode 100644
index 000000000..2fccb6c09
--- /dev/null
+++ b/addins/SoftFloat-3e/build/Win64-MinGW-w64/platform.h
@@ -0,0 +1,54 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define SOFTFLOAT_BUILTIN_CLZ 1
+#define SOFTFLOAT_INTRINSIC_INT128 1
+#include "opts-GCC.h"
+
diff --git a/addins/SoftFloat-3e/build/template-FAST_INT64/Makefile b/addins/SoftFloat-3e/build/template-FAST_INT64/Makefile
new file mode 100644
index 000000000..c5005e6e3
--- /dev/null
+++ b/addins/SoftFloat-3e/build/template-FAST_INT64/Makefile
@@ -0,0 +1,391 @@
+
+#=============================================================================
+#
+# This Makefile template is part of the SoftFloat IEEE Floating-Point
+# Arithmetic Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+# Edit lines marked with `==>'.  See "SoftFloat-source.html".
+
+==> SOURCE_DIR ?= ../../source
+==> SPECIALIZE_TYPE ?= 8086
+
+==> SOFTFLOAT_OPTS ?= \
+==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+==>   -DSOFTFLOAT_FAST_DIV64TO32
+
+==> DELETE = rm -f
+==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+==> COMPILE_C = \
+==>   cc -c -DSOFTFLOAT_FAST_INT64 $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+==> MAKELIB = ar crs $@
+
+==> OBJ = .o
+==> LIB = .a
+
+==> OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_eq128$(OBJ) \
+  s_le128$(OBJ) \
+  s_lt128$(OBJ) \
+  s_shortShiftLeft128$(OBJ) \
+  s_shortShiftRight128$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJam64Extra$(OBJ) \
+  s_shortShiftRightJam128$(OBJ) \
+  s_shortShiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJam64Extra$(OBJ) \
+  s_shiftRightJam128$(OBJ) \
+  s_shiftRightJam128Extra$(OBJ) \
+  s_shiftRightJam256M$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_add128$(OBJ) \
+  s_add256M$(OBJ) \
+  s_sub128$(OBJ) \
+  s_sub256M$(OBJ) \
+  s_mul64ByShifted32To128$(OBJ) \
+  s_mul64To128$(OBJ) \
+  s_mul128By32$(OBJ) \
+  s_mul128To256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80UIToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80UI$(OBJ) \
+  s_propagateNaNExtF80UI$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128UIToCommonNaN$(OBJ) \
+  s_commonNaNToF128UI$(OBJ) \
+  s_propagateNaNF128UI$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_normSubnormalExtF80Sig$(OBJ) \
+  s_roundPackToExtF80$(OBJ) \
+  s_normRoundPackToExtF80$(OBJ) \
+  s_addMagsExtF80$(OBJ) \
+  s_subMagsExtF80$(OBJ) \
+  s_normSubnormalF128Sig$(OBJ) \
+  s_roundPackToF128$(OBJ) \
+  s_normRoundPackToF128$(OBJ) \
+  s_addMagsF128$(OBJ) \
+  s_subMagsF128$(OBJ) \
+  s_mulAddF128$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80_to_ui32$(OBJ) \
+  extF80_to_ui64$(OBJ) \
+  extF80_to_i32$(OBJ) \
+  extF80_to_i64$(OBJ) \
+  extF80_to_ui32_r_minMag$(OBJ) \
+  extF80_to_ui64_r_minMag$(OBJ) \
+  extF80_to_i32_r_minMag$(OBJ) \
+  extF80_to_i64_r_minMag$(OBJ) \
+  extF80_to_f16$(OBJ) \
+  extF80_to_f32$(OBJ) \
+  extF80_to_f64$(OBJ) \
+  extF80_to_f128$(OBJ) \
+  extF80_roundToInt$(OBJ) \
+  extF80_add$(OBJ) \
+  extF80_sub$(OBJ) \
+  extF80_mul$(OBJ) \
+  extF80_div$(OBJ) \
+  extF80_rem$(OBJ) \
+  extF80_sqrt$(OBJ) \
+  extF80_eq$(OBJ) \
+  extF80_le$(OBJ) \
+  extF80_lt$(OBJ) \
+  extF80_eq_signaling$(OBJ) \
+  extF80_le_quiet$(OBJ) \
+  extF80_lt_quiet$(OBJ) \
+  extF80_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128_to_ui32$(OBJ) \
+  f128_to_ui64$(OBJ) \
+  f128_to_i32$(OBJ) \
+  f128_to_i64$(OBJ) \
+  f128_to_ui32_r_minMag$(OBJ) \
+  f128_to_ui64_r_minMag$(OBJ) \
+  f128_to_i32_r_minMag$(OBJ) \
+  f128_to_i64_r_minMag$(OBJ) \
+  f128_to_f16$(OBJ) \
+  f128_to_f32$(OBJ) \
+  f128_to_extF80$(OBJ) \
+  f128_to_f64$(OBJ) \
+  f128_roundToInt$(OBJ) \
+  f128_add$(OBJ) \
+  f128_sub$(OBJ) \
+  f128_mul$(OBJ) \
+  f128_mulAdd$(OBJ) \
+  f128_div$(OBJ) \
+  f128_rem$(OBJ) \
+  f128_sqrt$(OBJ) \
+  f128_eq$(OBJ) \
+  f128_le$(OBJ) \
+  f128_lt$(OBJ) \
+  f128_eq_signaling$(OBJ) \
+  f128_le_quiet$(OBJ) \
+  f128_lt_quiet$(OBJ) \
+  f128_isSignalingNaN$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/template-FAST_INT64/platform.h b/addins/SoftFloat-3e/build/template-FAST_INT64/platform.h
new file mode 100644
index 000000000..b63e2a720
--- /dev/null
+++ b/addins/SoftFloat-3e/build/template-FAST_INT64/platform.h
@@ -0,0 +1,50 @@
+
+/*============================================================================
+
+This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+// Edit lines marked with `==>'.  See "SoftFloat-source.html".
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define INLINE inline
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define THREAD_LOCAL _Thread_local
+
diff --git a/addins/SoftFloat-3e/build/template-not-FAST_INT64/Makefile b/addins/SoftFloat-3e/build/template-not-FAST_INT64/Makefile
new file mode 100644
index 000000000..49fddfd02
--- /dev/null
+++ b/addins/SoftFloat-3e/build/template-not-FAST_INT64/Makefile
@@ -0,0 +1,325 @@
+
+#=============================================================================
+#
+# This Makefile template is part of the SoftFloat IEEE Floating-Point
+# Arithmetic Package, Release 3e, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+# Edit lines marked with `==>'.  See "SoftFloat-source.html".
+
+==> SOURCE_DIR ?= ../../source
+==> SPECIALIZE_TYPE ?= 8086
+
+==> SOFTFLOAT_OPTS ?= \
+==>   -DSOFTFLOAT_ROUND_ODD -DINLINE_LEVEL=5 -DSOFTFLOAT_FAST_DIV32TO16 \
+==>   -DSOFTFLOAT_FAST_DIV64TO32
+
+==> DELETE = rm -f
+==> C_INCLUDES = -I. -I$(SOURCE_DIR)/$(SPECIALIZE_TYPE) -I$(SOURCE_DIR)/include
+==> COMPILE_C = cc -c $(SOFTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+==> MAKELIB = ar crs $@
+
+==> OBJ = .o
+==> LIB = .a
+
+==> OTHER_HEADERS =
+
+.PHONY: all
+all: softfloat$(LIB)
+
+OBJS_PRIMITIVES = \
+  s_compare96M$(OBJ) \
+  s_compare128M$(OBJ) \
+  s_shortShiftLeft64To96M$(OBJ) \
+  s_shortShiftLeftM$(OBJ) \
+  s_shiftLeftM$(OBJ) \
+  s_shortShiftRightM$(OBJ) \
+  s_shortShiftRightJam64$(OBJ) \
+  s_shortShiftRightJamM$(OBJ) \
+  s_shiftRightJam32$(OBJ) \
+  s_shiftRightJam64$(OBJ) \
+  s_shiftRightJamM$(OBJ) \
+  s_shiftRightM$(OBJ) \
+  s_countLeadingZeros8$(OBJ) \
+  s_countLeadingZeros16$(OBJ) \
+  s_countLeadingZeros32$(OBJ) \
+  s_countLeadingZeros64$(OBJ) \
+  s_addM$(OBJ) \
+  s_addCarryM$(OBJ) \
+  s_addComplCarryM$(OBJ) \
+  s_negXM$(OBJ) \
+  s_sub1XM$(OBJ) \
+  s_subM$(OBJ) \
+  s_mul64To128M$(OBJ) \
+  s_mul128MTo256M$(OBJ) \
+  s_approxRecip_1Ks$(OBJ) \
+  s_approxRecip32_1$(OBJ) \
+  s_approxRecipSqrt_1Ks$(OBJ) \
+  s_approxRecipSqrt32_1$(OBJ) \
+  s_remStepMBy32$(OBJ) \
+
+OBJS_SPECIALIZE = \
+  softfloat_raiseFlags$(OBJ) \
+  s_f16UIToCommonNaN$(OBJ) \
+  s_commonNaNToF16UI$(OBJ) \
+  s_propagateNaNF16UI$(OBJ) \
+  s_f32UIToCommonNaN$(OBJ) \
+  s_commonNaNToF32UI$(OBJ) \
+  s_propagateNaNF32UI$(OBJ) \
+  s_f64UIToCommonNaN$(OBJ) \
+  s_commonNaNToF64UI$(OBJ) \
+  s_propagateNaNF64UI$(OBJ) \
+  extF80M_isSignalingNaN$(OBJ) \
+  s_extF80MToCommonNaN$(OBJ) \
+  s_commonNaNToExtF80M$(OBJ) \
+  s_propagateNaNExtF80M$(OBJ) \
+  f128M_isSignalingNaN$(OBJ) \
+  s_f128MToCommonNaN$(OBJ) \
+  s_commonNaNToF128M$(OBJ) \
+  s_propagateNaNF128M$(OBJ) \
+
+OBJS_OTHERS = \
+  s_roundToUI32$(OBJ) \
+  s_roundMToUI64$(OBJ) \
+  s_roundToI32$(OBJ) \
+  s_roundMToI64$(OBJ) \
+  s_normSubnormalF16Sig$(OBJ) \
+  s_roundPackToF16$(OBJ) \
+  s_normRoundPackToF16$(OBJ) \
+  s_addMagsF16$(OBJ) \
+  s_subMagsF16$(OBJ) \
+  s_mulAddF16$(OBJ) \
+  s_normSubnormalF32Sig$(OBJ) \
+  s_roundPackToF32$(OBJ) \
+  s_normRoundPackToF32$(OBJ) \
+  s_addMagsF32$(OBJ) \
+  s_subMagsF32$(OBJ) \
+  s_mulAddF32$(OBJ) \
+  s_normSubnormalF64Sig$(OBJ) \
+  s_roundPackToF64$(OBJ) \
+  s_normRoundPackToF64$(OBJ) \
+  s_addMagsF64$(OBJ) \
+  s_subMagsF64$(OBJ) \
+  s_mulAddF64$(OBJ) \
+  s_tryPropagateNaNExtF80M$(OBJ) \
+  s_invalidExtF80M$(OBJ) \
+  s_normExtF80SigM$(OBJ) \
+  s_roundPackMToExtF80M$(OBJ) \
+  s_normRoundPackMToExtF80M$(OBJ) \
+  s_addExtF80M$(OBJ) \
+  s_compareNonnormExtF80M$(OBJ) \
+  s_isNaNF128M$(OBJ) \
+  s_tryPropagateNaNF128M$(OBJ) \
+  s_invalidF128M$(OBJ) \
+  s_shiftNormSigF128M$(OBJ) \
+  s_roundPackMToF128M$(OBJ) \
+  s_normRoundPackMToF128M$(OBJ) \
+  s_addF128M$(OBJ) \
+  s_mulAddF128M$(OBJ) \
+  softfloat_state$(OBJ) \
+  ui32_to_f16$(OBJ) \
+  ui32_to_f32$(OBJ) \
+  ui32_to_f64$(OBJ) \
+  ui32_to_extF80M$(OBJ) \
+  ui32_to_f128M$(OBJ) \
+  ui64_to_f16$(OBJ) \
+  ui64_to_f32$(OBJ) \
+  ui64_to_f64$(OBJ) \
+  ui64_to_extF80M$(OBJ) \
+  ui64_to_f128M$(OBJ) \
+  i32_to_f16$(OBJ) \
+  i32_to_f32$(OBJ) \
+  i32_to_f64$(OBJ) \
+  i32_to_extF80M$(OBJ) \
+  i32_to_f128M$(OBJ) \
+  i64_to_f16$(OBJ) \
+  i64_to_f32$(OBJ) \
+  i64_to_f64$(OBJ) \
+  i64_to_extF80M$(OBJ) \
+  i64_to_f128M$(OBJ) \
+  f16_to_ui32$(OBJ) \
+  f16_to_ui64$(OBJ) \
+  f16_to_i32$(OBJ) \
+  f16_to_i64$(OBJ) \
+  f16_to_ui32_r_minMag$(OBJ) \
+  f16_to_ui64_r_minMag$(OBJ) \
+  f16_to_i32_r_minMag$(OBJ) \
+  f16_to_i64_r_minMag$(OBJ) \
+  f16_to_f32$(OBJ) \
+  f16_to_f64$(OBJ) \
+  f16_to_extF80M$(OBJ) \
+  f16_to_f128M$(OBJ) \
+  f16_roundToInt$(OBJ) \
+  f16_add$(OBJ) \
+  f16_sub$(OBJ) \
+  f16_mul$(OBJ) \
+  f16_mulAdd$(OBJ) \
+  f16_div$(OBJ) \
+  f16_rem$(OBJ) \
+  f16_sqrt$(OBJ) \
+  f16_eq$(OBJ) \
+  f16_le$(OBJ) \
+  f16_lt$(OBJ) \
+  f16_eq_signaling$(OBJ) \
+  f16_le_quiet$(OBJ) \
+  f16_lt_quiet$(OBJ) \
+  f16_isSignalingNaN$(OBJ) \
+  f32_to_ui32$(OBJ) \
+  f32_to_ui64$(OBJ) \
+  f32_to_i32$(OBJ) \
+  f32_to_i64$(OBJ) \
+  f32_to_ui32_r_minMag$(OBJ) \
+  f32_to_ui64_r_minMag$(OBJ) \
+  f32_to_i32_r_minMag$(OBJ) \
+  f32_to_i64_r_minMag$(OBJ) \
+  f32_to_f16$(OBJ) \
+  f32_to_f64$(OBJ) \
+  f32_to_extF80M$(OBJ) \
+  f32_to_f128M$(OBJ) \
+  f32_roundToInt$(OBJ) \
+  f32_add$(OBJ) \
+  f32_sub$(OBJ) \
+  f32_mul$(OBJ) \
+  f32_mulAdd$(OBJ) \
+  f32_div$(OBJ) \
+  f32_rem$(OBJ) \
+  f32_sqrt$(OBJ) \
+  f32_eq$(OBJ) \
+  f32_le$(OBJ) \
+  f32_lt$(OBJ) \
+  f32_eq_signaling$(OBJ) \
+  f32_le_quiet$(OBJ) \
+  f32_lt_quiet$(OBJ) \
+  f32_isSignalingNaN$(OBJ) \
+  f64_to_ui32$(OBJ) \
+  f64_to_ui64$(OBJ) \
+  f64_to_i32$(OBJ) \
+  f64_to_i64$(OBJ) \
+  f64_to_ui32_r_minMag$(OBJ) \
+  f64_to_ui64_r_minMag$(OBJ) \
+  f64_to_i32_r_minMag$(OBJ) \
+  f64_to_i64_r_minMag$(OBJ) \
+  f64_to_f16$(OBJ) \
+  f64_to_f32$(OBJ) \
+  f64_to_extF80M$(OBJ) \
+  f64_to_f128M$(OBJ) \
+  f64_roundToInt$(OBJ) \
+  f64_add$(OBJ) \
+  f64_sub$(OBJ) \
+  f64_mul$(OBJ) \
+  f64_mulAdd$(OBJ) \
+  f64_div$(OBJ) \
+  f64_rem$(OBJ) \
+  f64_sqrt$(OBJ) \
+  f64_eq$(OBJ) \
+  f64_le$(OBJ) \
+  f64_lt$(OBJ) \
+  f64_eq_signaling$(OBJ) \
+  f64_le_quiet$(OBJ) \
+  f64_lt_quiet$(OBJ) \
+  f64_isSignalingNaN$(OBJ) \
+  extF80M_to_ui32$(OBJ) \
+  extF80M_to_ui64$(OBJ) \
+  extF80M_to_i32$(OBJ) \
+  extF80M_to_i64$(OBJ) \
+  extF80M_to_ui32_r_minMag$(OBJ) \
+  extF80M_to_ui64_r_minMag$(OBJ) \
+  extF80M_to_i32_r_minMag$(OBJ) \
+  extF80M_to_i64_r_minMag$(OBJ) \
+  extF80M_to_f16$(OBJ) \
+  extF80M_to_f32$(OBJ) \
+  extF80M_to_f64$(OBJ) \
+  extF80M_to_f128M$(OBJ) \
+  extF80M_roundToInt$(OBJ) \
+  extF80M_add$(OBJ) \
+  extF80M_sub$(OBJ) \
+  extF80M_mul$(OBJ) \
+  extF80M_div$(OBJ) \
+  extF80M_rem$(OBJ) \
+  extF80M_sqrt$(OBJ) \
+  extF80M_eq$(OBJ) \
+  extF80M_le$(OBJ) \
+  extF80M_lt$(OBJ) \
+  extF80M_eq_signaling$(OBJ) \
+  extF80M_le_quiet$(OBJ) \
+  extF80M_lt_quiet$(OBJ) \
+  f128M_to_ui32$(OBJ) \
+  f128M_to_ui64$(OBJ) \
+  f128M_to_i32$(OBJ) \
+  f128M_to_i64$(OBJ) \
+  f128M_to_ui32_r_minMag$(OBJ) \
+  f128M_to_ui64_r_minMag$(OBJ) \
+  f128M_to_i32_r_minMag$(OBJ) \
+  f128M_to_i64_r_minMag$(OBJ) \
+  f128M_to_f16$(OBJ) \
+  f128M_to_f32$(OBJ) \
+  f128M_to_f64$(OBJ) \
+  f128M_to_extF80M$(OBJ) \
+  f128M_roundToInt$(OBJ) \
+  f128M_add$(OBJ) \
+  f128M_sub$(OBJ) \
+  f128M_mul$(OBJ) \
+  f128M_mulAdd$(OBJ) \
+  f128M_div$(OBJ) \
+  f128M_rem$(OBJ) \
+  f128M_sqrt$(OBJ) \
+  f128M_eq$(OBJ) \
+  f128M_le$(OBJ) \
+  f128M_lt$(OBJ) \
+  f128M_eq_signaling$(OBJ) \
+  f128M_le_quiet$(OBJ) \
+  f128M_lt_quiet$(OBJ) \
+
+OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS)
+
+$(OBJS_ALL): \
+  $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \
+  $(SOURCE_DIR)/include/primitives.h
+$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \
+  $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \
+  $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \
+  $(SOURCE_DIR)/include/softfloat.h
+
+$(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+
+$(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c
+
+softfloat$(LIB): $(OBJS_ALL)
+	$(DELETE) $@
+	$(MAKELIB) $^
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_ALL) softfloat$(LIB)
+
diff --git a/addins/SoftFloat-3e/build/template-not-FAST_INT64/platform.h b/addins/SoftFloat-3e/build/template-not-FAST_INT64/platform.h
new file mode 100644
index 000000000..b63e2a720
--- /dev/null
+++ b/addins/SoftFloat-3e/build/template-not-FAST_INT64/platform.h
@@ -0,0 +1,50 @@
+
+/*============================================================================
+
+This C header template is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+// Edit lines marked with `==>'.  See "SoftFloat-source.html".
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define INLINE inline
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define THREAD_LOCAL _Thread_local
+
diff --git a/addins/SoftFloat-3e/doc/SoftFloat-history.html b/addins/SoftFloat-3e/doc/SoftFloat-history.html
new file mode 100644
index 000000000..daa48ca3b
--- /dev/null
+++ b/addins/SoftFloat-3e/doc/SoftFloat-history.html
@@ -0,0 +1,258 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley SoftFloat History</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>History of Berkeley SoftFloat, to Release 3e</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H3>Release 3e (2018 January)</H3>
+
+<UL>
+
+<LI>
+Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
+(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
+
+<LI>
+Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
+integer value (either conversion to an integer format or a
+&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
+Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
+as rounding to minimum magnitude.
+Now all operations are rounded consistently.
+
+<LI>
+Fixed some errors in the specialization code modeling Intel x86 floating-point,
+specifically the integers returned on invalid operations and the propagation of
+NaN payloads in a few rare cases.
+
+<LI>
+Added specialization code modeling ARM floating-point, conforming to VFPv2 or
+later.
+
+<LI>
+Added an example target for ARM processors.
+
+<LI>
+Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
+different integer than expected in the case that the floating-point operand is
+negative.
+
+<LI>
+Added example target-specific optimization for GCC, employing GCC instrinsics
+and support for <NOBR>128-bit</NOBR> integer arithmetic.
+
+<LI>
+Made other minor improvements.
+
+</UL>
+
+
+<H3>Release 3d (2017 August)</H3>
+
+<UL>
+
+<LI>
+Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
+double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
+<NOBR>128-bit</NOBR> quadruple-precision.
+For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
+could sometimes be off by <NOBR>1 unit</NOBR> in the last place
+(<NOBR>1 ulp</NOBR>) from what it should be.
+For the larger formats, the square root could be wrong in a large portion of
+the less-significant bits.
+(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
+
+</UL>
+
+
+<H3>Release 3c (2017 February)</H3>
+
+<UL>
+
+<LI>
+Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
+<EM>jamming</EM>).
+
+<LI>
+Corrected the documentation concerning non-canonical representations in
+<NOBR>80-bit</NOBR> double-extended-precision.
+
+</UL>
+
+
+<H3>Release 3b (2016 July)</H3>
+
+<UL>
+
+<LI>
+Implemented the common <NOBR>16-bit</NOBR> &ldquo;half-precision&rdquo;
+floating-point format (<CODE>float16_t</CODE>).
+
+<LI>
+Made the integer values returned on invalid conversions to integer formats
+be determined by the port-specific specialization instead of being the same for
+all ports.
+
+<LI>
+Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
+state (modes and exception flags) to be made per-thread.
+
+<LI>
+Modified the provided Makefiles to allow some options to be overridden from the
+<CODE>make</CODE> command.
+
+<LI>
+Made other minor improvements.
+
+</UL>
+
+
+<H3>Release 3a (2015 October)</H3>
+
+<UL>
+
+<LI>
+Replaced the license text supplied by the University of California, Berkeley.
+
+</UL>
+
+
+<H3>Release 3 (2015 February)</H3>
+
+<UL>
+
+<LI>
+Complete rewrite, funded by the University of California, Berkeley, and
+consequently having a different use license than earlier releases.
+Major changes included renaming most types and functions, upgrading some
+algorithms, restructuring the source files, and making SoftFloat into a true
+library.
+
+<LI>
+Added functions to convert between floating-point and unsigned integers, both
+<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
+<CODE>uint64_t</CODE>).
+
+<LI>
+Added functions for fused multiply-add, for all supported floating-point
+formats except <NOBR>80-bit</NOBR> double-extended-precision.
+
+<LI>
+Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
+nearest, with ties to maximum magnitude, away from zero).
+
+<LI>
+Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
+TestFloat package).
+
+</UL>
+
+
+<H3>Release 2c (2015 January)</H3>
+
+<UL>
+
+<LI>
+Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
+
+<LI>
+Further improved the documentation and the wording for the legal restrictions
+on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
+<NOBR>Release 3</NOBR> or later).
+
+</UL>
+
+
+<H3>Release 2b (2002 May)</H3>
+
+<UL>
+
+<LI>
+Made minor updates to the documentation, including improved wording for the
+legal restrictions on using SoftFloat.
+
+</UL>
+
+
+<H3>Release 2a (1998 December)</H3>
+
+<UL>
+
+<LI>
+Added functions to convert between <NOBR>64-bit</NOBR> integers
+(<CODE>int64</CODE>) and all supported floating-point formats.
+
+<LI>
+Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
+<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
+<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
+be.
+(Bug discovered by Paul Donahue.)
+
+<LI>
+Improved the Makefiles.
+</UL>
+
+
+<H3>Release 2 (1997 June)</H3>
+
+<UL>
+
+<LI>
+Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
+<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
+
+<LI>
+Changed the source directory structure, splitting the sources into a
+<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
+Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
+with environment variables.
+
+<LI>
+Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
+round the wrong way in nearest/even mode when the operand was between
+2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
+
+</UL>
+
+
+<H3>Release 1a (1996 July)</H3>
+
+<UL>
+
+<LI>
+Corrected a mistake that caused borderline underflow cases not to raise the
+underflow flag when they should have.
+(Problem reported by Doug Priest.)
+
+<LI>
+Added the <CODE>float_detect_tininess</CODE> variable to control whether
+tininess is detected before or after rounding.
+
+</UL>
+
+
+<H3>Release 1 (1996 July)</H3>
+
+<UL>
+
+<LI>
+Original release, based on work done for the International Computer Science
+Institute (ICSI) in Berkeley, California.
+
+</UL>
+
+
+</BODY>
+
diff --git a/addins/SoftFloat-3e/doc/SoftFloat-source.html b/addins/SoftFloat-3e/doc/SoftFloat-source.html
new file mode 100644
index 000000000..d4b85f7b0
--- /dev/null
+++ b/addins/SoftFloat-3e/doc/SoftFloat-source.html
@@ -0,0 +1,686 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley SoftFloat Source Documentation</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley SoftFloat Release 3e: Source Documentation</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Contents</H2>
+
+<BLOCKQUOTE>
+<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
+<COL WIDTH=25>
+<COL WIDTH=*>
+<TR><TD COLSPAN=2>1. Introduction</TD></TR>
+<TR><TD COLSPAN=2>2. Limitations</TD></TR>
+<TR><TD COLSPAN=2>3. Acknowledgments and License</TD></TR>
+<TR><TD COLSPAN=2>4. SoftFloat Package Directory Structure</TD></TR>
+<TR><TD COLSPAN=2>5. Issues for Porting SoftFloat to a New Target</TD></TR>
+<TR>
+  <TD></TD>
+  <TD>5.1. Standard Headers <CODE>&lt;stdbool.h&gt;</CODE> and
+    <CODE>&lt;stdint.h&gt;</CODE></TD>
+</TR>
+<TR><TD></TD><TD>5.2. Specializing Floating-Point Behavior</TD></TR>
+<TR><TD></TD><TD>5.3. Macros for Build Options</TD></TR>
+<TR><TD></TD><TD>5.4. Adapting a Template Target Directory</TD></TR>
+<TR>
+  <TD></TD><TD>5.5. Target-Specific Optimization of Primitive Functions</TD>
+</TR>
+<TR><TD COLSPAN=2>6. Testing SoftFloat</TD></TR>
+<TR>
+  <TD COLSPAN=2>7. Providing SoftFloat as a Common Library for Applications</TD>
+</TR>
+<TR><TD COLSPAN=2>8. Contact Information</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+
+
+<H2>1. Introduction</H2>
+
+<P>
+This document gives information needed for compiling and/or porting Berkeley
+SoftFloat, a library of C functions implementing binary floating-point
+conforming to the IEEE Standard for Floating-Point Arithmetic.
+For basic documentation about SoftFloat refer to
+<A HREF="SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A>.
+</P>
+
+<P>
+The source code for SoftFloat is intended to be relatively machine-independent
+and should be compilable with any ISO-Standard C compiler that also supports
+<NOBR>64-bit</NOBR> integers.
+SoftFloat has been successfully compiled with the GNU C Compiler
+(<CODE>gcc</CODE>) for several platforms.
+</P>
+
+<P>
+<NOBR>Release 3</NOBR> of SoftFloat was a complete rewrite relative to
+<NOBR>Release 2</NOBR> or earlier.
+Changes to the interface of SoftFloat functions are documented in
+<A HREF="SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A>.
+The current version of SoftFloat is <NOBR>Release 3e</NOBR>.
+</P>
+
+
+<H2>2. Limitations</H2>
+
+<P>
+SoftFloat assumes the computer has an addressable byte size of either 8 or
+<NOBR>16 bits</NOBR>.
+(Nearly all computers in use today have <NOBR>8-bit</NOBR> bytes.)
+</P>
+
+<P>
+SoftFloat is written in C and is designed to work with other C code.
+The C compiler used must conform at a minimum to the 1989 ANSI standard for the
+C language (same as the 1990 ISO standard) and must in addition support basic
+arithmetic on <NOBR>64-bit</NOBR> integers.
+Earlier releases of SoftFloat included implementations of <NOBR>32-bit</NOBR>
+single-precision and <NOBR>64-bit</NOBR> double-precision floating-point that
+did not require <NOBR>64-bit</NOBR> integers, but this option is not supported
+starting with <NOBR>Release 3</NOBR>.
+Since 1999, ISO standards for C have mandated compiler support for
+<NOBR>64-bit</NOBR> integers.
+A compiler conforming to the 1999 C Standard or later is recommended but not
+strictly required.
+</P>
+
+<P>
+<NOBR>C Standard</NOBR> header files <CODE>&lt;stdbool.h&gt;</CODE> and
+<CODE>&lt;stdint.h&gt;</CODE> are required for defining standard Boolean and
+integer types.
+If these headers are not supplied with the C compiler, minimal substitutes must
+be provided.
+SoftFloat&rsquo;s dependence on these headers is detailed later in
+<NOBR>section 5.1</NOBR>, <I>Standard Headers <CODE>&lt;stdbool.h&gt;</CODE>
+and <CODE>&lt;stdint.h&gt;</CODE></I>.
+</P>
+
+
+<H2>3. Acknowledgments and License</H2>
+
+<P>
+The SoftFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
+<NOBR>Release 3</NOBR> of SoftFloat was a completely new implementation
+supplanting earlier releases.
+The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
+done in the employ of the University of California, Berkeley, within the
+Department of Electrical Engineering and Computer Sciences, first for the
+Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
+The work was officially overseen by Prof. Krste Asanovic, with funding provided
+by these sources:
+<BLOCKQUOTE>
+<TABLE>
+<COL>
+<COL WIDTH=10>
+<COL>
+<TR>
+<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
+(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
+NVIDIA, Oracle, and Samsung.
+</TD>
+</TR>
+<TR>
+<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
+ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
+Oracle, and Samsung.
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The following applies to the whole of SoftFloat <NOBR>Release 3e</NOBR> as well
+as to each source file individually.
+</P>
+
+<P>
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.
+All rights reserved.
+</P>
+
+<P>
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+<OL>
+
+<LI>
+<P>
+Redistributions of source code must retain the above copyright notice, this
+list of conditions, and the following disclaimer.
+</P>
+
+<LI>
+<P>
+Redistributions in binary form must reproduce the above copyright notice, this
+list of conditions, and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+</P>
+
+<LI>
+<P>
+Neither the name of the University nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific
+prior written permission.
+</P>
+
+</OL>
+</P>
+
+<P>
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS &ldquo;AS IS&rdquo;,
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.
+IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+</P>
+
+
+<H2>4. SoftFloat Package Directory Structure</H2>
+
+<P>
+Because SoftFloat is targeted to multiple platforms, its source code is
+slightly scattered between target-specific and target-independent directories
+and files.
+The supplied directory structure is as follows:
+<BLOCKQUOTE>
+<PRE>
+doc
+source
+    include
+    8086
+    8086-SSE
+    ARM-VFPv2
+    ARM-VFPv2-defaultNaN
+build
+    template-FAST_INT64
+    template-not-FAST_INT64
+    Linux-386-GCC
+    Linux-386-SSE2-GCC
+    Linux-x86_64-GCC
+    Linux-ARM-VFPv2-GCC
+    Win32-MinGW
+    Win32-SSE2-MinGW
+    Win64-MinGW-w64
+</PRE>
+</BLOCKQUOTE>
+The majority of the SoftFloat sources are provided in the <CODE>source</CODE>
+directory.
+The <CODE>include</CODE> subdirectory contains several header files
+(unsurprisingly), while the other subdirectories of <CODE>source</CODE> contain
+source files that specialize the floating-point behavior to match particular
+processor families:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>8086</CODE></DT>
+<DD>
+Intel&rsquo;s older, 8087-derived floating-point, extended to all supported
+floating-point types
+</DD>
+<DT><CODE>8086-SSE</CODE></DT>
+<DD>
+Intel&rsquo;s x86 processors with Streaming SIMD Extensions (SSE) and later
+compatible extensions, having 8087 behavior for <NOBR>80-bit</NOBR>
+double-extended-precision (<CODE>extFloat80_t</CODE>) and SSE behavior for
+other floating-point types
+</DD>
+<DT><CODE>ARM-VFPv2</CODE></DT>
+<DD>
+ARM&rsquo;s VFPv2 or later floating-point, with NaN payload propagation
+</DD>
+<DT><CODE>ARM-VFPv2-defaultNaN</CODE></DT>
+<DD>
+ARM&rsquo;s VFPv2 or later floating-point, with the &ldquo;default NaN&rdquo;
+option
+</DD>
+</DL>
+</BLOCKQUOTE>
+If other specializations are attempted, these would be expected to be other
+subdirectories of <CODE>source</CODE> alongside the ones listed above.
+Specialization is covered later, in <NOBR>section 5.2</NOBR>, <I>Specializing
+Floating-Point Behavior</I>.
+</P>
+
+<P>
+The <CODE>build</CODE> directory is intended to contain a subdirectory for each
+target platform for which a build of the SoftFloat library may be created.
+For each build target, the target&rsquo;s subdirectory is where all derived
+object files and the completed SoftFloat library (typically
+<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) are created.
+The two <CODE>template</CODE> subdirectories are not actual build targets but
+contain sample files for creating new target directories.
+(The meaning of <CODE>FAST_INT64</CODE> will be explained later.)
+</P>
+
+<P>
+Ignoring the <CODE>template</CODE> directories, the supplied target directories
+are intended to follow a naming system of
+<NOBR><CODE>&lt;<I>execution-environment</I>&gt;-&lt;<I>compiler</I>&gt;</CODE></NOBR>.
+For the example targets,
+<NOBR><CODE>&lt;<I>execution-environment</I>&gt;</CODE></NOBR> is
+<NOBR><CODE>Linux-386</CODE></NOBR>, <NOBR><CODE>Linux-386-SSE2</CODE></NOBR>,
+<NOBR><CODE>Linux-x86_64</CODE></NOBR>,
+<NOBR><CODE>Linux-ARM-VFPv2</CODE></NOBR>, <CODE>Win32</CODE>,
+<NOBR><CODE>Win32-SSE2</CODE></NOBR>, or <CODE>Win64</CODE>, and
+<NOBR><CODE>&lt;<I>compiler</I>&gt;</CODE></NOBR> is <CODE>GCC</CODE>,
+<CODE>MinGW</CODE>, or <NOBR><CODE>MinGW-w64</CODE></NOBR>.
+</P>
+
+<P>
+All of the supplied target directories are merely examples that may or may not
+be correct for compiling on any particular system.
+Despite requests, there are currently no plans to include and maintain in the
+SoftFloat package the build files needed for a great many users&rsquo;
+compilation environments, which can span a huge range of operating systems,
+compilers, and other tools.
+</P>
+
+<P>
+As supplied, each target directory contains two files:
+<BLOCKQUOTE>
+<PRE>
+Makefile
+platform.h
+</PRE>
+</BLOCKQUOTE>
+The provided <CODE>Makefile</CODE> is written for GNU <CODE>make</CODE>.
+A build of SoftFloat for the specific target is begun by executing the
+<CODE>make</CODE> command with the target directory as the current directory.
+A completely different build tool can be used if an appropriate
+<CODE>Makefile</CODE> equivalent is created.
+</P>
+
+<P>
+The <CODE>platform.h</CODE> header file exists to provide a location for
+additional C declarations specific to the build target.
+Every C source file of SoftFloat contains a <CODE>#include</CODE> for
+<CODE>platform.h</CODE>.
+In many cases, the contents of <CODE>platform.h</CODE> can be as simple as one
+or two lines of code.
+At the other extreme, to get maximal performance from SoftFloat, it may be
+desirable to include in header <CODE>platform.h</CODE> (directly or via
+<CODE>#include</CODE>) declarations for numerous target-specific optimizations.
+Such possibilities are discussed in the next section, <I>Issues for Porting
+SoftFloat to a New Target</I>.
+If the target&rsquo;s compiler or library has bugs or other shortcomings,
+workarounds for these issues may also be possible with target-specific
+declarations in <CODE>platform.h</CODE>, avoiding the need to modify the main
+SoftFloat sources.
+</P>
+
+
+<H2>5. Issues for Porting SoftFloat to a New Target</H2>
+
+<H3>5.1. Standard Headers <CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE></H3>
+
+<P>
+The SoftFloat sources make use of standard headers
+<CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE>, which have
+been part of the ISO C Standard Library since 1999.
+With any recent compiler, these standard headers are likely to be supported,
+even if the compiler does not claim complete conformance to the latest ISO C
+Standard.
+For older or nonstandard compilers, substitutes for
+<CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE> may need to be
+created.
+SoftFloat depends on these names from <CODE>&lt;stdbool.h&gt;</CODE>:
+<BLOCKQUOTE>
+<PRE>
+bool
+true
+false
+</PRE>
+</BLOCKQUOTE>
+and on these names from <CODE>&lt;stdint.h&gt;</CODE>:
+<BLOCKQUOTE>
+<PRE>
+uint16_t
+uint32_t
+uint64_t
+int32_t
+int64_t
+UINT64_C
+INT64_C
+uint_least8_t
+uint_fast8_t
+uint_fast16_t
+uint_fast32_t
+uint_fast64_t
+int_fast8_t
+int_fast16_t
+int_fast32_t
+int_fast64_t
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+
+<H3>5.2. Specializing Floating-Point Behavior</H3>
+
+<P>
+The IEEE Floating-Point Standard allows for some flexibility in a conforming
+implementation, particularly concerning NaNs.
+The SoftFloat <CODE>source</CODE> directory is supplied with some
+<I>specialization</I> subdirectories containing possible definitions for this
+implementation-specific behavior.
+For example, the <CODE>8086</CODE> and <NOBR><CODE>8086-SSE</CODE></NOBR>
+subdirectories have source files that specialize SoftFloat&rsquo;s behavior to
+match that of Intel&rsquo;s x86 line of processors.
+The files in a specialization subdirectory must determine:
+<UL>
+<LI>
+whether tininess for underflow is detected before or after rounding by default;
+<LI>
+how signaling NaNs are distinguished from quiet NaNs;
+<LI>
+what (if anything) special happens when exceptions are raised;
+<LI>
+the default generated quiet NaNs;
+<LI>
+how NaNs are propagated from function inputs to output; and
+<LI>
+the integer results returned when conversions to integer type raise the
+<I>invalid</I> exception.
+</UL>
+</P>
+
+<P>
+As provided, the build process for a target expects to involve exactly
+<EM>one</EM> specialization directory that defines <EM>all</EM> of these
+implementation-specific details for the target.
+A specialization directory such as <CODE>8086</CODE> is expected to contain a
+header file called <CODE>specialize.h</CODE>, together with whatever other
+source files are needed to complete the specialization.
+</P>
+
+<P>
+A new build target may use an existing specialization, such as the ones
+provided by the <CODE>8086</CODE> and <NOBR><CODE>8086-SSE</CODE></NOBR>
+subdirectories.
+If a build target needs a new specialization, different from any existing ones,
+it is recommended that a new specialization directory be created for this
+purpose.
+The <CODE>specialize.h</CODE> header file from any of the provided
+specialization subdirectories can be used as a model for what definitions are
+needed.
+</P>
+
+
+<H3>5.3. Macros for Build Options</H3>
+
+<P>
+The SoftFloat source files adapt the floating-point implementation according to
+several C preprocessor macros:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>LITTLEENDIAN</CODE>
+<DD>
+Must be defined for little-endian machines; must not be defined for big-endian
+machines.
+<DT><CODE>INLINE</CODE>
+<DD>
+Specifies the sequence of tokens used to indicate that a C function should be
+inlined.
+If macro <CODE>INLINE_LEVEL</CODE> is defined with a value of 1 or higher, this
+macro must be defined; otherwise, this macro is ignored and need not be
+defined.
+For compilers that conform to the C Standard&rsquo;s rules for inline
+functions, this macro can be defined as the single keyword <CODE>inline</CODE>.
+For other compilers that follow a convention pre-dating the standardization of
+<CODE>inline</CODE>, this macro may need to be defined to <CODE>extern</CODE>
+<CODE>inline</CODE>.
+<DT><CODE>THREAD_LOCAL</CODE>
+<DD>
+Can be defined to a sequence of tokens that, when appearing at the start of a
+variable declaration, indicates to the C compiler that the variable is
+<I>per-thread</I>, meaning that each execution thread gets its own separate
+instance of the variable.
+This macro is used in header <CODE>softfloat.h</CODE> in the declarations of
+variables <CODE>softfloat_roundingMode</CODE>,
+<CODE>softfloat_detectTininess</CODE>, <CODE>extF80_roundingPrecision</CODE>,
+and <CODE>softfloat_exceptionFlags</CODE>.
+If macro <CODE>THREAD_LOCAL</CODE> is left undefined, these variables will
+default to being ordinary global variables.
+Depending on the compiler, possible valid definitions of this macro include
+<CODE>_Thread_local</CODE> and <CODE>__thread</CODE>.
+</DL>
+<DL>
+<DT><CODE>SOFTFLOAT_ROUND_ODD</CODE>
+<DD>
+Can be defined to enable support for optional rounding mode
+<CODE>softfloat_round_odd</CODE>.
+</DL>
+<DL>
+<DT><CODE>INLINE_LEVEL</CODE>
+<DD>
+Can be defined to an integer to determine the degree of inlining requested of
+the compiler.
+Larger numbers request that more inlining be done.
+If this macro is not defined or is defined to a value less <NOBR>than 1</NOBR>
+(zero or negative), no inlining is requested.
+The maximum effective value is no higher <NOBR>than 5</NOBR>.
+Defining this macro to a value greater than 5 is the same as defining it
+<NOBR>to 5</NOBR>.
+<DT><CODE>SOFTFLOAT_FAST_INT64</CODE>
+<DD>
+Can be defined to indicate that the build target&rsquo;s implementation of
+<NOBR>64-bit</NOBR> arithmetic is efficient.
+For newer <NOBR>64-bit</NOBR> processors, this macro should usually be defined.
+For very small microprocessors whose buses and registers are <NOBR>8-bit</NOBR>
+or <NOBR>16-bit</NOBR> in size, this macro should usually not be defined.
+Whether this macro should be defined for a <NOBR>32-bit</NOBR> processor may
+depend on the target machine and the applications that will use SoftFloat.
+<DT><CODE>SOFTFLOAT_FAST_DIV32TO16</CODE>
+<DD>
+Can be defined to indicate that the target&rsquo;s division operator
+<NOBR>in C</NOBR> (written as <CODE>/</CODE>) is reasonably efficient for
+dividing a <NOBR>32-bit</NOBR> unsigned integer by a <NOBR>16-bit</NOBR>
+unsigned integer.
+Setting this macro may affect the performance of function <CODE>f16_div</CODE>.
+<DT><CODE>SOFTFLOAT_FAST_DIV64TO32</CODE>
+<DD>
+Can be defined to indicate that the target&rsquo;s division operator
+<NOBR>in C</NOBR> (written as <CODE>/</CODE>) is reasonably efficient for
+dividing a <NOBR>64-bit</NOBR> unsigned integer by a <NOBR>32-bit</NOBR>
+unsigned integer.
+Setting this macro may affect the performance of division, remainder, and
+square root operations other than <CODE>f16_div</CODE>.
+</DL>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Following the usual custom <NOBR>for C</NOBR>, for most of these macros (all
+except <CODE>INLINE</CODE>, <CODE>THREAD_LOCAL</CODE>, and
+<CODE>INLINE_LEVEL</CODE>), the content of any definition is irrelevant;
+what matters is a macro&rsquo;s effect on <CODE>#ifdef</CODE> directives.
+</P>
+
+<P>
+It is recommended that any definitions of macros <CODE>LITTLEENDIAN</CODE>,
+<CODE>INLINE</CODE>, and <CODE>THREAD_LOCAL</CODE> be made in a build
+target&rsquo;s <CODE>platform.h</CODE> header file, because these macros are
+expected to be determined inflexibly by the target machine and compiler.
+The other five macros select options and control optimization, and thus might
+be better located in the target&rsquo;s Makefile (or its equivalent).
+</P>
+
+
+<H3>5.4. Adapting a Template Target Directory</H3>
+
+<P>
+In the <CODE>build</CODE> directory, two <CODE>template</CODE> subdirectories
+provide models for new target directories.
+Two different templates exist because different functions are needed in the
+SoftFloat library depending on whether macro <CODE>SOFTFLOAT_FAST_INT64</CODE>
+is defined.
+If macro <CODE>SOFTFLOAT_FAST_INT64</CODE> will be defined,
+<NOBR><CODE>template-FAST_INT64</CODE></NOBR> is the template to use;
+otherwise, <NOBR><CODE>template-not-FAST_INT64</CODE></NOBR> is the appropriate
+template.
+A new target directory can be created by copying the correct template directory
+and editing the files inside.
+To avoid confusion, it would be wise to refrain from editing the files within a
+template directory directly.
+</P>
+
+
+<H3>5.5. Target-Specific Optimization of Primitive Functions</H3>
+
+<P>
+Header file <CODE>primitives.h</CODE> (in directory
+<CODE>source/include</CODE>) declares macros and functions for numerous
+underlying arithmetic operations upon which many of SoftFloat&rsquo;s
+floating-point functions are ultimately built.
+The SoftFloat sources include implementations of all of these functions/macros,
+written as standard C code, so a complete and correct SoftFloat library can be
+created using only the supplied code for all functions.
+However, for many targets, SoftFloat&rsquo;s performance can be improved by
+substituting target-specific implementations of some of the functions/macros
+declared in <CODE>primitives.h</CODE>.
+</P>
+
+<P>
+For example, <CODE>primitives.h</CODE> declares a function called
+<CODE>softfloat_countLeadingZeros32</CODE> that takes an unsigned
+<NOBR>32-bit</NOBR> integer as an argument and returns the number of the
+integer&rsquo;s most-significant bits that are zeros.
+While the SoftFloat sources include an implementation of this function written
+in <NOBR>standard C</NOBR>, many processors can perform this same function
+directly in only one or two machine instructions.
+An alternative, target-specific implementation that maps to those instructions
+is likely to be more efficient than the generic C code from the SoftFloat
+package.
+</P>
+
+<P>
+A build target can replace the supplied version of any function or macro of
+<CODE>primitives.h</CODE> by defining a macro with the same name in the
+target&rsquo;s <CODE>platform.h</CODE> header file.
+For this purpose, it may be helpful for <CODE>platform.h</CODE> to
+<CODE>#include</CODE> header file <CODE>primitiveTypes.h</CODE>, which defines
+types used for arguments and results of functions declared in
+<CODE>primitives.h</CODE>.
+When a desired replacement implementation is a function, not a macro, it is
+sufficient for <CODE>platform.h</CODE> to include the line
+<BLOCKQUOTE>
+<PRE>
+#define &lt;<I>function-name</I>&gt; &lt;<I>function-name</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+where <NOBR><CODE>&lt;<I>function-name</I>&gt;</CODE></NOBR> is the name of the
+function.
+This technically defines <NOBR><CODE>&lt;<I>function-name</I>&gt;</CODE></NOBR>
+as a macro, but one that resolves to the same name, which may then be a
+function.
+(A preprocessor that conforms to the C Standard is required to limit recursive
+macro expansion from being applied more than once.)
+</P>
+
+<P>
+The supplied header file <CODE>opts-GCC.h</CODE> (in directory
+<CODE>source/include</CODE>) provides an example of target-specific
+optimization for the GCC compiler.
+Each GCC target example in the <CODE>build</CODE> directory has
+<BLOCKQUOTE>
+<CODE>#include "opts-GCC.h"</CODE>
+</BLOCKQUOTE>
+in its <CODE>platform.h</CODE> header file.
+Before <CODE>opts-GCC.h</CODE> is included, the following macros must be
+defined (or not) to control which features are invoked:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>SOFTFLOAT_BUILTIN_CLZ</CODE></DT>
+<DD>
+If defined, SoftFloat&rsquo;s internal
+&lsquo;<CODE>countLeadingZeros</CODE>&rsquo; functions use intrinsics
+<CODE>__builtin_clz</CODE> and <CODE>__builtin_clzll</CODE>.
+</DD>
+<DT><CODE>SOFTFLOAT_INTRINSIC_INT128</CODE></DT>
+<DD>
+If defined, SoftFloat makes use of GCC&rsquo;s nonstandard <NOBR>128-bit</NOBR>
+integer type <CODE>__int128</CODE>.
+</DD>
+</DL>
+</BLOCKQUOTE>
+On some machines, these improvements are observed to increase the speeds of
+<CODE>f64_mul</CODE> and <CODE>f128_mul</CODE> by around 20 to 25%, although
+other functions receive less dramatic boosts, or none at all.
+Results can vary greatly across different platforms.
+</P>
+
+
+<H2>6. Testing SoftFloat</H2>
+
+<P>
+SoftFloat can be tested using the <CODE>testsoftfloat</CODE> program by the
+same author.
+This program is part of the Berkeley TestFloat package available at the Web
+page
+<A HREF="http://www.jhauser.us/arithmetic/TestFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/TestFloat.html</CODE></NOBR></A>.
+The TestFloat package also has a program called <CODE>timesoftfloat</CODE> that
+measures the speed of SoftFloat&rsquo;s floating-point functions.
+</P>
+
+
+<H2>7. Providing SoftFloat as a Common Library for Applications</H2>
+
+<P>
+Header file <CODE>softfloat.h</CODE> defines the SoftFloat interface as seen by
+clients.
+If the SoftFloat library will be made a common library for programs on a
+system, the supplied <CODE>softfloat.h</CODE> has a couple of deficiencies for
+this purpose:
+<UL>
+<LI>
+As supplied, <CODE>softfloat.h</CODE> depends on another header,
+<CODE>softfloat_types.h</CODE>, that is not intended for public use but which
+must also be visible to the programmer&rsquo;s compiler.
+<LI>
+More troubling, at the time <CODE>softfloat.h</CODE> is included in a C source
+file, macros <CODE>SOFTFLOAT_FAST_INT64</CODE> and <CODE>THREAD_LOCAL</CODE>
+must be defined, or not defined, consistent with how these macro were defined
+when the SoftFloat library was built.
+</UL>
+In the situation that new programs may regularly <CODE>#include</CODE> header
+file <CODE>softfloat.h</CODE>, it is recommended that a custom, self-contained
+version of this header file be created that eliminates these issues.
+</P>
+
+
+<H2>8. Contact Information</H2>
+
+<P>
+At the time of this writing, the most up-to-date information about SoftFloat
+and the latest release can be found at the Web page
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/SoftFloat-3e/doc/SoftFloat.html b/addins/SoftFloat-3e/doc/SoftFloat.html
new file mode 100644
index 000000000..bb41770ec
--- /dev/null
+++ b/addins/SoftFloat-3e/doc/SoftFloat.html
@@ -0,0 +1,1527 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley SoftFloat Library Interface</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley SoftFloat Release 3e: Library Interface</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Contents</H2>
+
+<BLOCKQUOTE>
+<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
+<COL WIDTH=25>
+<COL WIDTH=*>
+<TR><TD COLSPAN=2>1. Introduction</TD></TR>
+<TR><TD COLSPAN=2>2. Limitations</TD></TR>
+<TR><TD COLSPAN=2>3. Acknowledgments and License</TD></TR>
+<TR><TD COLSPAN=2>4. Types and Functions</TD></TR>
+<TR><TD></TD><TD>4.1. Boolean and Integer Types</TD></TR>
+<TR><TD></TD><TD>4.2. Floating-Point Types</TD></TR>
+<TR><TD></TD><TD>4.3. Supported Floating-Point Functions</TD></TR>
+<TR>
+  <TD></TD>
+  <TD>4.4. Non-canonical Representations in <CODE>extFloat80_t</CODE></TD>
+</TR>
+<TR><TD></TD><TD>4.5. Conventions for Passing Arguments and Results</TD></TR>
+<TR><TD COLSPAN=2>5. Reserved Names</TD></TR>
+<TR><TD COLSPAN=2>6. Mode Variables</TD></TR>
+<TR><TD></TD><TD>6.1. Rounding Mode</TD></TR>
+<TR><TD></TD><TD>6.2. Underflow Detection</TD></TR>
+<TR>
+  <TD></TD>
+  <TD>6.3. Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</TD>
+</TR>
+<TR><TD COLSPAN=2>7. Exceptions and Exception Flags</TD></TR>
+<TR><TD COLSPAN=2>8. Function Details</TD></TR>
+<TR><TD></TD><TD>8.1. Conversions from Integer to Floating-Point</TD></TR>
+<TR><TD></TD><TD>8.2. Conversions from Floating-Point to Integer</TD></TR>
+<TR><TD></TD><TD>8.3. Conversions Among Floating-Point Types</TD></TR>
+<TR><TD></TD><TD>8.4. Basic Arithmetic Functions</TD></TR>
+<TR><TD></TD><TD>8.5. Fused Multiply-Add Functions</TD></TR>
+<TR><TD></TD><TD>8.6. Remainder Functions</TD></TR>
+<TR><TD></TD><TD>8.7. Round-to-Integer Functions</TD></TR>
+<TR><TD></TD><TD>8.8. Comparison Functions</TD></TR>
+<TR><TD></TD><TD>8.9. Signaling NaN Test Functions</TD></TR>
+<TR><TD></TD><TD>8.10. Raise-Exception Function</TD></TR>
+<TR><TD COLSPAN=2>9. Changes from SoftFloat <NOBR>Release 2</NOBR></TD></TR>
+<TR><TD></TD><TD>9.1. Name Changes</TD></TR>
+<TR><TD></TD><TD>9.2. Changes to Function Arguments</TD></TR>
+<TR><TD></TD><TD>9.3. Added Capabilities</TD></TR>
+<TR><TD></TD><TD>9.4. Better Compatibility with the C Language</TD></TR>
+<TR><TD></TD><TD>9.5. New Organization as a Library</TD></TR>
+<TR><TD></TD><TD>9.6. Optimization Gains (and Losses)</TD></TR>
+<TR><TD COLSPAN=2>10. Future Directions</TD></TR>
+<TR><TD COLSPAN=2>11. Contact Information</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+
+
+<H2>1. Introduction</H2>
+
+<P>
+Berkeley SoftFloat is a software implementation of binary floating-point that
+conforms to the IEEE Standard for Floating-Point Arithmetic.
+The current release supports five binary formats:  <NOBR>16-bit</NOBR>
+half-precision, <NOBR>32-bit</NOBR> single-precision, <NOBR>64-bit</NOBR>
+double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
+<NOBR>128-bit</NOBR> quadruple-precision.
+The following functions are supported for each format:
+<UL>
+<LI>
+addition, subtraction, multiplication, division, and square root;
+<LI>
+fused multiply-add as defined by the IEEE Standard, except for
+<NOBR>80-bit</NOBR> double-extended-precision;
+<LI>
+remainder as defined by the IEEE Standard;
+<LI>
+round to integral value;
+<LI>
+comparisons;
+<LI>
+conversions to/from other supported formats; and
+<LI>
+conversions to/from <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> integers,
+signed and unsigned.
+</UL>
+All operations required by the original 1985 version of the IEEE Floating-Point
+Standard are implemented, except for conversions to and from decimal.
+</P>
+
+<P>
+This document gives information about the types defined and the routines
+implemented by SoftFloat.
+It does not attempt to define or explain the IEEE Floating-Point Standard.
+Information about the standard is available elsewhere.
+</P>
+
+<P>
+The current version of SoftFloat is <NOBR>Release 3e</NOBR>.
+This release modifies the behavior of the rarely used <I>odd</I> rounding mode
+(<I>round to odd</I>, also known as <I>jamming</I>), and also adds some new
+specialization and optimization examples for those compiling SoftFloat.
+</P>
+
+<P>
+The previous <NOBR>Release 3d</NOBR> fixed bugs that were found in the square
+root functions for the <NOBR>64-bit</NOBR>, <NOBR>80-bit</NOBR>, and
+<NOBR>128-bit</NOBR> floating-point formats.
+(Thanks to Alexei Sibidanov at the University of Victoria for reporting an
+incorrect result.)
+The bugs affected all prior <NOBR>Release-3</NOBR> versions of SoftFloat
+<NOBR>through 3c</NOBR>.
+The flaw in the <NOBR>64-bit</NOBR> floating-point square root function was of
+very minor impact, causing a <NOBR>1-ulp</NOBR> error (<NOBR>1 unit</NOBR> in
+the last place) a few times out of a billion.
+The bugs in the <NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> square root
+functions were more serious.
+Although incorrect results again occurred only a few times out of a billion,
+when they did occur a large portion of the less-significant bits could be
+wrong.
+</P>
+
+<P>
+Among earlier releases, 3b was notable for adding support for the
+<NOBR>16-bit</NOBR> half-precision format.
+For more about the evolution of SoftFloat releases, see
+<A HREF="SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></NOBR></A>.
+</P>
+
+<P>
+The functional interface of SoftFloat <NOBR>Release 3</NOBR> and later differs
+in many details from the releases that came before.
+For specifics of these differences, see <NOBR>section 9</NOBR> below,
+<I>Changes from SoftFloat <NOBR>Release 2</NOBR></I>.
+</P>
+
+
+<H2>2. Limitations</H2>
+
+<P>
+SoftFloat assumes the computer has an addressable byte size of 8 or
+<NOBR>16 bits</NOBR>.
+(Nearly all computers in use today have <NOBR>8-bit</NOBR> bytes.)
+</P>
+
+<P>
+SoftFloat is written in C and is designed to work with other C code.
+The C compiler used must conform at a minimum to the 1989 ANSI standard for the
+C language (same as the 1990 ISO standard) and must in addition support basic
+arithmetic on <NOBR>64-bit</NOBR> integers.
+Earlier releases of SoftFloat included implementations of <NOBR>32-bit</NOBR>
+single-precision and <NOBR>64-bit</NOBR> double-precision floating-point that
+did not require <NOBR>64-bit</NOBR> integers, but this option is not supported
+starting with <NOBR>Release 3</NOBR>.
+Since 1999, ISO standards for C have mandated compiler support for
+<NOBR>64-bit</NOBR> integers.
+A compiler conforming to the 1999 C Standard or later is recommended but not
+strictly required.
+</P>
+
+<P>
+Most operations not required by the original 1985 version of the IEEE
+Floating-Point Standard but added in the 2008 version are not yet supported in
+SoftFloat <NOBR>Release 3e</NOBR>.
+</P>
+
+
+<H2>3. Acknowledgments and License</H2>
+
+<P>
+The SoftFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
+<NOBR>Release 3</NOBR> of SoftFloat was a completely new implementation
+supplanting earlier releases.
+The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
+done in the employ of the University of California, Berkeley, within the
+Department of Electrical Engineering and Computer Sciences, first for the
+Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
+The work was officially overseen by Prof. Krste Asanovic, with funding provided
+by these sources:
+<BLOCKQUOTE>
+<TABLE>
+<COL>
+<COL WIDTH=10>
+<COL>
+<TR>
+<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
+(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
+NVIDIA, Oracle, and Samsung.
+</TD>
+</TR>
+<TR>
+<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
+ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
+Oracle, and Samsung.
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The following applies to the whole of SoftFloat <NOBR>Release 3e</NOBR> as well
+as to each source file individually.
+</P>
+
+<P>
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.
+All rights reserved.
+</P>
+
+<P>
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+<OL>
+
+<LI>
+<P>
+Redistributions of source code must retain the above copyright notice, this
+list of conditions, and the following disclaimer.
+</P>
+
+<LI>
+<P>
+Redistributions in binary form must reproduce the above copyright notice, this
+list of conditions, and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+</P>
+
+<LI>
+<P>
+Neither the name of the University nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific
+prior written permission.
+</P>
+
+</OL>
+</P>
+
+<P>
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS &ldquo;AS IS&rdquo;,
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.
+IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+</P>
+
+
+<H2>4. Types and Functions</H2>
+
+<P>
+The types and functions of SoftFloat are declared in header file
+<CODE>softfloat.h</CODE>.
+</P>
+
+<H3>4.1. Boolean and Integer Types</H3>
+
+<P>
+Header file <CODE>softfloat.h</CODE> depends on standard headers
+<CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE> to define type
+<CODE>bool</CODE> and several integer types.
+These standard headers have been part of the ISO C Standard Library since 1999.
+With any recent compiler, they are likely to be supported, even if the compiler
+does not claim complete conformance to the latest ISO C Standard.
+For older or nonstandard compilers, a port of SoftFloat may have substitutes
+for these headers.
+Header <CODE>softfloat.h</CODE> depends only on the name <CODE>bool</CODE> from
+<CODE>&lt;stdbool.h&gt;</CODE> and on these type names from
+<CODE>&lt;stdint.h&gt;</CODE>:
+<BLOCKQUOTE>
+<PRE>
+uint16_t
+uint32_t
+uint64_t
+int32_t
+int64_t
+uint_fast8_t
+uint_fast32_t
+uint_fast64_t
+int_fast32_t
+int_fast64_t
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+
+<H3>4.2. Floating-Point Types</H3>
+
+<P>
+The <CODE>softfloat.h</CODE> header defines five floating-point types:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+<TD><CODE>float16_t</CODE></TD>
+<TD><NOBR>16-bit</NOBR> half-precision binary format</TD>
+</TR>
+<TR>
+<TD><CODE>float32_t</CODE></TD>
+<TD><NOBR>32-bit</NOBR> single-precision binary format</TD>
+</TR>
+<TR>
+<TD><CODE>float64_t</CODE></TD>
+<TD><NOBR>64-bit</NOBR> double-precision binary format</TD>
+</TR>
+<TR>
+<TD><CODE>extFloat80_t&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><NOBR>80-bit</NOBR> double-extended-precision binary format (old Intel or
+Motorola format)</TD>
+</TR>
+<TR>
+<TD><CODE>float128_t</CODE></TD>
+<TD><NOBR>128-bit</NOBR> quadruple-precision binary format</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+The non-extended types are each exactly the size specified:
+<NOBR>16 bits</NOBR> for <CODE>float16_t</CODE>, <NOBR>32 bits</NOBR> for
+<CODE>float32_t</CODE>, <NOBR>64 bits</NOBR> for <CODE>float64_t</CODE>, and
+<NOBR>128 bits</NOBR> for <CODE>float128_t</CODE>.
+Aside from these size requirements, the definitions of all these types may
+differ for different ports of SoftFloat to specific systems.
+A given port of SoftFloat may or may not define some of the floating-point
+types as aliases for the C standard types <CODE>float</CODE>,
+<CODE>double</CODE>, and <CODE>long</CODE> <CODE>double</CODE>.
+</P>
+
+<P>
+Header file <CODE>softfloat.h</CODE> also defines a structure,
+<CODE>struct</CODE> <CODE>extFloat80M</CODE>, for the representation of
+<NOBR>80-bit</NOBR> double-extended-precision floating-point values in memory.
+This structure is the same size as type <CODE>extFloat80_t</CODE> and contains
+at least these two fields (not necessarily in this order):
+<BLOCKQUOTE>
+<PRE>
+uint16_t signExp;
+uint64_t signif;
+</PRE>
+</BLOCKQUOTE>
+Field <CODE>signExp</CODE> contains the sign and exponent of the floating-point
+value, with the sign in the most significant bit (<NOBR>bit 15</NOBR>) and the
+encoded exponent in the other <NOBR>15 bits</NOBR>.
+Field <CODE>signif</CODE> is the complete <NOBR>64-bit</NOBR> significand of
+the floating-point value.
+(In the usual encoding for <NOBR>80-bit</NOBR> extended floating-point, the
+leading <NOBR>1 bit</NOBR> of normalized numbers is not implicit but is stored
+in the most significant bit of the significand.)
+</P>
+
+<H3>4.3. Supported Floating-Point Functions</H3>
+
+<P>
+SoftFloat implements these arithmetic operations for its floating-point types:
+<UL>
+<LI>
+conversions between any two floating-point formats;
+<LI>
+for each floating-point format, conversions to and from signed and unsigned
+<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> integers;
+<LI>
+for each format, the usual addition, subtraction, multiplication, division, and
+square root operations;
+<LI>
+for each format except <CODE>extFloat80_t</CODE>, the fused multiply-add
+operation defined by the IEEE Standard;
+<LI>
+for each format, the floating-point remainder operation defined by the IEEE
+Standard;
+<LI>
+for each format, a &ldquo;round to integer&rdquo; operation that rounds to the
+nearest integer value in the same format; and
+<LI>
+comparisons between two values in the same floating-point format.
+</UL>
+</P>
+
+<P>
+The following operations required by the 2008 IEEE Floating-Point Standard are
+not supported in SoftFloat <NOBR>Release 3e</NOBR>:
+<UL>
+<LI>
+<B>nextUp</B>, <B>nextDown</B>, <B>minNum</B>, <B>maxNum</B>, <B>minNumMag</B>,
+<B>maxNumMag</B>, <B>scaleB</B>, and <B>logB</B>;
+<LI>
+conversions between floating-point formats and decimal or hexadecimal character
+sequences;
+<LI>
+all &ldquo;quiet-computation&rdquo; operations (<B>copy</B>, <B>negate</B>,
+<B>abs</B>, and <B>copySign</B>, which all involve only simple copying and/or
+manipulation of the floating-point sign bit); and
+<LI>
+all &ldquo;non-computational&rdquo; operations other than <B>isSignaling</B>
+(which is supported).
+</UL>
+</P>
+
+<H3>4.4. Non-canonical Representations in <CODE>extFloat80_t</CODE></H3>
+
+<P>
+Because the <NOBR>80-bit</NOBR> double-extended-precision format,
+<CODE>extFloat80_t</CODE>, stores an explicit leading significand bit, many
+finite floating-point numbers are encodable in this type in multiple equivalent
+forms.
+Of these multiple encodings, there is always a unique one with the least
+encoded exponent value, and this encoding is considered the <I>canonical</I>
+representation of the floating-point number.
+Any other equivalent representations (having a higher encoded exponent value)
+are <I>non-canonical</I>.
+For a value in the subnormal range (including zero), the canonical
+representation always has an encoded exponent of zero and a leading significand
+bit <NOBR>of 0</NOBR>.
+For finite values outside the subnormal range, the canonical representation
+always has an encoded exponent that is nonzero and a leading significand bit
+<NOBR>of 1</NOBR>.
+</P>
+
+<P>
+For an infinity or NaN, the leading significand bit is similarly expected to
+<NOBR>be 1</NOBR>.
+An infinity or NaN with a leading significand bit <NOBR>of 0</NOBR> is again
+considered non-canonical.
+Hence, altogether, to be canonical, a value of type <CODE>extFloat80_t</CODE>
+must have a leading significand bit <NOBR>of 1</NOBR>, unless the value is
+subnormal or zero, in which case the leading significand bit and the encoded
+exponent must both be zero.
+</P>
+
+<P>
+SoftFloat&rsquo;s functions are not guaranteed to operate as expected when
+inputs of type <CODE>extFloat80_t</CODE> are non-canonical.
+Assuming all of a function&rsquo;s <CODE>extFloat80_t</CODE> inputs (if any)
+are canonical, function outputs of type <CODE>extFloat80_t</CODE> will always
+be canonical.
+</P>
+
+<H3>4.5. Conventions for Passing Arguments and Results</H3>
+
+<P>
+Values that are at most <NOBR>64 bits</NOBR> in size (i.e., not the
+<NOBR>80-bit</NOBR> or <NOBR>128-bit</NOBR> floating-point formats) are in all
+cases passed as function arguments by value.
+Likewise, when an output of a function is no more than <NOBR>64 bits</NOBR>, it
+is always returned directly as the function result.
+Thus, for example, the SoftFloat function for adding two <NOBR>64-bit</NOBR>
+floating-point values has this simple signature:
+<BLOCKQUOTE>
+<CODE>float64_t f64_add( float64_t, float64_t );</CODE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The story is more complex when function inputs and outputs are
+<NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> floating-point.
+For these types, SoftFloat always provides a function that passes these larger
+values into or out of the function indirectly, via pointers.
+For example, for adding two <NOBR>128-bit</NOBR> floating-point values,
+SoftFloat supplies this function:
+<BLOCKQUOTE>
+<CODE>void f128M_add( const float128_t *, const float128_t *, float128_t * );</CODE>
+</BLOCKQUOTE>
+The first two arguments point to the values to be added, and the last argument
+points to the location where the sum will be stored.
+The <CODE>M</CODE> in the name <CODE>f128M_add</CODE> is mnemonic for the fact
+that the <NOBR>128-bit</NOBR> inputs and outputs are &ldquo;in memory&rdquo;,
+pointed to by pointer arguments.
+</P>
+
+<P>
+All ports of SoftFloat implement these <I>pass-by-pointer</I> functions for
+types <CODE>extFloat80_t</CODE> and <CODE>float128_t</CODE>.
+At the same time, SoftFloat ports may also implement alternate versions of
+these same functions that pass <CODE>extFloat80_t</CODE> and
+<CODE>float128_t</CODE> by value, like the smaller formats.
+Thus, besides the function with name <CODE>f128M_add</CODE> shown above, a
+SoftFloat port may also supply an equivalent function with this signature:
+<BLOCKQUOTE>
+<CODE>float128_t f128_add( float128_t, float128_t );</CODE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+As a general rule, on computers where the machine word size is
+<NOBR>32 bits</NOBR> or smaller, only the pass-by-pointer versions of functions
+(e.g., <CODE>f128M_add</CODE>) are provided for types <CODE>extFloat80_t</CODE>
+and <CODE>float128_t</CODE>, because passing such large types directly can have
+significant extra cost.
+On computers where the word size is <NOBR>64 bits</NOBR> or larger, both
+function versions (<CODE>f128M_add</CODE> and <CODE>f128_add</CODE>) are
+provided, because the cost of passing by value is then more reasonable.
+Applications that must be portable accross both classes of computers must use
+the pointer-based functions, as these are always implemented.
+However, if it is known that SoftFloat includes the by-value functions for all
+platforms of interest, programmers can use whichever version they prefer.
+</P>
+
+
+<H2>5. Reserved Names</H2>
+
+<P>
+In addition to the variables and functions documented here, SoftFloat defines
+some symbol names for its own private use.
+These private names always begin with the prefix
+&lsquo;<CODE>softfloat_</CODE>&rsquo;.
+When a program includes header <CODE>softfloat.h</CODE> or links with the
+SoftFloat library, all names with prefix &lsquo;<CODE>softfloat_</CODE>&rsquo;
+are reserved for possible use by SoftFloat.
+Applications that use SoftFloat should not define their own names with this
+prefix, and should reference only such names as are documented.
+</P>
+
+
+<H2>6. Mode Variables</H2>
+
+<P>
+The following global variables control rounding mode, underflow detection, and
+the <NOBR>80-bit</NOBR> extended format&rsquo;s rounding precision:
+<BLOCKQUOTE>
+<CODE>softfloat_roundingMode</CODE><BR>
+<CODE>softfloat_detectTininess</CODE><BR>
+<CODE>extF80_roundingPrecision</CODE>
+</BLOCKQUOTE>
+These mode variables are covered in the next several subsections.
+For some SoftFloat ports, these variables may be <I>per-thread</I> (declared
+<CODE>thread_local</CODE>), meaning that different execution threads have their
+own separate copies of the variables.
+</P>
+
+<H3>6.1. Rounding Mode</H3>
+
+<P>
+All five rounding modes defined by the 2008 IEEE Floating-Point Standard are
+implemented for all operations that require rounding.
+Some ports of SoftFloat may also implement the <I>round-to-odd</I> mode.
+</P>
+
+<P>
+The rounding mode is selected by the global variable
+<BLOCKQUOTE>
+<CODE>uint_fast8_t softfloat_roundingMode;</CODE>
+</BLOCKQUOTE>
+This variable may be set to one of the values
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+<TD><CODE>softfloat_round_near_even</CODE></TD>
+<TD>round to nearest, with ties to even</TD>
+</TR>
+<TR>
+<TD><CODE>softfloat_round_near_maxMag&nbsp;&nbsp;</CODE></TD>
+<TD>round to nearest, with ties to maximum magnitude (away from zero)</TD>
+</TR>
+<TR>
+<TD><CODE>softfloat_round_minMag</CODE></TD>
+<TD>round to minimum magnitude (toward zero)</TD>
+</TR>
+<TR>
+<TD><CODE>softfloat_round_min</CODE></TD>
+<TD>round to minimum (down)</TD>
+</TR>
+<TR>
+<TD><CODE>softfloat_round_max</CODE></TD>
+<TD>round to maximum (up)</TD>
+</TR>
+<TR>
+<TD><CODE>softfloat_round_odd</CODE></TD>
+<TD>round to odd (jamming), if supported by the SoftFloat port</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+Variable <CODE>softfloat_roundingMode</CODE> is initialized to
+<CODE>softfloat_round_near_even</CODE>.
+</P>
+
+<P>
+When <CODE>softfloat_round_odd</CODE> is the rounding mode for a function that
+rounds to an integer value (either conversion to an integer format or a
+&lsquo;<CODE>roundToInt</CODE>&rsquo; function), if the input is not already an
+integer, the rounded result is the closest <EM>odd</EM> integer.
+For other operations, this rounding mode acts as though the floating-point
+result is first rounded to minimum magnitude, the same as
+<CODE>softfloat_round_minMag</CODE>, and then, if the result is inexact, the
+least-significant bit of the result is set <NOBR>to 1</NOBR>.
+Rounding to odd is also known as <EM>jamming</EM>.
+</P>
+
+<H3>6.2. Underflow Detection</H3>
+
+<P>
+In the terminology of the IEEE Standard, SoftFloat can detect tininess for
+underflow either before or after rounding.
+The choice is made by the global variable
+<BLOCKQUOTE>
+<CODE>uint_fast8_t softfloat_detectTininess;</CODE>
+</BLOCKQUOTE>
+which can be set to either
+<BLOCKQUOTE>
+<CODE>softfloat_tininess_beforeRounding</CODE><BR>
+<CODE>softfloat_tininess_afterRounding</CODE>
+</BLOCKQUOTE>
+Detecting tininess after rounding is usually better because it results in fewer
+spurious underflow signals.
+The other option is provided for compatibility with some systems.
+Like most systems (and as required by the newer 2008 IEEE Standard), SoftFloat
+always detects loss of accuracy for underflow as an inexact result.
+</P>
+
+<H3>6.3. Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</H3>
+
+<P>
+For <CODE>extFloat80_t</CODE> only, the rounding precision of the basic
+arithmetic operations is controlled by the global variable
+<BLOCKQUOTE>
+<CODE>uint_fast8_t extF80_roundingPrecision;</CODE>
+</BLOCKQUOTE>
+The operations affected are:
+<BLOCKQUOTE>
+<CODE>extF80_add</CODE><BR>
+<CODE>extF80_sub</CODE><BR>
+<CODE>extF80_mul</CODE><BR>
+<CODE>extF80_div</CODE><BR>
+<CODE>extF80_sqrt</CODE>
+</BLOCKQUOTE>
+When <CODE>extF80_roundingPrecision</CODE> is set to its default value of 80,
+these operations are rounded to the full precision of the <NOBR>80-bit</NOBR>
+double-extended-precision format, like occurs for other formats.
+Setting <CODE>extF80_roundingPrecision</CODE> to 32 or to 64 causes the
+operations listed to be rounded to <NOBR>32-bit</NOBR> precision (equivalent to
+<CODE>float32_t</CODE>) or to <NOBR>64-bit</NOBR> precision (equivalent to
+<CODE>float64_t</CODE>), respectively.
+When rounding to reduced precision, additional bits in the result significand
+beyond the rounding point are set to zero.
+The consequences of setting <CODE>extF80_roundingPrecision</CODE> to a value
+other than 32, 64, or 80 is not specified.
+Operations other than the ones listed above are not affected by
+<CODE>extF80_roundingPrecision</CODE>.
+</P>
+
+
+<H2>7. Exceptions and Exception Flags</H2>
+
+<P>
+All five exception flags required by the IEEE Floating-Point Standard are
+implemented.
+Each flag is stored as a separate bit in the global variable
+<BLOCKQUOTE>
+<CODE>uint_fast8_t softfloat_exceptionFlags;</CODE>
+</BLOCKQUOTE>
+The positions of the exception flag bits within this variable are determined by
+the bit masks
+<BLOCKQUOTE>
+<CODE>softfloat_flag_inexact</CODE><BR>
+<CODE>softfloat_flag_underflow</CODE><BR>
+<CODE>softfloat_flag_overflow</CODE><BR>
+<CODE>softfloat_flag_infinite</CODE><BR>
+<CODE>softfloat_flag_invalid</CODE>
+</BLOCKQUOTE>
+Variable <CODE>softfloat_exceptionFlags</CODE> is initialized to all zeros,
+meaning no exceptions.
+</P>
+
+<P>
+For some SoftFloat ports, <CODE>softfloat_exceptionFlags</CODE> may be
+<I>per-thread</I> (declared <CODE>thread_local</CODE>), meaning that different
+execution threads have their own separate instances of it.
+</P>
+
+<P>
+An individual exception flag can be cleared with the statement
+<BLOCKQUOTE>
+<CODE>softfloat_exceptionFlags &= ~softfloat_flag_&lt;<I>exception</I>&gt;;</CODE>
+</BLOCKQUOTE>
+where <CODE>&lt;<I>exception</I>&gt;</CODE> is the appropriate name.
+To raise a floating-point exception, function <CODE>softfloat_raiseFlags</CODE>
+should normally be used.
+</P>
+
+<P>
+When SoftFloat detects an exception other than <I>inexact</I>, it calls
+<CODE>softfloat_raiseFlags</CODE>.
+The default version of this function simply raises the corresponding exception
+flags.
+Particular ports of SoftFloat may support alternate behavior, such as exception
+traps, by modifying the default <CODE>softfloat_raiseFlags</CODE>.
+A program may also supply its own <CODE>softfloat_raiseFlags</CODE> function to
+override the one from the SoftFloat library.
+</P>
+
+<P>
+Because inexact results occur frequently under most circumstances (and thus are
+hardly exceptional), SoftFloat does not ordinarily call
+<CODE>softfloat_raiseFlags</CODE> for <I>inexact</I> exceptions.
+It does always raise the <I>inexact</I> exception flag as required.
+</P>
+
+
+<H2>8. Function Details</H2>
+
+<P>
+In this section, <CODE>&lt;<I>float</I>&gt;</CODE> appears in function names as
+a substitute for one of these abbreviations:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+<TD><CODE>f16</CODE></TD>
+<TD>indicates <CODE>float16_t</CODE>, passed by value</TD>
+</TR>
+<TR>
+<TD><CODE>f32</CODE></TD>
+<TD>indicates <CODE>float32_t</CODE>, passed by value</TD>
+</TR>
+<TR>
+<TD><CODE>f64</CODE></TD>
+<TD>indicates <CODE>float64_t</CODE>, passed by value</TD>
+</TR>
+<TR>
+<TD><CODE>extF80M&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>indicates <CODE>extFloat80_t</CODE>, passed indirectly via pointers</TD>
+</TR>
+<TR>
+<TD><CODE>extF80</CODE></TD>
+<TD>indicates <CODE>extFloat80_t</CODE>, passed by value</TD>
+</TR>
+<TR>
+<TD><CODE>f128M</CODE></TD>
+<TD>indicates <CODE>float128_t</CODE>, passed indirectly via pointers</TD>
+</TR>
+<TR>
+<TD><CODE>f128</CODE></TD>
+<TD>indicates <CODE>float128_t</CODE>, passed by value</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+The circumstances under which values of floating-point types
+<CODE>extFloat80_t</CODE> and <CODE>float128_t</CODE> may be passed either by
+value or indirectly via pointers was discussed earlier in
+<NOBR>section 4.5</NOBR>, <I>Conventions for Passing Arguments and Results</I>.
+</P>
+
+<H3>8.1. Conversions from Integer to Floating-Point</H3>
+
+<P>
+All conversions from a <NOBR>32-bit</NOBR> or <NOBR>64-bit</NOBR> integer,
+signed or unsigned, to a floating-point format are supported.
+Functions performing these conversions have these names:
+<BLOCKQUOTE>
+<CODE>ui32_to_&lt;<I>float</I>&gt;</CODE><BR>
+<CODE>ui64_to_&lt;<I>float</I>&gt;</CODE><BR>
+<CODE>i32_to_&lt;<I>float</I>&gt;</CODE><BR>
+<CODE>i64_to_&lt;<I>float</I>&gt;</CODE>
+</BLOCKQUOTE>
+Conversions from <NOBR>32-bit</NOBR> integers to <NOBR>64-bit</NOBR>
+double-precision and larger formats are always exact, and likewise conversions
+from <NOBR>64-bit</NOBR> integers to <NOBR>80-bit</NOBR>
+double-extended-precision and <NOBR>128-bit</NOBR> quadruple-precision are also
+always exact.
+</P>
+
+<P>
+Each conversion function takes one input of the appropriate type and generates
+one output.
+The following illustrates the signatures of these functions in cases when the
+floating-point result is passed either by value or via pointers:
+<BLOCKQUOTE>
+<PRE>
+float64_t i32_to_f64( int32_t <I>a</I> );
+</PRE>
+<PRE>
+void i32_to_f128M( int32_t <I>a</I>, float128_t *<I>destPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<H3>8.2. Conversions from Floating-Point to Integer</H3>
+
+<P>
+Conversions from a floating-point format to a <NOBR>32-bit</NOBR> or
+<NOBR>64-bit</NOBR> integer, signed or unsigned, are supported with these
+functions:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_to_ui32</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_ui64</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_i32</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_i64</CODE>
+</BLOCKQUOTE>
+The functions have signatures as follows, depending on whether the
+floating-point input is passed by value or via pointers:
+<BLOCKQUOTE>
+<PRE>
+int_fast32_t f64_to_i32( float64_t <I>a</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
+</PRE>
+<PRE>
+int_fast32_t
+ f128M_to_i32( const float128_t *<I>aPtr</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The <CODE><I>roundingMode</I></CODE> argument specifies the rounding mode for
+the conversion.
+The variable that usually indicates rounding mode,
+<CODE>softfloat_roundingMode</CODE>, is ignored.
+Argument <CODE><I>exact</I></CODE> determines whether the <I>inexact</I>
+exception flag is raised if the conversion is not exact.
+If <CODE><I>exact</I></CODE> is <CODE>true</CODE>, the <I>inexact</I> flag may
+be raised;
+otherwise, it will not be, even if the conversion is inexact.
+</P>
+
+<P>
+A conversion from floating-point to integer format raises the <I>invalid</I>
+exception if the source value cannot be rounded to a representable integer of
+the desired size (32 or 64 bits).
+In such circumstances, the integer result returned is determined by the
+particular port of SoftFloat, although typically this value will be either the
+maximum or minimum value of the integer format.
+The functions that convert to integer types never raise the floating-point
+<I>overflow</I> exception.
+</P>
+
+<P>
+Because languages such <NOBR>as C</NOBR> require that conversions to integers
+be rounded toward zero, the following functions are provided for improved speed
+and convenience:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_to_ui32_r_minMag</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_ui64_r_minMag</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_i32_r_minMag</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_to_i64_r_minMag</CODE>
+</BLOCKQUOTE>
+These functions round only toward zero (to minimum magnitude).
+The signatures for these functions are the same as above without the redundant
+<CODE><I>roundingMode</I></CODE> argument:
+<BLOCKQUOTE>
+<PRE>
+int_fast32_t f64_to_i32_r_minMag( float64_t <I>a</I>, bool <I>exact</I> );
+</PRE>
+<PRE>
+int_fast32_t f128M_to_i32_r_minMag( const float128_t *<I>aPtr</I>, bool <I>exact</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<H3>8.3. Conversions Among Floating-Point Types</H3>
+
+<P>
+Conversions between floating-point formats are done by functions with these
+names:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_to_&lt;<I>float</I>&gt;</CODE>
+</BLOCKQUOTE>
+All combinations of source and result type are supported where the source and
+result are different formats.
+There are four different styles of signature for these functions, depending on
+whether the input and the output floating-point values are passed by value or
+via pointers:
+<BLOCKQUOTE>
+<PRE>
+float32_t f64_to_f32( float64_t <I>a</I> );
+</PRE>
+<PRE>
+float32_t f128M_to_f32( const float128_t *<I>aPtr</I> );
+</PRE>
+<PRE>
+void f32_to_f128M( float32_t <I>a</I>, float128_t *<I>destPtr</I> );
+</PRE>
+<PRE>
+void extF80M_to_f128M( const extFloat80_t *<I>aPtr</I>, float128_t *<I>destPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Conversions from a smaller to a larger floating-point format are always exact
+and so require no rounding.
+</P>
+
+<H3>8.4. Basic Arithmetic Functions</H3>
+
+<P>
+The following basic arithmetic functions are provided:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_add</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_sub</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_mul</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_div</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_sqrt</CODE>
+</BLOCKQUOTE>
+Each floating-point operation takes two operands, except for <CODE>sqrt</CODE>
+(square root) which takes only one.
+The operands and result are all of the same floating-point format.
+Signatures for these functions take the following forms:
+<BLOCKQUOTE>
+<PRE>
+float64_t f64_add( float64_t <I>a</I>, float64_t <I>b</I> );
+</PRE>
+<PRE>
+void
+ f128M_add(
+     const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I>, float128_t *<I>destPtr</I> );
+</PRE>
+<PRE>
+float64_t f64_sqrt( float64_t <I>a</I> );
+</PRE>
+<PRE>
+void f128M_sqrt( const float128_t *<I>aPtr</I>, float128_t *<I>destPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+When floating-point values are passed indirectly through pointers, arguments
+<CODE><I>aPtr</I></CODE> and <CODE><I>bPtr</I></CODE> point to the input
+operands, and the last argument, <CODE><I>destPtr</I></CODE>, points to the
+location where the result is stored.
+</P>
+
+<P>
+Rounding of the <NOBR>80-bit</NOBR> double-extended-precision
+(<CODE>extFloat80_t</CODE>) functions is affected by variable
+<CODE>extF80_roundingPrecision</CODE>, as explained earlier in
+<NOBR>section 6.3</NOBR>,
+<I>Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</I>.
+</P>
+
+<H3>8.5. Fused Multiply-Add Functions</H3>
+
+<P>
+The 2008 version of the IEEE Floating-Point Standard defines a <I>fused
+multiply-add</I> operation that does a combined multiplication and addition
+with only a single rounding.
+SoftFloat implements fused multiply-add with functions
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_mulAdd</CODE>
+</BLOCKQUOTE>
+Unlike other operations, fused multiple-add is not supported for the
+<NOBR>80-bit</NOBR> double-extended-precision format,
+<CODE>extFloat80_t</CODE>.
+</P>
+
+<P>
+Depending on whether floating-point values are passed by value or via pointers,
+the fused multiply-add functions have signatures of these forms:
+<BLOCKQUOTE>
+<PRE>
+float64_t f64_mulAdd( float64_t <I>a</I>, float64_t <I>b</I>, float64_t <I>c</I> );
+</PRE>
+<PRE>
+void
+ f128M_mulAdd(
+     const float128_t *<I>aPtr</I>,
+     const float128_t *<I>bPtr</I>,
+     const float128_t *<I>cPtr</I>,
+     float128_t *<I>destPtr</I>
+ );
+</PRE>
+</BLOCKQUOTE>
+The functions compute
+<NOBR>(<CODE><I>a</I></CODE> &times; <CODE><I>b</I></CODE>)
+ + <CODE><I>c</I></CODE></NOBR>
+with a single rounding.
+When floating-point values are passed indirectly through pointers, arguments
+<CODE><I>aPtr</I></CODE>, <CODE><I>bPtr</I></CODE>, and
+<CODE><I>cPtr</I></CODE> point to operands <CODE><I>a</I></CODE>,
+<CODE><I>b</I></CODE>, and <CODE><I>c</I></CODE> respectively, and
+<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
+</P>
+
+<P>
+If one of the multiplication operands <CODE><I>a</I></CODE> and
+<CODE><I>b</I></CODE> is infinite and the other is zero, these functions raise
+the invalid exception even if operand <CODE><I>c</I></CODE> is a quiet NaN.
+</P>
+
+<H3>8.6. Remainder Functions</H3>
+
+<P>
+For each format, SoftFloat implements the remainder operation defined by the
+IEEE Floating-Point Standard.
+The remainder functions have names
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_rem</CODE>
+</BLOCKQUOTE>
+Each remainder operation takes two floating-point operands of the same format
+and returns a result in the same format.
+Depending on whether floating-point values are passed by value or via pointers,
+the remainder functions have signatures of these forms:
+<BLOCKQUOTE>
+<PRE>
+float64_t f64_rem( float64_t <I>a</I>, float64_t <I>b</I> );
+</PRE>
+<PRE>
+void
+ f128M_rem(
+     const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I>, float128_t *<I>destPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+When floating-point values are passed indirectly through pointers, arguments
+<CODE><I>aPtr</I></CODE> and <CODE><I>bPtr</I></CODE> point to operands
+<CODE><I>a</I></CODE> and <CODE><I>b</I></CODE> respectively, and
+<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
+</P>
+
+<P>
+The IEEE Standard remainder operation computes the value
+<NOBR><CODE><I>a</I></CODE>
+ &minus; <I>n</I> &times; <CODE><I>b</I></CODE></NOBR>,
+where <I>n</I> is the integer closest to
+<NOBR><CODE><I>a</I></CODE> &divide; <CODE><I>b</I></CODE></NOBR>.
+If <NOBR><CODE><I>a</I></CODE> &divide; <CODE><I>b</I></CODE></NOBR> is exactly
+halfway between two integers, <I>n</I> is the <EM>even</EM> integer closest to
+<NOBR><CODE><I>a</I></CODE> &divide; <CODE><I>b</I></CODE></NOBR>.
+The IEEE Standard&rsquo;s remainder operation is always exact and so requires
+no rounding.
+</P>
+
+<P>
+Depending on the relative magnitudes of the operands, the remainder
+functions can take considerably longer to execute than the other SoftFloat
+functions.
+This is an inherent characteristic of the remainder operation itself and is not
+a flaw in the SoftFloat implementation.
+</P>
+
+<H3>8.7. Round-to-Integer Functions</H3>
+
+<P>
+For each format, SoftFloat implements the round-to-integer operation specified
+by the IEEE Floating-Point Standard.
+These functions are named
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_roundToInt</CODE>
+</BLOCKQUOTE>
+Each round-to-integer operation takes a single floating-point operand.
+This operand is rounded to an integer according to a specified rounding mode,
+and the resulting integer value is returned in the same floating-point format.
+(Note that the result is not an integer type.)
+</P>
+
+<P>
+The signatures of the round-to-integer functions are similar to those for
+conversions to an integer type:
+<BLOCKQUOTE>
+<PRE>
+float64_t f64_roundToInt( float64_t <I>a</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
+</PRE>
+<PRE>
+void
+ f128M_roundToInt(
+     const float128_t *<I>aPtr</I>,
+     uint_fast8_t <I>roundingMode</I>,
+     bool <I>exact</I>,
+     float128_t *<I>destPtr</I>
+ );
+</PRE>
+</BLOCKQUOTE>
+When floating-point values are passed indirectly through pointers,
+<CODE><I>aPtr</I></CODE> points to the input operand and
+<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
+</P>
+
+<P>
+The <CODE><I>roundingMode</I></CODE> argument specifies the rounding mode to
+apply.
+The variable that usually indicates rounding mode,
+<CODE>softfloat_roundingMode</CODE>, is ignored.
+Argument <CODE><I>exact</I></CODE> determines whether the <I>inexact</I>
+exception flag is raised if the conversion is not exact.
+If <CODE><I>exact</I></CODE> is <CODE>true</CODE>, the <I>inexact</I> flag may
+be raised;
+otherwise, it will not be, even if the conversion is inexact.
+</P>
+
+<H3>8.8. Comparison Functions</H3>
+
+<P>
+For each format, the following floating-point comparison functions are
+provided:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_eq</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_le</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_lt</CODE>
+</BLOCKQUOTE>
+Each comparison takes two operands of the same type and returns a Boolean.
+The abbreviation <CODE>eq</CODE> stands for &ldquo;equal&rdquo; (=);
+<CODE>le</CODE> stands for &ldquo;less than or equal&rdquo; (&le;);
+and <CODE>lt</CODE> stands for &ldquo;less than&rdquo; (&lt;).
+Depending on whether the floating-point operands are passed by value or via
+pointers, the comparison functions have signatures of these forms:
+<BLOCKQUOTE>
+<PRE>
+bool f64_eq( float64_t <I>a</I>, float64_t <I>b</I> );
+</PRE>
+<PRE>
+bool f128M_eq( const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The usual greater-than (&gt;), greater-than-or-equal (&ge;), and not-equal
+(&ne;) comparisons are easily obtained from the functions provided.
+The not-equal function is just the logical complement of the equal function.
+The greater-than-or-equal function is identical to the less-than-or-equal
+function with the arguments in reverse order, and likewise the greater-than
+function is identical to the less-than function with the arguments reversed.
+</P>
+
+<P>
+The IEEE Floating-Point Standard specifies that the less-than-or-equal and
+less-than comparisons by default raise the <I>invalid</I> exception if either
+operand is any kind of NaN.
+Equality comparisons, on the other hand, are defined by default to raise the
+<I>invalid</I> exception only for signaling NaNs, not quiet NaNs.
+For completeness, SoftFloat provides these complementary functions:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_eq_signaling</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_le_quiet</CODE><BR>
+<CODE>&lt;<I>float</I>&gt;_lt_quiet</CODE>
+</BLOCKQUOTE>
+The <CODE>signaling</CODE> equality comparisons are identical to the default
+equality comparisons except that the <I>invalid</I> exception is raised for any
+NaN input, not just for signaling NaNs.
+Similarly, the <CODE>quiet</CODE> comparison functions are identical to their
+default counterparts except that the <I>invalid</I> exception is not raised for
+quiet NaNs.
+</P>
+
+<H3>8.9. Signaling NaN Test Functions</H3>
+
+<P>
+Functions for testing whether a floating-point value is a signaling NaN are
+provided with these names:
+<BLOCKQUOTE>
+<CODE>&lt;<I>float</I>&gt;_isSignalingNaN</CODE>
+</BLOCKQUOTE>
+The functions take one floating-point operand and return a Boolean indicating
+whether the operand is a signaling NaN.
+Accordingly, the functions have the forms
+<BLOCKQUOTE>
+<PRE>
+bool f64_isSignalingNaN( float64_t <I>a</I> );
+</PRE>
+<PRE>
+bool f128M_isSignalingNaN( const float128_t *<I>aPtr</I> );
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<H3>8.10. Raise-Exception Function</H3>
+
+<P>
+SoftFloat provides a single function for raising floating-point exceptions:
+<BLOCKQUOTE>
+<PRE>
+void softfloat_raiseFlags( uint_fast8_t <I>exceptions</I> );
+</PRE>
+</BLOCKQUOTE>
+The <CODE><I>exceptions</I></CODE> argument is a mask indicating the set of
+exceptions to raise.
+(See earlier section 7, <I>Exceptions and Exception Flags</I>.)
+In addition to setting the specified exception flags in variable
+<CODE>softfloat_exceptionFlags</CODE>, the <CODE>softfloat_raiseFlags</CODE>
+function may cause a trap or abort appropriate for the current system.
+</P>
+
+
+<H2>9. Changes from SoftFloat <NOBR>Release 2</NOBR></H2>
+
+<P>
+Apart from a change in the legal use license, <NOBR>Release 3</NOBR> of
+SoftFloat introduced numerous technical differences compared to earlier
+releases.
+</P>
+
+<H3>9.1. Name Changes</H3>
+
+<P>
+The most obvious and pervasive difference compared to <NOBR>Release 2</NOBR>
+is that the names of most functions and variables have changed, even when the
+behavior has not.
+First, the floating-point types, the mode variables, the exception flags
+variable, the function to raise exceptions, and various associated constants
+have been renamed as follows:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD>old name, Release 2:</TD>
+<TD>new name, Release 3:</TD>
+</TR>
+<TR>
+<TD><CODE>float32</CODE></TD>
+<TD><CODE>float32_t</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float64</CODE></TD>
+<TD><CODE>float64_t</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>floatx80</CODE></TD>
+<TD><CODE>extFloat80_t</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float128</CODE></TD>
+<TD><CODE>float128_t</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_rounding_mode</CODE></TD>
+<TD><CODE>softfloat_roundingMode</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_round_nearest_even</CODE></TD>
+<TD><CODE>softfloat_round_near_even</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_round_to_zero</CODE></TD>
+<TD><CODE>softfloat_round_minMag</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_round_down</CODE></TD>
+<TD><CODE>softfloat_round_min</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_round_up</CODE></TD>
+<TD><CODE>softfloat_round_max</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_detect_tininess</CODE></TD>
+<TD><CODE>softfloat_detectTininess</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_tininess_before_rounding&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>softfloat_tininess_beforeRounding</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_tininess_after_rounding</CODE></TD>
+<TD><CODE>softfloat_tininess_afterRounding</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>floatx80_rounding_precision</CODE></TD>
+<TD><CODE>extF80_roundingPrecision</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_exception_flags</CODE></TD>
+<TD><CODE>softfloat_exceptionFlags</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_flag_inexact</CODE></TD>
+<TD><CODE>softfloat_flag_inexact</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_flag_underflow</CODE></TD>
+<TD><CODE>softfloat_flag_underflow</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_flag_overflow</CODE></TD>
+<TD><CODE>softfloat_flag_overflow</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_flag_divbyzero</CODE></TD>
+<TD><CODE>softfloat_flag_infinite</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_flag_invalid</CODE></TD>
+<TD><CODE>softfloat_flag_invalid</CODE></TD>
+</TR>
+<TR>
+<TD><CODE>float_raise</CODE></TD>
+<TD><CODE>softfloat_raiseFlags</CODE></TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Furthermore, <NOBR>Release 3</NOBR> adopted the following new abbreviations for
+function names:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD>used in names in Release 2:<CODE>&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>used in names in Release 3:</TD>
+</TR>
+<TR> <TD><CODE>int32</CODE></TD>    <TD><CODE>i32</CODE></TD>    </TR>
+<TR> <TD><CODE>int64</CODE></TD>    <TD><CODE>i64</CODE></TD>    </TR>
+<TR> <TD><CODE>float32</CODE></TD>  <TD><CODE>f32</CODE></TD>    </TR>
+<TR> <TD><CODE>float64</CODE></TD>  <TD><CODE>f64</CODE></TD>    </TR>
+<TR> <TD><CODE>floatx80</CODE></TD> <TD><CODE>extF80</CODE></TD> </TR>
+<TR> <TD><CODE>float128</CODE></TD> <TD><CODE>f128</CODE></TD>   </TR>
+</TABLE>
+</BLOCKQUOTE>
+Thus, for example, the function to add two <NOBR>32-bit</NOBR> floating-point
+numbers, previously called <CODE>float32_add</CODE> in <NOBR>Release 2</NOBR>,
+is now <CODE>f32_add</CODE>.
+Lastly, there have been a few other changes to function names:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD>used in names in Release 2:<CODE>&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>used in names in Release 3:<CODE>&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>relevant functions:</TD>
+</TR>
+<TR>
+<TD><CODE>_round_to_zero</CODE></TD>
+<TD><CODE>_r_minMag</CODE></TD>
+<TD>conversions from floating-point to integer (<NOBR>section 8.2</NOBR>)</TD>
+</TR>
+<TR>
+<TD><CODE>round_to_int</CODE></TD>
+<TD><CODE>roundToInt</CODE></TD>
+<TD>round-to-integer functions (<NOBR>section 8.7</NOBR>)</TD>
+</TR>
+<TR>
+<TD><CODE>is_signaling_nan&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>isSignalingNaN</CODE></TD>
+<TD>signaling NaN test functions (<NOBR>section 8.9</NOBR>)</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<H3>9.2. Changes to Function Arguments</H3>
+
+<P>
+Besides simple name changes, some operations were given a different interface
+in <NOBR>Release 3</NOBR> than they had in <NOBR>Release 2</NOBR>:
+<UL>
+
+<LI>
+<P>
+Since <NOBR>Release 3</NOBR>, integer arguments and results of functions have
+standard types from header <CODE>&lt;stdint.h&gt;</CODE>, such as
+<CODE>uint32_t</CODE>, whereas previously their types could be defined
+differently for each port of SoftFloat, usually using traditional C types such
+as <CODE>unsigned</CODE> <CODE>int</CODE>.
+Likewise, functions in <NOBR>Release 3</NOBR> and later pass Booleans as
+standard type <CODE>bool</CODE> from <CODE>&lt;stdbool.h&gt;</CODE>, whereas
+previously these were again passed as a port-specific type (usually
+<CODE>int</CODE>).
+</P>
+
+<LI>
+<P>
+As explained earlier in <NOBR>section 4.5</NOBR>, <I>Conventions for Passing
+Arguments and Results</I>, SoftFloat functions in <NOBR>Release 3</NOBR> and
+later may pass <NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> floating-point
+values through pointers, meaning that functions take pointer arguments and then
+read or write floating-point values at the locations indicated by the pointers.
+In <NOBR>Release 2</NOBR>, floating-point arguments and results were always
+passed by value, regardless of their size.
+</P>
+
+<LI>
+<P>
+Functions that round to an integer have additional
+<CODE><I>roundingMode</I></CODE> and <CODE><I>exact</I></CODE> arguments that
+they did not have in <NOBR>Release 2</NOBR>.
+Refer to sections 8.2 <NOBR>and 8.7</NOBR> for descriptions of these functions
+since <NOBR>Release 3</NOBR>.
+For <NOBR>Release 2</NOBR>, the rounding mode, when needed, was taken from the
+same global variable that affects the basic arithmetic operations (now called
+<CODE>softfloat_roundingMode</CODE> but previously known as
+<CODE>float_rounding_mode</CODE>).
+Also, for <NOBR>Release 2</NOBR>, if the original floating-point input was not
+an exact integer value, and if the <I>invalid</I> exception was not raised by
+the function, the <I>inexact</I> exception was always raised.
+<NOBR>Release 2</NOBR> had no option to suppress raising <I>inexact</I> in this
+case.
+Applications using SoftFloat <NOBR>Release 3</NOBR> or later can get the same
+effect as <NOBR>Release 2</NOBR> by passing variable
+<CODE>softfloat_roundingMode</CODE> for argument
+<CODE><I>roundingMode</I></CODE> and <CODE>true</CODE> for argument
+<CODE><I>exact</I></CODE>.
+</P>
+
+</UL>
+</P>
+
+<H3>9.3. Added Capabilities</H3>
+
+<P>
+With <NOBR>Release 3</NOBR>, some new features have been added that were not
+present in <NOBR>Release 2</NOBR>:
+<UL>
+
+<LI>
+<P>
+A port of SoftFloat can now define any of the floating-point types
+<CODE>float32_t</CODE>, <CODE>float64_t</CODE>, <CODE>extFloat80_t</CODE>, and
+<CODE>float128_t</CODE> as aliases for C&rsquo;s standard floating-point types
+<CODE>float</CODE>, <CODE>double</CODE>, and <CODE>long</CODE>
+<CODE>double</CODE>, using either <CODE>#define</CODE> or <CODE>typedef</CODE>.
+This potential convenience was not supported under <NOBR>Release 2</NOBR>.
+</P>
+
+<P>
+(Note, however, that there may be a performance cost to defining
+SoftFloat&rsquo;s floating-point types this way, depending on the platform and
+the applications using SoftFloat.
+Ports of SoftFloat may choose to forgo the convenience in favor of better
+speed.)
+</P>
+
+<P>
+<LI>
+As of <NOBR>Release 3b</NOBR>, <NOBR>16-bit</NOBR> half-precision,
+<CODE>float16_t</CODE>, is supported.
+</P>
+
+<P>
+<LI>
+Functions have been added for converting between the floating-point types and
+unsigned integers.
+<NOBR>Release 2</NOBR> supported only signed integers, not unsigned.
+</P>
+
+<P>
+<LI>
+Fused multiply-add functions have been added for all floating-point formats
+except <NOBR>80-bit</NOBR> double-extended-precision,
+<CODE>extFloat80_t</CODE>.
+</P>
+
+<P>
+<LI>
+New rounding modes are supported:
+<CODE>softfloat_round_near_maxMag</CODE> (round to nearest, with ties to
+maximum magnitude, away from zero), and, as of <NOBR>Release 3c</NOBR>,
+optional <CODE>softfloat_round_odd</CODE> (round to odd, also known as
+jamming).
+</P>
+
+</UL>
+</P>
+
+<H3>9.4. Better Compatibility with the C Language</H3>
+
+<P>
+<NOBR>Release 3</NOBR> of SoftFloat was written to conform better to the ISO C
+Standard&rsquo;s rules for portability.
+For example, older releases of SoftFloat employed type conversions in ways
+that, while commonly practiced, are not fully defined by the C Standard.
+Such problematic type conversions have generally been replaced by the use of
+unions, the behavior around which is more strictly regulated these days.
+</P>
+
+<H3>9.5. New Organization as a Library</H3>
+
+<P>
+Starting with <NOBR>Release 3</NOBR>, SoftFloat now builds as a library.
+Previously, SoftFloat compiled into a single, monolithic object file containing
+all the SoftFloat functions, with the consequence that a program linking with
+SoftFloat would get every SoftFloat function in its binary file even if only a
+few functions were actually used.
+With SoftFloat in the form of a library, a program that is linked by a standard
+linker will include only those functions of SoftFloat that it needs and no
+others.
+</P>
+
+<H3>9.6. Optimization Gains (and Losses)</H3>
+
+<P>
+Individual SoftFloat functions have been variously improved in
+<NOBR>Release 3</NOBR> compared to earlier releases.
+In particular, better, faster algorithms have been deployed for the operations
+of division, square root, and remainder.
+For functions operating on the larger <NOBR>80-bit</NOBR> and
+<NOBR>128-bit</NOBR> formats, <CODE>extFloat80_t</CODE> and
+<CODE>float128_t</CODE>, code size has also generally been reduced.
+</P>
+
+<P>
+However, because <NOBR>Release 2</NOBR> compiled all of SoftFloat together as a
+single object file, compilers could make optimizations across function calls
+when one SoftFloat function calls another.
+Now that the functions of SoftFloat are compiled separately and only afterward
+linked together into a program, there is not usually the same opportunity to
+optimize across function calls.
+Some loss of speed has been observed due to this change.
+</P>
+
+
+<H2>10. Future Directions</H2>
+
+<P>
+The following improvements are anticipated for future releases of SoftFloat:
+<UL>
+<LI>
+more functions from the 2008 version of the IEEE Floating-Point Standard;
+<LI>
+consistent, defined behavior for non-canonical representations of extended
+format <CODE>extFloat80_t</CODE> (discussed in <NOBR>section 4.4</NOBR>,
+<I>Non-canonical Representations in <CODE>extFloat80_t</CODE></I>).
+
+</UL>
+</P>
+
+
+<H2>11. Contact Information</H2>
+
+<P>
+At the time of this writing, the most up-to-date information about SoftFloat
+and the latest release can be found at the Web page
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/extF80M_isSignalingNaN.c b/addins/SoftFloat-3e/source/8086-SSE/extF80M_isSignalingNaN.c
new file mode 100644
index 000000000..85ee211c2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/extF80M_isSignalingNaN.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint64_t uiA0;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
+    uiA0 = aSPtr->signif;
+    return
+        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
+            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/f128M_isSignalingNaN.c b/addins/SoftFloat-3e/source/8086-SSE/f128M_isSignalingNaN.c
new file mode 100644
index 000000000..79a707771
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/f128M_isSignalingNaN.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool f128M_isSignalingNaN( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
+    return
+        ((uiA96 & 0x00007FFF) != 0)
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                     | aWPtr[indexWord( 4, 0 )])
+                    != 0);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80M.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80M.c
new file mode 100644
index 000000000..3405b3ba4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| `zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+
+    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
+    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80UI.c
new file mode 100644
index 000000000..cb7424f43
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToExtF80UI.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
+    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128M.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128M.c
new file mode 100644
index 000000000..e7ea80258
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by `zWPtr'.  Argument
+| `zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+
+    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
+    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128UI.c
new file mode 100644
index 000000000..7a9423bea
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF128UI.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
+    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF16UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF16UI.c
new file mode 100644
index 000000000..d4e458a94
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF16UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF32UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF32UI.c
new file mode 100644
index 000000000..ed6c2268f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF32UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF64UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF64UI.c
new file mode 100644
index 000000000..1182be3c9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_commonNaNToF64UI.c
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
+{
+
+    return
+        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
+            | aPtr->v64>>12;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_extF80MToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_extF80MToCommonNaN.c
new file mode 100644
index 000000000..00baf35f8
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_extF80MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
+{
+
+    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = signExtF80UI64( aSPtr->signExp );
+    zPtr->v64 = aSPtr->signif<<1;
+    zPtr->v0  = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_extF80UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_extF80UIToCommonNaN.c
new file mode 100644
index 000000000..ab6311ef2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_extF80UIToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA64>>15;
+    zPtr->v64  = uiA0<<1;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_f128MToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_f128MToCommonNaN.c
new file mode 100644
index 000000000..55ec25b58
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_f128MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument `aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
+{
+
+    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
+    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_f128UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_f128UIToCommonNaN.c
new file mode 100644
index 000000000..f838f02aa
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_f128UIToCommonNaN.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+    struct uint128 NaNSig;
+
+    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
+    zPtr->sign = uiA64>>63;
+    zPtr->v64  = NaNSig.v64;
+    zPtr->v0   = NaNSig.v0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_f16UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_f16UIToCommonNaN.c
new file mode 100644
index 000000000..c1e242d23
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_f16UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF16UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>15;
+    zPtr->v64  = (uint_fast64_t) uiA<<54;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_f32UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_f32UIToCommonNaN.c
new file mode 100644
index 000000000..b21ba6603
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_f32UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>31;
+    zPtr->v64  = (uint_fast64_t) uiA<<41;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_f64UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086-SSE/s_f64UIToCommonNaN.c
new file mode 100644
index 000000000..6529d2ee5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_f64UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>63;
+    zPtr->v64  = uiA<<12;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80M.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80M.c
new file mode 100644
index 000000000..ea1d57a78
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80M.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by `zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ )
+{
+    bool isSigNaNA;
+    const struct extFloat80M *sPtr;
+    bool isSigNaNB;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiMagA64, uiMagB64;
+
+    isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr );
+    sPtr = aSPtr;
+    if ( ! bSPtr ) {
+        if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid );
+        goto copy;
+    }
+    isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr );
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            uiB64 = bSPtr->signExp;
+            if ( isSigNaNB ) goto returnLargerUIMag;
+            uiB0 = bSPtr->signif;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB;
+            goto copy;
+        } else {
+            uiA64 = aSPtr->signExp;
+            uiA0 = aSPtr->signif;
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy;
+            goto copyB;
+        }
+    }
+    uiB64 = bSPtr->signExp;
+ returnLargerUIMag:
+    uiA64 = aSPtr->signExp;
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto copyB;
+    if ( uiMagB64 < uiMagA64 ) goto copy;
+    uiA0 = aSPtr->signif;
+    uiB0 = bSPtr->signif;
+    if ( uiA0 < uiB0 ) goto copyB;
+    if ( uiB0 < uiA0 ) goto copy;
+    if ( uiA64 < uiB64 ) goto copy;
+ copyB:
+    sPtr = bSPtr;
+ copy:
+    zSPtr->signExp = sPtr->signExp;
+    zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80UI.c
new file mode 100644
index 000000000..cc3f0f42c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNExtF80UI.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast64_t uiNonsigA0, uiNonsigB0;
+    uint_fast16_t uiMagA64, uiMagB64;
+    struct uint128 uiZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 );
+    isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 );
+    uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
+            goto returnA;
+        } else {
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA;
+            goto returnB;
+        }
+    }
+ returnLargerMag:
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto returnB;
+    if ( uiMagB64 < uiMagA64 ) goto returnA;
+    if ( uiA0 < uiB0 ) goto returnB;
+    if ( uiB0 < uiA0 ) goto returnA;
+    if ( uiA64 < uiB64 ) goto returnA;
+ returnB:
+    uiZ.v64 = uiB64;
+    uiZ.v0  = uiNonsigB0;
+    return uiZ;
+ returnA:
+    uiZ.v64 = uiA64;
+    uiZ.v0  = uiNonsigA0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128M.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128M.c
new file mode 100644
index 000000000..aa903bf80
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128M.c
@@ -0,0 +1,76 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by `zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of `aWPtr', `bWPtr',
+| and `zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
+{
+    bool isSigNaNA;
+    const uint32_t *ptr;
+
+    ptr = aWPtr;
+    isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr );
+    if (
+        isSigNaNA
+            || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr ))
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto copy;
+    }
+    if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr;
+ copy:
+    zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000;
+    zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )];
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128UI.c
new file mode 100644
index 000000000..1c1c2f4a0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF128UI.c
@@ -0,0 +1,81 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating `uiA64' and
+| `uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating `uiB64' and `uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA;
+    struct uint128 uiZ;
+
+    isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 );
+    if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto returnNonsigA;
+    }
+    if ( isNaNF128UI( uiA64, uiA0 ) ) {
+ returnNonsigA:
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+    } else {
+        uiZ.v64 = uiB64;
+        uiZ.v0  = uiB0;
+    }
+    uiZ.v64 |= UINT64_C( 0x0000800000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF16UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF16UI.c
new file mode 100644
index 000000000..4e87ff41f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF16UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either `uiA' or `uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF16UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | 0x0200;
+    }
+    return (isNaNF16UI( uiA ) ? uiA : uiB) | 0x0200;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF32UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF32UI.c
new file mode 100644
index 000000000..e1a875525
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF32UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting `uiA' and `uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either `uiA' or `uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | 0x00400000;
+    }
+    return (isNaNF32UI( uiA ) ? uiA : uiB) | 0x00400000;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF64UI.c b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF64UI.c
new file mode 100644
index 000000000..1af349f3e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/s_propagateNaNF64UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting `uiA' and `uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either `uiA' or `uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) return uiA | UINT64_C( 0x0008000000000000 );
+    }
+    return (isNaNF64UI( uiA ) ? uiA : uiB) | UINT64_C( 0x0008000000000000 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/softfloat_raiseFlags.c b/addins/SoftFloat-3e/source/8086-SSE/softfloat_raiseFlags.c
new file mode 100644
index 000000000..3115306be
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/softfloat_raiseFlags.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply `softfloat_exceptionFlags |= flags;'.
+*----------------------------------------------------------------------------*/
+void softfloat_raiseFlags( uint_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086-SSE/specialize.h b/addins/SoftFloat-3e/source/8086-SSE/specialize.h
new file mode 100644
index 000000000..5fe119a1e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086-SSE/specialize.h
@@ -0,0 +1,376 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef specialize_h
+#define specialize_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Default value for 'softfloat_detectTininess'.
+*----------------------------------------------------------------------------*/
+#define init_detectTininess softfloat_tininess_afterRounding
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 32-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromNegOverflow 0xFFFFFFFF
+#define ui32_fromNaN         0xFFFFFFFF
+#define i32_fromPosOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNegOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNaN          (-0x7FFFFFFF - 1)
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 64-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define i64_fromPosOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN          (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+
+/*----------------------------------------------------------------------------
+| "Common NaN" structure, used to transfer NaN representations from one format
+| to another.
+*----------------------------------------------------------------------------*/
+struct commonNaN {
+    bool sign;
+#ifdef LITTLEENDIAN
+    uint64_t v0, v64;
+#else
+    uint64_t v64, v0;
+#endif
+};
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 16-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF16UI 0xFE00
+
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 32-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF32UI 0xFFC00000
+
+/*----------------------------------------------------------------------------
+| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a
+| 32-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 64-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
+| 64-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 80-bit extended floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNExtF80UI64 0xFFFF
+#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 80-bit unsigned integer formed from concatenating
+| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended
+| floating-point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI0  UINT64_C( 0 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 128-bit unsigned integer formed from concatenating
+| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating-
+| point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+#else
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI96 0xFFFF8000
+#define defaultNaNF128UI64 0
+#define defaultNaNF128UI32 0
+#define defaultNaNF128UI0  0
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument 'aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/8086/extF80M_isSignalingNaN.c b/addins/SoftFloat-3e/source/8086/extF80M_isSignalingNaN.c
new file mode 100644
index 000000000..85ee211c2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/extF80M_isSignalingNaN.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint64_t uiA0;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
+    uiA0 = aSPtr->signif;
+    return
+        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
+            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/f128M_isSignalingNaN.c b/addins/SoftFloat-3e/source/8086/f128M_isSignalingNaN.c
new file mode 100644
index 000000000..79a707771
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/f128M_isSignalingNaN.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool f128M_isSignalingNaN( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
+    return
+        ((uiA96 & 0x00007FFF) != 0)
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                     | aWPtr[indexWord( 4, 0 )])
+                    != 0);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80M.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80M.c
new file mode 100644
index 000000000..3405b3ba4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| `zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+
+    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
+    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80UI.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80UI.c
new file mode 100644
index 000000000..cb7424f43
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToExtF80UI.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
+    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToF128M.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToF128M.c
new file mode 100644
index 000000000..e7ea80258
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToF128M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by `zWPtr'.  Argument
+| `zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+
+    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
+    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToF128UI.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToF128UI.c
new file mode 100644
index 000000000..7a9423bea
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToF128UI.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
+    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToF16UI.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToF16UI.c
new file mode 100644
index 000000000..d4e458a94
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToF16UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToF32UI.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToF32UI.c
new file mode 100644
index 000000000..ed6c2268f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToF32UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_commonNaNToF64UI.c b/addins/SoftFloat-3e/source/8086/s_commonNaNToF64UI.c
new file mode 100644
index 000000000..1182be3c9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_commonNaNToF64UI.c
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by `aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
+{
+
+    return
+        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
+            | aPtr->v64>>12;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_extF80MToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_extF80MToCommonNaN.c
new file mode 100644
index 000000000..00baf35f8
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_extF80MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by `aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by `zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
+{
+
+    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = signExtF80UI64( aSPtr->signExp );
+    zPtr->v64 = aSPtr->signif<<1;
+    zPtr->v0  = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_extF80UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_extF80UIToCommonNaN.c
new file mode 100644
index 000000000..ab6311ef2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_extF80UIToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA64>>15;
+    zPtr->v64  = uiA0<<1;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_f128MToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_f128MToCommonNaN.c
new file mode 100644
index 000000000..55ec25b58
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_f128MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by `aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by `zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument `aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
+{
+
+    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
+    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_f128UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_f128UIToCommonNaN.c
new file mode 100644
index 000000000..f838f02aa
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_f128UIToCommonNaN.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+    struct uint128 NaNSig;
+
+    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
+    zPtr->sign = uiA64>>63;
+    zPtr->v64  = NaNSig.v64;
+    zPtr->v0   = NaNSig.v0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_f16UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_f16UIToCommonNaN.c
new file mode 100644
index 000000000..c1e242d23
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_f16UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF16UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>15;
+    zPtr->v64  = (uint_fast64_t) uiA<<54;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_f32UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_f32UIToCommonNaN.c
new file mode 100644
index 000000000..b21ba6603
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_f32UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>31;
+    zPtr->v64  = (uint_fast64_t) uiA<<41;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_f64UIToCommonNaN.c b/addins/SoftFloat-3e/source/8086/s_f64UIToCommonNaN.c
new file mode 100644
index 000000000..6529d2ee5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_f64UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming `uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by `zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>63;
+    zPtr->v64  = uiA<<12;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80M.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80M.c
new file mode 100644
index 000000000..ea1d57a78
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80M.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by `aSPtr' and `bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by `zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ )
+{
+    bool isSigNaNA;
+    const struct extFloat80M *sPtr;
+    bool isSigNaNB;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiMagA64, uiMagB64;
+
+    isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr );
+    sPtr = aSPtr;
+    if ( ! bSPtr ) {
+        if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid );
+        goto copy;
+    }
+    isSigNaNB = extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr );
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            uiB64 = bSPtr->signExp;
+            if ( isSigNaNB ) goto returnLargerUIMag;
+            uiB0 = bSPtr->signif;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto copyB;
+            goto copy;
+        } else {
+            uiA64 = aSPtr->signExp;
+            uiA0 = aSPtr->signif;
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto copy;
+            goto copyB;
+        }
+    }
+    uiB64 = bSPtr->signExp;
+ returnLargerUIMag:
+    uiA64 = aSPtr->signExp;
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto copyB;
+    if ( uiMagB64 < uiMagA64 ) goto copy;
+    uiA0 = aSPtr->signif;
+    uiB0 = bSPtr->signif;
+    if ( uiA0 < uiB0 ) goto copyB;
+    if ( uiB0 < uiA0 ) goto copy;
+    if ( uiA64 < uiB64 ) goto copy;
+ copyB:
+    sPtr = bSPtr;
+ copy:
+    zSPtr->signExp = sPtr->signExp;
+    zSPtr->signif = sPtr->signif | UINT64_C( 0xC000000000000000 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80UI.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80UI.c
new file mode 100644
index 000000000..cc3f0f42c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNExtF80UI.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast64_t uiNonsigA0, uiNonsigB0;
+    uint_fast16_t uiMagA64, uiMagB64;
+    struct uint128 uiZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 );
+    isSigNaNB = softfloat_isSigNaNExtF80UI( uiB64, uiB0 );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA0 = uiA0 | UINT64_C( 0xC000000000000000 );
+    uiNonsigB0 = uiB0 | UINT64_C( 0xC000000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            if ( isNaNExtF80UI( uiB64, uiB0 ) ) goto returnB;
+            goto returnA;
+        } else {
+            if ( isNaNExtF80UI( uiA64, uiA0 ) ) goto returnA;
+            goto returnB;
+        }
+    }
+ returnLargerMag:
+    uiMagA64 = uiA64 & 0x7FFF;
+    uiMagB64 = uiB64 & 0x7FFF;
+    if ( uiMagA64 < uiMagB64 ) goto returnB;
+    if ( uiMagB64 < uiMagA64 ) goto returnA;
+    if ( uiA0 < uiB0 ) goto returnB;
+    if ( uiB0 < uiA0 ) goto returnA;
+    if ( uiA64 < uiB64 ) goto returnA;
+ returnB:
+    uiZ.v64 = uiB64;
+    uiZ.v0  = uiNonsigB0;
+    return uiZ;
+ returnA:
+    uiZ.v64 = uiA64;
+    uiZ.v0  = uiNonsigA0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNF128M.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNF128M.c
new file mode 100644
index 000000000..06554fbfe
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNF128M.c
@@ -0,0 +1,108 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| `aWPtr' and `bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by `zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of `aWPtr', `bWPtr',
+| and `zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
+{
+    bool isSigNaNA;
+    const uint32_t *ptr;
+    bool isSigNaNB;
+    uint32_t uiA96, uiB96, wordMagA, wordMagB;
+
+    isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr );
+    ptr = aWPtr;
+    if ( ! bWPtr ) {
+        if ( isSigNaNA ) softfloat_raiseFlags( softfloat_flag_invalid );
+        goto copy;
+    }
+    isSigNaNB = f128M_isSignalingNaN( (const float128_t *) bWPtr );
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerUIMag;
+            if ( softfloat_isNaNF128M( bWPtr ) ) goto copyB;
+            goto copy;
+        } else {
+            if ( softfloat_isNaNF128M( aWPtr ) ) goto copy;
+            goto copyB;
+        }
+    }
+ returnLargerUIMag:
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    wordMagA = uiA96 & 0x7FFFFFFF;
+    wordMagB = uiB96 & 0x7FFFFFFF;
+    if ( wordMagA < wordMagB ) goto copyB;
+    if ( wordMagB < wordMagA ) goto copy;
+    wordMagA = aWPtr[indexWord( 4, 2 )];
+    wordMagB = bWPtr[indexWord( 4, 2 )];
+    if ( wordMagA < wordMagB ) goto copyB;
+    if ( wordMagB < wordMagA ) goto copy;
+    wordMagA = aWPtr[indexWord( 4, 1 )];
+    wordMagB = bWPtr[indexWord( 4, 1 )];
+    if ( wordMagA < wordMagB ) goto copyB;
+    if ( wordMagB < wordMagA ) goto copy;
+    wordMagA = aWPtr[indexWord( 4, 0 )];
+    wordMagB = bWPtr[indexWord( 4, 0 )];
+    if ( wordMagA < wordMagB ) goto copyB;
+    if ( wordMagB < wordMagA ) goto copy;
+    if ( uiA96 < uiB96 ) goto copy;
+ copyB:
+    ptr = bWPtr;
+ copy:
+    zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000;
+    zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )];
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNF128UI.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNF128UI.c
new file mode 100644
index 000000000..46b9f5f2c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNF128UI.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast64_t uiNonsigA64, uiNonsigB64, uiMagA64, uiMagB64;
+    struct uint128 uiZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 );
+    isSigNaNB = softfloat_isSigNaNF128UI( uiB64, uiB0 );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA64 = uiA64 | UINT64_C( 0x0000800000000000 );
+    uiNonsigB64 = uiB64 | UINT64_C( 0x0000800000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            if ( isNaNF128UI( uiB64, uiB0 ) ) goto returnB;
+            goto returnA;
+        } else {
+            if ( isNaNF128UI( uiA64, uiA0 ) ) goto returnA;
+            goto returnB;
+        }
+    }
+ returnLargerMag:
+    uiMagA64 = uiA64 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    uiMagB64 = uiB64 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiMagA64 < uiMagB64 ) goto returnB;
+    if ( uiMagB64 < uiMagA64 ) goto returnA;
+    if ( uiA0 < uiB0 ) goto returnB;
+    if ( uiB0 < uiA0 ) goto returnA;
+    if ( uiNonsigA64 < uiNonsigB64 ) goto returnA;
+ returnB:
+    uiZ.v64 = uiNonsigB64;
+    uiZ.v0  = uiB0;
+    return uiZ;
+ returnA:
+    uiZ.v64 = uiNonsigA64;
+    uiZ.v0  = uiA0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNF16UI.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNF16UI.c
new file mode 100644
index 000000000..89cc0fe97
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNF16UI.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast16_t uiNonsigA, uiNonsigB, uiMagA, uiMagB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNF16UI( uiA );
+    isSigNaNB = softfloat_isSigNaNF16UI( uiB );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA = uiA | 0x0200;
+    uiNonsigB = uiB | 0x0200;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            return isNaNF16UI( uiB ) ? uiNonsigB : uiNonsigA;
+        } else {
+            return isNaNF16UI( uiA ) ? uiNonsigA : uiNonsigB;
+        }
+    }
+ returnLargerMag:
+    uiMagA = uiA & 0x7FFF;
+    uiMagB = uiB & 0x7FFF;
+    if ( uiMagA < uiMagB ) return uiNonsigB;
+    if ( uiMagB < uiMagA ) return uiNonsigA;
+    return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNF32UI.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNF32UI.c
new file mode 100644
index 000000000..aeb6024ac
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNF32UI.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast32_t uiNonsigA, uiNonsigB, uiMagA, uiMagB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );
+    isSigNaNB = softfloat_isSigNaNF32UI( uiB );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA = uiA | 0x00400000;
+    uiNonsigB = uiB | 0x00400000;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            return isNaNF32UI( uiB ) ? uiNonsigB : uiNonsigA;
+        } else {
+            return isNaNF32UI( uiA ) ? uiNonsigA : uiNonsigB;
+        }
+    }
+ returnLargerMag:
+    uiMagA = uiA & 0x7FFFFFFF;
+    uiMagB = uiB & 0x7FFFFFFF;
+    if ( uiMagA < uiMagB ) return uiNonsigB;
+    if ( uiMagB < uiMagA ) return uiNonsigA;
+    return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/s_propagateNaNF64UI.c b/addins/SoftFloat-3e/source/8086/s_propagateNaNF64UI.c
new file mode 100644
index 000000000..dabad4024
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/s_propagateNaNF64UI.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+    bool isSigNaNA, isSigNaNB;
+    uint_fast64_t uiNonsigA, uiNonsigB, uiMagA, uiMagB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    isSigNaNB = softfloat_isSigNaNF64UI( uiB );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiNonsigA = uiA | UINT64_C( 0x0008000000000000 );
+    uiNonsigB = uiB | UINT64_C( 0x0008000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) {
+            if ( isSigNaNB ) goto returnLargerMag;
+            return isNaNF64UI( uiB ) ? uiNonsigB : uiNonsigA;
+        } else {
+            return isNaNF64UI( uiA ) ? uiNonsigA : uiNonsigB;
+        }
+    }
+ returnLargerMag:
+    uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiMagA < uiMagB ) return uiNonsigB;
+    if ( uiMagB < uiMagA ) return uiNonsigA;
+    return (uiNonsigA < uiNonsigB) ? uiNonsigA : uiNonsigB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/softfloat_raiseFlags.c b/addins/SoftFloat-3e/source/8086/softfloat_raiseFlags.c
new file mode 100644
index 000000000..3115306be
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/softfloat_raiseFlags.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply `softfloat_exceptionFlags |= flags;'.
+*----------------------------------------------------------------------------*/
+void softfloat_raiseFlags( uint_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/8086/specialize.h b/addins/SoftFloat-3e/source/8086/specialize.h
new file mode 100644
index 000000000..5fe119a1e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/8086/specialize.h
@@ -0,0 +1,376 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef specialize_h
+#define specialize_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Default value for 'softfloat_detectTininess'.
+*----------------------------------------------------------------------------*/
+#define init_detectTininess softfloat_tininess_afterRounding
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 32-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromNegOverflow 0xFFFFFFFF
+#define ui32_fromNaN         0xFFFFFFFF
+#define i32_fromPosOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNegOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNaN          (-0x7FFFFFFF - 1)
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 64-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNaN         UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define i64_fromPosOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN          (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+
+/*----------------------------------------------------------------------------
+| "Common NaN" structure, used to transfer NaN representations from one format
+| to another.
+*----------------------------------------------------------------------------*/
+struct commonNaN {
+    bool sign;
+#ifdef LITTLEENDIAN
+    uint64_t v0, v64;
+#else
+    uint64_t v64, v0;
+#endif
+};
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 16-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF16UI 0xFE00
+
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 32-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF32UI 0xFFC00000
+
+/*----------------------------------------------------------------------------
+| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a
+| 32-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 64-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
+| 64-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 80-bit extended floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNExtF80UI64 0xFFFF
+#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 80-bit unsigned integer formed from concatenating
+| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended
+| floating-point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 )
+#define defaultNaNF128UI0  UINT64_C( 0 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 128-bit unsigned integer formed from concatenating
+| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating-
+| point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+#else
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI96 0xFFFF8000
+#define defaultNaNF128UI64 0
+#define defaultNaNF128UI32 0
+#define defaultNaNF128UI0  0
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument 'aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c
new file mode 100644
index 000000000..85ee211c2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/extF80M_isSignalingNaN.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint64_t uiA0;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
+    uiA0 = aSPtr->signif;
+    return
+        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
+            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c
new file mode 100644
index 000000000..79a707771
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/f128M_isSignalingNaN.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool f128M_isSignalingNaN( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
+    return
+        ((uiA96 & 0x00007FFF) != 0)
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                     | aWPtr[indexWord( 4, 0 )])
+                    != 0);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c
new file mode 100644
index 000000000..54a50dc35
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80M.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat_types.h"
+
+#define softfloat_commonNaNToExtF80M softfloat_commonNaNToExtF80M
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c
new file mode 100644
index 000000000..5b698f664
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToExtF80UI.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToExtF80UI softfloat_commonNaNToExtF80UI
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c
new file mode 100644
index 000000000..b22baa816
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128M.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToF128M softfloat_commonNaNToF128M
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c
new file mode 100644
index 000000000..70f0cf1c6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF128UI.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#define softfloat_commonNaNToF128UI softfloat_commonNaNToF128UI
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF16UI.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF32UI.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_commonNaNToF64UI.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80MToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_extF80UIToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128MToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f128UIToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f16UIToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f32UIToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c
new file mode 100644
index 000000000..7c7d5c82e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_f64UIToCommonNaN.c
@@ -0,0 +1,5 @@
+
+/*----------------------------------------------------------------------------
+| This file intentionally contains no code.
+*----------------------------------------------------------------------------*/
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c
new file mode 100644
index 000000000..1c6510c7e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80M.c
@@ -0,0 +1,74 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ )
+{
+    uint_fast16_t ui64;
+    uint_fast64_t ui0;
+
+    ui64 = aSPtr->signExp;
+    ui0  = aSPtr->signif;
+    if (
+        softfloat_isSigNaNExtF80UI( ui64, ui0 )
+            || (bSPtr
+                    && (ui64 = bSPtr->signExp,
+                        ui0  = bSPtr->signif,
+                        softfloat_isSigNaNExtF80UI( ui64, ui0 )))
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c
new file mode 100644
index 000000000..e1bb1555a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNExtF80UI.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    struct uint128 uiZ;
+
+    if (
+           softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+        || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c
new file mode 100644
index 000000000..9bddee955
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128M.c
@@ -0,0 +1,68 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
+{
+
+    if (
+        f128M_isSignalingNaN( (const float128_t *) aWPtr );
+            || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr ))
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c
new file mode 100644
index 000000000..57fddd158
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF128UI.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    struct uint128 uiZ;
+
+    if (
+           softfloat_isSigNaNF128UI( uiA64, uiA0 )
+        || softfloat_isSigNaNF128UI( uiB64, uiB0 )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c
new file mode 100644
index 000000000..0b08e0039
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF16UI.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+
+    if ( softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    return defaultNaNF16UI;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c
new file mode 100644
index 000000000..cab740358
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF32UI.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+
+    if ( softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    return defaultNaNF32UI;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c
new file mode 100644
index 000000000..83b91d3a9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/s_propagateNaNF64UI.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+
+    if ( softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    return defaultNaNF64UI;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c
new file mode 100644
index 000000000..61046da3c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/softfloat_raiseFlags.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by 'flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply 'softfloat_exceptionFlags |= flags;'.
+*----------------------------------------------------------------------------*/
+void softfloat_raiseFlags( uint_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h
new file mode 100644
index 000000000..2c481a259
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h
@@ -0,0 +1,407 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef specialize_h
+#define specialize_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Default value for 'softfloat_detectTininess'.
+*----------------------------------------------------------------------------*/
+#define init_detectTininess softfloat_tininess_beforeRounding
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 32-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromNegOverflow 0
+#define ui32_fromNaN         0
+#define i32_fromPosOverflow  0x7FFFFFFF
+#define i32_fromNegOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNaN          0
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 64-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow 0
+#define ui64_fromNaN         0
+#define i64_fromPosOverflow  INT64_C( 0x7FFFFFFFFFFFFFFF )
+#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN          0
+
+/*----------------------------------------------------------------------------
+| "Common NaN" structure, used to transfer NaN representations from one format
+| to another.
+*----------------------------------------------------------------------------*/
+struct commonNaN { char _unused; };
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 16-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF16UI 0x7E00
+
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+#define softfloat_commonNaNToF16UI( aPtr ) ((uint_fast16_t) defaultNaNF16UI)
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 32-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF32UI 0x7FC00000
+
+/*----------------------------------------------------------------------------
+| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a
+| 32-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+#define softfloat_commonNaNToF32UI( aPtr ) ((uint_fast32_t) defaultNaNF32UI)
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 64-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
+| 64-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+#define softfloat_commonNaNToF64UI( aPtr ) ((uint_fast64_t) defaultNaNF64UI)
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 80-bit extended floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNExtF80UI64 0x7FFF
+#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 80-bit unsigned integer formed from concatenating
+| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended
+| floating-point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToExtF80UI
+INLINE
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+    uiZ.v64 = defaultNaNExtF80UI64;
+    uiZ.v0  = defaultNaNExtF80UI0;
+    return uiZ;
+}
+#else
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+#endif
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 )
+#define defaultNaNF128UI0  UINT64_C( 0 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 128-bit unsigned integer formed from concatenating
+| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating-
+| point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToF128UI
+INLINE
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+    return uiZ;
+}
+#else
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+#endif
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+#else
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToExtF80M
+INLINE
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
+}
+#else
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+#endif
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI96 0x7FFF8000
+#define defaultNaNF128UI64 0
+#define defaultNaNF128UI32 0
+#define defaultNaNF128UI0  0
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument 'aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid )
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+#if defined INLINE && ! defined softfloat_commonNaNToF128M
+INLINE
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+}
+#else
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+#endif
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/extF80M_isSignalingNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/extF80M_isSignalingNaN.c
new file mode 100644
index 000000000..85ee211c2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/extF80M_isSignalingNaN.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool extF80M_isSignalingNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint64_t uiA0;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    if ( (aSPtr->signExp & 0x7FFF) != 0x7FFF ) return false;
+    uiA0 = aSPtr->signif;
+    return
+        ! (uiA0 & UINT64_C( 0x4000000000000000 ))
+            && (uiA0 & UINT64_C( 0x3FFFFFFFFFFFFFFF));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/f128M_isSignalingNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/f128M_isSignalingNaN.c
new file mode 100644
index 000000000..79a707771
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/f128M_isSignalingNaN.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool f128M_isSignalingNaN( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    if ( (uiA96 & 0x7FFF8000) != 0x7FFF0000 ) return false;
+    return
+        ((uiA96 & 0x00007FFF) != 0)
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                     | aWPtr[indexWord( 4, 0 )])
+                    != 0);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80M.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80M.c
new file mode 100644
index 000000000..543400bc1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr )
+{
+
+    zSPtr->signExp = packToExtF80UI64( aPtr->sign, 0x7FFF );
+    zSPtr->signif = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80UI.c
new file mode 100644
index 000000000..6cf1d1191
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToExtF80UI.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ.v64 = (uint_fast16_t) aPtr->sign<<15 | 0x7FFF;
+    uiZ.v0 = UINT64_C( 0xC000000000000000 ) | aPtr->v64>>1;
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128M.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128M.c
new file mode 100644
index 000000000..4e8ede07f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr )
+{
+
+    softfloat_shortShiftRight128M( (const uint32_t *) &aPtr->v0, 16, zWPtr );
+    zWPtr[indexWordHi( 4 )] |= (uint32_t) aPtr->sign<<31 | 0x7FFF8000;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128UI.c
new file mode 100644
index 000000000..f938c3f2d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF128UI.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr )
+{
+    struct uint128 uiZ;
+
+    uiZ = softfloat_shortShiftRight128( aPtr->v64, aPtr->v0, 16 );
+    uiZ.v64 |= (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FFF800000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF16UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF16UI.c
new file mode 100644
index 000000000..6cd4fc192
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF16UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast16_t) aPtr->sign<<15 | 0x7E00 | aPtr->v64>>54;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF32UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF32UI.c
new file mode 100644
index 000000000..7b38167f0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF32UI.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr )
+{
+
+    return (uint_fast32_t) aPtr->sign<<31 | 0x7FC00000 | aPtr->v64>>41;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF64UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF64UI.c
new file mode 100644
index 000000000..14847029d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_commonNaNToF64UI.c
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr )
+{
+
+    return
+        (uint_fast64_t) aPtr->sign<<63 | UINT64_C( 0x7FF8000000000000 )
+            | aPtr->v64>>12;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80MToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80MToCommonNaN.c
new file mode 100644
index 000000000..82216cf41
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr )
+{
+
+    if ( extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = signExtF80UI64( aSPtr->signExp );
+    zPtr->v64 = aSPtr->signif<<1;
+    zPtr->v0  = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80UIToCommonNaN.c
new file mode 100644
index 000000000..2559fb6d2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_extF80UIToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA64>>15;
+    zPtr->v64  = uiA0<<1;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128MToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128MToCommonNaN.c
new file mode 100644
index 000000000..322d25ab1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128MToCommonNaN.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument 'aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr )
+{
+
+    if ( f128M_isSignalingNaN( (const float128_t *) aWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = aWPtr[indexWordHi( 4 )]>>31;
+    softfloat_shortShiftLeft128M( aWPtr, 16, (uint32_t *) &zPtr->v0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128UIToCommonNaN.c
new file mode 100644
index 000000000..843c187a7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f128UIToCommonNaN.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr )
+{
+    struct uint128 NaNSig;
+
+    if ( softfloat_isSigNaNF128UI( uiA64, uiA0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    NaNSig = softfloat_shortShiftLeft128( uiA64, uiA0, 16 );
+    zPtr->sign = uiA64>>63;
+    zPtr->v64  = NaNSig.v64;
+    zPtr->v0   = NaNSig.v0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_f16UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f16UIToCommonNaN.c
new file mode 100644
index 000000000..f5fe58770
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f16UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF16UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>15;
+    zPtr->v64  = (uint_fast64_t) uiA<<54;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_f32UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f32UIToCommonNaN.c
new file mode 100644
index 000000000..58726a357
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f32UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>31;
+    zPtr->v64  = (uint_fast64_t) uiA<<41;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_f64UIToCommonNaN.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f64UIToCommonNaN.c
new file mode 100644
index 000000000..03761e433
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_f64UIToCommonNaN.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr )
+{
+
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    zPtr->sign = uiA>>63;
+    zPtr->v64  = uiA<<12;
+    zPtr->v0   = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80M.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80M.c
new file mode 100644
index 000000000..f10ed0b62
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80M.c
@@ -0,0 +1,86 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ )
+{
+    const struct extFloat80M *sPtr;
+    bool isSigNaNA;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    sPtr = aSPtr;
+    isSigNaNA = extF80M_isSignalingNaN( (const extFloat80_t *) aSPtr );
+    if (
+        isSigNaNA
+            || (bSPtr
+                    && extF80M_isSignalingNaN( (const extFloat80_t *) bSPtr ))
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto copyNonsig;
+        goto copyNonsigB;
+    }
+    uiZ64 = sPtr->signExp;
+    uiZ0  = sPtr->signif;
+    if ( isNaNExtF80UI( uiZ64, uiZ0 ) ) goto returnNonsig;
+ copyNonsigB:
+    sPtr = bSPtr;
+ copyNonsig:
+    uiZ64 = sPtr->signExp;
+    uiZ0  = sPtr->signif;
+ returnNonsig:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = uiZ0 | UINT64_C( 0xC000000000000000 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80UI.c
new file mode 100644
index 000000000..bd23c2473
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNExtF80UI.c
@@ -0,0 +1,83 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA;
+    struct uint128 uiZ;
+
+    isSigNaNA = softfloat_isSigNaNExtF80UI( uiA64, uiA0 );
+    if ( isSigNaNA || softfloat_isSigNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto returnNonsigA;
+        goto returnNonsigB;
+    }
+    if ( isNaNExtF80UI( uiA64, uiA0 ) ) {
+ returnNonsigA:
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+    } else {
+ returnNonsigB:
+        uiZ.v64 = uiB64;
+        uiZ.v0  = uiB0;
+    }
+    uiZ.v0 | UINT64_C( 0xC000000000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128M.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128M.c
new file mode 100644
index 000000000..23e766a19
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128M.c
@@ -0,0 +1,77 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
+{
+    const uint32_t *ptr;
+    bool isSigNaNA;
+
+    ptr = aWPtr;
+    isSigNaNA = f128M_isSignalingNaN( (const float128_t *) aWPtr );
+    if (
+        isSigNaNA
+            || (bWPtr && f128M_isSignalingNaN( (const float128_t *) bWPtr ))
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( ! isSigNaNA ) ptr = bWPtr;
+        goto copyNonsig;
+    }
+    if ( ! softfloat_isNaNF128M( aWPtr ) ) ptr = bWPtr;
+ copyNonsig:
+    zWPtr[indexWordHi( 4 )] = ptr[indexWordHi( 4 )] | 0x00008000;
+    zWPtr[indexWord( 4, 2 )] = ptr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = ptr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = ptr[indexWord( 4, 0 )];
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128UI.c
new file mode 100644
index 000000000..b8882d77c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF128UI.c
@@ -0,0 +1,83 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ )
+{
+    bool isSigNaNA;
+    struct uint128 uiZ;
+
+    isSigNaNA = softfloat_isSigNaNF128UI( uiA64, uiA0 );
+    if ( isSigNaNA || softfloat_isSigNaNF128UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        if ( isSigNaNA ) goto returnNonsigA;
+        goto returnNonsigB;
+    }
+    if ( isNaNF128UI( uiA64, uiA0 ) ) {
+ returnNonsigA:
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+    } else {
+ returnNonsigB:
+        uiZ.v64 = uiB64;
+        uiZ.v0  = uiB0;
+    }
+    uiZ.v64 |= UINT64_C( 0x0000800000000000 );
+    return uiZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF16UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF16UI.c
new file mode 100644
index 000000000..e33332874
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF16UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF16UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return (isSigNaNA ? uiA : uiB) | 0x0200;
+    }
+    return isNaNF16UI( uiA ) ? uiA : uiB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF32UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF32UI.c
new file mode 100644
index 000000000..c7508ae7c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF32UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return (isSigNaNA ? uiA : uiB) | 0x00400000;
+    }
+    return isNaNF32UI( uiA ) ? uiA : uiB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF64UI.c b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF64UI.c
new file mode 100644
index 000000000..8c6776381
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/s_propagateNaNF64UI.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+    bool isSigNaNA;
+
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    if ( isSigNaNA || softfloat_isSigNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return (isSigNaNA ? uiA : uiB) | UINT64_C( 0x0008000000000000 );
+    }
+    return isNaNF64UI( uiA ) ? uiA : uiB;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/softfloat_raiseFlags.c b/addins/SoftFloat-3e/source/ARM-VFPv2/softfloat_raiseFlags.c
new file mode 100644
index 000000000..61046da3c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/softfloat_raiseFlags.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by 'flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply 'softfloat_exceptionFlags |= flags;'.
+*----------------------------------------------------------------------------*/
+void softfloat_raiseFlags( uint_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ARM-VFPv2/specialize.h b/addins/SoftFloat-3e/source/ARM-VFPv2/specialize.h
new file mode 100644
index 000000000..5321f33bc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ARM-VFPv2/specialize.h
@@ -0,0 +1,376 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef specialize_h
+#define specialize_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitiveTypes.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Default value for 'softfloat_detectTininess'.
+*----------------------------------------------------------------------------*/
+#define init_detectTininess softfloat_tininess_beforeRounding
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 32-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui32_fromPosOverflow 0xFFFFFFFF
+#define ui32_fromNegOverflow 0
+#define ui32_fromNaN         0
+#define i32_fromPosOverflow  0x7FFFFFFF
+#define i32_fromNegOverflow  (-0x7FFFFFFF - 1)
+#define i32_fromNaN          0
+
+/*----------------------------------------------------------------------------
+| The values to return on conversions to 64-bit integer formats that raise an
+| invalid exception.
+*----------------------------------------------------------------------------*/
+#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF )
+#define ui64_fromNegOverflow 0
+#define ui64_fromNaN         0
+#define i64_fromPosOverflow  INT64_C( 0x7FFFFFFFFFFFFFFF )
+#define i64_fromNegOverflow  (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+#define i64_fromNaN          0
+
+/*----------------------------------------------------------------------------
+| "Common NaN" structure, used to transfer NaN representations from one format
+| to another.
+*----------------------------------------------------------------------------*/
+struct commonNaN {
+    bool sign;
+#ifdef LITTLEENDIAN
+    uint64_t v0, v64;
+#else
+    uint64_t v64, v0;
+#endif
+};
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 16-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF16UI 0x7E00
+
+/*----------------------------------------------------------------------------
+| Returns true when 16-bit unsigned integer 'uiA' has the bit pattern of a
+| 16-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast16_t
+ softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 32-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF32UI 0x7FC00000
+
+/*----------------------------------------------------------------------------
+| Returns true when 32-bit unsigned integer 'uiA' has the bit pattern of a
+| 32-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast32_t
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 64-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a
+| 64-bit floating-point signaling NaN.
+| Note:  This macro evaluates its argument more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF )))
+
+/*----------------------------------------------------------------------------
+| Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating-
+| point values, at least one of which is a NaN, returns the bit pattern of
+| the combined NaN result.  If either 'uiA' or 'uiB' has the pattern of a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 80-bit extended floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNExtF80UI64 0x7FFF
+#define defaultNaNExtF80UI0  UINT64_C( 0xC000000000000000 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 80-bit unsigned integer formed from concatenating
+| 16-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of an 80-bit extended
+| floating-point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF )))
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of an 80-bit extended floating-point NaN, converts
+| this NaN to the common NaN form, and stores the resulting common NaN at the
+| location pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80UIToCommonNaN(
+     uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and returns the bit pattern of this value as an unsigned
+| integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as an 80-bit extended floating-point value, and likewise interpreting
+| the unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 80-bit extended floating-point value, and assuming at least on of these
+| floating-point values is a NaN, returns the bit pattern of the combined NaN
+| result.  If either original floating-point value is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNExtF80UI(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 )
+#define defaultNaNF128UI0  UINT64_C( 0 )
+
+/*----------------------------------------------------------------------------
+| Returns true when the 128-bit unsigned integer formed from concatenating
+| 64-bit 'uiA64' and 64-bit 'uiA0' has the bit pattern of a 128-bit floating-
+| point signaling NaN.
+| Note:  This macro evaluates its arguments more than once.
+*----------------------------------------------------------------------------*/
+#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF ))))
+
+/*----------------------------------------------------------------------------
+| Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0'
+| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
+| the common NaN form, and stores the resulting common NaN at the location
+| pointed to by 'zPtr'.  If the NaN is a signaling NaN, the invalid exception
+| is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128UIToCommonNaN(
+     uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and returns the bit pattern of this value as an unsigned integer.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * );
+
+/*----------------------------------------------------------------------------
+| Interpreting the unsigned integer formed from concatenating 'uiA64' and
+| 'uiA0' as a 128-bit floating-point value, and likewise interpreting the
+| unsigned integer formed from concatenating 'uiB64' and 'uiB0' as another
+| 128-bit floating-point value, and assuming at least on of these floating-
+| point values is a NaN, returns the bit pattern of the combined NaN result.
+| If either original floating-point value is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_propagateNaNF128UI(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0
+ );
+
+#else
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not
+| defined.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+| Assuming the 80-bit extended floating-point value pointed to by 'aSPtr' is
+| a NaN, converts this NaN to the common NaN form, and stores the resulting
+| common NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling
+| NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_extF80MToCommonNaN(
+     const struct extFloat80M *aSPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into an 80-bit extended
+| floating-point NaN, and stores this NaN at the location pointed to by
+| 'zSPtr'.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToExtF80M(
+     const struct commonNaN *aPtr, struct extFloat80M *zSPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 80-bit extended floating-point values
+| pointed to by 'aSPtr' and 'bSPtr' is a NaN, stores the combined NaN result
+| at the location pointed to by 'zSPtr'.  If either original floating-point
+| value is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ );
+
+/*----------------------------------------------------------------------------
+| The bit pattern for a default generated 128-bit floating-point NaN.
+*----------------------------------------------------------------------------*/
+#define defaultNaNF128UI96 0x7FFF8000
+#define defaultNaNF128UI64 0
+#define defaultNaNF128UI32 0
+#define defaultNaNF128UI0  0
+
+/*----------------------------------------------------------------------------
+| Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN,
+| converts this NaN to the common NaN form, and stores the resulting common
+| NaN at the location pointed to by 'zPtr'.  If the NaN is a signaling NaN,
+| the invalid exception is raised.  Argument 'aWPtr' points to an array of
+| four 32-bit elements that concatenate in the platform's normal endian order
+| to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr );
+
+/*----------------------------------------------------------------------------
+| Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point
+| NaN, and stores this NaN at the location pointed to by 'zWPtr'.  Argument
+| 'zWPtr' points to an array of four 32-bit elements that concatenate in the
+| platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr );
+
+/*----------------------------------------------------------------------------
+| Assuming at least one of the two 128-bit floating-point values pointed to by
+| 'aWPtr' and 'bWPtr' is a NaN, stores the combined NaN result at the location
+| pointed to by 'zWPtr'.  If either original floating-point value is a
+| signaling NaN, the invalid exception is raised.  Each of 'aWPtr', 'bWPtr',
+| and 'zWPtr' points to an array of four 32-bit elements that concatenate in
+| the platform's normal endian order to form a 128-bit floating-point value.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_propagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr );
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_add.c b/addins/SoftFloat-3e/source/extF80M_add.c
new file mode 100644
index 000000000..02e415fcc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_add.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_add(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    extFloat80_t
+        (*magsFuncPtr)(
+            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+#endif
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    signA = signExtF80UI64( uiA64 );
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    signB = signExtF80UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        *zPtr = softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        *zPtr = softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80;
+    *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
+#else
+
+void
+ extF80M_add(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    softfloat_addExtF80M(
+        (const struct extFloat80M *) aPtr,
+        (const struct extFloat80M *) bPtr,
+        (struct extFloat80M *) zPtr,
+        false
+    );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_div.c b/addins/SoftFloat-3e/source/extF80M_div.c
new file mode 100644
index 000000000..4d543ce9e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_div.c
@@ -0,0 +1,194 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_div(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *zPtr = extF80_div( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ extF80M_div(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiA64;
+    int32_t expA;
+    uint_fast16_t uiB64;
+    int32_t expB;
+    bool signZ;
+    uint64_t sigA, x64;
+    int32_t expZ;
+    int shiftDist;
+    uint32_t y[3], recip32, sigB[3];
+    int ix;
+    uint32_t q, qs[2];
+    uint_fast16_t uiZ64;
+    uint64_t uiZ0;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    expA = expExtF80UI64( uiA64 );
+    uiB64 = bSPtr->signExp;
+    expB = expExtF80UI64( uiB64 );
+    signZ = signExtF80UI64( uiA64 ) ^ signExtF80UI64( uiB64 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return;
+        if ( expA == 0x7FFF ) {
+            if ( expB == 0x7FFF ) goto invalid;
+            goto infinity;
+        }
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigA = aSPtr->signif;
+    x64 = bSPtr->signif;
+    if ( ! expB ) expB = 1;
+    if ( ! (x64 & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! x64 ) {
+            if ( ! sigA ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        expB += softfloat_normExtF80SigM( &x64 );
+    }
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) goto zero;
+        expA += softfloat_normExtF80SigM( &sigA );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x3FFF;
+    shiftDist = 29;
+    if ( sigA < x64 ) {
+        --expZ;
+        shiftDist = 30;
+    }
+    softfloat_shortShiftLeft64To96M( sigA, shiftDist, y );
+    recip32 = softfloat_approxRecip32_1( x64>>32 );
+    sigB[indexWord( 3, 0 )] = (uint32_t) x64<<30;
+    x64 >>= 2;
+    sigB[indexWord( 3, 2 )] = x64>>32;
+    sigB[indexWord( 3, 1 )] = x64;
+    ix = 2;
+    for (;;) {
+        x64 = (uint64_t) y[indexWordHi( 3 )] * recip32;
+        q = (x64 + 0x80000000)>>32;
+        --ix;
+        if ( ix < 0 ) break;
+        softfloat_remStep96MBy32( y, 29, sigB, q, y );
+        if ( y[indexWordHi( 3 )] & 0x80000000 ) {
+            --q;
+            softfloat_add96M( y, sigB, y );
+        }
+        qs[ix] = q;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ((q + 1) & 0x3FFFFF) < 2 ) {
+        softfloat_remStep96MBy32( y, 29, sigB, q, y );
+        if ( y[indexWordHi( 3 )] & 0x80000000 ) {
+            --q;
+            softfloat_add96M( y, sigB, y );
+        } else if ( softfloat_compare96M( sigB, y ) <= 0 ) {
+            ++q;
+            softfloat_sub96M( y, sigB, y );
+        }
+        if (
+            y[indexWordLo( 3 )] || y[indexWord( 3, 1 )] || y[indexWord( 3, 2 )]
+        ) {
+            q |= 1;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    x64 = (uint64_t) q<<9;
+    y[indexWord( 3, 0 )] = x64;
+    x64 = ((uint64_t) qs[0]<<6) + (x64>>32);
+    y[indexWord( 3, 1 )] = x64;
+    y[indexWord( 3, 2 )] = (qs[1]<<3) + (x64>>32);
+    softfloat_roundPackMToExtF80M(
+        signZ, expZ, y, extF80_roundingPrecision, zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidExtF80M( zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ64 = packToExtF80UI64( signZ, 0x7FFF );
+    uiZ0  = UINT64_C( 0x8000000000000000 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ64 = packToExtF80UI64( signZ, 0 );
+    uiZ0  = 0;
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_eq.c b/addins/SoftFloat-3e/source/extF80M_eq.c
new file mode 100644
index 000000000..e17aa2435
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_eq.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_eq( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( uiA0 == uiB0 ) {
+        return (uiA64 == uiB64) || ! uiA0;
+    } else {
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return ! softfloat_compareNonnormExtF80M( aSPtr, bSPtr );
+        }
+        return false;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_eq_signaling.c b/addins/SoftFloat-3e/source/extF80M_eq_signaling.c
new file mode 100644
index 000000000..c4a732239
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_eq_signaling.c
@@ -0,0 +1,92 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_eq_signaling( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_eq_signaling( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_eq_signaling( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( uiA0 == uiB0 ) {
+        return (uiA64 == uiB64) || ! uiA0;
+    } else {
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return ! softfloat_compareNonnormExtF80M( aSPtr, bSPtr );
+        }
+        return false;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_le.c b/addins/SoftFloat-3e/source/extF80M_le.c
new file mode 100644
index 000000000..e54eb9eea
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_le.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_le( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    bool signA, ltMags;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signExtF80UI64( uiA64 );
+    if ( (uiA64 ^ uiB64) & 0x8000 ) {
+        /*--------------------------------------------------------------------
+        | Signs are different.
+        *--------------------------------------------------------------------*/
+        return signA || ! (uiA0 | uiB0);
+    } else {
+        /*--------------------------------------------------------------------
+        | Signs are the same.
+        *--------------------------------------------------------------------*/
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) <= 0);
+        }
+        if ( uiA64 == uiB64 ) {
+            if ( uiA0 == uiB0 ) return true;
+            ltMags = (uiA0 < uiB0);
+        } else {
+            ltMags = (uiA64 < uiB64);
+        }
+        return signA ^ ltMags;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_le_quiet.c b/addins/SoftFloat-3e/source/extF80M_le_quiet.c
new file mode 100644
index 000000000..943f26206
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_le_quiet.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_le_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_le_quiet( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_le_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    bool signA, ltMags;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signExtF80UI64( uiA64 );
+    if ( (uiA64 ^ uiB64) & 0x8000 ) {
+        /*--------------------------------------------------------------------
+        | Signs are different.
+        *--------------------------------------------------------------------*/
+        return signA || ! (uiA0 | uiB0);
+    } else {
+        /*--------------------------------------------------------------------
+        | Signs are the same.
+        *--------------------------------------------------------------------*/
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) <= 0);
+        }
+        if ( uiA64 == uiB64 ) {
+            if ( uiA0 == uiB0 ) return true;
+            ltMags = (uiA0 < uiB0);
+        } else {
+            ltMags = (uiA64 < uiB64);
+        }
+        return signA ^ ltMags;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_lt.c b/addins/SoftFloat-3e/source/extF80M_lt.c
new file mode 100644
index 000000000..cbc562f64
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_lt.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_lt( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    bool signA, ltMags;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signExtF80UI64( uiA64 );
+    if ( (uiA64 ^ uiB64) & 0x8000 ) {
+        /*--------------------------------------------------------------------
+        | Signs are different.
+        *--------------------------------------------------------------------*/
+        return signA && ((uiA0 | uiB0) != 0);
+    } else {
+        /*--------------------------------------------------------------------
+        | Signs are the same.
+        *--------------------------------------------------------------------*/
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) < 0);
+        }
+        if ( uiA64 == uiB64 ) {
+            if ( uiA0 == uiB0 ) return false;
+            ltMags = (uiA0 < uiB0);
+        } else {
+            ltMags = (uiA64 < uiB64);
+        }
+        return signA ^ ltMags;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_lt_quiet.c b/addins/SoftFloat-3e/source/extF80M_lt_quiet.c
new file mode 100644
index 000000000..650586d02
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_lt_quiet.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool extF80M_lt_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return extF80_lt_quiet( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool extF80M_lt_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint64_t uiA0;
+    uint_fast16_t uiB64;
+    uint64_t uiB0;
+    bool signA, ltMags;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signExtF80UI64( uiA64 );
+    if ( (uiA64 ^ uiB64) & 0x8000 ) {
+        /*--------------------------------------------------------------------
+        | Signs are different.
+        *--------------------------------------------------------------------*/
+        return signA && ((uiA0 | uiB0) != 0);
+    } else {
+        /*--------------------------------------------------------------------
+        | Signs are the same.
+        *--------------------------------------------------------------------*/
+        if ( ! ((uiA0 & uiB0) & UINT64_C( 0x8000000000000000 )) ) {
+            return (softfloat_compareNonnormExtF80M( aSPtr, bSPtr ) < 0);
+        }
+        if ( uiA64 == uiB64 ) {
+            if ( uiA0 == uiB0 ) return false;
+            ltMags = (uiA0 < uiB0);
+        } else {
+            ltMags = (uiA64 < uiB64);
+        }
+        return signA ^ ltMags;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_mul.c b/addins/SoftFloat-3e/source/extF80M_mul.c
new file mode 100644
index 000000000..281394f71
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_mul.c
@@ -0,0 +1,139 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_mul(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *zPtr = extF80_mul( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ extF80M_mul(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiA64;
+    int32_t expA;
+    uint_fast16_t uiB64;
+    int32_t expB;
+    bool signZ;
+    uint_fast16_t exp, uiZ64;
+    uint64_t uiZ0, sigA, sigB;
+    int32_t expZ;
+    uint32_t sigProd[4], *extSigZPtr;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    expA = expExtF80UI64( uiA64 );
+    uiB64 = bSPtr->signExp;
+    expB = expExtF80UI64( uiB64 );
+    signZ = signExtF80UI64( uiA64 ) ^ signExtF80UI64( uiB64 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return;
+        if (
+               (! aSPtr->signif && (expA != 0x7FFF))
+            || (! bSPtr->signif && (expB != 0x7FFF))
+        ) {
+            softfloat_invalidExtF80M( zSPtr );
+            return;
+        }
+        uiZ64 = packToExtF80UI64( signZ, 0x7FFF );
+        uiZ0  = UINT64_C( 0x8000000000000000 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) expA = 1;
+    sigA = aSPtr->signif;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) goto zero;
+        expA += softfloat_normExtF80SigM( &sigA );
+    }
+    if ( ! expB ) expB = 1;
+    sigB = bSPtr->signif;
+    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigB ) goto zero;
+        expB += softfloat_normExtF80SigM( &sigB );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FFE;
+    softfloat_mul64To128M( sigA, sigB, sigProd );
+    if ( sigProd[indexWordLo( 4 )] ) sigProd[indexWord( 4, 1 )] |= 1;
+    extSigZPtr = &sigProd[indexMultiwordHi( 4, 3 )];
+    if ( sigProd[indexWordHi( 4 )] < 0x80000000 ) {
+        --expZ;
+        softfloat_add96M( extSigZPtr, extSigZPtr, extSigZPtr );
+    }
+    softfloat_roundPackMToExtF80M(
+        signZ, expZ, extSigZPtr, extF80_roundingPrecision, zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ64 = packToExtF80UI64( signZ, 0 );
+    uiZ0  = 0;
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_rem.c b/addins/SoftFloat-3e/source/extF80M_rem.c
new file mode 100644
index 000000000..4aff18ae9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_rem.c
@@ -0,0 +1,204 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_rem(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *zPtr = extF80_rem( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ extF80M_rem(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiA64;
+    int32_t expA, expB;
+    uint64_t x64;
+    bool signRem;
+    uint64_t sigA;
+    int32_t expDiff;
+    uint32_t rem[3], x[3], sig32B, q, recip32, rem2[3], *remPtr, *altRemPtr;
+    uint32_t *newRemPtr, wordMeanRem;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    expA = expExtF80UI64( uiA64 );
+    expB = expExtF80UI64( bSPtr->signExp );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return;
+        if ( expA == 0x7FFF ) goto invalid;
+        /*--------------------------------------------------------------------
+        | If we get here, then argument b is an infinity and `expB' is 0x7FFF;
+        | Doubling `expB' is an easy way to ensure that `expDiff' later is
+        | less than -1, which will result in returning a canonicalized version
+        | of argument a.
+        *--------------------------------------------------------------------*/
+        expB += expB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) expB = 1;
+    x64 = bSPtr->signif;
+    if ( ! (x64 & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! x64 ) goto invalid;
+        expB += softfloat_normExtF80SigM( &x64 );
+    }
+    signRem = signExtF80UI64( uiA64 );
+    if ( ! expA ) expA = 1;
+    sigA = aSPtr->signif;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) {
+            expA = 0;
+            goto copyA;
+        }
+        expA += softfloat_normExtF80SigM( &sigA );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( expDiff < -1 ) goto copyA;
+    rem[indexWord( 3, 2 )] = sigA>>34;
+    rem[indexWord( 3, 1 )] = sigA>>2;
+    rem[indexWord( 3, 0 )] = (uint32_t) sigA<<30;
+    x[indexWord( 3, 0 )] = (uint32_t) x64<<30;
+    sig32B = x64>>32;
+    x64 >>= 2;
+    x[indexWord( 3, 2 )] = x64>>32;
+    x[indexWord( 3, 1 )] = x64;
+    if ( expDiff < 1 ) {
+        if ( expDiff ) {
+            --expB;
+            softfloat_add96M( x, x, x );
+            q = 0;
+        } else {
+            q = (softfloat_compare96M( x, rem ) <= 0);
+            if ( q ) softfloat_sub96M( rem, x, rem );
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( sig32B );
+        expDiff -= 30;
+        for (;;) {
+            x64 = (uint64_t) rem[indexWordHi( 3 )] * recip32;
+            if ( expDiff < 0 ) break;
+            q = (x64 + 0x80000000)>>32;
+            softfloat_remStep96MBy32( rem, 29, x, q, rem );
+            if ( rem[indexWordHi( 3 )] & 0x80000000 ) {
+                softfloat_add96M( rem, x, rem );
+            }
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -29 here.)
+        *--------------------------------------------------------------------*/
+        q = (uint32_t) (x64>>32)>>(~expDiff & 31);
+        softfloat_remStep96MBy32( rem, expDiff + 30, x, q, rem );
+        if ( rem[indexWordHi( 3 )] & 0x80000000 ) {
+            remPtr = rem;
+            altRemPtr = rem2;
+            softfloat_add96M( remPtr, x, altRemPtr );
+            goto selectRem;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    remPtr = rem;
+    altRemPtr = rem2;
+    do {
+        ++q;
+        newRemPtr = altRemPtr;
+        softfloat_sub96M( remPtr, x, newRemPtr );
+        altRemPtr = remPtr;
+        remPtr = newRemPtr;
+    } while ( ! (remPtr[indexWordHi( 3 )] & 0x80000000) );
+ selectRem:
+    softfloat_add96M( remPtr, altRemPtr, x );
+    wordMeanRem = x[indexWordHi( 3 )];
+    if (
+        (wordMeanRem & 0x80000000)
+            || (! wordMeanRem && (q & 1) && ! x[indexWord( 3, 0 )]
+                    && ! x[indexWord( 3, 1 )])
+    ) {
+        remPtr = altRemPtr;
+    }
+    if ( remPtr[indexWordHi( 3 )] & 0x80000000 ) {
+        signRem = ! signRem;
+        softfloat_negX96M( remPtr );
+    }
+    softfloat_normRoundPackMToExtF80M( signRem, expB + 2, remPtr, 80, zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidExtF80M( zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ copyA:
+    if ( expA < 1 ) {
+        sigA >>= 1 - expA;
+        expA = 0;
+    }
+    zSPtr->signExp = packToExtF80UI64( signRem, expA );
+    zSPtr->signif = sigA;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_roundToInt.c b/addins/SoftFloat-3e/source/extF80M_roundToInt.c
new file mode 100644
index 000000000..2e8572957
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_roundToInt.c
@@ -0,0 +1,176 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_roundToInt(
+     const extFloat80_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     extFloat80_t *zPtr
+ )
+{
+
+    *zPtr = extF80_roundToInt( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+void
+ extF80M_roundToInt(
+     const extFloat80_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     extFloat80_t *zPtr
+ )
+{
+    const struct extFloat80M *aSPtr;
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiA64, signUI64;
+    int32_t exp;
+    uint64_t sigA;
+    uint_fast16_t uiZ64;
+    uint64_t sigZ, lastBitMask, roundBitsMask;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    signUI64 = uiA64 & packToExtF80UI64( 1, 0 );
+    exp = expExtF80UI64( uiA64 );
+    sigA = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( !(sigA & UINT64_C( 0x8000000000000000 )) && (exp != 0x7FFF) ) {
+        if ( !sigA ) {
+            uiZ64 = signUI64;
+            sigZ = 0;
+            goto uiZ;
+        }
+        exp += softfloat_normExtF80SigM( &sigA );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp <= 0x3FFE ) {
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0x3FFE ) goto mag1;
+            break;
+         case softfloat_round_min:
+            if ( signUI64 ) goto mag1;
+            break;
+         case softfloat_round_max:
+            if ( !signUI64 ) goto mag1;
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            goto mag1;
+#endif
+        }
+        uiZ64 = signUI64;
+        sigZ = 0;
+        goto uiZ;
+     mag1:
+        uiZ64 = signUI64 | 0x3FFF;
+        sigZ = UINT64_C( 0x8000000000000000 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x403E <= exp ) {
+        if ( exp == 0x7FFF ) {
+            if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+                softfloat_propagateNaNExtF80M( aSPtr, 0, zSPtr );
+                return;
+            }
+            sigZ = UINT64_C( 0x8000000000000000 );
+        } else {
+            sigZ = sigA;
+        }
+        uiZ64 = signUI64 | exp;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = signUI64 | exp;
+    lastBitMask = (uint64_t) 1<<(0x403E - exp);
+    roundBitsMask = lastBitMask - 1;
+    sigZ = sigA;
+    if ( roundingMode == softfloat_round_near_maxMag ) {
+        sigZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_near_even ) {
+        sigZ += lastBitMask>>1;
+        if ( !(sigZ & roundBitsMask) ) sigZ &= ~lastBitMask;
+    } else if (
+        roundingMode == (signUI64 ? softfloat_round_min : softfloat_round_max)
+    ) {
+        sigZ += roundBitsMask;
+    }
+    sigZ &= ~roundBitsMask;
+    if ( !sigZ ) {
+        ++uiZ64;
+        sigZ = UINT64_C( 0x8000000000000000 );
+    }
+    if ( sigZ != sigA ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = sigZ;
+    return;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_sqrt.c b/addins/SoftFloat-3e/source/extF80M_sqrt.c
new file mode 100644
index 000000000..7ee91e0e5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_sqrt.c
@@ -0,0 +1,180 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void extF80M_sqrt( const extFloat80_t *aPtr, extFloat80_t *zPtr )
+{
+
+    *zPtr = extF80_sqrt( *aPtr );
+
+}
+
+#else
+
+void extF80M_sqrt( const extFloat80_t *aPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr;
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiA64, signUI64;
+    int32_t expA;
+    uint64_t rem64;
+    int32_t expZ;
+    uint32_t rem96[3], sig32A, recipSqrt32, sig32Z, q;
+    uint64_t sig64Z, x64;
+    uint32_t rem32, term[4], rem[4], extSigZ[3];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    signUI64 = uiA64 & packToExtF80UI64( 1, 0 );
+    expA = expExtF80UI64( uiA64 );
+    rem64 = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if ( rem64 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_propagateNaNExtF80M( aSPtr, 0, zSPtr );
+            return;
+        }
+        if ( signUI64 ) goto invalid;
+        rem64 = UINT64_C( 0x8000000000000000 );
+        goto copyA;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) expA = 1;
+    if ( ! (rem64 & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! rem64 ) {
+            uiA64 = signUI64;
+            goto copyA;
+        }
+        expA += softfloat_normExtF80SigM( &rem64 );
+    }
+    if ( signUI64 ) goto invalid;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x3FFF)>>1) + 0x3FFF;
+    expA &= 1;
+    softfloat_shortShiftLeft64To96M( rem64, 30 - expA, rem96 );
+    sig32A = rem64>>32;
+    recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A );
+    sig32Z = ((uint64_t) sig32A * recipSqrt32)>>32;
+    if ( expA ) sig32Z >>= 1;
+    rem64 =
+        ((uint64_t) rem96[indexWord( 3, 2 )]<<32 | rem96[indexWord( 3, 1 )])
+            - (uint64_t) sig32Z * sig32Z;
+    rem96[indexWord( 3, 2 )] = rem64>>32;
+    rem96[indexWord( 3, 1 )] = rem64;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32;
+    sig64Z = ((uint64_t) sig32Z<<32) + ((uint64_t) q<<3);
+    term[indexWord( 3, 2 )] = 0;
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        x64 = ((uint64_t) sig32Z<<32) + sig64Z;
+        term[indexWord( 3, 1 )] = x64>>32;
+        term[indexWord( 3, 0 )] = x64;
+        softfloat_remStep96MBy32(
+            rem96, 29, term, q, &rem[indexMultiwordHi( 4, 3 )] );
+        rem32 = rem[indexWord( 4, 3 )];
+        if ( ! (rem32 & 0x80000000) ) break;
+        --q;
+        sig64Z -= 1<<3;
+    }
+    rem64 = (uint64_t) rem32<<32 | rem[indexWord( 4, 2 )];
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = (((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32) + 2;
+    if ( rem64>>34 ) q += recipSqrt32;
+    x64 = (uint64_t) q<<7;
+    extSigZ[indexWord( 3, 0 )] = x64;
+    x64 = (sig64Z<<1) + (x64>>32);
+    extSigZ[indexWord( 3, 2 )] = x64>>32;
+    extSigZ[indexWord( 3, 1 )] = x64;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (q & 0xFFFFFF) <= 2 ) {
+        q &= ~(uint32_t) 0xFFFF;
+        extSigZ[indexWordLo( 3 )] = q<<7;
+        x64 = sig64Z + (q>>27);
+        term[indexWord( 4, 3 )] = 0;
+        term[indexWord( 4, 2 )] = x64>>32;
+        term[indexWord( 4, 1 )] = x64;
+        term[indexWord( 4, 0 )] = q<<5;
+        rem[indexWord( 4, 0 )] = 0;
+        softfloat_remStep128MBy32( rem, 28, term, q, rem );
+        q = rem[indexWordHi( 4 )];
+        if ( q & 0x80000000 ) {
+            softfloat_sub1X96M( extSigZ );
+        } else {
+            if ( q || rem[indexWord( 4, 1 )] || rem[indexWord( 4, 2 )] ) {
+                extSigZ[indexWordLo( 3 )] |= 1;
+            }
+        }
+    }
+    softfloat_roundPackMToExtF80M(
+        0, expZ, extSigZ, extF80_roundingPrecision, zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidExtF80M( zSPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ copyA:
+    zSPtr->signExp = uiA64;
+    zSPtr->signif  = rem64;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_sub.c b/addins/SoftFloat-3e/source/extF80M_sub.c
new file mode 100644
index 000000000..5d1895c7a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_sub.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ extF80M_sub(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    const struct extFloat80M *aSPtr, *bSPtr;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    extFloat80_t
+        (*magsFuncPtr)(
+            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+#endif
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    bSPtr = (const struct extFloat80M *) bPtr;
+    uiA64 = aSPtr->signExp;
+    uiA0  = aSPtr->signif;
+    signA = signExtF80UI64( uiA64 );
+    uiB64 = bSPtr->signExp;
+    uiB0  = bSPtr->signif;
+    signB = signExtF80UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        *zPtr = softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        *zPtr = softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80;
+    *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
+#else
+
+void
+ extF80M_sub(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    softfloat_addExtF80M(
+        (const struct extFloat80M *) aPtr,
+        (const struct extFloat80M *) bPtr,
+        (struct extFloat80M *) zPtr,
+        true
+    );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_f128M.c b/addins/SoftFloat-3e/source/extF80M_to_f128M.c
new file mode 100644
index 000000000..da81e8d6b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_f128M.c
@@ -0,0 +1,125 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *zPtr )
+{
+
+    *zPtr = extF80_to_f128( *aPtr );
+
+}
+
+#else
+
+void extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *zPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint32_t *zWPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    struct commonNaN commonNaN;
+    uint32_t uiZ96;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr[indexWord( 4, 0 )] = 0;
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80MToCommonNaN( aSPtr, &commonNaN );
+            softfloat_commonNaNToF128M( &commonNaN, zWPtr );
+            return;
+        }
+        uiZ96 = packToF128UI96( sign, 0x7FFF, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) --exp;
+    if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sig ) {
+            uiZ96 = packToF128UI96( sign, 0, 0 );
+            goto uiZ;
+        }
+        exp += softfloat_normExtF80SigM( &sig );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr[indexWord( 4, 1 )] = (uint32_t) sig<<17;
+    sig >>= 15;
+    zWPtr[indexWord( 4, 2 )] = sig;
+    if ( exp < 0 ) {
+        zWPtr[indexWordHi( 4 )] = sig>>32;
+        softfloat_shiftRight96M(
+            &zWPtr[indexMultiwordHi( 4, 3 )],
+            -exp,
+            &zWPtr[indexMultiwordHi( 4, 3 )]
+        );
+        exp = 0;
+        sig = (uint64_t) zWPtr[indexWordHi( 4 )]<<32;
+    }
+    zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp, sig>>32 );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_f16.c b/addins/SoftFloat-3e/source/extF80M_to_f16.c
new file mode 100644
index 000000000..5ae38d0c4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_f16.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float16_t extF80M_to_f16( const extFloat80_t *aPtr )
+{
+
+    return extF80_to_f16( *aPtr );
+
+}
+
+#else
+
+float16_t extF80M_to_f16( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    struct commonNaN commonNaN;
+    uint16_t uiZ, sig16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80MToCommonNaN( aSPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sig ) {
+            uiZ = packToF16UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        exp += softfloat_normExtF80SigM( &sig );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig16 = softfloat_shortShiftRightJam64( sig, 49 );
+    exp -= 0x3FF1;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x40 ) exp = -0x40;
+    }
+    return softfloat_roundPackToF16( sign, exp, sig16 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_f32.c b/addins/SoftFloat-3e/source/extF80M_to_f32.c
new file mode 100644
index 000000000..47cf224dc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_f32.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float32_t extF80M_to_f32( const extFloat80_t *aPtr )
+{
+
+    return extF80_to_f32( *aPtr );
+
+}
+
+#else
+
+float32_t extF80M_to_f32( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    struct commonNaN commonNaN;
+    uint32_t uiZ, sig32;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80MToCommonNaN( aSPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sig ) {
+            uiZ = packToF32UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        exp += softfloat_normExtF80SigM( &sig );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = softfloat_shortShiftRightJam64( sig, 33 );
+    exp -= 0x3F81;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF32( sign, exp, sig32 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_f64.c b/addins/SoftFloat-3e/source/extF80M_to_f64.c
new file mode 100644
index 000000000..5f8f4aa29
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_f64.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float64_t extF80M_to_f64( const extFloat80_t *aPtr )
+{
+
+    return extF80_to_f64( *aPtr );
+
+}
+
+#else
+
+float64_t extF80M_to_f64( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    struct commonNaN commonNaN;
+    uint64_t uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80MToCommonNaN( aSPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! (sig & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sig ) {
+            uiZ = packToF64UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        exp += softfloat_normExtF80SigM( &sig );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = softfloat_shortShiftRightJam64( sig, 1 );
+    exp -= 0x3C01;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF64( sign, exp, sig );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_i32.c b/addins/SoftFloat-3e/source/extF80M_to_i32.c
new file mode 100644
index 000000000..06394e341
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_i32.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast32_t
+ extF80M_to_i32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return extF80_to_i32( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+int_fast32_t
+ extF80M_to_i32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x4032 - exp;
+    if ( shiftDist <= 0 ) {
+        if ( sig>>32 ) goto invalid;
+        if ( -32 < shiftDist ) {
+            sig <<= -shiftDist;
+        } else {
+            if ( (uint32_t) sig ) goto invalid;
+        }
+    } else {
+        sig = softfloat_shiftRightJam64( sig, shiftDist );
+    }
+    return softfloat_roundToI32( sign, sig, roundingMode, exact );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ? i32_fromNaN
+            : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/extF80M_to_i32_r_minMag.c
new file mode 100644
index 000000000..5f5cf599d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_i32_r_minMag.c
@@ -0,0 +1,120 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+
+    return extF80_to_i32_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    bool sign, raiseInexact;
+    int32_t z;
+    uint64_t shiftedSig;
+    uint32_t absZ;
+    union { uint32_t ui; int32_t i; } u;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! sig && (exp != 0x7FFF) ) return 0;
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        raiseInexact = exact;
+        z = 0;
+    } else {
+        sign = signExtF80UI64( uiA64 );
+        raiseInexact = false;
+        if ( shiftDist < 0 ) {
+            if ( sig>>32 || (shiftDist <= -31) ) goto invalid;
+            shiftedSig = (uint64_t) (uint32_t) sig<<-shiftDist;
+            if ( shiftedSig>>32 ) goto invalid;
+            absZ = shiftedSig;
+        } else {
+            shiftedSig = sig;
+            if ( shiftDist ) shiftedSig >>= shiftDist;
+            if ( shiftedSig>>32 ) goto invalid;
+            absZ = shiftedSig;
+            if ( exact && shiftDist ) {
+                raiseInexact = ((uint64_t) absZ<<shiftDist != sig);
+            }
+        }
+        if ( sign ) {
+            if ( 0x80000000 < absZ ) goto invalid;
+            u.ui = -absZ;
+            z = u.i;
+        } else {
+            if ( 0x80000000 <= absZ ) goto invalid;
+            z = absZ;
+        }
+    }
+    if ( raiseInexact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ? i32_fromNaN
+            : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_i64.c b/addins/SoftFloat-3e/source/extF80M_to_i64.c
new file mode 100644
index 000000000..1b751dc8e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_i64.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast64_t
+ extF80M_to_i64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return extF80_to_i64( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+int_fast64_t
+ extF80M_to_i64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    uint32_t extSig[3];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist < 0 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    extSig[indexWord( 3, 2 )] = sig>>32;
+    extSig[indexWord( 3, 1 )] = sig;
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    return softfloat_roundMToI64( sign, extSig, roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/extF80M_to_i64_r_minMag.c
new file mode 100644
index 000000000..ec9b92844
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_i64_r_minMag.c
@@ -0,0 +1,115 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+
+    return extF80_to_i64_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    bool sign, raiseInexact;
+    int64_t z;
+    uint64_t absZ;
+    union { uint64_t ui; int64_t i; } u;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! sig && (exp != 0x7FFF) ) return 0;
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        raiseInexact = exact;
+        z = 0;
+    } else {
+        sign = signExtF80UI64( uiA64 );
+        raiseInexact = false;
+        if ( shiftDist < 0 ) {
+            if ( shiftDist <= -63 ) goto invalid;
+            shiftDist = -shiftDist;
+            absZ = sig<<shiftDist;
+            if ( absZ>>shiftDist != sig ) goto invalid;
+        } else {
+            absZ = sig;
+            if ( shiftDist ) absZ >>= shiftDist;
+            if ( exact && shiftDist ) raiseInexact = (absZ<<shiftDist != sig);
+        }
+        if ( sign ) {
+            if ( UINT64_C( 0x8000000000000000 ) < absZ ) goto invalid;
+            u.ui = -absZ;
+            z = u.i;
+        } else {
+            if ( UINT64_C( 0x8000000000000000 ) <= absZ ) goto invalid;
+            z = absZ;
+        }
+    }
+    if ( raiseInexact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ? i64_fromNaN
+            : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_ui32.c b/addins/SoftFloat-3e/source/extF80M_to_ui32.c
new file mode 100644
index 000000000..983a1ee34
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_ui32.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast32_t
+ extF80M_to_ui32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return extF80_to_ui32( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+uint_fast32_t
+ extF80M_to_ui32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x4032 - exp;
+    if ( shiftDist <= 0 ) {
+        if ( sig>>32 ) goto invalid;
+        if ( -32 < shiftDist ) {
+            sig <<= -shiftDist;
+        } else {
+            if ( (uint32_t) sig ) goto invalid;
+        }
+    } else {
+        sig = softfloat_shiftRightJam64( sig, shiftDist );
+    }
+    return softfloat_roundToUI32( sign, sig, roundingMode, exact );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            ? ui32_fromNaN
+            : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/extF80M_to_ui32_r_minMag.c
new file mode 100644
index 000000000..e28b08d70
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_ui32_r_minMag.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+
+    return extF80_to_ui32_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    bool sign;
+    uint64_t shiftedSig;
+    uint32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! sig && (exp != 0x7FFF) ) return 0;
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( shiftDist < 0 ) {
+        if ( sign || sig>>32 || (shiftDist <= -31) ) goto invalid;
+        shiftedSig = (uint64_t) (uint32_t) sig<<-shiftDist;
+        if ( shiftedSig>>32 ) goto invalid;
+        z = shiftedSig;
+    } else {
+        shiftedSig = sig;
+        if ( shiftDist ) shiftedSig >>= shiftDist;
+        if ( shiftedSig>>32 ) goto invalid;
+        z = shiftedSig;
+        if ( sign && z ) goto invalid;
+        if ( exact && shiftDist && ((uint64_t) z<<shiftDist != sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            ? ui32_fromNaN
+            : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_ui64.c b/addins/SoftFloat-3e/source/extF80M_to_ui64.c
new file mode 100644
index 000000000..9d4ef4a52
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_ui64.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast64_t
+ extF80M_to_ui64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return extF80_to_ui64( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+uint_fast64_t
+ extF80M_to_ui64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    bool sign;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    uint32_t extSig[3];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist < 0 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    extSig[indexWord( 3, 2 )] = sig>>32;
+    extSig[indexWord( 3, 1 )] = sig;
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    return softfloat_roundMToUI64( sign, extSig, roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80M_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/extF80M_to_ui64_r_minMag.c
new file mode 100644
index 000000000..87d80897b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80M_to_ui64_r_minMag.c
@@ -0,0 +1,108 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+
+    return extF80_to_ui64_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    int32_t exp;
+    uint64_t sig;
+    int32_t shiftDist;
+    bool sign;
+    uint64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = aSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! sig && (exp != 0x7FFF) ) return 0;
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( shiftDist < 0 ) {
+        if ( sign || (shiftDist <= -63) ) goto invalid;
+        shiftDist = -shiftDist;
+        z = sig<<shiftDist;
+        if ( z>>shiftDist != sig ) goto invalid;
+    } else {
+        z = sig;
+        if ( shiftDist ) z >>= shiftDist;
+        if ( sign && z ) goto invalid;
+        if ( exact && shiftDist && (z<<shiftDist != sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            ? ui64_fromNaN
+            : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/extF80_add.c b/addins/SoftFloat-3e/source/extF80_add.c
new file mode 100644
index 000000000..164cb05de
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_add.c
@@ -0,0 +1,80 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_add( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    extFloat80_t
+        (*magsFuncPtr)(
+            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    signB = signExtF80UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_addMagsExtF80 : softfloat_subMagsExtF80;
+    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_div.c b/addins/SoftFloat-3e/source/extF80_div.c
new file mode 100644
index 000000000..28dfb13de
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_div.c
@@ -0,0 +1,203 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_div( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+    int_fast32_t expB;
+    uint_fast64_t sigB;
+    bool signZ;
+    struct exp32_sig64 normExpSig;
+    int_fast32_t expZ;
+    struct uint128 rem;
+    uint_fast32_t recip32;
+    uint_fast64_t sigZ;
+    int ix;
+    uint_fast64_t q64;
+    uint_fast32_t q;
+    struct uint128 term;
+    uint_fast64_t sigZExtra;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    expA  = expExtF80UI64( uiA64 );
+    sigA  = uiA0;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    signB = signExtF80UI64( uiB64 );
+    expB  = expExtF80UI64( uiB64 );
+    sigB  = uiB0;
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        if ( expB == 0x7FFF ) {
+            if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) expB = 1;
+    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigB ) {
+            if ( ! sigA ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigB );
+        expB += normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigA );
+        expA += normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x3FFF;
+    if ( sigA < sigB ) {
+        --expZ;
+        rem = softfloat_shortShiftLeft128( 0, sigA, 32 );
+    } else {
+        rem = softfloat_shortShiftLeft128( 0, sigA, 31 );
+    }
+    recip32 = softfloat_approxRecip32_1( sigB>>32 );
+    sigZ = 0;
+    ix = 2;
+    for (;;) {
+        q64 = (uint_fast64_t) (uint32_t) (rem.v64>>2) * recip32;
+        q = (q64 + 0x80000000)>>32;
+        --ix;
+        if ( ix < 0 ) break;
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+        term = softfloat_mul64ByShifted32To128( sigB, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            --q;
+            rem = softfloat_add128( rem.v64, rem.v0, sigB>>32, sigB<<32 );
+        }
+        sigZ = (sigZ<<29) + q;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ((q + 1) & 0x3FFFFF) < 2 ) {
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+        term = softfloat_mul64ByShifted32To128( sigB, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        term = softfloat_shortShiftLeft128( 0, sigB, 32 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            --q;
+            rem = softfloat_add128( rem.v64, rem.v0, term.v64, term.v0 );
+        } else if ( softfloat_le128( term.v64, term.v0, rem.v64, rem.v0 ) ) {
+            ++q;
+            rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        }
+        if ( rem.v64 | rem.v0 ) q |= 1;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigZ = (sigZ<<6) + (q>>23);
+    sigZExtra = (uint64_t) ((uint_fast64_t) q<<41);
+    return
+        softfloat_roundPackToExtF80(
+            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ64 = uiZ.v64;
+    uiZ0  = uiZ.v0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ64 = defaultNaNExtF80UI64;
+    uiZ0  = defaultNaNExtF80UI0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ64 = packToExtF80UI64( signZ, 0x7FFF );
+    uiZ0  = UINT64_C( 0x8000000000000000 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ64 = packToExtF80UI64( signZ, 0 );
+    uiZ0  = 0;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_eq.c b/addins/SoftFloat-3e/source/extF80_eq.c
new file mode 100644
index 000000000..efcbc3714
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_eq.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_eq( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return
+           (uiA0 == uiB0)
+        && ((uiA64 == uiB64) || (! uiA0 && ! ((uiA64 | uiB64) & 0x7FFF)));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_eq_signaling.c b/addins/SoftFloat-3e/source/extF80_eq_signaling.c
new file mode 100644
index 000000000..193b191e6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_eq_signaling.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool extF80_eq_signaling( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return
+           (uiA0 == uiB0)
+        && ((uiA64 == uiB64) || (! uiA0 && ! ((uiA64 | uiB64) & 0x7FFF)));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_isSignalingNaN.c b/addins/SoftFloat-3e/source/extF80_isSignalingNaN.c
new file mode 100644
index 000000000..33d2abd7e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_isSignalingNaN.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_isSignalingNaN( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNExtF80UI( uA.s.signExp, uA.s.signif );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_le.c b/addins/SoftFloat-3e/source/extF80_le.c
new file mode 100644
index 000000000..4e23c5142
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_le.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_le( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signExtF80UI64( uiA64 );
+    signB = signExtF80UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA || ! (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0)
+            : ((uiA64 == uiB64) && (uiA0 == uiB0))
+                  || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_le_quiet.c b/addins/SoftFloat-3e/source/extF80_le_quiet.c
new file mode 100644
index 000000000..9839e47f9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_le_quiet.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_le_quiet( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signExtF80UI64( uiA64 );
+    signB = signExtF80UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA || ! (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0)
+            : ((uiA64 == uiB64) && (uiA0 == uiB0))
+                  || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_lt.c b/addins/SoftFloat-3e/source/extF80_lt.c
new file mode 100644
index 000000000..a4ac69fa6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_lt.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_lt( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signExtF80UI64( uiA64 );
+    signB = signExtF80UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA && (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0)
+            : ((uiA64 != uiB64) || (uiA0 != uiB0))
+                  && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_lt_quiet.c b/addins/SoftFloat-3e/source/extF80_lt_quiet.c
new file mode 100644
index 000000000..00f4d4768
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_lt_quiet.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool extF80_lt_quiet( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    if ( isNaNExtF80UI( uiA64, uiA0 ) || isNaNExtF80UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNExtF80UI( uiA64, uiA0 )
+            || softfloat_isSigNaNExtF80UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signExtF80UI64( uiA64 );
+    signB = signExtF80UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA && (((uiA64 | uiB64) & 0x7FFF) | uiA0 | uiB0)
+            : ((uiA64 != uiB64) || (uiA0 != uiB0))
+                  && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_mul.c b/addins/SoftFloat-3e/source/extF80_mul.c
new file mode 100644
index 000000000..39ce4012c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_mul.c
@@ -0,0 +1,158 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_mul( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+    int_fast32_t expB;
+    uint_fast64_t sigB;
+    bool signZ;
+    uint_fast64_t magBits;
+    struct exp32_sig64 normExpSig;
+    int_fast32_t expZ;
+    struct uint128 sig128Z, uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    expA  = expExtF80UI64( uiA64 );
+    sigA  = uiA0;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    signB = signExtF80UI64( uiB64 );
+    expB  = expExtF80UI64( uiB64 );
+    sigB  = uiB0;
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if (
+               (sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            || ((expB == 0x7FFF) && (sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+        ) {
+            goto propagateNaN;
+        }
+        magBits = expB | sigB;
+        goto infArg;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        magBits = expA | sigA;
+        goto infArg;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigA );
+        expA += normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) expB = 1;
+    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigB ) goto zero;
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigB );
+        expB += normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FFE;
+    sig128Z = softfloat_mul64To128( sigA, sigB );
+    if ( sig128Z.v64 < UINT64_C( 0x8000000000000000 ) ) {
+        --expZ;
+        sig128Z =
+            softfloat_add128(
+                sig128Z.v64, sig128Z.v0, sig128Z.v64, sig128Z.v0 );
+    }
+    return
+        softfloat_roundPackToExtF80(
+            signZ, expZ, sig128Z.v64, sig128Z.v0, extF80_roundingPrecision );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ64 = uiZ.v64;
+    uiZ0  = uiZ.v0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infArg:
+    if ( ! magBits ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ64 = defaultNaNExtF80UI64;
+        uiZ0  = defaultNaNExtF80UI0;
+    } else {
+        uiZ64 = packToExtF80UI64( signZ, 0x7FFF );
+        uiZ0  = UINT64_C( 0x8000000000000000 );
+    }
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ64 = packToExtF80UI64( signZ, 0 );
+    uiZ0  = 0;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_rem.c b/addins/SoftFloat-3e/source/extF80_rem.c
new file mode 100644
index 000000000..5ad977526
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_rem.c
@@ -0,0 +1,225 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_rem( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    int_fast32_t expB;
+    uint_fast64_t sigB;
+    struct exp32_sig64 normExpSig;
+    int_fast32_t expDiff;
+    struct uint128 rem, shiftedSigB;
+    uint_fast32_t q, recip32;
+    uint_fast64_t q64;
+    struct uint128 term, altRem, meanRem;
+    bool signRem;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    expA  = expExtF80UI64( uiA64 );
+    sigA  = uiA0;
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    expB  = expExtF80UI64( uiB64 );
+    sigB  = uiB0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if (
+               (sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            || ((expB == 0x7FFF) && (sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+        ) {
+            goto propagateNaN;
+        }
+        goto invalid;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        /*--------------------------------------------------------------------
+        | Argument b is an infinity.  Doubling `expB' is an easy way to ensure
+        | that `expDiff' later is less than -1, which will result in returning
+        | a canonicalized version of argument a.
+        *--------------------------------------------------------------------*/
+        expB += expB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) expB = 1;
+    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigB );
+        expB += normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) {
+            expA = 0;
+            goto copyA;
+        }
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigA );
+        expA += normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( expDiff < -1 ) goto copyA;
+    rem = softfloat_shortShiftLeft128( 0, sigA, 32 );
+    shiftedSigB = softfloat_shortShiftLeft128( 0, sigB, 32 );
+    if ( expDiff < 1 ) {
+        if ( expDiff ) {
+            --expB;
+            shiftedSigB = softfloat_shortShiftLeft128( 0, sigB, 33 );
+            q = 0;
+        } else {
+            q = (sigB <= sigA);
+            if ( q ) {
+                rem =
+                    softfloat_sub128(
+                        rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 );
+            }
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( sigB>>32 );
+        expDiff -= 30;
+        for (;;) {
+            q64 = (uint_fast64_t) (uint32_t) (rem.v64>>2) * recip32;
+            if ( expDiff < 0 ) break;
+            q = (q64 + 0x80000000)>>32;
+            rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+            term = softfloat_mul64ByShifted32To128( sigB, q );
+            rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+            if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+                rem =
+                    softfloat_add128(
+                        rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 );
+            }
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -29 here.)
+        *--------------------------------------------------------------------*/
+        q = (uint32_t) (q64>>32)>>(~expDiff & 31);
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, expDiff + 30 );
+        term = softfloat_mul64ByShifted32To128( sigB, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            altRem =
+                softfloat_add128(
+                    rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 );
+            goto selectRem;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    do {
+        altRem = rem;
+        ++q;
+        rem =
+            softfloat_sub128(
+                rem.v64, rem.v0, shiftedSigB.v64, shiftedSigB.v0 );
+    } while ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) );
+ selectRem:
+    meanRem = softfloat_add128( rem.v64, rem.v0, altRem.v64, altRem.v0 );
+    if (
+        (meanRem.v64 & UINT64_C( 0x8000000000000000 ))
+            || (! (meanRem.v64 | meanRem.v0) && (q & 1))
+    ) {
+        rem = altRem;
+    }
+    signRem = signA;
+    if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+        signRem = ! signRem;
+        rem = softfloat_sub128( 0, 0, rem.v64, rem.v0 );
+    }
+    return
+        softfloat_normRoundPackToExtF80(
+            signRem, rem.v64 | rem.v0 ? expB + 32 : 0, rem.v64, rem.v0, 80 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ64 = uiZ.v64;
+    uiZ0  = uiZ.v0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ64 = defaultNaNExtF80UI64;
+    uiZ0  = defaultNaNExtF80UI0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ copyA:
+    if ( expA < 1 ) {
+        sigA >>= 1 - expA;
+        expA = 0;
+    }
+    uiZ64 = packToExtF80UI64( signA, expA );
+    uiZ0  = sigA;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_roundToInt.c b/addins/SoftFloat-3e/source/extF80_roundToInt.c
new file mode 100644
index 000000000..6c12d84c9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_roundToInt.c
@@ -0,0 +1,154 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t
+ extF80_roundToInt( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64, signUI64;
+    int_fast32_t exp;
+    uint_fast64_t sigA;
+    uint_fast16_t uiZ64;
+    uint_fast64_t sigZ;
+    struct exp32_sig64 normExpSig;
+    struct uint128 uiZ;
+    uint_fast64_t lastBitMask, roundBitsMask;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    signUI64 = uiA64 & packToExtF80UI64( 1, 0 );
+    exp = expExtF80UI64( uiA64 );
+    sigA = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( !(sigA & UINT64_C( 0x8000000000000000 )) && (exp != 0x7FFF) ) {
+        if ( !sigA ) {
+            uiZ64 = signUI64;
+            sigZ = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigA );
+        exp += normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x403E <= exp ) {
+        if ( exp == 0x7FFF ) {
+            if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+                uiZ = softfloat_propagateNaNExtF80UI( uiA64, sigA, 0, 0 );
+                uiZ64 = uiZ.v64;
+                sigZ  = uiZ.v0;
+                goto uiZ;
+            }
+            sigZ = UINT64_C( 0x8000000000000000 );
+        } else {
+            sigZ = sigA;
+        }
+        uiZ64 = signUI64 | exp;
+        goto uiZ;
+    }
+    if ( exp <= 0x3FFE ) {
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !(sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0x3FFE ) goto mag1;
+            break;
+         case softfloat_round_min:
+            if ( signUI64 ) goto mag1;
+            break;
+         case softfloat_round_max:
+            if ( !signUI64 ) goto mag1;
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            goto mag1;
+#endif
+        }
+        uiZ64 = signUI64;
+        sigZ  = 0;
+        goto uiZ;
+     mag1:
+        uiZ64 = signUI64 | 0x3FFF;
+        sigZ  = UINT64_C( 0x8000000000000000 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = signUI64 | exp;
+    lastBitMask = (uint_fast64_t) 1<<(0x403E - exp);
+    roundBitsMask = lastBitMask - 1;
+    sigZ = sigA;
+    if ( roundingMode == softfloat_round_near_maxMag ) {
+        sigZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_near_even ) {
+        sigZ += lastBitMask>>1;
+        if ( !(sigZ & roundBitsMask) ) sigZ &= ~lastBitMask;
+    } else if (
+        roundingMode == (signUI64 ? softfloat_round_min : softfloat_round_max)
+    ) {
+        sigZ += roundBitsMask;
+    }
+    sigZ &= ~roundBitsMask;
+    if ( !sigZ ) {
+        ++uiZ64;
+        sigZ = UINT64_C( 0x8000000000000000 );
+    }
+    if ( sigZ != sigA ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) sigZ |= lastBitMask;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif = sigZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_sqrt.c b/addins/SoftFloat-3e/source/extF80_sqrt.c
new file mode 100644
index 000000000..af8c496e1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_sqrt.c
@@ -0,0 +1,176 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_sqrt( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    struct exp32_sig64 normExpSig;
+    int_fast32_t expZ;
+    uint_fast32_t sig32A, recipSqrt32, sig32Z;
+    struct uint128 rem;
+    uint_fast64_t q, x64, sigZ;
+    struct uint128 y, term;
+    uint_fast64_t sigZExtra;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    expA  = expExtF80UI64( uiA64 );
+    sigA  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, 0, 0 );
+            uiZ64 = uiZ.v64;
+            uiZ0  = uiZ.v0;
+            goto uiZ;
+        }
+        if ( ! signA ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signA ) {
+        if ( ! sigA ) goto zero;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalExtF80Sig( sigA );
+        expA += normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    | (`sig32Z' is guaranteed to be a lower bound on the square root of
+    | `sig32A', which makes `sig32Z' also a lower bound on the square root of
+    | `sigA'.)
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x3FFF)>>1) + 0x3FFF;
+    expA &= 1;
+    sig32A = sigA>>32;
+    recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A );
+    sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32;
+    if ( expA ) {
+        sig32Z >>= 1;
+        rem = softfloat_shortShiftLeft128( 0, sigA, 61 );
+    } else {
+        rem = softfloat_shortShiftLeft128( 0, sigA, 62 );
+    }
+    rem.v64 -= (uint_fast64_t) sig32Z * sig32Z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((uint32_t) (rem.v64>>2) * (uint_fast64_t) recipSqrt32)>>32;
+    x64 = (uint_fast64_t) sig32Z<<32;
+    sigZ = x64 + (q<<3);
+    y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        term = softfloat_mul64ByShifted32To128( x64 + sigZ, q );
+        rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 );
+        if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break;
+        --q;
+        sigZ -= 1<<3;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = (((rem.v64>>2) * recipSqrt32)>>32) + 2;
+    x64 = sigZ;
+    sigZ = (sigZ<<1) + (q>>25);
+    sigZExtra = (uint64_t) (q<<39);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (q & 0xFFFFFF) <= 2 ) {
+        q &= ~(uint_fast64_t) 0xFFFF;
+        sigZExtra = (uint64_t) (q<<39);
+        term = softfloat_mul64ByShifted32To128( x64 + (q>>27), q );
+        x64 = (uint32_t) (q<<5) * (uint_fast64_t) (uint32_t) q;
+        term = softfloat_add128( term.v64, term.v0, 0, x64 );
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 28 );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            if ( ! sigZExtra ) --sigZ;
+            --sigZExtra;
+        } else {
+            if ( rem.v64 | rem.v0 ) sigZExtra |= 1;
+        }
+    }
+    return
+        softfloat_roundPackToExtF80(
+            0, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ64 = defaultNaNExtF80UI64;
+    uiZ0  = defaultNaNExtF80UI0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ64 = packToExtF80UI64( signA, 0 );
+    uiZ0  = 0;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_sub.c b/addins/SoftFloat-3e/source/extF80_sub.c
new file mode 100644
index 000000000..770c7563a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_sub.c
@@ -0,0 +1,80 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t extF80_sub( extFloat80_t a, extFloat80_t b )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool signA;
+    union { struct extFloat80M s; extFloat80_t f; } uB;
+    uint_fast16_t uiB64;
+    uint_fast64_t uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    extFloat80_t
+        (*magsFuncPtr)(
+            uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    signA = signExtF80UI64( uiA64 );
+    uB.f = b;
+    uiB64 = uB.s.signExp;
+    uiB0  = uB.s.signif;
+    signB = signExtF80UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_subMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        return softfloat_addMagsExtF80( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_subMagsExtF80 : softfloat_addMagsExtF80;
+    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_f128.c b/addins/SoftFloat-3e/source/extF80_to_f128.c
new file mode 100644
index 000000000..4de90ae31
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_f128.c
@@ -0,0 +1,75 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t extF80_to_f128( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    uint_fast16_t exp;
+    uint_fast64_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    bool sign;
+    struct uint128 frac128;
+    union ui128_f128 uZ;
+
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    exp = expExtF80UI64( uiA64 );
+    frac = uiA0 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( (exp == 0x7FFF) && frac ) {
+        softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+        uiZ = softfloat_commonNaNToF128UI( &commonNaN );
+    } else {
+        sign = signExtF80UI64( uiA64 );
+        frac128 = softfloat_shortShiftLeft128( 0, frac, 49 );
+        uiZ.v64 = packToF128UI64( sign, exp, frac128.v64 );
+        uiZ.v0  = frac128.v0;
+    }
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_f16.c b/addins/SoftFloat-3e/source/extF80_to_f16.c
new file mode 100644
index 000000000..5919403fb
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_f16.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t extF80_to_f16( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ, sig16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig16 = softfloat_shortShiftRightJam64( sig, 49 );
+    if ( ! (exp | sig16) ) {
+        uiZ = packToF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3FF1;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x40 ) exp = -0x40;
+    }
+    return softfloat_roundPackToF16( sign, exp, sig16 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_f32.c b/addins/SoftFloat-3e/source/extF80_to_f32.c
new file mode 100644
index 000000000..77fcfdc11
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_f32.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t extF80_to_f32( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    struct commonNaN commonNaN;
+    uint_fast32_t uiZ, sig32;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = softfloat_shortShiftRightJam64( sig, 33 );
+    if ( ! (exp | sig32) ) {
+        uiZ = packToF32UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3F81;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF32( sign, exp, sig32 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_f64.c b/addins/SoftFloat-3e/source/extF80_to_f64.c
new file mode 100644
index 000000000..410d6622c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_f64.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t extF80_to_f64( extFloat80_t a )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    uint_fast64_t uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    struct commonNaN commonNaN;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    uiA0  = uA.s.signif;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! (exp | sig) ) {
+        uiZ = packToF64UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            softfloat_extF80UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = softfloat_shortShiftRightJam64( sig, 1 );
+    exp -= 0x3C01;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF64( sign, exp, sig );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_i32.c b/addins/SoftFloat-3e/source/extF80_to_i32.c
new file mode 100644
index 000000000..9acdc3c9b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_i32.c
@@ -0,0 +1,83 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t
+ extF80_to_i32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) {
+#if (i32_fromNaN == i32_fromPosOverflow)
+        sign = 0;
+#elif (i32_fromNaN == i32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return i32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x4032 - exp;
+    if ( shiftDist <= 0 ) shiftDist = 1;
+    sig = softfloat_shiftRightJam64( sig, shiftDist );
+    return softfloat_roundToI32( sign, sig, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/extF80_to_i32_r_minMag.c
new file mode 100644
index 000000000..03224678a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_i32_r_minMag.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t extF80_to_i32_r_minMag( extFloat80_t a, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    bool sign;
+    int_fast32_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( shiftDist < 33 ) {
+        if (
+            (uiA64 == packToExtF80UI64( 1, 0x401E ))
+                && (sig < UINT64_C( 0x8000000100000000 ))
+        ) {
+            if ( exact && (sig & UINT64_C( 0x00000000FFFFFFFF )) ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return -0x7FFFFFFF - 1;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    absZ = sig>>shiftDist;
+    if ( exact && ((uint_fast64_t) (uint_fast32_t) absZ<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_i64.c b/addins/SoftFloat-3e/source/extF80_to_i64.c
new file mode 100644
index 000000000..ba307a61c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_i64.c
@@ -0,0 +1,89 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t
+ extF80_to_i64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    uint_fast64_t sigExtra;
+    struct uint64_extra sig64Extra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist <= 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( shiftDist ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            return
+                (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                    ? i64_fromNaN
+                    : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sigExtra = 0;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64Extra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist );
+        sig = sig64Extra.v;
+        sigExtra = sig64Extra.extra;
+    }
+    return softfloat_roundToI64( sign, sig, sigExtra, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/extF80_to_i64_r_minMag.c
new file mode 100644
index 000000000..8871d01d1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_i64_r_minMag.c
@@ -0,0 +1,94 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t extF80_to_i64_r_minMag( extFloat80_t a, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    bool sign;
+    int_fast64_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( shiftDist <= 0 ) {
+        if (
+            (uiA64 == packToExtF80UI64( 1, 0x403E ))
+                && (sig == UINT64_C( 0x8000000000000000 ))
+        ) {
+            return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    absZ = sig>>shiftDist;
+    if ( exact && (uint64_t) (sig<<(-shiftDist & 63)) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_ui32.c b/addins/SoftFloat-3e/source/extF80_to_ui32.c
new file mode 100644
index 000000000..581297731
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_ui32.c
@@ -0,0 +1,83 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t
+ extF80_to_ui32( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) {
+#if (ui32_fromNaN == ui32_fromPosOverflow)
+        sign = 0;
+#elif (ui32_fromNaN == ui32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return ui32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x4032 - exp;
+    if ( shiftDist <= 0 ) shiftDist = 1;
+    sig = softfloat_shiftRightJam64( sig, shiftDist );
+    return softfloat_roundToUI32( sign, sig, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/extF80_to_ui32_r_minMag.c
new file mode 100644
index 000000000..be2c53b1d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_ui32_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t a, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    bool sign;
+    uint_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( sign || (shiftDist < 32) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    z = sig>>shiftDist;
+    if ( exact && ((uint_fast64_t) z<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_ui64.c b/addins/SoftFloat-3e/source/extF80_to_ui64.c
new file mode 100644
index 000000000..490b26aaf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_ui64.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t
+ extF80_to_ui64( extFloat80_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    uint_fast64_t sigExtra;
+    struct uint64_extra sig64Extra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    sign = signExtF80UI64( uiA64 );
+    exp  = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist < 0 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigExtra = 0;
+    if ( shiftDist ) {
+        sig64Extra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist );
+        sig = sig64Extra.v;
+        sigExtra = sig64Extra.extra;
+    }
+    return softfloat_roundToUI64( sign, sig, sigExtra, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/extF80_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/extF80_to_ui64_r_minMag.c
new file mode 100644
index 000000000..eca688c65
--- /dev/null
+++ b/addins/SoftFloat-3e/source/extF80_to_ui64_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t a, bool exact )
+{
+    union { struct extFloat80M s; extFloat80_t f; } uA;
+    uint_fast16_t uiA64;
+    int_fast32_t exp;
+    uint_fast64_t sig;
+    int_fast32_t shiftDist;
+    bool sign;
+    uint_fast64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.s.signExp;
+    exp = expExtF80UI64( uiA64 );
+    sig = uA.s.signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signExtF80UI64( uiA64 );
+    if ( sign || (shiftDist < 0) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && (sig & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    z = sig>>shiftDist;
+    if ( exact && (z<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128M_add.c b/addins/SoftFloat-3e/source/f128M_add.c
new file mode 100644
index 000000000..3062bee84
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_add.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_add( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    const uint64_t *aWPtr, *bWPtr;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float128_t
+        (*magsFuncPtr)(
+            uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    aWPtr = (const uint64_t *) aPtr;
+    bWPtr = (const uint64_t *) bPtr;
+    uiA64 = aWPtr[indexWord( 2, 1 )];
+    uiA0  = aWPtr[indexWord( 2, 0 )];
+    signA = signF128UI64( uiA64 );
+    uiB64 = bWPtr[indexWord( 2, 1 )];
+    uiB0  = bWPtr[indexWord( 2, 0 )];
+    signB = signF128UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        *zPtr = softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        *zPtr = softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_addMagsF128 : softfloat_subMagsF128;
+    *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
+#else
+
+void
+ f128M_add( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    softfloat_addF128M(
+        (const uint32_t *) aPtr,
+        (const uint32_t *) bPtr,
+        (uint32_t *) zPtr,
+        false
+    );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_div.c b/addins/SoftFloat-3e/source/f128M_div.c
new file mode 100644
index 000000000..b443548f5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_div.c
@@ -0,0 +1,187 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_div( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *zPtr = f128_div( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ f128M_div( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t *zWPtr, uiA96;
+    bool signA;
+    int32_t expA;
+    uint32_t uiB96;
+    bool signB;
+    int32_t expB;
+    bool signZ;
+    uint32_t y[5], sigB[4];
+    int32_t expZ;
+    uint32_t recip32;
+    int ix;
+    uint64_t q64;
+    uint32_t q, qs[3], uiZ96;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    expA  = expF128UI96( uiA96 );
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    signB = signF128UI96( uiB96 );
+    expB  = expF128UI96( uiB96 );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return;
+        if ( expA == 0x7FFF ) {
+            if ( expB == 0x7FFF ) goto invalid;
+            goto infinity;
+        }
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = softfloat_shiftNormSigF128M( aWPtr, 13, y );
+    expB = softfloat_shiftNormSigF128M( bWPtr, 13, sigB );
+    if ( expA == -128 ) {
+        if ( expB == -128 ) goto invalid;
+        goto zero;
+    }
+    if ( expB == -128 ) {
+        softfloat_raiseFlags( softfloat_flag_infinite );
+        goto infinity;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x3FFE;
+    if ( softfloat_compare128M( y, sigB ) < 0 ) {
+        --expZ;
+        softfloat_add128M( y, y, y );
+    }
+    recip32 =
+        softfloat_approxRecip32_1(
+            ((uint64_t) sigB[indexWord( 4, 3 )]<<32 | sigB[indexWord( 4, 2 )])
+                >>30
+        );
+    ix = 3;
+    for (;;) {
+        q64 = (uint64_t) y[indexWordHi( 4 )] * recip32;
+        q = (q64 + 0x80000000)>>32;
+        --ix;
+        if ( ix < 0 ) break;
+        softfloat_remStep128MBy32( y, 29, sigB, q, y );
+        if ( y[indexWordHi( 4 )] & 0x80000000 ) {
+            --q;
+            softfloat_add128M( y, sigB, y );
+        }
+        qs[ix] = q;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ((q + 1) & 7) < 2 ) {
+        softfloat_remStep128MBy32( y, 29, sigB, q, y );
+        if ( y[indexWordHi( 4 )] & 0x80000000 ) {
+            --q;
+            softfloat_add128M( y, sigB, y );
+        } else if ( softfloat_compare128M( sigB, y ) <= 0 ) {
+            ++q;
+            softfloat_sub128M( y, sigB, y );
+        }
+        if (
+            y[indexWordLo( 4 )] || y[indexWord( 4, 1 )]
+                || (y[indexWord( 4, 2 )] | y[indexWord( 4, 3 )])
+        ) {
+            q |= 1;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q64 = (uint64_t) q<<28;
+    y[indexWord( 5, 0 )] = q64;
+    q64 = ((uint64_t) qs[0]<<25) + (q64>>32);
+    y[indexWord( 5, 1 )] = q64;
+    q64 = ((uint64_t) qs[1]<<22) + (q64>>32);
+    y[indexWord( 5, 2 )] = q64;
+    q64 = ((uint64_t) qs[2]<<19) + (q64>>32);
+    y[indexWord( 5, 3 )] = q64;
+    y[indexWord( 5, 4 )] = q64>>32;
+    softfloat_roundPackMToF128M( signZ, expZ, y, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidF128M( zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ96 = packToF128UI96( signZ, 0x7FFF, 0 );
+    goto uiZ96;
+ zero:
+    uiZ96 = packToF128UI96( signZ, 0, 0 );
+ uiZ96:
+    zWPtr[indexWordHi( 4 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_eq.c b/addins/SoftFloat-3e/source/f128M_eq.c
new file mode 100644
index 000000000..497fdbf6f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_eq.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_eq( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_eq( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_eq( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t wordA, wordB, uiA96, uiB96;
+    bool possibleOppositeZeros;
+    uint32_t mashWord;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    wordA = aWPtr[indexWord( 4, 2 )];
+    wordB = bWPtr[indexWord( 4, 2 )];
+    if ( wordA != wordB ) goto false_checkSigNaNs;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    possibleOppositeZeros = false;
+    if ( uiA96 != uiB96 ) {
+        possibleOppositeZeros = (((uiA96 | uiB96) & 0x7FFFFFFF) == 0);
+        if ( ! possibleOppositeZeros ) goto false_checkSigNaNs;
+    }
+    mashWord = wordA | wordB;
+    wordA = aWPtr[indexWord( 4, 1 )];
+    wordB = bWPtr[indexWord( 4, 1 )];
+    if ( wordA != wordB ) goto false_checkSigNaNs;
+    mashWord |= wordA | wordB;
+    wordA = aWPtr[indexWord( 4, 0 )];
+    wordB = bWPtr[indexWord( 4, 0 )];
+    if ( wordA != wordB ) goto false_checkSigNaNs;
+    if ( possibleOppositeZeros && ((mashWord | wordA | wordB) != 0) ) {
+        goto false_checkSigNaNs;
+    }
+    if ( ! softfloat_isNaNF128M( aWPtr ) && ! softfloat_isNaNF128M( bWPtr ) ) {
+        return true;
+    }
+ false_checkSigNaNs:
+    if (
+           f128M_isSignalingNaN( (const float128_t *) aWPtr )
+        || f128M_isSignalingNaN( (const float128_t *) bWPtr )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    return false;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_eq_signaling.c b/addins/SoftFloat-3e/source/f128M_eq_signaling.c
new file mode 100644
index 000000000..a9fa4d510
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_eq_signaling.c
@@ -0,0 +1,92 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_eq_signaling( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_eq_signaling( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_eq_signaling( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t wordA, wordB, uiA96, uiB96;
+    bool possibleOppositeZeros;
+    uint32_t mashWord;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    wordA = aWPtr[indexWord( 4, 2 )];
+    wordB = bWPtr[indexWord( 4, 2 )];
+    if ( wordA != wordB ) return false;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    possibleOppositeZeros = false;
+    if ( uiA96 != uiB96 ) {
+        possibleOppositeZeros = (((uiA96 | uiB96) & 0x7FFFFFFF) == 0);
+        if ( ! possibleOppositeZeros ) return false;
+    }
+    mashWord = wordA | wordB;
+    wordA = aWPtr[indexWord( 4, 1 )];
+    wordB = bWPtr[indexWord( 4, 1 )];
+    if ( wordA != wordB ) return false;
+    mashWord |= wordA | wordB;
+    wordA = aWPtr[indexWord( 4, 0 )];
+    wordB = bWPtr[indexWord( 4, 0 )];
+    return
+        (wordA == wordB)
+            && (! possibleOppositeZeros || ((mashWord | wordA | wordB) == 0));
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_le.c b/addins/SoftFloat-3e/source/f128M_le.c
new file mode 100644
index 000000000..7306e45c3
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_le.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_le( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_le( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_le( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t uiA96, uiB96;
+    bool signA, signB;
+    uint32_t wordA, wordB;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    signB = signF128UI96( uiB96 );
+    if ( signA != signB ) {
+        if ( signA ) return true;
+        if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return false;
+        wordA = aWPtr[indexWord( 4, 2 )];
+        wordB = bWPtr[indexWord( 4, 2 )];
+        if ( wordA | wordB ) return false;
+        wordA = aWPtr[indexWord( 4, 1 )];
+        wordB = bWPtr[indexWord( 4, 1 )];
+        if ( wordA | wordB ) return false;
+        wordA = aWPtr[indexWord( 4, 0 )];
+        wordB = bWPtr[indexWord( 4, 0 )];
+        return ((wordA | wordB) == 0);
+    }
+    if ( signA ) {
+        aWPtr = (const uint32_t *) bPtr;
+        bWPtr = (const uint32_t *) aPtr;
+    }
+    return (softfloat_compare128M( aWPtr, bWPtr ) <= 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_le_quiet.c b/addins/SoftFloat-3e/source/f128M_le_quiet.c
new file mode 100644
index 000000000..d9e442942
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_le_quiet.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_le_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_le_quiet( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_le_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t uiA96, uiB96;
+    bool signA, signB;
+    uint32_t wordA, wordB;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        if ( f128M_isSignalingNaN( aPtr ) || f128M_isSignalingNaN( bPtr ) ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    signB = signF128UI96( uiB96 );
+    if ( signA != signB ) {
+        if ( signA ) return true;
+        if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return false;
+        wordA = aWPtr[indexWord( 4, 2 )];
+        wordB = bWPtr[indexWord( 4, 2 )];
+        if ( wordA | wordB ) return false;
+        wordA = aWPtr[indexWord( 4, 1 )];
+        wordB = bWPtr[indexWord( 4, 1 )];
+        if ( wordA | wordB ) return false;
+        wordA = aWPtr[indexWord( 4, 0 )];
+        wordB = bWPtr[indexWord( 4, 0 )];
+        return ((wordA | wordB) == 0);
+    }
+    if ( signA ) {
+        aWPtr = (const uint32_t *) bPtr;
+        bWPtr = (const uint32_t *) aPtr;
+    }
+    return (softfloat_compare128M( aWPtr, bWPtr ) <= 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_lt.c b/addins/SoftFloat-3e/source/f128M_lt.c
new file mode 100644
index 000000000..d2f797fea
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_lt.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_lt( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_lt( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_lt( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t uiA96, uiB96;
+    bool signA, signB;
+    uint32_t wordA, wordB;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    signB = signF128UI96( uiB96 );
+    if ( signA != signB ) {
+        if ( signB ) return false;
+        if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return true;
+        wordA = aWPtr[indexWord( 4, 2 )];
+        wordB = bWPtr[indexWord( 4, 2 )];
+        if ( wordA | wordB ) return true;
+        wordA = aWPtr[indexWord( 4, 1 )];
+        wordB = bWPtr[indexWord( 4, 1 )];
+        if ( wordA | wordB ) return true;
+        wordA = aWPtr[indexWord( 4, 0 )];
+        wordB = bWPtr[indexWord( 4, 0 )];
+        return ((wordA | wordB) != 0);
+    }
+    if ( signA ) {
+        aWPtr = (const uint32_t *) bPtr;
+        bWPtr = (const uint32_t *) aPtr;
+    }
+    return (softfloat_compare128M( aWPtr, bWPtr ) < 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_lt_quiet.c b/addins/SoftFloat-3e/source/f128M_lt_quiet.c
new file mode 100644
index 000000000..adbddea71
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_lt_quiet.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+bool f128M_lt_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return f128_lt_quiet( *aPtr, *bPtr );
+
+}
+
+#else
+
+bool f128M_lt_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t uiA96, uiB96;
+    bool signA, signB;
+    uint32_t wordA, wordB;
+
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        if ( f128M_isSignalingNaN( aPtr ) || f128M_isSignalingNaN( bPtr ) ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    signB = signF128UI96( uiB96 );
+    if ( signA != signB ) {
+        if ( signB ) return false;
+        if ( (uiA96 | uiB96) & 0x7FFFFFFF ) return true;
+        wordA = aWPtr[indexWord( 4, 2 )];
+        wordB = bWPtr[indexWord( 4, 2 )];
+        if ( wordA | wordB ) return true;
+        wordA = aWPtr[indexWord( 4, 1 )];
+        wordB = bWPtr[indexWord( 4, 1 )];
+        if ( wordA | wordB ) return true;
+        wordA = aWPtr[indexWord( 4, 0 )];
+        wordB = bWPtr[indexWord( 4, 0 )];
+        return ((wordA | wordB) != 0);
+    }
+    if ( signA ) {
+        aWPtr = (const uint32_t *) bPtr;
+        bWPtr = (const uint32_t *) aPtr;
+    }
+    return (softfloat_compare128M( aWPtr, bWPtr ) < 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_mul.c b/addins/SoftFloat-3e/source/f128M_mul.c
new file mode 100644
index 000000000..4b8292a27
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_mul.c
@@ -0,0 +1,158 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_mul( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *zPtr = f128_mul( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ f128M_mul( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t *zWPtr;
+    uint32_t uiA96;
+    int32_t expA;
+    uint32_t uiB96;
+    int32_t expB;
+    bool signZ;
+    const uint32_t *ptr;
+    uint32_t uiZ96, sigA[4];
+    uint_fast8_t shiftDist;
+    uint32_t sigB[4];
+    int32_t expZ;
+    uint32_t sigProd[8], *extSigZPtr;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    expA = expF128UI96( uiA96 );
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    expB = expF128UI96( uiB96 );
+    signZ = signF128UI96( uiA96 ) ^ signF128UI96( uiB96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return;
+        ptr = aWPtr;
+        if ( ! expA ) goto possiblyInvalid;
+        if ( ! expB ) {
+            ptr = bWPtr;
+     possiblyInvalid:
+            if (
+                ! fracF128UI96( ptr[indexWordHi( 4 )] )
+                    && ! (ptr[indexWord( 4, 2 )] | ptr[indexWord( 4, 1 )]
+                              | ptr[indexWord( 4, 0 )])
+            ) {
+                softfloat_invalidF128M( zWPtr );
+                return;
+            }
+        }
+        uiZ96 = packToF128UI96( signZ, 0x7FFF, 0 );
+        goto uiZ96;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA ) {
+        sigA[indexWordHi( 4 )] = fracF128UI96( uiA96 ) | 0x00010000;
+        sigA[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+        sigA[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+        sigA[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+    } else {
+        expA = softfloat_shiftNormSigF128M( aWPtr, 0, sigA );
+        if ( expA == -128 ) goto zero;
+    }
+    if ( expB ) {
+        sigB[indexWordHi( 4 )] = fracF128UI96( uiB96 ) | 0x00010000;
+        sigB[indexWord( 4, 2 )] = bWPtr[indexWord( 4, 2 )];
+        sigB[indexWord( 4, 1 )] = bWPtr[indexWord( 4, 1 )];
+        sigB[indexWord( 4, 0 )] = bWPtr[indexWord( 4, 0 )];
+    } else {
+        expB = softfloat_shiftNormSigF128M( bWPtr, 0, sigB );
+        if ( expB == -128 ) goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x4000;
+    softfloat_mul128MTo256M( sigA, sigB, sigProd );
+    if (
+        sigProd[indexWord( 8, 2 )]
+            || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )])
+    ) {
+        sigProd[indexWord( 8, 3 )] |= 1;
+    }
+    extSigZPtr = &sigProd[indexMultiwordHi( 8, 5 )];
+    shiftDist = 16;
+    if ( extSigZPtr[indexWordHi( 5 )] & 2 ) {
+        ++expZ;
+        shiftDist = 15;
+    }
+    softfloat_shortShiftLeft160M( extSigZPtr, shiftDist, extSigZPtr );
+    softfloat_roundPackMToF128M( signZ, expZ, extSigZPtr, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ96 = packToF128UI96( signZ, 0, 0 );
+ uiZ96:
+    zWPtr[indexWordHi( 4 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_mulAdd.c b/addins/SoftFloat-3e/source/f128M_mulAdd.c
new file mode 100644
index 000000000..2b0b7fe26
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_mulAdd.c
@@ -0,0 +1,92 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_mulAdd(
+     const float128_t *aPtr,
+     const float128_t *bPtr,
+     const float128_t *cPtr,
+     float128_t *zPtr
+ )
+{
+    const uint64_t *aWPtr, *bWPtr, *cWPtr;
+    uint_fast64_t uiA64, uiA0;
+    uint_fast64_t uiB64, uiB0;
+    uint_fast64_t uiC64, uiC0;
+
+    aWPtr = (const uint64_t *) aPtr;
+    bWPtr = (const uint64_t *) bPtr;
+    cWPtr = (const uint64_t *) cPtr;
+    uiA64 = aWPtr[indexWord( 2, 1 )];
+    uiA0  = aWPtr[indexWord( 2, 0 )];
+    uiB64 = bWPtr[indexWord( 2, 1 )];
+    uiB0  = bWPtr[indexWord( 2, 0 )];
+    uiC64 = cWPtr[indexWord( 2, 1 )];
+    uiC0  = cWPtr[indexWord( 2, 0 )];
+    *zPtr = softfloat_mulAddF128( uiA64, uiA0, uiB64, uiB0, uiC64, uiC0, 0 );
+
+}
+
+#else
+
+void
+ f128M_mulAdd(
+     const float128_t *aPtr,
+     const float128_t *bPtr,
+     const float128_t *cPtr,
+     float128_t *zPtr
+ )
+{
+
+    softfloat_mulAddF128M(
+        (const uint32_t *) aPtr,
+        (const uint32_t *) bPtr,
+        (const uint32_t *) cPtr,
+        (uint32_t *) zPtr,
+        0
+    );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_rem.c b/addins/SoftFloat-3e/source/f128M_rem.c
new file mode 100644
index 000000000..39aafdd6a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_rem.c
@@ -0,0 +1,182 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_rem( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *zPtr = f128_rem( *aPtr, *bPtr );
+
+}
+
+#else
+
+void
+ f128M_rem( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    const uint32_t *aWPtr, *bWPtr;
+    uint32_t *zWPtr, uiA96;
+    int32_t expA, expB;
+    uint32_t x[4], rem1[5], *remPtr;
+    bool signRem;
+    int32_t expDiff;
+    uint32_t q, recip32;
+    uint64_t q64;
+    uint32_t rem2[5], *altRemPtr, *newRemPtr, wordMeanRem;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    bWPtr = (const uint32_t *) bPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    expA = expF128UI96( uiA96 );
+    expB = expF128UI96( bWPtr[indexWordHi( 4 )] );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return;
+        if ( expA == 0x7FFF ) goto invalid;
+        goto copyA;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA < expB - 1 ) goto copyA;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expB = softfloat_shiftNormSigF128M( bWPtr, 13, x );
+    if ( expB == -128 ) goto invalid;
+    remPtr = &rem1[indexMultiwordLo( 5, 4 )];
+    expA = softfloat_shiftNormSigF128M( aWPtr, 13, remPtr );
+    if ( expA == -128 ) goto copyA;
+    signRem = signF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( expDiff < 1 ) {
+        if ( expDiff < -1 ) goto copyA;
+        if ( expDiff ) {
+            --expB;
+            softfloat_add128M( x, x, x );
+            q = 0;
+        } else {
+            q = (softfloat_compare128M( x, remPtr ) <= 0);
+            if ( q ) softfloat_sub128M( remPtr, x, remPtr );
+        }
+    } else {
+        recip32 =
+            softfloat_approxRecip32_1(
+                ((uint64_t) x[indexWord( 4, 3 )]<<32 | x[indexWord( 4, 2 )])
+                    >>30
+            );
+        expDiff -= 30;
+        for (;;) {
+            q64 = (uint64_t) remPtr[indexWordHi( 4 )] * recip32;
+            if ( expDiff < 0 ) break;
+            q = (q64 + 0x80000000)>>32;
+            softfloat_remStep128MBy32( remPtr, 29, x, q, remPtr );
+            if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) {
+                softfloat_add128M( remPtr, x, remPtr );
+            }
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -29 here.)
+        *--------------------------------------------------------------------*/
+        q = (uint32_t) (q64>>32)>>(~expDiff & 31);
+        softfloat_remStep128MBy32( remPtr, expDiff + 30, x, q, remPtr );
+        if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) {
+            altRemPtr = &rem2[indexMultiwordLo( 5, 4 )];
+            softfloat_add128M( remPtr, x, altRemPtr );
+            goto selectRem;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    altRemPtr = &rem2[indexMultiwordLo( 5, 4 )];
+    do {
+        ++q;
+        newRemPtr = altRemPtr;
+        softfloat_sub128M( remPtr, x, newRemPtr );
+        altRemPtr = remPtr;
+        remPtr = newRemPtr;
+    } while ( ! (remPtr[indexWordHi( 4 )] & 0x80000000) );
+ selectRem:
+    softfloat_add128M( remPtr, altRemPtr, x );
+    wordMeanRem = x[indexWordHi( 4 )];
+    if (
+        (wordMeanRem & 0x80000000)
+            || (! wordMeanRem && (q & 1) && ! x[indexWord( 4, 0 )]
+                    && ! (x[indexWord( 4, 2 )] | x[indexWord( 4, 1 )]))
+    ) {
+        remPtr = altRemPtr;
+    }
+    if ( remPtr[indexWordHi( 4 )] & 0x80000000 ) {
+        signRem = ! signRem;
+        softfloat_negX128M( remPtr );
+    }
+    remPtr -= indexMultiwordLo( 5, 4 );
+    remPtr[indexWordHi( 5 )] = 0;
+    softfloat_normRoundPackMToF128M( signRem, expB + 18, remPtr, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidF128M( zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ copyA:
+    zWPtr[indexWordHi( 4 )] = uiA96;
+    zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_roundToInt.c b/addins/SoftFloat-3e/source/f128M_roundToInt.c
new file mode 100644
index 000000000..b96d742b2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_roundToInt.c
@@ -0,0 +1,223 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_roundToInt(
+     const float128_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     float128_t *zPtr
+ )
+{
+
+    *zPtr = f128_roundToInt( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+void
+ f128M_roundToInt(
+     const float128_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     float128_t *zPtr
+ )
+{
+    const uint32_t *aWPtr;
+    uint32_t *zWPtr;
+    uint32_t ui96;
+    int32_t exp;
+    uint32_t sigExtra;
+    bool sign;
+    uint_fast8_t bitPos;
+    bool roundNear;
+    unsigned int index, lastIndex;
+    bool extra;
+    uint32_t wordA, bit, wordZ;
+    uint_fast8_t carry;
+    uint32_t extrasMask;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    ui96 = aWPtr[indexWordHi( 4 )];
+    exp = expF128UI96( ui96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp < 0x3FFF ) {
+        zWPtr[indexWord( 4, 2 )] = 0;
+        zWPtr[indexWord( 4, 1 )] = 0;
+        zWPtr[indexWord( 4, 0 )] = 0;
+        sigExtra = aWPtr[indexWord( 4, 2 )];
+        if ( !sigExtra ) {
+            sigExtra = aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )];
+        }
+        if ( !sigExtra && !(ui96 & 0x7FFFFFFF) ) goto ui96;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        sign = signF128UI96( ui96 );
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !fracF128UI96( ui96 ) && !sigExtra ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0x3FFE ) goto mag1;
+            break;
+         case softfloat_round_min:
+            if ( sign ) goto mag1;
+            break;
+         case softfloat_round_max:
+            if ( !sign ) goto mag1;
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            goto mag1;
+#endif
+        }
+        ui96 = packToF128UI96( sign, 0, 0 );
+        goto ui96;
+     mag1:
+        ui96 = packToF128UI96( sign, 0x3FFF, 0 );
+        goto ui96;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x406F <= exp ) {
+        if (
+            (exp == 0x7FFF)
+                && (fracF128UI96( ui96 )
+                        || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                                | aWPtr[indexWord( 4, 0 )]))
+        ) {
+            softfloat_propagateNaNF128M( aWPtr, 0, zWPtr );
+            return;
+        }
+        zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+        zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+        zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+        goto ui96;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    bitPos = 0x406F - exp;
+    roundNear =
+           (roundingMode == softfloat_round_near_maxMag)
+        || (roundingMode == softfloat_round_near_even);
+    bitPos -= roundNear;
+    index = indexWordLo( 4 );
+    lastIndex = indexWordHi( 4 );
+    extra = 0;
+    for (;;) {
+        wordA = aWPtr[index];
+        if ( bitPos < 32 ) break;
+        if ( wordA ) extra = 1;
+        zWPtr[index] = 0;
+        index += wordIncr;
+        bitPos -= 32;
+    }
+    bit = (uint32_t) 1<<bitPos;
+    if ( roundNear ) {
+        wordZ = wordA + bit;
+        carry = (wordZ < wordA);
+        bit <<= 1;
+        extrasMask = bit - 1;
+        if ( exact && (extra || (wordA & extrasMask)) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        if (
+            (roundingMode == softfloat_round_near_even)
+                && !extra && !(wordZ & extrasMask)
+        ) {
+            if ( !bit ) {
+                zWPtr[index] = wordZ;
+                index += wordIncr;
+                wordZ = aWPtr[index] + carry;
+                carry &= !wordZ;
+                zWPtr[index] = wordZ & ~1;
+                goto propagateCarry;
+            }
+            wordZ &= ~bit;
+        }
+    } else {
+        wordZ = wordA;
+        carry = 0;
+        extrasMask = bit - 1;
+        if ( extra || (wordA & extrasMask) ) {
+            if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+            if (
+                roundingMode
+                    == (signF128UI96( ui96 ) ? softfloat_round_min
+                            : softfloat_round_max)
+            ) {
+                wordZ += bit;
+                carry = (wordZ < wordA);
+#ifdef SOFTFLOAT_ROUND_ODD
+            } else if ( roundingMode == softfloat_round_odd ) {
+                wordZ |= bit;
+#endif
+            }
+        }
+    }
+    wordZ &= ~extrasMask;
+    zWPtr[index] = wordZ;
+ propagateCarry:
+    while ( index != lastIndex ) {
+        index += wordIncr;
+        wordZ = aWPtr[index] + carry;
+        zWPtr[index] = wordZ;
+        carry &= !wordZ;
+    }
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ ui96:
+    zWPtr[indexWordHi( 4 )] = ui96;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_sqrt.c b/addins/SoftFloat-3e/source/f128M_sqrt.c
new file mode 100644
index 000000000..a98420803
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_sqrt.c
@@ -0,0 +1,228 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f128M_sqrt( const float128_t *aPtr, float128_t *zPtr )
+{
+
+    *zPtr = f128_sqrt( *aPtr );
+
+}
+
+#else
+
+void f128M_sqrt( const float128_t *aPtr, float128_t *zPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t *zWPtr;
+    uint32_t uiA96;
+    bool signA;
+    int32_t rawExpA;
+    uint32_t rem[6];
+    int32_t expA, expZ;
+    uint64_t rem64;
+    uint32_t sig32A, recipSqrt32, sig32Z, qs[3], q;
+    uint64_t sig64Z;
+    uint32_t term[5];
+    uint64_t x64;
+    uint32_t y[5], rem32;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    signA = signF128UI96( uiA96 );
+    rawExpA  = expF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( rawExpA == 0x7FFF ) {
+        if (
+            fracF128UI96( uiA96 )
+                || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                        | aWPtr[indexWord( 4, 0 )])
+        ) {
+            softfloat_propagateNaNF128M( aWPtr, 0, zWPtr );
+            return;
+        }
+        if ( ! signA ) goto copyA;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = softfloat_shiftNormSigF128M( aWPtr, 13 - (rawExpA & 1), rem );
+    if ( expA == -128 ) goto copyA;
+    if ( signA ) goto invalid;
+    /*------------------------------------------------------------------------
+    | (`sig32Z' is guaranteed to be a lower bound on the square root of
+    | `sig32A', which makes `sig32Z' also a lower bound on the square root of
+    | `sigA'.)
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x3FFF)>>1) + 0x3FFE;
+    expA &= 1;
+    rem64 = (uint64_t) rem[indexWord( 4, 3 )]<<32 | rem[indexWord( 4, 2 )];
+    if ( expA ) {
+        if ( ! rawExpA ) {
+            softfloat_shortShiftRight128M( rem, 1, rem );
+            rem64 >>= 1;
+        }
+        sig32A = rem64>>29;
+    } else {
+        sig32A = rem64>>30;
+    }
+    recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A );
+    sig32Z = ((uint64_t) sig32A * recipSqrt32)>>32;
+    if ( expA ) sig32Z >>= 1;
+    qs[2] = sig32Z;
+    rem64 -= (uint64_t) sig32Z * sig32Z;
+    rem[indexWord( 4, 3 )] = rem64>>32;
+    rem[indexWord( 4, 2 )] = rem64;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32;
+    sig64Z = ((uint64_t) sig32Z<<32) + ((uint64_t) q<<3);
+    term[indexWord( 4, 3 )] = 0;
+    term[indexWord( 4, 0 )] = 0;
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        x64 = ((uint64_t) sig32Z<<32) + sig64Z;
+        term[indexWord( 4, 2 )] = x64>>32;
+        term[indexWord( 4, 1 )] = x64;
+        softfloat_remStep128MBy32( rem, 29, term, q, y );
+        rem32 = y[indexWord( 4, 3 )];
+        if ( ! (rem32 & 0x80000000) ) break;
+        --q;
+        sig64Z -= 1<<3;
+    }
+    qs[1] = q;
+    rem64 = (uint64_t) rem32<<32 | y[indexWord( 4, 2 )];
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32;
+    if ( rem64>>34 ) q += recipSqrt32;
+    sig64Z <<= 1;
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        x64 = sig64Z + (q>>26);
+        term[indexWord( 4, 2 )] = x64>>32;
+        term[indexWord( 4, 1 )] = x64;
+        term[indexWord( 4, 0 )] = q<<6;
+        softfloat_remStep128MBy32(
+            y, 29, term, q, &rem[indexMultiwordHi( 6, 4 )] );
+        rem32 = rem[indexWordHi( 6 )];
+        if ( ! (rem32 & 0x80000000) ) break;
+        --q;
+    }
+    qs[0] = q;
+    rem64 = (uint64_t) rem32<<32 | rem[indexWord( 6, 4 )];
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = (((uint32_t) (rem64>>2) * (uint64_t) recipSqrt32)>>32) + 2;
+    if ( rem64>>34 ) q += recipSqrt32;
+    x64 = (uint64_t) q<<27;
+    y[indexWord( 5, 0 )] = x64;
+    x64 = ((uint64_t) qs[0]<<24) + (x64>>32);
+    y[indexWord( 5, 1 )] = x64;
+    x64 = ((uint64_t) qs[1]<<21) + (x64>>32);
+    y[indexWord( 5, 2 )] = x64;
+    x64 = ((uint64_t) qs[2]<<18) + (x64>>32);
+    y[indexWord( 5, 3 )] = x64;
+    y[indexWord( 5, 4 )] = x64>>32;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (q & 0xF) <= 2 ) {
+        q &= ~3;
+        y[indexWordLo( 5 )] = q<<27;
+        term[indexWord( 5, 4 )] = 0;
+        term[indexWord( 5, 3 )] = 0;
+        term[indexWord( 5, 2 )] = 0;
+        term[indexWord( 5, 1 )] = q>>6;
+        term[indexWord( 5, 0 )] = q<<26;
+        softfloat_sub160M( y, term, term );
+        rem[indexWord( 6, 1 )] = 0;
+        rem[indexWord( 6, 0 )] = 0;
+        softfloat_remStep160MBy32(
+            &rem[indexMultiwordLo( 6, 5 )],
+            14,
+            term,
+            q,
+            &rem[indexMultiwordLo( 6, 5 )]
+        );
+        rem32 = rem[indexWord( 6, 4 )];
+        if ( rem32 & 0x80000000 ) {
+            softfloat_sub1X160M( y );
+        } else {
+            if (
+                rem32 || rem[indexWord( 6, 0 )] || rem[indexWord( 6, 1 )]
+                    || (rem[indexWord( 6, 3 )] | rem[indexWord( 6, 2 )])
+            ) {
+                y[indexWordLo( 5 )] |= 1;
+            }
+        }
+    }
+    softfloat_roundPackMToF128M( 0, expZ, y, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidF128M( zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ copyA:
+    zWPtr[indexWordHi( 4 )] = uiA96;
+    zWPtr[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_sub.c b/addins/SoftFloat-3e/source/f128M_sub.c
new file mode 100644
index 000000000..5d65c799f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_sub.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void
+ f128M_sub( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    const uint64_t *aWPtr, *bWPtr;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float128_t
+        (*magsFuncPtr)(
+            uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    aWPtr = (const uint64_t *) aPtr;
+    bWPtr = (const uint64_t *) bPtr;
+    uiA64 = aWPtr[indexWord( 2, 1 )];
+    uiA0  = aWPtr[indexWord( 2, 0 )];
+    signA = signF128UI64( uiA64 );
+    uiB64 = bWPtr[indexWord( 2, 1 )];
+    uiB0  = bWPtr[indexWord( 2, 0 )];
+    signB = signF128UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        *zPtr = softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        *zPtr = softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_subMagsF128 : softfloat_addMagsF128;
+    *zPtr = (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
+#else
+
+void
+ f128M_sub( const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    softfloat_addF128M(
+        (const uint32_t *) aPtr,
+        (const uint32_t *) bPtr,
+        (uint32_t *) zPtr,
+        true
+    );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_extF80M.c b/addins/SoftFloat-3e/source/f128M_to_extF80M.c
new file mode 100644
index 000000000..b0340c794
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_extF80M.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f128M_to_extF80M( const float128_t *aPtr, extFloat80_t *zPtr )
+{
+
+    *zPtr = f128_to_extF80( *aPtr );
+
+}
+
+#else
+
+void f128M_to_extF80M( const float128_t *aPtr, extFloat80_t *zPtr )
+{
+    const uint32_t *aWPtr;
+    struct extFloat80M *zSPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    struct commonNaN commonNaN;
+    uint32_t sig[4];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    zSPtr = (struct extFloat80M *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( softfloat_isNaNF128M( aWPtr ) ) {
+            softfloat_f128MToCommonNaN( aWPtr, &commonNaN );
+            softfloat_commonNaNToExtF80M( &commonNaN, zSPtr );
+            return;
+        }
+        zSPtr->signExp = packToExtF80UI64( sign, 0x7FFF );
+        zSPtr->signif = UINT64_C( 0x8000000000000000 );
+        return;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp = softfloat_shiftNormSigF128M( aWPtr, 15, sig );
+    if ( exp == -128 ) {
+        zSPtr->signExp = packToExtF80UI64( sign, 0 );
+        zSPtr->signif = 0;
+        return;
+    }
+    if ( sig[indexWord( 4, 0 )] ) sig[indexWord( 4, 1 )] |= 1;
+    softfloat_roundPackMToExtF80M(
+        sign, exp, &sig[indexMultiwordHi( 4, 3 )], 80, zSPtr );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_f16.c b/addins/SoftFloat-3e/source/f128M_to_f16.c
new file mode 100644
index 000000000..95109a771
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_f16.c
@@ -0,0 +1,113 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float16_t f128M_to_f16( const float128_t *aPtr )
+{
+
+    return f128_to_f16( *aPtr );
+
+}
+
+#else
+
+float16_t f128M_to_f16( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint32_t frac32;
+    struct commonNaN commonNaN;
+    uint16_t uiZ, frac16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    frac32 =
+        fracF128UI96( uiA96 )
+            | ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                    | aWPtr[indexWord( 4, 0 )])
+                   != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac32 ) {
+            softfloat_f128MToCommonNaN( aWPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac16 = frac32>>2 | (frac32 & 3);
+    if ( ! (exp | frac16) ) {
+        uiZ = packToF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3FF1;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x40 ) exp = -0x40;
+    }
+    return softfloat_roundPackToF16( sign, exp, frac16 | 0x4000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_f32.c b/addins/SoftFloat-3e/source/f128M_to_f32.c
new file mode 100644
index 000000000..4542deb0c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_f32.c
@@ -0,0 +1,109 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float32_t f128M_to_f32( const float128_t *aPtr )
+{
+
+    return f128_to_f32( *aPtr );
+
+}
+
+#else
+
+float32_t f128M_to_f32( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint64_t frac64;
+    struct commonNaN commonNaN;
+    uint32_t uiZ, frac32;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    frac64 =
+        (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )]
+            | ((aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )]) != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 ) {
+            softfloat_f128MToCommonNaN( aWPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac32 = softfloat_shortShiftRightJam64( frac64, 18 );
+    if ( ! (exp | frac32) ) {
+        uiZ = packToF32UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3F81;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF32( sign, exp, frac32 | 0x40000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_f64.c b/addins/SoftFloat-3e/source/f128M_to_f64.c
new file mode 100644
index 000000000..6213bb7f5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_f64.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float64_t f128M_to_f64( const float128_t *aPtr )
+{
+
+    return f128_to_f64( *aPtr );
+
+}
+
+#else
+
+float64_t f128M_to_f64( const float128_t *aPtr )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint64_t frac64;
+    struct commonNaN commonNaN;
+    uint64_t uiZ;
+    uint32_t frac32;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    frac64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )];
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 || aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) {
+            softfloat_f128MToCommonNaN( aWPtr, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac32 = aWPtr[indexWord( 4, 1 )];
+    frac64 = frac64<<14 | frac32>>18;
+    if ( (frac32 & 0x0003FFFF) || aWPtr[indexWord( 4, 0 )] ) frac64 |= 1;
+    if ( ! (exp | frac64) ) {
+        uiZ = packToF64UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3C01;
+    if ( sizeof (int_fast16_t) < sizeof (int32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return
+        softfloat_roundPackToF64(
+            sign, exp, frac64 | UINT64_C( 0x4000000000000000 ) );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_i32.c b/addins/SoftFloat-3e/source/f128M_to_i32.c
new file mode 100644
index 000000000..54cc6f603
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_i32.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast32_t
+ f128M_to_i32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return f128_to_i32( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+int_fast32_t
+ f128M_to_i32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint64_t sig64;
+    int32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )];
+    if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && sig64 ) {
+#if (i32_fromNaN == i32_fromPosOverflow)
+        sign = 0;
+#elif (i32_fromNaN == i32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return i32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+    shiftDist = 0x4023 - exp;
+    if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    return softfloat_roundToI32( sign, sig64, roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/f128M_to_i32_r_minMag.c
new file mode 100644
index 000000000..1f22039de
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_i32_r_minMag.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast32_t f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact )
+{
+
+    return f128_to_i32_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+int_fast32_t f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint64_t sig64;
+    int32_t shiftDist;
+    uint32_t absZ, uiZ;
+    union { uint32_t ui; int32_t i; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )];
+    if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp < 0x3FFF ) {
+        if ( exact && (exp | sig64) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x401F <= exp ) goto invalid;
+    shiftDist = 0x402F - exp;
+    sig64 |= UINT64_C( 0x0001000000000000 );
+    absZ = sig64>>shiftDist;
+    uiZ = sign ? -absZ : absZ;
+    if ( uiZ>>31 != sign ) goto invalid;
+    if ( exact && ((uint64_t) absZ<<shiftDist != sig64) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    uZ.ui = uiZ;
+    return uZ.i;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && sig64 ? i32_fromNaN
+            : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_i64.c b/addins/SoftFloat-3e/source/f128M_to_i64.c
new file mode 100644
index 000000000..08844b6be
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_i64.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast64_t
+ f128M_to_i64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return f128_to_i64( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+int_fast64_t
+ f128M_to_i64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint32_t sig96;
+    int32_t shiftDist;
+    uint32_t sig[4];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign  = signF128UI96( uiA96 );
+    exp   = expF128UI96( uiA96 );
+    sig96 = fracF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x404F - exp;
+    if ( shiftDist < 17 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF)
+                && (sig96
+                        || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                                | aWPtr[indexWord( 4, 0 )]))
+                ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig96 |= 0x00010000;
+    sig[indexWord( 4, 3 )] = sig96;
+    sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+    sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+    sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+    softfloat_shiftRightJam128M( sig, shiftDist, sig );
+    return
+        softfloat_roundMToI64(
+            sign, sig + indexMultiwordLo( 4, 3 ), roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/f128M_to_i64_r_minMag.c
new file mode 100644
index 000000000..da3d28ad0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_i64_r_minMag.c
@@ -0,0 +1,124 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+int_fast64_t f128M_to_i64_r_minMag( const float128_t *aPtr, bool exact )
+{
+
+    return f128_to_i64_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+int_fast64_t f128M_to_i64_r_minMag( const float128_t *aPtr, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint32_t sig96;
+    int32_t shiftDist;
+    uint32_t sig[4];
+    uint64_t uiZ;
+    union { uint64_t ui; int64_t i; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign  = signF128UI96( uiA96 );
+    exp   = expF128UI96( uiA96 );
+    sig96 = fracF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist < 0 ) goto invalid;
+    if ( exact ) {
+        if ( exp ) sig96 |= 0x00010000;
+        sig[indexWord( 4, 3 )] = sig96;
+        sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+        sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+        sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+        softfloat_shiftRightJam128M( sig, shiftDist + 17, sig );
+        uiZ = (uint64_t) sig[indexWord( 4, 2 )]<<32 | sig[indexWord( 4, 1 )];
+        if ( uiZ>>63 && (! sign || (uiZ != UINT64_C( 0x8000000000000000 ))) ) {
+            goto invalid;
+        }
+        if ( sig[indexWordLo( 4 )] ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    } else {
+        if ( 64 <= shiftDist ) return 0;
+        uiZ =
+              (uint64_t) sig96<<47
+            | (uint64_t) aWPtr[indexWord( 4, 2 )]<<15
+            | aWPtr[indexWord( 4, 1 )]>>17;
+        if ( shiftDist ) {
+            uiZ |= UINT64_C( 0x8000000000000000 );
+            uiZ >>= shiftDist;
+        } else {
+            if ( uiZ || ! sign ) goto invalid;
+            uiZ |= UINT64_C( 0x8000000000000000 );
+        }
+    }
+    if ( sign ) uiZ = -uiZ;
+    uZ.ui = uiZ;
+    return uZ.i;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF)
+            && (sig96
+                    || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                            | aWPtr[indexWord( 4, 0 )]))
+            ? i64_fromNaN
+            : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_ui32.c b/addins/SoftFloat-3e/source/f128M_to_ui32.c
new file mode 100644
index 000000000..c1baa063a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_ui32.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast32_t
+ f128M_to_ui32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return f128_to_ui32( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+uint_fast32_t
+ f128M_to_ui32( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint64_t sig64;
+    int32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign = signF128UI96( uiA96 );
+    exp  = expF128UI96( uiA96 );
+    sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )];
+    if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && sig64 ) {
+#if (ui32_fromNaN == ui32_fromPosOverflow)
+        sign = 0;
+#elif (ui32_fromNaN == ui32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return ui32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+    shiftDist = 0x4023 - exp;
+    if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    return softfloat_roundToUI32( sign, sig64, roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/f128M_to_ui32_r_minMag.c
new file mode 100644
index 000000000..a1aca621a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_ui32_r_minMag.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *aPtr, bool exact )
+{
+
+    return f128_to_ui32_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *aPtr, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    int32_t exp;
+    uint64_t sig64;
+    int32_t shiftDist;
+    bool sign;
+    uint32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    exp = expF128UI96( uiA96 );
+    sig64 = (uint64_t) fracF128UI96( uiA96 )<<32 | aWPtr[indexWord( 4, 2 )];
+    if ( aWPtr[indexWord( 4, 1 )] | aWPtr[indexWord( 4, 0 )] ) sig64 |= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( 49 <= shiftDist ) {
+        if ( exact && (exp | sig64) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF128UI96( uiA96 );
+    if ( sign || (shiftDist < 17) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && sig64 ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig64 |= UINT64_C( 0x0001000000000000 );
+    z = sig64>>shiftDist;
+    if ( exact && ((uint64_t) z<<shiftDist != sig64) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_ui64.c b/addins/SoftFloat-3e/source/f128M_to_ui64.c
new file mode 100644
index 000000000..abaa85543
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_ui64.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast64_t
+ f128M_to_ui64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return f128_to_ui64( *aPtr, roundingMode, exact );
+
+}
+
+#else
+
+uint_fast64_t
+ f128M_to_ui64( const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint32_t sig96;
+    int32_t shiftDist;
+    uint32_t sig[4];
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign  = signF128UI96( uiA96 );
+    exp   = expF128UI96( uiA96 );
+    sig96 = fracF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x404F - exp;
+    if ( shiftDist < 17 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF)
+                && (sig96
+                        || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                                | aWPtr[indexWord( 4, 0 )]))
+                ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig96 |= 0x00010000;
+    sig[indexWord( 4, 3 )] = sig96;
+    sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+    sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+    sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+    softfloat_shiftRightJam128M( sig, shiftDist, sig );
+    return
+        softfloat_roundMToUI64(
+            sign, sig + indexMultiwordLo( 4, 3 ), roundingMode, exact );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128M_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/f128M_to_ui64_r_minMag.c
new file mode 100644
index 000000000..7a1b60295
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128M_to_ui64_r_minMag.c
@@ -0,0 +1,114 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *aPtr, bool exact )
+{
+
+    return f128_to_ui64_r_minMag( *aPtr, exact );
+
+}
+
+#else
+
+uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *aPtr, bool exact )
+{
+    const uint32_t *aWPtr;
+    uint32_t uiA96;
+    bool sign;
+    int32_t exp;
+    uint32_t sig96;
+    int32_t shiftDist;
+    uint32_t sig[4];
+    uint64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    aWPtr = (const uint32_t *) aPtr;
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    sign  = signF128UI96( uiA96 );
+    exp   = expF128UI96( uiA96 );
+    sig96 = fracF128UI96( uiA96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x403E - exp;
+    if ( shiftDist < 0 ) goto invalid;
+    if ( exact ) {
+        if ( exp ) sig96 |= 0x00010000;
+        sig[indexWord( 4, 3 )] = sig96;
+        sig[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+        sig[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+        sig[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+        softfloat_shiftRightJam128M( sig, shiftDist + 17, sig );
+        z = (uint64_t) sig[indexWord( 4, 2 )]<<32 | sig[indexWord( 4, 1 )];
+        if ( sign && z ) goto invalid;
+        if ( sig[indexWordLo( 4 )] ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    } else {
+        if ( 64 <= shiftDist ) return 0;
+        if ( sign ) goto invalid;
+        z =   UINT64_C( 0x8000000000000000 )
+            | (uint64_t) sig96<<47
+            | (uint64_t) aWPtr[indexWord( 4, 2 )]<<15
+            | aWPtr[indexWord( 4, 1 )]>>17;
+        z >>= shiftDist;
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF)
+            && (sig96
+                    || (aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                            | aWPtr[indexWord( 4, 0 )]))
+            ? ui64_fromNaN
+            : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f128_add.c b/addins/SoftFloat-3e/source/f128_add.c
new file mode 100644
index 000000000..e9caba682
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_add.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t f128_add( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float128_t
+        (*magsFuncPtr)(
+            uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    signB = signF128UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_addMagsF128 : softfloat_subMagsF128;
+    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_div.c b/addins/SoftFloat-3e/source/f128_div.c
new file mode 100644
index 000000000..0693db754
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_div.c
@@ -0,0 +1,199 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f128_div( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    int_fast32_t expA;
+    struct uint128 sigA;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+    int_fast32_t expB;
+    struct uint128 sigB;
+    bool signZ;
+    struct exp32_sig128 normExpSig;
+    int_fast32_t expZ;
+    struct uint128 rem;
+    uint_fast32_t recip32;
+    int ix;
+    uint_fast64_t q64;
+    uint_fast32_t q;
+    struct uint128 term;
+    uint_fast32_t qs[3];
+    uint_fast64_t sigZExtra;
+    struct uint128 sigZ, uiZ;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    expA  = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    signB = signF128UI64( uiB64 );
+    expB  = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if ( sigA.v64 | sigA.v0 ) goto propagateNaN;
+        if ( expB == 0x7FFF ) {
+            if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! (sigB.v64 | sigB.v0) ) {
+            if ( ! (expA | sigA.v64 | sigA.v0) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! (sigA.v64 | sigA.v0) ) goto zero;
+        normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x3FFE;
+    sigA.v64 |= UINT64_C( 0x0001000000000000 );
+    sigB.v64 |= UINT64_C( 0x0001000000000000 );
+    rem = sigA;
+    if ( softfloat_lt128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 ) ) {
+        --expZ;
+        rem = softfloat_add128( sigA.v64, sigA.v0, sigA.v64, sigA.v0 );
+    }
+    recip32 = softfloat_approxRecip32_1( sigB.v64>>17 );
+    ix = 3;
+    for (;;) {
+        q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32;
+        q = (q64 + 0x80000000)>>32;
+        --ix;
+        if ( ix < 0 ) break;
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+        term = softfloat_mul128By32( sigB.v64, sigB.v0, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            --q;
+            rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+        }
+        qs[ix] = q;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ((q + 1) & 7) < 2 ) {
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+        term = softfloat_mul128By32( sigB.v64, sigB.v0, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            --q;
+            rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+        } else if ( softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 ) ) {
+            ++q;
+            rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+        }
+        if ( rem.v64 | rem.v0 ) q |= 1;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigZExtra = (uint64_t) ((uint_fast64_t) q<<60);
+    term = softfloat_shortShiftLeft128( 0, qs[1], 54 );
+    sigZ =
+        softfloat_add128(
+            (uint_fast64_t) qs[2]<<19, ((uint_fast64_t) qs[0]<<25) + (q>>4),
+            term.v64, term.v0
+        );
+    return
+        softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 );
+    goto uiZ0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ.v64 = packToF128UI64( signZ, 0, 0 );
+ uiZ0:
+    uiZ.v0 = 0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_eq.c b/addins/SoftFloat-3e/source/f128_eq.c
new file mode 100644
index 000000000..9462fc2ab
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_eq.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f128_eq( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNF128UI( uiA64, uiA0 )
+            || softfloat_isSigNaNF128UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return
+           (uiA0 == uiB0)
+        && (   (uiA64 == uiB64)
+            || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+           );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_eq_signaling.c b/addins/SoftFloat-3e/source/f128_eq_signaling.c
new file mode 100644
index 000000000..5d0819d29
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_eq_signaling.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f128_eq_signaling( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return
+           (uiA0 == uiB0)
+        && (   (uiA64 == uiB64)
+            || (! uiA0 && ! ((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+           );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_isSignalingNaN.c b/addins/SoftFloat-3e/source/f128_isSignalingNaN.c
new file mode 100644
index 000000000..a764ff6bf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_isSignalingNaN.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f128_isSignalingNaN( float128_t a )
+{
+    union ui128_f128 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF128UI( uA.ui.v64, uA.ui.v0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_le.c b/addins/SoftFloat-3e/source/f128_le.c
new file mode 100644
index 000000000..521a1cb03
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_le.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f128_le( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF128UI64( uiA64 );
+    signB = signF128UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA
+                  || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                            | uiA0 | uiB0)
+            : ((uiA64 == uiB64) && (uiA0 == uiB0))
+                  || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_le_quiet.c b/addins/SoftFloat-3e/source/f128_le_quiet.c
new file mode 100644
index 000000000..820b28b81
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_le_quiet.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f128_le_quiet( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNF128UI( uiA64, uiA0 )
+            || softfloat_isSigNaNF128UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF128UI64( uiA64 );
+    signB = signF128UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA
+                  || ! (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                            | uiA0 | uiB0)
+            : ((uiA64 == uiB64) && (uiA0 == uiB0))
+                  || (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_lt.c b/addins/SoftFloat-3e/source/f128_lt.c
new file mode 100644
index 000000000..fa46ae2bc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_lt.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f128_lt( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF128UI64( uiA64 );
+    signB = signF128UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA
+                  && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                          | uiA0 | uiB0)
+            : ((uiA64 != uiB64) || (uiA0 != uiB0))
+                  && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_lt_quiet.c b/addins/SoftFloat-3e/source/f128_lt_quiet.c
new file mode 100644
index 000000000..d491de2f2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_lt_quiet.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f128_lt_quiet( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    if ( isNaNF128UI( uiA64, uiA0 ) || isNaNF128UI( uiB64, uiB0 ) ) {
+        if (
+               softfloat_isSigNaNF128UI( uiA64, uiA0 )
+            || softfloat_isSigNaNF128UI( uiB64, uiB0 )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF128UI64( uiA64 );
+    signB = signF128UI64( uiB64 );
+    return
+        (signA != signB)
+            ? signA
+                  && (((uiA64 | uiB64) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                          | uiA0 | uiB0)
+            : ((uiA64 != uiB64) || (uiA0 != uiB0))
+                  && (signA ^ softfloat_lt128( uiA64, uiA0, uiB64, uiB0 ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_mul.c b/addins/SoftFloat-3e/source/f128_mul.c
new file mode 100644
index 000000000..24af86a24
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_mul.c
@@ -0,0 +1,163 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f128_mul( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    int_fast32_t expA;
+    struct uint128 sigA;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+    int_fast32_t expB;
+    struct uint128 sigB;
+    bool signZ;
+    uint_fast64_t magBits;
+    struct exp32_sig128 normExpSig;
+    int_fast32_t expZ;
+    uint64_t sig256Z[4];
+    uint_fast64_t sigZExtra;
+    struct uint128 sigZ;
+    struct uint128_extra sig128Extra;
+    struct uint128 uiZ;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    expA  = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    signB = signF128UI64( uiB64 );
+    expB  = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if (
+            (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0))
+        ) {
+            goto propagateNaN;
+        }
+        magBits = expB | sigB.v64 | sigB.v0;
+        goto infArg;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+        magBits = expA | sigA.v64 | sigA.v0;
+        goto infArg;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! (sigA.v64 | sigA.v0) ) goto zero;
+        normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! (sigB.v64 | sigB.v0) ) goto zero;
+        normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x4000;
+    sigA.v64 |= UINT64_C( 0x0001000000000000 );
+    sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 16 );
+    softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z );
+    sigZExtra = sig256Z[indexWord( 4, 1 )] | (sig256Z[indexWord( 4, 0 )] != 0);
+    sigZ =
+        softfloat_add128(
+            sig256Z[indexWord( 4, 3 )], sig256Z[indexWord( 4, 2 )],
+            sigA.v64, sigA.v0
+        );
+    if ( UINT64_C( 0x0002000000000000 ) <= sigZ.v64 ) {
+        ++expZ;
+        sig128Extra =
+            softfloat_shortShiftRightJam128Extra(
+                sigZ.v64, sigZ.v0, sigZExtra, 1 );
+        sigZ = sig128Extra.v;
+        sigZExtra = sig128Extra.extra;
+    }
+    return
+        softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infArg:
+    if ( ! magBits ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ.v64 = defaultNaNF128UI64;
+        uiZ.v0  = defaultNaNF128UI0;
+        goto uiZ;
+    }
+    uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 );
+    goto uiZ0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ.v64 = packToF128UI64( signZ, 0, 0 );
+ uiZ0:
+    uiZ.v0 = 0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_mulAdd.c b/addins/SoftFloat-3e/source/f128_mulAdd.c
new file mode 100644
index 000000000..c7272d4e0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_mulAdd.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t f128_mulAdd( float128_t a, float128_t b, float128_t c )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    union ui128_f128 uC;
+    uint_fast64_t uiC64, uiC0;
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    uC.f = c;
+    uiC64 = uC.ui.v64;
+    uiC0  = uC.ui.v0;
+    return softfloat_mulAddF128( uiA64, uiA0, uiB64, uiB0, uiC64, uiC0, 0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_rem.c b/addins/SoftFloat-3e/source/f128_rem.c
new file mode 100644
index 000000000..f525f697a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_rem.c
@@ -0,0 +1,190 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f128_rem( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    int_fast32_t expA;
+    struct uint128 sigA;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    int_fast32_t expB;
+    struct uint128 sigB;
+    struct exp32_sig128 normExpSig;
+    struct uint128 rem;
+    int_fast32_t expDiff;
+    uint_fast32_t q, recip32;
+    uint_fast64_t q64;
+    struct uint128 term, altRem, meanRem;
+    bool signRem;
+    struct uint128 uiZ;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    expA  = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    expB  = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if (
+            (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0))
+        ) {
+            goto propagateNaN;
+        }
+        goto invalid;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! (sigB.v64 | sigB.v0) ) goto invalid;
+        normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! (sigA.v64 | sigA.v0) ) return a;
+        normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigA.v64 |= UINT64_C( 0x0001000000000000 );
+    sigB.v64 |= UINT64_C( 0x0001000000000000 );
+    rem = sigA;
+    expDiff = expA - expB;
+    if ( expDiff < 1 ) {
+        if ( expDiff < -1 ) return a;
+        if ( expDiff ) {
+            --expB;
+            sigB = softfloat_add128( sigB.v64, sigB.v0, sigB.v64, sigB.v0 );
+            q = 0;
+        } else {
+            q = softfloat_le128( sigB.v64, sigB.v0, rem.v64, rem.v0 );
+            if ( q ) {
+                rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+            }
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( sigB.v64>>17 );
+        expDiff -= 30;
+        for (;;) {
+            q64 = (uint_fast64_t) (uint32_t) (rem.v64>>19) * recip32;
+            if ( expDiff < 0 ) break;
+            q = (q64 + 0x80000000)>>32;
+            rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+            term = softfloat_mul128By32( sigB.v64, sigB.v0, q );
+            rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+            if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+                rem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+            }
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -29 here.)
+        *--------------------------------------------------------------------*/
+        q = (uint32_t) (q64>>32)>>(~expDiff & 31);
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, expDiff + 30 );
+        term = softfloat_mul128By32( sigB.v64, sigB.v0, q );
+        rem = softfloat_sub128( rem.v64, rem.v0, term.v64, term.v0 );
+        if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            altRem = softfloat_add128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+            goto selectRem;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    do {
+        altRem = rem;
+        ++q;
+        rem = softfloat_sub128( rem.v64, rem.v0, sigB.v64, sigB.v0 );
+    } while ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) );
+ selectRem:
+    meanRem = softfloat_add128( rem.v64, rem.v0, altRem.v64, altRem.v0 );
+    if (
+        (meanRem.v64 & UINT64_C( 0x8000000000000000 ))
+            || (! (meanRem.v64 | meanRem.v0) && (q & 1))
+    ) {
+        rem = altRem;
+    }
+    signRem = signA;
+    if ( rem.v64 & UINT64_C( 0x8000000000000000 ) ) {
+        signRem = ! signRem;
+        rem = softfloat_sub128( 0, 0, rem.v64, rem.v0 );
+    }
+    return softfloat_normRoundPackToF128( signRem, expB - 1, rem.v64, rem.v0 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_roundToInt.c b/addins/SoftFloat-3e/source/f128_roundToInt.c
new file mode 100644
index 000000000..69185d6ef
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_roundToInt.c
@@ -0,0 +1,172 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t
+ f128_roundToInt( float128_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    int_fast32_t exp;
+    struct uint128 uiZ;
+    uint_fast64_t lastBitMask0, roundBitsMask;
+    bool roundNearEven;
+    uint_fast64_t lastBitMask64;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    exp = expF128UI64( uiA64 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x402F <= exp ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( 0x406F <= exp ) {
+            if ( (exp == 0x7FFF) && (fracF128UI64( uiA64 ) | uiA0) ) {
+                uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 );
+                goto uiZ;
+            }
+            return a;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        lastBitMask0 = (uint_fast64_t) 2<<(0x406E - exp);
+        roundBitsMask = lastBitMask0 - 1;
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+        roundNearEven = (roundingMode == softfloat_round_near_even);
+        if ( roundNearEven || (roundingMode == softfloat_round_near_maxMag) ) {
+            if ( exp == 0x402F ) {
+                if ( UINT64_C( 0x8000000000000000 ) <= uiZ.v0 ) {
+                    ++uiZ.v64;
+                    if (
+                        roundNearEven
+                            && (uiZ.v0 == UINT64_C( 0x8000000000000000 ))
+                    ) {
+                        uiZ.v64 &= ~1;
+                    }
+                }
+            } else {
+                uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, lastBitMask0>>1 );
+                if ( roundNearEven && !(uiZ.v0 & roundBitsMask) ) {
+                    uiZ.v0 &= ~lastBitMask0;
+                }
+            }
+        } else if (
+            roundingMode
+                == (signF128UI64( uiZ.v64 ) ? softfloat_round_min
+                        : softfloat_round_max)
+        ) {
+            uiZ = softfloat_add128( uiZ.v64, uiZ.v0, 0, roundBitsMask );
+        }
+        uiZ.v0 &= ~roundBitsMask;
+        lastBitMask64 = !lastBitMask0;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( exp < 0x3FFF ) {
+            if ( !((uiA64 & UINT64_C( 0x7FFFFFFFFFFFFFFF )) | uiA0) ) return a;
+            if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+            uiZ.v64 = uiA64 & packToF128UI64( 1, 0, 0 );
+            uiZ.v0  = 0;
+            switch ( roundingMode ) {
+             case softfloat_round_near_even:
+                if ( !(fracF128UI64( uiA64 ) | uiA0) ) break;
+             case softfloat_round_near_maxMag:
+                if ( exp == 0x3FFE ) uiZ.v64 |= packToF128UI64( 0, 0x3FFF, 0 );
+                break;
+             case softfloat_round_min:
+                if ( uiZ.v64 ) uiZ.v64 = packToF128UI64( 1, 0x3FFF, 0 );
+                break;
+             case softfloat_round_max:
+                if ( !uiZ.v64 ) uiZ.v64 = packToF128UI64( 0, 0x3FFF, 0 );
+                break;
+#ifdef SOFTFLOAT_ROUND_ODD
+             case softfloat_round_odd:
+                uiZ.v64 |= packToF128UI64( 0, 0x3FFF, 0 );
+                break;
+#endif
+            }
+            goto uiZ;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        uiZ.v64 = uiA64;
+        uiZ.v0  = 0;
+        lastBitMask64 = (uint_fast64_t) 1<<(0x402F - exp);
+        roundBitsMask = lastBitMask64 - 1;
+        if ( roundingMode == softfloat_round_near_maxMag ) {
+            uiZ.v64 += lastBitMask64>>1;
+        } else if ( roundingMode == softfloat_round_near_even ) {
+            uiZ.v64 += lastBitMask64>>1;
+            if ( !((uiZ.v64 & roundBitsMask) | uiA0) ) {
+                uiZ.v64 &= ~lastBitMask64;
+            }
+        } else if (
+            roundingMode
+                == (signF128UI64( uiZ.v64 ) ? softfloat_round_min
+                        : softfloat_round_max)
+        ) {
+            uiZ.v64 = (uiZ.v64 | (uiA0 != 0)) + roundBitsMask;
+        }
+        uiZ.v64 &= ~roundBitsMask;
+        lastBitMask0 = 0;
+    }
+    if ( (uiZ.v64 != uiA64) || (uiZ.v0 != uiA0) ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            uiZ.v64 |= lastBitMask64;
+            uiZ.v0  |= lastBitMask0;
+        }
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_sqrt.c b/addins/SoftFloat-3e/source/f128_sqrt.c
new file mode 100644
index 000000000..f1d9bac79
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_sqrt.c
@@ -0,0 +1,201 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f128_sqrt( float128_t a )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    int_fast32_t expA;
+    struct uint128 sigA, uiZ;
+    struct exp32_sig128 normExpSig;
+    int_fast32_t expZ;
+    uint_fast32_t sig32A, recipSqrt32, sig32Z;
+    struct uint128 rem;
+    uint32_t qs[3];
+    uint_fast32_t q;
+    uint_fast64_t x64, sig64Z;
+    struct uint128 y, term;
+    uint_fast64_t sigZExtra;
+    struct uint128 sigZ;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    expA  = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if ( sigA.v64 | sigA.v0 ) {
+            uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, 0, 0 );
+            goto uiZ;
+        }
+        if ( ! signA ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signA ) {
+        if ( ! (expA | sigA.v64 | sigA.v0) ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! (sigA.v64 | sigA.v0) ) return a;
+        normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    | (`sig32Z' is guaranteed to be a lower bound on the square root of
+    | `sig32A', which makes `sig32Z' also a lower bound on the square root of
+    | `sigA'.)
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x3FFF)>>1) + 0x3FFE;
+    expA &= 1;
+    sigA.v64 |= UINT64_C( 0x0001000000000000 );
+    sig32A = sigA.v64>>17;
+    recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A );
+    sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32;
+    if ( expA ) {
+        sig32Z >>= 1;
+        rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 12 );
+    } else {
+        rem = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 13 );
+    }
+    qs[2] = sig32Z;
+    rem.v64 -= (uint_fast64_t) sig32Z * sig32Z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((uint32_t) (rem.v64>>2) * (uint_fast64_t) recipSqrt32)>>32;
+    x64 = (uint_fast64_t) sig32Z<<32;
+    sig64Z = x64 + ((uint_fast64_t) q<<3);
+    y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        term = softfloat_mul64ByShifted32To128( x64 + sig64Z, q );
+        rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 );
+        if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break;
+        --q;
+        sig64Z -= 1<<3;
+    }
+    qs[1] = q;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = ((rem.v64>>2) * recipSqrt32)>>32;
+    y = softfloat_shortShiftLeft128( rem.v64, rem.v0, 29 );
+    sig64Z <<= 1;
+    /*------------------------------------------------------------------------
+    | (Repeating this loop is a rare occurrence.)
+    *------------------------------------------------------------------------*/
+    for (;;) {
+        term = softfloat_shortShiftLeft128( 0, sig64Z, 32 );
+        term = softfloat_add128( term.v64, term.v0, 0, (uint_fast64_t) q<<6 );
+        term = softfloat_mul128By32( term.v64, term.v0, q );
+        rem = softfloat_sub128( y.v64, y.v0, term.v64, term.v0 );
+        if ( ! (rem.v64 & UINT64_C( 0x8000000000000000 )) ) break;
+        --q;
+    }
+    qs[0] = q;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    q = (((rem.v64>>2) * recipSqrt32)>>32) + 2;
+    sigZExtra = (uint64_t) ((uint_fast64_t) q<<59);
+    term = softfloat_shortShiftLeft128( 0, qs[1], 53 );
+    sigZ =
+        softfloat_add128(
+            (uint_fast64_t) qs[2]<<18, ((uint_fast64_t) qs[0]<<24) + (q>>5),
+            term.v64, term.v0
+        );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (q & 0xF) <= 2 ) {
+        q &= ~3;
+        sigZExtra = (uint64_t) ((uint_fast64_t) q<<59);
+        y = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, 6 );
+        y.v0 |= sigZExtra>>58;
+        term = softfloat_sub128( y.v64, y.v0, 0, q );
+        y    = softfloat_mul64ByShifted32To128( term.v0,  q );
+        term = softfloat_mul64ByShifted32To128( term.v64, q );
+        term = softfloat_add128( term.v64, term.v0, 0, y.v64 );
+        rem = softfloat_shortShiftLeft128( rem.v64, rem.v0, 20 );
+        term = softfloat_sub128( term.v64, term.v0, rem.v64, rem.v0 );
+        /*--------------------------------------------------------------------
+        | The concatenation of `term' and `y.v0' is now the negative remainder
+        | (3 words altogether).
+        *--------------------------------------------------------------------*/
+        if ( term.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            sigZExtra |= 1;
+        } else {
+            if ( term.v64 | term.v0 | y.v0 ) {
+                if ( sigZExtra ) {
+                    --sigZExtra;
+                } else {
+                    sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 );
+                    sigZExtra = ~0;
+                }
+            }
+        }
+    }
+    return softfloat_roundPackToF128( 0, expZ, sigZ.v64, sigZ.v0, sigZExtra );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_sub.c b/addins/SoftFloat-3e/source/f128_sub.c
new file mode 100644
index 000000000..5181cc5ec
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_sub.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t f128_sub( float128_t a, float128_t b )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool signA;
+    union ui128_f128 uB;
+    uint_fast64_t uiB64, uiB0;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float128_t
+        (*magsFuncPtr)(
+            uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    signA = signF128UI64( uiA64 );
+    uB.f = b;
+    uiB64 = uB.ui.v64;
+    uiB0  = uB.ui.v0;
+    signB = signF128UI64( uiB64 );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_subMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    } else {
+        return softfloat_addMagsF128( uiA64, uiA0, uiB64, uiB0, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_subMagsF128 : softfloat_addMagsF128;
+    return (*magsFuncPtr)( uiA64, uiA0, uiB64, uiB0, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_extF80.c b/addins/SoftFloat-3e/source/f128_to_extF80.c
new file mode 100644
index 000000000..ec169c0ff
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_extF80.c
@@ -0,0 +1,109 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t f128_to_extF80( float128_t a )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t frac64, frac0;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    struct exp32_sig128 normExpSig;
+    struct uint128 sig128;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign   = signF128UI64( uiA64 );
+    exp    = expF128UI64( uiA64 );
+    frac64 = fracF128UI64( uiA64 );
+    frac0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 | frac0 ) {
+            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
+            uiZ64 = uiZ.v64;
+            uiZ0  = uiZ.v0;
+        } else {
+            uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+            uiZ0  = UINT64_C( 0x8000000000000000 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! (frac64 | frac0) ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF128Sig( frac64, frac0 );
+        exp   = normExpSig.exp;
+        frac64 = normExpSig.sig.v64;
+        frac0  = normExpSig.sig.v0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig128 =
+        softfloat_shortShiftLeft128(
+            frac64 | UINT64_C( 0x0001000000000000 ), frac0, 15 );
+    return softfloat_roundPackToExtF80( sign, exp, sig128.v64, sig128.v0, 80 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_f16.c b/addins/SoftFloat-3e/source/f128_to_f16.c
new file mode 100644
index 000000000..5a8ee7212
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_f16.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f128_to_f16( float128_t a )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t frac64;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ, frac16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 ) {
+            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac16 = softfloat_shortShiftRightJam64( frac64, 34 );
+    if ( ! (exp | frac16) ) {
+        uiZ = packToF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3FF1;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x40 ) exp = -0x40;
+    }
+    return softfloat_roundPackToF16( sign, exp, frac16 | 0x4000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_f32.c b/addins/SoftFloat-3e/source/f128_to_f32.c
new file mode 100644
index 000000000..07e4a80df
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_f32.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f128_to_f32( float128_t a )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t frac64;
+    struct commonNaN commonNaN;
+    uint_fast32_t uiZ, frac32;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    frac64 = fracF128UI64( uiA64 ) | (uiA0 != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 ) {
+            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac32 = softfloat_shortShiftRightJam64( frac64, 18 );
+    if ( ! (exp | frac32) ) {
+        uiZ = packToF32UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3F81;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return softfloat_roundPackToF32( sign, exp, frac32 | 0x40000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_f64.c b/addins/SoftFloat-3e/source/f128_to_f64.c
new file mode 100644
index 000000000..f791938b4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_f64.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f128_to_f64( float128_t a )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t frac64, frac0;
+    struct commonNaN commonNaN;
+    uint_fast64_t uiZ;
+    struct uint128 frac128;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    frac64 = fracF128UI64( uiA64 );
+    frac0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FFF ) {
+        if ( frac64 | frac0 ) {
+            softfloat_f128UIToCommonNaN( uiA64, uiA0, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac128 = softfloat_shortShiftLeft128( frac64, frac0, 14 );
+    frac64 = frac128.v64 | (frac128.v0 != 0);
+    if ( ! (exp | frac64) ) {
+        uiZ = packToF64UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    exp -= 0x3C01;
+    if ( sizeof (int_fast16_t) < sizeof (int_fast32_t) ) {
+        if ( exp < -0x1000 ) exp = -0x1000;
+    }
+    return
+        softfloat_roundPackToF64(
+            sign, exp, frac64 | UINT64_C( 0x4000000000000000 ) );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_i32.c b/addins/SoftFloat-3e/source/f128_to_i32.c
new file mode 100644
index 000000000..16c4a3ccd
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_i32.c
@@ -0,0 +1,85 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f128_to_i32( float128_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64, sig0;
+    int_fast32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 );
+    sig0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && (sig64 | sig0) ) {
+#if (i32_fromNaN == i32_fromPosOverflow)
+        sign = 0;
+#elif (i32_fromNaN == i32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return i32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+    sig64 |= (sig0 != 0);
+    shiftDist = 0x4023 - exp;
+    if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    return softfloat_roundToI32( sign, sig64, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/f128_to_i32_r_minMag.c
new file mode 100644
index 000000000..18cfeaee5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_i32_r_minMag.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f128_to_i32_r_minMag( float128_t a, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    int_fast32_t exp;
+    uint_fast64_t sig64;
+    int_fast32_t shiftDist;
+    bool sign;
+    int_fast32_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( 49 <= shiftDist ) {
+        if ( exact && (exp | sig64) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF128UI64( uiA64 );
+    if ( shiftDist < 18 ) {
+        if (
+            sign && (shiftDist == 17)
+                && (sig64 < UINT64_C( 0x0000000000020000 ))
+        ) {
+            if ( exact && sig64 ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return -0x7FFFFFFF - 1;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && sig64 ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig64 |= UINT64_C( 0x0001000000000000 );
+    absZ = sig64>>shiftDist;
+    if (
+        exact && ((uint_fast64_t) (uint_fast32_t) absZ<<shiftDist != sig64)
+    ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_i64.c b/addins/SoftFloat-3e/source/f128_to_i64.c
new file mode 100644
index 000000000..f5546604a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_i64.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f128_to_i64( float128_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64, sig0;
+    int_fast32_t shiftDist;
+    struct uint128 sig128;
+    struct uint64_extra sigExtra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 );
+    sig0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( shiftDist <= 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( shiftDist < -15 ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            return
+                (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN
+                    : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        if ( shiftDist ) {
+            sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist );
+            sig64 = sig128.v64;
+            sig0  = sig128.v0;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+        sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist );
+        sig64 = sigExtra.v;
+        sig0  = sigExtra.extra;
+    }
+    return softfloat_roundToI64( sign, sig64, sig0, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/f128_to_i64_r_minMag.c
new file mode 100644
index 000000000..e2cc62e27
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_i64_r_minMag.c
@@ -0,0 +1,113 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f128_to_i64_r_minMag( float128_t a, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64, sig0;
+    int_fast32_t shiftDist;
+    int_fast8_t negShiftDist;
+    int_fast64_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 );
+    sig0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( shiftDist < 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( shiftDist < -14 ) {
+            if (
+                   (uiA64 == UINT64_C( 0xC03E000000000000 ))
+                && (sig0 < UINT64_C( 0x0002000000000000 ))
+            ) {
+                if ( exact && sig0 ) {
+                    softfloat_exceptionFlags |= softfloat_flag_inexact;
+                }
+                return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;
+            }
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            return
+                (exp == 0x7FFF) && (sig64 | sig0) ? i64_fromNaN
+                    : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        negShiftDist = -shiftDist;
+        absZ = sig64<<negShiftDist | sig0>>(shiftDist & 63);
+        if ( exact && (uint64_t) (sig0<<negShiftDist) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( 49 <= shiftDist ) {
+            if ( exact && (exp | sig64 | sig0) ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return 0;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        absZ = sig64>>shiftDist;
+        if ( exact && (sig0 || (absZ<<shiftDist != sig64)) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_ui32.c b/addins/SoftFloat-3e/source/f128_to_ui32.c
new file mode 100644
index 000000000..7d8f3f8a1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_ui32.c
@@ -0,0 +1,86 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t
+ f128_to_ui32( float128_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64;
+    int_fast32_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
+    if ( (exp == 0x7FFF) && sig64 ) {
+#if (ui32_fromNaN == ui32_fromPosOverflow)
+        sign = 0;
+#elif (ui32_fromNaN == ui32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return ui32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+    shiftDist = 0x4023 - exp;
+    if ( 0 < shiftDist ) {
+        sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    }
+    return softfloat_roundToUI32( sign, sig64, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/f128_to_ui32_r_minMag.c
new file mode 100644
index 000000000..92facd517
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_ui32_r_minMag.c
@@ -0,0 +1,89 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f128_to_ui32_r_minMag( float128_t a, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    int_fast32_t exp;
+    uint_fast64_t sig64;
+    int_fast32_t shiftDist;
+    bool sign;
+    uint_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 ) | (uiA0 != 0);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( 49 <= shiftDist ) {
+        if ( exact && (exp | sig64) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF128UI64( uiA64 );
+    if ( sign || (shiftDist < 17) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FFF) && sig64 ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig64 |= UINT64_C( 0x0001000000000000 );
+    z = sig64>>shiftDist;
+    if ( exact && ((uint_fast64_t) z<<shiftDist != sig64) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_ui64.c b/addins/SoftFloat-3e/source/f128_to_ui64.c
new file mode 100644
index 000000000..3c38882ab
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_ui64.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t
+ f128_to_ui64( float128_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64, sig0;
+    int_fast32_t shiftDist;
+    struct uint128 sig128;
+    struct uint64_extra sigExtra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 );
+    sig0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( shiftDist <= 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( shiftDist < -15 ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            return
+                (exp == 0x7FFF) && (sig64 | sig0) ? ui64_fromNaN
+                    : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        if ( shiftDist ) {
+            sig128 = softfloat_shortShiftLeft128( sig64, sig0, -shiftDist );
+            sig64 = sig128.v64;
+            sig0  = sig128.v0;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( exp ) sig64 |= UINT64_C( 0x0001000000000000 );
+        sigExtra = softfloat_shiftRightJam64Extra( sig64, sig0, shiftDist );
+        sig64 = sigExtra.v;
+        sig0  = sigExtra.extra;
+    }
+    return softfloat_roundToUI64( sign, sig64, sig0, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f128_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/f128_to_ui64_r_minMag.c
new file mode 100644
index 000000000..edeafd3c8
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f128_to_ui64_r_minMag.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f128_to_ui64_r_minMag( float128_t a, bool exact )
+{
+    union ui128_f128 uA;
+    uint_fast64_t uiA64, uiA0;
+    bool sign;
+    int_fast32_t exp;
+    uint_fast64_t sig64, sig0;
+    int_fast32_t shiftDist;
+    int_fast8_t negShiftDist;
+    uint_fast64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA64 = uA.ui.v64;
+    uiA0  = uA.ui.v0;
+    sign  = signF128UI64( uiA64 );
+    exp   = expF128UI64( uiA64 );
+    sig64 = fracF128UI64( uiA64 );
+    sig0  = uiA0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x402F - exp;
+    if ( shiftDist < 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( sign || (shiftDist < -15) ) goto invalid;
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        negShiftDist = -shiftDist;
+        z = sig64<<negShiftDist | sig0>>(shiftDist & 63);
+        if ( exact && (uint64_t) (sig0<<negShiftDist) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( 49 <= shiftDist ) {
+            if ( exact && (exp | sig64 | sig0) ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return 0;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( sign ) goto invalid;
+        sig64 |= UINT64_C( 0x0001000000000000 );
+        z = sig64>>shiftDist;
+        if ( exact && (sig0 || (z<<shiftDist != sig64)) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FFF) && (sig64 | sig0) ? ui64_fromNaN
+            : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_add.c b/addins/SoftFloat-3e/source/f16_add.c
new file mode 100644
index 000000000..ff6ec258c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_add.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t f16_add( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1)
+    float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
+    if ( signF16UI( uiA ^ uiB ) ) {
+        return softfloat_subMagsF16( uiA, uiB );
+    } else {
+        return softfloat_addMagsF16( uiA, uiB );
+    }
+#else
+    magsFuncPtr =
+        signF16UI( uiA ^ uiB ) ? softfloat_subMagsF16 : softfloat_addMagsF16;
+    return (*magsFuncPtr)( uiA, uiB );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_div.c b/addins/SoftFloat-3e/source/f16_div.c
new file mode 100644
index 000000000..77f9a2cd2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_div.c
@@ -0,0 +1,186 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extern const uint16_t softfloat_approxRecip_1k0s[];
+extern const uint16_t softfloat_approxRecip_1k1s[];
+
+float16_t f16_div( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool signA;
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signB;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    bool signZ;
+    struct exp8_sig16 normExpSig;
+    int_fast8_t expZ;
+#ifdef SOFTFLOAT_FAST_DIV32TO16
+    uint_fast32_t sig32A;
+    uint_fast16_t sigZ;
+#else
+    int index;
+    uint16_t r0;
+    uint_fast16_t sigZ, rem;
+#endif
+    uint_fast16_t uiZ;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF16UI( uiA );
+    expA  = expF16UI( uiA );
+    sigA  = fracF16UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF16UI( uiB );
+    expB  = expF16UI( uiB );
+    sigB  = fracF16UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x1F ) {
+        if ( sigA ) goto propagateNaN;
+        if ( expB == 0x1F ) {
+            if ( sigB ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0x1F ) {
+        if ( sigB ) goto propagateNaN;
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) {
+            if ( ! (expA | sigA) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF16Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0xE;
+    sigA |= 0x0400;
+    sigB |= 0x0400;
+#ifdef SOFTFLOAT_FAST_DIV32TO16
+    if ( sigA < sigB ) {
+        --expZ;
+        sig32A = (uint_fast32_t) sigA<<15;
+    } else {
+        sig32A = (uint_fast32_t) sigA<<14;
+    }
+    sigZ = sig32A / sigB;
+    if ( ! (sigZ & 7) ) sigZ |= ((uint_fast32_t) sigB * sigZ != sig32A);
+#else
+    if ( sigA < sigB ) {
+        --expZ;
+        sigA <<= 5;
+    } else {
+        sigA <<= 4;
+    }
+    index = sigB>>6 & 0xF;
+    r0 = softfloat_approxRecip_1k0s[index]
+             - (((uint_fast32_t) softfloat_approxRecip_1k1s[index]
+                     * (sigB & 0x3F))
+                    >>10);
+    sigZ = ((uint_fast32_t) sigA * r0)>>16;
+    rem = (sigA<<10) - sigZ * sigB;
+    sigZ += (rem * (uint_fast32_t) r0)>>26;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    ++sigZ;
+    if ( ! (sigZ & 7) ) {
+        sigZ &= ~1;
+        rem = (sigA<<10) - sigZ * sigB;
+        if ( rem & 0x8000 ) {
+            sigZ -= 2;
+        } else {
+            if ( rem ) sigZ |= 1;
+        }
+    }
+#endif
+    return softfloat_roundPackToF16( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF16UI;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ = packToF16UI( signZ, 0x1F, 0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF16UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_eq.c b/addins/SoftFloat-3e/source/f16_eq.c
new file mode 100644
index 000000000..692fa035f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_eq.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f16_eq( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_eq_signaling.c b/addins/SoftFloat-3e/source/f16_eq_signaling.c
new file mode 100644
index 000000000..c1e7a509c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_eq_signaling.c
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f16_eq_signaling( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return (uiA == uiB) || ! (uint16_t) ((uiA | uiB)<<1);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_isSignalingNaN.c b/addins/SoftFloat-3e/source/f16_isSignalingNaN.c
new file mode 100644
index 000000000..3eb3d4cc6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_isSignalingNaN.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f16_isSignalingNaN( float16_t a )
+{
+    union ui16_f16 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF16UI( uA.ui );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_le.c b/addins/SoftFloat-3e/source/f16_le.c
new file mode 100644
index 000000000..d7313debd
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_le.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f16_le( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF16UI( uiA );
+    signB = signF16UI( uiB );
+    return
+        (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1)
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_le_quiet.c b/addins/SoftFloat-3e/source/f16_le_quiet.c
new file mode 100644
index 000000000..15181c260
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_le_quiet.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f16_le_quiet( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF16UI( uiA );
+    signB = signF16UI( uiB );
+    return
+        (signA != signB) ? signA || ! (uint16_t) ((uiA | uiB)<<1)
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_lt.c b/addins/SoftFloat-3e/source/f16_lt.c
new file mode 100644
index 000000000..7745699a2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_lt.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f16_lt( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF16UI( uiA );
+    signB = signF16UI( uiB );
+    return
+        (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0)
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_lt_quiet.c b/addins/SoftFloat-3e/source/f16_lt_quiet.c
new file mode 100644
index 000000000..a31e4a13f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_lt_quiet.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f16_lt_quiet( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF16UI( uiA ) || isNaNF16UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF16UI( uiA ) || softfloat_isSigNaNF16UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF16UI( uiA );
+    signB = signF16UI( uiB );
+    return
+        (signA != signB) ? signA && ((uint16_t) ((uiA | uiB)<<1) != 0)
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_mul.c b/addins/SoftFloat-3e/source/f16_mul.c
new file mode 100644
index 000000000..a47cab8ce
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_mul.c
@@ -0,0 +1,140 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f16_mul( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool signA;
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    bool signB;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    bool signZ;
+    uint_fast16_t magBits;
+    struct exp8_sig16 normExpSig;
+    int_fast8_t expZ;
+    uint_fast32_t sig32Z;
+    uint_fast16_t sigZ, uiZ;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF16UI( uiA );
+    expA  = expF16UI( uiA );
+    sigA  = fracF16UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF16UI( uiB );
+    expB  = expF16UI( uiB );
+    sigB  = fracF16UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x1F ) {
+        if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN;
+        magBits = expB | sigB;
+        goto infArg;
+    }
+    if ( expB == 0x1F ) {
+        if ( sigB ) goto propagateNaN;
+        magBits = expA | sigA;
+        goto infArg;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF16Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zero;
+        normExpSig = softfloat_normSubnormalF16Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0xF;
+    sigA = (sigA | 0x0400)<<4;
+    sigB = (sigB | 0x0400)<<5;
+    sig32Z = (uint_fast32_t) sigA * sigB;
+    sigZ = sig32Z>>16;
+    if ( sig32Z & 0xFFFF ) sigZ |= 1;
+    if ( sigZ < 0x4000 ) {
+        --expZ;
+        sigZ <<= 1;
+    }
+    return softfloat_roundPackToF16( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infArg:
+    if ( ! magBits ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ = defaultNaNF16UI;
+    } else {
+        uiZ = packToF16UI( signZ, 0x1F, 0 );
+    }
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF16UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_mulAdd.c b/addins/SoftFloat-3e/source/f16_mulAdd.c
new file mode 100644
index 000000000..e97571ac5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_mulAdd.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t f16_mulAdd( float16_t a, float16_t b, float16_t c )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    union ui16_f16 uC;
+    uint_fast16_t uiC;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    uC.f = c;
+    uiC = uC.ui;
+    return softfloat_mulAddF16( uiA, uiB, uiC, 0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_rem.c b/addins/SoftFloat-3e/source/f16_rem.c
new file mode 100644
index 000000000..0ffa498a1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_rem.c
@@ -0,0 +1,171 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f16_rem( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool signA;
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    struct exp8_sig16 normExpSig;
+    uint16_t rem;
+    int_fast8_t expDiff;
+    uint_fast16_t q;
+    uint32_t recip32, q32;
+    uint16_t altRem, meanRem;
+    bool signRem;
+    uint_fast16_t uiZ;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF16UI( uiA );
+    expA  = expF16UI( uiA );
+    sigA  = fracF16UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    expB = expF16UI( uiB );
+    sigB = fracF16UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x1F ) {
+        if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN;
+        goto invalid;
+    }
+    if ( expB == 0x1F ) {
+        if ( sigB ) goto propagateNaN;
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalF16Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF16Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    rem = sigA | 0x0400;
+    sigB |= 0x0400;
+    expDiff = expA - expB;
+    if ( expDiff < 1 ) {
+        if ( expDiff < -1 ) return a;
+        sigB <<= 3;
+        if ( expDiff ) {
+            rem <<= 2;
+            q = 0;
+        } else {
+            rem <<= 3;
+            q = (sigB <= rem);
+            if ( q ) rem -= sigB;
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( (uint_fast32_t) sigB<<21 );
+        /*--------------------------------------------------------------------
+        | Changing the shift of `rem' here requires also changing the initial
+        | subtraction from `expDiff'.
+        *--------------------------------------------------------------------*/
+        rem <<= 4;
+        expDiff -= 31;
+        /*--------------------------------------------------------------------
+        | The scale of `sigB' affects how many bits are obtained during each
+        | cycle of the loop.  Currently this is 29 bits per loop iteration,
+        | which is believed to be the maximum possible.
+        *--------------------------------------------------------------------*/
+        sigB <<= 3;
+        for (;;) {
+            q32 = (rem * (uint_fast64_t) recip32)>>16;
+            if ( expDiff < 0 ) break;
+            rem = -((uint_fast16_t) q32 * sigB);
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -30 here.)
+        *--------------------------------------------------------------------*/
+        q32 >>= ~expDiff & 31;
+        q = q32;
+        rem = (rem<<(expDiff + 30)) - q * sigB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    do {
+        altRem = rem;
+        ++q;
+        rem -= sigB;
+    } while ( ! (rem & 0x8000) );
+    meanRem = rem + altRem;
+    if ( (meanRem & 0x8000) || (! meanRem && (q & 1)) ) rem = altRem;
+    signRem = signA;
+    if ( 0x8000 <= rem ) {
+        signRem = ! signRem;
+        rem = -rem;
+    }
+    return softfloat_normRoundPackToF16( signRem, expB, rem );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF16UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_roundToInt.c b/addins/SoftFloat-3e/source/f16_roundToInt.c
new file mode 100644
index 000000000..a567d51d9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_roundToInt.c
@@ -0,0 +1,120 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f16_roundToInt( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast16_t uiZ, lastBitMask, roundBitsMask;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp <= 0xE ) {
+        if ( !(uint16_t) (uiA<<1) ) return a;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        uiZ = uiA & packToF16UI( 1, 0, 0 );
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !fracF16UI( uiA ) ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0xE ) uiZ |= packToF16UI( 0, 0xF, 0 );
+            break;
+         case softfloat_round_min:
+            if ( uiZ ) uiZ = packToF16UI( 1, 0xF, 0 );
+            break;
+         case softfloat_round_max:
+            if ( !uiZ ) uiZ = packToF16UI( 0, 0xF, 0 );
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            uiZ |= packToF16UI( 0, 0xF, 0 );
+            break;
+#endif
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x19 <= exp ) {
+        if ( (exp == 0x1F) && fracF16UI( uiA ) ) {
+            uiZ = softfloat_propagateNaNF16UI( uiA, 0 );
+            goto uiZ;
+        }
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = uiA;
+    lastBitMask = (uint_fast16_t) 1<<(0x19 - exp);
+    roundBitsMask = lastBitMask - 1;
+    if ( roundingMode == softfloat_round_near_maxMag ) {
+        uiZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_near_even ) {
+        uiZ += lastBitMask>>1;
+        if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask;
+    } else if (
+        roundingMode
+            == (signF16UI( uiZ ) ? softfloat_round_min : softfloat_round_max)
+    ) {
+        uiZ += roundBitsMask;
+    }
+    uiZ &= ~roundBitsMask;
+    if ( uiZ != uiA ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_sqrt.c b/addins/SoftFloat-3e/source/f16_sqrt.c
new file mode 100644
index 000000000..47a3bbf14
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_sqrt.c
@@ -0,0 +1,136 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extern const uint16_t softfloat_approxRecipSqrt_1k0s[];
+extern const uint16_t softfloat_approxRecipSqrt_1k1s[];
+
+float16_t f16_sqrt( float16_t a )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool signA;
+    int_fast8_t expA;
+    uint_fast16_t sigA, uiZ;
+    struct exp8_sig16 normExpSig;
+    int_fast8_t expZ;
+    int index;
+    uint_fast16_t r0;
+    uint_fast32_t ESqrR0;
+    uint16_t sigma0;
+    uint_fast16_t recipSqrt16, sigZ, shiftedSigZ;
+    uint16_t negRem;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF16UI( uiA );
+    expA  = expF16UI( uiA );
+    sigA  = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x1F ) {
+        if ( sigA ) {
+            uiZ = softfloat_propagateNaNF16UI( uiA, 0 );
+            goto uiZ;
+        }
+        if ( ! signA ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signA ) {
+        if ( ! (expA | sigA) ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF16Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0xF)>>1) + 0xE;
+    expA &= 1;
+    sigA |= 0x0400;
+    index = (sigA>>6 & 0xE) + expA;
+    r0 = softfloat_approxRecipSqrt_1k0s[index]
+             - (((uint_fast32_t) softfloat_approxRecipSqrt_1k1s[index]
+                     * (sigA & 0x7F))
+                    >>11);
+    ESqrR0 = ((uint_fast32_t) r0 * r0)>>1;
+    if ( expA ) ESqrR0 >>= 1;
+    sigma0 = ~(uint_fast16_t) ((ESqrR0 * sigA)>>16);
+    recipSqrt16 = r0 + (((uint_fast32_t) r0 * sigma0)>>25);
+    if ( ! (recipSqrt16 & 0x8000) ) recipSqrt16 = 0x8000;
+    sigZ = ((uint_fast32_t) (sigA<<5) * recipSqrt16)>>16;
+    if ( expA ) sigZ >>= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    ++sigZ;
+    if ( ! (sigZ & 7) ) {
+        shiftedSigZ = sigZ>>1;
+        negRem = shiftedSigZ * shiftedSigZ;
+        sigZ &= ~1;
+        if ( negRem & 0x8000 ) {
+            sigZ |= 1;
+        } else {
+            if ( negRem ) --sigZ;
+        }
+    }
+    return softfloat_roundPackToF16( 0, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF16UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_sub.c b/addins/SoftFloat-3e/source/f16_sub.c
new file mode 100644
index 000000000..03a87cf32
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_sub.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t f16_sub( float16_t a, float16_t b )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    union ui16_f16 uB;
+    uint_fast16_t uiB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1)
+    float16_t (*magsFuncPtr)( uint_fast16_t, uint_fast16_t );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
+    if ( signF16UI( uiA ^ uiB ) ) {
+        return softfloat_addMagsF16( uiA, uiB );
+    } else {
+        return softfloat_subMagsF16( uiA, uiB );
+    }
+#else
+    magsFuncPtr =
+        signF16UI( uiA ^ uiB ) ? softfloat_addMagsF16 : softfloat_subMagsF16;
+    return (*magsFuncPtr)( uiA, uiB );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_extF80.c b/addins/SoftFloat-3e/source/f16_to_extF80.c
new file mode 100644
index 000000000..99c2dfc74
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t f16_to_extF80( float16_t a )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    struct exp8_sig16 normExpSig;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
+            uiZ64 = uiZ.v64;
+            uiZ0  = uiZ.v0;
+        } else {
+            uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+            uiZ0  = UINT64_C( 0x8000000000000000 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3FF0 );
+    uiZ0  = (uint_fast64_t) (frac | 0x0400)<<53;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_extF80M.c b/addins/SoftFloat-3e/source/f16_to_extF80M.c
new file mode 100644
index 000000000..7f2d53458
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_extF80M.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f16_to_extF80M( float16_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = f16_to_extF80( a );
+
+}
+
+#else
+
+void f16_to_extF80M( float16_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    union ui16_f16 uA;
+    uint16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint16_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ64;
+    uint32_t uiZ32;
+    struct exp8_sig16 normExpSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zSPtr = (struct extFloat80M *) zPtr;
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToExtF80M( &commonNaN, zSPtr );
+            return;
+        }
+        uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+        uiZ32 = 0x80000000;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ32 = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3FF0 );
+    uiZ32 = 0x80000000 | (uint32_t) frac<<21;
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = (uint64_t) uiZ32<<32;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f16_to_f128.c b/addins/SoftFloat-3e/source/f16_to_f128.c
new file mode 100644
index 000000000..c4b81dc84
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_f128.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f16_to_f128( float16_t a )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    struct exp8_sig16 normExpSig;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF128UI( &commonNaN );
+        } else {
+            uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 );
+            uiZ.v0  = 0;
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ.v64 = packToF128UI64( sign, 0, 0 );
+            uiZ.v0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ.v64 = packToF128UI64( sign, exp + 0x3FF0, (uint_fast64_t) frac<<38 );
+    uiZ.v0  = 0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_f128M.c b/addins/SoftFloat-3e/source/f16_to_f128M.c
new file mode 100644
index 000000000..b4fc873b5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_f128M.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f16_to_f128M( float16_t a, float128_t *zPtr )
+{
+
+    *zPtr = f16_to_f128( a );
+
+}
+
+#else
+
+void f16_to_f128M( float16_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr;
+    union ui16_f16 uA;
+    uint16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint16_t frac;
+    struct commonNaN commonNaN;
+    uint32_t uiZ96;
+    struct exp8_sig16 normExpSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToF128M( &commonNaN, zWPtr );
+            return;
+        }
+        uiZ96 = packToF128UI96( sign, 0x7FFF, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ96 = packToF128UI96( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ96 = packToF128UI96( sign, exp + 0x3FF0, (uint32_t) frac<<6 );
+ uiZ:
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f16_to_f32.c b/addins/SoftFloat-3e/source/f16_to_f32.c
new file mode 100644
index 000000000..a219454bf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_f32.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f16_to_f32( float16_t a )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    struct commonNaN commonNaN;
+    uint_fast32_t uiZ;
+    struct exp8_sig16 normExpSig;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ = packToF32UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = packToF32UI( sign, exp + 0x70, (uint_fast32_t) frac<<13 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_f64.c b/addins/SoftFloat-3e/source/f16_to_f64.c
new file mode 100644
index 000000000..7e87c25f4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_f64.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f16_to_f64( float16_t a )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    struct commonNaN commonNaN;
+    uint_fast64_t uiZ;
+    struct exp8_sig16 normExpSig;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        if ( frac ) {
+            softfloat_f16UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ = packToF64UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = packToF64UI( sign, exp + 0x3F0, (uint_fast64_t) frac<<42 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_i32.c b/addins/SoftFloat-3e/source/f16_to_i32.c
new file mode 100644
index 000000000..805c4e550
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_i32.c
@@ -0,0 +1,87 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f16_to_i32( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast32_t sig32;
+    int_fast8_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            frac ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = frac;
+    if ( exp ) {
+        sig32 |= 0x0400;
+        shiftDist = exp - 0x19;
+        if ( 0 <= shiftDist ) {
+            sig32 <<= shiftDist;
+            return sign ? -sig32 : sig32;
+        }
+        shiftDist = exp - 0x0D;
+        if ( 0 < shiftDist ) sig32 <<= shiftDist;
+    }
+    return
+        softfloat_roundToI32(
+            sign, (uint_fast32_t) sig32, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/f16_to_i32_r_minMag.c
new file mode 100644
index 000000000..b1f996371
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_i32_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f16_to_i32_r_minMag( float16_t a, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast8_t shiftDist;
+    bool sign;
+    int_fast32_t alignedSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = exp - 0x0F;
+    if ( shiftDist < 0 ) {
+        if ( exact && (exp | frac) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF16UI( uiA );
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x1F) && frac ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    alignedSig = (int_fast32_t) (frac | 0x0400)<<shiftDist;
+    if ( exact && (alignedSig & 0x3FF) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    alignedSig >>= 10;
+    return sign ? -alignedSig : alignedSig;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_i64.c b/addins/SoftFloat-3e/source/f16_to_i64.c
new file mode 100644
index 000000000..e3c0065f6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_i64.c
@@ -0,0 +1,87 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f16_to_i64( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast32_t sig32;
+    int_fast8_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            frac ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = frac;
+    if ( exp ) {
+        sig32 |= 0x0400;
+        shiftDist = exp - 0x19;
+        if ( 0 <= shiftDist ) {
+            sig32 <<= shiftDist;
+            return sign ? -sig32 : sig32;
+        }
+        shiftDist = exp - 0x0D;
+        if ( 0 < shiftDist ) sig32 <<= shiftDist;
+    }
+    return
+        softfloat_roundToI32(
+            sign, (uint_fast32_t) sig32, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/f16_to_i64_r_minMag.c
new file mode 100644
index 000000000..a5a6a077e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_i64_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f16_to_i64_r_minMag( float16_t a, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast8_t shiftDist;
+    bool sign;
+    int_fast32_t alignedSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = exp - 0x0F;
+    if ( shiftDist < 0 ) {
+        if ( exact && (exp | frac) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF16UI( uiA );
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x1F) && frac ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    alignedSig = (int_fast32_t) (frac | 0x0400)<<shiftDist;
+    if ( exact && (alignedSig & 0x3FF) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    alignedSig >>= 10;
+    return sign ? -alignedSig : alignedSig;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_ui32.c b/addins/SoftFloat-3e/source/f16_to_ui32.c
new file mode 100644
index 000000000..5371ca339
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_ui32.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f16_to_ui32( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    uint_fast32_t sig32;
+    int_fast8_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            frac ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = frac;
+    if ( exp ) {
+        sig32 |= 0x0400;
+        shiftDist = exp - 0x19;
+        if ( (0 <= shiftDist) && ! sign ) {
+            return sig32<<shiftDist;
+        }
+        shiftDist = exp - 0x0D;
+        if ( 0 < shiftDist ) sig32 <<= shiftDist;
+    }
+    return softfloat_roundToUI32( sign, sig32, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/f16_to_ui32_r_minMag.c
new file mode 100644
index 000000000..5d51df5ec
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_ui32_r_minMag.c
@@ -0,0 +1,87 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f16_to_ui32_r_minMag( float16_t a, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast8_t shiftDist;
+    bool sign;
+    uint_fast32_t alignedSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = exp - 0x0F;
+    if ( shiftDist < 0 ) {
+        if ( exact && (exp | frac) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF16UI( uiA );
+    if ( sign || (exp == 0x1F) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x1F) && frac ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    alignedSig = (uint_fast32_t) (frac | 0x0400)<<shiftDist;
+    if ( exact && (alignedSig & 0x3FF) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return alignedSig>>10;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_ui64.c b/addins/SoftFloat-3e/source/f16_to_ui64.c
new file mode 100644
index 000000000..e6cb000f1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_ui64.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f16_to_ui64( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    bool sign;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    uint_fast32_t sig32;
+    int_fast8_t shiftDist;
+#ifndef SOFTFLOAT_FAST_INT64
+    uint32_t extSig[3];
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF16UI( uiA );
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x1F ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            frac ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig32 = frac;
+    if ( exp ) {
+        sig32 |= 0x0400;
+        shiftDist = exp - 0x19;
+        if ( (0 <= shiftDist) && ! sign ) {
+            return sig32<<shiftDist;
+        }
+        shiftDist = exp - 0x0D;
+        if ( 0 < shiftDist ) sig32 <<= shiftDist;
+    }
+#ifdef SOFTFLOAT_FAST_INT64
+    return
+        softfloat_roundToUI64(
+            sign, sig32>>12, (uint_fast64_t) sig32<<52, roundingMode, exact );
+#else
+    extSig[indexWord( 3, 2 )] = 0;
+    extSig[indexWord( 3, 1 )] = sig32>>12;
+    extSig[indexWord( 3, 0 )] = sig32<<20;
+    return softfloat_roundMToUI64( sign, extSig, roundingMode, exact );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f16_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/f16_to_ui64_r_minMag.c
new file mode 100644
index 000000000..b4f975f83
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f16_to_ui64_r_minMag.c
@@ -0,0 +1,87 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f16_to_ui64_r_minMag( float16_t a, bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast16_t frac;
+    int_fast8_t shiftDist;
+    bool sign;
+    uint_fast32_t alignedSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp  = expF16UI( uiA );
+    frac = fracF16UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = exp - 0x0F;
+    if ( shiftDist < 0 ) {
+        if ( exact && (exp | frac) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF16UI( uiA );
+    if ( sign || (exp == 0x1F) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x1F) && frac ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    alignedSig = (uint_fast32_t) (frac | 0x0400)<<shiftDist;
+    if ( exact && (alignedSig & 0x3FF) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return alignedSig>>10;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_add.c b/addins/SoftFloat-3e/source/f32_add.c
new file mode 100644
index 000000000..70e03e7f9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_add.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t f32_add( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1)
+    float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
+    if ( signF32UI( uiA ^ uiB ) ) {
+        return softfloat_subMagsF32( uiA, uiB );
+    } else {
+        return softfloat_addMagsF32( uiA, uiB );
+    }
+#else
+    magsFuncPtr =
+        signF32UI( uiA ^ uiB ) ? softfloat_subMagsF32 : softfloat_addMagsF32;
+    return (*magsFuncPtr)( uiA, uiB );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_div.c b/addins/SoftFloat-3e/source/f32_div.c
new file mode 100644
index 000000000..05ec701f7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_div.c
@@ -0,0 +1,180 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_div( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    bool signZ;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expZ;
+#ifdef SOFTFLOAT_FAST_DIV64TO32
+    uint_fast64_t sig64A;
+    uint_fast32_t sigZ;
+#else
+    uint_fast32_t sigZ;
+    uint_fast64_t rem;
+#endif
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA  = expF32UI( uiA );
+    sigA  = fracF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF32UI( uiB );
+    expB  = expF32UI( uiB );
+    sigB  = fracF32UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0xFF ) {
+        if ( sigA ) goto propagateNaN;
+        if ( expB == 0xFF ) {
+            if ( sigB ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) {
+            if ( ! (expA | sigA) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x7E;
+    sigA |= 0x00800000;
+    sigB |= 0x00800000;
+#ifdef SOFTFLOAT_FAST_DIV64TO32
+    if ( sigA < sigB ) {
+        --expZ;
+        sig64A = (uint_fast64_t) sigA<<31;
+    } else {
+        sig64A = (uint_fast64_t) sigA<<30;
+    }
+    sigZ = sig64A / sigB;
+    if ( ! (sigZ & 0x3F) ) sigZ |= ((uint_fast64_t) sigB * sigZ != sig64A);
+#else
+    if ( sigA < sigB ) {
+        --expZ;
+        sigA <<= 8;
+    } else {
+        sigA <<= 7;
+    }
+    sigB <<= 8;
+    sigZ = ((uint_fast64_t) sigA * softfloat_approxRecip32_1( sigB ))>>32;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigZ += 2;
+    if ( (sigZ & 0x3F) < 2 ) {
+        sigZ &= ~3;
+#ifdef SOFTFLOAT_FAST_INT64
+        rem = ((uint_fast64_t) sigA<<31) - (uint_fast64_t) sigZ * sigB;
+#else
+        rem = ((uint_fast64_t) sigA<<32) - (uint_fast64_t) (sigZ<<1) * sigB;
+#endif
+        if ( rem & UINT64_C( 0x8000000000000000 ) ) {
+            sigZ -= 4;
+        } else {
+            if ( rem ) sigZ |= 1;
+        }
+    }
+#endif
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ = packToF32UI( signZ, 0xFF, 0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF32UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_eq.c b/addins/SoftFloat-3e/source/f32_eq.c
new file mode 100644
index 000000000..801bbfd73
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_eq.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_eq( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_eq_signaling.c b/addins/SoftFloat-3e/source/f32_eq_signaling.c
new file mode 100644
index 000000000..4c610ffae
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_eq_signaling.c
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_eq_signaling( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return (uiA == uiB) || ! (uint32_t) ((uiA | uiB)<<1);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_isSignalingNaN.c b/addins/SoftFloat-3e/source/f32_isSignalingNaN.c
new file mode 100644
index 000000000..f5954cbbc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_isSignalingNaN.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_isSignalingNaN( float32_t a )
+{
+    union ui32_f32 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF32UI( uA.ui );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_le.c b/addins/SoftFloat-3e/source/f32_le.c
new file mode 100644
index 000000000..d89d1e88d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_le.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_le( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1)
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_le_quiet.c b/addins/SoftFloat-3e/source/f32_le_quiet.c
new file mode 100644
index 000000000..c2d4297a2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_le_quiet.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_le_quiet( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        (signA != signB) ? signA || ! (uint32_t) ((uiA | uiB)<<1)
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_lt.c b/addins/SoftFloat-3e/source/f32_lt.c
new file mode 100644
index 000000000..5b5fd2282
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_lt.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_lt( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0)
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_lt_quiet.c b/addins/SoftFloat-3e/source/f32_lt_quiet.c
new file mode 100644
index 000000000..015388143
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_lt_quiet.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_lt_quiet( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF32UI( uiA ) || isNaNF32UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        (signA != signB) ? signA && ((uint32_t) ((uiA | uiB)<<1) != 0)
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_mul.c b/addins/SoftFloat-3e/source/f32_mul.c
new file mode 100644
index 000000000..f5c856002
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_mul.c
@@ -0,0 +1,137 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_mul( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    bool signZ;
+    uint_fast32_t magBits;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ, uiZ;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA  = expF32UI( uiA );
+    sigA  = fracF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF32UI( uiB );
+    expB  = expF32UI( uiB );
+    sigB  = fracF32UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0xFF ) {
+        if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN;
+        magBits = expB | sigB;
+        goto infArg;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        magBits = expA | sigA;
+        goto infArg;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zero;
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x7F;
+    sigA = (sigA | 0x00800000)<<7;
+    sigB = (sigB | 0x00800000)<<8;
+    sigZ = softfloat_shortShiftRightJam64( (uint_fast64_t) sigA * sigB, 32 );
+    if ( sigZ < 0x40000000 ) {
+        --expZ;
+        sigZ <<= 1;
+    }
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infArg:
+    if ( ! magBits ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ = defaultNaNF32UI;
+    } else {
+        uiZ = packToF32UI( signZ, 0xFF, 0 );
+    }
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF32UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_mulAdd.c b/addins/SoftFloat-3e/source/f32_mulAdd.c
new file mode 100644
index 000000000..9a28e212c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_mulAdd.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t f32_mulAdd( float32_t a, float32_t b, float32_t c )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    union ui32_f32 uC;
+    uint_fast32_t uiC;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    uC.f = c;
+    uiC = uC.ui;
+    return softfloat_mulAddF32( uiA, uiB, uiC, 0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_rem.c b/addins/SoftFloat-3e/source/f32_rem.c
new file mode 100644
index 000000000..b29bf416e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_rem.c
@@ -0,0 +1,168 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_rem( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    struct exp16_sig32 normExpSig;
+    uint32_t rem;
+    int_fast16_t expDiff;
+    uint32_t q, recip32, altRem, meanRem;
+    bool signRem;
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA  = expF32UI( uiA );
+    sigA  = fracF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0xFF ) {
+        if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN;
+        goto invalid;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    rem = sigA | 0x00800000;
+    sigB |= 0x00800000;
+    expDiff = expA - expB;
+    if ( expDiff < 1 ) {
+        if ( expDiff < -1 ) return a;
+        sigB <<= 6;
+        if ( expDiff ) {
+            rem <<= 5;
+            q = 0;
+        } else {
+            rem <<= 6;
+            q = (sigB <= rem);
+            if ( q ) rem -= sigB;
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( sigB<<8 );
+        /*--------------------------------------------------------------------
+        | Changing the shift of `rem' here requires also changing the initial
+        | subtraction from `expDiff'.
+        *--------------------------------------------------------------------*/
+        rem <<= 7;
+        expDiff -= 31;
+        /*--------------------------------------------------------------------
+        | The scale of `sigB' affects how many bits are obtained during each
+        | cycle of the loop.  Currently this is 29 bits per loop iteration,
+        | which is believed to be the maximum possible.
+        *--------------------------------------------------------------------*/
+        sigB <<= 6;
+        for (;;) {
+            q = (rem * (uint_fast64_t) recip32)>>32;
+            if ( expDiff < 0 ) break;
+            rem = -(q * (uint32_t) sigB);
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -30 here.)
+        *--------------------------------------------------------------------*/
+        q >>= ~expDiff & 31;
+        rem = (rem<<(expDiff + 30)) - q * (uint32_t) sigB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    do {
+        altRem = rem;
+        ++q;
+        rem -= sigB;
+    } while ( ! (rem & 0x80000000) );
+    meanRem = rem + altRem;
+    if ( (meanRem & 0x80000000) || (! meanRem && (q & 1)) ) rem = altRem;
+    signRem = signA;
+    if ( 0x80000000 <= rem ) {
+        signRem = ! signRem;
+        rem = -rem;
+    }
+    return softfloat_normRoundPackToF32( signRem, expB, rem );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_roundToInt.c b/addins/SoftFloat-3e/source/f32_roundToInt.c
new file mode 100644
index 000000000..305af79dd
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_roundToInt.c
@@ -0,0 +1,120 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_roundToInt( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast32_t uiZ, lastBitMask, roundBitsMask;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp <= 0x7E ) {
+        if ( !(uint32_t) (uiA<<1) ) return a;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        uiZ = uiA & packToF32UI( 1, 0, 0 );
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !fracF32UI( uiA ) ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0x7E ) uiZ |= packToF32UI( 0, 0x7F, 0 );
+            break;
+         case softfloat_round_min:
+            if ( uiZ ) uiZ = packToF32UI( 1, 0x7F, 0 );
+            break;
+         case softfloat_round_max:
+            if ( !uiZ ) uiZ = packToF32UI( 0, 0x7F, 0 );
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            uiZ |= packToF32UI( 0, 0x7F, 0 );
+            break;
+#endif
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x96 <= exp ) {
+        if ( (exp == 0xFF) && fracF32UI( uiA ) ) {
+            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );
+            goto uiZ;
+        }
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = uiA;
+    lastBitMask = (uint_fast32_t) 1<<(0x96 - exp);
+    roundBitsMask = lastBitMask - 1;
+    if ( roundingMode == softfloat_round_near_maxMag ) {
+        uiZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_near_even ) {
+        uiZ += lastBitMask>>1;
+        if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask;
+    } else if (
+        roundingMode
+            == (signF32UI( uiZ ) ? softfloat_round_min : softfloat_round_max)
+    ) {
+        uiZ += roundBitsMask;
+    }
+    uiZ &= ~roundBitsMask;
+    if ( uiZ != uiA ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_sqrt.c b/addins/SoftFloat-3e/source/f32_sqrt.c
new file mode 100644
index 000000000..9263bde59
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_sqrt.c
@@ -0,0 +1,121 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_sqrt( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA, uiZ;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ, shiftedSigZ;
+    uint32_t negRem;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA  = expF32UI( uiA );
+    sigA  = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0xFF ) {
+        if ( sigA ) {
+            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );
+            goto uiZ;
+        }
+        if ( ! signA ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signA ) {
+        if ( ! (expA | sigA) ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x7F)>>1) + 0x7E;
+    expA &= 1;
+    sigA = (sigA | 0x00800000)<<8;
+    sigZ =
+        ((uint_fast64_t) sigA * softfloat_approxRecipSqrt32_1( expA, sigA ))
+            >>32;
+    if ( expA ) sigZ >>= 1;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sigZ += 2;
+    if ( (sigZ & 0x3F) < 2 ) {
+        shiftedSigZ = sigZ>>2;
+        negRem = shiftedSigZ * shiftedSigZ;
+        sigZ &= ~3;
+        if ( negRem & 0x80000000 ) {
+            sigZ |= 1;
+        } else {
+            if ( negRem ) --sigZ;
+        }
+    }
+    return softfloat_roundPackToF32( 0, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_sub.c b/addins/SoftFloat-3e/source/f32_sub.c
new file mode 100644
index 000000000..383484dae
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_sub.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t f32_sub( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 1)
+    float32_t (*magsFuncPtr)( uint_fast32_t, uint_fast32_t );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
+    if ( signF32UI( uiA ^ uiB ) ) {
+        return softfloat_addMagsF32( uiA, uiB );
+    } else {
+        return softfloat_subMagsF32( uiA, uiB );
+    }
+#else
+    magsFuncPtr =
+        signF32UI( uiA ^ uiB ) ? softfloat_addMagsF32 : softfloat_subMagsF32;
+    return (*magsFuncPtr)( uiA, uiB );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_extF80.c b/addins/SoftFloat-3e/source/f32_to_extF80.c
new file mode 100644
index 000000000..742ed649c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t f32_to_extF80( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    struct exp16_sig32 normExpSig;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
+            uiZ64 = uiZ.v64;
+            uiZ0  = uiZ.v0;
+        } else {
+            uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+            uiZ0  = UINT64_C( 0x8000000000000000 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3F80 );
+    uiZ0  = (uint_fast64_t) (frac | 0x00800000)<<40;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_extF80M.c b/addins/SoftFloat-3e/source/f32_to_extF80M.c
new file mode 100644
index 000000000..af7e32a76
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_extF80M.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f32_to_extF80M( float32_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = f32_to_extF80( a );
+
+}
+
+#else
+
+void f32_to_extF80M( float32_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    union ui32_f32 uA;
+    uint32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint32_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ64;
+    uint32_t uiZ32;
+    struct exp16_sig32 normExpSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zSPtr = (struct extFloat80M *) zPtr;
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToExtF80M( &commonNaN, zSPtr );
+            return;
+        }
+        uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+        uiZ32 = 0x80000000;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ32 = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3F80 );
+    uiZ32 = 0x80000000 | (uint32_t) frac<<8;
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = (uint64_t) uiZ32<<32;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f32_to_f128.c b/addins/SoftFloat-3e/source/f32_to_f128.c
new file mode 100644
index 000000000..6a765a44e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_f128.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f32_to_f128( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    struct exp16_sig32 normExpSig;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF128UI( &commonNaN );
+        } else {
+            uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 );
+            uiZ.v0  = 0;
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ.v64 = packToF128UI64( sign, 0, 0 );
+            uiZ.v0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ.v64 = packToF128UI64( sign, exp + 0x3F80, (uint_fast64_t) frac<<25 );
+    uiZ.v0  = 0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_f128M.c b/addins/SoftFloat-3e/source/f32_to_f128M.c
new file mode 100644
index 000000000..ee7e6b367
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_f128M.c
@@ -0,0 +1,115 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f32_to_f128M( float32_t a, float128_t *zPtr )
+{
+
+    *zPtr = f32_to_f128( a );
+
+}
+
+#else
+
+void f32_to_f128M( float32_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr;
+    union ui32_f32 uA;
+    uint32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint32_t frac, uiZ64;
+    struct commonNaN commonNaN;
+    uint32_t uiZ96;
+    struct exp16_sig32 normExpSig;
+    uint64_t frac64;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = 0;
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToF128M( &commonNaN, zWPtr );
+            return;
+        }
+        uiZ96 = packToF128UI96( sign, 0x7FFF, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ96 = packToF128UI96( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac64 = (uint64_t) frac<<25;
+    uiZ96 = packToF128UI96( sign, exp + 0x3F80, frac64>>32 );
+    uiZ64 = frac64;
+ uiZ:
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = uiZ64;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f32_to_f16.c b/addins/SoftFloat-3e/source/f32_to_f16.c
new file mode 100644
index 000000000..a9e77b775
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_f16.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f32_to_f16( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ, frac16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac16 = frac>>9 | ((frac & 0x1FF) != 0);
+    if ( ! (exp | frac16) ) {
+        uiZ = packToF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    return softfloat_roundPackToF16( sign, exp - 0x71, frac16 | 0x4000 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_f64.c b/addins/SoftFloat-3e/source/f32_to_f64.c
new file mode 100644
index 000000000..4f97519e8
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_f64.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f32_to_f64( float32_t a )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t frac;
+    struct commonNaN commonNaN;
+    uint_fast64_t uiZ;
+    struct exp16_sig32 normExpSig;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    frac = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0xFF ) {
+        if ( frac ) {
+            softfloat_f32UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF64UI( &commonNaN );
+        } else {
+            uiZ = packToF64UI( sign, 0x7FF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ = packToF64UI( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = packToF64UI( sign, exp + 0x380, (uint_fast64_t) frac<<29 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_i32.c b/addins/SoftFloat-3e/source/f32_to_i32.c
new file mode 100644
index 000000000..7d0356fbe
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_i32.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f32_to_i32( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    uint_fast64_t sig64;
+    int_fast16_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    sig  = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
+    if ( (exp == 0xFF) && sig ) {
+#if (i32_fromNaN == i32_fromPosOverflow)
+        sign = 0;
+#elif (i32_fromNaN == i32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return i32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= 0x00800000;
+    sig64 = (uint_fast64_t) sig<<32;
+    shiftDist = 0xAA - exp;
+    if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    return softfloat_roundToI32( sign, sig64, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/f32_to_i32_r_minMag.c
new file mode 100644
index 000000000..7652f2ebb
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_i32_r_minMag.c
@@ -0,0 +1,89 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f32_to_i32_r_minMag( float32_t a, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    int_fast32_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF32UI( uiA );
+    sig = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x9E - exp;
+    if ( 32 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF32UI( uiA );
+    if ( shiftDist <= 0 ) {
+        if ( uiA == packToF32UI( 1, 0x9E, 0 ) ) return -0x7FFFFFFF - 1;
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig | 0x00800000)<<8;
+    absZ = sig>>shiftDist;
+    if ( exact && ((uint_fast32_t) absZ<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_i64.c b/addins/SoftFloat-3e/source/f32_to_i64.c
new file mode 100644
index 000000000..4b125441f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_i64.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f32_to_i64( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+#ifdef SOFTFLOAT_FAST_INT64
+    uint_fast64_t sig64, extra;
+    struct uint64_extra sig64Extra;
+#else
+    uint32_t extSig[3];
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    sig  = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0xBE - exp;
+    if ( shiftDist < 0 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= 0x00800000;
+#ifdef SOFTFLOAT_FAST_INT64
+    sig64 = (uint_fast64_t) sig<<40;
+    extra = 0;
+    if ( shiftDist ) {
+        sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist );
+        sig64 = sig64Extra.v;
+        extra = sig64Extra.extra;
+    }
+    return softfloat_roundToI64( sign, sig64, extra, roundingMode, exact );
+#else
+    extSig[indexWord( 3, 2 )] = sig<<8;
+    extSig[indexWord( 3, 1 )] = 0;
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    return softfloat_roundMToI64( sign, extSig, roundingMode, exact );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/f32_to_i64_r_minMag.c
new file mode 100644
index 000000000..397ddf6d0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_i64_r_minMag.c
@@ -0,0 +1,94 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f32_to_i64_r_minMag( float32_t a, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    uint_fast64_t sig64;
+    int_fast64_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF32UI( uiA );
+    sig = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0xBE - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF32UI( uiA );
+    if ( shiftDist <= 0 ) {
+        if ( uiA == packToF32UI( 1, 0xBE, 0 ) ) {
+            return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? i64_fromNaN
+                : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig |= 0x00800000;
+    sig64 = (uint_fast64_t) sig<<40;
+    absZ = sig64>>shiftDist;
+    shiftDist = 40 - shiftDist;
+    if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_ui32.c b/addins/SoftFloat-3e/source/f32_to_ui32.c
new file mode 100644
index 000000000..cb47d9458
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_ui32.c
@@ -0,0 +1,84 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f32_to_ui32( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    uint_fast64_t sig64;
+    int_fast16_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    sig  = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
+    if ( (exp == 0xFF) && sig ) {
+#if (ui32_fromNaN == ui32_fromPosOverflow)
+        sign = 0;
+#elif (ui32_fromNaN == ui32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return ui32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= 0x00800000;
+    sig64 = (uint_fast64_t) sig<<32;
+    shiftDist = 0xAA - exp;
+    if ( 0 < shiftDist ) sig64 = softfloat_shiftRightJam64( sig64, shiftDist );
+    return softfloat_roundToUI32( sign, sig64, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/f32_to_ui32_r_minMag.c
new file mode 100644
index 000000000..cdeb75f9f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_ui32_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f32_to_ui32_r_minMag( float32_t a, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    uint_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF32UI( uiA );
+    sig = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x9E - exp;
+    if ( 32 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF32UI( uiA );
+    if ( sign || (shiftDist < 0) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig | 0x00800000)<<8;
+    z = sig>>shiftDist;
+    if ( exact && (z<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_ui64.c b/addins/SoftFloat-3e/source/f32_to_ui64.c
new file mode 100644
index 000000000..61f204af7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_ui64.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f32_to_ui64( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+#ifdef SOFTFLOAT_FAST_INT64
+    uint_fast64_t sig64, extra;
+    struct uint64_extra sig64Extra;
+#else
+    uint32_t extSig[3];
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF32UI( uiA );
+    exp  = expF32UI( uiA );
+    sig  = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0xBE - exp;
+    if ( shiftDist < 0 ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= 0x00800000;
+#ifdef SOFTFLOAT_FAST_INT64
+    sig64 = (uint_fast64_t) sig<<40;
+    extra = 0;
+    if ( shiftDist ) {
+        sig64Extra = softfloat_shiftRightJam64Extra( sig64, 0, shiftDist );
+        sig64 = sig64Extra.v;
+        extra = sig64Extra.extra;
+    }
+    return softfloat_roundToUI64( sign, sig64, extra, roundingMode, exact );
+#else
+    extSig[indexWord( 3, 2 )] = sig<<8;
+    extSig[indexWord( 3, 1 )] = 0;
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist ) softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    return softfloat_roundMToUI64( sign, extSig, roundingMode, exact );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f32_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/f32_to_ui64_r_minMag.c
new file mode 100644
index 000000000..c0fe54f6e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f32_to_ui64_r_minMag.c
@@ -0,0 +1,90 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f32_to_ui64_r_minMag( float32_t a, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast32_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    uint_fast64_t sig64, z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF32UI( uiA );
+    sig = fracF32UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0xBE - exp;
+    if ( 64 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF32UI( uiA );
+    if ( sign || (shiftDist < 0) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0xFF) && sig ? ui64_fromNaN
+                : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig |= 0x00800000;
+    sig64 = (uint_fast64_t) sig<<40;
+    z = sig64>>shiftDist;
+    shiftDist = 40 - shiftDist;
+    if ( exact && (shiftDist < 0) && (uint32_t) (sig<<(shiftDist & 31)) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_add.c b/addins/SoftFloat-3e/source/f64_add.c
new file mode 100644
index 000000000..42f840dc5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_add.c
@@ -0,0 +1,74 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t f64_add( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_addMagsF64( uiA, uiB, signA );
+    } else {
+        return softfloat_subMagsF64( uiA, uiB, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_addMagsF64 : softfloat_subMagsF64;
+    return (*magsFuncPtr)( uiA, uiB, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_div.c b/addins/SoftFloat-3e/source/f64_div.c
new file mode 100644
index 000000000..9c967bb74
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_div.c
@@ -0,0 +1,172 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_div( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    bool signZ;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+    uint32_t recip32, sig32Z, doubleTerm;
+    uint_fast64_t rem;
+    uint32_t q;
+    uint_fast64_t sigZ;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    expB  = expF64UI( uiB );
+    sigB  = fracF64UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA ) goto propagateNaN;
+        if ( expB == 0x7FF ) {
+            if ( sigB ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        goto zero;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) {
+            if ( ! (expA | sigA) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinite );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA - expB + 0x3FE;
+    sigA |= UINT64_C( 0x0010000000000000 );
+    sigB |= UINT64_C( 0x0010000000000000 );
+    if ( sigA < sigB ) {
+        --expZ;
+        sigA <<= 11;
+    } else {
+        sigA <<= 10;
+    }
+    sigB <<= 11;
+    recip32 = softfloat_approxRecip32_1( sigB>>32 ) - 2;
+    sig32Z = ((uint32_t) (sigA>>32) * (uint_fast64_t) recip32)>>32;
+    doubleTerm = sig32Z<<1;
+    rem =
+        ((sigA - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28)
+            - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4);
+    q = (((uint32_t) (rem>>32) * (uint_fast64_t) recip32)>>32) + 4;
+    sigZ = ((uint_fast64_t) sig32Z<<32) + ((uint_fast64_t) q<<4);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (sigZ & 0x1FF) < 4<<4 ) {
+        q &= ~7;
+        sigZ &= ~(uint_fast64_t) 0x7F;
+        doubleTerm = q<<1;
+        rem =
+            ((rem - (uint_fast64_t) doubleTerm * (uint32_t) (sigB>>32))<<28)
+                - (uint_fast64_t) doubleTerm * ((uint32_t) sigB>>4);
+        if ( rem & UINT64_C( 0x8000000000000000 ) ) {
+            sigZ -= 1<<7;
+        } else {
+            if ( rem ) sigZ |= 1;
+        }
+    }
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infinity:
+    uiZ = packToF64UI( signZ, 0x7FF, 0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF64UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_eq.c b/addins/SoftFloat-3e/source/f64_eq.c
new file mode 100644
index 000000000..360200379
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_eq.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_eq( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_eq_signaling.c b/addins/SoftFloat-3e/source/f64_eq_signaling.c
new file mode 100644
index 000000000..5daa17937
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_eq_signaling.c
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_eq_signaling( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return (uiA == uiB) || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_isSignalingNaN.c b/addins/SoftFloat-3e/source/f64_isSignalingNaN.c
new file mode 100644
index 000000000..e5d38321e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_isSignalingNaN.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_isSignalingNaN( float64_t a )
+{
+    union ui64_f64 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF64UI( uA.ui );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_le.c b/addins/SoftFloat-3e/source/f64_le.c
new file mode 100644
index 000000000..0b43d0467
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_le.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_le( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        (signA != signB)
+            ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_le_quiet.c b/addins/SoftFloat-3e/source/f64_le_quiet.c
new file mode 100644
index 000000000..832eee7a7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_le_quiet.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_le_quiet( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        (signA != signB)
+            ? signA || ! ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            : (uiA == uiB) || (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_lt.c b/addins/SoftFloat-3e/source/f64_lt.c
new file mode 100644
index 000000000..49ee05be0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_lt.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_lt( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        (signA != signB)
+            ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_lt_quiet.c b/addins/SoftFloat-3e/source/f64_lt_quiet.c
new file mode 100644
index 000000000..d64088054
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_lt_quiet.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_lt_quiet( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if ( isNaNF64UI( uiA ) || isNaNF64UI( uiB ) ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        (signA != signB)
+            ? signA && ((uiA | uiB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+            : (uiA != uiB) && (signA ^ (uiA < uiB));
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_mul.c b/addins/SoftFloat-3e/source/f64_mul.c
new file mode 100644
index 000000000..222e91dce
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_mul.c
@@ -0,0 +1,150 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_mul( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    bool signZ;
+    uint_fast64_t magBits;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+#ifdef SOFTFLOAT_FAST_INT64
+    struct uint128 sig128Z;
+#else
+    uint32_t sig128Z[4];
+#endif
+    uint_fast64_t sigZ, uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    expB  = expF64UI( uiB );
+    sigB  = fracF64UI( uiB );
+    signZ = signA ^ signB;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN;
+        magBits = expB | sigB;
+        goto infArg;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        magBits = expA | sigA;
+        goto infArg;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zero;
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FF;
+    sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10;
+    sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11;
+#ifdef SOFTFLOAT_FAST_INT64
+    sig128Z = softfloat_mul64To128( sigA, sigB );
+    sigZ = sig128Z.v64 | (sig128Z.v0 != 0);
+#else
+    softfloat_mul64To128M( sigA, sigB, sig128Z );
+    sigZ =
+        (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )];
+    if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1;
+#endif
+    if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {
+        --expZ;
+        sigZ <<= 1;
+    }
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infArg:
+    if ( ! magBits ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ = defaultNaNF64UI;
+    } else {
+        uiZ = packToF64UI( signZ, 0x7FF, 0 );
+    }
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zero:
+    uiZ = packToF64UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_mulAdd.c b/addins/SoftFloat-3e/source/f64_mulAdd.c
new file mode 100644
index 000000000..fea3d968b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_mulAdd.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    union ui64_f64 uC;
+    uint_fast64_t uiC;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    uC.f = c;
+    uiC = uC.ui;
+    return softfloat_mulAddF64( uiA, uiB, uiC, 0 );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_rem.c b/addins/SoftFloat-3e/source/f64_rem.c
new file mode 100644
index 000000000..ffce679aa
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_rem.c
@@ -0,0 +1,189 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_rem( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    struct exp16_sig64 normExpSig;
+    uint64_t rem;
+    int_fast16_t expDiff;
+    uint32_t q, recip32;
+    uint_fast64_t q64;
+    uint64_t altRem, meanRem;
+    bool signRem;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN;
+        goto invalid;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA < expB - 1 ) return a;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expB ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    rem = sigA | UINT64_C( 0x0010000000000000 );
+    sigB |= UINT64_C( 0x0010000000000000 );
+    expDiff = expA - expB;
+    if ( expDiff < 1 ) {
+        if ( expDiff < -1 ) return a;
+        sigB <<= 9;
+        if ( expDiff ) {
+            rem <<= 8;
+            q = 0;
+        } else {
+            rem <<= 9;
+            q = (sigB <= rem);
+            if ( q ) rem -= sigB;
+        }
+    } else {
+        recip32 = softfloat_approxRecip32_1( sigB>>21 );
+        /*--------------------------------------------------------------------
+        | Changing the shift of `rem' here requires also changing the initial
+        | subtraction from `expDiff'.
+        *--------------------------------------------------------------------*/
+        rem <<= 9;
+        expDiff -= 30;
+        /*--------------------------------------------------------------------
+        | The scale of `sigB' affects how many bits are obtained during each
+        | cycle of the loop.  Currently this is 29 bits per loop iteration,
+        | the maximum possible.
+        *--------------------------------------------------------------------*/
+        sigB <<= 9;
+        for (;;) {
+            q64 = (uint32_t) (rem>>32) * (uint_fast64_t) recip32;
+            if ( expDiff < 0 ) break;
+            q = (q64 + 0x80000000)>>32;
+#ifdef SOFTFLOAT_FAST_INT64
+            rem <<= 29;
+#else
+            rem = (uint_fast64_t) (uint32_t) (rem>>3)<<32;
+#endif
+            rem -= q * (uint64_t) sigB;
+            if ( rem & UINT64_C( 0x8000000000000000 ) ) rem += sigB;
+            expDiff -= 29;
+        }
+        /*--------------------------------------------------------------------
+        | (`expDiff' cannot be less than -29 here.)
+        *--------------------------------------------------------------------*/
+        q = (uint32_t) (q64>>32)>>(~expDiff & 31);
+        rem = (rem<<(expDiff + 30)) - q * (uint64_t) sigB;
+        if ( rem & UINT64_C( 0x8000000000000000 ) ) {
+            altRem = rem + sigB;
+            goto selectRem;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    do {
+        altRem = rem;
+        ++q;
+        rem -= sigB;
+    } while ( ! (rem & UINT64_C( 0x8000000000000000 )) );
+ selectRem:
+    meanRem = rem + altRem;
+    if (
+        (meanRem & UINT64_C( 0x8000000000000000 )) || (! meanRem && (q & 1))
+    ) {
+        rem = altRem;
+    }
+    signRem = signA;
+    if ( rem & UINT64_C( 0x8000000000000000 ) ) {
+        signRem = ! signRem;
+        rem = -rem;
+    }
+    return softfloat_normRoundPackToF64( signRem, expB, rem );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_roundToInt.c b/addins/SoftFloat-3e/source/f64_roundToInt.c
new file mode 100644
index 000000000..54e7b0542
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_roundToInt.c
@@ -0,0 +1,120 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_roundToInt( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t uiZ, lastBitMask, roundBitsMask;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp <= 0x3FE ) {
+        if ( !(uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) return a;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        uiZ = uiA & packToF64UI( 1, 0, 0 );
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( !fracF64UI( uiA ) ) break;
+         case softfloat_round_near_maxMag:
+            if ( exp == 0x3FE ) uiZ |= packToF64UI( 0, 0x3FF, 0 );
+            break;
+         case softfloat_round_min:
+            if ( uiZ ) uiZ = packToF64UI( 1, 0x3FF, 0 );
+            break;
+         case softfloat_round_max:
+            if ( !uiZ ) uiZ = packToF64UI( 0, 0x3FF, 0 );
+            break;
+#ifdef SOFTFLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            uiZ |= packToF64UI( 0, 0x3FF, 0 );
+            break;
+#endif
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x433 <= exp ) {
+        if ( (exp == 0x7FF) && fracF64UI( uiA ) ) {
+            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );
+            goto uiZ;
+        }
+        return a;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ = uiA;
+    lastBitMask = (uint_fast64_t) 1<<(0x433 - exp);
+    roundBitsMask = lastBitMask - 1;
+    if ( roundingMode == softfloat_round_near_maxMag ) {
+        uiZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_near_even ) {
+        uiZ += lastBitMask>>1;
+        if ( !(uiZ & roundBitsMask) ) uiZ &= ~lastBitMask;
+    } else if (
+        roundingMode
+            == (signF64UI( uiZ ) ? softfloat_round_min : softfloat_round_max)
+    ) {
+        uiZ += roundBitsMask;
+    }
+    uiZ &= ~roundBitsMask;
+    if ( uiZ != uiA ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) uiZ |= lastBitMask;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_sqrt.c b/addins/SoftFloat-3e/source/f64_sqrt.c
new file mode 100644
index 000000000..f9f226b69
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_sqrt.c
@@ -0,0 +1,133 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_sqrt( float64_t a )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA, uiZ;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+    uint32_t sig32A, recipSqrt32, sig32Z;
+    uint_fast64_t rem;
+    uint32_t q;
+    uint_fast64_t sigZ, shiftedSigZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA ) {
+            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );
+            goto uiZ;
+        }
+        if ( ! signA ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signA ) {
+        if ( ! (expA | sigA) ) return a;
+        goto invalid;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    | (`sig32Z' is guaranteed to be a lower bound on the square root of
+    | `sig32A', which makes `sig32Z' also a lower bound on the square root of
+    | `sigA'.)
+    *------------------------------------------------------------------------*/
+    expZ = ((expA - 0x3FF)>>1) + 0x3FE;
+    expA &= 1;
+    sigA |= UINT64_C( 0x0010000000000000 );
+    sig32A = sigA>>21;
+    recipSqrt32 = softfloat_approxRecipSqrt32_1( expA, sig32A );
+    sig32Z = ((uint_fast64_t) sig32A * recipSqrt32)>>32;
+    if ( expA ) {
+        sigA <<= 8;
+        sig32Z >>= 1;
+    } else {
+        sigA <<= 9;
+    }
+    rem = sigA - (uint_fast64_t) sig32Z * sig32Z;
+    q = ((uint32_t) (rem>>2) * (uint_fast64_t) recipSqrt32)>>32;
+    sigZ = ((uint_fast64_t) sig32Z<<32 | 1<<5) + ((uint_fast64_t) q<<3);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (sigZ & 0x1FF) < 0x22 ) {
+        sigZ &= ~(uint_fast64_t) 0x3F;
+        shiftedSigZ = sigZ>>6;
+        rem = (sigA<<52) - shiftedSigZ * shiftedSigZ;
+        if ( rem & UINT64_C( 0x8000000000000000 ) ) {
+            --sigZ;
+        } else {
+            if ( rem ) sigZ |= 1;
+        }
+    }
+    return softfloat_roundPackToF64( 0, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_sub.c b/addins/SoftFloat-3e/source/f64_sub.c
new file mode 100644
index 000000000..b5ccb882b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_sub.c
@@ -0,0 +1,74 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t f64_sub( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+#if ! defined INLINE_LEVEL || (INLINE_LEVEL < 2)
+    float64_t (*magsFuncPtr)( uint_fast64_t, uint_fast64_t, bool );
+#endif
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+    if ( signA == signB ) {
+        return softfloat_subMagsF64( uiA, uiB, signA );
+    } else {
+        return softfloat_addMagsF64( uiA, uiB, signA );
+    }
+#else
+    magsFuncPtr =
+        (signA == signB) ? softfloat_subMagsF64 : softfloat_addMagsF64;
+    return (*magsFuncPtr)( uiA, uiB, signA );
+#endif
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_extF80.c b/addins/SoftFloat-3e/source/f64_to_extF80.c
new file mode 100644
index 000000000..2799d9b07
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t f64_to_extF80( float64_t a )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    struct exp16_sig64 normExpSig;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToExtF80UI( &commonNaN );
+            uiZ64 = uiZ.v64;
+            uiZ0  = uiZ.v0;
+        } else {
+            uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+            uiZ0  = UINT64_C( 0x8000000000000000 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3C00 );
+    uiZ0  = (frac | UINT64_C( 0x0010000000000000 ))<<11;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_extF80M.c b/addins/SoftFloat-3e/source/f64_to_extF80M.c
new file mode 100644
index 000000000..a2e67e46f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_extF80M.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f64_to_extF80M( float64_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = f64_to_extF80( a );
+
+}
+
+#else
+
+void f64_to_extF80M( float64_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    union ui64_f64 uA;
+    uint64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint64_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ64;
+    uint64_t uiZ0;
+    struct exp16_sig64 normExpSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zSPtr = (struct extFloat80M *) zPtr;
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToExtF80M( &commonNaN, zSPtr );
+            return;
+        }
+        uiZ64 = packToExtF80UI64( sign, 0x7FFF );
+        uiZ0  = UINT64_C( 0x8000000000000000 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ64 = packToExtF80UI64( sign, 0 );
+            uiZ0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( frac );
+        exp = normExpSig.exp;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiZ64 = packToExtF80UI64( sign, exp + 0x3C00 );
+    uiZ0  = UINT64_C( 0x8000000000000000 ) | frac<<11;
+ uiZ:
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f64_to_f128.c b/addins/SoftFloat-3e/source/f64_to_f128.c
new file mode 100644
index 000000000..60af3b0be
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_f128.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t f64_to_f128( float64_t a )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t frac;
+    struct commonNaN commonNaN;
+    struct uint128 uiZ;
+    struct exp16_sig64 normExpSig;
+    struct uint128 frac128;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF128UI( &commonNaN );
+        } else {
+            uiZ.v64 = packToF128UI64( sign, 0x7FFF, 0 );
+            uiZ.v0  = 0;
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ.v64 = packToF128UI64( sign, 0, 0 );
+            uiZ.v0  = 0;
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac128 = softfloat_shortShiftLeft128( 0, frac, 60 );
+    uiZ.v64 = packToF128UI64( sign, exp + 0x3C00, frac128.v64 );
+    uiZ.v0  = frac128.v0;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_f128M.c b/addins/SoftFloat-3e/source/f64_to_f128M.c
new file mode 100644
index 000000000..fbc451537
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_f128M.c
@@ -0,0 +1,117 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void f64_to_f128M( float64_t a, float128_t *zPtr )
+{
+
+    *zPtr = f64_to_f128( a );
+
+}
+
+#else
+
+void f64_to_f128M( float64_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr;
+    union ui64_f64 uA;
+    uint64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint64_t frac;
+    struct commonNaN commonNaN;
+    uint32_t uiZ96;
+    struct exp16_sig64 normExpSig;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr = (uint32_t *) zPtr;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr[indexWord( 4, 0 )] = 0;
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            softfloat_commonNaNToF128M( &commonNaN, zWPtr );
+            return;
+        }
+        uiZ96 = packToF128UI96( sign, 0x7FFF, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! exp ) {
+        if ( ! frac ) {
+            uiZ96 = packToF128UI96( sign, 0, 0 );
+            goto uiZ;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( frac );
+        exp = normExpSig.exp - 1;
+        frac = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    zWPtr[indexWord( 4, 1 )] = (uint32_t) frac<<28;
+    frac >>= 4;
+    zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp + 0x3C00, frac>>32 );
+    zWPtr[indexWord( 4, 2 )] = frac;
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ uiZ:
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/f64_to_f16.c b/addins/SoftFloat-3e/source/f64_to_f16.c
new file mode 100644
index 000000000..121e3062a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_f16.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t f64_to_f16( float64_t a )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t frac;
+    struct commonNaN commonNaN;
+    uint_fast16_t uiZ, frac16;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF16UI( &commonNaN );
+        } else {
+            uiZ = packToF16UI( sign, 0x1F, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac16 = softfloat_shortShiftRightJam64( frac, 38 );
+    if ( ! (exp | frac16) ) {
+        uiZ = packToF16UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    return softfloat_roundPackToF16( sign, exp - 0x3F1, frac16 | 0x4000 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_f32.c b/addins/SoftFloat-3e/source/f64_to_f32.c
new file mode 100644
index 000000000..a18106556
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_f32.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f64_to_f32( float64_t a )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t frac;
+    struct commonNaN commonNaN;
+    uint_fast32_t uiZ, frac32;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    frac = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp == 0x7FF ) {
+        if ( frac ) {
+            softfloat_f64UIToCommonNaN( uiA, &commonNaN );
+            uiZ = softfloat_commonNaNToF32UI( &commonNaN );
+        } else {
+            uiZ = packToF32UI( sign, 0xFF, 0 );
+        }
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    frac32 = softfloat_shortShiftRightJam64( frac, 22 );
+    if ( ! (exp | frac32) ) {
+        uiZ = packToF32UI( sign, 0, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    return softfloat_roundPackToF32( sign, exp - 0x381, frac32 | 0x40000000 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_i32.c b/addins/SoftFloat-3e/source/f64_to_i32.c
new file mode 100644
index 000000000..8d9785b0b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_i32.c
@@ -0,0 +1,82 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f64_to_i32( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    sig  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
+    if ( (exp == 0x7FF) && sig ) {
+#if (i32_fromNaN == i32_fromPosOverflow)
+        sign = 0;
+#elif (i32_fromNaN == i32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return i32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );
+    shiftDist = 0x427 - exp;
+    if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist );
+    return softfloat_roundToI32( sign, sig, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_i32_r_minMag.c b/addins/SoftFloat-3e/source/f64_to_i32_r_minMag.c
new file mode 100644
index 000000000..8b7a91f1c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_i32_r_minMag.c
@@ -0,0 +1,96 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    int_fast32_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF64UI( uiA );
+    sig = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x433 - exp;
+    if ( 53 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF64UI( uiA );
+    if ( shiftDist < 22 ) {
+        if (
+            sign && (exp == 0x41E) && (sig < UINT64_C( 0x0000000000200000 ))
+        ) {
+            if ( exact && sig ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return -0x7FFFFFFF - 1;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FF) && sig ? i32_fromNaN
+                : sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig |= UINT64_C( 0x0010000000000000 );
+    absZ = sig>>shiftDist;
+    if ( exact && ((uint_fast64_t) (uint_fast32_t) absZ<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_i64.c b/addins/SoftFloat-3e/source/f64_to_i64.c
new file mode 100644
index 000000000..7199643ac
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_i64.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f64_to_i64( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+#ifdef SOFTFLOAT_FAST_INT64
+    struct uint64_extra sigExtra;
+#else
+    uint32_t extSig[3];
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    sig  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );
+    shiftDist = 0x433 - exp;
+#ifdef SOFTFLOAT_FAST_INT64
+    if ( shiftDist <= 0 ) {
+        if ( shiftDist < -11 ) goto invalid;
+        sigExtra.v = sig<<-shiftDist;
+        sigExtra.extra = 0;
+    } else {
+        sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist );
+    }
+    return
+        softfloat_roundToI64(
+            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );
+#else
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist <= 0 ) {
+        if ( shiftDist < -11 ) goto invalid;
+        sig <<= -shiftDist;
+        extSig[indexWord( 3, 2 )] = sig>>32;
+        extSig[indexWord( 3, 1 )] = sig;
+    } else {
+        extSig[indexWord( 3, 2 )] = sig>>32;
+        extSig[indexWord( 3, 1 )] = sig;
+        softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    }
+    return softfloat_roundMToI64( sign, extSig, roundingMode, exact );
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FF) && fracF64UI( uiA ) ? i64_fromNaN
+            : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_i64_r_minMag.c b/addins/SoftFloat-3e/source/f64_to_i64_r_minMag.c
new file mode 100644
index 000000000..56c6a1010
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_i64_r_minMag.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+    int_fast64_t absZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    sig  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x433 - exp;
+    if ( shiftDist <= 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( shiftDist < -10 ) {
+            if ( uiA == packToF64UI( 1, 0x43E, 0 ) ) {
+                return -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;
+            }
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            return
+                (exp == 0x7FF) && sig ? i64_fromNaN
+                    : sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig |= UINT64_C( 0x0010000000000000 );
+        absZ = sig<<-shiftDist;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( 53 <= shiftDist ) {
+            if ( exact && (exp | sig) ) {
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+            }
+            return 0;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig |= UINT64_C( 0x0010000000000000 );
+        absZ = sig>>shiftDist;
+        if ( exact && (absZ<<shiftDist != sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return sign ? -absZ : absZ;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_ui32.c b/addins/SoftFloat-3e/source/f64_to_ui32.c
new file mode 100644
index 000000000..9d2114633
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_ui32.c
@@ -0,0 +1,82 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f64_to_ui32( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    sig  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
+    if ( (exp == 0x7FF) && sig ) {
+#if (ui32_fromNaN == ui32_fromPosOverflow)
+        sign = 0;
+#elif (ui32_fromNaN == ui32_fromNegOverflow)
+        sign = 1;
+#else
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return ui32_fromNaN;
+#endif
+    }
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );
+    shiftDist = 0x427 - exp;
+    if ( 0 < shiftDist ) sig = softfloat_shiftRightJam64( sig, shiftDist );
+    return softfloat_roundToUI32( sign, sig, roundingMode, exact );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_ui32_r_minMag.c b/addins/SoftFloat-3e/source/f64_to_ui32_r_minMag.c
new file mode 100644
index 000000000..6e3d14e8f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_ui32_r_minMag.c
@@ -0,0 +1,88 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t f64_to_ui32_r_minMag( float64_t a, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    uint_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF64UI( uiA );
+    sig = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x433 - exp;
+    if ( 53 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF64UI( uiA );
+    if ( sign || (shiftDist < 21) ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return
+            (exp == 0x7FF) && sig ? ui32_fromNaN
+                : sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig |= UINT64_C( 0x0010000000000000 );
+    z = sig>>shiftDist;
+    if ( exact && ((uint_fast64_t) z<<shiftDist != sig) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_ui64.c b/addins/SoftFloat-3e/source/f64_to_ui64.c
new file mode 100644
index 000000000..292e47a44
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_ui64.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f64_to_ui64( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool sign;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+#ifdef SOFTFLOAT_FAST_INT64
+    struct uint64_extra sigExtra;
+#else
+    uint32_t extSig[3];
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    sign = signF64UI( uiA );
+    exp  = expF64UI( uiA );
+    sig  = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );
+    shiftDist = 0x433 - exp;
+#ifdef SOFTFLOAT_FAST_INT64
+    if ( shiftDist <= 0 ) {
+        if ( shiftDist < -11 ) goto invalid;
+        sigExtra.v = sig<<-shiftDist;
+        sigExtra.extra = 0;
+    } else {
+        sigExtra = softfloat_shiftRightJam64Extra( sig, 0, shiftDist );
+    }
+    return
+        softfloat_roundToUI64(
+            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );
+#else
+    extSig[indexWord( 3, 0 )] = 0;
+    if ( shiftDist <= 0 ) {
+        if ( shiftDist < -11 ) goto invalid;
+        sig <<= -shiftDist;
+        extSig[indexWord( 3, 2 )] = sig>>32;
+        extSig[indexWord( 3, 1 )] = sig;
+    } else {
+        extSig[indexWord( 3, 2 )] = sig>>32;
+        extSig[indexWord( 3, 1 )] = sig;
+        softfloat_shiftRightJam96M( extSig, shiftDist, extSig );
+    }
+    return softfloat_roundMToUI64( sign, extSig, roundingMode, exact );
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FF) && fracF64UI( uiA ) ? ui64_fromNaN
+            : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/f64_to_ui64_r_minMag.c b/addins/SoftFloat-3e/source/f64_to_ui64_r_minMag.c
new file mode 100644
index 000000000..87eb0d05c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/f64_to_ui64_r_minMag.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t f64_to_ui64_r_minMag( float64_t a, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t sig;
+    int_fast16_t shiftDist;
+    bool sign;
+    uint_fast64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uA.f = a;
+    uiA = uA.ui;
+    exp = expF64UI( uiA );
+    sig = fracF64UI( uiA );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 0x433 - exp;
+    if ( 53 <= shiftDist ) {
+        if ( exact && (exp | sig) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+        return 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sign = signF64UI( uiA );
+    if ( sign ) goto invalid;
+    if ( shiftDist <= 0 ) {
+        if ( shiftDist < -11 ) goto invalid;
+        z = (sig | UINT64_C( 0x0010000000000000 ))<<-shiftDist;
+    } else {
+        sig |= UINT64_C( 0x0010000000000000 );
+        z = sig>>shiftDist;
+        if ( exact && (uint64_t) (sig<<(-shiftDist & 63)) ) {
+            softfloat_exceptionFlags |= softfloat_flag_inexact;
+        }
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        (exp == 0x7FF) && sig ? ui64_fromNaN
+            : sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i32_to_extF80.c b/addins/SoftFloat-3e/source/i32_to_extF80.c
new file mode 100644
index 000000000..8036fa9f1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_extF80.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t i32_to_extF80( int32_t a )
+{
+    uint_fast16_t uiZ64;
+    uint_fast32_t absA;
+    bool sign;
+    int_fast8_t shiftDist;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    uiZ64 = 0;
+    absA = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a;
+        shiftDist = softfloat_countLeadingZeros32( absA );
+        uiZ64 = packToExtF80UI64( sign, 0x401E - shiftDist );
+        absA <<= shiftDist;
+    }
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif = (uint_fast64_t) absA<<32;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i32_to_extF80M.c b/addins/SoftFloat-3e/source/i32_to_extF80M.c
new file mode 100644
index 000000000..6d5431c1c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_extF80M.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void i32_to_extF80M( int32_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = i32_to_extF80( a );
+
+}
+
+#else
+
+void i32_to_extF80M( int32_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint64_t sigZ;
+    bool sign;
+    uint32_t absA;
+    int_fast8_t shiftDist;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = 0;
+    sigZ = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint32_t) a : (uint32_t) a;
+        shiftDist = softfloat_countLeadingZeros32( absA );
+        uiZ64 = packToExtF80UI64( sign, 0x401E - shiftDist );
+        sigZ = (uint64_t) (absA<<shiftDist)<<32;
+    }
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = sigZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/i32_to_f128.c b/addins/SoftFloat-3e/source/i32_to_f128.c
new file mode 100644
index 000000000..a7d55cba4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_f128.c
@@ -0,0 +1,64 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t i32_to_f128( int32_t a )
+{
+    uint_fast64_t uiZ64;
+    bool sign;
+    uint_fast32_t absA;
+    int_fast8_t shiftDist;
+    union ui128_f128 uZ;
+
+    uiZ64 = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a;
+        shiftDist = softfloat_countLeadingZeros32( absA ) + 17;
+        uiZ64 =
+            packToF128UI64(
+                sign, 0x402E - shiftDist, (uint_fast64_t) absA<<shiftDist );
+    }
+    uZ.ui.v64 = uiZ64;
+    uZ.ui.v0  = 0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i32_to_f128M.c b/addins/SoftFloat-3e/source/i32_to_f128M.c
new file mode 100644
index 000000000..beb3c1012
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_f128M.c
@@ -0,0 +1,81 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void i32_to_f128M( int32_t a, float128_t *zPtr )
+{
+
+    *zPtr = i32_to_f128( a );
+
+}
+
+#else
+
+void i32_to_f128M( int32_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr;
+    uint32_t uiZ96, uiZ64;
+    bool sign;
+    uint32_t absA;
+    int_fast8_t shiftDist;
+    uint64_t normAbsA;
+
+    zWPtr = (uint32_t *) zPtr;
+    uiZ96 = 0;
+    uiZ64 = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint32_t) a : (uint32_t) a;
+        shiftDist = softfloat_countLeadingZeros32( absA ) + 17;
+        normAbsA = (uint64_t) absA<<shiftDist;
+        uiZ96 = packToF128UI96( sign, 0x402E - shiftDist, normAbsA>>32 );
+        uiZ64 = normAbsA;
+    }
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = uiZ64;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/i32_to_f16.c b/addins/SoftFloat-3e/source/i32_to_f16.c
new file mode 100644
index 000000000..d3117248a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_f16.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t i32_to_f16( int32_t a )
+{
+    bool sign;
+    uint_fast32_t absA;
+    int_fast8_t shiftDist;
+    union ui16_f16 u;
+    uint_fast16_t sig;
+
+    sign = (a < 0);
+    absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a;
+    shiftDist = softfloat_countLeadingZeros32( absA ) - 21;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF16UI(
+                    sign, 0x18 - shiftDist, (uint_fast16_t) absA<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 4;
+        sig =
+            (shiftDist < 0)
+                ? absA>>(-shiftDist)
+                      | ((uint32_t) (absA<<(shiftDist & 31)) != 0)
+                : (uint_fast16_t) absA<<shiftDist;
+        return softfloat_roundPackToF16( sign, 0x1C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i32_to_f32.c b/addins/SoftFloat-3e/source/i32_to_f32.c
new file mode 100644
index 000000000..e6de3e837
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_f32.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t i32_to_f32( int32_t a )
+{
+    bool sign;
+    union ui32_f32 uZ;
+    uint_fast32_t absA;
+
+    sign = (a < 0);
+    if ( ! (a & 0x7FFFFFFF) ) {
+        uZ.ui = sign ? packToF32UI( 1, 0x9E, 0 ) : 0;
+        return uZ.f;
+    }
+    absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a;
+    return softfloat_normRoundPackToF32( sign, 0x9C, absA );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i32_to_f64.c b/addins/SoftFloat-3e/source/i32_to_f64.c
new file mode 100644
index 000000000..24feda542
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i32_to_f64.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t i32_to_f64( int32_t a )
+{
+    uint_fast64_t uiZ;
+    bool sign;
+    uint_fast32_t absA;
+    int_fast8_t shiftDist;
+    union ui64_f64 uZ;
+
+    if ( ! a ) {
+        uiZ = 0;
+    } else {
+        sign = (a < 0);
+        absA = sign ? -(uint_fast32_t) a : (uint_fast32_t) a;
+        shiftDist = softfloat_countLeadingZeros32( absA ) + 21;
+        uiZ =
+            packToF64UI(
+                sign, 0x432 - shiftDist, (uint_fast64_t) absA<<shiftDist );
+    }
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i64_to_extF80.c b/addins/SoftFloat-3e/source/i64_to_extF80.c
new file mode 100644
index 000000000..a1000be77
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_extF80.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t i64_to_extF80( int64_t a )
+{
+    uint_fast16_t uiZ64;
+    uint_fast64_t absA;
+    bool sign;
+    int_fast8_t shiftDist;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    uiZ64 = 0;
+    absA = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a;
+        shiftDist = softfloat_countLeadingZeros64( absA );
+        uiZ64 = packToExtF80UI64( sign, 0x403E - shiftDist );
+        absA <<= shiftDist;
+    }
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = absA;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i64_to_extF80M.c b/addins/SoftFloat-3e/source/i64_to_extF80M.c
new file mode 100644
index 000000000..4838dde6d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_extF80M.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void i64_to_extF80M( int64_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = i64_to_extF80( a );
+
+}
+
+#else
+
+void i64_to_extF80M( int64_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint64_t sigZ;
+    bool sign;
+    uint64_t absA;
+    int_fast8_t shiftDist;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = 0;
+    sigZ = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint64_t) a : (uint64_t) a;
+        shiftDist = softfloat_countLeadingZeros64( absA );
+        uiZ64 = packToExtF80UI64( sign, 0x403E - shiftDist );
+        sigZ = absA<<shiftDist;
+    }
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = sigZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/i64_to_f128.c b/addins/SoftFloat-3e/source/i64_to_f128.c
new file mode 100644
index 000000000..fcb017939
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_f128.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t i64_to_f128( int64_t a )
+{
+    uint_fast64_t uiZ64, uiZ0;
+    bool sign;
+    uint_fast64_t absA;
+    int_fast8_t shiftDist;
+    struct uint128 zSig;
+    union ui128_f128 uZ;
+
+    if ( ! a ) {
+        uiZ64 = 0;
+        uiZ0  = 0;
+    } else {
+        sign = (a < 0);
+        absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a;
+        shiftDist = softfloat_countLeadingZeros64( absA ) + 49;
+        if ( 64 <= shiftDist ) {
+            zSig.v64 = absA<<(shiftDist - 64);
+            zSig.v0  = 0;
+        } else {
+            zSig = softfloat_shortShiftLeft128( 0, absA, shiftDist );
+        }
+        uiZ64 = packToF128UI64( sign, 0x406E - shiftDist, zSig.v64 );
+        uiZ0  = zSig.v0;
+    }
+    uZ.ui.v64 = uiZ64;
+    uZ.ui.v0  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i64_to_f128M.c b/addins/SoftFloat-3e/source/i64_to_f128M.c
new file mode 100644
index 000000000..0a04eb8d0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_f128M.c
@@ -0,0 +1,92 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void i64_to_f128M( int64_t a, float128_t *zPtr )
+{
+
+    *zPtr = i64_to_f128( a );
+
+}
+
+#else
+
+void i64_to_f128M( int64_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr;
+    uint32_t uiZ96, uiZ64;
+    bool sign;
+    uint64_t absA;
+    uint_fast8_t shiftDist;
+    uint32_t *ptr;
+
+    zWPtr = (uint32_t *) zPtr;
+    uiZ96 = 0;
+    uiZ64 = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+    if ( a ) {
+        sign = (a < 0);
+        absA = sign ? -(uint64_t) a : (uint64_t) a;
+        shiftDist = softfloat_countLeadingZeros64( absA ) + 17;
+        if ( shiftDist < 32 ) {
+            ptr = zWPtr + indexMultiwordHi( 4, 3 );
+            ptr[indexWord( 3, 2 )] = 0;
+            ptr[indexWord( 3, 1 )] = absA>>32;
+            ptr[indexWord( 3, 0 )] = absA;
+            softfloat_shortShiftLeft96M( ptr, shiftDist, ptr );
+            ptr[indexWordHi( 3 )] =
+                packToF128UI96(
+                    sign, 0x404E - shiftDist, ptr[indexWordHi( 3 )] );
+            return;
+        }
+        absA <<= shiftDist - 32;
+        uiZ96 = packToF128UI96( sign, 0x404E - shiftDist, absA>>32 );
+        uiZ64 = absA;
+    }
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = uiZ64;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/i64_to_f16.c b/addins/SoftFloat-3e/source/i64_to_f16.c
new file mode 100644
index 000000000..cef7b6133
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_f16.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t i64_to_f16( int64_t a )
+{
+    bool sign;
+    uint_fast64_t absA;
+    int_fast8_t shiftDist;
+    union ui16_f16 u;
+    uint_fast16_t sig;
+
+    sign = (a < 0);
+    absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a;
+    shiftDist = softfloat_countLeadingZeros64( absA ) - 53;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF16UI(
+                    sign, 0x18 - shiftDist, (uint_fast16_t) absA<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 4;
+        sig =
+            (shiftDist < 0)
+                ? softfloat_shortShiftRightJam64( absA, -shiftDist )
+                : (uint_fast16_t) absA<<shiftDist;
+        return softfloat_roundPackToF16( sign, 0x1C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i64_to_f32.c b/addins/SoftFloat-3e/source/i64_to_f32.c
new file mode 100644
index 000000000..ca1dc7452
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_f32.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t i64_to_f32( int64_t a )
+{
+    bool sign;
+    uint_fast64_t absA;
+    int_fast8_t shiftDist;
+    union ui32_f32 u;
+    uint_fast32_t sig;
+
+    sign = (a < 0);
+    absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a;
+    shiftDist = softfloat_countLeadingZeros64( absA ) - 40;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF32UI(
+                    sign, 0x95 - shiftDist, (uint_fast32_t) absA<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 7;
+        sig =
+            (shiftDist < 0)
+                ? softfloat_shortShiftRightJam64( absA, -shiftDist )
+                : (uint_fast32_t) absA<<shiftDist;
+        return softfloat_roundPackToF32( sign, 0x9C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/i64_to_f64.c b/addins/SoftFloat-3e/source/i64_to_f64.c
new file mode 100644
index 000000000..ea9e821ad
--- /dev/null
+++ b/addins/SoftFloat-3e/source/i64_to_f64.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t i64_to_f64( int64_t a )
+{
+    bool sign;
+    union ui64_f64 uZ;
+    uint_fast64_t absA;
+
+    sign = (a < 0);
+    if ( ! (a & UINT64_C( 0x7FFFFFFFFFFFFFFF )) ) {
+        uZ.ui = sign ? packToF64UI( 1, 0x43E, 0 ) : 0;
+        return uZ.f;
+    }
+    absA = sign ? -(uint_fast64_t) a : (uint_fast64_t) a;
+    return softfloat_normRoundPackToF64( sign, 0x43C, absA );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/include/internals.h b/addins/SoftFloat-3e/source/include/internals.h
new file mode 100644
index 000000000..020b3402f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/internals.h
@@ -0,0 +1,278 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef internals_h
+#define internals_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitives.h"
+#include "softfloat_types.h"
+
+union ui16_f16 { uint16_t ui; float16_t f; };
+union ui32_f32 { uint32_t ui; float32_t f; };
+union ui64_f64 { uint64_t ui; float64_t f; };
+
+#ifdef SOFTFLOAT_FAST_INT64
+union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; };
+union ui128_f128 { struct uint128 ui; float128_t f; };
+#endif
+
+enum {
+    softfloat_mulAdd_subC    = 1,
+    softfloat_mulAdd_subProd = 2
+};
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool );
+
+#ifdef SOFTFLOAT_FAST_INT64
+uint_fast64_t
+ softfloat_roundToUI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+#else
+uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool );
+#endif
+
+int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool );
+
+#ifdef SOFTFLOAT_FAST_INT64
+int_fast64_t
+ softfloat_roundToI64(
+     bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool );
+#else
+int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signF16UI( a ) ((bool) ((uint16_t) (a)>>15))
+#define expF16UI( a ) ((int_fast8_t) ((a)>>10) & 0x1F)
+#define fracF16UI( a ) ((a) & 0x03FF)
+#define packToF16UI( sign, exp, sig ) (((uint16_t) (sign)<<15) + ((uint16_t) (exp)<<10) + (sig))
+
+#define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF))
+
+struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; };
+struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t );
+
+float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t );
+float16_t softfloat_normRoundPackToF16( bool, int_fast16_t, uint_fast16_t );
+
+float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t );
+float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t );
+float16_t
+ softfloat_mulAddF16(
+     uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signF32UI( a ) ((bool) ((uint32_t) (a)>>31))
+#define expF32UI( a ) ((int_fast16_t) ((a)>>23) & 0xFF)
+#define fracF32UI( a ) ((a) & 0x007FFFFF)
+#define packToF32UI( sign, exp, sig ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<23) + (sig))
+
+#define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF))
+
+struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };
+struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );
+
+float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );
+float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );
+
+float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t );
+float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t );
+float32_t
+ softfloat_mulAddF32(
+     uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signF64UI( a ) ((bool) ((uint64_t) (a)>>63))
+#define expF64UI( a ) ((int_fast16_t) ((a)>>52) & 0x7FF)
+#define fracF64UI( a ) ((a) & UINT64_C( 0x000FFFFFFFFFFFFF ))
+#define packToF64UI( sign, exp, sig ) ((uint64_t) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<52) + (sig)))
+
+#define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )))
+
+struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };
+struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );
+
+float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );
+float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );
+
+float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );
+float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );
+float64_t
+ softfloat_mulAddF64(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signExtF80UI64( a64 ) ((bool) ((uint16_t) (a64)>>15))
+#define expExtF80UI64( a64 ) ((a64) & 0x7FFF)
+#define packToExtF80UI64( sign, exp ) ((uint_fast16_t) (sign)<<15 | (exp))
+
+#define isNaNExtF80UI( a64, a0 ) ((((a64) & 0x7FFF) == 0x7FFF) && ((a0) & UINT64_C( 0x7FFFFFFFFFFFFFFF )))
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+struct exp32_sig64 { int_fast32_t exp; uint64_t sig; };
+struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t );
+
+extFloat80_t
+ softfloat_roundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+extFloat80_t
+ softfloat_normRoundPackToExtF80(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t );
+
+extFloat80_t
+ softfloat_addMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+extFloat80_t
+ softfloat_subMagsExtF80(
+     uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signF128UI64( a64 ) ((bool) ((uint64_t) (a64)>>63))
+#define expF128UI64( a64 ) ((int_fast32_t) ((a64)>>48) & 0x7FFF)
+#define fracF128UI64( a64 ) ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))
+#define packToF128UI64( sign, exp, sig64 ) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<48) + (sig64))
+
+#define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF ))))
+
+struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; };
+struct exp32_sig128
+ softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t );
+
+float128_t
+ softfloat_roundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t );
+float128_t
+ softfloat_normRoundPackToF128(
+     bool, int_fast32_t, uint_fast64_t, uint_fast64_t );
+
+float128_t
+ softfloat_addMagsF128(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_subMagsF128(
+     uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool );
+float128_t
+ softfloat_mulAddF128(
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast64_t,
+     uint_fast8_t
+ );
+
+#else
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+bool
+ softfloat_tryPropagateNaNExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *
+ );
+void softfloat_invalidExtF80M( struct extFloat80M * );
+
+int softfloat_normExtF80SigM( uint64_t * );
+
+void
+ softfloat_roundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+void
+ softfloat_normRoundPackMToExtF80M(
+     bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+
+void
+ softfloat_addExtF80M(
+     const struct extFloat80M *,
+     const struct extFloat80M *,
+     struct extFloat80M *,
+     bool
+ );
+
+int
+ softfloat_compareNonnormExtF80M(
+     const struct extFloat80M *, const struct extFloat80M * );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define signF128UI96( a96 ) ((bool) ((uint32_t) (a96)>>31))
+#define expF128UI96( a96 ) ((int32_t) ((a96)>>16) & 0x7FFF)
+#define fracF128UI96( a96 ) ((a96) & 0x0000FFFF)
+#define packToF128UI96( sign, exp, sig96 ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<16) + (sig96))
+
+bool softfloat_isNaNF128M( const uint32_t * );
+
+bool
+ softfloat_tryPropagateNaNF128M(
+     const uint32_t *, const uint32_t *, uint32_t * );
+void softfloat_invalidF128M( uint32_t * );
+
+int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * );
+
+void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
+void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * );
+
+void
+ softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool );
+void
+ softfloat_mulAddF128M(
+     const uint32_t *,
+     const uint32_t *,
+     const uint32_t *,
+     uint32_t *,
+     uint_fast8_t
+ );
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/include/opts-GCC.h b/addins/SoftFloat-3e/source/include/opts-GCC.h
new file mode 100644
index 000000000..18c1523e9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/opts-GCC.h
@@ -0,0 +1,114 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2017 The Regents of the University of California.  All rights
+reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef opts_GCC_h
+#define opts_GCC_h 1
+
+#ifdef INLINE
+
+#include <stdint.h>
+#include "primitiveTypes.h"
+
+#ifdef SOFTFLOAT_BUILTIN_CLZ
+
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+    { return a ? __builtin_clz( a ) - 16 : 16; }
+#define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
+
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+    { return a ? __builtin_clz( a ) : 32; }
+#define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
+
+INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
+    { return a ? __builtin_clzll( a ) : 64; }
+#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
+
+#endif
+
+#ifdef SOFTFLOAT_INTRINSIC_INT128
+
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+{
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
+    uZ.ui = (unsigned __int128) a * ((uint_fast64_t) b<<32);
+    return uZ.s;
+}
+#define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128
+
+INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
+{
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
+    uZ.ui = (unsigned __int128) a * b;
+    return uZ.s;
+}
+#define softfloat_mul64To128 softfloat_mul64To128
+
+INLINE
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+{
+    union { unsigned __int128 ui; struct uint128 s; } uZ;
+    uZ.ui = ((unsigned __int128) a64<<64 | a0) * b;
+    return uZ.s;
+}
+#define softfloat_mul128By32 softfloat_mul128By32
+
+INLINE
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
+{
+    unsigned __int128 z0, mid1, mid, z128;
+    z0 = (unsigned __int128) a0 * b0;
+    mid1 = (unsigned __int128) a64 * b0;
+    mid = mid1 + (unsigned __int128) a0 * b64;
+    z128 = (unsigned __int128) a64 * b64;
+    z128 += (unsigned __int128) (mid < mid1)<<64 | mid>>64;
+    mid <<= 64;
+    z0 += mid;
+    z128 += (z0 < mid);
+    zPtr[indexWord( 4, 0 )] = z0;
+    zPtr[indexWord( 4, 1 )] = z0>>64;
+    zPtr[indexWord( 4, 2 )] = z128;
+    zPtr[indexWord( 4, 3 )] = z128>>64;
+}
+#define softfloat_mul128To256M softfloat_mul128To256M
+
+#endif
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/include/primitiveTypes.h b/addins/SoftFloat-3e/source/include/primitiveTypes.h
new file mode 100644
index 000000000..a4a6dd11c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/primitiveTypes.h
@@ -0,0 +1,85 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef primitiveTypes_h
+#define primitiveTypes_h 1
+
+#include <stdint.h>
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+#ifdef LITTLEENDIAN
+struct uint128 { uint64_t v0, v64; };
+struct uint64_extra { uint64_t extra, v; };
+struct uint128_extra { uint64_t extra; struct uint128 v; };
+#else
+struct uint128 { uint64_t v64, v0; };
+struct uint64_extra { uint64_t v, extra; };
+struct uint128_extra { struct uint128 v; uint64_t extra; };
+#endif
+
+#endif
+
+/*----------------------------------------------------------------------------
+| These macros are used to isolate the differences in word order between big-
+| endian and little-endian platforms.
+*----------------------------------------------------------------------------*/
+#ifdef LITTLEENDIAN
+#define wordIncr 1
+#define indexWord( total, n ) (n)
+#define indexWordHi( total ) ((total) - 1)
+#define indexWordLo( total ) 0
+#define indexMultiword( total, m, n ) (n)
+#define indexMultiwordHi( total, n ) ((total) - (n))
+#define indexMultiwordLo( total, n ) 0
+#define indexMultiwordHiBut( total, n ) (n)
+#define indexMultiwordLoBut( total, n ) 0
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 }
+#else
+#define wordIncr -1
+#define indexWord( total, n ) ((total) - 1 - (n))
+#define indexWordHi( total ) 0
+#define indexWordLo( total ) ((total) - 1)
+#define indexMultiword( total, m, n ) ((total) - 1 - (m))
+#define indexMultiwordHi( total, n ) 0
+#define indexMultiwordLo( total, n ) ((total) - (n))
+#define indexMultiwordHiBut( total, n ) 0
+#define indexMultiwordLoBut( total, n ) (n)
+#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 }
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/include/primitives.h b/addins/SoftFloat-3e/source/include/primitives.h
new file mode 100644
index 000000000..863ab45b5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/primitives.h
@@ -0,0 +1,1160 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef primitives_h
+#define primitives_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightJam64
+/*----------------------------------------------------------------------------
+| Shifts 'a' right by the number of bits given in 'dist', which must be in
+| the range 1 to 63.  If any nonzero bits are shifted off, they are "jammed"
+| into the least-significant bit of the shifted value by setting the least-
+| significant bit to 1.  This shifted-and-jammed value is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
+    { return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0); }
+#else
+uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shiftRightJam32
+/*----------------------------------------------------------------------------
+| Shifts 'a' right by the number of bits given in 'dist', which must not
+| be zero.  If any nonzero bits are shifted off, they are "jammed" into the
+| least-significant bit of the shifted value by setting the least-significant
+| bit to 1.  This shifted-and-jammed value is returned.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
+| greater than 32, the result will be either 0 or 1, depending on whether 'a'
+| is zero or nonzero.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
+{
+    return
+        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
+}
+#else
+uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shiftRightJam64
+/*----------------------------------------------------------------------------
+| Shifts 'a' right by the number of bits given in 'dist', which must not
+| be zero.  If any nonzero bits are shifted off, they are "jammed" into the
+| least-significant bit of the shifted value by setting the least-significant
+| bit to 1.  This shifted-and-jammed value is returned.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
+| greater than 64, the result will be either 0 or 1, depending on whether 'a'
+| is zero or nonzero.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
+INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
+{
+    return
+        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
+}
+#else
+uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist );
+#endif
+#endif
+
+/*----------------------------------------------------------------------------
+| A constant table that translates an 8-bit unsigned integer (the array index)
+| into the number of leading 0 bits before the most-significant 1 of that
+| integer.  For integer zero (index 0), the corresponding table element is 8.
+*----------------------------------------------------------------------------*/
+extern const uint_least8_t softfloat_countLeadingZeros8[256];
+
+#ifndef softfloat_countLeadingZeros16
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| 'a'.  If 'a' is zero, 16 is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+{
+    uint_fast8_t count = 8;
+    if ( 0x100 <= a ) {
+        count = 0;
+        a >>= 8;
+    }
+    count += softfloat_countLeadingZeros8[a];
+    return count;
+}
+#else
+uint_fast8_t softfloat_countLeadingZeros16( uint16_t a );
+#endif
+#endif
+
+#ifndef softfloat_countLeadingZeros32
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| 'a'.  If 'a' is zero, 32 is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
+INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+{
+    uint_fast8_t count = 0;
+    if ( a < 0x10000 ) {
+        count = 16;
+        a <<= 16;
+    }
+    if ( a < 0x1000000 ) {
+        count += 8;
+        a <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[a>>24];
+    return count;
+}
+#else
+uint_fast8_t softfloat_countLeadingZeros32( uint32_t a );
+#endif
+#endif
+
+#ifndef softfloat_countLeadingZeros64
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| 'a'.  If 'a' is zero, 64 is returned.
+*----------------------------------------------------------------------------*/
+uint_fast8_t softfloat_countLeadingZeros64( uint64_t a );
+#endif
+
+extern const uint16_t softfloat_approxRecip_1k0s[16];
+extern const uint16_t softfloat_approxRecip_1k1s[16];
+
+#ifndef softfloat_approxRecip32_1
+/*----------------------------------------------------------------------------
+| Returns an approximation to the reciprocal of the number represented by 'a',
+| where 'a' is interpreted as an unsigned fixed-point number with one integer
+| bit and 31 fraction bits.  The 'a' input must be "normalized", meaning that
+| its most-significant bit (bit 31) must be 1.  Thus, if A is the value of
+| the fixed-point interpretation of 'a', then 1 <= A < 2.  The returned value
+| is interpreted as a pure unsigned fraction, having no integer bits and 32
+| fraction bits.  The approximation returned is never greater than the true
+| reciprocal 1/A, and it differs from the true reciprocal by at most 2.006 ulp
+| (units in the last place).
+*----------------------------------------------------------------------------*/
+#ifdef SOFTFLOAT_FAST_DIV64TO32
+#define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a)))
+#else
+uint32_t softfloat_approxRecip32_1( uint32_t a );
+#endif
+#endif
+
+extern const uint16_t softfloat_approxRecipSqrt_1k0s[16];
+extern const uint16_t softfloat_approxRecipSqrt_1k1s[16];
+
+#ifndef softfloat_approxRecipSqrt32_1
+/*----------------------------------------------------------------------------
+| Returns an approximation to the reciprocal of the square root of the number
+| represented by 'a', where 'a' is interpreted as an unsigned fixed-point
+| number either with one integer bit and 31 fraction bits or with two integer
+| bits and 30 fraction bits.  The format of 'a' is determined by 'oddExpA',
+| which must be either 0 or 1.  If 'oddExpA' is 1, 'a' is interpreted as
+| having one integer bit, and if 'oddExpA' is 0, 'a' is interpreted as having
+| two integer bits.  The 'a' input must be "normalized", meaning that its
+| most-significant bit (bit 31) must be 1.  Thus, if A is the value of the
+| fixed-point interpretation of 'a', it follows that 1 <= A < 2 when 'oddExpA'
+| is 1, and 2 <= A < 4 when 'oddExpA' is 0.
+|   The returned value is interpreted as a pure unsigned fraction, having
+| no integer bits and 32 fraction bits.  The approximation returned is never
+| greater than the true reciprocal 1/sqrt(A), and it differs from the true
+| reciprocal by at most 2.06 ulp (units in the last place).  The approximation
+| returned is also always within the range 0.5 to 1; thus, the most-
+| significant bit of the result is always set.
+*----------------------------------------------------------------------------*/
+uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a );
+#endif
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is
+| defined.
+*----------------------------------------------------------------------------*/
+
+#ifndef softfloat_eq128
+/*----------------------------------------------------------------------------
+| Returns true if the 128-bit unsigned integer formed by concatenating 'a64'
+| and 'a0' is equal to the 128-bit unsigned integer formed by concatenating
+| 'b64' and 'b0'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (1 <= INLINE_LEVEL)
+INLINE
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 == b64) && (a0 == b0); }
+#else
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+#endif
+#endif
+
+#ifndef softfloat_le128
+/*----------------------------------------------------------------------------
+| Returns true if the 128-bit unsigned integer formed by concatenating 'a64'
+| and 'a0' is less than or equal to the 128-bit unsigned integer formed by
+| concatenating 'b64' and 'b0'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); }
+#else
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+#endif
+#endif
+
+#ifndef softfloat_lt128
+/*----------------------------------------------------------------------------
+| Returns true if the 128-bit unsigned integer formed by concatenating 'a64'
+| and 'a0' is less than the 128-bit unsigned integer formed by concatenating
+| 'b64' and 'b0'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); }
+#else
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftLeft128
+/*----------------------------------------------------------------------------
+| Shifts the 128 bits formed by concatenating 'a64' and 'a0' left by the
+| number of bits given in 'dist', which must be in the range 1 to 63.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    struct uint128 z;
+    z.v64 = a64<<dist | a0>>(-dist & 63);
+    z.v0 = a0<<dist;
+    return z;
+}
+#else
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftRight128
+/*----------------------------------------------------------------------------
+| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the
+| number of bits given in 'dist', which must be in the range 1 to 63.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    struct uint128 z;
+    z.v64 = a64>>dist;
+    z.v0 = a64<<(-dist & 63) | a0>>dist;
+    return z;
+}
+#else
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftRightJam64Extra
+/*----------------------------------------------------------------------------
+| This function is the same as 'softfloat_shiftRightJam64Extra' (below),
+| except that 'dist' must be in the range 1 to 63.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist )
+{
+    struct uint64_extra z;
+    z.v = a>>dist;
+    z.extra = a<<(-dist & 63) | (extra != 0);
+    return z;
+}
+#else
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftRightJam128
+/*----------------------------------------------------------------------------
+| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the
+| number of bits given in 'dist', which must be in the range 1 to 63.  If any
+| nonzero bits are shifted off, they are "jammed" into the least-significant
+| bit of the shifted value by setting the least-significant bit to 1.  This
+| shifted-and-jammed value is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
+INLINE
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    uint_fast8_t negDist = -dist;
+    struct uint128 z;
+    z.v64 = a64>>dist;
+    z.v0 =
+        a64<<(negDist & 63) | a0>>dist
+            | ((uint64_t) (a0<<(negDist & 63)) != 0);
+    return z;
+}
+#else
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftRightJam128Extra
+/*----------------------------------------------------------------------------
+| This function is the same as 'softfloat_shiftRightJam128Extra' (below),
+| except that 'dist' must be in the range 1 to 63.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
+INLINE
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
+{
+    uint_fast8_t negDist = -dist;
+    struct uint128_extra z;
+    z.v.v64 = a64>>dist;
+    z.v.v0 = a64<<(negDist & 63) | a0>>dist;
+    z.extra = a0<<(negDist & 63) | (extra != 0);
+    return z;
+}
+#else
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shiftRightJam64Extra
+/*----------------------------------------------------------------------------
+| Shifts the 128 bits formed by concatenating 'a' and 'extra' right by 64
+| _plus_ the number of bits given in 'dist', which must not be zero.  This
+| shifted value is at most 64 nonzero bits and is returned in the 'v' field
+| of the 'struct uint64_extra' result.  The 64-bit 'extra' field of the result
+| contains a value formed as follows from the bits that were shifted off:  The
+| _last_ bit shifted off is the most-significant bit of the 'extra' field, and
+| the other 63 bits of the 'extra' field are all zero if and only if _all_but_
+| _the_last_ bits shifted off were all zero.
+|   (This function makes more sense if 'a' and 'extra' are considered to form
+| an unsigned fixed-point number with binary point between 'a' and 'extra'.
+| This fixed-point value is shifted right by the number of bits given in
+| 'dist', and the integer part of this shifted value is returned in the 'v'
+| field of the result.  The fractional part of the shifted value is modified
+| as described above and returned in the 'extra' field of the result.)
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
+INLINE
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist )
+{
+    struct uint64_extra z;
+    if ( dist < 64 ) {
+        z.v = a>>dist;
+        z.extra = a<<(-dist & 63);
+    } else {
+        z.v = 0;
+        z.extra = (dist == 64) ? a : (a != 0);
+    }
+    z.extra |= (extra != 0);
+    return z;
+}
+#else
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist );
+#endif
+#endif
+
+#ifndef softfloat_shiftRightJam128
+/*----------------------------------------------------------------------------
+| Shifts the 128 bits formed by concatenating 'a64' and 'a0' right by the
+| number of bits given in 'dist', which must not be zero.  If any nonzero bits
+| are shifted off, they are "jammed" into the least-significant bit of the
+| shifted value by setting the least-significant bit to 1.  This shifted-and-
+| jammed value is returned.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
+| greater than 128, the result will be either 0 or 1, depending on whether the
+| original 128 bits are all zeros.
+*----------------------------------------------------------------------------*/
+struct uint128
+ softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist );
+#endif
+
+#ifndef softfloat_shiftRightJam128Extra
+/*----------------------------------------------------------------------------
+| Shifts the 192 bits formed by concatenating 'a64', 'a0', and 'extra' right
+| by 64 _plus_ the number of bits given in 'dist', which must not be zero.
+| This shifted value is at most 128 nonzero bits and is returned in the 'v'
+| field of the 'struct uint128_extra' result.  The 64-bit 'extra' field of the
+| result contains a value formed as follows from the bits that were shifted
+| off:  The _last_ bit shifted off is the most-significant bit of the 'extra'
+| field, and the other 63 bits of the 'extra' field are all zero if and only
+| if _all_but_the_last_ bits shifted off were all zero.
+|   (This function makes more sense if 'a64', 'a0', and 'extra' are considered
+| to form an unsigned fixed-point number with binary point between 'a0' and
+| 'extra'.  This fixed-point value is shifted right by the number of bits
+| given in 'dist', and the integer part of this shifted value is returned
+| in the 'v' field of the result.  The fractional part of the shifted value
+| is modified as described above and returned in the 'extra' field of the
+| result.)
+*----------------------------------------------------------------------------*/
+struct uint128_extra
+ softfloat_shiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist );
+#endif
+
+#ifndef softfloat_shiftRightJam256M
+/*----------------------------------------------------------------------------
+| Shifts the 256-bit unsigned integer pointed to by 'aPtr' right by the number
+| of bits given in 'dist', which must not be zero.  If any nonzero bits are
+| shifted off, they are "jammed" into the least-significant bit of the shifted
+| value by setting the least-significant bit to 1.  This shifted-and-jammed
+| value is stored at the location pointed to by 'zPtr'.  Each of 'aPtr' and
+| 'zPtr' points to an array of four 64-bit elements that concatenate in the
+| platform's normal endian order to form a 256-bit integer.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist'
+| is greater than 256, the stored result will be either 0 or 1, depending on
+| whether the original 256 bits are all zeros.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shiftRightJam256M(
+     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr );
+#endif
+
+#ifndef softfloat_add128
+/*----------------------------------------------------------------------------
+| Returns the sum of the 128-bit integer formed by concatenating 'a64' and
+| 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'.  The
+| addition is modulo 2^128, so any carry out is lost.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+    z.v0 = a0 + b0;
+    z.v64 = a64 + b64 + (z.v0 < a0);
+    return z;
+}
+#else
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+#endif
+#endif
+
+#ifndef softfloat_add256M
+/*----------------------------------------------------------------------------
+| Adds the two 256-bit integers pointed to by 'aPtr' and 'bPtr'.  The addition
+| is modulo 2^256, so any carry out is lost.  The sum is stored at the
+| location pointed to by 'zPtr'.  Each of 'aPtr', 'bPtr', and 'zPtr' points to
+| an array of four 64-bit elements that concatenate in the platform's normal
+| endian order to form a 256-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_add256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
+#endif
+
+#ifndef softfloat_sub128
+/*----------------------------------------------------------------------------
+| Returns the difference of the 128-bit integer formed by concatenating 'a64'
+| and 'a0' and the 128-bit integer formed by concatenating 'b64' and 'b0'.
+| The subtraction is modulo 2^128, so any borrow out (carry out) is lost.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+    z.v0 = a0 - b0;
+    z.v64 = a64 - b64;
+    z.v64 -= (a0 < b0);
+    return z;
+}
+#else
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 );
+#endif
+#endif
+
+#ifndef softfloat_sub256M
+/*----------------------------------------------------------------------------
+| Subtracts the 256-bit integer pointed to by 'bPtr' from the 256-bit integer
+| pointed to by 'aPtr'.  The addition is modulo 2^256, so any borrow out
+| (carry out) is lost.  The difference is stored at the location pointed to
+| by 'zPtr'.  Each of 'aPtr', 'bPtr', and 'zPtr' points to an array of four
+| 64-bit elements that concatenate in the platform's normal endian order to
+| form a 256-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_sub256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr );
+#endif
+
+#ifndef softfloat_mul64ByShifted32To128
+/*----------------------------------------------------------------------------
+| Returns the 128-bit product of 'a', 'b', and 2^32.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (3 <= INLINE_LEVEL)
+INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+{
+    uint_fast64_t mid;
+    struct uint128 z;
+    mid = (uint_fast64_t) (uint32_t) a * b;
+    z.v0 = mid<<32;
+    z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32);
+    return z;
+}
+#else
+struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b );
+#endif
+#endif
+
+#ifndef softfloat_mul64To128
+/*----------------------------------------------------------------------------
+| Returns the 128-bit product of 'a' and 'b'.
+*----------------------------------------------------------------------------*/
+struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b );
+#endif
+
+#ifndef softfloat_mul128By32
+/*----------------------------------------------------------------------------
+| Returns the product of the 128-bit integer formed by concatenating 'a64' and
+| 'a0', multiplied by 'b'.  The multiplication is modulo 2^128; any overflow
+| bits are discarded.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (4 <= INLINE_LEVEL)
+INLINE
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+{
+    struct uint128 z;
+    uint_fast64_t mid;
+    uint_fast32_t carry;
+    z.v0 = a0 * b;
+    mid = (uint_fast64_t) (uint32_t) (a0>>32) * b;
+    carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid);
+    z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32);
+    return z;
+}
+#else
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b );
+#endif
+#endif
+
+#ifndef softfloat_mul128To256M
+/*----------------------------------------------------------------------------
+| Multiplies the 128-bit unsigned integer formed by concatenating 'a64' and
+| 'a0' by the 128-bit unsigned integer formed by concatenating 'b64' and
+| 'b0'.  The 256-bit product is stored at the location pointed to by 'zPtr'.
+| Argument 'zPtr' points to an array of four 64-bit elements that concatenate
+| in the platform's normal endian order to form a 256-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr );
+#endif
+
+#else
+
+/*----------------------------------------------------------------------------
+| The following functions are needed only when 'SOFTFLOAT_FAST_INT64' is not
+| defined.
+*----------------------------------------------------------------------------*/
+
+#ifndef softfloat_compare96M
+/*----------------------------------------------------------------------------
+| Compares the two 96-bit unsigned integers pointed to by 'aPtr' and 'bPtr'.
+| Returns -1 if the first integer (A) is less than the second (B); returns 0
+| if the two integers are equal; and returns +1 if the first integer (A)
+| is greater than the second (B).  (The result is thus the signum of A - B.)
+| Each of 'aPtr' and 'bPtr' points to an array of three 32-bit elements that
+| concatenate in the platform's normal endian order to form a 96-bit integer.
+*----------------------------------------------------------------------------*/
+int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr );
+#endif
+
+#ifndef softfloat_compare128M
+/*----------------------------------------------------------------------------
+| Compares the two 128-bit unsigned integers pointed to by 'aPtr' and 'bPtr'.
+| Returns -1 if the first integer (A) is less than the second (B); returns 0
+| if the two integers are equal; and returns +1 if the first integer (A)
+| is greater than the second (B).  (The result is thus the signum of A - B.)
+| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
+| concatenate in the platform's normal endian order to form a 128-bit integer.
+*----------------------------------------------------------------------------*/
+int_fast8_t
+ softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr );
+#endif
+
+#ifndef softfloat_shortShiftLeft64To96M
+/*----------------------------------------------------------------------------
+| Extends 'a' to 96 bits and shifts the value left by the number of bits given
+| in 'dist', which must be in the range 1 to 31.  The result is stored at the
+| location pointed to by 'zPtr'.  Argument 'zPtr' points to an array of three
+| 32-bit elements that concatenate in the platform's normal endian order to
+| form a 96-bit integer.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && (2 <= INLINE_LEVEL)
+INLINE
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
+{
+    zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist;
+    a >>= 32 - dist;
+    zPtr[indexWord( 3, 2 )] = a>>32;
+    zPtr[indexWord( 3, 1 )] = a;
+}
+#else
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr );
+#endif
+#endif
+
+#ifndef softfloat_shortShiftLeftM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must be in the range 1 to 31.  Any nonzero bits shifted off are lost.  The
+| shifted N-bit result is stored at the location pointed to by 'zPtr'.  Each
+| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements
+| that concatenate in the platform's normal endian order to form an N-bit
+| integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shortShiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_shortShiftLeft96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftLeftM' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftLeft96M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 3, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shortShiftLeft128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftLeftM' with
+| 'size_words' = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftLeft128M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 4, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shortShiftLeft160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftLeftM' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftLeft160M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 5, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftLeftM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' left by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must not be zero.  Any nonzero bits shifted off are lost.  The shifted
+| N-bit result is stored at the location pointed to by 'zPtr'.  Each of 'aPtr'
+| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that
+| concatenate in the platform's normal endian order to form an N-bit integer.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
+| greater than N, the stored result will be 0.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_shiftLeft96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftLeftM' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftLeft96M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 3, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftLeft128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftLeftM' with
+| 'size_words' = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftLeft128M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 4, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftLeft160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftLeftM' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftLeft160M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 5, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shortShiftRightM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must be in the range 1 to 31.  Any nonzero bits shifted off are lost.  The
+| shifted N-bit result is stored at the location pointed to by 'zPtr'.  Each
+| of 'aPtr' and 'zPtr' points to a 'size_words'-long array of 32-bit elements
+| that concatenate in the platform's normal endian order to form an N-bit
+| integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shortShiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_shortShiftRight128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftRightM' with
+| 'size_words' = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftRight128M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 4, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shortShiftRight160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftRightM' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftRight160M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 5, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shortShiftRightJamM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must be in the range 1 to 31.  If any nonzero bits are shifted off, they are
+| "jammed" into the least-significant bit of the shifted value by setting the
+| least-significant bit to 1.  This shifted-and-jammed N-bit result is stored
+| at the location pointed to by 'zPtr'.  Each of 'aPtr' and 'zPtr' points
+| to a 'size_words'-long array of 32-bit elements that concatenate in the
+| platform's normal endian order to form an N-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shortShiftRightJamM(
+     uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * );
+#endif
+
+#ifndef softfloat_shortShiftRightJam160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shortShiftRightJamM' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_shortShiftRightJam160M( aPtr, dist, zPtr ) softfloat_shortShiftRightJamM( 5, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftRightM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must not be zero.  Any nonzero bits shifted off are lost.  The shifted
+| N-bit result is stored at the location pointed to by 'zPtr'.  Each of 'aPtr'
+| and 'zPtr' points to a 'size_words'-long array of 32-bit elements that
+| concatenate in the platform's normal endian order to form an N-bit integer.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist' is
+| greater than N, the stored result will be 0.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_shiftRight96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftRightM' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftRight96M( aPtr, dist, zPtr ) softfloat_shiftRightM( 3, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftRightJamM
+/*----------------------------------------------------------------------------
+| Shifts the N-bit unsigned integer pointed to by 'aPtr' right by the number
+| of bits given in 'dist', where N = 'size_words' * 32.  The value of 'dist'
+| must not be zero.  If any nonzero bits are shifted off, they are "jammed"
+| into the least-significant bit of the shifted value by setting the least-
+| significant bit to 1.  This shifted-and-jammed N-bit result is stored
+| at the location pointed to by 'zPtr'.  Each of 'aPtr' and 'zPtr' points
+| to a 'size_words'-long array of 32-bit elements that concatenate in the
+| platform's normal endian order to form an N-bit integer.
+|   The value of 'dist' can be arbitrarily large.  In particular, if 'dist'
+| is greater than N, the stored result will be either 0 or 1, depending on
+| whether the original N bits are all zeros.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_shiftRightJamM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_shiftRightJam96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftRightJamM' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftRightJam96M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 3, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftRightJam128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftRightJamM' with
+| 'size_words' = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftRightJam128M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 4, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_shiftRightJam160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_shiftRightJamM' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_shiftRightJam160M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 5, aPtr, dist, zPtr )
+#endif
+
+#ifndef softfloat_addM
+/*----------------------------------------------------------------------------
+| Adds the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N =
+| 'size_words' * 32.  The addition is modulo 2^N, so any carry out is lost.
+| The N-bit sum is stored at the location pointed to by 'zPtr'.  Each of
+| 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long array of 32-bit
+| elements that concatenate in the platform's normal endian order to form an
+| N-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_addM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_add96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_addM' with 'size_words'
+| = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_add96M( aPtr, bPtr, zPtr ) softfloat_addM( 3, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_add128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_addM' with 'size_words'
+| = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_add128M( aPtr, bPtr, zPtr ) softfloat_addM( 4, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_add160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_addM' with 'size_words'
+| = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_add160M( aPtr, bPtr, zPtr ) softfloat_addM( 5, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_addCarryM
+/*----------------------------------------------------------------------------
+| Adds the two N-bit unsigned integers pointed to by 'aPtr' and 'bPtr', where
+| N = 'size_words' * 32, plus 'carry', which must be either 0 or 1.  The N-bit
+| sum (modulo 2^N) is stored at the location pointed to by 'zPtr', and any
+| carry out is returned as the result.  Each of 'aPtr', 'bPtr', and 'zPtr'
+| points to a 'size_words'-long array of 32-bit elements that concatenate in
+| the platform's normal endian order to form an N-bit integer.
+*----------------------------------------------------------------------------*/
+uint_fast8_t
+ softfloat_addCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_addComplCarryM
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_addCarryM', except that
+| the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed
+| before the addition.
+*----------------------------------------------------------------------------*/
+uint_fast8_t
+ softfloat_addComplCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_addComplCarry96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_addComplCarryM' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_addComplCarry96M( aPtr, bPtr, carry, zPtr ) softfloat_addComplCarryM( 3, aPtr, bPtr, carry, zPtr )
+#endif
+
+#ifndef softfloat_negXM
+/*----------------------------------------------------------------------------
+| Replaces the N-bit unsigned integer pointed to by 'zPtr' by the
+| 2s-complement of itself, where N = 'size_words' * 32.  Argument 'zPtr'
+| points to a 'size_words'-long array of 32-bit elements that concatenate in
+| the platform's normal endian order to form an N-bit integer.
+*----------------------------------------------------------------------------*/
+void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr );
+#endif
+
+#ifndef softfloat_negX96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_negXM' with 'size_words'
+| = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_negX96M( zPtr ) softfloat_negXM( 3, zPtr )
+#endif
+
+#ifndef softfloat_negX128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_negXM' with 'size_words'
+| = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_negX128M( zPtr ) softfloat_negXM( 4, zPtr )
+#endif
+
+#ifndef softfloat_negX160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_negXM' with 'size_words'
+| = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_negX160M( zPtr ) softfloat_negXM( 5, zPtr )
+#endif
+
+#ifndef softfloat_negX256M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_negXM' with 'size_words'
+| = 8 (N = 256).
+*----------------------------------------------------------------------------*/
+#define softfloat_negX256M( zPtr ) softfloat_negXM( 8, zPtr )
+#endif
+
+#ifndef softfloat_sub1XM
+/*----------------------------------------------------------------------------
+| Subtracts 1 from the N-bit integer pointed to by 'zPtr', where N =
+| 'size_words' * 32.  The subtraction is modulo 2^N, so any borrow out (carry
+| out) is lost.  Argument 'zPtr' points to a 'size_words'-long array of 32-bit
+| elements that concatenate in the platform's normal endian order to form an
+| N-bit integer.
+*----------------------------------------------------------------------------*/
+void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr );
+#endif
+
+#ifndef softfloat_sub1X96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_sub1XM' with 'size_words'
+| = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_sub1X96M( zPtr ) softfloat_sub1XM( 3, zPtr )
+#endif
+
+#ifndef softfloat_sub1X160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_sub1XM' with 'size_words'
+| = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_sub1X160M( zPtr ) softfloat_sub1XM( 5, zPtr )
+#endif
+
+#ifndef softfloat_subM
+/*----------------------------------------------------------------------------
+| Subtracts the two N-bit integers pointed to by 'aPtr' and 'bPtr', where N =
+| 'size_words' * 32.  The subtraction is modulo 2^N, so any borrow out (carry
+| out) is lost.  The N-bit difference is stored at the location pointed to by
+| 'zPtr'.  Each of 'aPtr', 'bPtr', and 'zPtr' points to a 'size_words'-long
+| array of 32-bit elements that concatenate in the platform's normal endian
+| order to form an N-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_subM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_sub96M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_subM' with 'size_words'
+| = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_sub96M( aPtr, bPtr, zPtr ) softfloat_subM( 3, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_sub128M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_subM' with 'size_words'
+| = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_sub128M( aPtr, bPtr, zPtr ) softfloat_subM( 4, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_sub160M
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_subM' with 'size_words'
+| = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_sub160M( aPtr, bPtr, zPtr ) softfloat_subM( 5, aPtr, bPtr, zPtr )
+#endif
+
+#ifndef softfloat_mul64To128M
+/*----------------------------------------------------------------------------
+| Multiplies 'a' and 'b' and stores the 128-bit product at the location
+| pointed to by 'zPtr'.  Argument 'zPtr' points to an array of four 32-bit
+| elements that concatenate in the platform's normal endian order to form a
+| 128-bit integer.
+*----------------------------------------------------------------------------*/
+void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr );
+#endif
+
+#ifndef softfloat_mul128MTo256M
+/*----------------------------------------------------------------------------
+| Multiplies the two 128-bit unsigned integers pointed to by 'aPtr' and
+| 'bPtr', and stores the 256-bit product at the location pointed to by 'zPtr'.
+| Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that
+| concatenate in the platform's normal endian order to form a 128-bit integer.
+| Argument 'zPtr' points to an array of eight 32-bit elements that concatenate
+| to form a 256-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_mul128MTo256M(
+     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr );
+#endif
+
+#ifndef softfloat_remStepMBy32
+/*----------------------------------------------------------------------------
+| Performs a "remainder reduction step" as follows:  Arguments 'remPtr' and
+| 'bPtr' both point to N-bit unsigned integers, where N = 'size_words' * 32.
+| Defining R and B as the values of those integers, the expression (R<<'dist')
+| - B * q is computed modulo 2^N, and the N-bit result is stored at the
+| location pointed to by 'zPtr'.  Each of 'remPtr', 'bPtr', and 'zPtr' points
+| to a 'size_words'-long array of 32-bit elements that concatenate in the
+| platform's normal endian order to form an N-bit integer.
+*----------------------------------------------------------------------------*/
+void
+ softfloat_remStepMBy32(
+     uint_fast8_t size_words,
+     const uint32_t *remPtr,
+     uint_fast8_t dist,
+     const uint32_t *bPtr,
+     uint32_t q,
+     uint32_t *zPtr
+ );
+#endif
+
+#ifndef softfloat_remStep96MBy32
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_remStepMBy32' with
+| 'size_words' = 3 (N = 96).
+*----------------------------------------------------------------------------*/
+#define softfloat_remStep96MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 3, remPtr, dist, bPtr, q, zPtr )
+#endif
+
+#ifndef softfloat_remStep128MBy32
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_remStepMBy32' with
+| 'size_words' = 4 (N = 128).
+*----------------------------------------------------------------------------*/
+#define softfloat_remStep128MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 4, remPtr, dist, bPtr, q, zPtr )
+#endif
+
+#ifndef softfloat_remStep160MBy32
+/*----------------------------------------------------------------------------
+| This function or macro is the same as 'softfloat_remStepMBy32' with
+| 'size_words' = 5 (N = 160).
+*----------------------------------------------------------------------------*/
+#define softfloat_remStep160MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 5, remPtr, dist, bPtr, q, zPtr )
+#endif
+
+#endif
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/include/softfloat.h b/addins/SoftFloat-3e/source/include/softfloat.h
new file mode 100644
index 000000000..b33374cd6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/softfloat.h
@@ -0,0 +1,372 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+
+/*============================================================================
+| Note:  If SoftFloat is made available as a general library for programs to
+| use, it is strongly recommended that a platform-specific version of this
+| header, "softfloat.h", be created that folds in "softfloat_types.h" and that
+| eliminates all dependencies on compile-time macros.
+*============================================================================*/
+
+
+#ifndef softfloat_h
+#define softfloat_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat_types.h"
+
+#ifndef THREAD_LOCAL
+#define THREAD_LOCAL
+#endif
+
+/*----------------------------------------------------------------------------
+| Software floating-point underflow tininess-detection mode.
+*----------------------------------------------------------------------------*/
+extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess;
+enum {
+    softfloat_tininess_beforeRounding = 0,
+    softfloat_tininess_afterRounding  = 1
+};
+
+/*----------------------------------------------------------------------------
+| Software floating-point rounding mode.  (Mode "odd" is supported only if
+| SoftFloat is compiled with macro 'SOFTFLOAT_ROUND_ODD' defined.)
+*----------------------------------------------------------------------------*/
+extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode;
+enum {
+    softfloat_round_near_even   = 0,
+    softfloat_round_minMag      = 1,
+    softfloat_round_min         = 2,
+    softfloat_round_max         = 3,
+    softfloat_round_near_maxMag = 4,
+    softfloat_round_odd         = 6
+};
+
+/*----------------------------------------------------------------------------
+| Software floating-point exception flags.
+*----------------------------------------------------------------------------*/
+extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags;
+enum {
+    softfloat_flag_inexact   =  1,
+    softfloat_flag_underflow =  2,
+    softfloat_flag_overflow  =  4,
+    softfloat_flag_infinite  =  8,
+    softfloat_flag_invalid   = 16
+};
+
+/*----------------------------------------------------------------------------
+| Routine to raise any or all of the software floating-point exception flags.
+*----------------------------------------------------------------------------*/
+void softfloat_raiseFlags( uint_fast8_t );
+
+/*----------------------------------------------------------------------------
+| Integer-to-floating-point conversion routines.
+*----------------------------------------------------------------------------*/
+float16_t ui32_to_f16( uint32_t );
+float32_t ui32_to_f32( uint32_t );
+float64_t ui32_to_f64( uint32_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t ui32_to_extF80( uint32_t );
+float128_t ui32_to_f128( uint32_t );
+#endif
+void ui32_to_extF80M( uint32_t, extFloat80_t * );
+void ui32_to_f128M( uint32_t, float128_t * );
+float16_t ui64_to_f16( uint64_t );
+float32_t ui64_to_f32( uint64_t );
+float64_t ui64_to_f64( uint64_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t ui64_to_extF80( uint64_t );
+float128_t ui64_to_f128( uint64_t );
+#endif
+void ui64_to_extF80M( uint64_t, extFloat80_t * );
+void ui64_to_f128M( uint64_t, float128_t * );
+float16_t i32_to_f16( int32_t );
+float32_t i32_to_f32( int32_t );
+float64_t i32_to_f64( int32_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t i32_to_extF80( int32_t );
+float128_t i32_to_f128( int32_t );
+#endif
+void i32_to_extF80M( int32_t, extFloat80_t * );
+void i32_to_f128M( int32_t, float128_t * );
+float16_t i64_to_f16( int64_t );
+float32_t i64_to_f32( int64_t );
+float64_t i64_to_f64( int64_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t i64_to_extF80( int64_t );
+float128_t i64_to_f128( int64_t );
+#endif
+void i64_to_extF80M( int64_t, extFloat80_t * );
+void i64_to_f128M( int64_t, float128_t * );
+
+/*----------------------------------------------------------------------------
+| 16-bit (half-precision) floating-point operations.
+*----------------------------------------------------------------------------*/
+uint_fast32_t f16_to_ui32( float16_t, uint_fast8_t, bool );
+uint_fast64_t f16_to_ui64( float16_t, uint_fast8_t, bool );
+int_fast32_t f16_to_i32( float16_t, uint_fast8_t, bool );
+int_fast64_t f16_to_i64( float16_t, uint_fast8_t, bool );
+uint_fast32_t f16_to_ui32_r_minMag( float16_t, bool );
+uint_fast64_t f16_to_ui64_r_minMag( float16_t, bool );
+int_fast32_t f16_to_i32_r_minMag( float16_t, bool );
+int_fast64_t f16_to_i64_r_minMag( float16_t, bool );
+float32_t f16_to_f32( float16_t );
+float64_t f16_to_f64( float16_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t f16_to_extF80( float16_t );
+float128_t f16_to_f128( float16_t );
+#endif
+void f16_to_extF80M( float16_t, extFloat80_t * );
+void f16_to_f128M( float16_t, float128_t * );
+float16_t f16_roundToInt( float16_t, uint_fast8_t, bool );
+float16_t f16_add( float16_t, float16_t );
+float16_t f16_sub( float16_t, float16_t );
+float16_t f16_mul( float16_t, float16_t );
+float16_t f16_mulAdd( float16_t, float16_t, float16_t );
+float16_t f16_div( float16_t, float16_t );
+float16_t f16_rem( float16_t, float16_t );
+float16_t f16_sqrt( float16_t );
+bool f16_eq( float16_t, float16_t );
+bool f16_le( float16_t, float16_t );
+bool f16_lt( float16_t, float16_t );
+bool f16_eq_signaling( float16_t, float16_t );
+bool f16_le_quiet( float16_t, float16_t );
+bool f16_lt_quiet( float16_t, float16_t );
+bool f16_isSignalingNaN( float16_t );
+
+/*----------------------------------------------------------------------------
+| 32-bit (single-precision) floating-point operations.
+*----------------------------------------------------------------------------*/
+uint_fast32_t f32_to_ui32( float32_t, uint_fast8_t, bool );
+uint_fast64_t f32_to_ui64( float32_t, uint_fast8_t, bool );
+int_fast32_t f32_to_i32( float32_t, uint_fast8_t, bool );
+int_fast64_t f32_to_i64( float32_t, uint_fast8_t, bool );
+uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool );
+uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool );
+int_fast32_t f32_to_i32_r_minMag( float32_t, bool );
+int_fast64_t f32_to_i64_r_minMag( float32_t, bool );
+float16_t f32_to_f16( float32_t );
+float64_t f32_to_f64( float32_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t f32_to_extF80( float32_t );
+float128_t f32_to_f128( float32_t );
+#endif
+void f32_to_extF80M( float32_t, extFloat80_t * );
+void f32_to_f128M( float32_t, float128_t * );
+float32_t f32_roundToInt( float32_t, uint_fast8_t, bool );
+float32_t f32_add( float32_t, float32_t );
+float32_t f32_sub( float32_t, float32_t );
+float32_t f32_mul( float32_t, float32_t );
+float32_t f32_mulAdd( float32_t, float32_t, float32_t );
+float32_t f32_div( float32_t, float32_t );
+float32_t f32_rem( float32_t, float32_t );
+float32_t f32_sqrt( float32_t );
+bool f32_eq( float32_t, float32_t );
+bool f32_le( float32_t, float32_t );
+bool f32_lt( float32_t, float32_t );
+bool f32_eq_signaling( float32_t, float32_t );
+bool f32_le_quiet( float32_t, float32_t );
+bool f32_lt_quiet( float32_t, float32_t );
+bool f32_isSignalingNaN( float32_t );
+
+/*----------------------------------------------------------------------------
+| 64-bit (double-precision) floating-point operations.
+*----------------------------------------------------------------------------*/
+uint_fast32_t f64_to_ui32( float64_t, uint_fast8_t, bool );
+uint_fast64_t f64_to_ui64( float64_t, uint_fast8_t, bool );
+int_fast32_t f64_to_i32( float64_t, uint_fast8_t, bool );
+int_fast64_t f64_to_i64( float64_t, uint_fast8_t, bool );
+uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool );
+uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool );
+int_fast32_t f64_to_i32_r_minMag( float64_t, bool );
+int_fast64_t f64_to_i64_r_minMag( float64_t, bool );
+float16_t f64_to_f16( float64_t );
+float32_t f64_to_f32( float64_t );
+#ifdef SOFTFLOAT_FAST_INT64
+extFloat80_t f64_to_extF80( float64_t );
+float128_t f64_to_f128( float64_t );
+#endif
+void f64_to_extF80M( float64_t, extFloat80_t * );
+void f64_to_f128M( float64_t, float128_t * );
+float64_t f64_roundToInt( float64_t, uint_fast8_t, bool );
+float64_t f64_add( float64_t, float64_t );
+float64_t f64_sub( float64_t, float64_t );
+float64_t f64_mul( float64_t, float64_t );
+float64_t f64_mulAdd( float64_t, float64_t, float64_t );
+float64_t f64_div( float64_t, float64_t );
+float64_t f64_rem( float64_t, float64_t );
+float64_t f64_sqrt( float64_t );
+bool f64_eq( float64_t, float64_t );
+bool f64_le( float64_t, float64_t );
+bool f64_lt( float64_t, float64_t );
+bool f64_eq_signaling( float64_t, float64_t );
+bool f64_le_quiet( float64_t, float64_t );
+bool f64_lt_quiet( float64_t, float64_t );
+bool f64_isSignalingNaN( float64_t );
+
+/*----------------------------------------------------------------------------
+| Rounding precision for 80-bit extended double-precision floating-point.
+| Valid values are 32, 64, and 80.
+*----------------------------------------------------------------------------*/
+extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision;
+
+/*----------------------------------------------------------------------------
+| 80-bit extended double-precision floating-point operations.
+*----------------------------------------------------------------------------*/
+#ifdef SOFTFLOAT_FAST_INT64
+uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool );
+uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool );
+int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool );
+int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool );
+uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool );
+uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool );
+int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool );
+int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool );
+float16_t extF80_to_f16( extFloat80_t );
+float32_t extF80_to_f32( extFloat80_t );
+float64_t extF80_to_f64( extFloat80_t );
+float128_t extF80_to_f128( extFloat80_t );
+extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool );
+extFloat80_t extF80_add( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_sub( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_mul( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_div( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_rem( extFloat80_t, extFloat80_t );
+extFloat80_t extF80_sqrt( extFloat80_t );
+bool extF80_eq( extFloat80_t, extFloat80_t );
+bool extF80_le( extFloat80_t, extFloat80_t );
+bool extF80_lt( extFloat80_t, extFloat80_t );
+bool extF80_eq_signaling( extFloat80_t, extFloat80_t );
+bool extF80_le_quiet( extFloat80_t, extFloat80_t );
+bool extF80_lt_quiet( extFloat80_t, extFloat80_t );
+bool extF80_isSignalingNaN( extFloat80_t );
+#endif
+uint_fast32_t extF80M_to_ui32( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast64_t extF80M_to_ui64( const extFloat80_t *, uint_fast8_t, bool );
+int_fast32_t extF80M_to_i32( const extFloat80_t *, uint_fast8_t, bool );
+int_fast64_t extF80M_to_i64( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *, bool );
+uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *, bool );
+int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *, bool );
+int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *, bool );
+float16_t extF80M_to_f16( const extFloat80_t * );
+float32_t extF80M_to_f32( const extFloat80_t * );
+float64_t extF80M_to_f64( const extFloat80_t * );
+void extF80M_to_f128M( const extFloat80_t *, float128_t * );
+void
+ extF80M_roundToInt(
+     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
+void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_div( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_rem( const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void extF80M_sqrt( const extFloat80_t *, extFloat80_t * );
+bool extF80M_eq( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_le( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_lt( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_isSignalingNaN( const extFloat80_t * );
+
+/*----------------------------------------------------------------------------
+| 128-bit (quadruple-precision) floating-point operations.
+*----------------------------------------------------------------------------*/
+#ifdef SOFTFLOAT_FAST_INT64
+uint_fast32_t f128_to_ui32( float128_t, uint_fast8_t, bool );
+uint_fast64_t f128_to_ui64( float128_t, uint_fast8_t, bool );
+int_fast32_t f128_to_i32( float128_t, uint_fast8_t, bool );
+int_fast64_t f128_to_i64( float128_t, uint_fast8_t, bool );
+uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool );
+uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool );
+int_fast32_t f128_to_i32_r_minMag( float128_t, bool );
+int_fast64_t f128_to_i64_r_minMag( float128_t, bool );
+float16_t f128_to_f16( float128_t );
+float32_t f128_to_f32( float128_t );
+float64_t f128_to_f64( float128_t );
+extFloat80_t f128_to_extF80( float128_t );
+float128_t f128_roundToInt( float128_t, uint_fast8_t, bool );
+float128_t f128_add( float128_t, float128_t );
+float128_t f128_sub( float128_t, float128_t );
+float128_t f128_mul( float128_t, float128_t );
+float128_t f128_mulAdd( float128_t, float128_t, float128_t );
+float128_t f128_div( float128_t, float128_t );
+float128_t f128_rem( float128_t, float128_t );
+float128_t f128_sqrt( float128_t );
+bool f128_eq( float128_t, float128_t );
+bool f128_le( float128_t, float128_t );
+bool f128_lt( float128_t, float128_t );
+bool f128_eq_signaling( float128_t, float128_t );
+bool f128_le_quiet( float128_t, float128_t );
+bool f128_lt_quiet( float128_t, float128_t );
+bool f128_isSignalingNaN( float128_t );
+#endif
+uint_fast32_t f128M_to_ui32( const float128_t *, uint_fast8_t, bool );
+uint_fast64_t f128M_to_ui64( const float128_t *, uint_fast8_t, bool );
+int_fast32_t f128M_to_i32( const float128_t *, uint_fast8_t, bool );
+int_fast64_t f128M_to_i64( const float128_t *, uint_fast8_t, bool );
+uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *, bool );
+uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *, bool );
+int_fast32_t f128M_to_i32_r_minMag( const float128_t *, bool );
+int_fast64_t f128M_to_i64_r_minMag( const float128_t *, bool );
+float16_t f128M_to_f16( const float128_t * );
+float32_t f128M_to_f32( const float128_t * );
+float64_t f128M_to_f64( const float128_t * );
+void f128M_to_extF80M( const float128_t *, extFloat80_t * );
+void f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * );
+void f128M_add( const float128_t *, const float128_t *, float128_t * );
+void f128M_sub( const float128_t *, const float128_t *, float128_t * );
+void f128M_mul( const float128_t *, const float128_t *, float128_t * );
+void
+ f128M_mulAdd(
+     const float128_t *, const float128_t *, const float128_t *, float128_t *
+ );
+void f128M_div( const float128_t *, const float128_t *, float128_t * );
+void f128M_rem( const float128_t *, const float128_t *, float128_t * );
+void f128M_sqrt( const float128_t *, float128_t * );
+bool f128M_eq( const float128_t *, const float128_t * );
+bool f128M_le( const float128_t *, const float128_t * );
+bool f128M_lt( const float128_t *, const float128_t * );
+bool f128M_eq_signaling( const float128_t *, const float128_t * );
+bool f128M_le_quiet( const float128_t *, const float128_t * );
+bool f128M_lt_quiet( const float128_t *, const float128_t * );
+bool f128M_isSignalingNaN( const float128_t * );
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/include/softfloat_types.h b/addins/SoftFloat-3e/source/include/softfloat_types.h
new file mode 100644
index 000000000..bc30e3144
--- /dev/null
+++ b/addins/SoftFloat-3e/source/include/softfloat_types.h
@@ -0,0 +1,81 @@
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef softfloat_types_h
+#define softfloat_types_h 1
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+| Types used to pass 16-bit, 32-bit, 64-bit, and 128-bit floating-point
+| arguments and results to/from functions.  These types must be exactly
+| 16 bits, 32 bits, 64 bits, and 128 bits in size, respectively.  Where a
+| platform has "native" support for IEEE-Standard floating-point formats,
+| the types below may, if desired, be defined as aliases for the native types
+| (typically 'float' and 'double', and possibly 'long double').
+*----------------------------------------------------------------------------*/
+typedef struct { uint16_t v; } float16_t;
+typedef struct { uint32_t v; } float32_t;
+typedef struct { uint64_t v; } float64_t;
+typedef struct { uint64_t v[2]; } float128_t;
+
+/*----------------------------------------------------------------------------
+| The format of an 80-bit extended floating-point number in memory.  This
+| structure must contain a 16-bit field named 'signExp' and a 64-bit field
+| named 'signif'.
+*----------------------------------------------------------------------------*/
+#ifdef LITTLEENDIAN
+struct extFloat80M { uint64_t signif; uint16_t signExp; };
+#else
+struct extFloat80M { uint16_t signExp; uint64_t signif; };
+#endif
+
+/*----------------------------------------------------------------------------
+| The type used to pass 80-bit extended floating-point arguments and
+| results to/from functions.  This type must have size identical to
+| 'struct extFloat80M'.  Type 'extFloat80_t' can be defined as an alias for
+| 'struct extFloat80M'.  Alternatively, if a platform has "native" support
+| for IEEE-Standard 80-bit extended floating-point, it may be possible,
+| if desired, to define 'extFloat80_t' as an alias for the native type
+| (presumably either 'long double' or a nonstandard compiler-intrinsic type).
+| In that case, the 'signif' and 'signExp' fields of 'struct extFloat80M'
+| must align exactly with the locations in memory of the sign, exponent, and
+| significand of the native type.
+*----------------------------------------------------------------------------*/
+typedef struct extFloat80M extFloat80_t;
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_add128.c b/addins/SoftFloat-3e/source/s_add128.c
new file mode 100644
index 000000000..5a9d5082a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_add128.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_add128
+
+struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+
+    z.v0 = a0 + b0;
+    z.v64 = a64 + b64 + (z.v0 < a0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_add256M.c b/addins/SoftFloat-3e/source/s_add256M.c
new file mode 100644
index 000000000..4fb46a174
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_add256M.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_add256M
+
+void
+ softfloat_add256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr )
+{
+    unsigned int index;
+    uint_fast8_t carry;
+    uint64_t wordA, wordZ;
+
+    index = indexWordLo( 4 );
+    carry = 0;
+    for (;;) {
+        wordA = aPtr[index];
+        wordZ = wordA + bPtr[index] + carry;
+        zPtr[index] = wordZ;
+        if ( index == indexWordHi( 4 ) ) break;
+        if ( wordZ != wordA ) carry = (wordZ < wordA);
+        index += wordIncr;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_addCarryM.c b/addins/SoftFloat-3e/source/s_addCarryM.c
new file mode 100644
index 000000000..f0ccf6724
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addCarryM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_addCarryM
+
+uint_fast8_t
+ softfloat_addCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ )
+{
+    unsigned int index, lastIndex;
+    uint32_t wordA, wordZ;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    for (;;) {
+        wordA = aPtr[index];
+        wordZ = wordA + bPtr[index] + carry;
+        zPtr[index] = wordZ;
+        if ( wordZ != wordA ) carry = (wordZ < wordA);
+        if ( index == lastIndex ) break;
+        index += wordIncr;
+    }
+    return carry;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_addComplCarryM.c b/addins/SoftFloat-3e/source/s_addComplCarryM.c
new file mode 100644
index 000000000..e1584c669
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addComplCarryM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_addComplCarryM
+
+uint_fast8_t
+ softfloat_addComplCarryM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint_fast8_t carry,
+     uint32_t *zPtr
+ )
+{
+    unsigned int index, lastIndex;
+    uint32_t wordA, wordZ;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    for (;;) {
+        wordA = aPtr[index];
+        wordZ = wordA + ~bPtr[index] + carry;
+        zPtr[index] = wordZ;
+        if ( wordZ != wordA ) carry = (wordZ < wordA);
+        if ( index == lastIndex ) break;
+        index += wordIncr;
+    }
+    return carry;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_addExtF80M.c b/addins/SoftFloat-3e/source/s_addExtF80M.c
new file mode 100644
index 000000000..febfb6577
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addExtF80M.c
@@ -0,0 +1,186 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+void
+ softfloat_addExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr,
+     bool negateB
+ )
+{
+    uint32_t uiA64;
+    int32_t expA;
+    uint32_t uiB64;
+    int32_t expB;
+    uint32_t uiZ64;
+    bool signZ, signB;
+    const struct extFloat80M *tempSPtr;
+    uint64_t sigZ, sigB;
+    void
+     (*roundPackRoutinePtr)(
+         bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * );
+    int32_t expDiff;
+    uint32_t extSigX[3], sigZExtra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    expA = expExtF80UI64( uiA64 );
+    uiB64 = bSPtr->signExp;
+    expB = expExtF80UI64( uiB64 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNExtF80M( aSPtr, bSPtr, zSPtr ) ) return;
+        uiZ64 = uiA64;
+        if ( expB == 0x7FFF ) {
+            uiZ64 = uiB64 ^ packToExtF80UI64( negateB, 0 );
+            if ( (expA == 0x7FFF) && (uiZ64 != uiA64) ) {
+                softfloat_invalidExtF80M( zSPtr );
+                return;
+            }
+        }
+        zSPtr->signExp = uiZ64;
+        zSPtr->signif = UINT64_C( 0x8000000000000000 );
+        return;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signZ = signExtF80UI64( uiA64 );
+    signB = signExtF80UI64( uiB64 ) ^ negateB;
+    negateB = (signZ != signB);
+    if ( expA < expB ) {
+        signZ = signB;
+        expA = expB;
+        expB = expExtF80UI64( uiA64 );
+        tempSPtr = aSPtr;
+        aSPtr = bSPtr;
+        bSPtr = tempSPtr;
+    }
+    if ( ! expB ) {
+        expB = 1;
+        if ( ! expA ) expA = 1;
+    }
+    sigZ = aSPtr->signif;
+    sigB = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundPackRoutinePtr = softfloat_roundPackMToExtF80M;
+    expDiff = expA - expB;
+    if ( expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        extSigX[indexWord( 3, 2 )] = sigB>>32;
+        extSigX[indexWord( 3, 1 )] = sigB;
+        extSigX[indexWord( 3, 0 )] = 0;
+        softfloat_shiftRightJam96M( extSigX, expDiff, extSigX );
+        sigB =
+            (uint64_t) extSigX[indexWord( 3, 2 )]<<32
+                | extSigX[indexWord( 3, 1 )];
+        if ( negateB ) {
+            sigZ -= sigB;
+            sigZExtra = extSigX[indexWordLo( 3 )];
+            if ( sigZExtra ) {
+                --sigZ;
+                sigZExtra = -sigZExtra;
+            }
+            if ( ! (sigZ & UINT64_C( 0x8000000000000000 )) ) {
+                if ( sigZ & UINT64_C( 0x4000000000000000 ) ) {
+                    --expA;
+                    sigZ = sigZ<<1 | sigZExtra>>31;
+                    sigZExtra <<= 1;
+                } else {
+                    roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M;
+                }
+            }
+        } else {
+            sigZ += sigB;
+            if ( sigZ & UINT64_C( 0x8000000000000000 ) ) goto sigZ;
+            sigZExtra = (uint32_t) sigZ<<31 | (extSigX[indexWordLo( 3 )] != 0);
+            goto completeNormAfterAdd;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sigZExtra = 0;
+        if ( negateB ) {
+            if ( sigZ < sigB ) {
+                signZ = ! signZ;
+                sigZ = sigB - sigZ;
+            } else {
+                sigZ -= sigB;
+                if ( ! sigZ ) {
+                    signZ = (softfloat_roundingMode == softfloat_round_min);
+                    zSPtr->signExp = packToExtF80UI64( signZ, 0 );
+                    zSPtr->signif = 0;
+                    return;
+                }
+            }
+            roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M;
+        } else {
+            sigZ += sigB;
+            if ( sigZ < sigB ) {
+                sigZExtra = (uint32_t) sigZ<<31;
+ completeNormAfterAdd:
+                ++expA;
+                sigZ = UINT64_C( 0x8000000000000000 ) | sigZ>>1;
+            } else {
+                if ( ! (sigZ & UINT64_C( 0x8000000000000000 )) ) {
+                    roundPackRoutinePtr = softfloat_normRoundPackMToExtF80M;
+                }
+            }
+        }
+    }
+    extSigX[indexWord( 3, 0 )] = sigZExtra;
+ sigZ:
+    extSigX[indexWord( 3, 2 )] = sigZ>>32;
+    extSigX[indexWord( 3, 1 )] = sigZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ roundPack:
+    (*roundPackRoutinePtr)(
+        signZ, expA, extSigX, extF80_roundingPrecision, zSPtr );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addF128M.c b/addins/SoftFloat-3e/source/s_addF128M.c
new file mode 100644
index 000000000..8ed9d271f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addF128M.c
@@ -0,0 +1,211 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+void
+ softfloat_addF128M(
+     const uint32_t *aWPtr,
+     const uint32_t *bWPtr,
+     uint32_t *zWPtr,
+     bool negateB
+ )
+{
+    uint32_t uiA96;
+    int32_t expA;
+    uint32_t uiB96;
+    int32_t expB;
+    uint32_t uiZ96;
+    bool signZ, signB;
+    const uint32_t *tempPtr;
+    uint32_t sig96A, sig96B;
+    int32_t expDiff;
+    uint_fast8_t
+     (*addCarryMRoutinePtr)(
+         uint_fast8_t,
+         const uint32_t *,
+         const uint32_t *,
+         uint_fast8_t,
+         uint32_t *
+     );
+    uint32_t extSigZ[5], wordSigZ;
+    uint_fast8_t carry;
+    void (*roundPackRoutinePtr)( bool, int32_t, uint32_t *, uint32_t * );
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    expA = expF128UI96( uiA96 );
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    expB = expF128UI96( uiB96 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) return;
+        uiZ96 = uiA96;
+        if ( expB == 0x7FFF ) {
+            uiZ96 = uiB96 ^ packToF128UI96( negateB, 0, 0 );
+            if ( (expA == 0x7FFF) && (uiZ96 != uiA96) ) {
+                softfloat_invalidF128M( zWPtr );
+                return;
+            }
+        }
+        zWPtr[indexWordHi( 4 )] = uiZ96;
+        zWPtr[indexWord( 4, 2 )] = 0;
+        zWPtr[indexWord( 4, 1 )] = 0;
+        zWPtr[indexWord( 4, 0 )] = 0;
+        return;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signZ = signF128UI96( uiA96 );
+    signB = signF128UI96( uiB96 ) ^ negateB;
+    negateB = (signZ != signB);
+    if ( (uint32_t) (uiA96<<1) < (uint32_t) (uiB96<<1) ) {
+        signZ = signB;
+        expA = expB;
+        expB = expF128UI96( uiA96 );
+        tempPtr = aWPtr;
+        aWPtr = bWPtr;
+        bWPtr = tempPtr;
+        uiA96 = uiB96;
+        uiB96 = bWPtr[indexWordHi( 4 )];
+    }
+    sig96A = fracF128UI96( uiA96 );
+    sig96B = fracF128UI96( uiB96 );
+    if ( expA ) {
+        --expA;
+        sig96A |= 0x00010000;
+        if ( expB ) {
+            --expB;
+            sig96B |= 0x00010000;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    addCarryMRoutinePtr =
+        negateB ? softfloat_addComplCarryM : softfloat_addCarryM;
+    expDiff = expA - expB;
+    if ( expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        extSigZ[indexWordHi( 5 )] = sig96B;
+        extSigZ[indexWord( 5, 3 )] = bWPtr[indexWord( 4, 2 )];
+        extSigZ[indexWord( 5, 2 )] = bWPtr[indexWord( 4, 1 )];
+        extSigZ[indexWord( 5, 1 )] = bWPtr[indexWord( 4, 0 )];
+        extSigZ[indexWord( 5, 0 )] = 0;
+        softfloat_shiftRightJam160M( extSigZ, expDiff, extSigZ );
+        sig96B = extSigZ[indexWordHi( 5 )];
+        carry = 0;
+        if ( negateB ) {
+            sig96B = ~sig96B;
+            wordSigZ = extSigZ[indexWordLo( 5 )];
+            extSigZ[indexWordLo( 5 )] = -wordSigZ;
+            carry = ! wordSigZ;
+        }
+        carry =
+            (*addCarryMRoutinePtr)(
+                3,
+                &aWPtr[indexMultiwordLo( 4, 3 )],
+                &extSigZ[indexMultiword( 5, 3, 1 )],
+                carry,
+                &extSigZ[indexMultiword( 5, 3, 1 )]
+            );
+        wordSigZ = sig96A + sig96B + carry;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        extSigZ[indexWordLo( 5 )] = 0;
+        carry =
+            (*addCarryMRoutinePtr)(
+                3,
+                &aWPtr[indexMultiwordLo( 4, 3 )],
+                &bWPtr[indexMultiwordLo( 4, 3 )],
+                negateB,
+                &extSigZ[indexMultiword( 5, 3, 1 )]
+            );
+        if ( negateB ) {
+            wordSigZ = sig96A + ~sig96B + carry;
+            if ( wordSigZ & 0x80000000 ) {
+                signZ = ! signZ;
+                carry =
+                    softfloat_addComplCarry96M(
+                        &bWPtr[indexMultiwordLo( 4, 3 )],
+                        &aWPtr[indexMultiwordLo( 4, 3 )],
+                        1,
+                        &extSigZ[indexMultiword( 5, 3, 1 )]
+                    );
+                wordSigZ = sig96B + ~sig96A + carry;
+            } else {
+                if (
+                    ! wordSigZ && ! extSigZ[indexWord( 5, 3 )]
+                        && ! (  extSigZ[indexWord( 5, 2 )]
+                              | extSigZ[indexWord( 5, 1 )]
+                              | extSigZ[indexWord( 5, 0 )]
+                             )
+                ) {
+                    signZ = (softfloat_roundingMode == softfloat_round_min);
+                    zWPtr[indexWordHi( 4 )] = packToF128UI96( signZ, 0, 0 );
+                    zWPtr[indexWord( 4, 2 )] = 0;
+                    zWPtr[indexWord( 4, 1 )] = 0;
+                    zWPtr[indexWord( 4, 0 )] = 0;
+                    return;
+                }
+            }
+        } else {
+            wordSigZ = sig96A + sig96B + carry;
+        }
+    }
+    extSigZ[indexWordHi( 5 )] = wordSigZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundPackRoutinePtr = softfloat_normRoundPackMToF128M;
+    if ( 0x00010000 <= wordSigZ ) {
+        if ( 0x00020000 <= wordSigZ ) {
+            ++expA;
+            softfloat_shortShiftRightJam160M( extSigZ, 1, extSigZ );
+        }
+        roundPackRoutinePtr = softfloat_roundPackMToF128M;
+    }
+    (*roundPackRoutinePtr)( signZ, expA, extSigZ, zWPtr );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addM.c b/addins/SoftFloat-3e/source/s_addM.c
new file mode 100644
index 000000000..c935baaf7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_addM
+
+void
+ softfloat_addM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ )
+{
+    unsigned int index, lastIndex;
+    uint_fast8_t carry;
+    uint32_t wordA, wordZ;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    carry = 0;
+    for (;;) {
+        wordA = aPtr[index];
+        wordZ = wordA + bPtr[index] + carry;
+        zPtr[index] = wordZ;
+        if ( index == lastIndex ) break;
+        if ( wordZ != wordA ) carry = (wordZ < wordA);
+        index += wordIncr;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_addMagsExtF80.c b/addins/SoftFloat-3e/source/s_addMagsExtF80.c
new file mode 100644
index 000000000..b1bb5dbe6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addMagsExtF80.c
@@ -0,0 +1,156 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t
+ softfloat_addMagsExtF80(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0,
+     bool signZ
+ )
+{
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    int_fast32_t expB;
+    uint_fast64_t sigB;
+    int_fast32_t expDiff;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0, sigZ, sigZExtra;
+    struct exp32_sig64 normExpSig;
+    int_fast32_t expZ;
+    struct uint64_extra sig64Extra;
+    struct uint128 uiZ;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expExtF80UI64( uiA64 );
+    sigA = uiA0;
+    expB = expExtF80UI64( uiB64 );
+    sigB = uiB0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        if ( expA == 0x7FFF ) {
+            if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+                goto propagateNaN;
+            }
+            uiZ64 = uiA64;
+            uiZ0  = uiA0;
+            goto uiZ;
+        }
+        sigZ = sigA + sigB;
+        sigZExtra = 0;
+        if ( ! expA ) {
+            normExpSig = softfloat_normSubnormalExtF80Sig( sigZ );
+            expZ = normExpSig.exp + 1;
+            sigZ = normExpSig.sig;
+            goto roundAndPack;
+        }
+        expZ = expA;
+        goto shiftRight1;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expDiff < 0 ) {
+        if ( expB == 0x7FFF ) {
+            if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+            uiZ64 = packToExtF80UI64( signZ, 0x7FFF );
+            uiZ0  = uiB0;
+            goto uiZ;
+        }
+        expZ = expB;
+        if ( ! expA ) {
+            ++expDiff;
+            sigZExtra = 0;
+            if ( ! expDiff ) goto newlyAligned;
+        }
+        sig64Extra = softfloat_shiftRightJam64Extra( sigA, 0, -expDiff );
+        sigA = sig64Extra.v;
+        sigZExtra = sig64Extra.extra;
+    } else {
+        if ( expA == 0x7FFF ) {
+            if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+            uiZ64 = uiA64;
+            uiZ0  = uiA0;
+            goto uiZ;
+        }
+        expZ = expA;
+        if ( ! expB ) {
+            --expDiff;
+            sigZExtra = 0;
+            if ( ! expDiff ) goto newlyAligned;
+        }
+        sig64Extra = softfloat_shiftRightJam64Extra( sigB, 0, expDiff );
+        sigB = sig64Extra.v;
+        sigZExtra = sig64Extra.extra;
+    }
+ newlyAligned:
+    sigZ = sigA + sigB;
+    if ( sigZ & UINT64_C( 0x8000000000000000 ) ) goto roundAndPack;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ shiftRight1:
+    sig64Extra = softfloat_shortShiftRightJam64Extra( sigZ, sigZExtra, 1 );
+    sigZ = sig64Extra.v | UINT64_C( 0x8000000000000000 );
+    sigZExtra = sig64Extra.extra;
+    ++expZ;
+ roundAndPack:
+    return
+        softfloat_roundPackToExtF80(
+            signZ, expZ, sigZ, sigZExtra, extF80_roundingPrecision );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ64 = uiZ.v64;
+    uiZ0  = uiZ.v0;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addMagsF128.c b/addins/SoftFloat-3e/source/s_addMagsF128.c
new file mode 100644
index 000000000..8e5ce5b34
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addMagsF128.c
@@ -0,0 +1,154 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+float128_t
+ softfloat_addMagsF128(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0,
+     bool signZ
+ )
+{
+    int_fast32_t expA;
+    struct uint128 sigA;
+    int_fast32_t expB;
+    struct uint128 sigB;
+    int_fast32_t expDiff;
+    struct uint128 uiZ, sigZ;
+    int_fast32_t expZ;
+    uint_fast64_t sigZExtra;
+    struct uint128_extra sig128Extra;
+    union ui128_f128 uZ;
+
+    expA = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    expB = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        if ( expA == 0x7FFF ) {
+            if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN;
+            uiZ.v64 = uiA64;
+            uiZ.v0  = uiA0;
+            goto uiZ;
+        }
+        sigZ = softfloat_add128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 );
+        if ( ! expA ) {
+            uiZ.v64 = packToF128UI64( signZ, 0, sigZ.v64 );
+            uiZ.v0  = sigZ.v0;
+            goto uiZ;
+        }
+        expZ = expA;
+        sigZ.v64 |= UINT64_C( 0x0002000000000000 );
+        sigZExtra = 0;
+        goto shiftRight1;
+    }
+    if ( expDiff < 0 ) {
+        if ( expB == 0x7FFF ) {
+            if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+            uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 );
+            uiZ.v0  = 0;
+            goto uiZ;
+        }
+        expZ = expB;
+        if ( expA ) {
+            sigA.v64 |= UINT64_C( 0x0001000000000000 );
+        } else {
+            ++expDiff;
+            sigZExtra = 0;
+            if ( ! expDiff ) goto newlyAligned;
+        }
+        sig128Extra =
+            softfloat_shiftRightJam128Extra( sigA.v64, sigA.v0, 0, -expDiff );
+        sigA = sig128Extra.v;
+        sigZExtra = sig128Extra.extra;
+    } else {
+        if ( expA == 0x7FFF ) {
+            if ( sigA.v64 | sigA.v0 ) goto propagateNaN;
+            uiZ.v64 = uiA64;
+            uiZ.v0  = uiA0;
+            goto uiZ;
+        }
+        expZ = expA;
+        if ( expB ) {
+            sigB.v64 |= UINT64_C( 0x0001000000000000 );
+        } else {
+            --expDiff;
+            sigZExtra = 0;
+            if ( ! expDiff ) goto newlyAligned;
+        }
+        sig128Extra =
+            softfloat_shiftRightJam128Extra( sigB.v64, sigB.v0, 0, expDiff );
+        sigB = sig128Extra.v;
+        sigZExtra = sig128Extra.extra;
+    }
+ newlyAligned:
+    sigZ =
+        softfloat_add128(
+            sigA.v64 | UINT64_C( 0x0001000000000000 ),
+            sigA.v0,
+            sigB.v64,
+            sigB.v0
+        );
+    --expZ;
+    if ( sigZ.v64 < UINT64_C( 0x0002000000000000 ) ) goto roundAndPack;
+    ++expZ;
+ shiftRight1:
+    sig128Extra =
+        softfloat_shortShiftRightJam128Extra(
+            sigZ.v64, sigZ.v0, sigZExtra, 1 );
+    sigZ = sig128Extra.v;
+    sigZExtra = sig128Extra.extra;
+ roundAndPack:
+    return
+        softfloat_roundPackToF128( signZ, expZ, sigZ.v64, sigZ.v0, sigZExtra );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addMagsF16.c b/addins/SoftFloat-3e/source/s_addMagsF16.c
new file mode 100644
index 000000000..b7fba0928
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addMagsF16.c
@@ -0,0 +1,183 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t softfloat_addMagsF16( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    int_fast8_t expDiff;
+    uint_fast16_t uiZ;
+    bool signZ;
+    int_fast8_t expZ;
+    uint_fast16_t sigZ;
+    uint_fast16_t sigX, sigY;
+    int_fast8_t shiftDist;
+    uint_fast32_t sig32Z;
+    int_fast8_t roundingMode;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF16UI( uiA );
+    sigA = fracF16UI( uiA );
+    expB = expF16UI( uiB );
+    sigB = fracF16UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( ! expA ) {
+            uiZ = uiA + sigB;
+            goto uiZ;
+        }
+        if ( expA == 0x1F ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            uiZ = uiA;
+            goto uiZ;
+        }
+        signZ = signF16UI( uiA );
+        expZ = expA;
+        sigZ = 0x0800 + sigA + sigB;
+        if ( ! (sigZ & 1) && (expZ < 0x1E) ) {
+            sigZ >>= 1;
+            goto pack;
+        }
+        sigZ <<= 3;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signF16UI( uiA );
+        if ( expDiff < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            if ( expB == 0x1F ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF16UI( signZ, 0x1F, 0 );
+                goto uiZ;
+            }
+            if ( expDiff <= -13 ) {
+                uiZ = packToF16UI( signZ, expB, sigB );
+                if ( expA | sigA ) goto addEpsilon;
+                goto uiZ;
+            }
+            expZ = expB;
+            sigX = sigB | 0x0400;
+            sigY = sigA + (expA ? 0x0400 : sigA);
+            shiftDist = 19 + expDiff;
+        } else {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            uiZ = uiA;
+            if ( expA == 0x1F ) {
+                if ( sigA ) goto propagateNaN;
+                goto uiZ;
+            }
+            if ( 13 <= expDiff ) {
+                if ( expB | sigB ) goto addEpsilon;
+                goto uiZ;
+            }
+            expZ = expA;
+            sigX = sigA | 0x0400;
+            sigY = sigB + (expB ? 0x0400 : sigB);
+            shiftDist = 19 - expDiff;
+        }
+        sig32Z =
+            ((uint_fast32_t) sigX<<19) + ((uint_fast32_t) sigY<<shiftDist);
+        if ( sig32Z < 0x40000000 ) {
+            --expZ;
+            sig32Z <<= 1;
+        }
+        sigZ = sig32Z>>16;
+        if ( sig32Z & 0xFFFF ) {
+            sigZ |= 1;
+        } else {
+            if ( ! (sigZ & 0xF) && (expZ < 0x1E) ) {
+                sigZ >>= 4;
+                goto pack;
+            }
+        }
+    }
+    return softfloat_roundPackToF16( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ addEpsilon:
+    roundingMode = softfloat_roundingMode;
+    if ( roundingMode != softfloat_round_near_even ) {
+        if (
+            roundingMode
+                == (signF16UI( uiZ ) ? softfloat_round_min
+                        : softfloat_round_max)
+        ) {
+            ++uiZ;
+            if ( (uint16_t) (uiZ<<1) == 0xF800 ) {
+                softfloat_raiseFlags(
+                    softfloat_flag_overflow | softfloat_flag_inexact );
+            }
+        }
+#ifdef SOFTFLOAT_ROUND_ODD
+        else if ( roundingMode == softfloat_round_odd ) {
+            uiZ |= 1;
+        }
+#endif
+    }
+    softfloat_exceptionFlags |= softfloat_flag_inexact;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ pack:
+    uiZ = packToF16UI( signZ, expZ, sigZ );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addMagsF32.c b/addins/SoftFloat-3e/source/s_addMagsF32.c
new file mode 100644
index 000000000..b74489dec
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addMagsF32.c
@@ -0,0 +1,126 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+float32_t softfloat_addMagsF32( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    int_fast16_t expDiff;
+    uint_fast32_t uiZ;
+    bool signZ;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF32UI( uiA );
+    sigA = fracF32UI( uiA );
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( ! expA ) {
+            uiZ = uiA + sigB;
+            goto uiZ;
+        }
+        if ( expA == 0xFF ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            uiZ = uiA;
+            goto uiZ;
+        }
+        signZ = signF32UI( uiA );
+        expZ = expA;
+        sigZ = 0x01000000 + sigA + sigB;
+        if ( ! (sigZ & 1) && (expZ < 0xFE) ) {
+            uiZ = packToF32UI( signZ, expZ, sigZ>>1 );
+            goto uiZ;
+        }
+        sigZ <<= 6;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signF32UI( uiA );
+        sigA <<= 6;
+        sigB <<= 6;
+        if ( expDiff < 0 ) {
+            if ( expB == 0xFF ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF32UI( signZ, 0xFF, 0 );
+                goto uiZ;
+            }
+            expZ = expB;
+            sigA += expA ? 0x20000000 : sigA;
+            sigA = softfloat_shiftRightJam32( sigA, -expDiff );
+        } else {
+            if ( expA == 0xFF ) {
+                if ( sigA ) goto propagateNaN;
+                uiZ = uiA;
+                goto uiZ;
+            }
+            expZ = expA;
+            sigB += expB ? 0x20000000 : sigB;
+            sigB = softfloat_shiftRightJam32( sigB, expDiff );
+        }
+        sigZ = 0x20000000 + sigA + sigB;
+        if ( sigZ < 0x40000000 ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    }
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_addMagsF64.c b/addins/SoftFloat-3e/source/s_addMagsF64.c
new file mode 100644
index 000000000..e8a489874
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_addMagsF64.c
@@ -0,0 +1,128 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+float64_t
+ softfloat_addMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
+{
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    int_fast16_t expDiff;
+    uint_fast64_t uiZ;
+    int_fast16_t expZ;
+    uint_fast64_t sigZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( ! expA ) {
+            uiZ = uiA + sigB;
+            goto uiZ;
+        }
+        if ( expA == 0x7FF ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            uiZ = uiA;
+            goto uiZ;
+        }
+        expZ = expA;
+        sigZ = UINT64_C( 0x0020000000000000 ) + sigA + sigB;
+        sigZ <<= 9;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sigA <<= 9;
+        sigB <<= 9;
+        if ( expDiff < 0 ) {
+            if ( expB == 0x7FF ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF64UI( signZ, 0x7FF, 0 );
+                goto uiZ;
+            }
+            expZ = expB;
+            if ( expA ) {
+                sigA += UINT64_C( 0x2000000000000000 );
+            } else {
+                sigA <<= 1;
+            }
+            sigA = softfloat_shiftRightJam64( sigA, -expDiff );
+        } else {
+            if ( expA == 0x7FF ) {
+                if ( sigA ) goto propagateNaN;
+                uiZ = uiA;
+                goto uiZ;
+            }
+            expZ = expA;
+            if ( expB ) {
+                sigB += UINT64_C( 0x2000000000000000 );
+            } else {
+                sigB <<= 1;
+            }
+            sigB = softfloat_shiftRightJam64( sigB, expDiff );
+        }
+        sigZ = UINT64_C( 0x2000000000000000 ) + sigA + sigB;
+        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    }
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_approxRecip32_1.c b/addins/SoftFloat-3e/source/s_approxRecip32_1.c
new file mode 100644
index 000000000..4a326a438
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_approxRecip32_1.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_approxRecip32_1
+
+extern const uint16_t softfloat_approxRecip_1k0s[16];
+extern const uint16_t softfloat_approxRecip_1k1s[16];
+
+uint32_t softfloat_approxRecip32_1( uint32_t a )
+{
+    int index;
+    uint16_t eps, r0;
+    uint32_t sigma0;
+    uint_fast32_t r;
+    uint32_t sqrSigma0;
+
+    index = a>>27 & 0xF;
+    eps = (uint16_t) (a>>11);
+    r0 = softfloat_approxRecip_1k0s[index]
+             - ((softfloat_approxRecip_1k1s[index] * (uint_fast32_t) eps)>>20);
+    sigma0 = ~(uint_fast32_t) ((r0 * (uint_fast64_t) a)>>7);
+    r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>24);
+    sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32;
+    r += ((uint32_t) r * (uint_fast64_t) sqrSigma0)>>48;
+    return r;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_approxRecipSqrt32_1.c b/addins/SoftFloat-3e/source/s_approxRecipSqrt32_1.c
new file mode 100644
index 000000000..b3fdeba68
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_approxRecipSqrt32_1.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_approxRecipSqrt32_1
+
+extern const uint16_t softfloat_approxRecipSqrt_1k0s[];
+extern const uint16_t softfloat_approxRecipSqrt_1k1s[];
+
+uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a )
+{
+    int index;
+    uint16_t eps, r0;
+    uint_fast32_t ESqrR0;
+    uint32_t sigma0;
+    uint_fast32_t r;
+    uint32_t sqrSigma0;
+
+    index = (a>>27 & 0xE) + oddExpA;
+    eps = (uint16_t) (a>>12);
+    r0 = softfloat_approxRecipSqrt_1k0s[index]
+             - ((softfloat_approxRecipSqrt_1k1s[index] * (uint_fast32_t) eps)
+                    >>20);
+    ESqrR0 = (uint_fast32_t) r0 * r0;
+    if ( ! oddExpA ) ESqrR0 <<= 1;
+    sigma0 = ~(uint_fast32_t) (((uint32_t) ESqrR0 * (uint_fast64_t) a)>>23);
+    r = ((uint_fast32_t) r0<<16) + ((r0 * (uint_fast64_t) sigma0)>>25);
+    sqrSigma0 = ((uint_fast64_t) sigma0 * sigma0)>>32;
+    r += ((uint32_t) ((r>>1) + (r>>3) - ((uint_fast32_t) r0<<14))
+              * (uint_fast64_t) sqrSigma0)
+             >>48;
+    if ( ! (r & 0x80000000) ) r = 0x80000000;
+    return r;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_approxRecipSqrt_1Ks.c b/addins/SoftFloat-3e/source/s_approxRecipSqrt_1Ks.c
new file mode 100644
index 000000000..38a27985c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_approxRecipSqrt_1Ks.c
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+const uint16_t softfloat_approxRecipSqrt_1k0s[16] = {
+    0xB4C9, 0xFFAB, 0xAA7D, 0xF11C, 0xA1C5, 0xE4C7, 0x9A43, 0xDA29,
+    0x93B5, 0xD0E5, 0x8DED, 0xC8B7, 0x88C6, 0xC16D, 0x8424, 0xBAE1
+};
+const uint16_t softfloat_approxRecipSqrt_1k1s[16] = {
+    0xA5A5, 0xEA42, 0x8C21, 0xC62D, 0x788F, 0xAA7F, 0x6928, 0x94B6,
+    0x5CC7, 0x8335, 0x52A6, 0x74E2, 0x4A3E, 0x68FE, 0x432B, 0x5EFD
+};
+
diff --git a/addins/SoftFloat-3e/source/s_approxRecip_1Ks.c b/addins/SoftFloat-3e/source/s_approxRecip_1Ks.c
new file mode 100644
index 000000000..f1fca74e7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_approxRecip_1Ks.c
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+const uint16_t softfloat_approxRecip_1k0s[16] = {
+    0xFFC4, 0xF0BE, 0xE363, 0xD76F, 0xCCAD, 0xC2F0, 0xBA16, 0xB201,
+    0xAA97, 0xA3C6, 0x9D7A, 0x97A6, 0x923C, 0x8D32, 0x887E, 0x8417
+};
+const uint16_t softfloat_approxRecip_1k1s[16] = {
+    0xF0F1, 0xD62C, 0xBFA1, 0xAC77, 0x9C0A, 0x8DDB, 0x8185, 0x76BA,
+    0x6D3B, 0x64D4, 0x5D5C, 0x56B1, 0x50B6, 0x4B55, 0x4679, 0x4211
+};
+
diff --git a/addins/SoftFloat-3e/source/s_compare128M.c b/addins/SoftFloat-3e/source/s_compare128M.c
new file mode 100644
index 000000000..dc97ce9e5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_compare128M.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_compare128M
+
+int_fast8_t softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr )
+{
+    unsigned int index, lastIndex;
+    uint32_t wordA, wordB;
+
+    index = indexWordHi( 4 );
+    lastIndex = indexWordLo( 4 );
+    for (;;) {
+        wordA = aPtr[index];
+        wordB = bPtr[index];
+        if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1;
+        if ( index == lastIndex ) break;
+        index -= wordIncr;
+    }
+    return 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_compare96M.c b/addins/SoftFloat-3e/source/s_compare96M.c
new file mode 100644
index 000000000..2681c4627
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_compare96M.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_compare96M
+
+int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr )
+{
+    unsigned int index, lastIndex;
+    uint32_t wordA, wordB;
+
+    index = indexWordHi( 3 );
+    lastIndex = indexWordLo( 3 );
+    for (;;) {
+        wordA = aPtr[index];
+        wordB = bPtr[index];
+        if ( wordA != wordB ) return (wordA < wordB) ? -1 : 1;
+        if ( index == lastIndex ) break;
+        index -= wordIncr;
+    }
+    return 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_compareNonnormExtF80M.c b/addins/SoftFloat-3e/source/s_compareNonnormExtF80M.c
new file mode 100644
index 000000000..267315304
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_compareNonnormExtF80M.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat_types.h"
+
+int
+ softfloat_compareNonnormExtF80M(
+     const struct extFloat80M *aSPtr, const struct extFloat80M *bSPtr )
+{
+    uint_fast16_t uiA64, uiB64;
+    uint64_t sigA;
+    bool signB;
+    uint64_t sigB;
+    int32_t expA, expB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA64 = aSPtr->signExp;
+    uiB64 = bSPtr->signExp;
+    sigA = aSPtr->signif;
+    signB = signExtF80UI64( uiB64 );
+    sigB = bSPtr->signif;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( (uiA64 ^ uiB64) & 0x8000 ) {
+        if ( ! (sigA | sigB) ) return 0;
+        goto resultFromSignB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expExtF80UI64( uiA64 );
+    expB = expExtF80UI64( uiB64 );
+    if ( expA == 0x7FFF ) {
+        if (expB == 0x7FFF) return 0;
+        signB = ! signB;
+        goto resultFromSignB;
+    }
+    if ( expB == 0x7FFF ) {
+        goto resultFromSignB;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) expA = 1;
+    if ( ! (sigA & UINT64_C( 0x8000000000000000 )) ) {
+        if ( sigA ) {
+            expA += softfloat_normExtF80SigM( &sigA );
+        } else {
+            expA = -128;
+        }
+    }
+    if ( ! expB ) expB = 1;
+    if ( ! (sigB & UINT64_C( 0x8000000000000000 )) ) {
+        if ( sigB ) {
+            expB += softfloat_normExtF80SigM( &sigB );
+        } else {
+            expB = -128;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signB ) {
+        if ( expA < expB ) return 1;
+        if ( (expB < expA) || (sigB < sigA) ) return -1;
+    } else {
+        if ( expB < expA ) return 1;
+        if ( (expA < expB) || (sigA < sigB) ) return -1;
+    }
+    return (sigA != sigB);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ resultFromSignB:
+    return signB ? 1 : -1;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_countLeadingZeros16.c b/addins/SoftFloat-3e/source/s_countLeadingZeros16.c
new file mode 100644
index 000000000..7a68da52f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_countLeadingZeros16.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_countLeadingZeros16
+
+#define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16
+#include "primitives.h"
+
+uint_fast8_t softfloat_countLeadingZeros16( uint16_t a )
+{
+    uint_fast8_t count;
+
+    count = 8;
+    if ( 0x100 <= a ) {
+        count = 0;
+        a >>= 8;
+    }
+    count += softfloat_countLeadingZeros8[a];
+    return count;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_countLeadingZeros32.c b/addins/SoftFloat-3e/source/s_countLeadingZeros32.c
new file mode 100644
index 000000000..53ab22824
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_countLeadingZeros32.c
@@ -0,0 +1,64 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_countLeadingZeros32
+
+#define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32
+#include "primitives.h"
+
+uint_fast8_t softfloat_countLeadingZeros32( uint32_t a )
+{
+    uint_fast8_t count;
+
+    count = 0;
+    if ( a < 0x10000 ) {
+        count = 16;
+        a <<= 16;
+    }
+    if ( a < 0x1000000 ) {
+        count += 8;
+        a <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[a>>24];
+    return count;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_countLeadingZeros64.c b/addins/SoftFloat-3e/source/s_countLeadingZeros64.c
new file mode 100644
index 000000000..13a222463
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_countLeadingZeros64.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_countLeadingZeros64
+
+#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
+#include "primitives.h"
+
+uint_fast8_t softfloat_countLeadingZeros64( uint64_t a )
+{
+    uint_fast8_t count;
+    uint32_t a32;
+
+    count = 0;
+    a32 = a>>32;
+    if ( ! a32 ) {
+        count = 32;
+        a32 = a;
+    }
+    /*------------------------------------------------------------------------
+    | From here, result is current count + count leading zeros of `a32'.
+    *------------------------------------------------------------------------*/
+    if ( a32 < 0x10000 ) {
+        count += 16;
+        a32 <<= 16;
+    }
+    if ( a32 < 0x1000000 ) {
+        count += 8;
+        a32 <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[a32>>24];
+    return count;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_countLeadingZeros8.c b/addins/SoftFloat-3e/source/s_countLeadingZeros8.c
new file mode 100644
index 000000000..a56f5a40c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_countLeadingZeros8.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+const uint_least8_t softfloat_countLeadingZeros8[256] = {
+    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
diff --git a/addins/SoftFloat-3e/source/s_eq128.c b/addins/SoftFloat-3e/source/s_eq128.c
new file mode 100644
index 000000000..275b8ae29
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_eq128.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_eq128
+
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+
+    return (a64 == b64) && (a0 == b0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_invalidExtF80M.c b/addins/SoftFloat-3e/source/s_invalidExtF80M.c
new file mode 100644
index 000000000..237d21721
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_invalidExtF80M.c
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+void softfloat_invalidExtF80M( struct extFloat80M *zSPtr )
+{
+
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    zSPtr->signExp = defaultNaNExtF80UI64;
+    zSPtr->signif  = defaultNaNExtF80UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_invalidF128M.c b/addins/SoftFloat-3e/source/s_invalidF128M.c
new file mode 100644
index 000000000..a20840e5f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_invalidF128M.c
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+void softfloat_invalidF128M( uint32_t *zWPtr )
+{
+
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96;
+    zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64;
+    zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32;
+    zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_isNaNF128M.c b/addins/SoftFloat-3e/source/s_isNaNF128M.c
new file mode 100644
index 000000000..6008cf3eb
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_isNaNF128M.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+bool softfloat_isNaNF128M( const uint32_t *aWPtr )
+{
+    uint32_t uiA96;
+
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    if ( (~uiA96 & 0x7FFF0000) != 0 ) return false;
+    return
+        ((uiA96 & 0x0000FFFF) != 0)
+            || ((aWPtr[indexWord( 4, 2 )] | aWPtr[indexWord( 4, 1 )]
+                     | aWPtr[indexWord( 4, 0 )])
+                    != 0);
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_le128.c b/addins/SoftFloat-3e/source/s_le128.c
new file mode 100644
index 000000000..1fce7af98
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_le128.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_le128
+
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+
+    return (a64 < b64) || ((a64 == b64) && (a0 <= b0));
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_lt128.c b/addins/SoftFloat-3e/source/s_lt128.c
new file mode 100644
index 000000000..d7ce3b997
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_lt128.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_lt128
+
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+
+    return (a64 < b64) || ((a64 == b64) && (a0 < b0));
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul128By32.c b/addins/SoftFloat-3e/source/s_mul128By32.c
new file mode 100644
index 000000000..7c0fdc867
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul128By32.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_mul128By32
+
+struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b )
+{
+    struct uint128 z;
+    uint_fast64_t mid;
+    uint_fast32_t carry;
+
+    z.v0 = a0 * b;
+    mid = (uint_fast64_t) (uint32_t) (a0>>32) * b;
+    carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid);
+    z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul128MTo256M.c b/addins/SoftFloat-3e/source/s_mul128MTo256M.c
new file mode 100644
index 000000000..ea8865ea3
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul128MTo256M.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_mul128MTo256M
+
+void
+ softfloat_mul128MTo256M(
+     const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr )
+{
+    uint32_t *lastZPtr, wordB;
+    uint64_t dwordProd;
+    uint32_t wordZ;
+    uint_fast8_t carry;
+
+    bPtr += indexWordLo( 4 );
+    lastZPtr = zPtr + indexMultiwordHi( 8, 5 );
+    zPtr += indexMultiwordLo( 8, 5 );
+    wordB = *bPtr;
+    dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB;
+    zPtr[indexWord( 5, 0 )] = dwordProd;
+    dwordProd = (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32);
+    zPtr[indexWord( 5, 1 )] = dwordProd;
+    dwordProd = (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32);
+    zPtr[indexWord( 5, 2 )] = dwordProd;
+    dwordProd = (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32);
+    zPtr[indexWord( 5, 3 )] = dwordProd;
+    zPtr[indexWord( 5, 4 )] = dwordProd>>32;
+    do {
+        bPtr += wordIncr;
+        zPtr += wordIncr;
+        wordB = *bPtr;
+        dwordProd = (uint64_t) aPtr[indexWord( 4, 0 )] * wordB;
+        wordZ = zPtr[indexWord( 5, 0 )] + (uint32_t) dwordProd;
+        zPtr[indexWord( 5, 0 )] = wordZ;
+        carry = (wordZ < (uint32_t) dwordProd);
+        dwordProd =
+            (uint64_t) aPtr[indexWord( 4, 1 )] * wordB + (dwordProd>>32);
+        wordZ = zPtr[indexWord( 5, 1 )] + (uint32_t) dwordProd + carry;
+        zPtr[indexWord( 5, 1 )] = wordZ;
+        if ( wordZ != (uint32_t) dwordProd ) {
+            carry = (wordZ < (uint32_t) dwordProd);
+        }
+        dwordProd =
+            (uint64_t) aPtr[indexWord( 4, 2 )] * wordB + (dwordProd>>32);
+        wordZ = zPtr[indexWord( 5, 2 )] + (uint32_t) dwordProd + carry;
+        zPtr[indexWord( 5, 2 )] = wordZ;
+        if ( wordZ != (uint32_t) dwordProd ) {
+            carry = (wordZ < (uint32_t) dwordProd);
+        }
+        dwordProd =
+            (uint64_t) aPtr[indexWord( 4, 3 )] * wordB + (dwordProd>>32);
+        wordZ = zPtr[indexWord( 5, 3 )] + (uint32_t) dwordProd + carry;
+        zPtr[indexWord( 5, 3 )] = wordZ;
+        if ( wordZ != (uint32_t) dwordProd ) {
+            carry = (wordZ < (uint32_t) dwordProd);
+        }
+        zPtr[indexWord( 5, 4 )] = (dwordProd>>32) + carry;
+    } while ( zPtr != lastZPtr );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul128To256M.c b/addins/SoftFloat-3e/source/s_mul128To256M.c
new file mode 100644
index 000000000..7c9d9b584
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul128To256M.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_mul128To256M
+
+#define softfloat_mul128To256M softfloat_mul128To256M
+#include "primitives.h"
+
+void
+ softfloat_mul128To256M(
+     uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr )
+{
+    struct uint128 p0, p64, p128;
+    uint_fast64_t z64, z128, z192;
+
+    p0 = softfloat_mul64To128( a0, b0 );
+    zPtr[indexWord( 4, 0 )] = p0.v0;
+    p64 = softfloat_mul64To128( a64, b0 );
+    z64 = p64.v0 + p0.v64;
+    z128 = p64.v64 + (z64 < p64.v0);
+    p128 = softfloat_mul64To128( a64, b64 );
+    z128 += p128.v0;
+    z192 = p128.v64 + (z128 < p128.v0);
+    p64 = softfloat_mul64To128( a0, b64 );
+    z64 += p64.v0;
+    zPtr[indexWord( 4, 1 )] = z64;
+    p64.v64 += (z64 < p64.v0);
+    z128 += p64.v64;
+    zPtr[indexWord( 4, 2 )] = z128;
+    zPtr[indexWord( 4, 3 )] = z192 + (z128 < p64.v64);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul64ByShifted32To128.c b/addins/SoftFloat-3e/source/s_mul64ByShifted32To128.c
new file mode 100644
index 000000000..57e528888
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul64ByShifted32To128.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_mul64ByShifted32To128
+
+struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b )
+{
+    uint_fast64_t mid;
+    struct uint128 z;
+
+    mid = (uint_fast64_t) (uint32_t) a * b;
+    z.v0 = mid<<32;
+    z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul64To128.c b/addins/SoftFloat-3e/source/s_mul64To128.c
new file mode 100644
index 000000000..5d360aa4b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul64To128.c
@@ -0,0 +1,66 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_mul64To128
+
+struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
+{
+    uint32_t a32, a0, b32, b0;
+    struct uint128 z;
+    uint64_t mid1, mid;
+
+    a32 = a>>32;
+    a0 = a;
+    b32 = b>>32;
+    b0 = b;
+    z.v0 = (uint_fast64_t) a0 * b0;
+    mid1 = (uint_fast64_t) a32 * b0;
+    mid = mid1 + (uint_fast64_t) a0 * b32;
+    z.v64 = (uint_fast64_t) a32 * b32;
+    z.v64 += (uint_fast64_t) (mid < mid1)<<32 | mid>>32;
+    mid <<= 32;
+    z.v0 += mid;
+    z.v64 += (z.v0 < mid);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mul64To128M.c b/addins/SoftFloat-3e/source/s_mul64To128M.c
new file mode 100644
index 000000000..ed10be324
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mul64To128M.c
@@ -0,0 +1,68 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_mul64To128M
+
+void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr )
+{
+    uint32_t a32, a0, b32, b0;
+    uint64_t z0, mid1, z64, mid;
+
+    a32 = a>>32;
+    a0 = a;
+    b32 = b>>32;
+    b0 = b;
+    z0 = (uint64_t) a0 * b0;
+    mid1 = (uint64_t) a32 * b0;
+    mid = mid1 + (uint64_t) a0 * b32;
+    z64 = (uint64_t) a32 * b32;
+    z64 += (uint64_t) (mid < mid1)<<32 | mid>>32;
+    mid <<= 32;
+    z0 += mid;
+    zPtr[indexWord( 4, 1 )] = z0>>32;
+    zPtr[indexWord( 4, 0 )] = z0;
+    z64 += (z0 < mid);
+    zPtr[indexWord( 4, 3 )] = z64>>32;
+    zPtr[indexWord( 4, 2 )] = z64;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_mulAddF128.c b/addins/SoftFloat-3e/source/s_mulAddF128.c
new file mode 100644
index 000000000..f6b2b45df
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mulAddF128.c
@@ -0,0 +1,350 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t
+ softfloat_mulAddF128(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0,
+     uint_fast64_t uiC64,
+     uint_fast64_t uiC0,
+     uint_fast8_t op
+ )
+{
+    bool signA;
+    int_fast32_t expA;
+    struct uint128 sigA;
+    bool signB;
+    int_fast32_t expB;
+    struct uint128 sigB;
+    bool signC;
+    int_fast32_t expC;
+    struct uint128 sigC;
+    bool signZ;
+    uint_fast64_t magBits;
+    struct uint128 uiZ;
+    struct exp32_sig128 normExpSig;
+    int_fast32_t expZ;
+    uint64_t sig256Z[4];
+    struct uint128 sigZ;
+    int_fast32_t shiftDist, expDiff;
+    struct uint128 x128;
+    uint64_t sig256C[4];
+    static uint64_t zero256[4] = INIT_UINTM4( 0, 0, 0, 0 );
+    uint_fast64_t sigZExtra, sig256Z0;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signF128UI64( uiA64 );
+    expA  = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    signB = signF128UI64( uiB64 );
+    expB  = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    signC = signF128UI64( uiC64 ) ^ (op == softfloat_mulAdd_subC);
+    expC  = expF128UI64( uiC64 );
+    sigC.v64 = fracF128UI64( uiC64 );
+    sigC.v0  = uiC0;
+    signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FFF ) {
+        if (
+            (sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0))
+        ) {
+            goto propagateNaN_ABC;
+        }
+        magBits = expB | sigB.v64 | sigB.v0;
+        goto infProdArg;
+    }
+    if ( expB == 0x7FFF ) {
+        if ( sigB.v64 | sigB.v0 ) goto propagateNaN_ABC;
+        magBits = expA | sigA.v64 | sigA.v0;
+        goto infProdArg;
+    }
+    if ( expC == 0x7FFF ) {
+        if ( sigC.v64 | sigC.v0 ) {
+            uiZ.v64 = 0;
+            uiZ.v0  = 0;
+            goto propagateNaN_ZC;
+        }
+        uiZ.v64 = uiC64;
+        uiZ.v0  = uiC0;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! (sigA.v64 | sigA.v0) ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF128Sig( sigA.v64, sigA.v0 );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! (sigB.v64 | sigB.v0) ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF128Sig( sigB.v64, sigB.v0 );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FFE;
+    sigA.v64 |= UINT64_C( 0x0001000000000000 );
+    sigB.v64 |= UINT64_C( 0x0001000000000000 );
+    sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 8 );
+    sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 15 );
+    softfloat_mul128To256M( sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z );
+    sigZ.v64 = sig256Z[indexWord( 4, 3 )];
+    sigZ.v0  = sig256Z[indexWord( 4, 2 )];
+    shiftDist = 0;
+    if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) {
+        --expZ;
+        shiftDist = -1;
+    }
+    if ( ! expC ) {
+        if ( ! (sigC.v64 | sigC.v0) ) {
+            shiftDist += 8;
+            goto sigZ;
+        }
+        normExpSig = softfloat_normSubnormalF128Sig( sigC.v64, sigC.v0 );
+        expC = normExpSig.exp;
+        sigC = normExpSig.sig;
+    }
+    sigC.v64 |= UINT64_C( 0x0001000000000000 );
+    sigC = softfloat_shortShiftLeft128( sigC.v64, sigC.v0, 8 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expZ - expC;
+    if ( expDiff < 0 ) {
+        expZ = expC;
+        if ( (signZ == signC) || (expDiff < -1) ) {
+            shiftDist -= expDiff;
+            if ( shiftDist ) {
+                sigZ =
+                    softfloat_shiftRightJam128( sigZ.v64, sigZ.v0, shiftDist );
+            }
+        } else {
+            if ( ! shiftDist ) {
+                x128 =
+                    softfloat_shortShiftRight128(
+                        sig256Z[indexWord( 4, 1 )], sig256Z[indexWord( 4, 0 )],
+                        1
+                    );
+                sig256Z[indexWord( 4, 1 )] = (sigZ.v0<<63) | x128.v64;
+                sig256Z[indexWord( 4, 0 )] = x128.v0;
+                sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, 1 );
+                sig256Z[indexWord( 4, 3 )] = sigZ.v64;
+                sig256Z[indexWord( 4, 2 )] = sigZ.v0;
+            }
+        }
+    } else {
+        if ( shiftDist ) softfloat_add256M( sig256Z, sig256Z, sig256Z );
+        if ( ! expDiff ) {
+            sigZ.v64 = sig256Z[indexWord( 4, 3 )];
+            sigZ.v0  = sig256Z[indexWord( 4, 2 )];
+        } else {
+            sig256C[indexWord( 4, 3 )] = sigC.v64;
+            sig256C[indexWord( 4, 2 )] = sigC.v0;
+            sig256C[indexWord( 4, 1 )] = 0;
+            sig256C[indexWord( 4, 0 )] = 0;
+            softfloat_shiftRightJam256M( sig256C, expDiff, sig256C );
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    shiftDist = 8;
+    if ( signZ == signC ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff <= 0 ) {
+            sigZ = softfloat_add128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 );
+        } else {
+            softfloat_add256M( sig256Z, sig256C, sig256Z );
+            sigZ.v64 = sig256Z[indexWord( 4, 3 )];
+            sigZ.v0  = sig256Z[indexWord( 4, 2 )];
+        }
+        if ( sigZ.v64 & UINT64_C( 0x0200000000000000 ) ) {
+            ++expZ;
+            shiftDist = 9;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff < 0 ) {
+            signZ = signC;
+            if ( expDiff < -1 ) {
+                sigZ =
+                    softfloat_sub128( sigC.v64, sigC.v0, sigZ.v64, sigZ.v0 );
+                sigZExtra =
+                    sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )];
+                if ( sigZExtra ) {
+                    sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, 0, 1 );
+                }
+                if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) {
+                    --expZ;
+                    shiftDist = 7;
+                }
+                goto shiftRightRoundPack;
+            } else {
+                sig256C[indexWord( 4, 3 )] = sigC.v64;
+                sig256C[indexWord( 4, 2 )] = sigC.v0;
+                sig256C[indexWord( 4, 1 )] = 0;
+                sig256C[indexWord( 4, 0 )] = 0;
+                softfloat_sub256M( sig256C, sig256Z, sig256Z );
+            }
+        } else if ( ! expDiff ) {
+            sigZ = softfloat_sub128( sigZ.v64, sigZ.v0, sigC.v64, sigC.v0 );
+            if (
+                ! (sigZ.v64 | sigZ.v0) && ! sig256Z[indexWord( 4, 1 )]
+                    && ! sig256Z[indexWord( 4, 0 )]
+            ) {
+                goto completeCancellation;
+            }
+            sig256Z[indexWord( 4, 3 )] = sigZ.v64;
+            sig256Z[indexWord( 4, 2 )] = sigZ.v0;
+            if ( sigZ.v64 & UINT64_C( 0x8000000000000000 ) ) {
+                signZ = ! signZ;
+                softfloat_sub256M( zero256, sig256Z, sig256Z );
+            }
+        } else {
+            softfloat_sub256M( sig256Z, sig256C, sig256Z );
+            if ( 1 < expDiff ) {
+                sigZ.v64 = sig256Z[indexWord( 4, 3 )];
+                sigZ.v0  = sig256Z[indexWord( 4, 2 )];
+                if ( ! (sigZ.v64 & UINT64_C( 0x0100000000000000 )) ) {
+                    --expZ;
+                    shiftDist = 7;
+                }
+                goto sigZ;
+            }
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sigZ.v64  = sig256Z[indexWord( 4, 3 )];
+        sigZ.v0   = sig256Z[indexWord( 4, 2 )];
+        sigZExtra = sig256Z[indexWord( 4, 1 )];
+        sig256Z0  = sig256Z[indexWord( 4, 0 )];
+        if ( sigZ.v64 ) {
+            if ( sig256Z0 ) sigZExtra |= 1;
+        } else {
+            expZ -= 64;
+            sigZ.v64  = sigZ.v0;
+            sigZ.v0   = sigZExtra;
+            sigZExtra = sig256Z0;
+            if ( ! sigZ.v64 ) {
+                expZ -= 64;
+                sigZ.v64  = sigZ.v0;
+                sigZ.v0   = sigZExtra;
+                sigZExtra = 0;
+                if ( ! sigZ.v64 ) {
+                    expZ -= 64;
+                    sigZ.v64 = sigZ.v0;
+                    sigZ.v0  = 0;
+                }
+            }
+        }
+        shiftDist = softfloat_countLeadingZeros64( sigZ.v64 );
+        expZ += 7 - shiftDist;
+        shiftDist = 15 - shiftDist;
+        if ( 0 < shiftDist ) goto shiftRightRoundPack;
+        if ( shiftDist ) {
+            shiftDist = -shiftDist;
+            sigZ = softfloat_shortShiftLeft128( sigZ.v64, sigZ.v0, shiftDist );
+            x128 = softfloat_shortShiftLeft128( 0, sigZExtra, shiftDist );
+            sigZ.v0 |= x128.v64;
+            sigZExtra = x128.v0;
+        }
+        goto roundPack;
+    }
+ sigZ:
+    sigZExtra = sig256Z[indexWord( 4, 1 )] | sig256Z[indexWord( 4, 0 )];
+ shiftRightRoundPack:
+    sigZExtra = (uint64_t) (sigZ.v0<<(64 - shiftDist)) | (sigZExtra != 0);
+    sigZ = softfloat_shortShiftRight128( sigZ.v64, sigZ.v0, shiftDist );
+ roundPack:
+    return
+        softfloat_roundPackToF128(
+            signZ, expZ - 1, sigZ.v64, sigZ.v0, sigZExtra );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN_ABC:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+    goto propagateNaN_ZC;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infProdArg:
+    if ( magBits ) {
+        uiZ.v64 = packToF128UI64( signZ, 0x7FFF, 0 );
+        uiZ.v0 = 0;
+        if ( expC != 0x7FFF ) goto uiZ;
+        if ( sigC.v64 | sigC.v0 ) goto propagateNaN_ZC;
+        if ( signZ == signC ) goto uiZ;
+    }
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ.v64 = defaultNaNF128UI64;
+    uiZ.v0  = defaultNaNF128UI0;
+ propagateNaN_ZC:
+    uiZ = softfloat_propagateNaNF128UI( uiZ.v64, uiZ.v0, uiC64, uiC0 );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    uiZ.v64 = uiC64;
+    uiZ.v0  = uiC0;
+    if ( ! (expC | sigC.v64 | sigC.v0) && (signZ != signC) ) {
+ completeCancellation:
+        uiZ.v64 =
+            packToF128UI64(
+                (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+        uiZ.v0 = 0;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_mulAddF128M.c b/addins/SoftFloat-3e/source/s_mulAddF128M.c
new file mode 100644
index 000000000..f51fc71d2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mulAddF128M.c
@@ -0,0 +1,382 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+void
+ softfloat_mulAddF128M(
+     const uint32_t *aWPtr,
+     const uint32_t *bWPtr,
+     const uint32_t *cWPtr,
+     uint32_t *zWPtr,
+     uint_fast8_t op
+ )
+{
+    uint32_t uiA96;
+    int32_t expA;
+    uint32_t uiB96;
+    int32_t expB;
+    uint32_t uiC96;
+    bool signC;
+    int32_t expC;
+    bool signProd, prodIsInfinite;
+    uint32_t *ptr, uiZ96, sigA[4];
+    uint_fast8_t shiftDist;
+    uint32_t sigX[5];
+    int32_t expProd;
+    uint32_t sigProd[8], wordSig;
+    bool doSub;
+    uint_fast8_t
+     (*addCarryMRoutinePtr)(
+         uint_fast8_t,
+         const uint32_t *,
+         const uint32_t *,
+         uint_fast8_t,
+         uint32_t *
+     );
+    int32_t expDiff;
+    bool signZ;
+    int32_t expZ;
+    uint32_t *extSigPtr;
+    uint_fast8_t carry;
+    void (*roundPackRoutinePtr)( bool, int32_t, uint32_t *, uint32_t * );
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uiA96 = aWPtr[indexWordHi( 4 )];
+    expA = expF128UI96( uiA96 );
+    uiB96 = bWPtr[indexWordHi( 4 )];
+    expB = expF128UI96( uiB96 );
+    uiC96 = cWPtr[indexWordHi( 4 )];
+    signC = signF128UI96( uiC96 ) ^ (op == softfloat_mulAdd_subC);
+    expC = expF128UI96( uiC96 );
+    signProd =
+        signF128UI96( uiA96 ) ^ signF128UI96( uiB96 )
+            ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    prodIsInfinite = false;
+    if ( (expA == 0x7FFF) || (expB == 0x7FFF) ) {
+        if ( softfloat_tryPropagateNaNF128M( aWPtr, bWPtr, zWPtr ) ) {
+            goto propagateNaN_ZC;
+        }
+        ptr = (uint32_t *) aWPtr;
+        if ( ! (uint32_t) (uiA96<<1) ) goto possibleInvalidProd;
+        if ( ! (uint32_t) (uiB96<<1) ) {
+            ptr = (uint32_t *) bWPtr;
+     possibleInvalidProd:
+            if (
+                ! (ptr[indexWord( 4, 2 )] | ptr[indexWord( 4, 1 )]
+                       | ptr[indexWord( 4, 0 )])
+            ) {
+                goto invalid;
+            }
+        }
+        prodIsInfinite = true;
+    }
+    if ( expC == 0x7FFF ) {
+        if (
+            fracF128UI96( uiC96 )
+                || (cWPtr[indexWord( 4, 2 )] | cWPtr[indexWord( 4, 1 )]
+                        | cWPtr[indexWord( 4, 0 )])
+        ) {
+            zWPtr[indexWordHi( 4 )] = 0;
+            goto propagateNaN_ZC;
+        }
+        if ( prodIsInfinite && (signProd != signC) ) goto invalid;
+        goto copyC;
+    }
+    if ( prodIsInfinite ) {
+        uiZ96 = packToF128UI96( signProd, 0x7FFF, 0 );
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA ) {
+        sigA[indexWordHi( 4 )] = fracF128UI96( uiA96 ) | 0x00010000;
+        sigA[indexWord( 4, 2 )] = aWPtr[indexWord( 4, 2 )];
+        sigA[indexWord( 4, 1 )] = aWPtr[indexWord( 4, 1 )];
+        sigA[indexWord( 4, 0 )] = aWPtr[indexWord( 4, 0 )];
+    } else {
+        expA = softfloat_shiftNormSigF128M( aWPtr, 0, sigA );
+        if ( expA == -128 ) goto zeroProd;
+    }
+    if ( expB ) {
+        sigX[indexWordHi( 4 )] = fracF128UI96( uiB96 ) | 0x00010000;
+        sigX[indexWord( 4, 2 )] = bWPtr[indexWord( 4, 2 )];
+        sigX[indexWord( 4, 1 )] = bWPtr[indexWord( 4, 1 )];
+        sigX[indexWord( 4, 0 )] = bWPtr[indexWord( 4, 0 )];
+    } else {
+        expB = softfloat_shiftNormSigF128M( bWPtr, 0, sigX );
+        if ( expB == -128 ) goto zeroProd;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expProd = expA + expB - 0x3FF0;
+    softfloat_mul128MTo256M( sigA, sigX, sigProd );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    wordSig = fracF128UI96( uiC96 );
+    if ( expC ) {
+        --expC;
+        wordSig |= 0x00010000;
+    }
+    sigX[indexWordHi( 5 )] = wordSig;
+    sigX[indexWord( 5, 3 )] = cWPtr[indexWord( 4, 2 )];
+    sigX[indexWord( 5, 2 )] = cWPtr[indexWord( 4, 1 )];
+    sigX[indexWord( 5, 1 )] = cWPtr[indexWord( 4, 0 )];
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    doSub = (signProd != signC);
+    addCarryMRoutinePtr =
+        doSub ? softfloat_addComplCarryM : softfloat_addCarryM;
+    expDiff = expProd - expC;
+    if ( expDiff <= 0 ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signC;
+        expZ = expC;
+        if (
+            sigProd[indexWord( 8, 2 )]
+                || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )])
+        ) {
+            sigProd[indexWord( 8, 3 )] |= 1;
+        }
+        extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )];
+        if ( expDiff ) {
+            softfloat_shiftRightJam160M( extSigPtr, -expDiff, extSigPtr );
+        }
+        carry = 0;
+        if ( doSub ) {
+            wordSig = extSigPtr[indexWordLo( 5 )];
+            extSigPtr[indexWordLo( 5 )] = -wordSig;
+            carry = ! wordSig;
+        }
+        (*addCarryMRoutinePtr)(
+            4,
+            &sigX[indexMultiwordHi( 5, 4 )],
+            extSigPtr + indexMultiwordHi( 5, 4 ),
+            carry,
+            extSigPtr + indexMultiwordHi( 5, 4 )
+        );
+        wordSig = extSigPtr[indexWordHi( 5 )];
+        if ( ! expZ ) {
+            if ( wordSig & 0x80000000 ) {
+                signZ = ! signZ;
+                softfloat_negX160M( extSigPtr );
+                wordSig = extSigPtr[indexWordHi( 5 )];
+            }
+            goto checkCancellation;
+        }
+        if ( wordSig < 0x00010000 ) {
+            --expZ;
+            softfloat_add160M( extSigPtr, extSigPtr, extSigPtr );
+            goto roundPack;
+        }
+        goto extSigReady_noCancellation;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signProd;
+        expZ = expProd;
+        sigX[indexWordLo( 5 )] = 0;
+        expDiff -= 128;
+        if ( 0 <= expDiff ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            if ( expDiff ) softfloat_shiftRightJam160M( sigX, expDiff, sigX );
+            wordSig = sigX[indexWordLo( 5 )];
+            carry = 0;
+            if ( doSub ) {
+                carry = ! wordSig;
+                wordSig = -wordSig;
+            }
+            carry =
+                (*addCarryMRoutinePtr)(
+                    4,
+                    &sigProd[indexMultiwordLo( 8, 4 )],
+                    &sigX[indexMultiwordHi( 5, 4 )],
+                    carry,
+                    &sigProd[indexMultiwordLo( 8, 4 )]
+                );
+            sigProd[indexWord( 8, 2 )] |= wordSig;
+            ptr = &sigProd[indexWord( 8, 4 )];
+        } else {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            shiftDist = expDiff & 31;
+            if ( shiftDist ) {
+                softfloat_shortShiftRight160M( sigX, shiftDist, sigX );
+            }
+            expDiff >>= 5;
+            extSigPtr =
+                &sigProd[indexMultiwordLo( 8, 5 )] - wordIncr
+                    + expDiff * -wordIncr;
+            carry =
+                (*addCarryMRoutinePtr)( 5, extSigPtr, sigX, doSub, extSigPtr );
+            if ( expDiff == -4 ) {
+                /*------------------------------------------------------------
+                *------------------------------------------------------------*/
+                wordSig = sigProd[indexWordHi( 8 )];
+                if ( wordSig & 0x80000000 ) {
+                    signZ = ! signZ;
+                    softfloat_negX256M( sigProd );
+                    wordSig = sigProd[indexWordHi( 8 )];
+                }
+                /*------------------------------------------------------------
+                *------------------------------------------------------------*/
+                if ( wordSig ) goto expProdBigger_noWordShift;
+                wordSig = sigProd[indexWord( 8, 6 )];
+                if ( 0x00040000 <= wordSig ) goto expProdBigger_noWordShift;
+                expZ -= 32;
+                extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )] - wordIncr;
+                for (;;) {
+                    if ( wordSig ) break;
+                    wordSig = extSigPtr[indexWord( 5, 3 )];
+                    if ( 0x00040000 <= wordSig ) break;
+                    expZ -= 32;
+                    extSigPtr -= wordIncr;
+                    if ( extSigPtr == &sigProd[indexMultiwordLo( 8, 5 )] ) {
+                        goto checkCancellation;
+                    }
+                }
+                /*------------------------------------------------------------
+                *------------------------------------------------------------*/
+                ptr = extSigPtr + indexWordLo( 5 );
+                do {
+                    ptr -= wordIncr;
+                    if ( *ptr ) {
+                        extSigPtr[indexWordLo( 5 )] |= 1;
+                        break;
+                    }
+                } while ( ptr != &sigProd[indexWordLo( 8 )] );
+                wordSig = extSigPtr[indexWordHi( 5 )];
+                goto extSigReady;
+            }
+            ptr = extSigPtr + indexWordHi( 5 ) + wordIncr;
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( carry != doSub ) {
+            if ( doSub ) {
+                do {
+                    wordSig = *ptr;
+                    *ptr = wordSig - 1;
+                    ptr += wordIncr;
+                } while ( ! wordSig );
+            } else {
+                do {
+                    wordSig = *ptr + 1;
+                    *ptr = wordSig;
+                    ptr += wordIncr;
+                } while ( ! wordSig );
+            }
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     expProdBigger_noWordShift:
+        if (
+            sigProd[indexWord( 8, 2 )]
+                || (sigProd[indexWord( 8, 1 )] | sigProd[indexWord( 8, 0 )])
+        ) {
+            sigProd[indexWord( 8, 3 )] |= 1;
+        }
+        extSigPtr = &sigProd[indexMultiwordHi( 8, 5 )];
+        wordSig = extSigPtr[indexWordHi( 5 )];
+    }
+ extSigReady:
+    roundPackRoutinePtr = softfloat_normRoundPackMToF128M;
+    if ( wordSig < 0x00010000 ) goto doRoundPack;
+ extSigReady_noCancellation:
+    if ( 0x00020000 <= wordSig ) {
+        ++expZ;
+        softfloat_shortShiftRightJam160M( extSigPtr, 1, extSigPtr );
+    }
+ roundPack:
+    roundPackRoutinePtr = softfloat_roundPackMToF128M;
+ doRoundPack:
+    (*roundPackRoutinePtr)( signZ, expZ, extSigPtr, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_invalidF128M( zWPtr );
+ propagateNaN_ZC:
+    softfloat_propagateNaNF128M( zWPtr, cWPtr, zWPtr );
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    if (
+        ! (uint32_t) (uiC96<<1) && (signProd != signC)
+            && ! cWPtr[indexWord( 4, 2 )]
+            && ! (cWPtr[indexWord( 4, 1 )] | cWPtr[indexWord( 4, 0 )])
+    ) {
+        goto completeCancellation;
+    }
+ copyC:
+    zWPtr[indexWordHi( 4 )] = uiC96;
+    zWPtr[indexWord( 4, 2 )] = cWPtr[indexWord( 4, 2 )];
+    zWPtr[indexWord( 4, 1 )] = cWPtr[indexWord( 4, 1 )];
+    zWPtr[indexWord( 4, 0 )] = cWPtr[indexWord( 4, 0 )];
+    return;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ checkCancellation:
+    if (
+        wordSig
+            || (extSigPtr[indexWord( 5, 3 )] | extSigPtr[indexWord( 5, 2 )])
+            || (extSigPtr[indexWord( 5, 1 )] | extSigPtr[indexWord( 5, 0 )])
+    ) {
+        goto extSigReady;
+    }
+ completeCancellation:
+    uiZ96 =
+        packToF128UI96(
+            (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+ uiZ:
+    zWPtr[indexWordHi( 4 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_mulAddF16.c b/addins/SoftFloat-3e/source/s_mulAddF16.c
new file mode 100644
index 000000000..3a684ac32
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mulAddF16.c
@@ -0,0 +1,226 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t
+ softfloat_mulAddF16(
+     uint_fast16_t uiA, uint_fast16_t uiB, uint_fast16_t uiC, uint_fast8_t op )
+{
+    bool signA;
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    bool signB;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    bool signC;
+    int_fast8_t expC;
+    uint_fast16_t sigC;
+    bool signProd;
+    uint_fast16_t magBits, uiZ;
+    struct exp8_sig16 normExpSig;
+    int_fast8_t expProd;
+    uint_fast32_t sigProd;
+    bool signZ;
+    int_fast8_t expZ;
+    uint_fast16_t sigZ;
+    int_fast8_t expDiff;
+    uint_fast32_t sig32Z, sig32C;
+    int_fast8_t shiftDist;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signF16UI( uiA );
+    expA  = expF16UI( uiA );
+    sigA  = fracF16UI( uiA );
+    signB = signF16UI( uiB );
+    expB  = expF16UI( uiB );
+    sigB  = fracF16UI( uiB );
+    signC = signF16UI( uiC ) ^ (op == softfloat_mulAdd_subC);
+    expC  = expF16UI( uiC );
+    sigC  = fracF16UI( uiC );
+    signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x1F ) {
+        if ( sigA || ((expB == 0x1F) && sigB) ) goto propagateNaN_ABC;
+        magBits = expB | sigB;
+        goto infProdArg;
+    }
+    if ( expB == 0x1F ) {
+        if ( sigB ) goto propagateNaN_ABC;
+        magBits = expA | sigA;
+        goto infProdArg;
+    }
+    if ( expC == 0x1F ) {
+        if ( sigC ) {
+            uiZ = 0;
+            goto propagateNaN_ZC;
+        }
+        uiZ = uiC;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF16Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF16Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expProd = expA + expB - 0xE;
+    sigA = (sigA | 0x0400)<<4;
+    sigB = (sigB | 0x0400)<<4;
+    sigProd = (uint_fast32_t) sigA * sigB;
+    if ( sigProd < 0x20000000 ) {
+        --expProd;
+        sigProd <<= 1;
+    }
+    signZ = signProd;
+    if ( ! expC ) {
+        if ( ! sigC ) {
+            expZ = expProd - 1;
+            sigZ = sigProd>>15 | ((sigProd & 0x7FFF) != 0);
+            goto roundPack;
+        }
+        normExpSig = softfloat_normSubnormalF16Sig( sigC );
+        expC = normExpSig.exp;
+        sigC = normExpSig.sig;
+    }
+    sigC = (sigC | 0x0400)<<3;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expProd - expC;
+    if ( signProd == signC ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff <= 0 ) {
+            expZ = expC;
+            sigZ = sigC + softfloat_shiftRightJam32( sigProd, 16 - expDiff );
+        } else {
+            expZ = expProd;
+            sig32Z =
+                sigProd
+                    + softfloat_shiftRightJam32(
+                          (uint_fast32_t) sigC<<16, expDiff );
+            sigZ = sig32Z>>16 | ((sig32Z & 0xFFFF) != 0 );
+        }
+        if ( sigZ < 0x4000 ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig32C = (uint_fast32_t) sigC<<16;
+        if ( expDiff < 0 ) {
+            signZ = signC;
+            expZ = expC;
+            sig32Z = sig32C - softfloat_shiftRightJam32( sigProd, -expDiff );
+        } else if ( ! expDiff ) {
+            expZ = expProd;
+            sig32Z = sigProd - sig32C;
+            if ( ! sig32Z ) goto completeCancellation;
+            if ( sig32Z & 0x80000000 ) {
+                signZ = ! signZ;
+                sig32Z = -sig32Z;
+            }
+        } else {
+            expZ = expProd;
+            sig32Z = sigProd - softfloat_shiftRightJam32( sig32C, expDiff );
+        }
+        shiftDist = softfloat_countLeadingZeros32( sig32Z ) - 1;
+        expZ -= shiftDist;
+        shiftDist -= 16;
+        if ( shiftDist < 0 ) {
+            sigZ =
+                sig32Z>>(-shiftDist)
+                    | ((uint32_t) (sig32Z<<(shiftDist & 31)) != 0);
+        } else {
+            sigZ = (uint_fast16_t) sig32Z<<shiftDist;
+        }
+    }
+ roundPack:
+    return softfloat_roundPackToF16( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN_ABC:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto propagateNaN_ZC;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infProdArg:
+    if ( magBits ) {
+        uiZ = packToF16UI( signProd, 0x1F, 0 );
+        if ( expC != 0x1F ) goto uiZ;
+        if ( sigC ) goto propagateNaN_ZC;
+        if ( signProd == signC ) goto uiZ;
+    }
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF16UI;
+ propagateNaN_ZC:
+    uiZ = softfloat_propagateNaNF16UI( uiZ, uiC );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    uiZ = uiC;
+    if ( ! (expC | sigC) && (signProd != signC) ) {
+ completeCancellation:
+        uiZ =
+            packToF16UI(
+                (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_mulAddF32.c b/addins/SoftFloat-3e/source/s_mulAddF32.c
new file mode 100644
index 000000000..6cdd9fdc0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mulAddF32.c
@@ -0,0 +1,224 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t
+ softfloat_mulAddF32(
+     uint_fast32_t uiA, uint_fast32_t uiB, uint_fast32_t uiC, uint_fast8_t op )
+{
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    bool signC;
+    int_fast16_t expC;
+    uint_fast32_t sigC;
+    bool signProd;
+    uint_fast32_t magBits, uiZ;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expProd;
+    uint_fast64_t sigProd;
+    bool signZ;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ;
+    int_fast16_t expDiff;
+    uint_fast64_t sig64Z, sig64C;
+    int_fast8_t shiftDist;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signF32UI( uiA );
+    expA  = expF32UI( uiA );
+    sigA  = fracF32UI( uiA );
+    signB = signF32UI( uiB );
+    expB  = expF32UI( uiB );
+    sigB  = fracF32UI( uiB );
+    signC = signF32UI( uiC ) ^ (op == softfloat_mulAdd_subC);
+    expC  = expF32UI( uiC );
+    sigC  = fracF32UI( uiC );
+    signProd = signA ^ signB ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0xFF ) {
+        if ( sigA || ((expB == 0xFF) && sigB) ) goto propagateNaN_ABC;
+        magBits = expB | sigB;
+        goto infProdArg;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN_ABC;
+        magBits = expA | sigA;
+        goto infProdArg;
+    }
+    if ( expC == 0xFF ) {
+        if ( sigC ) {
+            uiZ = 0;
+            goto propagateNaN_ZC;
+        }
+        uiZ = uiC;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expProd = expA + expB - 0x7E;
+    sigA = (sigA | 0x00800000)<<7;
+    sigB = (sigB | 0x00800000)<<7;
+    sigProd = (uint_fast64_t) sigA * sigB;
+    if ( sigProd < UINT64_C( 0x2000000000000000 ) ) {
+        --expProd;
+        sigProd <<= 1;
+    }
+    signZ = signProd;
+    if ( ! expC ) {
+        if ( ! sigC ) {
+            expZ = expProd - 1;
+            sigZ = softfloat_shortShiftRightJam64( sigProd, 31 );
+            goto roundPack;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( sigC );
+        expC = normExpSig.exp;
+        sigC = normExpSig.sig;
+    }
+    sigC = (sigC | 0x00800000)<<6;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expProd - expC;
+    if ( signProd == signC ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff <= 0 ) {
+            expZ = expC;
+            sigZ = sigC + softfloat_shiftRightJam64( sigProd, 32 - expDiff );
+        } else {
+            expZ = expProd;
+            sig64Z =
+                sigProd
+                    + softfloat_shiftRightJam64(
+                          (uint_fast64_t) sigC<<32, expDiff );
+            sigZ = softfloat_shortShiftRightJam64( sig64Z, 32 );
+        }
+        if ( sigZ < 0x40000000 ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sig64C = (uint_fast64_t) sigC<<32;
+        if ( expDiff < 0 ) {
+            signZ = signC;
+            expZ = expC;
+            sig64Z = sig64C - softfloat_shiftRightJam64( sigProd, -expDiff );
+        } else if ( ! expDiff ) {
+            expZ = expProd;
+            sig64Z = sigProd - sig64C;
+            if ( ! sig64Z ) goto completeCancellation;
+            if ( sig64Z & UINT64_C( 0x8000000000000000 ) ) {
+                signZ = ! signZ;
+                sig64Z = -sig64Z;
+            }
+        } else {
+            expZ = expProd;
+            sig64Z = sigProd - softfloat_shiftRightJam64( sig64C, expDiff );
+        }
+        shiftDist = softfloat_countLeadingZeros64( sig64Z ) - 1;
+        expZ -= shiftDist;
+        shiftDist -= 32;
+        if ( shiftDist < 0 ) {
+            sigZ = softfloat_shortShiftRightJam64( sig64Z, -shiftDist );
+        } else {
+            sigZ = (uint_fast32_t) sig64Z<<shiftDist;
+        }
+    }
+ roundPack:
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN_ABC:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto propagateNaN_ZC;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infProdArg:
+    if ( magBits ) {
+        uiZ = packToF32UI( signProd, 0xFF, 0 );
+        if ( expC != 0xFF ) goto uiZ;
+        if ( sigC ) goto propagateNaN_ZC;
+        if ( signProd == signC ) goto uiZ;
+    }
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+ propagateNaN_ZC:
+    uiZ = softfloat_propagateNaNF32UI( uiZ, uiC );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    uiZ = uiC;
+    if ( ! (expC | sigC) && (signProd != signC) ) {
+ completeCancellation:
+        uiZ =
+            packToF32UI(
+                (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_mulAddF64.c b/addins/SoftFloat-3e/source/s_mulAddF64.c
new file mode 100644
index 000000000..b8bb4c430
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_mulAddF64.c
@@ -0,0 +1,496 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+float64_t
+ softfloat_mulAddF64(
+     uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op )
+{
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    bool signC;
+    int_fast16_t expC;
+    uint_fast64_t sigC;
+    bool signZ;
+    uint_fast64_t magBits, uiZ;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+    struct uint128 sig128Z;
+    uint_fast64_t sigZ;
+    int_fast16_t expDiff;
+    struct uint128 sig128C;
+    int_fast8_t shiftDist;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    signB = signF64UI( uiB );
+    expB  = expF64UI( uiB );
+    sigB  = fracF64UI( uiB );
+    signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC);
+    expC  = expF64UI( uiC );
+    sigC  = fracF64UI( uiC );
+    signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC;
+        magBits = expB | sigB;
+        goto infProdArg;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN_ABC;
+        magBits = expA | sigA;
+        goto infProdArg;
+    }
+    if ( expC == 0x7FF ) {
+        if ( sigC ) {
+            uiZ = 0;
+            goto propagateNaN_ZC;
+        }
+        uiZ = uiC;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FE;
+    sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10;
+    sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<10;
+    sig128Z = softfloat_mul64To128( sigA, sigB );
+    if ( sig128Z.v64 < UINT64_C( 0x2000000000000000 ) ) {
+        --expZ;
+        sig128Z =
+            softfloat_add128(
+                sig128Z.v64, sig128Z.v0, sig128Z.v64, sig128Z.v0 );
+    }
+    if ( ! expC ) {
+        if ( ! sigC ) {
+            --expZ;
+            sigZ = sig128Z.v64<<1 | (sig128Z.v0 != 0);
+            goto roundPack;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( sigC );
+        expC = normExpSig.exp;
+        sigC = normExpSig.sig;
+    }
+    sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<9;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expZ - expC;
+    if ( expDiff < 0 ) {
+        expZ = expC;
+        if ( (signZ == signC) || (expDiff < -1) ) {
+            sig128Z.v64 = softfloat_shiftRightJam64( sig128Z.v64, -expDiff );
+        } else {
+            sig128Z =
+                softfloat_shortShiftRightJam128( sig128Z.v64, sig128Z.v0, 1 );
+        }
+    } else if ( expDiff ) {
+        sig128C = softfloat_shiftRightJam128( sigC, 0, expDiff );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signZ == signC ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff <= 0 ) {
+            sigZ = (sigC + sig128Z.v64) | (sig128Z.v0 != 0);
+        } else {
+            sig128Z =
+                softfloat_add128(
+                    sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 );
+            sigZ = sig128Z.v64 | (sig128Z.v0 != 0);
+        }
+        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff < 0 ) {
+            signZ = signC;
+            sig128Z = softfloat_sub128( sigC, 0, sig128Z.v64, sig128Z.v0 );
+        } else if ( ! expDiff ) {
+            sig128Z.v64 = sig128Z.v64 - sigC;
+            if ( ! (sig128Z.v64 | sig128Z.v0) ) goto completeCancellation;
+            if ( sig128Z.v64 & UINT64_C( 0x8000000000000000 ) ) {
+                signZ = ! signZ;
+                sig128Z = softfloat_sub128( 0, 0, sig128Z.v64, sig128Z.v0 );
+            }
+        } else {
+            sig128Z =
+                softfloat_sub128(
+                    sig128Z.v64, sig128Z.v0, sig128C.v64, sig128C.v0 );
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( ! sig128Z.v64 ) {
+            expZ -= 64;
+            sig128Z.v64 = sig128Z.v0;
+            sig128Z.v0 = 0;
+        }
+        shiftDist = softfloat_countLeadingZeros64( sig128Z.v64 ) - 1;
+        expZ -= shiftDist;
+        if ( shiftDist < 0 ) {
+            sigZ = softfloat_shortShiftRightJam64( sig128Z.v64, -shiftDist );
+        } else {
+            sig128Z =
+                softfloat_shortShiftLeft128(
+                    sig128Z.v64, sig128Z.v0, shiftDist );
+            sigZ = sig128Z.v64;
+        }
+        sigZ |= (sig128Z.v0 != 0);
+    }
+ roundPack:
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN_ABC:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto propagateNaN_ZC;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infProdArg:
+    if ( magBits ) {
+        uiZ = packToF64UI( signZ, 0x7FF, 0 );
+        if ( expC != 0x7FF ) goto uiZ;
+        if ( sigC ) goto propagateNaN_ZC;
+        if ( signZ == signC ) goto uiZ;
+    }
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+ propagateNaN_ZC:
+    uiZ = softfloat_propagateNaNF64UI( uiZ, uiC );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    uiZ = uiC;
+    if ( ! (expC | sigC) && (signZ != signC) ) {
+ completeCancellation:
+        uiZ =
+            packToF64UI(
+                (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#else
+
+float64_t
+ softfloat_mulAddF64(
+     uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC, uint_fast8_t op )
+{
+    bool signA;
+    int_fast16_t expA;
+    uint64_t sigA;
+    bool signB;
+    int_fast16_t expB;
+    uint64_t sigB;
+    bool signC;
+    int_fast16_t expC;
+    uint64_t sigC;
+    bool signZ;
+    uint64_t magBits, uiZ;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+    uint32_t sig128Z[4];
+    uint64_t sigZ;
+    int_fast16_t shiftDist, expDiff;
+    uint32_t sig128C[4];
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signA = signF64UI( uiA );
+    expA  = expF64UI( uiA );
+    sigA  = fracF64UI( uiA );
+    signB = signF64UI( uiB );
+    expB  = expF64UI( uiB );
+    sigB  = fracF64UI( uiB );
+    signC = signF64UI( uiC ) ^ (op == softfloat_mulAdd_subC);
+    expC  = expF64UI( uiC );
+    sigC  = fracF64UI( uiC );
+    signZ = signA ^ signB ^ (op == softfloat_mulAdd_subProd);
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( expA == 0x7FF ) {
+        if ( sigA || ((expB == 0x7FF) && sigB) ) goto propagateNaN_ABC;
+        magBits = expB | sigB;
+        goto infProdArg;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN_ABC;
+        magBits = expA | sigA;
+        goto infProdArg;
+    }
+    if ( expC == 0x7FF ) {
+        if ( sigC ) {
+            uiZ = 0;
+            goto propagateNaN_ZC;
+        }
+        uiZ = uiC;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( ! expA ) {
+        if ( ! sigA ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto zeroProd;
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA + expB - 0x3FE;
+    sigA = (sigA | UINT64_C( 0x0010000000000000 ))<<10;
+    sigB = (sigB | UINT64_C( 0x0010000000000000 ))<<11;
+    softfloat_mul64To128M( sigA, sigB, sig128Z );
+    sigZ =
+        (uint64_t) sig128Z[indexWord( 4, 3 )]<<32 | sig128Z[indexWord( 4, 2 )];
+    shiftDist = 0;
+    if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) {
+        --expZ;
+        shiftDist = -1;
+    }
+    if ( ! expC ) {
+        if ( ! sigC ) {
+            if ( shiftDist ) sigZ <<= 1;
+            goto sigZ;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( sigC );
+        expC = normExpSig.exp;
+        sigC = normExpSig.sig;
+    }
+    sigC = (sigC | UINT64_C( 0x0010000000000000 ))<<10;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expZ - expC;
+    if ( expDiff < 0 ) {
+        expZ = expC;
+        if ( (signZ == signC) || (expDiff < -1) ) {
+            shiftDist -= expDiff;
+            if ( shiftDist) {
+                sigZ = softfloat_shiftRightJam64( sigZ, shiftDist );
+            }
+        } else {
+            if ( ! shiftDist ) {
+                softfloat_shortShiftRight128M( sig128Z, 1, sig128Z );
+            }
+        }
+    } else {
+        if ( shiftDist ) softfloat_add128M( sig128Z, sig128Z, sig128Z );
+        if ( ! expDiff ) {
+            sigZ =
+                (uint64_t) sig128Z[indexWord( 4, 3 )]<<32
+                    | sig128Z[indexWord( 4, 2 )];
+        } else {
+            sig128C[indexWord( 4, 3 )] = sigC>>32;
+            sig128C[indexWord( 4, 2 )] = sigC;
+            sig128C[indexWord( 4, 1 )] = 0;
+            sig128C[indexWord( 4, 0 )] = 0;
+            softfloat_shiftRightJam128M( sig128C, expDiff, sig128C );
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( signZ == signC ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff <= 0 ) {
+            sigZ += sigC;
+        } else {
+            softfloat_add128M( sig128Z, sig128C, sig128Z );
+            sigZ =
+                (uint64_t) sig128Z[indexWord( 4, 3 )]<<32
+                    | sig128Z[indexWord( 4, 2 )];
+        }
+        if ( sigZ & UINT64_C( 0x8000000000000000 ) ) {
+            ++expZ;
+            sigZ = softfloat_shortShiftRightJam64( sigZ, 1 );
+        }
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expDiff < 0 ) {
+            signZ = signC;
+            if ( expDiff < -1 ) {
+                sigZ = sigC - sigZ;
+                if (
+                    sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )]
+                ) {
+                    sigZ = (sigZ - 1) | 1;
+                }
+                if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) {
+                    --expZ;
+                    sigZ <<= 1;
+                }
+                goto roundPack;
+            } else {
+                sig128C[indexWord( 4, 3 )] = sigC>>32;
+                sig128C[indexWord( 4, 2 )] = sigC;
+                sig128C[indexWord( 4, 1 )] = 0;
+                sig128C[indexWord( 4, 0 )] = 0;
+                softfloat_sub128M( sig128C, sig128Z, sig128Z );
+            }
+        } else if ( ! expDiff ) {
+            sigZ -= sigC;
+            if (
+                ! sigZ && ! sig128Z[indexWord( 4, 1 )]
+                    && ! sig128Z[indexWord( 4, 0 )]
+            ) {
+                goto completeCancellation;
+            }
+            sig128Z[indexWord( 4, 3 )] = sigZ>>32;
+            sig128Z[indexWord( 4, 2 )] = sigZ;
+            if ( sigZ & UINT64_C( 0x8000000000000000 ) ) {
+                signZ = ! signZ;
+                softfloat_negX128M( sig128Z );
+            }
+        } else {
+            softfloat_sub128M( sig128Z, sig128C, sig128Z );
+            if ( 1 < expDiff ) {
+                sigZ =
+                    (uint64_t) sig128Z[indexWord( 4, 3 )]<<32
+                        | sig128Z[indexWord( 4, 2 )];
+                if ( ! (sigZ & UINT64_C( 0x4000000000000000 )) ) {
+                    --expZ;
+                    sigZ <<= 1;
+                }
+                goto sigZ;
+            }
+        }
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        shiftDist = 0;
+        sigZ =
+            (uint64_t) sig128Z[indexWord( 4, 3 )]<<32
+                | sig128Z[indexWord( 4, 2 )];
+        if ( ! sigZ ) {
+            shiftDist = 64;
+            sigZ =
+                (uint64_t) sig128Z[indexWord( 4, 1 )]<<32
+                    | sig128Z[indexWord( 4, 0 )];
+        }
+        shiftDist += softfloat_countLeadingZeros64( sigZ ) - 1;
+        if ( shiftDist ) {
+            expZ -= shiftDist;
+            softfloat_shiftLeft128M( sig128Z, shiftDist, sig128Z );
+            sigZ =
+                (uint64_t) sig128Z[indexWord( 4, 3 )]<<32
+                    | sig128Z[indexWord( 4, 2 )];
+        }
+    }
+ sigZ:
+    if ( sig128Z[indexWord( 4, 1 )] || sig128Z[indexWord( 4, 0 )] ) sigZ |= 1;
+ roundPack:
+    return softfloat_roundPackToF64( signZ, expZ - 1, sigZ );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN_ABC:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto propagateNaN_ZC;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ infProdArg:
+    if ( magBits ) {
+        uiZ = packToF64UI( signZ, 0x7FF, 0 );
+        if ( expC != 0x7FF ) goto uiZ;
+        if ( sigC ) goto propagateNaN_ZC;
+        if ( signZ == signC ) goto uiZ;
+    }
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+ propagateNaN_ZC:
+    uiZ = softfloat_propagateNaNF64UI( uiZ, uiC );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ zeroProd:
+    uiZ = uiC;
+    if ( ! (expC | sigC) && (signZ != signC) ) {
+ completeCancellation:
+        uiZ =
+            packToF64UI(
+                (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_negXM.c b/addins/SoftFloat-3e/source/s_negXM.c
new file mode 100644
index 000000000..ec8c92886
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_negXM.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_negXM
+
+void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr )
+{
+    unsigned int index, lastIndex;
+    uint_fast8_t carry;
+    uint32_t word;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    carry = 1;
+    for (;;) {
+        word = ~zPtr[index] + carry;
+        zPtr[index] = word;
+        if ( index == lastIndex ) break;
+        index += wordIncr;
+        if ( word ) carry = 0;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_normExtF80SigM.c b/addins/SoftFloat-3e/source/s_normExtF80SigM.c
new file mode 100644
index 000000000..acc54dc63
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normExtF80SigM.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+int softfloat_normExtF80SigM( uint64_t *sigPtr )
+{
+    uint64_t sig;
+    int_fast8_t shiftDist;
+
+    sig = *sigPtr;
+    shiftDist = softfloat_countLeadingZeros64( sig );
+    *sigPtr = sig<<shiftDist;
+    return -shiftDist;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackMToExtF80M.c b/addins/SoftFloat-3e/source/s_normRoundPackMToExtF80M.c
new file mode 100644
index 000000000..88b69cd4c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackMToExtF80M.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+void
+ softfloat_normRoundPackMToExtF80M(
+     bool sign,
+     int32_t exp,
+     uint32_t *extSigPtr,
+     uint_fast8_t roundingPrecision,
+     struct extFloat80M *zSPtr
+ )
+{
+    int_fast16_t shiftDist;
+    uint32_t wordSig;
+
+    shiftDist = 0;
+    wordSig = extSigPtr[indexWord( 3, 2 )];
+    if ( ! wordSig ) {
+        shiftDist = 32;
+        wordSig = extSigPtr[indexWord( 3, 1 )];
+        if ( ! wordSig ) {
+            shiftDist = 64;
+            wordSig = extSigPtr[indexWord( 3, 0 )];
+            if ( ! wordSig ) {
+                zSPtr->signExp = packToExtF80UI64( sign, 0 );
+                zSPtr->signif = 0;
+                return;
+            }
+        }
+    }
+    shiftDist += softfloat_countLeadingZeros32( wordSig );
+    if ( shiftDist ) {
+        exp -= shiftDist;
+        softfloat_shiftLeft96M( extSigPtr, shiftDist, extSigPtr );
+    }
+    softfloat_roundPackMToExtF80M(
+        sign, exp, extSigPtr, roundingPrecision, zSPtr );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackMToF128M.c b/addins/SoftFloat-3e/source/s_normRoundPackMToF128M.c
new file mode 100644
index 000000000..309455998
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackMToF128M.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+void
+ softfloat_normRoundPackMToF128M(
+     bool sign, int32_t exp, uint32_t *extSigPtr, uint32_t *zWPtr )
+{
+    const uint32_t *ptr;
+    int_fast16_t shiftDist;
+    uint32_t wordSig;
+
+    ptr = extSigPtr + indexWordHi( 5 );
+    shiftDist = 0;
+    for (;;) {
+        wordSig = *ptr;
+        if ( wordSig ) break;
+        shiftDist += 32;
+        if ( 160 <= shiftDist ) {
+            zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, 0, 0 );
+            zWPtr[indexWord( 4, 2 )] = 0;
+            zWPtr[indexWord( 4, 1 )] = 0;
+            zWPtr[indexWord( 4, 0 )] = 0;
+            return;
+        }
+        ptr -= wordIncr;
+    }
+    shiftDist += softfloat_countLeadingZeros32( wordSig ) - 15;
+    if ( shiftDist ) {
+        exp -= shiftDist;
+        softfloat_shiftLeft160M( extSigPtr, shiftDist, extSigPtr );
+    }
+    softfloat_roundPackMToF128M( sign, exp, extSigPtr, zWPtr );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackToExtF80.c b/addins/SoftFloat-3e/source/s_normRoundPackToExtF80.c
new file mode 100644
index 000000000..76e791d91
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackToExtF80.c
@@ -0,0 +1,71 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+extFloat80_t
+ softfloat_normRoundPackToExtF80(
+     bool sign,
+     int_fast32_t exp,
+     uint_fast64_t sig,
+     uint_fast64_t sigExtra,
+     uint_fast8_t roundingPrecision
+ )
+{
+    int_fast8_t shiftDist;
+    struct uint128 sig128;
+
+    if ( ! sig ) {
+        exp -= 64;
+        sig = sigExtra;
+        sigExtra = 0;
+    }
+    shiftDist = softfloat_countLeadingZeros64( sig );
+    exp -= shiftDist;
+    if ( shiftDist ) {
+        sig128 = softfloat_shortShiftLeft128( sig, sigExtra, shiftDist );
+        sig = sig128.v64;
+        sigExtra = sig128.v0;
+    }
+    return
+        softfloat_roundPackToExtF80(
+            sign, exp, sig, sigExtra, roundingPrecision );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackToF128.c b/addins/SoftFloat-3e/source/s_normRoundPackToF128.c
new file mode 100644
index 000000000..67f5b4349
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackToF128.c
@@ -0,0 +1,81 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+float128_t
+ softfloat_normRoundPackToF128(
+     bool sign, int_fast32_t exp, uint_fast64_t sig64, uint_fast64_t sig0 )
+{
+    int_fast8_t shiftDist;
+    struct uint128 sig128;
+    union ui128_f128 uZ;
+    uint_fast64_t sigExtra;
+    struct uint128_extra sig128Extra;
+
+    if ( ! sig64 ) {
+        exp -= 64;
+        sig64 = sig0;
+        sig0 = 0;
+    }
+    shiftDist = softfloat_countLeadingZeros64( sig64 ) - 15;
+    exp -= shiftDist;
+    if ( 0 <= shiftDist ) {
+        if ( shiftDist ) {
+            sig128 = softfloat_shortShiftLeft128( sig64, sig0, shiftDist );
+            sig64 = sig128.v64;
+            sig0  = sig128.v0;
+        }
+        if ( (uint32_t) exp < 0x7FFD ) {
+            uZ.ui.v64 = packToF128UI64( sign, sig64 | sig0 ? exp : 0, sig64 );
+            uZ.ui.v0  = sig0;
+            return uZ.f;
+        }
+        sigExtra = 0;
+    } else {
+        sig128Extra =
+            softfloat_shortShiftRightJam128Extra( sig64, sig0, 0, -shiftDist );
+        sig64 = sig128Extra.v.v64;
+        sig0  = sig128Extra.v.v0;
+        sigExtra = sig128Extra.extra;
+    }
+    return softfloat_roundPackToF128( sign, exp, sig64, sig0, sigExtra );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackToF16.c b/addins/SoftFloat-3e/source/s_normRoundPackToF16.c
new file mode 100644
index 000000000..1d184d58b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackToF16.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+float16_t
+ softfloat_normRoundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig )
+{
+    int_fast8_t shiftDist;
+    union ui16_f16 uZ;
+
+    shiftDist = softfloat_countLeadingZeros16( sig ) - 1;
+    exp -= shiftDist;
+    if ( (4 <= shiftDist) && ((unsigned int) exp < 0x1D) ) {
+        uZ.ui = packToF16UI( sign, sig ? exp : 0, sig<<(shiftDist - 4) );
+        return uZ.f;
+    } else {
+        return softfloat_roundPackToF16( sign, exp, sig<<shiftDist );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackToF32.c b/addins/SoftFloat-3e/source/s_normRoundPackToF32.c
new file mode 100644
index 000000000..9fae91631
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackToF32.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+float32_t
+ softfloat_normRoundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
+{
+    int_fast8_t shiftDist;
+    union ui32_f32 uZ;
+
+    shiftDist = softfloat_countLeadingZeros32( sig ) - 1;
+    exp -= shiftDist;
+    if ( (7 <= shiftDist) && ((unsigned int) exp < 0xFD) ) {
+        uZ.ui = packToF32UI( sign, sig ? exp : 0, sig<<(shiftDist - 7) );
+        return uZ.f;
+    } else {
+        return softfloat_roundPackToF32( sign, exp, sig<<shiftDist );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normRoundPackToF64.c b/addins/SoftFloat-3e/source/s_normRoundPackToF64.c
new file mode 100644
index 000000000..109141fad
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normRoundPackToF64.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+float64_t
+ softfloat_normRoundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
+{
+    int_fast8_t shiftDist;
+    union ui64_f64 uZ;
+
+    shiftDist = softfloat_countLeadingZeros64( sig ) - 1;
+    exp -= shiftDist;
+    if ( (10 <= shiftDist) && ((unsigned int) exp < 0x7FD) ) {
+        uZ.ui = packToF64UI( sign, sig ? exp : 0, sig<<(shiftDist - 10) );
+        return uZ.f;
+    } else {
+        return softfloat_roundPackToF64( sign, exp, sig<<shiftDist );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalExtF80Sig.c b/addins/SoftFloat-3e/source/s_normSubnormalExtF80Sig.c
new file mode 100644
index 000000000..c1d7788b1
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalExtF80Sig.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t sig )
+{
+    int_fast8_t shiftDist;
+    struct exp32_sig64 z;
+
+    shiftDist = softfloat_countLeadingZeros64( sig );
+    z.exp = -shiftDist;
+    z.sig = sig<<shiftDist;
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalF128Sig.c b/addins/SoftFloat-3e/source/s_normSubnormalF128Sig.c
new file mode 100644
index 000000000..597d558cc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalF128Sig.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp32_sig128
+ softfloat_normSubnormalF128Sig( uint_fast64_t sig64, uint_fast64_t sig0 )
+{
+    int_fast8_t shiftDist;
+    struct exp32_sig128 z;
+
+    if ( ! sig64 ) {
+        shiftDist = softfloat_countLeadingZeros64( sig0 ) - 15;
+        z.exp = -63 - shiftDist;
+        if ( shiftDist < 0 ) {
+            z.sig.v64 = sig0>>-shiftDist;
+            z.sig.v0  = sig0<<(shiftDist & 63);
+        } else {
+            z.sig.v64 = sig0<<shiftDist;
+            z.sig.v0  = 0;
+        }
+    } else {
+        shiftDist = softfloat_countLeadingZeros64( sig64 ) - 15;
+        z.exp = 1 - shiftDist;
+        z.sig = softfloat_shortShiftLeft128( sig64, sig0, shiftDist );
+    }
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalF128SigM.c b/addins/SoftFloat-3e/source/s_normSubnormalF128SigM.c
new file mode 100644
index 000000000..7b8ced1d4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalF128SigM.c
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+int softfloat_normSubnormalF128SigM( uint32_t *sigPtr )
+{
+    const uint32_t *ptr;
+    int_fast16_t shiftDist;
+    uint32_t wordSig;
+
+    ptr = sigPtr + indexWordHi( 4 );
+    shiftDist = 0;
+    for (;;) {
+        wordSig = *ptr;
+        if ( wordSig ) break;
+        shiftDist += 32;
+        if ( 128 <= shiftDist ) return 1;
+        ptr -= wordIncr;
+    }
+    shiftDist += softfloat_countLeadingZeros32( wordSig ) - 15;
+    if ( shiftDist ) softfloat_shiftLeft128M( sigPtr, shiftDist, sigPtr );
+    return 1 - shiftDist;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalF16Sig.c b/addins/SoftFloat-3e/source/s_normSubnormalF16Sig.c
new file mode 100644
index 000000000..bb92adfea
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalF16Sig.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t sig )
+{
+    int_fast8_t shiftDist;
+    struct exp8_sig16 z;
+
+    shiftDist = softfloat_countLeadingZeros16( sig ) - 5;
+    z.exp = 1 - shiftDist;
+    z.sig = sig<<shiftDist;
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalF32Sig.c b/addins/SoftFloat-3e/source/s_normSubnormalF32Sig.c
new file mode 100644
index 000000000..d4bff9b41
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalF32Sig.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig )
+{
+    int_fast8_t shiftDist;
+    struct exp16_sig32 z;
+
+    shiftDist = softfloat_countLeadingZeros32( sig ) - 8;
+    z.exp = 1 - shiftDist;
+    z.sig = sig<<shiftDist;
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_normSubnormalF64Sig.c b/addins/SoftFloat-3e/source/s_normSubnormalF64Sig.c
new file mode 100644
index 000000000..0c63b97d5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_normSubnormalF64Sig.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig )
+{
+    int_fast8_t shiftDist;
+    struct exp16_sig64 z;
+
+    shiftDist = softfloat_countLeadingZeros64( sig ) - 11;
+    z.exp = 1 - shiftDist;
+    z.sig = sig<<shiftDist;
+    return z;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_remStepMBy32.c b/addins/SoftFloat-3e/source/s_remStepMBy32.c
new file mode 100644
index 000000000..dd7d78d46
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_remStepMBy32.c
@@ -0,0 +1,86 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_remStepMBy32
+
+void
+ softfloat_remStepMBy32(
+     uint_fast8_t size_words,
+     const uint32_t *remPtr,
+     uint_fast8_t dist,
+     const uint32_t *bPtr,
+     uint32_t q,
+     uint32_t *zPtr
+ )
+{
+    unsigned int index, lastIndex;
+    uint64_t dwordProd;
+    uint32_t wordRem, wordShiftedRem, wordProd;
+    uint_fast8_t uNegDist, borrow;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    dwordProd = (uint64_t) bPtr[index] * q;
+    wordRem = remPtr[index];
+    wordShiftedRem = wordRem<<dist;
+    wordProd = dwordProd;
+    zPtr[index] = wordShiftedRem - wordProd;
+    if ( index != lastIndex ) {
+        uNegDist = -dist;
+        borrow = (wordShiftedRem < wordProd);
+        for (;;) {
+            wordShiftedRem = wordRem>>(uNegDist & 31);
+            index += wordIncr;
+            dwordProd = (uint64_t) bPtr[index] * q + (dwordProd>>32);
+            wordRem = remPtr[index];
+            wordShiftedRem |= wordRem<<dist;
+            wordProd = dwordProd;
+            zPtr[index] = wordShiftedRem - wordProd - borrow;
+            if ( index == lastIndex ) break;
+            borrow =
+                borrow ? (wordShiftedRem <= wordProd)
+                    : (wordShiftedRem < wordProd);
+        }
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_roundMToI64.c b/addins/SoftFloat-3e/source/s_roundMToI64.c
new file mode 100644
index 000000000..66f43b24d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundMToI64.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t
+ softfloat_roundMToI64(
+     bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint64_t sig;
+    uint32_t sigExtra;
+    union { uint64_t ui; int64_t i; } uZ;
+    int64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig =
+        (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32
+            | extSigPtr[indexWord( 3, 1 )];
+    sigExtra = extSigPtr[indexWordLo( 3 )];
+    if (
+        (roundingMode == softfloat_round_near_maxMag)
+            || (roundingMode == softfloat_round_near_even)
+    ) {
+        if ( 0x80000000 <= sigExtra ) goto increment;
+    } else {
+        if (
+            sigExtra
+                && (sign
+                        ? (roundingMode == softfloat_round_min)
+#ifdef SOFTFLOAT_ROUND_ODD
+                              || (roundingMode == softfloat_round_odd)
+#endif
+                        : (roundingMode == softfloat_round_max))
+        ) {
+ increment:
+            ++sig;
+            if ( !sig ) goto invalid;
+            if (
+                (sigExtra == 0x80000000)
+                    && (roundingMode == softfloat_round_near_even)
+            ) {
+                sig &= ~(uint_fast64_t) 1;
+            }
+        }
+    }
+    uZ.ui = sign ? -sig : sig;
+    z = uZ.i;
+    if ( z && ((z < 0) ^ sign) ) goto invalid;
+    if ( sigExtra ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) z |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundMToUI64.c b/addins/SoftFloat-3e/source/s_roundMToUI64.c
new file mode 100644
index 000000000..196f53735
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundMToUI64.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t
+ softfloat_roundMToUI64(
+     bool sign, uint32_t *extSigPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint64_t sig;
+    uint32_t sigExtra;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig =
+        (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32
+            | extSigPtr[indexWord( 3, 1 )];
+    sigExtra = extSigPtr[indexWordLo( 3 )];
+    if (
+        (roundingMode == softfloat_round_near_maxMag)
+            || (roundingMode == softfloat_round_near_even)
+    ) {
+        if ( 0x80000000 <= sigExtra ) goto increment;
+    } else {
+        if ( sign ) {
+            if ( !(sig | sigExtra) ) return 0;
+            if ( roundingMode == softfloat_round_min ) goto invalid;
+#ifdef SOFTFLOAT_ROUND_ODD
+            if ( roundingMode == softfloat_round_odd ) goto invalid;
+#endif
+        } else {
+            if ( (roundingMode == softfloat_round_max) && sigExtra ) {
+ increment:
+                ++sig;
+                if ( !sig ) goto invalid;
+                if (
+                    (sigExtra == 0x80000000)
+                        && (roundingMode == softfloat_round_near_even)
+                ) {
+                    sig &= ~(uint_fast64_t) 1;
+                }
+            }
+        }
+    }
+    if ( sign && sig ) goto invalid;
+    if ( sigExtra ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) sig |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sig;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackMToExtF80M.c b/addins/SoftFloat-3e/source/s_roundPackMToExtF80M.c
new file mode 100644
index 000000000..08620159f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackMToExtF80M.c
@@ -0,0 +1,256 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+void
+ softfloat_roundPackMToExtF80M(
+     bool sign,
+     int32_t exp,
+     uint32_t *extSigPtr,
+     uint_fast8_t roundingPrecision,
+     struct extFloat80M *zSPtr
+ )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint64_t sig, roundIncrement, roundMask, roundBits;
+    bool isTiny;
+    uint32_t sigExtra;
+    bool doIncrement;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    sig =
+        (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32
+            | extSigPtr[indexWord( 3, 1 )];
+    if ( roundingPrecision == 80 ) goto precision80;
+    if ( roundingPrecision == 64 ) {
+        roundIncrement = UINT64_C( 0x0000000000000400 );
+        roundMask = UINT64_C( 0x00000000000007FF );
+    } else if ( roundingPrecision == 32 ) {
+        roundIncrement = UINT64_C( 0x0000008000000000 );
+        roundMask = UINT64_C( 0x000000FFFFFFFFFF );
+    } else {
+        goto precision80;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( extSigPtr[indexWordLo( 3 )] ) sig |= 1;
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? roundMask
+                : 0;
+    }
+    roundBits = sig & roundMask;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) (exp - 1) ) {
+        if ( exp <= 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < 0)
+                || (sig <= (uint64_t) (sig + roundIncrement));
+            sig = softfloat_shiftRightJam64( sig, 1 - exp );
+            roundBits = sig & roundMask;
+            if ( roundBits ) {
+                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+                if ( roundingMode == softfloat_round_odd ) {
+                    sig |= roundMask + 1;
+                }
+#endif
+            }
+            sig += roundIncrement;
+            exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0);
+            roundIncrement = roundMask + 1;
+            if ( roundNearEven && (roundBits<<1 == roundIncrement) ) {
+                roundMask |= roundIncrement;
+            }
+            sig &= ~roundMask;
+            goto packReturn;
+        }
+        if (
+               (0x7FFE < exp)
+            || ((exp == 0x7FFE) && ((uint64_t) (sig + roundIncrement) < sig))
+        ) {
+            goto overflow;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig = (sig & ~roundMask) | (roundMask + 1);
+            goto packReturn;
+        }
+#endif
+    }
+    sig += roundIncrement;
+    if ( sig < roundIncrement ) {
+        ++exp;
+        sig = UINT64_C( 0x8000000000000000 );
+    }
+    roundIncrement = roundMask + 1;
+    if ( roundNearEven && (roundBits<<1 == roundIncrement) ) {
+        roundMask |= roundIncrement;
+    }
+    sig &= ~roundMask;
+    goto packReturn;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ precision80:
+    sigExtra = extSigPtr[indexWordLo( 3 )];
+    doIncrement = (0x80000000 <= sigExtra);
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        doIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                && sigExtra;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) (exp - 1) ) {
+        if ( exp <= 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < 0)
+                || ! doIncrement
+                || (sig < UINT64_C( 0xFFFFFFFFFFFFFFFF ));
+            softfloat_shiftRightJam96M( extSigPtr, 1 - exp, extSigPtr );
+            exp = 0;
+            sig =
+                (uint64_t) extSigPtr[indexWord( 3, 2 )]<<32
+                    | extSigPtr[indexWord( 3, 1 )];
+            sigExtra = extSigPtr[indexWordLo( 3 )];
+            if ( sigExtra ) {
+                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+                if ( roundingMode == softfloat_round_odd ) {
+                    sig |= 1;
+                    goto packReturn;
+                }
+#endif
+            }
+            doIncrement = (0x80000000 <= sigExtra);
+            if (
+                ! roundNearEven
+                    && (roundingMode != softfloat_round_near_maxMag)
+            ) {
+                doIncrement =
+                    (roundingMode
+                         == (sign ? softfloat_round_min : softfloat_round_max))
+                        && sigExtra;
+            }
+            if ( doIncrement ) {
+                ++sig;
+                sig &= ~(uint64_t) (! (sigExtra & 0x7FFFFFFF) & roundNearEven);
+                exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0);
+            }
+            goto packReturn;
+        }
+        if (
+               (0x7FFE < exp)
+            || ((exp == 0x7FFE) && (sig == UINT64_C( 0xFFFFFFFFFFFFFFFF ))
+                    && doIncrement)
+        ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            roundMask = 0;
+ overflow:
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            if (
+                   roundNearEven
+                || (roundingMode == softfloat_round_near_maxMag)
+                || (roundingMode
+                        == (sign ? softfloat_round_min : softfloat_round_max))
+            ) {
+                exp = 0x7FFF;
+                sig = UINT64_C( 0x8000000000000000 );
+            } else {
+                exp = 0x7FFE;
+                sig = ~roundMask;
+            }
+            goto packReturn;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( sigExtra ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    if ( doIncrement ) {
+        ++sig;
+        if ( ! sig ) {
+            ++exp;
+            sig = UINT64_C( 0x8000000000000000 );
+        } else {
+            sig &= ~(uint64_t) (! (sigExtra & 0x7FFFFFFF) & roundNearEven);
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    zSPtr->signExp = packToExtF80UI64( sign, exp );
+    zSPtr->signif = sig;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackMToF128M.c b/addins/SoftFloat-3e/source/s_roundPackMToF128M.c
new file mode 100644
index 000000000..22591b835
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackMToF128M.c
@@ -0,0 +1,178 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+void
+ softfloat_roundPackMToF128M(
+     bool sign, int32_t exp, uint32_t *extSigPtr, uint32_t *zWPtr )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint32_t sigExtra;
+    bool doIncrement, isTiny;
+    static const uint32_t maxSig[4] =
+        INIT_UINTM4( 0x0001FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF );
+    uint32_t ui, uj;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    sigExtra = extSigPtr[indexWordLo( 5 )];
+    doIncrement = (0x80000000 <= sigExtra);
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        doIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                && sigExtra;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < -1)
+                || ! doIncrement
+                || (softfloat_compare128M(
+                        extSigPtr + indexMultiwordHi( 5, 4 ), maxSig )
+                        < 0);
+            softfloat_shiftRightJam160M( extSigPtr, -exp, extSigPtr );
+            exp = 0;
+            sigExtra = extSigPtr[indexWordLo( 5 )];
+            if ( isTiny && sigExtra ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+            doIncrement = (0x80000000 <= sigExtra);
+            if (
+                   ! roundNearEven
+                && (roundingMode != softfloat_round_near_maxMag)
+            ) {
+                doIncrement =
+                    (roundingMode
+                         == (sign ? softfloat_round_min : softfloat_round_max))
+                        && sigExtra;
+            }
+        } else if (
+               (0x7FFD < exp)
+            || ((exp == 0x7FFD) && doIncrement
+                    && (softfloat_compare128M(
+                            extSigPtr + indexMultiwordHi( 5, 4 ), maxSig )
+                            == 0))
+        ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            if (
+                   roundNearEven
+                || (roundingMode == softfloat_round_near_maxMag)
+                || (roundingMode
+                        == (sign ? softfloat_round_min : softfloat_round_max))
+            ) {
+                ui = packToF128UI96( sign, 0x7FFF, 0 );
+                uj = 0;
+            } else {
+                ui = packToF128UI96( sign, 0x7FFE, 0x0000FFFF );
+                uj = 0xFFFFFFFF;
+            }
+            zWPtr[indexWordHi( 4 )] = ui;
+            zWPtr[indexWord( 4, 2 )] = uj;
+            zWPtr[indexWord( 4, 1 )] = uj;
+            zWPtr[indexWord( 4, 0 )] = uj;
+            return;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    uj = extSigPtr[indexWord( 5, 1 )];
+    if ( sigExtra ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            uj |= 1;
+            goto noIncrementPackReturn;
+        }
+#endif
+    }
+    if ( doIncrement ) {
+        ++uj;
+        if ( uj ) {
+            if ( ! (sigExtra & 0x7FFFFFFF) && roundNearEven ) uj &= ~1;
+            zWPtr[indexWord( 4, 2 )] = extSigPtr[indexWord( 5, 3 )];
+            zWPtr[indexWord( 4, 1 )] = extSigPtr[indexWord( 5, 2 )];
+            zWPtr[indexWord( 4, 0 )] = uj;
+            ui = extSigPtr[indexWordHi( 5 )];
+        } else {
+            zWPtr[indexWord( 4, 0 )] = uj;
+            ui = extSigPtr[indexWord( 5, 2 )] + 1;
+            zWPtr[indexWord( 4, 1 )] = ui;
+            uj = extSigPtr[indexWord( 5, 3 )];
+            if ( ui ) {
+                zWPtr[indexWord( 4, 2 )] = uj;
+                ui = extSigPtr[indexWordHi( 5 )];
+            } else {
+                ++uj;
+                zWPtr[indexWord( 4, 2 )] = uj;
+                ui = extSigPtr[indexWordHi( 5 )];
+                if ( ! uj ) ++ui;
+            }
+        }
+    } else {
+ noIncrementPackReturn:
+        zWPtr[indexWord( 4, 0 )] = uj;
+        ui = extSigPtr[indexWord( 5, 2 )];
+        zWPtr[indexWord( 4, 1 )] = ui;
+        uj |= ui;
+        ui = extSigPtr[indexWord( 5, 3 )];
+        zWPtr[indexWord( 4, 2 )] = ui;
+        uj |= ui;
+        ui = extSigPtr[indexWordHi( 5 )];
+        uj |= ui;
+        if ( ! uj ) exp = 0;
+    }
+    zWPtr[indexWordHi( 4 )] = packToF128UI96( sign, exp, ui );
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackToExtF80.c b/addins/SoftFloat-3e/source/s_roundPackToExtF80.c
new file mode 100644
index 000000000..0cc7af985
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackToExtF80.c
@@ -0,0 +1,256 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t
+ softfloat_roundPackToExtF80(
+     bool sign,
+     int_fast32_t exp,
+     uint_fast64_t sig,
+     uint_fast64_t sigExtra,
+     uint_fast8_t roundingPrecision
+ )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint_fast64_t roundIncrement, roundMask, roundBits;
+    bool isTiny, doIncrement;
+    struct uint64_extra sig64Extra;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    if ( roundingPrecision == 80 ) goto precision80;
+    if ( roundingPrecision == 64 ) {
+        roundIncrement = UINT64_C( 0x0000000000000400 );
+        roundMask = UINT64_C( 0x00000000000007FF );
+    } else if ( roundingPrecision == 32 ) {
+        roundIncrement = UINT64_C( 0x0000008000000000 );
+        roundMask = UINT64_C( 0x000000FFFFFFFFFF );
+    } else {
+        goto precision80;
+    }
+    sig |= (sigExtra != 0);
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? roundMask
+                : 0;
+    }
+    roundBits = sig & roundMask;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) (exp - 1) ) {
+        if ( exp <= 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < 0)
+                || (sig <= (uint64_t) (sig + roundIncrement));
+            sig = softfloat_shiftRightJam64( sig, 1 - exp );
+            roundBits = sig & roundMask;
+            if ( roundBits ) {
+                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+                if ( roundingMode == softfloat_round_odd ) {
+                    sig |= roundMask + 1;
+                }
+#endif
+            }
+            sig += roundIncrement;
+            exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0);
+            roundIncrement = roundMask + 1;
+            if ( roundNearEven && (roundBits<<1 == roundIncrement) ) {
+                roundMask |= roundIncrement;
+            }
+            sig &= ~roundMask;
+            goto packReturn;
+        }
+        if (
+               (0x7FFE < exp)
+            || ((exp == 0x7FFE) && ((uint64_t) (sig + roundIncrement) < sig))
+        ) {
+            goto overflow;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig = (sig & ~roundMask) | (roundMask + 1);
+            goto packReturn;
+        }
+#endif
+    }
+    sig = (uint64_t) (sig + roundIncrement);
+    if ( sig < roundIncrement ) {
+        ++exp;
+        sig = UINT64_C( 0x8000000000000000 );
+    }
+    roundIncrement = roundMask + 1;
+    if ( roundNearEven && (roundBits<<1 == roundIncrement) ) {
+        roundMask |= roundIncrement;
+    }
+    sig &= ~roundMask;
+    goto packReturn;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ precision80:
+    doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra);
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        doIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                && sigExtra;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) (exp - 1) ) {
+        if ( exp <= 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < 0)
+                || ! doIncrement
+                || (sig < UINT64_C( 0xFFFFFFFFFFFFFFFF ));
+            sig64Extra =
+                softfloat_shiftRightJam64Extra( sig, sigExtra, 1 - exp );
+            exp = 0;
+            sig = sig64Extra.v;
+            sigExtra = sig64Extra.extra;
+            if ( sigExtra ) {
+                if ( isTiny ) softfloat_raiseFlags( softfloat_flag_underflow );
+                softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+                if ( roundingMode == softfloat_round_odd ) {
+                    sig |= 1;
+                    goto packReturn;
+                }
+#endif
+            }
+            doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra);
+            if (
+                ! roundNearEven
+                    && (roundingMode != softfloat_round_near_maxMag)
+            ) {
+                doIncrement =
+                    (roundingMode
+                         == (sign ? softfloat_round_min : softfloat_round_max))
+                        && sigExtra;
+            }
+            if ( doIncrement ) {
+                ++sig;
+                sig &=
+                    ~(uint_fast64_t)
+                         (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                              & roundNearEven);
+                exp = ((sig & UINT64_C( 0x8000000000000000 )) != 0);
+            }
+            goto packReturn;
+        }
+        if (
+               (0x7FFE < exp)
+            || ((exp == 0x7FFE) && (sig == UINT64_C( 0xFFFFFFFFFFFFFFFF ))
+                    && doIncrement)
+        ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            roundMask = 0;
+ overflow:
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            if (
+                   roundNearEven
+                || (roundingMode == softfloat_round_near_maxMag)
+                || (roundingMode
+                        == (sign ? softfloat_round_min : softfloat_round_max))
+            ) {
+                exp = 0x7FFF;
+                sig = UINT64_C( 0x8000000000000000 );
+            } else {
+                exp = 0x7FFE;
+                sig = ~roundMask;
+            }
+            goto packReturn;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( sigExtra ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    if ( doIncrement ) {
+        ++sig;
+        if ( ! sig ) {
+            ++exp;
+            sig = UINT64_C( 0x8000000000000000 );
+        } else {
+            sig &=
+                ~(uint_fast64_t)
+                     (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                          & roundNearEven);
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uZ.s.signExp = packToExtF80UI64( sign, exp );
+    uZ.s.signif = sig;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackToF128.c b/addins/SoftFloat-3e/source/s_roundPackToF128.c
new file mode 100644
index 000000000..41584316a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackToF128.c
@@ -0,0 +1,171 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t
+ softfloat_roundPackToF128(
+     bool sign,
+     int_fast32_t exp,
+     uint_fast64_t sig64,
+     uint_fast64_t sig0,
+     uint_fast64_t sigExtra
+ )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven, doIncrement, isTiny;
+    struct uint128_extra sig128Extra;
+    uint_fast64_t uiZ64, uiZ0;
+    struct uint128 sig128;
+    union ui128_f128 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra);
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        doIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                && sigExtra;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FFD <= (uint32_t) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                   (softfloat_detectTininess
+                        == softfloat_tininess_beforeRounding)
+                || (exp < -1)
+                || ! doIncrement
+                || softfloat_lt128(
+                       sig64,
+                       sig0,
+                       UINT64_C( 0x0001FFFFFFFFFFFF ),
+                       UINT64_C( 0xFFFFFFFFFFFFFFFF )
+                   );
+            sig128Extra =
+                softfloat_shiftRightJam128Extra( sig64, sig0, sigExtra, -exp );
+            sig64 = sig128Extra.v.v64;
+            sig0  = sig128Extra.v.v0;
+            sigExtra = sig128Extra.extra;
+            exp = 0;
+            if ( isTiny && sigExtra ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+            doIncrement = (UINT64_C( 0x8000000000000000 ) <= sigExtra);
+            if (
+                   ! roundNearEven
+                && (roundingMode != softfloat_round_near_maxMag)
+            ) {
+                doIncrement =
+                    (roundingMode
+                         == (sign ? softfloat_round_min : softfloat_round_max))
+                        && sigExtra;
+            }
+        } else if (
+               (0x7FFD < exp)
+            || ((exp == 0x7FFD)
+                    && softfloat_eq128( 
+                           sig64,
+                           sig0,
+                           UINT64_C( 0x0001FFFFFFFFFFFF ),
+                           UINT64_C( 0xFFFFFFFFFFFFFFFF )
+                       )
+                    && doIncrement)
+        ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            if (
+                   roundNearEven
+                || (roundingMode == softfloat_round_near_maxMag)
+                || (roundingMode
+                        == (sign ? softfloat_round_min : softfloat_round_max))
+            ) {
+                uiZ64 = packToF128UI64( sign, 0x7FFF, 0 );
+                uiZ0  = 0;
+            } else {
+                uiZ64 =
+                    packToF128UI64(
+                        sign, 0x7FFE, UINT64_C( 0x0000FFFFFFFFFFFF ) );
+                uiZ0 = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+            }
+            goto uiZ;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( sigExtra ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig0 |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    if ( doIncrement ) {
+        sig128 = softfloat_add128( sig64, sig0, 0, 1 );
+        sig64 = sig128.v64;
+        sig0 =
+            sig128.v0
+                & ~(uint64_t)
+                       (! (sigExtra & UINT64_C( 0x7FFFFFFFFFFFFFFF ))
+                            & roundNearEven);
+    } else {
+        if ( ! (sig64 | sig0) ) exp = 0;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uiZ64 = packToF128UI64( sign, exp, sig64 );
+    uiZ0  = sig0;
+ uiZ:
+    uZ.ui.v64 = uiZ64;
+    uZ.ui.v0  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackToF16.c b/addins/SoftFloat-3e/source/s_roundPackToF16.c
new file mode 100644
index 000000000..2dde55bb4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackToF16.c
@@ -0,0 +1,113 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t
+ softfloat_roundPackToF16( bool sign, int_fast16_t exp, uint_fast16_t sig )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint_fast8_t roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast16_t uiZ;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    roundIncrement = 0x8;
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? 0xF
+                : 0;
+    }
+    roundBits = sig & 0xF;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x1D <= (unsigned int) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                    || (exp < -1) || (sig + roundIncrement < 0x8000);
+            sig = softfloat_shiftRightJam32( sig, -exp );
+            exp = 0;
+            roundBits = sig & 0xF;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if ( (0x1D < exp) || (0x8000 <= sig + roundIncrement) ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToF16UI( sign, 0x1F, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig + roundIncrement)>>4;
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    sig &= ~(uint_fast16_t) (! (roundBits ^ 8) & roundNearEven);
+    if ( ! sig ) exp = 0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uiZ = packToF16UI( sign, exp, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackToF32.c b/addins/SoftFloat-3e/source/s_roundPackToF32.c
new file mode 100644
index 000000000..a69b8d4d7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackToF32.c
@@ -0,0 +1,113 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t
+ softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint_fast8_t roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    roundIncrement = 0x40;
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? 0x7F
+                : 0;
+    }
+    roundBits = sig & 0x7F;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0xFD <= (unsigned int) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                    || (exp < -1) || (sig + roundIncrement < 0x80000000);
+            sig = softfloat_shiftRightJam32( sig, -exp );
+            exp = 0;
+            roundBits = sig & 0x7F;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if ( (0xFD < exp) || (0x80000000 <= sig + roundIncrement) ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig + roundIncrement)>>7;
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    sig &= ~(uint_fast32_t) (! (roundBits ^ 0x40) & roundNearEven);
+    if ( ! sig ) exp = 0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uiZ = packToF32UI( sign, exp, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundPackToF64.c b/addins/SoftFloat-3e/source/s_roundPackToF64.c
new file mode 100644
index 000000000..f7f3abff5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundPackToF64.c
@@ -0,0 +1,117 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t
+ softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
+{
+    uint_fast8_t roundingMode;
+    bool roundNearEven;
+    uint_fast16_t roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundingMode = softfloat_roundingMode;
+    roundNearEven = (roundingMode == softfloat_round_near_even);
+    roundIncrement = 0x200;
+    if ( ! roundNearEven && (roundingMode != softfloat_round_near_maxMag) ) {
+        roundIncrement =
+            (roundingMode
+                 == (sign ? softfloat_round_min : softfloat_round_max))
+                ? 0x3FF
+                : 0;
+    }
+    roundBits = sig & 0x3FF;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( 0x7FD <= (uint16_t) exp ) {
+        if ( exp < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            isTiny =
+                (softfloat_detectTininess == softfloat_tininess_beforeRounding)
+                    || (exp < -1)
+                    || (sig + roundIncrement < UINT64_C( 0x8000000000000000 ));
+            sig = softfloat_shiftRightJam64( sig, -exp );
+            exp = 0;
+            roundBits = sig & 0x3FF;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if (
+            (0x7FD < exp)
+                || (UINT64_C( 0x8000000000000000 ) <= sig + roundIncrement)
+        ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    sig = (sig + roundIncrement)>>10;
+    if ( roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) {
+            sig |= 1;
+            goto packReturn;
+        }
+#endif
+    }
+    sig &= ~(uint_fast64_t) (! (roundBits ^ 0x200) & roundNearEven);
+    if ( ! sig ) exp = 0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ packReturn:
+    uiZ = packToF64UI( sign, exp, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundToI32.c b/addins/SoftFloat-3e/source/s_roundToI32.c
new file mode 100644
index 000000000..a3e727dc7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundToI32.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast32_t
+ softfloat_roundToI32(
+     bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast16_t roundIncrement, roundBits;
+    uint_fast32_t sig32;
+    union { uint32_t ui; int32_t i; } uZ;
+    int_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundIncrement = 0x800;
+    if (
+        (roundingMode != softfloat_round_near_maxMag)
+            && (roundingMode != softfloat_round_near_even)
+    ) {
+        roundIncrement = 0;
+        if ( 
+            sign
+                ? (roundingMode == softfloat_round_min)
+#ifdef SOFTFLOAT_ROUND_ODD
+                      || (roundingMode == softfloat_round_odd)
+#endif
+                : (roundingMode == softfloat_round_max)
+        ) {
+            roundIncrement = 0xFFF;
+        }
+    }
+    roundBits = sig & 0xFFF;
+    sig += roundIncrement;
+    if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid;
+    sig32 = sig>>12;
+    if (
+        (roundBits == 0x800) && (roundingMode == softfloat_round_near_even)
+    ) {
+        sig32 &= ~(uint_fast32_t) 1;
+    }
+    uZ.ui = sign ? -sig32 : sig32;
+    z = uZ.i;
+    if ( z && ((z < 0) ^ sign) ) goto invalid;
+    if ( roundBits ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) z |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? i32_fromNegOverflow : i32_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundToI64.c b/addins/SoftFloat-3e/source/s_roundToI64.c
new file mode 100644
index 000000000..773c82cfc
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundToI64.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+int_fast64_t
+ softfloat_roundToI64(
+     bool sign,
+     uint_fast64_t sig,
+     uint_fast64_t sigExtra,
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union { uint64_t ui; int64_t i; } uZ;
+    int_fast64_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if (
+        (roundingMode == softfloat_round_near_maxMag)
+            || (roundingMode == softfloat_round_near_even)
+    ) {
+        if ( UINT64_C( 0x8000000000000000 ) <= sigExtra ) goto increment;
+    } else {
+        if (
+            sigExtra
+                && (sign
+                        ? (roundingMode == softfloat_round_min)
+#ifdef SOFTFLOAT_ROUND_ODD
+                              || (roundingMode == softfloat_round_odd)
+#endif
+                        : (roundingMode == softfloat_round_max))
+        ) {
+ increment:
+            ++sig;
+            if ( !sig ) goto invalid;
+            if (
+                (sigExtra == UINT64_C( 0x8000000000000000 ))
+                    && (roundingMode == softfloat_round_near_even)
+            ) {
+                sig &= ~(uint_fast64_t) 1;
+            }
+        }
+    }
+    uZ.ui = sign ? -sig : sig;
+    z = uZ.i;
+    if ( z && ((z < 0) ^ sign) ) goto invalid;
+    if ( sigExtra ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) z |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? i64_fromNegOverflow : i64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundToUI32.c b/addins/SoftFloat-3e/source/s_roundToUI32.c
new file mode 100644
index 000000000..059e231e2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundToUI32.c
@@ -0,0 +1,93 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast32_t
+ softfloat_roundToUI32(
+     bool sign, uint_fast64_t sig, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast16_t roundIncrement, roundBits;
+    uint_fast32_t z;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    roundIncrement = 0x800;
+    if ( 
+        (roundingMode != softfloat_round_near_maxMag) 
+            && (roundingMode != softfloat_round_near_even)
+    ) {
+        roundIncrement = 0;
+        if ( sign ) {
+            if ( !sig ) return 0;
+            if ( roundingMode == softfloat_round_min ) goto invalid;
+#ifdef SOFTFLOAT_ROUND_ODD
+            if ( roundingMode == softfloat_round_odd ) goto invalid;
+#endif
+        } else {
+            if ( roundingMode == softfloat_round_max ) roundIncrement = 0xFFF;
+        }
+    }
+    roundBits = sig & 0xFFF;
+    sig += roundIncrement;
+    if ( sig & UINT64_C( 0xFFFFF00000000000 ) ) goto invalid;
+    z = sig>>12;
+    if ( 
+        (roundBits == 0x800) && (roundingMode == softfloat_round_near_even)
+    ) {
+        z &= ~(uint_fast32_t) 1;
+    }
+    if ( sign && z ) goto invalid;
+    if ( roundBits ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) z |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_roundToUI64.c b/addins/SoftFloat-3e/source/s_roundToUI64.c
new file mode 100644
index 000000000..856ad9792
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_roundToUI64.c
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+uint_fast64_t
+ softfloat_roundToUI64(
+     bool sign,
+     uint_fast64_t sig,
+     uint_fast64_t sigExtra,
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if (
+        (roundingMode == softfloat_round_near_maxMag)
+            || (roundingMode == softfloat_round_near_even)
+    ) {
+        if ( UINT64_C( 0x8000000000000000 ) <= sigExtra ) goto increment;
+    } else {
+        if ( sign ) {
+            if ( !(sig | sigExtra) ) return 0;
+            if ( roundingMode == softfloat_round_min ) goto invalid;
+#ifdef SOFTFLOAT_ROUND_ODD
+            if ( roundingMode == softfloat_round_odd ) goto invalid;
+#endif
+        } else {
+            if ( (roundingMode == softfloat_round_max) && sigExtra ) {
+ increment:
+                ++sig;
+                if ( !sig ) goto invalid;
+                if ( 
+                    (sigExtra == UINT64_C( 0x8000000000000000 ))
+                        && (roundingMode == softfloat_round_near_even)
+                ) {
+                    sig &= ~(uint_fast64_t) 1;
+                }
+            }
+        }
+    }
+    if ( sign && sig ) goto invalid;
+    if ( sigExtra ) {
+#ifdef SOFTFLOAT_ROUND_ODD
+        if ( roundingMode == softfloat_round_odd ) sig |= 1;
+#endif
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return sig;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_shiftLeftM.c b/addins/SoftFloat-3e/source/s_shiftLeftM.c
new file mode 100644
index 000000000..71a309919
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftLeftM.c
@@ -0,0 +1,91 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shiftLeftM
+
+#define softfloat_shiftLeftM softfloat_shiftLeftM
+#include "primitives.h"
+
+void
+ softfloat_shiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint32_t wordDist;
+    uint_fast8_t innerDist;
+    uint32_t *destPtr;
+    uint_fast8_t i;
+
+    wordDist = dist>>5;
+    if ( wordDist < size_words ) {
+        aPtr += indexMultiwordLoBut( size_words, wordDist );
+        innerDist = dist & 31;
+        if ( innerDist ) {
+            softfloat_shortShiftLeftM(
+                size_words - wordDist,
+                aPtr,
+                innerDist,
+                zPtr + indexMultiwordHiBut( size_words, wordDist )
+            );
+            if ( ! wordDist ) return;
+        } else {
+            aPtr += indexWordHi( size_words - wordDist );
+            destPtr = zPtr + indexWordHi( size_words );
+            for ( i = size_words - wordDist; i; --i ) {
+                *destPtr = *aPtr;
+                aPtr -= wordIncr;
+                destPtr -= wordIncr;
+            }
+        }
+        zPtr += indexMultiwordLo( size_words, wordDist );
+    } else {
+        wordDist = size_words;
+    }
+    do {
+        *zPtr++ = 0;
+        --wordDist;
+    } while ( wordDist );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftNormSigF128M.c b/addins/SoftFloat-3e/source/s_shiftNormSigF128M.c
new file mode 100644
index 000000000..fa4976c8e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftNormSigF128M.c
@@ -0,0 +1,78 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+
+int
+ softfloat_shiftNormSigF128M(
+     const uint32_t *wPtr, uint_fast8_t shiftDist, uint32_t *sigPtr )
+{
+    uint32_t wordSig;
+    int32_t exp;
+    uint32_t leadingBit;
+
+    wordSig = wPtr[indexWordHi( 4 )];
+    exp = expF128UI96( wordSig );
+    if ( exp ) {
+        softfloat_shortShiftLeft128M( wPtr, shiftDist, sigPtr );
+        leadingBit = 0x00010000<<shiftDist;
+        sigPtr[indexWordHi( 4 )] =
+            (sigPtr[indexWordHi( 4 )] & (leadingBit - 1)) | leadingBit;
+    } else {
+        exp = 16;
+        wordSig &= 0x7FFFFFFF;
+        if ( ! wordSig ) {
+            exp = -16;
+            wordSig = wPtr[indexWord( 4, 2 )];
+            if ( ! wordSig ) {
+                exp = -48;
+                wordSig = wPtr[indexWord( 4, 1 )];
+                if ( ! wordSig ) {
+                    wordSig = wPtr[indexWord( 4, 0 )];
+                    if ( ! wordSig ) return -128;
+                    exp = -80;
+                }
+            }
+        }
+        exp -= softfloat_countLeadingZeros32( wordSig );
+        softfloat_shiftLeft128M( wPtr, 1 - exp + shiftDist, sigPtr );
+    }
+    return exp;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam128.c b/addins/SoftFloat-3e/source/s_shiftRightJam128.c
new file mode 100644
index 000000000..aac5f6db0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam128.c
@@ -0,0 +1,69 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shiftRightJam128
+
+struct uint128
+ softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist )
+{
+    uint_fast8_t u8NegDist;
+    struct uint128 z;
+
+    if ( dist < 64 ) {
+        u8NegDist = -dist;
+        z.v64 = a64>>dist;
+        z.v0 =
+            a64<<(u8NegDist & 63) | a0>>dist
+                | ((uint64_t) (a0<<(u8NegDist & 63)) != 0);
+    } else {
+        z.v64 = 0;
+        z.v0 =
+            (dist < 127)
+                ? a64>>(dist & 63)
+                      | (((a64 & (((uint_fast64_t) 1<<(dist & 63)) - 1)) | a0)
+                             != 0)
+                : ((a64 | a0) != 0);
+    }
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam128Extra.c b/addins/SoftFloat-3e/source/s_shiftRightJam128Extra.c
new file mode 100644
index 000000000..75722887b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam128Extra.c
@@ -0,0 +1,77 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shiftRightJam128Extra
+
+struct uint128_extra
+ softfloat_shiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist )
+{
+    uint_fast8_t u8NegDist;
+    struct uint128_extra z;
+
+    u8NegDist = -dist;
+    if ( dist < 64 ) {
+        z.v.v64 = a64>>dist;
+        z.v.v0 = a64<<(u8NegDist & 63) | a0>>dist;
+        z.extra = a0<<(u8NegDist & 63);
+    } else {
+        z.v.v64 = 0;
+        if ( dist == 64 ) {
+            z.v.v0 = a64;
+            z.extra = a0;
+        } else {
+            extra |= a0;
+            if ( dist < 128 ) {
+                z.v.v0 = a64>>(dist & 63);
+                z.extra = a64<<(u8NegDist & 63);
+            } else {
+                z.v.v0 = 0;
+                z.extra = (dist == 128) ? a64 : (a64 != 0);
+            }
+        }
+    }
+    z.extra |= (extra != 0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam256M.c b/addins/SoftFloat-3e/source/s_shiftRightJam256M.c
new file mode 100644
index 000000000..433870a81
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam256M.c
@@ -0,0 +1,126 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shiftRightJam256M
+
+static
+ void
+  softfloat_shortShiftRightJamM(
+      uint_fast8_t size_words,
+      const uint64_t *aPtr,
+      uint_fast8_t dist,
+      uint64_t *zPtr
+  )
+{
+    uint_fast8_t uNegDist;
+    unsigned int index, lastIndex;
+    uint64_t partWordZ, wordA;
+
+    uNegDist = -dist;
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    wordA = aPtr[index];
+    partWordZ = wordA>>dist;
+    if ( partWordZ<<dist != wordA ) partWordZ |= 1;
+    while ( index != lastIndex ) {
+        wordA = aPtr[index + wordIncr];
+        zPtr[index] = wordA<<(uNegDist & 63) | partWordZ;
+        index += wordIncr;
+        partWordZ = wordA>>dist;
+    }
+    zPtr[index] = partWordZ;
+
+}
+
+void
+ softfloat_shiftRightJam256M(
+     const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr )
+{
+    uint64_t wordJam;
+    uint_fast32_t wordDist;
+    uint64_t *ptr;
+    uint_fast8_t i, innerDist;
+
+    wordJam = 0;
+    wordDist = dist>>6;
+    if ( wordDist ) {
+        if ( 4 < wordDist ) wordDist = 4;
+        ptr = (uint64_t *) (aPtr + indexMultiwordLo( 4, wordDist ));
+        i = wordDist;
+        do {
+            wordJam = *ptr++;
+            if ( wordJam ) break;
+            --i;
+        } while ( i );
+        ptr = zPtr;
+    }
+    if ( wordDist < 4 ) {
+        aPtr += indexMultiwordHiBut( 4, wordDist );
+        innerDist = dist & 63;
+        if ( innerDist ) {
+            softfloat_shortShiftRightJamM(
+                4 - wordDist,
+                aPtr,
+                innerDist,
+                zPtr + indexMultiwordLoBut( 4, wordDist )
+            );
+            if ( ! wordDist ) goto wordJam;
+        } else {
+            aPtr += indexWordLo( 4 - wordDist );
+            ptr = zPtr + indexWordLo( 4 );
+            for ( i = 4 - wordDist; i; --i ) {
+                *ptr = *aPtr;
+                aPtr += wordIncr;
+                ptr += wordIncr;
+            }
+        }
+        ptr = zPtr + indexMultiwordHi( 4, wordDist );
+    }
+    do {
+        *ptr++ = 0;
+        --wordDist;
+    } while ( wordDist );
+ wordJam:
+    if ( wordJam ) zPtr[indexWordLo( 4 )] |= 1;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam32.c b/addins/SoftFloat-3e/source/s_shiftRightJam32.c
new file mode 100644
index 000000000..2533fcd95
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam32.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shiftRightJam32
+
+uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist )
+{
+
+    return
+        (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam64.c b/addins/SoftFloat-3e/source/s_shiftRightJam64.c
new file mode 100644
index 000000000..4b40e3de6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam64.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shiftRightJam64
+
+uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist )
+{
+
+    return
+        (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJam64Extra.c b/addins/SoftFloat-3e/source/s_shiftRightJam64Extra.c
new file mode 100644
index 000000000..b93fad39c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJam64Extra.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shiftRightJam64Extra
+
+struct uint64_extra
+ softfloat_shiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast32_t dist )
+{
+    struct uint64_extra z;
+
+    if ( dist < 64 ) {
+        z.v = a>>dist;
+        z.extra = a<<(-dist & 63);
+    } else {
+        z.v = 0;
+        z.extra = (dist == 64) ? a : (a != 0);
+    }
+    z.extra |= (extra != 0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightJamM.c b/addins/SoftFloat-3e/source/s_shiftRightJamM.c
new file mode 100644
index 000000000..edf5f956b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightJamM.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shiftRightJamM
+
+#define softfloat_shiftRightJamM softfloat_shiftRightJamM
+#include "primitives.h"
+
+void
+ softfloat_shiftRightJamM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint32_t wordJam, wordDist, *ptr;
+    uint_fast8_t i, innerDist;
+
+    wordJam = 0;
+    wordDist = dist>>5;
+    if ( wordDist ) {
+        if ( size_words < wordDist ) wordDist = size_words;
+        ptr = (uint32_t *) (aPtr + indexMultiwordLo( size_words, wordDist ));
+        i = wordDist;
+        do {
+            wordJam = *ptr++;
+            if ( wordJam ) break;
+            --i;
+        } while ( i );
+        ptr = zPtr;
+    }
+    if ( wordDist < size_words ) {
+        aPtr += indexMultiwordHiBut( size_words, wordDist );
+        innerDist = dist & 31;
+        if ( innerDist ) {
+            softfloat_shortShiftRightJamM(
+                size_words - wordDist,
+                aPtr,
+                innerDist,
+                zPtr + indexMultiwordLoBut( size_words, wordDist )
+            );
+            if ( ! wordDist ) goto wordJam;
+        } else {
+            aPtr += indexWordLo( size_words - wordDist );
+            ptr = zPtr + indexWordLo( size_words );
+            for ( i = size_words - wordDist; i; --i ) {
+                *ptr = *aPtr;
+                aPtr += wordIncr;
+                ptr += wordIncr;
+            }
+        }
+        ptr = zPtr + indexMultiwordHi( size_words, wordDist );
+    }
+    do {
+        *ptr++ = 0;
+        --wordDist;
+    } while ( wordDist );
+ wordJam:
+    if ( wordJam ) zPtr[indexWordLo( size_words )] |= 1;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shiftRightM.c b/addins/SoftFloat-3e/source/s_shiftRightM.c
new file mode 100644
index 000000000..00265ea23
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shiftRightM.c
@@ -0,0 +1,91 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shiftRightM
+
+#define softfloat_shiftRightM softfloat_shiftRightM
+#include "primitives.h"
+
+void
+ softfloat_shiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint32_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint32_t wordDist;
+    uint_fast8_t innerDist;
+    uint32_t *destPtr;
+    uint_fast8_t i;
+
+    wordDist = dist>>5;
+    if ( wordDist < size_words ) {
+        aPtr += indexMultiwordHiBut( size_words, wordDist );
+        innerDist = dist & 31;
+        if ( innerDist ) {
+            softfloat_shortShiftRightM(
+                size_words - wordDist,
+                aPtr,
+                innerDist,
+                zPtr + indexMultiwordLoBut( size_words, wordDist )
+            );
+            if ( ! wordDist ) return;
+        } else {
+            aPtr += indexWordLo( size_words - wordDist );
+            destPtr = zPtr + indexWordLo( size_words );
+            for ( i = size_words - wordDist; i; --i ) {
+                *destPtr = *aPtr;
+                aPtr += wordIncr;
+                destPtr += wordIncr;
+            }
+        }
+        zPtr += indexMultiwordHi( size_words, wordDist );
+    } else {
+        wordDist = size_words;
+    }
+    do {
+        *zPtr++ = 0;
+        --wordDist;
+    } while ( wordDist );
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftLeft128.c b/addins/SoftFloat-3e/source/s_shortShiftLeft128.c
new file mode 100644
index 000000000..7513bc627
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftLeft128.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftLeft128
+
+struct uint128
+ softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    struct uint128 z;
+
+    z.v64 = a64<<dist | a0>>(-dist & 63);
+    z.v0 = a0<<dist;
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftLeft64To96M.c b/addins/SoftFloat-3e/source/s_shortShiftLeft64To96M.c
new file mode 100644
index 000000000..ce1f09b23
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftLeft64To96M.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftLeft64To96M
+
+void
+ softfloat_shortShiftLeft64To96M(
+     uint64_t a, uint_fast8_t dist, uint32_t *zPtr )
+{
+
+    zPtr[indexWord( 3, 0 )] = (uint32_t) a<<dist;
+    a >>= 32 - dist;
+    zPtr[indexWord( 3, 2 )] = a>>32;
+    zPtr[indexWord( 3, 1 )] = a;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftLeftM.c b/addins/SoftFloat-3e/source/s_shortShiftLeftM.c
new file mode 100644
index 000000000..48e6e03b5
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftLeftM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftLeftM
+
+void
+ softfloat_shortShiftLeftM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint_fast8_t uNegDist;
+    unsigned int index, lastIndex;
+    uint32_t partWordZ, wordA;
+
+    uNegDist = -dist;
+    index = indexWordHi( size_words );
+    lastIndex = indexWordLo( size_words );
+    partWordZ = aPtr[index]<<dist;
+    while ( index != lastIndex ) {
+        wordA = aPtr[index - wordIncr];
+        zPtr[index] = partWordZ | wordA>>(uNegDist & 31);
+        index -= wordIncr;
+        partWordZ = wordA<<dist;
+    }
+    zPtr[index] = partWordZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRight128.c b/addins/SoftFloat-3e/source/s_shortShiftRight128.c
new file mode 100644
index 000000000..8f5c650b2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRight128.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRight128
+
+struct uint128
+ softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    struct uint128 z;
+
+    z.v64 = a64>>dist;
+    z.v0 = a64<<(-dist & 63) | a0>>dist;
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightExtendM.c b/addins/SoftFloat-3e/source/s_shortShiftRightExtendM.c
new file mode 100644
index 000000000..bc441c731
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightExtendM.c
@@ -0,0 +1,73 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightExtendM
+
+void
+ softfloat_shortShiftRightExtendM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint_fast8_t uNegDist;
+    unsigned int indexA, lastIndexA;
+    uint32_t partWordZ, wordA;
+
+    uNegDist = -dist;
+    indexA = indexWordLo( size_words );
+    lastIndexA = indexWordHi( size_words );
+    zPtr += indexWordLo( size_words + 1 );
+    partWordZ = 0;
+    for (;;) {
+        wordA = aPtr[indexA];
+        *zPtr = wordA<<(uNegDist & 31) | partWordZ;
+        zPtr += wordIncr;
+        partWordZ = wordA>>dist;
+        if ( indexA == lastIndexA ) break;
+        indexA += wordIncr;
+    }
+    *zPtr = partWordZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightJam128.c b/addins/SoftFloat-3e/source/s_shortShiftRightJam128.c
new file mode 100644
index 000000000..76008722b
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightJam128.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightJam128
+
+struct uint128
+ softfloat_shortShiftRightJam128(
+     uint64_t a64, uint64_t a0, uint_fast8_t dist )
+{
+    uint_fast8_t uNegDist;
+    struct uint128 z;
+
+    uNegDist = -dist;
+    z.v64 = a64>>dist;
+    z.v0 =
+        a64<<(uNegDist & 63) | a0>>dist
+            | ((uint64_t) (a0<<(uNegDist & 63)) != 0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightJam128Extra.c b/addins/SoftFloat-3e/source/s_shortShiftRightJam128Extra.c
new file mode 100644
index 000000000..b0774401d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightJam128Extra.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightJam128Extra
+
+struct uint128_extra
+ softfloat_shortShiftRightJam128Extra(
+     uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist )
+{
+    uint_fast8_t uNegDist;
+    struct uint128_extra z;
+
+    uNegDist = -dist;
+    z.v.v64 = a64>>dist;
+    z.v.v0 = a64<<(uNegDist & 63) | a0>>dist;
+    z.extra = a0<<(uNegDist & 63) | (extra != 0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightJam64.c b/addins/SoftFloat-3e/source/s_shortShiftRightJam64.c
new file mode 100644
index 000000000..d3044c853
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightJam64.c
@@ -0,0 +1,50 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifndef softfloat_shortShiftRightJam64
+
+uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist )
+{
+
+    return a>>dist | ((a & (((uint_fast64_t) 1<<dist) - 1)) != 0);
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightJam64Extra.c b/addins/SoftFloat-3e/source/s_shortShiftRightJam64Extra.c
new file mode 100644
index 000000000..f2af92bc0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightJam64Extra.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightJam64Extra
+
+struct uint64_extra
+ softfloat_shortShiftRightJam64Extra(
+     uint64_t a, uint64_t extra, uint_fast8_t dist )
+{
+    struct uint64_extra z;
+
+    z.v = a>>dist;
+    z.extra = a<<(-dist & 63) | (extra != 0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightJamM.c b/addins/SoftFloat-3e/source/s_shortShiftRightJamM.c
new file mode 100644
index 000000000..b567e482a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightJamM.c
@@ -0,0 +1,72 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightJamM
+
+void
+ softfloat_shortShiftRightJamM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint_fast8_t uNegDist;
+    unsigned int index, lastIndex;
+    uint32_t partWordZ, wordA;
+
+    uNegDist = -dist;
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    wordA = aPtr[index];
+    partWordZ = wordA>>dist;
+    if ( partWordZ<<dist != wordA ) partWordZ |= 1;
+    while ( index != lastIndex ) {
+        wordA = aPtr[index + wordIncr];
+        zPtr[index] = wordA<<(uNegDist & 31) | partWordZ;
+        index += wordIncr;
+        partWordZ = wordA>>dist;
+    }
+    zPtr[index] = partWordZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_shortShiftRightM.c b/addins/SoftFloat-3e/source/s_shortShiftRightM.c
new file mode 100644
index 000000000..54e0071c7
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_shortShiftRightM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_shortShiftRightM
+
+void
+ softfloat_shortShiftRightM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     uint_fast8_t dist,
+     uint32_t *zPtr
+ )
+{
+    uint_fast8_t uNegDist;
+    unsigned int index, lastIndex;
+    uint32_t partWordZ, wordA;
+
+    uNegDist = -dist;
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    partWordZ = aPtr[index]>>dist;
+    while ( index != lastIndex ) {
+        wordA = aPtr[index + wordIncr];
+        zPtr[index] = wordA<<(uNegDist & 31) | partWordZ;
+        index += wordIncr;
+        partWordZ = wordA>>dist;
+    }
+    zPtr[index] = partWordZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_sub128.c b/addins/SoftFloat-3e/source/s_sub128.c
new file mode 100644
index 000000000..9bf346391
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_sub128.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_sub128
+
+struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+
+    z.v0 = a0 - b0;
+    z.v64 = a64 - b64 - (a0 < b0);
+    return z;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_sub1XM.c b/addins/SoftFloat-3e/source/s_sub1XM.c
new file mode 100644
index 000000000..30c5d36ee
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_sub1XM.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_sub1XM
+
+void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr )
+{
+    unsigned int index, lastIndex;
+    uint32_t wordA;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    for (;;) {
+        wordA = zPtr[index];
+        zPtr[index] = wordA - 1;
+        if ( wordA || (index == lastIndex) ) break;
+        index += wordIncr;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_sub256M.c b/addins/SoftFloat-3e/source/s_sub256M.c
new file mode 100644
index 000000000..a4af5a1c9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_sub256M.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_sub256M
+
+void
+ softfloat_sub256M(
+     const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr )
+{
+    unsigned int index;
+    uint_fast8_t borrow;
+    uint64_t wordA, wordB;
+
+    index = indexWordLo( 4 );
+    borrow = 0;
+    for (;;) {
+        wordA = aPtr[index];
+        wordB = bPtr[index];
+        zPtr[index] = wordA - wordB - borrow;
+        if ( index == indexWordHi( 4 ) ) break;
+        borrow = borrow ? (wordA <= wordB) : (wordA < wordB);
+        index += wordIncr;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_subM.c b/addins/SoftFloat-3e/source/s_subM.c
new file mode 100644
index 000000000..fcccc744c
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subM.c
@@ -0,0 +1,70 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitiveTypes.h"
+
+#ifndef softfloat_subM
+
+void
+ softfloat_subM(
+     uint_fast8_t size_words,
+     const uint32_t *aPtr,
+     const uint32_t *bPtr,
+     uint32_t *zPtr
+ )
+{
+    unsigned int index, lastIndex;
+    uint_fast8_t borrow;
+    uint32_t wordA, wordB;
+
+    index = indexWordLo( size_words );
+    lastIndex = indexWordHi( size_words );
+    borrow = 0;
+    for (;;) {
+        wordA = aPtr[index];
+        wordB = bPtr[index];
+        zPtr[index] = wordA - wordB - borrow;
+        if ( index == lastIndex ) break;
+        borrow = borrow ? (wordA <= wordB) : (wordA < wordB);
+        index += wordIncr;
+    }
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/s_subMagsExtF80.c b/addins/SoftFloat-3e/source/s_subMagsExtF80.c
new file mode 100644
index 000000000..0c46c61a2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subMagsExtF80.c
@@ -0,0 +1,158 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+extFloat80_t
+ softfloat_subMagsExtF80(
+     uint_fast16_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast16_t uiB64,
+     uint_fast64_t uiB0,
+     bool signZ
+ )
+{
+    int_fast32_t expA;
+    uint_fast64_t sigA;
+    int_fast32_t expB;
+    uint_fast64_t sigB;
+    int_fast32_t expDiff;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+    int_fast32_t expZ;
+    uint_fast64_t sigExtra;
+    struct uint128 sig128, uiZ;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expExtF80UI64( uiA64 );
+    sigA = uiA0;
+    expB = expExtF80UI64( uiB64 );
+    sigB = uiB0;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( 0 < expDiff ) goto expABigger;
+    if ( expDiff < 0 ) goto expBBigger;
+    if ( expA == 0x7FFF ) {
+        if ( (sigA | sigB) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            goto propagateNaN;
+        }
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ64 = defaultNaNExtF80UI64;
+        uiZ0  = defaultNaNExtF80UI0;
+        goto uiZ;
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expZ = expA;
+    if ( ! expZ ) expZ = 1;
+    sigExtra = 0;
+    if ( sigB < sigA ) goto aBigger;
+    if ( sigA < sigB ) goto bBigger;
+    uiZ64 =
+        packToExtF80UI64( (softfloat_roundingMode == softfloat_round_min), 0 );
+    uiZ0 = 0;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ expBBigger:
+    if ( expB == 0x7FFF ) {
+        if ( sigB & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        uiZ64 = packToExtF80UI64( signZ ^ 1, 0x7FFF );
+        uiZ0  = UINT64_C( 0x8000000000000000 );
+        goto uiZ;
+    }
+    if ( ! expA ) {
+        ++expDiff;
+        sigExtra = 0;
+        if ( ! expDiff ) goto newlyAlignedBBigger;
+    }
+    sig128 = softfloat_shiftRightJam128( sigA, 0, -expDiff );
+    sigA = sig128.v64;
+    sigExtra = sig128.v0;
+ newlyAlignedBBigger:
+    expZ = expB;
+ bBigger:
+    signZ = ! signZ;
+    sig128 = softfloat_sub128( sigB, 0, sigA, sigExtra );
+    goto normRoundPack;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ expABigger:
+    if ( expA == 0x7FFF ) {
+        if ( sigA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) goto propagateNaN;
+        uiZ64 = uiA64;
+        uiZ0  = uiA0;
+        goto uiZ;
+    }
+    if ( ! expB ) {
+        --expDiff;
+        sigExtra = 0;
+        if ( ! expDiff ) goto newlyAlignedABigger;
+    }
+    sig128 = softfloat_shiftRightJam128( sigB, 0, expDiff );
+    sigB = sig128.v64;
+    sigExtra = sig128.v0;
+ newlyAlignedABigger:
+    expZ = expA;
+ aBigger:
+    sig128 = softfloat_sub128( sigA, 0, sigB, sigExtra );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ normRoundPack:
+    return
+        softfloat_normRoundPackToExtF80(
+            signZ, expZ, sig128.v64, sig128.v0, extF80_roundingPrecision );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNExtF80UI( uiA64, uiA0, uiB64, uiB0 );
+    uiZ64 = uiZ.v64;
+    uiZ0  = uiZ.v0;
+ uiZ:
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_subMagsF128.c b/addins/SoftFloat-3e/source/s_subMagsF128.c
new file mode 100644
index 000000000..e93543f09
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subMagsF128.c
@@ -0,0 +1,139 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float128_t
+ softfloat_subMagsF128(
+     uint_fast64_t uiA64,
+     uint_fast64_t uiA0,
+     uint_fast64_t uiB64,
+     uint_fast64_t uiB0,
+     bool signZ
+ )
+{
+    int_fast32_t expA;
+    struct uint128 sigA;
+    int_fast32_t expB;
+    struct uint128 sigB, sigZ;
+    int_fast32_t expDiff, expZ;
+    struct uint128 uiZ;
+    union ui128_f128 uZ;
+
+    expA = expF128UI64( uiA64 );
+    sigA.v64 = fracF128UI64( uiA64 );
+    sigA.v0  = uiA0;
+    expB = expF128UI64( uiB64 );
+    sigB.v64 = fracF128UI64( uiB64 );
+    sigB.v0  = uiB0;
+    sigA = softfloat_shortShiftLeft128( sigA.v64, sigA.v0, 4 );
+    sigB = softfloat_shortShiftLeft128( sigB.v64, sigB.v0, 4 );
+    expDiff = expA - expB;
+    if ( 0 < expDiff ) goto expABigger;
+    if ( expDiff < 0 ) goto expBBigger;
+    if ( expA == 0x7FFF ) {
+        if ( sigA.v64 | sigA.v0 | sigB.v64 | sigB.v0 ) goto propagateNaN;
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ.v64 = defaultNaNF128UI64;
+        uiZ.v0  = defaultNaNF128UI0;
+        goto uiZ;
+    }
+    expZ = expA;
+    if ( ! expZ ) expZ = 1;
+    if ( sigB.v64 < sigA.v64 ) goto aBigger;
+    if ( sigA.v64 < sigB.v64 ) goto bBigger;
+    if ( sigB.v0 < sigA.v0 ) goto aBigger;
+    if ( sigA.v0 < sigB.v0 ) goto bBigger;
+    uiZ.v64 =
+        packToF128UI64(
+            (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+    uiZ.v0 = 0;
+    goto uiZ;
+ expBBigger:
+    if ( expB == 0x7FFF ) {
+        if ( sigB.v64 | sigB.v0 ) goto propagateNaN;
+        uiZ.v64 = packToF128UI64( signZ ^ 1, 0x7FFF, 0 );
+        uiZ.v0  = 0;
+        goto uiZ;
+    }
+    if ( expA ) {
+        sigA.v64 |= UINT64_C( 0x0010000000000000 );
+    } else {
+        ++expDiff;
+        if ( ! expDiff ) goto newlyAlignedBBigger;
+    }
+    sigA = softfloat_shiftRightJam128( sigA.v64, sigA.v0, -expDiff );
+ newlyAlignedBBigger:
+    expZ = expB;
+    sigB.v64 |= UINT64_C( 0x0010000000000000 );
+ bBigger:
+    signZ = ! signZ;
+    sigZ = softfloat_sub128( sigB.v64, sigB.v0, sigA.v64, sigA.v0 );
+    goto normRoundPack;
+ expABigger:
+    if ( expA == 0x7FFF ) {
+        if ( sigA.v64 | sigA.v0 ) goto propagateNaN;
+        uiZ.v64 = uiA64;
+        uiZ.v0  = uiA0;
+        goto uiZ;
+    }
+    if ( expB ) {
+        sigB.v64 |= UINT64_C( 0x0010000000000000 );
+    } else {
+        --expDiff;
+        if ( ! expDiff ) goto newlyAlignedABigger;
+    }
+    sigB = softfloat_shiftRightJam128( sigB.v64, sigB.v0, expDiff );
+ newlyAlignedABigger:
+    expZ = expA;
+    sigA.v64 |= UINT64_C( 0x0010000000000000 );
+ aBigger:
+    sigZ = softfloat_sub128( sigA.v64, sigA.v0, sigB.v64, sigB.v0 );
+ normRoundPack:
+    return softfloat_normRoundPackToF128( signZ, expZ - 5, sigZ.v64, sigZ.v0 );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF128UI( uiA64, uiA0, uiB64, uiB0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_subMagsF16.c b/addins/SoftFloat-3e/source/s_subMagsF16.c
new file mode 100644
index 000000000..ae1417ea9
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subMagsF16.c
@@ -0,0 +1,187 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float16_t softfloat_subMagsF16( uint_fast16_t uiA, uint_fast16_t uiB )
+{
+    int_fast8_t expA;
+    uint_fast16_t sigA;
+    int_fast8_t expB;
+    uint_fast16_t sigB;
+    int_fast8_t expDiff;
+    uint_fast16_t uiZ;
+    int_fast16_t sigDiff;
+    bool signZ;
+    int_fast8_t shiftDist, expZ;
+    uint_fast16_t sigZ, sigX, sigY;
+    uint_fast32_t sig32Z;
+    int_fast8_t roundingMode;
+    union ui16_f16 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF16UI( uiA );
+    sigA = fracF16UI( uiA );
+    expB = expF16UI( uiB );
+    sigB = fracF16UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expA == 0x1F ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            uiZ = defaultNaNF16UI;
+            goto uiZ;
+        }
+        sigDiff = sigA - sigB;
+        if ( ! sigDiff ) {
+            uiZ =
+                packToF16UI(
+                    (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+            goto uiZ;
+        }
+        if ( expA ) --expA;
+        signZ = signF16UI( uiA );
+        if ( sigDiff < 0 ) {
+            signZ = ! signZ;
+            sigDiff = -sigDiff;
+        }
+        shiftDist = softfloat_countLeadingZeros16( sigDiff ) - 5;
+        expZ = expA - shiftDist;
+        if ( expZ < 0 ) {
+            shiftDist = expA;
+            expZ = 0;
+        }
+        sigZ = sigDiff<<shiftDist;
+        goto pack;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signF16UI( uiA );
+        if ( expDiff < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            signZ = ! signZ;
+            if ( expB == 0x1F ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF16UI( signZ, 0x1F, 0 );
+                goto uiZ;
+            }
+            if ( expDiff <= -13 ) {
+                uiZ = packToF16UI( signZ, expB, sigB );
+                if ( expA | sigA ) goto subEpsilon;
+                goto uiZ;
+            }
+            expZ = expA + 19;
+            sigX = sigB | 0x0400;
+            sigY = sigA + (expA ? 0x0400 : sigA);
+            expDiff = -expDiff;
+        } else {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            uiZ = uiA;
+            if ( expA == 0x1F ) {
+                if ( sigA ) goto propagateNaN;
+                goto uiZ;
+            }
+            if ( 13 <= expDiff ) {
+                if ( expB | sigB ) goto subEpsilon;
+                goto uiZ;
+            }
+            expZ = expB + 19;
+            sigX = sigA | 0x0400;
+            sigY = sigB + (expB ? 0x0400 : sigB);
+        }
+        sig32Z = ((uint_fast32_t) sigX<<expDiff) - sigY;
+        shiftDist = softfloat_countLeadingZeros32( sig32Z ) - 1;
+        sig32Z <<= shiftDist;
+        expZ -= shiftDist;
+        sigZ = sig32Z>>16;
+        if ( sig32Z & 0xFFFF ) {
+            sigZ |= 1;
+        } else {
+            if ( ! (sigZ & 0xF) && ((unsigned int) expZ < 0x1E) ) {
+                sigZ >>= 4;
+                goto pack;
+            }
+        }
+        return softfloat_roundPackToF16( signZ, expZ, sigZ );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF16UI( uiA, uiB );
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ subEpsilon:
+    roundingMode = softfloat_roundingMode;
+    if ( roundingMode != softfloat_round_near_even ) {
+        if (
+            (roundingMode == softfloat_round_minMag)
+                || (roundingMode
+                        == (signF16UI( uiZ ) ? softfloat_round_max
+                                : softfloat_round_min))
+        ) {
+            --uiZ;
+        }
+#ifdef SOFTFLOAT_ROUND_ODD
+        else if ( roundingMode == softfloat_round_odd ) {
+            uiZ = (uiZ - 1) | 1;
+        }
+#endif
+    }
+    softfloat_exceptionFlags |= softfloat_flag_inexact;
+    goto uiZ;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ pack:
+    uiZ = packToF16UI( signZ, expZ, sigZ );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_subMagsF32.c b/addins/SoftFloat-3e/source/s_subMagsF32.c
new file mode 100644
index 000000000..0c1f32ed6
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subMagsF32.c
@@ -0,0 +1,143 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t softfloat_subMagsF32( uint_fast32_t uiA, uint_fast32_t uiB )
+{
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    int_fast16_t expDiff;
+    uint_fast32_t uiZ;
+    int_fast32_t sigDiff;
+    bool signZ;
+    int_fast8_t shiftDist;
+    int_fast16_t expZ;
+    uint_fast32_t sigX, sigY;
+    union ui32_f32 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF32UI( uiA );
+    sigA = fracF32UI( uiA );
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expA == 0xFF ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            uiZ = defaultNaNF32UI;
+            goto uiZ;
+        }
+        sigDiff = sigA - sigB;
+        if ( ! sigDiff ) {
+            uiZ =
+                packToF32UI(
+                    (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+            goto uiZ;
+        }
+        if ( expA ) --expA;
+        signZ = signF32UI( uiA );
+        if ( sigDiff < 0 ) {
+            signZ = ! signZ;
+            sigDiff = -sigDiff;
+        }
+        shiftDist = softfloat_countLeadingZeros32( sigDiff ) - 8;
+        expZ = expA - shiftDist;
+        if ( expZ < 0 ) {
+            shiftDist = expA;
+            expZ = 0;
+        }
+        uiZ = packToF32UI( signZ, expZ, sigDiff<<shiftDist );
+        goto uiZ;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        signZ = signF32UI( uiA );
+        sigA <<= 7;
+        sigB <<= 7;
+        if ( expDiff < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            signZ = ! signZ;
+            if ( expB == 0xFF ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF32UI( signZ, 0xFF, 0 );
+                goto uiZ;
+            }
+            expZ = expB - 1;
+            sigX = sigB | 0x40000000;
+            sigY = sigA + (expA ? 0x40000000 : sigA);
+            expDiff = -expDiff;
+        } else {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            if ( expA == 0xFF ) {
+                if ( sigA ) goto propagateNaN;
+                uiZ = uiA;
+                goto uiZ;
+            }
+            expZ = expA - 1;
+            sigX = sigA | 0x40000000;
+            sigY = sigB + (expB ? 0x40000000 : sigB);
+        }
+        return
+            softfloat_normRoundPackToF32(
+                signZ, expZ, sigX - softfloat_shiftRightJam32( sigY, expDiff )
+            );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_subMagsF64.c b/addins/SoftFloat-3e/source/s_subMagsF64.c
new file mode 100644
index 000000000..a4a0ebc44
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_subMagsF64.c
@@ -0,0 +1,141 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t
+ softfloat_subMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
+{
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    int_fast16_t expDiff;
+    uint_fast64_t uiZ;
+    int_fast64_t sigDiff;
+    int_fast8_t shiftDist;
+    int_fast16_t expZ;
+    uint_fast64_t sigZ;
+    union ui64_f64 uZ;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    expDiff = expA - expB;
+    if ( ! expDiff ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        if ( expA == 0x7FF ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            softfloat_raiseFlags( softfloat_flag_invalid );
+            uiZ = defaultNaNF64UI;
+            goto uiZ;
+        }
+        sigDiff = sigA - sigB;
+        if ( ! sigDiff ) {
+            uiZ =
+                packToF64UI(
+                    (softfloat_roundingMode == softfloat_round_min), 0, 0 );
+            goto uiZ;
+        }
+        if ( expA ) --expA;
+        if ( sigDiff < 0 ) {
+            signZ = ! signZ;
+            sigDiff = -sigDiff;
+        }
+        shiftDist = softfloat_countLeadingZeros64( sigDiff ) - 11;
+        expZ = expA - shiftDist;
+        if ( expZ < 0 ) {
+            shiftDist = expA;
+            expZ = 0;
+        }
+        uiZ = packToF64UI( signZ, expZ, sigDiff<<shiftDist );
+        goto uiZ;
+    } else {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+        sigA <<= 10;
+        sigB <<= 10;
+        if ( expDiff < 0 ) {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            signZ = ! signZ;
+            if ( expB == 0x7FF ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF64UI( signZ, 0x7FF, 0 );
+                goto uiZ;
+            }
+            sigA += expA ? UINT64_C( 0x4000000000000000 ) : sigA;
+            sigA = softfloat_shiftRightJam64( sigA, -expDiff );
+            sigB |= UINT64_C( 0x4000000000000000 );
+            expZ = expB;
+            sigZ = sigB - sigA;
+        } else {
+            /*----------------------------------------------------------------
+            *----------------------------------------------------------------*/
+            if ( expA == 0x7FF ) {
+                if ( sigA ) goto propagateNaN;
+                uiZ = uiA;
+                goto uiZ;
+            }
+            sigB += expB ? UINT64_C( 0x4000000000000000 ) : sigB;
+            sigB = softfloat_shiftRightJam64( sigB, expDiff );
+            sigA |= UINT64_C( 0x4000000000000000 );
+            expZ = expA;
+            sigZ = sigA - sigB;
+        }
+        return softfloat_normRoundPackToF64( signZ, expZ - 1, sigZ );
+    }
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_tryPropagateNaNExtF80M.c b/addins/SoftFloat-3e/source/s_tryPropagateNaNExtF80M.c
new file mode 100644
index 000000000..70092fe6a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_tryPropagateNaNExtF80M.c
@@ -0,0 +1,64 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+bool
+ softfloat_tryPropagateNaNExtF80M(
+     const struct extFloat80M *aSPtr,
+     const struct extFloat80M *bSPtr,
+     struct extFloat80M *zSPtr
+ )
+{
+    uint_fast16_t ui64;
+    uint64_t ui0;
+
+    ui64 = aSPtr->signExp;
+    ui0  = aSPtr->signif;
+    if ( isNaNExtF80UI( ui64, ui0 ) ) goto propagateNaN;
+    ui64 = bSPtr->signExp;
+    ui0  = bSPtr->signif;
+    if ( isNaNExtF80UI( ui64, ui0 ) ) goto propagateNaN;
+    return false;
+ propagateNaN:
+    softfloat_propagateNaNExtF80M( aSPtr, bSPtr, zSPtr );
+    return true;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/s_tryPropagateNaNF128M.c b/addins/SoftFloat-3e/source/s_tryPropagateNaNF128M.c
new file mode 100644
index 000000000..bab04a7c0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/s_tryPropagateNaNF128M.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+
+bool
+ softfloat_tryPropagateNaNF128M(
+     const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr )
+{
+
+    if ( softfloat_isNaNF128M( aWPtr ) || softfloat_isNaNF128M( bWPtr ) ) {
+        softfloat_propagateNaNF128M( aWPtr, bWPtr, zWPtr );
+        return true;
+    }
+    return false;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/softfloat_state.c b/addins/SoftFloat-3e/source/softfloat_state.c
new file mode 100644
index 000000000..0f296654f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/softfloat_state.c
@@ -0,0 +1,52 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+#ifndef THREAD_LOCAL
+#define THREAD_LOCAL
+#endif
+
+THREAD_LOCAL uint_fast8_t softfloat_roundingMode = softfloat_round_near_even;
+THREAD_LOCAL uint_fast8_t softfloat_detectTininess = init_detectTininess;
+THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags = 0;
+
+THREAD_LOCAL uint_fast8_t extF80_roundingPrecision = 80;
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_extF80.c b/addins/SoftFloat-3e/source/ui32_to_extF80.c
new file mode 100644
index 000000000..34f79368f
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_extF80.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t ui32_to_extF80( uint32_t a )
+{
+    uint_fast16_t uiZ64;
+    int_fast8_t shiftDist;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    uiZ64 = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros32( a );
+        uiZ64 = 0x401E - shiftDist;
+        a <<= shiftDist;
+    }
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif = (uint_fast64_t) a<<32;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_extF80M.c b/addins/SoftFloat-3e/source/ui32_to_extF80M.c
new file mode 100644
index 000000000..0a0c098c0
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_extF80M.c
@@ -0,0 +1,74 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = ui32_to_extF80( a );
+
+}
+
+#else
+
+void ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint64_t sigZ;
+    int_fast8_t shiftDist;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = 0;
+    sigZ = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros32( a );
+        uiZ64 = packToExtF80UI64( 0, 0x401E - shiftDist );
+        sigZ = (uint64_t) (a<<shiftDist)<<32;
+    }
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = sigZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_f128.c b/addins/SoftFloat-3e/source/ui32_to_f128.c
new file mode 100644
index 000000000..c3ab53daf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_f128.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t ui32_to_f128( uint32_t a )
+{
+    uint_fast64_t uiZ64;
+    int_fast8_t shiftDist;
+    union ui128_f128 uZ;
+
+    uiZ64 = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros32( a ) + 17;
+        uiZ64 =
+            packToF128UI64(
+                0, 0x402E - shiftDist, (uint_fast64_t) a<<shiftDist );
+    }
+    uZ.ui.v64 = uiZ64;
+    uZ.ui.v0  = 0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_f128M.c b/addins/SoftFloat-3e/source/ui32_to_f128M.c
new file mode 100644
index 000000000..02b0434ca
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_f128M.c
@@ -0,0 +1,76 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void ui32_to_f128M( uint32_t a, float128_t *zPtr )
+{
+
+    *zPtr = ui32_to_f128( a );
+
+}
+
+#else
+
+void ui32_to_f128M( uint32_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr, uiZ96, uiZ64;
+    int_fast8_t shiftDist;
+    uint64_t normA;
+
+    zWPtr = (uint32_t *) zPtr;
+    uiZ96 = 0;
+    uiZ64 = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros32( a ) + 17;
+        normA = (uint64_t) a<<shiftDist;
+        uiZ96 = packToF128UI96( 0, 0x402E - shiftDist, normA>>32 );
+        uiZ64 = normA;
+    }
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = uiZ64;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_f16.c b/addins/SoftFloat-3e/source/ui32_to_f16.c
new file mode 100644
index 000000000..6fc377bca
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_f16.c
@@ -0,0 +1,65 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t ui32_to_f16( uint32_t a )
+{
+    int_fast8_t shiftDist;
+    union ui16_f16 u;
+    uint_fast16_t sig;
+
+    shiftDist = softfloat_countLeadingZeros32( a ) - 21;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF16UI(
+                    0, 0x18 - shiftDist, (uint_fast16_t) a<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 4;
+        sig =
+            (shiftDist < 0)
+                ? a>>(-shiftDist) | ((uint32_t) (a<<(shiftDist & 31)) != 0)
+                : (uint_fast16_t) a<<shiftDist;
+        return softfloat_roundPackToF16( 0, 0x1C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_f32.c b/addins/SoftFloat-3e/source/ui32_to_f32.c
new file mode 100644
index 000000000..d75911f2d
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_f32.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t ui32_to_f32( uint32_t a )
+{
+    union ui32_f32 uZ;
+
+    if ( ! a ) {
+        uZ.ui = 0;
+        return uZ.f;
+    }
+    if ( a & 0x80000000 ) {
+        return softfloat_roundPackToF32( 0, 0x9D, a>>1 | (a & 1) );
+    } else {
+        return softfloat_normRoundPackToF32( 0, 0x9C, a );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui32_to_f64.c b/addins/SoftFloat-3e/source/ui32_to_f64.c
new file mode 100644
index 000000000..504f96e6e
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui32_to_f64.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t ui32_to_f64( uint32_t a )
+{
+    uint_fast64_t uiZ;
+    int_fast8_t shiftDist;
+    union ui64_f64 uZ;
+
+    if ( ! a ) {
+        uiZ = 0;
+    } else {
+        shiftDist = softfloat_countLeadingZeros32( a ) + 21;
+        uiZ =
+            packToF64UI( 0, 0x432 - shiftDist, (uint_fast64_t) a<<shiftDist );
+    }
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_extF80.c b/addins/SoftFloat-3e/source/ui64_to_extF80.c
new file mode 100644
index 000000000..b0e932fed
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_extF80.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+extFloat80_t ui64_to_extF80( uint64_t a )
+{
+    uint_fast16_t uiZ64;
+    int_fast8_t shiftDist;
+    union { struct extFloat80M s; extFloat80_t f; } uZ;
+
+    uiZ64 = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros64( a );
+        uiZ64 = 0x403E - shiftDist;
+        a <<= shiftDist;
+    }
+    uZ.s.signExp = uiZ64;
+    uZ.s.signif  = a;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_extF80M.c b/addins/SoftFloat-3e/source/ui64_to_extF80M.c
new file mode 100644
index 000000000..e676d904a
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_extF80M.c
@@ -0,0 +1,74 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr )
+{
+
+    *zPtr = ui64_to_extF80( a );
+
+}
+
+#else
+
+void ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint64_t sigZ;
+    int_fast8_t shiftDist;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = 0;
+    sigZ = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros64( a );
+        uiZ64 = packToExtF80UI64( 0, 0x403E - shiftDist );
+        sigZ = a<<shiftDist;
+    }
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = sigZ;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_f128.c b/addins/SoftFloat-3e/source/ui64_to_f128.c
new file mode 100644
index 000000000..6ff6a6fcf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_f128.c
@@ -0,0 +1,68 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float128_t ui64_to_f128( uint64_t a )
+{
+    uint_fast64_t uiZ64, uiZ0;
+    int_fast8_t shiftDist;
+    struct uint128 zSig;
+    union ui128_f128 uZ;
+
+    if ( ! a ) {
+        uiZ64 = 0;
+        uiZ0  = 0;
+    } else {
+        shiftDist = softfloat_countLeadingZeros64( a ) + 49;
+        if ( 64 <= shiftDist ) {
+            zSig.v64 = a<<(shiftDist - 64);
+            zSig.v0  = 0;
+        } else {
+            zSig = softfloat_shortShiftLeft128( 0, a, shiftDist );
+        }
+        uiZ64 = packToF128UI64( 0, 0x406E - shiftDist, zSig.v64 );
+        uiZ0  = zSig.v0;
+    }
+    uZ.ui.v64 = uiZ64;
+    uZ.ui.v0  = uiZ0;
+    return uZ.f;
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_f128M.c b/addins/SoftFloat-3e/source/ui64_to_f128M.c
new file mode 100644
index 000000000..043406cc4
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_f128M.c
@@ -0,0 +1,86 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+#ifdef SOFTFLOAT_FAST_INT64
+
+void ui64_to_f128M( uint64_t a, float128_t *zPtr )
+{
+
+    *zPtr = ui64_to_f128( a );
+
+}
+
+#else
+
+void ui64_to_f128M( uint64_t a, float128_t *zPtr )
+{
+    uint32_t *zWPtr, uiZ96, uiZ64;
+    uint_fast8_t shiftDist;
+    uint32_t *ptr;
+
+    zWPtr = (uint32_t *) zPtr;
+    uiZ96 = 0;
+    uiZ64 = 0;
+    zWPtr[indexWord( 4, 1 )] = 0;
+    zWPtr[indexWord( 4, 0 )] = 0;
+    if ( a ) {
+        shiftDist = softfloat_countLeadingZeros64( a ) + 17;
+        if ( shiftDist < 32 ) {
+            ptr = zWPtr + indexMultiwordHi( 4, 3 );
+            ptr[indexWord( 3, 2 )] = 0;
+            ptr[indexWord( 3, 1 )] = a>>32;
+            ptr[indexWord( 3, 0 )] = a;
+            softfloat_shortShiftLeft96M( ptr, shiftDist, ptr );
+            ptr[indexWordHi( 3 )] =
+                packToF128UI96( 0, 0x404E - shiftDist, ptr[indexWordHi( 3 )] );
+            return;
+        }
+        a <<= shiftDist - 32;
+        uiZ96 = packToF128UI96( 0, 0x404E - shiftDist, a>>32 );
+        uiZ64 = a;
+    }
+    zWPtr[indexWord( 4, 3 )] = uiZ96;
+    zWPtr[indexWord( 4, 2 )] = uiZ64;
+
+}
+
+#endif
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_f16.c b/addins/SoftFloat-3e/source/ui64_to_f16.c
new file mode 100644
index 000000000..3d58e85cf
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_f16.c
@@ -0,0 +1,64 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float16_t ui64_to_f16( uint64_t a )
+{
+    int_fast8_t shiftDist;
+    union ui16_f16 u;
+    uint_fast16_t sig;
+
+    shiftDist = softfloat_countLeadingZeros64( a ) - 53;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF16UI(
+                    0, 0x18 - shiftDist, (uint_fast16_t) a<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 4;
+        sig =
+            (shiftDist < 0) ? softfloat_shortShiftRightJam64( a, -shiftDist )
+                : (uint_fast16_t) a<<shiftDist;
+        return softfloat_roundPackToF16( 0, 0x1C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_f32.c b/addins/SoftFloat-3e/source/ui64_to_f32.c
new file mode 100644
index 000000000..cbe3a9db2
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_f32.c
@@ -0,0 +1,64 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t ui64_to_f32( uint64_t a )
+{
+    int_fast8_t shiftDist;
+    union ui32_f32 u;
+    uint_fast32_t sig;
+
+    shiftDist = softfloat_countLeadingZeros64( a ) - 40;
+    if ( 0 <= shiftDist ) {
+        u.ui =
+            a ? packToF32UI(
+                    0, 0x95 - shiftDist, (uint_fast32_t) a<<shiftDist )
+                : 0;
+        return u.f;
+    } else {
+        shiftDist += 7;
+        sig =
+            (shiftDist < 0) ? softfloat_shortShiftRightJam64( a, -shiftDist )
+                : (uint_fast32_t) a<<shiftDist;
+        return softfloat_roundPackToF32( 0, 0x9C - shiftDist, sig );
+    }
+
+}
+
diff --git a/addins/SoftFloat-3e/source/ui64_to_f64.c b/addins/SoftFloat-3e/source/ui64_to_f64.c
new file mode 100644
index 000000000..032894378
--- /dev/null
+++ b/addins/SoftFloat-3e/source/ui64_to_f64.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
+Package, Release 3e, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t ui64_to_f64( uint64_t a )
+{
+    union ui64_f64 uZ;
+
+    if ( ! a ) {
+        uZ.ui = 0;
+        return uZ.f;
+    }
+    if ( a & UINT64_C( 0x8000000000000000 ) ) {
+        return
+            softfloat_roundPackToF64(
+                0, 0x43D, softfloat_shortShiftRightJam64( a, 1 ) );
+    } else {
+        return softfloat_normRoundPackToF64( 0, 0x43C, a );
+    }
+
+}
+
diff --git a/addins/TestFloat-3e/COPYING.txt b/addins/TestFloat-3e/COPYING.txt
new file mode 100644
index 000000000..c7443450e
--- /dev/null
+++ b/addins/TestFloat-3e/COPYING.txt
@@ -0,0 +1,37 @@
+
+License for Berkeley TestFloat Release 3e
+
+John R. Hauser
+2018 January 20
+
+The following applies to the whole of TestFloat Release 3e as well as to
+each source file individually.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions, and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors
+    may be used to endorse or promote products derived from this software
+    without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
diff --git a/addins/TestFloat-3e/README.html b/addins/TestFloat-3e/README.html
new file mode 100644
index 000000000..251408cbd
--- /dev/null
+++ b/addins/TestFloat-3e/README.html
@@ -0,0 +1,82 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley TestFloat Package Overview</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Package Overview for Berkeley TestFloat Release 3e</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+<P>
+Berkeley TestFloat is a small collection of programs for testing that an
+implementation of binary floating-point conforms to the IEEE Standard for
+Floating-Point Arithmetic.
+TestFloat is distributed in the form of C source code.
+</P>
+
+<P>
+The TestFloat package is documented in the following files in the
+<CODE>doc</CODE> subdirectory:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD><A HREF="doc/TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A></TD>
+<TD>
+General documentation for understanding and using the TestFloat programs.
+</TD>
+</TR>
+<TD><A HREF="doc/testfloat_gen.html"><NOBR><CODE>testfloat_gen.html</CODE></NOBR></A></TD>
+<TD>
+Specific documentation for the <CODE>testfloat_gen</CODE> program.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/testfloat_ver.html"><NOBR><CODE>testfloat_ver.html</CODE></NOBR></A></TD>
+<TD>
+Specific documentation for the <CODE>testfloat_ver</CODE> program.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/testfloat.html"><NOBR><CODE>testfloat.html</CODE></NOBR></A></TD>
+<TD>
+Specific documentation for the all-in-one <CODE>testfloat</CODE> program.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/testsoftfloat.html"><NOBR><CODE>testsoftfloat.html</CODE></NOBR></A></TD>
+<TD>
+Specific documentation for the <CODE>testsoftfloat</CODE> program.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/timesoftfloat.html"><NOBR><CODE>timesoftfloat.html</CODE></NOBR></A></TD>
+<TD>
+Specific documentation for the <CODE>timesoftfloat</CODE> program.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/TestFloat-source.html"><NOBR><CODE>TestFloat-source.html</CODE></NOBR></A></TD>
+<TD>
+Documentation for building TestFloat.
+</TD>
+</TR>
+<TR>
+<TD><A HREF="doc/TestFloat-history.html"><NOBR><CODE>TestFloat-history.html</CODE></NOBR></A><CODE>&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>
+History of the major changes to TestFloat.
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+Other files in the package comprise the source code for TestFloat.
+</P>
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/README.txt b/addins/TestFloat-3e/README.txt
new file mode 100644
index 000000000..f2c33db31
--- /dev/null
+++ b/addins/TestFloat-3e/README.txt
@@ -0,0 +1,26 @@
+
+Package Overview for Berkeley TestFloat Release 3e
+
+John R. Hauser
+2018 January 20
+
+Berkeley TestFloat is a small collection of programs for testing that an
+implementation of binary floating-point conforms to the IEEE Standard for
+Floating-Point Arithmetic.  TestFloat is distributed in the form of C source
+code.
+
+The TestFloat package is documented in the following files in the "doc"
+subdirectory:
+
+    TestFloat-general.html  General documentation for understanding and using
+                             the TestFloat programs.
+    testfloat_gen.html      \
+    testfloat_ver.html      | Specific documentation for each TestFloat
+    testfloat.html          |  program.
+    testsoftfloat.html      |
+    timesoftfloat.html      /
+    TestFloat-source.html   Documentation for building TestFloat.
+    TestFloat-history.html  History of the major changes to TestFloat.
+
+Other files in the package comprise the source code for TestFloat.
+
diff --git a/addins/TestFloat-3e/build/Linux-386-GCC/Makefile b/addins/TestFloat-3e/build/Linux-386-GCC/Makefile
new file mode 100644
index 000000000..440830dea
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-386-GCC/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Linux-386-GCC
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE =
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Linux-386-GCC/platform.h b/addins/TestFloat-3e/build/Linux-386-GCC/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-386-GCC/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/Makefile b/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/Makefile
new file mode 100644
index 000000000..2d0a667af
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Linux-386-SSE2-GCC
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration -msse2 -mfpmath=sse \
+    $(TESTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE =
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/platform.h b/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-386-SSE2-GCC/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile b/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile
new file mode 100644
index 000000000..37c979c46
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile
@@ -0,0 +1,353 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Linux-ARM-VFPv2-GCC
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE =
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h b/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-ARM-VFPv2-GCC/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Linux-x86_64-GCC/Makefile b/addins/TestFloat-3e/build/Linux-x86_64-GCC/Makefile
new file mode 100644
index 000000000..65ad2d89d
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-x86_64-GCC/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Linux-x86_64-GCC
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE =
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Linux-x86_64-GCC/platform.h b/addins/TestFloat-3e/build/Linux-x86_64-GCC/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Linux-x86_64-GCC/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Win32-MinGW/Makefile b/addins/TestFloat-3e/build/Win32-MinGW/Makefile
new file mode 100644
index 000000000..bfc0670b6
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win32-MinGW/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Win32-MinGW
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE = .exe
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Win32-MinGW/platform.h b/addins/TestFloat-3e/build/Win32-MinGW/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win32-MinGW/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Win32-SSE2-MinGW/Makefile b/addins/TestFloat-3e/build/Win32-SSE2-MinGW/Makefile
new file mode 100644
index 000000000..5e0acba91
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win32-SSE2-MinGW/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Win32-SSE2-MinGW
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration -msse2 -mfpmath=sse \
+    $(TESTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  gcc -std=c99 -c -Werror-implicit-function-declaration $(TESTFLOAT_OPTS) \
+    $(C_INCLUDES) -O3 -o $@
+MAKELIB = ar crs $@
+LINK = gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE = .exe
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Win32-SSE2-MinGW/platform.h b/addins/TestFloat-3e/build/Win32-SSE2-MinGW/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win32-SSE2-MinGW/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/Win64-MinGW-w64/Makefile b/addins/TestFloat-3e/build/Win64-MinGW-w64/Makefile
new file mode 100644
index 000000000..914266904
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win64-MinGW-w64/Makefile
@@ -0,0 +1,355 @@
+
+#=============================================================================
+#
+# This Makefile is part of TestFloat, Release 3e, a package of programs for
+# testing the correctness of floating-point arithmetic complying with the IEEE
+# Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+SOURCE_DIR ?= ../../source
+SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+PLATFORM ?= Win64-MinGW-w64
+
+SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+SOFTFLOAT_H = \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+  $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+TESTFLOAT_OPTS ?= \
+  -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+  -DLONG_DOUBLE_IS_EXTFLOAT80
+
+DELETE = rm -f
+C_INCLUDES = \
+  -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+COMPILE_C = \
+  x86_64-w64-mingw32-gcc -std=c99 -c -Werror-implicit-function-declaration \
+    $(TESTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+COMPILE_SLOWFLOAT_C = \
+  x86_64-w64-mingw32-gcc -std=c99 -c -Werror-implicit-function-declaration \
+    $(TESTFLOAT_OPTS) $(C_INCLUDES) -O3 -o $@
+MAKELIB = x86_64-w64-mingw32-ar crs $@
+LINK = x86_64-w64-mingw32-gcc -o $@
+OTHER_LIBS = -lm
+
+OBJ = .o
+LIB = .a
+EXE = .exe
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/Win64-MinGW-w64/platform.h b/addins/TestFloat-3e/build/Win64-MinGW-w64/platform.h
new file mode 100644
index 000000000..3ccb35e9b
--- /dev/null
+++ b/addins/TestFloat-3e/build/Win64-MinGW-w64/platform.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef __GNUC_STDC_INLINE__
+#define INLINE inline
+#else
+#define INLINE extern inline
+#endif
+
diff --git a/addins/TestFloat-3e/build/template/Makefile b/addins/TestFloat-3e/build/template/Makefile
new file mode 100644
index 000000000..f5c3b602f
--- /dev/null
+++ b/addins/TestFloat-3e/build/template/Makefile
@@ -0,0 +1,353 @@
+
+#=============================================================================
+#
+# This Makefile template is part of TestFloat, Release 3e, a package of
+# programs for testing the correctness of floating-point arithmetic complying
+# with the IEEE Standard for Floating-Point, by John R. Hauser.
+#
+# Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+# University of California.  All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+#  1. Redistributions of source code must retain the above copyright notice,
+#     this list of conditions, and the following disclaimer.
+#
+#  2. Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions, and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  3. Neither the name of the University nor the names of its contributors
+#     may be used to endorse or promote products derived from this software
+#     without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+# DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=============================================================================
+
+# Edit lines marked with `==>'.  See "TestFloat-source.html".
+
+==> SOURCE_DIR ?= ../../source
+==> SOFTFLOAT_DIR ?= ../../../SoftFloat-3e
+==> PLATFORM ?= Win32-MinGW
+
+==> SUBJ_SOURCE_DIR = $(SOURCE_DIR)/subj-C
+==> SOFTFLOAT_INCLUDE_DIR = $(SOFTFLOAT_DIR)/source/include
+
+==> SOFTFLOAT_H = \
+==>   $(SOFTFLOAT_INCLUDE_DIR)/softfloat_types.h \
+==>   $(SOFTFLOAT_INCLUDE_DIR)/softfloat.h
+==> SOFTFLOAT_LIB = $(SOFTFLOAT_DIR)/build/$(PLATFORM)/softfloat$(LIB)
+
+==> TESTFLOAT_OPTS ?= \
+==>   -DFLOAT16 -DFLOAT64 -DEXTFLOAT80 -DFLOAT128 -DFLOAT_ROUND_ODD \
+==>   -DLONG_DOUBLE_IS_EXTFLOAT80
+
+==> DELETE = rm -f
+==> C_INCLUDES = \
+==>   -I. -I$(SUBJ_SOURCE_DIR) -I$(SOURCE_DIR) -I$(SOFTFLOAT_INCLUDE_DIR)
+==> COMPILE_C = cc -c $(TESTFLOAT_OPTS) $(C_INCLUDES) -O2 -o $@
+==> COMPILE_SLOWFLOAT_C = cc -c $(TESTFLOAT_OPTS) $(C_INCLUDES) -O3 -o $@
+==> MAKELIB = ar crs $@
+==> LINK = ld -o $@
+==> OTHER_LIBS = -lm
+
+==> OBJ = .o
+==> LIB = .a
+==> EXE = .exe
+
+.PHONY: all
+all: \
+  testsoftfloat$(EXE) \
+  timesoftfloat$(EXE) \
+  testfloat_gen$(EXE) \
+  testfloat_ver$(EXE) \
+  testfloat$(EXE) \
+
+OBJS_GENCASES = \
+  genCases_ui32$(OBJ) \
+  genCases_ui64$(OBJ) \
+  genCases_i32$(OBJ) \
+  genCases_i64$(OBJ) \
+  genCases_f16$(OBJ) \
+  genCases_f32$(OBJ) \
+  genCases_f64$(OBJ) \
+  genCases_extF80$(OBJ) \
+  genCases_f128$(OBJ) \
+
+OBJS_WRITECASE = \
+  writeCase_a_ui32$(OBJ) \
+  writeCase_a_ui64$(OBJ) \
+  writeCase_a_f16$(OBJ) \
+  writeCase_ab_f16$(OBJ) \
+  writeCase_abc_f16$(OBJ) \
+  writeCase_a_f32$(OBJ) \
+  writeCase_ab_f32$(OBJ) \
+  writeCase_abc_f32$(OBJ) \
+  writeCase_a_f64$(OBJ) \
+  writeCase_ab_f64$(OBJ) \
+  writeCase_abc_f64$(OBJ) \
+  writeCase_a_extF80M$(OBJ) \
+  writeCase_ab_extF80M$(OBJ) \
+  writeCase_a_f128M$(OBJ) \
+  writeCase_ab_f128M$(OBJ) \
+  writeCase_abc_f128M$(OBJ) \
+  writeCase_z_bool$(OBJ) \
+  writeCase_z_ui32$(OBJ) \
+  writeCase_z_ui64$(OBJ) \
+  writeCase_z_f16$(OBJ) \
+  writeCase_z_f32$(OBJ) \
+  writeCase_z_f64$(OBJ) \
+  writeCase_z_extF80M$(OBJ) \
+  writeCase_z_f128M$(OBJ) \
+
+OBJS_TEST = \
+  test_a_ui32_z_f16$(OBJ) \
+  test_a_ui32_z_f32$(OBJ) \
+  test_a_ui32_z_f64$(OBJ) \
+  test_a_ui32_z_extF80$(OBJ) \
+  test_a_ui32_z_f128$(OBJ) \
+  test_a_ui64_z_f16$(OBJ) \
+  test_a_ui64_z_f32$(OBJ) \
+  test_a_ui64_z_f64$(OBJ) \
+  test_a_ui64_z_extF80$(OBJ) \
+  test_a_ui64_z_f128$(OBJ) \
+  test_a_i32_z_f16$(OBJ) \
+  test_a_i32_z_f32$(OBJ) \
+  test_a_i32_z_f64$(OBJ) \
+  test_a_i32_z_extF80$(OBJ) \
+  test_a_i32_z_f128$(OBJ) \
+  test_a_i64_z_f16$(OBJ) \
+  test_a_i64_z_f32$(OBJ) \
+  test_a_i64_z_f64$(OBJ) \
+  test_a_i64_z_extF80$(OBJ) \
+  test_a_i64_z_f128$(OBJ) \
+  test_a_f16_z_ui32_rx$(OBJ) \
+  test_a_f16_z_ui64_rx$(OBJ) \
+  test_a_f16_z_i32_rx$(OBJ) \
+  test_a_f16_z_i64_rx$(OBJ) \
+  test_a_f16_z_ui32_x$(OBJ) \
+  test_a_f16_z_ui64_x$(OBJ) \
+  test_a_f16_z_i32_x$(OBJ) \
+  test_a_f16_z_i64_x$(OBJ) \
+  test_a_f16_z_f32$(OBJ) \
+  test_a_f16_z_f64$(OBJ) \
+  test_a_f16_z_extF80$(OBJ) \
+  test_a_f16_z_f128$(OBJ) \
+  test_az_f16$(OBJ) \
+  test_az_f16_rx$(OBJ) \
+  test_abz_f16$(OBJ) \
+  test_abcz_f16$(OBJ) \
+  test_ab_f16_z_bool$(OBJ) \
+  test_a_f32_z_ui32_rx$(OBJ) \
+  test_a_f32_z_ui64_rx$(OBJ) \
+  test_a_f32_z_i32_rx$(OBJ) \
+  test_a_f32_z_i64_rx$(OBJ) \
+  test_a_f32_z_ui32_x$(OBJ) \
+  test_a_f32_z_ui64_x$(OBJ) \
+  test_a_f32_z_i32_x$(OBJ) \
+  test_a_f32_z_i64_x$(OBJ) \
+  test_a_f32_z_f16$(OBJ) \
+  test_a_f32_z_f64$(OBJ) \
+  test_a_f32_z_extF80$(OBJ) \
+  test_a_f32_z_f128$(OBJ) \
+  test_az_f32$(OBJ) \
+  test_az_f32_rx$(OBJ) \
+  test_abz_f32$(OBJ) \
+  test_abcz_f32$(OBJ) \
+  test_ab_f32_z_bool$(OBJ) \
+  test_a_f64_z_ui32_rx$(OBJ) \
+  test_a_f64_z_ui64_rx$(OBJ) \
+  test_a_f64_z_i32_rx$(OBJ) \
+  test_a_f64_z_i64_rx$(OBJ) \
+  test_a_f64_z_ui32_x$(OBJ) \
+  test_a_f64_z_ui64_x$(OBJ) \
+  test_a_f64_z_i32_x$(OBJ) \
+  test_a_f64_z_i64_x$(OBJ) \
+  test_a_f64_z_f16$(OBJ) \
+  test_a_f64_z_f32$(OBJ) \
+  test_a_f64_z_extF80$(OBJ) \
+  test_a_f64_z_f128$(OBJ) \
+  test_az_f64$(OBJ) \
+  test_az_f64_rx$(OBJ) \
+  test_abz_f64$(OBJ) \
+  test_abcz_f64$(OBJ) \
+  test_ab_f64_z_bool$(OBJ) \
+  test_a_extF80_z_ui32_rx$(OBJ) \
+  test_a_extF80_z_ui64_rx$(OBJ) \
+  test_a_extF80_z_i32_rx$(OBJ) \
+  test_a_extF80_z_i64_rx$(OBJ) \
+  test_a_extF80_z_ui32_x$(OBJ) \
+  test_a_extF80_z_ui64_x$(OBJ) \
+  test_a_extF80_z_i32_x$(OBJ) \
+  test_a_extF80_z_i64_x$(OBJ) \
+  test_a_extF80_z_f16$(OBJ) \
+  test_a_extF80_z_f32$(OBJ) \
+  test_a_extF80_z_f64$(OBJ) \
+  test_a_extF80_z_f128$(OBJ) \
+  test_az_extF80$(OBJ) \
+  test_az_extF80_rx$(OBJ) \
+  test_abz_extF80$(OBJ) \
+  test_ab_extF80_z_bool$(OBJ) \
+  test_a_f128_z_ui32_rx$(OBJ) \
+  test_a_f128_z_ui64_rx$(OBJ) \
+  test_a_f128_z_i32_rx$(OBJ) \
+  test_a_f128_z_i64_rx$(OBJ) \
+  test_a_f128_z_ui32_x$(OBJ) \
+  test_a_f128_z_ui64_x$(OBJ) \
+  test_a_f128_z_i32_x$(OBJ) \
+  test_a_f128_z_i64_x$(OBJ) \
+  test_a_f128_z_f16$(OBJ) \
+  test_a_f128_z_f32$(OBJ) \
+  test_a_f128_z_f64$(OBJ) \
+  test_a_f128_z_extF80$(OBJ) \
+  test_az_f128$(OBJ) \
+  test_az_f128_rx$(OBJ) \
+  test_abz_f128$(OBJ) \
+  test_abcz_f128$(OBJ) \
+  test_ab_f128_z_bool$(OBJ) \
+
+OBJS_LIB = \
+  uint128_inline$(OBJ) \
+  uint128$(OBJ) \
+  fail$(OBJ) \
+  functions_common$(OBJ) \
+  functionInfos$(OBJ) \
+  standardFunctionInfos$(OBJ) \
+  random$(OBJ) \
+  genCases_common$(OBJ) \
+  $(OBJS_GENCASES) \
+  genCases_writeTestsTotal$(OBJ) \
+  verCases_inline$(OBJ) \
+  verCases_common$(OBJ) \
+  verCases_writeFunctionName$(OBJ) \
+  readHex$(OBJ) \
+  writeHex$(OBJ) \
+  $(OBJS_WRITECASE) \
+  testLoops_common$(OBJ) \
+  $(OBJS_TEST) \
+
+uint128$(OBJ): $(SOURCE_DIR)/uint128.h
+fail$(OBJ): $(SOURCE_DIR)/fail.h
+functions_common$(OBJ): $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h
+functionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+standardFunctionInfos$(OBJ): $(SOURCE_DIR)/functions.h
+random$(OBJ): $(SOURCE_DIR)/random.h
+genCases_common$(OBJ): $(SOURCE_DIR)/fail.h $(SOURCE_DIR)/genCases.h
+$(OBJS_GENCASES): \
+  $(SOURCE_DIR)/random.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h
+genCases_f128$(OBJ): $(SOURCE_DIR)/uint128.h
+genCases_writeTestsTotal$(OBJ): $(SOURCE_DIR)/genCases.h
+verCases_common$(OBJ): $(SOURCE_DIR)/verCases.h
+verCases_writeFunctionName$(OBJ): $(SOURCE_DIR)/verCases.h
+readHex$(OBJ): $(SOURCE_DIR)/readHex.h
+writeHex$(OBJ): $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h
+$(OBJS_WRITECASE): \
+  $(SOFTFLOAT_H) $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/writeCase.h
+testLoops_common$(OBJ): $(SOURCE_DIR)/testLoops.h
+$(OBJS_TEST): \
+  $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) $(SOURCE_DIR)/genCases.h \
+  $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/testLoops.h
+$(OBJS_LIB): %$(OBJ): platform.h $(SOURCE_DIR)/%.c
+	$(COMPILE_C) $(SOURCE_DIR)/$*.c
+testfloat$(LIB): $(OBJS_LIB)
+	$(MAKELIB) $^
+
+OBJS_TESTSOFTFLOAT = slowfloat$(OBJ) testsoftfloat$(OBJ)
+
+slowfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/slowfloat.c
+	$(COMPILE_SLOWFLOAT_C) $(SOURCE_DIR)/slowfloat.c
+testsoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/slowfloat.h $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testsoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testsoftfloat.c
+
+testsoftfloat$(EXE): $(OBJS_TESTSOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TIMESOFTFLOAT = timesoftfloat$(OBJ)
+
+timesoftfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/timesoftfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/timesoftfloat.c
+
+timesoftfloat$(EXE): $(OBJS_TIMESOFTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_GEN = genLoops$(OBJ) testfloat_gen$(OBJ)
+
+genLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/writeHex.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/genLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/genLoops.c
+testfloat_gen$(OBJ): \
+  $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) $(SOURCE_DIR)/functions.h \
+  $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/genLoops.h \
+  $(SOURCE_DIR)/testfloat_gen.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_gen.c
+
+testfloat_gen$(EXE): $(OBJS_TESTFLOAT_GEN) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT_VER = verLoops$(OBJ) testfloat_ver$(OBJ)
+
+verLoops$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/readHex.h $(SOURCE_DIR)/verCases.h $(SOURCE_DIR)/writeCase.h \
+  $(SOURCE_DIR)/verLoops.h $(SOURCE_DIR)/verLoops.c
+	$(COMPILE_C) $(SOURCE_DIR)/verLoops.c
+testfloat_ver$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/writeCase.h $(SOURCE_DIR)/verLoops.h \
+  $(SOURCE_DIR)/testfloat_ver.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat_ver.c
+
+testfloat_ver$(EXE): $(OBJS_TESTFLOAT_VER) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+OBJS_TESTFLOAT = subjfloat$(OBJ) subjfloat_functions$(OBJ) testfloat$(OBJ)
+
+subjfloat$(OBJ): \
+  platform.h $(SOFTFLOAT_H) $(SUBJ_SOURCE_DIR)/subjfloat_config.h \
+  $(SOURCE_DIR)/subjfloat.h $(SUBJ_SOURCE_DIR)/subjfloat.c
+	$(COMPILE_C) $(SUBJ_SOURCE_DIR)/subjfloat.c
+subjfloat_functions$(OBJ): \
+  platform.h $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/subjfloat_functions.c
+	$(COMPILE_C) $(SOURCE_DIR)/subjfloat_functions.c
+testfloat$(OBJ): \
+  platform.h $(SOURCE_DIR)/uint128.h $(SOURCE_DIR)/fail.h $(SOFTFLOAT_H) \
+  $(SUBJ_SOURCE_DIR)/subjfloat_config.h $(SOURCE_DIR)/subjfloat.h \
+  $(SOURCE_DIR)/functions.h $(SOURCE_DIR)/genCases.h $(SOURCE_DIR)/verCases.h \
+  $(SOURCE_DIR)/testLoops.h $(SOURCE_DIR)/testfloat.c
+	$(COMPILE_C) $(SOURCE_DIR)/testfloat.c
+
+testfloat$(EXE): $(OBJS_TESTFLOAT) testfloat$(LIB) $(SOFTFLOAT_LIB)
+	$(LINK) $^ $(OTHER_LIBS)
+
+.PHONY: clean
+clean:
+	$(DELETE) $(OBJS_LIB) testfloat$(LIB)
+	$(DELETE) $(OBJS_TESTSOFTFLOAT) testsoftfloat$(EXE)
+	$(DELETE) $(OBJS_TIMESOFTFLOAT) timesoftfloat$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_GEN) testfloat_gen$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT_VER) testfloat_ver$(EXE)
+	$(DELETE) $(OBJS_TESTFLOAT) testfloat$(EXE)
+
diff --git a/addins/TestFloat-3e/build/template/platform.h b/addins/TestFloat-3e/build/template/platform.h
new file mode 100644
index 000000000..29cb8cc0c
--- /dev/null
+++ b/addins/TestFloat-3e/build/template/platform.h
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C header template is part of TestFloat, Release 3e, a package of programs
+for testing the correctness of floating-point arithmetic complying with the
+IEEE Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+// Edit lines marked with `==>'.  See "TestFloat-source.html".
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define LITTLEENDIAN 1
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define INLINE inline
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+==> #define THREAD_LOCAL _Thread_local
+
diff --git a/addins/TestFloat-3e/doc/TestFloat-general.html b/addins/TestFloat-3e/doc/TestFloat-general.html
new file mode 100644
index 000000000..730edc4be
--- /dev/null
+++ b/addins/TestFloat-3e/doc/TestFloat-general.html
@@ -0,0 +1,1148 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley TestFloat General Documentation</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: General Documentation</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Contents</H2>
+
+<BLOCKQUOTE>
+<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
+<COL WIDTH=25>
+<COL WIDTH=*>
+<TR><TD COLSPAN=2>1. Introduction</TD></TR>
+<TR><TD COLSPAN=2>2. Limitations</TD></TR>
+<TR><TD COLSPAN=2>3. Acknowledgments and License</TD></TR>
+<TR><TD COLSPAN=2>4. What TestFloat Does</TD></TR>
+<TR><TD COLSPAN=2>5. Executing TestFloat</TD></TR>
+<TR><TD COLSPAN=2>6. Operations Tested by TestFloat</TD></TR>
+<TR><TD></TD><TD>6.1. Conversion Operations</TD></TR>
+<TR><TD></TD><TD>6.2. Basic Arithmetic Operations</TD></TR>
+<TR><TD></TD><TD>6.3. Fused Multiply-Add Operations</TD></TR>
+<TR><TD></TD><TD>6.4. Remainder Operations</TD></TR>
+<TR><TD></TD><TD>6.5. Round-to-Integer Operations</TD></TR>
+<TR><TD></TD><TD>6.6. Comparison Operations</TD></TR>
+<TR><TD COLSPAN=2>7. Interpreting TestFloat Output</TD></TR>
+<TR>
+  <TD COLSPAN=2>8. Variations Allowed by the IEEE Floating-Point Standard</TD>
+</TR>
+<TR><TD></TD><TD>8.1. Underflow</TD></TR>
+<TR><TD></TD><TD>8.2. NaNs</TD></TR>
+<TR><TD></TD><TD>8.3. Conversions to Integer</TD></TR>
+<TR><TD COLSPAN=2>9. Contact Information</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+
+
+<H2>1. Introduction</H2>
+
+<P>
+Berkeley TestFloat is a small collection of programs for testing that an
+implementation of binary floating-point conforms to the IEEE Standard for
+Floating-Point Arithmetic.
+All operations required by the original 1985 version of the IEEE Floating-Point
+Standard can be tested, except for conversions to and from decimal.
+With the current release, the following binary formats can be tested:
+<NOBR>16-bit</NOBR> half-precision, <NOBR>32-bit</NOBR> single-precision,
+<NOBR>64-bit</NOBR> double-precision, <NOBR>80-bit</NOBR>
+double-extended-precision, and/or <NOBR>128-bit</NOBR> quadruple-precision.
+TestFloat cannot test decimal floating-point.
+</P>
+
+<P>
+Included in the TestFloat package are the <CODE>testsoftfloat</CODE> and
+<CODE>timesoftfloat</CODE> programs for testing the Berkeley SoftFloat software
+implementation of floating-point and for measuring its speed.
+Information about SoftFloat can be found at the SoftFloat Web page,
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+The <CODE>testsoftfloat</CODE> and <CODE>timesoftfloat</CODE> programs are
+expected to be of interest only to people compiling the SoftFloat sources.
+</P>
+
+<P>
+This document explains how to use the TestFloat programs.
+It does not attempt to define or explain much of the IEEE Floating-Point
+Standard.
+Details about the standard are available elsewhere.
+</P>
+
+<P>
+The current version of TestFloat is <NOBR>Release 3e</NOBR>.
+This version differs from earlier releases 3b through 3d in only minor ways.
+Compared to the original <NOBR>Release 3</NOBR>:
+<UL>
+<LI>
+<NOBR>Release 3b</NOBR> added the ability to test the <NOBR>16-bit</NOBR>
+half-precision format.
+<LI>
+<NOBR>Release 3c</NOBR> added the ability to test a rarely used rounding mode,
+<I>round to odd</I>, also known as <I>jamming</I>.
+<LI>
+<NOBR>Release 3d</NOBR> modified the code for testing C arithmetic to
+potentially include testing newer library functions <CODE>sqrtf</CODE>,
+<CODE>sqrtl</CODE>, <CODE>fmaf</CODE>, <CODE>fma</CODE>, and <CODE>fmal</CODE>.
+</UL>
+This release adds a few more small improvements, including modifying the
+expected behavior of rounding mode <CODE>odd</CODE> and fixing a minor bug in
+the all-in-one <CODE>testfloat</CODE> program.
+</P>
+
+<P>
+Compared to Release 2c and earlier, the set of TestFloat programs, as well as
+the programs&rsquo; arguments and behavior, changed some with
+<NOBR>Release 3</NOBR>.
+For more about the evolution of TestFloat releases, see
+<A HREF="TestFloat-history.html"><NOBR><CODE>TestFloat-history.html</CODE></NOBR></A>.
+</P>
+
+
+<H2>2. Limitations</H2>
+
+<P>
+TestFloat output is not always easily interpreted.
+Detailed knowledge of the IEEE Floating-Point Standard and its vagaries is
+needed to use TestFloat responsibly.
+</P>
+
+<P>
+TestFloat performs relatively simple tests designed to check the fundamental
+soundness of the floating-point under test.
+TestFloat may also at times manage to find rarer and more subtle bugs, but it
+will probably only find such bugs by chance.
+Software that purposefully seeks out various kinds of subtle floating-point
+bugs can be found through links posted on the TestFloat Web page,
+<A HREF="http://www.jhauser.us/arithmetic/TestFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/TestFloat.html</CODE></NOBR></A>.
+</P>
+
+
+<H2>3. Acknowledgments and License</H2>
+
+<P>
+The TestFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
+<NOBR>Release 3</NOBR> of TestFloat was a completely new implementation
+supplanting earlier releases.
+The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
+done in the employ of the University of California, Berkeley, within the
+Department of Electrical Engineering and Computer Sciences, first for the
+Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
+The work was officially overseen by Prof. Krste Asanovic, with funding provided
+by these sources:
+<BLOCKQUOTE>
+<TABLE>
+<COL>
+<COL WIDTH=10>
+<COL>
+<TR>
+<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
+(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
+NVIDIA, Oracle, and Samsung.
+</TD>
+</TR>
+<TR>
+<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
+ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
+Oracle, and Samsung.
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The following applies to the whole of TestFloat <NOBR>Release 3e</NOBR> as well
+as to each source file individually.
+</P>
+
+<P>
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.
+All rights reserved.
+</P>
+
+<P>
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+<OL>
+
+<LI>
+<P>
+Redistributions of source code must retain the above copyright notice, this
+list of conditions, and the following disclaimer.
+</P>
+
+<LI>
+<P>
+Redistributions in binary form must reproduce the above copyright notice, this
+list of conditions, and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+</P>
+
+<LI>
+<P>
+Neither the name of the University nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific
+prior written permission.
+</P>
+
+</OL>
+</P>
+
+<P>
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS &ldquo;AS IS&rdquo;,
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.
+IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+</P>
+
+
+<H2>4. What TestFloat Does</H2>
+
+<P>
+TestFloat is designed to test a floating-point implementation by comparing its
+behavior with that of TestFloat&rsquo;s own internal floating-point implemented
+in software.
+For each operation to be tested, the TestFloat programs can generate a large
+number of test cases, made up of simple pattern tests intermixed with weighted
+random inputs.
+The cases generated should be adequate for testing carry chain propagations,
+and the rounding of addition, subtraction, multiplication, and simple
+operations like conversions.
+TestFloat makes a point of checking all boundary cases of the arithmetic,
+including underflows, overflows, invalid operations, subnormal inputs, zeros
+(positive and negative), infinities, and NaNs.
+For the interesting operations like addition and multiplication, millions of
+test cases may be checked.
+</P>
+
+<P>
+TestFloat is not remarkably good at testing difficult rounding cases for
+division and square root.
+It also makes no attempt to find bugs specific to SRT division and the like
+(such as the infamous Pentium division bug).
+Software that tests for such failures can be found through links on the
+TestFloat Web page,
+<A HREF="http://www.jhauser.us/arithmetic/TestFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/TestFloat.html</CODE></NOBR></A>.
+</P>
+
+<P>
+NOTE!<BR>
+It is the responsibility of the user to verify that the discrepancies TestFloat
+finds actually represent faults in the implementation being tested.
+Advice to help with this task is provided later in this document.
+Furthermore, even if TestFloat finds no fault with a floating-point
+implementation, that in no way guarantees that the implementation is bug-free.
+</P>
+
+<P>
+For each operation, TestFloat can test all five rounding modes defined by the
+IEEE Floating-Point Standard, plus possibly a sixth mode, <I>round to odd</I>
+(depending on the options selected when TestFloat was built).
+TestFloat verifies not only that the numeric results of an operation are
+correct, but also that the proper floating-point exception flags are raised.
+All five exception flags are tested, including the <I>inexact</I> flag.
+TestFloat does not attempt to verify that the floating-point exception flags
+are actually implemented as sticky flags.
+</P>
+
+<P>
+For the <NOBR>80-bit</NOBR> double-extended-precision format, TestFloat can
+test the addition, subtraction, multiplication, division, and square root
+operations at all three of the standard rounding precisions.
+The rounding precision can be set to <NOBR>32 bits</NOBR>, equivalent to
+single-precision, to <NOBR>64 bits</NOBR>, equivalent to double-precision, or
+to the full <NOBR>80 bits</NOBR> of the double-extended-precision.
+Rounding precision control can be applied only to the double-extended-precision
+format and only for the five basic arithmetic operations:  addition,
+subtraction, multiplication, division, and square root.
+Other operations can be tested only at full precision.
+</P>
+
+<P>
+As a rule, TestFloat is not particular about the bit patterns of NaNs that
+appear as operation results.
+Any NaN is considered as good a result as another.
+This laxness can be overridden so that TestFloat checks for particular bit
+patterns within NaN results.
+See <NOBR>section 8</NOBR> below, <I>Variations Allowed by the IEEE
+Floating-Point Standard</I>, plus the <CODE>-checkNaNs</CODE> and
+<CODE>-checkInvInts</CODE> options documented for programs
+<CODE>testfloat_ver</CODE> and <CODE>testfloat</CODE>.
+</P>
+
+<P>
+TestFloat normally compares an implementation of floating-point against the
+Berkeley SoftFloat software implementation of floating-point, also created by
+me.
+The SoftFloat functions are linked into each TestFloat program&rsquo;s
+executable.
+Information about SoftFloat can be found at the Web page
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+</P>
+
+<P>
+For testing SoftFloat itself, the TestFloat package includes a
+<CODE>testsoftfloat</CODE> program that compares SoftFloat&rsquo;s
+floating-point against <EM>another</EM> software floating-point implementation.
+The second software floating-point is simpler and slower than SoftFloat, and is
+completely independent of SoftFloat.
+Although the second software floating-point cannot be guaranteed to be
+bug-free, the chance that it would mimic any of SoftFloat&rsquo;s bugs is low.
+Consequently, an error in one or the other floating-point version should appear
+as an unexpected difference between the two implementations.
+Note that testing SoftFloat should be necessary only when compiling a new
+TestFloat executable or when compiling SoftFloat for some other reason.
+</P>
+
+
+<H2>5. Executing TestFloat</H2>
+
+<P>
+The TestFloat package consists of five programs, all intended to be executed
+from a command-line interpreter:
+<BLOCKQUOTE>
+<TABLE>
+<TR>
+<TD>
+<A HREF="testfloat_gen.html"><CODE>testfloat_gen</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE>
+</TD>
+<TD>
+Generates test cases for a specific floating-point operation.
+</TD>
+</TR>
+<TR>
+<TD>
+<A HREF="testfloat_ver.html"><CODE>testfloat_ver</CODE></A>
+</TD>
+<TD>
+Verifies whether the results from executing a floating-point operation are as
+expected.
+</TD>
+</TR>
+<TR>
+<TD>
+<A HREF="testfloat.html"><CODE>testfloat</CODE></A>
+</TD>
+<TD>
+An all-in-one program that generates test cases, executes floating-point
+operations, and verifies whether the results match expectations.
+</TD>
+</TR>
+<TR>
+<TD>
+<A HREF="testsoftfloat.html"><CODE>testsoftfloat</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE>
+</TD>
+<TD>
+Like <CODE>testfloat</CODE>, but for testing SoftFloat.
+</TD>
+</TR>
+<TR>
+<TD>
+<A HREF="timesoftfloat.html"><CODE>timesoftfloat</CODE></A><CODE>&nbsp;&nbsp;&nbsp;</CODE>
+</TD>
+<TD>
+A program for measuring the speed of SoftFloat (included in the TestFloat
+package for convenience).
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+Each program has its own page of documentation that can be opened through the
+links in the table above.
+</P>
+
+<P>
+To test a floating-point implementation other than SoftFloat, one of three
+different methods can be used.
+The first method pipes output from <CODE>testfloat_gen</CODE> to a program
+that:
+<NOBR>(a) reads</NOBR> the incoming test cases, <NOBR>(b) invokes</NOBR> the
+floating-point operation being tested, and <NOBR>(c) writes</NOBR> the
+operation results to output.
+These results can then be piped to <CODE>testfloat_ver</CODE> to be checked for
+correctness.
+Assuming a vertical bar (<CODE>|</CODE>) indicates a pipe between programs, the
+complete process could be written as a single command like so:
+<BLOCKQUOTE>
+<PRE>
+testfloat_gen ... &lt;<I>type</I>&gt; | &lt;<I>program-that-invokes-op</I>&gt; | testfloat_ver ... &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+The program in the middle is not supplied by TestFloat but must be created
+independently.
+If for some reason this program cannot take command-line arguments, the
+<CODE>-prefix</CODE> option of <CODE>testfloat_gen</CODE> can communicate
+parameters through the pipe.
+</P>
+
+<P>
+A second method for running TestFloat is similar but has
+<CODE>testfloat_gen</CODE> supply not only the test inputs but also the
+expected results for each case.
+With this additional information, the job done by <CODE>testfloat_ver</CODE>
+can be folded into the invoking program to give the following command:
+<BLOCKQUOTE>
+<PRE>
+testfloat_gen ... &lt;<I>function</I>&gt; | &lt;<I>program-that-invokes-op-and-compares-results</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Again, the program that actually invokes the floating-point operation is not
+supplied by TestFloat but must be created independently.
+Depending on circumstance, it may be preferable either to let
+<CODE>testfloat_ver</CODE> check and report suspected errors (first method) or
+to include this step in the invoking program (second method).
+</P>
+
+<P>
+The third way to use TestFloat is the all-in-one <CODE>testfloat</CODE>
+program.
+This program can perform all the steps of creating test cases, invoking the
+floating-point operation, checking the results, and reporting suspected errors.
+However, for this to be possible, <CODE>testfloat</CODE> must be compiled to
+contain the method for invoking the floating-point operations to test.
+Each build of <CODE>testfloat</CODE> is therefore capable of testing
+<EM>only</EM> the floating-point implementation it was built to invoke.
+To test a new implementation of floating-point, a new <CODE>testfloat</CODE>
+must be created, linked to that specific implementation.
+By comparison, the <CODE>testfloat_gen</CODE> and <CODE>testfloat_ver</CODE>
+programs are entirely generic;
+one instance is usable for testing any floating-point implementation, because
+implementation-specific details are segregated in the custom program that
+follows <CODE>testfloat_gen</CODE>.
+</P>
+
+<P>
+Program <CODE>testsoftfloat</CODE> is another all-in-one program specifically
+for testing SoftFloat.
+</P>
+
+<P>
+Programs <CODE>testfloat_ver</CODE>, <CODE>testfloat</CODE>, and
+<CODE>testsoftfloat</CODE> all report status and error information in a common
+way.
+As it executes, each of these programs writes status information to the
+standard error output, which should be the screen by default.
+In order for this status to be displayed properly, the standard error stream
+should not be redirected to a file.
+Any discrepancies that are found are written to the standard output stream,
+which is easily redirected to a file if desired.
+Unless redirected, reported errors will appear intermixed with the ongoing
+status information in the output.
+</P>
+
+
+<H2>6. Operations Tested by TestFloat</H2>
+
+<P>
+TestFloat can test all operations required by the original 1985 IEEE
+Floating-Point Standard except for conversions to and from decimal.
+These operations are:
+<UL>
+<LI>
+conversions among the supported floating-point formats, and also between
+integers (<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR>, signed and unsigned) and
+any of the floating-point formats;
+<LI>
+for each floating-point format, the usual addition, subtraction,
+multiplication, division, and square root operations;
+<LI>
+for each format, the floating-point remainder operation defined by the IEEE
+Standard;
+<LI>
+for each format, a &ldquo;round to integer&rdquo; operation that rounds to the
+nearest integer value in the same format; and
+<LI>
+comparisons between two values in the same floating-point format.
+</UL>
+In addition, TestFloat can also test
+<UL>
+<LI>
+for each floating-point format except <NOBR>80-bit</NOBR>
+double-extended-precision, the fused multiply-add operation defined by the 2008
+IEEE Standard.
+</UL>
+</P>
+
+<P>
+More information about all these operations is given below.
+In the operation names used by TestFloat, <NOBR>16-bit</NOBR> half-precision is
+called <CODE>f16</CODE>, <NOBR>32-bit</NOBR> single-precision is
+<CODE>f32</CODE>, <NOBR>64-bit</NOBR> double-precision is <CODE>f64</CODE>,
+<NOBR>80-bit</NOBR> double-extended-precision is <CODE>extF80</CODE>, and
+<NOBR>128-bit</NOBR> quadruple-precision is <CODE>f128</CODE>.
+TestFloat generally uses the same names for operations as Berkeley SoftFloat,
+except that TestFloat&rsquo;s names never include the <CODE>M</CODE> that
+SoftFloat uses to indicate that values are passed through pointers.
+</P>
+
+<H3>6.1. Conversion Operations</H3>
+
+<P>
+All conversions among the floating-point formats and all conversions between a
+floating-point format and <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> integers
+can be tested.
+The conversion operations are:
+<BLOCKQUOTE>
+<PRE>
+ui32_to_f16      ui64_to_f16      i32_to_f16       i64_to_f16
+ui32_to_f32      ui64_to_f32      i32_to_f32       i64_to_f32
+ui32_to_f64      ui64_to_f64      i32_to_f64       i64_to_f64
+ui32_to_extF80   ui64_to_extF80   i32_to_extF80    i64_to_extF80
+ui32_to_f128     ui64_to_f128     i32_to_f128      i64_to_f128
+
+f16_to_ui32      f32_to_ui32      f64_to_ui32      extF80_to_ui32    f128_to_ui32
+f16_to_ui64      f32_to_ui64      f64_to_ui64      extF80_to_ui64    f128_to_ui64
+f16_to_i32       f32_to_i32       f64_to_i32       extF80_to_i32     f128_to_i32
+f16_to_i64       f32_to_i64       f64_to_i64       extF80_to_i64     f128_to_i64
+
+f16_to_f32       f32_to_f16       f64_to_f16       extF80_to_f16     f128_to_f16
+f16_to_f64       f32_to_f64       f64_to_f32       extF80_to_f32     f128_to_f32
+f16_to_extF80    f32_to_extF80    f64_to_extF80    extF80_to_f64     f128_to_f64
+f16_to_f128      f32_to_f128      f64_to_f128      extF80_to_f128    f128_to_extF80
+</PRE>
+</BLOCKQUOTE>
+Abbreviations <CODE>ui32</CODE> and <CODE>ui64</CODE> indicate
+<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> unsigned integer types, while
+<CODE>i32</CODE> and <CODE>i64</CODE> indicate their signed counterparts.
+These conversions all round according to the current rounding mode as relevant.
+Conversions from a smaller to a larger floating-point format are always exact
+and so require no rounding.
+Likewise, conversions from <NOBR>32-bit</NOBR> integers to <NOBR>64-bit</NOBR>
+double-precision or to any larger floating-point format are also exact, as are
+conversions from <NOBR>64-bit</NOBR> integers to <NOBR>80-bit</NOBR>
+double-extended-precision and <NOBR>128-bit</NOBR> quadruple-precision.
+</P>
+
+<P>
+For the all-in-one <CODE>testfloat</CODE> program, this list of conversion
+operations requires amendment.
+For <CODE>testfloat</CODE> only, conversions to an integer type have names that
+explicitly specify the rounding mode and treatment of inexactness.
+Thus, instead of
+<BLOCKQUOTE>
+<PRE>
+&lt;<I>float</I>&gt;_to_&lt;<I>int</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+as listed above, operations converting to integer type have names of these
+forms:
+<BLOCKQUOTE>
+<PRE>
+&lt;<I>float</I>&gt;_to_&lt;<I>int</I>&gt;_r_&lt;<I>round</I>&gt;
+&lt;<I>float</I>&gt;_to_&lt;<I>int</I>&gt;_rx_&lt;<I>round</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+The <CODE>&lt;<I>round</I>&gt;</CODE> component is one of
+&lsquo;<CODE>near_even</CODE>&rsquo;, &lsquo;<CODE>near_maxMag</CODE>&rsquo;,
+&lsquo;<CODE>minMag</CODE>&rsquo;, &lsquo;<CODE>min</CODE>&rsquo;, or
+&lsquo;<CODE>max</CODE>&rsquo;, choosing the rounding mode.
+Any other indication of rounding mode is ignored.
+The operations with &lsquo;<CODE>_r_</CODE>&rsquo; in their names never raise
+the <I>inexact</I> exception, while those with &lsquo;<CODE>_rx_</CODE>&rsquo;
+raise the <I>inexact</I> exception whenever the result is not exact.
+</P>
+
+<P>
+TestFloat assumes that conversions from floating-point to an integer type
+should raise the <I>invalid</I> exception if the input cannot be rounded to an
+integer representable in the result format.
+In such a circumstance:
+<UL>
+
+<LI>
+<P>
+If the result type is an unsigned integer, TestFloat normally expects the
+result of the operation to be the type&rsquo;s largest integer value.
+In the case that the input is a negative number (not a NaN), a zero result may
+also be accepted.
+</P>
+
+<LI>
+<P>
+If the result type is a signed integer and the input is a number (not a NaN),
+TestFloat expects the result to be the largest-magnitude integer with the same
+sign as the input.
+When a NaN is converted to a signed integer type, TestFloat allows either the
+largest postive or largest-magnitude negative integer to be returned.
+</P>
+
+</UL>
+Conversions to integer types are expected never to raise the <I>overflow</I>
+exception.
+</P>
+
+<H3>6.2. Basic Arithmetic Operations</H3>
+
+<P>
+The following standard arithmetic operations can be tested:
+<BLOCKQUOTE>
+<PRE>
+f16_add      f16_sub      f16_mul      f16_div      f16_sqrt
+f32_add      f32_sub      f32_mul      f32_div      f32_sqrt
+f64_add      f64_sub      f64_mul      f64_div      f64_sqrt
+extF80_add   extF80_sub   extF80_mul   extF80_div   extF80_sqrt
+f128_add     f128_sub     f128_mul     f128_div     f128_sqrt
+</PRE>
+</BLOCKQUOTE>
+The double-extended-precision (<CODE>extF80</CODE>) operations can be rounded
+to reduced precision under rounding precision control.
+</P>
+
+<H3>6.3. Fused Multiply-Add Operations</H3>
+
+<P>
+For all floating-point formats except <NOBR>80-bit</NOBR>
+double-extended-precision, TestFloat can test the fused multiply-add operation
+defined by the 2008 IEEE Floating-Point Standard.
+The fused multiply-add operations are:
+<BLOCKQUOTE>
+<PRE>
+f16_mulAdd
+f32_mulAdd
+f64_mulAdd
+f128_mulAdd
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+If one of the multiplication operands is infinite and the other is zero,
+TestFloat expects the fused multiply-add operation to raise the <I>invalid</I>
+exception even if the third operand is a quiet NaN.
+</P>
+
+<H3>6.4. Remainder Operations</H3>
+
+<P>
+For each format, TestFloat can test the IEEE Standard&rsquo;s remainder
+operation.
+These operations are:
+<BLOCKQUOTE>
+<PRE>
+f16_rem
+f32_rem
+f64_rem
+extF80_rem
+f128_rem
+</PRE>
+</BLOCKQUOTE>
+The remainder operations are always exact and so require no rounding.
+</P>
+
+<H3>6.5. Round-to-Integer Operations</H3>
+
+<P>
+For each format, TestFloat can test the IEEE Standard&rsquo;s round-to-integer
+operation.
+For most TestFloat programs, these operations are:
+<BLOCKQUOTE>
+<PRE>
+f16_roundToInt
+f32_roundToInt
+f64_roundToInt
+extF80_roundToInt
+f128_roundToInt
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Just as for conversions to integer types (<NOBR>section 6.1</NOBR> above), the
+all-in-one <CODE>testfloat</CODE> program is again an exception.
+For <CODE>testfloat</CODE> only, the round-to-integer operations have names of
+these forms:
+<BLOCKQUOTE>
+<PRE>
+&lt;<I>float</I>&gt;_roundToInt_r_&lt;<I>round</I>&gt;
+&lt;<I>float</I>&gt;_roundToInt_x
+</PRE>
+</BLOCKQUOTE>
+For the &lsquo;<CODE>_r_</CODE>&rsquo; versions, the <I>inexact</I> exception
+is never raised, and the <CODE>&lt;<I>round</I>&gt;</CODE> component specifies
+the rounding mode as one of &lsquo;<CODE>near_even</CODE>&rsquo;,
+&lsquo;<CODE>near_maxMag</CODE>&rsquo;, &lsquo;<CODE>minMag</CODE>&rsquo;,
+&lsquo;<CODE>min</CODE>&rsquo;, or &lsquo;<CODE>max</CODE>&rsquo;.
+The usual indication of rounding mode is ignored.
+In contrast, the &lsquo;<CODE>_x</CODE>&rsquo; versions accept the usual
+indication of rounding mode and raise the <I>inexact</I> exception whenever the
+result is not exact.
+This irregular system follows the IEEE Standard&rsquo;s particular
+specification for the round-to-integer operations.
+</P>
+
+<H3>6.6. Comparison Operations</H3>
+
+<P>
+The following floating-point comparison operations can be tested:
+<BLOCKQUOTE>
+<PRE>
+f16_eq      f16_le      f16_lt
+f32_eq      f32_le      f32_lt
+f64_eq      f64_le      f64_lt
+extF80_eq   extF80_le   extF80_lt
+f128_eq     f128_le     f128_lt
+</PRE>
+</BLOCKQUOTE>
+The abbreviation <CODE>eq</CODE> stands for &ldquo;equal&rdquo; (=),
+<CODE>le</CODE> stands for &ldquo;less than or equal&rdquo; (&le;), and
+<CODE>lt</CODE> stands for &ldquo;less than&rdquo; (&lt;).
+</P>
+
+<P>
+The IEEE Standard specifies that, by default, the less-than-or-equal and
+less-than comparisons raise the <I>invalid</I> exception if either input is any
+kind of NaN.
+The equality comparisons, on the other hand, are defined by default to raise
+the <I>invalid</I> exception only for signaling NaNs, not for quiet NaNs.
+For completeness, the following additional operations can be tested if
+supported:
+<BLOCKQUOTE>
+<PRE>
+f16_eq_signaling      f16_le_quiet      f16_lt_quiet
+f32_eq_signaling      f32_le_quiet      f32_lt_quiet
+f64_eq_signaling      f64_le_quiet      f64_lt_quiet
+extF80_eq_signaling   extF80_le_quiet   extF80_lt_quiet
+f128_eq_signaling     f128_le_quiet     f128_lt_quiet
+</PRE>
+</BLOCKQUOTE>
+The <CODE>signaling</CODE> equality comparisons are identical to the standard
+operations except that the <I>invalid</I> exception should be raised for any
+NaN input.
+Similarly, the <CODE>quiet</CODE> comparison operations should be identical to
+their counterparts except that the <I>invalid</I> exception is not raised for
+quiet NaNs.
+</P>
+
+<P>
+Obviously, no comparison operations ever require rounding.
+Any rounding mode is ignored.
+</P>
+
+
+<H2>7. Interpreting TestFloat Output</H2>
+
+<P>
+The &ldquo;errors&rdquo; reported by TestFloat programs may or may not really
+represent errors in the system being tested.
+For each test case tried, the results from the floating-point implementation
+being tested could differ from the expected results for several reasons:
+<UL>
+<LI>
+The IEEE Floating-Point Standard allows for some variation in how conforming
+floating-point behaves.
+Two implementations can sometimes give different results without either being
+incorrect.
+<LI>
+The trusted floating-point emulation could be faulty.
+This could be because there is a bug in the way the emulation is coded, or
+because a mistake was made when the code was compiled for the current system.
+<LI>
+The TestFloat program may not work properly, reporting differences that do not
+exist.
+<LI>
+Lastly, the floating-point being tested could actually be faulty.
+</UL>
+It is the responsibility of the user to determine the causes for the
+discrepancies that are reported.
+Making this determination can require detailed knowledge about the IEEE
+Standard.
+Assuming TestFloat is working properly, any differences found will be due to
+either the first or last of the reasons above.
+Variations in the IEEE Standard that could lead to false error reports are
+discussed in <NOBR>section 8</NOBR>, <I>Variations Allowed by the IEEE
+Floating-Point Standard</I>.
+</P>
+
+<P>
+For each reported error (or apparent error), a line of text is written to the
+default output.
+If a line would be longer than 79 characters, it is divided.
+The first part of each error line begins in the leftmost column, and any
+subsequent &ldquo;continuation&rdquo; lines are indented with a tab.
+</P>
+
+<P>
+Each error reported is of the form:
+<BLOCKQUOTE>
+<PRE>
+&lt;<I>inputs</I>&gt;  => &lt;<I>observed-output</I>&gt;  expected: &lt;<I>expected-output</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+The <CODE>&lt;<I>inputs</I>&gt;</CODE> are the inputs to the operation.
+Each output (observed or expected) is shown as a pair:  the result value first,
+followed by the exception flags.
+</P>
+
+<P>
+For example, two typical error lines could be
+<BLOCKQUOTE>
+<PRE>
+-00.7FFF00  -7F.000100  => +01.000000 ...ux  expected: +01.000000 ....x
++81.000004  +00.1FFFFF  => +01.000000 ...ux  expected: +01.000000 ....x
+</PRE>
+</BLOCKQUOTE>
+In the first line, the inputs are <CODE>-00.7FFF00</CODE> and
+<CODE>-7F.000100</CODE>, and the observed result is <CODE>+01.000000</CODE>
+with flags <CODE>...ux</CODE>.
+The trusted emulation result is the same but with different flags,
+<CODE>....x</CODE>.
+Items such as <CODE>-00.7FFF00</CODE> composed of a sign character
+<NOBR>(<CODE>+</CODE>/<CODE>-</CODE>)</NOBR>, hexadecimal digits, and a single
+period represent floating-point values (here <NOBR>32-bit</NOBR>
+single-precision).
+The two instances above were reported as errors because the exception flag
+results differ.
+</P>
+
+<P>
+Aside from the exception flags, there are ten data types that may be
+represented.
+Five are floating-point types:  <NOBR>16-bit</NOBR> half-precision,
+<NOBR>32-bit</NOBR> single-precision, <NOBR>64-bit</NOBR> double-precision,
+<NOBR>80-bit</NOBR> double-extended-precision, and <NOBR>128-bit</NOBR>
+quadruple-precision.
+The remaining five types are <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR>
+unsigned integers, <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR>
+two&rsquo;s-complement signed integers, and Boolean values (the results of
+comparison operations).
+Boolean values are represented as a single character, either a <CODE>0</CODE>
+(false) or a <CODE>1</CODE> (true).
+A <NOBR>32-bit</NOBR> integer is represented as 8 hexadecimal digits.
+Thus, for a signed <NOBR>32-bit</NOBR> integer, <CODE>FFFFFFFF</CODE> is
+&minus;1, and <CODE>7FFFFFFF</CODE> is the largest positive value.
+<NOBR>64-bit</NOBR> integers are the same except with 16 hexadecimal digits.
+</P>
+
+<P>
+Floating-point values are written decomposed into their sign, encoded exponent,
+and encoded significand.
+First is the sign character <NOBR>(<CODE>+</CODE> or <CODE>-</CODE>),</NOBR>
+followed by the encoded exponent in hexadecimal, then a period
+(<CODE>.</CODE>), and lastly the encoded significand in hexadecimal.
+</P>
+
+<P>
+For <NOBR>16-bit</NOBR> half-precision, notable values include:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR><TD><CODE>+00.000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD><TD>+0</TD></TR>
+<TR><TD><CODE>+0F.000</CODE></TD><TD>&nbsp;1</TD></TR>
+<TR><TD><CODE>+10.000</CODE></TD><TD>&nbsp;2</TD></TR>
+<TR><TD><CODE>+1E.3FF</CODE></TD><TD>maximum finite value</TD></TR>
+<TR><TD><CODE>+1F.000</CODE></TD><TD>+infinity</TD></TR>
+<TR><TD>&nbsp;</TD></TR>
+<TR><TD><CODE>-00.000</CODE></TD><TD>&minus;0</TD></TR>
+<TR><TD><CODE>-0F.000</CODE></TD><TD>&minus;1</TD></TR>
+<TR><TD><CODE>-10.000</CODE></TD><TD>&minus;2</TD></TR>
+<TR>
+  <TD><CODE>-1E.3FF</CODE></TD>
+  <TD>minimum finite value (largest magnitude, but negative)</TD>
+</TR>
+<TR><TD><CODE>-1F.000</CODE></TD><TD>&minus;infinity</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+Certain categories are easily distinguished (assuming the <CODE>x</CODE>s are
+not all 0):
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+  <TD><CODE>+00.xxx&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+  <TD>positive subnormal numbers</TD>
+</TR>
+<TR><TD><CODE>+1F.xxx</CODE></TD><TD>positive NaNs</TD></TR>
+<TR><TD><CODE>-00.xxx</CODE></TD><TD>negative subnormal numbers</TD></TR>
+<TR><TD><CODE>-1F.xxx</CODE></TD><TD>negative NaNs</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Likewise for other formats:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR><TD>32-bit single</TD><TD>64-bit double</TD><TD>128-bit quadruple</TD></TR>
+<TR><TD>&nbsp;</TD></TR>
+<TR>
+<TD><CODE>+00.000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>+000.0000000000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>+0000.0000000000000000000000000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>+0</TD>
+</TR>
+<TR>
+<TD><CODE>+7F.000000</CODE></TD>
+<TD><CODE>+3FF.0000000000000</CODE></TD>
+<TD><CODE>+3FFF.0000000000000000000000000000</CODE></TD>
+<TD>&nbsp;1</TD>
+</TR>
+<TR>
+<TD><CODE>+80.000000</CODE></TD>
+<TD><CODE>+400.0000000000000</CODE></TD>
+<TD><CODE>+4000.0000000000000000000000000000</CODE></TD>
+<TD>&nbsp;2</TD>
+</TR>
+<TR>
+<TD><CODE>+FE.7FFFFF</CODE></TD>
+<TD><CODE>+7FE.FFFFFFFFFFFFF</CODE></TD>
+<TD><CODE>+7FFE.FFFFFFFFFFFFFFFFFFFFFFFFFFFF</CODE></TD>
+<TD>maximum finite value</TD>
+</TR>
+<TR>
+<TD><CODE>+FF.000000</CODE></TD>
+<TD><CODE>+7FF.0000000000000</CODE></TD>
+<TD><CODE>+7FFF.0000000000000000000000000000</CODE></TD>
+<TD>+infinity</TD>
+</TR>
+<TR><TD>&nbsp;</TD></TR>
+<TR>
+<TD><CODE>-00.000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>-000.0000000000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD><CODE>-0000.0000000000000000000000000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>&minus;0</TD>
+</TR>
+<TR>
+<TD><CODE>-7F.000000</CODE></TD>
+<TD><CODE>-3FF.0000000000000</CODE></TD>
+<TD><CODE>-3FFF.0000000000000000000000000000</CODE></TD>
+<TD>&minus;1</TD>
+</TR>
+<TR>
+<TD><CODE>-80.000000</CODE></TD>
+<TD><CODE>-400.0000000000000</CODE></TD>
+<TD><CODE>-4000.0000000000000000000000000000</CODE></TD>
+<TD>&minus;2</TD>
+</TR>
+<TR>
+<TD><CODE>-FE.7FFFFF</CODE></TD>
+<TD><CODE>-7FE.FFFFFFFFFFFFF</CODE></TD>
+<TD><CODE>-7FFE.FFFFFFFFFFFFFFFFFFFFFFFFFFFF</CODE></TD>
+<TD>minimum finite value</TD>
+</TR>
+<TR>
+<TD><CODE>-FF.000000</CODE></TD>
+<TD><CODE>-7FF.0000000000000</CODE></TD>
+<TD><CODE>-7FFF.0000000000000000000000000000</CODE></TD>
+<TD>&minus;infinity</TD>
+</TR>
+<TR><TD>&nbsp;</TD></TR>
+<TR>
+<TD><CODE>+00.xxxxxx</CODE></TD>
+<TD><CODE>+000.xxxxxxxxxxxxx</CODE></TD>
+<TD><CODE>+0000.xxxxxxxxxxxxxxxxxxxxxxxxxxxx</CODE></TD>
+<TD>positive subnormals</TD>
+</TR>
+<TR>
+<TD><CODE>+FF.xxxxxx</CODE></TD>
+<TD><CODE>+7FF.xxxxxxxxxxxxx</CODE></TD>
+<TD><CODE>+7FFF.xxxxxxxxxxxxxxxxxxxxxxxxxxxx</CODE></TD>
+<TD>positive NaNs</TD>
+</TR>
+<TR>
+<TD><CODE>-00.xxxxxx</CODE></TD>
+<TD><CODE>-000.xxxxxxxxxxxxx</CODE></TD>
+<TD><CODE>-0000.xxxxxxxxxxxxxxxxxxxxxxxxxxxx</CODE></TD>
+<TD>negative subnormals</TD>
+</TR>
+<TR>
+<TD><CODE>-FF.xxxxxx</CODE></TD>
+<TD><CODE>-7FF.xxxxxxxxxxxxx</CODE></TD>
+<TD><CODE>-7FFF.xxxxxxxxxxxxxxxxxxxxxxxxxxxx</CODE></TD>
+<TD>negative NaNs</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The <NOBR>80-bit</NOBR> double-extended-precision values are a little unusual
+in that the leading bit of precision is not hidden as with other formats.
+When canonically encoded, the leading significand bit of an <NOBR>80-bit</NOBR>
+double-extended-precision value will be 0 if the value is zero or subnormal,
+and will be 1 otherwise.
+Hence, the same values listed above appear in <NOBR>80-bit</NOBR>
+double-extended-precision as follows (note the leading <CODE>8</CODE> digit in
+the significands):
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+  <TD><CODE>+0000.0000000000000000&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+  <TD>+0</TD>
+</TR>
+<TR><TD><CODE>+3FFF.8000000000000000</CODE></TD><TD>&nbsp;1</TD></TR>
+<TR><TD><CODE>+4000.8000000000000000</CODE></TD><TD>&nbsp;2</TD></TR>
+<TR>
+  <TD><CODE>+7FFE.FFFFFFFFFFFFFFFF</CODE></TD>
+  <TD>maximum finite value</TD>
+</TR>
+<TR><TD><CODE>+7FFF.8000000000000000</CODE></TD><TD>+infinity</TD></TR>
+<TR><TD>&nbsp;</TD></TR>
+<TR><TD><CODE>-0000.0000000000000000</CODE></TD><TD>&minus;0</TD></TR>
+<TR><TD><CODE>-3FFF.8000000000000000</CODE></TD><TD>&minus;1</TD></TR>
+<TR><TD><CODE>-4000.8000000000000000</CODE></TD><TD>&minus;2</TD></TR>
+<TR>
+  <TD><CODE>-7FFE.FFFFFFFFFFFFFFFF</CODE></TD>
+  <TD>minimum finite value</TD>
+</TR>
+<TR><TD><CODE>-7FFF.8000000000000000</CODE></TD><TD>&minus;infinity</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+Lastly, exception flag values are represented by five characters, one character
+per flag.
+Each flag is written as either a letter or a period (<CODE>.</CODE>) according
+to whether the flag was set or not by the operation.
+A period indicates the flag was not set.
+The letter used to indicate a set flag depends on the flag:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+  <TD><CODE>v&nbsp;&nbsp;&nbsp;&nbsp;</CODE></TD>
+  <TD><I>invalid</I> exception</TD>
+</TR>
+<TR>
+  <TD><CODE>i</CODE></TD>
+  <TD><I>infinite</I> exception (&ldquo;divide by zero&rdquo;)</TD>
+</TR>
+<TR><TD><CODE>o</CODE></TD><TD><I>overflow</I> exception</TD></TR>
+<TR><TD><CODE>u</CODE></TD><TD><I>underflow</I> exception</TD></TR>
+<TR><TD><CODE>x</CODE></TD><TD><I>inexact</I> exception</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+For example, the notation <CODE>...ux</CODE> indicates that the
+<I>underflow</I> and <I>inexact</I> exception flags were set and that the other
+three flags (<I>invalid</I>, <I>infinite</I>, and <I>overflow</I>) were not
+set.
+The exception flags are always written following the value returned as the
+result of the operation.
+</P>
+
+
+<H2>8. Variations Allowed by the IEEE Floating-Point Standard</H2>
+
+<P>
+The IEEE Floating-Point Standard admits some variation among conforming
+implementations.
+Because TestFloat expects the two implementations being compared to deliver
+bit-for-bit identical results under most circumstances, this leeway in the
+standard can result in false errors being reported if the two implementations
+do not make the same choices everywhere the standard provides an option.
+</P>
+
+<H3>8.1. Underflow</H3>
+
+<P>
+The standard specifies that the <I>underflow</I> exception flag is to be raised
+when two conditions are met simultaneously:
+<NOBR>(1) <I>tininess</I></NOBR> and <NOBR>(2) <I>loss of accuracy</I></NOBR>.
+</P>
+
+<P>
+A result is tiny when its magnitude is nonzero yet smaller than any normalized
+floating-point number.
+The standard allows tininess to be determined either before or after a result
+is rounded to the destination precision.
+If tininess is detected before rounding, some borderline cases will be flagged
+as underflows even though the result after rounding actually lies within the
+normal floating-point range.
+By detecting tininess after rounding, a system can avoid some unnecessary
+signaling of underflow.
+All the TestFloat programs support options <CODE>-tininessbefore</CODE> and
+<CODE>-tininessafter</CODE> to control whether TestFloat expects tininess on
+underflow to be detected before or after rounding.
+One or the other is selected as the default when TestFloat is compiled, but
+these command options allow the default to be overridden.
+</P>
+
+<P>
+Loss of accuracy occurs when the subnormal format is not sufficient to
+represent an underflowed result accurately.
+The original 1985 version of the IEEE Standard allowed loss of accuracy to be
+detected either as an <I>inexact result</I> or as a
+<I>denormalization loss</I>;
+however, few if any systems ever chose the latter.
+The latest standard requires that loss of accuracy be detected as an inexact
+result, and TestFloat can test only for this case.
+</P>
+
+<H3>8.2. NaNs</H3>
+
+<P>
+The IEEE Standard gives the floating-point formats a large number of NaN
+encodings and specifies that NaNs are to be returned as results under certain
+conditions.
+However, the standard allows an implementation almost complete freedom over
+<EM>which</EM> NaN to return in each situation.
+</P>
+
+<P>
+By default, TestFloat does not check the bit patterns of NaN results.
+When the result of an operation should be a NaN, any NaN is considered as good
+as another.
+This laxness can be overridden with the <CODE>-checkNaNs</CODE> option of
+programs <CODE>testfloat_ver</CODE> and <CODE>testfloat</CODE>.
+In order for this option to be sensible, TestFloat must have been compiled so
+that its internal floating-point implementation (SoftFloat) generates the
+proper NaN results for the system being tested.
+</P>
+
+<H3>8.3. Conversions to Integer</H3>
+
+<P>
+Conversion of a floating-point value to an integer format will fail if the
+source value is a NaN or if it is too large.
+The IEEE Standard does not specify what value should be returned as the integer
+result in these cases.
+Moreover, according to the standard, the <I>invalid</I> exception can be raised
+or an unspecified alternative mechanism may be used to signal such cases.
+</P>
+
+<P>
+TestFloat assumes that conversions to integer will raise the <I>invalid</I>
+exception if the source value cannot be rounded to a representable integer.
+In such cases, TestFloat expects the result value to be the largest-magnitude
+positive or negative integer or zero, as detailed earlier in
+<NOBR>section 6.1</NOBR>, <I>Conversion Operations</I>.
+If option <CODE>-checkInvInts</CODE> is selected with programs
+<CODE>testfloat_ver</CODE> and <CODE>testfloat</CODE>, integer results of
+invalid operations are checked for an exact match.
+In order for this option to be sensible, TestFloat must have been compiled so
+that its internal floating-point implementation (SoftFloat) generates the
+proper integer results for the system being tested.
+</P>
+
+
+<H2>9. Contact Information</H2>
+
+<P>
+At the time of this writing, the most up-to-date information about TestFloat
+and the latest release can be found at the Web page
+<A HREF="http://www.jhauser.us/arithmetic/TestFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/TestFloat.html</CODE></NOBR></A>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/TestFloat-history.html b/addins/TestFloat-3e/doc/TestFloat-history.html
new file mode 100644
index 000000000..8de782cad
--- /dev/null
+++ b/addins/TestFloat-3e/doc/TestFloat-history.html
@@ -0,0 +1,272 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley TestFloat History</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>History of Berkeley TestFloat, to Release 3e</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<P>
+Releases of Berkeley TestFloat normally parallel those of Berkeley SoftFloat,
+on which TestFloat is based.
+Each TestFloat release necessarily incorporates all bug fixes from the
+corresponding release of SoftFloat.
+</P>
+
+
+<H3>Release 3e (2018 January)</H3>
+
+<UL>
+
+<LI>
+Fixed a problem with the all-in-one <CODE>testfloat</CODE> program whereby
+function set <CODE>-all1</CODE> incorrectly also tested the three-operand fused
+multiply-add operations.
+
+<LI>
+Modified the expected behavior of rounding mode <CODE>odd</CODE> (jamming) when
+rounding to an integer value (either conversion to an integer format or a
+&lsquo;<CODE>roundToInt</CODE>&rsquo; function).
+Previously, for those cases only, rounding mode <CODE>odd</CODE> was expected
+to act the same as rounding to minimum magnitude.
+Now, when rounding to an integer value, the nearest odd integer is expected,
+consistent with the round-to-odd result of other operations.
+
+<LI>
+Added options <CODE>-checkInvInts</CODE> and <CODE>-checkAll</CODE> to programs
+<CODE>testfloat_ver</CODE> and <CODE>testfloat</CODE>.
+
+<LI>
+Improved the checking of integer results of invalid operations.
+
+</UL>
+
+
+<H3>Release 3d (2017 August)</H3>
+
+<UL>
+
+<LI>
+When the all-in-one <CODE>testfloat</CODE> program is compiled to test the C
+language&rsquo;s arithmetic, added the ability to test library functions
+<CODE>sqrtf</CODE>, <CODE>sqrtl</CODE>, <CODE>fmaf</CODE>, <CODE>fma</CODE>,
+and <CODE>fmal</CODE>, which were added to the <NOBR>C Standard</NOBR> in 1999.
+
+</UL>
+
+
+<H3>Release 3c (2017 February)</H3>
+
+<UL>
+
+<LI>
+Added support for testing rounding mode <CODE>odd</CODE> (jamming).
+
+<LI>
+Made support for testing <NOBR>64-bit</NOBR> double-precistion floating-point
+be subject to macro <CODE>FLOAT64</CODE> (akin to macros <CODE>FLOAT16</CODE>,
+<CODE>EXTFLOAT80</CODE>, and <CODE>FLOAT128</CODE> from before).
+
+<LI>
+Fixed some bugs that caused compilation to fail with certain combinations of
+option macro settings.
+
+<LI>
+Corrected the types of two internal variables to be <CODE>sig_atomic_t</CODE>
+instead of <CODE>bool</CODE>.
+
+<LI>
+Improved the formatting of some error reports (concerning where lines are
+broken when they exceed 79 characters in length).
+
+</UL>
+
+
+<H3>Release 3b (2016 July)</H3>
+
+<UL>
+
+<LI>
+Added the ability to test the common <NOBR>16-bit</NOBR>
+&ldquo;half-precision&rdquo; floating-point format.
+
+<LI>
+Added a <CODE>-seed</CODE> option to programs <CODE>testfloat_gen</CODE>,
+<CODE>testfloat</CODE>, and <CODE>testsoftfloat</CODE> for setting the seed for
+the pseudo-random number generator used to generate test cases.
+
+<LI>
+Where a specific choice is needed for how tininess is detected on underflow,
+changed the default to be the detection of tininess after rounding
+(<CODE>-tininessafter</CODE>) instead of before rounding
+(<CODE>-tininessbefore</CODE>).
+
+<LI>
+Modified the format of reported discrepancies to show the signs of
+floating-point values using <CODE>+</CODE> and <CODE>-</CODE> characters.
+
+<LI>
+Documented the use of the <CODE>INLINE</CODE> macro, and fixed the sources for
+the case that function inlining is not supported by the C compiler.
+
+<LI>
+Documented the possible need to define macro <CODE>THREAD_LOCAL</CODE> to match
+how the SoftFloat library was built.
+
+<LI>
+Modified the provided Makefiles to allow some options to be overridden from the
+<CODE>make</CODE> command.
+
+</UL>
+
+
+<H3>Release 3a (2015 October)</H3>
+
+<UL>
+
+<LI>
+Replaced the license text supplied by the University of California, Berkeley,
+and fixed some minor build problems.
+
+</UL>
+
+
+<H3>Release 3 (2015 February)</H3>
+
+<UL>
+
+<LI>
+Complete rewrite, funded by the University of California, Berkeley, and
+consequently having a different use license than earlier releases.
+Visible changes included different names for testable functions and command
+options.
+
+<LI>
+Reinstated separate programs for generating test cases
+(<CODE>testfloat_ver</CODE>) and verifying test results
+(<CODE>testfloat_gen</CODE>), as alternatives to the all-in-one
+<CODE>testfloat</CODE> program (which remained supported).
+
+<LI>
+Added support for testing conversions between floating-point and unsigned
+integers, both <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR>.
+
+<LI>
+Added support for testing a fused multiply-add operation, for all testable
+floating-point formats except <NOBR>80-bit</NOBR> double-extended-precision.
+
+<LI>
+Added support for testing a fifth rounding mode, <CODE>near_maxMag</CODE>
+(round to nearest, with ties to maximum magnitude, away from zero).
+
+<LI>
+Added <CODE>timesoftfloat</CODE> (previously found in the Berkeley SoftFloat
+package).
+
+</UL>
+
+
+<H3>Release 2c (2015 January)</H3>
+
+<UL>
+
+<LI>
+Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
+
+<LI>
+Made minor updates to the documentation, including improved wording for the
+legal restrictions on using TestFloat releases <NOBR>through 2c</NOBR> (not
+applicable to <NOBR>Release 3</NOBR> or later).
+
+</UL>
+
+
+<P>
+There was never a <NOBR>Release 2b</NOBR>.
+</P>
+
+
+<H3>Release 2a (1998 December)</H3>
+
+<UL>
+
+<LI>
+Added support for testing conversions between floating-point and
+<NOBR>64-bit</NOBR> signed integers.
+
+<LI>
+Improved the Makefiles.
+
+</UL>
+
+
+<H3>Release 2 (1997 June)</H3>
+
+<UL>
+
+<LI>
+Integrated the generation of test cases and the checking of system results into
+a single program.
+(Before they were separate programs, normally joined by explicit command-line
+pipes.)
+
+<LI>
+Improved the sequence of test cases.
+
+<LI>
+Added support for testing <NOBR>80-bit</NOBR> double-extended-precision and
+<NOBR>128-bit</NOBR> quadruple precision.
+
+<LI>
+Made program output more readable, and added new command arguments.
+
+<LI>
+Reduced dependence on the quality of the standard <CODE>rand</CODE> function
+for generating test cases.
+(Previously naively expected <CODE>rand</CODE> to be able to generate good
+random bits for the entire machine word width.)
+
+<LI>
+Created <CODE>testsoftfloat</CODE>, with its own simpler complete software
+floating-point (&ldquo;slowfloat&rdquo;) for comparison purposes.
+
+<LI>
+Made some changes to the source file structure, including renaming
+<CODE>environment.h</CODE> to <CODE>milieu.h</CODE> (to avoid confusion with
+environment variables).
+
+</UL>
+
+
+<H3>Release 1a (1996 July)</H3>
+
+<UL>
+
+<LI>
+Added the <CODE>-tininessbefore</CODE> and <CODE>-tininessafter</CODE> options
+to control whether tininess should be detected before or after rounding.
+
+</UL>
+
+
+<H3>Release 1 (1996 July)</H3>
+
+<UL>
+
+<LI>
+Original release.
+
+</UL>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/TestFloat-source.html b/addins/TestFloat-3e/doc/TestFloat-source.html
new file mode 100644
index 000000000..ec3a4b47d
--- /dev/null
+++ b/addins/TestFloat-3e/doc/TestFloat-source.html
@@ -0,0 +1,639 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>Berkeley TestFloat Source Documentation</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: Source Documentation</H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Contents</H2>
+
+<BLOCKQUOTE>
+<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
+<COL WIDTH=25>
+<COL WIDTH=*>
+<TR><TD COLSPAN=2>1. Introduction</TD></TR>
+<TR><TD COLSPAN=2>2. Limitations</TD></TR>
+<TR><TD COLSPAN=2>3. Acknowledgments and License</TD></TR>
+<TR><TD COLSPAN=2>4. TestFloat Package Directory Structure</TD></TR>
+<TR><TD COLSPAN=2>5. Dependence on Berkeley SoftFloat</TD></TR>
+<TR><TD COLSPAN=2>6. Issues for Porting TestFloat to a New Target</TD></TR>
+<TR>
+  <TD></TD>
+  <TD>6.1. Standard Headers <CODE>&lt;stdbool.h&gt;</CODE> and
+    <CODE>&lt;stdint.h&gt;</CODE></TD>
+</TR>
+<TR><TD></TD><TD>6.2. Standard Header <CODE>&lt;fenv.h&gt;</CODE></TD></TR>
+<TR><TD></TD><TD>6.3. Macros for Build Options</TD></TR>
+<TR><TD></TD><TD>6.4. Specializing the <CODE>testfloat</CODE> Program</TD></TR>
+<TR><TD></TD><TD>6.5. Improving the Random Number Functions</TD></TR>
+<TR><TD COLSPAN=2>7. Contact Information</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+
+
+<H2>1. Introduction</H2>
+
+<P>
+This document gives information needed for compiling and/or porting Berkeley
+TestFloat, a small collection of programs for testing that an implementation of
+binary floating-point conforms to the IEEE Standard for Floating-Point
+Arithmetic.
+For basic documentation about TestFloat refer to
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+The source code for TestFloat is intended to be relatively machine-independent.
+Most programs in the TestFloat package should be compilable with any
+ISO-Standard C compiler that also supports <NOBR>64-bit</NOBR> integers.
+If the all-in-one <CODE>testfloat</CODE> program will be used to test a new
+floating-point implementation, additional effort will likely be required to
+retarget that program to invoke the new floating-point operations.
+TestFloat has been successfully compiled with the GNU C Compiler
+(<CODE>gcc</CODE>) for several platforms.
+</P>
+
+<P>
+<NOBR>Release 3</NOBR> of TestFloat was a complete rewrite relative to
+<NOBR>Release 2c</NOBR> or earlier.
+The current version of TestFloat is <NOBR>Release 3e</NOBR>.
+</P>
+
+<P>
+TestFloat depends on Berkeley SoftFloat, which is a software implementation of
+binary floating-point that conforms to the IEEE Standard for Floating-Point
+Arithmetic.
+SoftFloat is not included with the TestFloat sources.
+It can be obtained from the Web page
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+</P>
+
+
+<H2>2. Limitations</H2>
+
+<P>
+TestFloat assumes the computer has an addressable byte size of either 8 or
+<NOBR>16 bits</NOBR>.
+(Nearly all computers in use today have <NOBR>8-bit</NOBR> bytes.)
+</P>
+
+<P>
+TestFloat is written entirely <NOBR>in C</NOBR>.
+The C compiler used must conform at a minimum to the 1989 ANSI standard for the
+C language (same as the 1990 ISO standard) and must in addition support basic
+arithmetic on <NOBR>64-bit</NOBR> integers.
+Earlier releases of TestFloat were capable of testing <NOBR>32-bit</NOBR>
+single-precision and <NOBR>64-bit</NOBR> double-precision floating-point
+without requiring compiler support for <NOBR>64-bit</NOBR> integers, but this
+option is not supported starting with <NOBR>Release 3</NOBR>.
+Since 1999, ISO standards for C have mandated compiler support for
+<NOBR>64-bit</NOBR> integers.
+A compiler conforming to the 1999 C Standard or later is recommended but not
+strictly required.
+</P>
+
+<P>
+<NOBR>C Standard</NOBR> header files <CODE>&lt;stdbool.h&gt;</CODE> and
+<CODE>&lt;stdint.h&gt;</CODE> are required for defining standard Boolean and
+integer types.
+If these headers are not supplied with the C compiler, minimal substitutes must
+be provided.
+TestFloat&rsquo;s dependence on these headers is detailed later in
+<NOBR>section 6.1</NOBR>, <I>Standard Headers <CODE>&lt;stdbool.h&gt;</CODE>
+and <CODE>&lt;stdint.h&gt;</CODE></I>.
+</P>
+
+
+<H2>3. Acknowledgments and License</H2>
+
+<P>
+The TestFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
+<NOBR>Release 3</NOBR> of TestFloat was a completely new implementation
+supplanting earlier releases.
+The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
+done in the employ of the University of California, Berkeley, within the
+Department of Electrical Engineering and Computer Sciences, first for the
+Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
+The work was officially overseen by Prof. Krste Asanovic, with funding provided
+by these sources:
+<BLOCKQUOTE>
+<TABLE>
+<COL>
+<COL WIDTH=10>
+<COL>
+<TR>
+<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
+(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
+NVIDIA, Oracle, and Samsung.
+</TD>
+</TR>
+<TR>
+<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
+<TD></TD>
+<TD>
+DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
+ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
+Oracle, and Samsung.
+</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+The following applies to the whole of TestFloat <NOBR>Release 3e</NOBR> as well
+as to each source file individually.
+</P>
+
+<P>
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.
+All rights reserved.
+</P>
+
+<P>
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+<OL>
+
+<LI>
+<P>
+Redistributions of source code must retain the above copyright notice, this
+list of conditions, and the following disclaimer.
+</P>
+
+<LI>
+<P>
+Redistributions in binary form must reproduce the above copyright notice, this
+list of conditions, and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+</P>
+
+<LI>
+<P>
+Neither the name of the University nor the names of its contributors may be
+used to endorse or promote products derived from this software without specific
+prior written permission.
+</P>
+
+</OL>
+</P>
+
+<P>
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS &ldquo;AS IS&rdquo;,
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.
+IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+</P>
+
+
+<H2>4. TestFloat Package Directory Structure</H2>
+
+<P>
+Because TestFloat is targeted to multiple platforms, its source code is
+slightly scattered between target-specific and target-independent directories
+and files.
+The supplied directory structure is as follows:
+<BLOCKQUOTE>
+<PRE>
+doc
+source
+    subj-C
+build
+    template
+    Linux-386-GCC
+    Linux-386-SSE2-GCC
+    Linux-x86_64-GCC
+    Linux-ARM-VFPv2-GCC
+    Win32-MinGW
+    Win32-SSE2-MinGW
+    Win64-MinGW-w64
+</PRE>
+</BLOCKQUOTE>
+The majority of the TestFloat sources are provided in the <CODE>source</CODE>
+directory.
+The <NOBR><CODE>subj-C</CODE></NOBR> subdirectory contains the sources that
+configure the all-in-one <CODE>testfloat</CODE> program to test the C
+compiler&rsquo;s implementation of the standard C types <CODE>float</CODE>,
+<CODE>double</CODE>, and possibly <CODE>long</CODE> <CODE>double</CODE>.
+The &lsquo;<CODE>subj</CODE>&rsquo; in <NOBR><CODE>subj-C</CODE></NOBR> is an
+abbreviation of <I>subject</I>, referring to the floating-point that is the
+subject of the test.
+If <CODE>testfloat</CODE> is retargeted to test other floating-point
+implementations, the corresponding source files would be expected to be in
+other subdirectories alongside <NOBR><CODE>subj-C</CODE></NOBR>, with names of
+the form <NOBR><CODE>subj-&lt;<I>target</I>&gt;</CODE></NOBR>.
+More about retargeting <CODE>testfloat</CODE> is found in
+<NOBR>section 6.4</NOBR>, <I>Specializing the <CODE>testfloat</CODE>
+Program</I>.
+</P>
+
+<P>
+The <CODE>build</CODE> directory is intended to contain a subdirectory for each
+target platform for which builds of the TestFloat programs may be created.
+For each build target, the target&rsquo;s subdirectory is where all derived
+object files and the completed TestFloat executables are created.
+The <CODE>template</CODE> subdirectory is not an actual build target but
+contains sample files for creating new target directories.
+</P>
+
+<P>
+Ignoring the <CODE>template</CODE> directory, the supplied target directories
+are intended to follow a naming system of
+<NOBR><CODE>&lt;<I>execution-environment</I>&gt;-&lt;<I>compiler</I>&gt;</CODE></NOBR>.
+For the example targets,
+<NOBR><CODE>&lt;<I>execution-environment</I>&gt;</CODE></NOBR> is
+<NOBR><CODE>Linux-386</CODE></NOBR>, <NOBR><CODE>Linux-386-SSE2</CODE></NOBR>,
+<NOBR><CODE>Linux-x86_64</CODE></NOBR>,
+<NOBR><CODE>Linux-ARM-VFPv2</CODE></NOBR>, <CODE>Win32</CODE>,
+<NOBR><CODE>Win32-SSE2</CODE></NOBR>, or <CODE>Win64</CODE>, and
+<NOBR><CODE>&lt;<I>compiler</I>&gt;</CODE></NOBR> is <CODE>GCC</CODE>,
+<CODE>MinGW</CODE>, or <NOBR><CODE>MinGW-w64</CODE></NOBR>.
+</P>
+
+<P>
+All of the supplied target directories are merely examples that may or may not
+be correct for compiling on any particular system.
+There are currently no plans to include and maintain in the TestFloat package
+the build files needed for a great many users&rsquo; compilation environments,
+which can span a huge range of operating systems, compilers, and other tools.
+</P>
+
+<P>
+As supplied, each target directory contains two files:
+<BLOCKQUOTE>
+<PRE>
+Makefile
+platform.h
+</PRE>
+</BLOCKQUOTE>
+The provided <CODE>Makefile</CODE> is written for GNU <CODE>make</CODE>.
+A build of TestFloat for the specific target is begun by executing the
+<CODE>make</CODE> command with the target directory as the current directory.
+A completely different build tool can be used if an appropriate
+<CODE>Makefile</CODE> equivalent is created.
+</P>
+
+<P>
+The <CODE>platform.h</CODE> header file exists to provide a location for
+additional C declarations specific to the build target.
+Every C source file of TestFloat contains a <CODE>#include</CODE> for
+<CODE>platform.h</CODE>.
+In many cases, the contents of <CODE>platform.h</CODE> can be as simple as one
+or two lines of code.
+If the target&rsquo;s compiler or library has bugs or other shortcomings,
+workarounds for these issues may be possible with target-specific declarations
+in <CODE>platform.h</CODE>, without the need to modify the main TestFloat
+sources.
+</P>
+
+<P>
+It may not be necessary to build all of the TestFloat programs.
+For testing a floating-point implementation, typically
+<CODE>testfloat_gen</CODE> and <CODE>testfloat</CODE> will not both be used,
+and <CODE>testfloat_ver</CODE> may not be needed either.
+The Makefile (or equivalent) can be modified not to create unneeded programs.
+This may be especially relevant for the all-in-one test program
+<CODE>testfloat</CODE>, which might not build without special attention.
+</P>
+
+
+<H2>5. Dependence on Berkeley SoftFloat</H2>
+
+<P>
+In addition to the distributed sources, TestFloat depends on the existence of a
+compatible Berkeley SoftFloat library and the corresponding header file
+<CODE>softfloat.h</CODE>.
+As mentioned earlier, SoftFloat is a separate package available at Web page
+<A HREF="http://www.jhauser.us/arithmetic/SoftFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/SoftFloat.html</CODE></NOBR></A>.
+The SoftFloat library must be compiled before the TestFloat programs can be
+built.
+In the example Makefiles, the locations of the SoftFloat header files and
+pre-compiled library are specified by these macros:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>SOFTFLOAT_INCLUDE_DIR</CODE>
+<DD>
+The path of the directory containing <CODE>softfloat.h</CODE>, as well as other
+nonstandard header files referenced by <CODE>softfloat.h</CODE>, if any.
+<DT><CODE>SOFTFLOAT_H</CODE>
+<DD>
+A list of the full paths of all SoftFloat header files needed by SoftFloat
+clients.  This list must include <CODE>softfloat.h</CODE> and may also include
+other header files referenced by <CODE>softfloat.h</CODE>, such as
+<CODE>softfloat_types.h</CODE>.
+This macro is used only to establish build dependencies between the SoftFloat
+header files and TestFloat&rsquo;s source files, in case the SoftFloat header
+files are changed.
+<DT><CODE>SOFTFLOAT_LIB</CODE>
+<DD>
+The full path of the compiled SoftFloat library (usually
+<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>).
+</DL>
+</BLOCKQUOTE>
+</P>
+
+
+<H2>6. Issues for Porting TestFloat to a New Target</H2>
+
+<H3>6.1. Standard Headers <CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE></H3>
+
+<P>
+The TestFloat sources make use of standard headers
+<CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE>, which have
+been part of the ISO C Standard Library since 1999.
+With any recent compiler, these standard headers are likely to be supported,
+even if the compiler does not claim complete conformance to the latest ISO C
+Standard.
+For older or nonstandard compilers, substitutes for
+<CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE> may need to be
+created.
+TestFloat depends on these names from <CODE>&lt;stdbool.h&gt;</CODE>:
+<BLOCKQUOTE>
+<PRE>
+bool
+true
+false
+</PRE>
+</BLOCKQUOTE>
+and on these names from <CODE>&lt;stdint.h&gt;</CODE>:
+<BLOCKQUOTE>
+<PRE>
+uint16_t
+uint32_t
+uint64_t
+int32_t
+int64_t
+UINT64_C
+INT64_C
+uint_least8_t
+uint_fast8_t
+uint_fast16_t
+uint_fast32_t
+uint_fast64_t
+int_fast8_t
+int_fast16_t
+int_fast32_t
+int_fast64_t
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+
+<H3>6.2. Standard Header <CODE>&lt;fenv.h&gt;</CODE></H3>
+
+<P>
+Because the supplied all-in-one <CODE>testfloat</CODE> program tests the
+floating-point operations of the C language, it uses the facilities provided by
+standard C header <CODE>&lt;fenv.h&gt;</CODE> to access the floating-point
+environment of C, in particular to set the rounding mode and to access the
+floating-point exception flags.
+Like <CODE>&lt;stdbool.h&gt;</CODE> and <CODE>&lt;stdint.h&gt;</CODE>,
+<CODE>&lt;fenv.h&gt;</CODE> has been part of the ISO C Standard Library since
+1999, but older or nonstandard C compilers may not support it.
+</P>
+
+<P>
+Some form of standard header <CODE>&lt;fenv.h&gt;</CODE> is needed only if the
+<CODE>testfloat</CODE> program is wanted <EM>and</EM> the program will not be
+retargeted to invoke a floating-point implementation in a way that bypasses the
+standard C environment.
+Typically, if <CODE>testfloat</CODE> is wanted, it will be retargeted to invoke
+a new floating-point implementation directly, making
+<CODE>&lt;fenv.h&gt;</CODE> irrelevant.
+For more about retargeting <CODE>testfloat</CODE>, see <NOBR>section 6.4</NOBR>
+below, <I>Specializing the <CODE>testfloat</CODE> Program</I>.
+</P>
+
+
+<H3>6.3. Macros for Build Options</H3>
+
+<P>
+The TestFloat source files are affected by several C preprocessor macros:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>LITTLEENDIAN</CODE>
+<DD>
+Must be defined for little-endian machines;
+must not be defined for big-endian machines.
+<DT><CODE>INLINE</CODE>
+<DD>
+Can be defined to a sequence of tokens used to indicate that a C function
+should be inlined.
+If the compiler does not support the inlining of functions, this macro must not
+be defined.
+For compilers that conform to the C Standard&rsquo;s rules for inline
+functions, this macro can be defined as the single keyword <CODE>inline</CODE>.
+For other compilers that follow a convention pre-dating the standardization of
+<CODE>inline</CODE>, this macro may need to be defined to <CODE>extern</CODE>
+<CODE>inline</CODE>.
+<DT><CODE>THREAD_LOCAL</CODE>
+<DD>
+Can be defined to a sequence of tokens that, when appearing at the start of a
+variable declaration, indicates to the C compiler that the variable is
+<I>per-thread</I>, meaning that each execution thread gets its own separate
+instance of the variable.
+This macro is used in the supplied version of Berkeley SoftFloat&rsquo;s header
+<CODE>softfloat.h</CODE>, in the declarations of variables
+<CODE>softfloat_roundingMode</CODE>, <CODE>softfloat_detectTininess</CODE>,
+<CODE>extF80_roundingPrecision</CODE>, and
+<CODE>softfloat_exceptionFlags</CODE>.
+To use the supplied, unmodified header <CODE>softfloat.h</CODE>, this macro
+must be defined (or not defined) the same as when the SoftFloat library was
+built.
+</DL>
+<DL>
+<DT><CODE>FLOAT16</CODE>
+<DD>
+Must be defined if the TestFloat programs are to support the
+<NOBR>16-bit</NOBR> half-precision floating-point format.
+<DT><CODE>FLOAT64</CODE>
+<DD>
+Must be defined if the TestFloat programs are to support the
+<NOBR>64-bit</NOBR> double-precision floating-point format.
+<DT><CODE>EXTFLOAT80</CODE>
+<DD>
+Must be defined if the TestFloat programs are to support the
+<NOBR>80-bit</NOBR> double-extended-precision floating-point format.
+<DT><CODE>FLOAT128</CODE>
+<DD>
+Must be defined if the TestFloat programs are to support the
+<NOBR>128-bit</NOBR> quadruple-precision floating-point format.
+<DT><CODE>FLOAT_ROUND_ODD</CODE>
+<DD>
+Must be defined if the TestFloat programs are to support rounding to odd
+(jamming).
+To be useful, this option also requires that the Berkeley SoftFloat library was
+compiled with macro <CODE>SOFTFLOAT_ROUND_ODD</CODE> defined.
+</DL>
+</BLOCKQUOTE>
+Following the usual custom <NOBR>for C</NOBR>, for all the macros except
+<CODE>INLINE</CODE> and <CODE>THREAD_LOCAL</CODE>, the content of a
+macro&rsquo;s definition is irrelevant;
+what matters is a macro&rsquo;s effect on <CODE>#ifdef</CODE> directives.
+</P>
+
+<P>
+It is recommended that any definition of macros <CODE>LITTLEENDIAN</CODE>,
+<CODE>INLINE</CODE>, and <CODE>THREAD_LOCAL</CODE> be made in a build
+target&rsquo;s <CODE>platform.h</CODE> header file, because these macros are
+expected to be determined inflexibly by the target machine and compiler.
+The other five macros select build options, and hence might be better located
+in the target&rsquo;s Makefile (or its equivalent).
+</P>
+
+
+<H3>6.4. Specializing the <CODE>testfloat</CODE> Program</H3>
+
+<P>
+The supplied sources for the all-in-one <CODE>testfloat</CODE> program cause
+<CODE>testfloat</CODE> to test the C compiler&rsquo;s <CODE>float</CODE> and
+<CODE>double</CODE> types for C operations <CODE>+</CODE>, <CODE>-</CODE>,
+<CODE>*</CODE>, <CODE>/</CODE>, etc.
+The supplied version is also capable of testing C type <CODE>long</CODE>
+<CODE>double</CODE> if the sources are compiled with one of these macros
+defined:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>LONG_DOUBLE_IS_EXTFLOAT80</CODE>
+<DD>
+Indicates that type <CODE>long</CODE> <CODE>double</CODE> is
+<NOBR>80-bit</NOBR> double-extended-precision floating-point.
+<DT><CODE>LONG_DOUBLE_IS_FLOAT128</CODE>
+<DD>
+Indicates that type <CODE>long</CODE> <CODE>double</CODE> is
+<NOBR>128-bit</NOBR> quadruple-precision floating-point.
+</DL>
+</BLOCKQUOTE>
+By default, <CODE>testfloat</CODE> assumes that only the IEEE Standard&rsquo;s
+original four rounding modes (<CODE>near_even</CODE>, <CODE>minMag</CODE>,
+<CODE>min</CODE>, and <CODE>max</CODE>) are supported by the floating-point
+being tested.
+For other rounding modes, additional macro can be defined:
+<BLOCKQUOTE>
+<DL>
+<DT><CODE>SUBJFLOAT_ROUND_NEAR_MAXMAG</CODE>
+<DD>
+Indicates that the subject floating-point supports rounding mode
+<CODE>near_maxMag</CODE> (nearest/away).
+<DT><CODE>SUBJFLOAT_ROUND_ODD</CODE>
+<DD>
+Indicates that the subject floating-point supports rounding mode
+<CODE>odd</CODE> (jamming).
+</DL>
+</BLOCKQUOTE>
+</P>
+
+<P>
+To test a new and/or different implementation of floating-point,
+<CODE>testfloat</CODE> must normally be retargeted to invoke this other
+floating-point instead of C&rsquo;s floating-point.
+Two source files define the functions that <CODE>testfloat</CODE> uses to
+invoke floating-point operations for testing:
+<BLOCKQUOTE>
+<PRE>
+subjfloat_config.h
+subjfloat.c
+</PRE>
+</BLOCKQUOTE>
+For the default target of testing C&rsquo;s floating-point, these files are
+contained in directory <NOBR><CODE>source/subj-C</CODE></NOBR> as discussed
+earlier.
+For a different subject floating-point, it is recommended that appropriate
+versions of <CODE>subjfloat_config.h</CODE> and <CODE>subjfloat.c</CODE> be
+stored in a sibling <NOBR><CODE>subj-&lt;<I>target</I>&gt;</CODE></NOBR>
+directory, where <CODE>&lt;<I>target</I>&gt;</CODE> names the particular
+target.
+</P>
+
+<P>
+Header file <CODE>subjfloat_config.h</CODE> defines a macro of the form
+<CODE>SUBJ_*</CODE> for each subject function supported.
+For example, if function <CODE>subj_f32_add</CODE> exists to perform
+<NOBR>32-bit</NOBR> floating-point addition, then
+<CODE>subjfloat_config.h</CODE> should have a definition for macro
+<CODE>SUBJ_F32_ADD</CODE>.
+The actual function <CODE>subj_f32_add</CODE> is expected to be defined in
+<CODE>subjfloat.c</CODE>, along with all other subject functions.
+A common header file, <CODE>subjfloat.h</CODE>, (not target-specific) provides
+prototype declarations for all possible subject functions that
+<CODE>testfloat</CODE> may be compiled to test, whether actually existing or
+not.
+(There is no penalty for the header to declare prototypes of nonexistent
+functions that are never called.)
+For a specific build of <CODE>testfloat</CODE>, the <CODE>-list</CODE> option
+will list all subject functions that the <CODE>testfloat</CODE> program is able
+to invoke and thus test.
+</P>
+
+<P>
+In the source code as supplied, macros <CODE>LONG_DOUBLE_IS_EXTFLOAT80</CODE>
+and <CODE>LONG_DOUBLE_IS_FLOAT128</CODE> affect only the target-specific source
+files in <NOBR><CODE>source/subj-C</CODE></NOBR>, so these macros can be
+ignored for any other subject floating-point that does not depend on them.
+On the other hand, macros <CODE>SUBJFLOAT_ROUND_NEAR_MAXMAG</CODE> and
+<CODE>SUBJFLOAT_ROUND_ODD</CODE> always determine whether the
+<CODE>testfloat</CODE> program attempts to test rounding modes
+<CODE>near_maxMag</CODE> and <CODE>odd</CODE>, regardless of the subject
+floating-point.
+</P>
+
+
+<H3>6.5. Improving the Random Number Functions</H3>
+
+<P>
+If you are serious about using TestFloat for testing floating-point, you should
+consider replacing the random number functions in <CODE>random.c</CODE>.
+The supplied random number functions are built on top of the standard C
+<CODE>rand</CODE> function.
+Because function <CODE>rand</CODE> is rather poor on some systems, the
+functions in <CODE>random.c</CODE> assume very little about the quality of
+<CODE>rand</CODE>.
+As a result, <CODE>rand</CODE> is called more frequently than it might need to
+be, shortening the time before random number sequences repeat, and possibly
+wasting time as well.
+If <CODE>rand</CODE> is better on a given target platform, or if another,
+better random number generator is available (such as <CODE>rand48</CODE> on
+UNIX-derived systems), TestFloat can be improved by overriding the given
+<CODE>random.c</CODE> with a target-specific one.
+</P>
+
+<P>
+Rather than modifying the supplied file <CODE>random.c</CODE>, it is
+recommended instead that a new, alternate file be created and the
+target&rsquo;s Makefile be modified to refer to that alternate file in place of
+<CODE>random.c</CODE>.
+</P>
+
+
+<H2>7. Contact Information</H2>
+
+<P>
+At the time of this writing, the most up-to-date information about TestFloat
+and the latest release can be found at the Web page
+<A HREF="http://www.jhauser.us/arithmetic/TestFloat.html"><NOBR><CODE>http://www.jhauser.us/arithmetic/TestFloat.html</CODE></NOBR></A>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/testfloat.html b/addins/TestFloat-3e/doc/testfloat.html
new file mode 100644
index 000000000..34313cbba
--- /dev/null
+++ b/addins/TestFloat-3e/doc/testfloat.html
@@ -0,0 +1,286 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>testfloat</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: <CODE>testfloat</CODE></H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Overview</H2>
+
+<P>
+The <CODE>testfloat</CODE> program tests an implementation of floating-point
+arithmetic for conformity to the IEEE Standard for Binary Floating-Point
+Arithmetic.
+<CODE>testfloat</CODE> is part of the Berkeley TestFloat package, a small
+collection of programs for performing such tests.
+For general information about TestFloat, see file
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+The <CODE>testfloat</CODE> program is an all-in-one tool for testing
+floating-point arithmetic.
+It generates test operand values, invokes a floating-point operation with the
+generated operands, and examines the corresponding computed results, reporting
+unexpected results as likely errors.
+While the processes of generating inputs and examining results are generic, a
+particular build of <CODE>testfloat</CODE> is limited to testing only the one
+implementation of floating-point it has been compiled to invoke.
+For example, while one instance of <CODE>testfloat</CODE> might be compiled to
+execute a computer&rsquo;s hardware instruction for floating-point addition, a
+different version might be compiled to call a subroutine called
+<CODE>myAddFloat</CODE> that is linked into the <CODE>testfloat</CODE> program.
+To test a new implementation of floating-point (a new set of machine
+instructions or a new set of subroutines), a new <CODE>testfloat</CODE> must be
+compiled containing the code needed to invoke the new floating-point.
+</P>
+
+<P>
+The default build of <CODE>testfloat</CODE> assumes that C types
+<CODE>float</CODE> and <CODE>double</CODE> are <NOBR>32-bit</NOBR> and
+<NOBR>64-bit</NOBR> binary floating-point types conforming to the IEEE
+Standard, and tests the C operations of <CODE>+</CODE>, <CODE>-</CODE>,
+<CODE>*</CODE>, <CODE>/</CODE>, type conversions, etc.
+This tests the floating-point arithmetic seen by C programs.
+Depending on the compiler and the options selected during compilation, this may
+or may not be the same as the computer&rsquo;s floating-point hardware, if any.
+</P>
+
+<P>
+The <CODE>testfloat</CODE> program will ordinarily test an operation for all
+five rounding modes defined by the IEEE Floating-Point Standard, one after the
+other, plus possibly a sixth mode, <I>round to odd</I> (depending on the
+options selected when <CODE>testfloat</CODE> was compiled).
+If the rounding mode is not supposed to have any affect on the
+results&mdash;for instance, some operations do not require rounding&mdash;only
+the nearest/even rounding mode is checked.
+For double-extended-precision operations affected by rounding precision
+control, <CODE>testfloat</CODE> also tests all three rounding precision modes,
+one after the other.
+Testing can be limited to a single rounding mode and/or rounding precision with
+appropriate command-line options.
+</P>
+
+<P>
+For more about the operation of <CODE>testfloat</CODE> and how to interpret its
+output, refer to
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+
+<H2>Command Syntax</H2>
+
+<P>
+The <CODE>testfloat</CODE> program is executed as a command with this syntax:
+<BLOCKQUOTE>
+<PRE>
+testfloat [&lt;<I>option</I>&gt;...] &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Square brackets (<CODE>[ ]</CODE>) denote optional arguments,
+<CODE>&lt;<I>option</I>&gt;</CODE> is a supported option, and
+<CODE>&lt;<I>function</I>&gt;</CODE> is the name of either a testable operation
+or a function set.
+The available options and function sets are documented below.
+The <CODE>-list</CODE> option can be used to obtain a list of all testable
+operations for a given build of <CODE>testfloat</CODE>.
+If <CODE>testfloat</CODE> is executed without any arguments, a summary of usage
+is written.
+</P>
+
+
+<H2>Options</H2>
+
+<P>
+The <CODE>testfloat</CODE> program accepts several command options.
+If mutually contradictory options are given, the last one has priority.
+</P>
+
+<H3><CODE>-help</CODE></H3>
+
+<P>
+The <CODE>-help</CODE> option causes a summary of program usage to be written,
+after which the program exits.
+</P>
+
+<H3><CODE>-list</CODE></H3>
+
+<P>
+The <CODE>-list</CODE> option causes a list of testable operations to be
+written, after which the program exits.
+An operation is testable by <CODE>testfloat</CODE> if the program knows some
+way to invoke the operation.
+</P>
+
+<H3><CODE>-seed &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-seed</CODE> option sets the seed for the pseudo-random number
+generator used for generating test cases.
+The argument to <CODE>-seed</CODE> is a nonnegative integer.
+Executing the same compiled <CODE>testfloat</CODE> program with the same
+arguments (including the same pseudo-random number seed) should always perform
+the same sequence of tests, whereas changing the pseudo-random number seed
+should result in a different sequence of tests.
+The default seed number <NOBR>is 1</NOBR>.
+</P>
+
+<H3><CODE>-level &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-level</CODE> option sets the level of testing.
+The argument to <CODE>-level</CODE> can be either 1 <NOBR>or 2</NOBR>.
+The default is <NOBR>level 1</NOBR>.
+Level 2 performs many more tests than <NOBR>level 1</NOBR> and thus can reveal
+bugs not found by <NOBR>level 1</NOBR>.
+</P>
+
+<H3><CODE>-errors &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-errors</CODE> option instructs <CODE>testfloat</CODE> to report no
+more than the specified number of errors for any combination of operation,
+rounding mode, etc.
+The argument to <CODE>-errors</CODE> must be a nonnegative decimal integer.
+Once the specified number of error reports has been generated,
+<CODE>testfloat</CODE> ends the current test and begins the next one, if any.
+The default is <NOBR><CODE>-errors</CODE> <CODE>20</CODE></NOBR>.
+</P>
+
+<P>
+Against intuition, <NOBR><CODE>-errors</CODE> <CODE>0</CODE></NOBR> causes
+<CODE>testfloat</CODE> to report every error it finds.
+</P>
+
+<H3><CODE>-errorstop</CODE></H3>
+
+<P>
+The <CODE>-errorstop</CODE> option causes the program to exit after the first
+operation for which any errors are reported.
+</P>
+
+<H3><CODE>-forever</CODE></H3>
+
+<P>
+The <CODE>-forever</CODE> option causes a single operation to be repeatedly
+tested.
+Only one rounding mode and/or rounding precision can be tested in a single
+execution.
+If not specified, the rounding mode defaults to nearest/even.
+For <NOBR>80-bit</NOBR> double-extended-precision operations, the rounding
+precision defaults to full double-extended precision.
+The testing level is set to 2 by this option.
+</P>
+
+<H3><CODE>-checkNaNs</CODE></H3>
+
+<P>
+The <CODE>-checkNaNs</CODE> option causes <CODE>testfloat</CODE> to verify the
+bitwise correctness of NaN results.
+In order for this option to be sensible, <CODE>testfloat</CODE> must have been
+compiled so that its internal reference implementation of floating-point
+(Berkeley SoftFloat) generates the proper NaN results for the system being
+tested.
+</P>
+
+<H3><CODE>-checkInvInts</CODE></H3>
+
+<P>
+The <CODE>-checkInvInts</CODE> option causes <CODE>testfloat</CODE> to verify
+the bitwise correctness of integer results of invalid operations.
+In order for this option to be sensible, <CODE>testfloat</CODE> must have been
+compiled so that its internal reference implementation of floating-point
+(Berkeley SoftFloat) generates the proper integer results for the system being
+tested.
+</P>
+
+<H3><CODE>-checkAll</CODE></H3>
+
+<P>
+Enables both <CODE>-checkNaNs</CODE> and <CODE>-checkInvInts</CODE>.
+</P>
+
+<H3><CODE>-precision32, -precision64, -precision80</CODE></H3>
+
+<P>
+For <NOBR>80-bit</NOBR> double-extended-precision operations affected by
+rounding precision control, the <CODE>-precision32</CODE> option restricts
+testing to only the cases in which the rounding precision is
+<NOBR>32 bits</NOBR>, equivalent to <NOBR>32-bit</NOBR> single-precision.
+The other rounding precision choices are not tested.
+Likewise, <CODE>-precision64</CODE> fixes the rounding precision to
+<NOBR>64 bits</NOBR>, equivalent to <NOBR>64-bit</NOBR> double-precision, and
+<CODE>-precision80</CODE> fixes the rounding precision to the full
+<NOBR>80 bits</NOBR> of the double-extended-precision format.
+All these options are ignored for operations not affected by rounding precision
+control.
+</P>
+
+<P>
+The precision-control options may not be supported at all if no
+double-extended-precision operations are testable.
+</P>
+
+<H3><CODE>-rnear_even, -rnear_maxMag, -rminMag, -rmin, -rmax, -rodd</CODE></H3>
+
+<P>
+The <CODE>-rnear_even</CODE> option restricts testing to only the cases in
+which the rounding mode is nearest/even.
+The other rounding mode choices are not tested.
+Likewise, <CODE>-rnear_maxMag</CODE> forces rounding to nearest/maximum
+magnitude (nearest-away), <CODE>-rminMag</CODE> forces rounding to minimum
+magnitude (toward zero), <CODE>-rmin</CODE> forces rounding to minimum (down,
+toward negative infinity), <CODE>-rmax</CODE> forces rounding to maximum (up,
+toward positive infinity), and <CODE>-rodd</CODE>, if supported, forces
+rounding to odd.
+These options are ignored for operations that are exact and thus do not round,
+or that have the rounding mode included in the function name (such as
+<CODE>f32_to_i32_r_near_maxMag</CODE>).
+</P>
+
+<H3><CODE>-tininessbefore, -tininessafter</CODE></H3>
+
+<P>
+The <CODE>-tininessbefore</CODE> option indicates that the floating-point
+implementation being tested detects tininess on underflow before rounding.
+The <CODE>-tininessafter</CODE> option indicates that tininess is detected
+after rounding.
+The <CODE>testfloat</CODE> program alters its expectations accordingly.
+These options override the default selected when <CODE>testfloat</CODE> was
+compiled.
+Choosing the wrong one of these two options should cause error reports for some
+(but not all) operations.
+</P>
+
+
+<H2>Function Sets</H2>
+
+<P>
+Just as <CODE>testfloat</CODE> can test an operation for all five or six
+rounding modes in sequence, multiple operations can be tested with a single
+execution of <CODE>testfloat</CODE>.
+Two sets are recognized:  <CODE>-all1</CODE> and <CODE>-all2</CODE>.
+The set <CODE>-all1</CODE> is all one-operand operations, while
+<CODE>-all2</CODE> is all two-operand operations.
+A function set is used in place of an operation name in the
+<CODE>testfloat</CODE> command line, such as
+<BLOCKQUOTE>
+<PRE>
+testfloat [&lt;<I>option</I>&gt;...] -all1
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/testfloat_gen.html b/addins/TestFloat-3e/doc/testfloat_gen.html
new file mode 100644
index 000000000..dfc5abe02
--- /dev/null
+++ b/addins/TestFloat-3e/doc/testfloat_gen.html
@@ -0,0 +1,367 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>testfloat_gen</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: <CODE>testfloat_gen</CODE></H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Overview</H2>
+
+<P>
+The <CODE>testfloat_gen</CODE> program generates test cases for testing that an
+implementation of floating-point arithmetic conforms to the IEEE Standard for
+Binary Floating-Point Arithmetic.
+<CODE>testfloat_gen</CODE> is part of the Berkeley TestFloat package, a small
+collection of programs for performing such tests.
+For general information about TestFloat, see file
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+A single execution of <CODE>testfloat_gen</CODE> generates test cases for only
+a single floating-point operation and associated options.
+The <CODE>testfloat_gen</CODE> program must be repeatedly executed to generate
+test cases for each operation to be tested.
+</P>
+
+<P>
+The <CODE>testfloat_gen</CODE> program writes the test cases it generates to
+standard output.
+This output can either be captured in a file through redirection, or be piped
+to another program that exercises a floating-point operation using the test
+cases as they are supplied.
+Depending on use, the total output from <CODE>testfloat_gen</CODE> can be
+large, so piping to another program may be the best choice to avoid using
+inordinate file space.
+The format of <CODE>testfloat_gen</CODE>&rsquo;s output is raw hexadecimal
+text, described in the section below titled <I>Output Format</I>.
+</P>
+
+
+<H2>Command Syntax</H2>
+
+<P>
+The <CODE>testfloat_gen</CODE> program is executed as a command in one of these
+forms:
+<BLOCKQUOTE>
+<PRE>
+testfloat_gen [&lt;<I>option</I>&gt;...] &lt;<I>type</I>&gt;
+testfloat_gen [&lt;<I>option</I>&gt;...] &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Square brackets (<CODE>[ ]</CODE>) denote optional arguments, and
+<CODE>&lt;<I>option</I>&gt;</CODE> is a supported option, documented below.
+A <CODE>testfloat_gen</CODE> command expects either a
+<CODE>&lt;<I>type</I>&gt;</CODE> specifying the type and number of outputs or a
+<CODE>&lt;<I>function</I>&gt;</CODE> naming a floating-point operation.
+If <CODE>testfloat_gen</CODE> is executed without any arguments, a summary of
+usage is written.
+</P>
+
+<P>
+A <CODE>&lt;<I>type</I>&gt;</CODE> can be one of the following:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+<TD><CODE>ui32</CODE></TD>
+<TD>unsigned <NOBR>32-bit</NOBR> integers</TD>
+</TR>
+<TR>
+<TD><CODE>ui64</CODE></TD>
+<TD>unsigned <NOBR>64-bit</NOBR> integers</TD>
+</TR>
+<TR>
+<TD><CODE>i32</CODE></TD>
+<TD>signed <NOBR>32-bit</NOBR> integers</TD>
+</TR>
+<TR>
+<TD><CODE>i64</CODE></TD>
+<TD>signed <NOBR>64-bit</NOBR> integers</TD>
+</TR>
+<TR>
+<TD><CODE>f16 [&lt;<I>num</I>&gt;]</CODE></TD>
+<TD>one or more <NOBR>16-bit</NOBR> half-precision floating-point values</TD>
+</TR>
+<TR>
+<TD><CODE>f32 [&lt;<I>num</I>&gt;]</CODE></TD>
+<TD>one or more <NOBR>32-bit</NOBR> single-precision floating-point values</TD>
+</TR>
+<TR>
+<TD><CODE>f64 [&lt;<I>num</I>&gt;]</CODE></TD>
+<TD>one or more <NOBR>64-bit</NOBR> double-precision floating-point values</TD>
+</TR>
+<TR>
+<TD><CODE>extF80 [&lt;<I>num</I>&gt;]&nbsp;&nbsp;&nbsp;</CODE></TD>
+<TD>one or more <NOBR>80-bit</NOBR> double-extended-precision floating-point
+values</TD>
+</TR>
+<TR>
+<TD><CODE>f128 [&lt;<I>num</I>&gt;]</CODE></TD>
+<TD>one or more <NOBR>128-bit</NOBR> quadruple-precision floating-point
+values</TD>
+</TR>
+</TABLE>
+</BLOCKQUOTE>
+Optional <CODE>&lt;<I>num</I>&gt;</CODE> is one of 1, 2, <NOBR>or 3</NOBR>.
+If a <CODE>&lt;<I>type</I>&gt;</CODE> is given without
+<CODE>&lt;<I>num</I>&gt;</CODE> (such as <CODE>ui32</CODE> or
+<CODE>f64</CODE>), <CODE>testfloat_gen</CODE> outputs a list of values of the
+specified type, one value per line, appropriate for testing a floating-point
+operation with exactly one operand of the given type.
+If a floating-point type and number are given (such as
+<NOBR><CODE>f32</CODE> <CODE>2</CODE></NOBR> or
+<NOBR><CODE>extF80</CODE> <CODE>1</CODE></NOBR>), <CODE>testfloat_gen</CODE>
+outputs the specified number of values per line, appropriate for testing a
+floating-point operation with that number of operands.
+Although the exact operation being tested is not specified, the test cases
+output by <CODE>testfloat_gen</CODE> cover all standard floating-point
+operations, to the degree explained in
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+If a <CODE>&lt;<I>function</I>&gt;</CODE> operation name is given, then each
+line of output from <CODE>testfloat_gen</CODE> contains not only the operands
+for that operation (as would be generated by an appropriate
+<CODE>&lt;<I>type</I>&gt;</CODE> argument) but also the expected results as
+determined by <CODE>testfloat_gen</CODE>&rsquo;s internal floating-point
+emulation (Berkeley SoftFloat).
+The available operation names are listed in
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+In all cases, floating-point operations have two results:
+first, a value, which may be floating-point, integer, or Boolean, and, second,
+the floating-point exception flags raised by the operation.
+If the output from a tested floating-point operation does not match the
+expected output specified by <CODE>testfloat_gen</CODE>, this may or may not
+indicate an error in the floating-point operation.
+For further explanation, see
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>,
+especially the section titled <I>Variations Allowed by the IEEE Floating-Point
+Standard</I>.
+</P>
+
+
+<H2>Options</H2>
+
+<P>
+The <CODE>testfloat_gen</CODE> program accepts several command options.
+If mutually contradictory options are given, the last one has priority.
+</P>
+
+<H3><CODE>-help</CODE></H3>
+
+<P>
+The <CODE>-help</CODE> option causes a summary of program usage to be written,
+after which the program exits.
+</P>
+
+<H3><CODE>-prefix &lt;<I>text</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-prefix</CODE> option causes <CODE>testfloat_gen</CODE> to write the
+supplied text argument verbatim as the first line of output before any test
+cases.
+This can be used, for example, to indicate to a downstream program what kind of
+test to perform for the test cases that follow.
+</P>
+
+<H3><CODE>-seed &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-seed</CODE> option sets the seed for the pseudo-random number
+generator used for generating test cases.
+The argument to <CODE>-seed</CODE> is a nonnegative integer.
+Executing the same <CODE>testfloat_gen</CODE> program with the same arguments
+(including the same pseudo-random number seed) should always generate the same
+sequence of test cases, whereas changing the pseudo-random number seed should
+result in a different sequence of test cases.
+The default seed number <NOBR>is 1</NOBR>.
+</P>
+
+<H3><CODE>-level &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-level</CODE> option sets the level of testing.
+The argument to <CODE>-level</CODE> can be either 1 <NOBR>or 2</NOBR>.
+The default is <NOBR>level 1</NOBR>.
+<NOBR>Level 2</NOBR> causes many more test cases to be generated, with better
+coverage, than <NOBR>level 1</NOBR>.
+</P>
+
+<H3><CODE>-n &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+Option <CODE>-n</CODE> specifies the number of test cases to generate.
+For each <CODE>&lt;<I>type</I>&gt;</CODE> or
+<CODE>&lt;<I>function</I>&gt;</CODE> and each testing level (set by
+<CODE>-level</CODE>), there is a minimum value that <CODE>testfloat_gen</CODE>
+will accept for <CODE>&lt;<I>num</I>&gt;</CODE>.
+If no <CODE>-n</CODE> option is given, the number of test cases generated by
+<CODE>testfloat_gen</CODE> equals the minimum value acceptable for the
+<CODE>-n</CODE> argument.
+Option <CODE>-n</CODE> cannot be used to reduce this number, but can increase
+it, without changing the testing level.
+</P>
+
+<H3><CODE>-forever</CODE></H3>
+
+<P>
+The <CODE>-forever</CODE> option causes test cases to be generated
+indefinitely, without limit (until the program is terminated by some external
+cause).
+The testing level is set to 2 by this option.
+</P>
+
+<H3><CODE>-precision32, -precision64, -precision80</CODE></H3>
+
+<P>
+When a <CODE>&lt;<I>function</I>&gt;</CODE> is specified that is an
+<NOBR>80-bit</NOBR> double-extended-precision operation affected by rounding
+precision control, the <CODE>-precision32</CODE> option sets the rounding
+precision to <NOBR>32 bits</NOBR>, equivalent to <NOBR>32-bit</NOBR>
+single-precision.
+Likewise, <CODE>-precision64</CODE> sets the rounding precision to
+<NOBR>64 bits</NOBR>, equivalent to <NOBR>64-bit</NOBR> double-precision, and
+<CODE>-precision80</CODE> sets the rounding precision to the full
+<NOBR>80 bits</NOBR> of the double-extended-precision format.
+All these options are ignored for operations not affected by rounding precision
+control.
+When rounding precision is applicable but not specified, the default is the
+full <NOBR>80 bits</NOBR>, same as <CODE>-precision80</CODE>.
+</P>
+
+<H3><CODE>-rnear_even, -rnear_maxMag, -rminMag, -rmin, -rmax, -rodd</CODE></H3>
+
+<P>
+When a <CODE>&lt;<I>function</I>&gt;</CODE> is specified that requires
+rounding, the <CODE>-rnear_even</CODE> option sets the rounding mode to
+nearest/even;
+<CODE>-rnear_maxMag</CODE> sets rounding to nearest/maximum magnitude
+(nearest-away);
+<CODE>-rminMag</CODE> sets rounding to minimum magnitude (toward zero);
+<CODE>-rmin</CODE> sets rounding to minimum (down, toward negative infinity);
+<CODE>-rmax</CODE> sets rounding to maximum (up, toward positive infinity);
+and <CODE>-rodd</CODE>, if supported, sets rounding to odd.
+These options are ignored for operations that are exact and thus do not round.
+When rounding mode is relevant but not specified, the default is to round to
+nearest/even, same as <CODE>-rnear_even</CODE>.
+</P>
+
+<H3><CODE>-tininessbefore, -tininessafter</CODE></H3>
+
+<P>
+When a <CODE>&lt;<I>function</I>&gt;</CODE> is specified that requires
+rounding, the <CODE>-tininessbefore</CODE> option indicates that tininess on
+underflow will be detected before rounding, while <CODE>-tininessafter</CODE>
+indicates that tininess on underflow will be detected after rounding.
+These options are ignored for operations that are exact and thus do not round.
+When the method of tininess detection matters but is not specified, the default
+is to detect tininess on underflow after rounding, same as
+<CODE>-tininessafter</CODE>.
+</P>
+
+<H3><CODE>-notexact, -exact</CODE></H3>
+
+<P>
+When a <CODE>&lt;<I>function</I>&gt;</CODE> is specified that rounds to an
+integer (either conversion to an integer type or a <CODE>roundToInt</CODE>
+operation), the <CODE>-notexact</CODE> option indicates that the <I>inexact</I>
+exception flag is never raised, while <CODE>-exact</CODE> indicates that the
+<I>inexact</I> exception flag is to be raised if the result is inexact.
+For other operations, these options are ignored.
+If neither option is specified, the default is not to raise the <I>inexact</I>
+exception flag when rounding to an integer, same as <CODE>-notexact</CODE>.
+</P>
+
+
+<H2>Output Format</H2>
+
+<P>
+For each test case generated, <CODE>testfloat_gen</CODE> writes a single line
+of text to standard output.
+When the <CODE>testfloat_gen</CODE> command is given a
+<CODE>&lt;<I>type</I>&gt;</CODE> argument, each test case consists of either
+one integer value or one, two, or three floating-point values.
+Each value is written to output as a raw hexadecimal number.
+When there is more than one value per line, they are separated by spaces.
+For example, output from executing
+<BLOCKQUOTE>
+<PRE>
+testfloat_gen f64 2
+</PRE>
+</BLOCKQUOTE>
+might look like this:
+<BLOCKQUOTE>
+<PRE>
+3F90EB5825D6851E C3E0080080000000
+41E3C00000000000 C182024F8AE474A8
+7FD80FFFFFFFFFFF 7FEFFFFFFFFFFF80
+3FFFED6A25C534BE 3CA1000000020000
+...
+</PRE>
+</BLOCKQUOTE>
+with each hexadecimal number being one <NOBR>64-bit</NOBR> floating-point
+value.
+Note that, for floating-point values, the sign and exponent are at the
+most-significant end of the number.
+Thus, for the first number on the first line above, the leading hexadecimal
+digits <CODE>3F9</CODE> are the sign and encoded exponent of the
+<NOBR>64-bit</NOBR> floating-point value, and the remaining digits are the
+encoded significand.
+</P>
+
+<P>
+When <CODE>testfloat_gen</CODE> is given a <CODE>&lt;<I>function</I>&gt;</CODE>
+operation name, each line of output has not only the operands for the operation
+but also the expected output, consisting of a result value and the exception
+flags that are raised.
+For example, the output from
+<BLOCKQUOTE>
+<PRE>
+testfloat_gen f64_add
+</PRE>
+</BLOCKQUOTE>
+could include these lines:
+<BLOCKQUOTE>
+<PRE>
+3F90EB5825D6851E C3E0080080000000 C3E0080080000000 01
+41E3C00000000000 C182024F8AE474A8 41E377F6C1D46E2D 01
+7FD80FFFFFFFFFFF 7FEFFFFFFFFFFF80 7FF0000000000000 05
+3FFFED6A25C534BE 3CA1000000020000 3FFFED6A25C534BF 01
+...
+</PRE>
+</BLOCKQUOTE>
+On each line, the first two numbers are the operands for the floating-point
+addition, and the third and fourth numbers are the expected floating-point
+result (the sum) and the exception flags raised.
+Exception flags are encoded with one bit per flag as follows:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+  <TD>bit 0<CODE>&nbsp;&nbsp;&nbsp;</CODE></TD>
+  <TD><I>inexact</I> exception</TD>
+</TR>
+<TR><TD>bit 1</TD><TD><I>underflow</I> exception</TD></TR>
+<TR><TD>bit 2</TD><TD><I>overflow</I> exception</TD></TR>
+<TR>
+  <TD>bit 3</TD>
+  <TD><I>infinite</I> exception (&ldquo;divide by zero&rdquo;)</TD>
+</TR>
+<TR><TD>bit 4</TD><TD><I>invalid</I> exception</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/testfloat_ver.html b/addins/TestFloat-3e/doc/testfloat_ver.html
new file mode 100644
index 000000000..83c6ea82d
--- /dev/null
+++ b/addins/TestFloat-3e/doc/testfloat_ver.html
@@ -0,0 +1,270 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>testfloat_ver</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: <CODE>testfloat_ver</CODE></H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Overview</H2>
+
+<P>
+The <CODE>testfloat_ver</CODE> program accepts test-case results obtained from
+exercising an implementation of floating-point arithmetic and verifies that
+those results conform to the IEEE Standard for Binary Floating-Point
+Arithmetic.
+<CODE>testfloat_ver</CODE> is part of the Berkeley TestFloat package, a small
+collection of programs for performing such tests.
+For general information about TestFloat, see file
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+A single execution of <CODE>testfloat_ver</CODE> verifies results for only a
+single floating-point operation and associated options.
+The <CODE>testfloat_ver</CODE> program must be repeatedly executed to verify
+results for each operation to be tested.
+</P>
+
+<P>
+The test cases to be verified are read by <CODE>testfloat_ver</CODE> from
+standard input.
+This input will typically be piped from another program that, for each test
+case, invokes the floating-point operation and writes out the results.
+The format of <CODE>testfloat_ver</CODE>&rsquo;s input is raw hexadecimal text,
+described in the section below titled <I>Input Format</I>.
+</P>
+
+<P>
+For each test case given to it, <CODE>testfloat_ver</CODE> examines the
+computed results and reports any unexpected results as likely errors.
+
+For more about the operation of <CODE>testfloat_ver</CODE> and how to interpret
+its output, refer to
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+
+<H2>Command Syntax</H2>
+
+<P>
+The <CODE>testfloat_ver</CODE> program is executed as a command with this
+syntax:
+<BLOCKQUOTE>
+<PRE>
+testfloat_ver [&lt;<I>option</I>&gt;...] &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Square brackets (<CODE>[ ]</CODE>) denote optional arguments,
+<CODE>&lt;<I>option</I>&gt;</CODE> is a supported option, and
+<CODE>&lt;<I>function</I>&gt;</CODE> is the name of a testable operation.
+The available options are documented below.
+The testable operation names are listed in
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+If <CODE>testfloat_ver</CODE> is executed without any arguments, a summary of
+usage is written.
+</P>
+
+
+<H2>Options</H2>
+
+<P>
+The <CODE>testfloat_ver</CODE> program accepts several command options.
+If mutually contradictory options are given, the last one has priority.
+</P>
+
+<H3><CODE>-help</CODE></H3>
+
+<P>
+The <CODE>-help</CODE> option causes a summary of program usage to be written,
+after which the program exits.
+</P>
+
+<H3><CODE>-errors &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-errors</CODE> option instructs <CODE>testfloat_ver</CODE> to report
+no more than the specified number of errors.
+The argument to <CODE>-errors</CODE> must be a nonnegative decimal integer.
+Once the specified number of error reports has been generated, the program
+exits.
+The default is <NOBR><CODE>-errors</CODE> <CODE>20</CODE></NOBR>.
+</P>
+
+<P>
+Against intuition, <NOBR><CODE>-errors</CODE> <CODE>0</CODE></NOBR> causes
+<CODE>testfloat_ver</CODE> to continue for any number of errors.
+</P>
+
+<H3><CODE>-checkNaNs</CODE></H3>
+
+<P>
+The <CODE>-checkNaNs</CODE> option causes <CODE>testfloat_ver</CODE> to verify
+the bitwise correctness of NaN results.
+In order for this option to be sensible, <CODE>testfloat_ver</CODE> must have
+been compiled so that its internal reference implementation of floating-point
+(Berkeley SoftFloat) generates the proper NaN results for the system being
+tested.
+</P>
+
+<H3><CODE>-checkInvInts</CODE></H3>
+
+<P>
+The <CODE>-checkInvInts</CODE> option causes <CODE>testfloat_ver</CODE> to
+verify the bitwise correctness of integer results of invalid operations.
+In order for this option to be sensible, <CODE>testfloat_ver</CODE> must have
+been compiled so that its internal reference implementation of floating-point
+(Berkeley SoftFloat) generates the proper integer results for the system being
+tested.
+</P>
+
+<H3><CODE>-checkAll</CODE></H3>
+
+<P>
+Enables both <CODE>-checkNaNs</CODE> and <CODE>-checkInvInts</CODE>.
+</P>
+
+<H3><CODE>-precision32, -precision64, -precision80</CODE></H3>
+
+<P>
+When <CODE>&lt;<I>function</I>&gt;</CODE> is an <NOBR>80-bit</NOBR>
+double-extended-precision operation affected by rounding precision control, the
+<CODE>-precision32</CODE> option indicates that the rounding precision should
+be <NOBR>32 bits</NOBR>, equivalent to <NOBR>32-bit</NOBR> single-precision.
+Likewise, <CODE>-precision64</CODE> indicates that the rounding precision
+should be <NOBR>64 bits</NOBR>, equivalent to <NOBR>64-bit</NOBR>
+double-precision, and <CODE>-precision80</CODE> indicates that the rounding
+precision should be the full <NOBR>80 bits</NOBR> of the
+double-extended-precision format.
+All these options are ignored for operations not affected by rounding precision
+control.
+When rounding precision is applicable but not specified, the default assumption
+is the full <NOBR>80 bits</NOBR>, same as <CODE>-precision80</CODE>.
+</P>
+
+<H3><CODE>-rnear_even, -rnear_maxMag, -rminMag, -rmin, -rmax, -rodd</CODE></H3>
+
+<P>
+When <CODE>&lt;<I>function</I>&gt;</CODE> is an operation that requires
+rounding, the <CODE>-rnear_even</CODE> option indicates that rounding should be
+to nearest/even, <CODE>-rnear_maxMag</CODE> indicates rounding to
+nearest/maximum magnitude (nearest-away), <CODE>-rminMag</CODE> indicates
+rounding to minimum magnitude (toward zero), <CODE>-rmin</CODE> indicates
+rounding to minimum (down, toward negative infinity), <CODE>-rmax</CODE>
+indicates rounding to maximum (up, toward positive infinity), and
+<CODE>-rodd</CODE>, if supported, indicates rounding to odd.
+These options are ignored for operations that are exact and thus do not round.
+When rounding mode is relevant but not specified, the default assumption is
+rounding to nearest/even, same as <CODE>-rnear_even</CODE>.
+</P>
+
+<H3><CODE>-tininessbefore, -tininessafter</CODE></H3>
+
+<P>
+When <CODE>&lt;<I>function</I>&gt;</CODE> is an operation that requires
+rounding, the <CODE>-tininessbefore</CODE> option indicates that tininess on
+underflow should be detected before rounding, while <CODE>-tininessafter</CODE>
+indicates that tininess on underflow should be detected after rounding.
+These options are ignored for operations that are exact and thus do not round.
+When the method of tininess detection matters but is not specified, the default
+assumption is that tininess should be detected after rounding, same as
+<CODE>-tininessafter</CODE>.
+</P>
+
+<H3><CODE>-notexact, -exact</CODE></H3>
+
+<P>
+When <CODE>&lt;<I>function</I>&gt;</CODE> is an operation that rounds to an
+integer (either conversion to an integer type or a <CODE>roundToInt</CODE>
+operation), the <CODE>-notexact</CODE> option indicates that the <I>inexact</I>
+exception flag should never be raised, while <CODE>-exact</CODE> indicates that
+the <I>inexact</I> exception flag should be raised when the result is inexact.
+For other operations, these options are ignored.
+If neither option is specified, the default assumption is that the
+<I>inexact</I> exception flag should not be raised when rounding to an integer,
+same as <CODE>-notexact</CODE>.
+</P>
+
+
+<H2>Input Format</H2>
+
+<P>
+For a given <CODE>&lt;<I>function</I>&gt;</CODE> argument, the input format
+expected by <CODE>testfloat_ver</CODE> is the same as the output generated by
+program
+<A HREF="testfloat_gen.html"><NOBR><CODE>testfloat_gen</CODE></NOBR></A> for
+the same argument.
+</P>
+
+<P>
+Input to <CODE>testfloat_ver</CODE> is expected to be text, with each line
+containing the data for one test case.
+The number of input lines thus equals the number of test cases.
+A single test case is organized as follows:  first are the operands for the
+operation, next is the result value obtained, and last is a number indicating
+the exception flags that were raised.
+These values are all expected to be provided as raw hexadecimal numbers
+separated on the line by spaces.
+For example, for the command
+<BLOCKQUOTE>
+<PRE>
+testfloat_ver f64_add
+</PRE>
+</BLOCKQUOTE>
+valid input could include these lines:
+<BLOCKQUOTE>
+<PRE>
+3F90EB5825D6851E C3E0080080000000 C3E0080080000000 01
+41E3C00000000000 C182024F8AE474A8 41E377F6C1D46E2D 01
+7FD80FFFFFFFFFFF 7FEFFFFFFFFFFF80 7FF0000000000000 05
+3FFFED6A25C534BE 3CA1000000020000 3FFFED6A25C534BF 01
+...
+</PRE>
+</BLOCKQUOTE>
+On each line above, the first two hexadecimal numbers represent the
+<NOBR>64-bit</NOBR> floating-point operands, the third hexadecimal number is
+the <NOBR>64-bit</NOBR> floating-point result of the operation (the sum), and
+the last hexadecimal number gives the exception flags that were raised by the
+operation.
+</P>
+
+<P>
+Note that, for floating-point values, the sign and exponent are at the
+most-significant end of the number.
+Thus, for the first number on the first line above, the leading hexadecimal
+digits <CODE>3F9</CODE> are the sign and encoded exponent of the
+<NOBR>64-bit</NOBR> floating-point value, and the remaining digits are the
+encoded significand.
+</P>
+
+<P>
+Exception flags are encoded with one bit per flag as follows:
+<BLOCKQUOTE>
+<TABLE CELLSPACING=0 CELLPADDING=0>
+<TR>
+  <TD>bit 0<CODE>&nbsp;&nbsp;&nbsp;</CODE></TD>
+  <TD><I>inexact</I> exception</TD>
+</TR>
+<TR><TD>bit 1</TD><TD><I>underflow</I> exception</TD></TR>
+<TR><TD>bit 2</TD><TD><I>overflow</I> exception</TD></TR>
+<TR>
+  <TD>bit 3</TD>
+  <TD><I>infinite</I> exception (&ldquo;divide by zero&rdquo;)</TD>
+</TR>
+<TR><TD>bit 4</TD><TD><I>invalid</I> exception</TD></TR>
+</TABLE>
+</BLOCKQUOTE>
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/testsoftfloat.html b/addins/TestFloat-3e/doc/testsoftfloat.html
new file mode 100644
index 000000000..cd8af6921
--- /dev/null
+++ b/addins/TestFloat-3e/doc/testsoftfloat.html
@@ -0,0 +1,236 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>testsoftfloat</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: <CODE>testsoftfloat</CODE></H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Overview</H2>
+
+<P>
+The <CODE>testsoftfloat</CODE> program tests that a build of the Berkeley
+SoftFloat library conforms to the IEEE Standard for Binary Floating-Point
+Arithmetic as expected.
+Program <CODE>testsoftfloat</CODE> is part of the Berkeley TestFloat package, a
+small collection of programs for performing such tests.
+For general information about TestFloat, as well as for basics about the
+operation of <CODE>testsoftfloat</CODE> and how to interpret its output, see
+file
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+Note that, even if there are no bugs in the source code for SoftFloat (not
+guaranteed), a build of SoftFloat might still fail due to an issue with the
+build process, such as an incompatible compiler option or a compiler bug.
+</P>
+
+<P>
+The <CODE>testsoftfloat</CODE> program will ordinarily test a function for all
+five rounding modes defined by the IEEE Floating-Point Standard, one after the
+other, plus possibly a sixth mode, <I>round to odd</I> (depending on the
+options selected when <CODE>testsoftfloat</CODE> was compiled).
+If an operation is not supposed to require rounding, it will by default be
+tested only with the rounding mode set to <CODE>near_even</CODE>
+(nearest/even).
+In the same way, if an operation is affected by the way in which underflow
+tininess is detected, <CODE>testsoftfloat</CODE> tests the function with
+tininess detected both before rounding and after rounding.
+For <NOBR>80-bit</NOBR> double-extended-precision operations affected by
+rounding precision control, <CODE>testsoftfloat</CODE> also tests the function
+for all three rounding precision modes, one after the other.
+Testing can be limited to a single rounding mode, a single tininess mode,
+and/or a single rounding precision with appropriate command-line options.
+</P>
+
+
+<H2>Command Syntax</H2>
+
+<P>
+The <CODE>testsoftfloat</CODE> program is executed as a command with this
+syntax:
+<BLOCKQUOTE>
+<PRE>
+testsoftfloat [&lt;<I>option</I>&gt;...] &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Square brackets (<CODE>[ ]</CODE>) denote optional arguments,
+<CODE>&lt;<I>option</I>&gt;</CODE> is a supported option, and
+<CODE>&lt;<I>function</I>&gt;</CODE> is the name of either a testable function
+or a function set.
+The available options and function sets are documented below.
+If <CODE>testsoftfloat</CODE> is executed without any arguments, a summary of
+usage is written.
+</P>
+
+
+<H2>Options</H2>
+
+<P>
+The <CODE>testsoftfloat</CODE> program accepts several command options.
+If mutually contradictory options are given, the last one has priority.
+</P>
+
+<H3><CODE>-help</CODE></H3>
+
+<P>
+The <CODE>-help</CODE> option causes a summary of program usage to be written,
+after which the program exits.
+</P>
+
+<H3><CODE>-seed &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-seed</CODE> option sets the seed for the pseudo-random number
+generator used for generating test cases.
+The argument to <CODE>-seed</CODE> is a nonnegative integer.
+Executing the same <CODE>testsoftfloat</CODE> program with the same arguments
+(including the same pseudo-random number seed) should always perform the same
+sequence of tests, whereas changing the pseudo-random number seed should result
+in a different sequence of tests.
+The default seed number <NOBR>is 1</NOBR>.
+</P>
+
+<H3><CODE>-level &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-level</CODE> option sets the level of testing.
+The argument to <CODE>-level</CODE> can be either 1 <NOBR>or 2</NOBR>.
+The default is <NOBR>level 1</NOBR>.
+Level 2 performs many more tests than <NOBR>level 1</NOBR> and thus can reveal
+bugs not found by <NOBR>level 1</NOBR>.
+</P>
+
+<H3><CODE>-errors &lt;<I>num</I>&gt;</CODE></H3>
+
+<P>
+The <CODE>-errors</CODE> option instructs <CODE>testsoftfloat</CODE> to report
+no more than the specified number of errors for any combination of function,
+rounding mode, etc.
+The argument to <CODE>-errors</CODE> must be a nonnegative decimal integer.
+Once the specified number of error reports has been generated,
+<CODE>testsoftfloat</CODE> ends the current test and begins the next one, if
+any.
+The default is <NOBR><CODE>-errors</CODE> <CODE>20</CODE></NOBR>.
+</P>
+
+<P>
+Against intuition, <NOBR><CODE>-errors</CODE> <CODE>0</CODE></NOBR> causes
+<CODE>testsoftfloat</CODE> to report every error it finds.
+</P>
+
+<H3><CODE>-errorstop</CODE></H3>
+
+<P>
+The <CODE>-errorstop</CODE> option causes the program to exit after the first
+function for which any errors are reported.
+</P>
+
+<H3><CODE>-forever</CODE></H3>
+
+<P>
+The <CODE>-forever</CODE> option causes a single function to be repeatedly
+tested.
+Only one rounding mode and/or rounding precision can be tested in a single
+execution.
+If not specified, the rounding mode defaults to nearest/even.
+For <NOBR>80-bit</NOBR> double-extended-precision functions, the rounding
+precision defaults to full double-extended precision.
+The testing level is set to 2 by this option.
+</P>
+
+<H3><CODE>-precision32, -precision64, -precision80</CODE></H3>
+
+<P>
+For <NOBR>80-bit</NOBR> double-extended-precision funcions affected by
+rounding precision control, the <CODE>-precision32</CODE> option restricts
+testing to only the cases in which the rounding precision is
+<NOBR>32 bits</NOBR>, equivalent to <NOBR>32-bit</NOBR> single-precision.
+The other rounding precision choices are not tested.
+Likewise, <CODE>-precision64</CODE> fixes the rounding precision to
+<NOBR>64 bits</NOBR>, equivalent to <NOBR>64-bit</NOBR> double-precision;
+and <CODE>-precision80</CODE> fixes the rounding precision to the full
+<NOBR>80 bits</NOBR> of the double-extended-precision format.
+All these options are ignored for operations not affected by rounding precision
+control.
+</P>
+
+<H3><CODE>-rnear_even, -rnear_maxMag, -rminMag, -rmin, -rmax, -rodd</CODE></H3>
+
+<P>
+The <CODE>-rnear_even</CODE> option restricts testing to only the cases in
+which the rounding mode is nearest/even.
+The other rounding mode choices are not tested.
+Likewise, <CODE>-rnear_maxMag</CODE> forces rounding to nearest/maximum
+magnitude (nearest-away), <CODE>-rminMag</CODE> forces rounding to minimum
+magnitude (toward zero), <CODE>-rmin</CODE> forces rounding to minimum (down,
+toward negative infinity), <CODE>-rmax</CODE> forces rounding to maximum (up,
+toward positive infinity), and <CODE>-rodd</CODE>, if supported, forces
+rounding to odd.
+These options are ignored for operations that are exact and thus do not round.
+</P>
+
+<H3><CODE>-tininessbefore, -tininessafter</CODE></H3>
+
+<P>
+The <CODE>-tininessbefore</CODE> option restricts testing to only the cases in
+which tininess on underflow is detected before rounding.
+Likewise, <CODE>-tininessafter</CODE> restricts testing to only the cases in
+which tininess on underflow is detected after rounding.
+</P>
+
+<H3><CODE>-notexact, -exact</CODE></H3>
+
+<P>
+For functions that round to an integer (conversions to integer types and the
+<CODE>roundToInt</CODE> functions), the <CODE>-notexact</CODE> option restricts
+testing to only the cases for which the <CODE><I>exact</I></CODE> operand
+(specifying whether the <I>inexact</I> exception flag may be raised) is
+<CODE>false</CODE>.
+Likewise, the <CODE>-exact</CODE> option restricts testing to only the cases
+for which the <CODE><I>exact</I></CODE> operand is <CODE>true</CODE>.
+</P>
+
+
+<H2>Function Sets</H2>
+
+<P>
+Just as <CODE>testsoftfloat</CODE> can test a function for all five or six
+rounding modes in sequence, multiple functions can be tested with a single
+execution of <CODE>testsoftfloat</CODE>.
+Two sets are recognized:  <CODE>-all1</CODE> and <CODE>-all2</CODE>.
+The set <CODE>-all1</CODE> is all one-operand operations, while
+<CODE>-all2</CODE> is all two-operand operations.
+A function set is used in place of a function name in the
+<CODE>testsoftfloat</CODE> command line, such as
+<BLOCKQUOTE>
+<PRE>
+testsoftfloat [&lt;<I>option</I>&gt;...] -all1
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+For the purpose of deciding the number of operands of an operation, any
+<CODE><I>roundingMode</I></CODE> and <CODE><I>exact</I></CODE> arguments are
+ignored.
+(Such arguments specify the rounding mode and whether the <I>inexact</I>
+exception flag may be raised, respectively.)
+Thus, functions that convert to integer type and the <CODE>roundToInt</CODE>
+functions are included in the set of one-operand operations tested by
+<CODE>-all1</CODE>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/doc/timesoftfloat.html b/addins/TestFloat-3e/doc/timesoftfloat.html
new file mode 100644
index 000000000..bb7264784
--- /dev/null
+++ b/addins/TestFloat-3e/doc/timesoftfloat.html
@@ -0,0 +1,196 @@
+
+<HTML>
+
+<HEAD>
+<TITLE>timesoftfloat</TITLE>
+</HEAD>
+
+<BODY>
+
+<H1>Berkeley TestFloat Release 3e: <CODE>timesoftfloat</CODE></H1>
+
+<P>
+John R. Hauser<BR>
+2018 January 20<BR>
+</P>
+
+
+<H2>Overview</H2>
+
+<P>
+The <CODE>timesoftfloat</CODE> program provides a simple way to evaluate the
+speed of the floating-point operations of the Berkeley SoftFloat library.
+Program <CODE>timesoftfloat</CODE> is included with the Berkeley TestFloat
+package, a small collection of programs for testing that an implementation of
+floating-point conforms to the IEEE Standard for Binary Floating-Point
+Arithmetic.
+Although <CODE>timesoftfloat</CODE> does not test floating-point correctness
+like the other TestFloat programs, nevertheless <CODE>timesoftfloat</CODE> is a
+partner to TestFloat&rsquo;s <CODE>testsoftfloat</CODE> program.
+For more about TestFloat generally and <CODE>testsoftfloat</CODE> specifically,
+see file
+<A HREF="TestFloat-general.html"><NOBR><CODE>TestFloat-general.html</CODE></NOBR></A>.
+</P>
+
+<P>
+Ordinarily, <CODE>timesoftfloat</CODE> will measure a function&rsquo;s speed
+separately for each of the five rounding modes defined by the IEEE
+Floating-Point Standard, one after the other, plus possibly a sixth mode,
+<I>round to odd</I> (depending on the options selected when
+<CODE>timesoftfloat</CODE> was compiled).
+If an operation is not supposed to require rounding, it will by default be
+timed only with the rounding mode set to <CODE>near_even</CODE> (nearest/even).
+In the same way, if an operation is affected by the way in which underflow
+tininess is detected, <CODE>timesoftfloat</CODE> times the function with
+tininess detected both before rounding and after rounding.
+For <NOBR>80-bit</NOBR> double-extended-precision operations affected by
+rounding precision control, <CODE>timesoftfloat</CODE> also times the function
+for each of the three rounding precision modes, one after the other.
+Evaluation of a function can be limited to a single rounding mode, a single
+tininess mode, and/or a single rounding precision with appropriate command-line
+options.
+</P>
+
+<P>
+For each function and mode evaluated, <CODE>timesoftfloat</CODE> reports the
+measured speed of the function in Mop/s, or &ldquo;millions of operations per
+second&rdquo;.
+The speeds reported by <CODE>timesoftfloat</CODE> may be affected somewhat by
+other software executing at the same time as <CODE>timesoftfloat</CODE>.
+Be aware also that the exact execution time of any SoftFloat function depends
+partly on the values of arguments and the state of the processor&rsquo;s caches
+at the time the function is called.
+Your actual experience with SoftFloat may differ from the speeds reported by
+<CODE>timesoftfloat</CODE> for all these reasons.
+</P>
+
+<P>
+Note that the remainder operations for larger formats (<CODE>f64_rem</CODE>,
+<CODE>extF80_rem</CODE>, and <CODE>f128_rem</CODE>) can be markedly slower than
+other operations, particularly for double-extended-precision
+(<CODE>extF80_rem</CODE>) and quadruple precision (<CODE>f128_rem</CODE>).
+This is inherent to the remainder operation itself and is not a failing of the
+SoftFloat implementation.
+</P>
+
+
+<H2>Command Syntax</H2>
+
+<P>
+The <CODE>timesoftfloat</CODE> program is executed as a command with this
+syntax:
+<BLOCKQUOTE>
+<PRE>
+timesoftfloat [&lt;<I>option</I>&gt;...] &lt;<I>function</I>&gt;
+</PRE>
+</BLOCKQUOTE>
+Square brackets (<CODE>[ ]</CODE>) denote optional arguments,
+<CODE>&lt;<I>option</I>&gt;</CODE> is a supported option, and
+<CODE>&lt;<I>function</I>&gt;</CODE> is the name of either a testable function
+or a function set.
+The available options and function sets are documented below.
+If <CODE>timesoftfloat</CODE> is executed without any arguments, a summary of
+usage is written.
+</P>
+
+
+<H2>Options</H2>
+
+<P>
+The <CODE>timesoftfloat</CODE> program accepts several command options.
+If mutually contradictory options are given, the last one has priority.
+</P>
+
+<H3><CODE>-help</CODE></H3>
+
+<P>
+The <CODE>-help</CODE> option causes a summary of program usage to be written,
+after which the program exits.
+</P>
+
+<H3><CODE>-precision32, -precision64, -precision80</CODE></H3>
+
+<P>
+For <NOBR>80-bit</NOBR> double-extended-precision funcions affected by
+rounding precision control, the <CODE>-precision32</CODE> option restricts
+timing of an operation to only the cases in which the rounding precision is
+<NOBR>32 bits</NOBR>, equivalent to <NOBR>32-bit</NOBR> single-precision.
+Other rounding precision choices are not timed.
+Likewise, <CODE>-precision64</CODE> fixes the rounding precision to
+<NOBR>64 bits</NOBR>, equivalent to <NOBR>64-bit</NOBR> double-precision;
+and <CODE>-precision80</CODE> fixes the rounding precision to the full
+<NOBR>80 bits</NOBR> of the double-extended-precision format.
+All these options are ignored for operations not affected by rounding precision
+control.
+</P>
+
+<H3><CODE>-rnear_even, -rnear_maxMag, -rminMag, -rmin, -rmax, -rodd</CODE></H3>
+
+<P>
+The <CODE>-rnear_even</CODE> option restricts timing of an operation to only
+the cases in which the rounding mode is nearest/even.
+Other rounding mode choices are not timed.
+Likewise, <CODE>-rnear_maxMag</CODE> forces rounding to nearest/maximum
+magnitude (nearest-away), <CODE>-rminMag</CODE> forces rounding to minimum
+magnitude (toward zero), <CODE>-rmin</CODE> forces rounding to minimum (down,
+toward negative infinity), <CODE>-rmax</CODE> forces rounding to maximum (up,
+toward positive infinity), and <CODE>-rodd</CODE>, if supported, forces
+rounding to odd.
+These options are ignored for operations that are exact and thus do not round.
+</P>
+
+<H3><CODE>-tininessbefore, -tininessafter</CODE></H3>
+
+<P>
+The <CODE>-tininessbefore</CODE> option restricts timing of an operation to
+only the cases in which tininess on underflow is detected before rounding.
+Likewise, <CODE>-tininessafter</CODE> restricts measurement to only the cases
+in which tininess on underflow is detected after rounding.
+</P>
+
+<H3><CODE>-notexact, -exact</CODE></H3>
+
+<P>
+For functions that round to an integer (conversions to integer types and the
+<CODE>roundToInt</CODE> functions), the <CODE>-notexact</CODE> option restricts
+timing of an operation to only the cases for which the
+<CODE><I>exact</I></CODE> operand (specifying whether the <I>inexact</I>
+exception flag may be raised) is <CODE>false</CODE>.
+Likewise, the <CODE>-exact</CODE> option restricts measurement to only the
+cases for which the <CODE><I>exact</I></CODE> operand is <CODE>true</CODE>.
+</P>
+
+
+<H2>Function Sets</H2>
+
+<P>
+Just as <CODE>timesoftfloat</CODE> can time a function for all five or six
+rounding modes in sequence, multiple functions can be timed with a single
+execution of <CODE>timesoftfloat</CODE>.
+Three sets are recognized:
+<CODE>-all1</CODE>, <CODE>-all2</CODE>, and <CODE>-all</CODE>.
+The set <CODE>-all1</CODE> is all one-operand operations, <CODE>-all2</CODE> is
+all two-operand operations, and <CODE>-all</CODE> is obviously all operations.
+A function set is used in place of a function name in the
+<CODE>timesoftfloat</CODE> command line, such as
+<BLOCKQUOTE>
+<PRE>
+timesoftfloat [&lt;<I>option</I>&gt;...] -all1
+</PRE>
+</BLOCKQUOTE>
+</P>
+
+<P>
+For the purpose of deciding the number of operands of an operation, any
+<CODE><I>roundingMode</I></CODE> and <CODE><I>exact</I></CODE> arguments are
+ignored.
+(Such arguments specify the rounding mode and whether the <I>inexact</I>
+exception flag may be raised, respectively.)
+Thus, functions that convert to integer type and the <CODE>roundToInt</CODE>
+functions are included in the set of one-operand operations timed by
+<CODE>-all1</CODE>.
+</P>
+
+
+</BODY>
+
diff --git a/addins/TestFloat-3e/source/fail.c b/addins/TestFloat-3e/source/fail.c
new file mode 100644
index 000000000..dae6c6422
--- /dev/null
+++ b/addins/TestFloat-3e/source/fail.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "platform.h"
+#include "fail.h"
+
+char *fail_programName = "";
+
+void fail( const char *messagePtr, ... )
+{
+    va_list varArgs;
+
+    fflush( 0 );
+    fprintf( stderr, "%s: ", fail_programName );
+    va_start( varArgs, messagePtr );
+    vfprintf( stderr, messagePtr, varArgs );
+    va_end( varArgs );
+    fputs( ".\n", stderr );
+    exit( EXIT_FAILURE );
+
+}
+
diff --git a/addins/TestFloat-3e/source/fail.h b/addins/TestFloat-3e/source/fail.h
new file mode 100644
index 000000000..0f1f48f78
--- /dev/null
+++ b/addins/TestFloat-3e/source/fail.h
@@ -0,0 +1,41 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+extern char *fail_programName;
+
+void fail( const char *, ... );
+
diff --git a/addins/TestFloat-3e/source/functionInfos.c b/addins/TestFloat-3e/source/functionInfos.c
new file mode 100644
index 000000000..e4d25e3fd
--- /dev/null
+++ b/addins/TestFloat-3e/source/functionInfos.c
@@ -0,0 +1,290 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "functions.h"
+
+#define ARG_1      FUNC_ARG_UNARY
+#define ARG_2      FUNC_ARG_BINARY
+#define ARG_R      FUNC_ARG_ROUNDINGMODE
+#define ARG_E      FUNC_ARG_EXACT
+#define EFF_P      FUNC_EFF_ROUNDINGPRECISION
+#define EFF_R      FUNC_EFF_ROUNDINGMODE
+#define EFF_T      FUNC_EFF_TININESSMODE
+#define EFF_T_REDP FUNC_EFF_TININESSMODE_REDUCEDPREC
+
+/*----------------------------------------------------------------------------
+| Warning:  This array must match the list of macros defined in "functions.h".
+*----------------------------------------------------------------------------*/
+const struct functionInfo functionInfos[NUM_FUNCTIONS] = {
+    { 0, 0 },
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    { "ui32_to_f16",    ARG_1 | EFF_R },
+#endif
+    { "ui32_to_f32",    ARG_1 | EFF_R },
+#ifdef FLOAT64
+    { "ui32_to_f64",    ARG_1         },
+#endif
+#ifdef EXTFLOAT80
+    { "ui32_to_extF80", ARG_1         },
+#endif
+#ifdef FLOAT128
+    { "ui32_to_f128",   ARG_1         },
+#endif
+#ifdef FLOAT16
+    { "ui64_to_f16",    ARG_1 | EFF_R },
+#endif
+    { "ui64_to_f32",    ARG_1 | EFF_R },
+#ifdef FLOAT64
+    { "ui64_to_f64",    ARG_1 | EFF_R },
+#endif
+#ifdef EXTFLOAT80
+    { "ui64_to_extF80", ARG_1         },
+#endif
+#ifdef FLOAT128
+    { "ui64_to_f128",   ARG_1         },
+#endif
+#ifdef FLOAT16
+    { "i32_to_f16",     ARG_1 | EFF_R },
+#endif
+    { "i32_to_f32",     ARG_1 | EFF_R },
+#ifdef FLOAT64
+    { "i32_to_f64",     ARG_1         },
+#endif
+#ifdef EXTFLOAT80
+    { "i32_to_extF80",  ARG_1         },
+#endif
+#ifdef FLOAT128
+    { "i32_to_f128",    ARG_1         },
+#endif
+#ifdef FLOAT16
+    { "i64_to_f16",     ARG_1 | EFF_R },
+#endif
+    { "i64_to_f32",     ARG_1 | EFF_R },
+#ifdef FLOAT64
+    { "i64_to_f64",     ARG_1 | EFF_R },
+#endif
+#ifdef EXTFLOAT80
+    { "i64_to_extF80",  ARG_1         },
+#endif
+#ifdef FLOAT128
+    { "i64_to_f128",    ARG_1         },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    { "f16_to_ui32", ARG_1 | ARG_R | ARG_E },
+    { "f16_to_ui64", ARG_1 | ARG_R | ARG_E },
+    { "f16_to_i32",  ARG_1 | ARG_R | ARG_E },
+    { "f16_to_i64",  ARG_1 | ARG_R | ARG_E },
+    { "f16_to_ui32_r_minMag", ARG_1 | ARG_E },
+    { "f16_to_ui64_r_minMag", ARG_1 | ARG_E },
+    { "f16_to_i32_r_minMag",  ARG_1 | ARG_E },
+    { "f16_to_i64_r_minMag",  ARG_1 | ARG_E },
+    { "f16_to_f32",    ARG_1 },
+#ifdef FLOAT64
+    { "f16_to_f64",    ARG_1 },
+#endif
+#ifdef EXTFLOAT80
+    { "f16_to_extF80", ARG_1 },
+#endif
+#ifdef FLOAT128
+    { "f16_to_f128",   ARG_1 },
+#endif
+    { "f16_roundToInt", ARG_1 | ARG_R | ARG_E },
+    { "f16_add",          ARG_2 | EFF_R         },
+    { "f16_sub",          ARG_2 | EFF_R         },
+    { "f16_mul",          ARG_2 | EFF_R | EFF_T },
+    { "f16_mulAdd",               EFF_R | EFF_T },
+    { "f16_div",          ARG_2 | EFF_R         },
+    { "f16_rem",          ARG_2                 },
+    { "f16_sqrt",         ARG_1 | EFF_R         },
+    { "f16_eq",           ARG_2                 },
+    { "f16_le",           ARG_2                 },
+    { "f16_lt",           ARG_2                 },
+    { "f16_eq_signaling", ARG_2                 },
+    { "f16_le_quiet",     ARG_2                 },
+    { "f16_lt_quiet",     ARG_2                 },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    { "f32_to_ui32", ARG_1 | ARG_R | ARG_E },
+    { "f32_to_ui64", ARG_1 | ARG_R | ARG_E },
+    { "f32_to_i32",  ARG_1 | ARG_R | ARG_E },
+    { "f32_to_i64",  ARG_1 | ARG_R | ARG_E },
+    { "f32_to_ui32_r_minMag", ARG_1 | ARG_E },
+    { "f32_to_ui64_r_minMag", ARG_1 | ARG_E },
+    { "f32_to_i32_r_minMag",  ARG_1 | ARG_E },
+    { "f32_to_i64_r_minMag",  ARG_1 | ARG_E },
+#ifdef FLOAT16
+    { "f32_to_f16", ARG_1 | EFF_R | EFF_T },
+#endif
+#ifdef FLOAT64
+    { "f32_to_f64",    ARG_1 },
+#endif
+#ifdef EXTFLOAT80
+    { "f32_to_extF80", ARG_1 },
+#endif
+#ifdef FLOAT128
+    { "f32_to_f128",   ARG_1 },
+#endif
+    { "f32_roundToInt", ARG_1 | ARG_R | ARG_E },
+    { "f32_add",          ARG_2 | EFF_R         },
+    { "f32_sub",          ARG_2 | EFF_R         },
+    { "f32_mul",          ARG_2 | EFF_R | EFF_T },
+    { "f32_mulAdd",               EFF_R | EFF_T },
+    { "f32_div",          ARG_2 | EFF_R         },
+    { "f32_rem",          ARG_2                 },
+    { "f32_sqrt",         ARG_1 | EFF_R         },
+    { "f32_eq",           ARG_2                 },
+    { "f32_le",           ARG_2                 },
+    { "f32_lt",           ARG_2                 },
+    { "f32_eq_signaling", ARG_2                 },
+    { "f32_le_quiet",     ARG_2                 },
+    { "f32_lt_quiet",     ARG_2                 },
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT64
+    { "f64_to_ui32", ARG_1 | ARG_R | ARG_E },
+    { "f64_to_ui64", ARG_1 | ARG_R | ARG_E },
+    { "f64_to_i32",  ARG_1 | ARG_R | ARG_E },
+    { "f64_to_i64",  ARG_1 | ARG_R | ARG_E },
+    { "f64_to_ui32_r_minMag", ARG_1 | ARG_E },
+    { "f64_to_ui64_r_minMag", ARG_1 | ARG_E },
+    { "f64_to_i32_r_minMag",  ARG_1 | ARG_E },
+    { "f64_to_i64_r_minMag",  ARG_1 | ARG_E },
+#ifdef FLOAT16
+    { "f64_to_f16", ARG_1 | EFF_R | EFF_T },
+#endif
+    { "f64_to_f32", ARG_1 | EFF_R | EFF_T },
+#ifdef EXTFLOAT80
+    { "f64_to_extF80", ARG_1 },
+#endif
+#ifdef FLOAT128
+    { "f64_to_f128",   ARG_1 },
+#endif
+    { "f64_roundToInt", ARG_1 | ARG_R | ARG_E },
+    { "f64_add",          ARG_2 | EFF_R         },
+    { "f64_sub",          ARG_2 | EFF_R         },
+    { "f64_mul",          ARG_2 | EFF_R | EFF_T },
+    { "f64_mulAdd",               EFF_R | EFF_T },
+    { "f64_div",          ARG_2 | EFF_R         },
+    { "f64_rem",          ARG_2                 },
+    { "f64_sqrt",         ARG_1 | EFF_R         },
+    { "f64_eq",           ARG_2                 },
+    { "f64_le",           ARG_2                 },
+    { "f64_lt",           ARG_2                 },
+    { "f64_eq_signaling", ARG_2                 },
+    { "f64_le_quiet",     ARG_2                 },
+    { "f64_lt_quiet",     ARG_2                 },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+    { "extF80_to_ui32", ARG_1 | ARG_R | ARG_E },
+    { "extF80_to_ui64", ARG_1 | ARG_R | ARG_E },
+    { "extF80_to_i32",  ARG_1 | ARG_R | ARG_E },
+    { "extF80_to_i64",  ARG_1 | ARG_R | ARG_E },
+    { "extF80_to_ui32_r_minMag", ARG_1 | ARG_E },
+    { "extF80_to_ui64_r_minMag", ARG_1 | ARG_E },
+    { "extF80_to_i32_r_minMag",  ARG_1 | ARG_E },
+    { "extF80_to_i64_r_minMag",  ARG_1 | ARG_E },
+#ifdef FLOAT16
+    { "extF80_to_f16", ARG_1 | EFF_R | EFF_T },
+#endif
+    { "extF80_to_f32", ARG_1 | EFF_R | EFF_T },
+#ifdef FLOAT64
+    { "extF80_to_f64", ARG_1 | EFF_R | EFF_T },
+#endif
+#ifdef FLOAT128
+    { "extF80_to_f128", ARG_1 },
+#endif
+    { "extF80_roundToInt", ARG_1 | ARG_R | ARG_E },
+    { "extF80_add",          ARG_2 | EFF_P | EFF_R         | EFF_T_REDP },
+    { "extF80_sub",          ARG_2 | EFF_P | EFF_R         | EFF_T_REDP },
+    { "extF80_mul",          ARG_2 | EFF_P | EFF_R | EFF_T | EFF_T_REDP },
+    { "extF80_div",          ARG_2 | EFF_P | EFF_R         | EFF_T_REDP },
+    { "extF80_rem",          ARG_2                                      },
+    { "extF80_sqrt",         ARG_1 | EFF_P | EFF_R                      },
+    { "extF80_eq",           ARG_2                                      },
+    { "extF80_le",           ARG_2                                      },
+    { "extF80_lt",           ARG_2                                      },
+    { "extF80_eq_signaling", ARG_2                                      },
+    { "extF80_le_quiet",     ARG_2                                      },
+    { "extF80_lt_quiet",     ARG_2                                      },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT128
+    { "f128_to_ui32", ARG_1 | ARG_R | ARG_E },
+    { "f128_to_ui64", ARG_1 | ARG_R | ARG_E },
+    { "f128_to_i32",  ARG_1 | ARG_R | ARG_E },
+    { "f128_to_i64",  ARG_1 | ARG_R | ARG_E },
+    { "f128_to_ui32_r_minMag", ARG_1 | ARG_E },
+    { "f128_to_ui64_r_minMag", ARG_1 | ARG_E },
+    { "f128_to_i32_r_minMag",  ARG_1 | ARG_E },
+    { "f128_to_i64_r_minMag",  ARG_1 | ARG_E },
+#ifdef FLOAT16
+    { "f128_to_f16",    ARG_1 | EFF_R | EFF_T },
+#endif
+    { "f128_to_f32",    ARG_1 | EFF_R | EFF_T },
+#ifdef FLOAT64
+    { "f128_to_f64",    ARG_1 | EFF_R | EFF_T },
+#endif
+#ifdef EXTFLOAT80
+    { "f128_to_extF80", ARG_1 | EFF_R | EFF_T },
+#endif
+    { "f128_roundToInt", ARG_1 | ARG_R | ARG_E },
+    { "f128_add",          ARG_2 | EFF_R         },
+    { "f128_sub",          ARG_2 | EFF_R         },
+    { "f128_mul",          ARG_2 | EFF_R | EFF_T },
+    { "f128_mulAdd",               EFF_R | EFF_T },
+    { "f128_div",          ARG_2 | EFF_R         },
+    { "f128_rem",          ARG_2                 },
+    { "f128_sqrt",         ARG_1 | EFF_R         },
+    { "f128_eq",           ARG_2                 },
+    { "f128_le",           ARG_2                 },
+    { "f128_lt",           ARG_2                 },
+    { "f128_eq_signaling", ARG_2                 },
+    { "f128_le_quiet",     ARG_2                 },
+    { "f128_lt_quiet",     ARG_2                 },
+#endif
+};
+
diff --git a/addins/TestFloat-3e/source/functions.h b/addins/TestFloat-3e/source/functions.h
new file mode 100644
index 000000000..85eaaf8be
--- /dev/null
+++ b/addins/TestFloat-3e/source/functions.h
@@ -0,0 +1,324 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+| Warning:  This list must match the contents of "functionInfos.c".
+*----------------------------------------------------------------------------*/
+enum {
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    UI32_TO_F16 = 1,
+    UI32_TO_F32,
+#else
+    UI32_TO_F32 = 1,
+#endif
+#ifdef FLOAT64
+    UI32_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    UI32_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    UI32_TO_F128,
+#endif
+#ifdef FLOAT16
+    UI64_TO_F16,
+#endif
+    UI64_TO_F32,
+#ifdef FLOAT64
+    UI64_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    UI64_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    UI64_TO_F128,
+#endif
+#ifdef FLOAT16
+    I32_TO_F16,
+#endif
+    I32_TO_F32,
+#ifdef FLOAT64
+    I32_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    I32_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    I32_TO_F128,
+#endif
+#ifdef FLOAT16
+    I64_TO_F16,
+#endif
+    I64_TO_F32,
+#ifdef FLOAT64
+    I64_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    I64_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    I64_TO_F128,
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    F16_TO_UI32,
+    F16_TO_UI64,
+    F16_TO_I32,
+    F16_TO_I64,
+    F16_TO_UI32_R_MINMAG,
+    F16_TO_UI64_R_MINMAG,
+    F16_TO_I32_R_MINMAG,
+    F16_TO_I64_R_MINMAG,
+    F16_TO_F32,
+#ifdef FLOAT64
+    F16_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    F16_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    F16_TO_F128,
+#endif
+    F16_ROUNDTOINT,
+    F16_ADD,
+    F16_SUB,
+    F16_MUL,
+    F16_MULADD,
+    F16_DIV,
+    F16_REM,
+    F16_SQRT,
+    F16_EQ,
+    F16_LE,
+    F16_LT,
+    F16_EQ_SIGNALING,
+    F16_LE_QUIET,
+    F16_LT_QUIET,
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    F32_TO_UI32,
+    F32_TO_UI64,
+    F32_TO_I32,
+    F32_TO_I64,
+    F32_TO_UI32_R_MINMAG,
+    F32_TO_UI64_R_MINMAG,
+    F32_TO_I32_R_MINMAG,
+    F32_TO_I64_R_MINMAG,
+#ifdef FLOAT16
+    F32_TO_F16,
+#endif
+#ifdef FLOAT64
+    F32_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    F32_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    F32_TO_F128,
+#endif
+    F32_ROUNDTOINT,
+    F32_ADD,
+    F32_SUB,
+    F32_MUL,
+    F32_MULADD,
+    F32_DIV,
+    F32_REM,
+    F32_SQRT,
+    F32_EQ,
+    F32_LE,
+    F32_LT,
+    F32_EQ_SIGNALING,
+    F32_LE_QUIET,
+    F32_LT_QUIET,
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT64
+    F64_TO_UI32,
+    F64_TO_UI64,
+    F64_TO_I32,
+    F64_TO_I64,
+    F64_TO_UI32_R_MINMAG,
+    F64_TO_UI64_R_MINMAG,
+    F64_TO_I32_R_MINMAG,
+    F64_TO_I64_R_MINMAG,
+#ifdef FLOAT16
+    F64_TO_F16,
+#endif
+    F64_TO_F32,
+#ifdef EXTFLOAT80
+    F64_TO_EXTF80,
+#endif
+#ifdef FLOAT128
+    F64_TO_F128,
+#endif
+    F64_ROUNDTOINT,
+    F64_ADD,
+    F64_SUB,
+    F64_MUL,
+    F64_MULADD,
+    F64_DIV,
+    F64_REM,
+    F64_SQRT,
+    F64_EQ,
+    F64_LE,
+    F64_LT,
+    F64_EQ_SIGNALING,
+    F64_LE_QUIET,
+    F64_LT_QUIET,
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+    EXTF80_TO_UI32,
+    EXTF80_TO_UI64,
+    EXTF80_TO_I32,
+    EXTF80_TO_I64,
+    EXTF80_TO_UI32_R_MINMAG,
+    EXTF80_TO_UI64_R_MINMAG,
+    EXTF80_TO_I32_R_MINMAG,
+    EXTF80_TO_I64_R_MINMAG,
+#ifdef FLOAT16
+    EXTF80_TO_F16,
+#endif
+    EXTF80_TO_F32,
+#ifdef FLOAT64
+    EXTF80_TO_F64,
+#endif
+#ifdef FLOAT128
+    EXTF80_TO_F128,
+#endif
+    EXTF80_ROUNDTOINT,
+    EXTF80_ADD,
+    EXTF80_SUB,
+    EXTF80_MUL,
+    EXTF80_DIV,
+    EXTF80_REM,
+    EXTF80_SQRT,
+    EXTF80_EQ,
+    EXTF80_LE,
+    EXTF80_LT,
+    EXTF80_EQ_SIGNALING,
+    EXTF80_LE_QUIET,
+    EXTF80_LT_QUIET,
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT128
+    F128_TO_UI32,
+    F128_TO_UI64,
+    F128_TO_I32,
+    F128_TO_I64,
+    F128_TO_UI32_R_MINMAG,
+    F128_TO_UI64_R_MINMAG,
+    F128_TO_I32_R_MINMAG,
+    F128_TO_I64_R_MINMAG,
+#ifdef FLOAT16
+    F128_TO_F16,
+#endif
+    F128_TO_F32,
+#ifdef FLOAT64
+    F128_TO_F64,
+#endif
+#ifdef EXTFLOAT80
+    F128_TO_EXTF80,
+#endif
+    F128_ROUNDTOINT,
+    F128_ADD,
+    F128_SUB,
+    F128_MUL,
+    F128_MULADD,
+    F128_DIV,
+    F128_REM,
+    F128_SQRT,
+    F128_EQ,
+    F128_LE,
+    F128_LT,
+    F128_EQ_SIGNALING,
+    F128_LE_QUIET,
+    F128_LT_QUIET,
+#endif
+    NUM_FUNCTIONS
+};
+
+enum {
+    ROUND_NEAR_EVEN = 1,
+    ROUND_MINMAG,
+    ROUND_MIN,
+    ROUND_MAX,
+    ROUND_NEAR_MAXMAG,
+#ifdef FLOAT_ROUND_ODD
+    ROUND_ODD,
+#endif
+    NUM_ROUNDINGMODES
+};
+enum {
+    TININESS_BEFORE_ROUNDING = 1,
+    TININESS_AFTER_ROUNDING,
+    NUM_TININESSMODES
+};
+
+extern const uint_fast8_t roundingModes[NUM_ROUNDINGMODES];
+extern const uint_fast8_t tininessModes[NUM_TININESSMODES];
+
+enum {
+    FUNC_ARG_UNARY                    = 0x01,
+    FUNC_ARG_BINARY                   = 0x02,
+    FUNC_ARG_ROUNDINGMODE             = 0x04,
+    FUNC_ARG_EXACT                    = 0x08,
+    FUNC_EFF_ROUNDINGPRECISION        = 0x10,
+    FUNC_EFF_ROUNDINGMODE             = 0x20,
+    FUNC_EFF_TININESSMODE             = 0x40,
+    FUNC_EFF_TININESSMODE_REDUCEDPREC = 0x80
+};
+struct functionInfo {
+    const char *namePtr;
+    unsigned char attribs;
+};
+extern const struct functionInfo functionInfos[NUM_FUNCTIONS];
+
+struct standardFunctionInfo {
+    const char *namePtr;
+    unsigned char functionCode;
+    char roundingCode, exact;
+};
+extern const struct standardFunctionInfo standardFunctionInfos[];
+
diff --git a/addins/TestFloat-3e/source/functions_common.c b/addins/TestFloat-3e/source/functions_common.c
new file mode 100644
index 000000000..16cf3c72f
--- /dev/null
+++ b/addins/TestFloat-3e/source/functions_common.c
@@ -0,0 +1,60 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "functions.h"
+
+const uint_fast8_t roundingModes[NUM_ROUNDINGMODES] = {
+    0,
+    softfloat_round_near_even,
+    softfloat_round_minMag,
+    softfloat_round_min,
+    softfloat_round_max,
+    softfloat_round_near_maxMag,
+#ifdef FLOAT_ROUND_ODD
+    softfloat_round_odd
+#endif
+};
+
+const uint_fast8_t tininessModes[NUM_TININESSMODES] = {
+    0,
+    softfloat_tininess_beforeRounding,
+    softfloat_tininess_afterRounding
+};
+
diff --git a/addins/TestFloat-3e/source/genCases.h b/addins/TestFloat-3e/source/genCases.h
new file mode 100644
index 000000000..efea7dd1a
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases.h
@@ -0,0 +1,114 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+extern int genCases_level;
+
+void genCases_setLevel( int );
+
+extern uint_fast64_t genCases_total;
+extern bool genCases_done;
+
+void genCases_ui32_a_init( void );
+void genCases_ui32_a_next( void );
+extern uint32_t genCases_ui32_a;
+
+void genCases_ui64_a_init( void );
+void genCases_ui64_a_next( void );
+extern uint64_t genCases_ui64_a;
+
+void genCases_i32_a_init( void );
+void genCases_i32_a_next( void );
+extern int32_t genCases_i32_a;
+
+void genCases_i64_a_init( void );
+void genCases_i64_a_next( void );
+extern int64_t genCases_i64_a;
+
+#ifdef FLOAT16
+void genCases_f16_a_init( void );
+void genCases_f16_a_next( void );
+void genCases_f16_ab_init( void );
+void genCases_f16_ab_next( void );
+void genCases_f16_abc_init( void );
+void genCases_f16_abc_next( void );
+extern float16_t genCases_f16_a, genCases_f16_b, genCases_f16_c;
+#endif
+
+void genCases_f32_a_init( void );
+void genCases_f32_a_next( void );
+void genCases_f32_ab_init( void );
+void genCases_f32_ab_next( void );
+void genCases_f32_abc_init( void );
+void genCases_f32_abc_next( void );
+extern float32_t genCases_f32_a, genCases_f32_b, genCases_f32_c;
+
+#ifdef FLOAT64
+void genCases_f64_a_init( void );
+void genCases_f64_a_next( void );
+void genCases_f64_ab_init( void );
+void genCases_f64_ab_next( void );
+void genCases_f64_abc_init( void );
+void genCases_f64_abc_next( void );
+extern float64_t genCases_f64_a, genCases_f64_b, genCases_f64_c;
+#endif
+
+#ifdef EXTFLOAT80
+void genCases_extF80_a_init( void );
+void genCases_extF80_a_next( void );
+void genCases_extF80_ab_init( void );
+void genCases_extF80_ab_next( void );
+void genCases_extF80_abc_init( void );
+void genCases_extF80_abc_next( void );
+extern extFloat80_t genCases_extF80_a, genCases_extF80_b, genCases_extF80_c;
+#endif
+
+#ifdef FLOAT128
+void genCases_f128_a_init( void );
+void genCases_f128_a_next( void );
+void genCases_f128_ab_init( void );
+void genCases_f128_ab_next( void );
+void genCases_f128_abc_init( void );
+void genCases_f128_abc_next( void );
+extern float128_t genCases_f128_a, genCases_f128_b, genCases_f128_c;
+#endif
+
+void genCases_writeTestsTotal( bool );
+
diff --git a/addins/TestFloat-3e/source/genCases_common.c b/addins/TestFloat-3e/source/genCases_common.c
new file mode 100644
index 000000000..25e733e45
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_common.c
@@ -0,0 +1,58 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "fail.h"
+#include "genCases.h"
+
+int genCases_level = 0;
+
+void genCases_setLevel( int newLevel )
+{
+
+    if ( (newLevel < 1) || (2 < newLevel) ) {
+        fail( "Invalid testing level %d", newLevel );
+    }
+    genCases_level = newLevel;
+
+}
+
+uint_fast64_t genCases_total;
+bool genCases_done;
+
diff --git a/addins/TestFloat-3e/source/genCases_extF80.c b/addins/TestFloat-3e/source/genCases_extF80.c
new file mode 100644
index 000000000..97e455777
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_extF80.c
@@ -0,0 +1,920 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "softfloat.h"
+#include "genCases.h"
+
+#ifdef EXTFLOAT80
+
+struct sequence {
+    int expNum, term1Num, term2Num;
+    bool done;
+};
+
+enum {
+    extF80NumQIn  =  22,
+    extF80NumQOut =  76,
+    extF80NumP1   =   4,
+    extF80NumP2   = 248
+};
+static const uint16_t extF80QIn[extF80NumQIn] = {
+    0x0000,    /* positive, subnormal       */
+    0x0001,    /* positive, -16382          */
+    0x3FBF,    /* positive,    -64          */
+    0x3FFD,    /* positive,     -2          */
+    0x3FFE,    /* positive,     -1          */
+    0x3FFF,    /* positive,      0          */
+    0x4000,    /* positive,      1          */
+    0x4001,    /* positive,      2          */
+    0x403F,    /* positive,     64          */
+    0x7FFE,    /* positive,  16383          */
+    0x7FFF,    /* positive, infinity or NaN */
+    0x8000,    /* negative, subnormal       */
+    0x8001,    /* negative, -16382          */
+    0xBFBF,    /* negative,    -64          */
+    0xBFFD,    /* negative,     -2          */
+    0xBFFE,    /* negative,     -1          */
+    0xBFFF,    /* negative,      0          */
+    0xC000,    /* negative,      1          */
+    0xC001,    /* negative,      2          */
+    0xC03F,    /* negative,     64          */
+    0xFFFE,    /* negative,  16383          */
+    0xFFFF     /* negative, infinity or NaN */
+};
+static const uint16_t extF80QOut[extF80NumQOut] = {
+    0x0000,    /* positive, subnormal       */
+    0x0001,    /* positive, -16382          */
+    0x0002,    /* positive, -16381          */
+    0x3BFE,    /* positive,  -1025          */
+    0x3BFF,    /* positive,  -1024          */
+    0x3C00,    /* positive,  -1023          */
+    0x3C01,    /* positive,  -1022          */
+    0x3F7E,    /* positive,   -129          */
+    0x3F7F,    /* positive,   -128          */
+    0x3F80,    /* positive,   -127          */
+    0x3F81,    /* positive,   -126          */
+    0x3FBF,    /* positive,    -64          */
+    0x3FFB,    /* positive,     -4          */
+    0x3FFC,    /* positive,     -3          */
+    0x3FFD,    /* positive,     -2          */
+    0x3FFE,    /* positive,     -1          */
+    0x3FFF,    /* positive,      0          */
+    0x4000,    /* positive,      1          */
+    0x4001,    /* positive,      2          */
+    0x4002,    /* positive,      3          */
+    0x4003,    /* positive,      4          */
+    0x401C,    /* positive,     29          */
+    0x401D,    /* positive,     30          */
+    0x401E,    /* positive,     31          */
+    0x401F,    /* positive,     32          */
+    0x403C,    /* positive,     61          */
+    0x403D,    /* positive,     62          */
+    0x403E,    /* positive,     63          */
+    0x403F,    /* positive,     64          */
+    0x407E,    /* positive,    127          */
+    0x407F,    /* positive,    128          */
+    0x4080,    /* positive,    129          */
+    0x43FE,    /* positive,   1023          */
+    0x43FF,    /* positive,   1024          */
+    0x4400,    /* positive,   1025          */
+    0x7FFD,    /* positive,  16382          */
+    0x7FFE,    /* positive,  16383          */
+    0x7FFF,    /* positive, infinity or NaN */
+    0x8000,    /* negative, subnormal       */
+    0x8001,    /* negative, -16382          */
+    0x8002,    /* negative, -16381          */
+    0xBBFE,    /* negative,  -1025          */
+    0xBBFF,    /* negative,  -1024          */
+    0xBC00,    /* negative,  -1023          */
+    0xBC01,    /* negative,  -1022          */
+    0xBF7E,    /* negative,   -129          */
+    0xBF7F,    /* negative,   -128          */
+    0xBF80,    /* negative,   -127          */
+    0xBF81,    /* negative,   -126          */
+    0xBFBF,    /* negative,    -64          */
+    0xBFFB,    /* negative,     -4          */
+    0xBFFC,    /* negative,     -3          */
+    0xBFFD,    /* negative,     -2          */
+    0xBFFE,    /* negative,     -1          */
+    0xBFFF,    /* negative,      0          */
+    0xC000,    /* negative,      1          */
+    0xC001,    /* negative,      2          */
+    0xC002,    /* negative,      3          */
+    0xC003,    /* negative,      4          */
+    0xC01C,    /* negative,     29          */
+    0xC01D,    /* negative,     30          */
+    0xC01E,    /* negative,     31          */
+    0xC01F,    /* negative,     32          */
+    0xC03C,    /* negative,     61          */
+    0xC03D,    /* negative,     62          */
+    0xC03E,    /* negative,     63          */
+    0xC03F,    /* negative,     64          */
+    0xC07E,    /* negative,    127          */
+    0xC07F,    /* negative,    128          */
+    0xC080,    /* negative,    129          */
+    0xC3FE,    /* negative,   1023          */
+    0xC3FF,    /* negative,   1024          */
+    0xC400,    /* negative,   1025          */
+    0xFFFD,    /* negative,  16382          */
+    0xFFFE,    /* negative,  16383          */
+    0xFFFF     /* negative, infinity or NaN */
+};
+static const uint64_t extF80P1[extF80NumP1] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFE )
+};
+static const uint64_t extF80P2[extF80NumP2] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x0000000000000002 ),
+    UINT64_C( 0x0000000000000004 ),
+    UINT64_C( 0x0000000000000008 ),
+    UINT64_C( 0x0000000000000010 ),
+    UINT64_C( 0x0000000000000020 ),
+    UINT64_C( 0x0000000000000040 ),
+    UINT64_C( 0x0000000000000080 ),
+    UINT64_C( 0x0000000000000100 ),
+    UINT64_C( 0x0000000000000200 ),
+    UINT64_C( 0x0000000000000400 ),
+    UINT64_C( 0x0000000000000800 ),
+    UINT64_C( 0x0000000000001000 ),
+    UINT64_C( 0x0000000000002000 ),
+    UINT64_C( 0x0000000000004000 ),
+    UINT64_C( 0x0000000000008000 ),
+    UINT64_C( 0x0000000000010000 ),
+    UINT64_C( 0x0000000000020000 ),
+    UINT64_C( 0x0000000000040000 ),
+    UINT64_C( 0x0000000000080000 ),
+    UINT64_C( 0x0000000000100000 ),
+    UINT64_C( 0x0000000000200000 ),
+    UINT64_C( 0x0000000000400000 ),
+    UINT64_C( 0x0000000000800000 ),
+    UINT64_C( 0x0000000001000000 ),
+    UINT64_C( 0x0000000002000000 ),
+    UINT64_C( 0x0000000004000000 ),
+    UINT64_C( 0x0000000008000000 ),
+    UINT64_C( 0x0000000010000000 ),
+    UINT64_C( 0x0000000020000000 ),
+    UINT64_C( 0x0000000040000000 ),
+    UINT64_C( 0x0000000080000000 ),
+    UINT64_C( 0x0000000100000000 ),
+    UINT64_C( 0x0000000200000000 ),
+    UINT64_C( 0x0000000400000000 ),
+    UINT64_C( 0x0000000800000000 ),
+    UINT64_C( 0x0000001000000000 ),
+    UINT64_C( 0x0000002000000000 ),
+    UINT64_C( 0x0000004000000000 ),
+    UINT64_C( 0x0000008000000000 ),
+    UINT64_C( 0x0000010000000000 ),
+    UINT64_C( 0x0000020000000000 ),
+    UINT64_C( 0x0000040000000000 ),
+    UINT64_C( 0x0000080000000000 ),
+    UINT64_C( 0x0000100000000000 ),
+    UINT64_C( 0x0000200000000000 ),
+    UINT64_C( 0x0000400000000000 ),
+    UINT64_C( 0x0000800000000000 ),
+    UINT64_C( 0x0001000000000000 ),
+    UINT64_C( 0x0002000000000000 ),
+    UINT64_C( 0x0004000000000000 ),
+    UINT64_C( 0x0008000000000000 ),
+    UINT64_C( 0x0010000000000000 ),
+    UINT64_C( 0x0020000000000000 ),
+    UINT64_C( 0x0040000000000000 ),
+    UINT64_C( 0x0080000000000000 ),
+    UINT64_C( 0x0100000000000000 ),
+    UINT64_C( 0x0200000000000000 ),
+    UINT64_C( 0x0400000000000000 ),
+    UINT64_C( 0x0800000000000000 ),
+    UINT64_C( 0x1000000000000000 ),
+    UINT64_C( 0x2000000000000000 ),
+    UINT64_C( 0x4000000000000000 ),
+    UINT64_C( 0x6000000000000000 ),
+    UINT64_C( 0x7000000000000000 ),
+    UINT64_C( 0x7800000000000000 ),
+    UINT64_C( 0x7C00000000000000 ),
+    UINT64_C( 0x7E00000000000000 ),
+    UINT64_C( 0x7F00000000000000 ),
+    UINT64_C( 0x7F80000000000000 ),
+    UINT64_C( 0x7FC0000000000000 ),
+    UINT64_C( 0x7FE0000000000000 ),
+    UINT64_C( 0x7FF0000000000000 ),
+    UINT64_C( 0x7FF8000000000000 ),
+    UINT64_C( 0x7FFC000000000000 ),
+    UINT64_C( 0x7FFE000000000000 ),
+    UINT64_C( 0x7FFF000000000000 ),
+    UINT64_C( 0x7FFF800000000000 ),
+    UINT64_C( 0x7FFFC00000000000 ),
+    UINT64_C( 0x7FFFE00000000000 ),
+    UINT64_C( 0x7FFFF00000000000 ),
+    UINT64_C( 0x7FFFF80000000000 ),
+    UINT64_C( 0x7FFFFC0000000000 ),
+    UINT64_C( 0x7FFFFE0000000000 ),
+    UINT64_C( 0x7FFFFF0000000000 ),
+    UINT64_C( 0x7FFFFF8000000000 ),
+    UINT64_C( 0x7FFFFFC000000000 ),
+    UINT64_C( 0x7FFFFFE000000000 ),
+    UINT64_C( 0x7FFFFFF000000000 ),
+    UINT64_C( 0x7FFFFFF800000000 ),
+    UINT64_C( 0x7FFFFFFC00000000 ),
+    UINT64_C( 0x7FFFFFFE00000000 ),
+    UINT64_C( 0x7FFFFFFF00000000 ),
+    UINT64_C( 0x7FFFFFFF80000000 ),
+    UINT64_C( 0x7FFFFFFFC0000000 ),
+    UINT64_C( 0x7FFFFFFFE0000000 ),
+    UINT64_C( 0x7FFFFFFFF0000000 ),
+    UINT64_C( 0x7FFFFFFFF8000000 ),
+    UINT64_C( 0x7FFFFFFFFC000000 ),
+    UINT64_C( 0x7FFFFFFFFE000000 ),
+    UINT64_C( 0x7FFFFFFFFF000000 ),
+    UINT64_C( 0x7FFFFFFFFF800000 ),
+    UINT64_C( 0x7FFFFFFFFFC00000 ),
+    UINT64_C( 0x7FFFFFFFFFE00000 ),
+    UINT64_C( 0x7FFFFFFFFFF00000 ),
+    UINT64_C( 0x7FFFFFFFFFF80000 ),
+    UINT64_C( 0x7FFFFFFFFFFC0000 ),
+    UINT64_C( 0x7FFFFFFFFFFE0000 ),
+    UINT64_C( 0x7FFFFFFFFFFF0000 ),
+    UINT64_C( 0x7FFFFFFFFFFF8000 ),
+    UINT64_C( 0x7FFFFFFFFFFFC000 ),
+    UINT64_C( 0x7FFFFFFFFFFFE000 ),
+    UINT64_C( 0x7FFFFFFFFFFFF000 ),
+    UINT64_C( 0x7FFFFFFFFFFFF800 ),
+    UINT64_C( 0x7FFFFFFFFFFFFC00 ),
+    UINT64_C( 0x7FFFFFFFFFFFFE00 ),
+    UINT64_C( 0x7FFFFFFFFFFFFF00 ),
+    UINT64_C( 0x7FFFFFFFFFFFFF80 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFC0 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFE0 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFF0 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFF8 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFC ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFE ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFD ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFB ),
+    UINT64_C( 0x7FFFFFFFFFFFFFF7 ),
+    UINT64_C( 0x7FFFFFFFFFFFFFEF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFDF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFBF ),
+    UINT64_C( 0x7FFFFFFFFFFFFF7F ),
+    UINT64_C( 0x7FFFFFFFFFFFFEFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFDFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFBFF ),
+    UINT64_C( 0x7FFFFFFFFFFFF7FF ),
+    UINT64_C( 0x7FFFFFFFFFFFEFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFDFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFBFFF ),
+    UINT64_C( 0x7FFFFFFFFFFF7FFF ),
+    UINT64_C( 0x7FFFFFFFFFFEFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFDFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFBFFFF ),
+    UINT64_C( 0x7FFFFFFFFFF7FFFF ),
+    UINT64_C( 0x7FFFFFFFFFEFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFDFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFBFFFFF ),
+    UINT64_C( 0x7FFFFFFFFF7FFFFF ),
+    UINT64_C( 0x7FFFFFFFFEFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFDFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFBFFFFFF ),
+    UINT64_C( 0x7FFFFFFFF7FFFFFF ),
+    UINT64_C( 0x7FFFFFFFEFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFDFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFBFFFFFFF ),
+    UINT64_C( 0x7FFFFFFF7FFFFFFF ),
+    UINT64_C( 0x7FFFFFFEFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFDFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFBFFFFFFFF ),
+    UINT64_C( 0x7FFFFFF7FFFFFFFF ),
+    UINT64_C( 0x7FFFFFEFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFDFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFBFFFFFFFFF ),
+    UINT64_C( 0x7FFFFF7FFFFFFFFF ),
+    UINT64_C( 0x7FFFFEFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFDFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFBFFFFFFFFFF ),
+    UINT64_C( 0x7FFFF7FFFFFFFFFF ),
+    UINT64_C( 0x7FFFEFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFDFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFBFFFFFFFFFFF ),
+    UINT64_C( 0x7FFF7FFFFFFFFFFF ),
+    UINT64_C( 0x7FFEFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFDFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFBFFFFFFFFFFFF ),
+    UINT64_C( 0x7FF7FFFFFFFFFFFF ),
+    UINT64_C( 0x7FEFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FDFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FBFFFFFFFFFFFFF ),
+    UINT64_C( 0x7F7FFFFFFFFFFFFF ),
+    UINT64_C( 0x7EFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7DFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7BFFFFFFFFFFFFFF ),
+    UINT64_C( 0x77FFFFFFFFFFFFFF ),
+    UINT64_C( 0x6FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x5FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x3FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x1FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x0FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x07FFFFFFFFFFFFFF ),
+    UINT64_C( 0x03FFFFFFFFFFFFFF ),
+    UINT64_C( 0x01FFFFFFFFFFFFFF ),
+    UINT64_C( 0x00FFFFFFFFFFFFFF ),
+    UINT64_C( 0x007FFFFFFFFFFFFF ),
+    UINT64_C( 0x003FFFFFFFFFFFFF ),
+    UINT64_C( 0x001FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F ),
+    UINT64_C( 0x0000000000000007 ),
+    UINT64_C( 0x0000000000000003 )
+};
+
+static const uint_fast32_t extF80NumQInP1 = extF80NumQIn * extF80NumP1;
+static const uint_fast32_t extF80NumQOutP1 = extF80NumQOut * extF80NumP1;
+
+static void extF80NextQInP1( struct sequence *sequencePtr, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int expNum, sigNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZ64 = extF80QIn[expNum];
+    uiZ0  = extF80P1[sigNum];
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+    ++sigNum;
+    if ( extF80NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( extF80NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static
+ void extF80NextQOutP1( struct sequence *sequencePtr, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int expNum, sigNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZ64 = extF80QOut[expNum];
+    uiZ0  = extF80P1[sigNum];
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+    ++sigNum;
+    if ( extF80NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( extF80NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static const uint_fast32_t extF80NumQInP2 = extF80NumQIn * extF80NumP2;
+static const uint_fast32_t extF80NumQOutP2 = extF80NumQOut * extF80NumP2;
+
+static void extF80NextQInP2( struct sequence *sequencePtr, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int expNum, sigNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZ64 = extF80QIn[expNum];
+    uiZ0  = extF80P2[sigNum];
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+    ++sigNum;
+    if ( extF80NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( extF80NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static
+ void extF80NextQOutP2( struct sequence *sequencePtr, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int expNum, sigNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZ64 = extF80QOut[expNum];
+    uiZ0  = extF80P2[sigNum];
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+    ++sigNum;
+    if ( extF80NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( extF80NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static void extF80RandomQOutP3( extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = extF80QOut[randomN_ui8( extF80NumQOut )];
+    uiZ0 =
+        (extF80P2[randomN_ui8( extF80NumP2 )]
+             + extF80P2[randomN_ui8( extF80NumP2 )])
+            & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+static void extF80RandomQOutPInf( extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    uiZ64 = extF80QOut[randomN_ui8( extF80NumQOut )];
+    uiZ0 = random_ui64() & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+enum { extF80NumQInfWeightMasks = 14 };
+static const uint16_t extF80QInfWeightMasks[extF80NumQInfWeightMasks] = {
+    0xFFFF,
+    0xFFFF,
+    0xBFFF,
+    0x9FFF,
+    0x87FF,
+    0x87FF,
+    0x83FF,
+    0x81FF,
+    0x80FF,
+    0x807F,
+    0x803F,
+    0x801F,
+    0x800F,
+    0x8007
+};
+static const uint16_t extF80QInfWeightOffsets[extF80NumQInfWeightMasks] = {
+    0x0000,
+    0x0000,
+    0x2000,
+    0x3000,
+    0x3800,
+    0x3C00,
+    0x3E00,
+    0x3F00,
+    0x3F80,
+    0x3FC0,
+    0x3FE0,
+    0x3FF0,
+    0x3FF8,
+    0x3FFC
+};
+
+static void extF80RandomQInfP3( extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int weightMaskNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    weightMaskNum = randomN_ui8( extF80NumQInfWeightMasks );
+    uiZ64 =
+        (random_ui16() & extF80QInfWeightMasks[weightMaskNum])
+            + extF80QInfWeightOffsets[weightMaskNum];
+    uiZ0 =
+        (extF80P2[randomN_ui8( extF80NumP2 )]
+             + extF80P2[randomN_ui8( extF80NumP2 )])
+            & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+static void extF80RandomQInfPInf( extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    int weightMaskNum;
+    uint_fast16_t uiZ64;
+    uint_fast64_t uiZ0;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    weightMaskNum = randomN_ui8( extF80NumQInfWeightMasks );
+    uiZ64 =
+        (random_ui16() & extF80QInfWeightMasks[weightMaskNum])
+            + extF80QInfWeightOffsets[weightMaskNum];
+    uiZ0 = random_ui64() & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    if ( uiZ64 & 0x7FFF ) uiZ0 |= UINT64_C( 0x8000000000000000 );
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif  = uiZ0;
+
+}
+
+static void extF80Random( extFloat80_t *zPtr )
+{
+
+    switch ( random_ui8() & 7 ) {
+     case 0:
+     case 1:
+     case 2:
+        extF80RandomQOutP3( zPtr );
+        break;
+     case 3:
+        extF80RandomQOutPInf( zPtr );
+        break;
+     case 4:
+     case 5:
+     case 6:
+        extF80RandomQInfP3( zPtr );
+        break;
+     case 7:
+        extF80RandomQInfPInf( zPtr );
+        break;
+    }
+
+}
+
+static struct sequence sequenceA, sequenceB, sequenceC;
+static extFloat80_t currentA, currentB, currentC;
+static int subcase;
+
+extFloat80_t genCases_extF80_a, genCases_extF80_b, genCases_extF80_c;
+
+void genCases_extF80_a_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total =
+        (genCases_level == 1) ? 3 * extF80NumQOutP1 : 2 * extF80NumQOutP2;
+    genCases_done = false;
+
+}
+
+void genCases_extF80_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+         case 1:
+            extF80Random( &genCases_extF80_a );
+            break;
+         case 2:
+            extF80NextQOutP1( &sequenceA, &genCases_extF80_a );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+     } else {
+        switch ( subcase ) {
+         case 0:
+            extF80Random( &genCases_extF80_a );
+            break;
+         case 1:
+            extF80NextQOutP2( &sequenceA, &genCases_extF80_a );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_extF80_ab_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 6 * extF80NumQInP1 * extF80NumQInP1;
+        extF80NextQInP1( &sequenceA, &currentA );
+    } else {
+        genCases_total = 2 * extF80NumQInP2 * extF80NumQInP2;
+        extF80NextQInP2( &sequenceA, &currentA );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_extF80_ab_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                extF80NextQInP1( &sequenceA, &currentA );
+            }
+            extF80NextQInP1( &sequenceB, &currentB );
+         case 2:
+         case 4:
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            break;
+         case 1:
+            genCases_extF80_a = currentA;
+            extF80Random( &genCases_extF80_b );
+            break;
+         case 3:
+            extF80Random( &genCases_extF80_a );
+            genCases_extF80_b = currentB;
+            break;
+         case 5:
+            genCases_extF80_a = currentA;
+            genCases_extF80_b = currentB;
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            break;
+         case 1:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                extF80NextQInP2( &sequenceA, &currentA );
+            }
+            genCases_extF80_a = currentA;
+            extF80NextQInP2( &sequenceB, &genCases_extF80_b );
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_extF80_abc_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    sequenceC.expNum = 0;
+    sequenceC.term1Num = 0;
+    sequenceC.term2Num = 0;
+    sequenceC.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 9 * extF80NumQInP1 * extF80NumQInP1 * extF80NumQInP1;
+        extF80NextQInP1( &sequenceA, &currentA );
+        extF80NextQInP1( &sequenceB, &currentB );
+    } else {
+        genCases_total = 2 * extF80NumQInP2 * extF80NumQInP2 * extF80NumQInP2;
+        extF80NextQInP2( &sequenceA, &currentA );
+        extF80NextQInP2( &sequenceB, &currentB );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_extF80_abc_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    extF80NextQInP1( &sequenceA, &currentA );
+                }
+                extF80NextQInP1( &sequenceB, &currentB );
+            }
+            extF80NextQInP1( &sequenceC, &currentC );
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            genCases_extF80_c = currentC;
+            break;
+         case 1:
+            genCases_extF80_a = currentA;
+            genCases_extF80_b = currentB;
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 2:
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 3:
+            extF80Random( &genCases_extF80_a );
+            genCases_extF80_b = currentB;
+            genCases_extF80_c = currentC;
+            break;
+         case 4:
+            genCases_extF80_a = currentA;
+            extF80Random( &genCases_extF80_b );
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 5:
+            extF80Random( &genCases_extF80_a );
+            genCases_extF80_b = currentB;
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 6:
+            genCases_extF80_a = currentA;
+            extF80Random( &genCases_extF80_b );
+            genCases_extF80_c = currentC;
+            break;
+         case 7:
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 8:
+            genCases_extF80_a = currentA;
+            genCases_extF80_b = currentB;
+            genCases_extF80_c = currentC;
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            extF80Random( &genCases_extF80_a );
+            extF80Random( &genCases_extF80_b );
+            extF80Random( &genCases_extF80_c );
+            break;
+         case 1:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    extF80NextQInP2( &sequenceA, &currentA );
+                }
+                extF80NextQInP2( &sequenceB, &currentB );
+            }
+            genCases_extF80_a = currentA;
+            genCases_extF80_b = currentB;
+            extF80NextQInP2( &sequenceC, &genCases_extF80_c );
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/genCases_f128.c b/addins/TestFloat-3e/source/genCases_f128.c
new file mode 100644
index 000000000..e20c7a17f
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_f128.c
@@ -0,0 +1,1090 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "uint128.h"
+#include "random.h"
+#include "softfloat.h"
+#include "genCases.h"
+
+#ifdef FLOAT128
+
+struct sequence {
+    int expNum, term1Num, term2Num;
+    bool done;
+};
+
+enum {
+    f128NumQIn  =  22,
+    f128NumQOut =  78,
+    f128NumP1   =   4,
+    f128NumP2   = 443
+};
+static const uint64_t f128QIn[f128NumQIn] = {
+    UINT64_C( 0x0000000000000000 ),    /* positive, subnormal       */
+    UINT64_C( 0x0001000000000000 ),    /* positive, -16382          */
+    UINT64_C( 0x3F8E000000000000 ),    /* positive,   -113          */
+    UINT64_C( 0x3FFD000000000000 ),    /* positive,     -2          */
+    UINT64_C( 0x3FFE000000000000 ),    /* positive,     -1          */
+    UINT64_C( 0x3FFF000000000000 ),    /* positive,      0          */
+    UINT64_C( 0x4000000000000000 ),    /* positive,      1          */
+    UINT64_C( 0x4001000000000000 ),    /* positive,      2          */
+    UINT64_C( 0x4070000000000000 ),    /* positive,    113          */
+    UINT64_C( 0x7FFE000000000000 ),    /* positive,  16383          */
+    UINT64_C( 0x7FFF000000000000 ),    /* positive, infinity or NaN */
+    UINT64_C( 0x8000000000000000 ),    /* negative, subnormal       */
+    UINT64_C( 0x8001000000000000 ),    /* negative, -16382          */
+    UINT64_C( 0xBF8E000000000000 ),    /* negative,   -113          */
+    UINT64_C( 0xBFFD000000000000 ),    /* negative,     -2          */
+    UINT64_C( 0xBFFE000000000000 ),    /* negative,     -1          */
+    UINT64_C( 0xBFFF000000000000 ),    /* negative,      0          */
+    UINT64_C( 0xC000000000000000 ),    /* negative,      1          */
+    UINT64_C( 0xC001000000000000 ),    /* negative,      2          */
+    UINT64_C( 0xC070000000000000 ),    /* negative,    113          */
+    UINT64_C( 0xFFFE000000000000 ),    /* negative,  16383          */
+    UINT64_C( 0xFFFF000000000000 )     /* negative, infinity or NaN */
+};
+static const uint64_t f128QOut[f128NumQOut] = {
+    UINT64_C( 0x0000000000000000 ),    /* positive, subnormal       */
+    UINT64_C( 0x0001000000000000 ),    /* positive, -16382          */
+    UINT64_C( 0x0002000000000000 ),    /* positive, -16381          */
+    UINT64_C( 0x3BFE000000000000 ),    /* positive,  -1025          */
+    UINT64_C( 0x3BFF000000000000 ),    /* positive,  -1024          */
+    UINT64_C( 0x3C00000000000000 ),    /* positive,  -1023          */
+    UINT64_C( 0x3C01000000000000 ),    /* positive,  -1022          */
+    UINT64_C( 0x3F7E000000000000 ),    /* positive,   -129          */
+    UINT64_C( 0x3F7F000000000000 ),    /* positive,   -128          */
+    UINT64_C( 0x3F80000000000000 ),    /* positive,   -127          */
+    UINT64_C( 0x3F81000000000000 ),    /* positive,   -126          */
+    UINT64_C( 0x3F8E000000000000 ),    /* positive,   -113          */
+    UINT64_C( 0x3FFB000000000000 ),    /* positive,     -4          */
+    UINT64_C( 0x3FFC000000000000 ),    /* positive,     -3          */
+    UINT64_C( 0x3FFD000000000000 ),    /* positive,     -2          */
+    UINT64_C( 0x3FFE000000000000 ),    /* positive,     -1          */
+    UINT64_C( 0x3FFF000000000000 ),    /* positive,      0          */
+    UINT64_C( 0x4000000000000000 ),    /* positive,      1          */
+    UINT64_C( 0x4001000000000000 ),    /* positive,      2          */
+    UINT64_C( 0x4002000000000000 ),    /* positive,      3          */
+    UINT64_C( 0x4003000000000000 ),    /* positive,      4          */
+    UINT64_C( 0x401C000000000000 ),    /* positive,     29          */
+    UINT64_C( 0x401D000000000000 ),    /* positive,     30          */
+    UINT64_C( 0x401E000000000000 ),    /* positive,     31          */
+    UINT64_C( 0x401F000000000000 ),    /* positive,     32          */
+    UINT64_C( 0x403C000000000000 ),    /* positive,     61          */
+    UINT64_C( 0x403D000000000000 ),    /* positive,     62          */
+    UINT64_C( 0x403E000000000000 ),    /* positive,     63          */
+    UINT64_C( 0x403F000000000000 ),    /* positive,     64          */
+    UINT64_C( 0x4070000000000000 ),    /* positive,    113          */
+    UINT64_C( 0x407E000000000000 ),    /* positive,    127          */
+    UINT64_C( 0x407F000000000000 ),    /* positive,    128          */
+    UINT64_C( 0x4080000000000000 ),    /* positive,    129          */
+    UINT64_C( 0x43FE000000000000 ),    /* positive,   1023          */
+    UINT64_C( 0x43FF000000000000 ),    /* positive,   1024          */
+    UINT64_C( 0x4400000000000000 ),    /* positive,   1025          */
+    UINT64_C( 0x7FFD000000000000 ),    /* positive,  16382          */
+    UINT64_C( 0x7FFE000000000000 ),    /* positive,  16383          */
+    UINT64_C( 0x7FFF000000000000 ),    /* positive, infinity or NaN */
+    UINT64_C( 0x8000000000000000 ),    /* negative, subnormal       */
+    UINT64_C( 0x8001000000000000 ),    /* negative, -16382          */
+    UINT64_C( 0x8002000000000000 ),    /* negative, -16381          */
+    UINT64_C( 0xBBFE000000000000 ),    /* negative,  -1025          */
+    UINT64_C( 0xBBFF000000000000 ),    /* negative,  -1024          */
+    UINT64_C( 0xBC00000000000000 ),    /* negative,  -1023          */
+    UINT64_C( 0xBC01000000000000 ),    /* negative,  -1022          */
+    UINT64_C( 0xBF7E000000000000 ),    /* negative,   -129          */
+    UINT64_C( 0xBF7F000000000000 ),    /* negative,   -128          */
+    UINT64_C( 0xBF80000000000000 ),    /* negative,   -127          */
+    UINT64_C( 0xBF81000000000000 ),    /* negative,   -126          */
+    UINT64_C( 0xBF8E000000000000 ),    /* negative,   -113          */
+    UINT64_C( 0xBFFB000000000000 ),    /* negative,     -4          */
+    UINT64_C( 0xBFFC000000000000 ),    /* negative,     -3          */
+    UINT64_C( 0xBFFD000000000000 ),    /* negative,     -2          */
+    UINT64_C( 0xBFFE000000000000 ),    /* negative,     -1          */
+    UINT64_C( 0xBFFF000000000000 ),    /* negative,      0          */
+    UINT64_C( 0xC000000000000000 ),    /* negative,      1          */
+    UINT64_C( 0xC001000000000000 ),    /* negative,      2          */
+    UINT64_C( 0xC002000000000000 ),    /* negative,      3          */
+    UINT64_C( 0xC003000000000000 ),    /* negative,      4          */
+    UINT64_C( 0xC01C000000000000 ),    /* negative,     29          */
+    UINT64_C( 0xC01D000000000000 ),    /* negative,     30          */
+    UINT64_C( 0xC01E000000000000 ),    /* negative,     31          */
+    UINT64_C( 0xC01F000000000000 ),    /* negative,     32          */
+    UINT64_C( 0xC03C000000000000 ),    /* negative,     61          */
+    UINT64_C( 0xC03D000000000000 ),    /* negative,     62          */
+    UINT64_C( 0xC03E000000000000 ),    /* negative,     63          */
+    UINT64_C( 0xC03F000000000000 ),    /* negative,     64          */
+    UINT64_C( 0xC070000000000000 ),    /* negative,    113          */
+    UINT64_C( 0xC07E000000000000 ),    /* negative,    127          */
+    UINT64_C( 0xC07F000000000000 ),    /* negative,    128          */
+    UINT64_C( 0xC080000000000000 ),    /* negative,    129          */
+    UINT64_C( 0xC3FE000000000000 ),    /* negative,   1023          */
+    UINT64_C( 0xC3FF000000000000 ),    /* negative,   1024          */
+    UINT64_C( 0xC400000000000000 ),    /* negative,   1025          */
+    UINT64_C( 0xFFFD000000000000 ),    /* negative,  16382          */
+    UINT64_C( 0xFFFE000000000000 ),    /* negative,  16383          */
+    UINT64_C( 0xFFFF000000000000 )     /* negative, infinity or NaN */
+};
+static const struct { uint64_t v64, v0; } f128P1[f128NumP1] = {
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000001 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFE ) }
+};
+static const struct { uint64_t v64, v0; } f128P2[f128NumP2] = {
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000001 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000002 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000004 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000008 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000010 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000020 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000040 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000080 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000100 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000200 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000400 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000800 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000001000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000002000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000004000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000008000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000010000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000020000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000040000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000080000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000100000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000200000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000400000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000800000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000001000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000002000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000004000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000008000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000010000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000020000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000040000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000080000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000100000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000200000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000400000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000800000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000001000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000002000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000004000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000008000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000010000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000020000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000040000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000080000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000100000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000200000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000400000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000800000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0001000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0002000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0004000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0008000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0010000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0020000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0040000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0080000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0100000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0200000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0400000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0800000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x1000000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x2000000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x4000000000000000 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x8000000000000000 ) },
+    { UINT64_C( 0x0000000000000001 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000002 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000004 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000008 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000010 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000020 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000040 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000080 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000100 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000200 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000400 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000000800 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000001000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000002000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000004000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000008000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000010000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000020000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000040000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000080000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000100000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000200000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000400000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000000800000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000001000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000002000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000004000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000008000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000010000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000020000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000040000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000080000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000100000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000200000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000400000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000000800000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000001000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000002000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000004000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000008000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000010000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000020000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000040000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000080000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000100000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000200000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000400000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000800000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000C00000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000E00000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000F00000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000F80000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FC0000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FE0000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FF0000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FF8000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFC000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFE000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFF000000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFF800000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFC00000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFE00000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFF00000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFF80000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFC0000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFE0000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFF0000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFF8000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFC000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFE000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFF000000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFF800000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFC00000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFE00000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFF00000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFF80000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFC0000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFE0000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFF0000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFF8000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFC000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFE000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFF000 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFF800 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFC00 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFE00 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFF00 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFF80 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFC0 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFE0 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFF0 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFF8 ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFC ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFE ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0x0000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0x8000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xC000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xE000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xF000000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xF800000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFC00000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFE00000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFF00000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFF80000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFC0000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFE0000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFF0000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFF8000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFC000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFE000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFF000000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFF800000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFC00000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFE00000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFF00000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFF80000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFC0000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFE0000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFF0000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFF8000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFC000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFE000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFF000000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFF800000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFC00000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFE00000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFF00000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFF80000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFC0000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFE0000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFF0000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFF8000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFC000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFE000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFF000000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFF800000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFC00000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFE00000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFF00000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFF80000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFC0000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFE0000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFF0000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFF8000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFC000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFE000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFF000 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFF800 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFC00 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFE00 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFF00 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFF80 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFC0 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFE0 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFF0 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFF8 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFC ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFE ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFD ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFB ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFF7 ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFEF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFDF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFBF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFF7F ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFEFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFDFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFBFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFF7FF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFEFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFDFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFBFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFF7FFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFEFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFDFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFBFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFF7FFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFEFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFDFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFBFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFF7FFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFEFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFDFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFBFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFF7FFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFEFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFDFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFBFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFF7FFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFEFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFDFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFBFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFF7FFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFEFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFDFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFFBFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFF7FFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFEFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFDFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFFBFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFF7FFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFEFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFDFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFFBFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFF7FFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFEFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFDFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFFBFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFF7FFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFEFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFDFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFFBFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFF7FFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFEFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFDFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xFBFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xF7FFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xEFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xDFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0xBFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFF ), UINT64_C( 0x7FFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFD ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFFB ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFF7 ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFEF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFDF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFFBF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFF7F ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFEFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFDFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFFBFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFF7FF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFEFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFDFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFFBFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFF7FFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFEFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFDFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFFBFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFF7FFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFEFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFDFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFFBFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFF7FFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFEFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFDFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFFBFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFF7FFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFEFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFDFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFFBFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFF7FFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFEFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFDFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFFBFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFF7FFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFEFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFDFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FFBFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FF7FFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FEFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FDFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000FBFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000F7FFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000EFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000DFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000BFFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00007FFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00003FFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00001FFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000FFFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000007FFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000003FFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000001FFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000FFFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000007FFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000003FFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000001FFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000FFFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000007FFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000003FFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000001FFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000FFFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000007FFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000003FFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000001FFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000FFFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000007FFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000003FFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000001FFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000FFFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000007FFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000003FFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000001FFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000000FFFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000007FFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000003FFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000001FFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000000FFFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000007FFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000003FFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000001FFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000FFF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000000007FF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000000003FF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000000001FF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x00000000000000FF ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000000007F ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000000003F ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000000001F ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x000000000000000F ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000007 ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000003 ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000001 ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0xFFFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x7FFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x3FFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x1FFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0FFFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x07FFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x03FFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x01FFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00FFFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x007FFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x003FFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x001FFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000FFFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0007FFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0003FFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0001FFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000FFFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00007FFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00003FFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00001FFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000FFFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000007FFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000003FFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000001FFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000FFFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000007FFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000003FFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000001FFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000FFFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000007FFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000003FFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000001FFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000FFFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000007FFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000003FFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000001FFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000FFFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000007FFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000003FFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000001FFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000FFFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000007FFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000003FFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000001FFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000000FFFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000007FFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000003FFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000001FFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000000FFFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000007FFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000003FFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000001FFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000FFF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000000007FF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000000003FF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000000001FF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x00000000000000FF ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000000007F ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000000003F ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000000001F ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x000000000000000F ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000007 ) },
+    { UINT64_C( 0x0000000000000000 ), UINT64_C( 0x0000000000000003 ) }
+};
+
+static const uint_fast64_t f128NumQInP1 = f128NumQIn * f128NumP1;
+static const uint_fast64_t f128NumQOutP1 = f128NumQOut * f128NumP1;
+
+static void f128NextQInP1( struct sequence *sequencePtr, float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int expNum, sigNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZPtr->v64 = f128QIn[expNum] | f128P1[sigNum].v64;
+    uiZPtr->v0  = f128P1[sigNum].v0;
+    ++sigNum;
+    if ( f128NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f128NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static void f128NextQOutP1( struct sequence *sequencePtr, float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int expNum, sigNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZPtr->v64 = f128QOut[expNum] | f128P1[sigNum].v64;
+    uiZPtr->v0 = f128P1[sigNum].v0;
+    ++sigNum;
+    if ( f128NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f128NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static const uint_fast64_t f128NumQInP2 = f128NumQIn * f128NumP2;
+static const uint_fast64_t f128NumQOutP2 = f128NumQOut * f128NumP2;
+
+static void f128NextQInP2( struct sequence *sequencePtr, float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int expNum, sigNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZPtr->v64 = f128QIn[expNum] | f128P2[sigNum].v64;
+    uiZPtr->v0 = f128P2[sigNum].v0;
+    ++sigNum;
+    if ( f128NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f128NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static void f128NextQOutP2( struct sequence *sequencePtr, float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int expNum, sigNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uiZPtr->v64 = f128QOut[expNum] | f128P2[sigNum].v64;
+    uiZPtr->v0 = f128P2[sigNum].v0;
+    ++sigNum;
+    if ( f128NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f128NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+
+}
+
+static void f128RandomQOutP3( float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int sigNum1, sigNum2;
+    uint_fast64_t sig1_0;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    sigNum1 = randomN_ui16( f128NumP2 );
+    sigNum2 = randomN_ui16( f128NumP2 );
+    sig1_0 = f128P2[sigNum1].v0;
+    uiZPtr->v0 = sig1_0 + f128P2[sigNum2].v0;
+    uiZPtr->v64 =
+          f128QOut[randomN_ui8( f128NumQOut )]
+        | ((f128P2[sigNum1].v64 + f128P2[sigNum2].v64 + (uiZPtr->v0 < sig1_0))
+               & UINT64_C( 0x0000FFFFFFFFFFFF ));
+
+}
+
+static void f128RandomQOutPInf( float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    uiZPtr->v64 =
+          f128QOut[randomN_ui8( f128NumQOut )]
+        | (random_ui64() & UINT64_C( 0x0000FFFFFFFFFFFF ));
+    uiZPtr->v0 = random_ui64();
+
+}
+
+enum { f128NumQInfWeightMasks = 14 };
+static const uint64_t f128QInfWeightMasks[f128NumQInfWeightMasks] = {
+    UINT64_C( 0xFFFF000000000000 ),
+    UINT64_C( 0xFFFF000000000000 ),
+    UINT64_C( 0xBFFF000000000000 ),
+    UINT64_C( 0x9FFF000000000000 ),
+    UINT64_C( 0x87FF000000000000 ),
+    UINT64_C( 0x87FF000000000000 ),
+    UINT64_C( 0x83FF000000000000 ),
+    UINT64_C( 0x81FF000000000000 ),
+    UINT64_C( 0x80FF000000000000 ),
+    UINT64_C( 0x807F000000000000 ),
+    UINT64_C( 0x803F000000000000 ),
+    UINT64_C( 0x801F000000000000 ),
+    UINT64_C( 0x800F000000000000 ),
+    UINT64_C( 0x8007000000000000 )
+};
+static const uint64_t f128QInfWeightOffsets[f128NumQInfWeightMasks] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x2000000000000000 ),
+    UINT64_C( 0x3000000000000000 ),
+    UINT64_C( 0x3800000000000000 ),
+    UINT64_C( 0x3C00000000000000 ),
+    UINT64_C( 0x3E00000000000000 ),
+    UINT64_C( 0x3F00000000000000 ),
+    UINT64_C( 0x3F80000000000000 ),
+    UINT64_C( 0x3FC0000000000000 ),
+    UINT64_C( 0x3FE0000000000000 ),
+    UINT64_C( 0x3FF0000000000000 ),
+    UINT64_C( 0x3FF8000000000000 ),
+    UINT64_C( 0x3FFC000000000000 )
+};
+
+static void f128RandomQInfP3( float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int sigNum1, sigNum2;
+    uint_fast64_t sig1_0;
+    int weightMaskNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    sigNum1 = randomN_ui16( f128NumP2 );
+    sigNum2 = randomN_ui16( f128NumP2 );
+    sig1_0 = f128P2[sigNum1].v0;
+    uiZPtr->v0 = sig1_0 + f128P2[sigNum2].v0;
+    weightMaskNum = randomN_ui8( f128NumQInfWeightMasks );
+    uiZPtr->v64 =
+          (((uint_fast64_t) random_ui16()<<48
+                & f128QInfWeightMasks[weightMaskNum])
+               + f128QInfWeightOffsets[weightMaskNum])
+        | ((f128P2[sigNum1].v64 + f128P2[sigNum2].v64 + (uiZPtr->v0 < sig1_0))
+               & UINT64_C( 0x0000FFFFFFFFFFFF ));
+
+}
+
+static void f128RandomQInfPInf( float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    int weightMaskNum;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    weightMaskNum = randomN_ui8( f128NumQInfWeightMasks );
+    uiZPtr->v64 =
+        (random_ui64()
+             & (f128QInfWeightMasks[weightMaskNum]
+                    | UINT64_C( 0x0000FFFFFFFFFFFF )))
+            + f128QInfWeightOffsets[weightMaskNum];
+    uiZPtr->v0 = random_ui64();
+
+}
+
+static void f128Random( float128_t *zPtr )
+{
+
+    switch ( random_ui8() & 7 ) {
+     case 0:
+     case 1:
+     case 2:
+        f128RandomQOutP3( zPtr );
+        break;
+     case 3:
+        f128RandomQOutPInf( zPtr );
+        break;
+     case 4:
+     case 5:
+     case 6:
+        f128RandomQInfP3( zPtr );
+        break;
+     case 7:
+        f128RandomQInfPInf( zPtr );
+        break;
+    }
+
+}
+
+static struct sequence sequenceA, sequenceB, sequenceC;
+static float128_t currentA, currentB, currentC;
+static int subcase;
+
+float128_t genCases_f128_a, genCases_f128_b, genCases_f128_c;
+
+void genCases_f128_a_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total =
+        (genCases_level == 1) ? 3 * f128NumQOutP1 : 2 * f128NumQOutP2;
+    genCases_done = false;
+
+}
+
+void genCases_f128_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+         case 1:
+            f128Random( &genCases_f128_a );
+            break;
+         case 2:
+            f128NextQOutP1( &sequenceA, &genCases_f128_a );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+     } else {
+        switch ( subcase ) {
+         case 0:
+            f128Random( &genCases_f128_a );
+            break;
+         case 1:
+            f128NextQOutP2( &sequenceA, &genCases_f128_a );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f128_ab_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 6 * f128NumQInP1 * f128NumQInP1;
+        f128NextQInP1( &sequenceA, &currentA );
+    } else {
+        genCases_total = 2 * f128NumQInP2 * f128NumQInP2;
+        f128NextQInP2( &sequenceA, &currentA );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f128_ab_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                f128NextQInP1( &sequenceA, &currentA );
+            }
+            f128NextQInP1( &sequenceB, &currentB );
+         case 2:
+         case 4:
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            break;
+         case 1:
+            genCases_f128_a = currentA;
+            f128Random( &genCases_f128_b );
+            break;
+         case 3:
+            f128Random( &genCases_f128_a );
+            genCases_f128_b = currentB;
+            break;
+         case 5:
+            genCases_f128_a = currentA;
+            genCases_f128_b = currentB;
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            break;
+         case 1:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                f128NextQInP2( &sequenceA, &currentA );
+            }
+            genCases_f128_a = currentA;
+            f128NextQInP2( &sequenceB, &genCases_f128_b );
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f128_abc_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    sequenceC.expNum = 0;
+    sequenceC.term1Num = 0;
+    sequenceC.term2Num = 0;
+    sequenceC.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 9 * f128NumQInP1 * f128NumQInP1 * f128NumQInP1;
+        f128NextQInP1( &sequenceA, &currentA );
+        f128NextQInP1( &sequenceB, &currentB );
+    } else {
+        genCases_total = 2 * f128NumQInP2 * f128NumQInP2 * f128NumQInP2;
+        f128NextQInP2( &sequenceA, &currentA );
+        f128NextQInP2( &sequenceB, &currentB );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f128_abc_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    f128NextQInP1( &sequenceA, &currentA );
+                }
+                f128NextQInP1( &sequenceB, &currentB );
+            }
+            f128NextQInP1( &sequenceC, &currentC );
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            genCases_f128_c = currentC;
+            break;
+         case 1:
+            genCases_f128_a = currentA;
+            genCases_f128_b = currentB;
+            f128Random( &genCases_f128_c );
+            break;
+         case 2:
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            f128Random( &genCases_f128_c );
+            break;
+         case 3:
+            f128Random( &genCases_f128_a );
+            genCases_f128_b = currentB;
+            genCases_f128_c = currentC;
+            break;
+         case 4:
+            genCases_f128_a = currentA;
+            f128Random( &genCases_f128_b );
+            f128Random( &genCases_f128_c );
+            break;
+         case 5:
+            f128Random( &genCases_f128_a );
+            genCases_f128_b = currentB;
+            f128Random( &genCases_f128_c );
+            break;
+         case 6:
+            genCases_f128_a = currentA;
+            f128Random( &genCases_f128_b );
+            genCases_f128_c = currentC;
+            break;
+         case 7:
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            f128Random( &genCases_f128_c );
+            break;
+         case 8:
+            genCases_f128_a = currentA;
+            genCases_f128_b = currentB;
+            genCases_f128_c = currentC;
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            f128Random( &genCases_f128_a );
+            f128Random( &genCases_f128_b );
+            f128Random( &genCases_f128_c );
+            break;
+         case 1:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    f128NextQInP2( &sequenceA, &currentA );
+                }
+                f128NextQInP2( &sequenceB, &currentB );
+            }
+            genCases_f128_a = currentA;
+            genCases_f128_b = currentB;
+            f128NextQInP2( &sequenceC, &genCases_f128_c );
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/genCases_f16.c b/addins/TestFloat-3e/source/genCases_f16.c
new file mode 100644
index 000000000..dd2ebbce4
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_f16.c
@@ -0,0 +1,585 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "softfloat.h"
+#include "genCases.h"
+
+#ifdef FLOAT16
+
+struct sequence {
+    int expNum, term1Num, term2Num;
+    bool done;
+};
+
+union ui16_f16 { uint16_t ui; float16_t f; };
+
+enum {
+    f16NumQIn  = 22,
+    f16NumQOut = 34,
+    f16NumP1   =  4,
+    f16NumP2   = 36
+};
+static const uint16_t f16QIn[f16NumQIn] = {
+    0x0000,    /* positive, subnormal       */
+    0x0400,    /* positive, -14             */
+    0x1000,    /* positive, -11             */
+    0x3400,    /* positive,  -2             */
+    0x3800,    /* positive,  -1             */
+    0x3C00,    /* positive,   0             */
+    0x4000,    /* positive,   1             */
+    0x4400,    /* positive,   2             */
+    0x6800,    /* positive,  11             */
+    0x7800,    /* positive,  15             */
+    0x7C00,    /* positive, infinity or NaN */
+    0x8000,    /* negative, subnormal       */
+    0x8400,    /* negative, -14             */
+    0x9000,    /* negative, -11             */
+    0xB400,    /* negative,  -2             */
+    0xB800,    /* negative,  -1             */
+    0xBC00,    /* negative,   0             */
+    0xC000,    /* negative,   1             */
+    0xC400,    /* negative,   2             */
+    0xE800,    /* negative,  11             */
+    0xF800,    /* negative,  15             */
+    0xFC00     /* negative, infinity or NaN */
+};
+static const uint16_t f16QOut[f16NumQOut] = {
+    0x0000,    /* positive, subnormal       */
+    0x0400,    /* positive, -14             */
+    0x0800,    /* positive, -13             */
+    0x1000,    /* positive, -11             */
+    0x2C00,    /* positive,  -4             */
+    0x3000,    /* positive,  -3             */
+    0x3400,    /* positive,  -2             */
+    0x3800,    /* positive,  -1             */
+    0x3C00,    /* positive,   0             */
+    0x4000,    /* positive,   1             */
+    0x4400,    /* positive,   2             */
+    0x4800,    /* positive,   3             */
+    0x4C00,    /* positive,   4             */
+    0x6800,    /* positive,  11             */
+    0x7400,    /* positive,  14             */
+    0x7800,    /* positive,  15             */
+    0x7C00,    /* positive, infinity or NaN */
+    0x8000,    /* negative, subnormal       */
+    0x8400,    /* negative, -14             */
+    0x8800,    /* negative, -13             */
+    0x9000,    /* negative, -11             */
+    0xAC00,    /* negative,  -4             */
+    0xB000,    /* negative,  -3             */
+    0xB400,    /* negative,  -2             */
+    0xB800,    /* negative,  -1             */
+    0xBC00,    /* negative,   0             */
+    0xC000,    /* negative,   1             */
+    0xC400,    /* negative,   2             */
+    0xC800,    /* negative,   3             */
+    0xCC00,    /* negative,   4             */
+    0xE800,    /* negative,  11             */
+    0xF400,    /* negative,  14             */
+    0xF800,    /* negative,  15             */
+    0xFC00     /* negative, infinity or NaN */
+};
+static const uint16_t f16P1[f16NumP1] = {
+    0x0000,
+    0x0001,
+    0x03FF,
+    0x03FE
+};
+static const uint16_t f16P2[f16NumP2] = {
+    0x0000,
+    0x0001,
+    0x0002,
+    0x0004,
+    0x0008,
+    0x0010,
+    0x0020,
+    0x0040,
+    0x0080,
+    0x0100,
+    0x0200,
+    0x0300,
+    0x0380,
+    0x03C0,
+    0x03E0,
+    0x03F0,
+    0x03F8,
+    0x03FC,
+    0x03FE,
+    0x03FF,
+    0x03FD,
+    0x03FB,
+    0x03F7,
+    0x03EF,
+    0x03DF,
+    0x03BF,
+    0x037F,
+    0x02FF,
+    0x01FF,
+    0x00FF,
+    0x007F,
+    0x003F,
+    0x001F,
+    0x000F,
+    0x0007,
+    0x0003
+};
+
+static const uint_fast64_t f16NumQInP1 = f16NumQIn * f16NumP1;
+static const uint_fast64_t f16NumQOutP1 = f16NumQOut * f16NumP1;
+
+static float16_t f16NextQInP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui16_f16 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f16QIn[expNum] | f16P1[sigNum];
+    ++sigNum;
+    if ( f16NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f16NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float16_t f16NextQOutP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui16_f16 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f16QOut[expNum] | f16P1[sigNum];
+    ++sigNum;
+    if ( f16NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f16NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static const uint_fast64_t f16NumQInP2 = f16NumQIn * f16NumP2;
+static const uint_fast64_t f16NumQOutP2 = f16NumQOut * f16NumP2;
+
+static float16_t f16NextQInP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui16_f16 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f16QIn[expNum] | f16P2[sigNum];
+    ++sigNum;
+    if ( f16NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f16NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float16_t f16NextQOutP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui16_f16 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f16QOut[expNum] | f16P2[sigNum];
+    ++sigNum;
+    if ( f16NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f16NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float16_t f16RandomQOutP3( void )
+{
+    union ui16_f16 uZ;
+
+    uZ.ui =
+          f16QOut[randomN_ui8( f16NumQOut )]
+        | ((f16P2[randomN_ui8( f16NumP2 )] + f16P2[randomN_ui8( f16NumP2 )])
+               & 0x03FF);
+    return uZ.f;
+
+}
+
+static float16_t f16RandomQOutPInf( void )
+{
+    union ui16_f16 uZ;
+
+    uZ.ui = f16QOut[randomN_ui8( f16NumQOut )] | (random_ui16() & 0x03FF);
+    return uZ.f;
+
+}
+
+enum { f16NumQInfWeightMasks = 4 };
+static const uint16_t f16QInfWeightMasks[f16NumQInfWeightMasks] =
+    { 0xFC00, 0xFC00, 0xBC00, 0x9C00 };
+static const uint16_t f16QInfWeightOffsets[f16NumQInfWeightMasks] =
+    { 0x0000, 0x0000, 0x2000, 0x3000 };
+
+static float16_t f16RandomQInfP3( void )
+{
+    int weightMaskNum;
+    union ui16_f16 uZ;
+
+    weightMaskNum = randomN_ui8( f16NumQInfWeightMasks );
+    uZ.ui =
+          ((random_ui16() & f16QInfWeightMasks[weightMaskNum])
+               + f16QInfWeightOffsets[weightMaskNum])
+        | ((f16P2[randomN_ui8( f16NumP2 )] + f16P2[randomN_ui8( f16NumP2 )])
+               & 0x03FF);
+    return uZ.f;
+
+}
+
+static float16_t f16RandomQInfPInf( void )
+{
+    int weightMaskNum;
+    union ui16_f16 uZ;
+
+    weightMaskNum = randomN_ui8( f16NumQInfWeightMasks );
+    uZ.ui =
+        (random_ui16() & (f16QInfWeightMasks[weightMaskNum] | 0x03FF))
+            + f16QInfWeightOffsets[weightMaskNum];
+    return uZ.f;
+
+}
+
+static float16_t f16Random( void )
+{
+
+    switch ( random_ui8() & 7 ) {
+     case 0:
+     case 1:
+     case 2:
+        return f16RandomQOutP3();
+     case 3:
+        return f16RandomQOutPInf();
+     case 4:
+     case 5:
+     case 6:
+        return f16RandomQInfP3();
+     case 7:
+        return f16RandomQInfPInf();
+    }
+
+}
+
+static struct sequence sequenceA, sequenceB, sequenceC;
+static float16_t currentA, currentB, currentC;
+static int subcase;
+
+float16_t genCases_f16_a, genCases_f16_b, genCases_f16_c;
+
+void genCases_f16_a_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total =
+        (genCases_level == 1) ? 3 * f16NumQOutP1 : 2 * f16NumQOutP2;
+    genCases_done = false;
+
+}
+
+void genCases_f16_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+         case 1:
+            genCases_f16_a = f16Random();
+            break;
+         case 2:
+            genCases_f16_a = f16NextQOutP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f16_a = f16Random();
+            break;
+         case 1:
+            genCases_f16_a = f16NextQOutP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f16_ab_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 6 * f16NumQInP1 * f16NumQInP1;
+        currentA = f16NextQInP1( &sequenceA );
+    } else {
+        genCases_total = 2 * f16NumQInP2 * f16NumQInP2;
+        currentA = f16NextQInP2( &sequenceA );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f16_ab_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f16NextQInP1( &sequenceA );
+            }
+            currentB = f16NextQInP1( &sequenceB );
+         case 2:
+         case 4:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            break;
+         case 1:
+            genCases_f16_a = currentA;
+            genCases_f16_b = f16Random();
+            break;
+         case 3:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = currentB;
+            break;
+         case 5:
+            genCases_f16_a = currentA;
+            genCases_f16_b = currentB;
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            break;
+         case 1:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f16NextQInP2( &sequenceA );
+            }
+            genCases_f16_a = currentA;
+            genCases_f16_b = f16NextQInP2( &sequenceB );
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f16_abc_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    sequenceC.expNum = 0;
+    sequenceC.term1Num = 0;
+    sequenceC.term2Num = 0;
+    sequenceC.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 9 * f16NumQInP1 * f16NumQInP1 * f16NumQInP1;
+        currentA = f16NextQInP1( &sequenceA );
+        currentB = f16NextQInP1( &sequenceB );
+    } else {
+        genCases_total = 2 * f16NumQInP2 * f16NumQInP2 * f16NumQInP2;
+        currentA = f16NextQInP2( &sequenceA );
+        currentB = f16NextQInP2( &sequenceB );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f16_abc_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f16NextQInP1( &sequenceA );
+                }
+                currentB = f16NextQInP1( &sequenceB );
+            }
+            currentC = f16NextQInP1( &sequenceC );
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            genCases_f16_c = currentC;
+            break;
+         case 1:
+            genCases_f16_a = currentA;
+            genCases_f16_b = currentB;
+            genCases_f16_c = f16Random();
+            break;
+         case 2:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            genCases_f16_c = f16Random();
+            break;
+         case 3:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = currentB;
+            genCases_f16_c = currentC;
+            break;
+         case 4:
+            genCases_f16_a = currentA;
+            genCases_f16_b = f16Random();
+            genCases_f16_c = f16Random();
+            break;
+         case 5:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = currentB;
+            genCases_f16_c = f16Random();
+            break;
+         case 6:
+            genCases_f16_a = currentA;
+            genCases_f16_b = f16Random();
+            genCases_f16_c = currentC;
+            break;
+         case 7:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            genCases_f16_c = f16Random();
+            break;
+         case 8:
+            genCases_f16_a = currentA;
+            genCases_f16_b = currentB;
+            genCases_f16_c = currentC;
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f16_a = f16Random();
+            genCases_f16_b = f16Random();
+            genCases_f16_c = f16Random();
+            break;
+         case 1:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f16NextQInP2( &sequenceA );
+                }
+                currentB = f16NextQInP2( &sequenceB );
+            }
+            genCases_f16_a = currentA;
+            genCases_f16_b = currentB;
+            genCases_f16_c = f16NextQInP2( &sequenceC );
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/genCases_f32.c b/addins/TestFloat-3e/source/genCases_f32.c
new file mode 100644
index 000000000..bb08ae902
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_f32.c
@@ -0,0 +1,664 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "softfloat.h"
+#include "genCases.h"
+
+struct sequence {
+    int expNum, term1Num, term2Num;
+    bool done;
+};
+
+union ui32_f32 { uint32_t ui; float32_t f; };
+
+enum {
+    f32NumQIn  = 22,
+    f32NumQOut = 50,
+    f32NumP1   =  4,
+    f32NumP2   = 88
+};
+static const uint32_t f32QIn[f32NumQIn] = {
+    0x00000000,    /* positive, subnormal       */
+    0x00800000,    /* positive, -126            */
+    0x33800000,    /* positive,  -24            */
+    0x3E800000,    /* positive,   -2            */
+    0x3F000000,    /* positive,   -1            */
+    0x3F800000,    /* positive,    0            */
+    0x40000000,    /* positive,    1            */
+    0x40800000,    /* positive,    2            */
+    0x4B800000,    /* positive,   24            */
+    0x7F000000,    /* positive,  127            */
+    0x7F800000,    /* positive, infinity or NaN */
+    0x80000000,    /* negative, subnormal       */
+    0x80800000,    /* negative, -126            */
+    0xB3800000,    /* negative,  -24            */
+    0xBE800000,    /* negative,   -2            */
+    0xBF000000,    /* negative,   -1            */
+    0xBF800000,    /* negative,    0            */
+    0xC0000000,    /* negative,    1            */
+    0xC0800000,    /* negative,    2            */
+    0xCB800000,    /* negative,   24            */
+    0xFE800000,    /* negative,  126            */
+    0xFF800000     /* negative, infinity or NaN */
+};
+static const uint32_t f32QOut[f32NumQOut] = {
+    0x00000000,    /* positive, subnormal       */
+    0x00800000,    /* positive, -126            */
+    0x01000000,    /* positive, -125            */
+    0x33800000,    /* positive,  -24            */
+    0x3D800000,    /* positive,   -4            */
+    0x3E000000,    /* positive,   -3            */
+    0x3E800000,    /* positive,   -2            */
+    0x3F000000,    /* positive,   -1            */
+    0x3F800000,    /* positive,    0            */
+    0x40000000,    /* positive,    1            */
+    0x40800000,    /* positive,    2            */
+    0x41000000,    /* positive,    3            */
+    0x41800000,    /* positive,    4            */
+    0x4B800000,    /* positive,   24            */
+    0x4E000000,    /* positive,   29            */
+    0x4E800000,    /* positive,   30            */
+    0x4F000000,    /* positive,   31            */
+    0x4F800000,    /* positive,   32            */
+    0x5E000000,    /* positive,   61            */
+    0x5E800000,    /* positive,   62            */
+    0x5F000000,    /* positive,   63            */
+    0x5F800000,    /* positive,   64            */
+    0x7E800000,    /* positive,  126            */
+    0x7F000000,    /* positive,  127            */
+    0x7F800000,    /* positive, infinity or NaN */
+    0x80000000,    /* negative, subnormal       */
+    0x80800000,    /* negative, -126            */
+    0x81000000,    /* negative, -125            */
+    0xB3800000,    /* negative,  -24            */
+    0xBD800000,    /* negative,   -4            */
+    0xBE000000,    /* negative,   -3            */
+    0xBE800000,    /* negative,   -2            */
+    0xBF000000,    /* negative,   -1            */
+    0xBF800000,    /* negative,    0            */
+    0xC0000000,    /* negative,    1            */
+    0xC0800000,    /* negative,    2            */
+    0xC1000000,    /* negative,    3            */
+    0xC1800000,    /* negative,    4            */
+    0xCB800000,    /* negative,   24            */
+    0xCE000000,    /* negative,   29            */
+    0xCE800000,    /* negative,   30            */
+    0xCF000000,    /* negative,   31            */
+    0xCF800000,    /* negative,   32            */
+    0xDE000000,    /* negative,   61            */
+    0xDE800000,    /* negative,   62            */
+    0xDF000000,    /* negative,   63            */
+    0xDF800000,    /* negative,   64            */
+    0xFE800000,    /* negative,  126            */
+    0xFF000000,    /* negative,  127            */
+    0xFF800000     /* negative, infinity or NaN */
+};
+static const uint32_t f32P1[f32NumP1] = {
+    0x00000000,
+    0x00000001,
+    0x007FFFFF,
+    0x007FFFFE
+};
+static const uint32_t f32P2[f32NumP2] = {
+    0x00000000,
+    0x00000001,
+    0x00000002,
+    0x00000004,
+    0x00000008,
+    0x00000010,
+    0x00000020,
+    0x00000040,
+    0x00000080,
+    0x00000100,
+    0x00000200,
+    0x00000400,
+    0x00000800,
+    0x00001000,
+    0x00002000,
+    0x00004000,
+    0x00008000,
+    0x00010000,
+    0x00020000,
+    0x00040000,
+    0x00080000,
+    0x00100000,
+    0x00200000,
+    0x00400000,
+    0x00600000,
+    0x00700000,
+    0x00780000,
+    0x007C0000,
+    0x007E0000,
+    0x007F0000,
+    0x007F8000,
+    0x007FC000,
+    0x007FE000,
+    0x007FF000,
+    0x007FF800,
+    0x007FFC00,
+    0x007FFE00,
+    0x007FFF00,
+    0x007FFF80,
+    0x007FFFC0,
+    0x007FFFE0,
+    0x007FFFF0,
+    0x007FFFF8,
+    0x007FFFFC,
+    0x007FFFFE,
+    0x007FFFFF,
+    0x007FFFFD,
+    0x007FFFFB,
+    0x007FFFF7,
+    0x007FFFEF,
+    0x007FFFDF,
+    0x007FFFBF,
+    0x007FFF7F,
+    0x007FFEFF,
+    0x007FFDFF,
+    0x007FFBFF,
+    0x007FF7FF,
+    0x007FEFFF,
+    0x007FDFFF,
+    0x007FBFFF,
+    0x007F7FFF,
+    0x007EFFFF,
+    0x007DFFFF,
+    0x007BFFFF,
+    0x0077FFFF,
+    0x006FFFFF,
+    0x005FFFFF,
+    0x003FFFFF,
+    0x001FFFFF,
+    0x000FFFFF,
+    0x0007FFFF,
+    0x0003FFFF,
+    0x0001FFFF,
+    0x0000FFFF,
+    0x00007FFF,
+    0x00003FFF,
+    0x00001FFF,
+    0x00000FFF,
+    0x000007FF,
+    0x000003FF,
+    0x000001FF,
+    0x000000FF,
+    0x0000007F,
+    0x0000003F,
+    0x0000001F,
+    0x0000000F,
+    0x00000007,
+    0x00000003
+};
+
+static const uint_fast64_t f32NumQInP1 = f32NumQIn * f32NumP1;
+static const uint_fast64_t f32NumQOutP1 = f32NumQOut * f32NumP1;
+
+static float32_t f32NextQInP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui32_f32 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f32QIn[expNum] | f32P1[sigNum];
+    ++sigNum;
+    if ( f32NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f32NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float32_t f32NextQOutP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui32_f32 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f32QOut[expNum] | f32P1[sigNum];
+    ++sigNum;
+    if ( f32NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f32NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static const uint_fast64_t f32NumQInP2 = f32NumQIn * f32NumP2;
+static const uint_fast64_t f32NumQOutP2 = f32NumQOut * f32NumP2;
+
+static float32_t f32NextQInP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui32_f32 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f32QIn[expNum] | f32P2[sigNum];
+    ++sigNum;
+    if ( f32NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f32NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float32_t f32NextQOutP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui32_f32 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f32QOut[expNum] | f32P2[sigNum];
+    ++sigNum;
+    if ( f32NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f32NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float32_t f32RandomQOutP3( void )
+{
+    union ui32_f32 uZ;
+
+    uZ.ui =
+          f32QOut[randomN_ui8( f32NumQOut )]
+        | ((f32P2[randomN_ui8( f32NumP2 )] + f32P2[randomN_ui8( f32NumP2 )])
+               & 0x007FFFFF);
+    return uZ.f;
+
+}
+
+static float32_t f32RandomQOutPInf( void )
+{
+    union ui32_f32 uZ;
+
+    uZ.ui = f32QOut[randomN_ui8( f32NumQOut )] | (random_ui32() & 0x007FFFFF);
+    return uZ.f;
+
+}
+
+enum { f32NumQInfWeightMasks = 7 };
+static const uint32_t f32QInfWeightMasks[f32NumQInfWeightMasks] = {
+    0xFF800000,
+    0xFF800000,
+    0xBF800000,
+    0x9F800000,
+    0x8F800000,
+    0x87800000,
+    0x83800000
+};
+static const uint32_t f32QInfWeightOffsets[f32NumQInfWeightMasks] = {
+    0x00000000,
+    0x00000000,
+    0x20000000,
+    0x30000000,
+    0x38000000,
+    0x3C000000,
+    0x3E000000
+};
+
+static float32_t f32RandomQInfP3( void )
+{
+    int weightMaskNum;
+    union ui32_f32 uZ;
+
+    weightMaskNum = randomN_ui8( f32NumQInfWeightMasks );
+    uZ.ui =
+          (((uint_fast32_t) random_ui16()<<16
+                & f32QInfWeightMasks[weightMaskNum])
+               + f32QInfWeightOffsets[weightMaskNum])
+        | ((f32P2[randomN_ui8( f32NumP2 )] + f32P2[randomN_ui8( f32NumP2 )])
+               & 0x007FFFFF);
+    return uZ.f;
+
+}
+
+static float32_t f32RandomQInfPInf( void )
+{
+    int weightMaskNum;
+    union ui32_f32 uZ;
+
+    weightMaskNum = randomN_ui8( f32NumQInfWeightMasks );
+    uZ.ui =
+        (random_ui32() & (f32QInfWeightMasks[weightMaskNum] | 0x007FFFFF))
+            + f32QInfWeightOffsets[weightMaskNum];
+    return uZ.f;
+
+}
+
+static float32_t f32Random( void )
+{
+
+    switch ( random_ui8() & 7 ) {
+     case 0:
+     case 1:
+     case 2:
+        return f32RandomQOutP3();
+     case 3:
+        return f32RandomQOutPInf();
+     case 4:
+     case 5:
+     case 6:
+        return f32RandomQInfP3();
+     case 7:
+        return f32RandomQInfPInf();
+    }
+
+}
+
+static struct sequence sequenceA, sequenceB, sequenceC;
+static float32_t currentA, currentB, currentC;
+static int subcase;
+
+float32_t genCases_f32_a, genCases_f32_b, genCases_f32_c;
+
+void genCases_f32_a_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total =
+        (genCases_level == 1) ? 3 * f32NumQOutP1 : 2 * f32NumQOutP2;
+    genCases_done = false;
+
+}
+
+void genCases_f32_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+         case 1:
+            genCases_f32_a = f32Random();
+            break;
+         case 2:
+            genCases_f32_a = f32NextQOutP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f32_a = f32Random();
+            break;
+         case 1:
+            genCases_f32_a = f32NextQOutP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f32_ab_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 6 * f32NumQInP1 * f32NumQInP1;
+        currentA = f32NextQInP1( &sequenceA );
+    } else {
+        genCases_total = 2 * f32NumQInP2 * f32NumQInP2;
+        currentA = f32NextQInP2( &sequenceA );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f32_ab_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f32NextQInP1( &sequenceA );
+            }
+            currentB = f32NextQInP1( &sequenceB );
+         case 2:
+         case 4:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            break;
+         case 1:
+            genCases_f32_a = currentA;
+            genCases_f32_b = f32Random();
+            break;
+         case 3:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = currentB;
+            break;
+         case 5:
+            genCases_f32_a = currentA;
+            genCases_f32_b = currentB;
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            break;
+         case 1:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f32NextQInP2( &sequenceA );
+            }
+            genCases_f32_a = currentA;
+            genCases_f32_b = f32NextQInP2( &sequenceB );
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f32_abc_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    sequenceC.expNum = 0;
+    sequenceC.term1Num = 0;
+    sequenceC.term2Num = 0;
+    sequenceC.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 9 * f32NumQInP1 * f32NumQInP1 * f32NumQInP1;
+        currentA = f32NextQInP1( &sequenceA );
+        currentB = f32NextQInP1( &sequenceB );
+    } else {
+        genCases_total = 2 * f32NumQInP2 * f32NumQInP2 * f32NumQInP2;
+        currentA = f32NextQInP2( &sequenceA );
+        currentB = f32NextQInP2( &sequenceB );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f32_abc_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f32NextQInP1( &sequenceA );
+                }
+                currentB = f32NextQInP1( &sequenceB );
+            }
+            currentC = f32NextQInP1( &sequenceC );
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            genCases_f32_c = currentC;
+            break;
+         case 1:
+            genCases_f32_a = currentA;
+            genCases_f32_b = currentB;
+            genCases_f32_c = f32Random();
+            break;
+         case 2:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            genCases_f32_c = f32Random();
+            break;
+         case 3:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = currentB;
+            genCases_f32_c = currentC;
+            break;
+         case 4:
+            genCases_f32_a = currentA;
+            genCases_f32_b = f32Random();
+            genCases_f32_c = f32Random();
+            break;
+         case 5:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = currentB;
+            genCases_f32_c = f32Random();
+            break;
+         case 6:
+            genCases_f32_a = currentA;
+            genCases_f32_b = f32Random();
+            genCases_f32_c = currentC;
+            break;
+         case 7:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            genCases_f32_c = f32Random();
+            break;
+         case 8:
+            genCases_f32_a = currentA;
+            genCases_f32_b = currentB;
+            genCases_f32_c = currentC;
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f32_a = f32Random();
+            genCases_f32_b = f32Random();
+            genCases_f32_c = f32Random();
+            break;
+         case 1:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f32NextQInP2( &sequenceA );
+                }
+                currentB = f32NextQInP2( &sequenceB );
+            }
+            genCases_f32_a = currentA;
+            genCases_f32_b = currentB;
+            genCases_f32_c = f32NextQInP2( &sequenceC );
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
diff --git a/addins/TestFloat-3e/source/genCases_f64.c b/addins/TestFloat-3e/source/genCases_f64.c
new file mode 100644
index 000000000..61b34dc2e
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_f64.c
@@ -0,0 +1,808 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "softfloat.h"
+#include "genCases.h"
+
+#ifdef FLOAT64
+
+struct sequence {
+    int expNum, term1Num, term2Num;
+    bool done;
+};
+
+union ui64_f64 { uint64_t ui; float64_t f; };
+
+enum {
+    f64NumQIn  =  22,
+    f64NumQOut =  64,
+    f64NumP1   =   4,
+    f64NumP2   = 204
+};
+static const uint64_t f64QIn[f64NumQIn] = {
+    UINT64_C( 0x0000000000000000 ),    /* positive, subnormal       */
+    UINT64_C( 0x0010000000000000 ),    /* positive, -1022           */
+    UINT64_C( 0x3CA0000000000000 ),    /* positive,   -53           */
+    UINT64_C( 0x3FD0000000000000 ),    /* positive,    -2           */
+    UINT64_C( 0x3FE0000000000000 ),    /* positive,    -1           */
+    UINT64_C( 0x3FF0000000000000 ),    /* positive,     0           */
+    UINT64_C( 0x4000000000000000 ),    /* positive,     1           */
+    UINT64_C( 0x4010000000000000 ),    /* positive,     2           */
+    UINT64_C( 0x4340000000000000 ),    /* positive,    53           */
+    UINT64_C( 0x7FE0000000000000 ),    /* positive,  1023           */
+    UINT64_C( 0x7FF0000000000000 ),    /* positive, infinity or NaN */
+    UINT64_C( 0x8000000000000000 ),    /* negative, subnormal       */
+    UINT64_C( 0x8010000000000000 ),    /* negative, -1022           */
+    UINT64_C( 0xBCA0000000000000 ),    /* negative,   -53           */
+    UINT64_C( 0xBFD0000000000000 ),    /* negative,    -2           */
+    UINT64_C( 0xBFE0000000000000 ),    /* negative,    -1           */
+    UINT64_C( 0xBFF0000000000000 ),    /* negative,     0           */
+    UINT64_C( 0xC000000000000000 ),    /* negative,     1           */
+    UINT64_C( 0xC010000000000000 ),    /* negative,     2           */
+    UINT64_C( 0xC340000000000000 ),    /* negative,    53           */
+    UINT64_C( 0xFFE0000000000000 ),    /* negative,  1023           */
+    UINT64_C( 0xFFF0000000000000 )     /* negative, infinity or NaN */
+};
+static const uint64_t f64QOut[f64NumQOut] = {
+    UINT64_C( 0x0000000000000000 ),    /* positive, subnormal       */
+    UINT64_C( 0x0010000000000000 ),    /* positive, -1022           */
+    UINT64_C( 0x0020000000000000 ),    /* positive, -1021           */
+    UINT64_C( 0x37E0000000000000 ),    /* positive,  -129           */
+    UINT64_C( 0x37F0000000000000 ),    /* positive,  -128           */
+    UINT64_C( 0x3800000000000000 ),    /* positive,  -127           */
+    UINT64_C( 0x3810000000000000 ),    /* positive,  -126           */
+    UINT64_C( 0x3CA0000000000000 ),    /* positive,   -53           */
+    UINT64_C( 0x3FB0000000000000 ),    /* positive,    -4           */
+    UINT64_C( 0x3FC0000000000000 ),    /* positive,    -3           */
+    UINT64_C( 0x3FD0000000000000 ),    /* positive,    -2           */
+    UINT64_C( 0x3FE0000000000000 ),    /* positive,    -1           */
+    UINT64_C( 0x3FF0000000000000 ),    /* positive,     0           */
+    UINT64_C( 0x4000000000000000 ),    /* positive,     1           */
+    UINT64_C( 0x4010000000000000 ),    /* positive,     2           */
+    UINT64_C( 0x4020000000000000 ),    /* positive,     3           */
+    UINT64_C( 0x4030000000000000 ),    /* positive,     4           */
+    UINT64_C( 0x41C0000000000000 ),    /* positive,    29           */
+    UINT64_C( 0x41D0000000000000 ),    /* positive,    30           */
+    UINT64_C( 0x41E0000000000000 ),    /* positive,    31           */
+    UINT64_C( 0x41F0000000000000 ),    /* positive,    32           */
+    UINT64_C( 0x4340000000000000 ),    /* positive,    53           */
+    UINT64_C( 0x43C0000000000000 ),    /* positive,    61           */
+    UINT64_C( 0x43D0000000000000 ),    /* positive,    62           */
+    UINT64_C( 0x43E0000000000000 ),    /* positive,    63           */
+    UINT64_C( 0x43F0000000000000 ),    /* positive,    64           */
+    UINT64_C( 0x47E0000000000000 ),    /* positive,   127           */
+    UINT64_C( 0x47F0000000000000 ),    /* positive,   128           */
+    UINT64_C( 0x4800000000000000 ),    /* positive,   129           */
+    UINT64_C( 0x7FD0000000000000 ),    /* positive,  1022           */
+    UINT64_C( 0x7FE0000000000000 ),    /* positive,  1023           */
+    UINT64_C( 0x7FF0000000000000 ),    /* positive, infinity or NaN */
+    UINT64_C( 0x8000000000000000 ),    /* negative, subnormal       */
+    UINT64_C( 0x8010000000000000 ),    /* negative, -1022           */
+    UINT64_C( 0x8020000000000000 ),    /* negative, -1021           */
+    UINT64_C( 0xB7E0000000000000 ),    /* negative,  -129           */
+    UINT64_C( 0xB7F0000000000000 ),    /* negative,  -128           */
+    UINT64_C( 0xB800000000000000 ),    /* negative,  -127           */
+    UINT64_C( 0xB810000000000000 ),    /* negative,  -126           */
+    UINT64_C( 0xBCA0000000000000 ),    /* negative,   -53           */
+    UINT64_C( 0xBFB0000000000000 ),    /* negative,    -4           */
+    UINT64_C( 0xBFC0000000000000 ),    /* negative,    -3           */
+    UINT64_C( 0xBFD0000000000000 ),    /* negative,    -2           */
+    UINT64_C( 0xBFE0000000000000 ),    /* negative,    -1           */
+    UINT64_C( 0xBFF0000000000000 ),    /* negative,     0           */
+    UINT64_C( 0xC000000000000000 ),    /* negative,     1           */
+    UINT64_C( 0xC010000000000000 ),    /* negative,     2           */
+    UINT64_C( 0xC020000000000000 ),    /* negative,     3           */
+    UINT64_C( 0xC030000000000000 ),    /* negative,     4           */
+    UINT64_C( 0xC1C0000000000000 ),    /* negative,    29           */
+    UINT64_C( 0xC1D0000000000000 ),    /* negative,    30           */
+    UINT64_C( 0xC1E0000000000000 ),    /* negative,    31           */
+    UINT64_C( 0xC1F0000000000000 ),    /* negative,    32           */
+    UINT64_C( 0xC340000000000000 ),    /* negative,    53           */
+    UINT64_C( 0xC3C0000000000000 ),    /* negative,    61           */
+    UINT64_C( 0xC3D0000000000000 ),    /* negative,    62           */
+    UINT64_C( 0xC3E0000000000000 ),    /* negative,    63           */
+    UINT64_C( 0xC3F0000000000000 ),    /* negative,    64           */
+    UINT64_C( 0xC7E0000000000000 ),    /* negative,   127           */
+    UINT64_C( 0xC7F0000000000000 ),    /* negative,   128           */
+    UINT64_C( 0xC800000000000000 ),    /* negative,   129           */
+    UINT64_C( 0xFFD0000000000000 ),    /* negative,  1022           */
+    UINT64_C( 0xFFE0000000000000 ),    /* negative,  1023           */
+    UINT64_C( 0xFFF0000000000000 )     /* negative, infinity or NaN */
+};
+static const uint64_t f64P1[f64NumP1] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFE )
+};
+static const uint64_t f64P2[f64NumP2] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x0000000000000002 ),
+    UINT64_C( 0x0000000000000004 ),
+    UINT64_C( 0x0000000000000008 ),
+    UINT64_C( 0x0000000000000010 ),
+    UINT64_C( 0x0000000000000020 ),
+    UINT64_C( 0x0000000000000040 ),
+    UINT64_C( 0x0000000000000080 ),
+    UINT64_C( 0x0000000000000100 ),
+    UINT64_C( 0x0000000000000200 ),
+    UINT64_C( 0x0000000000000400 ),
+    UINT64_C( 0x0000000000000800 ),
+    UINT64_C( 0x0000000000001000 ),
+    UINT64_C( 0x0000000000002000 ),
+    UINT64_C( 0x0000000000004000 ),
+    UINT64_C( 0x0000000000008000 ),
+    UINT64_C( 0x0000000000010000 ),
+    UINT64_C( 0x0000000000020000 ),
+    UINT64_C( 0x0000000000040000 ),
+    UINT64_C( 0x0000000000080000 ),
+    UINT64_C( 0x0000000000100000 ),
+    UINT64_C( 0x0000000000200000 ),
+    UINT64_C( 0x0000000000400000 ),
+    UINT64_C( 0x0000000000800000 ),
+    UINT64_C( 0x0000000001000000 ),
+    UINT64_C( 0x0000000002000000 ),
+    UINT64_C( 0x0000000004000000 ),
+    UINT64_C( 0x0000000008000000 ),
+    UINT64_C( 0x0000000010000000 ),
+    UINT64_C( 0x0000000020000000 ),
+    UINT64_C( 0x0000000040000000 ),
+    UINT64_C( 0x0000000080000000 ),
+    UINT64_C( 0x0000000100000000 ),
+    UINT64_C( 0x0000000200000000 ),
+    UINT64_C( 0x0000000400000000 ),
+    UINT64_C( 0x0000000800000000 ),
+    UINT64_C( 0x0000001000000000 ),
+    UINT64_C( 0x0000002000000000 ),
+    UINT64_C( 0x0000004000000000 ),
+    UINT64_C( 0x0000008000000000 ),
+    UINT64_C( 0x0000010000000000 ),
+    UINT64_C( 0x0000020000000000 ),
+    UINT64_C( 0x0000040000000000 ),
+    UINT64_C( 0x0000080000000000 ),
+    UINT64_C( 0x0000100000000000 ),
+    UINT64_C( 0x0000200000000000 ),
+    UINT64_C( 0x0000400000000000 ),
+    UINT64_C( 0x0000800000000000 ),
+    UINT64_C( 0x0001000000000000 ),
+    UINT64_C( 0x0002000000000000 ),
+    UINT64_C( 0x0004000000000000 ),
+    UINT64_C( 0x0008000000000000 ),
+    UINT64_C( 0x000C000000000000 ),
+    UINT64_C( 0x000E000000000000 ),
+    UINT64_C( 0x000F000000000000 ),
+    UINT64_C( 0x000F800000000000 ),
+    UINT64_C( 0x000FC00000000000 ),
+    UINT64_C( 0x000FE00000000000 ),
+    UINT64_C( 0x000FF00000000000 ),
+    UINT64_C( 0x000FF80000000000 ),
+    UINT64_C( 0x000FFC0000000000 ),
+    UINT64_C( 0x000FFE0000000000 ),
+    UINT64_C( 0x000FFF0000000000 ),
+    UINT64_C( 0x000FFF8000000000 ),
+    UINT64_C( 0x000FFFC000000000 ),
+    UINT64_C( 0x000FFFE000000000 ),
+    UINT64_C( 0x000FFFF000000000 ),
+    UINT64_C( 0x000FFFF800000000 ),
+    UINT64_C( 0x000FFFFC00000000 ),
+    UINT64_C( 0x000FFFFE00000000 ),
+    UINT64_C( 0x000FFFFF00000000 ),
+    UINT64_C( 0x000FFFFF80000000 ),
+    UINT64_C( 0x000FFFFFC0000000 ),
+    UINT64_C( 0x000FFFFFE0000000 ),
+    UINT64_C( 0x000FFFFFF0000000 ),
+    UINT64_C( 0x000FFFFFF8000000 ),
+    UINT64_C( 0x000FFFFFFC000000 ),
+    UINT64_C( 0x000FFFFFFE000000 ),
+    UINT64_C( 0x000FFFFFFF000000 ),
+    UINT64_C( 0x000FFFFFFF800000 ),
+    UINT64_C( 0x000FFFFFFFC00000 ),
+    UINT64_C( 0x000FFFFFFFE00000 ),
+    UINT64_C( 0x000FFFFFFFF00000 ),
+    UINT64_C( 0x000FFFFFFFF80000 ),
+    UINT64_C( 0x000FFFFFFFFC0000 ),
+    UINT64_C( 0x000FFFFFFFFE0000 ),
+    UINT64_C( 0x000FFFFFFFFF0000 ),
+    UINT64_C( 0x000FFFFFFFFF8000 ),
+    UINT64_C( 0x000FFFFFFFFFC000 ),
+    UINT64_C( 0x000FFFFFFFFFE000 ),
+    UINT64_C( 0x000FFFFFFFFFF000 ),
+    UINT64_C( 0x000FFFFFFFFFF800 ),
+    UINT64_C( 0x000FFFFFFFFFFC00 ),
+    UINT64_C( 0x000FFFFFFFFFFE00 ),
+    UINT64_C( 0x000FFFFFFFFFFF00 ),
+    UINT64_C( 0x000FFFFFFFFFFF80 ),
+    UINT64_C( 0x000FFFFFFFFFFFC0 ),
+    UINT64_C( 0x000FFFFFFFFFFFE0 ),
+    UINT64_C( 0x000FFFFFFFFFFFF0 ),
+    UINT64_C( 0x000FFFFFFFFFFFF8 ),
+    UINT64_C( 0x000FFFFFFFFFFFFC ),
+    UINT64_C( 0x000FFFFFFFFFFFFE ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFD ),
+    UINT64_C( 0x000FFFFFFFFFFFFB ),
+    UINT64_C( 0x000FFFFFFFFFFFF7 ),
+    UINT64_C( 0x000FFFFFFFFFFFEF ),
+    UINT64_C( 0x000FFFFFFFFFFFDF ),
+    UINT64_C( 0x000FFFFFFFFFFFBF ),
+    UINT64_C( 0x000FFFFFFFFFFF7F ),
+    UINT64_C( 0x000FFFFFFFFFFEFF ),
+    UINT64_C( 0x000FFFFFFFFFFDFF ),
+    UINT64_C( 0x000FFFFFFFFFFBFF ),
+    UINT64_C( 0x000FFFFFFFFFF7FF ),
+    UINT64_C( 0x000FFFFFFFFFEFFF ),
+    UINT64_C( 0x000FFFFFFFFFDFFF ),
+    UINT64_C( 0x000FFFFFFFFFBFFF ),
+    UINT64_C( 0x000FFFFFFFFF7FFF ),
+    UINT64_C( 0x000FFFFFFFFEFFFF ),
+    UINT64_C( 0x000FFFFFFFFDFFFF ),
+    UINT64_C( 0x000FFFFFFFFBFFFF ),
+    UINT64_C( 0x000FFFFFFFF7FFFF ),
+    UINT64_C( 0x000FFFFFFFEFFFFF ),
+    UINT64_C( 0x000FFFFFFFDFFFFF ),
+    UINT64_C( 0x000FFFFFFFBFFFFF ),
+    UINT64_C( 0x000FFFFFFF7FFFFF ),
+    UINT64_C( 0x000FFFFFFEFFFFFF ),
+    UINT64_C( 0x000FFFFFFDFFFFFF ),
+    UINT64_C( 0x000FFFFFFBFFFFFF ),
+    UINT64_C( 0x000FFFFFF7FFFFFF ),
+    UINT64_C( 0x000FFFFFEFFFFFFF ),
+    UINT64_C( 0x000FFFFFDFFFFFFF ),
+    UINT64_C( 0x000FFFFFBFFFFFFF ),
+    UINT64_C( 0x000FFFFF7FFFFFFF ),
+    UINT64_C( 0x000FFFFEFFFFFFFF ),
+    UINT64_C( 0x000FFFFDFFFFFFFF ),
+    UINT64_C( 0x000FFFFBFFFFFFFF ),
+    UINT64_C( 0x000FFFF7FFFFFFFF ),
+    UINT64_C( 0x000FFFEFFFFFFFFF ),
+    UINT64_C( 0x000FFFDFFFFFFFFF ),
+    UINT64_C( 0x000FFFBFFFFFFFFF ),
+    UINT64_C( 0x000FFF7FFFFFFFFF ),
+    UINT64_C( 0x000FFEFFFFFFFFFF ),
+    UINT64_C( 0x000FFDFFFFFFFFFF ),
+    UINT64_C( 0x000FFBFFFFFFFFFF ),
+    UINT64_C( 0x000FF7FFFFFFFFFF ),
+    UINT64_C( 0x000FEFFFFFFFFFFF ),
+    UINT64_C( 0x000FDFFFFFFFFFFF ),
+    UINT64_C( 0x000FBFFFFFFFFFFF ),
+    UINT64_C( 0x000F7FFFFFFFFFFF ),
+    UINT64_C( 0x000EFFFFFFFFFFFF ),
+    UINT64_C( 0x000DFFFFFFFFFFFF ),
+    UINT64_C( 0x000BFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F ),
+    UINT64_C( 0x0000000000000007 ),
+    UINT64_C( 0x0000000000000003 )
+};
+
+static const uint_fast64_t f64NumQInP1 = f64NumQIn * f64NumP1;
+static const uint_fast64_t f64NumQOutP1 = f64NumQOut * f64NumP1;
+
+static float64_t f64NextQInP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui64_f64 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f64QIn[expNum] | f64P1[sigNum];
+    ++sigNum;
+    if ( f64NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f64NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float64_t f64NextQOutP1( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui64_f64 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f64QOut[expNum] | f64P1[sigNum];
+    ++sigNum;
+    if ( f64NumP1 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f64NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static const uint_fast64_t f64NumQInP2 = f64NumQIn * f64NumP2;
+static const uint_fast64_t f64NumQOutP2 = f64NumQOut * f64NumP2;
+
+static float64_t f64NextQInP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui64_f64 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f64QIn[expNum] | f64P2[sigNum];
+    ++sigNum;
+    if ( f64NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f64NumQIn <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float64_t f64NextQOutP2( struct sequence *sequencePtr )
+{
+    int expNum, sigNum;
+    union ui64_f64 uZ;
+
+    expNum = sequencePtr->expNum;
+    sigNum = sequencePtr->term1Num;
+    uZ.ui = f64QOut[expNum] | f64P2[sigNum];
+    ++sigNum;
+    if ( f64NumP2 <= sigNum ) {
+        sigNum = 0;
+        ++expNum;
+        if ( f64NumQOut <= expNum ) {
+            expNum = 0;
+            sequencePtr->done = true;
+        }
+        sequencePtr->expNum = expNum;
+    }
+    sequencePtr->term1Num = sigNum;
+    return uZ.f;
+
+}
+
+static float64_t f64RandomQOutP3( void )
+{
+    union ui64_f64 uZ;
+
+    uZ.ui =
+          f64QOut[randomN_ui8( f64NumQOut )]
+        | ((f64P2[randomN_ui8( f64NumP2 )] + f64P2[randomN_ui8( f64NumP2 )])
+               & UINT64_C( 0x000FFFFFFFFFFFFF ));
+    return uZ.f;
+
+}
+
+static float64_t f64RandomQOutPInf( void )
+{
+    union ui64_f64 uZ;
+
+    uZ.ui =
+        f64QOut[randomN_ui8( f64NumQOut )]
+            | (random_ui64() & UINT64_C( 0x000FFFFFFFFFFFFF ));
+    return uZ.f;
+
+}
+
+enum { f64NumQInfWeightMasks = 10 };
+static const uint64_t f64QInfWeightMasks[f64NumQInfWeightMasks] = {
+    UINT64_C( 0xFFF0000000000000 ),
+    UINT64_C( 0xFFF0000000000000 ),
+    UINT64_C( 0xBFF0000000000000 ),
+    UINT64_C( 0x9FF0000000000000 ),
+    UINT64_C( 0x8FF0000000000000 ),
+    UINT64_C( 0x87F0000000000000 ),
+    UINT64_C( 0x83F0000000000000 ),
+    UINT64_C( 0x81F0000000000000 ),
+    UINT64_C( 0x80F0000000000000 ),
+    UINT64_C( 0x8070000000000000 )
+};
+static const uint64_t f64QInfWeightOffsets[f64NumQInfWeightMasks] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x2000000000000000 ),
+    UINT64_C( 0x3000000000000000 ),
+    UINT64_C( 0x3800000000000000 ),
+    UINT64_C( 0x3C00000000000000 ),
+    UINT64_C( 0x3E00000000000000 ),
+    UINT64_C( 0x3F00000000000000 ),
+    UINT64_C( 0x3F80000000000000 ),
+    UINT64_C( 0x3FC0000000000000 )
+};
+
+static float64_t f64RandomQInfP3( void )
+{
+    int weightMaskNum;
+    union ui64_f64 uZ;
+
+    weightMaskNum = randomN_ui8( f64NumQInfWeightMasks );
+    uZ.ui =
+          (((uint_fast64_t) random_ui16()<<48
+                & f64QInfWeightMasks[weightMaskNum])
+               + f64QInfWeightOffsets[weightMaskNum])
+        | ((f64P2[randomN_ui8( f64NumP2 )] + f64P2[randomN_ui8( f64NumP2 )])
+               & UINT64_C( 0x000FFFFFFFFFFFFF ));
+    return uZ.f;
+
+}
+
+static float64_t f64RandomQInfPInf( void )
+{
+    int weightMaskNum;
+    union ui64_f64 uZ;
+
+    weightMaskNum = randomN_ui8( f64NumQInfWeightMasks );
+    uZ.ui =
+        (random_ui64()
+             & (f64QInfWeightMasks[weightMaskNum]
+                    | UINT64_C( 0x000FFFFFFFFFFFFF )))
+            + f64QInfWeightOffsets[weightMaskNum];
+    return uZ.f;
+
+}
+
+static float64_t f64Random( void )
+{
+
+    switch ( random_ui8() & 7 ) {
+     case 0:
+     case 1:
+     case 2:
+        return f64RandomQOutP3();
+     case 3:
+        return f64RandomQOutPInf();
+     case 4:
+     case 5:
+     case 6:
+        return f64RandomQInfP3();
+     case 7:
+        return f64RandomQInfPInf();
+    }
+
+}
+
+static struct sequence sequenceA, sequenceB, sequenceC;
+static float64_t currentA, currentB, currentC;
+static int subcase;
+
+float64_t genCases_f64_a, genCases_f64_b, genCases_f64_c;
+
+void genCases_f64_a_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total =
+        (genCases_level == 1) ? 3 * f64NumQOutP1 : 2 * f64NumQOutP2;
+    genCases_done = false;
+
+}
+
+void genCases_f64_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+         case 1:
+            genCases_f64_a = f64Random();
+            break;
+         case 2:
+            genCases_f64_a = f64NextQOutP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+     } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f64_a = f64Random();
+            break;
+         case 1:
+            genCases_f64_a = f64NextQOutP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f64_ab_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 6 * f64NumQInP1 * f64NumQInP1;
+        currentA = f64NextQInP1( &sequenceA );
+    } else {
+        genCases_total = 2 * f64NumQInP2 * f64NumQInP2;
+        currentA = f64NextQInP2( &sequenceA );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f64_ab_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f64NextQInP1( &sequenceA );
+            }
+            currentB = f64NextQInP1( &sequenceB );
+         case 2:
+         case 4:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            break;
+         case 1:
+            genCases_f64_a = currentA;
+            genCases_f64_b = f64Random();
+            break;
+         case 3:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = currentB;
+            break;
+         case 5:
+            genCases_f64_a = currentA;
+            genCases_f64_b = currentB;
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            break;
+         case 1:
+            if ( sequenceB.done ) {
+                sequenceB.done = false;
+                currentA = f64NextQInP2( &sequenceA );
+            }
+            genCases_f64_a = currentA;
+            genCases_f64_b = f64NextQInP2( &sequenceB );
+            genCases_done = sequenceA.done & sequenceB.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+void genCases_f64_abc_init( void )
+{
+
+    sequenceA.expNum = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    sequenceB.expNum = 0;
+    sequenceB.term1Num = 0;
+    sequenceB.term2Num = 0;
+    sequenceB.done = false;
+    sequenceC.expNum = 0;
+    sequenceC.term1Num = 0;
+    sequenceC.term2Num = 0;
+    sequenceC.done = false;
+    subcase = 0;
+    if ( genCases_level == 1 ) {
+        genCases_total = 9 * f64NumQInP1 * f64NumQInP1 * f64NumQInP1;
+        currentA = f64NextQInP1( &sequenceA );
+        currentB = f64NextQInP1( &sequenceB );
+    } else {
+        genCases_total = 2 * f64NumQInP2 * f64NumQInP2 * f64NumQInP2;
+        currentA = f64NextQInP2( &sequenceA );
+        currentB = f64NextQInP2( &sequenceB );
+    }
+    genCases_done = false;
+
+}
+
+void genCases_f64_abc_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f64NextQInP1( &sequenceA );
+                }
+                currentB = f64NextQInP1( &sequenceB );
+            }
+            currentC = f64NextQInP1( &sequenceC );
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            genCases_f64_c = currentC;
+            break;
+         case 1:
+            genCases_f64_a = currentA;
+            genCases_f64_b = currentB;
+            genCases_f64_c = f64Random();
+            break;
+         case 2:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            genCases_f64_c = f64Random();
+            break;
+         case 3:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = currentB;
+            genCases_f64_c = currentC;
+            break;
+         case 4:
+            genCases_f64_a = currentA;
+            genCases_f64_b = f64Random();
+            genCases_f64_c = f64Random();
+            break;
+         case 5:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = currentB;
+            genCases_f64_c = f64Random();
+            break;
+         case 6:
+            genCases_f64_a = currentA;
+            genCases_f64_b = f64Random();
+            genCases_f64_c = currentC;
+            break;
+         case 7:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            genCases_f64_c = f64Random();
+            break;
+         case 8:
+            genCases_f64_a = currentA;
+            genCases_f64_b = currentB;
+            genCases_f64_c = currentC;
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_f64_a = f64Random();
+            genCases_f64_b = f64Random();
+            genCases_f64_c = f64Random();
+            break;
+         case 1:
+            if ( sequenceC.done ) {
+                sequenceC.done = false;
+                if ( sequenceB.done ) {
+                    sequenceB.done = false;
+                    currentA = f64NextQInP2( &sequenceA );
+                }
+                currentB = f64NextQInP2( &sequenceB );
+            }
+            genCases_f64_a = currentA;
+            genCases_f64_b = currentB;
+            genCases_f64_c = f64NextQInP2( &sequenceC );
+            genCases_done = sequenceA.done & sequenceB.done & sequenceC.done;
+            subcase = -1;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/genCases_i32.c b/addins/TestFloat-3e/source/genCases_i32.c
new file mode 100644
index 000000000..6a2fcad68
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_i32.c
@@ -0,0 +1,362 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "genCases.h"
+
+struct sequence {
+    int term1Num, term2Num;
+    bool done;
+};
+
+union ui32_i32 { uint32_t ui; int32_t i; };
+
+enum { i32NumP1 = 124 };
+static const uint32_t i32P1[i32NumP1] = {
+    0x00000000,
+    0x00000001,
+    0x00000002,
+    0x00000004,
+    0x00000008,
+    0x00000010,
+    0x00000020,
+    0x00000040,
+    0x00000080,
+    0x00000100,
+    0x00000200,
+    0x00000400,
+    0x00000800,
+    0x00001000,
+    0x00002000,
+    0x00004000,
+    0x00008000,
+    0x00010000,
+    0x00020000,
+    0x00040000,
+    0x00080000,
+    0x00100000,
+    0x00200000,
+    0x00400000,
+    0x00800000,
+    0x01000000,
+    0x02000000,
+    0x04000000,
+    0x08000000,
+    0x10000000,
+    0x20000000,
+    0x40000000,
+    0x80000000,
+    0xC0000000,
+    0xE0000000,
+    0xF0000000,
+    0xF8000000,
+    0xFC000000,
+    0xFE000000,
+    0xFF000000,
+    0xFF800000,
+    0xFFC00000,
+    0xFFE00000,
+    0xFFF00000,
+    0xFFF80000,
+    0xFFFC0000,
+    0xFFFE0000,
+    0xFFFF0000,
+    0xFFFF8000,
+    0xFFFFC000,
+    0xFFFFE000,
+    0xFFFFF000,
+    0xFFFFF800,
+    0xFFFFFC00,
+    0xFFFFFE00,
+    0xFFFFFF00,
+    0xFFFFFF80,
+    0xFFFFFFC0,
+    0xFFFFFFE0,
+    0xFFFFFFF0,
+    0xFFFFFFF8,
+    0xFFFFFFFC,
+    0xFFFFFFFE,
+    0xFFFFFFFF,
+    0xFFFFFFFD,
+    0xFFFFFFFB,
+    0xFFFFFFF7,
+    0xFFFFFFEF,
+    0xFFFFFFDF,
+    0xFFFFFFBF,
+    0xFFFFFF7F,
+    0xFFFFFEFF,
+    0xFFFFFDFF,
+    0xFFFFFBFF,
+    0xFFFFF7FF,
+    0xFFFFEFFF,
+    0xFFFFDFFF,
+    0xFFFFBFFF,
+    0xFFFF7FFF,
+    0xFFFEFFFF,
+    0xFFFDFFFF,
+    0xFFFBFFFF,
+    0xFFF7FFFF,
+    0xFFEFFFFF,
+    0xFFDFFFFF,
+    0xFFBFFFFF,
+    0xFF7FFFFF,
+    0xFEFFFFFF,
+    0xFDFFFFFF,
+    0xFBFFFFFF,
+    0xF7FFFFFF,
+    0xEFFFFFFF,
+    0xDFFFFFFF,
+    0xBFFFFFFF,
+    0x7FFFFFFF,
+    0x3FFFFFFF,
+    0x1FFFFFFF,
+    0x0FFFFFFF,
+    0x07FFFFFF,
+    0x03FFFFFF,
+    0x01FFFFFF,
+    0x00FFFFFF,
+    0x007FFFFF,
+    0x003FFFFF,
+    0x001FFFFF,
+    0x000FFFFF,
+    0x0007FFFF,
+    0x0003FFFF,
+    0x0001FFFF,
+    0x0000FFFF,
+    0x00007FFF,
+    0x00003FFF,
+    0x00001FFF,
+    0x00000FFF,
+    0x000007FF,
+    0x000003FF,
+    0x000001FF,
+    0x000000FF,
+    0x0000007F,
+    0x0000003F,
+    0x0000001F,
+    0x0000000F,
+    0x00000007,
+    0x00000003
+};
+
+static int32_t i32NextP1( struct sequence *sequencePtr )
+{
+    int termNum;
+    union ui32_i32 uZ;
+
+    termNum = sequencePtr->term1Num;
+    uZ.ui = i32P1[termNum];
+    ++termNum;
+    if ( i32NumP1 <= termNum ) {
+        termNum = 0;
+        sequencePtr->done = true;
+    }
+    sequencePtr->term1Num = termNum;
+    return uZ.i;
+
+}
+
+static const int_fast32_t i32NumP2 = (i32NumP1 * i32NumP1 + i32NumP1) / 2;
+
+static int32_t i32NextP2( struct sequence *sequencePtr )
+{
+    int term1Num, term2Num;
+    union ui32_i32 uZ;
+
+    term2Num = sequencePtr->term2Num;
+    term1Num = sequencePtr->term1Num;
+    uZ.ui = i32P1[term1Num] + i32P1[term2Num];
+    ++term2Num;
+    if ( i32NumP1 <= term2Num ) {
+        ++term1Num;
+        if ( i32NumP1 <= term1Num ) {
+            term1Num = 0;
+            sequencePtr->done = true;
+        }
+        term2Num = term1Num;
+        sequencePtr->term1Num = term1Num;
+    }
+    sequencePtr->term2Num = term2Num;
+    return uZ.i;
+
+}
+
+static int32_t i32RandomP3( void )
+{
+    union ui32_i32 uZ;
+
+    uZ.ui =
+        i32P1[randomN_ui8( i32NumP1 )] + i32P1[randomN_ui8( i32NumP1 )]
+            + i32P1[randomN_ui8( i32NumP1 )];
+    return uZ.i;
+
+}
+
+enum { i32NumPInfWeightMasks = 29 };
+static const uint32_t i32PInfWeightMasks[i32NumPInfWeightMasks] = {
+    0xFFFFFFFF,
+    0x7FFFFFFF,
+    0x3FFFFFFF,
+    0x1FFFFFFF,
+    0x0FFFFFFF,
+    0x07FFFFFF,
+    0x03FFFFFF,
+    0x01FFFFFF,
+    0x00FFFFFF,
+    0x007FFFFF,
+    0x003FFFFF,
+    0x001FFFFF,
+    0x000FFFFF,
+    0x0007FFFF,
+    0x0003FFFF,
+    0x0001FFFF,
+    0x0000FFFF,
+    0x00007FFF,
+    0x00003FFF,
+    0x00001FFF,
+    0x00000FFF,
+    0x000007FF,
+    0x000003FF,
+    0x000001FF,
+    0x000000FF,
+    0x0000007F,
+    0x0000003F,
+    0x0000001F,
+    0x0000000F
+};
+static const uint32_t i32PInfWeightOffsets[i32NumPInfWeightMasks] = {
+    0x00000000,
+    0xC0000000,
+    0xE0000000,
+    0xF0000000,
+    0xF8000000,
+    0xFC000000,
+    0xFE000000,
+    0xFF000000,
+    0xFF800000,
+    0xFFC00000,
+    0xFFE00000,
+    0xFFF00000,
+    0xFFF80000,
+    0xFFFC0000,
+    0xFFFE0000,
+    0xFFFF0000,
+    0xFFFF8000,
+    0xFFFFC000,
+    0xFFFFE000,
+    0xFFFFF000,
+    0xFFFFF800,
+    0xFFFFFC00,
+    0xFFFFFE00,
+    0xFFFFFF00,
+    0xFFFFFF80,
+    0xFFFFFFC0,
+    0xFFFFFFE0,
+    0xFFFFFFF0,
+    0xFFFFFFF8
+};
+
+static int32_t i32RandomPInf( void )
+{
+    int weightMaskNum;
+    union ui32_i32 uZ;
+
+    weightMaskNum = randomN_ui8( i32NumPInfWeightMasks );
+    uZ.ui =
+        (random_ui32() & i32PInfWeightMasks[weightMaskNum])
+            + i32PInfWeightOffsets[weightMaskNum];
+    return uZ.i;
+
+}
+
+static struct sequence sequenceA;
+static int subcase;
+
+int32_t genCases_i32_a;
+
+void genCases_i32_a_init( void )
+{
+
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total = (genCases_level == 1) ? 3 * i32NumP1 : 2 * i32NumP2;
+    genCases_done = false;
+
+}
+
+void genCases_i32_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            genCases_i32_a = i32RandomP3();
+            break;
+         case 1:
+            genCases_i32_a = i32RandomPInf();
+            break;
+         case 2:
+            genCases_i32_a = i32NextP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_i32_a = i32RandomP3();
+            break;
+         case 2:
+            genCases_i32_a = i32RandomPInf();
+            break;
+         case 3:
+            subcase = -1;
+         case 1:
+            genCases_i32_a = i32NextP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
diff --git a/addins/TestFloat-3e/source/genCases_i64.c b/addins/TestFloat-3e/source/genCases_i64.c
new file mode 100644
index 000000000..82ff7236e
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_i64.c
@@ -0,0 +1,554 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "genCases.h"
+
+struct sequence {
+    int term1Num, term2Num;
+    bool done;
+};
+
+union ui64_i64 { uint64_t ui; int64_t i; };
+
+enum { i64NumP1 = 252 };
+static const uint64_t i64P1[i64NumP1] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x0000000000000002 ),
+    UINT64_C( 0x0000000000000004 ),
+    UINT64_C( 0x0000000000000008 ),
+    UINT64_C( 0x0000000000000010 ),
+    UINT64_C( 0x0000000000000020 ),
+    UINT64_C( 0x0000000000000040 ),
+    UINT64_C( 0x0000000000000080 ),
+    UINT64_C( 0x0000000000000100 ),
+    UINT64_C( 0x0000000000000200 ),
+    UINT64_C( 0x0000000000000400 ),
+    UINT64_C( 0x0000000000000800 ),
+    UINT64_C( 0x0000000000001000 ),
+    UINT64_C( 0x0000000000002000 ),
+    UINT64_C( 0x0000000000004000 ),
+    UINT64_C( 0x0000000000008000 ),
+    UINT64_C( 0x0000000000010000 ),
+    UINT64_C( 0x0000000000020000 ),
+    UINT64_C( 0x0000000000040000 ),
+    UINT64_C( 0x0000000000080000 ),
+    UINT64_C( 0x0000000000100000 ),
+    UINT64_C( 0x0000000000200000 ),
+    UINT64_C( 0x0000000000400000 ),
+    UINT64_C( 0x0000000000800000 ),
+    UINT64_C( 0x0000000001000000 ),
+    UINT64_C( 0x0000000002000000 ),
+    UINT64_C( 0x0000000004000000 ),
+    UINT64_C( 0x0000000008000000 ),
+    UINT64_C( 0x0000000010000000 ),
+    UINT64_C( 0x0000000020000000 ),
+    UINT64_C( 0x0000000040000000 ),
+    UINT64_C( 0x0000000080000000 ),
+    UINT64_C( 0x0000000100000000 ),
+    UINT64_C( 0x0000000200000000 ),
+    UINT64_C( 0x0000000400000000 ),
+    UINT64_C( 0x0000000800000000 ),
+    UINT64_C( 0x0000001000000000 ),
+    UINT64_C( 0x0000002000000000 ),
+    UINT64_C( 0x0000004000000000 ),
+    UINT64_C( 0x0000008000000000 ),
+    UINT64_C( 0x0000010000000000 ),
+    UINT64_C( 0x0000020000000000 ),
+    UINT64_C( 0x0000040000000000 ),
+    UINT64_C( 0x0000080000000000 ),
+    UINT64_C( 0x0000100000000000 ),
+    UINT64_C( 0x0000200000000000 ),
+    UINT64_C( 0x0000400000000000 ),
+    UINT64_C( 0x0000800000000000 ),
+    UINT64_C( 0x0001000000000000 ),
+    UINT64_C( 0x0002000000000000 ),
+    UINT64_C( 0x0004000000000000 ),
+    UINT64_C( 0x0008000000000000 ),
+    UINT64_C( 0x0010000000000000 ),
+    UINT64_C( 0x0020000000000000 ),
+    UINT64_C( 0x0040000000000000 ),
+    UINT64_C( 0x0080000000000000 ),
+    UINT64_C( 0x0100000000000000 ),
+    UINT64_C( 0x0200000000000000 ),
+    UINT64_C( 0x0400000000000000 ),
+    UINT64_C( 0x0800000000000000 ),
+    UINT64_C( 0x1000000000000000 ),
+    UINT64_C( 0x2000000000000000 ),
+    UINT64_C( 0x4000000000000000 ),
+    UINT64_C( 0x8000000000000000 ),
+    UINT64_C( 0xC000000000000000 ),
+    UINT64_C( 0xE000000000000000 ),
+    UINT64_C( 0xF000000000000000 ),
+    UINT64_C( 0xF800000000000000 ),
+    UINT64_C( 0xFC00000000000000 ),
+    UINT64_C( 0xFE00000000000000 ),
+    UINT64_C( 0xFF00000000000000 ),
+    UINT64_C( 0xFF80000000000000 ),
+    UINT64_C( 0xFFC0000000000000 ),
+    UINT64_C( 0xFFE0000000000000 ),
+    UINT64_C( 0xFFF0000000000000 ),
+    UINT64_C( 0xFFF8000000000000 ),
+    UINT64_C( 0xFFFC000000000000 ),
+    UINT64_C( 0xFFFE000000000000 ),
+    UINT64_C( 0xFFFF000000000000 ),
+    UINT64_C( 0xFFFF800000000000 ),
+    UINT64_C( 0xFFFFC00000000000 ),
+    UINT64_C( 0xFFFFE00000000000 ),
+    UINT64_C( 0xFFFFF00000000000 ),
+    UINT64_C( 0xFFFFF80000000000 ),
+    UINT64_C( 0xFFFFFC0000000000 ),
+    UINT64_C( 0xFFFFFE0000000000 ),
+    UINT64_C( 0xFFFFFF0000000000 ),
+    UINT64_C( 0xFFFFFF8000000000 ),
+    UINT64_C( 0xFFFFFFC000000000 ),
+    UINT64_C( 0xFFFFFFE000000000 ),
+    UINT64_C( 0xFFFFFFF000000000 ),
+    UINT64_C( 0xFFFFFFF800000000 ),
+    UINT64_C( 0xFFFFFFFC00000000 ),
+    UINT64_C( 0xFFFFFFFE00000000 ),
+    UINT64_C( 0xFFFFFFFF00000000 ),
+    UINT64_C( 0xFFFFFFFF80000000 ),
+    UINT64_C( 0xFFFFFFFFC0000000 ),
+    UINT64_C( 0xFFFFFFFFE0000000 ),
+    UINT64_C( 0xFFFFFFFFF0000000 ),
+    UINT64_C( 0xFFFFFFFFF8000000 ),
+    UINT64_C( 0xFFFFFFFFFC000000 ),
+    UINT64_C( 0xFFFFFFFFFE000000 ),
+    UINT64_C( 0xFFFFFFFFFF000000 ),
+    UINT64_C( 0xFFFFFFFFFF800000 ),
+    UINT64_C( 0xFFFFFFFFFFC00000 ),
+    UINT64_C( 0xFFFFFFFFFFE00000 ),
+    UINT64_C( 0xFFFFFFFFFFF00000 ),
+    UINT64_C( 0xFFFFFFFFFFF80000 ),
+    UINT64_C( 0xFFFFFFFFFFFC0000 ),
+    UINT64_C( 0xFFFFFFFFFFFE0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF8000 ),
+    UINT64_C( 0xFFFFFFFFFFFFC000 ),
+    UINT64_C( 0xFFFFFFFFFFFFE000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF800 ),
+    UINT64_C( 0xFFFFFFFFFFFFFC00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFE00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF80 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFC0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFE0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF8 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFC ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFE ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFD ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFB ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF7 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFEF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFDF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFBF ),
+    UINT64_C( 0xFFFFFFFFFFFFFF7F ),
+    UINT64_C( 0xFFFFFFFFFFFFFEFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFDFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFBFF ),
+    UINT64_C( 0xFFFFFFFFFFFFF7FF ),
+    UINT64_C( 0xFFFFFFFFFFFFEFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFDFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFBFFF ),
+    UINT64_C( 0xFFFFFFFFFFFF7FFF ),
+    UINT64_C( 0xFFFFFFFFFFFEFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFDFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFBFFFF ),
+    UINT64_C( 0xFFFFFFFFFFF7FFFF ),
+    UINT64_C( 0xFFFFFFFFFFEFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFDFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFBFFFFF ),
+    UINT64_C( 0xFFFFFFFFFF7FFFFF ),
+    UINT64_C( 0xFFFFFFFFFEFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFDFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFBFFFFFF ),
+    UINT64_C( 0xFFFFFFFFF7FFFFFF ),
+    UINT64_C( 0xFFFFFFFFEFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFDFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFBFFFFFFF ),
+    UINT64_C( 0xFFFFFFFF7FFFFFFF ),
+    UINT64_C( 0xFFFFFFFEFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFDFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFBFFFFFFFF ),
+    UINT64_C( 0xFFFFFFF7FFFFFFFF ),
+    UINT64_C( 0xFFFFFFEFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFDFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFBFFFFFFFFF ),
+    UINT64_C( 0xFFFFFF7FFFFFFFFF ),
+    UINT64_C( 0xFFFFFEFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFDFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFBFFFFFFFFFF ),
+    UINT64_C( 0xFFFFF7FFFFFFFFFF ),
+    UINT64_C( 0xFFFFEFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFDFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFBFFFFFFFFFFF ),
+    UINT64_C( 0xFFFF7FFFFFFFFFFF ),
+    UINT64_C( 0xFFFEFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFDFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFBFFFFFFFFFFFF ),
+    UINT64_C( 0xFFF7FFFFFFFFFFFF ),
+    UINT64_C( 0xFFEFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFDFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFBFFFFFFFFFFFFF ),
+    UINT64_C( 0xFF7FFFFFFFFFFFFF ),
+    UINT64_C( 0xFEFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFDFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFBFFFFFFFFFFFFFF ),
+    UINT64_C( 0xF7FFFFFFFFFFFFFF ),
+    UINT64_C( 0xEFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xDFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xBFFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x3FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x1FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x0FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x07FFFFFFFFFFFFFF ),
+    UINT64_C( 0x03FFFFFFFFFFFFFF ),
+    UINT64_C( 0x01FFFFFFFFFFFFFF ),
+    UINT64_C( 0x00FFFFFFFFFFFFFF ),
+    UINT64_C( 0x007FFFFFFFFFFFFF ),
+    UINT64_C( 0x003FFFFFFFFFFFFF ),
+    UINT64_C( 0x001FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F ),
+    UINT64_C( 0x0000000000000007 ),
+    UINT64_C( 0x0000000000000003 )
+};
+
+static int64_t i64NextP1( struct sequence *sequencePtr )
+{
+    int termNum;
+    union ui64_i64 uZ;
+
+    termNum = sequencePtr->term1Num;
+    uZ.ui = i64P1[termNum];
+    ++termNum;
+    if ( i64NumP1 <= termNum ) {
+        termNum = 0;
+        sequencePtr->done = true;
+    }
+    sequencePtr->term1Num = termNum;
+    return uZ.i;
+
+}
+
+static const int_fast64_t i64NumP2 = (i64NumP1 * i64NumP1 + i64NumP1) / 2;
+
+static int64_t i64NextP2( struct sequence *sequencePtr )
+{
+    int term1Num, term2Num;
+    union ui64_i64 uZ;
+
+    term2Num = sequencePtr->term2Num;
+    term1Num = sequencePtr->term1Num;
+    uZ.ui = i64P1[term1Num] + i64P1[term2Num];
+    ++term2Num;
+    if ( i64NumP1 <= term2Num ) {
+        ++term1Num;
+        if ( i64NumP1 <= term1Num ) {
+            term1Num = 0;
+            sequencePtr->done = true;
+        }
+        term2Num = term1Num;
+        sequencePtr->term1Num = term1Num;
+    }
+    sequencePtr->term2Num = term2Num;
+    return uZ.i;
+
+}
+
+static int64_t i64RandomP3( void )
+{
+    union ui64_i64 uZ;
+
+    uZ.ui =
+        i64P1[randomN_ui8( i64NumP1 )] + i64P1[randomN_ui8( i64NumP1 )]
+            + i64P1[randomN_ui8( i64NumP1 )];
+    return uZ.i;
+
+}
+
+enum { i64NumPInfWeightMasks = 61 };
+static const uint64_t i64PInfWeightMasks[i64NumPInfWeightMasks] = {
+    UINT64_C( 0xFFFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x3FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x1FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x0FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x07FFFFFFFFFFFFFF ),
+    UINT64_C( 0x03FFFFFFFFFFFFFF ),
+    UINT64_C( 0x01FFFFFFFFFFFFFF ),
+    UINT64_C( 0x00FFFFFFFFFFFFFF ),
+    UINT64_C( 0x007FFFFFFFFFFFFF ),
+    UINT64_C( 0x003FFFFFFFFFFFFF ),
+    UINT64_C( 0x001FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F )
+};
+static const uint64_t i64PInfWeightOffsets[i64NumPInfWeightMasks] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0xC000000000000000 ),
+    UINT64_C( 0xE000000000000000 ),
+    UINT64_C( 0xF000000000000000 ),
+    UINT64_C( 0xF800000000000000 ),
+    UINT64_C( 0xFC00000000000000 ),
+    UINT64_C( 0xFE00000000000000 ),
+    UINT64_C( 0xFF00000000000000 ),
+    UINT64_C( 0xFF80000000000000 ),
+    UINT64_C( 0xFFC0000000000000 ),
+    UINT64_C( 0xFFE0000000000000 ),
+    UINT64_C( 0xFFF0000000000000 ),
+    UINT64_C( 0xFFF8000000000000 ),
+    UINT64_C( 0xFFFC000000000000 ),
+    UINT64_C( 0xFFFE000000000000 ),
+    UINT64_C( 0xFFFF000000000000 ),
+    UINT64_C( 0xFFFF800000000000 ),
+    UINT64_C( 0xFFFFC00000000000 ),
+    UINT64_C( 0xFFFFE00000000000 ),
+    UINT64_C( 0xFFFFF00000000000 ),
+    UINT64_C( 0xFFFFF80000000000 ),
+    UINT64_C( 0xFFFFFC0000000000 ),
+    UINT64_C( 0xFFFFFE0000000000 ),
+    UINT64_C( 0xFFFFFF0000000000 ),
+    UINT64_C( 0xFFFFFF8000000000 ),
+    UINT64_C( 0xFFFFFFC000000000 ),
+    UINT64_C( 0xFFFFFFE000000000 ),
+    UINT64_C( 0xFFFFFFF000000000 ),
+    UINT64_C( 0xFFFFFFF800000000 ),
+    UINT64_C( 0xFFFFFFFC00000000 ),
+    UINT64_C( 0xFFFFFFFE00000000 ),
+    UINT64_C( 0xFFFFFFFF00000000 ),
+    UINT64_C( 0xFFFFFFFF80000000 ),
+    UINT64_C( 0xFFFFFFFFC0000000 ),
+    UINT64_C( 0xFFFFFFFFE0000000 ),
+    UINT64_C( 0xFFFFFFFFF0000000 ),
+    UINT64_C( 0xFFFFFFFFF8000000 ),
+    UINT64_C( 0xFFFFFFFFFC000000 ),
+    UINT64_C( 0xFFFFFFFFFE000000 ),
+    UINT64_C( 0xFFFFFFFFFF000000 ),
+    UINT64_C( 0xFFFFFFFFFF800000 ),
+    UINT64_C( 0xFFFFFFFFFFC00000 ),
+    UINT64_C( 0xFFFFFFFFFFE00000 ),
+    UINT64_C( 0xFFFFFFFFFFF00000 ),
+    UINT64_C( 0xFFFFFFFFFFF80000 ),
+    UINT64_C( 0xFFFFFFFFFFFC0000 ),
+    UINT64_C( 0xFFFFFFFFFFFE0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF8000 ),
+    UINT64_C( 0xFFFFFFFFFFFFC000 ),
+    UINT64_C( 0xFFFFFFFFFFFFE000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF800 ),
+    UINT64_C( 0xFFFFFFFFFFFFFC00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFE00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF80 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFC0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFE0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF8 )
+};
+
+static int64_t i64RandomPInf( void )
+{
+    int weightMaskNum;
+    union ui64_i64 uZ;
+
+    weightMaskNum = randomN_ui8( i64NumPInfWeightMasks );
+    uZ.ui =
+        (random_ui64() & i64PInfWeightMasks[weightMaskNum])
+            + i64PInfWeightOffsets[weightMaskNum];
+    return uZ.i;
+
+}
+
+static struct sequence sequenceA;
+static int subcase;
+
+int64_t genCases_i64_a;
+
+void genCases_i64_a_init( void )
+{
+
+    sequenceA.term2Num = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total = (genCases_level == 1) ? 3 * i64NumP1 : 2 * i64NumP2;
+    genCases_done = false;
+
+}
+
+void genCases_i64_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            genCases_i64_a = i64RandomP3();
+            break;
+         case 1:
+            genCases_i64_a = i64RandomPInf();
+            break;
+         case 2:
+            genCases_i64_a = i64NextP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_i64_a = i64RandomP3();
+            break;
+         case 2:
+            genCases_i64_a = i64RandomPInf();
+            break;
+         case 3:
+            subcase = -1;
+         case 1:
+            genCases_i64_a = i64NextP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
diff --git a/addins/TestFloat-3e/source/genCases_ui32.c b/addins/TestFloat-3e/source/genCases_ui32.c
new file mode 100644
index 000000000..1298ff6a1
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_ui32.c
@@ -0,0 +1,323 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "genCases.h"
+
+struct sequence {
+    int term1Num, term2Num;
+    bool done;
+};
+
+enum { ui32NumP1 = 124 };
+static const uint32_t ui32P1[ui32NumP1] = {
+    0x00000000,
+    0x00000001,
+    0x00000002,
+    0x00000004,
+    0x00000008,
+    0x00000010,
+    0x00000020,
+    0x00000040,
+    0x00000080,
+    0x00000100,
+    0x00000200,
+    0x00000400,
+    0x00000800,
+    0x00001000,
+    0x00002000,
+    0x00004000,
+    0x00008000,
+    0x00010000,
+    0x00020000,
+    0x00040000,
+    0x00080000,
+    0x00100000,
+    0x00200000,
+    0x00400000,
+    0x00800000,
+    0x01000000,
+    0x02000000,
+    0x04000000,
+    0x08000000,
+    0x10000000,
+    0x20000000,
+    0x40000000,
+    0x80000000,
+    0xC0000000,
+    0xE0000000,
+    0xF0000000,
+    0xF8000000,
+    0xFC000000,
+    0xFE000000,
+    0xFF000000,
+    0xFF800000,
+    0xFFC00000,
+    0xFFE00000,
+    0xFFF00000,
+    0xFFF80000,
+    0xFFFC0000,
+    0xFFFE0000,
+    0xFFFF0000,
+    0xFFFF8000,
+    0xFFFFC000,
+    0xFFFFE000,
+    0xFFFFF000,
+    0xFFFFF800,
+    0xFFFFFC00,
+    0xFFFFFE00,
+    0xFFFFFF00,
+    0xFFFFFF80,
+    0xFFFFFFC0,
+    0xFFFFFFE0,
+    0xFFFFFFF0,
+    0xFFFFFFF8,
+    0xFFFFFFFC,
+    0xFFFFFFFE,
+    0xFFFFFFFF,
+    0xFFFFFFFD,
+    0xFFFFFFFB,
+    0xFFFFFFF7,
+    0xFFFFFFEF,
+    0xFFFFFFDF,
+    0xFFFFFFBF,
+    0xFFFFFF7F,
+    0xFFFFFEFF,
+    0xFFFFFDFF,
+    0xFFFFFBFF,
+    0xFFFFF7FF,
+    0xFFFFEFFF,
+    0xFFFFDFFF,
+    0xFFFFBFFF,
+    0xFFFF7FFF,
+    0xFFFEFFFF,
+    0xFFFDFFFF,
+    0xFFFBFFFF,
+    0xFFF7FFFF,
+    0xFFEFFFFF,
+    0xFFDFFFFF,
+    0xFFBFFFFF,
+    0xFF7FFFFF,
+    0xFEFFFFFF,
+    0xFDFFFFFF,
+    0xFBFFFFFF,
+    0xF7FFFFFF,
+    0xEFFFFFFF,
+    0xDFFFFFFF,
+    0xBFFFFFFF,
+    0x7FFFFFFF,
+    0x3FFFFFFF,
+    0x1FFFFFFF,
+    0x0FFFFFFF,
+    0x07FFFFFF,
+    0x03FFFFFF,
+    0x01FFFFFF,
+    0x00FFFFFF,
+    0x007FFFFF,
+    0x003FFFFF,
+    0x001FFFFF,
+    0x000FFFFF,
+    0x0007FFFF,
+    0x0003FFFF,
+    0x0001FFFF,
+    0x0000FFFF,
+    0x00007FFF,
+    0x00003FFF,
+    0x00001FFF,
+    0x00000FFF,
+    0x000007FF,
+    0x000003FF,
+    0x000001FF,
+    0x000000FF,
+    0x0000007F,
+    0x0000003F,
+    0x0000001F,
+    0x0000000F,
+    0x00000007,
+    0x00000003
+};
+
+static uint32_t ui32NextP1( struct sequence *sequencePtr )
+{
+    int termNum;
+    uint32_t z;
+
+    termNum = sequencePtr->term1Num;
+    z = ui32P1[termNum];
+    ++termNum;
+    if ( ui32NumP1 <= termNum ) {
+        termNum = 0;
+        sequencePtr->done = true;
+    }
+    sequencePtr->term1Num = termNum;
+    return z;
+
+}
+
+static const uint_fast32_t ui32NumP2 = (ui32NumP1 * ui32NumP1 + ui32NumP1) / 2;
+
+static uint32_t ui32NextP2( struct sequence *sequencePtr )
+{
+    int term1Num, term2Num;
+    uint32_t z;
+
+    term2Num = sequencePtr->term2Num;
+    term1Num = sequencePtr->term1Num;
+    z = ui32P1[term1Num] + ui32P1[term2Num];
+    ++term2Num;
+    if ( ui32NumP1 <= term2Num ) {
+        ++term1Num;
+        if ( ui32NumP1 <= term1Num ) {
+            term1Num = 0;
+            sequencePtr->done = true;
+        }
+        term2Num = term1Num;
+        sequencePtr->term1Num = term1Num;
+    }
+    sequencePtr->term2Num = term2Num;
+    return z;
+
+}
+
+static uint32_t ui32RandomP3( void )
+{
+
+    return
+        ui32P1[randomN_ui8( ui32NumP1 )] + ui32P1[randomN_ui8( ui32NumP1 )]
+            + ui32P1[randomN_ui8( ui32NumP1 )];
+
+}
+
+enum { ui32NumPInfWeightMasks = 29 };
+static const uint32_t ui32PInfWeightMasks[ui32NumPInfWeightMasks] = {
+    0xFFFFFFFF,
+    0x7FFFFFFF,
+    0x3FFFFFFF,
+    0x1FFFFFFF,
+    0x0FFFFFFF,
+    0x07FFFFFF,
+    0x03FFFFFF,
+    0x01FFFFFF,
+    0x00FFFFFF,
+    0x007FFFFF,
+    0x003FFFFF,
+    0x001FFFFF,
+    0x000FFFFF,
+    0x0007FFFF,
+    0x0003FFFF,
+    0x0001FFFF,
+    0x0000FFFF,
+    0x00007FFF,
+    0x00003FFF,
+    0x00001FFF,
+    0x00000FFF,
+    0x000007FF,
+    0x000003FF,
+    0x000001FF,
+    0x000000FF,
+    0x0000007F,
+    0x0000003F,
+    0x0000001F,
+    0x0000000F
+};
+
+static uint32_t ui32RandomPInf( void )
+{
+    int weightMaskNum;
+
+    weightMaskNum = randomN_ui8( ui32NumPInfWeightMasks );
+    return random_ui32() & ui32PInfWeightMasks[weightMaskNum];
+
+}
+
+static struct sequence sequenceA;
+static int subcase;
+
+uint32_t genCases_ui32_a;
+
+void genCases_ui32_a_init( void )
+{
+
+    sequenceA.term1Num = 0;
+    sequenceA.term2Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total = (genCases_level == 1) ? 3 * ui32NumP1 : 2 * ui32NumP2;
+    genCases_done = false;
+
+}
+
+void genCases_ui32_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            genCases_ui32_a = ui32RandomP3();
+            break;
+         case 1:
+            genCases_ui32_a = ui32RandomPInf();
+            break;
+         case 2:
+            genCases_ui32_a = ui32NextP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_ui32_a = ui32RandomP3();
+            break;
+         case 2:
+            genCases_ui32_a = ui32RandomPInf();
+            break;
+         case 3:
+            subcase = -1;
+         case 1:
+            genCases_ui32_a = ui32NextP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
diff --git a/addins/TestFloat-3e/source/genCases_ui64.c b/addins/TestFloat-3e/source/genCases_ui64.c
new file mode 100644
index 000000000..42d44a467
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_ui64.c
@@ -0,0 +1,483 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "random.h"
+#include "genCases.h"
+
+struct sequence {
+    int term1Num, term2Num;
+    bool done;
+};
+
+enum { ui64NumP1 = 252 };
+static const uint64_t ui64P1[ui64NumP1] = {
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x0000000000000001 ),
+    UINT64_C( 0x0000000000000002 ),
+    UINT64_C( 0x0000000000000004 ),
+    UINT64_C( 0x0000000000000008 ),
+    UINT64_C( 0x0000000000000010 ),
+    UINT64_C( 0x0000000000000020 ),
+    UINT64_C( 0x0000000000000040 ),
+    UINT64_C( 0x0000000000000080 ),
+    UINT64_C( 0x0000000000000100 ),
+    UINT64_C( 0x0000000000000200 ),
+    UINT64_C( 0x0000000000000400 ),
+    UINT64_C( 0x0000000000000800 ),
+    UINT64_C( 0x0000000000001000 ),
+    UINT64_C( 0x0000000000002000 ),
+    UINT64_C( 0x0000000000004000 ),
+    UINT64_C( 0x0000000000008000 ),
+    UINT64_C( 0x0000000000010000 ),
+    UINT64_C( 0x0000000000020000 ),
+    UINT64_C( 0x0000000000040000 ),
+    UINT64_C( 0x0000000000080000 ),
+    UINT64_C( 0x0000000000100000 ),
+    UINT64_C( 0x0000000000200000 ),
+    UINT64_C( 0x0000000000400000 ),
+    UINT64_C( 0x0000000000800000 ),
+    UINT64_C( 0x0000000001000000 ),
+    UINT64_C( 0x0000000002000000 ),
+    UINT64_C( 0x0000000004000000 ),
+    UINT64_C( 0x0000000008000000 ),
+    UINT64_C( 0x0000000010000000 ),
+    UINT64_C( 0x0000000020000000 ),
+    UINT64_C( 0x0000000040000000 ),
+    UINT64_C( 0x0000000080000000 ),
+    UINT64_C( 0x0000000100000000 ),
+    UINT64_C( 0x0000000200000000 ),
+    UINT64_C( 0x0000000400000000 ),
+    UINT64_C( 0x0000000800000000 ),
+    UINT64_C( 0x0000001000000000 ),
+    UINT64_C( 0x0000002000000000 ),
+    UINT64_C( 0x0000004000000000 ),
+    UINT64_C( 0x0000008000000000 ),
+    UINT64_C( 0x0000010000000000 ),
+    UINT64_C( 0x0000020000000000 ),
+    UINT64_C( 0x0000040000000000 ),
+    UINT64_C( 0x0000080000000000 ),
+    UINT64_C( 0x0000100000000000 ),
+    UINT64_C( 0x0000200000000000 ),
+    UINT64_C( 0x0000400000000000 ),
+    UINT64_C( 0x0000800000000000 ),
+    UINT64_C( 0x0001000000000000 ),
+    UINT64_C( 0x0002000000000000 ),
+    UINT64_C( 0x0004000000000000 ),
+    UINT64_C( 0x0008000000000000 ),
+    UINT64_C( 0x0010000000000000 ),
+    UINT64_C( 0x0020000000000000 ),
+    UINT64_C( 0x0040000000000000 ),
+    UINT64_C( 0x0080000000000000 ),
+    UINT64_C( 0x0100000000000000 ),
+    UINT64_C( 0x0200000000000000 ),
+    UINT64_C( 0x0400000000000000 ),
+    UINT64_C( 0x0800000000000000 ),
+    UINT64_C( 0x1000000000000000 ),
+    UINT64_C( 0x2000000000000000 ),
+    UINT64_C( 0x4000000000000000 ),
+    UINT64_C( 0x8000000000000000 ),
+    UINT64_C( 0xC000000000000000 ),
+    UINT64_C( 0xE000000000000000 ),
+    UINT64_C( 0xF000000000000000 ),
+    UINT64_C( 0xF800000000000000 ),
+    UINT64_C( 0xFC00000000000000 ),
+    UINT64_C( 0xFE00000000000000 ),
+    UINT64_C( 0xFF00000000000000 ),
+    UINT64_C( 0xFF80000000000000 ),
+    UINT64_C( 0xFFC0000000000000 ),
+    UINT64_C( 0xFFE0000000000000 ),
+    UINT64_C( 0xFFF0000000000000 ),
+    UINT64_C( 0xFFF8000000000000 ),
+    UINT64_C( 0xFFFC000000000000 ),
+    UINT64_C( 0xFFFE000000000000 ),
+    UINT64_C( 0xFFFF000000000000 ),
+    UINT64_C( 0xFFFF800000000000 ),
+    UINT64_C( 0xFFFFC00000000000 ),
+    UINT64_C( 0xFFFFE00000000000 ),
+    UINT64_C( 0xFFFFF00000000000 ),
+    UINT64_C( 0xFFFFF80000000000 ),
+    UINT64_C( 0xFFFFFC0000000000 ),
+    UINT64_C( 0xFFFFFE0000000000 ),
+    UINT64_C( 0xFFFFFF0000000000 ),
+    UINT64_C( 0xFFFFFF8000000000 ),
+    UINT64_C( 0xFFFFFFC000000000 ),
+    UINT64_C( 0xFFFFFFE000000000 ),
+    UINT64_C( 0xFFFFFFF000000000 ),
+    UINT64_C( 0xFFFFFFF800000000 ),
+    UINT64_C( 0xFFFFFFFC00000000 ),
+    UINT64_C( 0xFFFFFFFE00000000 ),
+    UINT64_C( 0xFFFFFFFF00000000 ),
+    UINT64_C( 0xFFFFFFFF80000000 ),
+    UINT64_C( 0xFFFFFFFFC0000000 ),
+    UINT64_C( 0xFFFFFFFFE0000000 ),
+    UINT64_C( 0xFFFFFFFFF0000000 ),
+    UINT64_C( 0xFFFFFFFFF8000000 ),
+    UINT64_C( 0xFFFFFFFFFC000000 ),
+    UINT64_C( 0xFFFFFFFFFE000000 ),
+    UINT64_C( 0xFFFFFFFFFF000000 ),
+    UINT64_C( 0xFFFFFFFFFF800000 ),
+    UINT64_C( 0xFFFFFFFFFFC00000 ),
+    UINT64_C( 0xFFFFFFFFFFE00000 ),
+    UINT64_C( 0xFFFFFFFFFFF00000 ),
+    UINT64_C( 0xFFFFFFFFFFF80000 ),
+    UINT64_C( 0xFFFFFFFFFFFC0000 ),
+    UINT64_C( 0xFFFFFFFFFFFE0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF0000 ),
+    UINT64_C( 0xFFFFFFFFFFFF8000 ),
+    UINT64_C( 0xFFFFFFFFFFFFC000 ),
+    UINT64_C( 0xFFFFFFFFFFFFE000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF000 ),
+    UINT64_C( 0xFFFFFFFFFFFFF800 ),
+    UINT64_C( 0xFFFFFFFFFFFFFC00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFE00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF00 ),
+    UINT64_C( 0xFFFFFFFFFFFFFF80 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFC0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFE0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF0 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF8 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFC ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFE ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFD ),
+    UINT64_C( 0xFFFFFFFFFFFFFFFB ),
+    UINT64_C( 0xFFFFFFFFFFFFFFF7 ),
+    UINT64_C( 0xFFFFFFFFFFFFFFEF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFDF ),
+    UINT64_C( 0xFFFFFFFFFFFFFFBF ),
+    UINT64_C( 0xFFFFFFFFFFFFFF7F ),
+    UINT64_C( 0xFFFFFFFFFFFFFEFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFDFF ),
+    UINT64_C( 0xFFFFFFFFFFFFFBFF ),
+    UINT64_C( 0xFFFFFFFFFFFFF7FF ),
+    UINT64_C( 0xFFFFFFFFFFFFEFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFDFFF ),
+    UINT64_C( 0xFFFFFFFFFFFFBFFF ),
+    UINT64_C( 0xFFFFFFFFFFFF7FFF ),
+    UINT64_C( 0xFFFFFFFFFFFEFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFDFFFF ),
+    UINT64_C( 0xFFFFFFFFFFFBFFFF ),
+    UINT64_C( 0xFFFFFFFFFFF7FFFF ),
+    UINT64_C( 0xFFFFFFFFFFEFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFDFFFFF ),
+    UINT64_C( 0xFFFFFFFFFFBFFFFF ),
+    UINT64_C( 0xFFFFFFFFFF7FFFFF ),
+    UINT64_C( 0xFFFFFFFFFEFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFDFFFFFF ),
+    UINT64_C( 0xFFFFFFFFFBFFFFFF ),
+    UINT64_C( 0xFFFFFFFFF7FFFFFF ),
+    UINT64_C( 0xFFFFFFFFEFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFDFFFFFFF ),
+    UINT64_C( 0xFFFFFFFFBFFFFFFF ),
+    UINT64_C( 0xFFFFFFFF7FFFFFFF ),
+    UINT64_C( 0xFFFFFFFEFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFDFFFFFFFF ),
+    UINT64_C( 0xFFFFFFFBFFFFFFFF ),
+    UINT64_C( 0xFFFFFFF7FFFFFFFF ),
+    UINT64_C( 0xFFFFFFEFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFDFFFFFFFFF ),
+    UINT64_C( 0xFFFFFFBFFFFFFFFF ),
+    UINT64_C( 0xFFFFFF7FFFFFFFFF ),
+    UINT64_C( 0xFFFFFEFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFDFFFFFFFFFF ),
+    UINT64_C( 0xFFFFFBFFFFFFFFFF ),
+    UINT64_C( 0xFFFFF7FFFFFFFFFF ),
+    UINT64_C( 0xFFFFEFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFDFFFFFFFFFFF ),
+    UINT64_C( 0xFFFFBFFFFFFFFFFF ),
+    UINT64_C( 0xFFFF7FFFFFFFFFFF ),
+    UINT64_C( 0xFFFEFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFDFFFFFFFFFFFF ),
+    UINT64_C( 0xFFFBFFFFFFFFFFFF ),
+    UINT64_C( 0xFFF7FFFFFFFFFFFF ),
+    UINT64_C( 0xFFEFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFDFFFFFFFFFFFFF ),
+    UINT64_C( 0xFFBFFFFFFFFFFFFF ),
+    UINT64_C( 0xFF7FFFFFFFFFFFFF ),
+    UINT64_C( 0xFEFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFDFFFFFFFFFFFFFF ),
+    UINT64_C( 0xFBFFFFFFFFFFFFFF ),
+    UINT64_C( 0xF7FFFFFFFFFFFFFF ),
+    UINT64_C( 0xEFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xDFFFFFFFFFFFFFFF ),
+    UINT64_C( 0xBFFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x3FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x1FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x0FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x07FFFFFFFFFFFFFF ),
+    UINT64_C( 0x03FFFFFFFFFFFFFF ),
+    UINT64_C( 0x01FFFFFFFFFFFFFF ),
+    UINT64_C( 0x00FFFFFFFFFFFFFF ),
+    UINT64_C( 0x007FFFFFFFFFFFFF ),
+    UINT64_C( 0x003FFFFFFFFFFFFF ),
+    UINT64_C( 0x001FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F ),
+    UINT64_C( 0x0000000000000007 ),
+    UINT64_C( 0x0000000000000003 )
+};
+
+static uint64_t ui64NextP1( struct sequence *sequencePtr )
+{
+    int termNum;
+    uint64_t z;
+
+    termNum = sequencePtr->term1Num;
+    z = ui64P1[termNum];
+    ++termNum;
+    if ( ui64NumP1 <= termNum ) {
+        termNum = 0;
+        sequencePtr->done = true;
+    }
+    sequencePtr->term1Num = termNum;
+    return z;
+
+}
+
+static const uint_fast64_t ui64NumP2 = (ui64NumP1 * ui64NumP1 + ui64NumP1) / 2;
+
+static uint64_t ui64NextP2( struct sequence *sequencePtr )
+{
+    int term1Num, term2Num;
+    uint64_t z;
+
+    term2Num = sequencePtr->term2Num;
+    term1Num = sequencePtr->term1Num;
+    z = ui64P1[term1Num] + ui64P1[term2Num];
+    ++term2Num;
+    if ( ui64NumP1 <= term2Num ) {
+        ++term1Num;
+        if ( ui64NumP1 <= term1Num ) {
+            term1Num = 0;
+            sequencePtr->done = true;
+        }
+        term2Num = term1Num;
+        sequencePtr->term1Num = term1Num;
+    }
+    sequencePtr->term2Num = term2Num;
+    return z;
+
+}
+
+static uint64_t ui64RandomP3( void )
+{
+
+    return
+        ui64P1[randomN_ui8( ui64NumP1 )] + ui64P1[randomN_ui8( ui64NumP1 )]
+            + ui64P1[randomN_ui8( ui64NumP1 )];
+
+}
+
+enum { ui64NumPInfWeightMasks = 61 };
+static const uint64_t ui64PInfWeightMasks[ui64NumPInfWeightMasks] = {
+    UINT64_C( 0xFFFFFFFFFFFFFFFF ),
+    UINT64_C( 0x7FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x3FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x1FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x0FFFFFFFFFFFFFFF ),
+    UINT64_C( 0x07FFFFFFFFFFFFFF ),
+    UINT64_C( 0x03FFFFFFFFFFFFFF ),
+    UINT64_C( 0x01FFFFFFFFFFFFFF ),
+    UINT64_C( 0x00FFFFFFFFFFFFFF ),
+    UINT64_C( 0x007FFFFFFFFFFFFF ),
+    UINT64_C( 0x003FFFFFFFFFFFFF ),
+    UINT64_C( 0x001FFFFFFFFFFFFF ),
+    UINT64_C( 0x000FFFFFFFFFFFFF ),
+    UINT64_C( 0x0007FFFFFFFFFFFF ),
+    UINT64_C( 0x0003FFFFFFFFFFFF ),
+    UINT64_C( 0x0001FFFFFFFFFFFF ),
+    UINT64_C( 0x0000FFFFFFFFFFFF ),
+    UINT64_C( 0x00007FFFFFFFFFFF ),
+    UINT64_C( 0x00003FFFFFFFFFFF ),
+    UINT64_C( 0x00001FFFFFFFFFFF ),
+    UINT64_C( 0x00000FFFFFFFFFFF ),
+    UINT64_C( 0x000007FFFFFFFFFF ),
+    UINT64_C( 0x000003FFFFFFFFFF ),
+    UINT64_C( 0x000001FFFFFFFFFF ),
+    UINT64_C( 0x000000FFFFFFFFFF ),
+    UINT64_C( 0x0000007FFFFFFFFF ),
+    UINT64_C( 0x0000003FFFFFFFFF ),
+    UINT64_C( 0x0000001FFFFFFFFF ),
+    UINT64_C( 0x0000000FFFFFFFFF ),
+    UINT64_C( 0x00000007FFFFFFFF ),
+    UINT64_C( 0x00000003FFFFFFFF ),
+    UINT64_C( 0x00000001FFFFFFFF ),
+    UINT64_C( 0x00000000FFFFFFFF ),
+    UINT64_C( 0x000000007FFFFFFF ),
+    UINT64_C( 0x000000003FFFFFFF ),
+    UINT64_C( 0x000000001FFFFFFF ),
+    UINT64_C( 0x000000000FFFFFFF ),
+    UINT64_C( 0x0000000007FFFFFF ),
+    UINT64_C( 0x0000000003FFFFFF ),
+    UINT64_C( 0x0000000001FFFFFF ),
+    UINT64_C( 0x0000000000FFFFFF ),
+    UINT64_C( 0x00000000007FFFFF ),
+    UINT64_C( 0x00000000003FFFFF ),
+    UINT64_C( 0x00000000001FFFFF ),
+    UINT64_C( 0x00000000000FFFFF ),
+    UINT64_C( 0x000000000007FFFF ),
+    UINT64_C( 0x000000000003FFFF ),
+    UINT64_C( 0x000000000001FFFF ),
+    UINT64_C( 0x000000000000FFFF ),
+    UINT64_C( 0x0000000000007FFF ),
+    UINT64_C( 0x0000000000003FFF ),
+    UINT64_C( 0x0000000000001FFF ),
+    UINT64_C( 0x0000000000000FFF ),
+    UINT64_C( 0x00000000000007FF ),
+    UINT64_C( 0x00000000000003FF ),
+    UINT64_C( 0x00000000000001FF ),
+    UINT64_C( 0x00000000000000FF ),
+    UINT64_C( 0x000000000000007F ),
+    UINT64_C( 0x000000000000003F ),
+    UINT64_C( 0x000000000000001F ),
+    UINT64_C( 0x000000000000000F )
+};
+
+static uint64_t ui64RandomPInf( void )
+{
+    int weightMaskNum;
+
+    weightMaskNum = randomN_ui8( ui64NumPInfWeightMasks );
+    return random_ui64() & ui64PInfWeightMasks[weightMaskNum];
+
+}
+
+static struct sequence sequenceA;
+static int subcase;
+
+uint64_t genCases_ui64_a;
+
+void genCases_ui64_a_init( void )
+{
+
+    sequenceA.term2Num = 0;
+    sequenceA.term1Num = 0;
+    sequenceA.done = false;
+    subcase = 0;
+    genCases_total = (genCases_level == 1) ? 3 * ui64NumP1 : 2 * ui64NumP2;
+    genCases_done = false;
+
+}
+
+void genCases_ui64_a_next( void )
+{
+
+    if ( genCases_level == 1 ) {
+        switch ( subcase ) {
+         case 0:
+            genCases_ui64_a = ui64RandomP3();
+            break;
+         case 1:
+            genCases_ui64_a = ui64RandomPInf();
+            break;
+         case 2:
+            genCases_ui64_a = ui64NextP1( &sequenceA );
+            genCases_done = sequenceA.done;
+            subcase = -1;
+            break;
+        }
+    } else {
+        switch ( subcase ) {
+         case 0:
+            genCases_ui64_a = ui64RandomP3();
+            break;
+         case 2:
+            genCases_ui64_a = ui64RandomPInf();
+            break;
+         case 3:
+            subcase = -1;
+         case 1:
+            genCases_ui64_a = ui64NextP2( &sequenceA );
+            genCases_done = sequenceA.done;
+            break;
+        }
+    }
+    ++subcase;
+
+}
+
diff --git a/addins/TestFloat-3e/source/genCases_writeTestsTotal.c b/addins/TestFloat-3e/source/genCases_writeTestsTotal.c
new file mode 100644
index 000000000..715a7cc2d
--- /dev/null
+++ b/addins/TestFloat-3e/source/genCases_writeTestsTotal.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "genCases.h"
+
+void genCases_writeTestsTotal( bool forever )
+{
+
+    if ( forever ) {
+        fputs( "Unbounded tests.\n", stderr );
+    } else {
+        if ( 2000000000 <= genCases_total ) {
+            fprintf(
+                stderr,
+                "\r%lu%09lu tests total.\n",
+                (long unsigned) (genCases_total / 1000000000),
+                (long unsigned) (genCases_total % 1000000000)
+            );
+        } else {
+            fprintf(
+                stderr, "\r%lu tests total.\n", (long unsigned) genCases_total
+            );
+        }
+    }
+
+}
+
diff --git a/addins/TestFloat-3e/source/genLoops.c b/addins/TestFloat-3e/source/genLoops.c
new file mode 100644
index 000000000..6082fc24e
--- /dev/null
+++ b/addins/TestFloat-3e/source/genLoops.c
@@ -0,0 +1,2890 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "uint128.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "writeHex.h"
+#include "genLoops.h"
+
+volatile sig_atomic_t genLoops_stop = false;
+
+bool genLoops_forever;
+bool genLoops_givenCount;
+uint_fast64_t genLoops_count;
+uint_fast8_t *genLoops_trueFlagsPtr;
+
+#ifdef FLOAT16
+union ui16_f16 { uint16_t ui; float16_t f; };
+#endif
+union ui32_f32 { uint32_t ui; float32_t f; };
+#ifdef FLOAT64
+union ui64_f64 { uint64_t ui; float64_t f; };
+#endif
+
+static void checkEnoughCases( void )
+{
+
+    if ( genLoops_givenCount && (genLoops_count < genCases_total) ) {
+        if ( 2000000000 <= genCases_total ) {
+            fail(
+                "Too few cases; minimum is %lu%09lu",
+                (unsigned long) (genCases_total / 1000000000),
+                (unsigned long) (genCases_total % 1000000000)
+            );
+        } else {
+            fail(
+                "Too few cases; minimum is %lu", (unsigned long) genCases_total
+            );
+        }
+    }
+
+}
+
+static void writeGenOutput_flags( uint_fast8_t flags )
+{
+    uint_fast8_t commonFlags;
+
+    commonFlags = 0;
+    if ( flags & softfloat_flag_invalid   ) commonFlags |= 0x10;
+    if ( flags & softfloat_flag_infinite  ) commonFlags |= 0x08;
+    if ( flags & softfloat_flag_overflow  ) commonFlags |= 0x04;
+    if ( flags & softfloat_flag_underflow ) commonFlags |= 0x02;
+    if ( flags & softfloat_flag_inexact   ) commonFlags |= 0x01;
+    writeHex_ui8( commonFlags, '\n' );
+
+}
+
+static bool writeGenOutputs_bool( bool z, uint_fast8_t flags )
+{
+
+    writeHex_bool( z, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+#ifdef FLOAT16
+
+static bool writeGenOutputs_ui16( uint_fast16_t z, uint_fast8_t flags )
+{
+
+    writeHex_ui16( z, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+#endif
+
+static bool writeGenOutputs_ui32( uint_fast32_t z, uint_fast8_t flags )
+{
+
+    writeHex_ui32( z, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+static bool writeGenOutputs_ui64( uint_fast64_t z, uint_fast8_t flags )
+{
+
+    writeHex_ui64( z, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+#ifdef EXTFLOAT80
+
+static void writeHex_uiExtF80M( const extFloat80_t *aPtr, char sepChar )
+{
+    const struct extFloat80M *aSPtr;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    writeHex_ui16( aSPtr->signExp, 0 );
+    writeHex_ui64( aSPtr->signif, sepChar );
+
+}
+
+static
+bool writeGenOutputs_extF80M( const extFloat80_t *aPtr, uint_fast8_t flags )
+{
+
+    writeHex_uiExtF80M( aPtr, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void writeHex_uiF128M( const float128_t *aPtr, char sepChar )
+{
+    const struct uint128 *uiAPtr;
+
+    uiAPtr = (const struct uint128 *) aPtr;
+    writeHex_ui64( uiAPtr->v64, 0 );
+    writeHex_ui64( uiAPtr->v0, sepChar );
+
+}
+
+static bool writeGenOutputs_f128M( const float128_t *aPtr, uint_fast8_t flags )
+{
+
+    writeHex_uiF128M( aPtr, ' ' );
+    writeGenOutput_flags( flags );
+    if ( genLoops_givenCount ) {
+        --genLoops_count;
+        if ( ! genLoops_count ) return true;
+    }
+    return false;
+
+}
+
+#endif
+
+void gen_a_ui32( void )
+{
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_a_ui64( void )
+{
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_a_i32( void )
+{
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_a_i64( void )
+{
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#ifdef FLOAT16
+
+void gen_a_f16( void )
+{
+    union ui16_f16 uA;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_ab_f16( void )
+{
+    union ui16_f16 u;
+
+    genCases_f16_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_ab_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_b;
+        writeHex_ui16( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_abc_f16( void )
+{
+    union ui16_f16 u;
+
+    genCases_f16_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_abc_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_b;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_c;
+        writeHex_ui16( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#endif
+
+void gen_a_f32( void )
+{
+    union ui32_f32 uA;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_ab_f32( void )
+{
+    union ui32_f32 u;
+
+    genCases_f32_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_ab_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_b;
+        writeHex_ui32( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_abc_f32( void )
+{
+    union ui32_f32 u;
+
+    genCases_f32_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_abc_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_b;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_c;
+        writeHex_ui32( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_f64( void )
+{
+    union ui64_f64 uA;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_ab_f64( void )
+{
+    union ui64_f64 u;
+
+    genCases_f64_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_ab_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_b;
+        writeHex_ui64( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_abc_f64( void )
+{
+    union ui64_f64 u;
+
+    genCases_f64_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_abc_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_b;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_c;
+        writeHex_ui64( u.ui, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_extF80( void )
+{
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_ab_extF80( void )
+{
+
+    genCases_extF80_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_ab_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        writeHex_uiExtF80M( &genCases_extF80_b, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_abc_extF80( void )
+{
+
+    genCases_extF80_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_abc_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        writeHex_uiExtF80M( &genCases_extF80_b, ' ' );
+        writeHex_uiExtF80M( &genCases_extF80_c, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_f128( void )
+{
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_ab_f128( void )
+{
+
+    genCases_f128_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_ab_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        writeHex_uiF128M( &genCases_f128_b, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+void gen_abc_f128( void )
+{
+
+    genCases_f128_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_abc_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        writeHex_uiF128M( &genCases_f128_b, ' ' );
+        writeHex_uiF128M( &genCases_f128_c, '\n' );
+        if ( genLoops_givenCount ) {
+            --genLoops_count;
+            if ( ! genLoops_count ) break;
+        }
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+void gen_a_ui32_z_f16( float16_t trueFunction( uint32_t ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_ui32_z_f32( float32_t trueFunction( uint32_t ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_ui32_z_f64( float64_t trueFunction( uint32_t ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_ui32_z_extF80( void trueFunction( uint32_t, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_ui32_z_f128( void trueFunction( uint32_t, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui32_a_next();
+        writeHex_ui32( genCases_ui32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+void gen_a_ui64_z_f16( float16_t trueFunction( uint64_t ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_ui64_z_f32( float32_t trueFunction( uint64_t ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_ui64_z_f64( float64_t trueFunction( uint64_t ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_ui64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_ui64_z_extF80( void trueFunction( uint64_t, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_ui64_z_f128( void trueFunction( uint64_t, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_ui64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_ui64_a_next();
+        writeHex_ui64( genCases_ui64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+void gen_a_i32_z_f16( float16_t trueFunction( int32_t ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_i32_z_f32( float32_t trueFunction( int32_t ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_i32_z_f64( float64_t trueFunction( int32_t ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_i32_z_extF80( void trueFunction( int32_t, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_i32_z_f128( void trueFunction( int32_t, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i32_a_next();
+        writeHex_ui32( genCases_i32_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+void gen_a_i64_z_f16( float16_t trueFunction( int64_t ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_i64_z_f32( float32_t trueFunction( int64_t ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_i64_z_f64( float64_t trueFunction( int64_t ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_i64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_i64_z_extF80( void trueFunction( int64_t, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_i64_z_f128( void trueFunction( int64_t, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_i64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_i64_a_next();
+        writeHex_ui64( genCases_i64_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+void
+ gen_a_f16_z_ui32_rx(
+     uint_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui16_f16 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_ui64_rx(
+     uint_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui16_f16 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_i32_rx(
+     int_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui16_f16 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_i64_rx(
+     int_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui16_f16 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_ui32_x(
+     uint_fast32_t trueFunction( float16_t, bool ), bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_ui64_x(
+     uint_fast64_t trueFunction( float16_t, bool ), bool exact )
+{
+    union ui16_f16 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_i32_x( int_fast32_t trueFunction( float16_t, bool ), bool exact )
+{
+    union ui16_f16 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f16_z_i64_x( int_fast64_t trueFunction( float16_t, bool ), bool exact )
+{
+    union ui16_f16 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void gen_a_f16_z_f32( float32_t trueFunction( float16_t ) )
+{
+    union ui16_f16 uA;
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f16_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_f16_z_f64( float64_t trueFunction( float16_t ) )
+{
+    union ui16_f16 uA;
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f16_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_f16_z_extF80( void trueFunction( float16_t, extFloat80_t * ) )
+{
+    union ui16_f16 uA;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f16_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_f16_z_f128( void trueFunction( float16_t, float128_t * ) )
+{
+    union ui16_f16 uA;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        uA.f = genCases_f16_a;
+        writeHex_ui16( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f16_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_az_f16( float16_t trueFunction( float16_t ) )
+{
+    union ui16_f16 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f16_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_az_f16_rx(
+     float16_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui16_f16 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_a_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abz_f16( float16_t trueFunction( float16_t, float16_t ) )
+{
+    union ui16_f16 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_ab_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_b;
+        writeHex_ui16( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f16_a, genCases_f16_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abcz_f16( float16_t trueFunction( float16_t, float16_t, float16_t ) )
+{
+    union ui16_f16 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_abc_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_b;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_c;
+        writeHex_ui16( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f16_a, genCases_f16_b, genCases_f16_c );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_ab_f16_z_bool( bool trueFunction( float16_t, float16_t ) )
+{
+    union ui16_f16 u;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f16_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f16_ab_next();
+        u.f = genCases_f16_a;
+        writeHex_ui16( u.ui, ' ' );
+        u.f = genCases_f16_b;
+        writeHex_ui16( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, genCases_f16_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_bool( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void
+ gen_a_f32_z_ui32_rx(
+     uint_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui32_f32 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_ui64_rx(
+     uint_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui32_f32 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_i32_rx(
+     int_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui32_f32 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_i64_rx(
+     int_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui32_f32 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_ui32_x(
+     uint_fast32_t trueFunction( float32_t, bool ), bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_ui64_x(
+     uint_fast64_t trueFunction( float32_t, bool ), bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_i32_x( int_fast32_t trueFunction( float32_t, bool ), bool exact )
+{
+    union ui32_f32 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f32_z_i64_x( int_fast64_t trueFunction( float32_t, bool ), bool exact )
+{
+    union ui32_f32 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT16
+
+void gen_a_f32_z_f16( float16_t trueFunction( float32_t ) )
+{
+    union ui32_f32 uA;
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT64
+
+void gen_a_f32_z_f64( float64_t trueFunction( float32_t ) )
+{
+    union ui32_f32 uA;
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void gen_a_f32_z_extF80( void trueFunction( float32_t, extFloat80_t * ) )
+{
+    union ui32_f32 uA;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_f32_z_f128( void trueFunction( float32_t, float128_t * ) )
+{
+    union ui32_f32 uA;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        uA.f = genCases_f32_a;
+        writeHex_ui32( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f32_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_az_f32( float32_t trueFunction( float32_t ) )
+{
+    union ui32_f32 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f32_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_az_f32_rx(
+     float32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui32_f32 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_a_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abz_f32( float32_t trueFunction( float32_t, float32_t ) )
+{
+    union ui32_f32 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_ab_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_b;
+        writeHex_ui32( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f32_a, genCases_f32_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abcz_f32( float32_t trueFunction( float32_t, float32_t, float32_t ) )
+{
+    union ui32_f32 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_abc_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_b;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_c;
+        writeHex_ui32( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f32_a, genCases_f32_b, genCases_f32_c );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_ab_f32_z_bool( bool trueFunction( float32_t, float32_t ) )
+{
+    union ui32_f32 u;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f32_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f32_ab_next();
+        u.f = genCases_f32_a;
+        writeHex_ui32( u.ui, ' ' );
+        u.f = genCases_f32_b;
+        writeHex_ui32( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, genCases_f32_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_bool( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void
+ gen_a_f64_z_ui32_rx(
+     uint_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui64_f64 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_ui64_rx(
+     uint_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui64_f64 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_i32_rx(
+     int_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui64_f64 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_i64_rx(
+     int_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui64_f64 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_ui32_x(
+     uint_fast32_t trueFunction( float64_t, bool ), bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_ui64_x(
+     uint_fast64_t trueFunction( float64_t, bool ), bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_i32_x( int_fast32_t trueFunction( float64_t, bool ), bool exact )
+{
+    union ui64_f64 uA;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f64_z_i64_x( int_fast64_t trueFunction( float64_t, bool ), bool exact )
+{
+    union ui64_f64 uA;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT16
+
+void gen_a_f64_z_f16( float16_t trueFunction( float64_t ) )
+{
+    union ui64_f64 uA;
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_f64_z_f32( float32_t trueFunction( float64_t ) )
+{
+    union ui64_f64 uA;
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( genCases_f64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef EXTFLOAT80
+
+void gen_a_f64_z_extF80( void trueFunction( float64_t, extFloat80_t * ) )
+{
+    union ui64_f64 uA;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void gen_a_f64_z_f128( void trueFunction( float64_t, float128_t * ) )
+{
+    union ui64_f64 uA;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        uA.f = genCases_f64_a;
+        writeHex_ui64( uA.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f64_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_az_f64( float64_t trueFunction( float64_t ) )
+{
+    union ui64_f64 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f64_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_az_f64_rx(
+     float64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    union ui64_f64 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_a_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abz_f64( float64_t trueFunction( float64_t, float64_t ) )
+{
+    union ui64_f64 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_ab_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_b;
+        writeHex_ui64( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f64_a, genCases_f64_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_abcz_f64( float64_t trueFunction( float64_t, float64_t, float64_t ) )
+{
+    union ui64_f64 u;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_abc_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_b;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_c;
+        writeHex_ui64( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        u.f = trueFunction( genCases_f64_a, genCases_f64_b, genCases_f64_c );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( u.ui, trueFlags ) ) break;
+    }
+
+}
+
+void gen_ab_f64_z_bool( bool trueFunction( float64_t, float64_t ) )
+{
+    union ui64_f64 u;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f64_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f64_ab_next();
+        u.f = genCases_f64_a;
+        writeHex_ui64( u.ui, ' ' );
+        u.f = genCases_f64_b;
+        writeHex_ui64( u.ui, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, genCases_f64_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_bool( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void
+ gen_a_extF80_z_ui32_rx(
+     uint_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_ui64_rx(
+     uint_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_i32_rx(
+     int_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_i64_rx(
+     int_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_ui32_x(
+     uint_fast32_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_ui64_x(
+     uint_fast64_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_i32_x(
+     int_fast32_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_extF80_z_i64_x(
+     int_fast64_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT16
+
+void gen_a_extF80_z_f16( float16_t trueFunction( const extFloat80_t * ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_extF80_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_extF80_z_f32( float32_t trueFunction( const extFloat80_t * ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_extF80_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_extF80_z_f64( float64_t trueFunction( const extFloat80_t * ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_extF80_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void
+ gen_a_extF80_z_f128( void trueFunction( const extFloat80_t *, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_az_extF80( void trueFunction( const extFloat80_t *, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_az_extF80_rx(
+     void
+      trueFunction( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_a_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, roundingMode, exact, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_abz_extF80(
+     void
+      trueFunction(
+          const extFloat80_t *, const extFloat80_t *, extFloat80_t * )
+ )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_ab_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        writeHex_uiExtF80M( &genCases_extF80_b, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &genCases_extF80_b, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_ab_extF80_z_bool(
+     bool trueFunction( const extFloat80_t *, const extFloat80_t * ) )
+{
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_extF80_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_extF80_ab_next();
+        writeHex_uiExtF80M( &genCases_extF80_a, ' ' );
+        writeHex_uiExtF80M( &genCases_extF80_b, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, &genCases_extF80_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_bool( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void
+ gen_a_f128_z_ui32_rx(
+     uint_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_ui64_rx(
+     uint_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_i32_rx(
+     int_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_i64_rx(
+     int_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_ui32_x(
+     uint_fast32_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_ui64_x(
+     uint_fast64_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_i32_x(
+     int_fast32_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_a_f128_z_i64_x(
+     int_fast64_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT16
+
+void gen_a_f128_z_f16( float16_t trueFunction( const float128_t * ) )
+{
+    union ui16_f16 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_f128_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui16( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_a_f128_z_f32( float32_t trueFunction( const float128_t * ) )
+{
+    union ui32_f32 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_f128_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui32( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#ifdef FLOAT64
+
+void gen_a_f128_z_f64( float64_t trueFunction( const float128_t * ) )
+{
+    union ui64_f64 uTrueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        uTrueZ.f = trueFunction( &genCases_f128_a );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_ui64( uTrueZ.ui, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void
+ gen_a_f128_z_extF80( void trueFunction( const float128_t *, extFloat80_t * ) )
+{
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_extF80M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
+void gen_az_f128( void trueFunction( const float128_t *, float128_t * ) )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_az_f128_rx(
+     void trueFunction( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_a_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_a_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, roundingMode, exact, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_abz_f128(
+     void trueFunction( const float128_t *, const float128_t *, float128_t * )
+ )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_ab_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        writeHex_uiF128M( &genCases_f128_b, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &genCases_f128_b, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_abcz_f128(
+     void
+      trueFunction(
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ )
+{
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_abc_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_abc_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        writeHex_uiF128M( &genCases_f128_b, ' ' );
+        writeHex_uiF128M( &genCases_f128_c, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueFunction(
+            &genCases_f128_a, &genCases_f128_b, &genCases_f128_c, &trueZ );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_f128M( &trueZ, trueFlags ) ) break;
+    }
+
+}
+
+void
+ gen_ab_f128_z_bool(
+     bool trueFunction( const float128_t *, const float128_t * ) )
+{
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    genCases_f128_ab_init();
+    checkEnoughCases();
+    while ( ! genLoops_stop && (! genCases_done || genLoops_forever) ) {
+        genCases_f128_ab_next();
+        writeHex_uiF128M( &genCases_f128_a, ' ' );
+        writeHex_uiF128M( &genCases_f128_b, ' ' );
+        *genLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, &genCases_f128_b );
+        trueFlags = *genLoops_trueFlagsPtr;
+        if ( writeGenOutputs_bool( trueZ, trueFlags ) ) break;
+    }
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/genLoops.h b/addins/TestFloat-3e/source/genLoops.h
new file mode 100644
index 000000000..f574b7757
--- /dev/null
+++ b/addins/TestFloat-3e/source/genLoops.h
@@ -0,0 +1,354 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <signal.h>
+#include "softfloat.h"
+
+extern volatile sig_atomic_t genLoops_stop;
+
+extern bool genLoops_forever;
+extern bool genLoops_givenCount;
+extern uint_fast64_t genLoops_count;
+extern uint_fast8_t *genLoops_trueFlagsPtr;
+
+void gen_a_ui32( void );
+void gen_a_ui64( void );
+void gen_a_i32( void );
+void gen_a_i64( void );
+#ifdef FLOAT16
+void gen_a_f16( void );
+void gen_ab_f16( void );
+void gen_abc_f16( void );
+#endif
+void gen_a_f32( void );
+void gen_ab_f32( void );
+void gen_abc_f32( void );
+#ifdef FLOAT64
+void gen_a_f64( void );
+void gen_ab_f64( void );
+void gen_abc_f64( void );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_extF80( void );
+void gen_ab_extF80( void );
+void gen_abc_extF80( void );
+#endif
+#ifdef FLOAT128
+void gen_a_f128( void );
+void gen_ab_f128( void );
+void gen_abc_f128( void );
+#endif
+
+#ifdef FLOAT16
+void gen_a_ui32_z_f16( float16_t ( uint32_t ) );
+#endif
+void gen_a_ui32_z_f32( float32_t ( uint32_t ) );
+#ifdef FLOAT64
+void gen_a_ui32_z_f64( float64_t ( uint32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_ui32_z_extF80( void ( uint32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_ui32_z_f128( void ( uint32_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void gen_a_ui64_z_f16( float16_t ( uint64_t ) );
+#endif
+void gen_a_ui64_z_f32( float32_t ( uint64_t ) );
+#ifdef FLOAT64
+void gen_a_ui64_z_f64( float64_t ( uint64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_ui64_z_extF80( void ( uint64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_ui64_z_f128( void ( uint64_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void gen_a_i32_z_f16( float16_t ( int32_t ) );
+#endif
+void gen_a_i32_z_f32( float32_t ( int32_t ) );
+#ifdef FLOAT64
+void gen_a_i32_z_f64( float64_t ( int32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_i32_z_extF80( void ( int32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_i32_z_f128( void ( int32_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void gen_a_i64_z_f16( float16_t ( int64_t ) );
+#endif
+void gen_a_i64_z_f32( float32_t ( int64_t ) );
+#ifdef FLOAT64
+void gen_a_i64_z_f64( float64_t ( int64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_i64_z_extF80( void ( int64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_i64_z_f128( void ( int64_t, float128_t * ) );
+#endif
+
+#ifdef FLOAT16
+void
+ gen_a_f16_z_ui32_rx(
+     uint_fast32_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f16_z_ui64_rx(
+     uint_fast64_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f16_z_i32_rx(
+     int_fast32_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f16_z_i64_rx(
+     int_fast64_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_a_f16_z_ui32_x( uint_fast32_t ( float16_t, bool ), bool );
+void gen_a_f16_z_ui64_x( uint_fast64_t ( float16_t, bool ), bool );
+void gen_a_f16_z_i32_x( int_fast32_t ( float16_t, bool ), bool );
+void gen_a_f16_z_i64_x( int_fast64_t ( float16_t, bool ), bool );
+void gen_a_f16_z_f32( float32_t ( float16_t ) );
+#ifdef FLOAT64
+void gen_a_f16_z_f64( float64_t ( float16_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_f16_z_extF80( void ( float16_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_f16_z_f128( void ( float16_t, float128_t * ) );
+#endif
+void gen_az_f16( float16_t ( float16_t ) );
+void
+ gen_az_f16_rx(
+     float16_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_abz_f16( float16_t ( float16_t, float16_t ) );
+void gen_abcz_f16( float16_t ( float16_t, float16_t, float16_t ) );
+void gen_ab_f16_z_bool( bool ( float16_t, float16_t ) );
+#endif
+
+void
+ gen_a_f32_z_ui32_rx(
+     uint_fast32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f32_z_ui64_rx(
+     uint_fast64_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f32_z_i32_rx(
+     int_fast32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f32_z_i64_rx(
+     int_fast64_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_a_f32_z_ui32_x( uint_fast32_t ( float32_t, bool ), bool );
+void gen_a_f32_z_ui64_x( uint_fast64_t ( float32_t, bool ), bool );
+void gen_a_f32_z_i32_x( int_fast32_t ( float32_t, bool ), bool );
+void gen_a_f32_z_i64_x( int_fast64_t ( float32_t, bool ), bool );
+#ifdef FLOAT16
+void gen_a_f32_z_f16( float16_t ( float32_t ) );
+#endif
+#ifdef FLOAT64
+void gen_a_f32_z_f64( float64_t ( float32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_f32_z_extF80( void ( float32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_f32_z_f128( void ( float32_t, float128_t * ) );
+#endif
+void gen_az_f32( float32_t ( float32_t ) );
+void
+ gen_az_f32_rx(
+     float32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_abz_f32( float32_t ( float32_t, float32_t ) );
+void gen_abcz_f32( float32_t ( float32_t, float32_t, float32_t ) );
+void gen_ab_f32_z_bool( bool ( float32_t, float32_t ) );
+
+#ifdef FLOAT64
+void
+ gen_a_f64_z_ui32_rx(
+     uint_fast32_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f64_z_ui64_rx(
+     uint_fast64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f64_z_i32_rx(
+     int_fast32_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ gen_a_f64_z_i64_rx(
+     int_fast64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_a_f64_z_ui32_x( uint_fast32_t ( float64_t, bool ), bool );
+void gen_a_f64_z_ui64_x( uint_fast64_t ( float64_t, bool ), bool );
+void gen_a_f64_z_i32_x( int_fast32_t ( float64_t, bool ), bool );
+void gen_a_f64_z_i64_x( int_fast64_t ( float64_t, bool ), bool );
+#ifdef FLOAT16
+void gen_a_f64_z_f16( float16_t ( float64_t ) );
+#endif
+void gen_a_f64_z_f32( float32_t ( float64_t ) );
+#ifdef EXTFLOAT80
+void gen_a_f64_z_extF80( void ( float64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_f64_z_f128( void ( float64_t, float128_t * ) );
+#endif
+void gen_az_f64( float64_t ( float64_t ) );
+void
+ gen_az_f64_rx(
+     float64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void gen_abz_f64( float64_t ( float64_t, float64_t ) );
+void gen_abcz_f64( float64_t ( float64_t, float64_t, float64_t ) );
+void gen_ab_f64_z_bool( bool ( float64_t, float64_t ) );
+#endif
+
+#ifdef EXTFLOAT80
+void
+ gen_a_extF80_z_ui32_rx(
+     uint_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_extF80_z_ui64_rx(
+     uint_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_extF80_z_i32_rx(
+     int_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_extF80_z_i64_rx(
+     int_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_extF80_z_ui32_x( uint_fast32_t ( const extFloat80_t *, bool ), bool );
+void
+ gen_a_extF80_z_ui64_x( uint_fast64_t ( const extFloat80_t *, bool ), bool );
+void gen_a_extF80_z_i32_x( int_fast32_t ( const extFloat80_t *, bool ), bool );
+void gen_a_extF80_z_i64_x( int_fast64_t ( const extFloat80_t *, bool ), bool );
+#ifdef FLOAT16
+void gen_a_extF80_z_f16( float16_t ( const extFloat80_t * ) );
+#endif
+void gen_a_extF80_z_f32( float32_t ( const extFloat80_t * ) );
+#ifdef FLOAT64
+void gen_a_extF80_z_f64( float64_t ( const extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void gen_a_extF80_z_f128( void ( const extFloat80_t *, float128_t * ) );
+#endif
+void gen_az_extF80( void ( const extFloat80_t *, extFloat80_t * ) );
+void
+ gen_az_extF80_rx(
+     void ( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_abz_extF80(
+     void ( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ) );
+void
+ gen_ab_extF80_z_bool( bool ( const extFloat80_t *, const extFloat80_t * ) );
+#endif
+
+#ifdef FLOAT128
+void
+ gen_a_f128_z_ui32_rx(
+     uint_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_f128_z_ui64_rx(
+     uint_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_f128_z_i32_rx(
+     int_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_a_f128_z_i64_rx(
+     int_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void gen_a_f128_z_ui32_x( uint_fast32_t ( const float128_t *, bool ), bool );
+void gen_a_f128_z_ui64_x( uint_fast64_t ( const float128_t *, bool ), bool );
+void gen_a_f128_z_i32_x( int_fast32_t ( const float128_t *, bool ), bool );
+void gen_a_f128_z_i64_x( int_fast64_t ( const float128_t *, bool ), bool );
+#ifdef FLOAT16
+void gen_a_f128_z_f16( float16_t ( const float128_t * ) );
+#endif
+void gen_a_f128_z_f32( float32_t ( const float128_t * ) );
+#ifdef FLOAT64
+void gen_a_f128_z_f64( float64_t ( const float128_t * ) );
+#endif
+#ifdef EXTFLOAT80
+void gen_a_f128_z_extF80( void ( const float128_t *, extFloat80_t * ) );
+#endif
+void gen_az_f128( void ( const float128_t *, float128_t * ) );
+void
+ gen_az_f128_rx(
+     void ( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ gen_abz_f128( void ( const float128_t *, const float128_t *, float128_t * ) );
+void
+ gen_abcz_f128(
+     void
+      (
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ );
+void gen_ab_f128_z_bool( bool ( const float128_t *, const float128_t * ) );
+#endif
+
diff --git a/addins/TestFloat-3e/source/random.c b/addins/TestFloat-3e/source/random.c
new file mode 100644
index 000000000..da0613db2
--- /dev/null
+++ b/addins/TestFloat-3e/source/random.c
@@ -0,0 +1,138 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "platform.h"
+#include "random.h"
+
+uint_fast8_t random_ui8( void )
+{
+
+    return rand()>>4 & 0xFF;
+
+}
+
+uint_fast16_t random_ui16( void )
+{
+
+    return (rand() & 0x0FF0)<<4 | (rand()>>4 & 0xFF);
+
+}
+
+uint_fast32_t random_ui32( void )
+{
+
+    return
+          (uint_fast32_t) (rand() & 0x0FF0)<<20
+        | (uint_fast32_t) (rand() & 0x0FF0)<<12
+        | (rand() & 0x0FF0)<<4
+        | (rand()>>4 & 0xFF);
+
+}
+
+uint_fast64_t random_ui64( void )
+{
+
+    return (uint_fast64_t) random_ui32()<<32 | random_ui32();
+
+}
+
+uint_fast8_t randomN_ui8( uint_fast8_t N )
+{
+    uint_fast8_t scale, z;
+
+    scale = 0;
+    while ( N < 0x80 ) {
+        ++scale;
+        N <<= 1;
+    }
+    do {
+        z = random_ui8();
+    } while ( N <= z );
+    return z>>scale;
+
+}
+
+uint_fast16_t randomN_ui16( uint_fast16_t N )
+{
+    uint_fast16_t scale, z;
+
+    scale = 0;
+    while ( N < 0x8000 ) {
+        ++scale;
+        N <<= 1;
+    }
+    do {
+        z = random_ui16();
+    } while ( N <= z );
+    return z>>scale;
+
+}
+
+uint_fast32_t randomN_ui32( uint_fast32_t N )
+{
+    uint_fast32_t scale, z;
+
+    scale = 0;
+    while ( N < 0x8000 ) {
+        ++scale;
+        N <<= 1;
+    }
+    do {
+        z = random_ui32();
+    } while ( N <= z );
+    return z>>scale;
+
+}
+
+uint_fast64_t randomN_ui64( uint_fast64_t N )
+{
+    uint_fast64_t scale, z;
+
+    scale = 0;
+    while ( N < 0x8000 ) {
+        ++scale;
+        N <<= 1;
+    }
+    do {
+        z = random_ui64();
+    } while ( N <= z );
+    return z>>scale;
+
+}
+
diff --git a/addins/TestFloat-3e/source/random.h b/addins/TestFloat-3e/source/random.h
new file mode 100644
index 000000000..92fe77975
--- /dev/null
+++ b/addins/TestFloat-3e/source/random.h
@@ -0,0 +1,49 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+
+uint_fast8_t random_ui8( void );
+uint_fast16_t random_ui16( void );
+uint_fast32_t random_ui32( void );
+uint_fast64_t random_ui64( void );
+
+uint_fast8_t randomN_ui8( uint_fast8_t );
+uint_fast16_t randomN_ui16( uint_fast16_t );
+uint_fast32_t randomN_ui32( uint_fast32_t );
+uint_fast64_t randomN_ui64( uint_fast64_t );
+
diff --git a/addins/TestFloat-3e/source/readHex.c b/addins/TestFloat-3e/source/readHex.c
new file mode 100644
index 000000000..31182b85c
--- /dev/null
+++ b/addins/TestFloat-3e/source/readHex.c
@@ -0,0 +1,190 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "readHex.h"
+
+bool readHex_bool( bool *aPtr, char sepChar )
+{
+    int i;
+    bool a;
+
+    i = fgetc( stdin );
+    if ( (i == EOF) || (i < '0') || ('1' < i) ) return false;
+    a = i - '0';
+    if ( sepChar ) {
+        i = fgetc( stdin );
+        if ( (sepChar != '\n') || (i != '\r') ) {
+            if ( i != sepChar ) return false;
+        }
+    }
+    *aPtr = a;
+    return true;
+
+}
+
+bool readHex_ui8( uint_least8_t *aPtr, char sepChar )
+{
+    int i;
+    uint_fast8_t a;
+
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a = i<<4;
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a |= i;
+    if ( sepChar ) {
+        i = fgetc( stdin );
+        if ( (sepChar != '\n') || (i != '\r') ) {
+            if ( i != sepChar ) return false;
+        }
+    }
+    *aPtr = a;
+    return true;
+
+}
+
+bool readHex_ui16( uint16_t *aPtr, char sepChar )
+{
+    int i;
+    uint_fast16_t a;
+
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a = (uint_fast16_t) i<<12;
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a |= (uint_fast16_t) i<<8;
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a |= (uint_fast16_t) i<<4;
+    i = fgetc( stdin );
+    if ( i == EOF ) return false;
+    if ( ('0' <= i) && (i <= '9') ) {
+        i -= '0';
+    } else if ( ('A' <= i) && (i <= 'F') ) {
+        i -= 'A' - 10;
+    } else if ( ('a' <= i) && (i <= 'f') ) {
+        i -= 'a' - 10;
+    } else {
+        return false;
+    }
+    a |= i;
+    if ( sepChar ) {
+        i = fgetc( stdin );
+        if ( (sepChar != '\n') || (i != '\r') ) {
+            if ( i != sepChar ) return false;
+        }
+    }
+    *aPtr = a;
+    return true;
+
+}
+
+bool readHex_ui32( uint32_t *aPtr, char sepChar )
+{
+    uint16_t v16, v0;
+
+    if ( ! readHex_ui16( &v16, 0 ) || ! readHex_ui16( &v0, sepChar ) ) {
+        return false;
+    }
+    *aPtr = (uint_fast32_t) v16<<16 | v0;
+    return true;
+
+}
+
+bool readHex_ui64( uint64_t *aPtr, char sepChar )
+{
+    uint32_t v32, v0;
+
+    if ( ! readHex_ui32( &v32, 0 ) || ! readHex_ui32( &v0, sepChar ) ) {
+        return false;
+    }
+    *aPtr = (uint_fast64_t) v32<<32 | v0;
+    return true;
+
+}
+
diff --git a/addins/TestFloat-3e/source/readHex.h b/addins/TestFloat-3e/source/readHex.h
new file mode 100644
index 000000000..82662571c
--- /dev/null
+++ b/addins/TestFloat-3e/source/readHex.h
@@ -0,0 +1,46 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+bool readHex_bool( bool *, char );
+bool readHex_ui8( uint_least8_t *, char );
+bool readHex_ui16( uint16_t *, char );
+bool readHex_ui32( uint32_t *, char );
+bool readHex_ui64( uint64_t *, char );
+
diff --git a/addins/TestFloat-3e/source/slowfloat.c b/addins/TestFloat-3e/source/slowfloat.c
new file mode 100644
index 000000000..d5252613d
--- /dev/null
+++ b/addins/TestFloat-3e/source/slowfloat.c
@@ -0,0 +1,3749 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "uint128.h"
+#include "softfloat.h"
+#include "slowfloat.h"
+
+uint_fast8_t slowfloat_roundingMode;
+uint_fast8_t slowfloat_detectTininess;
+uint_fast8_t slowfloat_exceptionFlags;
+#ifdef EXTFLOAT80
+uint_fast8_t slow_extF80_roundingPrecision;
+#endif
+
+#ifdef FLOAT16
+union ui16_f16 { uint16_t ui; float16_t f; };
+#endif
+union ui32_f32 { uint32_t ui; float32_t f; };
+#ifdef FLOAT64
+union ui64_f64 { uint64_t ui; float64_t f; };
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+struct floatX {
+    bool isNaN;
+    bool isInf;
+    bool isZero;
+    bool sign;
+    int_fast32_t exp;
+    struct uint128 sig;
+};
+
+static const struct floatX floatXNaN =
+    { true, false, false, false, 0, { 0, 0 } };
+static const struct floatX floatXPositiveZero =
+    { false, false, true, false, 0, { 0, 0 } };
+static const struct floatX floatXNegativeZero =
+    { false, false, true, true, 0, { 0, 0 } };
+
+static
+void
+ roundFloatXTo11(
+     bool isTiny, struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast64_t roundBits, sigX64;
+
+    sigX64 = xPtr->sig.v64;
+    roundBits = (sigX64 & UINT64_C( 0x1FFFFFFFFFFF )) | (xPtr->sig.v0 != 0);
+    if ( roundBits ) {
+        sigX64 &= UINT64_C( 0xFFFFE00000000000 );
+        if ( exact ) slowfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( isTiny ) slowfloat_exceptionFlags |= softfloat_flag_underflow;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( roundBits < UINT64_C( 0x100000000000 ) ) goto noIncrement;
+            if (
+                (roundBits == UINT64_C( 0x100000000000 ))
+                    && !(sigX64 & UINT64_C( 0x200000000000 ))
+            ) {
+                goto noIncrement;
+            }
+            break;
+         case softfloat_round_minMag:
+            goto noIncrement;
+         case softfloat_round_min:
+            if ( !xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_max:
+            if ( xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_near_maxMag:
+            if ( roundBits < UINT64_C( 0x100000000000 ) ) goto noIncrement;
+            break;
+#ifdef FLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            sigX64 |= UINT64_C( 0x200000000000 );
+            goto noIncrement;
+#endif
+        }
+        sigX64 += UINT64_C( 0x200000000000 );
+        if ( sigX64 == UINT64_C( 0x0100000000000000 ) ) {
+            ++xPtr->exp;
+            sigX64 = UINT64_C( 0x0080000000000000 );
+        }
+     noIncrement:
+        xPtr->sig.v64 = sigX64;
+        xPtr->sig.v0  = 0;
+    }
+
+}
+
+static
+void
+ roundFloatXTo24(
+     bool isTiny, struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast64_t sigX64;
+    uint_fast32_t roundBits;
+
+    sigX64 = xPtr->sig.v64;
+    roundBits = (uint32_t) sigX64 | (xPtr->sig.v0 != 0);
+    if ( roundBits ) {
+        sigX64 &= UINT64_C( 0xFFFFFFFF00000000 );
+        if ( exact ) slowfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( isTiny ) slowfloat_exceptionFlags |= softfloat_flag_underflow;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( roundBits < 0x80000000 ) goto noIncrement;
+            if (
+                (roundBits == 0x80000000)
+                    && !(sigX64 & UINT64_C( 0x100000000 ))
+            ) {
+                goto noIncrement;
+            }
+            break;
+         case softfloat_round_minMag:
+            goto noIncrement;
+         case softfloat_round_min:
+            if ( !xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_max:
+            if ( xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_near_maxMag:
+            if ( roundBits < 0x80000000 ) goto noIncrement;
+            break;
+#ifdef FLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            sigX64 |= UINT64_C( 0x100000000 );
+            goto noIncrement;
+#endif
+        }
+        sigX64 += UINT64_C( 0x100000000 );
+        if ( sigX64 == UINT64_C( 0x0100000000000000 ) ) {
+            ++xPtr->exp;
+            sigX64 = UINT64_C( 0x0080000000000000 );
+        }
+     noIncrement:
+        xPtr->sig.v64 = sigX64;
+        xPtr->sig.v0  = 0;
+    }
+
+}
+
+static
+void
+ roundFloatXTo53(
+     bool isTiny, struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast64_t sigX64;
+    uint_fast8_t roundBits;
+
+    sigX64 = xPtr->sig.v64;
+    roundBits = (sigX64 & 7) | (xPtr->sig.v0 != 0);
+    if ( roundBits ) {
+        sigX64 &= UINT64_C( 0xFFFFFFFFFFFFFFF8 );
+        if ( exact ) slowfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( isTiny ) slowfloat_exceptionFlags |= softfloat_flag_underflow;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( roundBits < 4 ) goto noIncrement;
+            if ( (roundBits == 4) && !(sigX64 & 8) ) goto noIncrement;
+            break;
+         case softfloat_round_minMag:
+            goto noIncrement;
+         case softfloat_round_min:
+            if ( !xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_max:
+            if ( xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_near_maxMag:
+            if ( roundBits < 4 ) goto noIncrement;
+            break;
+#ifdef FLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            sigX64 |= 8;
+            goto noIncrement;
+#endif
+        }
+        sigX64 += 8;
+        if ( sigX64 == UINT64_C( 0x0100000000000000 ) ) {
+            ++xPtr->exp;
+            sigX64 = UINT64_C( 0x0080000000000000 );
+        }
+     noIncrement:
+        xPtr->sig.v64 = sigX64;
+        xPtr->sig.v0  = 0;
+    }
+
+}
+
+static
+void
+ roundFloatXTo64(
+     bool isTiny, struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast64_t sigX0, roundBits, sigX64;
+
+    sigX0 = xPtr->sig.v0;
+    roundBits = sigX0 & UINT64_C( 0x00FFFFFFFFFFFFFF );
+    if ( roundBits ) {
+        sigX0 &= UINT64_C( 0xFF00000000000000 );
+        if ( exact ) slowfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( isTiny ) slowfloat_exceptionFlags |= softfloat_flag_underflow;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( roundBits < UINT64_C( 0x0080000000000000 ) ) goto noIncrement;
+            if (
+                (roundBits == UINT64_C( 0x0080000000000000 ))
+                    && !(sigX0 & UINT64_C( 0x0100000000000000 ))
+            ) {
+                goto noIncrement;
+            }
+            break;
+         case softfloat_round_minMag:
+            goto noIncrement;
+         case softfloat_round_min:
+            if ( !xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_max:
+            if ( xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_near_maxMag:
+            if ( roundBits < UINT64_C( 0x0080000000000000 ) ) goto noIncrement;
+            break;
+#ifdef FLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            sigX0 |= UINT64_C( 0x100000000000000 );
+            goto noIncrement;
+#endif
+        }
+        sigX0 += UINT64_C( 0x100000000000000 );
+        sigX64 = xPtr->sig.v64 + !sigX0;
+        if ( sigX64 == UINT64_C( 0x0100000000000000 ) ) {
+            ++xPtr->exp;
+            sigX64 = UINT64_C( 0x0080000000000000 );
+        }
+        xPtr->sig.v64 = sigX64;
+     noIncrement:
+        xPtr->sig.v0 = sigX0;
+    }
+
+}
+
+static
+void
+ roundFloatXTo113(
+     bool isTiny, struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast64_t sigX0;
+    uint_fast8_t roundBits;
+    uint_fast64_t sigX64;
+
+    sigX0 = xPtr->sig.v0;
+    roundBits = sigX0 & 0x7F;
+    if ( roundBits ) {
+        sigX0 &= UINT64_C( 0xFFFFFFFFFFFFFF80 );
+        if ( exact ) slowfloat_exceptionFlags |= softfloat_flag_inexact;
+        if ( isTiny ) slowfloat_exceptionFlags |= softfloat_flag_underflow;
+        switch ( roundingMode ) {
+         case softfloat_round_near_even:
+            if ( roundBits < 0x40 ) goto noIncrement;
+            if ( (roundBits == 0x40) && !(sigX0 & 0x80) ) goto noIncrement;
+            break;
+         case softfloat_round_minMag:
+            goto noIncrement;
+         case softfloat_round_min:
+            if ( !xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_max:
+            if ( xPtr->sign ) goto noIncrement;
+            break;
+         case softfloat_round_near_maxMag:
+            if ( roundBits < 0x40 ) goto noIncrement;
+            break;
+#ifdef FLOAT_ROUND_ODD
+         case softfloat_round_odd:
+            sigX0 |= 0x80;
+            goto noIncrement;
+#endif
+        }
+        sigX0 += 0x80;
+        sigX64 = xPtr->sig.v64 + !sigX0;
+        if ( sigX64 == UINT64_C( 0x0100000000000000 ) ) {
+            ++xPtr->exp;
+            sigX64 = UINT64_C( 0x0080000000000000 );
+        }
+        xPtr->sig.v64 = sigX64;
+     noIncrement:
+        xPtr->sig.v0 = sigX0;
+    }
+
+}
+
+static void ui32ToFloatX( uint_fast32_t a, struct floatX *xPtr )
+{
+    uint_fast64_t sig64;
+    int_fast32_t exp;
+
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->sign = false;
+    sig64 = a;
+    if ( a ) {
+        xPtr->isZero = false;
+        exp = 31;
+        sig64 <<= 24;
+        while ( sig64 < UINT64_C( 0x0080000000000000 ) ) {
+            --exp;
+            sig64 <<= 1;
+        }
+        xPtr->exp = exp;
+    } else {
+        xPtr->isZero = true;
+    }
+    xPtr->sig.v64 = sig64;
+    xPtr->sig.v0  = 0;
+
+}
+
+static
+uint_fast32_t
+ floatXToUI32(
+     const struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast8_t savedExceptionFlags;
+    struct floatX x;
+    int_fast32_t shiftDist;
+    uint_fast32_t z;
+
+    if ( xPtr->isInf || xPtr->isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+        return (xPtr->isInf && xPtr->sign) ? 0 : 0xFFFFFFFF;
+    }
+    if ( xPtr->isZero ) return 0;
+    savedExceptionFlags = slowfloat_exceptionFlags;
+    x = *xPtr;
+    shiftDist = 52 - x.exp;
+    if ( 56 < shiftDist ) {
+        x.sig.v64 = 0;
+        x.sig.v0  = 1;
+    } else {
+        while ( 0 < shiftDist ) {
+            x.sig = shortShiftRightJam128( x.sig, 1 );
+            --shiftDist;
+        }
+    }
+    roundFloatXTo53( false, &x, roundingMode, exact );
+    x.sig = shortShiftRightJam128( x.sig, 3 );
+    z = x.sig.v64;
+    if ( (shiftDist < 0) || x.sig.v64>>32 || (x.sign && z) ) {
+        slowfloat_exceptionFlags =
+            savedExceptionFlags | softfloat_flag_invalid;
+        return x.sign ? 0 : 0xFFFFFFFF;
+    }
+    return z;
+
+}
+
+static void ui64ToFloatX( uint_fast64_t a, struct floatX *xPtr )
+{
+    struct uint128 sig;
+    int_fast32_t exp;
+
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->sign = false;
+    sig.v64 = 0;
+    sig.v0  = a;
+    if ( a ) {
+        xPtr->isZero = false;
+        exp = 63;
+        sig = shortShiftLeft128( sig, 56 );
+        while ( sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+            --exp;
+            sig = shortShiftLeft128( sig, 1 );
+        }
+        xPtr->exp = exp;
+    } else {
+        xPtr->isZero = true;
+    }
+    xPtr->sig = sig;
+
+}
+
+static
+uint_fast64_t
+ floatXToUI64(
+     const struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast8_t savedExceptionFlags;
+    struct floatX x;
+    int_fast32_t shiftDist;
+    uint_fast64_t z;
+
+    if ( xPtr->isInf || xPtr->isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+        return
+            (xPtr->isInf && xPtr->sign) ? 0 : UINT64_C( 0xFFFFFFFFFFFFFFFF );
+    }
+    if ( xPtr->isZero ) return 0;
+    savedExceptionFlags = slowfloat_exceptionFlags;
+    x = *xPtr;
+    shiftDist = 112 - x.exp;
+    if ( 116 < shiftDist ) {
+        x.sig.v64 = 0;
+        x.sig.v0  = 1;
+    } else {
+        while ( 0 < shiftDist ) {
+            x.sig = shortShiftRightJam128( x.sig, 1 );
+            --shiftDist;
+        }
+    }
+    roundFloatXTo113( false, &x, roundingMode, exact );
+    x.sig = shortShiftRightJam128( x.sig, 7 );
+    z = x.sig.v0;
+    if ( (shiftDist < 0) || x.sig.v64 || (x.sign && z) ) {
+        slowfloat_exceptionFlags =
+            savedExceptionFlags | softfloat_flag_invalid;
+        return x.sign ? 0 : UINT64_C( 0xFFFFFFFFFFFFFFFF );
+    }
+    return z;
+
+}
+
+static void i32ToFloatX( int_fast32_t a, struct floatX *xPtr )
+{
+    bool sign;
+    uint_fast64_t sig64;
+    int_fast32_t exp;
+
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    sign = (a < 0);
+    xPtr->sign = sign;
+    sig64 = sign ? -(uint64_t) a : a;
+    if ( a ) {
+        xPtr->isZero = false;
+        exp = 31;
+        sig64 <<= 24;
+        while ( sig64 < UINT64_C( 0x0080000000000000 ) ) {
+            --exp;
+            sig64 <<= 1;
+        }
+        xPtr->exp = exp;
+    } else {
+        xPtr->isZero = true;
+    }
+    xPtr->sig.v64 = sig64;
+    xPtr->sig.v0  = 0;
+
+}
+
+static
+int_fast32_t
+ floatXToI32(
+     const struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast8_t savedExceptionFlags;
+    struct floatX x;
+    int_fast32_t shiftDist;
+    union { uint32_t ui; int32_t i; } uZ;
+
+    if ( xPtr->isInf || xPtr->isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+        return (xPtr->isInf && xPtr->sign) ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;
+    }
+    if ( xPtr->isZero ) return 0;
+    savedExceptionFlags = slowfloat_exceptionFlags;
+    x = *xPtr;
+    shiftDist = 52 - x.exp;
+    if ( 56 < shiftDist ) {
+        x.sig.v64 = 0;
+        x.sig.v0  = 1;
+    } else {
+        while ( 0 < shiftDist ) {
+            x.sig = shortShiftRightJam128( x.sig, 1 );
+            --shiftDist;
+        }
+    }
+    roundFloatXTo53( false, &x, roundingMode, exact );
+    x.sig = shortShiftRightJam128( x.sig, 3 );
+    uZ.ui = x.sig.v64;
+    if ( x.sign ) uZ.ui = -uZ.ui;
+    if (
+        (shiftDist < 0) || x.sig.v64>>32
+            || ((uZ.i != 0) && (x.sign != (uZ.i < 0)))
+    ) {
+        slowfloat_exceptionFlags =
+            savedExceptionFlags | softfloat_flag_invalid;
+        return x.sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;
+    }
+    return uZ.i;
+
+}
+
+static void i64ToFloatX( int_fast64_t a, struct floatX *xPtr )
+{
+    bool sign;
+    struct uint128 sig;
+    int_fast32_t exp;
+
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    sign = (a < 0);
+    xPtr->sign = sign;
+    sig.v64 = 0;
+    sig.v0  = sign ? -(uint_fast64_t) a : a;
+    if ( a ) {
+        xPtr->isZero = false;
+        exp = 63;
+        sig = shortShiftLeft128( sig, 56 );
+        while ( sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+            --exp;
+            sig = shortShiftLeft128( sig, 1 );
+        }
+        xPtr->exp = exp;
+    } else {
+        xPtr->isZero = true;
+    }
+    xPtr->sig = sig;
+
+}
+
+static
+int_fast64_t
+ floatXToI64(
+     const struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    uint_fast8_t savedExceptionFlags;
+    struct floatX x;
+    int_fast32_t shiftDist;
+    union { uint64_t ui; int64_t i; } uZ;
+
+    if ( xPtr->isInf || xPtr->isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+        return
+            (xPtr->isInf && xPtr->sign) ? -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1
+                : INT64_C( 0x7FFFFFFFFFFFFFFF );
+    }
+    if ( xPtr->isZero ) return 0;
+    savedExceptionFlags = slowfloat_exceptionFlags;
+    x = *xPtr;
+    shiftDist = 112 - x.exp;
+    if ( 116 < shiftDist ) {
+        x.sig.v64 = 0;
+        x.sig.v0  = 1;
+    } else {
+        while ( 0 < shiftDist ) {
+            x.sig = shortShiftRightJam128( x.sig, 1 );
+            --shiftDist;
+        }
+    }
+    roundFloatXTo113( false, &x, roundingMode, exact );
+    x.sig = shortShiftRightJam128( x.sig, 7 );
+    uZ.ui = x.sig.v0;
+    if ( x.sign ) uZ.ui = -uZ.ui;
+    if (
+        (shiftDist < 0) || x.sig.v64 || ((uZ.i != 0) && (x.sign != (uZ.i < 0)))
+    ) {
+        slowfloat_exceptionFlags =
+            savedExceptionFlags | softfloat_flag_invalid;
+        return
+            x.sign ? -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1
+                : INT64_C( 0x7FFFFFFFFFFFFFFF );
+    }
+    return uZ.i;
+
+}
+
+#ifdef FLOAT16
+
+static void f16ToFloatX( float16_t a, struct floatX *xPtr )
+{
+    union ui16_f16 uA;
+    uint_fast16_t uiA;
+    int_fast8_t exp;
+    uint_fast64_t sig64;
+
+    uA.f = a;
+    uiA = uA.ui;
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->isZero = false;
+    xPtr->sign = ((uiA & 0x8000) != 0);
+    exp = uiA>>10 & 0x1F;
+    sig64 = uiA & 0x03FF;
+    sig64 <<= 45;
+    if ( exp == 0x1F ) {
+        if ( sig64 ) {
+            xPtr->isNaN = true;
+        } else {
+            xPtr->isInf = true;
+        }
+    } else if ( !exp ) {
+        if ( !sig64 ) {
+            xPtr->isZero = true;
+        } else {
+            exp = 1 - 0xF;
+            do {
+                --exp;
+                sig64 <<= 1;
+            } while ( sig64 < UINT64_C( 0x0080000000000000 ) );
+            xPtr->exp = exp;
+        }
+    } else {
+        xPtr->exp = exp - 0xF;
+        sig64 |= UINT64_C( 0x0080000000000000 );
+    }
+    xPtr->sig.v64 = sig64;
+    xPtr->sig.v0  = 0;
+
+}
+
+static float16_t floatXToF16( const struct floatX *xPtr )
+{
+    uint_fast16_t uiZ;
+    struct floatX x, savedX;
+    bool isTiny;
+    int_fast32_t exp;
+    union ui16_f16 uZ;
+
+    if ( xPtr->isNaN ) {
+        uiZ = 0xFFFF;
+        goto uiZ;
+    }
+    if ( xPtr->isInf ) {
+        uiZ = xPtr->sign ? 0xFC00 : 0x7C00;
+        goto uiZ;
+    }
+    if ( xPtr->isZero ) {
+        uiZ = xPtr->sign ? 0x8000 : 0;
+        goto uiZ;
+    }
+    x = *xPtr;
+    while ( UINT64_C( 0x0100000000000000 ) <= x.sig.v64 ) {
+        ++x.exp;
+        x.sig = shortShiftRightJam128( x.sig, 1 );
+    }
+    while ( x.sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+        --x.exp;
+        x.sig = shortShiftLeft128( x.sig, 1 );
+    }
+    savedX = x;
+    isTiny =
+        (slowfloat_detectTininess == softfloat_tininess_beforeRounding)
+            && (x.exp + 0xF <= 0);
+    roundFloatXTo11( isTiny, &x, slowfloat_roundingMode, true );
+    exp = x.exp + 0xF;
+    if ( 0x1F <= exp ) {
+        slowfloat_exceptionFlags |=
+            softfloat_flag_overflow | softfloat_flag_inexact;
+        if ( x.sign ) {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_min:
+             case softfloat_round_near_maxMag:
+                uiZ = 0xFC00;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_max:
+             case softfloat_round_odd:
+                uiZ = 0xFBFF;
+                break;
+            }
+        } else {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_max:
+             case softfloat_round_near_maxMag:
+                uiZ = 0x7C00;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_min:
+             case softfloat_round_odd:
+                uiZ = 0x7BFF;
+                break;
+            }
+        }
+        goto uiZ;
+    }
+    if ( exp <= 0 ) {
+        isTiny = true;
+        x = savedX;
+        exp = x.exp + 0xF;
+        if ( exp < -14 ) {
+            x.sig.v0 = (x.sig.v64 != 0) || (x.sig.v0 != 0);
+            x.sig.v64 = 0;
+        } else {
+            while ( exp <= 0 ) {
+                ++exp;
+                x.sig = shortShiftRightJam128( x.sig, 1 );
+            }
+        }
+        roundFloatXTo11( isTiny, &x, slowfloat_roundingMode, true );
+        exp = (UINT64_C( 0x0080000000000000 ) <= x.sig.v64) ? 1 : 0;
+    }
+    uiZ = (uint_fast16_t) exp<<10;
+    if ( x.sign ) uiZ |= 0x8000;
+    uiZ |= x.sig.v64>>45 & 0x03FF;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
+static void f32ToFloatX( float32_t a, struct floatX *xPtr )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t sig64;
+
+    uA.f = a;
+    uiA = uA.ui;
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->isZero = false;
+    xPtr->sign = ((uiA & 0x80000000) != 0);
+    exp = uiA>>23 & 0xFF;
+    sig64 = uiA & 0x007FFFFF;
+    sig64 <<= 32;
+    if ( exp == 0xFF ) {
+        if ( sig64 ) {
+            xPtr->isNaN = true;
+        } else {
+            xPtr->isInf = true;
+        }
+    } else if ( !exp ) {
+        if ( !sig64 ) {
+            xPtr->isZero = true;
+        } else {
+            exp = 1 - 0x7F;
+            do {
+                --exp;
+                sig64 <<= 1;
+            } while ( sig64 < UINT64_C( 0x0080000000000000 ) );
+            xPtr->exp = exp;
+        }
+    } else {
+        xPtr->exp = exp - 0x7F;
+        sig64 |= UINT64_C( 0x0080000000000000 );
+    }
+    xPtr->sig.v64 = sig64;
+    xPtr->sig.v0  = 0;
+
+}
+
+static float32_t floatXToF32( const struct floatX *xPtr )
+{
+    uint_fast32_t uiZ;
+    struct floatX x, savedX;
+    bool isTiny;
+    int_fast32_t exp;
+    union ui32_f32 uZ;
+
+    if ( xPtr->isNaN ) {
+        uiZ = 0xFFFFFFFF;
+        goto uiZ;
+    }
+    if ( xPtr->isInf ) {
+        uiZ = xPtr->sign ? 0xFF800000 : 0x7F800000;
+        goto uiZ;
+    }
+    if ( xPtr->isZero ) {
+        uiZ = xPtr->sign ? 0x80000000 : 0;
+        goto uiZ;
+    }
+    x = *xPtr;
+    while ( UINT64_C( 0x0100000000000000 ) <= x.sig.v64 ) {
+        ++x.exp;
+        x.sig = shortShiftRightJam128( x.sig, 1 );
+    }
+    while ( x.sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+        --x.exp;
+        x.sig = shortShiftLeft128( x.sig, 1 );
+    }
+    savedX = x;
+    isTiny =
+        (slowfloat_detectTininess == softfloat_tininess_beforeRounding)
+            && (x.exp + 0x7F <= 0);
+    roundFloatXTo24( isTiny, &x, slowfloat_roundingMode, true );
+    exp = x.exp + 0x7F;
+    if ( 0xFF <= exp ) {
+        slowfloat_exceptionFlags |=
+            softfloat_flag_overflow | softfloat_flag_inexact;
+        if ( x.sign ) {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_min:
+             case softfloat_round_near_maxMag:
+                uiZ = 0xFF800000;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_max:
+             case softfloat_round_odd:
+                uiZ = 0xFF7FFFFF;
+                break;
+            }
+        } else {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_max:
+             case softfloat_round_near_maxMag:
+                uiZ = 0x7F800000;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_min:
+             case softfloat_round_odd:
+                uiZ = 0x7F7FFFFF;
+                break;
+            }
+        }
+        goto uiZ;
+    }
+    if ( exp <= 0 ) {
+        isTiny = true;
+        x = savedX;
+        exp = x.exp + 0x7F;
+        if ( exp < -27 ) {
+            x.sig.v0 = (x.sig.v64 != 0) || (x.sig.v0 != 0);
+            x.sig.v64 = 0;
+        } else {
+            while ( exp <= 0 ) {
+                ++exp;
+                x.sig = shortShiftRightJam128( x.sig, 1 );
+            }
+        }
+        roundFloatXTo24( isTiny, &x, slowfloat_roundingMode, true );
+        exp = (UINT64_C( 0x0080000000000000 ) <= x.sig.v64) ? 1 : 0;
+    }
+    uiZ = (uint_fast32_t) exp<<23;
+    if ( x.sign ) uiZ |= 0x80000000;
+    uiZ |= x.sig.v64>>32 & 0x007FFFFF;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#ifdef FLOAT64
+
+static void f64ToFloatX( float64_t a, struct floatX *xPtr )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t exp;
+    uint_fast64_t sig64;
+
+    uA.f = a;
+    uiA = uA.ui;
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->isZero = false;
+    xPtr->sign = ((uiA & UINT64_C( 0x8000000000000000 )) != 0);
+    exp = uiA>>52 & 0x7FF;
+    sig64 = uiA & UINT64_C( 0x000FFFFFFFFFFFFF );
+    if ( exp == 0x7FF ) {
+        if ( sig64 ) {
+            xPtr->isNaN = true;
+        } else {
+            xPtr->isInf = true;
+        }
+    } else if ( !exp ) {
+        if ( !sig64 ) {
+            xPtr->isZero = true;
+        } else {
+            exp = 1 - 0x3FF;
+            do {
+                --exp;
+                sig64 <<= 1;
+            } while ( sig64 < UINT64_C( 0x0010000000000000 ) );
+            xPtr->exp = exp;
+        }
+    } else {
+        xPtr->exp = exp - 0x3FF;
+        sig64 |= UINT64_C( 0x0010000000000000 );
+    }
+    xPtr->sig.v64 = sig64<<3;
+    xPtr->sig.v0  = 0;
+
+}
+
+static float64_t floatXToF64( const struct floatX *xPtr )
+{
+    uint_fast64_t uiZ;
+    struct floatX x, savedX;
+    bool isTiny;
+    int_fast32_t exp;
+    union ui64_f64 uZ;
+
+    if ( xPtr->isNaN ) {
+        uiZ = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+        goto uiZ;
+    }
+    if ( xPtr->isInf ) {
+        uiZ =
+            xPtr->sign ? UINT64_C( 0xFFF0000000000000 )
+                : UINT64_C( 0x7FF0000000000000 );
+        goto uiZ;
+    }
+    if ( xPtr->isZero ) {
+        uiZ = xPtr->sign ? UINT64_C( 0x8000000000000000 ) : 0;
+        goto uiZ;
+    }
+    x = *xPtr;
+    while ( UINT64_C( 0x0100000000000000 ) <= x.sig.v64 ) {
+        ++x.exp;
+        x.sig = shortShiftRightJam128( x.sig, 1 );
+    }
+    while ( x.sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+        --x.exp;
+        x.sig = shortShiftLeft128( x.sig, 1 );
+    }
+    savedX = x;
+    isTiny =
+        (slowfloat_detectTininess == softfloat_tininess_beforeRounding)
+            && (x.exp + 0x3FF <= 0);
+    roundFloatXTo53( isTiny, &x, slowfloat_roundingMode, true );
+    exp = x.exp + 0x3FF;
+    if ( 0x7FF <= exp ) {
+        slowfloat_exceptionFlags |=
+            softfloat_flag_overflow | softfloat_flag_inexact;
+        if ( x.sign ) {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_min:
+             case softfloat_round_near_maxMag:
+                uiZ = UINT64_C( 0xFFF0000000000000 );
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_max:
+             case softfloat_round_odd:
+                uiZ = UINT64_C( 0xFFEFFFFFFFFFFFFF );
+                break;
+            }
+        } else {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_max:
+             case softfloat_round_near_maxMag:
+                uiZ = UINT64_C( 0x7FF0000000000000 );
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_min:
+             case softfloat_round_odd:
+                uiZ = UINT64_C( 0x7FEFFFFFFFFFFFFF );
+                break;
+            }
+        }
+        goto uiZ;
+    }
+    if ( exp <= 0 ) {
+        isTiny = true;
+        x = savedX;
+        exp = x.exp + 0x3FF;
+        if ( exp < -56 ) {
+            x.sig.v0 = (x.sig.v64 != 0) || (x.sig.v0 != 0);
+            x.sig.v64 = 0;
+        } else {
+            while ( exp <= 0 ) {
+                ++exp;
+                x.sig = shortShiftRightJam128( x.sig, 1 );
+            }
+        }
+        roundFloatXTo53( isTiny, &x, slowfloat_roundingMode, true );
+        exp = (UINT64_C( 0x0080000000000000 ) <= x.sig.v64) ? 1 : 0;
+    }
+    uiZ = (uint_fast64_t) exp<<52;
+    if ( x.sign ) uiZ |= UINT64_C( 0x8000000000000000 );
+    uiZ |= x.sig.v64>>3 & UINT64_C( 0x000FFFFFFFFFFFFF );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void extF80MToFloatX( const extFloat80_t *aPtr, struct floatX *xPtr )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+    int_fast32_t exp;
+    struct uint128 sig;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->isZero = false;
+    uiA64 = aSPtr->signExp;
+    xPtr->sign = ((uiA64 & 0x8000) != 0);
+    exp = uiA64 & 0x7FFF;
+    sig.v64 = 0;
+    sig.v0  = aSPtr->signif;
+    if ( exp == 0x7FFF ) {
+        if ( sig.v0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) {
+            xPtr->isNaN = true;
+        } else {
+            xPtr->isInf = true;
+        }
+    } else {
+        if ( !exp ) ++exp;
+        exp -= 0x3FFF;
+        if ( !(sig.v0 & UINT64_C( 0x8000000000000000 )) ) {
+            if ( !sig.v0 ) {
+                xPtr->isZero = true;
+            } else {
+                do {
+                    --exp;
+                    sig.v0 <<= 1;
+                } while ( sig.v0 < UINT64_C( 0x8000000000000000 ) );
+            }
+        }
+        xPtr->exp = exp;
+    }
+    xPtr->sig = shortShiftLeft128( sig, 56 );
+
+}
+
+static void floatXToExtF80M( const struct floatX *xPtr, extFloat80_t *zPtr )
+{
+    struct extFloat80M *zSPtr;
+    struct floatX x, savedX;
+    bool isTiny;
+    int_fast32_t exp;
+    uint_fast64_t uiZ0;
+    uint_fast16_t uiZ64;
+
+    zSPtr = (struct extFloat80M *) zPtr;
+    if ( xPtr->isNaN ) {
+        zSPtr->signExp = 0xFFFF;
+        zSPtr->signif = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+        return;
+    }
+    if ( xPtr->isInf ) {
+        zSPtr->signExp = xPtr->sign ? 0xFFFF : 0x7FFF;
+        zSPtr->signif = UINT64_C( 0x8000000000000000 );
+        return;
+    }
+    if ( xPtr->isZero ) {
+        zSPtr->signExp = xPtr->sign ? 0x8000 : 0;
+        zSPtr->signif = 0;
+        return;
+    }
+    x = *xPtr;
+    while ( UINT64_C( 0x0100000000000000 ) <= x.sig.v64 ) {
+        ++x.exp;
+        x.sig = shortShiftRightJam128( x.sig, 1 );
+    }
+    while ( x.sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+        --x.exp;
+        x.sig = shortShiftLeft128( x.sig, 1 );
+    }
+    savedX = x;
+    isTiny =
+        (slowfloat_detectTininess == softfloat_tininess_beforeRounding)
+            && (x.exp + 0x3FFF <= 0);
+    switch ( slow_extF80_roundingPrecision ) {
+     case 32:
+        roundFloatXTo24( isTiny, &x, slowfloat_roundingMode, true );
+        break;
+     case 64:
+        roundFloatXTo53( isTiny, &x, slowfloat_roundingMode, true );
+        break;
+     default:
+        roundFloatXTo64( isTiny, &x, slowfloat_roundingMode, true );
+        break;
+    }
+    exp = x.exp + 0x3FFF;
+    if ( 0x7FFF <= exp ) {
+        slowfloat_exceptionFlags |=
+            softfloat_flag_overflow | softfloat_flag_inexact;
+        if ( x.sign ) {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_min:
+             case softfloat_round_near_maxMag:
+                zSPtr->signExp = 0xFFFF;
+                zSPtr->signif = UINT64_C( 0x8000000000000000 );
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_max:
+             case softfloat_round_odd:
+                switch ( slow_extF80_roundingPrecision ) {
+                 case 32:
+                    uiZ0 = UINT64_C( 0xFFFFFF0000000000 );
+                    break;
+                 case 64:
+                    uiZ0 = UINT64_C( 0xFFFFFFFFFFFFF800 );
+                    break;
+                 default:
+                    uiZ0 = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+                    break;
+                }
+                zSPtr->signExp = 0xFFFE;
+                zSPtr->signif = uiZ0;
+                break;
+            }
+        } else {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_max:
+             case softfloat_round_near_maxMag:
+                zSPtr->signExp = 0x7FFF;
+                zSPtr->signif = UINT64_C( 0x8000000000000000 );
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_min:
+             case softfloat_round_odd:
+                switch ( slow_extF80_roundingPrecision ) {
+                 case 32:
+                    uiZ0 = UINT64_C( 0xFFFFFF0000000000 );
+                    break;
+                 case 64:
+                    uiZ0 = UINT64_C( 0xFFFFFFFFFFFFF800 );
+                    break;
+                 default:
+                    uiZ0 = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+                    break;
+                }
+                zSPtr->signExp = 0x7FFE;
+                zSPtr->signif = uiZ0;
+                break;
+            }
+        }
+        return;
+    }
+    if ( exp <= 0 ) {
+        isTiny = true;
+        x = savedX;
+        exp = x.exp + 0x3FFF;
+        if ( exp < -70 ) {
+            x.sig.v0 = (x.sig.v64 != 0) || (x.sig.v0 != 0);
+            x.sig.v64 = 0;
+        } else {
+            while ( exp <= 0 ) {
+                ++exp;
+                x.sig = shortShiftRightJam128( x.sig, 1 );
+            }
+        }
+        switch ( slow_extF80_roundingPrecision ) {
+         case 32:
+            roundFloatXTo24( isTiny, &x, slowfloat_roundingMode, true );
+            break;
+         case 64:
+            roundFloatXTo53( isTiny, &x, slowfloat_roundingMode, true );
+            break;
+         default:
+            roundFloatXTo64( isTiny, &x, slowfloat_roundingMode, true );
+            break;
+        }
+        exp = (UINT64_C( 0x0080000000000000 ) <= x.sig.v64) ? 1 : 0;
+    }
+    uiZ64 = exp;
+    if ( x.sign ) uiZ64 |= 0x8000;
+    zSPtr->signExp = uiZ64;
+    zSPtr->signif = shortShiftRightJam128( x.sig, 56 ).v0;
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void f128MToFloatX( const float128_t *aPtr, struct floatX *xPtr )
+{
+    const struct uint128 *uiAPtr;
+    uint_fast64_t uiA64;
+    int_fast32_t exp;
+    struct uint128 sig;
+
+    uiAPtr = (const struct uint128 *) aPtr;
+    xPtr->isNaN = false;
+    xPtr->isInf = false;
+    xPtr->isZero = false;
+    uiA64 = uiAPtr->v64;
+    xPtr->sign = ((uiA64 & UINT64_C( 0x8000000000000000 )) != 0);
+    exp = uiA64>>48 & 0x7FFF;
+    sig.v64 = uiA64 & UINT64_C( 0x0000FFFFFFFFFFFF );
+    sig.v0  = uiAPtr->v0;
+    if ( exp == 0x7FFF ) {
+        if ( sig.v64 || sig.v0 ) {
+            xPtr->isNaN = true;
+        } else {
+            xPtr->isInf = true;
+        }
+    } else if ( !exp ) {
+        if ( !sig.v64 && !sig.v0 ) {
+            xPtr->isZero = true;
+        } else {
+            exp = 1 - 0x3FFF;
+            do {
+                --exp;
+                sig = shortShiftLeft128( sig, 1 );
+            } while ( sig.v64 < UINT64_C( 0x0001000000000000 ) );
+            xPtr->exp = exp;
+        }
+    } else {
+        xPtr->exp = exp - 0x3FFF;
+        sig.v64 |= UINT64_C( 0x0001000000000000 );
+    }
+    xPtr->sig = shortShiftLeft128( sig, 7 );
+
+}
+
+static void floatXToF128M( const struct floatX *xPtr, float128_t *zPtr )
+{
+    struct uint128 *uiZPtr;
+    struct floatX x, savedX;
+    bool isTiny;
+    int_fast32_t exp;
+    uint_fast64_t uiZ64;
+
+    uiZPtr = (struct uint128 *) zPtr;
+    if ( xPtr->isNaN ) {
+        uiZPtr->v64 = uiZPtr->v0 = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+        return;
+    }
+    if ( xPtr->isInf ) {
+        uiZPtr->v64 =
+            xPtr->sign ? UINT64_C( 0xFFFF000000000000 )
+                : UINT64_C( 0x7FFF000000000000 );
+        uiZPtr->v0 = 0;
+        return;
+    }
+    if ( xPtr->isZero ) {
+        uiZPtr->v64 = xPtr->sign ? UINT64_C( 0x8000000000000000 ) : 0;
+        uiZPtr->v0  = 0;
+        return;
+    }
+    x = *xPtr;
+    while ( UINT64_C( 0x0100000000000000 ) <= x.sig.v64 ) {
+        ++x.exp;
+        x.sig = shortShiftRightJam128( x.sig, 1 );
+    }
+    while ( x.sig.v64 < UINT64_C( 0x0080000000000000 ) ) {
+        --x.exp;
+        x.sig = shortShiftLeft128( x.sig, 1 );
+    }
+    savedX = x;
+    isTiny =
+        (slowfloat_detectTininess == softfloat_tininess_beforeRounding)
+            && (x.exp + 0x3FFF <= 0);
+    roundFloatXTo113( isTiny, &x, slowfloat_roundingMode, true );
+    exp = x.exp + 0x3FFF;
+    if ( 0x7FFF <= exp ) {
+        slowfloat_exceptionFlags |=
+            softfloat_flag_overflow | softfloat_flag_inexact;
+        if ( x.sign ) {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_min:
+             case softfloat_round_near_maxMag:
+                uiZPtr->v64 = UINT64_C( 0xFFFF000000000000 );
+                uiZPtr->v0  = 0;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_max:
+             case softfloat_round_odd:
+                uiZPtr->v64 = UINT64_C( 0xFFFEFFFFFFFFFFFF );
+                uiZPtr->v0  = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+                break;
+            }
+        } else {
+            switch ( slowfloat_roundingMode ) {
+             case softfloat_round_near_even:
+             case softfloat_round_max:
+             case softfloat_round_near_maxMag:
+                uiZPtr->v64 = UINT64_C( 0x7FFF000000000000 );
+                uiZPtr->v0  = 0;
+                break;
+             case softfloat_round_minMag:
+             case softfloat_round_min:
+             case softfloat_round_odd:
+                uiZPtr->v64 = UINT64_C( 0x7FFEFFFFFFFFFFFF );
+                uiZPtr->v0  = UINT64_C( 0xFFFFFFFFFFFFFFFF );
+                break;
+            }
+        }
+        return;
+    }
+    if ( exp <= 0 ) {
+        isTiny = true;
+        x = savedX;
+        exp = x.exp + 0x3FFF;
+        if ( exp < -120 ) {
+            x.sig.v0 = (x.sig.v64 != 0) || (x.sig.v0 != 0);
+            x.sig.v64 = 0;
+        } else {
+            while ( exp <= 0 ) {
+                ++exp;
+                x.sig = shortShiftRightJam128( x.sig, 1 );
+            }
+        }
+        roundFloatXTo113( isTiny, &x, slowfloat_roundingMode, true );
+        exp = (UINT64_C( 0x0080000000000000 ) <= x.sig.v64) ? 1 : 0;
+    }
+    uiZ64 = (uint_fast64_t) exp<<48;
+    if ( x.sign ) uiZ64 |= UINT64_C( 0x8000000000000000 );
+    x.sig = shortShiftRightJam128( x.sig, 7 );
+    uiZPtr->v64 = uiZ64 | (x.sig.v64 & UINT64_C( 0x0000FFFFFFFFFFFF ));
+    uiZPtr->v0  = x.sig.v0;
+
+}
+
+#endif
+
+static void floatXInvalid( struct floatX *xPtr )
+{
+
+    slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    *xPtr = floatXNaN;
+
+}
+
+static
+void
+ floatXRoundToInt( struct floatX *xPtr, uint_fast8_t roundingMode, bool exact )
+{
+    int_fast32_t exp, shiftDist;
+    struct uint128 sig;
+
+    if ( xPtr->isNaN || xPtr->isInf ) return;
+    exp = xPtr->exp;
+    shiftDist = 112 - exp;
+    if ( shiftDist <= 0 ) return;
+    if ( 119 < shiftDist ) {
+        xPtr->exp = 112;
+        xPtr->sig.v64 = 0;
+        xPtr->sig.v0 = !xPtr->isZero;
+    } else {
+        sig = xPtr->sig;
+        while ( 0 < shiftDist ) {
+            ++exp;
+            sig = shortShiftRightJam128( sig, 1 );
+            --shiftDist;
+        }
+        xPtr->exp = exp;
+        xPtr->sig = sig;
+    }
+    roundFloatXTo113( false, xPtr, roundingMode, exact );
+    if ( !xPtr->sig.v64 && !xPtr->sig.v0 ) xPtr->isZero = true;
+
+}
+
+static void floatXAdd( struct floatX *xPtr, const struct floatX *yPtr )
+{
+    int_fast32_t expX, expY, expDiff;
+    struct uint128 sigY;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) goto copyY;
+    if ( xPtr->isInf && yPtr->isInf ) {
+        if ( xPtr->sign != yPtr->sign ) floatXInvalid( xPtr );
+        return;
+    }
+    if ( xPtr->isInf ) return;
+    if ( yPtr->isInf ) goto copyY;
+    if ( xPtr->isZero && yPtr->isZero ) {
+        if ( xPtr->sign == yPtr->sign ) return;
+        goto completeCancellation;
+    }
+    expX = xPtr->exp;
+    expY = yPtr->exp;
+    if (
+        (xPtr->sign != yPtr->sign) && (expX == expY)
+            && eq128( xPtr->sig, yPtr->sig )
+    ) {
+ completeCancellation:
+        if (slowfloat_roundingMode == softfloat_round_min) {
+            *xPtr = floatXNegativeZero;
+        } else {
+            *xPtr = floatXPositiveZero;
+        }
+        return;
+    }
+    if ( xPtr->isZero ) goto copyY;
+    if ( yPtr->isZero ) return;
+    expDiff = expX - expY;
+    if ( expDiff < 0 ) {
+        xPtr->exp = expY;
+        if ( expDiff < -120 ) {
+            xPtr->sig.v64 = 0;
+            xPtr->sig.v0  = 1;
+        } else {
+            while ( expDiff < 0 ) {
+                ++expDiff;
+                xPtr->sig = shortShiftRightJam128( xPtr->sig, 1 );
+            }
+        }
+        if ( xPtr->sign != yPtr->sign ) xPtr->sig = neg128( xPtr->sig );
+        xPtr->sign = yPtr->sign;
+        xPtr->sig = add128( xPtr->sig, yPtr->sig );
+    } else {
+        sigY = yPtr->sig;
+        if ( 120 < expDiff ) {
+            sigY.v64 = 0;
+            sigY.v0  = 1;
+        } else {
+            while ( 0 < expDiff ) {
+                --expDiff;
+                sigY = shortShiftRightJam128( sigY, 1 );
+            }
+        }
+        if ( xPtr->sign != yPtr->sign ) sigY = neg128( sigY );
+        xPtr->sig = add128( xPtr->sig, sigY );
+    }
+    if ( xPtr->sig.v64 & UINT64_C( 0x8000000000000000 ) ) {
+        xPtr->sign = !xPtr->sign;
+        xPtr->sig = neg128( xPtr->sig );
+    }
+    return;
+ copyY:
+    *xPtr = *yPtr;
+
+}
+
+static void floatXMul( struct floatX *xPtr, const struct floatX *yPtr )
+{
+    struct uint128 sig;
+    int bitNum;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) {
+        xPtr->isNaN = true;
+        xPtr->isInf = false;
+        xPtr->isZero = false;
+        xPtr->sign = yPtr->sign;
+        return;
+    }
+    if ( yPtr->sign ) xPtr->sign = !xPtr->sign;
+    if ( xPtr->isInf ) {
+        if ( yPtr->isZero ) floatXInvalid( xPtr );
+        return;
+    }
+    if ( yPtr->isInf ) {
+        if ( xPtr->isZero ) {
+            floatXInvalid( xPtr );
+            return;
+        }
+        xPtr->isInf = true;
+        return;
+    }
+    if ( xPtr->isZero || yPtr->isZero ) {
+        if ( xPtr->sign ) {
+            *xPtr = floatXNegativeZero;
+        } else {
+            *xPtr = floatXPositiveZero;
+        }
+        return;
+    }
+    xPtr->exp += yPtr->exp;
+    sig.v64 = 0;
+    sig.v0  = 0;
+    for ( bitNum = 0; bitNum < 120; ++bitNum ) {
+        sig = shortShiftRightJam128( sig, 1 );
+        if ( xPtr->sig.v0 & 1 ) sig = add128( sig, yPtr->sig );
+        xPtr->sig = shortShiftRight128( xPtr->sig, 1 );
+    }
+    if ( UINT64_C( 0x0100000000000000 ) <= sig.v64 ) {
+        ++xPtr->exp;
+        sig = shortShiftRightJam128( sig, 1 );
+    }
+    xPtr->sig = sig;
+
+}
+
+static void floatXDiv( struct floatX *xPtr, const struct floatX *yPtr )
+{
+    struct uint128 sig, negSigY;
+    int bitNum;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) {
+        xPtr->isNaN = true;
+        xPtr->isInf = false;
+        xPtr->isZero = false;
+        xPtr->sign = yPtr->sign;
+        return;
+    }
+    if ( yPtr->sign ) xPtr->sign = !xPtr->sign;
+    if ( xPtr->isInf ) {
+        if ( yPtr->isInf ) floatXInvalid( xPtr );
+        return;
+    }
+    if ( yPtr->isZero ) {
+        if ( xPtr->isZero ) {
+            floatXInvalid( xPtr );
+            return;
+        }
+        slowfloat_exceptionFlags |= softfloat_flag_infinite;
+        xPtr->isInf = true;
+        return;
+    }
+    if ( xPtr->isZero || yPtr->isInf ) {
+        if ( xPtr->sign ) {
+            *xPtr = floatXNegativeZero;
+        } else {
+            *xPtr = floatXPositiveZero;
+        }
+        return;
+    }
+    xPtr->exp -= yPtr->exp + 1;
+    sig.v64 = 0;
+    sig.v0  = 0;
+    negSigY = neg128( yPtr->sig );
+    for ( bitNum = 0; bitNum < 120; ++bitNum ) {
+        if ( le128( yPtr->sig, xPtr->sig ) ) {
+            sig.v0 |= 1;
+            xPtr->sig = add128( xPtr->sig, negSigY );
+        }
+        xPtr->sig = shortShiftLeft128( xPtr->sig, 1 );
+        sig = shortShiftLeft128( sig, 1 );
+    }
+    if ( xPtr->sig.v64 || xPtr->sig.v0 ) sig.v0 |= 1;
+    xPtr->sig = sig;
+
+}
+
+static void floatXRem( struct floatX *xPtr, const struct floatX *yPtr )
+{
+    int_fast32_t expX, expY;
+    struct uint128 sigY, negSigY;
+    bool lastQuotientBit;
+    struct uint128 savedSigX;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) {
+        xPtr->isNaN = true;
+        xPtr->isInf = false;
+        xPtr->isZero = false;
+        xPtr->sign = yPtr->sign;
+        return;
+    }
+    if ( xPtr->isInf || yPtr->isZero ) {
+        floatXInvalid( xPtr );
+        return;
+    }
+    if ( xPtr->isZero || yPtr->isInf ) return;
+    expX = xPtr->exp;
+    expY = yPtr->exp - 1;
+    if ( expX < expY ) return;
+    sigY = shortShiftLeft128( yPtr->sig, 1 );
+    negSigY = neg128( sigY );
+    while ( expY < expX ) {
+        --expX;
+        if ( le128( sigY, xPtr->sig ) ) {
+            xPtr->sig = add128( xPtr->sig, negSigY );
+        }
+        xPtr->sig = shortShiftLeft128( xPtr->sig, 1 );
+    }
+    xPtr->exp = expX;
+    lastQuotientBit = le128( sigY, xPtr->sig );
+    if ( lastQuotientBit ) xPtr->sig = add128( xPtr->sig, negSigY );
+    savedSigX = xPtr->sig;
+    xPtr->sig = neg128( add128( xPtr->sig, negSigY ) );
+    if ( lt128( xPtr->sig, savedSigX ) ) {
+        xPtr->sign = !xPtr->sign;
+    } else if ( lt128( savedSigX, xPtr->sig ) ) {
+        goto restoreSavedSigX;
+    } else {
+        if ( lastQuotientBit ) {
+            xPtr->sign = !xPtr->sign;
+        } else {
+ restoreSavedSigX:
+            xPtr->sig = savedSigX;
+        }
+    }
+    if ( !xPtr->sig.v64 && !xPtr->sig.v0 ) xPtr->isZero = true;
+
+}
+
+static void floatXSqrt( struct floatX *xPtr )
+{
+    struct uint128 sig, bitSig;
+    int bitNum;
+    struct uint128 savedSigX;
+
+    if ( xPtr->isNaN || xPtr->isZero ) return;
+    if ( xPtr->sign ) {
+        floatXInvalid( xPtr );
+        return;
+    }
+    if ( xPtr->isInf ) return;
+    if ( !(xPtr->exp & 1) ) xPtr->sig = shortShiftRightJam128( xPtr->sig, 1 );
+    xPtr->exp >>= 1;
+    sig.v64 = 0;
+    sig.v0  = 0;
+    bitSig.v64 = UINT64_C( 0x0080000000000000 );
+    bitSig.v0  = 0;
+    for ( bitNum = 0; bitNum < 120; ++bitNum ) {
+        savedSigX = xPtr->sig;
+        xPtr->sig = add128( xPtr->sig, neg128( sig ) );
+        xPtr->sig = shortShiftLeft128( xPtr->sig, 1 );
+        xPtr->sig = add128( xPtr->sig, neg128( bitSig ) );
+        if ( xPtr->sig.v64 & UINT64_C( 0x8000000000000000 ) ) {
+            xPtr->sig = shortShiftLeft128( savedSigX, 1 );
+        } else {
+            sig.v64 |= bitSig.v64;
+            sig.v0  |= bitSig.v0;
+        }
+        bitSig = shortShiftRightJam128( bitSig, 1 );
+    }
+    if ( xPtr->sig.v64 || xPtr->sig.v0 ) sig.v0 |= 1;
+    xPtr->sig = sig;
+
+}
+
+static bool floatXEq( const struct floatX *xPtr, const struct floatX *yPtr )
+{
+
+    if ( xPtr->isNaN || yPtr->isNaN ) return false;
+    if ( xPtr->isZero && yPtr->isZero ) return true;
+    if ( xPtr->sign != yPtr->sign ) return false;
+    if ( xPtr->isInf || yPtr->isInf ) return xPtr->isInf && yPtr->isInf;
+    return ( xPtr->exp == yPtr->exp ) && eq128( xPtr->sig, yPtr->sig );
+
+}
+
+static bool floatXLe( const struct floatX *xPtr, const struct floatX *yPtr )
+{
+
+    if ( xPtr->isNaN || yPtr->isNaN ) return false;
+    if ( xPtr->isZero && yPtr->isZero ) return true;
+    if ( xPtr->sign != yPtr->sign ) return xPtr->sign;
+    if ( xPtr->sign ) {
+        if ( xPtr->isInf || yPtr->isZero ) return true;
+        if ( yPtr->isInf || xPtr->isZero ) return false;
+        if ( yPtr->exp < xPtr->exp ) return true;
+        if ( xPtr->exp < yPtr->exp ) return false;
+        return le128( yPtr->sig, xPtr->sig );
+    } else {
+        if ( yPtr->isInf || xPtr->isZero ) return true;
+        if ( xPtr->isInf || yPtr->isZero ) return false;
+        if ( xPtr->exp < yPtr->exp ) return true;
+        if ( yPtr->exp < xPtr->exp ) return false;
+        return le128( xPtr->sig, yPtr->sig );
+    }
+
+}
+
+static bool floatXLt( const struct floatX *xPtr, const struct floatX *yPtr )
+{
+
+    if ( xPtr->isNaN || yPtr->isNaN ) return false;
+    if ( xPtr->isZero && yPtr->isZero ) return false;
+    if ( xPtr->sign != yPtr->sign ) return xPtr->sign;
+    if ( xPtr->isInf && yPtr->isInf ) return false;
+    if ( xPtr->sign ) {
+        if ( xPtr->isInf || yPtr->isZero ) return true;
+        if ( yPtr->isInf || xPtr->isZero ) return false;
+        if ( yPtr->exp < xPtr->exp ) return true;
+        if ( xPtr->exp < yPtr->exp ) return false;
+        return lt128( yPtr->sig, xPtr->sig );
+    } else {
+        if ( yPtr->isInf || xPtr->isZero ) return true;
+        if ( xPtr->isInf || yPtr->isZero ) return false;
+        if ( xPtr->exp < yPtr->exp ) return true;
+        if ( yPtr->exp < xPtr->exp ) return false;
+        return lt128( xPtr->sig, yPtr->sig );
+    }
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#if defined EXTFLOAT80 || defined FLOAT128
+
+#ifdef LITTLEENDIAN
+struct uint256 { uint64_t v0, v64, v128, v192; };
+#else
+struct uint256 { uint64_t v192, v128, v64, v0; };
+#endif
+
+static bool eq256M( const struct uint256 *aPtr, const struct uint256 *bPtr )
+{
+
+    return
+        (aPtr->v192 == bPtr->v192) && (aPtr->v128 == bPtr->v128)
+            && (aPtr->v64 == bPtr->v64) && (aPtr->v0 == bPtr->v0);
+
+}
+
+static void shiftLeft1256M( struct uint256 *ptr )
+{
+    uint64_t dword1, dword2;
+
+    dword1 = ptr->v128;
+    ptr->v192 = ptr->v192<<1 | dword1>>63;
+    dword2 = ptr->v64;
+    ptr->v128 = dword1<<1 | dword2>>63;
+    dword1 = ptr->v0;
+    ptr->v64 = dword2<<1 | dword1>>63;
+    ptr->v0 = dword1<<1;
+
+}
+
+static void shiftRight1256M( struct uint256 *ptr )
+{
+    uint64_t dword1, dword2;
+
+    dword1 = ptr->v64;
+    ptr->v0 = dword1<<63 | ptr->v0>>1;
+    dword2 = ptr->v128;
+    ptr->v64 = dword2<<63 | dword1>>1;
+    dword1 = ptr->v192;
+    ptr->v128 = dword1<<63 | dword2>>1;
+    ptr->v192 = dword1>>1;
+
+}
+
+static void shiftRight1Jam256M( struct uint256 *ptr )
+{
+    int extra;
+
+    extra = ptr->v0 & 1;
+    shiftRight1256M( ptr );
+    ptr->v0 |= extra;
+
+}
+
+static void neg256M( struct uint256 *ptr )
+{
+    uint64_t v64, v0, v128;
+
+    v64 = ptr->v64;
+    v0  = ptr->v0;
+    if ( v64 | v0 ) {
+        ptr->v192 = ~ptr->v192;
+        ptr->v128 = ~ptr->v128;
+        if ( v0 ) {
+            ptr->v64 = ~v64;
+            ptr->v0  = -v0;
+        } else {
+            ptr->v64 = -v64;
+        }
+    } else {
+        v128 = ptr->v128;
+        if ( v128 ) {
+            ptr->v192 = ~ptr->v192;
+            ptr->v128 = -v128;
+        } else {
+            ptr->v192 = -ptr->v192;
+        }
+    }
+
+}
+
+static void add256M( struct uint256 *aPtr, const struct uint256 *bPtr )
+{
+    uint64_t dwordA, dwordZ;
+    unsigned int carry1, carry2;
+
+    dwordA = aPtr->v0;
+    dwordZ = dwordA + bPtr->v0;
+    carry1 = (dwordZ < dwordA);
+    aPtr->v0 = dwordZ;
+    dwordA = aPtr->v64;
+    dwordZ = dwordA + bPtr->v64;
+    carry2 = (dwordZ < dwordA);
+    dwordZ += carry1;
+    carry2 += (dwordZ < carry1);
+    aPtr->v64 = dwordZ;
+    dwordA = aPtr->v128;
+    dwordZ = dwordA + bPtr->v128;
+    carry1 = (dwordZ < dwordA);
+    dwordZ += carry2;
+    carry1 += (dwordZ < carry2);
+    aPtr->v128 = dwordZ;
+    aPtr->v192 = aPtr->v192 + bPtr->v192 + carry1;
+
+}
+
+struct floatX256 {
+    bool isNaN;
+    bool isInf;
+    bool isZero;
+    bool sign;
+    int_fast32_t exp;
+    struct uint256 sig;
+};
+
+static const struct floatX256 floatX256NaN =
+    { true, false, false, false, 0, { 0, 0, 0, 0 } };
+static const struct floatX256 floatX256PositiveZero =
+    { false, false, true, false, 0, { 0, 0, 0, 0 } };
+static const struct floatX256 floatX256NegativeZero =
+    { false, false, true, true, 0, { 0, 0, 0, 0 } };
+
+#ifdef FLOAT128
+
+static void f128MToFloatX256( const float128_t *aPtr, struct floatX256 *xPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    xPtr->isNaN  = x.isNaN;
+    xPtr->isInf  = x.isInf;
+    xPtr->isZero = x.isZero;
+    xPtr->sign   = x.sign;
+    xPtr->exp    = x.exp;
+    xPtr->sig.v192 = x.sig.v64;
+    xPtr->sig.v128 = x.sig.v0;
+    xPtr->sig.v64  = 0;
+    xPtr->sig.v0   = 0;
+
+}
+
+static void floatX256ToF128M( const struct floatX256 *xPtr, float128_t *zPtr )
+{
+    struct floatX x;
+    int_fast32_t expZ;
+    struct uint256 sig;
+
+    x.isNaN  = xPtr->isNaN;
+    x.isInf  = xPtr->isInf;
+    x.isZero = xPtr->isZero;
+    x.sign   = xPtr->sign;
+    if ( !(x.isNaN | x.isInf | x.isZero) ) {
+        expZ = xPtr->exp;
+        sig = xPtr->sig;
+        while ( !sig.v192 ) {
+            expZ -= 64;
+            sig.v192 = sig.v128;
+            sig.v128 = sig.v64;
+            sig.v64  = sig.v0;
+            sig.v0   = 0;
+        }
+        while ( sig.v192 < UINT64_C( 0x0100000000000000 ) ) {
+            --expZ;
+            shiftLeft1256M( &sig );
+        }
+        x.exp = expZ;
+        x.sig.v64 = sig.v192;
+        x.sig.v0 = sig.v128 | ((sig.v64 | sig.v0) != 0);
+    }
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+static void floatX256Invalid( struct floatX256 *xPtr )
+{
+
+    slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    *xPtr = floatX256NaN;
+
+}
+
+static
+void floatX256Add( struct floatX256 *xPtr, const struct floatX256 *yPtr )
+{
+    int_fast32_t expX, expY, expDiff;
+    struct uint256 sigY;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) goto copyY;
+    if ( xPtr->isInf && yPtr->isInf ) {
+        if ( xPtr->sign != yPtr->sign ) floatX256Invalid( xPtr );
+        return;
+    }
+    if ( xPtr->isInf ) return;
+    if ( yPtr->isInf ) goto copyY;
+    if ( xPtr->isZero && yPtr->isZero ) {
+        if ( xPtr->sign == yPtr->sign ) return;
+        goto completeCancellation;
+    }
+    expX = xPtr->exp;
+    expY = yPtr->exp;
+    if (
+        (xPtr->sign != yPtr->sign) && (expX == expY)
+            && eq256M( &xPtr->sig, &yPtr->sig )
+    ) {
+ completeCancellation:
+        if (slowfloat_roundingMode == softfloat_round_min) {
+            *xPtr = floatX256NegativeZero;
+        } else {
+            *xPtr = floatX256PositiveZero;
+        }
+        return;
+    }
+    if ( xPtr->isZero ) goto copyY;
+    if ( yPtr->isZero ) return;
+    expDiff = expX - expY;
+    if ( expDiff < 0 ) {
+        xPtr->exp = expY;
+        if ( expDiff < -248 ) {
+            xPtr->sig.v192 = 0;
+            xPtr->sig.v128 = 0;
+            xPtr->sig.v64  = 0;
+            xPtr->sig.v0   = 1;
+        } else {
+            while ( expDiff < 0 ) {
+                ++expDiff;
+                shiftRight1Jam256M( &xPtr->sig );
+            }
+        }
+        if ( xPtr->sign != yPtr->sign ) neg256M( &xPtr->sig );
+        xPtr->sign = yPtr->sign;
+        add256M( &xPtr->sig, &yPtr->sig );
+    } else {
+        sigY = yPtr->sig;
+        if ( 248 < expDiff ) {
+            sigY.v192 = 0;
+            sigY.v128 = 0;
+            sigY.v64  = 0;
+            sigY.v0   = 1;
+        } else {
+            while ( 0 < expDiff ) {
+                --expDiff;
+                shiftRight1Jam256M( &sigY );
+            }
+        }
+        if ( xPtr->sign != yPtr->sign ) neg256M( &sigY );
+        add256M( &xPtr->sig, &sigY );
+    }
+    if ( xPtr->sig.v192 & UINT64_C( 0x8000000000000000 ) ) {
+        xPtr->sign = !xPtr->sign;
+        neg256M( &xPtr->sig );
+    }
+    return;
+ copyY:
+    *xPtr = *yPtr;
+
+}
+
+static
+void floatX256Mul( struct floatX256 *xPtr, const struct floatX256 *yPtr )
+{
+    struct uint256 sig;
+    int bitNum;
+
+    if ( xPtr->isNaN ) return;
+    if ( yPtr->isNaN ) {
+        xPtr->isNaN = true;
+        xPtr->isInf = false;
+        xPtr->isZero = false;
+        xPtr->sign = yPtr->sign;
+        return;
+    }
+    if ( yPtr->sign ) xPtr->sign = !xPtr->sign;
+    if ( xPtr->isInf ) {
+        if ( yPtr->isZero ) floatX256Invalid( xPtr );
+        return;
+    }
+    if ( yPtr->isInf ) {
+        if ( xPtr->isZero ) {
+            floatX256Invalid( xPtr );
+            return;
+        }
+        xPtr->isInf = true;
+        return;
+    }
+    if ( xPtr->isZero || yPtr->isZero ) {
+        if ( xPtr->sign ) {
+            *xPtr = floatX256NegativeZero;
+        } else {
+            *xPtr = floatX256PositiveZero;
+        }
+        return;
+    }
+    xPtr->exp += yPtr->exp;
+    sig.v192 = 0;
+    sig.v128 = 0;
+    sig.v64  = 0;
+    sig.v0   = 0;
+    for ( bitNum = 0; bitNum < 248; ++bitNum ) {
+        shiftRight1Jam256M( &sig );
+        if ( xPtr->sig.v0 & 1 ) add256M( &sig, &yPtr->sig );
+        shiftRight1256M( &xPtr->sig );
+    }
+    if ( UINT64_C( 0x0100000000000000 ) <= sig.v192 ) {
+        ++xPtr->exp;
+        shiftRight1Jam256M( &sig );
+    }
+    xPtr->sig = sig;
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+float16_t slow_ui32_to_f16( uint32_t a )
+{
+    struct floatX x;
+
+    ui32ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_ui32_to_f32( uint32_t a )
+{
+    struct floatX x;
+
+    ui32ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_ui32_to_f64( uint32_t a )
+{
+    struct floatX x;
+
+    ui32ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    ui32ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_ui32_to_f128M( uint32_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    ui32ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+float16_t slow_ui64_to_f16( uint64_t a )
+{
+    struct floatX x;
+
+    ui64ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_ui64_to_f32( uint64_t a )
+{
+    struct floatX x;
+
+    ui64ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_ui64_to_f64( uint64_t a )
+{
+    struct floatX x;
+
+    ui64ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    ui64ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_ui64_to_f128M( uint64_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    ui64ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+float16_t slow_i32_to_f16( int32_t a )
+{
+    struct floatX x;
+
+    i32ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_i32_to_f32( int32_t a )
+{
+    struct floatX x;
+
+    i32ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_i32_to_f64( int32_t a )
+{
+    struct floatX x;
+
+    i32ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_i32_to_extF80M( int32_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    i32ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_i32_to_f128M( int32_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    i32ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+float16_t slow_i64_to_f16( int64_t a )
+{
+    struct floatX x;
+
+    i64ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_i64_to_f32( int64_t a )
+{
+    struct floatX x;
+
+    i64ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_i64_to_f64( int64_t a )
+{
+    struct floatX x;
+
+    i64ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_i64_to_extF80M( int64_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    i64ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_i64_to_f128M( int64_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    i64ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT16
+
+uint_fast32_t
+ slow_f16_to_ui32( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToUI32( &x, roundingMode, exact );
+
+}
+
+uint_fast64_t
+ slow_f16_to_ui64( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToUI64( &x, roundingMode, exact );
+
+}
+
+int_fast32_t
+ slow_f16_to_i32( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToI32( &x, roundingMode, exact );
+
+}
+
+int_fast64_t
+ slow_f16_to_i64( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToI64( &x, roundingMode, exact );
+
+}
+
+uint_fast32_t slow_f16_to_ui32_r_minMag( float16_t a, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToUI32( &x, softfloat_round_minMag, exact );
+
+}
+
+uint_fast64_t slow_f16_to_ui64_r_minMag( float16_t a, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToUI64( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast32_t slow_f16_to_i32_r_minMag( float16_t a, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToI32( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast64_t slow_f16_to_i64_r_minMag( float16_t a, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToI64( &x, softfloat_round_minMag, exact );
+
+}
+
+float32_t slow_f16_to_f32( float16_t a )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_f16_to_f64( float16_t a )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_f16_to_extF80M( float16_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_f16_to_f128M( float16_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+float16_t
+ slow_f16_roundToInt( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    floatXRoundToInt( &x, roundingMode, exact );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_add( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    floatXAdd( &x, &y );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_sub( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    y.sign = !y.sign;
+    floatXAdd( &x, &y );
+    return floatXToF16( &x );
+
+
+}
+
+float16_t slow_f16_mul( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_mulAdd( float16_t a, float16_t b, float16_t c )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    f16ToFloatX( c, &y );
+    floatXAdd( &x, &y );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_div( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    floatXDiv( &x, &y );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_rem( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    floatXRem( &x, &y );
+    return floatXToF16( &x );
+
+}
+
+float16_t slow_f16_sqrt( float16_t a )
+{
+    struct floatX x;
+
+    f16ToFloatX( a, &x );
+    floatXSqrt( &x );
+    return floatXToF16( &x );
+
+}
+
+bool slow_f16_eq( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f16_le( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f16_lt( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLt( &x, &y );
+
+}
+
+bool slow_f16_eq_signaling( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f16_le_quiet( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f16_lt_quiet( float16_t a, float16_t b )
+{
+    struct floatX x, y;
+
+    f16ToFloatX( a, &x );
+    f16ToFloatX( b, &y );
+    return floatXLt( &x, &y );
+
+}
+
+#endif
+
+uint_fast32_t
+ slow_f32_to_ui32( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToUI32( &x, roundingMode, exact );
+
+}
+
+uint_fast64_t
+ slow_f32_to_ui64( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToUI64( &x, roundingMode, exact );
+
+}
+
+int_fast32_t
+ slow_f32_to_i32( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToI32( &x, roundingMode, exact );
+
+}
+
+int_fast64_t
+ slow_f32_to_i64( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToI64( &x, roundingMode, exact );
+
+}
+
+uint_fast32_t slow_f32_to_ui32_r_minMag( float32_t a, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToUI32( &x, softfloat_round_minMag, exact );
+
+}
+
+uint_fast64_t slow_f32_to_ui64_r_minMag( float32_t a, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToUI64( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast32_t slow_f32_to_i32_r_minMag( float32_t a, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToI32( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast64_t slow_f32_to_i64_r_minMag( float32_t a, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToI64( &x, softfloat_round_minMag, exact );
+
+}
+
+#ifdef FLOAT16
+
+float16_t slow_f32_to_f16( float32_t a )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+#ifdef FLOAT64
+
+float64_t slow_f32_to_f64( float32_t a )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_f32_to_extF80M( float32_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_f32_to_f128M( float32_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+float32_t
+ slow_f32_roundToInt( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    floatXRoundToInt( &x, roundingMode, exact );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_add( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    floatXAdd( &x, &y );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_sub( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    y.sign = !y.sign;
+    floatXAdd( &x, &y );
+    return floatXToF32( &x );
+
+
+}
+
+float32_t slow_f32_mul( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_mulAdd( float32_t a, float32_t b, float32_t c )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    f32ToFloatX( c, &y );
+    floatXAdd( &x, &y );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_div( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    floatXDiv( &x, &y );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_rem( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    floatXRem( &x, &y );
+    return floatXToF32( &x );
+
+}
+
+float32_t slow_f32_sqrt( float32_t a )
+{
+    struct floatX x;
+
+    f32ToFloatX( a, &x );
+    floatXSqrt( &x );
+    return floatXToF32( &x );
+
+}
+
+bool slow_f32_eq( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f32_le( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f32_lt( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLt( &x, &y );
+
+}
+
+bool slow_f32_eq_signaling( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f32_le_quiet( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f32_lt_quiet( float32_t a, float32_t b )
+{
+    struct floatX x, y;
+
+    f32ToFloatX( a, &x );
+    f32ToFloatX( b, &y );
+    return floatXLt( &x, &y );
+
+}
+
+#ifdef FLOAT64
+
+uint_fast32_t
+ slow_f64_to_ui32( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToUI32( &x, roundingMode, exact );
+
+}
+
+uint_fast64_t
+ slow_f64_to_ui64( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToUI64( &x, roundingMode, exact );
+
+}
+
+int_fast32_t
+ slow_f64_to_i32( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToI32( &x, roundingMode, exact );
+
+}
+
+int_fast64_t
+ slow_f64_to_i64( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToI64( &x, roundingMode, exact );
+
+}
+
+uint_fast32_t slow_f64_to_ui32_r_minMag( float64_t a, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToUI32( &x, softfloat_round_minMag, exact );
+
+}
+
+uint_fast64_t slow_f64_to_ui64_r_minMag( float64_t a, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToUI64( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast32_t slow_f64_to_i32_r_minMag( float64_t a, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToI32( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast64_t slow_f64_to_i64_r_minMag( float64_t a, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToI64( &x, softfloat_round_minMag, exact );
+
+}
+
+#ifdef FLOAT16
+
+float16_t slow_f64_to_f16( float64_t a )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_f64_to_f32( float64_t a )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef EXTFLOAT80
+
+void slow_f64_to_extF80M( float64_t a, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_f64_to_f128M( float64_t a, float128_t *zPtr )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+float64_t
+ slow_f64_roundToInt( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    floatXRoundToInt( &x, roundingMode, exact );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_add( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    floatXAdd( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_sub( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    y.sign = !y.sign;
+    floatXAdd( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_mul( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_mulAdd( float64_t a, float64_t b, float64_t c )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    floatXMul( &x, &y );
+    f64ToFloatX( c, &y );
+    floatXAdd( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_div( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    floatXDiv( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_rem( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    floatXRem( &x, &y );
+    return floatXToF64( &x );
+
+}
+
+float64_t slow_f64_sqrt( float64_t a )
+{
+    struct floatX x;
+
+    f64ToFloatX( a, &x );
+    floatXSqrt( &x );
+    return floatXToF64( &x );
+
+}
+
+bool slow_f64_eq( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f64_le( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f64_lt( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLt( &x, &y );
+
+}
+
+bool slow_f64_eq_signaling( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f64_le_quiet( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f64_lt_quiet( float64_t a, float64_t b )
+{
+    struct floatX x, y;
+
+    f64ToFloatX( a, &x );
+    f64ToFloatX( b, &y );
+    return floatXLt( &x, &y );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+uint_fast32_t
+ slow_extF80M_to_ui32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToUI32( &x, roundingMode, exact );
+
+}
+
+uint_fast64_t
+ slow_extF80M_to_ui64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToUI64( &x, roundingMode, exact );
+
+}
+
+int_fast32_t
+ slow_extF80M_to_i32(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToI32( &x, roundingMode, exact );
+
+}
+
+int_fast64_t
+ slow_extF80M_to_i64(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToI64( &x, roundingMode, exact );
+
+}
+
+uint_fast32_t
+ slow_extF80M_to_ui32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToUI32( &x, softfloat_round_minMag, exact );
+
+}
+
+uint_fast64_t
+ slow_extF80M_to_ui64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToUI64( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast32_t
+ slow_extF80M_to_i32_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToI32( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast64_t
+ slow_extF80M_to_i64_r_minMag( const extFloat80_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToI64( &x, softfloat_round_minMag, exact );
+
+}
+
+#ifdef FLOAT16
+
+float16_t slow_extF80M_to_f16( const extFloat80_t *aPtr )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_extF80M_to_f32( const extFloat80_t *aPtr )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_extF80M_to_f64( const extFloat80_t *aPtr )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void slow_extF80M_to_f128M( const extFloat80_t *aPtr, float128_t *zPtr )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+#endif
+
+void
+ slow_extF80M_roundToInt(
+     const extFloat80_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     extFloat80_t *zPtr
+ )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    floatXRoundToInt( &x, roundingMode, exact );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void
+ slow_extF80M_add(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    floatXAdd( &x, &y );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void
+ slow_extF80M_sub(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    y.sign = !y.sign;
+    floatXAdd( &x, &y );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void
+ slow_extF80M_mul(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    floatXMul( &x, &y );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void
+ slow_extF80M_div(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    floatXDiv( &x, &y );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void
+ slow_extF80M_rem(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    floatXRem( &x, &y );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+void slow_extF80M_sqrt( const extFloat80_t *aPtr, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    extF80MToFloatX( aPtr, &x );
+    floatXSqrt( &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+bool slow_extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLt( &x, &y );
+
+}
+
+bool
+ slow_extF80M_eq_signaling(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_extF80M_le_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_extF80M_lt_quiet( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    struct floatX x, y;
+
+    extF80MToFloatX( aPtr, &x );
+    extF80MToFloatX( bPtr, &y );
+    return floatXLt( &x, &y );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+uint_fast32_t
+ slow_f128M_to_ui32(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToUI32( &x, roundingMode, exact );
+
+}
+
+uint_fast64_t
+ slow_f128M_to_ui64(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToUI64( &x, roundingMode, exact );
+
+}
+
+int_fast32_t
+ slow_f128M_to_i32(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToI32( &x, roundingMode, exact );
+
+}
+
+int_fast64_t
+ slow_f128M_to_i64(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToI64( &x, roundingMode, exact );
+
+}
+
+uint_fast32_t slow_f128M_to_ui32_r_minMag( const float128_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToUI32( &x, softfloat_round_minMag, exact );
+
+}
+
+uint_fast64_t slow_f128M_to_ui64_r_minMag( const float128_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToUI64( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast32_t slow_f128M_to_i32_r_minMag( const float128_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToI32( &x, softfloat_round_minMag, exact );
+
+}
+
+int_fast64_t slow_f128M_to_i64_r_minMag( const float128_t *aPtr, bool exact )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToI64( &x, softfloat_round_minMag, exact );
+
+}
+
+#ifdef FLOAT16
+
+float16_t slow_f128M_to_f16( const float128_t *aPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToF16( &x );
+
+}
+
+#endif
+
+float32_t slow_f128M_to_f32( const float128_t *aPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToF32( &x );
+
+}
+
+#ifdef FLOAT64
+
+float64_t slow_f128M_to_f64( const float128_t *aPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    return floatXToF64( &x );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void slow_f128M_to_extF80M( const float128_t *aPtr, extFloat80_t *zPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    floatXToExtF80M( &x, zPtr );
+
+}
+
+#endif
+
+void
+ slow_f128M_roundToInt(
+     const float128_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     float128_t *zPtr
+ )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    floatXRoundToInt( &x, roundingMode, exact );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_add(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    floatXAdd( &x, &y );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_sub(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    y.sign = !y.sign;
+    floatXAdd( &x, &y );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_mul(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    floatXMul( &x, &y );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_mulAdd(
+     const float128_t *aPtr,
+     const float128_t *bPtr,
+     const float128_t *cPtr,
+     float128_t *zPtr
+ )
+{
+    struct floatX256 x, y;
+
+    f128MToFloatX256( aPtr, &x );
+    f128MToFloatX256( bPtr, &y );
+    floatX256Mul( &x, &y );
+    f128MToFloatX256( cPtr, &y );
+    floatX256Add( &x, &y );
+    floatX256ToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_div(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    floatXDiv( &x, &y );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void
+ slow_f128M_rem(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    floatXRem( &x, &y );
+    floatXToF128M( &x, zPtr );
+
+}
+
+void slow_f128M_sqrt( const float128_t *aPtr, float128_t *zPtr )
+{
+    struct floatX x;
+
+    f128MToFloatX( aPtr, &x );
+    floatXSqrt( &x );
+    floatXToF128M( &x, zPtr );
+
+}
+
+bool slow_f128M_eq( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f128M_le( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f128M_lt( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXLt( &x, &y );
+
+}
+
+bool slow_f128M_eq_signaling( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    if ( x.isNaN || y.isNaN ) {
+        slowfloat_exceptionFlags |= softfloat_flag_invalid;
+    }
+    return floatXEq( &x, &y );
+
+}
+
+bool slow_f128M_le_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    return floatXLe( &x, &y );
+
+}
+
+bool slow_f128M_lt_quiet( const float128_t *aPtr, const float128_t *bPtr )
+{
+    struct floatX x, y;
+
+    f128MToFloatX( aPtr, &x );
+    f128MToFloatX( bPtr, &y );
+    return floatXLt( &x, &y );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/slowfloat.h b/addins/TestFloat-3e/source/slowfloat.h
new file mode 100644
index 000000000..7af1d1eb5
--- /dev/null
+++ b/addins/TestFloat-3e/source/slowfloat.h
@@ -0,0 +1,298 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+extern uint_fast8_t slowfloat_roundingMode;
+extern uint_fast8_t slowfloat_detectTininess;
+extern uint_fast8_t slowfloat_exceptionFlags;
+#ifdef EXTFLOAT80
+extern uint_fast8_t slow_extF80_roundingPrecision;
+#endif
+
+#ifdef FLOAT16
+float16_t slow_ui32_to_f16( uint32_t );
+#endif
+float32_t slow_ui32_to_f32( uint32_t );
+#ifdef FLOAT64
+float64_t slow_ui32_to_f64( uint32_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_ui32_to_extF80M( uint32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_ui32_to_f128M( uint32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t slow_ui64_to_f16( uint64_t );
+#endif
+float32_t slow_ui64_to_f32( uint64_t );
+#ifdef FLOAT64
+float64_t slow_ui64_to_f64( uint64_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_ui64_to_extF80M( uint64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_ui64_to_f128M( uint64_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t slow_i32_to_f16( int32_t );
+#endif
+float32_t slow_i32_to_f32( int32_t );
+#ifdef FLOAT64
+float64_t slow_i32_to_f64( int32_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_i32_to_extF80M( int32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_i32_to_f128M( int32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t slow_i64_to_f16( int64_t );
+#endif
+float32_t slow_i64_to_f32( int64_t );
+#ifdef FLOAT64
+float64_t slow_i64_to_f64( int64_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_i64_to_extF80M( int64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_i64_to_f128M( int64_t, float128_t * );
+#endif
+
+#ifdef FLOAT16
+uint_fast32_t slow_f16_to_ui32( float16_t, uint_fast8_t, bool );
+uint_fast64_t slow_f16_to_ui64( float16_t, uint_fast8_t, bool );
+int_fast32_t slow_f16_to_i32( float16_t, uint_fast8_t, bool );
+int_fast64_t slow_f16_to_i64( float16_t, uint_fast8_t, bool );
+uint_fast32_t slow_f16_to_ui32_r_minMag( float16_t, bool );
+uint_fast64_t slow_f16_to_ui64_r_minMag( float16_t, bool );
+int_fast32_t slow_f16_to_i32_r_minMag( float16_t, bool );
+int_fast64_t slow_f16_to_i64_r_minMag( float16_t, bool );
+float32_t slow_f16_to_f32( float16_t );
+#ifdef FLOAT64
+float64_t slow_f16_to_f64( float16_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_f16_to_extF80M( float16_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_f16_to_f128M( float16_t, float128_t * );
+#endif
+float16_t slow_f16_roundToInt( float16_t, uint_fast8_t, bool );
+float16_t slow_f16_add( float16_t, float16_t );
+float16_t slow_f16_sub( float16_t, float16_t );
+float16_t slow_f16_mul( float16_t, float16_t );
+float16_t slow_f16_mulAdd( float16_t, float16_t, float16_t );
+float16_t slow_f16_div( float16_t, float16_t );
+float16_t slow_f16_rem( float16_t, float16_t );
+float16_t slow_f16_sqrt( float16_t );
+bool slow_f16_eq( float16_t, float16_t );
+bool slow_f16_le( float16_t, float16_t );
+bool slow_f16_lt( float16_t, float16_t );
+bool slow_f16_eq_signaling( float16_t, float16_t );
+bool slow_f16_le_quiet( float16_t, float16_t );
+bool slow_f16_lt_quiet( float16_t, float16_t );
+#endif
+
+uint_fast32_t slow_f32_to_ui32( float32_t, uint_fast8_t, bool );
+uint_fast64_t slow_f32_to_ui64( float32_t, uint_fast8_t, bool );
+int_fast32_t slow_f32_to_i32( float32_t, uint_fast8_t, bool );
+int_fast64_t slow_f32_to_i64( float32_t, uint_fast8_t, bool );
+uint_fast32_t slow_f32_to_ui32_r_minMag( float32_t, bool );
+uint_fast64_t slow_f32_to_ui64_r_minMag( float32_t, bool );
+int_fast32_t slow_f32_to_i32_r_minMag( float32_t, bool );
+int_fast64_t slow_f32_to_i64_r_minMag( float32_t, bool );
+#ifdef FLOAT16
+float16_t slow_f32_to_f16( float32_t );
+#endif
+#ifdef FLOAT64
+float64_t slow_f32_to_f64( float32_t );
+#endif
+#ifdef EXTFLOAT80
+void slow_f32_to_extF80M( float32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_f32_to_f128M( float32_t, float128_t * );
+#endif
+float32_t slow_f32_roundToInt( float32_t, uint_fast8_t, bool );
+float32_t slow_f32_add( float32_t, float32_t );
+float32_t slow_f32_sub( float32_t, float32_t );
+float32_t slow_f32_mul( float32_t, float32_t );
+float32_t slow_f32_mulAdd( float32_t, float32_t, float32_t );
+float32_t slow_f32_div( float32_t, float32_t );
+float32_t slow_f32_rem( float32_t, float32_t );
+float32_t slow_f32_sqrt( float32_t );
+bool slow_f32_eq( float32_t, float32_t );
+bool slow_f32_le( float32_t, float32_t );
+bool slow_f32_lt( float32_t, float32_t );
+bool slow_f32_eq_signaling( float32_t, float32_t );
+bool slow_f32_le_quiet( float32_t, float32_t );
+bool slow_f32_lt_quiet( float32_t, float32_t );
+
+#ifdef FLOAT64
+uint_fast32_t slow_f64_to_ui32( float64_t, uint_fast8_t, bool );
+uint_fast64_t slow_f64_to_ui64( float64_t, uint_fast8_t, bool );
+int_fast32_t slow_f64_to_i32( float64_t, uint_fast8_t, bool );
+int_fast64_t slow_f64_to_i64( float64_t, uint_fast8_t, bool );
+uint_fast32_t slow_f64_to_ui32_r_minMag( float64_t, bool );
+uint_fast64_t slow_f64_to_ui64_r_minMag( float64_t, bool );
+int_fast32_t slow_f64_to_i32_r_minMag( float64_t, bool );
+int_fast64_t slow_f64_to_i64_r_minMag( float64_t, bool );
+#ifdef FLOAT16
+float16_t slow_f64_to_f16( float64_t );
+#endif
+float32_t slow_f64_to_f32( float64_t );
+#ifdef EXTFLOAT80
+void slow_f64_to_extF80M( float64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_f64_to_f128M( float64_t, float128_t * );
+#endif
+float64_t slow_f64_roundToInt( float64_t, uint_fast8_t, bool );
+float64_t slow_f64_add( float64_t, float64_t );
+float64_t slow_f64_sub( float64_t, float64_t );
+float64_t slow_f64_mul( float64_t, float64_t );
+float64_t slow_f64_mulAdd( float64_t, float64_t, float64_t );
+float64_t slow_f64_div( float64_t, float64_t );
+float64_t slow_f64_rem( float64_t, float64_t );
+float64_t slow_f64_sqrt( float64_t );
+bool slow_f64_eq( float64_t, float64_t );
+bool slow_f64_le( float64_t, float64_t );
+bool slow_f64_lt( float64_t, float64_t );
+bool slow_f64_eq_signaling( float64_t, float64_t );
+bool slow_f64_le_quiet( float64_t, float64_t );
+bool slow_f64_lt_quiet( float64_t, float64_t );
+#endif
+
+#ifdef EXTFLOAT80
+uint_fast32_t slow_extF80M_to_ui32( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast64_t slow_extF80M_to_ui64( const extFloat80_t *, uint_fast8_t, bool );
+int_fast32_t slow_extF80M_to_i32( const extFloat80_t *, uint_fast8_t, bool );
+int_fast64_t slow_extF80M_to_i64( const extFloat80_t *, uint_fast8_t, bool );
+uint_fast32_t slow_extF80M_to_ui32_r_minMag( const extFloat80_t *, bool );
+uint_fast64_t slow_extF80M_to_ui64_r_minMag( const extFloat80_t *, bool );
+int_fast32_t slow_extF80M_to_i32_r_minMag( const extFloat80_t *, bool );
+int_fast64_t slow_extF80M_to_i64_r_minMag( const extFloat80_t *, bool );
+#ifdef FLOAT16
+float16_t slow_extF80M_to_f16( const extFloat80_t * );
+#endif
+float32_t slow_extF80M_to_f32( const extFloat80_t * );
+#ifdef FLOAT64
+float64_t slow_extF80M_to_f64( const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void slow_extF80M_to_f128M( const extFloat80_t *, float128_t * );
+#endif
+void
+ slow_extF80M_roundToInt(
+     const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * );
+void
+ slow_extF80M_add(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ slow_extF80M_sub(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ slow_extF80M_mul(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ slow_extF80M_mulAdd(
+     const extFloat80_t *,
+     const extFloat80_t *,
+     const extFloat80_t *,
+     extFloat80_t *
+ );
+void
+ slow_extF80M_div(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ slow_extF80M_rem(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void slow_extF80M_sqrt( const extFloat80_t *, extFloat80_t * );
+bool slow_extF80M_eq( const extFloat80_t *, const extFloat80_t * );
+bool slow_extF80M_le( const extFloat80_t *, const extFloat80_t * );
+bool slow_extF80M_lt( const extFloat80_t *, const extFloat80_t * );
+bool slow_extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * );
+bool slow_extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * );
+bool slow_extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * );
+#endif
+
+#ifdef FLOAT128
+uint_fast32_t slow_f128M_to_ui32( const float128_t *, uint_fast8_t, bool );
+uint_fast64_t slow_f128M_to_ui64( const float128_t *, uint_fast8_t, bool );
+int_fast32_t slow_f128M_to_i32( const float128_t *, uint_fast8_t, bool );
+int_fast64_t slow_f128M_to_i64( const float128_t *, uint_fast8_t, bool );
+uint_fast32_t slow_f128M_to_ui32_r_minMag( const float128_t *, bool );
+uint_fast64_t slow_f128M_to_ui64_r_minMag( const float128_t *, bool );
+int_fast32_t slow_f128M_to_i32_r_minMag( const float128_t *, bool );
+int_fast64_t slow_f128M_to_i64_r_minMag( const float128_t *, bool );
+#ifdef FLOAT16
+float16_t slow_f128M_to_f16( const float128_t * );
+#endif
+float32_t slow_f128M_to_f32( const float128_t * );
+#ifdef FLOAT64
+float64_t slow_f128M_to_f64( const float128_t * );
+#endif
+#ifdef EXTFLOAT80
+void slow_f128M_to_extF80M( const float128_t *, extFloat80_t * );
+#endif
+void
+ slow_f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * );
+void slow_f128M_add( const float128_t *, const float128_t *, float128_t * );
+void slow_f128M_sub( const float128_t *, const float128_t *, float128_t * );
+void slow_f128M_mul( const float128_t *, const float128_t *, float128_t * );
+void
+ slow_f128M_mulAdd(
+     const float128_t *, const float128_t *, const float128_t *, float128_t *
+ );
+void slow_f128M_div( const float128_t *, const float128_t *, float128_t * );
+void slow_f128M_rem( const float128_t *, const float128_t *, float128_t * );
+void slow_f128M_sqrt( const float128_t *, float128_t * );
+bool slow_f128M_eq( const float128_t *, const float128_t * );
+bool slow_f128M_le( const float128_t *, const float128_t * );
+bool slow_f128M_lt( const float128_t *, const float128_t * );
+bool slow_f128M_eq_signaling( const float128_t *, const float128_t * );
+bool slow_f128M_le_quiet( const float128_t *, const float128_t * );
+bool slow_f128M_lt_quiet( const float128_t *, const float128_t * );
+#endif
+
diff --git a/addins/TestFloat-3e/source/standardFunctionInfos.c b/addins/TestFloat-3e/source/standardFunctionInfos.c
new file mode 100644
index 000000000..fa6a61dc5
--- /dev/null
+++ b/addins/TestFloat-3e/source/standardFunctionInfos.c
@@ -0,0 +1,471 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "functions.h"
+
+#define RNEVEN ROUND_NEAR_EVEN
+#define RMINM  ROUND_MINMAG
+#define RMIN   ROUND_MIN
+#define RMAX   ROUND_MAX
+#define RNMAXM ROUND_NEAR_MAXMAG
+
+const struct standardFunctionInfo standardFunctionInfos[] = {
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    { "ui32_to_f16",    UI32_TO_F16,    0, 0 },
+#endif
+    { "ui32_to_f32",    UI32_TO_F32,    0, 0 },
+#ifdef FLOAT64
+    { "ui32_to_f64",    UI32_TO_F64,    0, 0 },
+#endif
+#ifdef EXTFLOAT80
+    { "ui32_to_extF80", UI32_TO_EXTF80, 0, 0 },
+#endif
+#ifdef FLOAT128
+    { "ui32_to_f128",   UI32_TO_F128,   0, 0 },
+#endif
+#ifdef FLOAT16
+    { "ui64_to_f16",    UI64_TO_F16,    0, 0 },
+#endif
+    { "ui64_to_f32",    UI64_TO_F32,    0, 0 },
+#ifdef FLOAT64
+    { "ui64_to_f64",    UI64_TO_F64,    0, 0 },
+#endif
+#ifdef EXTFLOAT80
+    { "ui64_to_extF80", UI64_TO_EXTF80, 0, 0 },
+#endif
+#ifdef FLOAT128
+    { "ui64_to_f128",   UI64_TO_F128,   0, 0 },
+#endif
+#ifdef FLOAT16
+    { "i32_to_f16",     I32_TO_F16,     0, 0 },
+#endif
+    { "i32_to_f32",     I32_TO_F32,     0, 0 },
+#ifdef FLOAT64
+    { "i32_to_f64",     I32_TO_F64,     0, 0 },
+#endif
+#ifdef EXTFLOAT80
+    { "i32_to_extF80",  I32_TO_EXTF80,  0, 0 },
+#endif
+#ifdef FLOAT128
+    { "i32_to_f128",    I32_TO_F128,    0, 0 },
+#endif
+#ifdef FLOAT16
+    { "i64_to_f16",     I64_TO_F16,     0, 0 },
+#endif
+    { "i64_to_f32",     I64_TO_F32,     0, 0 },
+#ifdef FLOAT64
+    { "i64_to_f64",     I64_TO_F64,     0, 0 },
+#endif
+#ifdef EXTFLOAT80
+    { "i64_to_extF80",  I64_TO_EXTF80,  0, 0 },
+#endif
+#ifdef FLOAT128
+    { "i64_to_f128",    I64_TO_F128,    0, 0 },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+    { "f16_to_ui32_r_near_even",         F16_TO_UI32,         RNEVEN, false },
+    { "f16_to_ui32_r_minMag",            F16_TO_UI32,         RMINM,  false },
+    { "f16_to_ui32_r_min",               F16_TO_UI32,         RMIN,   false },
+    { "f16_to_ui32_r_max",               F16_TO_UI32,         RMAX,   false },
+    { "f16_to_ui32_r_near_maxMag",       F16_TO_UI32,         RNMAXM, false },
+    { "f16_to_ui64_r_near_even",         F16_TO_UI64,         RNEVEN, false },
+    { "f16_to_ui64_r_minMag",            F16_TO_UI64,         RMINM,  false },
+    { "f16_to_ui64_r_min",               F16_TO_UI64,         RMIN,   false },
+    { "f16_to_ui64_r_max",               F16_TO_UI64,         RMAX,   false },
+    { "f16_to_ui64_r_near_maxMag",       F16_TO_UI64,         RNMAXM, false },
+    { "f16_to_i32_r_near_even",          F16_TO_I32,          RNEVEN, false },
+    { "f16_to_i32_r_minMag",             F16_TO_I32,          RMINM,  false },
+    { "f16_to_i32_r_min",                F16_TO_I32,          RMIN,   false },
+    { "f16_to_i32_r_max",                F16_TO_I32,          RMAX,   false },
+    { "f16_to_i32_r_near_maxMag",        F16_TO_I32,          RNMAXM, false },
+    { "f16_to_i64_r_near_even",          F16_TO_I64,          RNEVEN, false },
+    { "f16_to_i64_r_minMag",             F16_TO_I64,          RMINM,  false },
+    { "f16_to_i64_r_min",                F16_TO_I64,          RMIN,   false },
+    { "f16_to_i64_r_max",                F16_TO_I64,          RMAX,   false },
+    { "f16_to_i64_r_near_maxMag",        F16_TO_I64,          RNMAXM, false },
+    { "f16_to_ui32_rx_near_even",        F16_TO_UI32,         RNEVEN, true  },
+    { "f16_to_ui32_rx_minMag",           F16_TO_UI32,         RMINM,  true  },
+    { "f16_to_ui32_rx_min",              F16_TO_UI32,         RMIN,   true  },
+    { "f16_to_ui32_rx_max",              F16_TO_UI32,         RMAX,   true  },
+    { "f16_to_ui32_rx_near_maxMag",      F16_TO_UI32,         RNMAXM, true  },
+    { "f16_to_ui64_rx_near_even",        F16_TO_UI64,         RNEVEN, true  },
+    { "f16_to_ui64_rx_minMag",           F16_TO_UI64,         RMINM,  true  },
+    { "f16_to_ui64_rx_min",              F16_TO_UI64,         RMIN,   true  },
+    { "f16_to_ui64_rx_max",              F16_TO_UI64,         RMAX,   true  },
+    { "f16_to_ui64_rx_near_maxMag",      F16_TO_UI64,         RNMAXM, true  },
+    { "f16_to_i32_rx_near_even",         F16_TO_I32,          RNEVEN, true  },
+    { "f16_to_i32_rx_minMag",            F16_TO_I32,          RMINM,  true  },
+    { "f16_to_i32_rx_min",               F16_TO_I32,          RMIN,   true  },
+    { "f16_to_i32_rx_max",               F16_TO_I32,          RMAX,   true  },
+    { "f16_to_i32_rx_near_maxMag",       F16_TO_I32,          RNMAXM, true  },
+    { "f16_to_i64_rx_near_even",         F16_TO_I64,          RNEVEN, true  },
+    { "f16_to_i64_rx_minMag",            F16_TO_I64,          RMINM,  true  },
+    { "f16_to_i64_rx_min",               F16_TO_I64,          RMIN,   true  },
+    { "f16_to_i64_rx_max",               F16_TO_I64,          RMAX,   true  },
+    { "f16_to_i64_rx_near_maxMag",       F16_TO_I64,          RNMAXM, true  },
+    { "f16_to_f32",                      F16_TO_F32,          0,      0     },
+#ifdef FLOAT64
+    { "f16_to_f64",                      F16_TO_F64,          0,      0     },
+#endif
+#ifdef EXTFLOAT80
+    { "f16_to_extF80",                   F16_TO_EXTF80,       0,      0     },
+#endif
+#ifdef FLOAT128
+    { "f16_to_f128",                     F16_TO_F128,         0,      0     },
+#endif
+    { "f16_roundToInt_r_near_even",      F16_ROUNDTOINT,      RNEVEN, false },
+    { "f16_roundToInt_r_minMag",         F16_ROUNDTOINT,      RMINM,  false },
+    { "f16_roundToInt_r_min",            F16_ROUNDTOINT,      RMIN,   false },
+    { "f16_roundToInt_r_max",            F16_ROUNDTOINT,      RMAX,   false },
+    { "f16_roundToInt_r_near_maxMag",    F16_ROUNDTOINT,      RNMAXM, false },
+    { "f16_roundToInt_x",                F16_ROUNDTOINT,      0,      true  },
+    { "f16_add",                         F16_ADD,             0,      0     },
+    { "f16_sub",                         F16_SUB,             0,      0     },
+    { "f16_mul",                         F16_MUL,             0,      0     },
+    { "f16_mulAdd",                      F16_MULADD,          0,      0     },
+    { "f16_div",                         F16_DIV,             0,      0     },
+    { "f16_rem",                         F16_REM,             0,      0     },
+    { "f16_sqrt",                        F16_SQRT,            0,      0     },
+    { "f16_eq",                          F16_EQ,              0,      0     },
+    { "f16_le",                          F16_LE,              0,      0     },
+    { "f16_lt",                          F16_LT,              0,      0     },
+    { "f16_eq_signaling",                F16_EQ_SIGNALING,    0,      0     },
+    { "f16_le_quiet",                    F16_LE_QUIET,        0,      0     },
+    { "f16_lt_quiet",                    F16_LT_QUIET,        0,      0     },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    { "f32_to_ui32_r_near_even",         F32_TO_UI32,         RNEVEN, false },
+    { "f32_to_ui32_r_minMag",            F32_TO_UI32,         RMINM,  false },
+    { "f32_to_ui32_r_min",               F32_TO_UI32,         RMIN,   false },
+    { "f32_to_ui32_r_max",               F32_TO_UI32,         RMAX,   false },
+    { "f32_to_ui32_r_near_maxMag",       F32_TO_UI32,         RNMAXM, false },
+    { "f32_to_ui64_r_near_even",         F32_TO_UI64,         RNEVEN, false },
+    { "f32_to_ui64_r_minMag",            F32_TO_UI64,         RMINM,  false },
+    { "f32_to_ui64_r_min",               F32_TO_UI64,         RMIN,   false },
+    { "f32_to_ui64_r_max",               F32_TO_UI64,         RMAX,   false },
+    { "f32_to_ui64_r_near_maxMag",       F32_TO_UI64,         RNMAXM, false },
+    { "f32_to_i32_r_near_even",          F32_TO_I32,          RNEVEN, false },
+    { "f32_to_i32_r_minMag",             F32_TO_I32,          RMINM,  false },
+    { "f32_to_i32_r_min",                F32_TO_I32,          RMIN,   false },
+    { "f32_to_i32_r_max",                F32_TO_I32,          RMAX,   false },
+    { "f32_to_i32_r_near_maxMag",        F32_TO_I32,          RNMAXM, false },
+    { "f32_to_i64_r_near_even",          F32_TO_I64,          RNEVEN, false },
+    { "f32_to_i64_r_minMag",             F32_TO_I64,          RMINM,  false },
+    { "f32_to_i64_r_min",                F32_TO_I64,          RMIN,   false },
+    { "f32_to_i64_r_max",                F32_TO_I64,          RMAX,   false },
+    { "f32_to_i64_r_near_maxMag",        F32_TO_I64,          RNMAXM, false },
+    { "f32_to_ui32_rx_near_even",        F32_TO_UI32,         RNEVEN, true  },
+    { "f32_to_ui32_rx_minMag",           F32_TO_UI32,         RMINM,  true  },
+    { "f32_to_ui32_rx_min",              F32_TO_UI32,         RMIN,   true  },
+    { "f32_to_ui32_rx_max",              F32_TO_UI32,         RMAX,   true  },
+    { "f32_to_ui32_rx_near_maxMag",      F32_TO_UI32,         RNMAXM, true  },
+    { "f32_to_ui64_rx_near_even",        F32_TO_UI64,         RNEVEN, true  },
+    { "f32_to_ui64_rx_minMag",           F32_TO_UI64,         RMINM,  true  },
+    { "f32_to_ui64_rx_min",              F32_TO_UI64,         RMIN,   true  },
+    { "f32_to_ui64_rx_max",              F32_TO_UI64,         RMAX,   true  },
+    { "f32_to_ui64_rx_near_maxMag",      F32_TO_UI64,         RNMAXM, true  },
+    { "f32_to_i32_rx_near_even",         F32_TO_I32,          RNEVEN, true  },
+    { "f32_to_i32_rx_minMag",            F32_TO_I32,          RMINM,  true  },
+    { "f32_to_i32_rx_min",               F32_TO_I32,          RMIN,   true  },
+    { "f32_to_i32_rx_max",               F32_TO_I32,          RMAX,   true  },
+    { "f32_to_i32_rx_near_maxMag",       F32_TO_I32,          RNMAXM, true  },
+    { "f32_to_i64_rx_near_even",         F32_TO_I64,          RNEVEN, true  },
+    { "f32_to_i64_rx_minMag",            F32_TO_I64,          RMINM,  true  },
+    { "f32_to_i64_rx_min",               F32_TO_I64,          RMIN,   true  },
+    { "f32_to_i64_rx_max",               F32_TO_I64,          RMAX,   true  },
+    { "f32_to_i64_rx_near_maxMag",       F32_TO_I64,          RNMAXM, true  },
+#ifdef FLOAT16
+    { "f32_to_f16",                      F32_TO_F16,          0,      0     },
+#endif
+#ifdef FLOAT64
+    { "f32_to_f64",                      F32_TO_F64,          0,      0     },
+#endif
+#ifdef EXTFLOAT80
+    { "f32_to_extF80",                   F32_TO_EXTF80,       0,      0     },
+#endif
+#ifdef FLOAT128
+    { "f32_to_f128",                     F32_TO_F128,         0,      0     },
+#endif
+    { "f32_roundToInt_r_near_even",      F32_ROUNDTOINT,      RNEVEN, false },
+    { "f32_roundToInt_r_minMag",         F32_ROUNDTOINT,      RMINM,  false },
+    { "f32_roundToInt_r_min",            F32_ROUNDTOINT,      RMIN,   false },
+    { "f32_roundToInt_r_max",            F32_ROUNDTOINT,      RMAX,   false },
+    { "f32_roundToInt_r_near_maxMag",    F32_ROUNDTOINT,      RNMAXM, false },
+    { "f32_roundToInt_x",                F32_ROUNDTOINT,      0,      true  },
+    { "f32_add",                         F32_ADD,             0,      0     },
+    { "f32_sub",                         F32_SUB,             0,      0     },
+    { "f32_mul",                         F32_MUL,             0,      0     },
+    { "f32_mulAdd",                      F32_MULADD,          0,      0     },
+    { "f32_div",                         F32_DIV,             0,      0     },
+    { "f32_rem",                         F32_REM,             0,      0     },
+    { "f32_sqrt",                        F32_SQRT,            0,      0     },
+    { "f32_eq",                          F32_EQ,              0,      0     },
+    { "f32_le",                          F32_LE,              0,      0     },
+    { "f32_lt",                          F32_LT,              0,      0     },
+    { "f32_eq_signaling",                F32_EQ_SIGNALING,    0,      0     },
+    { "f32_le_quiet",                    F32_LE_QUIET,        0,      0     },
+    { "f32_lt_quiet",                    F32_LT_QUIET,        0,      0     },
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT64
+    { "f64_to_ui32_r_near_even",         F64_TO_UI32,         RNEVEN, false },
+    { "f64_to_ui32_r_minMag",            F64_TO_UI32,         RMINM,  false },
+    { "f64_to_ui32_r_min",               F64_TO_UI32,         RMIN,   false },
+    { "f64_to_ui32_r_max",               F64_TO_UI32,         RMAX,   false },
+    { "f64_to_ui32_r_near_maxMag",       F64_TO_UI32,         RNMAXM, false },
+    { "f64_to_ui64_r_near_even",         F64_TO_UI64,         RNEVEN, false },
+    { "f64_to_ui64_r_minMag",            F64_TO_UI64,         RMINM,  false },
+    { "f64_to_ui64_r_min",               F64_TO_UI64,         RMIN,   false },
+    { "f64_to_ui64_r_max",               F64_TO_UI64,         RMAX,   false },
+    { "f64_to_ui64_r_near_maxMag",       F64_TO_UI64,         RNMAXM, false },
+    { "f64_to_i32_r_near_even",          F64_TO_I32,          RNEVEN, false },
+    { "f64_to_i32_r_minMag",             F64_TO_I32,          RMINM,  false },
+    { "f64_to_i32_r_min",                F64_TO_I32,          RMIN,   false },
+    { "f64_to_i32_r_max",                F64_TO_I32,          RMAX,   false },
+    { "f64_to_i32_r_near_maxMag",        F64_TO_I32,          RNMAXM, false },
+    { "f64_to_i64_r_near_even",          F64_TO_I64,          RNEVEN, false },
+    { "f64_to_i64_r_minMag",             F64_TO_I64,          RMINM,  false },
+    { "f64_to_i64_r_min",                F64_TO_I64,          RMIN,   false },
+    { "f64_to_i64_r_max",                F64_TO_I64,          RMAX,   false },
+    { "f64_to_i64_r_near_maxMag",        F64_TO_I64,          RNMAXM, false },
+    { "f64_to_ui32_rx_near_even",        F64_TO_UI32,         RNEVEN, true  },
+    { "f64_to_ui32_rx_minMag",           F64_TO_UI32,         RMINM,  true  },
+    { "f64_to_ui32_rx_min",              F64_TO_UI32,         RMIN,   true  },
+    { "f64_to_ui32_rx_max",              F64_TO_UI32,         RMAX,   true  },
+    { "f64_to_ui32_rx_near_maxMag",      F64_TO_UI32,         RNMAXM, true  },
+    { "f64_to_ui64_rx_near_even",        F64_TO_UI64,         RNEVEN, true  },
+    { "f64_to_ui64_rx_minMag",           F64_TO_UI64,         RMINM,  true  },
+    { "f64_to_ui64_rx_min",              F64_TO_UI64,         RMIN,   true  },
+    { "f64_to_ui64_rx_max",              F64_TO_UI64,         RMAX,   true  },
+    { "f64_to_ui64_rx_near_maxMag",      F64_TO_UI64,         RNMAXM, true  },
+    { "f64_to_i32_rx_near_even",         F64_TO_I32,          RNEVEN, true  },
+    { "f64_to_i32_rx_minMag",            F64_TO_I32,          RMINM,  true  },
+    { "f64_to_i32_rx_min",               F64_TO_I32,          RMIN,   true  },
+    { "f64_to_i32_rx_max",               F64_TO_I32,          RMAX,   true  },
+    { "f64_to_i32_rx_near_maxMag",       F64_TO_I32,          RNMAXM, true  },
+    { "f64_to_i64_rx_near_even",         F64_TO_I64,          RNEVEN, true  },
+    { "f64_to_i64_rx_minMag",            F64_TO_I64,          RMINM,  true  },
+    { "f64_to_i64_rx_min",               F64_TO_I64,          RMIN,   true  },
+    { "f64_to_i64_rx_max",               F64_TO_I64,          RMAX,   true  },
+    { "f64_to_i64_rx_near_maxMag",       F64_TO_I64,          RNMAXM, true  },
+#ifdef FLOAT16
+    { "f64_to_f16",                      F64_TO_F16,          0,      0     },
+#endif
+    { "f64_to_f32",                      F64_TO_F32,          0,      0     },
+#ifdef EXTFLOAT80
+    { "f64_to_extF80",                   F64_TO_EXTF80,       0,      0     },
+#endif
+#ifdef FLOAT128
+    { "f64_to_f128",                     F64_TO_F128,         0,      0     },
+#endif
+    { "f64_roundToInt_r_near_even",      F64_ROUNDTOINT,      RNEVEN, false },
+    { "f64_roundToInt_r_minMag",         F64_ROUNDTOINT,      RMINM,  false },
+    { "f64_roundToInt_r_min",            F64_ROUNDTOINT,      RMIN,   false },
+    { "f64_roundToInt_r_max",            F64_ROUNDTOINT,      RMAX,   false },
+    { "f64_roundToInt_r_near_maxMag",    F64_ROUNDTOINT,      RNMAXM, false },
+    { "f64_roundToInt_x",                F64_ROUNDTOINT,      0,      true  },
+    { "f64_add",                         F64_ADD,             0,      0     },
+    { "f64_sub",                         F64_SUB,             0,      0     },
+    { "f64_mul",                         F64_MUL,             0,      0     },
+    { "f64_mulAdd",                      F64_MULADD,          0,      0     },
+    { "f64_div",                         F64_DIV,             0,      0     },
+    { "f64_rem",                         F64_REM,             0,      0     },
+    { "f64_sqrt",                        F64_SQRT,            0,      0     },
+    { "f64_eq",                          F64_EQ,              0,      0     },
+    { "f64_le",                          F64_LE,              0,      0     },
+    { "f64_lt",                          F64_LT,              0,      0     },
+    { "f64_eq_signaling",                F64_EQ_SIGNALING,    0,      0     },
+    { "f64_le_quiet",                    F64_LE_QUIET,        0,      0     },
+    { "f64_lt_quiet",                    F64_LT_QUIET,        0,      0     },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+    { "extF80_to_ui32_r_near_even",      EXTF80_TO_UI32,      RNEVEN, false },
+    { "extF80_to_ui32_r_minMag",         EXTF80_TO_UI32,      RMINM,  false },
+    { "extF80_to_ui32_r_min",            EXTF80_TO_UI32,      RMIN,   false },
+    { "extF80_to_ui32_r_max",            EXTF80_TO_UI32,      RMAX,   false },
+    { "extF80_to_ui32_r_near_maxMag",    EXTF80_TO_UI32,      RNMAXM, false },
+    { "extF80_to_ui64_r_near_even",      EXTF80_TO_UI64,      RNEVEN, false },
+    { "extF80_to_ui64_r_minMag",         EXTF80_TO_UI64,      RMINM,  false },
+    { "extF80_to_ui64_r_min",            EXTF80_TO_UI64,      RMIN,   false },
+    { "extF80_to_ui64_r_max",            EXTF80_TO_UI64,      RMAX,   false },
+    { "extF80_to_ui64_r_near_maxMag",    EXTF80_TO_UI64,      RNMAXM, false },
+    { "extF80_to_i32_r_near_even",       EXTF80_TO_I32,       RNEVEN, false },
+    { "extF80_to_i32_r_minMag",          EXTF80_TO_I32,       RMINM,  false },
+    { "extF80_to_i32_r_min",             EXTF80_TO_I32,       RMIN,   false },
+    { "extF80_to_i32_r_max",             EXTF80_TO_I32,       RMAX,   false },
+    { "extF80_to_i32_r_near_maxMag",     EXTF80_TO_I32,       RNMAXM, false },
+    { "extF80_to_i64_r_near_even",       EXTF80_TO_I64,       RNEVEN, false },
+    { "extF80_to_i64_r_minMag",          EXTF80_TO_I64,       RMINM,  false },
+    { "extF80_to_i64_r_min",             EXTF80_TO_I64,       RMIN,   false },
+    { "extF80_to_i64_r_max",             EXTF80_TO_I64,       RMAX,   false },
+    { "extF80_to_i64_r_near_maxMag",     EXTF80_TO_I64,       RNMAXM, false },
+    { "extF80_to_ui32_rx_near_even",     EXTF80_TO_UI32,      RNEVEN, true  },
+    { "extF80_to_ui32_rx_minMag",        EXTF80_TO_UI32,      RMINM,  true  },
+    { "extF80_to_ui32_rx_min",           EXTF80_TO_UI32,      RMIN,   true  },
+    { "extF80_to_ui32_rx_max",           EXTF80_TO_UI32,      RMAX,   true  },
+    { "extF80_to_ui32_rx_near_maxMag",   EXTF80_TO_UI32,      RNMAXM, true  },
+    { "extF80_to_ui64_rx_near_even",     EXTF80_TO_UI64,      RNEVEN, true  },
+    { "extF80_to_ui64_rx_minMag",        EXTF80_TO_UI64,      RMINM,  true  },
+    { "extF80_to_ui64_rx_min",           EXTF80_TO_UI64,      RMIN,   true  },
+    { "extF80_to_ui64_rx_max",           EXTF80_TO_UI64,      RMAX,   true  },
+    { "extF80_to_ui64_rx_near_maxMag",   EXTF80_TO_UI64,      RNMAXM, true  },
+    { "extF80_to_i32_rx_near_even",      EXTF80_TO_I32,       RNEVEN, true  },
+    { "extF80_to_i32_rx_minMag",         EXTF80_TO_I32,       RMINM,  true  },
+    { "extF80_to_i32_rx_min",            EXTF80_TO_I32,       RMIN,   true  },
+    { "extF80_to_i32_rx_max",            EXTF80_TO_I32,       RMAX,   true  },
+    { "extF80_to_i32_rx_near_maxMag",    EXTF80_TO_I32,       RNMAXM, true  },
+    { "extF80_to_i64_rx_near_even",      EXTF80_TO_I64,       RNEVEN, true  },
+    { "extF80_to_i64_rx_minMag",         EXTF80_TO_I64,       RMINM,  true  },
+    { "extF80_to_i64_rx_min",            EXTF80_TO_I64,       RMIN,   true  },
+    { "extF80_to_i64_rx_max",            EXTF80_TO_I64,       RMAX,   true  },
+    { "extF80_to_i64_rx_near_maxMag",    EXTF80_TO_I64,       RNMAXM, true  },
+#ifdef FLOAT16
+    { "extF80_to_f16",                   EXTF80_TO_F16,       0,      0     },
+#endif
+    { "extF80_to_f32",                   EXTF80_TO_F32,       0,      0     },
+#ifdef FLOAT64
+    { "extF80_to_f64",                   EXTF80_TO_F64,       0,      0     },
+#endif
+#ifdef FLOAT128
+    { "extF80_to_f128",                  EXTF80_TO_F128,      0,      0     },
+#endif
+    { "extF80_roundToInt_r_near_even",   EXTF80_ROUNDTOINT,   RNEVEN, false },
+    { "extF80_roundToInt_r_minMag",      EXTF80_ROUNDTOINT,   RMINM,  false },
+    { "extF80_roundToInt_r_min",         EXTF80_ROUNDTOINT,   RMIN,   false },
+    { "extF80_roundToInt_r_max",         EXTF80_ROUNDTOINT,   RMAX,   false },
+    { "extF80_roundToInt_r_near_maxMag", EXTF80_ROUNDTOINT,   RNMAXM, false },
+    { "extF80_roundToInt_x",             EXTF80_ROUNDTOINT,   0,      true  },
+    { "extF80_add",                      EXTF80_ADD,          0,      0     },
+    { "extF80_sub",                      EXTF80_SUB,          0,      0     },
+    { "extF80_mul",                      EXTF80_MUL,          0,      0     },
+    { "extF80_div",                      EXTF80_DIV,          0,      0     },
+    { "extF80_rem",                      EXTF80_REM,          0,      0     },
+    { "extF80_sqrt",                     EXTF80_SQRT,         0,      0     },
+    { "extF80_eq",                       EXTF80_EQ,           0,      0     },
+    { "extF80_le",                       EXTF80_LE,           0,      0     },
+    { "extF80_lt",                       EXTF80_LT,           0,      0     },
+    { "extF80_eq_signaling",             EXTF80_EQ_SIGNALING, 0,      0     },
+    { "extF80_le_quiet",                 EXTF80_LE_QUIET,     0,      0     },
+    { "extF80_lt_quiet",                 EXTF80_LT_QUIET,     0,      0     },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT128
+    { "f128_to_ui32_r_near_even",        F128_TO_UI32,        RNEVEN, false },
+    { "f128_to_ui32_r_minMag",           F128_TO_UI32,        RMINM,  false },
+    { "f128_to_ui32_r_min",              F128_TO_UI32,        RMIN,   false },
+    { "f128_to_ui32_r_max",              F128_TO_UI32,        RMAX,   false },
+    { "f128_to_ui32_r_near_maxMag",      F128_TO_UI32,        RNMAXM, false },
+    { "f128_to_ui64_r_near_even",        F128_TO_UI64,        RNEVEN, false },
+    { "f128_to_ui64_r_minMag",           F128_TO_UI64,        RMINM,  false },
+    { "f128_to_ui64_r_min",              F128_TO_UI64,        RMIN,   false },
+    { "f128_to_ui64_r_max",              F128_TO_UI64,        RMAX,   false },
+    { "f128_to_ui64_r_near_maxMag",      F128_TO_UI64,        RNMAXM, false },
+    { "f128_to_i32_r_near_even",         F128_TO_I32,         RNEVEN, false },
+    { "f128_to_i32_r_minMag",            F128_TO_I32,         RMINM,  false },
+    { "f128_to_i32_r_min",               F128_TO_I32,         RMIN,   false },
+    { "f128_to_i32_r_max",               F128_TO_I32,         RMAX,   false },
+    { "f128_to_i32_r_near_maxMag",       F128_TO_I32,         RNMAXM, false },
+    { "f128_to_i64_r_near_even",         F128_TO_I64,         RNEVEN, false },
+    { "f128_to_i64_r_minMag",            F128_TO_I64,         RMINM,  false },
+    { "f128_to_i64_r_min",               F128_TO_I64,         RMIN,   false },
+    { "f128_to_i64_r_max",               F128_TO_I64,         RMAX,   false },
+    { "f128_to_i64_r_near_maxMag",       F128_TO_I64,         RNMAXM, false },
+    { "f128_to_ui32_rx_near_even",       F128_TO_UI32,        RNEVEN, true  },
+    { "f128_to_ui32_rx_minMag",          F128_TO_UI32,        RMINM,  true  },
+    { "f128_to_ui32_rx_min",             F128_TO_UI32,        RMIN,   true  },
+    { "f128_to_ui32_rx_max",             F128_TO_UI32,        RMAX,   true  },
+    { "f128_to_ui32_rx_near_maxMag",     F128_TO_UI32,        RNMAXM, true  },
+    { "f128_to_ui64_rx_near_even",       F128_TO_UI64,        RNEVEN, true  },
+    { "f128_to_ui64_rx_minMag",          F128_TO_UI64,        RMINM,  true  },
+    { "f128_to_ui64_rx_min",             F128_TO_UI64,        RMIN,   true  },
+    { "f128_to_ui64_rx_max",             F128_TO_UI64,        RMAX,   true  },
+    { "f128_to_ui64_rx_near_maxMag",     F128_TO_UI64,        RNMAXM, true  },
+    { "f128_to_i32_rx_near_even",        F128_TO_I32,         RNEVEN, true  },
+    { "f128_to_i32_rx_minMag",           F128_TO_I32,         RMINM,  true  },
+    { "f128_to_i32_rx_min",              F128_TO_I32,         RMIN,   true  },
+    { "f128_to_i32_rx_max",              F128_TO_I32,         RMAX,   true  },
+    { "f128_to_i32_rx_near_maxMag",      F128_TO_I32,         RNMAXM, true  },
+    { "f128_to_i64_rx_near_even",        F128_TO_I64,         RNEVEN, true  },
+    { "f128_to_i64_rx_minMag",           F128_TO_I64,         RMINM,  true  },
+    { "f128_to_i64_rx_min",              F128_TO_I64,         RMIN,   true  },
+    { "f128_to_i64_rx_max",              F128_TO_I64,         RMAX,   true  },
+    { "f128_to_i64_rx_near_maxMag",      F128_TO_I64,         RNMAXM, true  },
+#ifdef FLOAT16
+    { "f128_to_f16",                     F128_TO_F16,         0,      0     },
+#endif
+    { "f128_to_f32",                     F128_TO_F32,         0,      0     },
+#ifdef FLOAT64
+    { "f128_to_f64",                     F128_TO_F64,         0,      0     },
+#endif
+#ifdef EXTFLOAT80
+    { "f128_to_extF80",                  F128_TO_EXTF80,      0,      0     },
+#endif
+    { "f128_roundToInt_r_near_even",     F128_ROUNDTOINT,     RNEVEN, false },
+    { "f128_roundToInt_r_minMag",        F128_ROUNDTOINT,     RMINM,  false },
+    { "f128_roundToInt_r_min",           F128_ROUNDTOINT,     RMIN,   false },
+    { "f128_roundToInt_r_max",           F128_ROUNDTOINT,     RMAX,   false },
+    { "f128_roundToInt_r_near_maxMag",   F128_ROUNDTOINT,     RNMAXM, false },
+    { "f128_roundToInt_x",               F128_ROUNDTOINT,     0,      true  },
+    { "f128_add",                        F128_ADD,            0,      0     },
+    { "f128_sub",                        F128_SUB,            0,      0     },
+    { "f128_mul",                        F128_MUL,            0,      0     },
+    { "f128_mulAdd",                     F128_MULADD,         0,      0     },
+    { "f128_div",                        F128_DIV,            0,      0     },
+    { "f128_rem",                        F128_REM,            0,      0     },
+    { "f128_sqrt",                       F128_SQRT,           0,      0     },
+    { "f128_eq",                         F128_EQ,             0,      0     },
+    { "f128_le",                         F128_LE,             0,      0     },
+    { "f128_lt",                         F128_LT,             0,      0     },
+    { "f128_eq_signaling",               F128_EQ_SIGNALING,   0,      0     },
+    { "f128_le_quiet",                   F128_LE_QUIET,       0,      0     },
+    { "f128_lt_quiet",                   F128_LT_QUIET,       0,      0     },
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    { 0, 0, 0, 0 }
+};
+
diff --git a/addins/TestFloat-3e/source/subj-C/subjfloat.c b/addins/TestFloat-3e/source/subj-C/subjfloat.c
new file mode 100644
index 000000000..438d0ea37
--- /dev/null
+++ b/addins/TestFloat-3e/source/subj-C/subjfloat.c
@@ -0,0 +1,856 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <fenv.h>
+#include <math.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "subjfloat_config.h"
+#include "subjfloat.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void subjfloat_setRoundingMode( uint_fast8_t roundingMode )
+{
+
+    fesetround(
+          (roundingMode == softfloat_round_near_even) ? FE_TONEAREST
+        : (roundingMode == softfloat_round_minMag)    ? FE_TOWARDZERO
+        : (roundingMode == softfloat_round_min)       ? FE_DOWNWARD
+        : FE_UPWARD
+    );
+
+}
+
+void subjfloat_setExtF80RoundingPrecision( uint_fast8_t roundingPrecision )
+{
+
+}
+
+uint_fast8_t subjfloat_clearExceptionFlags( void )
+{
+    int subjExceptionFlags;
+    uint_fast8_t exceptionFlags;
+
+    subjExceptionFlags =
+        fetestexcept(
+            FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT
+        );
+    feclearexcept(
+        FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | FE_UNDERFLOW | FE_INEXACT );
+    exceptionFlags = 0;
+    if ( subjExceptionFlags & FE_INVALID ) {
+        exceptionFlags |= softfloat_flag_invalid;
+    }
+    if ( subjExceptionFlags & FE_DIVBYZERO ) {
+        exceptionFlags |= softfloat_flag_infinite;
+    }
+    if ( subjExceptionFlags & FE_OVERFLOW ) {
+        exceptionFlags |= softfloat_flag_overflow;
+    }
+    if ( subjExceptionFlags & FE_UNDERFLOW ) {
+        exceptionFlags |= softfloat_flag_underflow;
+    }
+    if ( subjExceptionFlags & FE_INEXACT ) {
+        exceptionFlags |= softfloat_flag_inexact;
+    }
+    return exceptionFlags;
+
+}
+
+union f32_f { float32_t f32; float f; };
+
+float32_t subj_ui32_to_f32( uint32_t a )
+{
+    union f32_f uZ;
+
+    uZ.f = a;
+    return uZ.f32;
+
+}
+
+float32_t subj_ui64_to_f32( uint64_t a )
+{
+    union f32_f uZ;
+
+    uZ.f = a;
+    return uZ.f32;
+
+}
+
+float32_t subj_i32_to_f32( int32_t a )
+{
+    union f32_f uZ;
+
+    uZ.f = a;
+    return uZ.f32;
+
+}
+
+float32_t subj_i64_to_f32( int64_t a )
+{
+    union f32_f uZ;
+
+    uZ.f = a;
+    return uZ.f32;
+
+}
+
+uint_fast32_t subj_f32_to_ui32_rx_minMag( float32_t a )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    return (uint32_t) uA.f;
+
+}
+
+uint_fast64_t subj_f32_to_ui64_rx_minMag( float32_t a )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    return (uint64_t) uA.f;
+
+}
+
+int_fast32_t subj_f32_to_i32_rx_minMag( float32_t a )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    return (int32_t) uA.f;
+
+}
+
+int_fast64_t subj_f32_to_i64_rx_minMag( float32_t a )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    return (int64_t) uA.f;
+
+}
+
+float32_t subj_f32_add( float32_t a, float32_t b )
+{
+    union f32_f uA, uB, uZ;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    uZ.f = uA.f + uB.f;
+    return uZ.f32;
+
+}
+
+float32_t subj_f32_sub( float32_t a, float32_t b )
+{
+    union f32_f uA, uB, uZ;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    uZ.f = uA.f - uB.f;
+    return uZ.f32;
+
+}
+
+float32_t subj_f32_mul( float32_t a, float32_t b )
+{
+    union f32_f uA, uB, uZ;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    uZ.f = uA.f * uB.f;
+    return uZ.f32;
+
+}
+
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+
+float32_t subj_f32_mulAdd( float32_t a, float32_t b, float32_t c )
+{
+    union f32_f uA, uB, uC, uZ;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    uC.f32 = c;
+    uZ.f = fmaf( uA.f, uB.f, uC.f );
+    return uZ.f32;
+
+}
+
+#endif
+#endif
+
+float32_t subj_f32_div( float32_t a, float32_t b )
+{
+    union f32_f uA, uB, uZ;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    uZ.f = uA.f / uB.f;
+    return uZ.f32;
+
+}
+
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+
+float32_t subj_f32_sqrt( float32_t a )
+{
+    union f32_f uA, uZ;
+
+    uA.f32 = a;
+    uZ.f = sqrtf( uA.f );
+    return uZ.f32;
+
+}
+
+#endif
+#endif
+
+bool subj_f32_eq( float32_t a, float32_t b )
+{
+    union f32_f uA, uB;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    return (uA.f == uB.f);
+
+}
+
+bool subj_f32_le( float32_t a, float32_t b )
+{
+    union f32_f uA, uB;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    return (uA.f <= uB.f);
+
+}
+
+bool subj_f32_lt( float32_t a, float32_t b )
+{
+    union f32_f uA, uB;
+
+    uA.f32 = a;
+    uB.f32 = b;
+    return (uA.f < uB.f);
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT64
+
+union f64_d { float64_t f64; double d; };
+
+float64_t subj_ui32_to_f64( uint32_t a )
+{
+    union f64_d uZ;
+
+    uZ.d = a;
+    return uZ.f64;
+
+}
+
+float64_t subj_ui64_to_f64( uint64_t a )
+{
+    union f64_d uZ;
+
+    uZ.d = a;
+    return uZ.f64;
+
+}
+
+float64_t subj_i32_to_f64( int32_t a )
+{
+    union f64_d uZ;
+
+    uZ.d = a;
+    return uZ.f64;
+
+}
+
+float64_t subj_i64_to_f64( int64_t a )
+{
+    union f64_d uZ;
+
+    uZ.d = a;
+    return uZ.f64;
+
+}
+
+float64_t subj_f32_to_f64( float32_t a )
+{
+    union f32_f uA;
+    union f64_d uZ;
+
+    uA.f32 = a;
+    uZ.d = uA.f;
+    return uZ.f64;
+
+}
+
+uint_fast32_t subj_f64_to_ui32_rx_minMag( float64_t a )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    return (uint32_t) uA.d;
+
+}
+
+uint_fast64_t subj_f64_to_ui64_rx_minMag( float64_t a )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    return (uint64_t) uA.d;
+
+}
+
+int_fast32_t subj_f64_to_i32_rx_minMag( float64_t a )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    return (int32_t) uA.d;
+
+}
+
+int_fast64_t subj_f64_to_i64_rx_minMag( float64_t a )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    return (int64_t) uA.d;
+
+}
+
+float32_t subj_f64_to_f32( float64_t a )
+{
+    union f64_d uA;
+    union f32_f uZ;
+
+    uA.f64 = a;
+    uZ.f = uA.d;
+    return uZ.f32;
+
+}
+
+float64_t subj_f64_add( float64_t a, float64_t b )
+{
+    union f64_d uA, uB, uZ;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    uZ.d = uA.d + uB.d;
+    return uZ.f64;
+
+}
+
+float64_t subj_f64_sub( float64_t a, float64_t b )
+{
+    union f64_d uA, uB, uZ;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    uZ.d = uA.d - uB.d;
+    return uZ.f64;
+
+}
+
+float64_t subj_f64_mul( float64_t a, float64_t b )
+{
+    union f64_d uA, uB, uZ;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    uZ.d = uA.d * uB.d;
+    return uZ.f64;
+
+}
+
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+
+float64_t subj_f64_mulAdd( float64_t a, float64_t b, float64_t c )
+{
+    union f64_d uA, uB, uC, uZ;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    uC.f64 = c;
+    uZ.d = fma( uA.d, uB.d, uC.d );
+    return uZ.f64;
+
+}
+
+#endif
+#endif
+
+float64_t subj_f64_div( float64_t a, float64_t b )
+{
+    union f64_d uA, uB, uZ;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    uZ.d = uA.d / uB.d;
+    return uZ.f64;
+
+}
+
+float64_t subj_f64_sqrt( float64_t a )
+{
+    union f64_d uA, uZ;
+
+    uA.f64 = a;
+    uZ.d = sqrt( uA.d );
+    return uZ.f64;
+
+}
+
+bool subj_f64_eq( float64_t a, float64_t b )
+{
+    union f64_d uA, uB;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    return (uA.d == uB.d);
+
+}
+
+bool subj_f64_le( float64_t a, float64_t b )
+{
+    union f64_d uA, uB;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    return (uA.d <= uB.d);
+
+}
+
+bool subj_f64_lt( float64_t a, float64_t b )
+{
+    union f64_d uA, uB;
+
+    uA.f64 = a;
+    uB.f64 = b;
+    return (uA.d < uB.d);
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#if defined EXTFLOAT80 && defined LONG_DOUBLE_IS_EXTFLOAT80
+
+void subj_ui32_to_extF80M( uint32_t a, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_ui64_to_extF80M( uint64_t a, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_i32_to_extF80M( int32_t a, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_i64_to_extF80M( int64_t a, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_f32_to_extF80M( float32_t a, extFloat80_t *zPtr )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    *((long double *) zPtr) = uA.f;
+
+}
+
+#ifdef FLOAT64
+
+void subj_f64_to_extF80M( float64_t a, extFloat80_t *zPtr )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    *((long double *) zPtr) = uA.d;
+
+}
+
+#endif
+
+uint_fast32_t subj_extF80M_to_ui32_rx_minMag( const extFloat80_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+uint_fast64_t subj_extF80M_to_ui64_rx_minMag( const extFloat80_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+int_fast32_t subj_extF80M_to_i32_rx_minMag( const extFloat80_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+int_fast64_t subj_extF80M_to_i64_rx_minMag( const extFloat80_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+float32_t subj_extF80M_to_f32( const extFloat80_t *aPtr )
+{
+    union f32_f uZ;
+
+    uZ.f = *((const long double *) aPtr);
+    return uZ.f32;
+
+}
+
+#ifdef FLOAT64
+
+float64_t subj_extF80M_to_f64( const extFloat80_t *aPtr )
+{
+    union f64_d uZ;
+
+    uZ.d = *((const long double *) aPtr);
+    return uZ.f64;
+
+}
+
+#endif
+
+void
+ subj_extF80M_add(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) + *((const long double *) bPtr);
+
+}
+
+void
+ subj_extF80M_sub(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) - *((const long double *) bPtr);
+
+}
+
+void
+ subj_extF80M_mul(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) * *((const long double *) bPtr);
+
+}
+
+void
+ subj_extF80M_div(
+     const extFloat80_t *aPtr, const extFloat80_t *bPtr, extFloat80_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) / *((const long double *) bPtr);
+
+}
+
+bool subj_extF80M_eq( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) == *((const long double *) bPtr));
+
+}
+
+bool subj_extF80M_le( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) <= *((const long double *) bPtr));
+
+}
+
+bool subj_extF80M_lt( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) < *((const long double *) bPtr));
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#if defined FLOAT128 && defined LONG_DOUBLE_IS_FLOAT128
+
+void subj_ui32_to_f128M( uint32_t a, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_ui64_to_f128M( uint64_t a, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_i32_to_f128M( int32_t a, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_i64_to_f128M( int64_t a, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) = a;
+
+}
+
+void subj_f32_to_f128M( float32_t a, float128_t *zPtr )
+{
+    union f32_f uA;
+
+    uA.f32 = a;
+    *((long double *) zPtr) = uA.f;
+
+}
+
+#ifdef FLOAT64
+
+void subj_f64_to_f128M( float64_t a, float128_t *zPtr )
+{
+    union f64_d uA;
+
+    uA.f64 = a;
+    *((long double *) zPtr) = uA.d;
+
+}
+
+#endif
+
+uint_fast32_t subj_f128M_to_ui32_rx_minMag( const float128_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+uint_fast64_t subj_f128M_to_ui64_rx_minMag( const float128_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+int_fast32_t subj_f128M_to_i32_rx_minMag( const float128_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+int_fast64_t subj_f128M_to_i64_rx_minMag( const float128_t *aPtr )
+{
+
+    return *((const long double *) aPtr);
+
+}
+
+float32_t subj_f128M_to_f32( const float128_t *aPtr )
+{
+    union f32_f uZ;
+
+    uZ.f = *((const long double *) aPtr);
+    return uZ.f32;
+
+}
+
+#ifdef FLOAT64
+
+float64_t subj_f128M_to_f64( const float128_t *aPtr )
+{
+    union f64_d uZ;
+
+    uZ.d = *((const long double *) aPtr);
+    return uZ.f64;
+
+}
+
+#endif
+
+void
+ subj_f128M_add(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) + *((const long double *) bPtr);
+
+}
+
+void
+ subj_f128M_sub(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) - *((const long double *) bPtr);
+
+}
+
+void
+ subj_f128M_mul(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) * *((const long double *) bPtr);
+
+}
+
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+
+void
+ subj_f128M_mulAdd(
+     const float128_t *aPtr,
+     const float128_t *bPtr,
+     const float128_t *cPtr,
+     float128_t *zPtr
+ )
+{
+
+    *((long double *) zPtr) =
+        fmal(
+            *((const long double *) aPtr),
+            *((const long double *) bPtr),
+            *((const long double *) cPtr)
+        );
+
+}
+
+#endif
+#endif
+
+void
+ subj_f128M_div(
+     const float128_t *aPtr, const float128_t *bPtr, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) =
+        *((const long double *) aPtr) / *((const long double *) bPtr);
+
+}
+
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+
+void subj_f128M_sqrt( const float128_t *aPtr, float128_t *zPtr )
+{
+
+    *((long double *) zPtr) = sqrtl( *((const long double *) aPtr) );
+
+}
+
+#endif
+#endif
+
+bool subj_f128M_eq( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) == *((const long double *) bPtr));
+
+}
+
+bool subj_f128M_le( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) <= *((const long double *) bPtr));
+
+}
+
+bool subj_f128M_lt( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    return (*((const long double *) aPtr) < *((const long double *) bPtr));
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/subj-C/subjfloat_config.h b/addins/TestFloat-3e/source/subj-C/subjfloat_config.h
new file mode 100644
index 000000000..01387e6d1
--- /dev/null
+++ b/addins/TestFloat-3e/source/subj-C/subjfloat_config.h
@@ -0,0 +1,133 @@
+
+/*----------------------------------------------------------------------------
+| The following macros are defined to indicate all the subject functions that
+| exist.
+*----------------------------------------------------------------------------*/
+
+#define SUBJ_UI32_TO_F32
+#define SUBJ_UI64_TO_F32
+#define SUBJ_I32_TO_F32
+#define SUBJ_I64_TO_F32
+
+#define SUBJ_F32_TO_UI32_RX_MINMAG
+#define SUBJ_F32_TO_UI64_RX_MINMAG
+#define SUBJ_F32_TO_I32_RX_MINMAG
+#define SUBJ_F32_TO_I64_RX_MINMAG
+#define SUBJ_F32_ADD
+#define SUBJ_F32_SUB
+#define SUBJ_F32_MUL
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+#define SUBJ_F32_MULADD
+#endif
+#endif
+#define SUBJ_F32_DIV
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+#define SUBJ_F32_SQRT
+#endif
+#endif
+#define SUBJ_F32_EQ
+#define SUBJ_F32_LE
+#define SUBJ_F32_LT
+
+#ifdef FLOAT64
+
+#define SUBJ_UI32_TO_F64
+#define SUBJ_UI64_TO_F64
+#define SUBJ_I32_TO_F64
+#define SUBJ_I64_TO_F64
+
+#define SUBJ_F32_TO_F64
+
+#define SUBJ_F64_TO_UI32_RX_MINMAG
+#define SUBJ_F64_TO_UI64_RX_MINMAG
+#define SUBJ_F64_TO_I32_RX_MINMAG
+#define SUBJ_F64_TO_I64_RX_MINMAG
+#define SUBJ_F64_TO_F32
+#define SUBJ_F64_ADD
+#define SUBJ_F64_SUB
+#define SUBJ_F64_MUL
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+#define SUBJ_F64_MULADD
+#endif
+#endif
+#define SUBJ_F64_DIV
+#define SUBJ_F64_SQRT
+#define SUBJ_F64_EQ
+#define SUBJ_F64_LE
+#define SUBJ_F64_LT
+
+#endif
+
+#if defined EXTFLOAT80 && defined LONG_DOUBLE_IS_EXTFLOAT80
+
+#define SUBJ_UI32_TO_EXTF80
+#define SUBJ_UI64_TO_EXTF80
+#define SUBJ_I32_TO_EXTF80
+#define SUBJ_I64_TO_EXTF80
+
+#define SUBJ_F32_TO_EXTF80
+#ifdef FLOAT64
+#define SUBJ_F64_TO_EXTF80
+#endif
+
+#define SUBJ_EXTF80_TO_UI32_RX_MINMAG
+#define SUBJ_EXTF80_TO_UI64_RX_MINMAG
+#define SUBJ_EXTF80_TO_I32_RX_MINMAG
+#define SUBJ_EXTF80_TO_I64_RX_MINMAG
+#define SUBJ_EXTF80_TO_F32
+#ifdef FLOAT64
+#define SUBJ_EXTF80_TO_F64
+#endif
+#define SUBJ_EXTF80_ADD
+#define SUBJ_EXTF80_SUB
+#define SUBJ_EXTF80_MUL
+#define SUBJ_EXTF80_DIV
+#define SUBJ_EXTF80_EQ
+#define SUBJ_EXTF80_LE
+#define SUBJ_EXTF80_LT
+
+#endif
+
+#if defined FLOAT128 && defined LONG_DOUBLE_IS_FLOAT128
+
+#define SUBJ_UI32_TO_F128
+#define SUBJ_UI64_TO_F128
+#define SUBJ_I32_TO_F128
+#define SUBJ_I64_TO_F128
+
+#define SUBJ_F32_TO_F128
+#ifdef FLOAT64
+#define SUBJ_F64_TO_F128
+#endif
+
+#define SUBJ_F128_TO_UI32_RX_MINMAG
+#define SUBJ_F128_TO_UI64_RX_MINMAG
+#define SUBJ_F128_TO_I32_RX_MINMAG
+#define SUBJ_F128_TO_I64_RX_MINMAG
+#define SUBJ_F128_TO_F32
+#ifdef FLOAT64
+#define SUBJ_F128_TO_F64
+#endif
+#define SUBJ_F128_ADD
+#define SUBJ_F128_SUB
+#define SUBJ_F128_MUL
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+#define SUBJ_F128_MULADD
+#endif
+#endif
+#define SUBJ_F128_DIV
+#ifdef __STDC_VERSION__
+#if 199901L <= __STDC_VERSION__
+#define SUBJ_F128_SQRT
+#endif
+#endif
+#define SUBJ_F128_EQ
+#define SUBJ_F128_LE
+#define SUBJ_F128_LT
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/subjfloat.h b/addins/TestFloat-3e/source/subjfloat.h
new file mode 100644
index 000000000..43076deee
--- /dev/null
+++ b/addins/TestFloat-3e/source/subjfloat.h
@@ -0,0 +1,516 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+extern void (*const subjfloat_functions[])();
+
+void subjfloat_setRoundingMode( uint_fast8_t );
+void subjfloat_setExtF80RoundingPrecision( uint_fast8_t );
+uint_fast8_t subjfloat_clearExceptionFlags( void );
+
+/*----------------------------------------------------------------------------
+| Subject function declarations.  (Many of these functions may not exist.)
+| WARNING:
+| This file should not normally be modified.  Use "subjfloat_config.h" to
+| specify which of these functions actually exist.
+*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT16
+float16_t subj_ui32_to_f16( uint32_t );
+#endif
+float32_t subj_ui32_to_f32( uint32_t );
+#ifdef FLOAT64
+float64_t subj_ui32_to_f64( uint32_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_ui32_to_extF80M( uint32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_ui32_to_f128M( uint32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t subj_ui64_to_f16( uint64_t );
+#endif
+float32_t subj_ui64_to_f32( uint64_t );
+#ifdef FLOAT64
+float64_t subj_ui64_to_f64( uint64_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_ui64_to_extF80M( uint64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_ui64_to_f128M( uint64_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t subj_i32_to_f16( int32_t );
+#endif
+float32_t subj_i32_to_f32( int32_t );
+#ifdef FLOAT64
+float64_t subj_i32_to_f64( int32_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_i32_to_extF80M( int32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_i32_to_f128M( int32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+float16_t subj_i64_to_f16( int64_t );
+#endif
+float32_t subj_i64_to_f32( int64_t );
+#ifdef FLOAT64
+float64_t subj_i64_to_f64( int64_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_i64_to_extF80M( int64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_i64_to_f128M( int64_t, float128_t * );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT16
+
+uint_fast32_t subj_f16_to_ui32_r_near_even( float16_t );
+uint_fast32_t subj_f16_to_ui32_r_minMag( float16_t );
+uint_fast32_t subj_f16_to_ui32_r_min( float16_t );
+uint_fast32_t subj_f16_to_ui32_r_max( float16_t );
+uint_fast32_t subj_f16_to_ui32_r_near_maxMag( float16_t );
+uint_fast64_t subj_f16_to_ui64_r_near_even( float16_t );
+uint_fast64_t subj_f16_to_ui64_r_minMag( float16_t );
+uint_fast64_t subj_f16_to_ui64_r_min( float16_t );
+uint_fast64_t subj_f16_to_ui64_r_max( float16_t );
+uint_fast64_t subj_f16_to_ui64_r_near_maxMag( float16_t );
+int_fast32_t subj_f16_to_i32_r_near_even( float16_t );
+int_fast32_t subj_f16_to_i32_r_minMag( float16_t );
+int_fast32_t subj_f16_to_i32_r_min( float16_t );
+int_fast32_t subj_f16_to_i32_r_max( float16_t );
+int_fast32_t subj_f16_to_i32_r_near_maxMag( float16_t );
+int_fast64_t subj_f16_to_i64_r_near_even( float16_t );
+int_fast64_t subj_f16_to_i64_r_minMag( float16_t );
+int_fast64_t subj_f16_to_i64_r_min( float16_t );
+int_fast64_t subj_f16_to_i64_r_max( float16_t );
+int_fast64_t subj_f16_to_i64_r_near_maxMag( float16_t );
+
+uint_fast32_t subj_f16_to_ui32_rx_near_even( float16_t );
+uint_fast32_t subj_f16_to_ui32_rx_minMag( float16_t );
+uint_fast32_t subj_f16_to_ui32_rx_min( float16_t );
+uint_fast32_t subj_f16_to_ui32_rx_max( float16_t );
+uint_fast32_t subj_f16_to_ui32_rx_near_maxMag( float16_t );
+uint_fast64_t subj_f16_to_ui64_rx_near_even( float16_t );
+uint_fast64_t subj_f16_to_ui64_rx_minMag( float16_t );
+uint_fast64_t subj_f16_to_ui64_rx_min( float16_t );
+uint_fast64_t subj_f16_to_ui64_rx_max( float16_t );
+uint_fast64_t subj_f16_to_ui64_rx_near_maxMag( float16_t );
+int_fast32_t subj_f16_to_i32_rx_near_even( float16_t );
+int_fast32_t subj_f16_to_i32_rx_minMag( float16_t );
+int_fast32_t subj_f16_to_i32_rx_min( float16_t );
+int_fast32_t subj_f16_to_i32_rx_max( float16_t );
+int_fast32_t subj_f16_to_i32_rx_near_maxMag( float16_t );
+int_fast64_t subj_f16_to_i64_rx_near_even( float16_t );
+int_fast64_t subj_f16_to_i64_rx_minMag( float16_t );
+int_fast64_t subj_f16_to_i64_rx_min( float16_t );
+int_fast64_t subj_f16_to_i64_rx_max( float16_t );
+int_fast64_t subj_f16_to_i64_rx_near_maxMag( float16_t );
+
+float32_t subj_f16_to_f32( float16_t );
+#ifdef FLOAT64
+float64_t subj_f16_to_f64( float16_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_f16_to_extF80M( float16_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_f16_to_f128M( float16_t, float128_t * );
+#endif
+
+float16_t subj_f16_roundToInt_r_near_even( float16_t );
+float16_t subj_f16_roundToInt_r_minMag( float16_t );
+float16_t subj_f16_roundToInt_r_min( float16_t );
+float16_t subj_f16_roundToInt_r_max( float16_t );
+float16_t subj_f16_roundToInt_r_near_maxMag( float16_t );
+float16_t subj_f16_roundToInt_x( float16_t );
+float16_t subj_f16_add( float16_t, float16_t );
+float16_t subj_f16_sub( float16_t, float16_t );
+float16_t subj_f16_mul( float16_t, float16_t );
+float16_t subj_f16_mulAdd( float16_t, float16_t, float16_t );
+float16_t subj_f16_div( float16_t, float16_t );
+float16_t subj_f16_rem( float16_t, float16_t );
+float16_t subj_f16_sqrt( float16_t );
+bool subj_f16_eq( float16_t, float16_t );
+bool subj_f16_le( float16_t, float16_t );
+bool subj_f16_lt( float16_t, float16_t );
+bool subj_f16_eq_signaling( float16_t, float16_t );
+bool subj_f16_le_quiet( float16_t, float16_t );
+bool subj_f16_lt_quiet( float16_t, float16_t );
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+uint_fast32_t subj_f32_to_ui32_r_near_even( float32_t );
+uint_fast32_t subj_f32_to_ui32_r_minMag( float32_t );
+uint_fast32_t subj_f32_to_ui32_r_min( float32_t );
+uint_fast32_t subj_f32_to_ui32_r_max( float32_t );
+uint_fast32_t subj_f32_to_ui32_r_near_maxMag( float32_t );
+uint_fast64_t subj_f32_to_ui64_r_near_even( float32_t );
+uint_fast64_t subj_f32_to_ui64_r_minMag( float32_t );
+uint_fast64_t subj_f32_to_ui64_r_min( float32_t );
+uint_fast64_t subj_f32_to_ui64_r_max( float32_t );
+uint_fast64_t subj_f32_to_ui64_r_near_maxMag( float32_t );
+int_fast32_t subj_f32_to_i32_r_near_even( float32_t );
+int_fast32_t subj_f32_to_i32_r_minMag( float32_t );
+int_fast32_t subj_f32_to_i32_r_min( float32_t );
+int_fast32_t subj_f32_to_i32_r_max( float32_t );
+int_fast32_t subj_f32_to_i32_r_near_maxMag( float32_t );
+int_fast64_t subj_f32_to_i64_r_near_even( float32_t );
+int_fast64_t subj_f32_to_i64_r_minMag( float32_t );
+int_fast64_t subj_f32_to_i64_r_min( float32_t );
+int_fast64_t subj_f32_to_i64_r_max( float32_t );
+int_fast64_t subj_f32_to_i64_r_near_maxMag( float32_t );
+
+uint_fast32_t subj_f32_to_ui32_rx_near_even( float32_t );
+uint_fast32_t subj_f32_to_ui32_rx_minMag( float32_t );
+uint_fast32_t subj_f32_to_ui32_rx_min( float32_t );
+uint_fast32_t subj_f32_to_ui32_rx_max( float32_t );
+uint_fast32_t subj_f32_to_ui32_rx_near_maxMag( float32_t );
+uint_fast64_t subj_f32_to_ui64_rx_near_even( float32_t );
+uint_fast64_t subj_f32_to_ui64_rx_minMag( float32_t );
+uint_fast64_t subj_f32_to_ui64_rx_min( float32_t );
+uint_fast64_t subj_f32_to_ui64_rx_max( float32_t );
+uint_fast64_t subj_f32_to_ui64_rx_near_maxMag( float32_t );
+int_fast32_t subj_f32_to_i32_rx_near_even( float32_t );
+int_fast32_t subj_f32_to_i32_rx_minMag( float32_t );
+int_fast32_t subj_f32_to_i32_rx_min( float32_t );
+int_fast32_t subj_f32_to_i32_rx_max( float32_t );
+int_fast32_t subj_f32_to_i32_rx_near_maxMag( float32_t );
+int_fast64_t subj_f32_to_i64_rx_near_even( float32_t );
+int_fast64_t subj_f32_to_i64_rx_minMag( float32_t );
+int_fast64_t subj_f32_to_i64_rx_min( float32_t );
+int_fast64_t subj_f32_to_i64_rx_max( float32_t );
+int_fast64_t subj_f32_to_i64_rx_near_maxMag( float32_t );
+
+#ifdef FLOAT16
+float16_t subj_f32_to_f16( float32_t );
+#endif
+#ifdef FLOAT64
+float64_t subj_f32_to_f64( float32_t );
+#endif
+#ifdef EXTFLOAT80
+void subj_f32_to_extF80M( float32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_f32_to_f128M( float32_t, float128_t * );
+#endif
+
+float32_t subj_f32_roundToInt_r_near_even( float32_t );
+float32_t subj_f32_roundToInt_r_minMag( float32_t );
+float32_t subj_f32_roundToInt_r_min( float32_t );
+float32_t subj_f32_roundToInt_r_max( float32_t );
+float32_t subj_f32_roundToInt_r_near_maxMag( float32_t );
+float32_t subj_f32_roundToInt_x( float32_t );
+float32_t subj_f32_add( float32_t, float32_t );
+float32_t subj_f32_sub( float32_t, float32_t );
+float32_t subj_f32_mul( float32_t, float32_t );
+float32_t subj_f32_mulAdd( float32_t, float32_t, float32_t );
+float32_t subj_f32_div( float32_t, float32_t );
+float32_t subj_f32_rem( float32_t, float32_t );
+float32_t subj_f32_sqrt( float32_t );
+bool subj_f32_eq( float32_t, float32_t );
+bool subj_f32_le( float32_t, float32_t );
+bool subj_f32_lt( float32_t, float32_t );
+bool subj_f32_eq_signaling( float32_t, float32_t );
+bool subj_f32_le_quiet( float32_t, float32_t );
+bool subj_f32_lt_quiet( float32_t, float32_t );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT64
+
+uint_fast32_t subj_f64_to_ui32_r_near_even( float64_t );
+uint_fast32_t subj_f64_to_ui32_r_minMag( float64_t );
+uint_fast32_t subj_f64_to_ui32_r_min( float64_t );
+uint_fast32_t subj_f64_to_ui32_r_max( float64_t );
+uint_fast32_t subj_f64_to_ui32_r_near_maxMag( float64_t );
+uint_fast64_t subj_f64_to_ui64_r_near_even( float64_t );
+uint_fast64_t subj_f64_to_ui64_r_minMag( float64_t );
+uint_fast64_t subj_f64_to_ui64_r_min( float64_t );
+uint_fast64_t subj_f64_to_ui64_r_max( float64_t );
+uint_fast64_t subj_f64_to_ui64_r_near_maxMag( float64_t );
+int_fast32_t subj_f64_to_i32_r_near_even( float64_t );
+int_fast32_t subj_f64_to_i32_r_minMag( float64_t );
+int_fast32_t subj_f64_to_i32_r_min( float64_t );
+int_fast32_t subj_f64_to_i32_r_max( float64_t );
+int_fast32_t subj_f64_to_i32_r_near_maxMag( float64_t );
+int_fast64_t subj_f64_to_i64_r_near_even( float64_t );
+int_fast64_t subj_f64_to_i64_r_minMag( float64_t );
+int_fast64_t subj_f64_to_i64_r_min( float64_t );
+int_fast64_t subj_f64_to_i64_r_max( float64_t );
+int_fast64_t subj_f64_to_i64_r_near_maxMag( float64_t );
+
+uint_fast32_t subj_f64_to_ui32_rx_near_even( float64_t );
+uint_fast32_t subj_f64_to_ui32_rx_minMag( float64_t );
+uint_fast32_t subj_f64_to_ui32_rx_min( float64_t );
+uint_fast32_t subj_f64_to_ui32_rx_max( float64_t );
+uint_fast32_t subj_f64_to_ui32_rx_near_maxMag( float64_t );
+uint_fast64_t subj_f64_to_ui64_rx_near_even( float64_t );
+uint_fast64_t subj_f64_to_ui64_rx_minMag( float64_t );
+uint_fast64_t subj_f64_to_ui64_rx_min( float64_t );
+uint_fast64_t subj_f64_to_ui64_rx_max( float64_t );
+uint_fast64_t subj_f64_to_ui64_rx_near_maxMag( float64_t );
+int_fast32_t subj_f64_to_i32_rx_near_even( float64_t );
+int_fast32_t subj_f64_to_i32_rx_minMag( float64_t );
+int_fast32_t subj_f64_to_i32_rx_min( float64_t );
+int_fast32_t subj_f64_to_i32_rx_max( float64_t );
+int_fast32_t subj_f64_to_i32_rx_near_maxMag( float64_t );
+int_fast64_t subj_f64_to_i64_rx_near_even( float64_t );
+int_fast64_t subj_f64_to_i64_rx_minMag( float64_t );
+int_fast64_t subj_f64_to_i64_rx_min( float64_t );
+int_fast64_t subj_f64_to_i64_rx_max( float64_t );
+int_fast64_t subj_f64_to_i64_rx_near_maxMag( float64_t );
+
+#ifdef FLOAT16
+float16_t subj_f64_to_f16( float64_t );
+#endif
+float32_t subj_f64_to_f32( float64_t );
+#ifdef EXTFLOAT80
+void subj_f64_to_extF80M( float64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+void subj_f64_to_f128M( float64_t, float128_t * );
+#endif
+
+float64_t subj_f64_roundToInt_r_near_even( float64_t );
+float64_t subj_f64_roundToInt_r_minMag( float64_t );
+float64_t subj_f64_roundToInt_r_min( float64_t );
+float64_t subj_f64_roundToInt_r_max( float64_t );
+float64_t subj_f64_roundToInt_r_near_maxMag( float64_t );
+float64_t subj_f64_roundToInt_x( float64_t );
+float64_t subj_f64_add( float64_t, float64_t );
+float64_t subj_f64_sub( float64_t, float64_t );
+float64_t subj_f64_mul( float64_t, float64_t );
+float64_t subj_f64_mulAdd( float64_t, float64_t, float64_t );
+float64_t subj_f64_div( float64_t, float64_t );
+float64_t subj_f64_rem( float64_t, float64_t );
+float64_t subj_f64_sqrt( float64_t );
+bool subj_f64_eq( float64_t, float64_t );
+bool subj_f64_le( float64_t, float64_t );
+bool subj_f64_lt( float64_t, float64_t );
+bool subj_f64_eq_signaling( float64_t, float64_t );
+bool subj_f64_le_quiet( float64_t, float64_t );
+bool subj_f64_lt_quiet( float64_t, float64_t );
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+
+uint_fast32_t subj_extF80M_to_ui32_r_near_even( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_r_minMag( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_r_min( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_r_max( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_r_near_maxMag( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_r_near_even( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_r_minMag( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_r_min( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_r_max( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_r_near_maxMag( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_r_near_even( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_r_minMag( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_r_min( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_r_max( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_r_near_maxMag( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_r_near_even( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_r_minMag( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_r_min( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_r_max( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_r_near_maxMag( const extFloat80_t * );
+
+uint_fast32_t subj_extF80M_to_ui32_rx_near_even( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_rx_minMag( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_rx_min( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_rx_max( const extFloat80_t * );
+uint_fast32_t subj_extF80M_to_ui32_rx_near_maxMag( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_rx_near_even( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_rx_minMag( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_rx_min( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_rx_max( const extFloat80_t * );
+uint_fast64_t subj_extF80M_to_ui64_rx_near_maxMag( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_rx_near_even( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_rx_minMag( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_rx_min( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_rx_max( const extFloat80_t * );
+int_fast32_t subj_extF80M_to_i32_rx_near_maxMag( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_rx_near_even( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_rx_minMag( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_rx_min( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_rx_max( const extFloat80_t * );
+int_fast64_t subj_extF80M_to_i64_rx_near_maxMag( const extFloat80_t * );
+
+#ifdef FLOAT16
+float16_t subj_extF80M_to_f16( const extFloat80_t * );
+#endif
+float32_t subj_extF80M_to_f32( const extFloat80_t * );
+#ifdef FLOAT64
+float64_t subj_extF80M_to_f64( const extFloat80_t * );
+#endif
+#ifdef EXTFLOAT80
+void subj_extF80M_to_f128M( const extFloat80_t *, float128_t * );
+#endif
+
+void
+ subj_extF80M_roundToInt_r_near_even( const extFloat80_t *, extFloat80_t * );
+void subj_extF80M_roundToInt_r_minMag( const extFloat80_t *, extFloat80_t * );
+void subj_extF80M_roundToInt_r_min( const extFloat80_t *, extFloat80_t * );
+void subj_extF80M_roundToInt_r_max( const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_roundToInt_r_near_maxMag( const extFloat80_t *, extFloat80_t * );
+void subj_extF80M_roundToInt_x( const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_add(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_sub(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_mul(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_div(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void
+ subj_extF80M_rem(
+     const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+void subj_extF80M_sqrt( const extFloat80_t *, extFloat80_t * );
+bool subj_extF80M_eq( const extFloat80_t *, const extFloat80_t * );
+bool subj_extF80M_le( const extFloat80_t *, const extFloat80_t * );
+bool subj_extF80M_lt( const extFloat80_t *, const extFloat80_t * );
+bool subj_extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * );
+bool subj_extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * );
+bool subj_extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * );
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT128
+
+uint_fast32_t subj_f128M_to_ui32_r_near_even( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_r_minMag( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_r_min( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_r_max( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_r_near_maxMag( extFloat80_t * );
+uint_fast64_t subj_f128M_to_ui64_r_near_even( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_r_minMag( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_r_min( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_r_max( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_r_near_maxMag( extFloat80_t * );
+int_fast32_t subj_f128M_to_i32_r_near_even( const float128_t * );
+int_fast32_t subj_f128M_to_i32_r_minMag( const float128_t * );
+int_fast32_t subj_f128M_to_i32_r_min( const float128_t * );
+int_fast32_t subj_f128M_to_i32_r_max( const float128_t * );
+int_fast32_t subj_f128M_to_i32_r_near_maxMag( extFloat80_t * );
+int_fast64_t subj_f128M_to_i64_r_near_even( const float128_t * );
+int_fast64_t subj_f128M_to_i64_r_minMag( const float128_t * );
+int_fast64_t subj_f128M_to_i64_r_min( const float128_t * );
+int_fast64_t subj_f128M_to_i64_r_max( const float128_t * );
+int_fast64_t subj_f128M_to_i64_r_near_maxMag( extFloat80_t * );
+
+uint_fast32_t subj_f128M_to_ui32_rx_near_even( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_rx_minMag( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_rx_min( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_rx_max( const float128_t * );
+uint_fast32_t subj_f128M_to_ui32_rx_near_maxMag( extFloat80_t * );
+uint_fast64_t subj_f128M_to_ui64_rx_near_even( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_rx_minMag( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_rx_min( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_rx_max( const float128_t * );
+uint_fast64_t subj_f128M_to_ui64_rx_near_maxMag( extFloat80_t * );
+int_fast32_t subj_f128M_to_i32_rx_near_even( const float128_t * );
+int_fast32_t subj_f128M_to_i32_rx_minMag( const float128_t * );
+int_fast32_t subj_f128M_to_i32_rx_min( const float128_t * );
+int_fast32_t subj_f128M_to_i32_rx_max( const float128_t * );
+int_fast32_t subj_f128M_to_i32_rx_near_maxMag( extFloat80_t * );
+int_fast64_t subj_f128M_to_i64_rx_near_even( const float128_t * );
+int_fast64_t subj_f128M_to_i64_rx_minMag( const float128_t * );
+int_fast64_t subj_f128M_to_i64_rx_min( const float128_t * );
+int_fast64_t subj_f128M_to_i64_rx_max( const float128_t * );
+int_fast64_t subj_f128M_to_i64_rx_near_maxMag( extFloat80_t * );
+
+#ifdef FLOAT16
+float16_t subj_f128M_to_f16( const float128_t * );
+#endif
+float32_t subj_f128M_to_f32( const float128_t * );
+#ifdef FLOAT64
+float64_t subj_f128M_to_f64( const float128_t * );
+#endif
+#ifdef FLOAT128
+void subj_f128M_to_extF80M( const float128_t *, extFloat80_t * );
+#endif
+
+void subj_f128M_roundToInt_r_near_even( const float128_t, float128_t * );
+void subj_f128M_roundToInt_r_minMag( const float128_t, float128_t * );
+void subj_f128M_roundToInt_r_min( const float128_t, float128_t * );
+void subj_f128M_roundToInt_r_max( const float128_t, float128_t * );
+void subj_f128M_roundToInt_r_near_maxMag( const float128_t, float128_t * );
+void subj_f128M_roundToInt_x( const float128_t, float128_t * );
+void subj_f128M_add( const float128_t *, const float128_t *, float128_t * );
+void subj_f128M_sub( const float128_t *, const float128_t *, float128_t * );
+void subj_f128M_mul( const float128_t *, const float128_t *, float128_t * );
+void
+ subj_f128M_mulAdd(
+     const float128_t *, const float128_t *, const float128_t *, float128_t *
+ );
+void subj_f128M_div( const float128_t *, const float128_t *, float128_t * );
+void subj_f128M_rem( const float128_t *, const float128_t *, float128_t * );
+void subj_f128M_sqrt( const float128_t *, float128_t * );
+bool subj_f128M_eq( const float128_t *, const float128_t * );
+bool subj_f128M_le( const float128_t *, const float128_t * );
+bool subj_f128M_lt( const float128_t *, const float128_t * );
+bool subj_f128M_eq_signaling( const float128_t *, const float128_t * );
+bool subj_f128M_le_quiet( const float128_t *, const float128_t * );
+bool subj_f128M_lt_quiet( const float128_t *, const float128_t * );
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/subjfloat_functions.c b/addins/TestFloat-3e/source/subjfloat_functions.c
new file mode 100644
index 000000000..4d3ff6248
--- /dev/null
+++ b/addins/TestFloat-3e/source/subjfloat_functions.c
@@ -0,0 +1,1810 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include "platform.h"
+#include "subjfloat_config.h"
+#include "subjfloat.h"
+#include "functions.h"
+
+typedef void genericFuncType();
+
+/*----------------------------------------------------------------------------
+| WARNING:
+| This file should not normally be modified.  See "subjfloat_config.h"
+| instead.
+|   The order of these array entries must match the order in the array
+| `standardFunctionInfos'.  Be careful about making changes.
+*----------------------------------------------------------------------------*/
+
+genericFuncType *const subjfloat_functions[] = {
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+#ifdef SUBJ_UI32_TO_F16
+    (genericFuncType *) subj_ui32_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_UI32_TO_F32
+    (genericFuncType *) subj_ui32_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_UI32_TO_F64
+    (genericFuncType *) subj_ui32_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_UI32_TO_EXTF80
+    (genericFuncType *) subj_ui32_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_UI32_TO_F128
+    (genericFuncType *) subj_ui32_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_UI64_TO_F16
+    (genericFuncType *) subj_ui64_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_UI64_TO_F32
+    (genericFuncType *) subj_ui64_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_UI64_TO_F64
+    (genericFuncType *) subj_ui64_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_UI64_TO_EXTF80
+    (genericFuncType *) subj_ui64_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_UI64_TO_F128
+    (genericFuncType *) subj_ui64_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_I32_TO_F16
+    (genericFuncType *) subj_i32_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_I32_TO_F32
+    (genericFuncType *) subj_i32_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_I32_TO_F64
+    (genericFuncType *) subj_i32_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_I32_TO_EXTF80
+    (genericFuncType *) subj_i32_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_I32_TO_F128
+    (genericFuncType *) subj_i32_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_I64_TO_F16
+    (genericFuncType *) subj_i64_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_I64_TO_F32
+    (genericFuncType *) subj_i64_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_I64_TO_F64
+    (genericFuncType *) subj_i64_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_I64_TO_EXTF80
+    (genericFuncType *) subj_i64_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_I64_TO_F128
+    (genericFuncType *) subj_i64_to_f128M,
+#else
+    0,
+#endif
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT16
+#ifdef SUBJ_F16_TO_UI32_R_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_ui32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_R_MINMAG
+    (genericFuncType *) subj_f16_to_ui32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_R_MIN
+    (genericFuncType *) subj_f16_to_ui32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_R_MAX
+    (genericFuncType *) subj_f16_to_ui32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_ui32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_R_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_ui64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_R_MINMAG
+    (genericFuncType *) subj_f16_to_ui64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_R_MIN
+    (genericFuncType *) subj_f16_to_ui64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_R_MAX
+    (genericFuncType *) subj_f16_to_ui64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_ui64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_R_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_i32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_R_MINMAG
+    (genericFuncType *) subj_f16_to_i32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_R_MIN
+    (genericFuncType *) subj_f16_to_i32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_R_MAX
+    (genericFuncType *) subj_f16_to_i32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_i32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_R_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_i64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_R_MINMAG
+    (genericFuncType *) subj_f16_to_i64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_R_MIN
+    (genericFuncType *) subj_f16_to_i64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_R_MAX
+    (genericFuncType *) subj_f16_to_i64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_i64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_ui32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_RX_MINMAG
+    (genericFuncType *) subj_f16_to_ui32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_RX_MIN
+    (genericFuncType *) subj_f16_to_ui32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_RX_MAX
+    (genericFuncType *) subj_f16_to_ui32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_ui32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_ui64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_RX_MINMAG
+    (genericFuncType *) subj_f16_to_ui64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_RX_MIN
+    (genericFuncType *) subj_f16_to_ui64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_RX_MAX
+    (genericFuncType *) subj_f16_to_ui64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_UI64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_ui64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_i32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_RX_MINMAG
+    (genericFuncType *) subj_f16_to_i32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_RX_MIN
+    (genericFuncType *) subj_f16_to_i32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_RX_MAX
+    (genericFuncType *) subj_f16_to_i32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_i32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f16_to_i64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_RX_MINMAG
+    (genericFuncType *) subj_f16_to_i64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_RX_MIN
+    (genericFuncType *) subj_f16_to_i64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_RX_MAX
+    (genericFuncType *) subj_f16_to_i64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_I64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_to_i64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_TO_F32
+    (genericFuncType *) subj_f16_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F16_TO_F64
+    (genericFuncType *) subj_f16_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F16_TO_EXTF80
+    (genericFuncType *) subj_f16_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F16_TO_F128
+    (genericFuncType *) subj_f16_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_R_NEAR_EVEN
+    (genericFuncType *) subj_f16_roundToInt_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_R_MINMAG
+    (genericFuncType *) subj_f16_roundToInt_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_R_MIN
+    (genericFuncType *) subj_f16_roundToInt_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_R_MAX
+    (genericFuncType *) subj_f16_roundToInt_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f16_roundToInt_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ROUNDTOINT_X
+    (genericFuncType *) subj_f16_roundToInt_x,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_ADD
+    (genericFuncType *) subj_f16_add,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_SUB
+    (genericFuncType *) subj_f16_sub,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_MUL
+    (genericFuncType *) subj_f16_mul,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_MULADD
+    (genericFuncType *) subj_f16_mulAdd,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_DIV
+    (genericFuncType *) subj_f16_div,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_REM
+    (genericFuncType *) subj_f16_rem,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_SQRT
+    (genericFuncType *) subj_f16_sqrt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_EQ
+    (genericFuncType *) subj_f16_eq,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_LE
+    (genericFuncType *) subj_f16_le,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_LT
+    (genericFuncType *) subj_f16_lt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_EQ_SIGNALING
+    (genericFuncType *) subj_f16_eq_signaling,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_LE_QUIET
+    (genericFuncType *) subj_f16_le_quiet,
+#else
+    0,
+#endif
+#ifdef SUBJ_F16_LT_QUIET
+    (genericFuncType *) subj_f16_lt_quiet,
+#else
+    0,
+#endif
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef SUBJ_F32_TO_UI32_R_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_ui32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_R_MINMAG
+    (genericFuncType *) subj_f32_to_ui32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_R_MIN
+    (genericFuncType *) subj_f32_to_ui32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_R_MAX
+    (genericFuncType *) subj_f32_to_ui32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_ui32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_R_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_ui64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_R_MINMAG
+    (genericFuncType *) subj_f32_to_ui64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_R_MIN
+    (genericFuncType *) subj_f32_to_ui64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_R_MAX
+    (genericFuncType *) subj_f32_to_ui64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_ui64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_R_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_i32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_R_MINMAG
+    (genericFuncType *) subj_f32_to_i32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_R_MIN
+    (genericFuncType *) subj_f32_to_i32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_R_MAX
+    (genericFuncType *) subj_f32_to_i32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_i32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_R_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_i64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_R_MINMAG
+    (genericFuncType *) subj_f32_to_i64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_R_MIN
+    (genericFuncType *) subj_f32_to_i64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_R_MAX
+    (genericFuncType *) subj_f32_to_i64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_i64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_ui32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_RX_MINMAG
+    (genericFuncType *) subj_f32_to_ui32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_RX_MIN
+    (genericFuncType *) subj_f32_to_ui32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_RX_MAX
+    (genericFuncType *) subj_f32_to_ui32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_ui32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_ui64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_RX_MINMAG
+    (genericFuncType *) subj_f32_to_ui64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_RX_MIN
+    (genericFuncType *) subj_f32_to_ui64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_RX_MAX
+    (genericFuncType *) subj_f32_to_ui64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_UI64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_ui64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_i32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_RX_MINMAG
+    (genericFuncType *) subj_f32_to_i32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_RX_MIN
+    (genericFuncType *) subj_f32_to_i32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_RX_MAX
+    (genericFuncType *) subj_f32_to_i32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_i32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f32_to_i64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_RX_MINMAG
+    (genericFuncType *) subj_f32_to_i64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_RX_MIN
+    (genericFuncType *) subj_f32_to_i64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_RX_MAX
+    (genericFuncType *) subj_f32_to_i64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_TO_I64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_to_i64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_F32_TO_F16
+    (genericFuncType *) subj_f32_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F32_TO_F64
+    (genericFuncType *) subj_f32_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F32_TO_EXTF80
+    (genericFuncType *) subj_f32_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F32_TO_F128
+    (genericFuncType *) subj_f32_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_R_NEAR_EVEN
+    (genericFuncType *) subj_f32_roundToInt_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_R_MINMAG
+    (genericFuncType *) subj_f32_roundToInt_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_R_MIN
+    (genericFuncType *) subj_f32_roundToInt_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_R_MAX
+    (genericFuncType *) subj_f32_roundToInt_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f32_roundToInt_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ROUNDTOINT_X
+    (genericFuncType *) subj_f32_roundToInt_x,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_ADD
+    (genericFuncType *) subj_f32_add,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_SUB
+    (genericFuncType *) subj_f32_sub,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_MUL
+    (genericFuncType *) subj_f32_mul,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_MULADD
+    (genericFuncType *) subj_f32_mulAdd,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_DIV
+    (genericFuncType *) subj_f32_div,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_REM
+    (genericFuncType *) subj_f32_rem,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_SQRT
+    (genericFuncType *) subj_f32_sqrt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_EQ
+    (genericFuncType *) subj_f32_eq,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_LE
+    (genericFuncType *) subj_f32_le,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_LT
+    (genericFuncType *) subj_f32_lt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_EQ_SIGNALING
+    (genericFuncType *) subj_f32_eq_signaling,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_LE_QUIET
+    (genericFuncType *) subj_f32_le_quiet,
+#else
+    0,
+#endif
+#ifdef SUBJ_F32_LT_QUIET
+    (genericFuncType *) subj_f32_lt_quiet,
+#else
+    0,
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT64
+#ifdef SUBJ_F64_TO_UI32_R_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_ui32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_R_MINMAG
+    (genericFuncType *) subj_f64_to_ui32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_R_MIN
+    (genericFuncType *) subj_f64_to_ui32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_R_MAX
+    (genericFuncType *) subj_f64_to_ui32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_ui32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_R_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_ui64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_R_MINMAG
+    (genericFuncType *) subj_f64_to_ui64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_R_MIN
+    (genericFuncType *) subj_f64_to_ui64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_R_MAX
+    (genericFuncType *) subj_f64_to_ui64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_ui64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_R_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_i32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_R_MINMAG
+    (genericFuncType *) subj_f64_to_i32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_R_MIN
+    (genericFuncType *) subj_f64_to_i32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_R_MAX
+    (genericFuncType *) subj_f64_to_i32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_i32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_R_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_i64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_R_MINMAG
+    (genericFuncType *) subj_f64_to_i64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_R_MIN
+    (genericFuncType *) subj_f64_to_i64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_R_MAX
+    (genericFuncType *) subj_f64_to_i64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_i64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_ui32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_RX_MINMAG
+    (genericFuncType *) subj_f64_to_ui32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_RX_MIN
+    (genericFuncType *) subj_f64_to_ui32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_RX_MAX
+    (genericFuncType *) subj_f64_to_ui32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_ui32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_ui64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_RX_MINMAG
+    (genericFuncType *) subj_f64_to_ui64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_RX_MIN
+    (genericFuncType *) subj_f64_to_ui64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_RX_MAX
+    (genericFuncType *) subj_f64_to_ui64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_UI64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_ui64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_i32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_RX_MINMAG
+    (genericFuncType *) subj_f64_to_i32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_RX_MIN
+    (genericFuncType *) subj_f64_to_i32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_RX_MAX
+    (genericFuncType *) subj_f64_to_i32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_i32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f64_to_i64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_RX_MINMAG
+    (genericFuncType *) subj_f64_to_i64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_RX_MIN
+    (genericFuncType *) subj_f64_to_i64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_RX_MAX
+    (genericFuncType *) subj_f64_to_i64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_TO_I64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_to_i64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_F64_TO_F16
+    (genericFuncType *) subj_f64_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F64_TO_F32
+    (genericFuncType *) subj_f64_to_f32,
+#else
+    0,
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F64_TO_EXTF80
+    (genericFuncType *) subj_f64_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F64_TO_F128
+    (genericFuncType *) subj_f64_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_R_NEAR_EVEN
+    (genericFuncType *) subj_f64_roundToInt_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_R_MINMAG
+    (genericFuncType *) subj_f64_roundToInt_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_R_MIN
+    (genericFuncType *) subj_f64_roundToInt_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_R_MAX
+    (genericFuncType *) subj_f64_roundToInt_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f64_roundToInt_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ROUNDTOINT_X
+    (genericFuncType *) subj_f64_roundToInt_x,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_ADD
+    (genericFuncType *) subj_f64_add,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_SUB
+    (genericFuncType *) subj_f64_sub,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_MUL
+    (genericFuncType *) subj_f64_mul,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_MULADD
+    (genericFuncType *) subj_f64_mulAdd,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_DIV
+    (genericFuncType *) subj_f64_div,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_REM
+    (genericFuncType *) subj_f64_rem,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_SQRT
+    (genericFuncType *) subj_f64_sqrt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_EQ
+    (genericFuncType *) subj_f64_eq,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_LE
+    (genericFuncType *) subj_f64_le,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_LT
+    (genericFuncType *) subj_f64_lt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_EQ_SIGNALING
+    (genericFuncType *) subj_f64_eq_signaling,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_LE_QUIET
+    (genericFuncType *) subj_f64_le_quiet,
+#else
+    0,
+#endif
+#ifdef SUBJ_F64_LT_QUIET
+    (genericFuncType *) subj_f64_lt_quiet,
+#else
+    0,
+#endif
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+#ifdef SUBJ_EXTF80_TO_UI32_R_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_ui32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_R_MINMAG
+    (genericFuncType *) subj_extF80M_to_ui32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_R_MIN
+    (genericFuncType *) subj_extF80M_to_ui32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_R_MAX
+    (genericFuncType *) subj_extF80M_to_ui32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_ui32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_R_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_ui64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_R_MINMAG
+    (genericFuncType *) subj_extF80M_to_ui64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_R_MIN
+    (genericFuncType *) subj_extF80M_to_ui64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_R_MAX
+    (genericFuncType *) subj_extF80M_to_ui64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_ui64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_R_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_i32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_R_MINMAG
+    (genericFuncType *) subj_extF80M_to_i32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_R_MIN
+    (genericFuncType *) subj_extF80M_to_i32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_R_MAX
+    (genericFuncType *) subj_extF80M_to_i32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_i32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_R_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_i64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_R_MINMAG
+    (genericFuncType *) subj_extF80M_to_i64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_R_MIN
+    (genericFuncType *) subj_extF80M_to_i64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_R_MAX
+    (genericFuncType *) subj_extF80M_to_i64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_i64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_RX_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_ui32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_RX_MINMAG
+    (genericFuncType *) subj_extF80M_to_ui32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_RX_MIN
+    (genericFuncType *) subj_extF80M_to_ui32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_RX_MAX
+    (genericFuncType *) subj_extF80M_to_ui32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_ui32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_RX_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_ui64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_RX_MINMAG
+    (genericFuncType *) subj_extF80M_to_ui64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_RX_MIN
+    (genericFuncType *) subj_extF80M_to_ui64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_RX_MAX
+    (genericFuncType *) subj_extF80M_to_ui64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_UI64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_ui64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_RX_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_i32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_RX_MINMAG
+    (genericFuncType *) subj_extF80M_to_i32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_RX_MIN
+    (genericFuncType *) subj_extF80M_to_i32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_RX_MAX
+    (genericFuncType *) subj_extF80M_to_i32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_i32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_RX_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_to_i64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_RX_MINMAG
+    (genericFuncType *) subj_extF80M_to_i64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_RX_MIN
+    (genericFuncType *) subj_extF80M_to_i64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_RX_MAX
+    (genericFuncType *) subj_extF80M_to_i64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_TO_I64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_to_i64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_EXTF80_TO_F16
+    (genericFuncType *) subj_extF80M_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_EXTF80_TO_F32
+    (genericFuncType *) subj_extF80M_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_EXTF80_TO_F64
+    (genericFuncType *) subj_extF80M_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_EXTF80_TO_F128
+    (genericFuncType *) subj_extF80M_to_f128M,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_R_NEAR_EVEN
+    (genericFuncType *) subj_extF80M_roundToInt_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_R_MINMAG
+    (genericFuncType *) subj_extF80M_roundToInt_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_R_MIN
+    (genericFuncType *) subj_extF80M_roundToInt_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_R_MAX
+    (genericFuncType *) subj_extF80M_roundToInt_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_R_NEAR_MAXMAG
+    (genericFuncType *) subj_extF80M_roundToInt_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ROUNDTOINT_X
+    (genericFuncType *) subj_extF80M_roundToInt_x,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_ADD
+    (genericFuncType *) subj_extF80M_add,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_SUB
+    (genericFuncType *) subj_extF80M_sub,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_MUL
+    (genericFuncType *) subj_extF80M_mul,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_DIV
+    (genericFuncType *) subj_extF80M_div,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_REM
+    (genericFuncType *) subj_extF80M_rem,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_SQRT
+    (genericFuncType *) subj_extF80M_sqrt,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_EQ
+    (genericFuncType *) subj_extF80M_eq,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_LE
+    (genericFuncType *) subj_extF80M_le,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_LT
+    (genericFuncType *) subj_extF80M_lt,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_EQ_SIGNALING
+    (genericFuncType *) subj_extF80M_eq_signaling,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_LE_QUIET
+    (genericFuncType *) subj_extF80M_le_quiet,
+#else
+    0,
+#endif
+#ifdef SUBJ_EXTF80_LT_QUIET
+    (genericFuncType *) subj_extF80M_lt_quiet,
+#else
+    0,
+#endif
+#endif
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+#ifdef FLOAT128
+#ifdef SUBJ_F128_TO_UI32_R_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_ui32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_R_MINMAG
+    (genericFuncType *) subj_f128M_to_ui32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_R_MIN
+    (genericFuncType *) subj_f128M_to_ui32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_R_MAX
+    (genericFuncType *) subj_f128M_to_ui32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_ui32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_R_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_ui64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_R_MINMAG
+    (genericFuncType *) subj_f128M_to_ui64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_R_MIN
+    (genericFuncType *) subj_f128M_to_ui64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_R_MAX
+    (genericFuncType *) subj_f128M_to_ui64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_ui64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_R_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_i32_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_R_MINMAG
+    (genericFuncType *) subj_f128M_to_i32_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_R_MIN
+    (genericFuncType *) subj_f128M_to_i32_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_R_MAX
+    (genericFuncType *) subj_f128M_to_i32_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_i32_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_R_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_i64_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_R_MINMAG
+    (genericFuncType *) subj_f128M_to_i64_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_R_MIN
+    (genericFuncType *) subj_f128M_to_i64_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_R_MAX
+    (genericFuncType *) subj_f128M_to_i64_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_i64_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_ui32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_RX_MINMAG
+    (genericFuncType *) subj_f128M_to_ui32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_RX_MIN
+    (genericFuncType *) subj_f128M_to_ui32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_RX_MAX
+    (genericFuncType *) subj_f128M_to_ui32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_ui32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_ui64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_RX_MINMAG
+    (genericFuncType *) subj_f128M_to_ui64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_RX_MIN
+    (genericFuncType *) subj_f128M_to_ui64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_RX_MAX
+    (genericFuncType *) subj_f128M_to_ui64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_UI64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_ui64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_RX_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_i32_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_RX_MINMAG
+    (genericFuncType *) subj_f128M_to_i32_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_RX_MIN
+    (genericFuncType *) subj_f128M_to_i32_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_RX_MAX
+    (genericFuncType *) subj_f128M_to_i32_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I32_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_i32_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_RX_NEAR_EVEN
+    (genericFuncType *) subj_f128M_to_i64_rx_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_RX_MINMAG
+    (genericFuncType *) subj_f128M_to_i64_rx_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_RX_MIN
+    (genericFuncType *) subj_f128M_to_i64_rx_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_RX_MAX
+    (genericFuncType *) subj_f128M_to_i64_rx_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_TO_I64_RX_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_to_i64_rx_near_maxMag,
+#else
+    0,
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_F128_TO_F16
+    (genericFuncType *) subj_f128M_to_f16,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F128_TO_F32
+    (genericFuncType *) subj_f128M_to_f32,
+#else
+    0,
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F128_TO_F64
+    (genericFuncType *) subj_f128M_to_f64,
+#else
+    0,
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F128_TO_EXTF80
+    (genericFuncType *) subj_f128M_to_extF80M,
+#else
+    0,
+#endif
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_R_NEAR_EVEN
+    (genericFuncType *) subj_f128M_roundToInt_r_near_even,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_R_MINMAG
+    (genericFuncType *) subj_f128M_roundToInt_r_minMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_R_MIN
+    (genericFuncType *) subj_f128M_roundToInt_r_min,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_R_MAX
+    (genericFuncType *) subj_f128M_roundToInt_r_max,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_R_NEAR_MAXMAG
+    (genericFuncType *) subj_f128M_roundToInt_r_near_maxMag,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ROUNDTOINT_X
+    (genericFuncType *) subj_f128M_roundToInt_x,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_ADD
+    (genericFuncType *) subj_f128M_add,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_SUB
+    (genericFuncType *) subj_f128M_sub,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_MUL
+    (genericFuncType *) subj_f128M_mul,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_MULADD
+    (genericFuncType *) subj_f128M_mulAdd,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_DIV
+    (genericFuncType *) subj_f128M_div,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_REM
+    (genericFuncType *) subj_f128M_rem,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_SQRT
+    (genericFuncType *) subj_f128M_sqrt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_EQ
+    (genericFuncType *) subj_f128M_eq,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_LE
+    (genericFuncType *) subj_f128M_le,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_LT
+    (genericFuncType *) subj_f128M_lt,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_EQ_SIGNALING
+    (genericFuncType *) subj_f128M_eq_signaling,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_LE_QUIET
+    (genericFuncType *) subj_f128M_le_quiet,
+#else
+    0,
+#endif
+#ifdef SUBJ_F128_LT_QUIET
+    (genericFuncType *) subj_f128M_lt_quiet,
+#else
+    0,
+#endif
+#endif
+};
+
diff --git a/addins/TestFloat-3e/source/testLoops.h b/addins/TestFloat-3e/source/testLoops.h
new file mode 100644
index 000000000..e198eaefb
--- /dev/null
+++ b/addins/TestFloat-3e/source/testLoops.h
@@ -0,0 +1,578 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "softfloat.h"
+
+extern bool testLoops_forever;
+
+extern uint_fast8_t *testLoops_trueFlagsPtr;
+extern uint_fast8_t (*testLoops_subjFlagsFunction)( void );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT16
+void test_a_ui32_z_f16( float16_t ( uint32_t ), float16_t ( uint32_t ) );
+#endif
+void test_a_ui32_z_f32( float32_t ( uint32_t ), float32_t ( uint32_t ) );
+#ifdef FLOAT64
+void test_a_ui32_z_f64( float64_t ( uint32_t ), float64_t ( uint32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_ui32_z_extF80(
+     void ( uint32_t, extFloat80_t * ), void ( uint32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_ui32_z_f128(
+     void ( uint32_t, float128_t * ), void ( uint32_t, float128_t * )
+ );
+#endif
+#ifdef FLOAT16
+void test_a_ui64_z_f16( float16_t ( uint64_t ), float16_t ( uint64_t ) );
+#endif
+void test_a_ui64_z_f32( float32_t ( uint64_t ), float32_t ( uint64_t ) );
+#ifdef FLOAT64
+void test_a_ui64_z_f64( float64_t ( uint64_t ), float64_t ( uint64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_ui64_z_extF80(
+     void ( uint64_t, extFloat80_t * ), void ( uint64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_ui64_z_f128(
+     void ( uint64_t, float128_t * ), void ( uint64_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void test_a_i32_z_f16( float16_t ( int32_t ), float16_t ( int32_t ) );
+#endif
+void test_a_i32_z_f32( float32_t ( int32_t ), float32_t ( int32_t ) );
+#ifdef FLOAT64
+void test_a_i32_z_f64( float64_t ( int32_t ), float64_t ( int32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_i32_z_extF80(
+     void ( int32_t, extFloat80_t * ), void ( int32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_i32_z_f128(
+     void ( int32_t, float128_t * ), void ( int32_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void test_a_i64_z_f16( float16_t ( int64_t ), float16_t ( int64_t ) );
+#endif
+void test_a_i64_z_f32( float32_t ( int64_t ), float32_t ( int64_t ) );
+#ifdef FLOAT64
+void test_a_i64_z_f64( float64_t ( int64_t ), float64_t ( int64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_i64_z_extF80(
+     void ( int64_t, extFloat80_t * ), void ( int64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_i64_z_f128(
+     void ( int64_t, float128_t * ), void ( int64_t, float128_t * ) );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT16
+void
+ test_a_f16_z_ui32_rx(
+     uint_fast32_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast32_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f16_z_ui64_rx(
+     uint_fast64_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast64_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f16_z_i32_rx(
+     int_fast32_t ( float16_t, uint_fast8_t, bool ),
+     int_fast32_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f16_z_i64_rx(
+     int_fast64_t ( float16_t, uint_fast8_t, bool ),
+     int_fast64_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f16_z_ui32_x(
+     uint_fast32_t ( float16_t, bool ), uint_fast32_t ( float16_t, bool ), bool
+ );
+void
+ test_a_f16_z_ui64_x(
+     uint_fast64_t ( float16_t, bool ), uint_fast64_t ( float16_t, bool ), bool
+ );
+void
+ test_a_f16_z_i32_x(
+     int_fast32_t ( float16_t, bool ), int_fast32_t ( float16_t, bool ), bool
+ );
+void
+ test_a_f16_z_i64_x(
+     int_fast64_t ( float16_t, bool ), int_fast64_t ( float16_t, bool ), bool
+ );
+void test_a_f16_z_f32( float32_t ( float16_t ), float32_t ( float16_t ) );
+#ifdef FLOAT64
+void test_a_f16_z_f64( float64_t ( float16_t ), float64_t ( float16_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_f16_z_extF80(
+     void ( float16_t, extFloat80_t * ), void ( float16_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_f16_z_f128(
+     void ( float16_t, float128_t * ), void ( float16_t, float128_t * ) );
+#endif
+void test_az_f16( float16_t ( float16_t ), float16_t ( float16_t ) );
+void
+ test_az_f16_rx(
+     float16_t ( float16_t, uint_fast8_t, bool ),
+     float16_t ( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_abz_f16(
+     float16_t ( float16_t, float16_t ), float16_t ( float16_t, float16_t ) );
+void
+ test_abcz_f16(
+     float16_t ( float16_t, float16_t, float16_t ),
+     float16_t ( float16_t, float16_t, float16_t )
+ );
+void
+ test_ab_f16_z_bool(
+     bool ( float16_t, float16_t ), bool ( float16_t, float16_t ) );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+void
+ test_a_f32_z_ui32_rx(
+     uint_fast32_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast32_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f32_z_ui64_rx(
+     uint_fast64_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast64_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f32_z_i32_rx(
+     int_fast32_t ( float32_t, uint_fast8_t, bool ),
+     int_fast32_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f32_z_i64_rx(
+     int_fast64_t ( float32_t, uint_fast8_t, bool ),
+     int_fast64_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f32_z_ui32_x(
+     uint_fast32_t ( float32_t, bool ), uint_fast32_t ( float32_t, bool ), bool
+ );
+void
+ test_a_f32_z_ui64_x(
+     uint_fast64_t ( float32_t, bool ), uint_fast64_t ( float32_t, bool ), bool
+ );
+void
+ test_a_f32_z_i32_x(
+     int_fast32_t ( float32_t, bool ), int_fast32_t ( float32_t, bool ), bool
+ );
+void
+ test_a_f32_z_i64_x(
+     int_fast64_t ( float32_t, bool ), int_fast64_t ( float32_t, bool ), bool
+ );
+#ifdef FLOAT16
+void test_a_f32_z_f16( float16_t ( float32_t ), float16_t ( float32_t ) );
+#endif
+#ifdef FLOAT64
+void test_a_f32_z_f64( float64_t ( float32_t ), float64_t ( float32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_f32_z_extF80(
+     void ( float32_t, extFloat80_t * ), void ( float32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_f32_z_f128(
+     void ( float32_t, float128_t * ), void ( float32_t, float128_t * ) );
+#endif
+void test_az_f32( float32_t ( float32_t ), float32_t ( float32_t ) );
+void
+ test_az_f32_rx(
+     float32_t ( float32_t, uint_fast8_t, bool ),
+     float32_t ( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_abz_f32(
+     float32_t ( float32_t, float32_t ), float32_t ( float32_t, float32_t ) );
+void
+ test_abcz_f32(
+     float32_t ( float32_t, float32_t, float32_t ),
+     float32_t ( float32_t, float32_t, float32_t )
+ );
+void
+ test_ab_f32_z_bool(
+     bool ( float32_t, float32_t ), bool ( float32_t, float32_t ) );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT64
+void
+ test_a_f64_z_ui32_rx(
+     uint_fast32_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast32_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f64_z_ui64_rx(
+     uint_fast64_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast64_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f64_z_i32_rx(
+     int_fast32_t ( float64_t, uint_fast8_t, bool ),
+     int_fast32_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f64_z_i64_rx(
+     int_fast64_t ( float64_t, uint_fast8_t, bool ),
+     int_fast64_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f64_z_ui32_x(
+     uint_fast32_t ( float64_t, bool ), uint_fast32_t ( float64_t, bool ), bool
+ );
+void
+ test_a_f64_z_ui64_x(
+     uint_fast64_t ( float64_t, bool ), uint_fast64_t ( float64_t, bool ), bool
+ );
+void
+ test_a_f64_z_i32_x(
+     int_fast32_t ( float64_t, bool ), int_fast32_t ( float64_t, bool ), bool
+ );
+void
+ test_a_f64_z_i64_x(
+     int_fast64_t ( float64_t, bool ), int_fast64_t ( float64_t, bool ), bool
+ );
+#ifdef FLOAT16
+void test_a_f64_z_f16( float16_t ( float64_t ), float16_t ( float64_t ) );
+#endif
+void test_a_f64_z_f32( float32_t ( float64_t ), float32_t ( float64_t ) );
+#ifdef EXTFLOAT80
+void
+ test_a_f64_z_extF80(
+     void ( float64_t, extFloat80_t * ), void ( float64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_f64_z_f128(
+     void ( float64_t, float128_t * ), void ( float64_t, float128_t * ) );
+#endif
+void test_az_f64( float64_t ( float64_t ), float64_t ( float64_t ) );
+void
+ test_az_f64_rx(
+     float64_t ( float64_t, uint_fast8_t, bool ),
+     float64_t ( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_abz_f64(
+     float64_t ( float64_t, float64_t ), float64_t ( float64_t, float64_t ) );
+void
+ test_abcz_f64(
+     float64_t ( float64_t, float64_t, float64_t ),
+     float64_t ( float64_t, float64_t, float64_t )
+ );
+void
+ test_ab_f64_z_bool(
+     bool ( float64_t, float64_t ), bool ( float64_t, float64_t ) );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+void
+ test_a_extF80_z_ui32_rx(
+     uint_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_extF80_z_ui64_rx(
+     uint_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_extF80_z_i32_rx(
+     int_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     int_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_extF80_z_i64_rx(
+     int_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     int_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_extF80_z_ui32_x(
+     uint_fast32_t ( const extFloat80_t *, bool ),
+     uint_fast32_t ( const extFloat80_t *, bool ),
+     bool
+ );
+void
+ test_a_extF80_z_ui64_x(
+     uint_fast64_t ( const extFloat80_t *, bool ),
+     uint_fast64_t ( const extFloat80_t *, bool ),
+     bool
+ );
+void
+ test_a_extF80_z_i32_x(
+     int_fast32_t ( const extFloat80_t *, bool ),
+     int_fast32_t ( const extFloat80_t *, bool ),
+     bool
+ );
+void
+ test_a_extF80_z_i64_x(
+     int_fast64_t ( const extFloat80_t *, bool ),
+     int_fast64_t ( const extFloat80_t *, bool ),
+     bool
+ );
+#ifdef FLOAT16
+void
+ test_a_extF80_z_f16(
+     float16_t ( const extFloat80_t * ), float16_t ( const extFloat80_t * ) );
+#endif
+void
+ test_a_extF80_z_f32(
+     float32_t ( const extFloat80_t * ), float32_t ( const extFloat80_t * ) );
+#ifdef FLOAT64
+void
+ test_a_extF80_z_f64(
+     float64_t ( const extFloat80_t * ), float64_t ( const extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void
+ test_a_extF80_z_f128(
+     void ( const extFloat80_t *, float128_t * ),
+     void ( const extFloat80_t *, float128_t * )
+ );
+#endif
+void
+ test_az_extF80(
+     void ( const extFloat80_t *, extFloat80_t * ),
+     void ( const extFloat80_t *, extFloat80_t * )
+ );
+void
+ test_az_extF80_rx(
+     void ( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     void ( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_abz_extF80(
+     void ( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ),
+     void ( const extFloat80_t *, const extFloat80_t *, extFloat80_t * )
+ );
+void
+ test_ab_extF80_z_bool(
+     bool ( const extFloat80_t *, const extFloat80_t * ),
+     bool ( const extFloat80_t *, const extFloat80_t * )
+ );
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#ifdef FLOAT128
+void
+ test_a_f128_z_ui32_rx(
+     uint_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f128_z_ui64_rx(
+     uint_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f128_z_i32_rx(
+     int_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     int_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f128_z_i64_rx(
+     int_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     int_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_a_f128_z_ui32_x(
+     uint_fast32_t ( const float128_t *, bool ),
+     uint_fast32_t ( const float128_t *, bool ),
+     bool
+ );
+void
+ test_a_f128_z_ui64_x(
+     uint_fast64_t ( const float128_t *, bool ),
+     uint_fast64_t ( const float128_t *, bool ),
+     bool
+ );
+void
+ test_a_f128_z_i32_x(
+     int_fast32_t ( const float128_t *, bool ),
+     int_fast32_t ( const float128_t *, bool ),
+     bool
+ );
+void
+ test_a_f128_z_i64_x(
+     int_fast64_t ( const float128_t *, bool ),
+     int_fast64_t ( const float128_t *, bool ),
+     bool
+ );
+#ifdef FLOAT16
+void
+ test_a_f128_z_f16(
+     float16_t ( const float128_t * ), float16_t ( const float128_t * ) );
+#endif
+void
+ test_a_f128_z_f32(
+     float32_t ( const float128_t * ), float32_t ( const float128_t * ) );
+#ifdef FLOAT64
+void
+ test_a_f128_z_f64(
+     float64_t ( const float128_t * ), float64_t ( const float128_t * ) );
+#endif
+#ifdef EXTFLOAT80
+void
+ test_a_f128_z_extF80(
+     void ( const float128_t *, extFloat80_t * ),
+     void ( const float128_t *, extFloat80_t * )
+ );
+#endif
+void
+ test_az_f128(
+     void ( const float128_t *, float128_t * ),
+     void ( const float128_t *, float128_t * )
+ );
+void
+ test_az_f128_rx(
+     void ( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     void ( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ test_abz_f128(
+     void ( const float128_t *, const float128_t *, float128_t * ),
+     void ( const float128_t *, const float128_t *, float128_t * )
+ );
+void
+ test_abcz_f128(
+     void
+      ( const float128_t *,
+        const float128_t *,
+        const float128_t *,
+        float128_t *
+      ),
+     void
+      ( const float128_t *,
+        const float128_t *,
+        const float128_t *,
+        float128_t *
+      )
+ );
+void
+ test_ab_f128_z_bool(
+     bool ( const float128_t *, const float128_t * ),
+     bool ( const float128_t *, const float128_t * )
+ );
+#endif
+
diff --git a/addins/TestFloat-3e/source/testLoops_common.c b/addins/TestFloat-3e/source/testLoops_common.c
new file mode 100644
index 000000000..1553aa110
--- /dev/null
+++ b/addins/TestFloat-3e/source/testLoops_common.c
@@ -0,0 +1,47 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "testLoops.h"
+
+bool testLoops_forever = false;
+
+uint_fast8_t *testLoops_trueFlagsPtr;
+uint_fast8_t (*testLoops_subjFlagsFunction)( void );
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_f128.c b/addins/TestFloat-3e/source/test_a_extF80_z_f128.c
new file mode 100644
index 000000000..505ef1279
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_f128.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined EXTFLOAT80 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_f128(
+     void trueFunction( const extFloat80_t *, float128_t * ),
+     void subjFunction( const extFloat80_t *, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_extF80_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_f16.c b/addins/TestFloat-3e/source/test_a_extF80_z_f16.c
new file mode 100644
index 000000000..e6a6651d2
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_f16.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_f16(
+     float16_t trueFunction( const extFloat80_t * ),
+     float16_t subjFunction( const extFloat80_t * )
+ )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_f32.c b/addins/TestFloat-3e/source/test_a_extF80_z_f32.c
new file mode 100644
index 000000000..c752515d1
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_f32.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_f32(
+     float32_t trueFunction( const extFloat80_t * ),
+     float32_t subjFunction( const extFloat80_t * )
+ )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_f64.c b/addins/TestFloat-3e/source/test_a_extF80_z_f64.c
new file mode 100644
index 000000000..4d24fb194
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_f64.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT64 && defined EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_f64(
+     float64_t trueFunction( const extFloat80_t * ),
+     float64_t subjFunction( const extFloat80_t * )
+ )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_i32_rx.c b/addins/TestFloat-3e/source/test_a_extF80_z_i32_rx.c
new file mode 100644
index 000000000..fd2eea41d
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_i32_rx.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_i32_rx(
+     int_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     int_fast32_t subjFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! extF80M_isNaN( &genCases_extF80_a )
+                                || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_i32_x.c b/addins/TestFloat-3e/source/test_a_extF80_z_i32_x.c
new file mode 100644
index 000000000..2260614d6
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_i32_x.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_i32_x(
+     int_fast32_t trueFunction( const extFloat80_t *, bool ),
+     int_fast32_t subjFunction( const extFloat80_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! extF80M_isNaN( &genCases_extF80_a )
+                                || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_i64_rx.c b/addins/TestFloat-3e/source/test_a_extF80_z_i64_rx.c
new file mode 100644
index 000000000..0b99e99b4
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_i64_rx.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_i64_rx(
+     int_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     int_fast64_t subjFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! extF80M_isNaN( &genCases_extF80_a )
+                                || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_i64_x.c b/addins/TestFloat-3e/source/test_a_extF80_z_i64_x.c
new file mode 100644
index 000000000..9e7a5b179
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_i64_x.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_i64_x(
+     int_fast64_t trueFunction( const extFloat80_t *, bool ),
+     int_fast64_t subjFunction( const extFloat80_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! extF80M_isNaN( &genCases_extF80_a )
+                                || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_ui32_rx.c b/addins/TestFloat-3e/source/test_a_extF80_z_ui32_rx.c
new file mode 100644
index 000000000..fcc92da85
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_ui32_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_ui32_rx(
+     uint_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast32_t subjFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_ui32_x.c b/addins/TestFloat-3e/source/test_a_extF80_z_ui32_x.c
new file mode 100644
index 000000000..ff16f1998
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_ui32_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_ui32_x(
+     uint_fast32_t trueFunction( const extFloat80_t *, bool ),
+     uint_fast32_t subjFunction( const extFloat80_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_ui64_rx.c b/addins/TestFloat-3e/source/test_a_extF80_z_ui64_rx.c
new file mode 100644
index 000000000..efab40e80
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_ui64_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_ui64_rx(
+     uint_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast64_t subjFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_extF80_z_ui64_x.c b/addins/TestFloat-3e/source/test_a_extF80_z_ui64_x.c
new file mode 100644
index 000000000..1c1d04ef1
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_extF80_z_ui64_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_extF80_z_ui64_x(
+     uint_fast64_t trueFunction( const extFloat80_t *, bool ),
+     uint_fast64_t subjFunction( const extFloat80_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_extF80.c b/addins/TestFloat-3e/source/test_a_f128_z_extF80.c
new file mode 100644
index 000000000..1bb3e19d2
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_extF80.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined EXTFLOAT80 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_extF80(
+     void trueFunction( const float128_t *, extFloat80_t * ),
+     void subjFunction( const float128_t *, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_f128_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_f16.c b/addins/TestFloat-3e/source/test_a_f128_z_f16.c
new file mode 100644
index 000000000..eb8b3fbec
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_f16.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_f16(
+     float16_t trueFunction( const float128_t * ),
+     float16_t subjFunction( const float128_t * )
+ )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_f32.c b/addins/TestFloat-3e/source/test_a_f128_z_f32.c
new file mode 100644
index 000000000..7df7b1fb0
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_f32.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_f32(
+     float32_t trueFunction( const float128_t * ),
+     float32_t subjFunction( const float128_t * )
+ )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_f64.c b/addins/TestFloat-3e/source/test_a_f128_z_f64.c
new file mode 100644
index 000000000..96ac1e00a
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_f64.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT64 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_f64(
+     float64_t trueFunction( const float128_t * ),
+     float64_t subjFunction( const float128_t * )
+ )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_i32_rx.c b/addins/TestFloat-3e/source/test_a_f128_z_i32_rx.c
new file mode 100644
index 000000000..7aa68b9fd
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_i32_rx.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_i32_rx(
+     int_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     int_fast32_t subjFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f128M_isNaN( &genCases_f128_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_i32_x.c b/addins/TestFloat-3e/source/test_a_f128_z_i32_x.c
new file mode 100644
index 000000000..3f2b1cb68
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_i32_x.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_i32_x(
+     int_fast32_t trueFunction( const float128_t *, bool ),
+     int_fast32_t subjFunction( const float128_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f128M_isNaN( &genCases_f128_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_i64_rx.c b/addins/TestFloat-3e/source/test_a_f128_z_i64_rx.c
new file mode 100644
index 000000000..cac33bf3c
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_i64_rx.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_i64_rx(
+     int_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     int_fast64_t subjFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f128M_isNaN( &genCases_f128_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_i64_x.c b/addins/TestFloat-3e/source/test_a_f128_z_i64_x.c
new file mode 100644
index 000000000..c5004c879
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_i64_x.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_i64_x(
+     int_fast64_t trueFunction( const float128_t *, bool ),
+     int_fast64_t subjFunction( const float128_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f128M_isNaN( &genCases_f128_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_ui32_rx.c b/addins/TestFloat-3e/source/test_a_f128_z_ui32_rx.c
new file mode 100644
index 000000000..e4ae8cdfa
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_ui32_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_ui32_rx(
+     uint_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast32_t subjFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_ui32_x.c b/addins/TestFloat-3e/source/test_a_f128_z_ui32_x.c
new file mode 100644
index 000000000..9493f4e67
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_ui32_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_ui32_x(
+     uint_fast32_t trueFunction( const float128_t *, bool ),
+     uint_fast32_t subjFunction( const float128_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_ui64_rx.c b/addins/TestFloat-3e/source/test_a_f128_z_ui64_rx.c
new file mode 100644
index 000000000..2f336de34
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_ui64_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_ui64_rx(
+     uint_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast64_t subjFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f128_z_ui64_x.c b/addins/TestFloat-3e/source/test_a_f128_z_ui64_x.c
new file mode 100644
index 000000000..37f703a4b
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f128_z_ui64_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f128_z_ui64_x(
+     uint_fast64_t trueFunction( const float128_t *, bool ),
+     uint_fast64_t subjFunction( const float128_t *, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_extF80.c b/addins/TestFloat-3e/source/test_a_f16_z_extF80.c
new file mode 100644
index 000000000..d8f39f6fd
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_extF80.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_extF80(
+     void trueFunction( float16_t, extFloat80_t * ),
+     void subjFunction( float16_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f16_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f16_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_f128.c b/addins/TestFloat-3e/source/test_a_f16_z_f128.c
new file mode 100644
index 000000000..433418b63
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_f128.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_f128(
+     void trueFunction( float16_t, float128_t * ),
+     void subjFunction( float16_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f16_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f16_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_f32.c b/addins/TestFloat-3e/source/test_a_f16_z_f32.c
new file mode 100644
index 000000000..8e8460787
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_f32.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_f32(
+     float32_t trueFunction( float16_t ), float32_t subjFunction( float16_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_f64.c b/addins/TestFloat-3e/source/test_a_f16_z_f64.c
new file mode 100644
index 000000000..bf0f343c5
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_f64.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_f64(
+     float64_t trueFunction( float16_t ), float64_t subjFunction( float16_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_i32_rx.c b/addins/TestFloat-3e/source/test_a_f16_z_i32_rx.c
new file mode 100644
index 000000000..c73fc7625
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_i32_rx.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_i32_rx(
+     int_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     int_fast32_t subjFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f16_isNaN( genCases_f16_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_i32_x.c b/addins/TestFloat-3e/source/test_a_f16_z_i32_x.c
new file mode 100644
index 000000000..2eaba6f2a
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_i32_x.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_i32_x(
+     int_fast32_t trueFunction( float16_t, bool ),
+     int_fast32_t subjFunction( float16_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f16_isNaN( genCases_f16_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_i64_rx.c b/addins/TestFloat-3e/source/test_a_f16_z_i64_rx.c
new file mode 100644
index 000000000..e31d3d380
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_i64_rx.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_i64_rx(
+     int_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     int_fast64_t subjFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f16_isNaN( genCases_f16_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_i64_x.c b/addins/TestFloat-3e/source/test_a_f16_z_i64_x.c
new file mode 100644
index 000000000..bda01182e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_i64_x.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_i64_x(
+     int_fast64_t trueFunction( float16_t, bool ),
+     int_fast64_t subjFunction( float16_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f16_isNaN( genCases_f16_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_ui32_rx.c b/addins/TestFloat-3e/source/test_a_f16_z_ui32_rx.c
new file mode 100644
index 000000000..fc302f7b0
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_ui32_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_ui32_rx(
+     uint_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast32_t subjFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_ui32_x.c b/addins/TestFloat-3e/source/test_a_f16_z_ui32_x.c
new file mode 100644
index 000000000..3905bd39d
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_ui32_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_ui32_x(
+     uint_fast32_t trueFunction( float16_t, bool ),
+     uint_fast32_t subjFunction( float16_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_ui64_rx.c b/addins/TestFloat-3e/source/test_a_f16_z_ui64_rx.c
new file mode 100644
index 000000000..9b34ae9cf
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_ui64_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_ui64_rx(
+     uint_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast64_t subjFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f16_z_ui64_x.c b/addins/TestFloat-3e/source/test_a_f16_z_ui64_x.c
new file mode 100644
index 000000000..2527de482
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f16_z_ui64_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f16_z_ui64_x(
+     uint_fast64_t trueFunction( float16_t, bool ),
+     uint_fast64_t subjFunction( float16_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_extF80.c b/addins/TestFloat-3e/source/test_a_f32_z_extF80.c
new file mode 100644
index 000000000..000ade09c
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_extF80.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_extF80(
+     void trueFunction( float32_t, extFloat80_t * ),
+     void subjFunction( float32_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_f128.c b/addins/TestFloat-3e/source/test_a_f32_z_f128.c
new file mode 100644
index 000000000..bc05438b8
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_f128.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_f128(
+     void trueFunction( float32_t, float128_t * ),
+     void subjFunction( float32_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_f16.c b/addins/TestFloat-3e/source/test_a_f32_z_f16.c
new file mode 100644
index 000000000..b89002c66
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_f16.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_f16(
+     float16_t trueFunction( float32_t ), float16_t subjFunction( float32_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_f64.c b/addins/TestFloat-3e/source/test_a_f32_z_f64.c
new file mode 100644
index 000000000..19267cbef
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_f64.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_f64(
+     float64_t trueFunction( float32_t ), float64_t subjFunction( float32_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_i32_rx.c b/addins/TestFloat-3e/source/test_a_f32_z_i32_rx.c
new file mode 100644
index 000000000..d4ff4782c
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_i32_rx.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_i32_rx(
+     int_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     int_fast32_t subjFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f32_isNaN( genCases_f32_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_i32_x.c b/addins/TestFloat-3e/source/test_a_f32_z_i32_x.c
new file mode 100644
index 000000000..4883d19c8
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_i32_x.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_i32_x(
+     int_fast32_t trueFunction( float32_t, bool ),
+     int_fast32_t subjFunction( float32_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f32_isNaN( genCases_f32_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_i64_rx.c b/addins/TestFloat-3e/source/test_a_f32_z_i64_rx.c
new file mode 100644
index 000000000..d3216bd8f
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_i64_rx.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_i64_rx(
+     int_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     int_fast64_t subjFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f32_isNaN( genCases_f32_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_i64_x.c b/addins/TestFloat-3e/source/test_a_f32_z_i64_x.c
new file mode 100644
index 000000000..4038135d0
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_i64_x.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_i64_x(
+     int_fast64_t trueFunction( float32_t, bool ),
+     int_fast64_t subjFunction( float32_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f32_isNaN( genCases_f32_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_ui32_rx.c b/addins/TestFloat-3e/source/test_a_f32_z_ui32_rx.c
new file mode 100644
index 000000000..9b120a589
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_ui32_rx.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_ui32_rx(
+     uint_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast32_t subjFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_ui32_x.c b/addins/TestFloat-3e/source/test_a_f32_z_ui32_x.c
new file mode 100644
index 000000000..18dc88126
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_ui32_x.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_ui32_x(
+     uint_fast32_t trueFunction( float32_t, bool ),
+     uint_fast32_t subjFunction( float32_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_ui64_rx.c b/addins/TestFloat-3e/source/test_a_f32_z_ui64_rx.c
new file mode 100644
index 000000000..2c792c2a1
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_ui64_rx.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_ui64_rx(
+     uint_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast64_t subjFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f32_z_ui64_x.c b/addins/TestFloat-3e/source/test_a_f32_z_ui64_x.c
new file mode 100644
index 000000000..7cf7c3173
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f32_z_ui64_x.c
@@ -0,0 +1,98 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f32_z_ui64_x(
+     uint_fast64_t trueFunction( float32_t, bool ),
+     uint_fast64_t subjFunction( float32_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_extF80.c b/addins/TestFloat-3e/source/test_a_f64_z_extF80.c
new file mode 100644
index 000000000..76a69acce
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_extF80.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT64 && defined EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_extF80(
+     void trueFunction( float64_t, extFloat80_t * ),
+     void subjFunction( float64_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_f128.c b/addins/TestFloat-3e/source/test_a_f64_z_f128.c
new file mode 100644
index 000000000..b53a75e7e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_f128.c
@@ -0,0 +1,106 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT64 && defined FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_f128(
+     void trueFunction( float64_t, float128_t * ),
+     void subjFunction( float64_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_f64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_f64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_f16.c b/addins/TestFloat-3e/source/test_a_f64_z_f16.c
new file mode 100644
index 000000000..9f43160b4
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_f16.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#if defined FLOAT16 && defined FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_f16(
+     float16_t trueFunction( float64_t ), float16_t subjFunction( float64_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_f32.c b/addins/TestFloat-3e/source/test_a_f64_z_f32.c
new file mode 100644
index 000000000..48ece56be
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_f32.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_f32(
+     float32_t trueFunction( float64_t ), float32_t subjFunction( float64_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_i32_rx.c b/addins/TestFloat-3e/source/test_a_f64_z_i32_rx.c
new file mode 100644
index 000000000..9c0f5ffa7
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_i32_rx.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_i32_rx(
+     int_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     int_fast32_t subjFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f64_isNaN( genCases_f64_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_i32_x.c b/addins/TestFloat-3e/source/test_a_f64_z_i32_x.c
new file mode 100644
index 000000000..5ff5dcb7a
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_i32_x.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_i32_x(
+     int_fast32_t trueFunction( float64_t, bool ),
+     int_fast32_t subjFunction( float64_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f64_isNaN( genCases_f64_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_i64_rx.c b/addins/TestFloat-3e/source/test_a_f64_z_i64_rx.c
new file mode 100644
index 000000000..ead748726
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_i64_rx.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_i64_rx(
+     int_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     int_fast64_t subjFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f64_isNaN( genCases_f64_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_i64_x.c b/addins/TestFloat-3e/source/test_a_f64_z_i64_x.c
new file mode 100644
index 000000000..03ddce529
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_i64_x.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_i64_x(
+     int_fast64_t trueFunction( float64_t, bool ),
+     int_fast64_t subjFunction( float64_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f64_isNaN( genCases_f64_a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_ui32_rx.c b/addins/TestFloat-3e/source/test_a_f64_z_ui32_rx.c
new file mode 100644
index 000000000..0aecb2243
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_ui32_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_ui32_rx(
+     uint_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast32_t subjFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_ui32_x.c b/addins/TestFloat-3e/source/test_a_f64_z_ui32_x.c
new file mode 100644
index 000000000..7bf6282bc
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_ui32_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_ui32_x(
+     uint_fast32_t trueFunction( float64_t, bool ),
+     uint_fast32_t subjFunction( float64_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_ui64_rx.c b/addins/TestFloat-3e/source/test_a_f64_z_ui64_rx.c
new file mode 100644
index 000000000..48066f61e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_ui64_rx.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_ui64_rx(
+     uint_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast64_t subjFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_f64_z_ui64_x.c b/addins/TestFloat-3e/source/test_a_f64_z_ui64_x.c
new file mode 100644
index 000000000..65cecb460
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_f64_z_ui64_x.c
@@ -0,0 +1,102 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_f64_z_ui64_x(
+     uint_fast64_t trueFunction( float64_t, bool ),
+     uint_fast64_t subjFunction( float64_t, bool ),
+     bool exact
+ )
+{
+    int count;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i32_z_extF80.c b/addins/TestFloat-3e/source/test_a_i32_z_extF80.c
new file mode 100644
index 000000000..deb846e64
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i32_z_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i32_z_extF80(
+     void trueFunction( int32_t, extFloat80_t * ),
+     void subjFunction( int32_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_i32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( genCases_i32_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i32_z_f128.c b/addins/TestFloat-3e/source/test_a_i32_z_f128.c
new file mode 100644
index 000000000..ffb57412e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i32_z_f128.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i32_z_f128(
+     void trueFunction( int32_t, float128_t * ),
+     void subjFunction( int32_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_i32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( genCases_i32_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i32_z_f16.c b/addins/TestFloat-3e/source/test_a_i32_z_f16.c
new file mode 100644
index 000000000..350d70460
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i32_z_f16.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i32_z_f16(
+     float16_t trueFunction( int32_t ), float16_t subjFunction( int32_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( genCases_i32_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i32_z_f32.c b/addins/TestFloat-3e/source/test_a_i32_z_f32.c
new file mode 100644
index 000000000..cd8118aa5
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i32_z_f32.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i32_z_f32(
+     float32_t trueFunction( int32_t ), float32_t subjFunction( int32_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( genCases_i32_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_i32_z_f64.c b/addins/TestFloat-3e/source/test_a_i32_z_f64.c
new file mode 100644
index 000000000..f9a2feb5e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i32_z_f64.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i32_z_f64(
+     float64_t trueFunction( int32_t ), float64_t subjFunction( int32_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( genCases_i32_a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i64_z_extF80.c b/addins/TestFloat-3e/source/test_a_i64_z_extF80.c
new file mode 100644
index 000000000..c453ab28e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i64_z_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i64_z_extF80(
+     void trueFunction( int64_t, extFloat80_t * ),
+     void subjFunction( int64_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_i64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( genCases_i64_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i64_z_f128.c b/addins/TestFloat-3e/source/test_a_i64_z_f128.c
new file mode 100644
index 000000000..b79a75533
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i64_z_f128.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i64_z_f128(
+     void trueFunction( int64_t, float128_t * ),
+     void subjFunction( int64_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_i64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_i64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( genCases_i64_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i64_z_f16.c b/addins/TestFloat-3e/source/test_a_i64_z_f16.c
new file mode 100644
index 000000000..0f7f4e2a7
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i64_z_f16.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i64_z_f16(
+     float16_t trueFunction( int64_t ), float16_t subjFunction( int64_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( genCases_i64_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_i64_z_f32.c b/addins/TestFloat-3e/source/test_a_i64_z_f32.c
new file mode 100644
index 000000000..d5bfb0ac8
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i64_z_f32.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i64_z_f32(
+     float32_t trueFunction( int64_t ), float32_t subjFunction( int64_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( genCases_i64_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_i64_z_f64.c b/addins/TestFloat-3e/source/test_a_i64_z_f64.c
new file mode 100644
index 000000000..39b07e88e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_i64_z_f64.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_i64_z_f64(
+     float64_t trueFunction( int64_t ), float64_t subjFunction( int64_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_i64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_i64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_i64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_i64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( genCases_i64_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui32_z_extF80.c b/addins/TestFloat-3e/source/test_a_ui32_z_extF80.c
new file mode 100644
index 000000000..53d9b0861
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui32_z_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui32_z_extF80(
+     void trueFunction( uint32_t, extFloat80_t * ),
+     void subjFunction( uint32_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_ui32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( genCases_ui32_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui32_z_f128.c b/addins/TestFloat-3e/source/test_a_ui32_z_f128.c
new file mode 100644
index 000000000..cfa43b6b0
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui32_z_f128.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui32_z_f128(
+     void trueFunction( uint32_t, float128_t * ),
+     void subjFunction( uint32_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui32_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_ui32_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( genCases_ui32_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui32_z_f16.c b/addins/TestFloat-3e/source/test_a_ui32_z_f16.c
new file mode 100644
index 000000000..404d1d10e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui32_z_f16.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui32_z_f16(
+     float16_t trueFunction( uint32_t ), float16_t subjFunction( uint32_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( genCases_ui32_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui32_z_f32.c b/addins/TestFloat-3e/source/test_a_ui32_z_f32.c
new file mode 100644
index 000000000..c9618e15a
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui32_z_f32.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui32_z_f32(
+     float32_t trueFunction( uint32_t ), float32_t subjFunction( uint32_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( genCases_ui32_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_ui32_z_f64.c b/addins/TestFloat-3e/source/test_a_ui32_z_f64.c
new file mode 100644
index 000000000..00876b7f1
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui32_z_f64.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui32_z_f64(
+     float64_t trueFunction( uint32_t ), float64_t subjFunction( uint32_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( genCases_ui32_a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui64_z_extF80.c b/addins/TestFloat-3e/source/test_a_ui64_z_extF80.c
new file mode 100644
index 000000000..4e34e2002
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui64_z_extF80.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui64_z_extF80(
+     void trueFunction( uint64_t, extFloat80_t * ),
+     void subjFunction( uint64_t, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_ui64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( genCases_ui64_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui64_z_f128.c b/addins/TestFloat-3e/source/test_a_ui64_z_f128.c
new file mode 100644
index 000000000..81ca81cc8
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui64_z_f128.c
@@ -0,0 +1,101 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui64_z_f128(
+     void trueFunction( uint64_t, float128_t * ),
+     void subjFunction( uint64_t, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( genCases_ui64_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( genCases_ui64_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( genCases_ui64_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui64_z_f16.c b/addins/TestFloat-3e/source/test_a_ui64_z_f16.c
new file mode 100644
index 000000000..54e68badf
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui64_z_f16.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui64_z_f16(
+     float16_t trueFunction( uint64_t ), float16_t subjFunction( uint64_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( genCases_ui64_a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_a_ui64_z_f32.c b/addins/TestFloat-3e/source/test_a_ui64_z_f32.c
new file mode 100644
index 000000000..98a0f5020
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui64_z_f32.c
@@ -0,0 +1,95 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui64_z_f32(
+     float32_t trueFunction( uint64_t ), float32_t subjFunction( uint64_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( genCases_ui64_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_a_ui64_z_f64.c b/addins/TestFloat-3e/source/test_a_ui64_z_f64.c
new file mode 100644
index 000000000..2dc6c64a5
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_a_ui64_z_f64.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_a_ui64_z_f64(
+     float64_t trueFunction( uint64_t ), float64_t subjFunction( uint64_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_ui64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_ui64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_ui64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_ui64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( genCases_ui64_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_ab_extF80_z_bool.c b/addins/TestFloat-3e/source/test_ab_extF80_z_bool.c
new file mode 100644
index 000000000..3270b4f9d
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_ab_extF80_z_bool.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_ab_extF80_z_bool(
+     bool trueFunction( const extFloat80_t *, const extFloat80_t * ),
+     bool subjFunction( const extFloat80_t *, const extFloat80_t * )
+ )
+{
+    int count;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_extF80_a, &genCases_extF80_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_extF80_a, &genCases_extF80_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (extF80M_isSignalingNaN( &genCases_extF80_a )
+                            || extF80M_isSignalingNaN( &genCases_extF80_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_extF80M(
+                    &genCases_extF80_a, &genCases_extF80_b, "  " );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_ab_f128_z_bool.c b/addins/TestFloat-3e/source/test_ab_f128_z_bool.c
new file mode 100644
index 000000000..920420295
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_ab_f128_z_bool.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_ab_f128_z_bool(
+     bool trueFunction( const float128_t *, const float128_t * ),
+     bool subjFunction( const float128_t *, const float128_t * )
+ )
+{
+    int count;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &genCases_f128_a, &genCases_f128_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( &genCases_f128_a, &genCases_f128_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f128M_isSignalingNaN( &genCases_f128_a )
+                            || f128M_isSignalingNaN( &genCases_f128_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f128M( &genCases_f128_a, &genCases_f128_b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_ab_f16_z_bool.c b/addins/TestFloat-3e/source/test_ab_f16_z_bool.c
new file mode 100644
index 000000000..712aa71e4
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_ab_f16_z_bool.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_ab_f16_z_bool(
+     bool trueFunction( float16_t, float16_t ),
+     bool subjFunction( float16_t, float16_t )
+ )
+{
+    int count;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, genCases_f16_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, genCases_f16_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f16_isSignalingNaN( genCases_f16_a )
+                            || f16_isSignalingNaN( genCases_f16_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f16( genCases_f16_a, genCases_f16_b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_ab_f32_z_bool.c b/addins/TestFloat-3e/source/test_ab_f32_z_bool.c
new file mode 100644
index 000000000..01919d5e9
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_ab_f32_z_bool.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_ab_f32_z_bool(
+     bool trueFunction( float32_t, float32_t ),
+     bool subjFunction( float32_t, float32_t )
+ )
+{
+    int count;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, genCases_f32_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, genCases_f32_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f32_isSignalingNaN( genCases_f32_a )
+                            || f32_isSignalingNaN( genCases_f32_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f32( genCases_f32_a, genCases_f32_b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_ab_f64_z_bool.c b/addins/TestFloat-3e/source/test_ab_f64_z_bool.c
new file mode 100644
index 000000000..599b2bf46
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_ab_f64_z_bool.c
@@ -0,0 +1,103 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_ab_f64_z_bool(
+     bool trueFunction( float64_t, float64_t ),
+     bool subjFunction( float64_t, float64_t )
+ )
+{
+    int count;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, genCases_f64_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, genCases_f64_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f64_isSignalingNaN( genCases_f64_a )
+                            || f64_isSignalingNaN( genCases_f64_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f64( genCases_f64_a, genCases_f64_b, "  " );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abcz_f128.c b/addins/TestFloat-3e/source/test_abcz_f128.c
new file mode 100644
index 000000000..94f5bc06c
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abcz_f128.c
@@ -0,0 +1,125 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abcz_f128(
+     void
+      trueFunction(
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      ),
+     void
+      subjFunction(
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_abc_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_abc_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction(
+            &genCases_f128_a, &genCases_f128_b, &genCases_f128_c, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction(
+            &genCases_f128_a, &genCases_f128_b, &genCases_f128_c, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (   f128M_isSignalingNaN( &genCases_f128_a )
+                        || f128M_isSignalingNaN( &genCases_f128_b )
+                        || f128M_isSignalingNaN( &genCases_f128_c )
+                       )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f128M(
+                    &genCases_f128_a, &genCases_f128_b, &genCases_f128_c );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abcz_f16.c b/addins/TestFloat-3e/source/test_abcz_f16.c
new file mode 100644
index 000000000..6469cb4a3
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abcz_f16.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abcz_f16(
+     float16_t trueFunction( float16_t, float16_t, float16_t ),
+     float16_t subjFunction( float16_t, float16_t, float16_t )
+ )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_abc_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_abc_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, genCases_f16_b, genCases_f16_c );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, genCases_f16_b, genCases_f16_c );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   ! verCases_checkNaNs
+                && (   f16_isSignalingNaN( genCases_f16_a )
+                    || f16_isSignalingNaN( genCases_f16_b )
+                    || f16_isSignalingNaN( genCases_f16_c )
+                   )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f16(
+                    genCases_f16_a, genCases_f16_b, genCases_f16_c );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abcz_f32.c b/addins/TestFloat-3e/source/test_abcz_f32.c
new file mode 100644
index 000000000..48ae071b2
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abcz_f32.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abcz_f32(
+     float32_t trueFunction( float32_t, float32_t, float32_t ),
+     float32_t subjFunction( float32_t, float32_t, float32_t )
+ )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_abc_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_abc_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, genCases_f32_b, genCases_f32_c );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, genCases_f32_b, genCases_f32_c );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   ! verCases_checkNaNs
+                && (   f32_isSignalingNaN( genCases_f32_a )
+                    || f32_isSignalingNaN( genCases_f32_b )
+                    || f32_isSignalingNaN( genCases_f32_c )
+                   )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f32(
+                    genCases_f32_a, genCases_f32_b, genCases_f32_c );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_abcz_f64.c b/addins/TestFloat-3e/source/test_abcz_f64.c
new file mode 100644
index 000000000..36626a511
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abcz_f64.c
@@ -0,0 +1,111 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abcz_f64(
+     float64_t trueFunction( float64_t, float64_t, float64_t ),
+     float64_t subjFunction( float64_t, float64_t, float64_t )
+ )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_abc_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_abc_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, genCases_f64_b, genCases_f64_c );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, genCases_f64_b, genCases_f64_c );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   ! verCases_checkNaNs
+                && (   f64_isSignalingNaN( genCases_f64_a )
+                    || f64_isSignalingNaN( genCases_f64_b )
+                    || f64_isSignalingNaN( genCases_f64_c )
+                   )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f64(
+                    genCases_f64_a, genCases_f64_b, genCases_f64_c );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abz_extF80.c b/addins/TestFloat-3e/source/test_abz_extF80.c
new file mode 100644
index 000000000..c4239f07d
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abz_extF80.c
@@ -0,0 +1,113 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abz_extF80(
+     void
+      trueFunction(
+          const extFloat80_t *, const extFloat80_t *, extFloat80_t * ),
+     void
+      subjFunction(
+          const extFloat80_t *, const extFloat80_t *, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &genCases_extF80_b, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_extF80_a, &genCases_extF80_b, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (extF80M_isSignalingNaN( &genCases_extF80_a )
+                            || extF80M_isSignalingNaN( &genCases_extF80_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_extF80M(
+                    &genCases_extF80_a, &genCases_extF80_b, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abz_f128.c b/addins/TestFloat-3e/source/test_abz_f128.c
new file mode 100644
index 000000000..6fe68415e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abz_f128.c
@@ -0,0 +1,108 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abz_f128(
+     void trueFunction( const float128_t *, const float128_t *, float128_t * ),
+     void subjFunction( const float128_t *, const float128_t *, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &genCases_f128_b, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_f128_a, &genCases_f128_b, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f128M_isSignalingNaN( &genCases_f128_a )
+                            || f128M_isSignalingNaN( &genCases_f128_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f128M( &genCases_f128_a, &genCases_f128_b );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abz_f16.c b/addins/TestFloat-3e/source/test_abz_f16.c
new file mode 100644
index 000000000..cc5e9436f
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abz_f16.c
@@ -0,0 +1,108 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abz_f16(
+     float16_t trueFunction( float16_t, float16_t ),
+     float16_t subjFunction( float16_t, float16_t )
+ )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, genCases_f16_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, genCases_f16_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f16_isSignalingNaN( genCases_f16_a )
+                            || f16_isSignalingNaN( genCases_f16_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f16( genCases_f16_a, genCases_f16_b );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_abz_f32.c b/addins/TestFloat-3e/source/test_abz_f32.c
new file mode 100644
index 000000000..cd595b6c9
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abz_f32.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abz_f32(
+     float32_t trueFunction( float32_t, float32_t ),
+     float32_t subjFunction( float32_t, float32_t )
+ )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, genCases_f32_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, genCases_f32_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f32_isSignalingNaN( genCases_f32_a )
+                            || f32_isSignalingNaN( genCases_f32_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f32( genCases_f32_a, genCases_f32_b );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_abz_f64.c b/addins/TestFloat-3e/source/test_abz_f64.c
new file mode 100644
index 000000000..f54b90350
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_abz_f64.c
@@ -0,0 +1,108 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_abz_f64(
+     float64_t trueFunction( float64_t, float64_t ),
+     float64_t subjFunction( float64_t, float64_t )
+ )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_ab_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_ab_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, genCases_f64_b );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, genCases_f64_b );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f64_isSignalingNaN( genCases_f64_a )
+                            || f64_isSignalingNaN( genCases_f64_b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f64( genCases_f64_a, genCases_f64_b, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_extF80.c b/addins/TestFloat-3e/source/test_az_extF80.c
new file mode 100644
index 000000000..e1e6a4618
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_extF80.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_extF80(
+     void trueFunction( const extFloat80_t *, extFloat80_t * ),
+     void subjFunction( const extFloat80_t *, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_extF80_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_extF80_rx.c b/addins/TestFloat-3e/source/test_az_extF80_rx.c
new file mode 100644
index 000000000..91a7cbad2
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_extF80_rx.c
@@ -0,0 +1,112 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef EXTFLOAT80
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_extF80_rx(
+     void
+      trueFunction( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     void
+      subjFunction( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_extF80_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_extF80_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_extF80_a, roundingMode, exact, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_extF80_a, roundingMode, exact, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && extF80M_isSignalingNaN( &genCases_extF80_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &genCases_extF80_a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f128.c b/addins/TestFloat-3e/source/test_az_f128.c
new file mode 100644
index 000000000..f10e7415d
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f128.c
@@ -0,0 +1,107 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f128(
+     void trueFunction( const float128_t *, float128_t * ),
+     void subjFunction( const float128_t *, float128_t * )
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_f128_a, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f128_rx.c b/addins/TestFloat-3e/source/test_az_f128_rx.c
new file mode 100644
index 000000000..9c93e8a0a
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f128_rx.c
@@ -0,0 +1,110 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT128
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f128_rx(
+     void trueFunction( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     void subjFunction( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f128_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f128_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueFunction( &genCases_f128_a, roundingMode, exact, &trueZ );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjFunction( &genCases_f128_a, roundingMode, exact, &subjZ );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && f128M_isSignalingNaN( &genCases_f128_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &genCases_f128_a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f16.c b/addins/TestFloat-3e/source/test_az_f16.c
new file mode 100644
index 000000000..ef9f45a5e
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f16.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f16(
+     float16_t trueFunction( float16_t ), float16_t subjFunction( float16_t ) )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f16_rx.c b/addins/TestFloat-3e/source/test_az_f16_rx.c
new file mode 100644
index 000000000..11c37e832
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f16_rx.c
@@ -0,0 +1,109 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT16
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f16_rx(
+     float16_t trueFunction( float16_t, uint_fast8_t, bool ),
+     float16_t subjFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f16_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f16_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f16_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f16_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f16_isSignalingNaN( genCases_f16_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( genCases_f16_a );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f32.c b/addins/TestFloat-3e/source/test_az_f32.c
new file mode 100644
index 000000000..499c07b58
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f32.c
@@ -0,0 +1,100 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f32(
+     float32_t trueFunction( float32_t ), float32_t subjFunction( float32_t ) )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_az_f32_rx.c b/addins/TestFloat-3e/source/test_az_f32_rx.c
new file mode 100644
index 000000000..5aeecaaf3
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f32_rx.c
@@ -0,0 +1,105 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f32_rx(
+     float32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     float32_t subjFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f32_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f32_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f32_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f32_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f32_isSignalingNaN( genCases_f32_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( genCases_f32_a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
diff --git a/addins/TestFloat-3e/source/test_az_f64.c b/addins/TestFloat-3e/source/test_az_f64.c
new file mode 100644
index 000000000..24963142b
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f64.c
@@ -0,0 +1,104 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f64(
+     float64_t trueFunction( float64_t ), float64_t subjFunction( float64_t ) )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/test_az_f64_rx.c b/addins/TestFloat-3e/source/test_az_f64_rx.c
new file mode 100644
index 000000000..c146c7320
--- /dev/null
+++ b/addins/TestFloat-3e/source/test_az_f64_rx.c
@@ -0,0 +1,109 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+#ifdef FLOAT64
+
+#pragma STDC FENV_ACCESS ON
+
+void
+ test_az_f64_rx(
+     float64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     float64_t subjFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+
+    genCases_f64_a_init();
+    genCases_writeTestsTotal( testLoops_forever );
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! genCases_done || testLoops_forever ) {
+        genCases_f64_a_next();
+        *testLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( genCases_f64_a, roundingMode, exact );
+        trueFlags = *testLoops_trueFlagsPtr;
+        testLoops_subjFlagsFunction();
+        subjZ = subjFunction( genCases_f64_a, roundingMode, exact );
+        subjFlags = testLoops_subjFlagsFunction();
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs && f64_isSignalingNaN( genCases_f64_a )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( genCases_f64_a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/testfloat.c b/addins/TestFloat-3e/source/testfloat.c
new file mode 100644
index 000000000..f83ca6d60
--- /dev/null
+++ b/addins/TestFloat-3e/source/testfloat.c
@@ -0,0 +1,1715 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "subjfloat_config.h"
+#include "subjfloat.h"
+#include "functions.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "testLoops.h"
+
+static void catchSIGINT( int signalCode )
+{
+
+    if ( verCases_stop ) exit( EXIT_FAILURE );
+    verCases_stop = true;
+
+}
+
+static void (*subjFunctionPtr)();
+
+#ifdef FLOAT16
+typedef float16_t funcType_a_ui32_z_f16( uint32_t );
+#endif
+typedef float32_t funcType_a_ui32_z_f32( uint32_t );
+#ifdef FLOAT64
+typedef float64_t funcType_a_ui32_z_f64( uint32_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_ui32_z_extF80( uint32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_ui32_z_f128( uint32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+typedef float16_t funcType_a_ui64_z_f16( uint64_t );
+#endif
+typedef float32_t funcType_a_ui64_z_f32( uint64_t );
+#ifdef FLOAT64
+typedef float64_t funcType_a_ui64_z_f64( uint64_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_ui64_z_extF80( uint64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_ui64_z_f128( uint64_t, float128_t * );
+#endif
+#ifdef FLOAT16
+typedef float16_t funcType_a_i32_z_f16( int32_t );
+#endif
+typedef float32_t funcType_a_i32_z_f32( int32_t );
+#ifdef FLOAT64
+typedef float64_t funcType_a_i32_z_f64( int32_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_i32_z_extF80( int32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_i32_z_f128( int32_t, float128_t * );
+#endif
+#ifdef FLOAT16
+typedef float16_t funcType_a_i64_z_f16( int64_t );
+#endif
+typedef float32_t funcType_a_i64_z_f32( int64_t );
+#ifdef FLOAT64
+typedef float64_t funcType_a_i64_z_f64( int64_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_i64_z_extF80( int64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_i64_z_f128( int64_t, float128_t * );
+#endif
+
+#ifdef FLOAT16
+typedef uint_fast32_t funcType_a_f16_z_ui32( float16_t );
+typedef uint_fast64_t funcType_a_f16_z_ui64( float16_t );
+typedef int_fast32_t funcType_a_f16_z_i32( float16_t );
+typedef int_fast64_t funcType_a_f16_z_i64( float16_t );
+typedef float32_t funcType_a_f16_z_f32( float16_t );
+#ifdef FLOAT64
+typedef float64_t funcType_a_f16_z_f64( float16_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_f16_z_extF80( float16_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_f16_z_f128( float16_t, float128_t * );
+#endif
+typedef float16_t funcType_az_f16( float16_t );
+typedef float16_t funcType_abz_f16( float16_t, float16_t );
+typedef float16_t funcType_abcz_f16( float16_t, float16_t, float16_t );
+typedef bool funcType_ab_f16_z_bool( float16_t, float16_t );
+#endif
+
+typedef uint_fast32_t funcType_a_f32_z_ui32( float32_t );
+typedef uint_fast64_t funcType_a_f32_z_ui64( float32_t );
+typedef int_fast32_t funcType_a_f32_z_i32( float32_t );
+typedef int_fast64_t funcType_a_f32_z_i64( float32_t );
+#ifdef FLOAT16
+typedef float16_t funcType_a_f32_z_f16( float32_t );
+#endif
+#ifdef FLOAT64
+typedef float64_t funcType_a_f32_z_f64( float32_t );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_f32_z_extF80( float32_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_f32_z_f128( float32_t, float128_t * );
+#endif
+typedef float32_t funcType_az_f32( float32_t );
+typedef float32_t funcType_abz_f32( float32_t, float32_t );
+typedef float32_t funcType_abcz_f32( float32_t, float32_t, float32_t );
+typedef bool funcType_ab_f32_z_bool( float32_t, float32_t );
+
+#ifdef FLOAT64
+typedef uint_fast32_t funcType_a_f64_z_ui32( float64_t );
+typedef uint_fast64_t funcType_a_f64_z_ui64( float64_t );
+typedef int_fast32_t funcType_a_f64_z_i32( float64_t );
+typedef int_fast64_t funcType_a_f64_z_i64( float64_t );
+#ifdef FLOAT16
+typedef float16_t funcType_a_f64_z_f16( float64_t );
+#endif
+typedef float32_t funcType_a_f64_z_f32( float64_t );
+#ifdef EXTFLOAT80
+typedef void funcType_a_f64_z_extF80( float64_t, extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_f64_z_f128( float64_t, float128_t * );
+#endif
+typedef float64_t funcType_az_f64( float64_t );
+typedef float64_t funcType_abz_f64( float64_t, float64_t );
+typedef float64_t funcType_abcz_f64( float64_t, float64_t, float64_t );
+typedef bool funcType_ab_f64_z_bool( float64_t, float64_t );
+#endif
+
+#ifdef EXTFLOAT80
+typedef uint_fast32_t funcType_a_extF80_z_ui32( const extFloat80_t * );
+typedef uint_fast64_t funcType_a_extF80_z_ui64( const extFloat80_t * );
+typedef int_fast32_t funcType_a_extF80_z_i32( const extFloat80_t * );
+typedef int_fast64_t funcType_a_extF80_z_i64( const extFloat80_t * );
+#ifdef FLOAT16
+typedef float16_t funcType_a_extF80_z_f16( const extFloat80_t * );
+#endif
+typedef float32_t funcType_a_extF80_z_f32( const extFloat80_t * );
+#ifdef FLOAT64
+typedef float64_t funcType_a_extF80_z_f64( const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+typedef void funcType_a_extF80_z_f128( const extFloat80_t *, float128_t * );
+#endif
+typedef void funcType_az_extF80( const extFloat80_t *, extFloat80_t * );
+typedef
+ void
+  funcType_abz_extF80(
+      const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+typedef
+ bool funcType_ab_extF80_z_bool( const extFloat80_t *, const extFloat80_t * );
+#endif
+
+#ifdef FLOAT128
+typedef uint_fast32_t funcType_a_f128_z_ui32( const float128_t * );
+typedef uint_fast64_t funcType_a_f128_z_ui64( const float128_t * );
+typedef int_fast32_t funcType_a_f128_z_i32( const float128_t * );
+typedef int_fast64_t funcType_a_f128_z_i64( const float128_t * );
+#ifdef FLOAT16
+typedef float16_t funcType_a_f128_z_f16( const float128_t * );
+#endif
+typedef float32_t funcType_a_f128_z_f32( const float128_t * );
+#ifdef FLOAT64
+typedef float64_t funcType_a_f128_z_f64( const float128_t * );
+#endif
+#ifdef EXTFLOAT80
+typedef void funcType_a_f128_z_extF80( const float128_t *, extFloat80_t * );
+#endif
+typedef void funcType_az_f128( const float128_t *, float128_t * );
+typedef
+ void
+  funcType_abz_f128( const float128_t *, const float128_t *, float128_t * );
+typedef
+ void
+  funcType_abcz_f128(
+      const float128_t *, const float128_t *, const float128_t *, float128_t *
+  );
+typedef bool funcType_ab_f128_z_bool( const float128_t *, const float128_t * );
+#endif
+
+#ifdef FLOAT16
+
+static
+uint_fast32_t
+ subjFunction_a_f16_z_ui32_rx(
+     float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f16_z_ui32 *) subjFunctionPtr)( a );
+
+}
+
+static
+uint_fast64_t
+ subjFunction_a_f16_z_ui64_rx(
+     float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f16_z_ui64 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast32_t
+ subjFunction_a_f16_z_i32_rx(
+     float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f16_z_i32 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast64_t
+ subjFunction_a_f16_z_i64_rx(
+     float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f16_z_i64 *) subjFunctionPtr)( a );
+
+}
+
+static
+float16_t
+ subjFunction_az_f16_rx( float16_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_az_f16 *) subjFunctionPtr)( a );
+
+}
+
+#endif
+
+static
+uint_fast32_t
+ subjFunction_a_f32_z_ui32_rx(
+     float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f32_z_ui32 *) subjFunctionPtr)( a );
+
+}
+
+static
+uint_fast64_t
+ subjFunction_a_f32_z_ui64_rx(
+     float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f32_z_ui64 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast32_t
+ subjFunction_a_f32_z_i32_rx(
+     float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f32_z_i32 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast64_t
+ subjFunction_a_f32_z_i64_rx(
+     float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f32_z_i64 *) subjFunctionPtr)( a );
+
+}
+
+static
+float32_t
+ subjFunction_az_f32_rx( float32_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_az_f32 *) subjFunctionPtr)( a );
+
+}
+
+#ifdef FLOAT64
+
+static
+uint_fast32_t
+ subjFunction_a_f64_z_ui32_rx(
+     float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f64_z_ui32 *) subjFunctionPtr)( a );
+
+}
+
+static
+uint_fast64_t
+ subjFunction_a_f64_z_ui64_rx(
+     float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f64_z_ui64 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast32_t
+ subjFunction_a_f64_z_i32_rx(
+     float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f64_z_i32 *) subjFunctionPtr)( a );
+
+}
+
+static
+int_fast64_t
+ subjFunction_a_f64_z_i64_rx(
+     float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f64_z_i64 *) subjFunctionPtr)( a );
+
+}
+
+static
+float64_t
+ subjFunction_az_f64_rx( float64_t a, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_az_f64 *) subjFunctionPtr)( a );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static
+uint_fast32_t
+ subjFunction_a_extF80_z_ui32_rx(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_extF80_z_ui32 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+uint_fast64_t
+ subjFunction_a_extF80_z_ui64_rx(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_extF80_z_ui64 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+int_fast32_t
+ subjFunction_a_extF80_z_i32_rx(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_extF80_z_i32 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+int_fast64_t
+ subjFunction_a_extF80_z_i64_rx(
+     const extFloat80_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_extF80_z_i64 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+void
+ subjFunction_az_extF80_rx(
+     const extFloat80_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     extFloat80_t *zPtr
+ )
+{
+
+    return ((funcType_az_extF80 *) subjFunctionPtr)( aPtr, zPtr );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static
+uint_fast32_t
+ subjFunction_a_f128_z_ui32_rx(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f128_z_ui32 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+uint_fast64_t
+ subjFunction_a_f128_z_ui64_rx(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f128_z_ui64 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+int_fast32_t
+ subjFunction_a_f128_z_i32_rx(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f128_z_i32 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+int_fast64_t
+ subjFunction_a_f128_z_i64_rx(
+     const float128_t *aPtr, uint_fast8_t roundingMode, bool exact )
+{
+
+    return ((funcType_a_f128_z_i64 *) subjFunctionPtr)( aPtr );
+
+}
+
+static
+void
+ subjFunction_az_f128_rx(
+     const float128_t *aPtr,
+     uint_fast8_t roundingMode,
+     bool exact,
+     float128_t *zPtr
+ )
+{
+
+    return ((funcType_az_f128 *) subjFunctionPtr)( aPtr, zPtr );
+
+}
+
+#endif
+
+static
+void
+ testFunctionInstance(
+     int functionCode, uint_fast8_t roundingMode, bool exact )
+{
+#ifdef FLOAT16
+    funcType_abz_f16 *trueFunction_abz_f16;
+    funcType_ab_f16_z_bool *trueFunction_ab_f16_z_bool;
+#endif
+    funcType_abz_f32 *trueFunction_abz_f32;
+    funcType_ab_f32_z_bool *trueFunction_ab_f32_z_bool;
+#ifdef FLOAT64
+    funcType_abz_f64 *trueFunction_abz_f64;
+    funcType_ab_f64_z_bool *trueFunction_ab_f64_z_bool;
+#endif
+#ifdef EXTFLOAT80
+    funcType_abz_extF80 *trueFunction_abz_extF80;
+    funcType_ab_extF80_z_bool *trueFunction_ab_extF80_z_bool;
+#endif
+#ifdef FLOAT128
+    funcType_abz_f128 *trueFunction_abz_f128;
+    funcType_ab_f128_z_bool *trueFunction_ab_f128_z_bool;
+#endif
+
+    fputs( "Testing ", stderr );
+    verCases_writeFunctionName( stderr );
+    fputs( ".\n", stderr );
+    switch ( functionCode ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+#ifdef SUBJ_UI32_TO_F16
+     case UI32_TO_F16:
+        test_a_ui32_z_f16(
+            ui32_to_f16, (funcType_a_ui32_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_UI32_TO_F32
+     case UI32_TO_F32:
+        test_a_ui32_z_f32(
+            ui32_to_f32, (funcType_a_ui32_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_UI32_TO_F64
+     case UI32_TO_F64:
+        test_a_ui32_z_f64(
+            ui32_to_f64, (funcType_a_ui32_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_UI32_TO_EXTF80
+     case UI32_TO_EXTF80:
+        test_a_ui32_z_extF80(
+            ui32_to_extF80M, (funcType_a_ui32_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_UI32_TO_F128
+     case UI32_TO_F128:
+        test_a_ui32_z_f128(
+            ui32_to_f128M, (funcType_a_ui32_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_UI64_TO_F16
+     case UI64_TO_F16:
+        test_a_ui64_z_f16(
+            ui64_to_f16, (funcType_a_ui64_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_UI64_TO_F32
+     case UI64_TO_F32:
+        test_a_ui64_z_f32(
+            ui64_to_f32, (funcType_a_ui64_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_UI64_TO_F64
+     case UI64_TO_F64:
+        test_a_ui64_z_f64(
+            ui64_to_f64, (funcType_a_ui64_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_UI64_TO_EXTF80
+     case UI64_TO_EXTF80:
+        test_a_ui64_z_extF80(
+            ui64_to_extF80M, (funcType_a_ui64_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_UI64_TO_F128
+     case UI64_TO_F128:
+        test_a_ui64_z_f128(
+            ui64_to_f128M, (funcType_a_ui64_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_I32_TO_F16
+     case I32_TO_F16:
+        test_a_i32_z_f16(
+            i32_to_f16, (funcType_a_i32_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_I32_TO_F32
+     case I32_TO_F32:
+        test_a_i32_z_f32(
+            i32_to_f32, (funcType_a_i32_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_I32_TO_F64
+     case I32_TO_F64:
+        test_a_i32_z_f64(
+            i32_to_f64, (funcType_a_i32_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_I32_TO_EXTF80
+     case I32_TO_EXTF80:
+        test_a_i32_z_extF80(
+            i32_to_extF80M, (funcType_a_i32_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_I32_TO_F128
+     case I32_TO_F128:
+        test_a_i32_z_f128(
+            i32_to_f128M, (funcType_a_i32_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT16
+#ifdef SUBJ_I64_TO_F16
+     case I64_TO_F16:
+        test_a_i64_z_f16(
+            i64_to_f16, (funcType_a_i64_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_I64_TO_F32
+     case I64_TO_F32:
+        test_a_i64_z_f32(
+            i64_to_f32, (funcType_a_i64_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_I64_TO_F64
+     case I64_TO_F64:
+        test_a_i64_z_f64(
+            i64_to_f64, (funcType_a_i64_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_I64_TO_EXTF80
+     case I64_TO_EXTF80:
+        test_a_i64_z_extF80(
+            i64_to_extF80M, (funcType_a_i64_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_I64_TO_F128
+     case I64_TO_F128:
+        test_a_i64_z_f128(
+            i64_to_f128M, (funcType_a_i64_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case F16_TO_UI32:
+        test_a_f16_z_ui32_rx(
+            f16_to_ui32, subjFunction_a_f16_z_ui32_rx, roundingMode, exact );
+        break;
+     case F16_TO_UI64:
+        test_a_f16_z_ui64_rx(
+            f16_to_ui64, subjFunction_a_f16_z_ui64_rx, roundingMode, exact );
+        break;
+     case F16_TO_I32:
+        test_a_f16_z_i32_rx(
+            f16_to_i32, subjFunction_a_f16_z_i32_rx, roundingMode, exact );
+        break;
+     case F16_TO_I64:
+        test_a_f16_z_i64_rx(
+            f16_to_i64, subjFunction_a_f16_z_i64_rx, roundingMode, exact );
+        break;
+#ifdef SUBJ_F16_TO_F32
+     case F16_TO_F32:
+        test_a_f16_z_f32(
+            f16_to_f32, (funcType_a_f16_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F16_TO_F64
+     case F16_TO_F64:
+        test_a_f16_z_f64(
+            f16_to_f64, (funcType_a_f16_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F16_TO_EXTF80
+     case F16_TO_EXTF80:
+        test_a_f16_z_extF80(
+            f16_to_extF80M, (funcType_a_f16_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F16_TO_F128
+     case F16_TO_F128:
+        test_a_f16_z_f128(
+            f16_to_f128M, (funcType_a_f16_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+     case F16_ROUNDTOINT:
+        test_az_f16_rx(
+            f16_roundToInt, subjFunction_az_f16_rx, roundingMode, exact );
+        break;
+#ifdef SUBJ_F16_ADD
+     case F16_ADD:
+        trueFunction_abz_f16 = f16_add;
+        goto test_abz_f16;
+#endif
+#ifdef SUBJ_F16_SUB
+     case F16_SUB:
+        trueFunction_abz_f16 = f16_sub;
+        goto test_abz_f16;
+#endif
+#ifdef SUBJ_F16_MUL
+     case F16_MUL:
+        trueFunction_abz_f16 = f16_mul;
+        goto test_abz_f16;
+#endif
+#ifdef SUBJ_F16_MULADD
+     case F16_MULADD:
+        test_abcz_f16( f16_mulAdd, (funcType_abcz_f16 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F16_DIV
+     case F16_DIV:
+        trueFunction_abz_f16 = f16_div;
+        goto test_abz_f16;
+#endif
+#ifdef SUBJ_F16_REM
+     case F16_REM:
+        trueFunction_abz_f16 = f16_rem;
+        goto test_abz_f16;
+#endif
+     test_abz_f16:
+        test_abz_f16(
+            trueFunction_abz_f16, (funcType_abz_f16 *) subjFunctionPtr );
+        break;
+#ifdef SUBJ_F16_SQRT
+     case F16_SQRT:
+        test_az_f16( f16_sqrt, (funcType_az_f16 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F16_EQ
+     case F16_EQ:
+        trueFunction_ab_f16_z_bool = f16_eq;
+        goto test_ab_f16_z_bool;
+#endif
+#ifdef SUBJ_F16_LE
+     case F16_LE:
+        trueFunction_ab_f16_z_bool = f16_le;
+        goto test_ab_f16_z_bool;
+#endif
+#ifdef SUBJ_F16_LT
+     case F16_LT:
+        trueFunction_ab_f16_z_bool = f16_lt;
+        goto test_ab_f16_z_bool;
+#endif
+#ifdef SUBJ_F16_EQ_SIGNALING
+     case F16_EQ_SIGNALING:
+        trueFunction_ab_f16_z_bool = f16_eq_signaling;
+        goto test_ab_f16_z_bool;
+#endif
+#ifdef SUBJ_F16_LE_QUIET
+     case F16_LE_QUIET:
+        trueFunction_ab_f16_z_bool = f16_le_quiet;
+        goto test_ab_f16_z_bool;
+#endif
+#ifdef SUBJ_F16_LT_QUIET
+     case F16_LT_QUIET:
+        trueFunction_ab_f16_z_bool = f16_lt_quiet;
+        goto test_ab_f16_z_bool;
+#endif
+     test_ab_f16_z_bool:
+        test_ab_f16_z_bool(
+            trueFunction_ab_f16_z_bool,
+            (funcType_ab_f16_z_bool *) subjFunctionPtr
+        );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case F32_TO_UI32:
+        test_a_f32_z_ui32_rx(
+            f32_to_ui32, subjFunction_a_f32_z_ui32_rx, roundingMode, exact );
+        break;
+     case F32_TO_UI64:
+        test_a_f32_z_ui64_rx(
+            f32_to_ui64, subjFunction_a_f32_z_ui64_rx, roundingMode, exact );
+        break;
+     case F32_TO_I32:
+        test_a_f32_z_i32_rx(
+            f32_to_i32, subjFunction_a_f32_z_i32_rx, roundingMode, exact );
+        break;
+     case F32_TO_I64:
+        test_a_f32_z_i64_rx(
+            f32_to_i64, subjFunction_a_f32_z_i64_rx, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+#ifdef SUBJ_F32_TO_F16
+     case F32_TO_F16:
+        test_a_f32_z_f16(
+            f32_to_f16, (funcType_a_f32_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F32_TO_F64
+     case F32_TO_F64:
+        test_a_f32_z_f64(
+            f32_to_f64, (funcType_a_f32_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F32_TO_EXTF80
+     case F32_TO_EXTF80:
+        test_a_f32_z_extF80(
+            f32_to_extF80M, (funcType_a_f32_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F32_TO_F128
+     case F32_TO_F128:
+        test_a_f32_z_f128(
+            f32_to_f128M, (funcType_a_f32_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+     case F32_ROUNDTOINT:
+        test_az_f32_rx(
+            f32_roundToInt, subjFunction_az_f32_rx, roundingMode, exact );
+        break;
+#ifdef SUBJ_F32_ADD
+     case F32_ADD:
+        trueFunction_abz_f32 = f32_add;
+        goto test_abz_f32;
+#endif
+#ifdef SUBJ_F32_SUB
+     case F32_SUB:
+        trueFunction_abz_f32 = f32_sub;
+        goto test_abz_f32;
+#endif
+#ifdef SUBJ_F32_MUL
+     case F32_MUL:
+        trueFunction_abz_f32 = f32_mul;
+        goto test_abz_f32;
+#endif
+#ifdef SUBJ_F32_MULADD
+     case F32_MULADD:
+        test_abcz_f32( f32_mulAdd, (funcType_abcz_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F32_DIV
+     case F32_DIV:
+        trueFunction_abz_f32 = f32_div;
+        goto test_abz_f32;
+#endif
+#ifdef SUBJ_F32_REM
+     case F32_REM:
+        trueFunction_abz_f32 = f32_rem;
+        goto test_abz_f32;
+#endif
+     test_abz_f32:
+        test_abz_f32(
+            trueFunction_abz_f32, (funcType_abz_f32 *) subjFunctionPtr );
+        break;
+#ifdef SUBJ_F32_SQRT
+     case F32_SQRT:
+        test_az_f32( f32_sqrt, (funcType_az_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F32_EQ
+     case F32_EQ:
+        trueFunction_ab_f32_z_bool = f32_eq;
+        goto test_ab_f32_z_bool;
+#endif
+#ifdef SUBJ_F32_LE
+     case F32_LE:
+        trueFunction_ab_f32_z_bool = f32_le;
+        goto test_ab_f32_z_bool;
+#endif
+#ifdef SUBJ_F32_LT
+     case F32_LT:
+        trueFunction_ab_f32_z_bool = f32_lt;
+        goto test_ab_f32_z_bool;
+#endif
+#ifdef SUBJ_F32_EQ_SIGNALING
+     case F32_EQ_SIGNALING:
+        trueFunction_ab_f32_z_bool = f32_eq_signaling;
+        goto test_ab_f32_z_bool;
+#endif
+#ifdef SUBJ_F32_LE_QUIET
+     case F32_LE_QUIET:
+        trueFunction_ab_f32_z_bool = f32_le_quiet;
+        goto test_ab_f32_z_bool;
+#endif
+#ifdef SUBJ_F32_LT_QUIET
+     case F32_LT_QUIET:
+        trueFunction_ab_f32_z_bool = f32_lt_quiet;
+        goto test_ab_f32_z_bool;
+#endif
+     test_ab_f32_z_bool:
+        test_ab_f32_z_bool(
+            trueFunction_ab_f32_z_bool,
+            (funcType_ab_f32_z_bool *) subjFunctionPtr
+        );
+        break;
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT64
+     case F64_TO_UI32:
+        test_a_f64_z_ui32_rx(
+            f64_to_ui32, subjFunction_a_f64_z_ui32_rx, roundingMode, exact );
+        break;
+     case F64_TO_UI64:
+        test_a_f64_z_ui64_rx(
+            f64_to_ui64, subjFunction_a_f64_z_ui64_rx, roundingMode, exact );
+        break;
+     case F64_TO_I32:
+        test_a_f64_z_i32_rx(
+            f64_to_i32, subjFunction_a_f64_z_i32_rx, roundingMode, exact );
+        break;
+     case F64_TO_I64:
+        test_a_f64_z_i64_rx(
+            f64_to_i64, subjFunction_a_f64_z_i64_rx, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+#ifdef SUBJ_F64_TO_F16
+     case F64_TO_F16:
+        test_a_f64_z_f16(
+            f64_to_f16, (funcType_a_f64_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_F64_TO_F32
+     case F64_TO_F32:
+        test_a_f64_z_f32(
+            f64_to_f32, (funcType_a_f64_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F64_TO_EXTF80
+     case F64_TO_EXTF80:
+        test_a_f64_z_extF80(
+            f64_to_extF80M, (funcType_a_f64_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_F64_TO_F128
+     case F64_TO_F128:
+        test_a_f64_z_f128(
+            f64_to_f128M, (funcType_a_f64_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+     case F64_ROUNDTOINT:
+        test_az_f64_rx(
+            f64_roundToInt, subjFunction_az_f64_rx, roundingMode, exact );
+        break;
+#ifdef SUBJ_F64_ADD
+     case F64_ADD:
+        trueFunction_abz_f64 = f64_add;
+        goto test_abz_f64;
+#endif
+#ifdef SUBJ_F64_SUB
+     case F64_SUB:
+        trueFunction_abz_f64 = f64_sub;
+        goto test_abz_f64;
+#endif
+#ifdef SUBJ_F64_MUL
+     case F64_MUL:
+        trueFunction_abz_f64 = f64_mul;
+        goto test_abz_f64;
+#endif
+#ifdef SUBJ_F64_MULADD
+     case F64_MULADD:
+        test_abcz_f64( f64_mulAdd, (funcType_abcz_f64 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F64_DIV
+     case F64_DIV:
+        trueFunction_abz_f64 = f64_div;
+        goto test_abz_f64;
+#endif
+#ifdef SUBJ_F64_REM
+     case F64_REM:
+        trueFunction_abz_f64 = f64_rem;
+        goto test_abz_f64;
+#endif
+     test_abz_f64:
+        test_abz_f64(
+            trueFunction_abz_f64, (funcType_abz_f64 *) subjFunctionPtr );
+        break;
+#ifdef SUBJ_F64_SQRT
+     case F64_SQRT:
+        test_az_f64( f64_sqrt, (funcType_az_f64 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F64_EQ
+     case F64_EQ:
+        trueFunction_ab_f64_z_bool = f64_eq;
+        goto test_ab_f64_z_bool;
+#endif
+#ifdef SUBJ_F64_LE
+     case F64_LE:
+        trueFunction_ab_f64_z_bool = f64_le;
+        goto test_ab_f64_z_bool;
+#endif
+#ifdef SUBJ_F64_LT
+     case F64_LT:
+        trueFunction_ab_f64_z_bool = f64_lt;
+        goto test_ab_f64_z_bool;
+#endif
+#ifdef SUBJ_F64_EQ_SIGNALING
+     case F64_EQ_SIGNALING:
+        trueFunction_ab_f64_z_bool = f64_eq_signaling;
+        goto test_ab_f64_z_bool;
+#endif
+#ifdef SUBJ_F64_LE_QUIET
+     case F64_LE_QUIET:
+        trueFunction_ab_f64_z_bool = f64_le_quiet;
+        goto test_ab_f64_z_bool;
+#endif
+#ifdef SUBJ_F64_LT_QUIET
+     case F64_LT_QUIET:
+        trueFunction_ab_f64_z_bool = f64_lt_quiet;
+        goto test_ab_f64_z_bool;
+#endif
+     test_ab_f64_z_bool:
+        test_ab_f64_z_bool(
+            trueFunction_ab_f64_z_bool,
+            (funcType_ab_f64_z_bool *) subjFunctionPtr
+        );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+     case EXTF80_TO_UI32:
+        test_a_extF80_z_ui32_rx(
+            extF80M_to_ui32,
+            subjFunction_a_extF80_z_ui32_rx,
+            roundingMode,
+            exact
+        );
+        break;
+     case EXTF80_TO_UI64:
+        test_a_extF80_z_ui64_rx(
+            extF80M_to_ui64,
+            subjFunction_a_extF80_z_ui64_rx,
+            roundingMode,
+            exact
+        );
+        break;
+     case EXTF80_TO_I32:
+        test_a_extF80_z_i32_rx(
+            extF80M_to_i32, subjFunction_a_extF80_z_i32_rx, roundingMode, exact
+        );
+        break;
+     case EXTF80_TO_I64:
+        test_a_extF80_z_i64_rx(
+            extF80M_to_i64, subjFunction_a_extF80_z_i64_rx, roundingMode, exact
+        );
+        break;
+#ifdef FLOAT16
+#ifdef SUBJ_EXTF80_TO_F16
+     case EXTF80_TO_F16:
+        test_a_extF80_z_f16(
+            extF80M_to_f16, (funcType_a_extF80_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_EXTF80_TO_F32
+     case EXTF80_TO_F32:
+        test_a_extF80_z_f32(
+            extF80M_to_f32, (funcType_a_extF80_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_EXTF80_TO_F64
+     case EXTF80_TO_F64:
+        test_a_extF80_z_f64(
+            extF80M_to_f64, (funcType_a_extF80_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef FLOAT128
+#ifdef SUBJ_EXTF80_TO_F128
+     case EXTF80_TO_F128:
+        test_a_extF80_z_f128(
+            extF80M_to_f128M, (funcType_a_extF80_z_f128 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+     case EXTF80_ROUNDTOINT:
+        test_az_extF80_rx(
+            extF80M_roundToInt, subjFunction_az_extF80_rx, roundingMode, exact
+        );
+        break;
+#ifdef SUBJ_EXTF80_ADD
+     case EXTF80_ADD:
+        trueFunction_abz_extF80 = extF80M_add;
+        goto test_abz_extF80;
+#endif
+#ifdef SUBJ_EXTF80_SUB
+     case EXTF80_SUB:
+        trueFunction_abz_extF80 = extF80M_sub;
+        goto test_abz_extF80;
+#endif
+#ifdef SUBJ_EXTF80_MUL
+     case EXTF80_MUL:
+        trueFunction_abz_extF80 = extF80M_mul;
+        goto test_abz_extF80;
+#endif
+#ifdef SUBJ_EXTF80_DIV
+     case EXTF80_DIV:
+        trueFunction_abz_extF80 = extF80M_div;
+        goto test_abz_extF80;
+#endif
+#ifdef SUBJ_EXTF80_REM
+     case EXTF80_REM:
+        trueFunction_abz_extF80 = extF80M_rem;
+        goto test_abz_extF80;
+#endif
+     test_abz_extF80:
+        test_abz_extF80(
+            trueFunction_abz_extF80, (funcType_abz_extF80 *) subjFunctionPtr );
+        break;
+#ifdef SUBJ_EXTF80_SQRT
+     case EXTF80_SQRT:
+        test_az_extF80( extF80M_sqrt, (funcType_az_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_EXTF80_EQ
+     case EXTF80_EQ:
+        trueFunction_ab_extF80_z_bool = extF80M_eq;
+        goto test_ab_extF80_z_bool;
+#endif
+#ifdef SUBJ_EXTF80_LE
+     case EXTF80_LE:
+        trueFunction_ab_extF80_z_bool = extF80M_le;
+        goto test_ab_extF80_z_bool;
+#endif
+#ifdef SUBJ_EXTF80_LT
+     case EXTF80_LT:
+        trueFunction_ab_extF80_z_bool = extF80M_lt;
+        goto test_ab_extF80_z_bool;
+#endif
+#ifdef SUBJ_EXTF80_EQ_SIGNALING
+     case EXTF80_EQ_SIGNALING:
+        trueFunction_ab_extF80_z_bool = extF80M_eq_signaling;
+        goto test_ab_extF80_z_bool;
+#endif
+#ifdef SUBJ_EXTF80_LE_QUIET
+     case EXTF80_LE_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_le_quiet;
+        goto test_ab_extF80_z_bool;
+#endif
+#ifdef SUBJ_EXTF80_LT_QUIET
+     case EXTF80_LT_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_lt_quiet;
+        goto test_ab_extF80_z_bool;
+#endif
+     test_ab_extF80_z_bool:
+        test_ab_extF80_z_bool(
+            trueFunction_ab_extF80_z_bool,
+            (funcType_ab_extF80_z_bool *) subjFunctionPtr
+        );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT128
+     case F128_TO_UI32:
+        test_a_f128_z_ui32_rx(
+            f128M_to_ui32, subjFunction_a_f128_z_ui32_rx, roundingMode, exact
+        );
+        break;
+     case F128_TO_UI64:
+        test_a_f128_z_ui64_rx(
+            f128M_to_ui64, subjFunction_a_f128_z_ui64_rx, roundingMode, exact
+        );
+        break;
+     case F128_TO_I32:
+        test_a_f128_z_i32_rx(
+            f128M_to_i32, subjFunction_a_f128_z_i32_rx, roundingMode, exact );
+        break;
+     case F128_TO_I64:
+        test_a_f128_z_i64_rx(
+            f128M_to_i64, subjFunction_a_f128_z_i64_rx, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+#ifdef SUBJ_F128_TO_F16
+     case F128_TO_F16:
+        test_a_f128_z_f16(
+            f128M_to_f16, (funcType_a_f128_z_f16 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef SUBJ_F128_TO_F32
+     case F128_TO_F32:
+        test_a_f128_z_f32(
+            f128M_to_f32, (funcType_a_f128_z_f32 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef FLOAT64
+#ifdef SUBJ_F128_TO_F64
+     case F128_TO_F64:
+        test_a_f128_z_f64(
+            f128M_to_f64, (funcType_a_f128_z_f64 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+#ifdef EXTFLOAT80
+#ifdef SUBJ_F128_TO_EXTF80
+     case F128_TO_EXTF80:
+        test_a_f128_z_extF80(
+            f128M_to_extF80M, (funcType_a_f128_z_extF80 *) subjFunctionPtr );
+        break;
+#endif
+#endif
+     case F128_ROUNDTOINT:
+        test_az_f128_rx(
+            f128M_roundToInt, subjFunction_az_f128_rx, roundingMode, exact );
+        break;
+#ifdef SUBJ_F128_ADD
+     case F128_ADD:
+        trueFunction_abz_f128 = f128M_add;
+        goto test_abz_f128;
+#endif
+#ifdef SUBJ_F128_SUB
+     case F128_SUB:
+        trueFunction_abz_f128 = f128M_sub;
+        goto test_abz_f128;
+#endif
+#ifdef SUBJ_F128_MUL
+     case F128_MUL:
+        trueFunction_abz_f128 = f128M_mul;
+        goto test_abz_f128;
+#endif
+#ifdef SUBJ_F128_MULADD
+     case F128_MULADD:
+        test_abcz_f128( f128M_mulAdd, (funcType_abcz_f128 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F128_DIV
+     case F128_DIV:
+        trueFunction_abz_f128 = f128M_div;
+        goto test_abz_f128;
+#endif
+#ifdef SUBJ_F128_REM
+     case F128_REM:
+        trueFunction_abz_f128 = f128M_rem;
+        goto test_abz_f128;
+#endif
+     test_abz_f128:
+        test_abz_f128(
+            trueFunction_abz_f128, (funcType_abz_f128 *) subjFunctionPtr );
+        break;
+#ifdef SUBJ_F128_SQRT
+     case F128_SQRT:
+        test_az_f128( f128M_sqrt, (funcType_az_f128 *) subjFunctionPtr );
+        break;
+#endif
+#ifdef SUBJ_F128_EQ
+     case F128_EQ:
+        trueFunction_ab_f128_z_bool = f128M_eq;
+        goto test_ab_f128_z_bool;
+#endif
+#ifdef SUBJ_F128_LE
+     case F128_LE:
+        trueFunction_ab_f128_z_bool = f128M_le;
+        goto test_ab_f128_z_bool;
+#endif
+#ifdef SUBJ_F128_LT
+     case F128_LT:
+        trueFunction_ab_f128_z_bool = f128M_lt;
+        goto test_ab_f128_z_bool;
+#endif
+#ifdef SUBJ_F128_EQ_SIGNALING
+     case F128_EQ_SIGNALING:
+        trueFunction_ab_f128_z_bool = f128M_eq_signaling;
+        goto test_ab_f128_z_bool;
+#endif
+#ifdef SUBJ_F128_LE_QUIET
+     case F128_LE_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_le_quiet;
+        goto test_ab_f128_z_bool;
+#endif
+#ifdef SUBJ_F128_LT_QUIET
+     case F128_LT_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_lt_quiet;
+        goto test_ab_f128_z_bool;
+#endif
+     test_ab_f128_z_bool:
+        test_ab_f128_z_bool(
+            trueFunction_ab_f128_z_bool,
+            (funcType_ab_f128_z_bool *) subjFunctionPtr
+        );
+        break;
+#endif
+    }
+    if ( (verCases_errorStop && verCases_anyErrors) || verCases_stop ) {
+        verCases_exitWithStatus();
+    }
+
+}
+
+static
+void
+ testFunction(
+     const struct standardFunctionInfo *standardFunctionInfoPtr,
+     uint_fast8_t roundingPrecisionIn,
+     int roundingCodeIn
+ )
+{
+    int functionCode, functionAttribs;
+    bool standardFunctionHasFixedRounding;
+    int roundingCode;
+    bool exact;
+    uint_fast8_t roundingPrecision, roundingMode;
+
+    functionCode = standardFunctionInfoPtr->functionCode;
+    functionAttribs = functionInfos[functionCode].attribs;
+    standardFunctionHasFixedRounding = false;
+    if ( functionAttribs & FUNC_ARG_ROUNDINGMODE ) {
+        roundingCode = standardFunctionInfoPtr->roundingCode;
+        if ( roundingCode ) {
+            standardFunctionHasFixedRounding = true;
+            roundingCodeIn = roundingCode;
+        }
+    }
+    exact = standardFunctionInfoPtr->exact;
+    verCases_functionNamePtr = standardFunctionInfoPtr->namePtr;
+    roundingPrecision = 32;
+    for (;;) {
+        if ( functionAttribs & FUNC_EFF_ROUNDINGPRECISION ) {
+            if ( roundingPrecisionIn ) roundingPrecision = roundingPrecisionIn;
+        } else {
+            roundingPrecision = 0;
+        }
+#ifdef EXTFLOAT80
+        verCases_roundingPrecision = roundingPrecision;
+        if ( roundingPrecision ) {
+            extF80_roundingPrecision = roundingPrecision;
+            subjfloat_setExtF80RoundingPrecision( roundingPrecision );
+        }
+#endif
+        for (
+            roundingCode = 1; roundingCode < NUM_ROUNDINGMODES; ++roundingCode
+        ) {
+#ifndef SUBJFLOAT_ROUND_NEAR_MAXMAG
+            if ( roundingCode != ROUND_NEAR_MAXMAG ) {
+#endif
+#if defined FLOAT_ROUND_ODD && ! defined SUBJFLOAT_ROUND_NEAR_MAXMAG
+            if ( roundingCode != ROUND_ODD ) {
+#endif
+                if (
+                    functionAttribs
+                        & (FUNC_ARG_ROUNDINGMODE | FUNC_EFF_ROUNDINGMODE)
+                ) {
+                    if ( roundingCodeIn ) roundingCode = roundingCodeIn;
+                } else {
+                    roundingCode = 0;
+                }
+                verCases_roundingCode =
+                    standardFunctionHasFixedRounding ? 0 : roundingCode;
+                if ( roundingCode ) {
+                    roundingMode = roundingModes[roundingCode];
+                    softfloat_roundingMode = roundingMode;
+                    if ( ! standardFunctionHasFixedRounding ) {
+                        subjfloat_setRoundingMode( roundingMode );
+                    }
+                }
+                testFunctionInstance( functionCode, roundingMode, exact );
+                if ( roundingCodeIn || ! roundingCode ) break;
+#if defined FLOAT_ROUND_ODD && ! defined SUBJFLOAT_ROUND_NEAR_MAXMAG
+            }
+#endif
+#ifndef SUBJFLOAT_ROUND_NEAR_MAXMAG
+            }
+#endif
+        }
+        if ( roundingPrecisionIn || ! roundingPrecision ) break;
+        if ( roundingPrecision == 80 ) {
+            break;
+        } else if ( roundingPrecision == 64 ) {
+            roundingPrecision = 80;
+        } else if ( roundingPrecision == 32 ) {
+            roundingPrecision = 64;
+        }
+    }
+
+}
+
+int main( int argc, char *argv[] )
+{
+    bool haveFunctionArg;
+    const struct standardFunctionInfo *standardFunctionInfoPtr;
+    int numOperands;
+    uint_fast8_t roundingPrecision;
+    int roundingCode;
+    const char *argPtr;
+    void (*const *subjFunctionPtrPtr)();
+    const char *functionNamePtr;
+    unsigned long ui;
+    long i;
+    int functionMatchAttrib;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    fail_programName = "testfloat";
+    if ( argc <= 1 ) goto writeHelpMessage;
+    genCases_setLevel( 1 );
+    verCases_maxErrorCount = 20;
+    testLoops_trueFlagsPtr = &softfloat_exceptionFlags;
+    testLoops_subjFlagsFunction = subjfloat_clearExceptionFlags;
+    haveFunctionArg = false;
+    standardFunctionInfoPtr = 0;
+    numOperands = 0;
+    roundingPrecision = 0;
+    roundingCode = 0;
+    for (;;) {
+        --argc;
+        if ( ! argc ) break;
+        argPtr = *++argv;
+        if ( ! argPtr ) break;
+        if ( argPtr[0] == '-' ) ++argPtr;
+        if (
+            ! strcmp( argPtr, "help" ) || ! strcmp( argPtr, "-help" )
+                || ! strcmp( argPtr, "h" )
+        ) {
+ writeHelpMessage:
+            fputs(
+"testfloat [<option>...] <function>\n"
+"  <option>:  (* is default)\n"
+"    -help            --Write this message and exit.\n"
+"    -list            --List all testable subject functions and exit.\n"
+"    -seed <num>      --Set pseudo-random number generator seed to <num>.\n"
+" *  -seed 1\n"
+"    -level <num>     --Testing level <num> (1 or 2).\n"
+" *  -level 1\n"
+"    -errors <num>    --Stop each function test after <num> errors.\n"
+" *  -errors 20\n"
+"    -errorstop       --Exit after first function with any error.\n"
+"    -forever         --Test one function repeatedly (implies '-level 2').\n"
+"    -checkNaNs       --Check for specific NaN results.\n"
+"    -checkInvInts    --Check for specific invalid integer results.\n"
+"    -checkAll        --Same as both '-checkNaNs' and '-checkInvInts'.\n"
+#ifdef EXTFLOAT80
+"    -precision32     --For extF80, test only 32-bit rounding precision.\n"
+"    -precision64     --For extF80, test only 64-bit rounding precision.\n"
+"    -precision80     --For extF80, test only 80-bit rounding precision.\n"
+#endif
+"    -r<round>        --Test only specified rounding (if not inherent to\n"
+"                         function).\n"
+"    -tininessbefore  --Underflow tininess is detected before rounding.\n"
+"    -tininessafter   --Underflow tininess is detected after rounding.\n"
+"  <function>:\n"
+"    <int>_to_<float>               <float>_add      <float>_eq\n"
+"    <float>_to_<int>_r_<round>     <float>_sub      <float>_le\n"
+"    <float>_to_<int>_rx_<round>    <float>_mul      <float>_lt\n"
+"    <float>_to_<float>             <float>_mulAdd   <float>_eq_signaling\n"
+"    <float>_roundToInt_r_<round>   <float>_div      <float>_le_quiet\n"
+"    <float>_roundToInt_x           <float>_rem      <float>_lt_quiet\n"
+"                                   <float>_sqrt\n"
+"    -all1            --All unary functions.\n"
+"    -all2            --All binary functions.\n"
+"  <int>:\n"
+"    ui32             --Unsigned 32-bit integer.\n"
+"    ui64             --Unsigned 64-bit integer.\n"
+"    i32              --Signed 32-bit integer.\n"
+"    i64              --Signed 64-bit integer.\n"
+"  <float>:\n"
+#ifdef FLOAT16
+"    f16              --Binary 16-bit floating-point (half-precision).\n"
+#endif
+"    f32              --Binary 32-bit floating-point (single-precision).\n"
+#ifdef FLOAT64
+"    f64              --Binary 64-bit floating-point (double-precision).\n"
+#endif
+#ifdef EXTFLOAT80
+"    extF80           --Binary 80-bit extended floating-point.\n"
+#endif
+#ifdef FLOAT128
+"    f128             --Binary 128-bit floating-point (quadruple-precision).\n"
+#endif
+"  <round>:\n"
+"    near_even        --Round to nearest/even.\n"
+"    minMag           --Round to minimum magnitude (toward zero).\n"
+"    min              --Round to minimum (down).\n"
+"    max              --Round to maximum (up).\n"
+#ifdef SUBJFLOAT_ROUND_NEAR_MAXMAG
+"    near_maxMag      --Round to nearest/maximum magnitude (nearest/away).\n"
+#endif
+#if defined FLOAT_ROUND_ODD && defined SUBJFLOAT_ROUND_ODD
+"    odd              --Round to odd (jamming).  (Not allowed as an inherent\n"
+"                         rounding mode.  For 'roundToInt_x', rounds to minimum\n"
+"                         magnitude instead.)\n"
+#endif
+                ,
+                stdout
+            );
+            return EXIT_SUCCESS;
+        } else if ( ! strcmp( argPtr, "list" ) ) {
+            standardFunctionInfoPtr = standardFunctionInfos;
+            subjFunctionPtrPtr = subjfloat_functions;
+            for (;;) {
+                functionNamePtr = standardFunctionInfoPtr->namePtr;
+                if ( ! functionNamePtr ) break;
+                if ( *subjFunctionPtrPtr ) puts( functionNamePtr );
+                ++standardFunctionInfoPtr;
+                ++subjFunctionPtrPtr;
+            }
+            return EXIT_SUCCESS;
+        } else if ( ! strcmp( argPtr, "seed" ) ) {
+            if ( argc < 2 ) goto optionError;
+            ui = strtoul( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            srand( ui );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            genCases_setLevel( i );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level1" ) ) {
+            genCases_setLevel( 1 );
+        } else if ( ! strcmp( argPtr, "level2" ) ) {
+            genCases_setLevel( 2 );
+        } else if ( ! strcmp( argPtr, "errors" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            verCases_maxErrorCount = i;
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "errorstop" ) ) {
+            verCases_errorStop = true;
+        } else if ( ! strcmp( argPtr, "forever" ) ) {
+            genCases_setLevel( 2 );
+            testLoops_forever = true;
+        } else if (
+            ! strcmp( argPtr, "checkNaNs" ) || ! strcmp( argPtr, "checknans" )
+        ) {
+            verCases_checkNaNs = true;
+        } else if (
+               ! strcmp( argPtr, "checkInvInts" )
+            || ! strcmp( argPtr, "checkinvints" )
+        ) {
+            verCases_checkInvInts = true;
+        } else if (
+            ! strcmp( argPtr, "checkAll" ) || ! strcmp( argPtr, "checkall" )
+        ) {
+            verCases_checkNaNs = true;
+            verCases_checkInvInts = true;
+#ifdef EXTFLOAT80
+        } else if ( ! strcmp( argPtr, "precision32" ) ) {
+            roundingPrecision = 32;
+        } else if ( ! strcmp( argPtr, "precision64" ) ) {
+            roundingPrecision = 64;
+        } else if ( ! strcmp( argPtr, "precision80" ) ) {
+            roundingPrecision = 80;
+#endif
+        } else if (
+               ! strcmp( argPtr, "rnear_even" )
+            || ! strcmp( argPtr, "rneareven" )
+            || ! strcmp( argPtr, "rnearest_even" )
+        ) {
+            roundingCode = ROUND_NEAR_EVEN;
+        } else if (
+            ! strcmp( argPtr, "rminmag" ) || ! strcmp( argPtr, "rminMag" )
+        ) {
+            roundingCode = ROUND_MINMAG;
+        } else if ( ! strcmp( argPtr, "rmin" ) ) {
+            roundingCode = ROUND_MIN;
+        } else if ( ! strcmp( argPtr, "rmax" ) ) {
+            roundingCode = ROUND_MAX;
+        } else if (
+               ! strcmp( argPtr, "rnear_maxmag" )
+            || ! strcmp( argPtr, "rnear_maxMag" )
+            || ! strcmp( argPtr, "rnearmaxmag" )
+            || ! strcmp( argPtr, "rnearest_maxmag" )
+            || ! strcmp( argPtr, "rnearest_maxMag" )
+        ) {
+#ifdef SUBJFLOAT_ROUND_NEAR_MAXMAG
+            roundingCode = ROUND_NEAR_MAXMAG;
+#else
+            fail(
+             "Rounding mode 'near_maxMag' is not supported or cannot be tested"
+            );
+#endif
+#ifdef FLOAT_ROUND_ODD
+        } else if ( ! strcmp( argPtr, "rodd" ) ) {
+#ifdef SUBJFLOAT_ROUND_ODD
+            roundingCode = ROUND_ODD;
+#else
+            fail( "Rounding mode 'odd' is not supported or cannot be tested" );
+#endif
+#endif
+        } else if ( ! strcmp( argPtr, "tininessbefore" ) ) {
+            softfloat_detectTininess = softfloat_tininess_beforeRounding;
+        } else if ( ! strcmp( argPtr, "tininessafter" ) ) {
+            softfloat_detectTininess = softfloat_tininess_afterRounding;
+        } else if ( ! strcmp( argPtr, "all1" ) ) {
+            haveFunctionArg = true;
+            standardFunctionInfoPtr = 0;
+            numOperands = 1;
+        } else if ( ! strcmp( argPtr, "all2" ) ) {
+            haveFunctionArg = true;
+            standardFunctionInfoPtr = 0;
+            numOperands = 2;
+        } else {
+            standardFunctionInfoPtr = standardFunctionInfos;
+            for (;;) {
+                functionNamePtr = standardFunctionInfoPtr->namePtr;
+                if ( ! functionNamePtr ) {
+                    fail( "Invalid argument '%s'", *argv );
+                }
+                if ( ! strcmp( argPtr, functionNamePtr ) ) break;
+                ++standardFunctionInfoPtr;
+            }
+            subjFunctionPtr =
+                subjfloat_functions
+                    [standardFunctionInfoPtr - standardFunctionInfos];
+            if ( ! subjFunctionPtr ) {
+                fail(
+                    "Function '%s' is not supported or cannot be tested",
+                    argPtr
+                );
+            }
+            haveFunctionArg = true;
+        }
+    }
+    if ( ! haveFunctionArg ) fail( "Function argument required" );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signal( SIGINT, catchSIGINT );
+    signal( SIGTERM, catchSIGINT );
+    if ( standardFunctionInfoPtr ) {
+        if ( testLoops_forever ) {
+            if ( ! roundingPrecision ) roundingPrecision = 80;
+            if ( ! roundingCode ) roundingCode = ROUND_NEAR_EVEN;
+        }
+        testFunction(
+            standardFunctionInfoPtr, roundingPrecision, roundingCode );
+    } else {
+        if ( testLoops_forever ) {
+            fail( "Can test only one function with '-forever' option" );
+        }
+        functionMatchAttrib =
+            (numOperands == 1) ? FUNC_ARG_UNARY : FUNC_ARG_BINARY;
+        standardFunctionInfoPtr = standardFunctionInfos;
+        subjFunctionPtrPtr = subjfloat_functions;
+        while ( standardFunctionInfoPtr->namePtr ) {
+            subjFunctionPtr = *subjFunctionPtrPtr;
+            if (
+                subjFunctionPtr
+                    && (functionInfos[standardFunctionInfoPtr->functionCode]
+                            .attribs
+                            & functionMatchAttrib)
+            ) {
+                testFunction(
+                    standardFunctionInfoPtr, roundingPrecision, roundingCode );
+            }
+            ++standardFunctionInfoPtr;
+            ++subjFunctionPtrPtr;
+        }
+    }
+    verCases_exitWithStatus();
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ optionError:
+    fail( "'%s' option requires numeric argument", *argv );
+
+}
+
diff --git a/addins/TestFloat-3e/source/testfloat_gen.c b/addins/TestFloat-3e/source/testfloat_gen.c
new file mode 100644
index 000000000..1a5aba986
--- /dev/null
+++ b/addins/TestFloat-3e/source/testfloat_gen.c
@@ -0,0 +1,953 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "functions.h"
+#include "genCases.h"
+#include "genLoops.h"
+
+enum {
+    TYPE_UI32 = NUM_FUNCTIONS,
+    TYPE_UI64,
+    TYPE_I32,
+    TYPE_I64,
+    TYPE_F16,
+    TYPE_F16_2,
+    TYPE_F16_3,
+    TYPE_F32,
+    TYPE_F32_2,
+    TYPE_F32_3,
+    TYPE_F64,
+    TYPE_F64_2,
+    TYPE_F64_3,
+    TYPE_EXTF80,
+    TYPE_EXTF80_2,
+    TYPE_EXTF80_3,
+    TYPE_F128,
+    TYPE_F128_2,
+    TYPE_F128_3
+};
+
+static void catchSIGINT( int signalCode )
+{
+
+    if ( genLoops_stop ) exit( EXIT_FAILURE );
+    genLoops_stop = true;
+
+}
+
+int main( int argc, char *argv[] )
+{
+    const char *prefixTextPtr;
+    uint_fast8_t roundingMode;
+    bool exact;
+    int functionCode;
+    const char *argPtr;
+    unsigned long ui;
+    long i;
+    int functionAttribs;
+#ifdef FLOAT16
+    float16_t (*trueFunction_abz_f16)( float16_t, float16_t );
+    bool (*trueFunction_ab_f16_z_bool)( float16_t, float16_t );
+#endif
+    float32_t (*trueFunction_abz_f32)( float32_t, float32_t );
+    bool (*trueFunction_ab_f32_z_bool)( float32_t, float32_t );
+#ifdef FLOAT64
+    float64_t (*trueFunction_abz_f64)( float64_t, float64_t );
+    bool (*trueFunction_ab_f64_z_bool)( float64_t, float64_t );
+#endif
+#ifdef EXTFLOAT80
+    void
+     (*trueFunction_abz_extF80)(
+         const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+    bool
+     (*trueFunction_ab_extF80_z_bool)(
+         const extFloat80_t *, const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+    void
+     (*trueFunction_abz_f128)(
+         const float128_t *, const float128_t *, float128_t * );
+    bool
+     (*trueFunction_ab_f128_z_bool)( const float128_t *, const float128_t * );
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    fail_programName = "testfloat_gen";
+    if ( argc <= 1 ) goto writeHelpMessage;
+    prefixTextPtr = 0;
+    softfloat_detectTininess = softfloat_tininess_afterRounding;
+#ifdef EXTFLOAT80
+    extF80_roundingPrecision = 80;
+#endif
+    roundingMode = softfloat_round_near_even;
+    exact = false;
+    genCases_setLevel( 1 );
+    genLoops_trueFlagsPtr = &softfloat_exceptionFlags;
+    genLoops_forever = false;
+    genLoops_givenCount = false;
+    functionCode = 0;
+    for (;;) {
+        --argc;
+        if ( ! argc ) break;
+        argPtr = *++argv;
+        if ( ! argPtr ) break;
+        if ( argPtr[0] == '-' ) ++argPtr;
+        if (
+            ! strcmp( argPtr, "help" ) || ! strcmp( argPtr, "-help" )
+                || ! strcmp( argPtr, "h" )
+        ) {
+ writeHelpMessage:
+            fputs(
+"testfloat_gen [<option>...] <type>|<function>\n"
+"  <option>:  (* is default)\n"
+"    -help            --Write this message and exit.\n"
+"    -prefix <text>   --Write <text> as a line of output before any test cases.\n"
+"    -seed <num>      --Set pseudo-random number generator seed to <num>.\n"
+" *  -seed 1\n"
+"    -level <num>     --Testing level <num> (1 or 2).\n"
+" *  -level 1\n"
+"    -n <num>         --Generate <num> test cases.\n"
+"    -forever         --Generate test cases indefinitely (implies '-level 2').\n"
+#ifdef EXTFLOAT80
+"    -precision32     --For extF80, rounding precision is 32 bits.\n"
+"    -precision64     --For extF80, rounding precision is 64 bits.\n"
+" *  -precision80     --For extF80, rounding precision is 80 bits.\n"
+#endif
+" *  -rnear_even      --Round to nearest/even.\n"
+"    -rminMag         --Round to minimum magnitude (toward zero).\n"
+"    -rmin            --Round to minimum (down).\n"
+"    -rmax            --Round to maximum (up).\n"
+"    -rnear_maxMag    --Round to nearest/maximum magnitude (nearest/away).\n"
+#ifdef FLOAT_ROUND_ODD
+"    -rodd            --Round to odd (jamming).  (For rounding to an integer\n"
+"                         value, rounds to minimum magnitude instead.)\n"
+#endif
+"    -tininessbefore  --Detect underflow tininess before rounding.\n"
+" *  -tininessafter   --Detect underflow tininess after rounding.\n"
+" *  -notexact        --Rounding to integer is not exact (no inexact\n"
+"                         exceptions).\n"
+"    -exact           --Rounding to integer is exact (raising inexact\n"
+"                         exceptions).\n"
+"  <type>:\n"
+"    <int>            --Generate test cases with one integer operand.\n"
+"    <float>          --Generate test cases with one floating-point operand.\n"
+"    <float> <num>    --Generate test cases with <num> (1, 2, or 3)\n"
+"                         floating-point operands.\n"
+"  <function>:\n"
+"    <int>_to_<float>     <float>_add      <float>_eq\n"
+"    <float>_to_<int>     <float>_sub      <float>_le\n"
+"    <float>_to_<float>   <float>_mul      <float>_lt\n"
+"    <float>_roundToInt   <float>_mulAdd   <float>_eq_signaling\n"
+"                         <float>_div      <float>_le_quiet\n"
+"                         <float>_rem      <float>_lt_quiet\n"
+"                         <float>_sqrt\n"
+"  <int>:\n"
+"    ui32             --Unsigned 32-bit integer.\n"
+"    ui64             --Unsigned 64-bit integer.\n"
+"    i32              --Signed 32-bit integer.\n"
+"    i64              --Signed 64-bit integer.\n"
+"  <float>:\n"
+#ifdef FLOAT16
+"    f16              --Binary 16-bit floating-point (half-precision).\n"
+#endif
+"    f32              --Binary 32-bit floating-point (single-precision).\n"
+#ifdef FLOAT64
+"    f64              --Binary 64-bit floating-point (double-precision).\n"
+#endif
+#ifdef EXTFLOAT80
+"    extF80           --Binary 80-bit extended floating-point.\n"
+#endif
+#ifdef FLOAT128
+"    f128             --Binary 128-bit floating-point (quadruple-precision).\n"
+#endif
+                ,
+                stdout
+            );
+            return EXIT_SUCCESS;
+        } else if ( ! strcmp( argPtr, "prefix" ) ) {
+            if ( argc < 2 ) goto optionError;
+            prefixTextPtr = argv[1];
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "seed" ) ) {
+            if ( argc < 2 ) goto optionError;
+            ui = strtoul( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            srand( ui );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            genCases_setLevel( i );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level1" ) ) {
+            genCases_setLevel( 1 );
+        } else if ( ! strcmp( argPtr, "level2" ) ) {
+            genCases_setLevel( 2 );
+        } else if ( ! strcmp( argPtr, "n" ) ) {
+            if ( argc < 2 ) goto optionError;
+            genLoops_forever = true;
+            genLoops_givenCount = true;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            genLoops_count = i;
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "forever" ) ) {
+            genCases_setLevel( 2 );
+            genLoops_forever = true;
+            genLoops_givenCount = false;
+#ifdef EXTFLOAT80
+        } else if ( ! strcmp( argPtr, "precision32" ) ) {
+            extF80_roundingPrecision = 32;
+        } else if ( ! strcmp( argPtr, "precision64" ) ) {
+            extF80_roundingPrecision = 64;
+        } else if ( ! strcmp( argPtr, "precision80" ) ) {
+            extF80_roundingPrecision = 80;
+#endif
+        } else if (
+               ! strcmp( argPtr, "rnear_even" )
+            || ! strcmp( argPtr, "rneareven" )
+            || ! strcmp( argPtr, "rnearest_even" )
+        ) {
+            roundingMode = softfloat_round_near_even;
+        } else if (
+            ! strcmp( argPtr, "rminmag" ) || ! strcmp( argPtr, "rminMag" )
+        ) {
+            roundingMode = softfloat_round_minMag;
+        } else if ( ! strcmp( argPtr, "rmin" ) ) {
+            roundingMode = softfloat_round_min;
+        } else if ( ! strcmp( argPtr, "rmax" ) ) {
+            roundingMode = softfloat_round_max;
+        } else if (
+               ! strcmp( argPtr, "rnear_maxmag" )
+            || ! strcmp( argPtr, "rnear_maxMag" )
+            || ! strcmp( argPtr, "rnearmaxmag" )
+            || ! strcmp( argPtr, "rnearest_maxmag" )
+            || ! strcmp( argPtr, "rnearest_maxMag" )
+        ) {
+            roundingMode = softfloat_round_near_maxMag;
+#ifdef FLOAT_ROUND_ODD
+        } else if ( ! strcmp( argPtr, "rodd" ) ) {
+            roundingMode = softfloat_round_odd;
+#endif
+        } else if ( ! strcmp( argPtr, "tininessbefore" ) ) {
+            softfloat_detectTininess = softfloat_tininess_beforeRounding;
+        } else if ( ! strcmp( argPtr, "tininessafter" ) ) {
+            softfloat_detectTininess = softfloat_tininess_afterRounding;
+        } else if ( ! strcmp( argPtr, "notexact" ) ) {
+            exact = false;
+        } else if ( ! strcmp( argPtr, "exact" ) ) {
+            exact = true;
+        } else if (
+            ! strcmp( argPtr, "ui32" ) || ! strcmp( argPtr, "uint32" )
+        ) {
+            functionCode = TYPE_UI32;
+            if ( 2 <= argc ) goto absorbArg1;
+        } else if (
+            ! strcmp( argPtr, "ui64" ) || ! strcmp( argPtr, "uint64" )
+        ) {
+            functionCode = TYPE_UI64;
+            if ( 2 <= argc ) goto absorbArg1;
+        } else if (
+            ! strcmp( argPtr, "i32" ) || ! strcmp( argPtr, "int32" )
+        ) {
+            functionCode = TYPE_I32;
+            if ( 2 <= argc ) goto absorbArg1;
+        } else if (
+            ! strcmp( argPtr, "i64" ) || ! strcmp( argPtr, "int64" )
+        ) {
+            functionCode = TYPE_I64;
+            if ( 2 <= argc ) goto absorbArg1;
+#ifdef FLOAT16
+        } else if (
+            ! strcmp( argPtr, "f16" ) || ! strcmp( argPtr, "float16" )
+        ) {
+            functionCode = TYPE_F16;
+            goto absorbArg;
+#endif
+        } else if (
+            ! strcmp( argPtr, "f32" ) || ! strcmp( argPtr, "float32" )
+        ) {
+            functionCode = TYPE_F32;
+#ifdef FLOAT64
+            goto absorbArg;
+        } else if (
+            ! strcmp( argPtr, "f64" ) || ! strcmp( argPtr, "float64" )
+        ) {
+            functionCode = TYPE_F64;
+#endif
+#ifdef EXTFLOAT80
+            goto absorbArg;
+        } else if (
+            ! strcmp( argPtr, "extF80" ) || ! strcmp( argPtr, "extFloat80" )
+        ) {
+            functionCode = TYPE_EXTF80;
+#endif
+#ifdef FLOAT128
+            goto absorbArg;
+        } else if (
+            ! strcmp( argPtr, "f128" ) || ! strcmp( argPtr, "float128" )
+        ) {
+            functionCode = TYPE_F128;
+#endif
+     absorbArg:
+            if ( 2 <= argc ) {
+                if ( ! strcmp( argv[1], "2" ) ) {
+                    --argc;
+                    ++argv;
+                    ++functionCode;
+                } else if ( ! strcmp( argv[1], "3" ) ) {
+                    --argc;
+                    ++argv;
+                    functionCode += 2;
+                } else {
+     absorbArg1:
+                    if ( ! strcmp( argv[1], "1" ) ) {
+                        --argc;
+                        ++argv;
+                    }
+                }
+            }
+        } else {
+            functionCode = 1;
+            while ( strcmp( argPtr, functionInfos[functionCode].namePtr ) ) {
+                ++functionCode;
+                if ( functionCode == NUM_FUNCTIONS ) goto invalidArg;
+            }
+            functionAttribs = functionInfos[functionCode].attribs;
+            if (
+                (functionAttribs & FUNC_ARG_EXACT)
+                    && ! (functionAttribs & FUNC_ARG_ROUNDINGMODE)
+            ) {
+                goto invalidArg;
+            }
+        }
+    }
+    if ( ! functionCode ) fail( "Type or function argument required" );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( prefixTextPtr ) {
+        fputs( prefixTextPtr, stdout );
+        fputc( '\n', stdout );
+    }
+    softfloat_roundingMode = roundingMode;
+    signal( SIGINT, catchSIGINT );
+    signal( SIGTERM, catchSIGINT );
+    switch ( functionCode ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case TYPE_UI32:
+        gen_a_ui32();
+        break;
+     case TYPE_UI64:
+        gen_a_ui64();
+        break;
+     case TYPE_I32:
+        gen_a_i32();
+        break;
+     case TYPE_I64:
+        gen_a_i64();
+        break;
+#ifdef FLOAT16
+     case TYPE_F16:
+        gen_a_f16();
+        break;
+     case TYPE_F16_2:
+        gen_ab_f16();
+        break;
+     case TYPE_F16_3:
+        gen_abc_f16();
+        break;
+#endif
+     case TYPE_F32:
+        gen_a_f32();
+        break;
+     case TYPE_F32_2:
+        gen_ab_f32();
+        break;
+     case TYPE_F32_3:
+        gen_abc_f32();
+        break;
+#ifdef FLOAT64
+     case TYPE_F64:
+        gen_a_f64();
+        break;
+     case TYPE_F64_2:
+        gen_ab_f64();
+        break;
+     case TYPE_F64_3:
+        gen_abc_f64();
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case TYPE_EXTF80:
+        gen_a_extF80();
+        break;
+     case TYPE_EXTF80_2:
+        gen_ab_extF80();
+        break;
+     case TYPE_EXTF80_3:
+        gen_abc_extF80();
+        break;
+#endif
+#ifdef FLOAT128
+     case TYPE_F128:
+        gen_a_f128();
+        break;
+     case TYPE_F128_2:
+        gen_ab_f128();
+        break;
+     case TYPE_F128_3:
+        gen_abc_f128();
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case UI32_TO_F16:
+        gen_a_ui32_z_f16( ui32_to_f16 );
+        break;
+#endif
+     case UI32_TO_F32:
+        gen_a_ui32_z_f32( ui32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI32_TO_F64:
+        gen_a_ui32_z_f64( ui32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI32_TO_EXTF80:
+        gen_a_ui32_z_extF80( ui32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI32_TO_F128:
+        gen_a_ui32_z_f128( ui32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case UI64_TO_F16:
+        gen_a_ui64_z_f16( ui64_to_f16 );
+        break;
+#endif
+     case UI64_TO_F32:
+        gen_a_ui64_z_f32( ui64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI64_TO_F64:
+        gen_a_ui64_z_f64( ui64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI64_TO_EXTF80:
+        gen_a_ui64_z_extF80( ui64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI64_TO_F128:
+        gen_a_ui64_z_f128( ui64_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I32_TO_F16:
+        gen_a_i32_z_f16( i32_to_f16 );
+        break;
+#endif
+     case I32_TO_F32:
+        gen_a_i32_z_f32( i32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I32_TO_F64:
+        gen_a_i32_z_f64( i32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I32_TO_EXTF80:
+        gen_a_i32_z_extF80( i32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I32_TO_F128:
+        gen_a_i32_z_f128( i32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I64_TO_F16:
+        gen_a_i64_z_f16( i64_to_f16 );
+        break;
+#endif
+     case I64_TO_F32:
+        gen_a_i64_z_f32( i64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I64_TO_F64:
+        gen_a_i64_z_f64( i64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I64_TO_EXTF80:
+        gen_a_i64_z_extF80( i64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I64_TO_F128:
+        gen_a_i64_z_f128( i64_to_f128M );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case F16_TO_UI32:
+        gen_a_f16_z_ui32_rx( f16_to_ui32, roundingMode, exact );
+        break;
+     case F16_TO_UI64:
+        gen_a_f16_z_ui64_rx( f16_to_ui64, roundingMode, exact );
+        break;
+     case F16_TO_I32:
+        gen_a_f16_z_i32_rx( f16_to_i32, roundingMode, exact );
+        break;
+     case F16_TO_I64:
+        gen_a_f16_z_i64_rx( f16_to_i64, roundingMode, exact );
+        break;
+     case F16_TO_F32:
+        gen_a_f16_z_f32( f16_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F16_TO_F64:
+        gen_a_f16_z_f64( f16_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F16_TO_EXTF80:
+        gen_a_f16_z_extF80( f16_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F16_TO_F128:
+        gen_a_f16_z_f128( f16_to_f128M );
+        break;
+#endif
+     case F16_ROUNDTOINT:
+        gen_az_f16_rx( f16_roundToInt, roundingMode, exact );
+        break;
+     case F16_ADD:
+        trueFunction_abz_f16 = f16_add;
+        goto gen_abz_f16;
+     case F16_SUB:
+        trueFunction_abz_f16 = f16_sub;
+        goto gen_abz_f16;
+     case F16_MUL:
+        trueFunction_abz_f16 = f16_mul;
+        goto gen_abz_f16;
+     case F16_DIV:
+        trueFunction_abz_f16 = f16_div;
+        goto gen_abz_f16;
+     case F16_REM:
+        trueFunction_abz_f16 = f16_rem;
+     gen_abz_f16:
+        gen_abz_f16( trueFunction_abz_f16 );
+        break;
+     case F16_MULADD:
+        gen_abcz_f16( f16_mulAdd );
+        break;
+     case F16_SQRT:
+        gen_az_f16( f16_sqrt );
+        break;
+     case F16_EQ:
+        trueFunction_ab_f16_z_bool = f16_eq;
+        goto gen_ab_f16_z_bool;
+     case F16_LE:
+        trueFunction_ab_f16_z_bool = f16_le;
+        goto gen_ab_f16_z_bool;
+     case F16_LT:
+        trueFunction_ab_f16_z_bool = f16_lt;
+        goto gen_ab_f16_z_bool;
+     case F16_EQ_SIGNALING:
+        trueFunction_ab_f16_z_bool = f16_eq_signaling;
+        goto gen_ab_f16_z_bool;
+     case F16_LE_QUIET:
+        trueFunction_ab_f16_z_bool = f16_le_quiet;
+        goto gen_ab_f16_z_bool;
+     case F16_LT_QUIET:
+        trueFunction_ab_f16_z_bool = f16_lt_quiet;
+     gen_ab_f16_z_bool:
+        gen_ab_f16_z_bool( trueFunction_ab_f16_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case F32_TO_UI32:
+        gen_a_f32_z_ui32_rx( f32_to_ui32, roundingMode, exact );
+        break;
+     case F32_TO_UI64:
+        gen_a_f32_z_ui64_rx( f32_to_ui64, roundingMode, exact );
+        break;
+     case F32_TO_I32:
+        gen_a_f32_z_i32_rx( f32_to_i32, roundingMode, exact );
+        break;
+     case F32_TO_I64:
+        gen_a_f32_z_i64_rx( f32_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F32_TO_F16:
+        gen_a_f32_z_f16( f32_to_f16 );
+        break;
+#endif
+#ifdef FLOAT64
+     case F32_TO_F64:
+        gen_a_f32_z_f64( f32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F32_TO_EXTF80:
+        gen_a_f32_z_extF80( f32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F32_TO_F128:
+        gen_a_f32_z_f128( f32_to_f128M );
+        break;
+#endif
+     case F32_ROUNDTOINT:
+        gen_az_f32_rx( f32_roundToInt, roundingMode, exact );
+        break;
+     case F32_ADD:
+        trueFunction_abz_f32 = f32_add;
+        goto gen_abz_f32;
+     case F32_SUB:
+        trueFunction_abz_f32 = f32_sub;
+        goto gen_abz_f32;
+     case F32_MUL:
+        trueFunction_abz_f32 = f32_mul;
+        goto gen_abz_f32;
+     case F32_DIV:
+        trueFunction_abz_f32 = f32_div;
+        goto gen_abz_f32;
+     case F32_REM:
+        trueFunction_abz_f32 = f32_rem;
+     gen_abz_f32:
+        gen_abz_f32( trueFunction_abz_f32 );
+        break;
+     case F32_MULADD:
+        gen_abcz_f32( f32_mulAdd );
+        break;
+     case F32_SQRT:
+        gen_az_f32( f32_sqrt );
+        break;
+     case F32_EQ:
+        trueFunction_ab_f32_z_bool = f32_eq;
+        goto gen_ab_f32_z_bool;
+     case F32_LE:
+        trueFunction_ab_f32_z_bool = f32_le;
+        goto gen_ab_f32_z_bool;
+     case F32_LT:
+        trueFunction_ab_f32_z_bool = f32_lt;
+        goto gen_ab_f32_z_bool;
+     case F32_EQ_SIGNALING:
+        trueFunction_ab_f32_z_bool = f32_eq_signaling;
+        goto gen_ab_f32_z_bool;
+     case F32_LE_QUIET:
+        trueFunction_ab_f32_z_bool = f32_le_quiet;
+        goto gen_ab_f32_z_bool;
+     case F32_LT_QUIET:
+        trueFunction_ab_f32_z_bool = f32_lt_quiet;
+     gen_ab_f32_z_bool:
+        gen_ab_f32_z_bool( trueFunction_ab_f32_z_bool );
+        break;
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT64
+     case F64_TO_UI32:
+        gen_a_f64_z_ui32_rx( f64_to_ui32, roundingMode, exact );
+        break;
+     case F64_TO_UI64:
+        gen_a_f64_z_ui64_rx( f64_to_ui64, roundingMode, exact );
+        break;
+     case F64_TO_I32:
+        gen_a_f64_z_i32_rx( f64_to_i32, roundingMode, exact );
+        break;
+     case F64_TO_I64:
+        gen_a_f64_z_i64_rx( f64_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F64_TO_F16:
+        gen_a_f64_z_f16( f64_to_f16 );
+        break;
+#endif
+     case F64_TO_F32:
+        gen_a_f64_z_f32( f64_to_f32 );
+        break;
+#ifdef EXTFLOAT80
+     case F64_TO_EXTF80:
+        gen_a_f64_z_extF80( f64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F64_TO_F128:
+        gen_a_f64_z_f128( f64_to_f128M );
+        break;
+#endif
+     case F64_ROUNDTOINT:
+        gen_az_f64_rx( f64_roundToInt, roundingMode, exact );
+        break;
+     case F64_ADD:
+        trueFunction_abz_f64 = f64_add;
+        goto gen_abz_f64;
+     case F64_SUB:
+        trueFunction_abz_f64 = f64_sub;
+        goto gen_abz_f64;
+     case F64_MUL:
+        trueFunction_abz_f64 = f64_mul;
+        goto gen_abz_f64;
+     case F64_DIV:
+        trueFunction_abz_f64 = f64_div;
+        goto gen_abz_f64;
+     case F64_REM:
+        trueFunction_abz_f64 = f64_rem;
+     gen_abz_f64:
+        gen_abz_f64( trueFunction_abz_f64 );
+        break;
+     case F64_MULADD:
+        gen_abcz_f64( f64_mulAdd );
+        break;
+     case F64_SQRT:
+        gen_az_f64( f64_sqrt );
+        break;
+     case F64_EQ:
+        trueFunction_ab_f64_z_bool = f64_eq;
+        goto gen_ab_f64_z_bool;
+     case F64_LE:
+        trueFunction_ab_f64_z_bool = f64_le;
+        goto gen_ab_f64_z_bool;
+     case F64_LT:
+        trueFunction_ab_f64_z_bool = f64_lt;
+        goto gen_ab_f64_z_bool;
+     case F64_EQ_SIGNALING:
+        trueFunction_ab_f64_z_bool = f64_eq_signaling;
+        goto gen_ab_f64_z_bool;
+     case F64_LE_QUIET:
+        trueFunction_ab_f64_z_bool = f64_le_quiet;
+        goto gen_ab_f64_z_bool;
+     case F64_LT_QUIET:
+        trueFunction_ab_f64_z_bool = f64_lt_quiet;
+     gen_ab_f64_z_bool:
+        gen_ab_f64_z_bool( trueFunction_ab_f64_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+     case EXTF80_TO_UI32:
+        gen_a_extF80_z_ui32_rx( extF80M_to_ui32, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI64:
+        gen_a_extF80_z_ui64_rx( extF80M_to_ui64, roundingMode, exact );
+        break;
+     case EXTF80_TO_I32:
+        gen_a_extF80_z_i32_rx( extF80M_to_i32, roundingMode, exact );
+        break;
+     case EXTF80_TO_I64:
+        gen_a_extF80_z_i64_rx( extF80M_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case EXTF80_TO_F16:
+        gen_a_extF80_z_f16( extF80M_to_f16 );
+        break;
+#endif
+     case EXTF80_TO_F32:
+        gen_a_extF80_z_f32( extF80M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case EXTF80_TO_F64:
+        gen_a_extF80_z_f64( extF80M_to_f64 );
+        break;
+#endif
+#ifdef FLOAT128
+     case EXTF80_TO_F128:
+        gen_a_extF80_z_f128( extF80M_to_f128M );
+        break;
+#endif
+     case EXTF80_ROUNDTOINT:
+        gen_az_extF80_rx( extF80M_roundToInt, roundingMode, exact );
+        break;
+     case EXTF80_ADD:
+        trueFunction_abz_extF80 = extF80M_add;
+        goto gen_abz_extF80;
+     case EXTF80_SUB:
+        trueFunction_abz_extF80 = extF80M_sub;
+        goto gen_abz_extF80;
+     case EXTF80_MUL:
+        trueFunction_abz_extF80 = extF80M_mul;
+        goto gen_abz_extF80;
+     case EXTF80_DIV:
+        trueFunction_abz_extF80 = extF80M_div;
+        goto gen_abz_extF80;
+     case EXTF80_REM:
+        trueFunction_abz_extF80 = extF80M_rem;
+     gen_abz_extF80:
+        gen_abz_extF80( trueFunction_abz_extF80 );
+        break;
+     case EXTF80_SQRT:
+        gen_az_extF80( extF80M_sqrt );
+        break;
+     case EXTF80_EQ:
+        trueFunction_ab_extF80_z_bool = extF80M_eq;
+        goto gen_ab_extF80_z_bool;
+     case EXTF80_LE:
+        trueFunction_ab_extF80_z_bool = extF80M_le;
+        goto gen_ab_extF80_z_bool;
+     case EXTF80_LT:
+        trueFunction_ab_extF80_z_bool = extF80M_lt;
+        goto gen_ab_extF80_z_bool;
+     case EXTF80_EQ_SIGNALING:
+        trueFunction_ab_extF80_z_bool = extF80M_eq_signaling;
+        goto gen_ab_extF80_z_bool;
+     case EXTF80_LE_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_le_quiet;
+        goto gen_ab_extF80_z_bool;
+     case EXTF80_LT_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_lt_quiet;
+     gen_ab_extF80_z_bool:
+        gen_ab_extF80_z_bool( trueFunction_ab_extF80_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT128
+     case F128_TO_UI32:
+        gen_a_f128_z_ui32_rx( f128M_to_ui32, roundingMode, exact );
+        break;
+     case F128_TO_UI64:
+        gen_a_f128_z_ui64_rx( f128M_to_ui64, roundingMode, exact );
+        break;
+     case F128_TO_I32:
+        gen_a_f128_z_i32_rx( f128M_to_i32, roundingMode, exact );
+        break;
+     case F128_TO_I64:
+        gen_a_f128_z_i64_rx( f128M_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F128_TO_F16:
+        gen_a_f128_z_f16( f128M_to_f16 );
+        break;
+#endif
+     case F128_TO_F32:
+        gen_a_f128_z_f32( f128M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F128_TO_F64:
+        gen_a_f128_z_f64( f128M_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F128_TO_EXTF80:
+        gen_a_f128_z_extF80( f128M_to_extF80M );
+        break;
+#endif
+     case F128_ROUNDTOINT:
+        gen_az_f128_rx( f128M_roundToInt, roundingMode, exact );
+        break;
+     case F128_ADD:
+        trueFunction_abz_f128 = f128M_add;
+        goto gen_abz_f128;
+     case F128_SUB:
+        trueFunction_abz_f128 = f128M_sub;
+        goto gen_abz_f128;
+     case F128_MUL:
+        trueFunction_abz_f128 = f128M_mul;
+        goto gen_abz_f128;
+     case F128_DIV:
+        trueFunction_abz_f128 = f128M_div;
+        goto gen_abz_f128;
+     case F128_REM:
+        trueFunction_abz_f128 = f128M_rem;
+     gen_abz_f128:
+        gen_abz_f128( trueFunction_abz_f128 );
+        break;
+     case F128_MULADD:
+        gen_abcz_f128( f128M_mulAdd );
+        break;
+     case F128_SQRT:
+        gen_az_f128( f128M_sqrt );
+        break;
+     case F128_EQ:
+        trueFunction_ab_f128_z_bool = f128M_eq;
+        goto gen_ab_f128_z_bool;
+     case F128_LE:
+        trueFunction_ab_f128_z_bool = f128M_le;
+        goto gen_ab_f128_z_bool;
+     case F128_LT:
+        trueFunction_ab_f128_z_bool = f128M_lt;
+        goto gen_ab_f128_z_bool;
+     case F128_EQ_SIGNALING:
+        trueFunction_ab_f128_z_bool = f128M_eq_signaling;
+        goto gen_ab_f128_z_bool;
+     case F128_LE_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_le_quiet;
+        goto gen_ab_f128_z_bool;
+     case F128_LT_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_lt_quiet;
+     gen_ab_f128_z_bool:
+        gen_ab_f128_z_bool( trueFunction_ab_f128_z_bool );
+        break;
+#endif
+    }
+    return EXIT_SUCCESS;
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ optionError:
+    fail( "'%s' option requires numeric argument", *argv );
+ invalidArg:
+    fail( "Invalid argument '%s'", *argv );
+
+}
+
diff --git a/addins/TestFloat-3e/source/testfloat_ver.c b/addins/TestFloat-3e/source/testfloat_ver.c
new file mode 100644
index 000000000..e9ec006d1
--- /dev/null
+++ b/addins/TestFloat-3e/source/testfloat_ver.c
@@ -0,0 +1,795 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "functions.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "verLoops.h"
+
+static void catchSIGINT( int signalCode )
+{
+
+    if ( verCases_stop ) exit( EXIT_FAILURE );
+    verCases_stop = true;
+
+}
+
+int main( int argc, char *argv[] )
+{
+    bool exact;
+    int functionCode, roundingCode, tininessCode;
+    const char *argPtr;
+    long i;
+    int functionAttribs;
+    uint_fast8_t roundingMode;
+#ifdef FLOAT16
+    float16_t (*trueFunction_abz_f16)( float16_t, float16_t );
+    bool (*trueFunction_ab_f16_z_bool)( float16_t, float16_t );
+#endif
+    float32_t (*trueFunction_abz_f32)( float32_t, float32_t );
+    bool (*trueFunction_ab_f32_z_bool)( float32_t, float32_t );
+#ifdef FLOAT64
+    float64_t (*trueFunction_abz_f64)( float64_t, float64_t );
+    bool (*trueFunction_ab_f64_z_bool)( float64_t, float64_t );
+#endif
+#ifdef EXTFLOAT80
+    void
+     (*trueFunction_abz_extF80)(
+         const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+    bool
+     (*trueFunction_ab_extF80_z_bool)(
+         const extFloat80_t *, const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+    void
+     (*trueFunction_abz_f128)(
+         const float128_t *, const float128_t *, float128_t * );
+    bool
+     (*trueFunction_ab_f128_z_bool)( const float128_t *, const float128_t * );
+#endif
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    fail_programName = "testfloat_ver";
+    if ( argc <= 1 ) goto writeHelpMessage;
+    softfloat_detectTininess = softfloat_tininess_afterRounding;
+#ifdef EXTFLOAT80
+    extF80_roundingPrecision = 80;
+#endif
+    roundingMode = softfloat_round_near_even;
+    exact = false;
+    verCases_maxErrorCount = 20;
+    verLoops_trueFlagsPtr = &softfloat_exceptionFlags;
+    functionCode = 0;
+    roundingCode = ROUND_NEAR_EVEN;
+    tininessCode = TININESS_AFTER_ROUNDING;
+    for (;;) {
+        --argc;
+        if ( ! argc ) break;
+        argPtr = *++argv;
+        if ( ! argPtr ) break;
+        if ( argPtr[0] == '-' ) ++argPtr;
+        if (
+            ! strcmp( argPtr, "help" ) || ! strcmp( argPtr, "-help" )
+                || ! strcmp( argPtr, "h" )
+        ) {
+ writeHelpMessage:
+            fputs(
+"testfloat_ver [<option>...] <function>\n"
+"  <option>:  (* is default)\n"
+"    -help            --Write this message and exit.\n"
+"    -errors <num>    --Stop after <num> errors.\n"
+" *  -errors 20\n"
+"    -checkNaNs       --Check for specific NaN results.\n"
+"    -checkInvInts    --Check for specific invalid integer results.\n"
+"    -checkAll        --Same as both '-checkNaNs' and '-checkInvInts'.\n"
+#ifdef EXTFLOAT80
+"    -precision32     --For extF80, rounding precision is 32 bits.\n"
+"    -precision64     --For extF80, rounding precision is 64 bits.\n"
+" *  -precision80     --For extF80, rounding precision is 80 bits.\n"
+#endif
+" *  -rnear_even      --Round to nearest/even.\n"
+"    -rminMag         --Round to minimum magnitude (toward zero).\n"
+"    -rmin            --Round to minimum (down).\n"
+"    -rmax            --Round to maximum (up).\n"
+"    -rnear_maxMag    --Round to nearest/maximum magnitude (nearest/away).\n"
+#ifdef FLOAT_ROUND_ODD
+"    -rodd            --Round to odd (jamming).  (For rounding to an integer\n"
+"                         value, rounds to minimum magnitude instead.)\n"
+#endif
+"    -tininessbefore  --Detect underflow tininess before rounding.\n"
+" *  -tininessafter   --Detect underflow tininess after rounding.\n"
+" *  -notexact        --Rounding to integer is not exact (no inexact\n"
+"                         exceptions).\n"
+"    -exact           --Rounding to integer is exact (raising inexact\n"
+"                         exceptions).\n"
+"  <function>:\n"
+"    <int>_to_<float>     <float>_add      <float>_eq\n"
+"    <float>_to_<int>     <float>_sub      <float>_le\n"
+"    <float>_to_<float>   <float>_mul      <float>_lt\n"
+"    <float>_roundToInt   <float>_mulAdd   <float>_eq_signaling\n"
+"                         <float>_div      <float>_le_quiet\n"
+"                         <float>_rem      <float>_lt_quiet\n"
+"                         <float>_sqrt\n"
+"  <int>:\n"
+"    ui32             --Unsigned 32-bit integer.\n"
+"    ui64             --Unsigned 64-bit integer.\n"
+"    i32              --Signed 32-bit integer.\n"
+"    i64              --Signed 64-bit integer.\n"
+"  <float>:\n"
+#ifdef FLOAT16
+"    f16              --Binary 16-bit floating-point (half-precision).\n"
+#endif
+"    f32              --Binary 32-bit floating-point (single-precision).\n"
+#ifdef FLOAT64
+"    f64              --Binary 64-bit floating-point (double-precision).\n"
+#endif
+#ifdef EXTFLOAT80
+"    extF80           --Binary 80-bit extended floating-point.\n"
+#endif
+#ifdef FLOAT128
+"    f128             --Binary 128-bit floating-point (quadruple-precision).\n"
+#endif
+                ,
+                stdout
+            );
+            return EXIT_SUCCESS;
+        } else if ( ! strcmp( argPtr, "errors" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            verCases_maxErrorCount = i;
+            --argc;
+            ++argv;
+        } else if (
+            ! strcmp( argPtr, "checkNaNs" ) || ! strcmp( argPtr, "checknans" )
+        ) {
+            verCases_checkNaNs = true;
+        } else if (
+               ! strcmp( argPtr, "checkInvInts" )
+            || ! strcmp( argPtr, "checkinvints" )
+        ) {
+            verCases_checkInvInts = true;
+        } else if (
+            ! strcmp( argPtr, "checkAll" ) || ! strcmp( argPtr, "checkall" )
+        ) {
+            verCases_checkNaNs = true;
+            verCases_checkInvInts = true;
+#ifdef EXTFLOAT80
+        } else if ( ! strcmp( argPtr, "precision32" ) ) {
+            extF80_roundingPrecision = 32;
+        } else if ( ! strcmp( argPtr, "precision64" ) ) {
+            extF80_roundingPrecision = 64;
+        } else if ( ! strcmp( argPtr, "precision80" ) ) {
+            extF80_roundingPrecision = 80;
+#endif
+        } else if (
+               ! strcmp( argPtr, "rnear_even" )
+            || ! strcmp( argPtr, "rneareven" )
+            || ! strcmp( argPtr, "rnearest_even" )
+        ) {
+            roundingCode = ROUND_NEAR_EVEN;
+        } else if (
+            ! strcmp( argPtr, "rminmag" ) || ! strcmp( argPtr, "rminMag" )
+        ) {
+            roundingCode = ROUND_MINMAG;
+        } else if ( ! strcmp( argPtr, "rmin" ) ) {
+            roundingCode = ROUND_MIN;
+        } else if ( ! strcmp( argPtr, "rmax" ) ) {
+            roundingCode = ROUND_MAX;
+        } else if (
+               ! strcmp( argPtr, "rnear_maxmag" )
+            || ! strcmp( argPtr, "rnear_maxMag" )
+            || ! strcmp( argPtr, "rnearmaxmag" )
+            || ! strcmp( argPtr, "rnearest_maxmag" )
+            || ! strcmp( argPtr, "rnearest_maxMag" )
+        ) {
+            roundingCode = ROUND_NEAR_MAXMAG;
+#ifdef FLOAT_ROUND_ODD
+        } else if ( ! strcmp( argPtr, "rodd" ) ) {
+            roundingCode = ROUND_ODD;
+#endif
+        } else if ( ! strcmp( argPtr, "tininessbefore" ) ) {
+            tininessCode = TININESS_BEFORE_ROUNDING;
+        } else if ( ! strcmp( argPtr, "tininessafter" ) ) {
+            tininessCode = TININESS_AFTER_ROUNDING;
+        } else if ( ! strcmp( argPtr, "notexact" ) ) {
+            exact = false;
+        } else if ( ! strcmp( argPtr, "exact" ) ) {
+            exact = true;
+        } else {
+            functionCode = 1;
+            while ( strcmp( argPtr, functionInfos[functionCode].namePtr ) ) {
+                ++functionCode;
+                if ( functionCode == NUM_FUNCTIONS ) goto invalidArg;
+            }
+            functionAttribs = functionInfos[functionCode].attribs;
+            if (
+                (functionAttribs & FUNC_ARG_EXACT)
+                    && ! (functionAttribs & FUNC_ARG_ROUNDINGMODE)
+            ) {
+                goto invalidArg;
+            }
+        }
+    }
+    if ( ! functionCode ) fail( "Function argument required" );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    verCases_functionNamePtr = functionInfos[functionCode].namePtr;
+#ifdef EXTFLOAT80
+    verCases_roundingPrecision =
+        functionAttribs & FUNC_EFF_ROUNDINGPRECISION ? extF80_roundingPrecision
+            : 0;
+#endif
+    verCases_roundingCode =
+        functionAttribs & (FUNC_ARG_ROUNDINGMODE | FUNC_EFF_ROUNDINGMODE)
+            ? roundingCode
+            : 0;
+#ifdef EXTFLOAT80
+    verCases_tininessCode =
+        (functionAttribs & FUNC_EFF_TININESSMODE)
+            || ((functionAttribs & FUNC_EFF_TININESSMODE_REDUCEDPREC)
+                    && extF80_roundingPrecision
+                    && (extF80_roundingPrecision < 80))
+            ? tininessCode
+            : 0;
+#else
+    verCases_tininessCode =
+        functionAttribs & FUNC_EFF_TININESSMODE ? tininessCode : 0;
+#endif
+    verCases_usesExact = ((functionAttribs & FUNC_ARG_EXACT) != 0);
+    verCases_exact = exact;
+    roundingMode = roundingModes[roundingCode];
+    softfloat_roundingMode = roundingMode;
+    softfloat_detectTininess = tininessModes[tininessCode];
+    signal( SIGINT, catchSIGINT );
+    signal( SIGTERM, catchSIGINT );
+    fputs( "Testing ", stderr );
+    verCases_writeFunctionName( stderr );
+    fputs( ".\n", stderr );
+    switch ( functionCode ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case UI32_TO_F16:
+        ver_a_ui32_z_f16( ui32_to_f16 );
+        break;
+#endif
+     case UI32_TO_F32:
+        ver_a_ui32_z_f32( ui32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI32_TO_F64:
+        ver_a_ui32_z_f64( ui32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI32_TO_EXTF80:
+        ver_a_ui32_z_extF80( ui32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI32_TO_F128:
+        ver_a_ui32_z_f128( ui32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case UI64_TO_F16:
+        ver_a_ui64_z_f16( ui64_to_f16 );
+        break;
+#endif
+     case UI64_TO_F32:
+        ver_a_ui64_z_f32( ui64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI64_TO_F64:
+        ver_a_ui64_z_f64( ui64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI64_TO_EXTF80:
+        ver_a_ui64_z_extF80( ui64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI64_TO_F128:
+        ver_a_ui64_z_f128( ui64_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I32_TO_F16:
+        ver_a_i32_z_f16( i32_to_f16 );
+        break;
+#endif
+     case I32_TO_F32:
+        ver_a_i32_z_f32( i32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I32_TO_F64:
+        ver_a_i32_z_f64( i32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I32_TO_EXTF80:
+        ver_a_i32_z_extF80( i32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I32_TO_F128:
+        ver_a_i32_z_f128( i32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I64_TO_F16:
+        ver_a_i64_z_f16( i64_to_f16 );
+        break;
+#endif
+     case I64_TO_F32:
+        ver_a_i64_z_f32( i64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I64_TO_F64:
+        ver_a_i64_z_f64( i64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I64_TO_EXTF80:
+        ver_a_i64_z_extF80( i64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I64_TO_F128:
+        ver_a_i64_z_f128( i64_to_f128M );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case F16_TO_UI32:
+        ver_a_f16_z_ui32_rx( f16_to_ui32, roundingMode, exact );
+        break;
+     case F16_TO_UI64:
+        ver_a_f16_z_ui64_rx( f16_to_ui64, roundingMode, exact );
+        break;
+     case F16_TO_I32:
+        ver_a_f16_z_i32_rx( f16_to_i32, roundingMode, exact );
+        break;
+     case F16_TO_I64:
+        ver_a_f16_z_i64_rx( f16_to_i64, roundingMode, exact );
+        break;
+     case F16_TO_F32:
+        ver_a_f16_z_f32( f16_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F16_TO_F64:
+        ver_a_f16_z_f64( f16_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F16_TO_EXTF80:
+        ver_a_f16_z_extF80( f16_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F16_TO_F128:
+        ver_a_f16_z_f128( f16_to_f128M );
+        break;
+#endif
+     case F16_ROUNDTOINT:
+        ver_az_f16_rx( f16_roundToInt, roundingMode, exact );
+        break;
+     case F16_ADD:
+        trueFunction_abz_f16 = f16_add;
+        goto ver_abz_f16;
+     case F16_SUB:
+        trueFunction_abz_f16 = f16_sub;
+        goto ver_abz_f16;
+     case F16_MUL:
+        trueFunction_abz_f16 = f16_mul;
+        goto ver_abz_f16;
+     case F16_DIV:
+        trueFunction_abz_f16 = f16_div;
+        goto ver_abz_f16;
+     case F16_REM:
+        trueFunction_abz_f16 = f16_rem;
+     ver_abz_f16:
+        ver_abz_f16( trueFunction_abz_f16 );
+        break;
+     case F16_MULADD:
+        ver_abcz_f16( f16_mulAdd );
+        break;
+     case F16_SQRT:
+        ver_az_f16( f16_sqrt );
+        break;
+     case F16_EQ:
+        trueFunction_ab_f16_z_bool = f16_eq;
+        goto ver_ab_f16_z_bool;
+     case F16_LE:
+        trueFunction_ab_f16_z_bool = f16_le;
+        goto ver_ab_f16_z_bool;
+     case F16_LT:
+        trueFunction_ab_f16_z_bool = f16_lt;
+        goto ver_ab_f16_z_bool;
+     case F16_EQ_SIGNALING:
+        trueFunction_ab_f16_z_bool = f16_eq_signaling;
+        goto ver_ab_f16_z_bool;
+     case F16_LE_QUIET:
+        trueFunction_ab_f16_z_bool = f16_le_quiet;
+        goto ver_ab_f16_z_bool;
+     case F16_LT_QUIET:
+        trueFunction_ab_f16_z_bool = f16_lt_quiet;
+     ver_ab_f16_z_bool:
+        ver_ab_f16_z_bool( trueFunction_ab_f16_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case F32_TO_UI32:
+        ver_a_f32_z_ui32_rx( f32_to_ui32, roundingMode, exact );
+        break;
+     case F32_TO_UI64:
+        ver_a_f32_z_ui64_rx( f32_to_ui64, roundingMode, exact );
+        break;
+     case F32_TO_I32:
+        ver_a_f32_z_i32_rx( f32_to_i32, roundingMode, exact );
+        break;
+     case F32_TO_I64:
+        ver_a_f32_z_i64_rx( f32_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F32_TO_F16:
+        ver_a_f32_z_f16( f32_to_f16 );
+        break;
+#endif
+#ifdef FLOAT64
+     case F32_TO_F64:
+        ver_a_f32_z_f64( f32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F32_TO_EXTF80:
+        ver_a_f32_z_extF80( f32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F32_TO_F128:
+        ver_a_f32_z_f128( f32_to_f128M );
+        break;
+#endif
+     case F32_ROUNDTOINT:
+        ver_az_f32_rx( f32_roundToInt, roundingMode, exact );
+        break;
+     case F32_ADD:
+        trueFunction_abz_f32 = f32_add;
+        goto ver_abz_f32;
+     case F32_SUB:
+        trueFunction_abz_f32 = f32_sub;
+        goto ver_abz_f32;
+     case F32_MUL:
+        trueFunction_abz_f32 = f32_mul;
+        goto ver_abz_f32;
+     case F32_DIV:
+        trueFunction_abz_f32 = f32_div;
+        goto ver_abz_f32;
+     case F32_REM:
+        trueFunction_abz_f32 = f32_rem;
+     ver_abz_f32:
+        ver_abz_f32( trueFunction_abz_f32 );
+        break;
+     case F32_MULADD:
+        ver_abcz_f32( f32_mulAdd );
+        break;
+     case F32_SQRT:
+        ver_az_f32( f32_sqrt );
+        break;
+     case F32_EQ:
+        trueFunction_ab_f32_z_bool = f32_eq;
+        goto ver_ab_f32_z_bool;
+     case F32_LE:
+        trueFunction_ab_f32_z_bool = f32_le;
+        goto ver_ab_f32_z_bool;
+     case F32_LT:
+        trueFunction_ab_f32_z_bool = f32_lt;
+        goto ver_ab_f32_z_bool;
+     case F32_EQ_SIGNALING:
+        trueFunction_ab_f32_z_bool = f32_eq_signaling;
+        goto ver_ab_f32_z_bool;
+     case F32_LE_QUIET:
+        trueFunction_ab_f32_z_bool = f32_le_quiet;
+        goto ver_ab_f32_z_bool;
+     case F32_LT_QUIET:
+        trueFunction_ab_f32_z_bool = f32_lt_quiet;
+     ver_ab_f32_z_bool:
+        ver_ab_f32_z_bool( trueFunction_ab_f32_z_bool );
+        break;
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT64
+     case F64_TO_UI32:
+        ver_a_f64_z_ui32_rx( f64_to_ui32, roundingMode, exact );
+        break;
+     case F64_TO_UI64:
+        ver_a_f64_z_ui64_rx( f64_to_ui64, roundingMode, exact );
+        break;
+     case F64_TO_I32:
+        ver_a_f64_z_i32_rx( f64_to_i32, roundingMode, exact );
+        break;
+     case F64_TO_I64:
+        ver_a_f64_z_i64_rx( f64_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F64_TO_F16:
+        ver_a_f64_z_f16( f64_to_f16 );
+        break;
+#endif
+     case F64_TO_F32:
+        ver_a_f64_z_f32( f64_to_f32 );
+        break;
+#ifdef EXTFLOAT80
+     case F64_TO_EXTF80:
+        ver_a_f64_z_extF80( f64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F64_TO_F128:
+        ver_a_f64_z_f128( f64_to_f128M );
+        break;
+#endif
+     case F64_ROUNDTOINT:
+        ver_az_f64_rx( f64_roundToInt, roundingMode, exact );
+        break;
+     case F64_ADD:
+        trueFunction_abz_f64 = f64_add;
+        goto ver_abz_f64;
+     case F64_SUB:
+        trueFunction_abz_f64 = f64_sub;
+        goto ver_abz_f64;
+     case F64_MUL:
+        trueFunction_abz_f64 = f64_mul;
+        goto ver_abz_f64;
+     case F64_DIV:
+        trueFunction_abz_f64 = f64_div;
+        goto ver_abz_f64;
+     case F64_REM:
+        trueFunction_abz_f64 = f64_rem;
+     ver_abz_f64:
+        ver_abz_f64( trueFunction_abz_f64 );
+        break;
+     case F64_MULADD:
+        ver_abcz_f64( f64_mulAdd );
+        break;
+     case F64_SQRT:
+        ver_az_f64( f64_sqrt );
+        break;
+     case F64_EQ:
+        trueFunction_ab_f64_z_bool = f64_eq;
+        goto ver_ab_f64_z_bool;
+     case F64_LE:
+        trueFunction_ab_f64_z_bool = f64_le;
+        goto ver_ab_f64_z_bool;
+     case F64_LT:
+        trueFunction_ab_f64_z_bool = f64_lt;
+        goto ver_ab_f64_z_bool;
+     case F64_EQ_SIGNALING:
+        trueFunction_ab_f64_z_bool = f64_eq_signaling;
+        goto ver_ab_f64_z_bool;
+     case F64_LE_QUIET:
+        trueFunction_ab_f64_z_bool = f64_le_quiet;
+        goto ver_ab_f64_z_bool;
+     case F64_LT_QUIET:
+        trueFunction_ab_f64_z_bool = f64_lt_quiet;
+     ver_ab_f64_z_bool:
+        ver_ab_f64_z_bool( trueFunction_ab_f64_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+     case EXTF80_TO_UI32:
+        ver_a_extF80_z_ui32_rx( extF80M_to_ui32, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI64:
+        ver_a_extF80_z_ui64_rx( extF80M_to_ui64, roundingMode, exact );
+        break;
+     case EXTF80_TO_I32:
+        ver_a_extF80_z_i32_rx( extF80M_to_i32, roundingMode, exact );
+        break;
+     case EXTF80_TO_I64:
+        ver_a_extF80_z_i64_rx( extF80M_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case EXTF80_TO_F16:
+        ver_a_extF80_z_f16( extF80M_to_f16 );
+        break;
+#endif
+     case EXTF80_TO_F32:
+        ver_a_extF80_z_f32( extF80M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case EXTF80_TO_F64:
+        ver_a_extF80_z_f64( extF80M_to_f64 );
+        break;
+#endif
+#ifdef FLOAT128
+     case EXTF80_TO_F128:
+        ver_a_extF80_z_f128( extF80M_to_f128M );
+        break;
+#endif
+     case EXTF80_ROUNDTOINT:
+        ver_az_extF80_rx( extF80M_roundToInt, roundingMode, exact );
+        break;
+     case EXTF80_ADD:
+        trueFunction_abz_extF80 = extF80M_add;
+        goto ver_abz_extF80;
+     case EXTF80_SUB:
+        trueFunction_abz_extF80 = extF80M_sub;
+        goto ver_abz_extF80;
+     case EXTF80_MUL:
+        trueFunction_abz_extF80 = extF80M_mul;
+        goto ver_abz_extF80;
+     case EXTF80_DIV:
+        trueFunction_abz_extF80 = extF80M_div;
+        goto ver_abz_extF80;
+     case EXTF80_REM:
+        trueFunction_abz_extF80 = extF80M_rem;
+     ver_abz_extF80:
+        ver_abz_extF80( trueFunction_abz_extF80 );
+        break;
+     case EXTF80_SQRT:
+        ver_az_extF80( extF80M_sqrt );
+        break;
+     case EXTF80_EQ:
+        trueFunction_ab_extF80_z_bool = extF80M_eq;
+        goto ver_ab_extF80_z_bool;
+     case EXTF80_LE:
+        trueFunction_ab_extF80_z_bool = extF80M_le;
+        goto ver_ab_extF80_z_bool;
+     case EXTF80_LT:
+        trueFunction_ab_extF80_z_bool = extF80M_lt;
+        goto ver_ab_extF80_z_bool;
+     case EXTF80_EQ_SIGNALING:
+        trueFunction_ab_extF80_z_bool = extF80M_eq_signaling;
+        goto ver_ab_extF80_z_bool;
+     case EXTF80_LE_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_le_quiet;
+        goto ver_ab_extF80_z_bool;
+     case EXTF80_LT_QUIET:
+        trueFunction_ab_extF80_z_bool = extF80M_lt_quiet;
+     ver_ab_extF80_z_bool:
+        ver_ab_extF80_z_bool( trueFunction_ab_extF80_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT128
+     case F128_TO_UI32:
+        ver_a_f128_z_ui32_rx( f128M_to_ui32, roundingMode, exact );
+        break;
+     case F128_TO_UI64:
+        ver_a_f128_z_ui64_rx( f128M_to_ui64, roundingMode, exact );
+        break;
+     case F128_TO_I32:
+        ver_a_f128_z_i32_rx( f128M_to_i32, roundingMode, exact );
+        break;
+     case F128_TO_I64:
+        ver_a_f128_z_i64_rx( f128M_to_i64, roundingMode, exact );
+        break;
+#ifdef FLOAT16
+     case F128_TO_F16:
+        ver_a_f128_z_f16( f128M_to_f16 );
+        break;
+#endif
+     case F128_TO_F32:
+        ver_a_f128_z_f32( f128M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F128_TO_F64:
+        ver_a_f128_z_f64( f128M_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F128_TO_EXTF80:
+        ver_a_f128_z_extF80( f128M_to_extF80M );
+        break;
+#endif
+     case F128_ROUNDTOINT:
+        ver_az_f128_rx( f128M_roundToInt, roundingMode, exact );
+        break;
+     case F128_ADD:
+        trueFunction_abz_f128 = f128M_add;
+        goto ver_abz_f128;
+     case F128_SUB:
+        trueFunction_abz_f128 = f128M_sub;
+        goto ver_abz_f128;
+     case F128_MUL:
+        trueFunction_abz_f128 = f128M_mul;
+        goto ver_abz_f128;
+     case F128_DIV:
+        trueFunction_abz_f128 = f128M_div;
+        goto ver_abz_f128;
+     case F128_REM:
+        trueFunction_abz_f128 = f128M_rem;
+     ver_abz_f128:
+        ver_abz_f128( trueFunction_abz_f128 );
+        break;
+     case F128_MULADD:
+        ver_abcz_f128( f128M_mulAdd );
+        break;
+     case F128_SQRT:
+        ver_az_f128( f128M_sqrt );
+        break;
+     case F128_EQ:
+        trueFunction_ab_f128_z_bool = f128M_eq;
+        goto ver_ab_f128_z_bool;
+     case F128_LE:
+        trueFunction_ab_f128_z_bool = f128M_le;
+        goto ver_ab_f128_z_bool;
+     case F128_LT:
+        trueFunction_ab_f128_z_bool = f128M_lt;
+        goto ver_ab_f128_z_bool;
+     case F128_EQ_SIGNALING:
+        trueFunction_ab_f128_z_bool = f128M_eq_signaling;
+        goto ver_ab_f128_z_bool;
+     case F128_LE_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_le_quiet;
+        goto ver_ab_f128_z_bool;
+     case F128_LT_QUIET:
+        trueFunction_ab_f128_z_bool = f128M_lt_quiet;
+     ver_ab_f128_z_bool:
+        ver_ab_f128_z_bool( trueFunction_ab_f128_z_bool );
+        break;
+#endif
+    }
+    verCases_exitWithStatus();
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ optionError:
+    fail( "'%s' option requires numeric argument", *argv );
+ invalidArg:
+    fail( "Invalid argument '%s'", *argv );
+
+}
+
diff --git a/addins/TestFloat-3e/source/testsoftfloat.c b/addins/TestFloat-3e/source/testsoftfloat.c
new file mode 100644
index 000000000..2b098124f
--- /dev/null
+++ b/addins/TestFloat-3e/source/testsoftfloat.c
@@ -0,0 +1,1127 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "slowfloat.h"
+#include "functions.h"
+#include "genCases.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "testLoops.h"
+
+static void catchSIGINT( int signalCode )
+{
+
+    if ( verCases_stop ) exit( EXIT_FAILURE );
+    verCases_stop = true;
+
+}
+
+static uint_fast8_t softfloat_clearExceptionFlags( void )
+{
+    uint_fast8_t prevFlags;
+
+    prevFlags = softfloat_exceptionFlags;
+    softfloat_exceptionFlags = 0;
+    return prevFlags;
+
+}
+
+static
+void
+ testFunctionInstance(
+     int functionCode, uint_fast8_t roundingMode, bool exact )
+{
+#ifdef FLOAT16
+    float16_t (*trueFunction_abz_f16)( float16_t, float16_t );
+    float16_t (*subjFunction_abz_f16)( float16_t, float16_t );
+    bool (*trueFunction_ab_f16_z_bool)( float16_t, float16_t );
+    bool (*subjFunction_ab_f16_z_bool)( float16_t, float16_t );
+#endif
+    float32_t (*trueFunction_abz_f32)( float32_t, float32_t );
+    float32_t (*subjFunction_abz_f32)( float32_t, float32_t );
+    bool (*trueFunction_ab_f32_z_bool)( float32_t, float32_t );
+    bool (*subjFunction_ab_f32_z_bool)( float32_t, float32_t );
+#ifdef FLOAT64
+    float64_t (*trueFunction_abz_f64)( float64_t, float64_t );
+    float64_t (*subjFunction_abz_f64)( float64_t, float64_t );
+    bool (*trueFunction_ab_f64_z_bool)( float64_t, float64_t );
+    bool (*subjFunction_ab_f64_z_bool)( float64_t, float64_t );
+#endif
+#ifdef EXTFLOAT80
+    void (*trueFunction_abz_extF80M)(
+        const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+    void (*subjFunction_abz_extF80M)(
+        const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+    bool (*trueFunction_ab_extF80M_z_bool)(
+        const extFloat80_t *, const extFloat80_t * );
+    bool (*subjFunction_ab_extF80M_z_bool)(
+        const extFloat80_t *, const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+    void (*trueFunction_abz_f128M)(
+        const float128_t *, const float128_t *, float128_t * );
+    void (*subjFunction_abz_f128M)(
+        const float128_t *, const float128_t *, float128_t * );
+    bool (*trueFunction_ab_f128M_z_bool)(
+        const float128_t *, const float128_t * );
+    bool (*subjFunction_ab_f128M_z_bool)(
+        const float128_t *, const float128_t * );
+#endif
+
+    fputs( "Testing ", stderr );
+    verCases_writeFunctionName( stderr );
+    fputs( ".\n", stderr );
+    switch ( functionCode ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case UI32_TO_F16:
+        test_a_ui32_z_f16( slow_ui32_to_f16, ui32_to_f16 );
+        break;
+#endif
+     case UI32_TO_F32:
+        test_a_ui32_z_f32( slow_ui32_to_f32, ui32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI32_TO_F64:
+        test_a_ui32_z_f64( slow_ui32_to_f64, ui32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI32_TO_EXTF80:
+        test_a_ui32_z_extF80( slow_ui32_to_extF80M, ui32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI32_TO_F128:
+        test_a_ui32_z_f128( slow_ui32_to_f128M, ui32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case UI64_TO_F16:
+        test_a_ui64_z_f16( slow_ui64_to_f16, ui64_to_f16 );
+        break;
+#endif
+     case UI64_TO_F32:
+        test_a_ui64_z_f32( slow_ui64_to_f32, ui64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI64_TO_F64:
+        test_a_ui64_z_f64( slow_ui64_to_f64, ui64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI64_TO_EXTF80:
+        test_a_ui64_z_extF80( slow_ui64_to_extF80M, ui64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI64_TO_F128:
+        test_a_ui64_z_f128( slow_ui64_to_f128M, ui64_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I32_TO_F16:
+        test_a_i32_z_f16( slow_i32_to_f16, i32_to_f16 );
+        break;
+#endif
+     case I32_TO_F32:
+        test_a_i32_z_f32( slow_i32_to_f32, i32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I32_TO_F64:
+        test_a_i32_z_f64( slow_i32_to_f64, i32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I32_TO_EXTF80:
+        test_a_i32_z_extF80( slow_i32_to_extF80M, i32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I32_TO_F128:
+        test_a_i32_z_f128( slow_i32_to_f128M, i32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I64_TO_F16:
+        test_a_i64_z_f16( slow_i64_to_f16, i64_to_f16 );
+        break;
+#endif
+     case I64_TO_F32:
+        test_a_i64_z_f32( slow_i64_to_f32, i64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I64_TO_F64:
+        test_a_i64_z_f64( slow_i64_to_f64, i64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I64_TO_EXTF80:
+        test_a_i64_z_extF80( slow_i64_to_extF80M, i64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I64_TO_F128:
+        test_a_i64_z_f128( slow_i64_to_f128M, i64_to_f128M );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case F16_TO_UI32:
+        test_a_f16_z_ui32_rx(
+            slow_f16_to_ui32, f16_to_ui32, roundingMode, exact );
+        break;
+     case F16_TO_UI64:
+        test_a_f16_z_ui64_rx(
+            slow_f16_to_ui64, f16_to_ui64, roundingMode, exact );
+        break;
+     case F16_TO_I32:
+        test_a_f16_z_i32_rx(
+            slow_f16_to_i32, f16_to_i32, roundingMode, exact );
+        break;
+     case F16_TO_I64:
+        test_a_f16_z_i64_rx(
+            slow_f16_to_i64, f16_to_i64, roundingMode, exact );
+        break;
+     case F16_TO_UI32_R_MINMAG:
+        test_a_f16_z_ui32_x(
+            slow_f16_to_ui32_r_minMag, f16_to_ui32_r_minMag, exact );
+        break;
+     case F16_TO_UI64_R_MINMAG:
+        test_a_f16_z_ui64_x(
+            slow_f16_to_ui64_r_minMag, f16_to_ui64_r_minMag, exact );
+        break;
+     case F16_TO_I32_R_MINMAG:
+        test_a_f16_z_i32_x(
+            slow_f16_to_i32_r_minMag, f16_to_i32_r_minMag, exact );
+        break;
+     case F16_TO_I64_R_MINMAG:
+        test_a_f16_z_i64_x(
+            slow_f16_to_i64_r_minMag, f16_to_i64_r_minMag, exact );
+        break;
+     case F16_TO_F32:
+        test_a_f16_z_f32( slow_f16_to_f32, f16_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F16_TO_F64:
+        test_a_f16_z_f64( slow_f16_to_f64, f16_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F16_TO_EXTF80:
+        test_a_f16_z_extF80( slow_f16_to_extF80M, f16_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F16_TO_F128:
+        test_a_f16_z_f128( slow_f16_to_f128M, f16_to_f128M );
+        break;
+#endif
+     case F16_ROUNDTOINT:
+        test_az_f16_rx(
+            slow_f16_roundToInt, f16_roundToInt, roundingMode, exact );
+        break;
+     case F16_ADD:
+        trueFunction_abz_f16 = slow_f16_add;
+        subjFunction_abz_f16 = f16_add;
+        goto test_abz_f16;
+     case F16_SUB:
+        trueFunction_abz_f16 = slow_f16_sub;
+        subjFunction_abz_f16 = f16_sub;
+        goto test_abz_f16;
+     case F16_MUL:
+        trueFunction_abz_f16 = slow_f16_mul;
+        subjFunction_abz_f16 = f16_mul;
+        goto test_abz_f16;
+     case F16_DIV:
+        trueFunction_abz_f16 = slow_f16_div;
+        subjFunction_abz_f16 = f16_div;
+        goto test_abz_f16;
+     case F16_REM:
+        trueFunction_abz_f16 = slow_f16_rem;
+        subjFunction_abz_f16 = f16_rem;
+     test_abz_f16:
+        test_abz_f16( trueFunction_abz_f16, subjFunction_abz_f16 );
+        break;
+     case F16_MULADD:
+        test_abcz_f16( slow_f16_mulAdd, f16_mulAdd );
+        break;
+     case F16_SQRT:
+        test_az_f16( slow_f16_sqrt, f16_sqrt );
+        break;
+     case F16_EQ:
+        trueFunction_ab_f16_z_bool = slow_f16_eq;
+        subjFunction_ab_f16_z_bool = f16_eq;
+        goto test_ab_f16_z_bool;
+     case F16_LE:
+        trueFunction_ab_f16_z_bool = slow_f16_le;
+        subjFunction_ab_f16_z_bool = f16_le;
+        goto test_ab_f16_z_bool;
+     case F16_LT:
+        trueFunction_ab_f16_z_bool = slow_f16_lt;
+        subjFunction_ab_f16_z_bool = f16_lt;
+        goto test_ab_f16_z_bool;
+     case F16_EQ_SIGNALING:
+        trueFunction_ab_f16_z_bool = slow_f16_eq_signaling;
+        subjFunction_ab_f16_z_bool = f16_eq_signaling;
+        goto test_ab_f16_z_bool;
+     case F16_LE_QUIET:
+        trueFunction_ab_f16_z_bool = slow_f16_le_quiet;
+        subjFunction_ab_f16_z_bool = f16_le_quiet;
+        goto test_ab_f16_z_bool;
+     case F16_LT_QUIET:
+        trueFunction_ab_f16_z_bool = slow_f16_lt_quiet;
+        subjFunction_ab_f16_z_bool = f16_lt_quiet;
+     test_ab_f16_z_bool:
+        test_ab_f16_z_bool(
+            trueFunction_ab_f16_z_bool, subjFunction_ab_f16_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case F32_TO_UI32:
+        test_a_f32_z_ui32_rx(
+            slow_f32_to_ui32, f32_to_ui32, roundingMode, exact );
+        break;
+     case F32_TO_UI64:
+        test_a_f32_z_ui64_rx(
+            slow_f32_to_ui64, f32_to_ui64, roundingMode, exact );
+        break;
+     case F32_TO_I32:
+        test_a_f32_z_i32_rx(
+            slow_f32_to_i32, f32_to_i32, roundingMode, exact );
+        break;
+     case F32_TO_I64:
+        test_a_f32_z_i64_rx(
+            slow_f32_to_i64, f32_to_i64, roundingMode, exact );
+        break;
+     case F32_TO_UI32_R_MINMAG:
+        test_a_f32_z_ui32_x(
+            slow_f32_to_ui32_r_minMag, f32_to_ui32_r_minMag, exact );
+        break;
+     case F32_TO_UI64_R_MINMAG:
+        test_a_f32_z_ui64_x(
+            slow_f32_to_ui64_r_minMag, f32_to_ui64_r_minMag, exact );
+        break;
+     case F32_TO_I32_R_MINMAG:
+        test_a_f32_z_i32_x(
+            slow_f32_to_i32_r_minMag, f32_to_i32_r_minMag, exact );
+        break;
+     case F32_TO_I64_R_MINMAG:
+        test_a_f32_z_i64_x(
+            slow_f32_to_i64_r_minMag, f32_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F32_TO_F16:
+        test_a_f32_z_f16( slow_f32_to_f16, f32_to_f16 );
+        break;
+#endif
+#ifdef FLOAT64
+     case F32_TO_F64:
+        test_a_f32_z_f64( slow_f32_to_f64, f32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F32_TO_EXTF80:
+        test_a_f32_z_extF80( slow_f32_to_extF80M, f32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F32_TO_F128:
+        test_a_f32_z_f128( slow_f32_to_f128M, f32_to_f128M );
+        break;
+#endif
+     case F32_ROUNDTOINT:
+        test_az_f32_rx(
+            slow_f32_roundToInt, f32_roundToInt, roundingMode, exact );
+        break;
+     case F32_ADD:
+        trueFunction_abz_f32 = slow_f32_add;
+        subjFunction_abz_f32 = f32_add;
+        goto test_abz_f32;
+     case F32_SUB:
+        trueFunction_abz_f32 = slow_f32_sub;
+        subjFunction_abz_f32 = f32_sub;
+        goto test_abz_f32;
+     case F32_MUL:
+        trueFunction_abz_f32 = slow_f32_mul;
+        subjFunction_abz_f32 = f32_mul;
+        goto test_abz_f32;
+     case F32_DIV:
+        trueFunction_abz_f32 = slow_f32_div;
+        subjFunction_abz_f32 = f32_div;
+        goto test_abz_f32;
+     case F32_REM:
+        trueFunction_abz_f32 = slow_f32_rem;
+        subjFunction_abz_f32 = f32_rem;
+     test_abz_f32:
+        test_abz_f32( trueFunction_abz_f32, subjFunction_abz_f32 );
+        break;
+     case F32_MULADD:
+        test_abcz_f32( slow_f32_mulAdd, f32_mulAdd );
+        break;
+     case F32_SQRT:
+        test_az_f32( slow_f32_sqrt, f32_sqrt );
+        break;
+     case F32_EQ:
+        trueFunction_ab_f32_z_bool = slow_f32_eq;
+        subjFunction_ab_f32_z_bool = f32_eq;
+        goto test_ab_f32_z_bool;
+     case F32_LE:
+        trueFunction_ab_f32_z_bool = slow_f32_le;
+        subjFunction_ab_f32_z_bool = f32_le;
+        goto test_ab_f32_z_bool;
+     case F32_LT:
+        trueFunction_ab_f32_z_bool = slow_f32_lt;
+        subjFunction_ab_f32_z_bool = f32_lt;
+        goto test_ab_f32_z_bool;
+     case F32_EQ_SIGNALING:
+        trueFunction_ab_f32_z_bool = slow_f32_eq_signaling;
+        subjFunction_ab_f32_z_bool = f32_eq_signaling;
+        goto test_ab_f32_z_bool;
+     case F32_LE_QUIET:
+        trueFunction_ab_f32_z_bool = slow_f32_le_quiet;
+        subjFunction_ab_f32_z_bool = f32_le_quiet;
+        goto test_ab_f32_z_bool;
+     case F32_LT_QUIET:
+        trueFunction_ab_f32_z_bool = slow_f32_lt_quiet;
+        subjFunction_ab_f32_z_bool = f32_lt_quiet;
+     test_ab_f32_z_bool:
+        test_ab_f32_z_bool(
+            trueFunction_ab_f32_z_bool, subjFunction_ab_f32_z_bool );
+        break;
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT64
+     case F64_TO_UI32:
+        test_a_f64_z_ui32_rx(
+            slow_f64_to_ui32, f64_to_ui32, roundingMode, exact );
+        break;
+     case F64_TO_UI64:
+        test_a_f64_z_ui64_rx(
+            slow_f64_to_ui64, f64_to_ui64, roundingMode, exact );
+        break;
+     case F64_TO_I32:
+        test_a_f64_z_i32_rx(
+            slow_f64_to_i32, f64_to_i32, roundingMode, exact );
+        break;
+     case F64_TO_I64:
+        test_a_f64_z_i64_rx(
+            slow_f64_to_i64, f64_to_i64, roundingMode, exact );
+        break;
+     case F64_TO_UI32_R_MINMAG:
+        test_a_f64_z_ui32_x(
+            slow_f64_to_ui32_r_minMag, f64_to_ui32_r_minMag, exact );
+        break;
+     case F64_TO_UI64_R_MINMAG:
+        test_a_f64_z_ui64_x(
+            slow_f64_to_ui64_r_minMag, f64_to_ui64_r_minMag, exact );
+        break;
+     case F64_TO_I32_R_MINMAG:
+        test_a_f64_z_i32_x(
+            slow_f64_to_i32_r_minMag, f64_to_i32_r_minMag, exact );
+        break;
+     case F64_TO_I64_R_MINMAG:
+        test_a_f64_z_i64_x(
+            slow_f64_to_i64_r_minMag, f64_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F64_TO_F16:
+        test_a_f64_z_f16( slow_f64_to_f16, f64_to_f16 );
+        break;
+#endif
+     case F64_TO_F32:
+        test_a_f64_z_f32( slow_f64_to_f32, f64_to_f32 );
+        break;
+#ifdef EXTFLOAT80
+     case F64_TO_EXTF80:
+        test_a_f64_z_extF80( slow_f64_to_extF80M, f64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F64_TO_F128:
+        test_a_f64_z_f128( slow_f64_to_f128M, f64_to_f128M );
+        break;
+#endif
+     case F64_ROUNDTOINT:
+        test_az_f64_rx(
+            slow_f64_roundToInt, f64_roundToInt, roundingMode, exact );
+        break;
+     case F64_ADD:
+        trueFunction_abz_f64 = slow_f64_add;
+        subjFunction_abz_f64 = f64_add;
+        goto test_abz_f64;
+     case F64_SUB:
+        trueFunction_abz_f64 = slow_f64_sub;
+        subjFunction_abz_f64 = f64_sub;
+        goto test_abz_f64;
+     case F64_MUL:
+        trueFunction_abz_f64 = slow_f64_mul;
+        subjFunction_abz_f64 = f64_mul;
+        goto test_abz_f64;
+     case F64_DIV:
+        trueFunction_abz_f64 = slow_f64_div;
+        subjFunction_abz_f64 = f64_div;
+        goto test_abz_f64;
+     case F64_REM:
+        trueFunction_abz_f64 = slow_f64_rem;
+        subjFunction_abz_f64 = f64_rem;
+     test_abz_f64:
+        test_abz_f64( trueFunction_abz_f64, subjFunction_abz_f64 );
+        break;
+     case F64_MULADD:
+        test_abcz_f64( slow_f64_mulAdd, f64_mulAdd );
+        break;
+     case F64_SQRT:
+        test_az_f64( slow_f64_sqrt, f64_sqrt );
+        break;
+     case F64_EQ:
+        trueFunction_ab_f64_z_bool = slow_f64_eq;
+        subjFunction_ab_f64_z_bool = f64_eq;
+        goto test_ab_f64_z_bool;
+     case F64_LE:
+        trueFunction_ab_f64_z_bool = slow_f64_le;
+        subjFunction_ab_f64_z_bool = f64_le;
+        goto test_ab_f64_z_bool;
+     case F64_LT:
+        trueFunction_ab_f64_z_bool = slow_f64_lt;
+        subjFunction_ab_f64_z_bool = f64_lt;
+        goto test_ab_f64_z_bool;
+     case F64_EQ_SIGNALING:
+        trueFunction_ab_f64_z_bool = slow_f64_eq_signaling;
+        subjFunction_ab_f64_z_bool = f64_eq_signaling;
+        goto test_ab_f64_z_bool;
+     case F64_LE_QUIET:
+        trueFunction_ab_f64_z_bool = slow_f64_le_quiet;
+        subjFunction_ab_f64_z_bool = f64_le_quiet;
+        goto test_ab_f64_z_bool;
+     case F64_LT_QUIET:
+        trueFunction_ab_f64_z_bool = slow_f64_lt_quiet;
+        subjFunction_ab_f64_z_bool = f64_lt_quiet;
+     test_ab_f64_z_bool:
+        test_ab_f64_z_bool(
+            trueFunction_ab_f64_z_bool, subjFunction_ab_f64_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+     case EXTF80_TO_UI32:
+        test_a_extF80_z_ui32_rx(
+            slow_extF80M_to_ui32, extF80M_to_ui32, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI64:
+        test_a_extF80_z_ui64_rx(
+            slow_extF80M_to_ui64, extF80M_to_ui64, roundingMode, exact );
+        break;
+     case EXTF80_TO_I32:
+        test_a_extF80_z_i32_rx(
+            slow_extF80M_to_i32, extF80M_to_i32, roundingMode, exact );
+        break;
+     case EXTF80_TO_I64:
+        test_a_extF80_z_i64_rx(
+            slow_extF80M_to_i64, extF80M_to_i64, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI32_R_MINMAG:
+        test_a_extF80_z_ui32_x(
+            slow_extF80M_to_ui32_r_minMag, extF80M_to_ui32_r_minMag, exact );
+        break;
+     case EXTF80_TO_UI64_R_MINMAG:
+        test_a_extF80_z_ui64_x(
+            slow_extF80M_to_ui64_r_minMag, extF80M_to_ui64_r_minMag, exact );
+        break;
+     case EXTF80_TO_I32_R_MINMAG:
+        test_a_extF80_z_i32_x(
+            slow_extF80M_to_i32_r_minMag, extF80M_to_i32_r_minMag, exact );
+        break;
+     case EXTF80_TO_I64_R_MINMAG:
+        test_a_extF80_z_i64_x(
+            slow_extF80M_to_i64_r_minMag, extF80M_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case EXTF80_TO_F16:
+        test_a_extF80_z_f16( slow_extF80M_to_f16, extF80M_to_f16 );
+        break;
+#endif
+     case EXTF80_TO_F32:
+        test_a_extF80_z_f32( slow_extF80M_to_f32, extF80M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case EXTF80_TO_F64:
+        test_a_extF80_z_f64( slow_extF80M_to_f64, extF80M_to_f64 );
+        break;
+#endif
+#ifdef FLOAT128
+     case EXTF80_TO_F128:
+        test_a_extF80_z_f128( slow_extF80M_to_f128M, extF80M_to_f128M );
+        break;
+#endif
+     case EXTF80_ROUNDTOINT:
+        test_az_extF80_rx(
+            slow_extF80M_roundToInt, extF80M_roundToInt, roundingMode, exact );
+        break;
+     case EXTF80_ADD:
+        trueFunction_abz_extF80M = slow_extF80M_add;
+        subjFunction_abz_extF80M = extF80M_add;
+        goto test_abz_extF80;
+     case EXTF80_SUB:
+        trueFunction_abz_extF80M = slow_extF80M_sub;
+        subjFunction_abz_extF80M = extF80M_sub;
+        goto test_abz_extF80;
+     case EXTF80_MUL:
+        trueFunction_abz_extF80M = slow_extF80M_mul;
+        subjFunction_abz_extF80M = extF80M_mul;
+        goto test_abz_extF80;
+     case EXTF80_DIV:
+        trueFunction_abz_extF80M = slow_extF80M_div;
+        subjFunction_abz_extF80M = extF80M_div;
+        goto test_abz_extF80;
+     case EXTF80_REM:
+        trueFunction_abz_extF80M = slow_extF80M_rem;
+        subjFunction_abz_extF80M = extF80M_rem;
+     test_abz_extF80:
+        test_abz_extF80( trueFunction_abz_extF80M, subjFunction_abz_extF80M );
+        break;
+     case EXTF80_SQRT:
+        test_az_extF80( slow_extF80M_sqrt, extF80M_sqrt );
+        break;
+     case EXTF80_EQ:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_eq;
+        subjFunction_ab_extF80M_z_bool = extF80M_eq;
+        goto test_ab_extF80_z_bool;
+     case EXTF80_LE:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_le;
+        subjFunction_ab_extF80M_z_bool = extF80M_le;
+        goto test_ab_extF80_z_bool;
+     case EXTF80_LT:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_lt;
+        subjFunction_ab_extF80M_z_bool = extF80M_lt;
+        goto test_ab_extF80_z_bool;
+     case EXTF80_EQ_SIGNALING:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_eq_signaling;
+        subjFunction_ab_extF80M_z_bool = extF80M_eq_signaling;
+        goto test_ab_extF80_z_bool;
+     case EXTF80_LE_QUIET:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_le_quiet;
+        subjFunction_ab_extF80M_z_bool = extF80M_le_quiet;
+        goto test_ab_extF80_z_bool;
+     case EXTF80_LT_QUIET:
+        trueFunction_ab_extF80M_z_bool = slow_extF80M_lt_quiet;
+        subjFunction_ab_extF80M_z_bool = extF80M_lt_quiet;
+     test_ab_extF80_z_bool:
+        test_ab_extF80_z_bool(
+            trueFunction_ab_extF80M_z_bool, subjFunction_ab_extF80M_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT128
+     case F128_TO_UI32:
+        test_a_f128_z_ui32_rx(
+            slow_f128M_to_ui32, f128M_to_ui32, roundingMode, exact );
+        break;
+     case F128_TO_UI64:
+        test_a_f128_z_ui64_rx(
+            slow_f128M_to_ui64, f128M_to_ui64, roundingMode, exact );
+        break;
+     case F128_TO_I32:
+        test_a_f128_z_i32_rx(
+            slow_f128M_to_i32, f128M_to_i32, roundingMode, exact );
+        break;
+     case F128_TO_I64:
+        test_a_f128_z_i64_rx(
+            slow_f128M_to_i64, f128M_to_i64, roundingMode, exact );
+        break;
+     case F128_TO_UI32_R_MINMAG:
+        test_a_f128_z_ui32_x(
+            slow_f128M_to_ui32_r_minMag, f128M_to_ui32_r_minMag, exact );
+        break;
+     case F128_TO_UI64_R_MINMAG:
+        test_a_f128_z_ui64_x(
+            slow_f128M_to_ui64_r_minMag, f128M_to_ui64_r_minMag, exact );
+        break;
+     case F128_TO_I32_R_MINMAG:
+        test_a_f128_z_i32_x(
+            slow_f128M_to_i32_r_minMag, f128M_to_i32_r_minMag, exact );
+        break;
+     case F128_TO_I64_R_MINMAG:
+        test_a_f128_z_i64_x(
+            slow_f128M_to_i64_r_minMag, f128M_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F128_TO_F16:
+        test_a_f128_z_f16( slow_f128M_to_f16, f128M_to_f16 );
+        break;
+#endif
+     case F128_TO_F32:
+        test_a_f128_z_f32( slow_f128M_to_f32, f128M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F128_TO_F64:
+        test_a_f128_z_f64( slow_f128M_to_f64, f128M_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F128_TO_EXTF80:
+        test_a_f128_z_extF80( slow_f128M_to_extF80M, f128M_to_extF80M );
+        break;
+#endif
+     case F128_ROUNDTOINT:
+        test_az_f128_rx(
+            slow_f128M_roundToInt, f128M_roundToInt, roundingMode, exact );
+        break;
+     case F128_ADD:
+        trueFunction_abz_f128M = slow_f128M_add;
+        subjFunction_abz_f128M = f128M_add;
+        goto test_abz_f128;
+     case F128_SUB:
+        trueFunction_abz_f128M = slow_f128M_sub;
+        subjFunction_abz_f128M = f128M_sub;
+        goto test_abz_f128;
+     case F128_MUL:
+        trueFunction_abz_f128M = slow_f128M_mul;
+        subjFunction_abz_f128M = f128M_mul;
+        goto test_abz_f128;
+     case F128_DIV:
+        trueFunction_abz_f128M = slow_f128M_div;
+        subjFunction_abz_f128M = f128M_div;
+        goto test_abz_f128;
+     case F128_REM:
+        trueFunction_abz_f128M = slow_f128M_rem;
+        subjFunction_abz_f128M = f128M_rem;
+     test_abz_f128:
+        test_abz_f128( trueFunction_abz_f128M, subjFunction_abz_f128M );
+        break;
+     case F128_MULADD:
+        test_abcz_f128( slow_f128M_mulAdd, f128M_mulAdd );
+        break;
+     case F128_SQRT:
+        test_az_f128( slow_f128M_sqrt, f128M_sqrt );
+        break;
+     case F128_EQ:
+        trueFunction_ab_f128M_z_bool = slow_f128M_eq;
+        subjFunction_ab_f128M_z_bool = f128M_eq;
+        goto test_ab_f128_z_bool;
+     case F128_LE:
+        trueFunction_ab_f128M_z_bool = slow_f128M_le;
+        subjFunction_ab_f128M_z_bool = f128M_le;
+        goto test_ab_f128_z_bool;
+     case F128_LT:
+        trueFunction_ab_f128M_z_bool = slow_f128M_lt;
+        subjFunction_ab_f128M_z_bool = f128M_lt;
+        goto test_ab_f128_z_bool;
+     case F128_EQ_SIGNALING:
+        trueFunction_ab_f128M_z_bool = slow_f128M_eq_signaling;
+        subjFunction_ab_f128M_z_bool = f128M_eq_signaling;
+        goto test_ab_f128_z_bool;
+     case F128_LE_QUIET:
+        trueFunction_ab_f128M_z_bool = slow_f128M_le_quiet;
+        subjFunction_ab_f128M_z_bool = f128M_le_quiet;
+        goto test_ab_f128_z_bool;
+     case F128_LT_QUIET:
+        trueFunction_ab_f128M_z_bool = slow_f128M_lt_quiet;
+        subjFunction_ab_f128M_z_bool = f128M_lt_quiet;
+     test_ab_f128_z_bool:
+        test_ab_f128_z_bool(
+            trueFunction_ab_f128M_z_bool, subjFunction_ab_f128M_z_bool );
+        break;
+#endif
+    }
+    if ( (verCases_errorStop && verCases_anyErrors) || verCases_stop ) {
+        verCases_exitWithStatus();
+    }
+
+}
+
+enum { EXACT_FALSE = 1, EXACT_TRUE };
+
+static
+void
+ testFunction(
+     int functionCode,
+     uint_fast8_t roundingPrecisionIn,
+     int roundingCodeIn,
+     int tininessCodeIn,
+     int exactCodeIn
+ )
+{
+    int functionAttribs;
+    uint_fast8_t roundingPrecision;
+    int roundingCode;
+    uint_fast8_t roundingMode;
+    int exactCode;
+    bool exact;
+    int tininessCode;
+    uint_fast8_t tininessMode;
+
+    functionAttribs = functionInfos[functionCode].attribs;
+    verCases_functionNamePtr = functionInfos[functionCode].namePtr;
+    roundingPrecision = 32;
+    for (;;) {
+        if ( functionAttribs & FUNC_EFF_ROUNDINGPRECISION ) {
+            if ( roundingPrecisionIn ) roundingPrecision = roundingPrecisionIn;
+        } else {
+            roundingPrecision = 0;
+        }
+#ifdef EXTFLOAT80
+        verCases_roundingPrecision = roundingPrecision;
+        if ( roundingPrecision ) {
+            slow_extF80_roundingPrecision = roundingPrecision;
+            extF80_roundingPrecision = roundingPrecision;
+        }
+#endif
+        for (
+            roundingCode = 1; roundingCode < NUM_ROUNDINGMODES; ++roundingCode
+        ) {
+            if (
+                functionAttribs
+                    & (FUNC_ARG_ROUNDINGMODE | FUNC_EFF_ROUNDINGMODE)
+            ) {
+                if ( roundingCodeIn ) roundingCode = roundingCodeIn;
+            } else {
+                roundingCode = 0;
+            }
+            verCases_roundingCode = roundingCode;
+            if ( roundingCode ) {
+                roundingMode = roundingModes[roundingCode];
+                if ( functionAttribs & FUNC_EFF_ROUNDINGMODE ) {
+                    slowfloat_roundingMode = roundingMode;
+                    softfloat_roundingMode = roundingMode;
+                }
+            }
+            for (
+                exactCode = EXACT_FALSE; exactCode <= EXACT_TRUE; ++exactCode
+            ) {
+                if ( functionAttribs & FUNC_ARG_EXACT ) {
+                    if ( exactCodeIn ) exactCode = exactCodeIn;
+                } else {
+                    exactCode = 0;
+                }
+                exact = (exactCode == EXACT_TRUE);
+                verCases_usesExact = (exactCode != 0);
+                verCases_exact = exact;
+                for (
+                    tininessCode = 1;
+                    tininessCode < NUM_TININESSMODES;
+                    ++tininessCode
+                ) {
+                    if (
+                        (functionAttribs & FUNC_EFF_TININESSMODE)
+                            || ((functionAttribs
+                                     & FUNC_EFF_TININESSMODE_REDUCEDPREC)
+                                    && roundingPrecision
+                                    && (roundingPrecision < 80))
+                    ) {
+                        if ( tininessCodeIn ) tininessCode = tininessCodeIn;
+                    } else {
+                        tininessCode = 0;
+                    }
+                    verCases_tininessCode = tininessCode;
+                    if ( tininessCode ) {
+                        tininessMode = tininessModes[tininessCode];
+                        slowfloat_detectTininess = tininessMode;
+                        softfloat_detectTininess = tininessMode;
+                    }
+                    testFunctionInstance( functionCode, roundingMode, exact );
+                    if ( tininessCodeIn || ! tininessCode ) break;
+                }
+                if ( exactCodeIn || ! exactCode ) break;
+            }
+            if ( roundingCodeIn || ! roundingCode ) break;
+        }
+        if ( roundingPrecisionIn || ! roundingPrecision ) break;
+        if ( roundingPrecision == 80 ) {
+            break;
+        } else if ( roundingPrecision == 64 ) {
+            roundingPrecision = 80;
+        } else if ( roundingPrecision == 32 ) {
+            roundingPrecision = 64;
+        }
+    }
+
+}
+
+int main( int argc, char *argv[] )
+{
+    bool haveFunctionArg;
+    int functionCode, numOperands;
+    uint_fast8_t roundingPrecision;
+    int roundingCode, tininessCode, exactCode;
+    const char *argPtr;
+    unsigned long ui;
+    long i;
+    int functionMatchAttrib;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    fail_programName = "testsoftfloat";
+    if ( argc <= 1 ) goto writeHelpMessage;
+    genCases_setLevel( 1 );
+    verCases_maxErrorCount = 20;
+    testLoops_trueFlagsPtr = &slowfloat_exceptionFlags;
+    testLoops_subjFlagsFunction = softfloat_clearExceptionFlags;
+    haveFunctionArg = false;
+    functionCode = 0;
+    numOperands = 0;
+    roundingPrecision = 0;
+    roundingCode = 0;
+    tininessCode = 0;
+    exactCode = 0;
+    for (;;) {
+        --argc;
+        if ( ! argc ) break;
+        argPtr = *++argv;
+        if ( ! argPtr ) break;
+        if ( argPtr[0] == '-' ) ++argPtr;
+        if (
+            ! strcmp( argPtr, "help" ) || ! strcmp( argPtr, "-help" )
+                || ! strcmp( argPtr, "h" )
+        ) {
+ writeHelpMessage:
+            fputs(
+"testsoftfloat [<option>...] <function>\n"
+"  <option>:  (* is default)\n"
+"    -help            --Write this message and exit.\n"
+"    -seed <num>      --Set pseudo-random number generator seed to <num>.\n"
+" *  -seed 1\n"
+"    -level <num>     --Testing level <num> (1 or 2).\n"
+" *  -level 1\n"
+"    -errors <num>    --Stop each function test after <num> errors.\n"
+" *  -errors 20\n"
+"    -errorstop       --Exit after first function with any error.\n"
+"    -forever         --Test one function repeatedly (implies '-level 2').\n"
+#ifdef EXTFLOAT80
+"    -precision32     --For extF80, test only 32-bit rounding precision.\n"
+"    -precision64     --For extF80, test only 64-bit rounding precision.\n"
+"    -precision80     --For extF80, test only 80-bit rounding precision.\n"
+#endif
+"    -rnear_even      --Test only rounding to nearest/even.\n"
+"    -rminMag         --Test only rounding to minimum magnitude (toward zero).\n"
+"    -rmin            --Test only rounding to minimum (down).\n"
+"    -rmax            --Test only rounding to maximum (up).\n"
+"    -rnear_maxMag    --Test only rounding to nearest/maximum magnitude\n"
+"                         (nearest/away).\n"
+#ifdef FLOAT_ROUND_ODD
+"    -rodd            --Test only rounding to odd (jamming).  (For rounding to\n"
+"                         an integer value, 'minMag' rounding is done instead.)\n"
+#endif
+"    -tininessbefore  --Test only underflow tininess detected before rounding.\n"
+"    -tininessafter   --Test only underflow tininess detected after rounding.\n"
+"    -notexact        --Test only non-exact rounding to integer (no inexact\n"
+"                         exceptions).\n"
+"    -exact           --Test only exact rounding to integer (raising inexact\n"
+"                         exceptions).\n"
+"  <function>:\n"
+"    <int>_to_<float>            <float>_add      <float>_eq\n"
+"    <float>_to_<int>            <float>_sub      <float>_le\n"
+"    <float>_to_<int>_r_minMag   <float>_mul      <float>_lt\n"
+"    <float>_to_<float>          <float>_mulAdd   <float>_eq_signaling\n"
+"    <float>_roundToInt          <float>_div      <float>_le_quiet\n"
+"                                <float>_rem      <float>_lt_quiet\n"
+"                                <float>_sqrt\n"
+"    -all1            --All unary functions.\n"
+"    -all2            --All binary functions.\n"
+"  <int>:\n"
+"    ui32             --Unsigned 32-bit integer.\n"
+"    ui64             --Unsigned 64-bit integer.\n"
+"    i32              --Signed 32-bit integer.\n"
+"    i64              --Signed 64-bit integer.\n"
+"  <float>:\n"
+#ifdef FLOAT16
+"    f16              --Binary 16-bit floating-point (half-precision).\n"
+#endif
+"    f32              --Binary 32-bit floating-point (single-precision).\n"
+#ifdef FLOAT64
+"    f64              --Binary 64-bit floating-point (double-precision).\n"
+#endif
+#ifdef EXTFLOAT80
+"    extF80           --Binary 80-bit extended floating-point.\n"
+#endif
+#ifdef FLOAT128
+"    f128             --Binary 128-bit floating-point (quadruple-precision).\n"
+#endif
+                ,
+                stdout
+            );
+            return EXIT_SUCCESS;
+        } else if ( ! strcmp( argPtr, "seed" ) ) {
+            if ( argc < 2 ) goto optionError;
+            ui = strtoul( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            srand( ui );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            genCases_setLevel( i );
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "level1" ) ) {
+            genCases_setLevel( 1 );
+        } else if ( ! strcmp( argPtr, "level2" ) ) {
+            genCases_setLevel( 2 );
+        } else if ( ! strcmp( argPtr, "errors" ) ) {
+            if ( argc < 2 ) goto optionError;
+            i = strtol( argv[1], (char **) &argPtr, 10 );
+            if ( *argPtr ) goto optionError;
+            verCases_maxErrorCount = i;
+            --argc;
+            ++argv;
+        } else if ( ! strcmp( argPtr, "errorstop" ) ) {
+            verCases_errorStop = true;
+        } else if ( ! strcmp( argPtr, "forever" ) ) {
+            genCases_setLevel( 2 );
+            testLoops_forever = true;
+#ifdef EXTFLOAT80
+        } else if ( ! strcmp( argPtr, "precision32" ) ) {
+            roundingPrecision = 32;
+        } else if ( ! strcmp( argPtr, "precision64" ) ) {
+            roundingPrecision = 64;
+        } else if ( ! strcmp( argPtr, "precision80" ) ) {
+            roundingPrecision = 80;
+#endif
+        } else if (
+               ! strcmp( argPtr, "rnear_even" )
+            || ! strcmp( argPtr, "rneareven" )
+            || ! strcmp( argPtr, "rnearest_even" )
+        ) {
+            roundingCode = ROUND_NEAR_EVEN;
+        } else if (
+            ! strcmp( argPtr, "rminmag" ) || ! strcmp( argPtr, "rminMag" )
+        ) {
+            roundingCode = ROUND_MINMAG;
+        } else if ( ! strcmp( argPtr, "rmin" ) ) {
+            roundingCode = ROUND_MIN;
+        } else if ( ! strcmp( argPtr, "rmax" ) ) {
+            roundingCode = ROUND_MAX;
+        } else if (
+               ! strcmp( argPtr, "rnear_maxmag" )
+            || ! strcmp( argPtr, "rnear_maxMag" )
+            || ! strcmp( argPtr, "rnearmaxmag" )
+            || ! strcmp( argPtr, "rnearest_maxmag" )
+            || ! strcmp( argPtr, "rnearest_maxMag" )
+        ) {
+            roundingCode = ROUND_NEAR_MAXMAG;
+#ifdef FLOAT_ROUND_ODD
+        } else if ( ! strcmp( argPtr, "rodd" ) ) {
+            roundingCode = ROUND_ODD;
+#endif
+        } else if ( ! strcmp( argPtr, "tininessbefore" ) ) {
+            tininessCode = TININESS_BEFORE_ROUNDING;
+        } else if ( ! strcmp( argPtr, "tininessafter" ) ) {
+            tininessCode = TININESS_AFTER_ROUNDING;
+        } else if ( ! strcmp( argPtr, "notexact" ) ) {
+            exactCode = EXACT_FALSE;
+        } else if ( ! strcmp( argPtr, "exact" ) ) {
+            exactCode = EXACT_TRUE;
+        } else if ( ! strcmp( argPtr, "all1" ) ) {
+            haveFunctionArg = true;
+            functionCode = 0;
+            numOperands = 1;
+        } else if ( ! strcmp( argPtr, "all2" ) ) {
+            haveFunctionArg = true;
+            functionCode = 0;
+            numOperands = 2;
+        } else {
+            functionCode = 1;
+            while ( strcmp( argPtr, functionInfos[functionCode].namePtr ) ) {
+                ++functionCode;
+                if ( functionCode == NUM_FUNCTIONS ) {
+                    fail( "Invalid argument '%s'", *argv );
+                }
+            }
+            haveFunctionArg = true;
+        }
+    }
+    if ( ! haveFunctionArg ) fail( "Function argument required" );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    signal( SIGINT, catchSIGINT );
+    signal( SIGTERM, catchSIGINT );
+    if ( functionCode ) {
+        if ( testLoops_forever ) {
+            if ( ! roundingPrecision ) roundingPrecision = 80;
+            if ( ! roundingCode ) roundingCode = ROUND_NEAR_EVEN;
+        }
+        testFunction(
+            functionCode,
+            roundingPrecision,
+            roundingCode,
+            tininessCode,
+            exactCode
+        );
+    } else {
+        if ( testLoops_forever ) {
+             fail( "Can test only one function with '-forever' option" );
+        }
+        functionMatchAttrib =
+            (numOperands == 1) ? FUNC_ARG_UNARY : FUNC_ARG_BINARY;
+        for (
+            functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode
+        ) {
+            if ( functionInfos[functionCode].attribs & functionMatchAttrib ) {
+                testFunction(
+                    functionCode,
+                    roundingPrecision,
+                    roundingCode,
+                    tininessCode,
+                    exactCode
+                );
+            }
+        }
+    }
+    verCases_exitWithStatus();
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+ optionError:
+    fail( "'%s' option requires numeric argument", *argv );
+
+}
+
diff --git a/addins/TestFloat-3e/source/timesoftfloat.c b/addins/TestFloat-3e/source/timesoftfloat.c
new file mode 100644
index 000000000..0bb2bd51d
--- /dev/null
+++ b/addins/TestFloat-3e/source/timesoftfloat.c
@@ -0,0 +1,5060 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <time.h>
+#include "platform.h"
+#include "uint128.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "functions.h"
+
+enum { minIterations = 1000 };
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+static const char *functionNamePtr;
+static uint_fast8_t roundingPrecision;
+static int roundingCode;
+static int tininessCode;
+static bool usesExact;
+static bool exact;
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+static void reportTime( int_fast64_t count, clock_t clockTicks )
+{
+    static const char *roundingModeNames[NUM_ROUNDINGMODES] = {
+        0,
+        ", rounding near_even",
+        ", rounding minMag",
+        ", rounding min",
+        ", rounding max",
+        ", rounding near_maxMag",
+#ifdef FLOAT_ROUND_ODD
+        ", rounding odd"
+#endif
+    };
+
+    printf(
+        "%9.4f Mop/s: %s",
+        count / ((float) clockTicks / CLOCKS_PER_SEC) / 1000000,
+        functionNamePtr
+    );
+    if ( roundingCode ) {
+#ifdef EXTFLOAT80
+        if ( roundingPrecision ) {
+            printf( ", precision %d", (int) roundingPrecision );
+        }
+#endif
+        fputs( roundingModeNames[roundingCode], stdout );
+        if ( tininessCode ) {
+            fputs(
+                (tininessCode == TININESS_BEFORE_ROUNDING)
+                    ? ", tininess before rounding"
+                    : ", tininess after rounding",
+                stdout
+            );
+        }
+    }
+    if ( usesExact ) fputs( exact ? ", exact" : ", not exact", stdout );
+    fputc( '\n', stdout );
+    fflush( stdout );
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+union ui16_f16 { uint16_t ui; float16_t f; };
+#endif
+union ui32_f32 { uint32_t ui; float32_t f; };
+#ifdef FLOAT64
+union ui64_f64 { uint64_t ui; float64_t f; };
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+enum { numInputs_ui32 = 32 };
+
+static const uint32_t inputs_ui32[numInputs_ui32] = {
+    0x00004487, 0x405CF80F, 0x00000000, 0x000002FC,
+    0x000DFFFE, 0x0C8EF795, 0x0FFFEE01, 0x000006CA,
+    0x00009BFE, 0x00B79D1D, 0x60001002, 0x00000049,
+    0x0BFF7FFF, 0x0000F37A, 0x0011DFFE, 0x00000006,
+    0x000FDFFA, 0x0000082F, 0x10200003, 0x2172089B,
+    0x00003E02, 0x000019E8, 0x0008FFFE, 0x000004A4,
+    0x00208002, 0x07C42FBF, 0x0FFFE3FF, 0x040B9F13,
+    0x40000008, 0x0001BF56, 0x000017F6, 0x000A908A
+};
+
+#ifdef FLOAT16
+
+static void time_a_ui32_z_f16( float16_t function( uint32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_ui32_z_f32( float32_t function( uint32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_ui32_z_f64( float64_t function( uint32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_ui32_z_extF80( void function( uint32_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui32[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui32[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_ui32_z_f128( void function( uint32_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui32[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui32[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_ui32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+enum { numInputs_ui64 = 32 };
+
+static const int64_t inputs_ui64[numInputs_ui64] = {
+    UINT64_C( 0x04003C0000000001 ), UINT64_C( 0x0000000003C589BC ),
+    UINT64_C( 0x00000000400013FE ), UINT64_C( 0x0000000000186171 ),
+    UINT64_C( 0x0000000000010406 ), UINT64_C( 0x000002861920038D ),
+    UINT64_C( 0x0000000010001DFF ), UINT64_C( 0x22E5F0F387AEC8F0 ),
+    UINT64_C( 0x00007C0000010002 ), UINT64_C( 0x00756EBD1AD0C1C7 ),
+    UINT64_C( 0x0003FDFFFFFFFFBE ), UINT64_C( 0x0007D0FB2C2CA951 ),
+    UINT64_C( 0x0007FC0007FFFFFE ), UINT64_C( 0x0000001F942B18BB ),
+    UINT64_C( 0x0000080101FFFFFE ), UINT64_C( 0x000000000000F688 ),
+    UINT64_C( 0x000000000008BFFF ), UINT64_C( 0x0000000006F5AF08 ),
+    UINT64_C( 0x0021008000000002 ), UINT64_C( 0x0000000000000003 ),
+    UINT64_C( 0x3FFFFFFFFF80007D ), UINT64_C( 0x0000000000000078 ),
+    UINT64_C( 0x0007FFFFFF802003 ), UINT64_C( 0x1BBC775B78016AB0 ),
+    UINT64_C( 0x0006FFE000000002 ), UINT64_C( 0x0002B89854671BC1 ),
+    UINT64_C( 0x0000010001FFFFE2 ), UINT64_C( 0x00000000000FB103 ),
+    UINT64_C( 0x07FFFFFFFFFFF7FF ), UINT64_C( 0x00036155C7076FB0 ),
+    UINT64_C( 0x00000020FBFFFFFE ), UINT64_C( 0x0000099AE6455357 )
+};
+
+#ifdef FLOAT16
+
+static void time_a_ui64_z_f16( float16_t function( uint64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_ui64_z_f32( float32_t function( uint64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_ui64_z_f64( float64_t function( uint64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_ui64_z_extF80( void function( uint64_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui64[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui64[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_ui64_z_f128( void function( uint64_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_ui64[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_ui64[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_ui64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+enum { numInputs_i32 = 32 };
+
+static const int32_t inputs_i32[numInputs_i32] = {
+    -0x00004487,  0x405CF80F,  0x00000000, -0x000002FC,
+    -0x000DFFFE,  0x0C8EF795, -0x0FFFEE01,  0x000006CA,
+     0x00009BFE, -0x00B79D1D, -0x60001002, -0x00000049,
+     0x0BFF7FFF,  0x0000F37A,  0x0011DFFE,  0x00000006,
+    -0x000FDFFA, -0x0000082F,  0x10200003, -0x2172089B,
+     0x00003E02,  0x000019E8,  0x0008FFFE, -0x000004A4,
+    -0x00208002,  0x07C42FBF,  0x0FFFE3FF,  0x040B9F13,
+    -0x40000008,  0x0001BF56,  0x000017F6,  0x000A908A
+};
+
+#ifdef FLOAT16
+
+static void time_a_i32_z_f16( float16_t function( int32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_i32_z_f32( float32_t function( int32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_i32_z_f64( float64_t function( int32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i32[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i32[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_i32_z_extF80( void function( int32_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i32[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i32[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_i32_z_f128( void function( int32_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i32[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i32[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_i32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+enum { numInputs_i64 = 32 };
+
+static const int64_t inputs_i64[numInputs_i64] = {
+    -INT64_C( 0x04003C0000000001 ),  INT64_C( 0x0000000003C589BC ),
+     INT64_C( 0x00000000400013FE ),  INT64_C( 0x0000000000186171 ),
+    -INT64_C( 0x0000000000010406 ), -INT64_C( 0x000002861920038D ),
+     INT64_C( 0x0000000010001DFF ), -INT64_C( 0x22E5F0F387AEC8F0 ),
+    -INT64_C( 0x00007C0000010002 ),  INT64_C( 0x00756EBD1AD0C1C7 ),
+     INT64_C( 0x0003FDFFFFFFFFBE ),  INT64_C( 0x0007D0FB2C2CA951 ),
+     INT64_C( 0x0007FC0007FFFFFE ),  INT64_C( 0x0000001F942B18BB ),
+     INT64_C( 0x0000080101FFFFFE ), -INT64_C( 0x000000000000F688 ),
+     INT64_C( 0x000000000008BFFF ),  INT64_C( 0x0000000006F5AF08 ),
+    -INT64_C( 0x0021008000000002 ),  INT64_C( 0x0000000000000003 ),
+     INT64_C( 0x3FFFFFFFFF80007D ),  INT64_C( 0x0000000000000078 ),
+    -INT64_C( 0x0007FFFFFF802003 ),  INT64_C( 0x1BBC775B78016AB0 ),
+    -INT64_C( 0x0006FFE000000002 ), -INT64_C( 0x0002B89854671BC1 ),
+    -INT64_C( 0x0000010001FFFFE2 ), -INT64_C( 0x00000000000FB103 ),
+     INT64_C( 0x07FFFFFFFFFFF7FF ), -INT64_C( 0x00036155C7076FB0 ),
+     INT64_C( 0x00000020FBFFFFFE ),  INT64_C( 0x0000099AE6455357 )
+};
+
+#ifdef FLOAT16
+
+static void time_a_i64_z_f16( float16_t function( int64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_i64_z_f32( float32_t function( int64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_i64_z_f64( float64_t function( int64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i64[inputNum] );
+            inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i64[inputNum] );
+        inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_i64_z_extF80( void function( int64_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i64[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i64[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_i64_z_f128( void function( int64_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( inputs_i64[inputNum], &z );
+            inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( inputs_i64[inputNum], &z );
+        inputNum = (inputNum + 1) & (numInputs_i64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+enum { numInputs_f16 = 32 };
+
+static const uint16_t inputs_F16UI[numInputs_f16] = {
+    0x0BBA, 0x77FE, 0x084F, 0x9C0F, 0x7800, 0x4436, 0xCE67, 0x80F3,
+    0x87EF, 0xC2FA, 0x7BFF, 0x13FE, 0x7BFE, 0x1C00, 0xAC46, 0xEAFA,
+    0x3813, 0x4804, 0x385E, 0x8000, 0xB86C, 0x4B7D, 0xC7FD, 0xC97F,
+    0x260C, 0x78EE, 0xB84F, 0x249E, 0x0D27, 0x37DC, 0x8400, 0xE8EF
+};
+
+static
+void
+ time_a_f16_z_ui32_rx(
+     uint_fast32_t function( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f16_z_ui64_rx(
+     uint_fast64_t function( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f16_z_i32_rx(
+     int_fast32_t function( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f16_z_i64_rx(
+     int_fast64_t function( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f16_z_ui32_x( uint_fast32_t function( float16_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f16_z_ui64_x( uint_fast64_t function( float16_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f16_z_i32_x( int_fast32_t function( float16_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f16_z_i64_x( int_fast64_t function( float16_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_a_f16_z_f32( float32_t function( float16_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_f16_z_f64( float64_t function( float16_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_f16_z_extF80( void function( float16_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_f16_z_f128( void function( float16_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static
+void
+ time_az_f16_rx(
+     float16_t function( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_abz_f16( float16_t function( float16_t, float16_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNumA];
+            uB.ui = inputs_F16UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNumA];
+        uB.ui = inputs_F16UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_abcz_f16( float16_t function( float16_t, float16_t, float16_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB, inputNumC;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA, uB, uC;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNumA];
+            uB.ui = inputs_F16UI[inputNumB];
+            uC.ui = inputs_F16UI[inputNumC];
+            function( uA.f, uB.f, uC.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+            if ( ! inputNumB ) ++inputNumC;
+            inputNumC = (inputNumC + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNumA];
+        uB.ui = inputs_F16UI[inputNumB];
+        uC.ui = inputs_F16UI[inputNumC];
+        function( uA.f, uB.f, uC.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+        if ( ! inputNumB ) ++inputNumC;
+        inputNumC = (inputNumC + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_ab_f16_z_bool( bool function( float16_t, float16_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI[inputNumA];
+            uB.ui = inputs_F16UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI[inputNumA];
+        uB.ui = inputs_F16UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f16 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static const uint16_t inputs_F16UI_pos[numInputs_f16] = {
+    0x0BBA, 0x77FE, 0x084F, 0x1C0F, 0x7800, 0x4436, 0x4E67, 0x00F3,
+    0x07EF, 0x42FA, 0x7BFF, 0x13FE, 0x7BFE, 0x1C00, 0x2C46, 0x6AFA,
+    0x3813, 0x4804, 0x385E, 0x0000, 0x386C, 0x4B7D, 0x47FD, 0x497F,
+    0x260C, 0x78EE, 0x384F, 0x249E, 0x0D27, 0x37DC, 0x0400, 0x68EF
+};
+
+static void time_az_f16_pos( float16_t function( float16_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui16_f16 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F16UI_pos[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F16UI_pos[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f16 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+enum { numInputs_f32 = 32 };
+
+static const uint32_t inputs_F32UI[numInputs_f32] = {
+    0x4EFA0000, 0xC1D0B328, 0x80000000, 0x3E69A31E,
+    0xAF803EFF, 0x3F800000, 0x17BF8000, 0xE74A301A,
+    0x4E010003, 0x7EE3C75D, 0xBD803FE0, 0xBFFEFF00,
+    0x7981F800, 0x431FFFFC, 0xC100C000, 0x3D87EFFF,
+    0x4103FEFE, 0xBC000007, 0xBF01F7FF, 0x4E6C6B5C,
+    0xC187FFFE, 0xC58B9F13, 0x4F88007F, 0xDF004007,
+    0xB7FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,
+    0xDB428661, 0x33F89B1F, 0xA3BFEFFF, 0x537BFFBE
+};
+
+static
+void
+ time_a_f32_z_ui32_rx(
+     uint_fast32_t function( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f32_z_ui64_rx(
+     uint_fast64_t function( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f32_z_i32_rx(
+     int_fast32_t function( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f32_z_i64_rx(
+     int_fast64_t function( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f32_z_ui32_x( uint_fast32_t function( float32_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f32_z_ui64_x( uint_fast64_t function( float32_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f32_z_i32_x( int_fast32_t function( float32_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f32_z_i64_x( int_fast64_t function( float32_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT16
+
+static void time_a_f32_z_f16( float16_t function( float32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT64
+
+static void time_a_f32_z_f64( float64_t function( float32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void time_a_f32_z_extF80( void function( float32_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_f32_z_f128( void function( float32_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static
+void
+ time_az_f32_rx(
+     float32_t function( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_abz_f32( float32_t function( float32_t, float32_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNumA];
+            uB.ui = inputs_F32UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNumA];
+        uB.ui = inputs_F32UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_abcz_f32( float32_t function( float32_t, float32_t, float32_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB, inputNumC;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA, uB, uC;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNumA];
+            uB.ui = inputs_F32UI[inputNumB];
+            uC.ui = inputs_F32UI[inputNumC];
+            function( uA.f, uB.f, uC.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+            if ( ! inputNumB ) ++inputNumC;
+            inputNumC = (inputNumC + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNumA];
+        uB.ui = inputs_F32UI[inputNumB];
+        uC.ui = inputs_F32UI[inputNumC];
+        function( uA.f, uB.f, uC.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+        if ( ! inputNumB ) ++inputNumC;
+        inputNumC = (inputNumC + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_ab_f32_z_bool( bool function( float32_t, float32_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI[inputNumA];
+            uB.ui = inputs_F32UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI[inputNumA];
+        uB.ui = inputs_F32UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f32 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static const uint32_t inputs_F32UI_pos[numInputs_f32] = {
+    0x4EFA0000, 0x41D0B328, 0x00000000, 0x3E69A31E,
+    0x2F803EFF, 0x3F800000, 0x17BF8000, 0x674A301A,
+    0x4E010003, 0x7EE3C75D, 0x3D803FE0, 0x3FFEFF00,
+    0x7981F800, 0x431FFFFC, 0x4100C000, 0x3D87EFFF,
+    0x4103FEFE, 0x3C000007, 0x3F01F7FF, 0x4E6C6B5C,
+    0x4187FFFE, 0x458B9F13, 0x4F88007F, 0x5F004007,
+    0x37FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,
+    0x5B428661, 0x33F89B1F, 0x23BFEFFF, 0x537BFFBE
+};
+
+static void time_az_f32_pos( float32_t function( float32_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui32_f32 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F32UI_pos[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F32UI_pos[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f32 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT64
+
+enum { numInputs_f64 = 32 };
+
+static const uint64_t inputs_F64UI[numInputs_f64] = {
+    UINT64_C( 0x422FFFC008000000 ),
+    UINT64_C( 0xB7E0000480000000 ),
+    UINT64_C( 0xF3FD2546120B7935 ),
+    UINT64_C( 0x3FF0000000000000 ),
+    UINT64_C( 0xCE07F766F09588D6 ),
+    UINT64_C( 0x8000000000000000 ),
+    UINT64_C( 0x3FCE000400000000 ),
+    UINT64_C( 0x8313B60F0032BED8 ),
+    UINT64_C( 0xC1EFFFFFC0002000 ),
+    UINT64_C( 0x3FB3C75D224F2B0F ),
+    UINT64_C( 0x7FD00000004000FF ),
+    UINT64_C( 0xA12FFF8000001FFF ),
+    UINT64_C( 0x3EE0000000FE0000 ),
+    UINT64_C( 0x0010000080000004 ),
+    UINT64_C( 0x41CFFFFE00000020 ),
+    UINT64_C( 0x40303FFFFFFFFFFD ),
+    UINT64_C( 0x3FD000003FEFFFFF ),
+    UINT64_C( 0xBFD0000010000000 ),
+    UINT64_C( 0xB7FC6B5C16CA55CF ),
+    UINT64_C( 0x413EEB940B9D1301 ),
+    UINT64_C( 0xC7E00200001FFFFF ),
+    UINT64_C( 0x47F00021FFFFFFFE ),
+    UINT64_C( 0xBFFFFFFFF80000FF ),
+    UINT64_C( 0xC07FFFFFE00FFFFF ),
+    UINT64_C( 0x001497A63740C5E8 ),
+    UINT64_C( 0xC4BFFFE0001FFFFF ),
+    UINT64_C( 0x96FFDFFEFFFFFFFF ),
+    UINT64_C( 0x403FC000000001FE ),
+    UINT64_C( 0xFFD00000000001F6 ),
+    UINT64_C( 0x0640400002000000 ),
+    UINT64_C( 0x479CEE1E4F789FE0 ),
+    UINT64_C( 0xC237FFFFFFFFFDFE )
+};
+
+static
+void
+ time_a_f64_z_ui32_rx(
+     uint_fast32_t function( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f64_z_ui64_rx(
+     uint_fast64_t function( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f64_z_i32_rx(
+     int_fast32_t function( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f64_z_i64_rx(
+     int_fast64_t function( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f64_z_ui32_x( uint_fast32_t function( float64_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f64_z_ui64_x( uint_fast64_t function( float64_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f64_z_i32_x( int_fast32_t function( float64_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_a_f64_z_i64_x( int_fast64_t function( float64_t, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT16
+
+static void time_a_f64_z_f16( float16_t function( float64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_f64_z_f32( float32_t function( float64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef EXTFLOAT80
+
+static void time_a_f64_z_extF80( void function( float64_t, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void time_a_f64_z_f128( void function( float64_t, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static
+void
+ time_az_f64_rx(
+     float64_t function( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNum];
+            function( uA.f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNum];
+        function( uA.f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_abz_f64( float64_t function( float64_t, float64_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNumA];
+            uB.ui = inputs_F64UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNumA];
+        uB.ui = inputs_F64UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void time_abcz_f64( float64_t function( float64_t, float64_t, float64_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB, inputNumC;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA, uB, uC;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNumA];
+            uB.ui = inputs_F64UI[inputNumB];
+            uC.ui = inputs_F64UI[inputNumC];
+            function( uA.f, uB.f, uC.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+            if ( ! inputNumB ) ++inputNumC;
+            inputNumC = (inputNumC + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNumA];
+        uB.ui = inputs_F64UI[inputNumB];
+        uC.ui = inputs_F64UI[inputNumC];
+        function( uA.f, uB.f, uC.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+        if ( ! inputNumB ) ++inputNumC;
+        inputNumC = (inputNumC + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static void time_ab_f64_z_bool( bool function( float64_t, float64_t ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA, uB;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI[inputNumA];
+            uB.ui = inputs_F64UI[inputNumB];
+            function( uA.f, uB.f );
+            inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI[inputNumA];
+        uB.ui = inputs_F64UI[inputNumB];
+        function( uA.f, uB.f );
+        inputNumA = (inputNumA + 1) & (numInputs_f64 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static const uint64_t inputs_F64UI_pos[numInputs_f64] = {
+    UINT64_C( 0x422FFFC008000000 ),
+    UINT64_C( 0x37E0000480000000 ),
+    UINT64_C( 0x73FD2546120B7935 ),
+    UINT64_C( 0x3FF0000000000000 ),
+    UINT64_C( 0x4E07F766F09588D6 ),
+    UINT64_C( 0x0000000000000000 ),
+    UINT64_C( 0x3FCE000400000000 ),
+    UINT64_C( 0x0313B60F0032BED8 ),
+    UINT64_C( 0x41EFFFFFC0002000 ),
+    UINT64_C( 0x3FB3C75D224F2B0F ),
+    UINT64_C( 0x7FD00000004000FF ),
+    UINT64_C( 0x212FFF8000001FFF ),
+    UINT64_C( 0x3EE0000000FE0000 ),
+    UINT64_C( 0x0010000080000004 ),
+    UINT64_C( 0x41CFFFFE00000020 ),
+    UINT64_C( 0x40303FFFFFFFFFFD ),
+    UINT64_C( 0x3FD000003FEFFFFF ),
+    UINT64_C( 0x3FD0000010000000 ),
+    UINT64_C( 0x37FC6B5C16CA55CF ),
+    UINT64_C( 0x413EEB940B9D1301 ),
+    UINT64_C( 0x47E00200001FFFFF ),
+    UINT64_C( 0x47F00021FFFFFFFE ),
+    UINT64_C( 0x3FFFFFFFF80000FF ),
+    UINT64_C( 0x407FFFFFE00FFFFF ),
+    UINT64_C( 0x001497A63740C5E8 ),
+    UINT64_C( 0x44BFFFE0001FFFFF ),
+    UINT64_C( 0x16FFDFFEFFFFFFFF ),
+    UINT64_C( 0x403FC000000001FE ),
+    UINT64_C( 0x7FD00000000001F6 ),
+    UINT64_C( 0x0640400002000000 ),
+    UINT64_C( 0x479CEE1E4F789FE0 ),
+    UINT64_C( 0x4237FFFFFFFFFDFE )
+};
+
+static void time_az_f64_pos( float64_t function( float64_t ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    union ui64_f64 uA;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            uA.ui = inputs_F64UI_pos[inputNum];
+            function( uA.f );
+            inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        uA.ui = inputs_F64UI_pos[inputNum];
+        function( uA.f );
+        inputNum = (inputNum + 1) & (numInputs_f64 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef EXTFLOAT80
+
+#ifdef LITTLEENDIAN
+#define extF80Const( v64, v0 ) { UINT64_C( v0 ), v64 }
+#else
+#define extF80Const( v64, v0 ) { v64, UINT64_C( v0 ) }
+#endif
+
+enum { numInputs_extF80 = 32 };
+
+static
+const union { struct extFloat80M s; extFloat80_t f; }
+    inputs_extF80[numInputs_extF80] = {
+        extF80Const( 0xC03F, 0xA9BE15A19C1E8B62 ),
+        extF80Const( 0x8000, 0x0000000000000000 ),
+        extF80Const( 0x75A8, 0xE59591E4788957A5 ),
+        extF80Const( 0xBFFF, 0xFFF0000000000040 ),
+        extF80Const( 0x0CD8, 0xFC000000000007FE ),
+        extF80Const( 0x43BA, 0x99A4000000000000 ),
+        extF80Const( 0x3FFF, 0x8000000000000000 ),
+        extF80Const( 0x4081, 0x94FBF1BCEB5545F0 ),
+        extF80Const( 0x403E, 0xFFF0000000002000 ),
+        extF80Const( 0x3FFE, 0xC860E3C75D224F28 ),
+        extF80Const( 0x407E, 0xFC00000FFFFFFFFE ),
+        extF80Const( 0x737A, 0x800000007FFDFFFE ),
+        extF80Const( 0x4044, 0xFFFFFF80000FFFFF ),
+        extF80Const( 0xBBFE, 0x8000040000001FFE ),
+        extF80Const( 0xC002, 0xFF80000000000020 ),
+        extF80Const( 0xDE8D, 0xFFFFFFFFFFE00004 ),
+        extF80Const( 0xC004, 0x8000000000003FFB ),
+        extF80Const( 0x407F, 0x800000000003FFFE ),
+        extF80Const( 0xC000, 0xA459EE6A5C16CA55 ),
+        extF80Const( 0x8003, 0xC42CBF7399AEEB94 ),
+        extF80Const( 0xBF7F, 0xF800000000000006 ),
+        extF80Const( 0xC07F, 0xBF56BE8871F28FEA ),
+        extF80Const( 0xC07E, 0xFFFF77FFFFFFFFFE ),
+        extF80Const( 0xADC9, 0x8000000FFFFFFFDE ),
+        extF80Const( 0xC001, 0xEFF7FFFFFFFFFFFF ),
+        extF80Const( 0x4001, 0xBE84F30125C497A6 ),
+        extF80Const( 0xC06B, 0xEFFFFFFFFFFFFFFF ),
+        extF80Const( 0x4080, 0xFFFFFFFFBFFFFFFF ),
+        extF80Const( 0x87E9, 0x81FFFFFFFFFFFBFF ),
+        extF80Const( 0xA63F, 0x801FFFFFFEFFFFFE ),
+        extF80Const( 0x403C, 0x801FFFFFFFF7FFFF ),
+        extF80Const( 0x4018, 0x8000000000080003 )
+    };
+
+static
+void
+ time_a_extF80_z_ui32_rx(
+     uint_fast32_t function( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_ui64_rx(
+     uint_fast64_t function( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_i32_rx(
+     int_fast32_t function( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_i64_rx(
+     int_fast64_t function( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_ui32_x(
+     uint_fast32_t function( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_ui64_x(
+     uint_fast64_t function( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_i32_x(
+     int_fast32_t function( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_extF80_z_i64_x(
+     int_fast64_t function( const extFloat80_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT16
+
+static void time_a_extF80_z_f16( float16_t function( const extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_extF80_z_f32( float32_t function( const extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_extF80_z_f64( float64_t function( const extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static
+void
+ time_a_extF80_z_f128( void function( const extFloat80_t *, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, &z );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, &z );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static
+void
+ time_az_extF80_rx(
+     void function( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, roundingMode, exact, &z );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, roundingMode, exact, &z );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_abz_extF80(
+     void
+      function( const extFloat80_t *, const extFloat80_t *, extFloat80_t * )
+ )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function(
+                &inputs_extF80[inputNumA].f, &inputs_extF80[inputNumB].f, &z );
+            inputNumA = (inputNumA + 1) & (numInputs_extF80 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function(
+            &inputs_extF80[inputNumA].f, &inputs_extF80[inputNumB].f, &z );
+        inputNumA = (inputNumA + 1) & (numInputs_extF80 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_ab_extF80_z_bool(
+     bool function( const extFloat80_t *, const extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function(
+                &inputs_extF80[inputNumA].f, &inputs_extF80[inputNumB].f );
+            inputNumA = (inputNumA + 1) & (numInputs_extF80 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNumA].f, &inputs_extF80[inputNumB].f );
+        inputNumA = (inputNumA + 1) & (numInputs_extF80 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+const union { struct extFloat80M s; extFloat80_t f; }
+    inputs_extF80_pos[numInputs_extF80] = {
+        extF80Const( 0x403F, 0xA9BE15A19C1E8B62 ),
+        extF80Const( 0x0000, 0x0000000000000000 ),
+        extF80Const( 0x75A8, 0xE59591E4788957A5 ),
+        extF80Const( 0x3FFF, 0xFFF0000000000040 ),
+        extF80Const( 0x0CD8, 0xFC000000000007FE ),
+        extF80Const( 0x43BA, 0x99A4000000000000 ),
+        extF80Const( 0x3FFF, 0x8000000000000000 ),
+        extF80Const( 0x4081, 0x94FBF1BCEB5545F0 ),
+        extF80Const( 0x403E, 0xFFF0000000002000 ),
+        extF80Const( 0x3FFE, 0xC860E3C75D224F28 ),
+        extF80Const( 0x407E, 0xFC00000FFFFFFFFE ),
+        extF80Const( 0x737A, 0x800000007FFDFFFE ),
+        extF80Const( 0x4044, 0xFFFFFF80000FFFFF ),
+        extF80Const( 0x3BFE, 0x8000040000001FFE ),
+        extF80Const( 0x4002, 0xFF80000000000020 ),
+        extF80Const( 0x5E8D, 0xFFFFFFFFFFE00004 ),
+        extF80Const( 0x4004, 0x8000000000003FFB ),
+        extF80Const( 0x407F, 0x800000000003FFFE ),
+        extF80Const( 0x4000, 0xA459EE6A5C16CA55 ),
+        extF80Const( 0x0003, 0xC42CBF7399AEEB94 ),
+        extF80Const( 0x3F7F, 0xF800000000000006 ),
+        extF80Const( 0x407F, 0xBF56BE8871F28FEA ),
+        extF80Const( 0x407E, 0xFFFF77FFFFFFFFFE ),
+        extF80Const( 0x2DC9, 0x8000000FFFFFFFDE ),
+        extF80Const( 0x4001, 0xEFF7FFFFFFFFFFFF ),
+        extF80Const( 0x4001, 0xBE84F30125C497A6 ),
+        extF80Const( 0x406B, 0xEFFFFFFFFFFFFFFF ),
+        extF80Const( 0x4080, 0xFFFFFFFFBFFFFFFF ),
+        extF80Const( 0x07E9, 0x81FFFFFFFFFFFBFF ),
+        extF80Const( 0x263F, 0x801FFFFFFEFFFFFE ),
+        extF80Const( 0x403C, 0x801FFFFFFFF7FFFF ),
+        extF80Const( 0x4018, 0x8000000000080003 )
+    };
+
+static
+void
+ time_az_extF80_pos( void function( const extFloat80_t *, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_extF80[inputNum].f, &z );
+            inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_extF80[inputNum].f, &z );
+        inputNum = (inputNum + 1) & (numInputs_extF80 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT128
+
+#ifdef LITTLEENDIAN
+#define f128Const( v64, v0 ) { UINT64_C( v0 ), UINT64_C( v64 ) }
+#else
+#define f128Const( v64, v0 ) { UINT64_C( v64 ), UINT64_C( v0 ) }
+#endif
+
+enum { numInputs_f128 = 32 };
+
+static
+const union { struct uint128 ui; float128_t f; }
+    inputs_f128[numInputs_f128] = {
+        f128Const( 0x3FDA200000100000, 0x0000000000000000 ),
+        f128Const( 0x3FFF000000000000, 0x0000000000000000 ),
+        f128Const( 0x85F14776190C8306, 0xD8715F4E3D54BB92 ),
+        f128Const( 0xF2B00000007FFFFF, 0xFFFFFFFFFFF7FFFF ),
+        f128Const( 0x8000000000000000, 0x0000000000000000 ),
+        f128Const( 0xBFFFFFFFFFE00000, 0x0000008000000000 ),
+        f128Const( 0x407F1719CE722F3E, 0xDA6B3FE5FF29425B ),
+        f128Const( 0x43FFFF8000000000, 0x0000000000400000 ),
+        f128Const( 0x401E000000000100, 0x0000000000002000 ),
+        f128Const( 0x3FFED71DACDA8E47, 0x4860E3C75D224F28 ),
+        f128Const( 0xBF7ECFC1E90647D1, 0x7A124FE55623EE44 ),
+        f128Const( 0x0DF7007FFFFFFFFF, 0xFFFFFFFFEFFFFFFF ),
+        f128Const( 0x3FE5FFEFFFFFFFFF, 0xFFFFFFFFFFFFEFFF ),
+        f128Const( 0x403FFFFFFFFFFFFF, 0xFFFFFFFFFFFFFBFE ),
+        f128Const( 0xBFFB2FBF7399AFEB, 0xA459EE6A5C16CA55 ),
+        f128Const( 0xBDB8FFFFFFFFFFFC, 0x0000000000000400 ),
+        f128Const( 0x3FC8FFDFFFFFFFFF, 0xFFFFFFFFF0000000 ),
+        f128Const( 0x3FFBFFFFFFDFFFFF, 0xFFF8000000000000 ),
+        f128Const( 0x407043C11737BE84, 0xDDD58212ADC937F4 ),
+        f128Const( 0x8001000000000000, 0x0000001000000001 ),
+        f128Const( 0xC036FFFFFFFFFFFF, 0xFE40000000000000 ),
+        f128Const( 0x4002FFFFFE000002, 0x0000000000000000 ),
+        f128Const( 0x4000C3FEDE897773, 0x326AC4FD8EFBE6DC ),
+        f128Const( 0xBFFF0000000FFFFF, 0xFFFFFE0000000000 ),
+        f128Const( 0x62C3E502146E426D, 0x43F3CAA0DC7DF1A0 ),
+        f128Const( 0xB5CBD32E52BB570E, 0xBCC477CB11C6236C ),
+        f128Const( 0xE228FFFFFFC00000, 0x0000000000000000 ),
+        f128Const( 0x3F80000000000000, 0x0000000080000008 ),
+        f128Const( 0xC1AFFFDFFFFFFFFF, 0xFFFC000000000000 ),
+        f128Const( 0xC96F000000000000, 0x00000001FFFBFFFF ),
+        f128Const( 0x3DE09BFE7923A338, 0xBCC8FBBD7CEC1F4F ),
+        f128Const( 0x401CFFFFFFFFFFFF, 0xFFFFFFFEFFFFFF80 )
+    };
+
+static
+void
+ time_a_f128_z_ui32_rx(
+     uint_fast32_t function( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_ui64_rx(
+     uint_fast64_t function( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_i32_rx(
+     int_fast32_t function( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_i64_rx(
+     int_fast64_t function( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, roundingMode, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, roundingMode, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_ui32_x(
+     uint_fast32_t function( const float128_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_ui64_x(
+     uint_fast64_t function( const float128_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_i32_x(
+     int_fast32_t function( const float128_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_a_f128_z_i64_x(
+     int_fast64_t function( const float128_t *, bool ), bool exact )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, exact );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, exact );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT16
+
+static void time_a_f128_z_f16( float16_t function( const float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static void time_a_f128_z_f32( float32_t function( const float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#ifdef FLOAT64
+
+static void time_a_f128_z_f64( float64_t function( const float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static
+void
+ time_a_f128_z_extF80( void function( const float128_t *, extFloat80_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    extFloat80_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+static
+void
+ time_az_f128_rx(
+     void function( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, roundingMode, exact, &z );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, roundingMode, exact, &z );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_abz_f128(
+     void function( const float128_t *, const float128_t *, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function(
+                &inputs_f128[inputNumA].f, &inputs_f128[inputNumB].f, &z );
+            inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNumA].f, &inputs_f128[inputNumB].f, &z );
+        inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_abcz_f128(
+     void
+      function(
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB, inputNumC;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function(
+                &inputs_f128[inputNumA].f,
+                &inputs_f128[inputNumB].f,
+                &inputs_f128[inputNumC].f,
+                &z
+            );
+            inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+            if ( ! inputNumB ) ++inputNumC;
+            inputNumC = (inputNumC + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    inputNumC = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function(
+            &inputs_f128[inputNumA].f,
+            &inputs_f128[inputNumB].f,
+            &inputs_f128[inputNumC].f,
+            &z
+        );
+        inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+        if ( ! inputNumB ) ++inputNumC;
+        inputNumC = (inputNumC + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+void
+ time_ab_f128_z_bool( bool function( const float128_t *, const float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNumA, inputNumB;
+    clock_t startClock;
+    int_fast64_t i;
+    clock_t endClock;
+
+    count = 0;
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNumA].f, &inputs_f128[inputNumB].f );
+            inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+            if ( ! inputNumA ) ++inputNumB;
+            inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNumA = 0;
+    inputNumB = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNumA].f, &inputs_f128[inputNumB].f );
+        inputNumA = (inputNumA + 1) & (numInputs_f128 - 1);
+        if ( ! inputNumA ) ++inputNumB;
+        inputNumB = (inputNumB + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+static
+const union { struct uint128 ui; float128_t f; }
+    inputs_f128_pos[numInputs_f128] = {
+        f128Const( 0x3FDA200000100000, 0x0000000000000000 ),
+        f128Const( 0x3FFF000000000000, 0x0000000000000000 ),
+        f128Const( 0x05F14776190C8306, 0xD8715F4E3D54BB92 ),
+        f128Const( 0x72B00000007FFFFF, 0xFFFFFFFFFFF7FFFF ),
+        f128Const( 0x0000000000000000, 0x0000000000000000 ),
+        f128Const( 0x3FFFFFFFFFE00000, 0x0000008000000000 ),
+        f128Const( 0x407F1719CE722F3E, 0xDA6B3FE5FF29425B ),
+        f128Const( 0x43FFFF8000000000, 0x0000000000400000 ),
+        f128Const( 0x401E000000000100, 0x0000000000002000 ),
+        f128Const( 0x3FFED71DACDA8E47, 0x4860E3C75D224F28 ),
+        f128Const( 0x3F7ECFC1E90647D1, 0x7A124FE55623EE44 ),
+        f128Const( 0x0DF7007FFFFFFFFF, 0xFFFFFFFFEFFFFFFF ),
+        f128Const( 0x3FE5FFEFFFFFFFFF, 0xFFFFFFFFFFFFEFFF ),
+        f128Const( 0x403FFFFFFFFFFFFF, 0xFFFFFFFFFFFFFBFE ),
+        f128Const( 0x3FFB2FBF7399AFEB, 0xA459EE6A5C16CA55 ),
+        f128Const( 0x3DB8FFFFFFFFFFFC, 0x0000000000000400 ),
+        f128Const( 0x3FC8FFDFFFFFFFFF, 0xFFFFFFFFF0000000 ),
+        f128Const( 0x3FFBFFFFFFDFFFFF, 0xFFF8000000000000 ),
+        f128Const( 0x407043C11737BE84, 0xDDD58212ADC937F4 ),
+        f128Const( 0x0001000000000000, 0x0000001000000001 ),
+        f128Const( 0x4036FFFFFFFFFFFF, 0xFE40000000000000 ),
+        f128Const( 0x4002FFFFFE000002, 0x0000000000000000 ),
+        f128Const( 0x4000C3FEDE897773, 0x326AC4FD8EFBE6DC ),
+        f128Const( 0x3FFF0000000FFFFF, 0xFFFFFE0000000000 ),
+        f128Const( 0x62C3E502146E426D, 0x43F3CAA0DC7DF1A0 ),
+        f128Const( 0x35CBD32E52BB570E, 0xBCC477CB11C6236C ),
+        f128Const( 0x6228FFFFFFC00000, 0x0000000000000000 ),
+        f128Const( 0x3F80000000000000, 0x0000000080000008 ),
+        f128Const( 0x41AFFFDFFFFFFFFF, 0xFFFC000000000000 ),
+        f128Const( 0x496F000000000000, 0x00000001FFFBFFFF ),
+        f128Const( 0x3DE09BFE7923A338, 0xBCC8FBBD7CEC1F4F ),
+        f128Const( 0x401CFFFFFFFFFFFF, 0xFFFFFFFEFFFFFF80 )
+    };
+
+static
+void time_az_f128_pos( void function( const float128_t *, float128_t * ) )
+{
+    int_fast64_t count;
+    int inputNum;
+    clock_t startClock;
+    int_fast64_t i;
+    float128_t z;
+    clock_t endClock;
+
+    count = 0;
+    inputNum = 0;
+    startClock = clock();
+    do {
+        for ( i = minIterations; i; --i ) {
+            function( &inputs_f128[inputNum].f, &z );
+            inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+        }
+        count += minIterations;
+    } while ( clock() - startClock < CLOCKS_PER_SEC );
+    inputNum = 0;
+    startClock = clock();
+    for ( i = count; i; --i ) {
+        function( &inputs_f128[inputNum].f, &z );
+        inputNum = (inputNum + 1) & (numInputs_f128 - 1);
+    }
+    endClock = clock();
+    reportTime( count, endClock - startClock );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+static
+void
+ timeFunctionInstance(
+     int functionCode, uint_fast8_t roundingMode, bool exact )
+{
+#ifdef FLOAT16
+    float16_t (*function_abz_f16)( float16_t, float16_t );
+    bool (*function_ab_f16_z_bool)( float16_t, float16_t );
+#endif
+    float32_t (*function_abz_f32)( float32_t, float32_t );
+    bool (*function_ab_f32_z_bool)( float32_t, float32_t );
+#ifdef FLOAT64
+    float64_t (*function_abz_f64)( float64_t, float64_t );
+    bool (*function_ab_f64_z_bool)( float64_t, float64_t );
+#endif
+#ifdef EXTFLOAT80
+    void
+     (*function_abz_extF80)(
+         const extFloat80_t *, const extFloat80_t *, extFloat80_t * );
+    bool
+     (*function_ab_extF80_z_bool)(
+         const extFloat80_t *, const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+    void
+     (*function_abz_f128)(
+         const float128_t *, const float128_t *, float128_t * );
+    bool (*function_ab_f128_z_bool)( const float128_t *, const float128_t * );
+#endif
+
+    switch ( functionCode ) {
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case UI32_TO_F16:
+        time_a_ui32_z_f16( ui32_to_f16 );
+        break;
+#endif
+     case UI32_TO_F32:
+        time_a_ui32_z_f32( ui32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI32_TO_F64:
+        time_a_ui32_z_f64( ui32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI32_TO_EXTF80:
+        time_a_ui32_z_extF80( ui32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI32_TO_F128:
+        time_a_ui32_z_f128( ui32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case UI64_TO_F16:
+        time_a_ui64_z_f16( ui64_to_f16 );
+        break;
+#endif
+     case UI64_TO_F32:
+        time_a_ui64_z_f32( ui64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case UI64_TO_F64:
+        time_a_ui64_z_f64( ui64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case UI64_TO_EXTF80:
+        time_a_ui64_z_extF80( ui64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case UI64_TO_F128:
+        time_a_ui64_z_f128( ui64_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I32_TO_F16:
+        time_a_i32_z_f16( i32_to_f16 );
+        break;
+#endif
+     case I32_TO_F32:
+        time_a_i32_z_f32( i32_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I32_TO_F64:
+        time_a_i32_z_f64( i32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I32_TO_EXTF80:
+        time_a_i32_z_extF80( i32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I32_TO_F128:
+        time_a_i32_z_f128( i32_to_f128M );
+        break;
+#endif
+#ifdef FLOAT16
+     case I64_TO_F16:
+        time_a_i64_z_f16( i64_to_f16 );
+        break;
+#endif
+     case I64_TO_F32:
+        time_a_i64_z_f32( i64_to_f32 );
+        break;
+#ifdef FLOAT64
+     case I64_TO_F64:
+        time_a_i64_z_f64( i64_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case I64_TO_EXTF80:
+        time_a_i64_z_extF80( i64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case I64_TO_F128:
+        time_a_i64_z_f128( i64_to_f128M );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT16
+     case F16_TO_UI32:
+        time_a_f16_z_ui32_rx( f16_to_ui32, roundingMode, exact );
+        break;
+     case F16_TO_UI64:
+        time_a_f16_z_ui64_rx( f16_to_ui64, roundingMode, exact );
+        break;
+     case F16_TO_I32:
+        time_a_f16_z_i32_rx( f16_to_i32, roundingMode, exact );
+        break;
+     case F16_TO_I64:
+        time_a_f16_z_i64_rx( f16_to_i64, roundingMode, exact );
+        break;
+     case F16_TO_UI32_R_MINMAG:
+        time_a_f16_z_ui32_x( f16_to_ui32_r_minMag, exact );
+        break;
+     case F16_TO_UI64_R_MINMAG:
+        time_a_f16_z_ui64_x( f16_to_ui64_r_minMag, exact );
+        break;
+     case F16_TO_I32_R_MINMAG:
+        time_a_f16_z_i32_x( f16_to_i32_r_minMag, exact );
+        break;
+     case F16_TO_I64_R_MINMAG:
+        time_a_f16_z_i64_x( f16_to_i64_r_minMag, exact );
+        break;
+     case F16_TO_F32:
+        time_a_f16_z_f32( f16_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F16_TO_F64:
+        time_a_f16_z_f64( f16_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F16_TO_EXTF80:
+        time_a_f16_z_extF80( f16_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F16_TO_F128:
+        time_a_f16_z_f128( f16_to_f128M );
+        break;
+#endif
+     case F16_ROUNDTOINT:
+        time_az_f16_rx( f16_roundToInt, roundingMode, exact );
+        break;
+     case F16_ADD:
+        function_abz_f16 = f16_add;
+        goto time_abz_f16;
+     case F16_SUB:
+        function_abz_f16 = f16_sub;
+        goto time_abz_f16;
+     case F16_MUL:
+        function_abz_f16 = f16_mul;
+        goto time_abz_f16;
+     case F16_DIV:
+        function_abz_f16 = f16_div;
+        goto time_abz_f16;
+     case F16_REM:
+        function_abz_f16 = f16_rem;
+     time_abz_f16:
+        time_abz_f16( function_abz_f16 );
+        break;
+     case F16_MULADD:
+        time_abcz_f16( f16_mulAdd );
+        break;
+     case F16_SQRT:
+        time_az_f16_pos( f16_sqrt );
+        break;
+     case F16_EQ:
+        function_ab_f16_z_bool = f16_eq;
+        goto time_ab_f16_z_bool;
+     case F16_LE:
+        function_ab_f16_z_bool = f16_le;
+        goto time_ab_f16_z_bool;
+     case F16_LT:
+        function_ab_f16_z_bool = f16_lt;
+        goto time_ab_f16_z_bool;
+     case F16_EQ_SIGNALING:
+        function_ab_f16_z_bool = f16_eq_signaling;
+        goto time_ab_f16_z_bool;
+     case F16_LE_QUIET:
+        function_ab_f16_z_bool = f16_le_quiet;
+        goto time_ab_f16_z_bool;
+     case F16_LT_QUIET:
+        function_ab_f16_z_bool = f16_lt_quiet;
+     time_ab_f16_z_bool:
+        time_ab_f16_z_bool( function_ab_f16_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+     case F32_TO_UI32:
+        time_a_f32_z_ui32_rx( f32_to_ui32, roundingMode, exact );
+        break;
+     case F32_TO_UI64:
+        time_a_f32_z_ui64_rx( f32_to_ui64, roundingMode, exact );
+        break;
+     case F32_TO_I32:
+        time_a_f32_z_i32_rx( f32_to_i32, roundingMode, exact );
+        break;
+     case F32_TO_I64:
+        time_a_f32_z_i64_rx( f32_to_i64, roundingMode, exact );
+        break;
+     case F32_TO_UI32_R_MINMAG:
+        time_a_f32_z_ui32_x( f32_to_ui32_r_minMag, exact );
+        break;
+     case F32_TO_UI64_R_MINMAG:
+        time_a_f32_z_ui64_x( f32_to_ui64_r_minMag, exact );
+        break;
+     case F32_TO_I32_R_MINMAG:
+        time_a_f32_z_i32_x( f32_to_i32_r_minMag, exact );
+        break;
+     case F32_TO_I64_R_MINMAG:
+        time_a_f32_z_i64_x( f32_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F32_TO_F16:
+        time_a_f32_z_f16( f32_to_f16 );
+        break;
+#endif
+#ifdef FLOAT64
+     case F32_TO_F64:
+        time_a_f32_z_f64( f32_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F32_TO_EXTF80:
+        time_a_f32_z_extF80( f32_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F32_TO_F128:
+        time_a_f32_z_f128( f32_to_f128M );
+        break;
+#endif
+     case F32_ROUNDTOINT:
+        time_az_f32_rx( f32_roundToInt, roundingMode, exact );
+        break;
+     case F32_ADD:
+        function_abz_f32 = f32_add;
+        goto time_abz_f32;
+     case F32_SUB:
+        function_abz_f32 = f32_sub;
+        goto time_abz_f32;
+     case F32_MUL:
+        function_abz_f32 = f32_mul;
+        goto time_abz_f32;
+     case F32_DIV:
+        function_abz_f32 = f32_div;
+        goto time_abz_f32;
+     case F32_REM:
+        function_abz_f32 = f32_rem;
+     time_abz_f32:
+        time_abz_f32( function_abz_f32 );
+        break;
+     case F32_MULADD:
+        time_abcz_f32( f32_mulAdd );
+        break;
+     case F32_SQRT:
+        time_az_f32_pos( f32_sqrt );
+        break;
+     case F32_EQ:
+        function_ab_f32_z_bool = f32_eq;
+        goto time_ab_f32_z_bool;
+     case F32_LE:
+        function_ab_f32_z_bool = f32_le;
+        goto time_ab_f32_z_bool;
+     case F32_LT:
+        function_ab_f32_z_bool = f32_lt;
+        goto time_ab_f32_z_bool;
+     case F32_EQ_SIGNALING:
+        function_ab_f32_z_bool = f32_eq_signaling;
+        goto time_ab_f32_z_bool;
+     case F32_LE_QUIET:
+        function_ab_f32_z_bool = f32_le_quiet;
+        goto time_ab_f32_z_bool;
+     case F32_LT_QUIET:
+        function_ab_f32_z_bool = f32_lt_quiet;
+     time_ab_f32_z_bool:
+        time_ab_f32_z_bool( function_ab_f32_z_bool );
+        break;
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT64
+     case F64_TO_UI32:
+        time_a_f64_z_ui32_rx( f64_to_ui32, roundingMode, exact );
+        break;
+     case F64_TO_UI64:
+        time_a_f64_z_ui64_rx( f64_to_ui64, roundingMode, exact );
+        break;
+     case F64_TO_I32:
+        time_a_f64_z_i32_rx( f64_to_i32, roundingMode, exact );
+        break;
+     case F64_TO_I64:
+        time_a_f64_z_i64_rx( f64_to_i64, roundingMode, exact );
+        break;
+     case F64_TO_UI32_R_MINMAG:
+        time_a_f64_z_ui32_x( f64_to_ui32_r_minMag, exact );
+        break;
+     case F64_TO_UI64_R_MINMAG:
+        time_a_f64_z_ui64_x( f64_to_ui64_r_minMag, exact );
+        break;
+     case F64_TO_I32_R_MINMAG:
+        time_a_f64_z_i32_x( f64_to_i32_r_minMag, exact );
+        break;
+     case F64_TO_I64_R_MINMAG:
+        time_a_f64_z_i64_x( f64_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F64_TO_F16:
+        time_a_f64_z_f16( f64_to_f16 );
+        break;
+#endif
+     case F64_TO_F32:
+        time_a_f64_z_f32( f64_to_f32 );
+        break;
+#ifdef EXTFLOAT80
+     case F64_TO_EXTF80:
+        time_a_f64_z_extF80( f64_to_extF80M );
+        break;
+#endif
+#ifdef FLOAT128
+     case F64_TO_F128:
+        time_a_f64_z_f128( f64_to_f128M );
+        break;
+#endif
+     case F64_ROUNDTOINT:
+        time_az_f64_rx( f64_roundToInt, roundingMode, exact );
+        break;
+     case F64_ADD:
+        function_abz_f64 = f64_add;
+        goto time_abz_f64;
+     case F64_SUB:
+        function_abz_f64 = f64_sub;
+        goto time_abz_f64;
+     case F64_MUL:
+        function_abz_f64 = f64_mul;
+        goto time_abz_f64;
+     case F64_DIV:
+        function_abz_f64 = f64_div;
+        goto time_abz_f64;
+     case F64_REM:
+        function_abz_f64 = f64_rem;
+     time_abz_f64:
+        time_abz_f64( function_abz_f64 );
+        break;
+     case F64_MULADD:
+        time_abcz_f64( f64_mulAdd );
+        break;
+     case F64_SQRT:
+        time_az_f64_pos( f64_sqrt );
+        break;
+     case F64_EQ:
+        function_ab_f64_z_bool = f64_eq;
+        goto time_ab_f64_z_bool;
+     case F64_LE:
+        function_ab_f64_z_bool = f64_le;
+        goto time_ab_f64_z_bool;
+     case F64_LT:
+        function_ab_f64_z_bool = f64_lt;
+        goto time_ab_f64_z_bool;
+     case F64_EQ_SIGNALING:
+        function_ab_f64_z_bool = f64_eq_signaling;
+        goto time_ab_f64_z_bool;
+     case F64_LE_QUIET:
+        function_ab_f64_z_bool = f64_le_quiet;
+        goto time_ab_f64_z_bool;
+     case F64_LT_QUIET:
+        function_ab_f64_z_bool = f64_lt_quiet;
+     time_ab_f64_z_bool:
+        time_ab_f64_z_bool( function_ab_f64_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef EXTFLOAT80
+     case EXTF80_TO_UI32:
+        time_a_extF80_z_ui32_rx( extF80M_to_ui32, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI64:
+        time_a_extF80_z_ui64_rx( extF80M_to_ui64, roundingMode, exact );
+        break;
+     case EXTF80_TO_I32:
+        time_a_extF80_z_i32_rx( extF80M_to_i32, roundingMode, exact );
+        break;
+     case EXTF80_TO_I64:
+        time_a_extF80_z_i64_rx( extF80M_to_i64, roundingMode, exact );
+        break;
+     case EXTF80_TO_UI32_R_MINMAG:
+        time_a_extF80_z_ui32_x( extF80M_to_ui32_r_minMag, exact );
+        break;
+     case EXTF80_TO_UI64_R_MINMAG:
+        time_a_extF80_z_ui64_x( extF80M_to_ui64_r_minMag, exact );
+        break;
+     case EXTF80_TO_I32_R_MINMAG:
+        time_a_extF80_z_i32_x( extF80M_to_i32_r_minMag, exact );
+        break;
+     case EXTF80_TO_I64_R_MINMAG:
+        time_a_extF80_z_i64_x( extF80M_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case EXTF80_TO_F16:
+        time_a_extF80_z_f16( extF80M_to_f16 );
+        break;
+#endif
+     case EXTF80_TO_F32:
+        time_a_extF80_z_f32( extF80M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case EXTF80_TO_F64:
+        time_a_extF80_z_f64( extF80M_to_f64 );
+        break;
+#endif
+#ifdef FLOAT128
+     case EXTF80_TO_F128:
+        time_a_extF80_z_f128( extF80M_to_f128M );
+        break;
+#endif
+     case EXTF80_ROUNDTOINT:
+        time_az_extF80_rx( extF80M_roundToInt, roundingMode, exact );
+        break;
+     case EXTF80_ADD:
+        function_abz_extF80 = extF80M_add;
+        goto time_abz_extF80;
+     case EXTF80_SUB:
+        function_abz_extF80 = extF80M_sub;
+        goto time_abz_extF80;
+     case EXTF80_MUL:
+        function_abz_extF80 = extF80M_mul;
+        goto time_abz_extF80;
+     case EXTF80_DIV:
+        function_abz_extF80 = extF80M_div;
+        goto time_abz_extF80;
+     case EXTF80_REM:
+        function_abz_extF80 = extF80M_rem;
+     time_abz_extF80:
+        time_abz_extF80( function_abz_extF80 );
+        break;
+     case EXTF80_SQRT:
+        time_az_extF80_pos( extF80M_sqrt );
+        break;
+     case EXTF80_EQ:
+        function_ab_extF80_z_bool = extF80M_eq;
+        goto time_ab_extF80_z_bool;
+     case EXTF80_LE:
+        function_ab_extF80_z_bool = extF80M_le;
+        goto time_ab_extF80_z_bool;
+     case EXTF80_LT:
+        function_ab_extF80_z_bool = extF80M_lt;
+        goto time_ab_extF80_z_bool;
+     case EXTF80_EQ_SIGNALING:
+        function_ab_extF80_z_bool = extF80M_eq_signaling;
+        goto time_ab_extF80_z_bool;
+     case EXTF80_LE_QUIET:
+        function_ab_extF80_z_bool = extF80M_le_quiet;
+        goto time_ab_extF80_z_bool;
+     case EXTF80_LT_QUIET:
+        function_ab_extF80_z_bool = extF80M_lt_quiet;
+     time_ab_extF80_z_bool:
+        time_ab_extF80_z_bool( function_ab_extF80_z_bool );
+        break;
+#endif
+        /*--------------------------------------------------------------------
+        *--------------------------------------------------------------------*/
+#ifdef FLOAT128
+     case F128_TO_UI32:
+        time_a_f128_z_ui32_rx( f128M_to_ui32, roundingMode, exact );
+        break;
+     case F128_TO_UI64:
+        time_a_f128_z_ui64_rx( f128M_to_ui64, roundingMode, exact );
+        break;
+     case F128_TO_I32:
+        time_a_f128_z_i32_rx( f128M_to_i32, roundingMode, exact );
+        break;
+     case F128_TO_I64:
+        time_a_f128_z_i64_rx( f128M_to_i64, roundingMode, exact );
+        break;
+     case F128_TO_UI32_R_MINMAG:
+        time_a_f128_z_ui32_x( f128M_to_ui32_r_minMag, exact );
+        break;
+     case F128_TO_UI64_R_MINMAG:
+        time_a_f128_z_ui64_x( f128M_to_ui64_r_minMag, exact );
+        break;
+     case F128_TO_I32_R_MINMAG:
+        time_a_f128_z_i32_x( f128M_to_i32_r_minMag, exact );
+        break;
+     case F128_TO_I64_R_MINMAG:
+        time_a_f128_z_i64_x( f128M_to_i64_r_minMag, exact );
+        break;
+#ifdef FLOAT16
+     case F128_TO_F16:
+        time_a_f128_z_f16( f128M_to_f16 );
+        break;
+#endif
+     case F128_TO_F32:
+        time_a_f128_z_f32( f128M_to_f32 );
+        break;
+#ifdef FLOAT64
+     case F128_TO_F64:
+        time_a_f128_z_f64( f128M_to_f64 );
+        break;
+#endif
+#ifdef EXTFLOAT80
+     case F128_TO_EXTF80:
+        time_a_f128_z_extF80( f128M_to_extF80M );
+        break;
+#endif
+     case F128_ROUNDTOINT:
+        time_az_f128_rx( f128M_roundToInt, roundingMode, exact );
+        break;
+     case F128_ADD:
+        function_abz_f128 = f128M_add;
+        goto time_abz_f128;
+     case F128_SUB:
+        function_abz_f128 = f128M_sub;
+        goto time_abz_f128;
+     case F128_MUL:
+        function_abz_f128 = f128M_mul;
+        goto time_abz_f128;
+     case F128_DIV:
+        function_abz_f128 = f128M_div;
+        goto time_abz_f128;
+     case F128_REM:
+        function_abz_f128 = f128M_rem;
+     time_abz_f128:
+        time_abz_f128( function_abz_f128 );
+        break;
+     case F128_MULADD:
+        time_abcz_f128( f128M_mulAdd );
+        break;
+     case F128_SQRT:
+        time_az_f128_pos( f128M_sqrt );
+        break;
+     case F128_EQ:
+        function_ab_f128_z_bool = f128M_eq;
+        goto time_ab_f128_z_bool;
+     case F128_LE:
+        function_ab_f128_z_bool = f128M_le;
+        goto time_ab_f128_z_bool;
+     case F128_LT:
+        function_ab_f128_z_bool = f128M_lt;
+        goto time_ab_f128_z_bool;
+     case F128_EQ_SIGNALING:
+        function_ab_f128_z_bool = f128M_eq_signaling;
+        goto time_ab_f128_z_bool;
+     case F128_LE_QUIET:
+        function_ab_f128_z_bool = f128M_le_quiet;
+        goto time_ab_f128_z_bool;
+     case F128_LT_QUIET:
+        function_ab_f128_z_bool = f128M_lt_quiet;
+     time_ab_f128_z_bool:
+        time_ab_f128_z_bool( function_ab_f128_z_bool );
+        break;
+#endif
+    }
+
+}
+
+enum { EXACT_FALSE = 1, EXACT_TRUE };
+
+static
+void
+ timeFunction(
+     int functionCode,
+     uint_fast8_t roundingPrecisionIn,
+     int roundingCodeIn,
+     int tininessCodeIn,
+     int exactCodeIn
+ )
+{
+    int functionAttribs, exactCode;
+    uint_fast8_t roundingMode, tininessMode;
+
+    functionNamePtr = functionInfos[functionCode].namePtr;
+    functionAttribs = functionInfos[functionCode].attribs;
+    roundingPrecision = 32;
+    for (;;) {
+        if ( functionAttribs & FUNC_EFF_ROUNDINGPRECISION ) {
+            if ( roundingPrecisionIn ) roundingPrecision = roundingPrecisionIn;
+        } else {
+            roundingPrecision = 0;
+        }
+#ifdef EXTFLOAT80
+        if ( roundingPrecision ) extF80_roundingPrecision = roundingPrecision;
+#endif
+        for (
+            roundingCode = 1; roundingCode < NUM_ROUNDINGMODES; ++roundingCode
+        ) {
+            if (
+                functionAttribs
+                    & (FUNC_ARG_ROUNDINGMODE | FUNC_EFF_ROUNDINGMODE)
+            ) {
+                if ( roundingCodeIn ) roundingCode = roundingCodeIn;
+            } else {
+                roundingCode = 0;
+            }
+            if ( roundingCode ) {
+                roundingMode = roundingModes[roundingCode];
+                if ( functionAttribs & FUNC_EFF_ROUNDINGMODE ) {
+                    softfloat_roundingMode = roundingMode;
+                }
+            }
+            for (
+                exactCode = EXACT_FALSE; exactCode <= EXACT_TRUE; ++exactCode
+            ) {
+                if ( functionAttribs & FUNC_ARG_EXACT ) {
+                    if ( exactCodeIn ) exactCode = exactCodeIn;
+                } else {
+                    exactCode = 0;
+                }
+                exact = (exactCode == EXACT_TRUE );
+                usesExact = (exactCode != 0 );
+                for (
+                    tininessCode = 1;
+                    tininessCode < NUM_TININESSMODES;
+                    ++tininessCode
+                ) {
+                    if (
+                        (functionAttribs & FUNC_EFF_TININESSMODE)
+                            || ((functionAttribs
+                                     & FUNC_EFF_TININESSMODE_REDUCEDPREC)
+                                    && roundingPrecision
+                                    && (roundingPrecision < 80))
+                    ) {
+                        if ( tininessCodeIn ) tininessCode = tininessCodeIn;
+                    } else {
+                        tininessCode = 0;
+                    }
+                    if ( tininessCode ) {
+                        tininessMode = tininessModes[tininessCode];
+                        softfloat_detectTininess = tininessMode;
+                    }
+                    timeFunctionInstance( functionCode, roundingMode, exact );
+                    if ( tininessCodeIn || ! tininessCode ) break;
+                }
+                if ( exactCodeIn || ! exactCode ) break;
+            }
+            if ( roundingCodeIn || ! roundingCode ) break;
+        }
+        if ( roundingPrecisionIn || ! roundingPrecision ) break;
+        if ( roundingPrecision == 80 ) {
+            break;
+        } else if ( roundingPrecision == 64 ) {
+            roundingPrecision = 80;
+        } else if ( roundingPrecision == 32 ) {
+            roundingPrecision = 64;
+        }
+    }
+
+}
+
+int main( int argc, char *argv[] )
+{
+    bool haveFunctionArg;
+    int functionCode, numOperands;
+    uint_fast8_t roundingPrecision;
+    int roundingCode, tininessCode, exactCode;
+    const char *argPtr;
+
+    fail_programName = "timesoftfloat";
+    if ( argc <= 1 ) goto writeHelpMessage;
+    haveFunctionArg = false;
+    functionCode = 0;
+    numOperands = 0;
+    roundingPrecision = 0;
+    roundingCode = 0;
+    tininessCode = 0;
+    exactCode = 0;
+    for (;;) {
+        --argc;
+        if ( ! argc ) break;
+        argPtr = *++argv;
+        if ( ! argPtr ) break;
+        if ( argPtr[0] == '-' ) ++argPtr;
+        if (
+            ! strcmp( argPtr, "help" ) || ! strcmp( argPtr, "-help" )
+                || ! strcmp( argPtr, "h" )
+        ) {
+ writeHelpMessage:
+            fputs(
+"timesoftfloat [<option>...] <function>\n"
+"  <option>:  (* is default)\n"
+"    -help            --Write this message and exit.\n"
+#ifdef EXTFLOAT80
+"    -precision32     --For extF80, time only 32-bit rounding precision.\n"
+"    -precision64     --For extF80, time only 64-bit rounding precision.\n"
+"    -precision80     --For extF80, time only 80-bit rounding precision.\n"
+#endif
+"    -rnear_even      --Time only rounding to nearest/even.\n"
+"    -rminMag         --Time only rounding to minimum magnitude (toward zero).\n"
+"    -rmin            --Time only rounding to minimum (down).\n"
+"    -rmax            --Time only rounding to maximum (up).\n"
+"    -rnear_maxMag    --Time only rounding to nearest/maximum magnitude\n"
+"                         (nearest/away).\n"
+#ifdef FLOAT_ROUND_ODD
+"    -rodd            --Time only rounding to odd (jamming).\n"
+#endif
+"    -tininessbefore  --Time only underflow tininess detected before rounding.\n"
+"    -tininessafter   --Time only underflow tininess detected after rounding.\n"
+"    -notexact        --Time only non-exact rounding to integer (no inexact\n"
+"                         exception).\n"
+"    -exact           --Time only exact rounding to integer (allow inexact\n"
+"                         exception).\n"
+"  <function>:\n"
+"    <int>_to_<float>            <float>_add      <float>_eq\n"
+"    <float>_to_<int>            <float>_sub      <float>_le\n"
+"    <float>_to_<int>_r_minMag   <float>_mul      <float>_lt\n"
+"    <float>_to_<float>          <float>_mulAdd   <float>_eq_signaling\n"
+"    <float>_roundToInt          <float>_div      <float>_le_quiet\n"
+"                                <float>_rem      <float>_lt_quiet\n"
+"                                <float>_sqrt\n"
+"    -all1            --All unary functions.\n"
+"    -all2            --All binary functions.\n"
+"    -all             --All functions.\n"
+"  <int>:\n"
+"    ui32             --Unsigned 32-bit integer.\n"
+"    ui64             --Unsigned 64-bit integer.\n"
+"    i32              --Signed 32-bit integer.\n"
+"    i64              --Signed 64-bit integer.\n"
+"  <float>:\n"
+#ifdef FLOAT16
+"    f16              --Binary 16-bit floating-point (half-precision).\n"
+#endif
+"    f32              --Binary 32-bit floating-point (single-precision).\n"
+#ifdef FLOAT64
+"    f64              --Binary 64-bit floating-point (double-precision).\n"
+#endif
+#ifdef EXTFLOAT80
+"    extF80           --Binary 80-bit extended floating-point.\n"
+#endif
+#ifdef FLOAT128
+"    f128             --Binary 128-bit floating-point (quadruple-precision).\n"
+#endif
+                ,
+                stdout
+            );
+            return EXIT_SUCCESS;
+#ifdef EXTFLOAT80
+        } else if ( ! strcmp( argPtr, "precision32" ) ) {
+            roundingPrecision = 32;
+        } else if ( ! strcmp( argPtr, "precision64" ) ) {
+            roundingPrecision = 64;
+        } else if ( ! strcmp( argPtr, "precision80" ) ) {
+            roundingPrecision = 80;
+#endif
+        } else if (
+               ! strcmp( argPtr, "rnear_even" )
+            || ! strcmp( argPtr, "rneareven" )
+            || ! strcmp( argPtr, "rnearest_even" )
+        ) {
+            roundingCode = ROUND_NEAR_EVEN;
+        } else if (
+            ! strcmp( argPtr, "rminmag" ) || ! strcmp( argPtr, "rminMag" )
+        ) {
+            roundingCode = ROUND_MINMAG;
+        } else if ( ! strcmp( argPtr, "rmin" ) ) {
+            roundingCode = ROUND_MIN;
+        } else if ( ! strcmp( argPtr, "rmax" ) ) {
+            roundingCode = ROUND_MAX;
+        } else if (
+               ! strcmp( argPtr, "rnear_maxmag" )
+            || ! strcmp( argPtr, "rnear_maxMag" )
+            || ! strcmp( argPtr, "rnearmaxmag" )
+            || ! strcmp( argPtr, "rnearest_maxmag" )
+            || ! strcmp( argPtr, "rnearest_maxMag" )
+        ) {
+            roundingCode = ROUND_NEAR_MAXMAG;
+#ifdef FLOAT_ROUND_ODD
+        } else if ( ! strcmp( argPtr, "rodd" ) ) {
+            roundingCode = ROUND_ODD;
+#endif
+        } else if ( ! strcmp( argPtr, "tininessbefore" ) ) {
+            tininessCode = TININESS_BEFORE_ROUNDING;
+        } else if ( ! strcmp( argPtr, "tininessafter" ) ) {
+            tininessCode = TININESS_AFTER_ROUNDING;
+        } else if ( ! strcmp( argPtr, "notexact" ) ) {
+            exactCode = EXACT_FALSE;
+        } else if ( ! strcmp( argPtr, "exact" ) ) {
+            exactCode = EXACT_TRUE;
+        } else if ( ! strcmp( argPtr, "all1" ) ) {
+            haveFunctionArg = true;
+            functionCode = 0;
+            numOperands = 1;
+        } else if ( ! strcmp( argPtr, "all2" ) ) {
+            haveFunctionArg = true;
+            functionCode = 0;
+            numOperands = 2;
+        } else if ( ! strcmp( argPtr, "all" ) ) {
+            haveFunctionArg = true;
+            functionCode = 0;
+            numOperands = 0;
+        } else {
+            functionCode = 1;
+            while ( strcmp( argPtr, functionInfos[functionCode].namePtr ) ) {
+                ++functionCode;
+                if ( functionCode == NUM_FUNCTIONS ) {
+                    fail( "Invalid argument '%s'", *argv );
+                }
+            }
+            haveFunctionArg = true;
+        }
+    }
+    if ( ! haveFunctionArg ) fail( "Function argument required" );
+    if ( functionCode ) {
+        timeFunction(
+            functionCode,
+            roundingPrecision,
+            roundingCode,
+            tininessCode,
+            exactCode
+        );
+    } else {
+        for (
+            functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode
+        ) {
+            if (
+                ! numOperands
+                    || (functionInfos[functionCode].attribs
+                            & ((numOperands == 1) ? FUNC_ARG_UNARY
+                                   : FUNC_ARG_BINARY))
+            ) {
+                timeFunction(
+                    functionCode,
+                    roundingPrecision,
+                    roundingCode,
+                    tininessCode,
+                    exactCode
+                );
+            }
+        }
+    }
+    return EXIT_SUCCESS;
+
+}
+
diff --git a/addins/TestFloat-3e/source/uint128.c b/addins/TestFloat-3e/source/uint128.c
new file mode 100644
index 000000000..eeda08231
--- /dev/null
+++ b/addins/TestFloat-3e/source/uint128.c
@@ -0,0 +1,99 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "uint128.h"
+
+struct uint128 shortShiftLeft128( struct uint128 a, int count )
+{
+    struct uint128 z;
+
+    z.v64 = a.v64<<count | a.v0>>(-count & 63);
+    z.v0 = a.v0<<count;
+    return z;
+
+}
+
+struct uint128 shortShiftRight128( struct uint128 a, int count )
+{
+    struct uint128 z;
+
+    z.v64 = a.v64>>count;
+    z.v0 = a.v64<<(-count & 63) | a.v0>>count;
+    return z;
+
+}
+
+struct uint128 shortShiftRightJam128( struct uint128 a, int count )
+{
+    int negCount;
+    struct uint128 z;
+
+    negCount = -count;
+    z.v64 = a.v64>>count;
+    z.v0 =
+        a.v64<<(negCount & 63) | a.v0>>count
+            | ((uint64_t) (a.v0<<(negCount & 63)) != 0);
+    return z;
+
+}
+
+struct uint128 neg128( struct uint128 a )
+{
+
+    if ( a.v0 ) {
+        a.v64 = ~a.v64;
+        a.v0 = -a.v0;
+    } else {
+        a.v64 = -a.v64;
+    }
+    return a;
+
+}
+
+struct uint128 add128( struct uint128 a, struct uint128 b )
+{
+    struct uint128 z;
+
+    z.v0 = a.v0 + b.v0;
+    z.v64 = a.v64 + b.v64 + (z.v0 < a.v0);
+    return z;
+
+}
+
diff --git a/addins/TestFloat-3e/source/uint128.h b/addins/TestFloat-3e/source/uint128.h
new file mode 100644
index 000000000..035a1e89c
--- /dev/null
+++ b/addins/TestFloat-3e/source/uint128.h
@@ -0,0 +1,76 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#ifndef uint128_h
+#define uint128_h 1
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef LITTLEENDIAN
+struct uint128 { uint64_t v0, v64; };
+#else
+struct uint128 { uint64_t v64, v0; };
+#endif
+
+#ifdef INLINE
+
+INLINE bool eq128( struct uint128 a, struct uint128 b )
+    { return (a.v64 == b.v64) && (a.v0 == b.v0); }
+
+INLINE bool le128( struct uint128 a, struct uint128 b )
+    { return (a.v64 < b.v64) || ((a.v64 == b.v64) && (a.v0 <= b.v0)); }
+
+INLINE bool lt128( struct uint128 a, struct uint128 b )
+    { return (a.v64 < b.v64) || ((a.v64 == b.v64) && (a.v0 < b.v0)); }
+
+#else
+
+bool eq128( struct uint128, struct uint128 );
+bool le128( struct uint128, struct uint128 );
+bool lt128( struct uint128, struct uint128 );
+
+#endif
+
+struct uint128 shortShiftLeft128( struct uint128, int );
+struct uint128 shortShiftRight128( struct uint128, int );
+struct uint128 shortShiftRightJam128( struct uint128, int );
+struct uint128 neg128( struct uint128 );
+struct uint128 add128( struct uint128, struct uint128 );
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/uint128_inline.c b/addins/TestFloat-3e/source/uint128_inline.c
new file mode 100644
index 000000000..45d6cc2a9
--- /dev/null
+++ b/addins/TestFloat-3e/source/uint128_inline.c
@@ -0,0 +1,56 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef LITTLEENDIAN
+struct uint128 { uint64_t v0, v64; };
+#else
+struct uint128 { uint64_t v64, v0; };
+#endif
+
+bool eq128( struct uint128 a, struct uint128 b )
+    { return (a.v64 == b.v64) && (a.v0 == b.v0); }
+
+bool le128( struct uint128 a, struct uint128 b )
+    { return (a.v64 < b.v64) || ((a.v64 == b.v64) && (a.v0 <= b.v0)); }
+
+bool lt128( struct uint128 a, struct uint128 b )
+    { return (a.v64 < b.v64) || ((a.v64 == b.v64) && (a.v0 < b.v0)); }
+
diff --git a/addins/TestFloat-3e/source/verCases.h b/addins/TestFloat-3e/source/verCases.h
new file mode 100644
index 000000000..7860ede75
--- /dev/null
+++ b/addins/TestFloat-3e/source/verCases.h
@@ -0,0 +1,193 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <signal.h>
+#include "uint128.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+extern const char *verCases_functionNamePtr;
+extern uint_fast8_t verCases_roundingPrecision;
+extern int verCases_roundingCode;
+extern int verCases_tininessCode;
+extern bool verCases_usesExact, verCases_exact;
+extern bool verCases_checkNaNs, verCases_checkInvInts;
+extern uint_fast32_t verCases_maxErrorCount;
+extern bool verCases_errorStop;
+
+void verCases_writeFunctionName( FILE * );
+
+extern volatile sig_atomic_t verCases_stop;
+
+extern bool verCases_anyErrors;
+
+void verCases_exitWithStatus( void );
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef INLINE
+
+#ifdef FLOAT16
+
+INLINE bool f16_same( float16_t a, float16_t b )
+{
+    union { uint16_t ui; float16_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+INLINE bool f16_isNaN( float16_t a )
+{
+    union { uint16_t ui; float16_t f; } uA;
+    uA.f = a;
+    return 0x7C00 < (uA.ui & 0x7FFF);
+}
+
+#endif
+
+INLINE bool f32_same( float32_t a, float32_t b )
+{
+    union { uint32_t ui; float32_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+INLINE bool f32_isNaN( float32_t a )
+{
+    union { uint32_t ui; float32_t f; } uA;
+    uA.f = a;
+    return 0x7F800000 < (uA.ui & 0x7FFFFFFF);
+}
+
+#ifdef FLOAT64
+
+INLINE bool f64_same( float64_t a, float64_t b )
+{
+    union { uint64_t ui; float64_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+INLINE bool f64_isNaN( float64_t a )
+{
+    union { uint64_t ui; float64_t f; } uA;
+    uA.f = a;
+    return
+        UINT64_C( 0x7FF0000000000000 )
+            < (uA.ui & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+INLINE bool extF80M_same( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr = (const struct extFloat80M *) aPtr;
+    const struct extFloat80M *bSPtr = (const struct extFloat80M *) bPtr;
+    return
+        (aSPtr->signExp == bSPtr->signExp) && (aSPtr->signif == bSPtr->signif);
+}
+
+INLINE bool extF80M_isNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr = (const struct extFloat80M *) aPtr;
+    return
+        ((aSPtr->signExp & 0x7FFF) == 0x7FFF)
+            && (aSPtr->signif & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+}
+
+#endif
+
+#ifdef FLOAT128
+
+INLINE bool f128M_same( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const struct uint128 *uiAPtr = (const struct uint128 *) aPtr;
+    const struct uint128 *uiBPtr = (const struct uint128 *) bPtr;
+    return (uiAPtr->v64 == uiBPtr->v64) && (uiAPtr->v0 == uiBPtr->v0);
+}
+
+INLINE bool f128M_isNaN( const float128_t *aPtr )
+{
+    const struct uint128 *uiAPtr = (const struct uint128 *) aPtr;
+    uint_fast64_t absA64 = uiAPtr->v64 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    return
+        (UINT64_C( 0x7FFF000000000000 ) < absA64)
+            || ((absA64 == UINT64_C( 0x7FFF000000000000 )) && uiAPtr->v0);
+}
+
+#endif
+
+#else
+
+#ifdef FLOAT16
+bool f16_same( float16_t, float16_t );
+bool f16_isNaN( float16_t );
+#endif
+bool f32_same( float32_t, float32_t );
+bool f32_isNaN( float32_t );
+#ifdef FLOAT64
+bool f64_same( float64_t, float64_t );
+bool f64_isNaN( float64_t );
+#endif
+#ifdef EXTFLOAT80
+bool extF80M_same( const extFloat80_t *, const extFloat80_t * );
+bool extF80M_isNaN( const extFloat80_t * );
+#endif
+#ifdef FLOAT128
+bool f128M_same( const float128_t *, const float128_t * );
+bool f128M_isNaN( const float128_t * );
+#endif
+
+#endif
+
+extern uint_fast32_t verCases_tenThousandsCount, verCases_errorCount;
+
+void verCases_writeTestsPerformed( int );
+void verCases_perTenThousand( void );
+void verCases_writeErrorFound( int );
+
diff --git a/addins/TestFloat-3e/source/verCases_common.c b/addins/TestFloat-3e/source/verCases_common.c
new file mode 100644
index 000000000..416cfdbdc
--- /dev/null
+++ b/addins/TestFloat-3e/source/verCases_common.c
@@ -0,0 +1,138 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017, 2018 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <signal.h>
+#include "platform.h"
+#include "verCases.h"
+
+const char *verCases_functionNamePtr;
+uint_fast8_t verCases_roundingPrecision = 0;
+int verCases_roundingCode = 0;
+int verCases_tininessCode = 0;
+bool verCases_usesExact = false;
+bool verCases_exact;
+bool verCases_checkNaNs = false;
+bool verCases_checkInvInts = false;
+uint_fast32_t verCases_maxErrorCount = 0;
+bool verCases_errorStop = false;
+
+volatile sig_atomic_t verCases_stop = false;
+
+bool verCases_anyErrors = false;
+
+void verCases_exitWithStatus( void )
+{
+
+    exit( verCases_anyErrors ? EXIT_FAILURE : EXIT_SUCCESS );
+
+}
+
+uint_fast32_t verCases_tenThousandsCount, verCases_errorCount;
+
+void verCases_writeTestsPerformed( int count )
+{
+
+    if ( verCases_tenThousandsCount ) {
+        fprintf(
+            stderr,
+            "\r%lu%04d tests performed",
+            (unsigned long) verCases_tenThousandsCount,
+            count
+        );
+    } else {
+        fprintf( stderr, "\r%d tests performed", count );
+    }
+    if ( verCases_errorCount ) {
+        fprintf(
+            stderr,
+            "; %lu error%s found.\n",
+            (unsigned long) verCases_errorCount,
+            (verCases_errorCount == 1) ? "" : "s"
+        );
+    } else {
+        fputs( ".\n", stderr );
+        if ( verCases_tenThousandsCount ) {
+            fprintf(
+                stdout,
+                "In %lu%04d tests, no errors found in ",
+                (unsigned long) verCases_tenThousandsCount,
+                count
+            );
+        } else {
+            fprintf( stdout, "In %d tests, no errors found in ", count );
+        }
+        verCases_writeFunctionName( stdout );
+        fputs( ".\n", stdout );
+        fflush( stdout );
+    }
+
+}
+
+void verCases_perTenThousand( void )
+{
+
+    ++verCases_tenThousandsCount;
+    if ( verCases_stop ) {
+        verCases_writeTestsPerformed( 0 );
+        verCases_exitWithStatus();
+    }
+    fprintf(
+        stderr, "\r%3lu0000", (unsigned long) verCases_tenThousandsCount );
+
+}
+
+void verCases_writeErrorFound( int count )
+{
+
+    fputc( '\r', stderr );
+    if ( verCases_errorCount == 1 ) {
+        fputs( "Errors found in ", stdout );
+        verCases_writeFunctionName( stdout );
+        fputs( ":\n", stdout );
+    }
+    if ( verCases_stop ) {
+        verCases_writeTestsPerformed( count );
+        verCases_exitWithStatus();
+    }
+    verCases_anyErrors = true;
+
+}
+
diff --git a/addins/TestFloat-3e/source/verCases_inline.c b/addins/TestFloat-3e/source/verCases_inline.c
new file mode 100644
index 000000000..90799f455
--- /dev/null
+++ b/addins/TestFloat-3e/source/verCases_inline.c
@@ -0,0 +1,138 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "uint128.h"
+#include "softfloat.h"
+
+#ifdef FLOAT16
+
+bool f16_same( float16_t a, float16_t b )
+{
+    union { uint16_t ui; float16_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+bool f16_isNaN( float16_t a )
+{
+    union { uint16_t ui; float16_t f; } uA;
+    uA.f = a;
+    return 0x7C00 < (uA.ui & 0x7FFF);
+}
+
+#endif
+
+bool f32_same( float32_t a, float32_t b )
+{
+    union { uint32_t ui; float32_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+bool f32_isNaN( float32_t a )
+{
+    union { uint32_t ui; float32_t f; } uA;
+    uA.f = a;
+    return 0x7F800000 < (uA.ui & 0x7FFFFFFF);
+}
+
+#ifdef FLOAT64
+
+bool f64_same( float64_t a, float64_t b )
+{
+    union { uint64_t ui; float64_t f; } uA, uB;
+    uA.f = a;
+    uB.f = b;
+    return (uA.ui == uB.ui);
+}
+
+bool f64_isNaN( float64_t a )
+{
+    union { uint64_t ui; float64_t f; } uA;
+    uA.f = a;
+    return
+        UINT64_C( 0x7FF0000000000000 )
+            < (uA.ui & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+bool extF80M_same( const extFloat80_t *aPtr, const extFloat80_t *bPtr )
+{
+    const struct extFloat80M *aSPtr = (const struct extFloat80M *) aPtr;
+    const struct extFloat80M *bSPtr = (const struct extFloat80M *) bPtr;
+    return
+        (aSPtr->signExp == bSPtr->signExp) && (aSPtr->signif == bSPtr->signif);
+}
+
+bool extF80M_isNaN( const extFloat80_t *aPtr )
+{
+    const struct extFloat80M *aSPtr = (const struct extFloat80M *) aPtr;
+    return
+        ((aSPtr->signExp & 0x7FFF) == 0x7FFF)
+            && (aSPtr->signif & UINT64_C( 0x7FFFFFFFFFFFFFFF ));
+}
+
+#endif
+
+#ifdef FLOAT128
+
+bool f128M_same( const float128_t *aPtr, const float128_t *bPtr )
+{
+    const struct uint128 *uiAPtr = (const struct uint128 *) aPtr;
+    const struct uint128 *uiBPtr = (const struct uint128 *) bPtr;
+    return (uiAPtr->v64 == uiBPtr->v64) && (uiAPtr->v0 == uiBPtr->v0);
+}
+
+bool f128M_isNaN( const float128_t *aPtr )
+{
+    const struct uint128 *uiAPtr = (const struct uint128 *) aPtr;
+    uint_fast64_t absA64 = uiAPtr->v64 & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+    return
+        (UINT64_C( 0x7FFF000000000000 ) < absA64)
+            || ((absA64 == UINT64_C( 0x7FFF000000000000 )) && uiAPtr->v0);
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/verCases_writeFunctionName.c b/addins/TestFloat-3e/source/verCases_writeFunctionName.c
new file mode 100644
index 000000000..d4e250a2b
--- /dev/null
+++ b/addins/TestFloat-3e/source/verCases_writeFunctionName.c
@@ -0,0 +1,79 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdio.h>
+#include "platform.h"
+#include "functions.h"
+#include "verCases.h"
+
+void verCases_writeFunctionName( FILE *streamPtr )
+{
+    static const char *roundingModeNames[NUM_ROUNDINGMODES] = {
+        0,
+        ", rounding near_even",
+        ", rounding minMag",
+        ", rounding min",
+        ", rounding max",
+        ", rounding near_maxMag",
+#ifdef FLOAT_ROUND_ODD
+        ", rounding odd"
+#endif
+    };
+
+    fputs( verCases_functionNamePtr, streamPtr );
+    if ( verCases_roundingCode ) {
+        if ( verCases_roundingPrecision ) {
+            fprintf(
+                streamPtr, ", precision %d", (int) verCases_roundingPrecision
+            );
+        }
+        fputs( roundingModeNames[verCases_roundingCode], streamPtr );
+        if ( verCases_tininessCode ) {
+            fputs(
+                (verCases_tininessCode == TININESS_BEFORE_ROUNDING)
+                    ? ", tininess before rounding"
+                    : ", tininess after rounding",
+                streamPtr
+            );
+        }
+    }
+    if ( verCases_usesExact ) {
+        fputs( verCases_exact ? ", exact" : ", not exact", streamPtr );
+    }
+
+}
+
diff --git a/addins/TestFloat-3e/source/verLoops.c b/addins/TestFloat-3e/source/verLoops.c
new file mode 100644
index 000000000..125971384
--- /dev/null
+++ b/addins/TestFloat-3e/source/verLoops.c
@@ -0,0 +1,5283 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "platform.h"
+#include "uint128.h"
+#include "fail.h"
+#include "softfloat.h"
+#include "readHex.h"
+#include "verCases.h"
+#include "writeCase.h"
+#include "verLoops.h"
+
+uint_fast8_t *verLoops_trueFlagsPtr;
+
+static bool atEndOfInput( void )
+{
+    int i;
+
+    i = fgetc( stdin );
+    if ( i == EOF ) {
+        if ( ! ferror( stdin ) && feof( stdin ) ) return true;
+        fail( "Error reading input" );
+    }
+    ungetc( i, stdin );
+    return false;
+
+}
+
+static void failFromBadInput( void )
+{
+
+    fail( "Invalid input format" );
+
+}
+
+static void readVerInput_bool( bool *aPtr )
+{
+
+    if ( ! readHex_bool( aPtr, ' ' ) ) failFromBadInput();
+
+}
+
+static void readVerInput_ui32( uint_fast32_t *aPtr )
+{
+    uint32_t a;
+
+    if ( ! readHex_ui32( &a, ' ' ) ) failFromBadInput();
+    *aPtr = a;
+
+}
+
+static void readVerInput_ui64( uint_fast64_t *aPtr )
+{
+    uint64_t a;
+
+    if ( ! readHex_ui64( &a, ' ' ) ) failFromBadInput();
+    *aPtr = a;
+
+}
+
+static void readVerInput_i32( int_fast32_t *aPtr )
+{
+    union { uint32_t ui; int32_t i; } uA;
+
+    if ( ! readHex_ui32( &uA.ui, ' ' ) ) failFromBadInput();
+    *aPtr = uA.i;
+
+}
+
+static void readVerInput_i64( int_fast64_t *aPtr )
+{
+    union { uint64_t ui; int64_t i; } uA;
+
+    if ( ! readHex_ui64( &uA.ui, ' ' ) ) failFromBadInput();
+    *aPtr = uA.i;
+
+}
+
+#ifdef FLOAT16
+
+static void readVerInput_f16( float16_t *aPtr )
+{
+    union { uint16_t ui; float16_t f; } uA;
+
+    if ( ! readHex_ui16( &uA.ui, ' ' ) ) failFromBadInput();
+    *aPtr = uA.f;
+
+}
+
+#endif
+
+static void readVerInput_f32( float32_t *aPtr )
+{
+    union { uint32_t ui; float32_t f; } uA;
+
+    if ( ! readHex_ui32( &uA.ui, ' ' ) ) failFromBadInput();
+    *aPtr = uA.f;
+
+}
+
+#ifdef FLOAT64
+
+static void readVerInput_f64( float64_t *aPtr )
+{
+    union { uint64_t ui; float64_t f; } uA;
+
+    if ( ! readHex_ui64( &uA.ui, ' ' ) ) failFromBadInput();
+    *aPtr = uA.f;
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+static void readVerInput_extF80( extFloat80_t *aPtr )
+{
+    struct extFloat80M *aSPtr;
+
+    aSPtr = (struct extFloat80M *) aPtr;
+    if (
+           ! readHex_ui16( &aSPtr->signExp, 0 )
+        || ! readHex_ui64( &aSPtr->signif, ' ' )
+    ) {
+        failFromBadInput();
+    }
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+static void readVerInput_f128( float128_t *aPtr )
+{
+    struct uint128 *uiAPtr;
+
+    uiAPtr = (struct uint128 *) aPtr;
+    if (
+        ! readHex_ui64( &uiAPtr->v64, 0 ) || ! readHex_ui64( &uiAPtr->v0, ' ' )
+    ) {
+        failFromBadInput();
+    }
+
+}
+
+#endif
+
+static void readVerInput_flags( uint_fast8_t *flagsPtr )
+{
+    uint_least8_t commonFlags;
+    uint_fast8_t flags;
+
+    if ( ! readHex_ui8( &commonFlags, '\n' ) || (0x20 <= commonFlags) ) {
+        failFromBadInput();
+    }
+    flags = 0;
+    if ( commonFlags & 0x10 ) flags |= softfloat_flag_invalid;
+    if ( commonFlags & 0x08 ) flags |= softfloat_flag_infinite;
+    if ( commonFlags & 0x04 ) flags |= softfloat_flag_overflow;
+    if ( commonFlags & 0x02 ) flags |= softfloat_flag_underflow;
+    if ( commonFlags & 0x01 ) flags |= softfloat_flag_inexact;
+    *flagsPtr = flags;
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+void ver_a_ui32_z_f16( float16_t trueFunction( uint32_t ) )
+{
+    int count;
+    uint_fast32_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui32( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_ui32_z_f32( float32_t trueFunction( uint32_t ) )
+{
+    int count;
+    uint_fast32_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui32( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_ui32_z_f64( float64_t trueFunction( uint32_t ) )
+{
+    int count;
+    uint_fast32_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui32( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_ui32_z_extF80( void trueFunction( uint32_t, extFloat80_t * ) )
+{
+    int count;
+    uint_fast32_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui32( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_ui32_z_f128( void trueFunction( uint32_t, float128_t * ) )
+{
+    int count;
+    uint_fast32_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui32( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui32( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+void ver_a_ui64_z_f16( float16_t trueFunction( uint64_t ) )
+{
+    int count;
+    uint_fast64_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui64( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_ui64_z_f32( float32_t trueFunction( uint64_t ) )
+{
+    int count;
+    uint_fast64_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui64( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_ui64_z_f64( float64_t trueFunction( uint64_t ) )
+{
+    int count;
+    uint_fast64_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui64( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_ui64_z_extF80( void trueFunction( uint64_t, extFloat80_t * ) )
+{
+    int count;
+    uint_fast64_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui64( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_ui64_z_f128( void trueFunction( uint64_t, float128_t * ) )
+{
+    int count;
+    uint_fast64_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_ui64( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_ui64( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+void ver_a_i32_z_f16( float16_t trueFunction( int32_t ) )
+{
+    int count;
+    int_fast32_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i32( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_i32_z_f32( float32_t trueFunction( int32_t ) )
+{
+    int count;
+    int_fast32_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i32( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_i32_z_f64( float64_t trueFunction( int32_t ) )
+{
+    int count;
+    int_fast32_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i32( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_i32_z_extF80( void trueFunction( int32_t, extFloat80_t * ) )
+{
+    int count;
+    int_fast32_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i32( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_i32_z_f128( void trueFunction( int32_t, float128_t * ) )
+{
+    int count;
+    int_fast32_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i32( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i32( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+void ver_a_i64_z_f16( float16_t trueFunction( int64_t ) )
+{
+    int count;
+    int_fast64_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i64( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_i64_z_f32( float32_t trueFunction( int64_t ) )
+{
+    int count;
+    int_fast64_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i64( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_i64_z_f64( float64_t trueFunction( int64_t ) )
+{
+    int count;
+    int_fast64_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i64( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_i64_z_extF80( void trueFunction( int64_t, extFloat80_t * ) )
+{
+    int count;
+    int_fast64_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i64( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_i64_z_f128( void trueFunction( int64_t, float128_t * ) )
+{
+    int count;
+    int_fast64_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_i64( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_i64( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT16
+
+void
+ ver_a_f16_z_ui32_rx(
+     uint_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_ui64_rx(
+     uint_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_i32_rx(
+     int_fast32_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f16_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_i64_rx(
+     int_fast64_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f16_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_ui32_x(
+     uint_fast32_t trueFunction( float16_t, bool ), bool exact )
+{
+    int count;
+    float16_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_ui64_x(
+     uint_fast64_t trueFunction( float16_t, bool ), bool exact )
+{
+    int count;
+    float16_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_i32_x(
+     int_fast32_t trueFunction( float16_t, bool ), bool exact )
+{
+    int count;
+    float16_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f16_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f16_z_i64_x(
+     int_fast64_t trueFunction( float16_t, bool ), bool exact )
+{
+    int count;
+    float16_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f16_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_a_f16_z_f32( float32_t trueFunction( float16_t ) )
+{
+    int count;
+    float16_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_f16_z_f64( float64_t trueFunction( float16_t ) )
+{
+    int count;
+    float16_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_f16_z_extF80( void trueFunction( float16_t, extFloat80_t * ) )
+{
+    int count;
+    float16_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_f16_z_f128( void trueFunction( float16_t, float128_t * ) )
+{
+    int count;
+    float16_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_az_f16( float16_t trueFunction( float16_t ) )
+{
+    int count;
+    float16_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_az_f16_rx(
+     float16_t trueFunction( float16_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float16_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f16_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f16( a );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abz_f16( float16_t trueFunction( float16_t, float16_t ) )
+{
+    int count;
+    float16_t a, b, subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f16( &b );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f16_isSignalingNaN( a ) || f16_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f16( a, b );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abcz_f16( float16_t trueFunction( float16_t, float16_t, float16_t ) )
+{
+    int count;
+    float16_t a, b, c, subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f16( &b );
+        readVerInput_f16( &c );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b, c );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   ! verCases_checkNaNs
+                && (f16_isSignalingNaN( a ) || f16_isSignalingNaN( b )
+                        || f16_isSignalingNaN( c ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f16( a, b, c );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_ab_f16_z_bool( bool trueFunction( float16_t, float16_t ) )
+{
+    int count;
+    float16_t a, b;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f16( &a );
+        readVerInput_f16( &b );
+        readVerInput_bool( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f16_isSignalingNaN( a ) || f16_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f16( a, b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+void
+ ver_a_f32_z_ui32_rx(
+     uint_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_ui64_rx(
+     uint_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_i32_rx(
+     int_fast32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f32_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_i64_rx(
+     int_fast64_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f32_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_ui32_x(
+     uint_fast32_t trueFunction( float32_t, bool ), bool exact )
+{
+    int count;
+    float32_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_ui64_x(
+     uint_fast64_t trueFunction( float32_t, bool ), bool exact )
+{
+    int count;
+    float32_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_i32_x(
+     int_fast32_t trueFunction( float32_t, bool ), bool exact )
+{
+    int count;
+    float32_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f32_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f32_z_i64_x(
+     int_fast64_t trueFunction( float32_t, bool ), bool exact )
+{
+    int count;
+    float32_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f32_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT16
+
+void ver_a_f32_z_f16( float16_t trueFunction( float32_t ) )
+{
+    int count;
+    float32_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT64
+
+void ver_a_f32_z_f64( float64_t trueFunction( float32_t ) )
+{
+    int count;
+    float32_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void ver_a_f32_z_extF80( void trueFunction( float32_t, extFloat80_t * ) )
+{
+    int count;
+    float32_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_f32_z_f128( void trueFunction( float32_t, float128_t * ) )
+{
+    int count;
+    float32_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_az_f32( float32_t trueFunction( float32_t ) )
+{
+    int count;
+    float32_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_az_f32_rx(
+     float32_t trueFunction( float32_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float32_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f32_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f32( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abz_f32( float32_t trueFunction( float32_t, float32_t ) )
+{
+    int count;
+    float32_t a, b, subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f32( &b );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f32_isSignalingNaN( a ) || f32_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f32( a, b );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abcz_f32( float32_t trueFunction( float32_t, float32_t, float32_t ) )
+{
+    int count;
+    float32_t a, b, c, subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f32( &b );
+        readVerInput_f32( &c );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b, c );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                   ! verCases_checkNaNs
+                && (f32_isSignalingNaN( a ) || f32_isSignalingNaN( b )
+                        || f32_isSignalingNaN( c ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f32( a, b, c );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_ab_f32_z_bool( bool trueFunction( float32_t, float32_t ) )
+{
+    int count;
+    float32_t a, b;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f32( &a );
+        readVerInput_f32( &b );
+        readVerInput_bool( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f32_isSignalingNaN( a ) || f32_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f32( a, b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT64
+
+void
+ ver_a_f64_z_ui32_rx(
+     uint_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_ui64_rx(
+     uint_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_i32_rx(
+     int_fast32_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f64_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_i64_rx(
+     int_fast64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f64_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_ui32_x(
+     uint_fast32_t trueFunction( float64_t, bool ), bool exact )
+{
+    int count;
+    float64_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_ui64_x(
+     uint_fast64_t trueFunction( float64_t, bool ), bool exact )
+{
+    int count;
+    float64_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_i32_x(
+     int_fast32_t trueFunction( float64_t, bool ), bool exact )
+{
+    int count;
+    float64_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f64_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f64_z_i64_x(
+     int_fast64_t trueFunction( float64_t, bool ), bool exact )
+{
+    int count;
+    float64_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f64_isNaN( a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT16
+
+void ver_a_f64_z_f16( float16_t trueFunction( float64_t ) )
+{
+    int count;
+    float64_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_f64_z_f32( float32_t trueFunction( float64_t ) )
+{
+    int count;
+    float64_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef EXTFLOAT80
+
+void ver_a_f64_z_extF80( void trueFunction( float64_t, extFloat80_t * ) )
+{
+    int count;
+    float64_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void ver_a_f64_z_f128( void trueFunction( float64_t, float128_t * ) )
+{
+    int count;
+    float64_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_az_f64( float64_t trueFunction( float64_t ) )
+{
+    int count;
+    float64_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_az_f64_rx(
+     float64_t trueFunction( float64_t, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float64_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f64_isSignalingNaN( a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f64( a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abz_f64( float64_t trueFunction( float64_t, float64_t ) )
+{
+    int count;
+    float64_t a, b, subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f64( &b );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f64_isSignalingNaN( a ) || f64_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f64( a, b, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_abcz_f64( float64_t trueFunction( float64_t, float64_t, float64_t ) )
+{
+    int count;
+    float64_t a, b, c, subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f64( &b );
+        readVerInput_f64( &c );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b, c );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f64_isSignalingNaN( a ) || f64_isSignalingNaN( b )
+                             || f64_isSignalingNaN( c ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f64( a, b, c );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void ver_ab_f64_z_bool( bool trueFunction( float64_t, float64_t ) )
+{
+    int count;
+    float64_t a, b;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f64( &a );
+        readVerInput_f64( &b );
+        readVerInput_bool( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( a, b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f64_isSignalingNaN( a ) || f64_isSignalingNaN( b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f64( a, b, "  " );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef EXTFLOAT80
+
+void
+ ver_a_extF80_z_ui32_rx(
+     uint_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_ui64_rx(
+     uint_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_i32_rx(
+     int_fast32_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! extF80M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_i64_rx(
+     int_fast64_t trueFunction( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! extF80M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_ui32_x(
+     uint_fast32_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int count;
+    extFloat80_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_ui64_x(
+     uint_fast64_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int count;
+    extFloat80_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_i32_x(
+     int_fast32_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int count;
+    extFloat80_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! extF80M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_extF80_z_i64_x(
+     int_fast64_t trueFunction( const extFloat80_t *, bool ), bool exact )
+{
+    int count;
+    extFloat80_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! extF80M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT16
+
+void ver_a_extF80_z_f16( float16_t trueFunction( const extFloat80_t * ) )
+{
+    int count;
+    extFloat80_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_extF80_z_f32( float32_t trueFunction( const extFloat80_t * ) )
+{
+    int count;
+    extFloat80_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_extF80_z_f64( float64_t trueFunction( const extFloat80_t * ) )
+{
+    int count;
+    extFloat80_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void
+ ver_a_extF80_z_f128( void trueFunction( const extFloat80_t *, float128_t * ) )
+{
+    int count;
+    extFloat80_t a;
+    float128_t subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_az_extF80( void trueFunction( const extFloat80_t *, extFloat80_t * ) )
+{
+    int count;
+    extFloat80_t a, subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_az_extF80_rx(
+     void
+      trueFunction( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    extFloat80_t a, subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, roundingMode, exact, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && extF80M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_extF80M( &a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_abz_extF80(
+     void
+      trueFunction(
+          const extFloat80_t *, const extFloat80_t *, extFloat80_t * )
+ )
+{
+    int count;
+    extFloat80_t a, b, subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_extF80( &b );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &b, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (extF80M_isSignalingNaN( &a )
+                            || extF80M_isSignalingNaN( &b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_extF80M( &a, &b, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_ab_extF80_z_bool(
+     bool trueFunction( const extFloat80_t *, const extFloat80_t * ) )
+{
+    int count;
+    extFloat80_t a, b;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_extF80( &a );
+        readVerInput_extF80( &b );
+        readVerInput_bool( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, &b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (extF80M_isSignalingNaN( &a )
+                            || extF80M_isSignalingNaN( &b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_extF80M( &a, &b, "  " );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+
+#ifdef FLOAT128
+
+void
+ ver_a_f128_z_ui32_rx(
+     uint_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_ui64_rx(
+     uint_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_i32_rx(
+     int_fast32_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f128M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_i64_rx(
+     int_fast64_t trueFunction( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, roundingMode, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f128M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_ui32_x(
+     uint_fast32_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int count;
+    float128_t a;
+    uint_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_ui32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0xFFFFFFFF) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_ui32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_ui64_x(
+     uint_fast64_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int count;
+    float128_t a;
+    uint_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    uint_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_ui64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != UINT64_C( 0xFFFFFFFFFFFFFFFF )) && (subjZ != 0))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_ui64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_i32_x(
+     int_fast32_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int count;
+    float128_t a;
+    int_fast32_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_i32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != 0x7FFFFFFF) && (subjZ != -0x7FFFFFFF - 1)
+                        && (! f128M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_i32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_a_f128_z_i64_x(
+     int_fast64_t trueFunction( const float128_t *, bool ), bool exact )
+{
+    int count;
+    float128_t a;
+    int_fast64_t subjZ;
+    uint_fast8_t subjFlags;
+    int_fast64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_i64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, exact );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                   verCases_checkInvInts
+                || (trueFlags != softfloat_flag_invalid)
+                || (subjFlags != softfloat_flag_invalid)
+                || ((subjZ != INT64_C( 0x7FFFFFFFFFFFFFFF ))
+                        && (subjZ != -INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1)
+                        && (! f128M_isNaN( &a ) || (subjZ != 0)))
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_i64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT16
+
+void ver_a_f128_z_f16( float16_t trueFunction( const float128_t * ) )
+{
+    int count;
+    float128_t a;
+    float16_t subjZ;
+    uint_fast8_t subjFlags;
+    float16_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f16( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f16_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f16_isNaN( trueZ )
+                || ! f16_isNaN( subjZ )
+                || f16_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_f16( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_a_f128_z_f32( float32_t trueFunction( const float128_t * ) )
+{
+    int count;
+    float128_t a;
+    float32_t subjZ;
+    uint_fast8_t subjFlags;
+    float32_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f32( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f32_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f32_isNaN( trueZ )
+                || ! f32_isNaN( subjZ )
+                || f32_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_f32( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#ifdef FLOAT64
+
+void ver_a_f128_z_f64( float64_t trueFunction( const float128_t * ) )
+{
+    int count;
+    float128_t a;
+    float64_t subjZ;
+    uint_fast8_t subjFlags;
+    float64_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f64( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f64_same( trueZ, subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f64_isNaN( trueZ )
+                || ! f64_isNaN( subjZ )
+                || f64_isSignalingNaN( subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_f64( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void
+ ver_a_f128_z_extF80( void trueFunction( const float128_t *, extFloat80_t * ) )
+{
+    int count;
+    float128_t a;
+    extFloat80_t subjZ;
+    uint_fast8_t subjFlags;
+    extFloat80_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_extF80( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! extF80M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! extF80M_isNaN( &trueZ )
+                || ! extF80M_isNaN( &subjZ )
+                || extF80M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "\n\t" );
+                writeCase_z_extF80M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
+void ver_az_f128( void trueFunction( const float128_t *, float128_t * ) )
+{
+    int count;
+    float128_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_az_f128_rx(
+     void trueFunction( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t roundingMode,
+     bool exact
+ )
+{
+    int count;
+    float128_t a, subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, roundingMode, exact, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if ( ! verCases_checkNaNs && f128M_isSignalingNaN( &a ) ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_a_f128M( &a, "  " );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_abz_f128(
+     void trueFunction( const float128_t *, const float128_t *, float128_t * )
+ )
+{
+    int count;
+    float128_t a, b, subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f128( &b );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &b, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f128M_isSignalingNaN( &a )
+                            || f128M_isSignalingNaN( &b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f128M( &a, &b );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_abcz_f128(
+     void
+      trueFunction(
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ )
+{
+    int count;
+    float128_t a, b, c, subjZ;
+    uint_fast8_t subjFlags;
+    float128_t trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f128( &b );
+        readVerInput_f128( &c );
+        readVerInput_f128( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueFunction( &a, &b, &c, &trueZ );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( ! f128M_same( &trueZ, &subjZ ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (   f128M_isSignalingNaN( &a )
+                        || f128M_isSignalingNaN( &b )
+                        || f128M_isSignalingNaN( &c )
+                       )
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if (
+                   verCases_checkNaNs
+                || ! f128M_isNaN( &trueZ )
+                || ! f128M_isNaN( &subjZ )
+                || f128M_isSignalingNaN( &subjZ )
+                || (trueFlags != subjFlags)
+            ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_abc_f128M( &a, &b, &c );
+                writeCase_z_f128M( &trueZ, trueFlags, &subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+void
+ ver_ab_f128_z_bool(
+     bool trueFunction( const float128_t *, const float128_t * ) )
+{
+    int count;
+    float128_t a, b;
+    bool subjZ;
+    uint_fast8_t subjFlags;
+    bool trueZ;
+    uint_fast8_t trueFlags;
+
+    verCases_errorCount = 0;
+    verCases_tenThousandsCount = 0;
+    count = 10000;
+    while ( ! atEndOfInput() ) {
+        readVerInput_f128( &a );
+        readVerInput_f128( &b );
+        readVerInput_bool( &subjZ );
+        readVerInput_flags( &subjFlags );
+        *verLoops_trueFlagsPtr = 0;
+        trueZ = trueFunction( &a, &b );
+        trueFlags = *verLoops_trueFlagsPtr;
+        --count;
+        if ( ! count ) {
+            verCases_perTenThousand();
+            count = 10000;
+        }
+        if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+            if (
+                ! verCases_checkNaNs
+                    && (f128M_isSignalingNaN( &a )
+                            || f128M_isSignalingNaN( &b ))
+            ) {
+                trueFlags |= softfloat_flag_invalid;
+            }
+            if ( (trueZ != subjZ) || (trueFlags != subjFlags) ) {
+                ++verCases_errorCount;
+                verCases_writeErrorFound( 10000 - count );
+                writeCase_ab_f128M( &a, &b );
+                writeCase_z_bool( trueZ, trueFlags, subjZ, subjFlags );
+                if ( verCases_errorCount == verCases_maxErrorCount ) break;
+            }
+        }
+    }
+    verCases_writeTestsPerformed( 10000 - count );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/verLoops.h b/addins/TestFloat-3e/source/verLoops.h
new file mode 100644
index 000000000..e02457a42
--- /dev/null
+++ b/addins/TestFloat-3e/source/verLoops.h
@@ -0,0 +1,320 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+extern uint_fast8_t *verLoops_trueFlagsPtr;
+
+#ifdef FLOAT16
+void ver_a_ui32_z_f16( float16_t ( uint32_t ) );
+#endif
+void ver_a_ui32_z_f32( float32_t ( uint32_t ) );
+#ifdef FLOAT64
+void ver_a_ui32_z_f64( float64_t ( uint32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_ui32_z_extF80( void ( uint32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_ui32_z_f128( void ( uint32_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void ver_a_ui64_z_f16( float16_t ( uint64_t ) );
+#endif
+void ver_a_ui64_z_f32( float32_t ( uint64_t ) );
+#ifdef FLOAT64
+void ver_a_ui64_z_f64( float64_t ( uint64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_ui64_z_extF80( void ( uint64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_ui64_z_f128( void ( uint64_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void ver_a_i32_z_f16( float16_t ( int32_t ) );
+#endif
+void ver_a_i32_z_f32( float32_t ( int32_t ) );
+#ifdef FLOAT64
+void ver_a_i32_z_f64( float64_t ( int32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_i32_z_extF80( void ( int32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_i32_z_f128( void ( int32_t, float128_t * ) );
+#endif
+#ifdef FLOAT16
+void ver_a_i64_z_f16( float16_t ( int64_t ) );
+#endif
+void ver_a_i64_z_f32( float32_t ( int64_t ) );
+#ifdef FLOAT64
+void ver_a_i64_z_f64( float64_t ( int64_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_i64_z_extF80( void ( int64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_i64_z_f128( void ( int64_t, float128_t * ) );
+#endif
+
+#ifdef FLOAT16
+void
+ ver_a_f16_z_ui32_rx(
+     uint_fast32_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f16_z_ui64_rx(
+     uint_fast64_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f16_z_i32_rx(
+     int_fast32_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f16_z_i64_rx(
+     int_fast64_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_a_f16_z_ui32_x( uint_fast32_t ( float16_t, bool ), bool );
+void ver_a_f16_z_ui64_x( uint_fast64_t ( float16_t, bool ), bool );
+void ver_a_f16_z_i32_x( int_fast32_t ( float16_t, bool ), bool );
+void ver_a_f16_z_i64_x( int_fast64_t ( float16_t, bool ), bool );
+void ver_a_f16_z_f32( float32_t ( float16_t ) );
+#ifdef FLOAT64
+void ver_a_f16_z_f64( float64_t ( float16_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_f16_z_extF80( void ( float16_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_f16_z_f128( void ( float16_t, float128_t * ) );
+#endif
+void ver_az_f16( float16_t ( float16_t ) );
+void
+ ver_az_f16_rx(
+     float16_t ( float16_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_abz_f16( float16_t ( float16_t, float16_t ) );
+void ver_abcz_f16( float16_t ( float16_t, float16_t, float16_t ) );
+void ver_ab_f16_z_bool( bool ( float16_t, float16_t ) );
+#endif
+
+void
+ ver_a_f32_z_ui32_rx(
+     uint_fast32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f32_z_ui64_rx(
+     uint_fast64_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f32_z_i32_rx(
+     int_fast32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f32_z_i64_rx(
+     int_fast64_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_a_f32_z_ui32_x( uint_fast32_t ( float32_t, bool ), bool );
+void ver_a_f32_z_ui64_x( uint_fast64_t ( float32_t, bool ), bool );
+void ver_a_f32_z_i32_x( int_fast32_t ( float32_t, bool ), bool );
+void ver_a_f32_z_i64_x( int_fast64_t ( float32_t, bool ), bool );
+#ifdef FLOAT16
+void ver_a_f32_z_f16( float16_t ( float32_t ) );
+#endif
+#ifdef FLOAT64
+void ver_a_f32_z_f64( float64_t ( float32_t ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_f32_z_extF80( void ( float32_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_f32_z_f128( void ( float32_t, float128_t * ) );
+#endif
+void ver_az_f32( float32_t ( float32_t ) );
+void
+ ver_az_f32_rx(
+     float32_t ( float32_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_abz_f32( float32_t ( float32_t, float32_t ) );
+void ver_abcz_f32( float32_t ( float32_t, float32_t, float32_t ) );
+void ver_ab_f32_z_bool( bool ( float32_t, float32_t ) );
+
+#ifdef FLOAT64
+void
+ ver_a_f64_z_ui32_rx(
+     uint_fast32_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f64_z_ui64_rx(
+     uint_fast64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f64_z_i32_rx(
+     int_fast32_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void
+ ver_a_f64_z_i64_rx(
+     int_fast64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_a_f64_z_ui32_x( uint_fast32_t ( float64_t, bool ), bool );
+void ver_a_f64_z_ui64_x( uint_fast64_t ( float64_t, bool ), bool );
+void ver_a_f64_z_i32_x( int_fast32_t ( float64_t, bool ), bool );
+void ver_a_f64_z_i64_x( int_fast64_t ( float64_t, bool ), bool );
+#ifdef FLOAT16
+void ver_a_f64_z_f16( float16_t ( float64_t ) );
+#endif
+void ver_a_f64_z_f32( float32_t ( float64_t ) );
+#ifdef EXTFLOAT80
+void ver_a_f64_z_extF80( void ( float64_t, extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_f64_z_f128( void ( float64_t, float128_t * ) );
+#endif
+void ver_az_f64( float64_t ( float64_t ) );
+void
+ ver_az_f64_rx(
+     float64_t ( float64_t, uint_fast8_t, bool ), uint_fast8_t, bool );
+void ver_abz_f64( float64_t ( float64_t, float64_t ) );
+void ver_abcz_f64( float64_t ( float64_t, float64_t, float64_t ) );
+void ver_ab_f64_z_bool( bool ( float64_t, float64_t ) );
+#endif
+
+#ifdef EXTFLOAT80
+void
+ ver_a_extF80_z_ui32_rx(
+     uint_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_extF80_z_ui64_rx(
+     uint_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_extF80_z_i32_rx(
+     int_fast32_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_extF80_z_i64_rx(
+     int_fast64_t ( const extFloat80_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_extF80_z_ui32_x( uint_fast32_t ( const extFloat80_t *, bool ), bool );
+void
+ ver_a_extF80_z_ui64_x( uint_fast64_t ( const extFloat80_t *, bool ), bool );
+void ver_a_extF80_z_i32_x( int_fast32_t ( const extFloat80_t *, bool ), bool );
+void ver_a_extF80_z_i64_x( int_fast64_t ( const extFloat80_t *, bool ), bool );
+#ifdef FLOAT16
+void ver_a_extF80_z_f16( float16_t ( const extFloat80_t * ) );
+#endif
+void ver_a_extF80_z_f32( float32_t ( const extFloat80_t * ) );
+#ifdef FLOAT64
+void ver_a_extF80_z_f64( float64_t ( const extFloat80_t * ) );
+#endif
+#ifdef FLOAT128
+void ver_a_extF80_z_f128( void ( const extFloat80_t *, float128_t * ) );
+#endif
+void ver_az_extF80( void ( const extFloat80_t *, extFloat80_t * ) );
+void
+ ver_az_extF80_rx(
+     void ( const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_abz_extF80(
+     void ( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ) );
+void
+ ver_ab_extF80_z_bool( bool ( const extFloat80_t *, const extFloat80_t * ) );
+#endif
+
+#ifdef FLOAT128
+void
+ ver_a_f128_z_ui32_rx(
+     uint_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_f128_z_ui64_rx(
+     uint_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_f128_z_i32_rx(
+     int_fast32_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_a_f128_z_i64_rx(
+     int_fast64_t ( const float128_t *, uint_fast8_t, bool ),
+     uint_fast8_t,
+     bool
+ );
+void ver_a_f128_z_ui32_x( uint_fast32_t ( const float128_t *, bool ), bool );
+void ver_a_f128_z_ui64_x( uint_fast64_t ( const float128_t *, bool ), bool );
+void ver_a_f128_z_i32_x( int_fast32_t ( const float128_t *, bool ), bool );
+void ver_a_f128_z_i64_x( int_fast64_t ( const float128_t *, bool ), bool );
+#ifdef FLOAT16
+void ver_a_f128_z_f16( float16_t ( const float128_t * ) );
+#endif
+void ver_a_f128_z_f32( float32_t ( const float128_t * ) );
+#ifdef FLOAT64
+void ver_a_f128_z_f64( float64_t ( const float128_t * ) );
+#endif
+#ifdef EXTFLOAT80
+void ver_a_f128_z_extF80( void ( const float128_t *, extFloat80_t * ) );
+#endif
+void ver_az_f128( void ( const float128_t *, float128_t * ) );
+void
+ ver_az_f128_rx(
+     void ( const float128_t *, uint_fast8_t, bool, float128_t * ),
+     uint_fast8_t,
+     bool
+ );
+void
+ ver_abz_f128( void ( const float128_t *, const float128_t *, float128_t * ) );
+void
+ ver_abcz_f128(
+     void
+      (
+          const float128_t *,
+          const float128_t *,
+          const float128_t *,
+          float128_t *
+      )
+ );
+void ver_ab_f128_z_bool( bool ( const float128_t *, const float128_t * ) );
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase.h b/addins/TestFloat-3e/source/writeCase.h
new file mode 100644
index 000000000..8dc834e05
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase.h
@@ -0,0 +1,97 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+void writeCase_a_ui32( uint_fast32_t, const char * );
+void writeCase_a_ui64( uint_fast64_t, const char * );
+#define writeCase_a_i32 writeCase_a_ui32
+#define writeCase_a_i64 writeCase_a_ui64
+#ifdef FLOAT16
+void writeCase_a_f16( float16_t );
+void writeCase_ab_f16( float16_t, float16_t );
+void writeCase_abc_f16( float16_t, float16_t, float16_t );
+#endif
+void writeCase_a_f32( float32_t, const char * );
+void writeCase_ab_f32( float32_t, float32_t );
+void writeCase_abc_f32( float32_t, float32_t, float32_t );
+#ifdef FLOAT64
+void writeCase_a_f64( float64_t, const char * );
+void writeCase_ab_f64( float64_t, float64_t, const char * );
+void writeCase_abc_f64( float64_t, float64_t, float64_t );
+#endif
+#ifdef EXTFLOAT80
+void writeCase_a_extF80M( const extFloat80_t *, const char * );
+void
+ writeCase_ab_extF80M(
+     const extFloat80_t *, const extFloat80_t *, const char * );
+#endif
+#ifdef FLOAT128
+void writeCase_a_f128M( const float128_t *, const char * );
+void writeCase_ab_f128M( const float128_t *, const float128_t * );
+void
+ writeCase_abc_f128M(
+     const float128_t *, const float128_t *, const float128_t * );
+#endif
+
+void writeCase_z_bool( bool, uint_fast8_t, bool, uint_fast8_t );
+void
+ writeCase_z_ui32( uint_fast32_t, uint_fast8_t, uint_fast32_t, uint_fast8_t );
+void
+ writeCase_z_ui64( uint_fast64_t, uint_fast8_t, uint_fast64_t, uint_fast8_t );
+#define writeCase_z_i32 writeCase_z_ui32
+#define writeCase_z_i64 writeCase_z_ui64
+#ifdef FLOAT16
+void writeCase_z_f16( float16_t, uint_fast8_t, float16_t, uint_fast8_t );
+#endif
+void writeCase_z_f32( float32_t, uint_fast8_t, float32_t, uint_fast8_t );
+#ifdef FLOAT64
+void writeCase_z_f64( float64_t, uint_fast8_t, float64_t, uint_fast8_t );
+#endif
+#ifdef EXTFLOAT80
+void
+ writeCase_z_extF80M(
+     const extFloat80_t *, uint_fast8_t, const extFloat80_t *, uint_fast8_t );
+#endif
+#ifdef FLOAT128
+void
+ writeCase_z_f128M(
+     const float128_t *, uint_fast8_t, const float128_t *, uint_fast8_t );
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_extF80M.c b/addins/TestFloat-3e/source/writeCase_a_extF80M.c
new file mode 100644
index 000000000..7b7f09811
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_extF80M.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef EXTFLOAT80
+
+void writeCase_a_extF80M( const extFloat80_t *aPtr, const char *sepStringPtr )
+{
+
+    writeHex_extF80M( aPtr, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_f128M.c b/addins/TestFloat-3e/source/writeCase_a_f128M.c
new file mode 100644
index 000000000..fafe7d255
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_f128M.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT128
+
+void writeCase_a_f128M( const float128_t *aPtr, const char *sepStringPtr )
+{
+
+    writeHex_f128M( aPtr, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_f16.c b/addins/TestFloat-3e/source/writeCase_a_f16.c
new file mode 100644
index 000000000..27e1786f7
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_f16.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT16
+
+void writeCase_a_f16( float16_t a )
+{
+
+    writeHex_f16( a, 0 );
+    fputs( "  ", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_f32.c b/addins/TestFloat-3e/source/writeCase_a_f32.c
new file mode 100644
index 000000000..0dc45b5bb
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_f32.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void writeCase_a_f32( float32_t a, const char *sepStringPtr )
+{
+
+    writeHex_f32( a, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_f64.c b/addins/TestFloat-3e/source/writeCase_a_f64.c
new file mode 100644
index 000000000..d8e71d688
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_f64.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT64
+
+void writeCase_a_f64( float64_t a, const char *sepStringPtr )
+{
+
+    writeHex_f64( a, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_ui32.c b/addins/TestFloat-3e/source/writeCase_a_ui32.c
new file mode 100644
index 000000000..22abfa7a5
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_ui32.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void writeCase_a_ui32( uint_fast32_t a, const char *sepStringPtr )
+{
+
+    writeHex_ui32( a, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_a_ui64.c b/addins/TestFloat-3e/source/writeCase_a_ui64.c
new file mode 100644
index 000000000..f67e5e6f9
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_a_ui64.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void writeCase_a_ui64( uint_fast64_t a, const char *sepStringPtr )
+{
+
+    writeHex_ui64( a, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_ab_extF80M.c b/addins/TestFloat-3e/source/writeCase_ab_extF80M.c
new file mode 100644
index 000000000..bf2d7a65f
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_ab_extF80M.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef EXTFLOAT80
+
+void
+ writeCase_ab_extF80M(
+     const extFloat80_t *aPtr,
+     const extFloat80_t *bPtr,
+     const char *sepStringPtr
+ )
+{
+
+    writeHex_extF80M( aPtr, 0 );
+    fputs( "  ", stdout );
+    writeHex_extF80M( bPtr, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_ab_f128M.c b/addins/TestFloat-3e/source/writeCase_ab_f128M.c
new file mode 100644
index 000000000..ffd905078
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_ab_f128M.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT128
+
+void writeCase_ab_f128M( const float128_t *aPtr, const float128_t *bPtr )
+{
+
+    writeHex_f128M( aPtr, 0 );
+    fputs( "  ", stdout );
+    writeHex_f128M( bPtr, 0 );
+    fputs( "\n\t", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_ab_f16.c b/addins/TestFloat-3e/source/writeCase_ab_f16.c
new file mode 100644
index 000000000..37df821be
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_ab_f16.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT16
+
+void writeCase_ab_f16( float16_t a, float16_t b )
+{
+
+    writeHex_f16( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f16( b, 0 );
+    fputs( "  ", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_ab_f32.c b/addins/TestFloat-3e/source/writeCase_ab_f32.c
new file mode 100644
index 000000000..16be4779d
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_ab_f32.c
@@ -0,0 +1,53 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void writeCase_ab_f32( float32_t a, float32_t b )
+{
+
+    writeHex_f32( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f32( b, 0 );
+    fputs( "  ", stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_ab_f64.c b/addins/TestFloat-3e/source/writeCase_ab_f64.c
new file mode 100644
index 000000000..2480416ff
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_ab_f64.c
@@ -0,0 +1,57 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT64
+
+void writeCase_ab_f64( float64_t a, float64_t b, const char *sepStringPtr )
+{
+
+    writeHex_f64( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f64( b, 0 );
+    fputs( sepStringPtr, stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_abc_f128M.c b/addins/TestFloat-3e/source/writeCase_abc_f128M.c
new file mode 100644
index 000000000..99b91d83b
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_abc_f128M.c
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT128
+
+void
+ writeCase_abc_f128M(
+     const float128_t *aPtr, const float128_t *bPtr, const float128_t *cPtr )
+{
+
+    writeHex_f128M( aPtr, 0 );
+    fputs( "  ", stdout );
+    writeHex_f128M( bPtr, 0 );
+    fputs( "\n\t", stdout );
+    writeHex_f128M( cPtr, 0 );
+    fputs( "\n\t", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_abc_f16.c b/addins/TestFloat-3e/source/writeCase_abc_f16.c
new file mode 100644
index 000000000..2f9a0c9c2
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_abc_f16.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT16
+
+void writeCase_abc_f16( float16_t a, float16_t b, float16_t c )
+{
+
+    writeHex_f16( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f16( b, 0 );
+    fputs( "  ", stdout );
+    writeHex_f16( c, 0 );
+    fputs( "  ", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_abc_f32.c b/addins/TestFloat-3e/source/writeCase_abc_f32.c
new file mode 100644
index 000000000..c7953b33d
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_abc_f32.c
@@ -0,0 +1,55 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void writeCase_abc_f32( float32_t a, float32_t b, float32_t c )
+{
+
+    writeHex_f32( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f32( b, 0 );
+    fputs( "  ", stdout );
+    writeHex_f32( c, 0 );
+    fputs( "\n\t", stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_abc_f64.c b/addins/TestFloat-3e/source/writeCase_abc_f64.c
new file mode 100644
index 000000000..778f9a229
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_abc_f64.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT64
+
+void writeCase_abc_f64( float64_t a, float64_t b, float64_t c )
+{
+
+    writeHex_f64( a, 0 );
+    fputs( "  ", stdout );
+    writeHex_f64( b, 0 );
+    fputs( "  ", stdout );
+    writeHex_f64( c, 0 );
+    fputs( "\n\t", stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_bool.c b/addins/TestFloat-3e/source/writeCase_z_bool.c
new file mode 100644
index 000000000..0deecc275
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_bool.c
@@ -0,0 +1,59 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void
+ writeCase_z_bool(
+     bool trueZ, uint_fast8_t trueFlags, bool subjZ, uint_fast8_t subjFlags )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_bool( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_bool( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_extF80M.c b/addins/TestFloat-3e/source/writeCase_z_extF80M.c
new file mode 100644
index 000000000..cc07766b8
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_extF80M.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef EXTFLOAT80
+
+void
+ writeCase_z_extF80M(
+     const extFloat80_t *trueZPtr,
+     uint_fast8_t trueFlags,
+     const extFloat80_t *subjZPtr,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_extF80M( subjZPtr, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_extF80M( trueZPtr, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_f128M.c b/addins/TestFloat-3e/source/writeCase_z_f128M.c
new file mode 100644
index 000000000..2f7f566b6
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_f128M.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT128
+
+void
+ writeCase_z_f128M(
+     const float128_t *trueZPtr,
+     uint_fast8_t trueFlags,
+     const float128_t *subjZPtr,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_f128M( subjZPtr, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "\n\texpected ", stdout );
+    writeHex_f128M( trueZPtr, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_f16.c b/addins/TestFloat-3e/source/writeCase_z_f16.c
new file mode 100644
index 000000000..42dc49e68
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_f16.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT16
+
+void
+ writeCase_z_f16(
+     float16_t trueZ,
+     uint_fast8_t trueFlags,
+     float16_t subjZ,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_f16( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_f16( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_f32.c b/addins/TestFloat-3e/source/writeCase_z_f32.c
new file mode 100644
index 000000000..fea40e43f
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_f32.c
@@ -0,0 +1,63 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void
+ writeCase_z_f32(
+     float32_t trueZ,
+     uint_fast8_t trueFlags,
+     float32_t subjZ,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_f32( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_f32( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_f64.c b/addins/TestFloat-3e/source/writeCase_z_f64.c
new file mode 100644
index 000000000..f84f60565
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_f64.c
@@ -0,0 +1,67 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "softfloat.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+#ifdef FLOAT64
+
+void
+ writeCase_z_f64(
+     float64_t trueZ,
+     uint_fast8_t trueFlags,
+     float64_t subjZ,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_f64( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_f64( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
+#endif
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_ui32.c b/addins/TestFloat-3e/source/writeCase_z_ui32.c
new file mode 100644
index 000000000..a287032f2
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_ui32.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void
+ writeCase_z_ui32(
+     uint_fast32_t trueZ,
+     uint_fast8_t trueFlags,
+     uint_fast32_t subjZ,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_ui32( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_ui32( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeCase_z_ui64.c b/addins/TestFloat-3e/source/writeCase_z_ui64.c
new file mode 100644
index 000000000..e5e99ab4d
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeCase_z_ui64.c
@@ -0,0 +1,62 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014 The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "writeHex.h"
+#include "writeCase.h"
+
+void
+ writeCase_z_ui64(
+     uint_fast64_t trueZ,
+     uint_fast8_t trueFlags,
+     uint_fast64_t subjZ,
+     uint_fast8_t subjFlags
+ )
+{
+
+    fputs( "=> ", stdout );
+    writeHex_ui64( subjZ, ' ' );
+    writeHex_softfloat_flags( subjFlags, 0 );
+    fputs( "  expected ", stdout );
+    writeHex_ui64( trueZ, ' ' );
+    writeHex_softfloat_flags( trueFlags, '\n' );
+    fflush( stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeHex.c b/addins/TestFloat-3e/source/writeHex.c
new file mode 100644
index 000000000..bb642dff1
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeHex.c
@@ -0,0 +1,224 @@
+
+/*============================================================================
+
+This C source file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
+University of California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "platform.h"
+#include "uint128.h"
+#include "softfloat.h"
+#include "writeHex.h"
+
+void writeHex_bool( bool a, char sepChar )
+{
+
+    fputc( a ? '1' : '0', stdout );
+    if ( sepChar ) fputc( sepChar, stdout );
+
+}
+
+void writeHex_ui8( uint_fast8_t a, char sepChar )
+{
+    int digit;
+
+    digit = a>>4 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    if ( sepChar ) fputc( sepChar, stdout );
+
+}
+
+static void writeHex_ui12( uint_fast16_t a, char sepChar )
+{
+    int digit;
+
+    digit = a>>8 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a>>4 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    if ( sepChar ) fputc( sepChar, stdout );
+
+}
+
+void writeHex_ui16( uint_fast16_t a, char sepChar )
+{
+    int digit;
+
+    digit = a>>12 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a>>8 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a>>4 & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    digit = a & 0xF;
+    if ( 9 < digit ) digit += 'A' - ('0' + 10);
+    fputc( '0' + digit, stdout );
+    if ( sepChar ) fputc( sepChar, stdout );
+
+}
+
+void writeHex_ui32( uint_fast32_t a, char sepChar )
+{
+
+    writeHex_ui16( a>>16, 0 );
+    writeHex_ui16( a, sepChar );
+
+}
+
+void writeHex_ui64( uint_fast64_t a, char sepChar )
+{
+
+    writeHex_ui32( a>>32, 0 );
+    writeHex_ui32( a, sepChar );
+
+}
+
+#ifdef FLOAT16
+
+void writeHex_f16( float16_t a, char sepChar )
+{
+    union { uint16_t ui; float16_t f; } uA;
+    uint_fast16_t uiA;
+
+    uA.f = a;
+    uiA = uA.ui;
+    fputc( uiA & 0x8000 ? '-' : '+', stdout );
+    writeHex_ui8( uiA>>10 & 0x1F, 0 );
+    fputc( '.', stdout );
+    fputc( '0' + (uiA>>8 & 3), stdout );
+    writeHex_ui8( uiA, sepChar );
+
+}
+
+#endif
+
+void writeHex_f32( float32_t a, char sepChar )
+{
+    union { uint32_t ui; float32_t f; } uA;
+    uint_fast32_t uiA;
+
+    uA.f = a;
+    uiA = uA.ui;
+    fputc( uiA & 0x80000000 ? '-' : '+', stdout );
+    writeHex_ui8( uiA>>23, 0 );
+    fputc( '.', stdout );
+    writeHex_ui8( uiA>>16 & 0x7F, 0 );
+    writeHex_ui16( uiA, sepChar );
+
+}
+
+#ifdef FLOAT64
+
+void writeHex_f64( float64_t a, char sepChar )
+{
+    union { uint64_t ui; float64_t f; } uA;
+    uint_fast64_t uiA;
+
+    uA.f = a;
+    uiA = uA.ui;
+    fputc( uiA & UINT64_C( 0x8000000000000000 ) ? '-' : '+', stdout );
+    writeHex_ui12( uiA>>52 & 0x7FF, 0 );
+    fputc( '.', stdout );
+    writeHex_ui12( uiA>>40, 0 );
+    writeHex_ui8( uiA>>32, 0 );
+    writeHex_ui32( uiA, sepChar );
+
+}
+
+#endif
+
+#ifdef EXTFLOAT80
+
+void writeHex_extF80M( const extFloat80_t *aPtr, char sepChar )
+{
+    const struct extFloat80M *aSPtr;
+    uint_fast16_t uiA64;
+
+    aSPtr = (const struct extFloat80M *) aPtr;
+    uiA64 = aSPtr->signExp;
+    fputc( uiA64 & 0x8000 ? '-' : '+', stdout );
+    writeHex_ui16( uiA64 & 0x7FFF, 0 );
+    fputc( '.', stdout );
+    writeHex_ui64( aSPtr->signif, sepChar );
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+void writeHex_f128M( const float128_t *aPtr, char sepChar )
+{
+    const struct uint128 *uiAPtr;
+    uint_fast64_t uiA64;
+
+    uiAPtr = (const struct uint128 *) aPtr;
+    uiA64 = uiAPtr->v64;
+    fputc( uiA64 & UINT64_C( 0x8000000000000000 ) ? '-' : '+', stdout );
+    writeHex_ui16( uiA64>>48 & 0x7FFF, 0 );
+    fputc( '.', stdout );
+    writeHex_ui16( uiA64>>32, 0 );
+    writeHex_ui32( uiA64, 0 );
+    writeHex_ui64( uiAPtr->v0, sepChar );
+
+}
+
+#endif
+
+void writeHex_softfloat_flags( uint_fast8_t flags, char sepChar )
+{
+
+    fputc( flags & softfloat_flag_invalid   ? 'v' : '.', stdout );
+    fputc( flags & softfloat_flag_infinite  ? 'i' : '.', stdout );
+    fputc( flags & softfloat_flag_overflow  ? 'o' : '.', stdout );
+    fputc( flags & softfloat_flag_underflow ? 'u' : '.', stdout );
+    fputc( flags & softfloat_flag_inexact   ? 'x' : '.', stdout );
+    if ( sepChar ) fputc( sepChar, stdout );
+
+}
+
diff --git a/addins/TestFloat-3e/source/writeHex.h b/addins/TestFloat-3e/source/writeHex.h
new file mode 100644
index 000000000..bfc55cec2
--- /dev/null
+++ b/addins/TestFloat-3e/source/writeHex.h
@@ -0,0 +1,61 @@
+
+/*============================================================================
+
+This C header file is part of TestFloat, Release 3e, a package of programs for
+testing the correctness of floating-point arithmetic complying with the IEEE
+Standard for Floating-Point, by John R. Hauser.
+
+Copyright 2011, 2012, 2013, 2014, 2015, 2017 The Regents of the University of
+California.  All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+    this list of conditions, and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions, and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+
+ 3. Neither the name of the University nor the names of its contributors may
+    be used to endorse or promote products derived from this software without
+    specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
+DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "softfloat.h"
+
+void writeHex_bool( bool, char );
+void writeHex_ui8( uint_fast8_t, char );
+void writeHex_ui16( uint_fast16_t, char );
+void writeHex_ui32( uint_fast32_t, char );
+void writeHex_ui64( uint_fast64_t, char );
+#ifdef FLOAT16
+void writeHex_f16( float16_t, char );
+#endif
+void writeHex_f32( float32_t, char );
+#ifdef FLOAT64
+void writeHex_f64( float64_t, char );
+#endif
+#ifdef EXTFLOAT80
+void writeHex_extF80M( const extFloat80_t *, char );
+#endif
+#ifdef FLOAT128
+void writeHex_f128M( const float128_t *, char );
+#endif
+void writeHex_softfloat_flags( uint_fast8_t, char );
+
diff --git a/addins/berkeley-softfloat-3 b/addins/berkeley-softfloat-3
deleted file mode 160000
index a0c6494cd..000000000
--- a/addins/berkeley-softfloat-3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a0c6494cdc11865811dec815d5c0049fba9d82a8
diff --git a/addins/berkeley-testfloat-3 b/addins/berkeley-testfloat-3
deleted file mode 160000
index a9c849f1b..000000000
--- a/addins/berkeley-testfloat-3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a9c849f1b0eb0264b626d9686ffae167d996e3be
diff --git a/addins/branch-predictor-simulator b/addins/branch-predictor-simulator
deleted file mode 160000
index 3e424e902..000000000
--- a/addins/branch-predictor-simulator
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 3e424e902f2088d0c9f482f3900ab780affb6350
diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif
deleted file mode 160000
index ce1b9c0f5..000000000
--- a/addins/cvw-arch-verif
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ce1b9c0f5b2a049182cf08531d7876b0f1c7bfae
diff --git a/addins/embench-iot b/addins/embench-iot
index 54fd9a0f1..1480febc3 160000
--- a/addins/embench-iot
+++ b/addins/embench-iot
@@ -1 +1 @@
-Subproject commit 54fd9a0f10aabc662991567ca19ff3e61bfd3939
+Subproject commit 1480febc3ace5f471baeee4b1ae0d8fea16e4762
diff --git a/addins/imperas-riscv-tests b/addins/imperas-riscv-tests
new file mode 120000
index 000000000..c3f365a40
--- /dev/null
+++ b/addins/imperas-riscv-tests
@@ -0,0 +1 @@
+/opt/riscv/imperas-riscv-tests/
\ No newline at end of file
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 3aa9b50e6..ee028eb32 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 3aa9b50e68c064b2e893c3dda283aa99505ae622
+Subproject commit ee028eb325525148a34420a4ca7959b24220a91e
diff --git a/addins/riscv-dv b/addins/riscv-dv
index f0c570d11..a7e27bc04 160000
--- a/addins/riscv-dv
+++ b/addins/riscv-dv
@@ -1 +1 @@
-Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
+Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
diff --git a/addins/riscv-tests b/addins/riscv-tests
new file mode 160000
index 000000000..cf04274f5
--- /dev/null
+++ b/addins/riscv-tests
@@ -0,0 +1 @@
+Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7
diff --git a/addins/sparse-checkout b/addins/sparse-checkout
deleted file mode 100644
index 74cc3f25a..000000000
--- a/addins/sparse-checkout
+++ /dev/null
@@ -1,17 +0,0 @@
-rtl/eth_mac_mii_fifo.sv
-rtl/eth_mac_mii.sv
-rtl/mii_phy_if.sv
-rtl/ssio_ddr_in.sv
-rtl/ssio_sdr_in.sv
-rtl/eth_mac_1g.sv
-rtl/axis_gmii_rx.sv
-rtl/lfsr.sv
-rtl/eth_axis_tx.sv
-rtl/mac_ctrl_tx.sv
-rtl/axis_gmii_tx.sv
-rtl/mac_ctrl_rx.sv
-rtl/mac_pause_ctrl_tx.sv
-rtl/mac_pause_ctrl_rx.sv
-lib/axis/rtl/axis_async_fifo_adapter.sv
-lib/axis/rtl/axis_adapter.sv
-lib/axis/rtl/axis_async_fifo.sv
diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet
deleted file mode 160000
index c180b22ed..000000000
--- a/addins/verilog-ethernet
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d
diff --git a/addins/vivado-boards b/addins/vivado-boards
deleted file mode 160000
index d1898bd01..000000000
--- a/addins/vivado-boards
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit d1898bd01f25d4965f9e50659bbdf70365745a06
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index a999e70f3..8c467d581 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -1,23 +1,16 @@
 # Wally Coremark Makefile
 # Daniel Torres & David Harris 28 July 2022
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 PORT_DIR = $(CURDIR)/riscv64-baremetal
-cmbase= $(WALLY)/addins/coremark
-work_dir= $(WALLY)/benchmarks/coremark/work
-XLEN ?=32
+cmbase=../../addins/coremark
+work_dir= ../../benchmarks/coremark/work
+XLEN ?=64
 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
 	$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
-ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs
-CONFIG := rv$(XLEN)gc
-#ARCH := rv$(XLEN)gc
-#ARCH := rv$(XLEN)imc_zicsr
-#ARCH := rv$(XLEN)im_zicsr
-#ARCH := rv$(XLEN)i_zicsr
-
+ARCH := rv$(XLEN)im
 PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 	-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
 	-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
@@ -27,9 +20,11 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
-run: $(work_dir)/coremark.bare.riscv.elf.memfile
-#	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
-	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
+run:
+	(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	cd ../../benchmarks/coremark/
+#	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
+	python3 coremark-postprocess.py
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
@@ -37,14 +32,13 @@ $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	extractFunctionRadix.sh $<.elf.objdump
 
 $(work_dir)/coremark.bare.riscv: $(sources) Makefile
-	$(MAKE) -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV) XCFLAGS="$(PORT_CFLAGS)"
+	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)"
 	mkdir -p $(work_dir)
 	mv $(cmbase)/coremark.bare.riscv $(work_dir)
 
 .PHONY: clean
 
 clean:
-	$(MAKE) -C $(cmbase) clean
 	rm -f $(work_dir)/*
 
 
diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py
new file mode 100644
index 000000000..d069e8744
--- /dev/null
+++ b/benchmarks/coremark/coremark-postprocess.py
@@ -0,0 +1,68 @@
+#!/usr/bin/env python
+#########################################################
+#
+# coremark postprocessing script
+#
+# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+#
+# Created 2022-09-25
+#
+# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+# is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+##################################################
+
+logFile = "../../benchmarks/coremark/work/coremark.sim.log"
+
+with open(logFile, "r") as logRead:
+    logLines = logRead.readlines()
+
+for lineNum in range(len(logLines)):
+    contents = logLines[lineNum].lower().split()
+    if "branches" in contents and "miss" in contents:
+        branchMisses = int(contents[-1])
+    elif "branches" in contents:
+        branchesTot = int(contents[-1])
+        branchLineNum = lineNum + 2
+    
+    if "d-cache" in contents and "misses" in contents:
+        dCacheMisses = int(contents[-1])
+    elif "d-cache" in contents:
+        dCacheAccess = int(contents[-1])
+        dCacheLineNum = lineNum + 2
+
+    if "i-cache" in contents and "misses" in contents:
+        ICacheMisses = int(contents[-1])
+    elif "i-cache" in contents:
+        ICacheAccess = int(contents[-1])
+        ICacheLineNum = lineNum + 2
+
+# need to add the number of previously added lines to the line number so that they stay in the intedned order.
+logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
+logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")
+logLines.insert(dCacheLineNum+2, "# D-cache Hit Rate " + str((dCacheAccess - dCacheMisses) / dCacheAccess) + "\n")
+
+logLines.insert(ICacheLineNum+3, "# I-cache Hits " + str(ICacheAccess - ICacheMisses) + "\n")
+logLines.insert(ICacheLineNum+4, "# I-cache Miss Rate " + str(ICacheMisses / ICacheAccess) + "\n")
+logLines.insert(ICacheLineNum+5, "# I-cache Hit Rate " + str((ICacheAccess - ICacheMisses) / ICacheAccess) + "\n")
+
+logLines.insert(branchLineNum+6, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
+
+
+with open(logFile, "w") as logWrite:
+    logWrite.writelines(logLines)
+
+
+
+
+
diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py
deleted file mode 100755
index 2e2ab4555..000000000
--- a/benchmarks/coremark/coremark_sweep.py
+++ /dev/null
@@ -1,110 +0,0 @@
-#!/usr/bin/env python3
-##################################################
-## coremark_sweep.py
-
-## Written: Shreesh Kulkarni, kshreesh5@gmail.com
-## Created: 20 March 2024
-## Modified: 08 April 2024
-## Purpose: Wally  Coremark sweep Script for both 32 and 64 bit configs with csv file extraction. 
- 
-## Documentation: 
-
-# A component of the CORE-V-WALLY configurable RISC-V project.
-# https://github.com/openhwgroup/cvw
- 
-# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-# except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-# may obtain a copy of the License at
-
-# https://solderpad.org/licenses/SHL-2.1/
-
-# Unless required by applicable law or agreed to in writing, any work distributed under the 
-# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-# either express or implied. See the License for the specific language governing permissions 
-# and limitations under the License.
-###########################################################################################
-
-
-import csv
-import os
-import re
-
-# list of architectures to run. 
-arch_list = [
-    "rv32i_zicsr",
-    "rv32im_zicsr",
-    "rv32imc_zicsr",
-    "rv32im_zicsr_zba_zbb_zbs",
-    "rv32gc",
-    "rv32gc_zba_zbb_zbs",
-    "rv64i_zicsr",
-    "rv64im_zicsr",
-    "rv64imc_zicsr",
-    "rv64im_zicsr_zba_zbb_zbs",
-    "rv64gc",
-    "rv64gc_zba_zbb_zbs"
-]
-        
-# Define regular expressions to match the desired fields
-mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
-#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
-#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
-# Open a CSV file to write the results
-resultfile = 'coremark_results.csv'
-with open(resultfile, mode='w', newline='') as csvfile:
-    fieldnames = ['Architecture', 'CM / MHz','CPI','MTIME','MINSTRET','Load Stalls','Store Stalls','D$ Accesses',
-                    'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
-                    'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
-    writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
-
-    writer.writeheader()
-
-    # Loop through each architecture and run the make commands
-    for arch in arch_list:
-        xlen_value = "32" if "32" in arch else "64"
-        os.system("make clean")
-        make_all = f"make all XLEN={xlen_value} ARCH={arch}"
-        os.system(make_all)
-
-        make_run = f"make run XLEN={xlen_value} ARCH={arch}"
-        print("Running: " + make_run)
-        output = os.popen(make_run).read()  # Capture the output of the command
-
-        # Extract the Coremark values using regular expressions
-        mt_match = re.search(mt_regex, output,re.DOTALL)
-        #cpi_match = re.search(cpi_regex,output,re.DOTALL)
-        #cmhz_match = re.search(cmhz_regex,output,re.DOTALL)
-        #minstret_match = re.search(minstret_regex,output)
-
-        # Write the architecture and extracted values to the CSV file
-    
-        mtime = mt_match.group(1)
-        minstret= mt_match.group(2)
-        cmhz= mt_match.group(3)
-        cpi= mt_match.group(4)
-        lstalls= mt_match.group(5)
-        swtalls= mt_match.group(6)
-        dacc= mt_match.group(7)
-        dmiss= mt_match.group(8)
-        iacc= mt_match.group(9)
-        imiss= mt_match.group(10)
-        br= mt_match.group(11)
-        brm= mt_match.group(12)
-        btb= mt_match.group(13)
-        jmp= mt_match.group(14)
-        ras= mt_match.group(15)
-        ret= mt_match.group(16)
-        bpc= mt_match.group(17)
-        #minstret = mt_instret_match.group(2)
-        writer.writerow({'Architecture': arch, 'CM / MHz':cmhz,'CPI':cpi, 'MTIME': mtime,'MINSTRET':minstret,
-                            'Load Stalls':lstalls,
-                            'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
-                            'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})
-        csvfile.flush()
-    csvfile.close()
-
-
diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.h b/benchmarks/coremark/riscv64-baremetal/core_portme.h
index 8db43d20a..ce88f7239 100755
--- a/benchmarks/coremark/riscv64-baremetal/core_portme.h
+++ b/benchmarks/coremark/riscv64-baremetal/core_portme.h
@@ -109,11 +109,10 @@ typedef unsigned short ee_u16;
 typedef signed int ee_s32;
 typedef double ee_f32;
 typedef unsigned char ee_u8;
+typedef unsigned int ee_u32;
 #if (XLEN==64) 
-	typedef signed int ee_u32; // replaced with signed to improve performance by avoiding zero extension in RV64 per https://github.com/sifive/benchmark-coremark/blob/master/linux64/core_portme.h#L102
 	typedef unsigned long long ee_ptr_int;
 #else
-	typedef unsigned int ee_u32;
 	typedef ee_u32 ee_ptr_int;
 #endif
 typedef size_t ee_size_t;
diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.mak b/benchmarks/coremark/riscv64-baremetal/core_portme.mak
index e07196061..27e31b859 100755
--- a/benchmarks/coremark/riscv64-baremetal/core_portme.mak
+++ b/benchmarks/coremark/riscv64-baremetal/core_portme.mak
@@ -107,7 +107,7 @@ port_prebuild: $(PGO_STAGE)
 
 .PHONY: build_pgo_gcc
 build_pgo_gcc:
-	$(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" gen_pgo_data REBUILD=1
+	$(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
 
 # Target: port_postbuild
 # Generate any files that are needed after actual build end.
diff --git a/benchmarks/coremark/riscv64-baremetal/crt.S b/benchmarks/coremark/riscv64-baremetal/crt.S
index bf974c847..d75e81e06 100644
--- a/benchmarks/coremark/riscv64-baremetal/crt.S
+++ b/benchmarks/coremark/riscv64-baremetal/crt.S
@@ -134,8 +134,6 @@ _start:
   add sp, sp, tp
 
   j _init
-sig_end_canary:       
-  nop
 
   .align 2
 trap_entry:
diff --git a/benchmarks/coremark/riscv64-baremetal/syscalls.c b/benchmarks/coremark/riscv64-baremetal/syscalls.c
index 25c47b797..34615b6e4 100644
--- a/benchmarks/coremark/riscv64-baremetal/syscalls.c
+++ b/benchmarks/coremark/riscv64-baremetal/syscalls.c
@@ -84,11 +84,6 @@ void setStats(int enable)
   READ_CTR(mhpmcounter10);
   READ_CTR(mhpmcounter11);
   READ_CTR(mhpmcounter12);  
-  READ_CTR(mhpmcounter13);  
-  READ_CTR(mhpmcounter14);  
-  READ_CTR(mhpmcounter15);  
-  READ_CTR(mhpmcounter16);  
-  READ_CTR(mhpmcounter17);  
 
 #undef READ_CTR
 }
@@ -172,22 +167,18 @@ void _init(int cid, int nc)
   counters[12] = read_csr(mhpmcounter12) - counters[12];
   counters[13] = read_csr(mhpmcounter13) - counters[13];
   counters[14] = read_csr(mhpmcounter14) - counters[14];
-  counters[15] = read_csr(mhpmcounter15) - counters[15];
-  counters[16] = read_csr(mhpmcounter16) - counters[16];
-  counters[17] = read_csr(mhpmcounter17) - counters[17];
 
-  ee_printf("Load Stalls %d\n", counters[11]);
-  ee_printf("Store Stalls %d\n", counters[12]);
-  ee_printf("D-Cache Accesses %d\n", counters[13]);
-  ee_printf("D-Cache Misses %d\n", counters[14]); 
-  ee_printf("I-Cache Accesses %d\n", counters[16]);
-  ee_printf("I-Cache Misses %d\n", counters[17]);
-  ee_printf("Branches %d\n", counters[3]);
-  ee_printf("Branches Miss Predictions %d\n", counters[7]);
-  ee_printf("BTB Misses %d\n", counters[8]);
-  ee_printf("Jump and JR %d\n", counters[4]);
-  ee_printf("RAS Wrong %d\n", counters[9]);
-  ee_printf("Returns %d\n", counters[5]);
+  ee_printf("Load Stalls %d\n", counters[3]);
+  ee_printf("D-Cache Accesses %d\n", counters[11]);
+  ee_printf("D-Cache Misses %d\n", counters[12]); 
+  ee_printf("I-Cache Accesses %d\n", counters[13]);
+  ee_printf("I-Cache Misses %d\n", counters[14]);
+  ee_printf("Branches %d\n", counters[5]);
+  ee_printf("Branches Miss Predictions %d\n", counters[4]);
+  ee_printf("BTB Misses %d\n", counters[6]);
+  ee_printf("Jump, JAL, JALR %d\n", counters[7]);
+  ee_printf("RAS Wrong %d\n", counters[8]);
+  ee_printf("Returns %d\n", counters[9]);
   ee_printf("BP Class Wrong %d\n", counters[10]);
   ee_printf("Done printing performance counters\n");
 
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 09d2939b0..21c30cf6e 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -3,10 +3,9 @@
 # Compile Embench for Wally
 
 embench_dir = ../../addins/embench-iot
-ARCH=rv32imac_zicsr
 
 all: build 
-run: build size sim
+run: size sim
 
 allClean: clean all
 
@@ -16,46 +15,39 @@ buildsize: build_speedopt_size build_sizeopt_size
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_speed:
-	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-O2 -nostartfiles -march=$(ARCH)" 
-	# remove files not used in embench1.0  When changing to 2.0, restore these files		
-	#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
-	#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
-	#rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount	
+	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
 	find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 build_sizeopt_speed:
-	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-Os -nostartfiles -march=$(ARCH)" 
-	# remove files not used in embench1.0  When changing to 2.0, restore these files		
-	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
-	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
-	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount	
+	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" 
 	find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_size:
-	$(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-O2 -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0"
+	$(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-O2 -msave-restore" --dummy-libs="libgcc libm libc crt0"
 
 build_sizeopt_size:
-	$(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-Os -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0"
+	$(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0"
 
-# builds dependencies, then launches sim and finally runs python wrapper script to present results
-sim: sim_build_memfile sim_run speed
+# builds dependencies, then launches modelsim and finally runs python wrapper script to present results
+sim: modelsim_build_memfile modelsim_run speed
 
-# launches sim to simulate tests on wally
-sim_run:
-	wsim rv32gc embench --params "BPRED_LOGGER=1\'b1" 
+# launches modelsim to simulate tests on wally
+modelsim_run:
+	(cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
 objdump:
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done
 
 # build memfiles, objdump.lab and objdump.addr files
-sim_build_memfile: objdump
+modelsim_build_memfile: objdump
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
 
 # builds the tests for speed, runs them on spike and then launches python script to present results
-# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and questa
+# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim
 # you'll need to manually remove one of the two .output files, or run make clean
 spike: buildspeed spike_run speed
 
@@ -81,4 +73,4 @@ clean:
 allclean: clean
 	rm -rf $(embench_dir)/logs/
 
-# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c
+# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c
\ No newline at end of file
diff --git a/benchmarks/embench/embench_arch_sweep.py b/benchmarks/embench/embench_arch_sweep.py
deleted file mode 100755
index 992f34844..000000000
--- a/benchmarks/embench/embench_arch_sweep.py
+++ /dev/null
@@ -1,83 +0,0 @@
-#!/usr/bin/env python3
-# embench_arch_sweep.py
-# David_Harris@hmc.edu 16 November 2023
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Run embench on a variety of architectures and collate results
-
-import collections
-import os
-import re
-from datetime import datetime
-
-archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
-
-def calcgeomean(d, arch):
-    progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"]
-    result = 1.0
-    for p in progs:
-        #val = d[arch][p]
-        val = d[arch].get(p, 1.0)
-        result = result *float(val)
-    result = pow(result, (1.0/float(len(progs))))
-    return result
-
-def tabulate_arch_sweep(directory):
-    for case in ["wallySizeOpt_size", "wallySpeedOpt_size",  "wallySizeOpt_speed", "wallySpeedOpt_speed"]:
-        print(case)
-        d = collections.defaultdict(dict)
-        for arch in archs:
-            file = case+"_"+arch+".json"
-            file_path = os.path.join(directory, file)
-            lines = []
-            with open(file_path) as f:
-                lines = f.readlines()
-            for line in lines:
-                #print("File: "+file+" Line: "+line)
-                #p = re.compile('".*" : .*,')
-                p = r'"([^"]*)" : ([^,\n]+)'
-                match = re.search(p, line)
-                if match:
-                    prog = match.group(1)
-                    result = match.group(2)
-                    d[arch][prog] = result
-                    #print(match.group(1)+" " + match.group(2))
-            f.close()
-        for arch in [""] + archs:
-            print (arch, end="\t")
-        print("")
-        for prog in d[archs[0]]:
-            print(prog, end="\t")
-            for arch in archs:
-                entry = d[arch].get(prog, "n/a")
-                print (entry, end="\t")
-            print("")
-        print("New geo mean", end="\t")
-        for arch in archs:
-            geomean = calcgeomean(d, arch)
-            print(geomean, end="\t")
-        print("\n\n")
- 
-def run_arch_sweep():
-    # make a folder whose name depends on the date
-    # Get current date
-    current_date = datetime.now()
-    # Format date as a string in the format YYYYMMDD
-    date_string = current_date.strftime('%Y%m%d_%H%M%S')
-    target_dir = "run_"+date_string
-    # Create a directory with the date string as its name
-    os.mkdir(target_dir)
-
-    # make a directory with the current date as its name 
-
-    # sweep the runs and save the results in the run directory
-    for arch in archs:
-        os.system("make clean")
-        os.system("make run ARCH="+arch)
-        for res in ["SizeOpt_size", "SizeOpt_speed", "SpeedOpt_size", "SpeedOpt_speed"]:
-            os.system("mv -f wally"+res+".json "+target_dir+"/wally"+res+"_"+arch+".json")
-    return target_dir
-
-directory = run_arch_sweep()
-#directory = "run_20231120_072037-caches"
-tabulate_arch_sweep(directory)
diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py
index fd283190e..de8b70ce9 100755
--- a/benchmarks/graphGen.py
+++ b/benchmarks/graphGen.py
@@ -1,23 +1,19 @@
-#!/usr/bin/env python3
-# Daniel Torres 2022
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-import json
+#!/usr/bin/env python
 import subprocess
 import sys
-
+import json
 import plotly.graph_objects as go
 from plotly.subplots import make_subplots
 
 debug = True
 
-def loadCoremark(coremarkData):
+def loadCoremark():
     """loads the coremark data dictionary"""
     coremarkPath = "riscv-coremark/work/coremark.sim.log"
     
     keywordlist = ["CoreMark 1.0", "CoreMark Size", "MTIME", "MINSTRET", "Branches Miss Predictions", "BTB Misses"]
     for keyword in keywordlist:
-        bashInst = "cat " + coremarkPath + ' | grep "' + keyword +  "\" | cut -d ':' -f 2 | cut -d \" \" -f 2 | tail -1"
+        bashInst = "cat " + coremarkPath + " | grep \"" + keyword +  "\" | cut -d \':\' -f 2 | cut -d \" \" -f 2 | tail -1"
         result = subprocess.run(bashInst, stdout=subprocess.PIPE, shell=True)
         if (debug): print(result)
         coremarkData[keyword] = int(result.stdout)
@@ -26,8 +22,8 @@ def loadCoremark(coremarkData):
 
 def loadEmbench(embenchPath, embenchData):
     """loads the embench data dictionary"""
-    with open(embenchPath) as f:
-        embenchData = json.load(f)
+    f = open(embenchPath)
+    embenchData = json.load(f)
     if (debug): print(embenchData)
     return embenchData
 
@@ -94,7 +90,7 @@ def main():
     embenchSpeedOpt_SpeedData = {}
     embenchSizeOpt_SizeData = {}
     embenchSpeedOpt_SizeData = {}
-    coremarkData = loadCoremark(coremarkData)
+    # coremarkData = loadCoremark()
     embenchSpeedOpt_SpeedData = loadEmbench("embench/wallySpeedOpt_speed.json", embenchSpeedOpt_SpeedData)
     embenchSizeOpt_SpeedData = loadEmbench("embench/wallySizeOpt_speed.json", embenchSizeOpt_SpeedData)
     embenchSpeedOpt_SizeData = loadEmbench("embench/wallySpeedOpt_size.json", embenchSpeedOpt_SizeData)
@@ -105,4 +101,4 @@ def main():
 if __name__ == '__main__':
     sys.exit(main())
 
-# "ls -Art ../addins/embench-iot/logs/*speed* | tail -n 1 " # gets most recent embench speed log
+# "ls -Art ../addins/embench-iot/logs/*speed* | tail -n 1 " # gets most recent embench speed log
\ No newline at end of file
diff --git a/bin/CModelBTBAccuracy.sh b/bin/CModelBTBAccuracy.sh
deleted file mode 100755
index 504edf439..000000000
--- a/bin/CModelBTBAccuracy.sh
+++ /dev/null
@@ -1,58 +0,0 @@
-#!/bin/bash
-
-###########################################
-## Written: rose@rosethompson.net
-## Created: 23 October 2023
-## Modified: 
-##
-## Purpose: Takes a directory of branch outcomes organized as 1 files per benchmark.
-##          Computes the geometric mean for btb accuracy
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-Directory="$1"
-Files="$1/*.log"
-
-for Size in $(seq 6 2 16)
-do
-    Product=1.0
-    Count=0
-    BMDRArray=()
-    for File in $Files
-    do
-	lines=`sim_bp gshare 16 16 $Size 1  $File | tail -5`
-        Total=`echo "$lines" | head -1 | awk '{print $5}'`
-        Miss=`echo "$lines" | tail -2 | head -1 | awk '{print $8}'`
-        BMDR=`echo "100.0 * $Miss / $Total" | bc -l`
-        BMDRArray+=("$BMDR")
-        if [ $Miss -eq 0 ]; then
-	    Product=`echo "scale=200; $Product * 100 / $Total" | bc -l`
-        else
-            Product=`echo "scale=200; $Product * $BMDR" | bc -l`
-        fi
-	Count=$((Count+1))
-    done
-    # with such long precision bc outputs onto multiple lines
-    # must remove \n and \ from string
-    Product=`echo "$Product" | tr -d '\n' | tr -d '\\\'`
-    GeoMean=`perl -E "say $Product**(1/$Count)"`
-    echo "$Pred$Size $GeoMean"
-done
diff --git a/bin/CModelBranchAccuracy.sh b/bin/CModelBranchAccuracy.sh
deleted file mode 100755
index 039e38a8b..000000000
--- a/bin/CModelBranchAccuracy.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/bash
-
-###########################################
-## Written: rose@rosethompson.net
-## Created: 12 March 2023
-## Modified: 
-##
-## Purpose: Takes a directory of branch outcomes organized as 1 files per benchmark.
-##          Computes the geometric mean.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-Directory="$1"
-Files="$1/*.log"
-
-for Pred in "bimodal" "gshare" "local4" "local8" "local10"
-do
-    for Size in $(seq 6 2 16)
-    do
-	if [ $Pred = "gshare" ]; then
-	    SizeString="$Size $Size 18 1"
-	elif [ $Pred = "bimodal" ]; then
-	    SizeString="$Size 18 1"
-	elif [ $Pred = "local4" ]; then
-	    SizeString="$Size 4 18 1"
-	    Pred="yehpatt"
-	elif [ $Pred = "local8" ]; then
-	    SizeString="$Size 8 18 1"
-	    Pred="yehpatt"
-	elif [ $Pred = "local10" ]; then
-	    SizeString="$Size 10 18 1"
-	    Pred="yehpatt"
-	fi
-
-	Product=1.0
-	Count=0
-	for File in $Files
-	do
-	    #echo "sim_bp $Pred $Size $Size 18 1 $File | tail -1 | awk '{print $4}'"
-	    #echo "sim_bp $Pred $SizeString $File | tail -1 | awk '{print $4}'"
-	    BMDR=`sim_bp -c $Pred $SizeString $File | tail -1 | awk '{print $4}'`
-	    Product=`echo "$Product * $BMDR" | bc`
-	    Count=$((Count+1))
-	done
-
-	GeoMean=`perl -E "say $Product**(1/$Count)"`
-	echo "$Pred$Size $GeoMean"
-    done
-done
diff --git a/bin/CacheSim.py b/bin/CacheSim.py
deleted file mode 100755
index abf5874c5..000000000
--- a/bin/CacheSim.py
+++ /dev/null
@@ -1,307 +0,0 @@
-#!/usr/bin/env python3
-
-###########################################
-## CacheSim.py
-##
-## Written: lserafini@hmc.edu
-## Created: 27 March 2023
-## Modified: 12 April 2023
-##
-## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-# how to invoke this simulator:
-# CacheSim.py <number of lines> <number of ways> <length of physical address> <length of tag> -f <log file> (-v)
-# so the default invocation for rv64gc is 'CacheSim.py 64 4 56 44 -f <log file>'
-# the log files to run this simulator on can be generated from testbench.sv
-# by setting I_CACHE_ADDR_LOGGER and/or D_CACHE_ADDR_LOGGER to 1 before running tests.
-# I (Lim) recommend logging a single set of tests (such as wally64priv) at a time.
-# This helps avoid unexpected logger behavior.
-# With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
-# With verbose mode on, the simulator logs each access into the cache.
-# Add -p or --perf to report the hit/miss ratio.
-# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
-# These distributions may not add up to 100; this is because of flushes or invalidations.
-
-import argparse
-import math
-import os
-import sys
-
-
-class CacheLine:
-    def __init__(self):
-        self.tag = 0
-        self.valid = False
-        self.dirty = False
-
-    def __str__(self):
-        string = f"(V: {self.valid}, D: {self.dirty}"
-        string += f", Tag: {hex(self.tag)})"
-        return string
-
-    def __repr__(self):
-        return self.__str__()
-
-class Cache:
-    def __init__(self, numsets, numways, addrlen, taglen):
-        self.numways = numways
-        self.numsets = numsets
-
-        self.addrlen = addrlen
-        self.taglen = taglen
-        self.setlen = int(math.log(numsets, 2))
-        self.offsetlen = self.addrlen - self.taglen - self.setlen
-
-        self.ways = []
-        for i in range(numways):
-            self.ways.append([])
-            for _ in range(numsets):
-                self.ways[i].append(CacheLine())
-
-        self.pLRU = []
-        for i in range(self.numsets):
-            self.pLRU.append([0]*(self.numways-1))
-
-    # flushes the cache by setting all dirty bits to False
-    def flush(self):
-        for way in self.ways:
-            for line in way:
-                line.dirty = False
-
-    # access a cbo type instruction
-    def cbo(self, addr, invalidate):
-        tag, setnum, _ = self.splitaddr(addr)
-        for waynum in range(self.numways):
-            line = self.ways[waynum][setnum]
-            if line.tag == tag and line.valid:
-                line.dirty = 0
-                if invalidate:
-                    line.valid = 0
-
-    # invalidates the cache by setting all valid bits to False
-    def invalidate(self):
-        for way in self.ways:
-            for line in way:
-                line.valid = False
-
-    # resets the pLRU to a fresh 2-D array of 0s
-    def clear_pLRU(self):
-        self.pLRU = []
-        for _ in range(self.numsets):
-            self.pLRU.append([0]*(self.numways-1))
-
-    # splits the given address into tag, set, and offset
-    def splitaddr(self, addr):
-        # no need for offset in the sim, but it's here for debug
-        tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2)
-        setnum = (addr >> self.offsetlen) & int('1'*self.setlen, 2)
-        offset = addr & int('1'*self.offsetlen, 2)
-        return tag, setnum, offset
-
-    # performs a cache access with the given address.
-    # returns a character representing the outcome:
-    # H/M/E/D - hit, miss, eviction, or eviction with writeback
-    def cacheaccess(self, addr, write=False):
-        tag, setnum, _ = self.splitaddr(addr)
-
-        # check our ways to see if we have a hit
-        for waynum in range(self.numways):
-            line = self.ways[waynum][setnum]
-            if line.tag == tag and line.valid:
-                line.dirty = line.dirty or write
-                self.update_pLRU(waynum, setnum)
-                return 'H'
-
-        # we didn't hit, but we may not need to evict.
-        # check for an empty way line.
-        for waynum in range(self.numways):
-            line = self.ways[waynum][setnum]
-            if not line.valid:
-                line.tag = tag
-                line.valid = True
-                line.dirty = write
-                self.update_pLRU(waynum, setnum)
-                return 'M'
-
-        # we need to evict. Select a victim and overwrite.
-        victim = self.getvictimway(setnum)
-        line = self.ways[victim][setnum]
-        prevdirty = line.dirty
-        line.tag = tag
-        line.valid = True   # technically redundant
-        line.dirty = write
-        self.update_pLRU(victim, setnum)
-        return 'D' if prevdirty else 'E'
-
-    # updates the psuedo-LRU tree for the given set
-    # with an access to the given way
-    def update_pLRU(self, waynum, setnum):
-        if self.numways == 1:
-            return
-
-        tree = self.pLRU[setnum]
-        bottomrow = (self.numways - 1)//2
-        index = (waynum // 2) + bottomrow
-        tree[index] = int(not waynum % 2)
-        while index > 0:
-            parent = (index-1) // 2
-            tree[parent] = index % 2
-            index = parent
-
-    # uses the psuedo-LRU tree to select
-    # a victim way from the given set
-    # returns the victim way as an integer
-    def getvictimway(self, setnum):
-        if self.numways == 1:
-            return 0
-
-        tree = self.pLRU[setnum]
-        index = 0
-        bottomrow = (self.numways - 1) // 2 #first index on the bottom row of the tree
-        while index < bottomrow:
-            if tree[index] == 0:
-                # Go to the left child
-                index = index*2 + 1
-            else: #tree[index] == 1
-                # Go to the right child
-                index = index*2 + 2
-
-        victim = (index - bottomrow)*2
-        if tree[index] == 1:
-            victim += 1
-
-        return victim
-
-    def __str__(self):
-        string = ""
-        for i in range(self.numways):
-            string += f"Way {i}: "
-            for line in self.ways[i]:
-                string += f"{line}, "
-            string += "\n\n"
-        return string
-
-    def __repr__(self):
-        return self.__str__()
-
-
-def parseArgs():
-    parser = argparse.ArgumentParser(description="Simulates a L1 cache.")
-    parser.add_argument('numlines', type=int, help="The number of lines per way (a power of 2)", metavar="L")
-    parser.add_argument('numways', type=int, help="The number of ways (a power of 2)", metavar='W')
-    parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A")
-    parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
-    parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
-    parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
-    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
-    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
-    return parser.parse_args()
-
-def main(args):
-    cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
-    extfile = os.path.expanduser(args.file)
-    mismatches = 0
-
-    if args.perf:
-        hits = 0
-        misses = 0
-
-    if args.dist:
-        loads = 0
-        stores = 0
-        atoms = 0
-        totalops = 0
-
-    with open(extfile) as f:
-        for ln in f:
-            ln = ln.strip()
-            lninfo = ln.split()
-            if len(lninfo) < 3: #non-address line
-                if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'):
-                    # currently BEGIN and END traces aren't being recorded correctly
-                    # trying TRAIN clears instead
-                    cache.invalidate() # a new test is starting, so 'empty' the cache
-                    cache.clear_pLRU()
-                    if args.verbose:
-                        print("New Test")
-
-            else:
-                if args.dist:
-                    totalops += 1
-
-                if lninfo[1] == 'F':
-                    cache.flush()
-                    if args.verbose:
-                        print("F")
-                elif lninfo[1] == 'I':
-                    cache.invalidate()
-                    if args.verbose:
-                        print("I")
-                elif lninfo[1] == 'V' or lninfo[1] == 'L' or lninfo[1] == 'C':
-                    addr = int(lninfo[0], 16)
-                    IsCBOClean = lninfo[1] != 'C'
-                    cache.cbo(addr, IsCBOClean)
-                    if args.verbose:
-                        print(lninfo[1])
-                else:
-                    addr = int(lninfo[0], 16)
-                    iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z'
-                    result = cache.cacheaccess(addr, iswrite)
-
-                    if args.verbose:
-                        tag, setnum, offset = cache.splitaddr(addr)
-                        print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
-
-                    if args.perf:
-                        if result == 'H':
-                            hits += 1
-                        else:
-                            misses += 1
-
-                    if args.dist:
-                        if lninfo[1] == 'R':
-                            loads += 1
-                        elif lninfo[1] == 'W':
-                            stores += 1
-                        elif lninfo[1] == 'A':
-                            atoms += 1
-
-                    if result != lninfo[2]:
-                        print(f"Result mismatch at address {lninfo[0]}. Wally: {lninfo[2]}, Sim: {result}")
-                        mismatches += 1
-    if args.dist:
-        percent_loads = str(round(100*loads/totalops))
-        percent_stores = str(round(100*stores/totalops))
-        percent_atoms = str(round(100*atoms/totalops))
-        print(f"This log had {percent_loads}% loads, {percent_stores}% stores, and {percent_atoms}% atomic operations.")
-
-    if args.perf:
-        ratio = round(hits/misses,3)
-        print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
-
-    if mismatches == 0:
-        print("SUCCESS! There were no mismatches between Wally and the sim.")
-    return mismatches
-
-if __name__ == '__main__':
-    args = parseArgs()
-    sys.exit(main(args))
diff --git a/bin/SeparateBranch.sh b/bin/SeparateBranch.sh
deleted file mode 100755
index 32968453b..000000000
--- a/bin/SeparateBranch.sh
+++ /dev/null
@@ -1,56 +0,0 @@
-#!/bin/bash
-
-###########################################
-## Written: rose@rosethompson.net
-## Created: 12 March 2023
-## Modified: 15 April 2025 jcarlin@hmc.edu
-##
-## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
-##          separate files, one for each program.
-## Input:   branch log file generated by modelsim
-## output:  outputs to directory branch a collection of files with the branch outcomes
-##          separated by benchmark application.  Example names are aha-mot64bd_sizeopt_speed_branch.log
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-File="$1"
-TrainLineNumbers=$(grep -n "TRAIN" "$File" | awk -NF ':' '{print $1}')
-Name=$(grep -n "BEGIN" "$File" | awk -NF '/' '{print $7_$5}')
-EndLineNumbers=$(grep -n "END" "$File" | awk -NF ':' '{print $1}')
-
-echo Name: "$Name"
-echo TrainLineNumbers: "$TrainLineNumbers"
-echo EndLineNumbers: "$EndLineNumbers"
-
-mapfile -t NameArray <<< "$Name"
-mapfile -t TrainLineNumberArray <<< "$TrainLineNumbers"
-mapfile -t EndLineNumberArray <<< "$EndLineNumbers"
-
-OutputPath=${File%%.*}
-mkdir -p "$OutputPath"
-Length=${#EndLineNumberArray[@]}
-for i in $(seq 0 1 $((Length-1)))
-do
-    CurrName=${NameArray[$i]}
-    CurrTrain=$((${TrainLineNumberArray[$i]}+1))
-    CurrEnd=$((${EndLineNumberArray[$i]}-1))
-    echo "${CurrName}", "${CurrTrain}", "${CurrEnd}"
-    sed -n "${CurrTrain},${CurrEnd}p" "$File" > "${OutputPath}/${CurrName}_${File}"
-done
diff --git a/bin/analyze_riscv_elf.py b/bin/analyze_riscv_elf.py
deleted file mode 100755
index 3da03f466..000000000
--- a/bin/analyze_riscv_elf.py
+++ /dev/null
@@ -1,83 +0,0 @@
-#!/usr/bin/env python3
-
-###########################################
-## analyze_riscv_elf.py
-##
-## Written: james.stine@okstate.edu
-## Created: April 7, 2025
-##
-## Purpose: Analyze a RISC-V ELF file and report which instructions are used,
-##          along with their frequency. The script disassembles the ELF using
-##          riscv64-unknown-elf-objdump, filters real instructions (excluding
-##          pseudo-ops and section headers), and displays a histogram of 
-##          instruction use.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-25 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-import re
-import subprocess
-import sys
-from collections import Counter
-
-
-def disassemble_elf(elf_path):
-    try:
-        result = subprocess.run(
-            ["riscv64-unknown-elf-objdump", "-d", "-M", "no-aliases", elf_path],
-            capture_output=True,
-            text=True,
-            check=True
-        )
-        return result.stdout
-    except subprocess.CalledProcessError as e:
-        print(f"Error running objdump: {e.stderr}")
-        sys.exit(1)
-
-def extract_instructions(disassembly):
-    instructions = []
-    for line in disassembly.splitlines():
-        # Match instruction lines only: address: machine-code instruction [operands...]
-        match = re.match(r'^\s*[0-9a-f]+:\s+([0-9a-f]{8}|\s{8})\s+(\S+)', line)
-        if match:
-            instr = match.group(2)
-            instructions.append(instr)
-    return instructions
-
-def main():
-    if len(sys.argv) != 2:
-        print("Usage: python3 analyze_riscv_elf.py <file.elf>")
-        sys.exit(1)
-
-    elf_path = sys.argv[1]
-    disassembly = disassemble_elf(elf_path)
-    instructions = extract_instructions(disassembly)
-    counter = Counter(instructions)
-
-    print(f"\nInstruction usage in {elf_path}:\n")
-    if not counter:
-        print("No instructions found (did you use the correct target ELF file?)")
-    else:
-        for instr, count in counter.most_common():
-            count_str = f"{count:,}"  # Add comma as thousands separator
-            print(f"{instr:<10} {count_str}")
-
-if __name__ == "__main__":
-    main()
-
diff --git a/bin/derivgen.pl b/bin/derivgen.pl
deleted file mode 100755
index dd736895d..000000000
--- a/bin/derivgen.pl
+++ /dev/null
@@ -1,157 +0,0 @@
-#!/usr/bin/env -S perl -w
-
-###########################################
-## derivgen.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 29 January 2024
-## Modified: 
-##
-## Purpose: Read config/derivlist.txt and generate config/deriv/*/config.vh
-##          derivative configurations from the base configurations
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-use strict;
-use warnings;
-import os; 
-use Data::Dumper;
-
-my $curderiv = "";
-my @derivlist = ();
-my %derivs;
-my %basederiv;
-my @derivnames = ();
-
-if ($#ARGV != -1) {
-    die("Usage: $0")
-}
-my $derivlist = "$ENV{WALLY}/config/derivlist.txt";
-open(my $fh, $derivlist) or die "Could not open file '$derivlist' $!";
-foreach my $line (<$fh>) {
-    chomp $line;
-    my @tokens = split('\s+', $line);
-    if ($#tokens < 0 || $tokens[0] =~ /^#/) {   # skip blank lines and comments
-        next;
-    }
-    if ($tokens[0] =~ /deriv/) {   # start of a new derivative
-        &terminateDeriv();
-        $curderiv = $tokens[1];
-        $basederiv{$curderiv} = $tokens[2];
-        @derivlist = ();
-        if ($#tokens > 2) {
-            my $inherits = $derivs{$tokens[3]};
-            @derivlist = @{$inherits};
-        }
-    } else {   # add to the current derivative
-        $line =~ /\s*(\S+)\s*(.*)/;
-        my @entry = ($1, $2);
-        push(@derivlist, \@entry);
-    }
-}
-&terminateDeriv();
-close($fh);
-system("rm -rf $ENV{WALLY}/config/deriv");
-#foreach my $key (keys %derivs) {
-foreach my $key (@derivnames) {
-    my $dir = "$ENV{WALLY}/config/deriv/$key";
-    system("mkdir -p $dir");
-    my $configunmod = "$dir/config_unmod.vh";
-    my $config = "$dir/config.vh";
-    my $base = "$ENV{WALLY}/config/$basederiv{$key}/config.vh";
-    if (! -e $base) {
-        $base = "$ENV{WALLY}/config/deriv/$basederiv{$key}/config.vh";
-        #if (! -e $base) {
-        #    die("Unable to find base config $base for $key\n");
-        #}
-    }
-    system("cp $base $configunmod");
-    open(my $unmod, $configunmod) or die "Could not open file '$configunmod' $!";
-    open(my $fh, '>>', $config) or die "Could not open file '$config' $!";
-
-    # Create symlink to imperas.ic for deriv buildroot
-    if ($key eq "buildroot") {
-        my $baseimperas_ic = "$ENV{WALLY}/config/$basederiv{$key}/imperas.ic";
-        if (! -e $baseimperas_ic) {
-            my $baseimperas_ic = "$ENV{WALLY}/config/deriv/$basederiv{$key}/config.vh";
-        }
-        if (-e $baseimperas_ic) { # If imperas.ic exists for base derivative, create hardlink to it
-            my $imperas_ic = "$dir/imperas.ic";
-            system("ln -T $baseimperas_ic $imperas_ic");
-        }
-    }
-
-    # Create symlink to coverage.svh for deriv breker
-    if ($key eq "breker") {
-        my $basecoverage_svh = "$ENV{WALLY}/config/$basederiv{$key}/coverage.svh";
-        if (! -e $basecoverage_svh) {
-            my $basecoverage_svh = "$ENV{WALLY}/config/deriv/$basederiv{$key}/coverage.svh";
-        }
-        if (-e $basecoverage_svh) { # If imperas.ic exists for base derivative, create hardlink to it
-            my $coverage_svh = "$dir/coverage.svh";
-            system("ln -T $basecoverage_svh $coverage_svh");
-        }
-    }
-
-    my $datestring = localtime();
-    my %hit = ();
-    print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring using derivgen.pl\n";
-    foreach my $line (<$unmod>) {
-        foreach my $entry (@{$derivs{$key}}) {    
-            my @ent = @{$entry};
-            my $param = $ent[0];
-            my $value = $ent[1]; 
-            if ($line =~ s/\b$param\s*=\s*.*;/$param = $value;/) {
-                $hit{$param} = 1;
-#               print("Hit: new line in $config for $param is $line");
-            }
-        }
-        print $fh $line;
-    }
-    close($fh);
-    close($unmod);
-    foreach my $entry (@{$derivs{$key}}) {
-        my @ent = @{$entry};
-        my $param = $ent[0];
-        if (!exists($hit{$param})) {
-            print("Unable to find $param in $key\n");
-        }
-    }
-    system("rm -f $dir/config_unmod.vh");
-}
-
-sub terminateDeriv {
-    if ($curderiv ne "") { # close out the previous derivative
-        my @dl = @derivlist;
-        $derivs{$curderiv} = \@dl;
-        push(@derivnames, $curderiv);
-    }
-};
-
-sub printref {
-    my $ref = shift;
-    my @array = @{$ref};
-    foreach my $entry (@array) {
-        print join('_', @{$entry}), ', ';
-    }
-    print("\n");
-}
diff --git a/bin/docker.sh b/bin/docker.sh
deleted file mode 100644
index 3b827398c..000000000
--- a/bin/docker.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-# script to install docker
-# based on https://docs.docker.com/engine/install/ubuntu/
-# from Kunlin Han, entered by David Harris
-
-# Add Docker's official GPG key:
-sudo apt-get update
-sudo apt-get install ca-certificates curl
-sudo install -m 0755 -d /etc/apt/keyrings
-sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
-sudo chmod a+r /etc/apt/keyrings/docker.asc
-
-# Add the repository to Apt sources:
-echo \
-  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
-  $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
-  sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
-sudo apt-get update
-sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
-
-# verify
-sudo docker run hello-world
-
-# install podman
-sudo apt-get -y install podman
- 
\ No newline at end of file
diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh
index d36678e9c..5808f4109 100755
--- a/bin/elf2hex.sh
+++ b/bin/elf2hex.sh
@@ -1,31 +1,8 @@
 #!/bin/bash
 
-###########################################
-## Written: james.stine@okstate.edu
-## Created: 4 Jan 2022
-## Modified: 
-##
-## Purpose: Script to run elf2hex for memfile for
-##          Imperas and riscv-arch-test benchmarks
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
+# james.stine@okstate.edu 4 Jan 2022
+# Script to run elf2hex for memfile for
+# Imperas and riscv-arch-test benchmarks
 
 for file in work/rv64i_m/*/*.elf ; do
     memfile=${file%.elf}.elf.memfile
diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl
index 2d09c1fdb..70e51167e 100755
--- a/bin/exe2memfile.pl
+++ b/bin/exe2memfile.pl
@@ -1,36 +1,9 @@
-#!/usr/bin/env -S perl -w
+#!/usr/bin/perl -w
 
-###########################################
-## exe2memfile.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 26 November 2020
-## Modified: 
-##
-## Purpose: Converts an executable file to a series of 32-bit hex instructions
-##          to read into a Verilog simulation with $readmemh
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-# 
-# 
+# exe2memfile.pl
+# David_Harris@hmc.edu 26 November 2020
+# Converts an executable file to a series of 32-bit hex instructions
+# to read into a Verilog simulation with $readmemh
 
 use File::stat;
 use IO::Handle;
@@ -194,4 +167,4 @@ sub fixadr {
     my $adr = shift;
     if ($adr =~ s/^8/0/) { return hex($adr); }
     else { die("address $adr lacks leading 8\n"); }
-}
+}
\ No newline at end of file
diff --git a/bin/extractFunctionRadix.sh b/bin/extractFunctionRadix.sh
index c9446a3b5..cb37f5378 100755
--- a/bin/extractFunctionRadix.sh
+++ b/bin/extractFunctionRadix.sh
@@ -1,33 +1,34 @@
 #!/bin/bash
 
 ######################
-## extractFunctionRadix.sh
-##
-## Written: Rose Thompson
-## email: rose@rosethompson.net
-## Created: March 1, 2021
-## Modified: March 10, 2021
-##
-## Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications.
-##          File 1: .addr: A sorted list of function starting addresses. 
-##                  When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address.
-##          File 2: .lab: A sorted list of funciton labels. The names of functions.  Modelsim will display these names rather than the function address.
-## 
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
+# extractFunctionRadix.sh
+#
+# Written: Ross Thompson
+# email: ross1728@gmail.com
+# Created: March 1, 2021
+# Modified: March 10, 2021
+#
+# Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications.
+#          File 1: .addr: A sorted list of function starting addresses. 
+#                  When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address.
+#          File 2: .lab: A sorted list of funciton labels. The names of functions.  Modelsim will display these names rather than the function address.
+# 
+# A component of the Wally configurable RISC-V project.
+# 
+# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+# is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+######################
 
 
 function processProgram {
diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh
deleted file mode 100755
index 852cafecb..000000000
--- a/bin/fparchtest.sh
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/bin/bash
-#
-# fparchtest.sh
-# David_Harris@hmc.edu 26 December 2023
-#
-# Drive the riscv-isac and riscv-ctg tools to generate floating-point tests
-
-# Set up with (not retested)
-# cd ~/repos
-# git clone https://github.com/riscv/riscv-ctg.git
-# git clone https://github.com/riscv/riscv-isac.git
-# pip3 install git+https://github.com/riscv/riscv-ctg.git
-# pip3 install git+https://github.com/riscv/riscv-isac.git
-# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
-
-#riscv_isac --verbose debug  normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
-#riscv_isac --verbose debug  normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
-riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug
-#riscv_ctg -cf $RISCVCTG/sample_cgfs/dataset.cgf -cf  $RISCVCTG/sample_cgfs/rv32im.cgf -d $RISCVCTG/tests --base-isa rv32i # --verbose debug
diff --git a/bin/iterelf b/bin/iterelf
deleted file mode 100755
index 64c537a92..000000000
--- a/bin/iterelf
+++ /dev/null
@@ -1,107 +0,0 @@
-#!/usr/bin/env python3
-
-# iterelf
-# David_Harris@hmc.edu and Rose Thompson 7/3/2024
-# Run wsim on all the ELF files in a directory in parallel in lockstep
-
-
-import argparse
-import multiprocessing
-import os
-import sys
-from multiprocessing import Pool
-from multiprocessing import TimeoutError as MPTimeoutError
-
-TIMEOUT_DUR = 60  # 1` minute
-
-class bcolors:
-    HEADER = "\033[95m"
-    OKBLUE = "\033[94m"
-    OKCYAN = "\033[96m"
-    OKGREEN = "\033[92m"
-    WARNING = "\033[93m"
-    FAIL = "\033[91m"
-    ENDC = "\033[0m"
-    BOLD = "\033[1m"
-    UNDERLINE = "\033[4m"
-
-def search_log_for_mismatches(logfile):
-    """Search through the given log file for text, returning True if it is found or False if it is not"""
-    grepwarn = "grep -H Warning: " + logfile
-    os.system(grepwarn)
-    greperr = "grep -H Error: " + logfile
-    os.system(greperr)
-    grepcmd = f"grep -a -e 'Mismatches            : 0' '{logfile}' > /dev/null"
-    return os.system(grepcmd) == 0
-
-def run_test_case(elf):
-    """Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
-    WALLY = os.environ.get("WALLY")
-    fields = elf.rsplit("/", 3)
-    if fields[2] == "ref":
-        shortelf = fields[1] + "_" + fields[3]
-    else:
-        shortelf = fields[2] + "_" + fields[3]
-    #    shortelf = fields[1] + "_" + fields[2]
-    logfile = WALLY + "/sim/" + args.sim + "/logs/" + shortelf + ".log"
-    cmd = "wsim " + args.config + " " + shortelf + " --elf " + elf + " --sim " + args.sim + " --lockstep > " + logfile  # add coveerage flags if necessary
-    #    print("cmd = " + cmd)
-    os.system(cmd)
-    if search_log_for_mismatches(logfile):
-        print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}")
-        return 0
-    elif "WALLY-cbom-01" in elf:
-        # Remove this when CBO instructions are modeled in ImperasDV
-        print(f"{bcolors.OKCYAN}{cmd}: Expected mismatch because ImperasDV does not yet model cache for CBO instructions {bcolors.ENDC}")
-        return 0
-    else:
-        print(f"{bcolors.FAIL}{cmd}: Failures detected in output{bcolors.ENDC}")
-        print(f"  Check {logfile}")
-        return 1
-
-##################################
-# Main body
-##################################
-
-# Parse arguments
-parser = argparse.ArgumentParser()
-parser.add_argument("dir", help="Configuration file")
-parser.add_argument("--config", help="Configuration", default="rv64gc")
-parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "vcs"], default="questa")
-parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
-parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
-parser.add_argument("--exclude", help="Exclude files with this sufix", default="my.elf")
-args = parser.parse_args()
-
-# find all ELF files in directory
-
-ElfList = []
-if os.path.isdir(args.dir):
-    DirectorMode = 1
-    for dirpath, dirnames, filenames in os.walk(os.path.abspath(args.dir)):
-        for file in filenames:
-            if file.endswith("elf") and not file.endswith(args.exclude):
-                ElfList.append(os.path.join(dirpath, file))
-else:
-    print(args.dir + " is not a directory")
-    sys.exit(1)
-
-# spawn parallel wsim jobs for each ELF file
-
-ImperasDVLicenseCount = 8
-with Pool(processes=min(len(ElfList), multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
-    num_fail = 0
-    results = {}
-    for elf in ElfList:
-        results[elf] = pool.apply_async(run_test_case, (elf,))
-    for elf, result in results.items():
-        try:
-            num_fail += result.get(timeout=TIMEOUT_DUR)
-        except MPTimeoutError:
-            num_fail += 1
-            print(f"{bcolors.FAIL}{elf}: Timeout - runtime exceeded {TIMEOUT_DUR} seconds{bcolors.ENDC}")
-
-if num_fail == 0:
-    print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
-else:
-    print(f"{bcolors.FAIL}Completed {len(ElfList)} tests with {num_fail} failures{bcolors.ENDC}")
diff --git a/bin/libppa.pl b/bin/libppa.pl
deleted file mode 100755
index eddfc3686..000000000
--- a/bin/libppa.pl
+++ /dev/null
@@ -1,257 +0,0 @@
-#!/usr/bin/env -S perl -w
-
-###########################################
-## libppa.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 28 January 2023
-##
-## Purpose: Extract PPA information from Liberty files
-##          presently characterizes Skywater 90 and TSMC28hpc+
-##
-## The user will need to change $libpath to point to the desired library in your local installation
-## and for TSMC change the $cellname to the actual name of the inverter.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-use strict;
-use warnings;
-
-# global variables for simplicity
-my @index1; my @index2;
-my @values;
-my @cr; my @cf; my @rt; my @ft;
-
-# cell and corners to analyze
-my $libpath; my $libbase; my $cellname; my @corners;
-
-# Sky130
-$libpath ="$ENV{RISCV}/cad/lib/sky130_osu_sc_t12/12T_ms/lib";
-$libbase = "sky130_osu_sc_12T_ms_";
-$cellname = "sky130_osu_sc_12T_ms__inv_1";
-@corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs");
-printf("Library $libbase Cell $cellname\n");
-foreach my $corner (@corners) {
-    &analyzeCell($corner);
-}
-
-# Sky90
-$libpath ="$ENV{RISCV}/cad/lib/sky90/sky90_sc/V1.7.4/lib";
-$libbase = "scc9gena_";
-$cellname = "scc9gena_inv_1";
-@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");
-printf("Library $libbase Cell $cellname\n");
-foreach my $corner (@corners) {
-    &analyzeCell($corner);
-}
-
-# TSMC
-$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
-$libbase = "tcbn28hpcplusbwp30p140";
-$cellname = "INVD1..."; # replace this with the full name of the library cell
-@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
-printf("\nLibrary $libbase Cell $cellname\n");
-foreach my $corner (@corners) {
-    &analyzeCell($corner);
-}
-
-#############
-# subroutines
-#############
-
-sub analyzeCell {
-    my $corner = shift;
-    my $fname = $libpath."/".$libbase.$corner.".lib";
-    open (FILE, $fname) || die("Can't read $fname");
-    my $incell = 0;
-    my $inleakage = 0;
-    my $inpin = 0;
-    my $incellrise = 0;
-    my $incellfall = 0;
-    my $inrisetrans = 0;
-    my $infalltrans = 0;
-    my $inindex = 0;
-    my $invalues = 0;
-    my $searchstring = "cell (".$cellname.")";
-    my $area; my $leakage; my $cap;
-     while (<FILE>) {
-	if (index($_, $searchstring) != -1) { $incell = 1;}
-	elsif ($incell) {
-	    if (/cell \(/) {
-		$incell = 0;
-		close(FILE);
-		last;
-	    }
-	    if (/area\s*:\s*(.*);/) { $area = $1; }
-	    if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; }
-	    if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; }
-	    if ($inleakage == 1 && /value\s*:\s*(.*);/) {
-		$leakage = $1;
-		$inleakage = 2;
-	    }
-	    if ($inpin == 0 && /pin/) { $inpin = 1; }
-	    if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) {
-		$cap = $1;
-		$inpin = 2;
-	    }
-	    if ($inindex == 0 && /index_1/) { $inindex = 1; }
-	    if ($inindex == 1) {
-		if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); }
-		if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; }
-	    }
-	    if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;}
-	    if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; }
-	    if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; }
-	    if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; }
-	    if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) {
-		if (/values/) { $invalues = 1; @values = (); }
-		elsif ($invalues == 1) {
-		    if (/\);/) {
-			$invalues = 2;
-			if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; }
-			if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; }
-			if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; }
-			if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; }
-		    }
-		    elsif (/\"(.*)\"/) { push(@values, $1); }
-		}
-	    }
-#	    print $_;
-	}
-    }
-    
-    my $delay = &computeDelay($cap);
-    my $cornerr = sprintf("%20s", $corner);
-    my $delayr = sprintf("%2.1f", $delay*1000);
-    my $leakager = sprintf("%3.3f", $leakage);
-    
-    print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
-    #print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
-    #print(" index1: @index1\n");
-    #print(" index2: @index2\n");
-    #print("Cell Rise\n"); printMatrix(\@cr);
-    #print("Cell Fall\n"); printMatrix(\@cf);
-    #print("Rise Trans\n"); printMatrix(\@rt);
-    #print("Fall Trans\n"); printMatrix(\@ft);
-}
-
-sub computeDelay {
-    # relies on cr, cf, rt, ft, index1, index2
-    # index1 for rows of matrix (different trans times, units of ns)
-    # index2 for cols of matrix (different load capacitances, units of pF)
-
-    # first, given true load, create a rise/fall delay and transition
-    # as a function of trans time, interpolated
-    my $cap = shift;
-    my $fo4cap = 4*$cap;
-    my @cri = &interp2(\@cr, $fo4cap);
-    my @cfi = &interp2(\@cf, $fo4cap);
-    my @rti = &interp2(\@rt, $fo4cap);
-    my @fti = &interp2(\@ft, $fo4cap);
-
-    # initially guess second smallest transition time
-    my $tt = $index1[1];
-    # assume falling input with this transition, compute rise delay & trans
-    my $cr0 = &interp1(\@cri, \@index1, $tt);
-    my $rt0 = &interp1(\@rti, \@index1, $tt);
-    # now assuming rising input with rt0, compute fall delay & trans
-    my $cf1 = &interp1(\@cfi, \@index1, $rt0);
-    my $ft1 = &interp1(\@fti, \@index1, $rt0);
-    # now assuming falling input with ft1, compute rise delay & trans
-    my $cr2 = &interp1(\@cri, \@index1, $ft1);
-    my $rt2 = &interp1(\@rti, \@index1, $ft1);
-    # now assuming rising input with rt2, compute fall delay & trans
-    my $cf3 = &interp1(\@cfi, \@index1, $rt2);
-    my $ft3 = &interp1(\@fti, \@index1, $rt2);
-
-    # delay is average of rising and falling
-    my $delay = ($cr2 + $cf3)/2;
-    return $delay;
-    
-#    print("tt $tt cr0 $cr0 rt0 $rt0\n");
-#    print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n");
-}
-
-sub interp2 {
-    my $matref = shift;
-    my @matrix = @$matref;
-    my $fo4cap = shift;
-    my @interp = ();
-    
-    my $i;
-    # interpolate row by row
-    for ($i=0; $i <= $#index1; $i++) {
-	my @row = @{$matrix[$i]};
-	#print ("Extracted row $i = @row\n");
-	$interp[$i] = &interp1(\@row, \@index2, $fo4cap);
-    }
-    return @interp;
-}
-
-sub interp1 {
-    my $vecref = shift;
-    my @vec = @$vecref;
-    my $indexref = shift;
-    my @index = @$indexref;
-    my $x = shift;
-
-    # find entry i containing the first index greater than x
-    my $i = 0;
-    while ($index[$i] < $x) {$i++}
-    my $start = $index[$i-1];
-    my $end = $index[$i];
-    my $fract = ($x-$start)/($end-$start);
-    my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract;
-
-#    print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n");
-
-    return $interp;
-}
-
-sub parseVals {
-    # relies on global variables @values, @index1, @index2
-    my @vals;
-    my $i; my $j;
-    for ($i=0; $i <= $#index1; $i++) {
-	my @row = split(/, /,$values[$i]);
-	for ($j = 0; $j <= $#index2; $j++) {
-	    $vals[$i][$j] = $row[$j];
-	}
-    }
-    return @vals;
-}
-
-sub printMatrix {
-    my $mat = shift;
-    my @matrix = @$mat;
-    my $i; my $j;
-    for ($i=0; $i <= $#index1; $i++) {
-	for ($j = 0; $j <= $#index2; $j++) {
-	    print($matrix[$i][$j]." ");
-	}
-	print("\n");
-    }
-}
-
-    
-    
-
-
-
diff --git a/bin/lint-wally b/bin/lint-wally
deleted file mode 100755
index 692d8667b..000000000
--- a/bin/lint-wally
+++ /dev/null
@@ -1,55 +0,0 @@
-#!/bin/bash
-# check for warnings in Verilog code
-# The verilator lint tool is faster and better than Questa so it is best to run this first.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-verilator=$(which verilator)
-
-basepath=$(dirname "$0")/..
-RED='\033[0;31m'
-GREEN='\033[0;32m'
-NC='\033[0m' # No Color
-fails=0
-
-if [ "$1" == "--nightly" ]; then
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) 
-    derivconfigs=$(ls "$WALLY"/config/deriv)
-    for entry in $derivconfigs
-    do
-        if [[ $entry != *"syn_sram"* ]]; then  # ignore syn_sram* configs that contain undefined module
-            configs[${#configs[@]}]=$entry
-        fi
-    done
-else
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
-fi
-
-for config in ${configs[@]}; do
-#    echo "$config linting..."
-    if ! ($verilator --lint-only --quiet --top-module wallywrapper \
-         "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
-         $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
-         -Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
-        if [ "$1" == "-nightly" ]; then
-            echo -e "${RED}$config failed lint${NC}"
-            fails=$((fails+1))
-        else
-            echo -e "${RED}$config fails with lint errors or warnings"
-            exit 1
-        fi
-    else
-        echo -e "${GREEN}$config passed lint${NC}"
-    fi
-done
-if [ $fails -gt 0 ]; then
-    echo -e "${RED}Linting failed for $fails of ${#configs[@]} configurations${NC}"
-    exit 1
-fi
-echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings${NC}"
-
-# --lint-only just runs lint rather than trying to compile and simulate
-# -I points to the include directory where files such as `include config.vh  are found
-
-# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
-# verilator --lint-only -Wall --quiet --top-module wallywrapper -Iconfig/shared -Iconfig/rv64gc src/cvw.sv testbench/wallywrapper.sv src/*/*.sv src/*/*/*.sv -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY
-# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
diff --git a/bin/nightly_build.py b/bin/nightly_build.py
deleted file mode 100755
index 9c6250eda..000000000
--- a/bin/nightly_build.py
+++ /dev/null
@@ -1,852 +0,0 @@
-#!/usr/bin/env python3
-"""
-Python Regression Build Automation Script
-
-This Python script serves the purpose of automating nightly regression builds for a software project. 
-The script is designed to handle the setup, execution, and reporting aspects of the regression testing process.
-
-Features:
-
-    1.  Nightly Regression Builds: The script is scheduled to run on a nightly basis, making and executing the regression builds.
-
-    2.  Markdown Report Generation: Upon completion of the regression tests, the script generates detailed reports in Markdown format. 
-        These reports provide comprehensive insights into the test results, including test cases executed, pass/fail status, and any encountered issues.    
-
-    3.  Email Notification: The script is configured to send out email notifications summarizing the regression test results. 
-        These emails serve as communication channels for stakeholders, providing them with timely updates on the software's regression status.
-
-Usage:
-                    shutil.rmtree(file)
-
-- The script is designed to be scheduled and executed automatically on a nightly basis using task scheduling tools such as Cronjobs. To create a cronjob do the following:
-    1)  Open Terminal:
-
-        Open your terminal application. This is where you'll enter the commands to create and manage cron jobs.
-
-    2)  Access the Cron Table:
-
-        Type the following command and press Enter:
-
-        crontab -e
-
-        This command opens the crontab file in your default text editor. If it's your first time, you might be prompted to choose a text editor.
-
-    3)  Edit the Cron Table:
-        The crontab file will open in your text editor. Each line in this file represents a cron job. You can now add your new cron job.
-
-    4)  Syntax:
-
-        Our cron job has the following syntax:
-        0 3 * * * BASH_ENV=~/.bashrc bash -l -c "*WHERE YOUR CVW IS MUST PUT FULL PATH*/cvw/bin/wrapper_nightly_runs.sh > *WHERE YOU WANT TO STORE LOG FILES/cron.log 2>&1" 
-
-        This cronjob sources the .bashrc file and executes the wrapper script as a user. 
-
-    5)  Double check:
-
-        Execute the following command to see your cronjobs:
-        
-        crontab -l
-
-Dependencies:
-    Python:
-        - os
-        - shutil
-        - datetime from datetime
-        - re
-        - markdown
-        - subprocess
-        - argparse
-        - logging
-
-    Bash:
-        - mutt (email sender)
-
-Conclusion:
-
-In summary, this Python script facilitates the automation of nightly regression builds, providing comprehensive reporting and email notification capabilities to ensure effective communication and monitoring of regression test results.
-"""
-
-import argparse
-import logging
-import os
-import re
-import shutil
-import subprocess
-import time
-from datetime import datetime
-from pathlib import Path
-
-import markdown
-
-
-class FolderManager:
-    """A class for managing folders and repository cloning."""
-
-    def __init__(self, basedir):
-        """
-        Initialize the FolderManager instance.
-
-        Args:
-            base_dir (str): The base directory where folders will be managed and repository will be cloned.
-        """
-        env_extract_var = 'WALLY'
-        if os.environ.get(env_extract_var):
-            self.base_dir = os.environ.get(env_extract_var)
-            self.base_parent_dir = os.path.dirname(self.base_dir)
-        else:
-            self.base_dir = basedir
-            self.base_parent_dir = self.base_dir
-
-        # logger.info(f"Base directory: {self.base_dir}")
-        # logger.info(f"Parent Base directory: {self.base_parent_dir}")
-
-
-    def create_folders(self, folders):
-        """
-        Create preliminary folders if they do not exist. 
-
-        Args:
-            folders (list): A list of folder names to be created.
-
-        Returns:
-            None
-        """
-        
-        for folder in folders:
-            if not os.path.exists(folder):
-                os.makedirs(folder)
-
-
-    def remove_folder(self, folders):
-        """
-        Delete a folder, including all of its contents
-
-        Args:
-            folders (list): A folder to be deleted
-        
-        Returns:
-            None
-        """
-
-        for folder in folders:
-            if os.path.exists(folder):
-                shutil.rmtree(folder)
-
-    def remove_stale_folders(self, folder, days_old=30):
-        """
-        Delete all folders over X days old in a folder. 
-
-        Args:
-            folder (str): Folder to delete folders and files from
-            days_old (int): Number of days old a file must be before deleting
-
-        Returns:
-            None
-        """
-        dirs = os.listdir(folder)
-        threshold = time.time() - days_old*86400
-        
-        for file in dirs:
-            file = os.path.join(folder, file)
-            file_mtime = os.stat(file).st_mtime
-            if file_mtime < threshold:
-                if os.path.isfile(file):
-                    os.remove(file)
-                elif os.path.isdir(file):
-                    shutil.rmtree(file)
-
-
-    def clone_repository(self, folder, repo_url):
-        """
-        Clone a repository into the 'cvw' folder if it does not already exist.
-
-        Args:
-            repo_url (str): The URL of the repository to be cloned.
-
-        Returns:
-            None
-        """
-        cvw = folder.joinpath("cvw")
-        tmp_folder = os.path.join(cvw, "tmp") # temprorary files will be stored in here
-        if not cvw.exists():
-            os.system(f"git clone --recurse-submodules {repo_url} {cvw}")
-            os.makedirs(tmp_folder)
-
-        # logger.info(f"Repository cloned: {repo_url}")
-
-class TestRunner:
-    """A class for making, running, and formatting test results."""
-
-    def __init__(self, logger, log_dir): 
-        self.todays_date = datetime.now().strftime("%Y-%m-%d")
-        self.current_datetime = datetime.now()
-        self.logger = logger
-        self.logger.info("Test runner object is initialized")
-        self.log_dir = log_dir
-        
-        
-    def copy_setup_script(self, folder):
-        """
-        Copy the setup script to the destination folder.
-
-        The setup script will be copied from the base directory to a specific folder structure inside the base directory.
-
-        Args:
-            folder: the "nightly-runs/repos/"
-            folder: the "nightly-runs/repos/"
-
-        Returns:
-            bool: True if the script is copied successfuly, False otherwise.
-        """
-        # Get today's date in YYYY-MM-DD format
-        self.todays_date = datetime.now().strftime("%Y-%m-%d")
-
-        # Define the source and destination paths
-        source_script = os.path.join(self.cvw, "setup_host.sh")
-        destination_folder = os.path.join(self.base_parent_dir, folder, self.todays_date, 'cvw')
-        
-        # Check if the source script exists
-        if not os.path.exists(source_script):
-            self.logger.error(f"Error: Source script '{source_script}' not found.")
-            return False
-
-
-        # Check if the destination folder exists, create it if necessary
-        if not os.path.exists(destination_folder):
-            self.logger.error(f"Error: Destination folder '{destination_folder}' not found.")
-            return False
-
-        # Copy the script to the destination folder
-        try:
-            shutil.copy(source_script, destination_folder)
-            self.logger.info(f"Setup script copied to: {destination_folder}")
-            return True
-        except Exception as e:
-            self.logger.error(f"Error copying setup script: {e}")
-            return False
-
-    
-    def set_env_var(self, envar, value):
-        """
-        Set an environment variable to a value
-
-        Args:
-            envar (str): Environment variable to set
-            value (str): New value for the environment variable
-
-        Returns:
-            None
-        """
-        self.logger.info(f"Setting {envar}={value}")
-        os.environ[envar] = value
-
-
-    def source_setup(self, folder):
-        """
-        Source a shell script.
-
-        Args:
-            script_path (str): Path to the script to be sourced.
-
-        Returns:
-            None
-        """
-        # find the new repository made
-        cvw = folder.joinpath("cvw")
-        self.logger.info(f"cvw is: {cvw}")
-
-        self.cvw = cvw
-        self.sim_dir = cvw.joinpath("bin")
-        self.base_parent_dir = folder
-        self.results_dir = folder.joinpath("results")
-
-        self.logger.info(f"Tests are going to be ran from: {self.cvw}")
-
-
-    def execute_makefile(self, makefile_path=None, target=None):
-        """
-        Execute a Makefile with optional target.
-
-        Args:
-            makefile_path (str): Path to the Makefile within the test repository
-            target (str, optional): Target to execute in the Makefile.
-
-        Returns:
-            True if the tests were made
-            False if the tests didnt pass
-        """
-        # Prepare the command to execute the Makefile
-        makefile_location = self.cvw.joinpath(makefile_path)
-        os.chdir(makefile_location)
-
-        if target: 
-            output_file = self.log_dir.joinpath(f"make-{target}-output.log")
-        else: output_file = self.log_dir.joinpath("make-output.log")
-
-        # Source setup script and execute make with target and cores/2
-        if target: 
-            command = [f"source {os.path.join(self.cvw, 'setup.sh')} > /dev/null && make {target} --jobs=$(($(nproc)/2))"]
-        else:
-            command = [f"source {os.path.join(self.cvw, 'setup.sh')} > /dev/null && make --jobs=$(($(nproc)/2))"]
-
-        self.logger.info(f"Command used in directory {makefile_location}: {' '.join(command)}")
-
-        # Execute the command using subprocess and save the output into a file
-        with open(output_file, "w") as f:
-            formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S")
-            f.write(formatted_datetime)
-            f.write("\n\n")
-            result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True, shell=True, executable="/bin/bash")
-        
-        # Execute the command using a subprocess and not save the output
-        #result = subprocess.run(command, text=True)
-
-        # Check the result
-        if result.returncode == 0:
-            self.logger.info(f"Tests have been made with target: {' '.join(command)}")
-            return True
-        else:
-            self.logger.error(f"Error making the tests. Command: {' '.join(command)}")
-            return False
-            
-    def run_tests(self, test_type=None, test_name=None, test_extensions=None):
-        """
-        Run a script through the terminal and save the output to a file.
-
-        Args:
-            test_name (str): The test name will allow the function to know what test to execute in the sim directory
-            test_type (str): The type such as python, bash, etc
-        Returns:
-            True and the output file location
-        """
-
-        # Prepare the function to execute the simulation
-        
-        output_file = self.log_dir.joinpath(f"{test_name}-output.log")
-        os.chdir(self.sim_dir)
-
-        # Source setup script and delete output from log on whatever test command gets run
-        command = f"source {os.path.join(self.cvw, 'setup.sh')} > /dev/null && "
-
-        if test_extensions:
-            commandext = [test_type, test_name] + test_extensions
-            self.logger.info(f"Command used to run tests in directory {self.sim_dir}: {test_type} {test_name} {' '.join(test_extensions)}")
-        else:
-            commandext = [test_type, test_name]
-            self.logger.info(f"Command used to run tests in directory {self.sim_dir}: {test_type} {test_name}")
-        command += " ".join(commandext)
-
-
-        # Execute the command using subprocess and save the output into a file
-        try:
-            with open(output_file, "w") as f:
-                formatted_datetime = self.current_datetime.strftime("%Y-%m-%d %H:%M:%S")
-                f.write(formatted_datetime)
-                f.write("\n\n")
-                result = subprocess.run(command, stdout=f, stderr=subprocess.STDOUT, text=True, shell=True, executable="/bin/bash")
-        except Exception as e:
-            self.logger.error(f"There was an error in running the tests in the run_tests function: {e}")
-        # Check if the command executed successfuly
-        if result.returncode or result.returncode == 0:
-            self.logger.info(f"Test ran successfuly. Test name: {test_name}, test extension: {' '.join(test_extensions)}")
-            return True, output_file
-        else:
-            self.logger.error(f"Error making test. Test name: {test_name}, test extension: {' '.join(test_extensions)}")
-            return False, output_file
-
-
-    def copy_sim_logs(self, sim_log_folders):
-        """
-        Save script outputs from a directory back into the main log directory.
-
-        Args:
-            sim_log_folders (list): Locations to grab logs from. Will name new log folder the directory 
-            the log directory is in
-        Returns:
-            None
-        """
-
-        for sim_log_folder in sim_log_folders:
-            try:
-                log_folder_name = os.path.basename(sim_log_folder)
-                self.logger.info(f"{log_folder_name}")
-                sim_folder_name = os.path.basename(os.path.dirname(sim_log_folder))
-                new_log_folder = self.log_dir / sim_folder_name
-                self.logger.info(f"Copying {sim_log_folder} to {new_log_folder}")
-                shutil.copytree(sim_log_folder, new_log_folder)
-            except Exception as e:
-                self.logger.error(f"There was an error copying simulation logs from {sim_log_folder} to {new_log_folder}: {e}")
-
-
-    def clean_format_output(self, input_file, output_file=None):
-        """
-        Clean and format the output from tests.
-
-        Args:
-            input_file (str): Path to the input file with raw test results.
-            output_file (str): Path to the file where cleaned and formatted output will be saved.
-
-        Returns:
-            None
-        """
-        # Implement cleaning and formatting logic here
-
-        # Open up the file with only read permissions
-        with open(input_file) as input_file:
-            uncleaned_output = input_file.read()
-
-        # use something like this function to detect pass and fail
-        passed_configs = []
-        failed_configs = []
-
-        lines = uncleaned_output.split('\n')
-        index = 0
-
-        while index < len(lines):
-            # Remove ANSI escape codes
-            line = re.sub(r'\x1b\[[0-9;]*[mGK]', '', lines[index])  
-            
-            if "Success" in line: # test succeeds
-                passed_configs.append(line.split(':')[0].strip())
-            elif "passed lint" in line:
-                passed_configs.append(f"Lint: {line.split(' ')[0].strip()}")
-                #passed_configs.append(line) # potentially use a space
-            elif "failed lint" in line:
-                failed_configs.append([f"Lint: {line.split(' ')[0].strip()}", "No Log File"])
-                #failed_configs.append(line)
-
-            elif "Failures detected in output" in line: # Text explicitly fails
-                try:
-                    config_name = line.split(':')[0].strip()
-                    log_file = os.path.abspath(os.path.join("logs", config_name))
-                    failed_configs.append((config_name, log_file))
-                except:
-                    failed_configs.append((config_name, "Log file not found"))
-
-            elif "Timeout" in line: # Test times out
-                try:
-                    config_name = line.split(':')[0].strip()
-                    log_file = os.path.abspath("logs/"+config_name+".log")
-                    failed_configs.append((f"Timeout: {config_name}", log_file))
-                except:
-                    failed_configs.append((f"Timeout: {config_name}", "No Log File"))
-            
-
-            index += 1
-
-        # alphabetically sort the configurations
-        if len(passed_configs) != 0:
-            passed_configs.sort()
-
-        if len(failed_configs) != 0:
-            failed_configs.sort()
-        self.logger.info(f"Cleaned test results. Passed configs {passed_configs}. Failed configs: {failed_configs}")
-        return passed_configs, failed_configs
-
-    def rewrite_to_markdown(self, test_name, passed_configs, failed_configs):
-        """
-        Rewrite test results to markdown format.
-
-        Args:
-            input_file (str): Path to the input file with cleaned and formatted output.
-            markdown_file (str): Path to the markdown file where test results will be saved.
-
-        Returns:
-            None
-        """
-        # Implement markdown rewriting logic here
-
-        # output_directory = self.base_parent_dir.joinpath("results")
-        os.chdir(self.results_dir)
-        # current_directory = os.getcwd()
-        output_file = os.path.join(self.results_dir, f"{test_name}.md")
-        
-
-        with open(output_file, 'w') as md_file:
-
-            # Title
-            md_file.write(f"\n\n# Regression Test Results - {self.todays_date}\n\n")
-            #md_file.write(f"\n\n<div class=\"regression\">\n# Regression Test Results - {timestamp}\n</div>\n\n")
-
-            # File Path
-            md_file.write(f"\n**File:** {output_file}\n\n")
-
-            if failed_configs:
-                md_file.write("## Failed Configurations\n\n")
-                for config, log_file in failed_configs:
-                    md_file.write(f'- <span class="failure" style="color: red;">{config}</span> ({log_file})\n')
-                md_file.write("\n")
-            else:
-                md_file.write("## Failed Configurations\n")
-                md_file.write("No Failures\n")
-            
-            md_file.write("\n## Passed Configurations\n")
-            for config in passed_configs:
-                md_file.write(f'- <span class="success" style="color: green;">{config}</span>\n')
-
-        self.logger.info("writing test outputs to markdown")
-
-    def combine_markdown_files(self, passed_tests, failed_tests, test_list, total_number_failures, total_number_success, test_type="default", markdown_file=None, args=None):
-        """
-        First we want to display the server properties like:
-            - Server full name
-            - Operating System
-
-        Combine the markdown files and format them to display all of the failures at the top categorized by what kind of test it was
-        Then display all of the successes.
-
-        Args:
-            passed_tests (list): a list of successful tests
-            failed_tests (list): a list of failed tests
-            test_list (list): a list of the test names. 
-            markdown_file (str): Path to the markdown file where test results will be saved.
-
-        Returns:
-            None
-        """
-
-        os.chdir(self.results_dir)
-        output_file = self.results_dir.joinpath("results.md")
-        
-
-        with open(output_file, 'w') as md_file:
-            # Title
-            md_file.write(f"\n\n# Nightly Test Results - {self.todays_date}\n\n")
-            # Host information
-            try:
-                # Run hostname command
-                hostname = subprocess.check_output(['hostname', '-A']).strip().decode('utf-8')
-                md_file.write(f"**Host name:** {hostname}")
-                md_file.write("\n")
-                # Run uname command to get OS information
-                os_info = subprocess.check_output(['uname', '-a']).strip().decode('utf-8')
-                md_file.write(f"\n**Operating System Information:** {os_info}")
-                md_file.write("\n")
-
-                md_file.write(f"\n**Command used to execute test:** python nightly_build.py --path {args.path} --repository {args.repository} --target {args.target} --send_email {args.send_email}")
-                md_file.write("\n")
-            except subprocess.CalledProcessError as e:
-                # Handle if the command fails
-                md_file.write(f"Failed to identify host and Operating System information: {e!s}")
-            
-            # Which tests did we run
-            md_file.write(f"\n**Tests made:** `make {test_type}`\n")
-
-            # File Path
-            md_file.write(f"\n**File:** {output_file}\n\n") # *** needs to be changed
-            md_file.write(f"**Total Successes: {total_number_success}**\n")
-            md_file.write(f"**Total Failures: {total_number_failures}**\n")
-
-            # Failed Tests
-            md_file.write("\n\n## Failed Tests")
-            md_file.write(f"\n**Total failed tests: {total_number_failures}**")
-            for (test_item, item) in zip(test_list, failed_tests):
-                md_file.write(f"\n\n### {test_item[1]} test")
-                md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {' '.join(test_item[2])}\n\n")
-                md_file.write("**Failed Tests:**\n")
-
-                
-
-                if len(item) == 0:
-                    md_file.write("\n")
-                    md_file.write('* <span class="no-failure" style="color: green;">No failures</span>\n')
-                    md_file.write("\n")
-                else:
-                    for failed_test in item:
-                        config = failed_test[0]
-                        log_file = failed_test[1]
-
-                        md_file.write("\n")
-                        md_file.write(f'* <span class="failure" style="color: red;">{config}</span> ({log_file})\n')
-                        md_file.write("\n")
-            # Successful Tests
-
-            md_file.write("\n\n## Successful Tests")
-            md_file.write(f"\n**Total successful tests: {total_number_success}**")
-            for (test_item, item) in zip(test_list, passed_tests):
-                md_file.write(f"\n\n### {test_item[1]} test")
-                md_file.write(f"\n**Command used:** {test_item[0]} {test_item[1]} {' '.join(test_item[2])}\n\n")
-                md_file.write("\n**Successful Tests:**\n")
-
-                
-
-                if len(item) == 0:
-                    md_file.write("\n")
-                    md_file.write('* <span class="no-successes" style="color: red;">No successes</span>\n')
-                    md_file.write("\n")
-                else:
-                    for passed_tests in item:
-                        config = passed_tests
-                        
-                        md_file.write("\n")
-                        md_file.write(f'* <span class="success" style="color: green;">{config}</span>\n')
-                        md_file.write("\n")
-                    
-        self.logger.info("Combining markdown files")
-
-
-    def convert_to_html(self, markdown_file="results.md", html_file="results.html"):
-        """
-        Convert markdown file to HTML.
-
-        Args:
-            markdown_file (str): Path to the markdown file.
-            html_file (str): Path to the HTML file where converted output will be saved.
-
-        Returns:
-            None
-        """
-        # Implement markdown to HTML conversion logic here
-        os.chdir(self.results_dir)
-
-        with open(markdown_file) as md_file:
-            md_content = md_file.read()
-            html_content = markdown.markdown(md_content)
-        
-        with open(html_file, 'w') as html_file:
-            html_file.write(html_content)
-        
-        self.logger.info("Converting markdown file to html file.")
-
-    def send_email(self, receiver_emails=None, subject="Nightly Regression Test"):
-        """
-        Send email with HTML content. 
-        
-        !!! Requires mutt to be set up to send emails !!!
-
-        Args:
-            self: The instance of the class.
-            sender_email (str): The sender's email address. Defaults to None.
-            receiver_emails (list[str]): List of receiver email addresses. Defaults to None.
-            subject (str, optional): Subject of the email. Defaults to "Nightly Regression Test".
-
-        Returns:
-            None
-        """
-
-        # check if there are any emails
-        if not receiver_emails:
-            self.logger.error("No receiver emails provided.")
-            return
-
-        # grab the html file
-        os.chdir(self.results_dir)
-        html_file = "results.html"
-
-        with open(html_file) as html_file:
-                body = html_file.read()
-
-        try:
-            for receiver_email in receiver_emails:
-                # Compose the mutt command for each receiver email
-                command = [
-                    '/usr/bin/mutt',
-                    '-s', subject,
-                    '-e', 'set content_type=text/html',
-                    '--', receiver_email
-                ]
-                try:
-                    # Open a subprocess to run the mutt command
-                    process = subprocess.Popen(command, stdin=subprocess.PIPE)
-                    # Write the email body to the subprocess
-                    process.communicate(body.encode('utf-8'))
-                    self.logger.info(f"Sent email to {receiver_email}")
-                except Exception as identifier:
-                    self.logger.error(f"Error sending email with error: {identifier}")
-        except Exception as identifier:
-            self.logger.error(f"Error sending email with error: {identifier}")
-
-
-
-def main():
-    #############################################
-    #                 ARG PARSER                #
-    #############################################
-
-    parser = argparse.ArgumentParser(description='Nightly Verification Testing for WALLY.')
-
-    parser.add_argument('--path',default = "nightly", help='specify the path for where the nightly repositories will be cloned ex: "nightly-runs')
-    parser.add_argument('--repository',default = "https://github.com/openhwgroup/cvw", help='specify which github repository you want to clone')
-    parser.add_argument('--target', default = "", help='types of tests you can make are: all, wally-riscv-arch-test, no')
-    parser.add_argument('--tests', default = "nightly", help='types of tests you can run are: nightly, test, test_lint')
-    parser.add_argument('--send_email',default = "", nargs="+", help='What emails to send test results to. Example: "[email1],[email2],..."')
-
-    args = parser.parse_args()
-
-    #############################################
-    #                 SETUP                     #
-    #############################################
-
-    receiver_emails = args.send_email
-
-    # file paths for where the results and repos will be saved: repos and results can be changed to whatever
-    today = datetime.now().strftime("%Y-%m-%d")
-    cvw_path = Path.home().joinpath(args.path, today)
-    results_path = Path.home().joinpath(args.path, today, "results")
-    log_path = Path.home().joinpath(args.path, today, "logs")
-    log_file_path = log_path.joinpath("nightly_build.log")
-    # creates the object
-    folder_manager = FolderManager(basedir=args.path)
-
-    # setting the path on where to clone new repositories of cvw
-    folder_manager.create_folders([cvw_path, results_path, log_path])
-
-    # clone the cvw repo
-    folder_manager.clone_repository(cvw_path, args.repository)
-
-    # Define tests that we can run
-    #
-    # flags are a list
-    if (args.tests == "all"):
-        test_list = [["python", "./regression-wally", ["--nightly", "--buildroot"]]]
-    elif (args.tests == "nightly"):
-        test_list = [["python", "./regression-wally", ["--nightly"]]]
-    elif (args.tests == "regression"):
-        test_list = [["python", "./regression-wally", []]]
-    elif (args.tests == "lint"):
-        test_list = [["bash", "./lint-wally", ["--nightly"]]]
-    else:
-        print(f"Error: Invalid test {args.tests} specified")
-        raise SystemExit
-
-    #############################################
-    #                 LOGGER                    #
-    #############################################
-    
-
-    # Set up the logger
-    logger = logging.getLogger(__name__)
-    logger.setLevel(logging.DEBUG)
-
-    # Create a file handler
-    #file_handler = logging.FileHandler('../../logs/nightly_build.log')
-    
-    file_handler = logging.FileHandler(log_file_path)
-    file_handler.setLevel(logging.DEBUG)
-
-    # Create a console handler
-    console_handler = logging.StreamHandler()
-    console_handler.setLevel(logging.INFO)
-
-    # Create a formatter and add it to the handlers
-    formatter = logging.Formatter('%(asctime)s - %(levelname)s - %(message)s')
-    file_handler.setFormatter(formatter)
-    console_handler.setFormatter(formatter)
-
-    # Add the handlers to the logger
-    logger.addHandler(file_handler)
-    logger.addHandler(console_handler)
-
-    logger.info(f"arg parser path: {args.path}")
-    logger.info(f"arg parser repository: {args.repository}")
-    logger.info(f"arg parser target: {args.target}")
-    logger.info(f"arg parser send_email: {args.send_email}")
-    logger.info(f"cvw path: {cvw_path}")
-    logger.info(f"results path: {results_path}")
-    logger.info(f"log folder path: {log_path}")
-    logger.info(f"log file path: {log_file_path}")
-    
-
-    test_runner = TestRunner(logger, log_path) # creates the object
-    test_runner.source_setup(cvw_path) # ensures that the new WALLY environmental variable is set correctly
-    #############################################
-    #              MAKE TESTS                   #
-    #############################################
-
-    if args.target != "no":
-        test_runner.execute_makefile(target = args.target, makefile_path=test_runner.cvw)
-
-    #############################################
-    #               RUN TESTS                   #
-    #############################################
-
-
-    output_log_list = [] # a list where the output markdown file locations will be saved to
-    total_number_failures = 0  # an integer where the total number failures from all of the tests will be collected
-    total_number_success = 0    # an integer where the total number of sucess will be collected
-
-    total_failures = []
-    total_success = []
-
-    for test_type, test_name, test_extensions in test_list:
-        
-        check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_extensions=test_extensions)
-        try:
-            if check: # this checks if the test actually ran successfuly
-                output_log_list.append(output_location)
-                logger.info(f"{test_name} ran successfuly. Output location: {output_location}")
-                # format tests to markdown
-                try:
-                    passed, failed = test_runner.clean_format_output(input_file = output_location)
-                    logger.info(f"{test_name} has been formatted to markdown")
-                except:
-                    logger.error(f"Error occured with formatting {test_name}")
-
-                logger.info(f"The # of failures are for {test_name}: {len(failed)}")
-                total_number_failures+= len(failed)
-                total_failures.append(failed)
-
-                logger.info(f"The # of sucesses are for {test_name}: {len(passed)}")
-                total_number_success += len(passed)
-                total_success.append(passed)
-                test_runner.rewrite_to_markdown(test_name, passed, failed)
-                
-                newlinechar = "\n"
-                logger.info(f"Failed tests: \n{newlinechar.join([x[0] for x in failed])}")
-    
-        except Exception as e:
-            logger.error(f"There was an error in running the tests: {e}")
-
-    logger.info(f"The total sucesses for all tests ran are: {total_number_success}")
-    logger.info(f"The total failures for all tests ran are: {total_number_failures}")
-
-    # Copy actual test logs from sim/questa, sim/verilator, sim/vcs
-    if args.tests != 'test_lint':
-        test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs", test_runner.cvw / "sim/vcs/logs"])
-
-    #############################################
-    #               FORMAT TESTS                #
-    #############################################
-
-    # Combine multiple markdown files into one file
-    try:
-        test_runner.combine_markdown_files(passed_tests = total_success, failed_tests = total_failures, test_list = test_list, total_number_failures = total_number_failures, total_number_success = total_number_success, test_type=args.target, markdown_file=None, args=args)
-    except Exception as e:
-        logger.error(f"Error combining the markdown tests called from main: {e}")
-
-    #############################################
-    #             WRITE MD TESTS                #
-    #############################################
-    test_runner.convert_to_html()
-
-
-    #############################################
-    #                SEND EMAIL                 #
-    #############################################
-
-    if receiver_emails:
-        test_runner.send_email(receiver_emails=receiver_emails)
-
-    #############################################
-    #   DELETE REPOSITORY OF PREVIOUS NIGHTLYS  #
-    #############################################
-    threshold = time.time() - 86400*1
-
-    for log_dir in os.listdir(args.path):
-        try:
-            cvw_dir = os.path.join(args.path,log_dir,"cvw")
-            cvw_mtime = os.stat(cvw_dir).st_mtime
-            if cvw_mtime < threshold:
-                    logger.info(f"Found {cvw_dir} older than 1 day, removing")
-                    shutil.rmtree(cvw_dir)
-        except Exception as e:
-            if os.path.exists(cvw_dir):
-                logger.info(f"ERROR: Failed to remove previous nightly run repo with error {e}")
-
-    #############################################
-    #      DELETE STALE LOGS AFTER TESTING      #
-    #############################################
-    folder_manager.remove_stale_folders(folder=args.path, days_old=30)
-
-if __name__ == "__main__":
-    main()
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index f845ba68c..2bc998e51 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -1,507 +1,178 @@
-#!/usr/bin/env python3
+#!/usr/bin/python3
 
-###########################################
-## Written: Rose Thompson rose@rosethompson.net
-## Created: 20 September 2023
-## Modified: 
-##
-## Purpose: Parses the performance counters from a modelsim trace.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-import argparse
-import math
 import os
 import sys
-
 import matplotlib.pyplot as plt
-import numpy as np
 
-WALLY = os.environ.get('WALLY')
+def ComputeCPI(benchmark):
+    'Computes and inserts CPI into benchmark stats.'
+    (nameString, opt, dataDict) = benchmark
+    CPI = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
+    dataDict['CPI'] = CPI
 
-RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151),
-           ('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082),
-           ('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015),
-           ('gshareCModel12', 'gshareCModel', 4096, 8192, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 32768, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 131072, 1.90424999467293)]
-RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 128, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 512, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 2048, 0.0117345454469572),
-              ('BTBCModel12', 'BTBCModel', 4096, 8192, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 32768, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 131072, 0.000732471628510962)]
+def ComputeBranchDirMissRate(benchmark):
+    'Computes and inserts branch direction miss prediction rate.'
+    (nameString, opt, dataDict) = benchmark
+    branchDirMissRate = 100.0 * int(dataDict['Br Dir Wrong']) / int(dataDict['Br Count'])
+    dataDict['BDMR'] = branchDirMissRate
 
-def ParseBranchListFile(path):
-    '''Take the path to the list of Questa Sim log files containing the performance counters outputs.  File
-    is formated in row columns.  Each row is a trace with the file, branch predictor type, and the parameters.
-    parameters can be any number and depend on the predictor type. Returns a list of lists.'''
-    lst = []
-    with open(path) as BranchList:
-        for line in BranchList:
-            tokens = line.split()
-            predictorLog = f"{WALLY}/sim/{args.sim}/logs/{tokens[0]}"
-            predictorType = tokens[1]
-            predictorParams = tokens[2::]
-            lst.append([predictorLog, predictorType, predictorParams])
-            #print(predictorLog, predictorType, predictorParams)
-    return lst
+def ComputeBranchTargetMissRate(benchmark):
+    'Computes and inserts branch target miss prediction rate.'
+    # *** this is wrong in the verilog test bench
+    (nameString, opt, dataDict) = benchmark
+    branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret']))
+    dataDict['BTMR'] = branchTargetMissRate
+
+def ComputeRASMissRate(benchmark):
+    'Computes and inserts return address stack miss prediction rate.'
+    (nameString, opt, dataDict) = benchmark
+    RASMPR = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['ret'])
+    dataDict['RASMPR'] = RASMPR
+
+def ComputeInstrClassMissRate(benchmark):
+    'Computes and inserts instruction class miss prediction rate.'
+    (nameString, opt, dataDict) = benchmark
+    ClassMPR = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
+    dataDict['ClassMPR'] = ClassMPR
     
+def ComputeICacheMissRate(benchmark):
+    'Computes and inserts instruction class miss prediction rate.'
+    (nameString, opt, dataDict) = benchmark
+    ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
+    dataDict['ICacheMR'] = ICacheMR
+
+def ComputeDCacheMissRate(benchmark):
+    'Computes and inserts instruction class miss prediction rate.'
+    (nameString, opt, dataDict) = benchmark
+    DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
+    dataDict['DCacheMR'] = DCacheMR
+
+def ComputeAll(benchmarks):
+    for benchmark in benchmarks:
+        ComputeCPI(benchmark)
+        ComputeBranchDirMissRate(benchmark)
+        ComputeBranchTargetMissRate(benchmark)
+        ComputeRASMissRate(benchmark)
+        ComputeInstrClassMissRate(benchmark)
+        ComputeICacheMissRate(benchmark)
+        ComputeDCacheMissRate(benchmark)
+    
+def printStats(benchmark):
+    (nameString, opt, dataDict) = benchmark
+    CPI = dataDict['CPI']
+    BDMR = dataDict['BDMR']
+    BTMR = dataDict['BTMR']
+    RASMPR = dataDict['RASMPR']
+    print('Test', nameString)
+    print('Compile configuration', opt)
+    print('CPI \t\t\t  %1.2f' % CPI)
+    print('Branch Dir Pred Miss Rate %2.2f' % BDMR)
+    print('Branch Target Pred Miss Rate %2.2f' % BTMR)
+    print('RAS Miss Rate \t\t  %1.2f' % RASMPR)
+    print('Instr Class Miss Rate  %1.2f' % dataDict['ClassMPR'])
+    print('I Cache Miss Rate  %1.4f' % dataDict['ICacheMR'])
+    print('D Cache Miss Rate  %1.4f' % dataDict['DCacheMR'])
+    print()
+
 def ProcessFile(fileName):
     '''Extract preformance counters from a modelsim log.  Outputs a list of tuples for each test/benchmark.
     The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
     # 1 find lines with Read memfile and extract test name
     # 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
     benchmarks = []
+    transcript = open(fileName, 'r')
     HPMClist = { }
     testName = ''
-    opt = ''
-    with open(fileName) as transcript:
-        for line in transcript.readlines():
-            lineToken = line.split()
-            if (args.sim == "questa") & (lineToken[0] == "#"):
-                lineToken = lineToken[1:] # Questa uses a leading # for each line, other simulators do not
-            if(len(lineToken) > 2 and lineToken[0] == 'Read' and lineToken[1] == 'memfile'):
-                opt = lineToken[2].split('/')[-4]
-                testName = lineToken[2].split('/')[-1].split('.')[0]
-                HPMClist = { }
-            elif(len(lineToken) > 3 and lineToken[0][0:3] == 'Cnt'):
-                countToken = line.split('=')[1].split()
-                value = int(countToken[0]) if countToken[0] != 'x' else 0
-                name = ' '.join(countToken[1:])
-                HPMClist[name] = value
-            elif ('is done' in line):
-                benchmarks.append((testName, opt, HPMClist))
+    for line in transcript.readlines():
+        lineToken = line.split()
+        if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
+            opt = lineToken[3].split('/')[-4]
+            testName = lineToken[3].split('/')[-1].split('.')[0]
+            HPMClist = { }
+        elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
+            countToken = line.split('=')[1].split()
+            value = int(countToken[0])
+            name = ' '.join(countToken[1:])
+            HPMClist[name] = value
+        elif ('is done' in line):
+            benchmarks.append((testName, opt, HPMClist))
     return benchmarks
 
+def ComputeAverage(benchmarks):
+    average = {}
+    for (testName, opt, HPMClist) in benchmarks:
+        for field in HPMClist:
+            value = HPMClist[field]
+            if field not in average:
+                average[field] = value
+            else:
+                average[field] += value
+    benchmarks.append(('All', '', average))
 
-def ComputeStats(benchmarks):
-    for benchmark in benchmarks:
-        (nameString, opt, dataDict) = benchmark
-        dataDict['CPI'] = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
-        dataDict['BDMR'] = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
-        dataDict['BTMR'] = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
-        dataDict['RASMPR'] = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
-        dataDict['ClassMPR'] = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
-        dataDict['ICacheMR'] = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
+def FormatToPlot(currBenchmark):
+    names = []
+    values = []
+    for config in currBenchmark:
+        print ('config' , config)
+        names.append(config[0])
+        values.append(config[1])
+    return (names, values)
 
-        cycles = int(dataDict['I Cache Miss'])
-        if(cycles == 0): ICacheMR = 0
-        else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
-        dataDict['ICacheMT'] = ICacheMR
+if(sys.argv[1] == '-b'):
+    configList = []
+    for config in sys.argv[2::]:
+        benchmarks = ProcessFile(config)
+        ComputeAverage(benchmarks)
+        ComputeAll(benchmarks)
+        configList.append((config.split('.')[0], benchmarks))
 
-        dataDict['DCacheMR'] = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
-
-        (nameString, opt, dataDict) = benchmark
-        cycles = int(dataDict['D Cache Miss'])
-        if(cycles == 0): DCacheMR = 0
-        else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
-        dataDict['DCacheMT'] = DCacheMR
-
-
-def ComputeGeometricAverage(benchmarks):
-    fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
-    AllAve = {}
-    for field in fields:
-        Product = 1
-        index = 0
-        for (testName, opt, HPMCList) in benchmarks:
-            #print(HPMCList)
-            value = HPMCList[field]
-            if(value != 0): Product *= value # if that value is 0 exclude from mean because it destories the geo mean
-            index += 1
-        AllAve[field] = Product ** (1.0/index)
-    benchmarks.append(('Mean', '', AllAve))
-
-def GenerateName(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
-        return predictorType + predictorParams[0]
-    elif(predictorType == 'local'):
-        return predictorType + predictorParams[0] + '_' + predictorParams[1]
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-
-def GenerateDisplayName(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
-        return predictorType
-    elif(predictorType == 'local'):
-        return predictorType + predictorParams[0]
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-
-def ComputePredNumEntries(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
-        return 2**int(predictorParams[0])
-    elif(predictorType == 'ras'):
-        return int(predictorParams[0])
-    elif(predictorType == 'local'):
-        return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-
-def ComputePredSize(predictorType, predictorParams):
-    if(predictorType == 'gshare' or  predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
-        return 2*2**int(predictorParams[0])
-    elif(predictorType == 'ras'):
-        return int(predictorParams[0])
-    elif(predictorType == 'local'):
-        return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2*2**int(predictorParams[1])
-    else:
-        print(f'Error unsupported predictor type {predictorType}')
-        sys.exit(-1)
-        
-def BuildDataBase(predictorLogs):
-    # Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
-    # raw performance counter data and the processed data on a per benchmark basis.  It also includes the geometric mean.
-    # list
-    #   branch predictor configuration 0 (tuple)
-    #     benchmark name
-    #     compiler optimization
-    #     data (dictionary)
-    #       dictionary of performance counters
-    #   branch predictor configuration 1 (tuple)
-    #     benchmark name (dictionary)
-    #     compiler optimization
-    #     data
-    #       dictionary of performance counters
-    # ...
-    performanceCounterList = []
-    for trace in predictorLogs:
-        predictorLog = trace[0]
-        predictorType = trace[1]
-        predictorParams = trace[2]
-        # Extract the performance counter data
-        performanceCounters = ProcessFile(predictorLog)
-        ComputeStats(performanceCounters)
-        ComputeGeometricAverage(performanceCounters)
-        #print(performanceCounters)
-        performanceCounterList.append([GenerateName(predictorType, predictorParams), GenerateDisplayName(predictorType, predictorParams), performanceCounters, ComputePredNumEntries(predictorType, predictorParams), ComputePredSize(predictorType, predictorParams)])
-    return performanceCounterList
-
-def ReorderDataBase(performanceCounterList):
-    # Reorder the data so the benchmark name comes first, then the branch predictor configuration
-    benchmarkFirstList = []
-    for (predictorName, predictorPrefixName, benchmarks, entries, size) in performanceCounterList:
+    # Merge all configruations into a single list
+    benchmarkAll = []
+    for (config, benchmarks) in configList:
+        print(config)
         for benchmark in benchmarks:
             (nameString, opt, dataDict) = benchmark
-            benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, size, dataDict))
-    return benchmarkFirstList
+            benchmarkAll.append((nameString, opt, config, dataDict))
 
-def ExtractSelectedData(benchmarkFirstList):
     # now extract all branch prediction direction miss rates for each
     # namestring + opt, config
     benchmarkDict = { }
-    for benchmark in benchmarkFirstList:
-        (name, opt, config, prefixName, entries, size, dataDict) = benchmark
-        #print(f'config = {config}, prefixName = {prefixName} entries = {entries}')
-        # use this code to distinguish speed opt and size opt.
-        #if opt == 'bd_speedopt_speed': NewName = name+'Sp'
-        #elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
-        #else: NewName = name
-        NewName = name
-        #print(NewName)
-        #NewName = name+'_'+opt
-        if NewName in benchmarkDict:
-            benchmarkDict[NewName].append((config, prefixName, entries, size, dataDict[ReportPredictorType]))
+    for benchmark in benchmarkAll:
+        (name, opt, config, dataDict) = benchmark
+        if name+'_'+opt in benchmarkDict:
+            benchmarkDict[name+'_'+opt].append((config, dataDict['BDMR']))
         else:
-            benchmarkDict[NewName] = [(config, prefixName, entries, size, dataDict[ReportPredictorType])]
-    return benchmarkDict
+            benchmarkDict[name+'_'+opt] = [(config, dataDict['BDMR'])]
 
-def ReportAsTable(benchmarkDict):
-    refLine = benchmarkDict['Mean']
-    FirstLine = []
-    SecondLine = []
-    for Elements in refLine:
-        (name, typ, size, entries, val) = Elements
-        FirstLine.append(name)
-        SecondLine.append(entries if not args.size else size)
-
-    sys.stdout.write('benchmark\t\t')
-    for name in FirstLine:
-        if(len(name) < 8): sys.stdout.write(f'{name}\t\t')
-        else: sys.stdout.write(f'{name}\t')        
-    sys.stdout.write('\n')
-    sys.stdout.write('size\t\t\t')
-    for size in SecondLine:
-        if(len(str(size)) < 8): sys.stdout.write(f'{size}\t\t')
-        else: sys.stdout.write(f'{size}\t')        
-    sys.stdout.write('\n')
-
-    if(args.summary):
-        sys.stdout.write('Mean\t\t\t')
-        for (name, typ, size, entries, val) in refLine:
-            sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
-        sys.stdout.write('\n')
-
-    if(not args.summary):
-        for benchmark in benchmarkDict:
-            length = len(benchmark)
-            if(length < 8): sys.stdout.write(f'{benchmark}\t\t\t')
-            elif(length < 16): sys.stdout.write(f'{benchmark}\t\t')
-            else: sys.stdout.write(f'{benchmark}\t')
-            for (name, typ, entries, size, val) in benchmarkDict[benchmark]:
-                sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
-            sys.stdout.write('\n')
-
-def ReportAsText(benchmarkDict):
-    if(args.summary):
-        mean = benchmarkDict['Mean']
-        print('Mean')
-        for (name, typ, entries, size, val) in mean:
-            sys.stdout.write(f'{name} {entries if not args.size else size} {val if not args.invert else 100 - val:0.2f}\n')
-        
-    if(not args.summary):
-        for benchmark in benchmarkDict:
-            print(benchmark)
-            for (name, prefixName, entries, size, val) in benchmarkDict[benchmark]:
-                sys.stdout.write(f'{name} {entries if not args.size else size} {val if not args.invert else 100 - val:0.2f}\n')
-
-def Inversion(lst):
-    return [x if not args.invert else 100 - x for x in lst]
-
-def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName, IncludeLegend):
-    index = 0
-    NumberInGroup = len(seriesDict)
-    # Figure out width of bars.  NumberInGroup bars + want 2 bar space
-    # the space between groups is 1
-    EffectiveNumInGroup = NumberInGroup + 2
-    barWidth = 1 / EffectiveNumInGroup
-    _ = plt.subplots(figsize = (EffectiveNumInGroup*BenchPerRow/8, 4))
-    colors = ['blue', 'blue', 'blue', 'blue', 'blue', 'blue', 'black', 'black', 'black', 'black', 'black', 'black']
-    for name in seriesDict:
-        values = seriesDict[name]
-        xpos = np.arange(len(values))
-        xpos = [x + index*barWidth for x in xpos]
-        plt.bar(xpos, Inversion(values), width=barWidth, edgecolor='grey', label=name, color=colors[index%len(colors)])
+    size = len(benchmarkDict)
+    index = 1
+    print('Number of plots', size)
+    for benchmarkName in benchmarkDict:
+        currBenchmark = benchmarkDict[benchmarkName]
+        (names, values) = FormatToPlot(currBenchmark)
+        print(names, values)
+        plt.subplot(6, 7, index)
+        plt.bar(names, values)
+        plt.title(benchmarkName)
+        plt.ylabel('BR Dir Miss Rate (%)')
+        #plt.xlabel('Predictor')
         index += 1
-    plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList)
-    plt.xlabel('Benchmark')
-    if(not args.invert): plt.ylabel('Misprediction Rate (%)')
-    else:  plt.ylabel('Prediction Accuracy (%)')
-    if(IncludeLegend): plt.legend(loc='upper right', ncol=2)
-    plt.savefig(FileName)
-
-def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow):
-    seriesDictTrunk = {}
-    for benchmarkName in seriesDictBig:
-        lst = seriesDictBig[benchmarkName]
-        seriesDictTrunk[benchmarkName] = lst[group*BenchPerRow:(group+1)*BenchPerRow]
-    xlabelListTrunk = xlabelListBig[group*BenchPerRow:(group+1)*BenchPerRow]
-    return(xlabelListTrunk, seriesDictTrunk)
-
-
-def ReportAsGraph(benchmarkDict, bar, FileName):
-    def FormatToPlot(currBenchmark):
-        names = []
-        sizes = []
-        values = []
-        typs = []
-        for config in currBenchmark:
-            names.append(config[0])
-            sizes.append(config[1])
-            values.append(config[2])
-            typs.append(config[3])
-        return (names, sizes, values, typs)
-    titlesInvert = {'BDMR' : 'Branch Direction Accuracy',
-              'BTMR' : 'Branch Target Accuracy',
-              'RASMPR': 'RAS Accuracy',
-              'ClassMPR': 'Class Prediction Accuracy'}
-    titles = {'BDMR' : 'Branch Direction Misprediction',
-              'BTMR' : 'Branch Target Misprediction',
-              'RASMPR': 'RAS Misprediction',
-              'ClassMPR': 'Class Misprediction'}
-    if(args.summary):
-        markers = ['x', '.', '+', '*', '^', 'o', ',', 's']
-        colors = ['blue', 'black', 'gray', 'dodgerblue', 'lightsteelblue', 'turquoise', 'black', 'blue']
-
-        # the benchmarkDict['Mean'] contains sequencies of results for multiple
-        # branch predictors with various parameterizations
-        # group the parameterizations by the common typ.
-        sequencies = {}
-        for (name, typ, entries, size, value) in benchmarkDict['Mean']:
-            if typ not in sequencies:
-                sequencies[typ] = [(entries if not args.size else int(size/8), value)]
-            else:
-                sequencies[typ].append((entries if not args.size else int(size/8) ,value))
-        # then graph the common typ as a single line+scatter plot
-        # finally repeat for all typs of branch predictors and overlay
-        fig, axes = plt.subplots()
-        index = 0
-        if(args.invert): plt.title(titlesInvert[ReportPredictorType])
-        else: plt.title(titles[ReportPredictorType])
-        for branchPredName in sequencies:
-            data = sequencies[branchPredName]
-            (xdata, ydata) = zip(*data) 
-            if args.invert: ydata = [100 - x for x in ydata]
-            axes.plot(xdata, ydata, color=colors[index])
-            axes.scatter(xdata, ydata, label=branchPredName, color=colors[index], marker=markers[index])
-            index = (index + 1) % len(markers)
-        axes.legend(loc='upper left')
-        axes.set_xscale("log")
-        axes.set_ylabel('Prediction Accuracy')
-        Xlabel = 'Entries' if not args.size else 'Size (bytes)'
-        axes.set_xlabel(Xlabel)
-        axes.set_xticks(xdata)
-        axes.set_xticklabels(xdata)
-        axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
-        if FileName is None: plt.show()
-        else: plt.savefig(FileName)        
-
-    # if(not args.summary):
-    #     size = len(benchmarkDict)
-    #     sizeSqrt = math.sqrt(size)
-    #     isSquare = math.isclose(sizeSqrt, round(sizeSqrt))
-    #     numCol = math.floor(sizeSqrt)
-    #     numRow = numCol + (0 if isSquare else 1)
-    #     index = 1
-    #     fig = plt.figure()
-    #     for benchmarkName in benchmarkDict:
-    #         currBenchmark = benchmarkDict[benchmarkName]
-    #         (names, typs, sizes, values) = FormatToPlot(currBenchmark)
-    #         #axes.plot(numRow, numCol, index)
-    #         ax = fig.add_subplot(numRow, numCol, index)
-    #         ax.bar(names, values)
-    #         ax.title.set_text(benchmarkName)
-    #         #plt.ylabel('BR Dir Miss Rate (%)')
-    #         #plt.xlabel('Predictor')
-    #         index += 1
-
-    if(not args.summary):
-        NumBenchmarks = len(benchmarkDict)
-        # NumBenchmarksSqrt = math.sqrt(NumBenchmarks)
-        # isSquare = math.isclose(NumBenchmarksSqrt, round(NumBenchmarksSqrt))
-        # numCol = math.floor(NumBenchmarksSqrt)
-        # numRow = numCol + (0 if isSquare else 1)
-        index = 1
-        BenchPerRow = 5
-
-        xlabelList = []
-        seriesDict = {}
-
-        for benchmarkName in benchmarkDict:
-            currBenchmark = benchmarkDict[benchmarkName]
-            xlabelList.append(benchmarkName)
-            for (name, typ, entries, size, value) in currBenchmark:
-                if(name not in seriesDict):
-                    seriesDict[name] = [value]
-                else:
-                    seriesDict[name].append(value)
-            if(index >= BenchPerRow): break
-            index += 1
-
-        xlabelListBig = []
-        seriesDictBig = {}
-        for benchmarkName in benchmarkDict:
-            currBenchmark = benchmarkDict[benchmarkName]
-            xlabelListBig.append(benchmarkName)
-            for (name, typ, entries, size, value) in currBenchmark:
-                if(name not in seriesDictBig):
-                    seriesDictBig[name] = [value]
-                else:
-                    seriesDictBig[name].append(value)
-
-        #The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code
-        # on each piece.
-        for row in range(0, math.ceil(NumBenchmarks / BenchPerRow)):
-            (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow)
-            FileName = f'barSegment{row}.svg'
-            groupLen = len(xlabelListTrunk)
-            BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName, (row == 0))
-
-
-# main
-parser = argparse.ArgumentParser(description='Parses performance counters from a Questa Sim trace to produce a graph or graphs.')
-
-# parse program arguments
-metric = parser.add_mutually_exclusive_group()
-metric.add_argument('-r', '--ras', action='store_const', help='Plot return address stack (RAS) performance.', default=False, const=True)
-metric.add_argument('-d', '--direction', action='store_const', help='Plot direction prediction (2-bit, Gshare, local, etc) performance.', default=False, const=True)
-metric.add_argument('-t', '--target', action='store_const', help='Plot branch target buffer (BTB) performance.', default=False, const=True)
-metric.add_argument('-c', '--iclass', action='store_const', help='Plot instruction classification performance.', default=False, const=True)
-
-parser.add_argument('-s', '--summary', action='store_const', help='Show only the geometric average for all benchmarks.', default=False, const=True)
-parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
-parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s.  If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
-parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
-parser.add_argument('--size', action='store_const', help='Display x-axis as size in bits rather than number of table entries', default=False, const=True)
-
-displayMode = parser.add_mutually_exclusive_group()
-displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--table', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--gui', action='store_const', help='Display in text format only.', default=False, const=True)
-displayMode.add_argument('--debug', action='store_const', help='Display in text format only.', default=False, const=True)
-parser.add_argument('sources', nargs=1, help='File lists the input Questa transcripts to process.')
-parser.add_argument('sim', choices=["questa", "verilator", "vcs"], help='Simulator that was used to generate logs. This is used to find the files specified in the sources file.')
-parser.add_argument('FileName', metavar='FileName', type=str, nargs='?', help='output graph to file <name>.png If not included outputs to screen.', default=None)
-
-args = parser.parse_args()
-
-# Figure what we are reporting
-ReportPredictorType = 'BDMR'  # default
-if(args.ras): ReportPredictorType = 'RASMPR'
-if(args.target): ReportPredictorType = 'BTMR'
-if(args.iclass): ReportPredictorType = 'ClassMPR'
-
-# Figure how we are displaying the data
-ReportMode = 'gui' # default
-if(args.text): ReportMode = 'text'
-if(args.table): ReportMode = 'table'
-if(args.debug): ReportMode = 'debug'
-
-# read the questa sim list file.
-# row, col format.  each row is a questa sim run with performance counters and a particular
-# branch predictor type and size. size can be multiple parameters for more complex predictors like
-# local history and tage.
-# <file> <type> <size>
-predictorLogs = ParseBranchListFile(args.sources[0])          # digests the traces
-performanceCounterList = BuildDataBase(predictorLogs)         # builds a database of performance counters by trace and then by benchmark
-benchmarkFirstList = ReorderDataBase(performanceCounterList)  # reorder first by benchmark then trace
-benchmarkDict = ExtractSelectedData(benchmarkFirstList)       # filters to just the desired performance counter metric
-
-if(args.reference and args.direction): benchmarkDict['Mean'].extend(RefDataBP)
-if(args.reference and args.target): benchmarkDict['Mean'].extend(RefDataBTB)
-#print(benchmarkDict['Mean'])
-#print(benchmarkDict['aha-mont64Speed'])
-#print(benchmarkDict)
-
-# table format
-if(ReportMode == 'table'):
-    ReportAsTable(benchmarkDict)
-
-if(ReportMode == 'text'):
-    ReportAsText(benchmarkDict)
-
-if(ReportMode == 'gui'):
-    ReportAsGraph(benchmarkDict, args.bar, args.FileName)
+    #plt.tight_layout()
+    plt.show()
+    
             
-# *** this is only needed of -b (no -s)
+else:
+    # steps 1 and 2
+    benchmarks = ProcessFile(sys.argv[1])
+    ComputeAverage(benchmarks)
+    # 3 process into useful data
+    # cache hit rates
+    # cache fill time
+    # branch predictor status
+    # hazard counts
+    # CPI
+    # instruction distribution
+    ComputeAll(benchmarks)
+    for benchmark in benchmarks:
+        printStats(benchmark)
 
-# debug
-#config0 = performanceCounterList[0][0]
-#data0 = performanceCounterList[0][1]
-#bench0 = data0[0]
-#bench0name = bench0[0]
-#bench0data = bench0[2]
-#bench0BrCount = bench0data['Br Count']
-#bench1 = data0[1]
-
-#print(data0)
-#print(bench0)
-#print(bench1)
-
-#print(bench0name)
-#print(bench0BrCount)
diff --git a/bin/regression-wally b/bin/regression-wally
deleted file mode 100755
index be2e77480..000000000
--- a/bin/regression-wally
+++ /dev/null
@@ -1,557 +0,0 @@
-#!/usr/bin/env python3
-##################################
-#
-# regression-wally
-# David_Harris@Hmc.edu 25 January 2021
-# Modified by Jarred Allen <jaallen@g.hmc.edu> and many others
-# jcarlin@hmc.edu December 2024
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Run a regression with multiple configurations in parallel and exit with
-# non-zero status code if an error happened, as well as printing human-readable
-# output.
-#
-##################################
-import argparse
-import multiprocessing
-import os
-import shutil
-import sys
-from collections import namedtuple
-from multiprocessing import Pool
-from multiprocessing import TimeoutError as MPTimeoutError
-
-# Globals
-WALLY = os.environ.get('WALLY')
-regressionDir = f'{WALLY}/sim'
-archVerifDir = f'{WALLY}/addins/cvw-arch-verif'
-coveragesim = "questa"     # Questa is required for code/functional coverage
-defaultsim = "verilator"   # Default simulator for all other tests
-lockstepsim = "questa"
-testfloatsim = "questa"    # change to Verilator when Issue #707 about testfloat not running Verilator is resolved
-
-
-##################################
-# Define lists of configurations and tests to run on each configuration
-##################################
-
-# The tests are a list with one element for each configuration
-# The element consists of the configuration name, a list of test suites to run,
-# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
-
-standard_tests = [
-        ["rv32e", ["arch32e"]],
-        ["rv32i", ["arch32i"]],
-        ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]], 
-        ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
-                    "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
-                    "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
-                    "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
-                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh", "arch32vm_sv32", "arch32pmp"]],
-        ["rv64i", ["arch64i"]],
-        ["rv64gc", ["arch64f", "arch64d", "arch64zfh", "arch64f_fma", "arch64d_fma", "arch64zfh_fma", "arch64f_divsqrt",
-                    "arch64d_divsqrt", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad", "coverage64gc", "arch64i", "arch64priv",
-                    "arch64c",  "arch64m", "arch64zcb", "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc",
-                    "wally64periph", "wally64priv", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
-                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs", "arch64pmp"]], # add when working:  "arch64zicboz"
-    ]
-
-# Separate test for short buildroot run through OpenSBI UART output
-tests_buildrootshort = [
-                    ["buildroot", ["buildroot"], "--args +INSTR_LIMIT=1600000", # Instruction limit gets to first OpenSBI UART output
-                        "OpenSBI v", "buildroot_uart.out"]
-    ]
-
-# Separate test for full buildroot run
-tests_buildrootboot = [
-                    ["buildroot", ["buildroot"], "--args +INSTR_LIMIT=600000000", # boot entire buildroot Linux to login prompt
-                        "WallyHostname login: ", "buildroot_uart.out"]
-    ]
-
-tests_buildrootbootlockstep = [
-                    ["buildroot", ["buildroot"], "--args +INSTR_LIMIT=600000000 --lockstep", # boot entire buildroot Linux to login prompt
-                        "WallyHostname login: ", "buildroot_uart.out"]
-    ]
-
-derivconfigtests = [
-        # memory system
-        ["tlb2_rv32gc", ["wally32priv"]],
-        ["tlb16_rv32gc", ["wally32priv"]],
-        ["tlb2_rv64gc", ["wally64priv"]],
-        ["tlb16_rv64gc", ["wally64priv"]],
-        ["way_1_4096_512_rv32gc", ["arch32i"]],
-        ["way_2_4096_512_rv32gc", ["arch32i"]],
-        ["way_8_4096_512_rv32gc", ["arch32i"]],
-        ["way_4_2048_512_rv32gc", ["arch32i"]],
-        ["way_4_4096_256_rv32gc", ["arch32i"]],
-        ["way_1_4096_512_rv64gc", ["arch64i"]],
-        ["way_2_4096_512_rv64gc", ["arch64i"]],
-        ["way_8_4096_512_rv64gc", ["arch64i"]],
-        ["way_4_2048_512_rv64gc", ["arch64i"]],
-        ["way_4_4096_256_rv64gc", ["arch64i"]],
-        ["way_4_4096_1024_rv64gc", ["arch64i"]],
-        ["ram_0_0_rv64gc", ["ahb64"]],
-        ["ram_1_0_rv64gc", ["ahb64"]],
-        ["ram_1_1_rv64gc", ["ahb64"]],
-        ["ram_2_0_rv64gc", ["ahb64"]],
-        ["ram_2_1_rv64gc", ["ahb64"]],
-        # RV32 cacheless designs will not work unless DTIM supports FLEN > XLEN.  This support is not planned.
-        # ["nodcache_rv32gc", ["ahb32"]],
-        # ["nocache_rv32gc", ["ahb32"]],
-        ["noicache_rv32gc", ["ahb32"]],
-        ["noicache_rv64gc", ["ahb64"]],
-        ["nodcache_rv64gc", ["ahb64"]],
-        ["nocache_rv64gc", ["ahb64"]],
-
-        # Atomic variants
-        ["zaamo_rv64gc", ["arch64i", "arch64a_amo"]],
-        ["zalrsc_rv64gc", ["arch64i", "wally64a_lrsc"]],
-        ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
-        ["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
-
-        # Bit manipulation and crypto variants
-        ["zba_rv32gc", ["arch32i", "arch32zba"]],
-        ["zbb_rv32gc", ["arch32i", "arch32zbb"]],
-        ["zbc_rv32gc", ["arch32i", "arch32zbc"]],
-        ["zbs_rv32gc", ["arch32i", "arch32zbs"]],
-        ["zbkb_rv32gc", ["arch32i", "arch32zbkb"]],
-        ["zbkc_rv32gc", ["arch32i", "arch32zbkc"]],
-        ["zbkx_rv32gc", ["arch32i", "arch32zbkx"]],
-        ["zkne_rv32gc", ["arch32i", "arch32zkne"]],
-        ["zknd_rv32gc", ["arch32i", "arch32zknd"]],
-        ["zknh_rv32gc", ["arch32i", "arch32zknh"]],
-
-        ["zba_rv64gc", ["arch64i", "arch64zba"]],
-        ["zbb_rv64gc", ["arch64i", "arch64zbb"]],
-        ["zbc_rv64gc", ["arch64i", "arch64zbc"]],
-        ["zbs_rv64gc", ["arch64i", "arch64zbs"]],
-        ["zbkb_rv64gc", ["arch64i", "arch64zbkb"]],
-        ["zbkc_rv64gc", ["arch64i", "arch64zbkc"]],
-        ["zbkx_rv64gc", ["arch64i", "arch64zbkx"]],
-        ["zkne_rv64gc", ["arch64i", "arch64zkne"]],
-        ["zknd_rv64gc", ["arch64i", "arch64zknd"]],
-        ["zknh_rv64gc", ["arch64i", "arch64zknh"]],
-
-        # No privilege modes variants
-        ["noS_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
-                        "arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]],
-        ["noS_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond",
-                        "arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]],
-        ["noU_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
-                        "arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]],
-        ["noU_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond",
-                        "arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]],
-
-        ### add misaligned tests
-
-        # fp/int divider permutations
-        ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
-        ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-
-        # fpu permutations
-        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfaf"]],
-        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf"]],
-        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad"]],
-        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i", "arch32zfaf", "arch32zfad"]],
-        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i", "arch32zfaf", "arch32zfad"]],
-        ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfaf"]],
-        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf"]],
-        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad"]],
-        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i", "arch64zfaf", "arch64zfad"]],
-        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i",  "arch64zfaf", "arch64zfad"]], # "wally64q" when Q is supported again in riscof config file
-    ]
-
-bpredtests = [
-        ["nobpred_rv32gc",                 ["arch32i"], "--params \"PrintHPMCounters=1\\'b1\""],
-
-        # twobit dirpred
-        ["bpred_TWOBIT_6_16_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_6_16_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_8_16_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_8_16_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-
-        # gshare dirpred
-        ["bpred_GSHARE_6_16_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_6_16_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_8_16_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_8_16_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-
-        # btb
-        ["bpred_GSHARE_10_16_6_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_6_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_8_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_8_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        # bpred_GSHARE_10_16_10_* tested above
-        ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_14_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_14_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_16_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_16_16_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-
-        # ras
-        ["bpred_GSHARE_10_2_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_2_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_3_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_3_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_4_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_4_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_6_10_0_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_6_10_1_rv32gc",  ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "--params \"PrintHPMCounters=1\\'b1\""],
-        # bpred_GSHARE_10_16_10_* tested above
-]
-
-testfloatdivconfigs = [
-    "fdh_div_2_1_rv32gc", "fdh_div_2_1_rv64gc", "fdh_div_2_2_rv32gc",
-    "fdh_div_2_2_rv64gc", "fdh_div_2_4_rv32gc", "fdh_div_2_4_rv64gc",
-    "fdh_div_4_1_rv32gc", "fdh_div_4_1_rv64gc", "fdh_div_4_2_rv32gc",
-    "fdh_div_4_2_rv64gc", "fdh_div_4_4_rv32gc", "fdh_div_4_4_rv64gc",
-    "fd_div_2_1_rv32gc", "fd_div_2_1_rv64gc", "fd_div_2_2_rv32gc",
-    "fd_div_2_2_rv64gc", "fd_div_2_4_rv32gc", "fd_div_2_4_rv64gc",
-    "fd_div_4_1_rv32gc", "fd_div_4_1_rv64gc", "fd_div_4_2_rv32gc",
-    "fd_div_4_2_rv64gc", "fd_div_4_4_rv32gc", "fd_div_4_4_rv64gc",
-    "fdqh_div_2_1_rv32gc", "fdqh_div_2_1_rv64gc", "fdqh_div_2_2_rv32gc",
-    "fdqh_div_2_2_rv64gc", "fdqh_div_2_4_rv32gc", "fdqh_div_2_4_rv64gc",
-    "fdqh_div_4_1_rv32gc", "fdqh_div_4_1_rv64gc", "fdqh_div_4_2_rv32gc",
-    "fdqh_div_4_2_rv64gc", "fdqh_div_4_4_rv32gc", "fdqh_div_4_4_rv64gc",
-    "fdq_div_2_1_rv32gc", "fdq_div_2_1_rv64gc", "fdq_div_2_2_rv32gc",
-    "fdq_div_2_2_rv64gc", "fdq_div_2_4_rv32gc", "fdq_div_2_4_rv64gc",
-    "fdq_div_4_1_rv32gc", "fdq_div_4_1_rv64gc", "fdq_div_4_2_rv32gc",
-    "fdq_div_4_2_rv64gc", "fdq_div_4_4_rv32gc", "fdq_div_4_4_rv64gc",
-    "fh_div_2_1_rv32gc", "fh_div_2_1_rv64gc", "fh_div_2_2_rv32gc",
-    "fh_div_2_2_rv64gc", "fh_div_2_4_rv32gc", "fh_div_2_4_rv64gc",
-    "fh_div_4_1_rv32gc", "fh_div_4_1_rv64gc", "fh_div_4_2_rv32gc",
-    "fh_div_4_2_rv64gc", "fh_div_4_4_rv32gc", "fh_div_4_4_rv64gc",
-    "f_div_2_1_rv32gc", "f_div_2_1_rv64gc", "f_div_2_2_rv32gc",
-    "f_div_2_2_rv64gc", "f_div_2_4_rv32gc", "f_div_2_4_rv64gc",
-    "f_div_4_1_rv32gc", "f_div_4_1_rv64gc", "f_div_4_2_rv32gc",
-    "f_div_4_2_rv64gc", "f_div_4_4_rv32gc", "f_div_4_4_rv64gc",
-]
-
-# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
-lockstepwaivers = [
-    "WALLY-q-01.S_ref.elf",     # Q extension is not supported by ImperasDV
-    "WALLY-cbom-01.S_ref.elf", #,  # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
-]
-
-##################################
-# Data Types & Functions
-##################################
-
-TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
-# name:     the name of this test configuration (used in printing human-readable
-#           output and picking logfile names)
-# cmd:      the command to run to test (should include the logfile as '{}', and
-#           the command needs to write to that file)
-# grepstr:  the string to grep through the log file for. The test succeeds iff
-#           grep finds that string in the logfile (is used by grep, so it may
-#           be any pattern grep accepts, see `man 1 grep` for more info).
-# grepfile:  a string containing the location of the file to be searched for output
-
-class bcolors:
-    HEADER = '\033[95m'
-    OKBLUE = '\033[94m'
-    OKCYAN = '\033[96m'
-    OKGREEN = '\033[92m'
-    WARNING = '\033[93m'
-    FAIL = '\033[91m'
-    ENDC = '\033[0m'
-    BOLD = '\033[1m'
-    UNDERLINE = '\033[4m'
-
-
-def addTests(testList, sim, coverStr, configs):
-    sim_logdir = f"{regressionDir}/{sim}/logs/"
-    for test in testList:
-        config = test[0]
-        suites = test[1]
-        flags = f"{test[2]}" if len(test) >= 3 else ""
-        gs = test[3] if len(test) >= 4 else "All tests ran without failures"
-        cmdPrefix=f"wsim --sim {sim} {coverStr} {flags} {config}"
-        for t in suites:
-            sim_log = f"{sim_logdir}{config}_{t}.log"
-            grepfile = sim_logdir + test[4] if len(test) >= 5 else sim_log
-            tc = TestCase(
-                    name=t,
-                    variant=config,
-                    cmd=f"{cmdPrefix} {t} > {sim_log}",
-                    grepstr=gs,
-                    grepfile = grepfile)
-            configs.append(tc)
-
-
-def addTestsByDir(testDir, config, sim, coverStr, configs, lockstepMode=0, brekerMode=0):
-    if not os.path.isdir(testDir):
-        print(f"Error: Directory not found: {testDir}")
-        sys.exit(1)
-
-    sim_logdir = f"{regressionDir}/{sim}/logs/"
-    cmdPrefix = f"wsim --sim {sim} {coverStr} {'--lockstep' if lockstepMode else ''} {config}"
-    fileStart = "ref" if "riscv-arch-test" in testDir else ""
-    fileEnd = ".elf"
-    if lockstepMode:
-        gs = "Mismatches            : 0"
-    elif brekerMode:
-        gs="# trek: info: summary: Test PASSED"
-    elif coverStr == "--fcov":
-        gs = "Functional coverage test complete."
-    else:
-        gs = "Single Elf file tests are not signatured verified."
-    for dirpath, _, filenames in os.walk(os.path.abspath(testDir)):
-        for file in filenames:
-            if file.endswith(fileEnd) and file.startswith(fileStart):
-                fullfile = os.path.join(dirpath, file)
-                fields = fullfile.rsplit('/', 3)
-                shortelf = f"{fields[1]}_{fields[3]}" if fields[2] == "ref" else f"{fields[2]}_{fields[3]}"
-                if shortelf in lockstepwaivers: # skip tests that itch bugs in ImperasDV
-                    print(f"{bcolors.WARNING}Skipping waived test {shortelf}{bcolors.ENDC}")
-                    continue
-                sim_log = f"{sim_logdir}{config}_{shortelf}.log"
-                tc = TestCase(
-                        name=file,
-                        variant=config,
-                        cmd=f"{cmdPrefix} {fullfile} > {sim_log}",
-                        grepstr=gs,
-                        grepfile = sim_log)
-                configs.append(tc)
-
-def search_log_for_text(text, grepfile):
-    with open(grepfile, errors="ignore") as file:
-        content = file.readlines()
-        for line in content:
-            if "warning:" in line.lower():
-                print(f"{bcolors.WARNING}{line.strip()}{bcolors.ENDC}")
-            if "error:" in line.lower():
-                print(f"{bcolors.FAIL}{line.strip()}{bcolors.ENDC}")
-        return any(text in line for line in content)
-
-def run_test_case(config, dryrun: bool = False):
-    grepfile = config.grepfile
-    cmd = config.cmd
-    if dryrun:
-        print(f"Executing {cmd}", flush=True)
-        return 0
-    else:
-        os.system(cmd)
-        if search_log_for_text(config.grepstr, grepfile):
-            # Flush is needed to flush output to stdout when running in multiprocessing Pool
-            print(f"{bcolors.OKGREEN}{cmd}: Success{bcolors.ENDC}", flush=True)
-            return 0
-        else:
-            print(f"{bcolors.FAIL}{cmd}: Failures detected in output{bcolors.ENDC}", flush=True)
-            print(f"  Check {grepfile}", flush=True)
-            return 1
-
-
-def parse_args():
-    parser = argparse.ArgumentParser()
-    parser.add_argument("--ccov", help="Code Coverage", action="store_true")
-    parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
-    parser.add_argument("--fcov-act", help="Functional Coverage from riscv-arch-test tests", action="store_true")
-    parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
-    parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
-    parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
-    parser.add_argument("--branch", help="Run branch predictor accuracy tests", action="store_true")
-    parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
-    parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
-    parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
-    return parser.parse_args()
-
-
-def process_args(args):
-    coverStr = ""
-    # exercise all simulators in nightly; can omit a sim if no license is available
-    sims = ["questa", "verilator", "vcs"] if args.nightly else [defaultsim]
-    if args.ccov:
-        sims = [coveragesim]
-        coverStr = "--ccov"
-        TIMEOUT_DUR = 20*60 # seconds
-        for d in ["ucdb", "cov"]:
-            shutil.rmtree(f"{regressionDir}/questa/{d}", ignore_errors=True)
-            os.makedirs(f"{regressionDir}/questa/{d}", exist_ok=True)
-    elif args.fcov or args.fcov_act or args.breker:
-        sims = [coveragesim]
-        coverStr = "--fcov"
-        TIMEOUT_DUR = 30*60
-        shutil.rmtree(f"{regressionDir}/questa/fcov_ucdb", ignore_errors=True)
-        os.makedirs(f"{regressionDir}/questa/fcov_ucdb", exist_ok=True)
-    elif args.buildroot:
-        TIMEOUT_DUR = 60*3600 # 2.5 days
-    elif args.testfloat:
-        sims = [testfloatsim]
-        TIMEOUT_DUR = 30*60 # seconds
-    elif args.branch:
-        TIMEOUT_DUR = 120*60 # seconds
-    elif args.nightly:
-        TIMEOUT_DUR = 30*60 # seconds
-    else:
-        TIMEOUT_DUR = 10*60 # seconds
-
-    return sims, coverStr, TIMEOUT_DUR
-
-
-def selectTests(args, sims, coverStr):
-    # Run Lint
-    configs = [
-        TestCase(
-            name="lints",
-            variant="all",
-            cmd=f"lint-wally {'--nightly' if args.nightly else ''} | tee {regressionDir}/verilator/logs/all_lints.log",
-            grepstr="lints run with no errors or warnings",
-            grepfile = f"{regressionDir}/verilator/logs/all_lints.log")
-        ]
-
-    # run full buildroot boot simulation (slow) if buildroot flag is set.  Start it early to overlap with other tests
-    if args.buildroot:
-        # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
-        addTests(tests_buildrootbootlockstep, lockstepsim, coverStr, configs) # lockstep with Questa and ImperasDV runs overnight
-    # only run RV64GC tests on in code coverage mode
-    if args.ccov:
-        addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs)
-        addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs) # doesn't help coverage much dh 4/12/25
-        addTestsByDir(WALLY+"/tests/coverage/", "rv64gc", coveragesim, coverStr, configs)
-        # Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
-        addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs)
-        addTestsByDir(f"{WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege", "rv64gc", coveragesim, coverStr, configs)
-        # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/F", "rv64gc", coveragesim, coverStr, configs) # doesn't help fdivsqrt coverage 4/3/2025
-    # run tests in lockstep in functional coverage mode
-    if args.fcov:
-        addTestsByDir(f"{archVerifDir}/tests/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/priv/rv32/", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{archVerifDir}/tests/priv/rv64/", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
-        # Extra tests from riscv-arch-test that should be run as part of the functional coverage suite
-        addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/vm_sv32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/pmp32", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
-        # addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/pmp", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1) TODO: Add when working in lockstep
-    # run riscv-arch-test tests in functional coverage mode
-    if args.fcov_act:
-        addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m", "rv32gc", coveragesim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(f"{WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m", "rv64gc", coveragesim, coverStr, configs, lockstepMode=1)
-    # run branch predictor tests
-    if args.branch:
-        addTests(bpredtests, defaultsim, coverStr, configs)
-    # run Breker tests (requires a license for the breker tool)
-    if args.breker:
-        addTestsByDir(WALLY+"/tests/breker/work", "breker", "questa", coverStr, configs, brekerMode=1)
-    # standard tests
-    if not(args.testfloat or args.ccov or args.fcov or args.fcov_act or args.branch or args.breker):
-        for sim in sims:
-            if not (args.buildroot and sim == lockstepsim):  # skip short buildroot sim if running long one
-                addTests(tests_buildrootshort, sim, coverStr, configs)
-            addTests(standard_tests, sim, coverStr, configs)
-    # run derivative configurations and lockstep tests in nightly regression
-    if args.nightly:
-        addTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, coverStr, configs, lockstepMode=1)
-        addTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, coverStr, configs, lockstepMode=1)
-        addTests(derivconfigtests, defaultsim, coverStr, configs)
-        # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
-    # testfloat tests
-    if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
-        testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"]
-        for config in testfloatconfigs + testfloatdivconfigs:
-            tests = ["div", "sqrt", "cvtint", "cvtfp"]
-            if config in testfloatconfigs:
-                tests.extend(["add", "sub", "mul", "fma", "cmp"])
-            if "f_" in config:
-                tests.remove("cvtfp")
-            for test in tests:
-                sim_log = f"{regressionDir}/{testfloatsim}/logs/{config}_{test}.log"
-                tc = TestCase(
-                        name=test,
-                        variant=config,
-                        cmd=f"wsim --tb testbench_fp --sim {testfloatsim} {config} {test} > {sim_log}",
-                        grepstr="All Tests completed with          0 errors",
-                        grepfile = sim_log)
-                configs.append(tc)
-    return configs
-
-
-def makeDirs(sims):
-    # Always need verilator directories for lint
-    if "verilator" not in sims: sims.append("verilator")
-    for sim in sims:
-        dirs = [f"{regressionDir}/{sim}/wkdir", f"{regressionDir}/{sim}/logs"]
-        for d in dirs:
-            shutil.rmtree(d, ignore_errors=True)
-            os.makedirs(d, exist_ok=True)
-
-
-def main(args):
-    sims, coverStr, TIMEOUT_DUR = process_args(args)
-    makeDirs(sims)
-    configs = selectTests(args, sims, coverStr)
-    # Scale the number of concurrent processes to the number of test cases, but
-    # max out at a limited number of concurrent processes to not overwhelm the system
-    # right now fcov and nightly use Imperas
-    ImperasDVLicenseCount = 16 if args.fcov or args.fcov_act or args.nightly else 10000
-    with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
-        num_fail = 0
-        results = {}
-        for config in configs:
-            results[config] = pool.apply_async(run_test_case,(config, args.dryrun))
-        for (config,result) in results.items():
-            try:
-                num_fail+=result.get(timeout=TIMEOUT_DUR)
-            except MPTimeoutError:
-                pool.terminate()
-                pool.join()
-                num_fail+=1
-                print(f"{bcolors.FAIL}{config.cmd}: Timeout - runtime exceeded {TIMEOUT_DUR} seconds{bcolors.ENDC}")
-
-    # Coverage report
-    if args.ccov:
-        os.system(f"make -C {regressionDir} QuestaCodeCoverage")
-    if args.fcov or args.fcov_act or args.breker:
-        os.system(f"make -C {archVerifDir} merge")
-    # Count the number of failures
-    if num_fail:
-        print(f"{bcolors.FAIL}Regression failed with {num_fail} failed configurations{bcolors.ENDC}")
-    else:
-        print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
-    return num_fail
-
-if __name__ == '__main__':
-    args = parse_args()
-    sys.exit(main(args))
diff --git a/bin/requirements.txt b/bin/requirements.txt
deleted file mode 100644
index fd60841d1..000000000
--- a/bin/requirements.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-adjustText>=1.2
-lief>=0.14.1
-Markdown>=3.6
-matplotlib>=3.9.0
-pre-commit>=4.0.0
-PyYAML>=5.2
-riscof @ git+https://github.com/riscv/riscof.git
-riscv-config>=3.18.3
-riscv-isac @ git+https://github.com/riscv-non-isa/riscv-arch-test/#subdirectory=riscv-isac
-scikit-learn>=1.5.0
-scipy>=1.13.0
-setuptools
-Sphinx~=7.3.7 # QEMU fails to build with Sphinx 8
-sphinx-rtd-theme>=2.0.0
-testresources>=2.0.1
diff --git a/bin/sim_bp b/bin/sim_bp
deleted file mode 120000
index a85da9901..000000000
--- a/bin/sim_bp
+++ /dev/null
@@ -1 +0,0 @@
-../addins/branch-predictor-simulator/src/sim_bp
\ No newline at end of file
diff --git a/bin/testcount.pl b/bin/testcount.pl
index 7ac75d676..65d662293 100755
--- a/bin/testcount.pl
+++ b/bin/testcount.pl
@@ -1,43 +1,13 @@
 #!/bin/bash
-
-###########################################
-## testcount.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 25 December 2022
-## Modified: Read the riscv-test-suite directories from riscv-arch-test
-## and count how many tests are in each
-##
-## Purpose: Read the riscv-test-suite directories from riscv-arch-test
-##          and count how many tests are in each
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
+# testcount.pl
+# David_Harris@hmc.edu 25 December 2022
+# Read the riscv-test-suite directories from riscv-arch-test
+# and count how many tests are in each
 
 for dir in `ls ${WALLY}/addins/riscv-arch-test/riscv-test-suite/rv*/*`
 do
     dir=$(echo $dir | cut -d':' -f1)
     echo $dir
-    if [ $dir == "src" ]
-    then
-        continue
-    fi
     for fn in `ls $dir/src/*.S`
     do
         result=`grep 'inst_' $fn | tail -n 1`
diff --git a/bin/testlist.pl b/bin/testlist.pl
index 50b77eb78..12be0a913 100755
--- a/bin/testlist.pl
+++ b/bin/testlist.pl
@@ -1,34 +1,8 @@
-#!/usr/bin/env -S perl -w
-
-###########################################
-## testlist.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 25 December 2021
-## Modified: 
-##
-## Purpose: Read the work directories from riscv-arch-test or imperas-riscv-tests
-##          and generate a list of tests and signature addresses for tests.vh
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
+#!/bin/perl -W
+# testlist.pl
+# David_Harris@hmc.edu 25 December 2021
+# Read the work directories from riscv-arch-test or imperas-riscv-tests
+# and generate a list of tests and signature addresses for tests.vh
 
 use strict;
 use warnings;
diff --git a/bin/vclean.pl b/bin/vclean.pl
index 94a14c54c..2bc25d3d3 100755
--- a/bin/vclean.pl
+++ b/bin/vclean.pl
@@ -1,33 +1,9 @@
-#!/usr/bin/env -S perl -w
+#!/usr/bin/perl -w
 
-###########################################
-## vclean.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 7 December 2023
-## Modified: 
-##
-## Purpose: Identifies unused signals in Verilog files
-##          verilator should do this, but it also reports partially used signals
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
+# vclean.pl
+# David_Harris@hmc.edu 7 December 2023
+# Identifies unused signals in Verilog files
+#   verilator should do this, but it also reports partially used signals
 
 use strict;
 
@@ -67,4 +43,4 @@ sub clean {
             printf("$sig not used in $fname\n");
         }
     }
-}
+}
\ No newline at end of file
diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh
deleted file mode 100755
index 2f24c3daf..000000000
--- a/bin/wally-distro-check.sh
+++ /dev/null
@@ -1,136 +0,0 @@
-#!/bin/bash
-###########################################
-## Get Linux distro information
-##
-## Written: Jordan Carlin, jcarlin@hmc.edu
-## Created: 30 June 2024
-## Modified:
-##
-## Purpose: Check for compatible Linux distibution and set variables accordingly
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-set -e # break on error
-
-# Colors
-BOLD='\033[1m'
-UNDERLINE='\033[4m'
-SECTION_COLOR='\033[95m'$BOLD
-OK_COLOR='\033[94m'
-WARNING_COLOR='\033[93m'
-FAIL_COLOR='\033[91m'
-ENDC='\033[0m' # Reset to default color
-
-# Print section header
-section_header() {
-    if tput cols > /dev/null 2>&1; then
-        printf "${SECTION_COLOR}%$(tput cols)s\n" | tr ' ' '#'
-        printf "%$(tput cols)s\n" | tr ' ' '#'
-        printf "%s\n" "$1"
-        printf "%$(tput cols)s\n" | tr ' ' '#'
-        printf "%$(tput cols)s${ENDC}\n" | tr ' ' '#'
-    else
-        printf "${SECTION_COLOR}%s\n${ENDC}" "$1"
-    fi
-}
-
-section_header "Checking System Requirements and Configuring Installation"
-
-# Get distribution information
-if [ -f /etc/os-release ]; then
-    source /etc/os-release
-else
-    printf "${FAIL_COLOR}%s\n${ENDC}" "/etc/os-release file not found. Distribution unknown."
-    PRETTY_NAME=UNKNOWN
-fi
-
-# Check for compatible distro
-if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then
-    export FAMILY=rhel
-    if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then
-        printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Red Hat family distros, the Wally installation script has only been tested on RHEL, Rocky Linux," \
-            " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there may be issues."
-    fi
-    export RHEL_VERSION="${VERSION_ID:0:1}"
-    if (( RHEL_VERSION < 8 )); then
-        printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION."
-        exit 1
-    fi
-elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then
-    export FAMILY=ubuntu
-    if [ "$ID" != ubuntu ]; then
-        printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Ubuntu family distros, the Wally installation script is only tested on standard Ubuntu. Your distro " \
-            "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues."
-        # Ubuntu derivates may use different version numbers. Attempt to derive version from Ubuntu codename
-        case "$UBUNTU_CODENAME" in
-            noble)
-                export UBUNTU_VERSION=24
-                ;;
-            jammy)
-                export UBUNTU_VERSION=22
-                ;;
-            focal)
-                export UBUNTU_VERSION=20
-                ;;
-            *)
-                printf "${FAIL_COLOR}%s\n${ENDC}" "Unable to determine which base Ubuntu version you are using."
-                exit 1
-                ;;
-        esac
-        echo "Detected Ubuntu derivative baesd on Ubuntu $UBUNTU_VERSION.04."
-    else
-        export UBUNTU_VERSION="${VERSION_ID:0:2}"
-    fi
-    if (( UBUNTU_VERSION < 20 )); then
-        printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Ubuntu versions 20.04 LTS, 22.04 LTS, and 24.04 LTS. You have version $VERSION."
-        exit 1
-    fi
-elif [[ "$ID" == debian || "$ID_LIKE" == *debian* ]]; then
-    export FAMILY=debian
-    if [ "$ID" != debian ]; then
-        printf "${WARNING_COLOR}%s%s\n${ENDC}" "For Debian family distros, the Wally installation script has only been tested on standard Debian (and Ubuntu). Your distro " \
-            "is $PRETTY_NAME. The regular Debian install will be attempted, but there may be issues."
-    fi
-    export DEBIAN_VERSION="$VERSION_ID"
-    if (( DEBIAN_VERSION < 11 )); then
-        printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with Debian versions 11 and 12. You have version $VERSION."
-        exit 1
-    fi
-elif [[ "$ID" == opensuse-leap || "$ID" == sles || "$ID_LIKE" == *suse* ]]; then
-    export FAMILY=suse
-    if [[ "$ID" != opensuse-leap && "$ID" != sles  ]]; then
-        printf "${WARNING_COLOR}%s%s\n${ENDC}" "For SUSE family distros, the Wally installation script has only been tested on OpenSUSE Leap and SLES. Your distro " \
-            "is $PRETTY_NAME. The regular SUSE install will be attempted, but there may be issues. If you are using OpenSUSE Tumbleweed, the version check will fail."
-    fi
-    export SUSE_VERSION="${VERSION_ID//.}"
-    if (( SUSE_VERSION < 156 )); then
-        printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally installation script has only been tested with SUSE version 15.6. You have version $VERSION."
-        exit 1
-    fi
-else
-    printf "${FAIL_COLOR}%s%s%s\n${ENDC}" "The Wally installation script is currently only compatible with Ubuntu, Debian, SUSE, and Red Hat family " \
-        "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \
-        "commands in this script, but it is likely that some will need to be altered."
-    exit 1
-fi
-
-printf "${OK_COLOR}${UNDERLINE}%s\n${ENDC}" "Detected information"
-echo "Distribution: $PRETTY_NAME"
-echo "Version: $VERSION"
diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh
deleted file mode 100755
index d7ca0a718..000000000
--- a/bin/wally-package-install.sh
+++ /dev/null
@@ -1,164 +0,0 @@
-#!/bin/bash
-###########################################
-## Package installation
-##
-## Written: Jordan Carlin, jcarlin@hmc.edu
-## Created: 30 June 2024
-## Modified:
-##
-## Purpose: Package manager installation for open source tool chain installation script
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-set -e # break on error
-
-# Colors
-BOLD='\033[1m'
-SECTION_COLOR='\033[95m'$BOLD
-SUCCESS_COLOR='\033[92m'
-FAIL_COLOR='\033[91m'
-ENDC='\033[0m' # Reset to default color
-
-# If run standalone, determine distro information. Otherwise, use info from main install script
-if [ -z "$FAMILY" ]; then
-    dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-    source "${dir}"/wally-distro-check.sh
-fi
-
-
-# Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only
-# Packages that are constant across distros
-GENERAL_PACKAGES+=(rsync git make cmake curl wget tar unzip bzip2 dialog mutt)
-GNU_PACKAGES+=(autoconf automake gawk bison flex texinfo gperf libtool patchutils bc gcc)
-VERILATOR_PACKAGES+=(help2man perl clang ccache numactl)
-BUILDROOT_PACKAGES+=(cpio)
-
-# Distro specific packages and package manager
-case "$FAMILY" in
-    rhel)
-        PYTHON_VERSION=python3.12
-        PACKAGE_MANAGER="dnf -y"
-        UPDATE_COMMAND="$PACKAGE_MANAGER update"
-        GENERAL_PACKAGES+=(which "$PYTHON_VERSION" "$PYTHON_VERSION"-pip pkgconf-pkg-config gcc-c++ ssmtp)
-        GNU_PACKAGES+=(libmpc-devel mpfr-devel gmp-devel zlib-devel expat-devel libslirp-devel ninja-build)
-        QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel)
-        SPIKE_PACKAGES+=(dtc boost-regex boost-system)
-        VERILATOR_PACKAGES+=(gperftools mold)
-        BUILDROOT_PACKAGES+=(ncurses ncurses-base ncurses-libs ncurses-devel gcc-gfortran) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux
-        # Extra packages not availale in rhel8, nice for Verilator
-        if (( RHEL_VERSION >= 9 )); then
-            VERILATOR_PACKAGES+=(perl-doc)
-        fi
-        # A newer version of gcc is required for qemu
-        OTHER_PACKAGES+=(gcc-toolset-13)
-        ;;
-    ubuntu | debian)
-        if (( UBUNTU_VERSION >= 24 )); then
-            PYTHON_VERSION=python3.12
-        elif (( UBUNTU_VERSION >= 22 )); then
-            PYTHON_VERSION=python3.11
-        elif (( UBUNTU_VERSION >= 20 )); then
-            PYTHON_VERSION=python3.9
-            OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator
-        elif (( DEBIAN_VERSION >= 12 )); then
-            PYTHON_VERSION=python3.11
-        elif (( DEBIAN_VERSION >= 11 )); then
-            PYTHON_VERSION=python3.9
-        fi
-        # Mold not available in older distros for Verilator, will download binary instead
-        if (( UBUNTU_VERSION != 20 && DEBIAN_VERSION != 11 )); then
-            VERILATOR_PACKAGES+=(mold)
-        fi
-        PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get -y"
-        UPDATE_COMMAND="$PACKAGE_MANAGER update && $PACKAGE_MANAGER upgrade --with-new-pkgs"
-        GENERAL_PACKAGES+=("$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv pkg-config g++ ssmtp)
-        GNU_PACKAGES+=(autotools-dev libmpc-dev libmpfr-dev libgmp-dev build-essential ninja-build zlib1g-dev libexpat1-dev libglib2.0-dev libslirp-dev)
-        QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev)
-        SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev)
-        VERILATOR_PACKAGES+=(libunwind-dev libgoogle-perftools-dev perl-doc libfl2 libfl-dev zlib1g)
-        BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran) # gfortran is only needed for compiling spec benchmarks on buildroot linux
-        VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this
-        ;;
-    suse)
-        PYTHON_VERSION=python3.12
-        PYTHON_VERSION_PACKAGE=python312
-        PACKAGE_MANAGER="zypper -n"
-        UPDATE_COMMAND="$PACKAGE_MANAGER update"
-        GENERAL_PACKAGES+=("$PYTHON_VERSION_PACKAGE" "$PYTHON_VERSION_PACKAGE"-pip pkg-config)
-        GNU_PACKAGES+=(mpc-devel mpfr-devel gmp-devel zlib-devel libexpat-devel libslirp-devel ninja)
-        QEMU_PACKAGES+=(glib2-devel libpixman-1-0-devel) # maybe also need qemu itself?
-        SPIKE_PACKAGES+=(dtc libboost_regex1_75_0-devel libboost_system1_75_0-devel)
-        VERILATOR_PACKAGES+=(gperftools perl-doc)
-        BUILDROOT_PACKAGES+=(ncurses-utils ncurses-devel ncurses5-devel gcc-fortran) # gcc-fortran is only needed for compiling spec benchmarks on buildroot linux
-        OTHER_PACKAGES+=(gcc13 gcc13-c++ cpp13) # Newer version of gcc needed for many tools. Default is gcc7
-        ;;
-esac
-
-
-# Check if required packages are installed or install/update them depending on passed flag.
-if [ "${1}" == "--check" ]; then
-    section_header "Checking Dependencies from Package Manager"
-    if [[ "$FAMILY" == rhel || "$FAMILY" == suse ]]; then
-        for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do
-            rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1)
-        done
-    elif [[ "$FAMILY" == ubuntu || "$FAMILY" == debian ]]; then
-        for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do
-            dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1)
-        done
-    fi
-    echo -e "${OK_COLOR}All required packages detected.${ENDC}"
-else
-    # Check if root, otherwise exit with error message
-    [ "${EUID:=$(id -u)}" -ne 0 ] && echo -e "\n${FAIL_COLOR}Must be run as root${ENDC}" && exit 1
-
-    section_header "Installing/Updating Dependencies from Package Manager"
-    # Enable extra repos necessary for rhel
-    if [ "$FAMILY" == rhel ]; then
-        dnf install -y dnf-plugins-core
-        dnf group install -y "Development Tools"
-        if [ "$ID" == rhel ]; then
-            subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms"
-            dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm"
-        else # RHEL clone
-            if (( RHEL_VERSION == 8 )); then
-                dnf config-manager -y --set-enabled powertools
-            else # Version 9
-                dnf config-manager -y --set-enabled crb
-            fi
-            dnf install -y epel-release
-        fi
-    fi
-
-    # Update and Upgrade tools
-    eval "$UPDATE_COMMAND"
-    # Install packages listed above using appropriate package manager
-    eval $PACKAGE_MANAGER install "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}"
-
-    # Post install steps
-    # Vivado looks for ncurses5 libraries, but Ubuntu 24.04 only has ncurses6
-    # Create symbolic links to the ncurses6 libraries to fool Vivado
-    if (( UBUNTU_VERSION >= 24 )); then
-        ln -vsf /lib/x86_64-linux-gnu/libncurses.so.6 /lib/x86_64-linux-gnu/libncurses.so.5
-        ln -vsf /lib/x86_64-linux-gnu/libtinfo.so.6 /lib/x86_64-linux-gnu/libntinfo.so.5
-    fi
-
-    echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}"
-fi
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
deleted file mode 100755
index c40b23592..000000000
--- a/bin/wally-tool-chain-install.sh
+++ /dev/null
@@ -1,525 +0,0 @@
-#!/bin/bash
-###########################################
-## Tool chain install script.
-##
-## Written: Rose Thompson rose@rosethompson.net
-## Created: 18 January 2023
-## Modified: 22 January 2023
-## Modified: 23 March 2023
-## Modified: 30 June 2024, Jordan Carlin jcarlin@hmc.edu
-## Modified: 1 September 2024
-##
-## Purpose: Open source tool chain installation script
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-# Increasing NUM_THREADS will speed up parallel compilation of the tools
-NUM_THREADS=$(nproc --ignore 1) # One less than the total number of threads
-
-# Colors
-BOLD='\033[1m'
-UNDERLINE='\033[4m'
-SECTION_COLOR='\033[95m'$BOLD
-OK_COLOR='\033[94m'
-SUCCESS_COLOR='\033[92m'
-WARNING_COLOR='\033[93m'
-FAIL_COLOR='\033[91m'
-ENDC='\033[0m' # Reset to default color
-
-## Helper functions
-# Error handler
-error() {
-    echo -e "${FAIL_COLOR}Error: $STATUS installation failed"
-    echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}"
-    if [ -e "$RISCV/logs/$STATUS.log" ]; then
-        echo -e "Please check the log in $RISCV/logs/$STATUS.log for more information."
-    fi
-    exit 1
-}
-
-# Check if a git repository exists, is up to date, and has been installed
-# clones the repository if it doesn't exist
-# $1: repo name
-# $2: repo url to clone from
-# $3: file to check if already installed
-# $4: upstream branch, optional, default is master
-git_check() {
-    local repo=$1
-    local url=$2
-    local check=$3
-    local branch="${4:-master}"
-
-    # Clone repo if it doesn't exist
-    if [[ ! -e $repo ]]; then
-        for ((i=1; i<=5; i++)); do
-            git clone "$url" && break
-            echo -e "${WARNING_COLOR}Failed to clone $repo. Retrying.${ENDC}"
-            rm -rf "$repo"
-            sleep $i
-        done
-        if [[ ! -e $repo ]]; then
-            echo -e "${ERROR_COLOR}Failed to clone $repo after 5 attempts. Exiting.${ENDC}"
-            exit 1
-        fi
-    fi
-
-    # Get the current HEAD commit hash and the remote branch commit hash
-    cd "$repo"
-    git fetch
-    local local_head=$(git rev-parse HEAD)
-    local remote_head=$(git rev-parse origin/"$branch")
-
-    # Check if the git repository is not up to date or the specified file does not exist
-    if [[ "$local_head" != "$remote_head" ]]; then
-        echo "$repo is not up to date. Updating now."
-        true
-    elif [[ ! -e $check ]]; then
-        true
-    else
-        false
-    fi
-}
-
-# Log output to a file and only print lines with keywords
-logger() {
-    local log_file="$RISCV/logs/$STATUS.log"
-    local keyword_pattern="(\bwarning|\berror|\bfail|\bsuccess|\bstamp|\bdoesn't work)"
-    local exclude_pattern="(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)"
-
-    cat < /dev/stdin | tee -a "$log_file" | \
-    (grep -iE --color=never "$keyword_pattern" || true) | \
-    (grep -viE --color=never "$exclude_pattern" || true)
-}
-
-set -e # break on error
-trap error ERR # run error handler on error
-STATUS="setup" # keep track of what part of the installation is running for error messages
-
-# Check for clean flag
-if [ "$1" == "--clean" ] || [ "$2" == "--clean" ]; then
-    clean=true
-    shift
-fi
-
-# Check for no-buildroot flag
-if [ "$1" == "--no-buildroot" ] || [ "$2" == "--no-buildroot" ]; then
-    no_buidroot=true
-    shift
-fi
-
-# Determine script directory to locate related scripts
-dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-WALLY=$(dirname "$dir")
-export WALLY
-
-# Get Linux distro and version
-source "${dir}"/wally-distro-check.sh
-
-# Check if root
-ROOT=$( [ "${EUID:=$(id -u)}" == 0 ] && echo true || echo false);
-
-# Set installation directory based on execution privileges
-# If the script is run as root, the default installation path is /opt/riscv
-# If the script is run as a user, the default installation path is ~/riscv
-# The installation path can be overridden with an argument passed to the script.
-if [ "$ROOT" == true ]; then
-    export RISCV="${1:-/opt/riscv}"
-else
-    export RISCV="${1:-$HOME/riscv}"
-fi
-
-# Set environment variables
-export PATH=$PATH:$RISCV/bin:/usr/bin
-export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH
-
-# wget retry on host error flag not available with older wget on RHEL 8
-if (( RHEL_VERSION != 8 )); then
-    retry_on_host_error="--retry-on-host-error"
-fi
-
-# Check for incompatible PATH environment variable before proceeding with installation
-if [[ ":$PATH:" == *::* || ":$PATH:" == *:.:* ]]; then
-    echo -e "${FAIL_COLOR}Error: You seem to have the current working directory in your \$PATH environment variable."
-    echo -e "This won't work. Please update your \$PATH and try again.${ENDC}"
-    exit 1
-fi
-
-# Check available memory
-total_mem=$(grep MemTotal < /proc/meminfo | awk '{print $2}')
-total_mem_gb=$((total_mem / 1024 / 1024))
-
-# Print system information
-echo "Running as root: $ROOT"
-echo "Installation path: $RISCV"
-echo "Number of cores: $(nproc)"
-echo "Total memory: $total_mem_gb GB"
-
-# Reduce number of threads for systems with less than 8 GB of memory
-if ((total_mem < 8400000 )) ; then
-    NUM_THREADS=1
-    echo -e "${WARNING_COLOR}Detected less than or equal to 8 GB of memory. Using a single thread for compiling tools. This may take a while.${ENDC}"
-fi
-
-# Print number of threads
-echo "Using $NUM_THREADS thread(s) for compilation"
-
-# Create installation directory
-mkdir -p "$RISCV"/logs
-
-# Install/update system packages if root. Otherwise, check that packages are already installed.
-STATUS="system_packages"
-if [ "$ROOT" == true ]; then
-    source "${dir}"/wally-package-install.sh
-else
-    source "${dir}"/wally-package-install.sh --check
-fi
-
-# Older version of git defaults to protocol version incompatible with riscv-gnu-toolchain
-if (( UBUNTU_VERSION == 20 )); then
-    git config --global protocol.version 2
-fi
-
-# Enable newer version of gcc for older distros (required for QEMU/Verilator)
-if [ "$FAMILY" == rhel ]; then
-    source /opt/rh/gcc-toolset-13/enable
-elif [ "$FAMILY" == suse ]; then
-    mkdir -p "$RISCV"/gcc-13/bin
-    for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do
-        ln -vsf /usr/bin/$f-13 "$RISCV"/gcc-13/bin/$f
-    done
-    export PATH="$RISCV"/gcc-13/bin:$PATH
-elif (( UBUNTU_VERSION == 20 )); then
-    mkdir -p "$RISCV"/gcc-10/bin
-    for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do
-        ln -vsf /usr/bin/$f-10 "$RISCV"/gcc-10/bin/$f
-    done
-    export PATH="$RISCV"/gcc-10/bin:$PATH
-fi
-
-
-# Create python virtual environment so the python command targets desired version of python
-# and installed packages are isolated from the rest of the system.
-section_header "Setting up Python Environment"
-STATUS="python_virtual_environment"
-cd "$RISCV"
-if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then
-    "$PYTHON_VERSION" -m venv riscv-python --prompt cvw
-    echo -e "${OK_COLOR}Python virtual environment created!\nInstalling pip packages.${ENDC}"
-else
-    echo -e "${OK_COLOR}Python virtual environment already exists.\nUpdating pip packages.${ENDC}"
-fi
-
-source "$RISCV"/riscv-python/bin/activate # activate python virtual environment
-
-# Install python packages, including RISCOF (https://github.com/riscv-software-src/riscof.git)
-# RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests.
-STATUS="python packages"
-pip install --upgrade pip && pip install --upgrade -r "$dir"/requirements.txt
-
-source "$RISCV"/riscv-python/bin/activate # reload python virtual environment
-echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}"
-
-# Extra dependecies needed for older distros that don't have new enough versions available from package manager
-if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then
-    # Newer versin of glib required for QEMU.
-    # Anything newer than this won't build on red hat 8
-    STATUS="glib"
-    if [ ! -e "$RISCV"/include/glib-2.0 ]; then
-        section_header "Installing glib"
-        pip install -U meson # Meson is needed to build glib
-        cd "$RISCV"
-        wget -nv --retry-connrefused $retry_on_host_error https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz
-        tar -xJf glib-2.70.5.tar.xz
-        rm -f glib-2.70.5.tar.xz
-        cd glib-2.70.5
-        meson setup _build --prefix="$RISCV"
-        meson compile -C _build -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-        meson install -C _build 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-        cd "$RISCV"
-        rm -rf glib-2.70.5
-        echo -e "${SUCCESS_COLOR}glib successfully installed!${ENDC}"
-    fi
-fi
-
-# Newer version of gmp needed for sail-riscv model
-if (( RHEL_VERSION == 8 )); then
-    STATUS="gmp"
-    if [ ! -e "$RISCV"/include/gmp.h ]; then
-        section_header "Installing gmp"
-        cd "$RISCV"
-        wget -nv --retry-connrefused $retry_on_host_error https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz
-        tar -xJf gmp-6.3.0.tar.xz
-        rm -f gmp-6.3.0.tar.xz
-        cd gmp-6.3.0
-        ./configure --prefix="$RISCV"
-        make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-        make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-        cd "$RISCV"
-        rm -rf gmp-6.3.0
-        echo -e "${SUCCESS_COLOR}gmp successfully installed!${ENDC}"
-    fi
-fi
-
-# Mold needed for Verilator
-if (( UBUNTU_VERSION == 20  || DEBIAN_VERSION == 11 )) || [ "$FAMILY" == suse ]; then
-    STATUS="mold"
-    if [ ! -e "$RISCV"/bin/mold ]; then
-        section_header "Installing mold"
-        cd "$RISCV"
-        wget -nv --retry-connrefused $retry_on_host_error --output-document=mold.tar.gz https://github.com/rui314/mold/releases/download/v2.34.1/mold-2.34.1-x86_64-linux.tar.gz
-        tar xz --directory="$RISCV" --strip-components=1 -f mold.tar.gz
-        rm -f mold.tar.gz
-        echo -e "${SUCCESS_COLOR}Mold successfully installed/updated!${ENDC}"
-    else
-        echo -e "${SUCCESS_COLOR}Mold already installed.${ENDC}"
-    fi
-fi
-
-# Newer version of CMake needed to build sail-riscv model (at least 3.20)
-if (( UBUNTU_VERSION == 20  || DEBIAN_VERSION == 11 )); then
-    STATUS="cmake"
-    if [ ! -e "$RISCV"/bin/cmake ]; then
-        section_header "Installing cmake"
-        cd "$RISCV"
-        wget -nv --retry-connrefused $retry_on_host_error --output-document=cmake.tar.gz https://github.com/Kitware/CMake/releases/download/v3.31.5/cmake-3.31.5-linux-x86_64.tar.gz
-        tar xz --directory="$RISCV" --strip-components=1 -f cmake.tar.gz
-        rm -f cmake.tar.gz
-        echo -e "${SUCCESS_COLOR}CMake successfully installed/updated!${ENDC}"
-    else
-        echo -e "${SUCCESS_COLOR}CMake already installed.${ENDC}"
-    fi
-fi
-
-# RISC-V GNU Toolchain (https://github.com/riscv-collab/riscv-gnu-toolchain)
-# The RISC-V GNU Toolchain includes the GNU Compiler Collection (gcc), GNU Binutils, Newlib,
-# and the GNU Debugger Project (gdb). It is a collection of tools used to compile RISC-V programs.
-# To install GCC from source can take hours to compile.
-# This configuration enables multilib to target many flavors of RISC-V.
-# This book is tested with GCC 13.2.0 and 14.2.0.
-section_header "Installing/Updating RISC-V GNU Toolchain"
-STATUS="riscv-gnu-toolchain"
-cd "$RISCV"
-if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
-    cd "$RISCV"/riscv-gnu-toolchain
-    git reset --hard && git clean -f && git checkout master && git pull && git submodule update
-    # sed commands needed to fix broken shallow cloning of submodules
-    sed -i '/shallow = true/d' .gitmodules
-    sed -i 's/--depth 1//g' Makefile.in
-    ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
-    make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf riscv-gnu-toolchain
-    fi
-    echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}"
-fi
-
-
-# elf2hex (https://github.com/sifive/elf2hex)
-# The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation.
-# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t
-# handle programs that start at 0x80000000. The SiFive version above is touchy to install.
-# For example, if Python version 2.x is in your path, it won’t install correctly.
-# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin
-# at the time of compilation, or elf2hex won’t work properly.
-section_header "Installing/Updating elf2hex"
-STATUS="elf2hex"
-cd "$RISCV"
-export PATH=$RISCV/bin:$PATH
-if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv64-unknown-elf-elf2bin"; then
-    cd "$RISCV"/elf2hex
-    git reset --hard && git clean -f && git checkout master && git pull
-    autoreconf -i
-    ./configure --target=riscv64-unknown-elf --prefix="$RISCV"
-    make 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf elf2hex
-    fi
-    echo -e "${SUCCESS_COLOR}elf2hex successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}elf2hex already up to date.${ENDC}"
-fi
-
-
-# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html)
-# QEMU is an open source machine emulator and virtualizer capable of emulating RISC-V
-section_header "Installing/Updating QEMU"
-STATUS="qemu"
-cd "$RISCV"
-if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then
-    cd "$RISCV"/qemu
-    git reset --hard && git clean -f && git checkout master && git pull
-    ./configure --target-list=riscv64-softmmu --prefix="$RISCV"
-    make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf qemu
-    fi
-    echo -e "${SUCCESS_COLOR}QEMU successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}QEMU already up to date.${ENDC}"
-fi
-
-
-# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
-# Spike is a reference model for RISC-V. It is a functional simulator that can be used to run RISC-V programs.
-section_header "Installing/Updating SPIKE"
-STATUS="spike"
-cd "$RISCV"
-if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then
-    cd "$RISCV"/riscv-isa-sim
-    git reset --hard && git clean -f && git checkout master && git pull
-    mkdir -p build
-    cd build
-    ../configure --prefix="$RISCV"
-    make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf riscv-isa-sim
-    fi
-    echo -e "${SUCCESS_COLOR}Spike successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}Spike already up to date.${ENDC}"
-fi
-
-
-# Verilator (https://github.com/verilator/verilator)
-# Verilator is a fast open-source Verilog simulator that compiles synthesizable Verilog code into C++ code.
-# It is used for linting and simulation of Wally.
-# Verilator needs to be built from source to get the latest version (Wally needs 5.021 or later).
-section_header "Installing/Updating Verilator"
-STATUS="verilator"
-cd "$RISCV"
-if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then
-    unset VERILATOR_ROOT
-    cd "$RISCV"/verilator
-    git reset --hard && git clean -f && git checkout master && git pull
-    autoconf
-    ./configure --prefix="$RISCV"
-    make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    make install 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf verilator
-    fi
-    echo -e "${SUCCESS_COLOR}Verilator successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}Verilator already up to date.${ENDC}"
-fi
-
-
-# Sail Compiler (https://github.com/rems-project/sail)
-# Sail is a formal specification language designed for describing the semantics of an ISA.
-# It is used to generate the RISC-V Sail Model, which is the golden reference model for RISC-V.
-# The Sail Compiler is written in OCaml, which is an object-oriented extension of ML, which in turn
-# is a functional programming language suited to formal verification.
-section_header "Installing/Updating Sail Compiler"
-STATUS="sail_compiler"
-cd "$RISCV"
-wget -nv --retry-connrefused $retry_on_host_error --output-document=sail.tar.gz https://github.com/rems-project/sail/releases/latest/download/sail.tar.gz
-tar xz --directory="$RISCV" --strip-components=1 -f sail.tar.gz
-rm -f sail.tar.gz
-echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}"
-
-# RISC-V Sail Model (https://github.com/riscv/sail-riscv)
-# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above)
-section_header "Installing/Updating RISC-V Sail Model"
-STATUS="riscv-sail-model"
-if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_rv32d"; then
-    cd "$RISCV"/sail-riscv
-    git reset --hard && git clean -f && git checkout master && git pull
-    cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX="$RISCV" -GNinja 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    cmake --build build 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    cmake --install build 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-    if [ "$clean" ]; then
-        cd "$RISCV"
-        rm -rf sail-riscv
-    fi
-    echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed/updated!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date.${ENDC}"
-fi
-
-
-# OSU Skywater 130 cell library (https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12)
-# The OSU Skywater 130 cell library is a standard cell library that is used to synthesize Wally.
-section_header "Installing/Updating OSU Skywater 130 cell library"
-STATUS="osu_skywater_130_cell_library"
-mkdir -p "$RISCV"/cad/lib
-cd "$RISCV"/cad/lib
-if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then
-    cd "$RISCV"/sky130_osu_sc_t12
-    git reset --hard && git clean -f && git checkout main && git pull
-    echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed!${ENDC}"
-else
-    echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date.${ENDC}"
-fi
-
-
-# Buildroot and Linux testvectors
-# Buildroot is used to boot a minimal versio of Linux on Wally.
-# Testvectors are generated using QEMU.
-if [ ! "$no_buidroot" ]; then
-    section_header "Installing Buildroot and Creating Linux testvectors"
-    STATUS="buildroot"
-    if [ -z "$LD_LIBRARY_PATH" ]; then
-        export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/
-    else
-        export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/
-    fi
-    cd "$dir"/../linux
-    if [ ! -e "$RISCV"/buildroot ]; then
-        FORCE_UNSAFE_CONFIGURE=1 make 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ] # FORCE_UNSAFE_CONFIGURE is needed to allow buildroot to compile when run as root
-        echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}"
-    elif [ ! -e "$RISCV"/linux-testvectors ]; then
-        echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}"
-        make dumptvs 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ]
-        echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}"
-    else
-        echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}"
-    fi
-else
-    echo -e "${OK_COLOR}Skipping Buildroot and Linux testvectors.${ENDC}"
-fi
-
-
-# Download site-setup scripts
-# The site-setup script is used to set up the environment for the RISC-V tools and EDA tools by setting
-# the PATH and other environment variables. It also sources the Python virtual environment.
-section_header "Downloading Site Setup Script"
-STATUS="site-setup_scripts"
-cd "$RISCV"
-if [ ! -e "${RISCV}"/site-setup.sh ]; then
-    wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh
-    wget -nv --retry-connrefused $retry_on_host_error https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh
-    echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}"
-    echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}"
-else
-    echo -e "${OK_COLOR}Site setup script already exists. Not checking for updates to avoid overwritng modifications."
-    echo -e "You may need to manually update it if there were changes upstream.${ENDC}"
-fi
-
-echo -e "${SUCCESS_COLOR}${BOLD}\n\nWALLY INSTALLATION SUCCESSFUL!!!\n\n${ENDC}"
diff --git a/bin/wsim b/bin/wsim
deleted file mode 100755
index 1a89a57a8..000000000
--- a/bin/wsim
+++ /dev/null
@@ -1,195 +0,0 @@
-#!/usr/bin/env python3
-#
-# wsim
-# David_Harris@hmc.edu 5 April 2024
-# Invoke a Wally simulation for a desired configuration and test suite or ELF on the specified simulator
-# usage: wsim CONFIG TESTSUITE [-s/--sim SIMULATOR] [-g/--gui]
-# example: wsim rv64gc arch64i
-# example: wsim rv64gc tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ref/ref.elf
-# example: wsim rv32i arch32i -s verilator
-# example: wsim fdqh_ieee_rv64gc add -t testbench_fp        # run TestFloat
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-import argparse
-import os
-import sys
-
-# Global variable
-WALLY = os.environ.get("WALLY")
-
-def parseArgs():
-    parser = argparse.ArgumentParser()
-    parser.add_argument("config", help="Configuration file")
-    parser.add_argument("testsuite", nargs="?", help="Test suite or path to .elf file")
-    parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end in .elf", default="")
-    parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
-    parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
-    parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
-    parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
-    parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif", action="store_true")
-    parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
-    parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
-    parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
-    parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
-    parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
-    parser.add_argument("--lockstepverbose", "-lv", help="Run ImperasDV lock, step, and compare with tracing enabled", action="store_true")
-    parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true")
-    return parser.parse_args()
-
-def validateArgs(args):
-    if not args.testsuite and not args.elf:
-        print("Error: Missing test suite or ELF file")
-        sys.exit(1)
-    if (args.lockstep or args.lockstepverbose) and not ((args.testsuite and args.testsuite.endswith(".elf")) or args.elf) and args.testsuite != "buildroot":
-        print(f"Invalid Options. Cannot run a testsuite, {args.testsuite} with lockstep. Must run a single elf or buildroot.")
-        sys.exit(1)
-    elif args.gui and args.sim != "questa":
-        print("GUI only supported by Questa")
-        sys.exit(1)
-    elif any([args.gui, args.ccov, args.fcov]) and args.sim != "questa":
-        print("Coverage only supported by Questa")
-        sys.exit(1)
-    elif any([args.lockstep, args.lockstepverbose]) and args.sim not in ["questa", "vcs"]:
-        print("Lockstep only supported by Questa and VCS")
-        sys.exit(1)
-    elif args.tb == "testbench_fp" and args.sim != "questa":
-        print("Error: testbench_fp presently only supported by Questa, not VCS or Verilator, because of a touchy testbench")
-        sys.exit(1)
-    elif (args.config == "breker" and args.sim != "questa"):
-        print("Error: Breker tests currently only supported by Questa")
-        sys.exit(1)
-
-def elfFileCheck(args):
-    ElfFile = ""
-    if os.path.isfile(args.elf):
-        ElfFile = os.path.abspath(args.elf)
-    elif args.elf:
-        print(f"ELF file not found: {args.elf}")
-        sys.exit(1)
-    elif args.testsuite.endswith(".elf"): # No --elf argument; check if testsuite has a .elf extension and use that instead
-        if os.path.isfile(args.testsuite):
-            ElfFile = os.path.abspath(args.testsuite)
-            # extract the elf name from the path to be the test suite
-            fields = args.testsuite.rsplit("/", 3)
-            # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
-            if "breker" in args.testsuite:
-                args.testsuite = fields[-1]
-            elif len(fields) > 3:
-                if fields[2] == "ref":
-                    args.testsuite = f"{fields[1]}_{fields[3]}"
-                else:
-                    args.testsuite = f"{fields[2]}_{fields[3]}"
-            elif "/" in args.testsuite:
-                args.testsuite = args.testsuite.rsplit("/", 1)[1] # strip off path if present
-        else:
-            print(f"ELF file not found: {args.testsuite}")
-            sys.exit(1)
-    return ElfFile
-
-def prepSim(args, ElfFile):
-    prefix = ""
-    paramsList = []
-    argsList = []
-    flagsList = []
-    defineList = []
-    if args.vcd:
-        paramsList.append("MAKE_VCD=1")
-        if args.sim == "questa":
-            flagsList.append("--vcd")
-    if args.rvvi:
-        paramsList.append("RVVI_SYNTH_SUPPORTED=1")
-    if args.tb == "testbench_fp":
-        paramsList.append(f'TEST="{args.testsuite}"')
-    if ElfFile:
-        argsList.append(f"+ElfFile={ElfFile}")
-    if args.gui and args.tb == "testbench":
-        paramsList.append("DEBUG=1")
-    if args.ccov:
-        flagsList.append("--ccov")
-    if args.fcov:
-        flagsList.append("--fcov")
-        defineList.append("+define+FCOV")
-    if args.gui:
-        flagsList.append("--gui")
-    if args.lockstep or args.lockstepverbose:
-        flagsList.append("--lockstep")
-        prefix = lockstepSetup(args)
-        defineList.append("+define+USE_IMPERAS_DV")
-    if args.config == "breker": # Requires a license for the breker tool. See tests/breker/README.md for details
-        ElfFileNoExtension = os.path.splitext(ElfFile)[0]
-        flagsList.append("--breker")
-        defineList.append("+define+USE_TREK_DV")
-        argsList.append(f"+TREK_TBX_FILE={ElfFileNoExtension}.tbx")
-    # Combine into a single string
-    args.args += " " + " ".join(argsList)
-    args.params += " " + " ".join(paramsList)
-    args.define += " " + " ".join(defineList)
-    flags = " ".join(flagsList)
-    return flags, prefix
-
-def lockstepSetup(args):
-    imperasicSharedPath = os.path.join(WALLY, "config", "shared", "imperas-shared.ic")
-    imperasicVerbosePath = os.path.join(WALLY, "sim", "imperas-verbose.ic")
-    imperasicPath = os.path.join(WALLY, "config", args.config, "imperas.ic")
-    if not os.path.isfile(imperasicPath): # If config is a derivative, look for imperas.ic in derivative configs
-        imperasicPath = os.path.join(WALLY, "config", "deriv", args.config, "imperas.ic")
-        if not os.path.isfile(imperasicPath):
-            print("Error: imperas.ic not found")
-            sys.exit(1)
-    prefix = f"IMPERAS_TOOLS={imperasicSharedPath}:{imperasicPath}{f':{imperasicVerbosePath}' if args.lockstepverbose else ''}"
-    return prefix
-
-def createDirs(sim):
-    for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]:
-        os.makedirs(os.path.join(WALLY, "sim", sim, d), exist_ok=True)
-
-def runSim(args, flags, prefix):
-    if args.sim == "questa":
-        runQuesta(args, flags, prefix)
-    elif args.sim == "verilator":
-        runVerilator(args)
-    elif args.sim == "vcs":
-        runVCS(args, flags, prefix)
-
-def runQuesta(args, flags, prefix):
-    # Force Questa to use 64-bit mode, sometimes it defaults to 32-bit even on 64-bit machines
-    prefix = "MTI_VCO_MODE=64 " + prefix
-    if args.args:
-        args.args = fr'--args \"{args.args}\"'
-    if args.params:
-        args.params = fr'--params \"{args.params}\"'
-    if args.define:
-        args.define = fr'--define \"{args.define}\"'
-    cmd = f"do wally.do {args.config} {args.testsuite} {args.tb} {args.args} {args.params} {args.define} {flags}"
-    cmd = f'cd $WALLY/sim/questa; {prefix} vsim {"-c" if not args.gui else ""} -do "{cmd}"'
-    print(f"Running Questa with command: {cmd}")
-    os.system(cmd)
-
-def runVerilator(args):
-    print(f"Running Verilator on {args.config} {args.testsuite}")
-    os.system(f'make -C {WALLY}/sim/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} PLUS_ARGS="{args.args}" PARAM_ARGS="{args.params}" DEFINE_ARGS="{args.define}"')
-
-def runVCS(args, flags, prefix):
-    print(f"Running VCS on {args.config} {args.testsuite}")
-    if args.args:
-        args.args = f'--args "{args.args}"'
-    if args.params:
-        args.params = f'--params "{args.params}"'
-    if args.define:
-        args.define = f'--define "{args.define}"'
-    cmd = f"cd $WALLY/sim/vcs; {prefix} ./run_vcs {args.config} {args.testsuite} --tb {args.tb} {args.args} {args.params} {args.define} {flags}"
-    print(cmd)
-    os.system(cmd)
-
-def main(args):
-    validateArgs(args)
-    print(f"Config={args.config} tests={args.testsuite} sim={args.sim} gui={args.gui} args='{args.args}' params='{args.params}' define='{args.define}'")
-    ElfFile = elfFileCheck(args)
-    flags, prefix = prepSim(args, ElfFile)
-    createDirs(args.sim)
-    sys.exit(runSim(args, flags, prefix))
-
-if __name__ == "__main__":
-    args = parseArgs()
-    main(args)
diff --git a/bugs.txt b/bugs.txt
new file mode 100644
index 000000000..f2a22fd81
--- /dev/null
+++ b/bugs.txt
@@ -0,0 +1,2 @@
+1. [X] Cache is suppressing d cache flush if there is a dtlb miss.
+   1. Fixed by disabling mmu's address translation on flush.
diff --git a/config/derivlist.txt b/config/derivlist.txt
deleted file mode 100644
index 9bda59337..000000000
--- a/config/derivlist.txt
+++ /dev/null
@@ -1,1446 +0,0 @@
-###########################################
-## derivlist.txt
-## Wally Derivative Configuration List
-##
-## Written: David_Harris@hmc.edu, kekim@hmc.edu 
-## Created: 29 January 2024
-## Modified: 
-##
-## Purpose: Used by sim/make deriv to generate derivative configurations
-##          in config/deriv that are variants of the base configurations.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-# Format:
-# begin a derivative with "deriv <derivative name> <base configuration name> <inherited config name>
-# Followed by a list of parameters and their new value in the derivative configuration
-# All other parameter values are inherited from the original configuration
-# If <inherited config name> is not empty, all the list of parameter changes in the inherited 
-# configuration are also applied to this configuration
-
-
-# buildroot is used for the Linux boot
-deriv   buildroot   rv64gc
-RESET_VECTOR    64'h1000
-UNCORE_RAM_RANGE    64'h0FFFFFFF
-UNCORE_RAM_PRELOAD  1
-GPIO_LOOPBACK_TEST  0
-SPI_LOOPBACK_TEST   0   
-UART_PRESCALE       32'd0
-PLIC_NUM_SRC        32'd53
-
-# fpga is used for FPGA hardware.  It adds the SDC and DDR (EXT_MEM)
-deriv fpga  buildroot 
-BOOTROM_PRELOAD     1
-UNCORE_RAM_BASE     64'h2000
-UNCORE_RAM_RANGE    64'h1FFF
-BOOTROM_RANGE       64'hFFF
-EXT_MEM_SUPPORTED   1
-EXT_MEM_BASE        64'h80000000
-EXT_MEM_RANGE       64'h7FFFFFFF
-SDC_SUPPORTED       1
-PLIC_SDC_ID         32'd20
-BPRED_SIZE          32'd12
-
-deriv fpgaArtyA7 fpga
-EXT_MEM_RANGE       64'h0FFFFFFF
-
-deriv fpgavcu108 fpga
-EXT_MEM_RANGE       64'h7FFFFFFF
-
-# temporary spitest configuration
-deriv spitest rv64gc
-UNCORE_RAM_RANGE    64'h0FFFFFFF
-SPI_LOOPBACK_TEST   1
-UART_PRESCALE       32'd0
-PLIC_NUM_SRC        32'd53
-SDC_SUPPORTED       1
-PLIC_SDC_ID         32'd20
-BPRED_SIZE          32'd12
-
-# The syn configurations are trimmed down for faster synthesis.  
-deriv   syn_rv32e       rv32e
-DTIM_RANGE              64'h1FF
-IROM_RANGE              64'h1FF
-BOOTROM_RANGE           64'h1FF
-UNCORE_RAM_RANGE        64'h1FF
-DCACHE_WAYSIZEINBYTES   32'd512
-ICACHE_WAYSIZEINBYTES   32'd512
-DCACHE_NUMWAYS          32'd1
-ICACHE_NUMWAYS          32'd1
-BPRED_SIZE              32'd5
-BTB_SIZE                32'd5 
-
-# The other syn configurations have the same trimming
-deriv syn_rv32i rv32i syn_rv32e
-deriv syn_rv32imc rv32imc syn_rv32e
-deriv syn_rv32gc rv32gc syn_rv32e
-deriv syn_rv64i rv64i syn_rv32e
-deriv syn_rv64gc rv64gc syn_rv32e
-
-# The syn_sram configurations use SRAM macros
-deriv   syn_sram_rv32e   rv32e
-DTIM_RANGE          64'h1FF
-IROM_RANGE          64'h1FF
-USE_SRAM            1
-
-# The other syn configurations have the same trimming
-deriv syn_sram_rv32i rv32i syn_sram_rv32e
-deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
-deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
-deriv syn_sram_rv64i rv64i syn_sram_rv32e
-deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
-
-# The following syn configurations gradually turn off features
-deriv syn_rv64gc_pmp0 syn_rv64gc
-PMP_ENTRIES         32'd0
-deriv syn_sram_rv64gc_pmp0 syn_sram_rv64gc
-PMP_ENTRIES         32'd0
-
-deriv syn_rv64gc_noPriv syn_rv64gc_pmp0
-ZICSR_SUPPORTED     0
-deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0
-ZICSR_SUPPORTED     0
-
-deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
-F_SUPPORTED         0
-ZCF_SUPPORTED       0
-D_SUPPORTED         0
-ZCD_SUPPORTED       0
-
-deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
-F_SUPPORTED         0
-ZCF_SUPPORTED       0
-D_SUPPORTED         0
-ZCD_SUPPORTED       0
-
-deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
-M_SUPPORTED         0
-ZMMUL_SUPPORTED     0
-deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
-M_SUPPORTED         0
-ZMMUL_SUPPORTED     0
-
-deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
-ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED    0
-deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
-ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED    0
-
-# Divider variants to check logical correctness
-
-deriv div_2_1_rv32gc    rv32gc
-RADIX               32'd2
-DIVCOPIES           32'd1
-IDIV_ON_FPU         0
-
-deriv div_2_2_rv32gc    rv32gc
-RADIX               32'd2
-DIVCOPIES           32'd2
-IDIV_ON_FPU         0
-
-deriv div_2_4_rv32gc    rv32gc
-RADIX               32'd2
-DIVCOPIES           32'd4
-IDIV_ON_FPU         0
-
-deriv div_4_1_rv32gc    rv32gc
-RADIX               32'd4
-DIVCOPIES           32'd1
-IDIV_ON_FPU         0
-
-deriv div_4_2_rv32gc    rv32gc
-RADIX               32'd4
-IDIV_ON_FPU         0
-DIVCOPIES           32'd2
-
-deriv div_4_4_rv32gc    rv32gc
-RADIX               32'd4
-DIVCOPIES           32'd4
-IDIV_ON_FPU         0
-
-deriv div_2_1i_rv32gc div_2_1_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_2_2i_rv32gc div_2_2_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_2_4i_rv32gc div_2_4_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_4_1i_rv32gc div_4_1_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_4_2i_rv32gc div_4_2_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_4_4i_rv32gc div_4_4_rv32gc
-IDIV_ON_FPU         1
-
-deriv div_2_1_rv64gc    rv64gc
-RADIX               32'd2
-DIVCOPIES           32'd1
-IDIV_ON_FPU         0
-
-deriv div_2_2_rv64gc    rv64gc
-RADIX               32'd2
-DIVCOPIES           32'd2
-IDIV_ON_FPU         0
-
-deriv div_2_4_rv64gc    rv64gc
-RADIX               32'd2
-DIVCOPIES           32'd4
-IDIV_ON_FPU         0
-
-deriv div_4_1_rv64gc    rv64gc
-RADIX               32'd4
-DIVCOPIES           32'd1
-IDIV_ON_FPU         0
-
-deriv div_4_2_rv64gc    rv64gc
-RADIX               32'd4
-DIVCOPIES           32'd2
-IDIV_ON_FPU         0
-
-deriv div_4_4_rv64gc    rv64gc
-RADIX               32'd4
-DIVCOPIES           32'd4
-IDIV_ON_FPU         0
-
-deriv div_2_1i_rv64gc div_2_1_rv64gc
-IDIV_ON_FPU         1
-
-deriv div_2_2i_rv64gc div_2_2_rv64gc
-IDIV_ON_FPU         1
-
-deriv div_2_4i_rv64gc div_2_4_rv64gc
-IDIV_ON_FPU         1
-
-deriv div_4_1i_rv64gc div_4_1_rv64gc
-IDIV_ON_FPU         1
-
-deriv div_4_2i_rv64gc div_4_2_rv64gc
-IDIV_ON_FPU         1
-
-deriv div_4_4i_rv64gc div_4_4_rv64gc
-IDIV_ON_FPU         1
-
-# RAM latency and Burst mode for bus stress testing
-
-deriv ram_0_0_rv64gc rv64gc
-RAM_LATENCY         32'd0
-BURST_EN            0
-
-deriv ram_1_0_rv64gc rv64gc
-RAM_LATENCY         32'd1
-BURST_EN            0
-
-deriv ram_2_0_rv64gc rv64gc
-RAM_LATENCY         32'd2
-BURST_EN            0
-
-deriv ram_1_1_rv64gc rv64gc
-RAM_LATENCY         32'd1
-BURST_EN            1
-
-deriv ram_2_1_rv64gc rv64gc
-RAM_LATENCY         32'd2
-BURST_EN            1
-
-# Branch predictor simulations
-
-deriv nobpred_rv32gc rv32gc 
-BPRED_SUPPORTED     0
-
-deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc 
-BPRED_SIZE          32'd6
-
-deriv bpred_GSHARE_8_16_10_1_rv32gc rv32gc
-BPRED_SIZE          32'd8
-
-deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
-BPRED_SIZE          32'd10
-
-deriv bpred_GSHARE_12_16_10_1_rv32gc rv32gc
-BPRED_SIZE          32'd12
-
-deriv bpred_GSHARE_14_16_10_1_rv32gc rv32gc
-BPRED_SIZE          32'd14
-
-deriv bpred_GSHARE_16_16_10_1_rv32gc rv32gc
-BPRED_SIZE          32'd16
-
-deriv bpred_TWOBIT_6_16_10_1_rv32gc bpred_GSHARE_6_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_TWOBIT_8_16_10_1_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_TWOBIT_10_16_10_1_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_TWOBIT_12_16_10_1_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_TWOBIT_14_16_10_1_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_TWOBIT_16_16_10_1_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
-BPRED_TYPE          `BP_TWOBIT
-
-deriv bpred_GSHARE_10_2_10_1_rv32gc rv32gc
-RAS_SIZE         32'd2
-
-deriv bpred_GSHARE_10_3_10_1_rv32gc rv32gc
-RAS_SIZE          32'd3
-
-deriv bpred_GSHARE_10_4_10_1_rv32gc rv32gc
-RAS_SIZE          32'd4
-
-deriv bpred_GSHARE_10_6_10_1_rv32gc rv32gc
-RAS_SIZE          32'd6
-
-deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc
-RAS_SIZE          32'd10
-
-deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc
-BTB_SIZE          32'd6
-
-deriv bpred_GSHARE_10_16_8_1_rv32gc rv32gc
-BTB_SIZE          32'd8
-
-deriv bpred_GSHARE_10_16_12_1_rv32gc rv32gc
-BTB_SIZE          32'd12
-
-deriv bpred_GSHARE_10_16_14_1_rv32gc rv32gc
-BTB_SIZE          32'd14
-
-deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc
-BTB_SIZE          32'd16
-
-
-
-
-deriv bpred_GSHARE_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_1_rv32gc 
-INSTR_CLASS_PRED  0
-
-deriv bpred_GSHARE_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_3_10_0_rv32gc bpred_GSHARE_10_3_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_4_10_0_rv32gc bpred_GSHARE_10_4_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_6_10_0_rv32gc bpred_GSHARE_10_6_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_8_0_rv32gc bpred_GSHARE_10_16_8_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_12_0_rv32gc bpred_GSHARE_10_16_12_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_14_0_rv32gc bpred_GSHARE_10_16_14_1_rv32gc
-INSTR_CLASS_PRED          0
-
-deriv bpred_GSHARE_10_16_16_0_rv32gc bpred_GSHARE_10_16_16_1_rv32gc
-INSTR_CLASS_PRED          0
-
-# Cache configurations
-
-deriv noicache_rv32gc rv32gc
-ICACHE_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-
-deriv nodcache_rv32gc rv32gc
-DCACHE_SUPPORTED    0
-D_SUPPORTED         0
-ZCD_SUPPORTED       0
-ZALRSC_SUPPORTED    0
-ZAAMO_SUPPORTED     0
-ZICBOM_SUPPORTED    0
-ZICBOZ_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-
-# nocache_rv32gc must also disable several features incompatible with no cache
-deriv nocache_rv32gc rv32gc
-ICACHE_SUPPORTED    0
-DCACHE_SUPPORTED    0
-D_SUPPORTED         0
-ZCD_SUPPORTED       0
-ZALRSC_SUPPORTED    0
-ZAAMO_SUPPORTED     0
-ZICBOM_SUPPORTED    0
-ZICBOZ_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-
-deriv noicache_rv64gc rv64gc
-ICACHE_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-SVPBMT_SUPPORTED    0
-SVNAPOT_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-
-deriv nodcache_rv64gc rv64gc
-DCACHE_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-ZICBOM_SUPPORTED    0
-ZICBOZ_SUPPORTED    0
-ZICCLSM_SUPPORTED   0
-SVPBMT_SUPPORTED    0
-SVNAPOT_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED    0
-
-deriv nocache_rv64gc rv64gc
-ICACHE_SUPPORTED    0
-DCACHE_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-ZICBOM_SUPPORTED    0
-ZICBOZ_SUPPORTED    0
-ZICCLSM_SUPPORTED   0
-SVPBMT_SUPPORTED    0
-SVNAPOT_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED    0
-
-deriv way_1_4096_512_rv32gc rv32gc
-DCACHE_NUMWAYS      32'd1
-DCACHE_WAYSIZEINBYTES 32'd4096
-DCACHE_LINELENINBITS 32'd512
-ICACHE_NUMWAYS      32'd1
-ICACHE_WAYSIZEINBYTES 32'd4096
-ICACHE_LINELENINBITS 32'd512
-
-deriv way_2_4096_512_rv32gc way_1_4096_512_rv32gc
-DCACHE_NUMWAYS      32'd1
-ICACHE_NUMWAYS      32'd1
-
-deriv way_4_4096_512_rv32gc way_1_4096_512_rv32gc
-DCACHE_NUMWAYS      32'd4
-ICACHE_NUMWAYS      32'd4
-
-deriv way_8_4096_512_rv32gc way_1_4096_512_rv32gc
-DCACHE_NUMWAYS      32'd8
-ICACHE_NUMWAYS      32'd8
-
-deriv way_4_2048_512_rv32gc way_4_4096_512_rv32gc
-DCACHE_WAYSIZEINBYTES 32'd2048
-ICACHE_WAYSIZEINBYTES 32'd2048
-
-deriv way_4_4096_256_rv32gc way_4_4096_512_rv32gc
-DCACHE_LINELENINBITS 32'd256
-ICACHE_LINELENINBITS 32'd256
-
-deriv way_1_4096_512_rv64gc rv64gc
-DCACHE_NUMWAYS      32'd1
-DCACHE_WAYSIZEINBYTES 32'd4096
-DCACHE_LINELENINBITS 32'd512
-ICACHE_NUMWAYS      32'd1
-ICACHE_WAYSIZEINBYTES 32'd4096
-ICACHE_LINELENINBITS 32'd512
-
-deriv way_2_4096_512_rv64gc way_1_4096_512_rv64gc
-DCACHE_NUMWAYS      32'd1
-ICACHE_NUMWAYS      32'd1
-
-deriv way_4_4096_512_rv64gc way_1_4096_512_rv64gc
-DCACHE_NUMWAYS      32'd4
-ICACHE_NUMWAYS      32'd4
-
-deriv way_8_4096_512_rv64gc way_1_4096_512_rv64gc
-DCACHE_NUMWAYS      32'd8
-ICACHE_NUMWAYS      32'd8
-
-deriv way_4_2048_512_rv64gc way_4_4096_512_rv64gc
-DCACHE_WAYSIZEINBYTES 32'd2048
-ICACHE_WAYSIZEINBYTES 32'd2048
-
-deriv way_4_4096_256_rv64gc way_4_4096_512_rv64gc
-DCACHE_LINELENINBITS 32'd256
-ICACHE_LINELENINBITS 32'd256
-
-deriv way_4_4096_1024_rv64gc way_4_4096_512_rv64gc
-DCACHE_LINELENINBITS 32'd1024
-ICACHE_LINELENINBITS 32'd1024
-
-# TLB Size variants
-
-deriv tlb2_rv32gc rv32gc
-ITLB_ENTRIES 32'd2
-DTLB_ENTRIES 32'd2
-
-deriv tlb16_rv32gc rv32gc
-ITLB_ENTRIES 32'd16
-DTLB_ENTRIES 32'd16
-
-deriv tlb2_rv64gc rv64gc
-ITLB_ENTRIES 32'd2
-DTLB_ENTRIES 32'd2
-
-deriv tlb16_rv64gc rv64gc
-ITLB_ENTRIES 32'd16
-DTLB_ENTRIES 32'd16
-
-# Feature variants
-
-deriv misaligned_rv32gc rv32gc
-ZICCLSM_SUPPORTED 1
-
-deriv nomisaligned_rv64gc rv64gc
-ZICCLSM_SUPPORTED 0
-
-deriv nobigendian_rv32gc rv32gc
-BIGENDIAN_SUPPORTED 0
-
-deriv nobigendian_rv64gc rv64gc
-BIGENDIAN_SUPPORTED 0
-
-deriv zaamo_rv32gc rv32gc
-ZALRSC_SUPPORTED    0
-
-deriv zalrsc_rv32gc rv32gc
-ZAAMO_SUPPORTED     0
-
-deriv zaamo_rv64gc rv64gc
-ZALRSC_SUPPORTED    0
-
-deriv zalrsc_rv64gc rv64gc
-ZAAMO_SUPPORTED     0
-
-deriv zba_rv32gc rv32gc
-ZBA_SUPPORTED     1     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbb_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     1     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbc_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     1     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbs_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     1     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkb_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     1     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkc_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     1     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkx_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     1     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zknd_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     1     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zkne_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     1     
-ZKNH_SUPPORTED     0     
-
-deriv zknh_rv32gc rv32gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     1     
-
-deriv zba_rv64gc rv64gc
-ZBA_SUPPORTED     1     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbb_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     1     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbc_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     1     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbs_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     1     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkb_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     1     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkc_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     1     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zbkx_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     1     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zknd_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     1     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     0     
-
-deriv zkne_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     1     
-ZKNH_SUPPORTED     0     
-
-deriv zknh_rv64gc rv64gc
-ZBA_SUPPORTED     0     
-ZBB_SUPPORTED     0     
-ZBS_SUPPORTED     0     
-ZBC_SUPPORTED     0     
-ZBKB_SUPPORTED     0     
-ZBKC_SUPPORTED     0     
-ZBKX_SUPPORTED     0     
-ZKND_SUPPORTED     0     
-ZKNE_SUPPORTED     0     
-ZKNH_SUPPORTED     1     
-
-deriv noS_rv32gc rv32gc
-S_SUPPORTED        0
-SSTC_SUPPORTED     0
-VIRTMEM_SUPPORTED  0
-SVINVAL_SUPPORTED  0
-SVADU_SUPPORTED    0
-
-deriv noS_rv64gc rv64gc
-S_SUPPORTED       0
-SSTC_SUPPORTED    0
-VIRTMEM_SUPPORTED 0
-SVPBMT_SUPPORTED  0
-SVNAPOT_SUPPORTED 0
-SVINVAL_SUPPORTED 0
-SVADU_SUPPORTED   0
-
-deriv noU_rv32gc noS_rv32gc
-U_SUPPORTED    0
-
-deriv noU_rv64gc noS_rv64gc
-U_SUPPORTED    0
-
-# Floating-point modes supported
-
-deriv f_rv32gc rv32gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-ZCD_SUPPORTED   0
-
-deriv fh_rv32gc rv32gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-ZCD_SUPPORTED   0
-
-deriv fd_rv32gc rv32gc
-ZFH_SUPPORTED   0
-
-deriv fdh_rv32gc rv32gc
-ZFH_SUPPORTED   1
-
-deriv fdq_rv32gc rv32gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdqh_rv32gc rv32gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv f_rv64gc rv64gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-ZCD_SUPPORTED   0
-
-deriv fh_rv64gc rv64gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-ZCD_SUPPORTED   0
-
-deriv fd_rv64gc rv64gc
-ZFH_SUPPORTED   0
-
-deriv fdh_rv64gc rv64gc
-ZFH_SUPPORTED   1
-
-deriv fdq_rv64gc rv64gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdqh_rv64gc rv64gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-#### MORE DIVIDER variants
-
-#### F_only, RK variable
-deriv f_div_2_1_rv32gc    div_2_1_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_2_2_rv32gc    div_2_2_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_2_4_rv32gc    div_2_4_rv32gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_1_rv32gc    div_4_1_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_2_rv32gc    div_4_2_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_4_rv32gc    div_4_4_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_2_1_rv64gc    div_2_1_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_2_2_rv64gc    div_2_2_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_2_4_rv64gc    div_2_4_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_1_rv64gc    div_4_1_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_2_rv64gc    div_4_2_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-deriv f_div_4_4_rv64gc    div_4_4_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   0
-
-
-#### FH_only, RK variable
-deriv fh_div_2_1_rv32gc    div_2_1_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_2_2_rv32gc    div_2_2_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_2_4_rv32gc    div_2_4_rv32gc
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_1_rv32gc    div_4_1_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_2_rv32gc    div_4_2_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_4_rv32gc    div_4_4_rv32gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_2_1_rv64gc    div_2_1_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_2_2_rv64gc    div_2_2_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_2_4_rv64gc    div_2_4_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_1_rv64gc    div_4_1_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_2_rv64gc    div_4_2_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-deriv fh_div_4_4_rv64gc    div_4_4_rv64gc    
-D_SUPPORTED     0
-ZCD_SUPPORTED   0
-ZFH_SUPPORTED   1
-
-# FD only , rk variable
-
-deriv fd_div_2_1_rv32gc    div_2_1_rv32gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_2_2_rv32gc    div_2_2_rv32gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_2_4_rv32gc    div_2_4_rv32gc
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_1_rv32gc    div_4_1_rv32gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_2_rv32gc    div_4_2_rv32gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_4_rv32gc    div_4_4_rv32gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_2_1_rv64gc    div_2_1_rv64gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_2_2_rv64gc    div_2_2_rv64gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_2_4_rv64gc    div_2_4_rv64gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_1_rv64gc    div_4_1_rv64gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_2_rv64gc    div_4_2_rv64gc    
-ZFH_SUPPORTED   0
-
-deriv fd_div_4_4_rv64gc    div_4_4_rv64gc    
-ZFH_SUPPORTED   0
-
-
-# FDH only , rk variable
-
-deriv fdh_div_2_1_rv32gc    div_2_1_rv32gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_2_2_rv32gc    div_2_2_rv32gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_2_4_rv32gc    div_2_4_rv32gc
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_1_rv32gc    div_4_1_rv32gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_2_rv32gc    div_4_2_rv32gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_4_rv32gc    div_4_4_rv32gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_2_1_rv64gc    div_2_1_rv64gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_2_2_rv64gc    div_2_2_rv64gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_2_4_rv64gc    div_2_4_rv64gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_1_rv64gc    div_4_1_rv64gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_2_rv64gc    div_4_2_rv64gc    
-ZFH_SUPPORTED   1
-
-deriv fdh_div_4_4_rv64gc    div_4_4_rv64gc    
-ZFH_SUPPORTED   1
-
-# FDQ only , rk variable
-
-deriv fdq_div_2_1_rv32gc    div_2_1_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_2_2_rv32gc    div_2_2_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_2_4_rv32gc    div_2_4_rv32gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_1_rv32gc    div_4_1_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_2_rv32gc    div_4_2_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_4_rv32gc    div_4_4_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_2_1_rv64gc    div_2_1_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_2_2_rv64gc    div_2_2_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_2_4_rv64gc    div_2_4_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_1_rv64gc    div_4_1_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_2_rv64gc    div_4_2_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-deriv fdq_div_4_4_rv64gc    div_4_4_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   0
-
-# FDQH only , rk variable
-
-deriv fdqh_div_2_1_rv32gc    div_2_1_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_2_2_rv32gc    div_2_2_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_2_4_rv32gc    div_2_4_rv32gc
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_1_rv32gc    div_4_1_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_2_rv32gc    div_4_2_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_4_rv32gc    div_4_4_rv32gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_2_1_rv64gc    div_2_1_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_2_2_rv64gc    div_2_2_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_2_4_rv64gc    div_2_4_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_1_rv64gc    div_4_1_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_2_rv64gc    div_4_2_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-deriv fdqh_div_4_4_rv64gc    div_4_4_rv64gc    
-Q_SUPPORTED     1
-ZFH_SUPPORTED   1
-
-#### DIVIDER VARIANTS WITH IDIV ON FPU
-
-deriv f_div_2_1i_rv32gc f_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_2_2i_rv32gc f_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_2_4i_rv32gc f_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_1i_rv32gc f_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_2i_rv32gc f_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_4i_rv32gc f_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv f_div_2_1i_rv64gc f_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv f_div_2_2i_rv64gc f_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv f_div_2_4i_rv64gc f_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_1i_rv64gc f_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_2i_rv64gc f_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv f_div_4_4i_rv64gc f_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-#### FH_only, RK variable
-deriv fh_div_2_1i_rv32gc fh_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_2_2i_rv32gc fh_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_2_4i_rv32gc fh_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_1i_rv32gc fh_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_2i_rv32gc fh_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_4i_rv32gc fh_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fh_div_2_1i_rv64gc fh_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fh_div_2_2i_rv64gc fh_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fh_div_2_4i_rv64gc fh_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_1i_rv64gc fh_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_2i_rv64gc fh_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fh_div_4_4i_rv64gc fh_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-# FD only , rk variable
-
-deriv fd_div_2_1i_rv32gc fd_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_2_2i_rv32gc fd_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_2_4i_rv32gc fd_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_1i_rv32gc fd_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_2i_rv32gc fd_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_4i_rv32gc fd_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fd_div_2_1i_rv64gc fd_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fd_div_2_2i_rv64gc fd_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fd_div_2_4i_rv64gc fd_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_1i_rv64gc fd_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_2i_rv64gc fd_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fd_div_4_4i_rv64gc fd_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-# FDH only , rk variable
-
-deriv fdh_div_2_1i_rv32gc fdh_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_2_2i_rv32gc fdh_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_2_4i_rv32gc fdh_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_1i_rv32gc fdh_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_2i_rv32gc fdh_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_4i_rv32gc fdh_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_2_1i_rv64gc fdh_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_2_2i_rv64gc fdh_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_2_4i_rv64gc fdh_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_1i_rv64gc fdh_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_2i_rv64gc fdh_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdh_div_4_4i_rv64gc fdh_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-# FDQ only , rk variable
-
-deriv fdq_div_2_1i_rv32gc fdq_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_2_2i_rv32gc fdq_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_2_4i_rv32gc fdq_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_1i_rv32gc fdq_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_2i_rv32gc fdq_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_4i_rv32gc fdq_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_2_1i_rv64gc fdq_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_2_2i_rv64gc fdq_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_2_4i_rv64gc fdq_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_1i_rv64gc fdq_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_2i_rv64gc fdq_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdq_div_4_4i_rv64gc fdq_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-# FDQH only , rk variable
-
-deriv fdqh_div_2_1i_rv32gc fdqh_div_2_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_2_2i_rv32gc fdqh_div_2_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_2_4i_rv32gc fdqh_div_2_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_1i_rv32gc fdqh_div_4_1_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_2i_rv32gc fdqh_div_4_2_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_4i_rv32gc fdqh_div_4_4_rv32gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_2_1i_rv64gc fdqh_div_2_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_2_2i_rv64gc fdqh_div_2_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_2_4i_rv64gc fdqh_div_2_4_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_1i_rv64gc fdqh_div_4_1_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_2i_rv64gc fdqh_div_4_2_rv64gc
-IDIV_ON_FPU     1
-
-deriv fdqh_div_4_4i_rv64gc fdqh_div_4_4_rv64gc
-IDIV_ON_FPU     1
-
-# imperas used for a smart memory
-# VCS doesn't like removing the bootrom, but make it tiny in a random unused location
-derive ImperasTG rv64gc
-ICACHE_SUPPORTED    0
-DCACHE_SUPPORTED    0
-VIRTMEM_SUPPORTED   0
-ZICCLSM_SUPPORTED   0
-ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED    0
-ZICBOM_SUPPORTED    0
-ZICBOZ_SUPPORTED    0
-SVPBMT_SUPPORTED    0
-SVNAPOT_SUPPORTED   0
-SVINVAL_SUPPORTED   0
-BOOTROM_BASE        64'h700012340080
-BOOTROM_RANGE       64'h10
-CLINT_SUPPORTED     0
-GPIO_SUPPORTED      0
-UART_SUPPORTED      0
-PLIC_SUPPORTED      0
-SPI_SUPPORTED       0
-
-# Breker tests require a different memory configuration
-# See tests/breker/README.md for details on the testsuite
-derive breker rv64gc
-EXT_MEM_SUPPORTED   1
-EXT_MEM_BASE        64'h90000000
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
deleted file mode 100644
index 7b0f43913..000000000
--- a/config/rv32e/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd32;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 1;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 0;
-localparam logic ZMMUL_SUPPORTED = 0;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 0;
-localparam logic ZALRSC_SUPPORTED = 0;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 0;
-localparam logic ZBB_SUPPORTED = 0;
-localparam logic ZBS_SUPPORTED = 0;
-localparam logic ZBC_SUPPORTED = 0;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 0;
-localparam logic ZBKC_SUPPORTED = 0;
-localparam logic ZBKX_SUPPORTED = 0;
-localparam logic ZKND_SUPPORTED = 0;
-localparam logic ZKNE_SUPPORTED = 0;
-localparam logic ZKNH_SUPPORTED = 0;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 0;
-localparam logic ZCB_SUPPORTED = 0;
-localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 0; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 0;
-localparam logic D_SUPPORTED   = 0;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 0;
-localparam logic ZFA_SUPPORTED = 0;
-
-// privilege modes
-localparam logic S_SUPPORTED = 0; // Supervisor mode
-localparam logic U_SUPPORTED = 0; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 0;
-localparam logic ZIHPM_SUPPORTED  = 0;
-localparam COUNTERS = 12'd0;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 0;
-localparam logic ZICBOZ_SUPPORTED = 0;
-localparam logic ZICBOP_SUPPORTED = 0;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 0;
-localparam logic SVNAPOT_SUPPORTED = 0;
-localparam logic SVINVAL_SUPPORTED = 0;
-localparam logic SVADU_SUPPORTED   = 0;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 1;
-localparam logic DCACHE_SUPPORTED = 0;
-localparam logic ICACHE_SUPPORTED = 0;
-localparam logic VIRTMEM_SUPPORTED = 0;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 0;
-localparam logic BIGENDIAN_SUPPORTED = 0;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd0;
-localparam DTLB_ENTRIES = 32'd0;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd1;
-localparam logic IDIV_ON_FPU = 0;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd0;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h80000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 0;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 0;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 1;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 1;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 0;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 0;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 0;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 0;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 0;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 0;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 0;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 0;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd4;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
deleted file mode 100644
index 14c100a49..000000000
--- a/config/rv32gc/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd32;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 0;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 1; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 1;
-localparam logic ZMMUL_SUPPORTED = 1;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 1;
-localparam logic ZALRSC_SUPPORTED = 1;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 1;
-localparam logic ZBB_SUPPORTED = 1;
-localparam logic ZBS_SUPPORTED = 1;
-localparam logic ZBC_SUPPORTED = 1;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 1;
-localparam logic ZBKC_SUPPORTED = 1;
-localparam logic ZBKX_SUPPORTED = 1;
-localparam logic ZKND_SUPPORTED = 1;
-localparam logic ZKNE_SUPPORTED = 1;
-localparam logic ZKNH_SUPPORTED = 1;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 1;
-localparam logic ZCB_SUPPORTED = 1;
-localparam logic ZCF_SUPPORTED = 1; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 1; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 1;
-localparam logic D_SUPPORTED   = 1;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 1;
-localparam logic ZFA_SUPPORTED = 1;
-
-// privilege modes
-localparam logic S_SUPPORTED = 1; // Supervisor mode
-localparam logic U_SUPPORTED = 1; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 1;
-localparam logic ZIHPM_SUPPORTED  = 1;
-localparam COUNTERS = 12'd32;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 1;
-localparam logic ZICBOZ_SUPPORTED = 1;
-localparam logic ZICBOP_SUPPORTED = 1;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 0;
-localparam logic SVNAPOT_SUPPORTED = 0;
-localparam logic SVINVAL_SUPPORTED = 1;
-localparam logic SVADU_SUPPORTED   = 1;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 1;
-localparam logic DCACHE_SUPPORTED = 1;
-localparam logic ICACHE_SUPPORTED = 1;
-localparam logic VIRTMEM_SUPPORTED = 1;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam logic BIGENDIAN_SUPPORTED = 1;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd32;
-localparam DTLB_ENTRIES = 32'd32;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd2;
-localparam logic IDIV_ON_FPU = 0;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd16;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h80000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 0;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 0;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 1;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 1;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 1;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 1;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 1;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 1;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 1;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 1;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 1;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 1;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd2;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
deleted file mode 100644
index e506015e7..000000000
--- a/config/rv32gc/coverage.svh
+++ /dev/null
@@ -1,74 +0,0 @@
-// coverage.svh
-// David_Harris@hmc.edu 7 September 2024
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-// This file is needed in the config subdirectory for each config supporting coverage.
-// It defines which extensions are enabled for that config.
-
-// Define XLEN, used in covergroups
-`define XLEN32
-
-// Define relevant addresses
-`define ACCESS_FAULT_ADDRESS 32'h0000
-`define CLINT_BASE 64'h02000000
-
-// Unprivileged extensions
-`define I_COVERAGE
-`define M_COVERAGE
-`define F_COVERAGE
-`define D_COVERAGE
-`define ZBA_COVERAGE
-`define ZBB_COVERAGE
-`define ZBC_COVERAGE
-`define ZBS_COVERAGE
-`define ZFA_COVERAGE
-`define ZFH_COVERAGE
-// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used.  When Zfhmin and D are supported, ZfhD should also be enabled
-`define ZFHMIN_COVERAGE
-// Note: Zmmul is a subset of M, so usually only one or the other would be used.
-`define ZMMUL_COVERAGE
-`define ZICOND_COVERAGE
-`define ZCA_COVERAGE
-`define ZCB_COVERAGE
-`define ZCF_COVERAGE
-`define ZCD_COVERAGE
-`define ZICSR_COVERAGE
-`define ZBKB_COVERAGE
-`define ZBKC_COVERAGE
-`define ZBKX_COVERAGE
-`define ZKND_COVERAGE
-`define ZKNE_COVERAGE
-`define ZKNH_COVERAGE
-`define ZAAMO_COVERAGE
-`define ZALRSC_COVERAGE
-
-// Privileged extensions
-`define RV32VM_COVERAGE
-`define RV32VM_PMP_COVERAGE
-`define RV32PMP_COVERAGE
-`define ZICSRM_COVERAGE
-`define ZICSRS_COVERAGE
-`define ZICSRU_COVERAGE
-`define ZICSRF_COVERAGE
-`define ENDIANU_COVERAGE
-`define ENDIANS_COVERAGE
-`define ENDIANM_COVERAGE
-`define EXCEPTIONSM_COVERAGE
-`define EXCEPTIONSS_COVERAGE
-`define EXCEPTIONSU_COVERAGE
-`define EXCEPTIONSF_COVERAGE
-`define EXCEPTIONSZC_COVERAGE
-`define EXCEPTIONSZAAMO_COVERAGE
-`define EXCEPTIONSZALRSC_COVERAGE
-`define EXCEPTIONSZICBOS_COVERAGE
-`define EXCEPTIONSZICBOU_COVERAGE
-`define EXCEPTIONSVM_COVERAGE
-`define ZICNTRU_COVERAGE
-`define ZICNTRS_COVERAGE
-`define ZICNTRM_COVERAGE
-`define INTERRUPTSU_COVERAGE
-`define INTERRUPTSM_COVERAGE
-`define INTERRUPTSS_COVERAGE
-`define INTERRUPTSSSTC_COVERAGE
-`define SSSTRICTS_COVERAGE
-`define SSSTRICTM_COVERAGE
\ No newline at end of file
diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic
deleted file mode 100644
index 254c32858..000000000
--- a/config/rv32gc/imperas.ic
+++ /dev/null
@@ -1,74 +0,0 @@
-# imperas.ic
-# Initialization file for rv32gc ImperasDV lock step simulation
-# David_Harris@hmc.edu 15 August 2024
-# jcarlin@hmc.edu 19 March 2025
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Base configuration
---variant RV32GCK # for RV32GC
-
-# Bit manipulation
---override cpu/add_Extensions=B
---override cpu/misa_B_Zba_Zbb_Zbs=T
-
-# Cache block operations
---override cpu/Zicbom=T
---override cpu/Zicbop=T
---override cpu/Zicboz=T
---override cmomp_bytes=64  # Zic64b
---override cmoz_bytes=64   # Zic64b
---override lr_sc_grain=4   # Za64rs requires <=64; we use native word size
-
-# Virtual memory
---override cpu/Sv_modes=3 # SV32 supported
---override cpu/Svadu=T # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
---override cpu/Svinval=T
-
-# Crypto extensions
---override cpu/Zkr=F # Zkr entropy source and seed register not supported.
---override cpu/Zksed=F # ShangMi Crypto not supported
---override cpu/Zksh=F # ShangMi Crypto not supported
---override cpu/mnoise_undefined=T # nonratified mnoise register not implemented
-
-# Miscellaneous extensions
---override cpu/Zicond=T
---override cpu/Zfh=T
---override cpu/Zfa=T
---override cpu/Zcb=T
---override cpu/Sstc=T
-
-# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
---override cpu/ecode_mask=0x8000000F  # for RV32
-
-# Misaligned access (Zicclsm) is not supported
---override cpu/unaligned=F 
-
-# PMP Configuration
---override cpu/PMP_registers=16
---override cpu/PMP_undefined=T
-
-# PMA Settings
-# 'r': read access allowed
-# 'w': write access allowed
-# 'x': execute access allowed
-# 'a': aligned access required
-# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
-# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
-# '1': 1-byte accesses allowed
-# '2': 2-byte accesses allowed
-# '4': 4-byte accesses allowed
-# '8': 8-byte accesses allowed
-# '-', space: ignored (use for input string formatting).
-#
-# SVxx Memory 0x0000000000 0x7FFFFFFFFF
-#
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
---callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
---callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
---callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
---callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
deleted file mode 100644
index 2eb40c8d4..000000000
--- a/config/rv32i/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd32;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 0;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 0;
-localparam logic ZMMUL_SUPPORTED = 0;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 0;
-localparam logic ZALRSC_SUPPORTED = 0;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 0;
-localparam logic ZBB_SUPPORTED = 0;
-localparam logic ZBS_SUPPORTED = 0;
-localparam logic ZBC_SUPPORTED = 0;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 0;
-localparam logic ZBKC_SUPPORTED = 0;
-localparam logic ZBKX_SUPPORTED = 0;
-localparam logic ZKND_SUPPORTED = 0;
-localparam logic ZKNE_SUPPORTED = 0;
-localparam logic ZKNH_SUPPORTED = 0;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 0;
-localparam logic ZCB_SUPPORTED = 0;
-localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 0; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 0;
-localparam logic D_SUPPORTED   = 0;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 0;
-localparam logic ZFA_SUPPORTED = 0;
-
-// privilege modes
-localparam logic S_SUPPORTED = 0; // Supervisor mode
-localparam logic U_SUPPORTED = 0; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 0;
-localparam logic ZIHPM_SUPPORTED  = 0;
-localparam COUNTERS = 12'd0;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 0;
-localparam logic ZICBOZ_SUPPORTED = 0;
-localparam logic ZICBOP_SUPPORTED = 0;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 0;
-localparam logic SVNAPOT_SUPPORTED = 0;
-localparam logic SVINVAL_SUPPORTED = 0;
-localparam logic SVADU_SUPPORTED   = 0;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 0;
-localparam logic DCACHE_SUPPORTED = 0;
-localparam logic ICACHE_SUPPORTED = 0;
-localparam logic VIRTMEM_SUPPORTED = 0;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam logic BIGENDIAN_SUPPORTED = 0;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd32;
-localparam DTLB_ENTRIES = 32'd32;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam logic IDIV_ON_FPU = 0;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd0;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h80000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 1;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 1;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 0;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 0;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 0;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 0;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 0;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 0;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 0;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 1;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 0;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 0;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd4;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
deleted file mode 100644
index 6ec9d9ace..000000000
--- a/config/rv32imc/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd32;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 0;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 1;
-localparam logic ZMMUL_SUPPORTED = 1;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 0;
-localparam logic ZALRSC_SUPPORTED = 0;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 0;
-localparam logic ZBB_SUPPORTED = 0;
-localparam logic ZBS_SUPPORTED = 0;
-localparam logic ZBC_SUPPORTED = 0;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 0;
-localparam logic ZBKC_SUPPORTED = 0;
-localparam logic ZBKX_SUPPORTED = 0;
-localparam logic ZKND_SUPPORTED = 0;
-localparam logic ZKNE_SUPPORTED = 0;
-localparam logic ZKNH_SUPPORTED = 0;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 1;
-localparam logic ZCB_SUPPORTED = 0;
-localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 0; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 0;
-localparam logic D_SUPPORTED   = 0;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 0;
-localparam logic ZFA_SUPPORTED = 0;
-
-// privilege modes
-localparam logic S_SUPPORTED = 0; // Supervisor mode
-localparam logic U_SUPPORTED = 1; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 1;
-localparam logic ZIHPM_SUPPORTED  = 1;
-localparam COUNTERS = 12'd32;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 0;
-localparam logic ZICBOZ_SUPPORTED = 0;
-localparam logic ZICBOP_SUPPORTED = 0;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 0;
-localparam logic SVNAPOT_SUPPORTED = 0;
-localparam logic SVINVAL_SUPPORTED = 0;
-localparam logic SVADU_SUPPORTED   = 0;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 1;
-localparam logic DCACHE_SUPPORTED = 0;
-localparam logic ICACHE_SUPPORTED = 0;
-localparam logic VIRTMEM_SUPPORTED = 0;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam logic BIGENDIAN_SUPPORTED = 0;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd0;
-localparam DTLB_ENTRIES = 32'd0;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd2;
-localparam logic IDIV_ON_FPU = 0;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd0;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h80000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 1;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 1;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 0;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 0;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 1;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 1;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 1;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 1;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 1;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 1;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 0;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 0;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd4;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/rv32imc/coverage.svh b/config/rv32imc/coverage.svh
deleted file mode 100644
index ce01b9f35..000000000
--- a/config/rv32imc/coverage.svh
+++ /dev/null
@@ -1,30 +0,0 @@
-// coverage.svh
-// David_Harris@hmc.edu 7 September 2024
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-// This file is needed in the config subdirectory for each config supporting coverage.
-// It defines which extensions are enabled for that config.
-
-// Define XLEN, used in covergroups
-`define XLEN32
-
-// Define relevant addresses
-`define ACCESS_FAULT_ADDRESS 32'h0000
-`define CLINT_BASE 64'h02000000
-
-// Unprivileged extensions
-`define I_COVERAGE
-`define M_COVERAGE
-`define ZCA_COVERAGE
-`define ZICSR_COVERAGE
-
-// Privileged extensions
-`define ZICSRM_COVERAGE
-`define ZICSRU_COVERAGE
-`define EXCEPTIONSM_COVERAGE
-`define EXCEPTIONSU_COVERAGE
-`define EXCEPTIONSZC_COVERAGE
-`define ZICNTRU_COVERAGE
-`define ZICNTRM_COVERAGE
-`define INTERRUPTSU_COVERAGE
-`define INTERRUPTSM_COVERAGE
diff --git a/config/rv32imc/imperas.ic b/config/rv32imc/imperas.ic
deleted file mode 100644
index f68405fd5..000000000
--- a/config/rv32imc/imperas.ic
+++ /dev/null
@@ -1,47 +0,0 @@
-# imperas.ic
-# Initialization file for rv32imc ImperasDV lock step simulation
-# jcarlin@hmc.edu 15 March 2025
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Base configuration
---variant RV32IMC
-
-# No Supervisor mode
---override cpu/sub_Extensions="S"
-
-# Zifencei extension not implemented
---override cpu/Zifencei=F
-
-# Little endian only
---override cpu/endianFixed=T
-
-# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
---override cpu/ecode_mask=0x8000000F  # for RV32
-
-# No PMP
---override cpu/PMP_registers=0
---override cpu/PMP_undefined=T
-
-# PMA Settings
-# 'r': read access allowed
-# 'w': write access allowed
-# 'x': execute access allowed
-# 'a': aligned access required
-# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
-# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
-# '1': 1-byte accesses allowed
-# '2': 2-byte accesses allowed
-# '4': 4-byte accesses allowed
-# '8': 8-byte accesses allowed
-# '-', space: ignored (use for input string formatting).
-#
-# SVxx Memory 0x0000000000 0x7FFFFFFFFF
-#
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
---callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
---callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x00807FFFFF -attributes " rwx--- 1248 " # DTIM/IROM
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
deleted file mode 100644
index 9c0bef1a1..000000000
--- a/config/rv64gc/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd64;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 0;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 1; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 1; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 1;
-localparam logic ZMMUL_SUPPORTED = 1;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 1;
-localparam logic ZALRSC_SUPPORTED = 1;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 1;
-localparam logic ZBB_SUPPORTED = 1;
-localparam logic ZBS_SUPPORTED = 1;
-localparam logic ZBC_SUPPORTED = 1;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 1;
-localparam logic ZBKC_SUPPORTED = 1;
-localparam logic ZBKX_SUPPORTED = 1;
-localparam logic ZKND_SUPPORTED = 1;
-localparam logic ZKNE_SUPPORTED = 1;
-localparam logic ZKNH_SUPPORTED = 1;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 1;
-localparam logic ZCB_SUPPORTED = 1;
-localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 1; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 1;
-localparam logic D_SUPPORTED   = 1;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 1;
-localparam logic ZFA_SUPPORTED = 1;
-
-// privilege modes
-localparam logic S_SUPPORTED = 1; // Supervisor mode
-localparam logic U_SUPPORTED = 1; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 1;
-localparam logic ZIHPM_SUPPORTED  = 1;
-localparam COUNTERS = 12'd32;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 1;
-localparam logic ZICBOZ_SUPPORTED = 1;
-localparam logic ZICBOP_SUPPORTED = 1;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 1;
-localparam logic SVNAPOT_SUPPORTED = 1;
-localparam logic SVINVAL_SUPPORTED = 1;
-localparam logic SVADU_SUPPORTED   = 1;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 1;
-localparam logic DCACHE_SUPPORTED = 1;
-localparam logic ICACHE_SUPPORTED = 1;
-localparam logic VIRTMEM_SUPPORTED = 1;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam logic BIGENDIAN_SUPPORTED = 1;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd32;
-localparam DTLB_ENTRIES = 32'd32;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam logic IDIV_ON_FPU = 1;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd16;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 0;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 0;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 1;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 1;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 1;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 1;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 1;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 1;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 1;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 1;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 1;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 1;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd4;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
deleted file mode 100644
index 67ad14410..000000000
--- a/config/rv64gc/coverage.svh
+++ /dev/null
@@ -1,75 +0,0 @@
-// coverage.svh
-// David_Harris@hmc.edu 7 September 2024
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-// This file is needed in the config subdirectory for each config supporting coverage.
-// It defines which extensions are enabled for that config.
-
-// Define XLEN, used in covergroups
-`define XLEN64
-
-// Define relevant addresses
-`define ACCESS_FAULT_ADDRESS 64'h00000000
-`define CLINT_BASE 64'h02000000
-
-// Unprivileged extensions
-`define I_COVERAGE
-`define M_COVERAGE
-`define F_COVERAGE
-`define D_COVERAGE
-`define ZBA_COVERAGE
-`define ZBB_COVERAGE
-`define ZBC_COVERAGE
-`define ZBS_COVERAGE
-`define ZFA_COVERAGE
-`define ZFH_COVERAGE
-// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used.  When Zfhmin and D are supported, ZfhD should also be enabled
-`define ZFHMIN_COVERAGE
-// Note: Zmmul is a subset of M, so usually only one or the other would be used.
-`define ZMMUL_COVERAGE
-`define ZICOND_COVERAGE
-`define ZCA_COVERAGE
-`define ZCB_COVERAGE
-`define ZCD_COVERAGE
-`define ZICSR_COVERAGE
-`define ZBKB_COVERAGE
-`define ZBKC_COVERAGE
-`define ZBKX_COVERAGE
-`define ZKND_COVERAGE
-`define ZKNE_COVERAGE
-`define ZKNH_COVERAGE
-`define ZAAMO_COVERAGE
-`define ZALRSC_COVERAGE
-
-// Privileged extensions
-`define RV64VM_COVERAGE
-`define ZICSRM_COVERAGE
-`define ZICSRS_COVERAGE
-`define ZICSRU_COVERAGE
-`define ZICSRF_COVERAGE
-`define ENDIANU_COVERAGE
-`define ENDIANS_COVERAGE
-`define ENDIANM_COVERAGE
-`define EXCEPTIONSM_COVERAGE
-`define EXCEPTIONSS_COVERAGE
-`define EXCEPTIONSU_COVERAGE
-`define EXCEPTIONSF_COVERAGE
-`define EXCEPTIONSZC_COVERAGE
-`define EXCEPTIONSVM_COVERAGE
-`define EXCEPTIONSZAAMO_COVERAGE
-`define EXCEPTIONSZALRSC_COVERAGE
-`define EXCEPTIONSZICBOS_COVERAGE
-`define EXCEPTIONSZICBOU_COVERAGE
-`define ZICNTRU_COVERAGE
-`define ZICNTRS_COVERAGE
-`define ZICNTRM_COVERAGE
-`define INTERRUPTSU_COVERAGE
-`define INTERRUPTSM_COVERAGE
-`define INTERRUPTSS_COVERAGE
-`define INTERRUPTSSSTC_COVERAGE
-`define SSSTRICTS_COVERAGE
-`define SSSTRICTM_COVERAGE
-
-// `define RV64VM_PMP_COVERAGE
-// `define RV64CBO_VM_COVERAGE
-// `define RV64CBO_PMP_COVERAGE
diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic
deleted file mode 100644
index 2e2a74478..000000000
--- a/config/rv64gc/imperas.ic
+++ /dev/null
@@ -1,77 +0,0 @@
-# imperas.ic
-# Initialization file for rv64gc ImperasDV lock step simulation
-# David_Harris@hmc.edu 15 August 2024
-# jcarlin@hmc.edu 19 March 2025
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Base configuration
---variant RV64GCK # for RV64GC
-
-# Bit manipulation
---override cpu/add_Extensions=B
---override cpu/misa_B_Zba_Zbb_Zbs=T
-
-# Cache block operations
---override cpu/Zicbom=T
---override cpu/Zicbop=T
---override cpu/Zicboz=T
---override cmomp_bytes=64  # Zic64b
---override cmoz_bytes=64   # Zic64b
---override lr_sc_grain=8   # Za64rs requires <=64; we use native word size
-
-# Virtual memory
---override cpu/Sv_modes=768 # SV39 and SV48 supported
---override cpu/Svadu=T # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
---override cpu/Svinval=T
---override cpu/Svpbmt=T
---override cpu/aligned_uncached_PBMT=T # when PBMT designates a page as uncachable, require aligned accesses
---override cpu/Svnapot_page_mask=65536 # 64 KiB continuous huge pages supported
-
-# Crypto extensions
---override cpu/Zkr=F # Zkr entropy source and seed register not supported.
---override cpu/Zksed=F # ShangMi Crypto not supported
---override cpu/Zksh=F # ShangMi Crypto not supported
---override cpu/mnoise_undefined=T # nonratified mnoise register not implemented
-
-# Miscellaneous extensions
---override cpu/Zicond=T
---override cpu/Zfh=T
---override cpu/Zfa=T
---override cpu/Zcb=T
---override cpu/Sstc=T
-
-# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
---override cpu/ecode_mask=0x800000000000000F # for RV64
-
-# Misaligned access (Zicclsm) is supported
---override cpu/unaligned=T
-
-# PMP Configuration
---override cpu/PMP_registers=16
---override cpu/PMP_undefined=T
-
-# PMA Settings
-# 'r': read access allowed
-# 'w': write access allowed
-# 'x': execute access allowed
-# 'a': aligned access required
-# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
-# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
-# '1': 1-byte accesses allowed
-# '2': 2-byte accesses allowed
-# '4': 4-byte accesses allowed
-# '8': 8-byte accesses allowed
-# '-', space: ignored (use for input string formatting).
-#
-# SVxx Memory 0x0000000000 0x7FFFFFFFFF
-#
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
---callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
---callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
---callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
---callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
---callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0
---callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO
---callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI
---callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
deleted file mode 100644
index 1779d764d..000000000
--- a/config/rv64i/config.vh
+++ /dev/null
@@ -1,227 +0,0 @@
-//////////////////////////////////////////
-// config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
-//
-// Purpose: Specify which features of Wally are enabled and set
-//          configuration parameters
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "BranchPredictorType.vh"
-
-// RV32 or RV64: XLEN = 32 or 64
-localparam XLEN = 32'd64;
-
-// IEEE 754 compliance
-localparam logic IEEE754 = 0;
-
-// RISC-V configuration per specification
-// Base instruction set (defaults to I if E is not supported)
-localparam logic E_SUPPORTED = 0;
-
-// Integer instruction set extensions
-localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
-localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
-localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
-
-// Multiplication & division extensions
-// M implies (and in the configuration file requires) Zmmul
-localparam logic M_SUPPORTED     = 0;
-localparam logic ZMMUL_SUPPORTED = 0;
-
-// Atomic extensions
-// A extension is Zaamo + Zalrsc
-localparam logic ZAAMO_SUPPORTED  = 0;
-localparam logic ZALRSC_SUPPORTED = 0;
-
-// Bit manipulation extensions
-// B extension is Zba + Zbb + Zbs
-localparam logic ZBA_SUPPORTED = 0;
-localparam logic ZBB_SUPPORTED = 0;
-localparam logic ZBS_SUPPORTED = 0;
-localparam logic ZBC_SUPPORTED = 0;
-
-// Scalar crypto extensions
-// Zkn is all 6 of these
-localparam logic ZBKB_SUPPORTED = 0;
-localparam logic ZBKC_SUPPORTED = 0;
-localparam logic ZBKX_SUPPORTED = 0;
-localparam logic ZKND_SUPPORTED = 0;
-localparam logic ZKNE_SUPPORTED = 0;
-localparam logic ZKNH_SUPPORTED = 0;
-
-// Compressed extensions
-// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
-// All compressed extensions require Zca
-localparam logic ZCA_SUPPORTED = 0;
-localparam logic ZCB_SUPPORTED = 0;
-localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
-localparam logic ZCD_SUPPORTED = 0; // requires D
-
-// Floating point extensions
-localparam logic F_SUPPORTED   = 0;
-localparam logic D_SUPPORTED   = 0;
-localparam logic Q_SUPPORTED   = 0;
-localparam logic ZFH_SUPPORTED = 0;
-localparam logic ZFA_SUPPORTED = 0;
-
-// privilege modes
-localparam logic S_SUPPORTED = 0; // Supervisor mode
-localparam logic U_SUPPORTED = 0; // User mode
-
-// Supervisor level extensions
-localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
-
-// Hardware performance counters
-localparam logic ZICNTR_SUPPORTED = 0;
-localparam logic ZIHPM_SUPPORTED  = 0;
-localparam COUNTERS = 12'd0;
-
-// Cache-management operation extensions
-localparam logic ZICBOM_SUPPORTED = 0;
-localparam logic ZICBOZ_SUPPORTED = 0;
-localparam logic ZICBOP_SUPPORTED = 0;
-
-// Virtual memory extensions
-localparam logic SVPBMT_SUPPORTED  = 0;
-localparam logic SVNAPOT_SUPPORTED = 0;
-localparam logic SVINVAL_SUPPORTED = 0;
-localparam logic SVADU_SUPPORTED   = 0;
-
-
-// LSU microarchitectural Features
-localparam logic BUS_SUPPORTED = 0;
-localparam logic DCACHE_SUPPORTED = 0;
-localparam logic ICACHE_SUPPORTED = 0;
-localparam logic VIRTMEM_SUPPORTED = 0;
-localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam logic BIGENDIAN_SUPPORTED = 0;
-
-// TLB configuration.  Entries should be a power of 2
-localparam ITLB_ENTRIES = 32'd0;
-localparam DTLB_ENTRIES = 32'd0;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
-localparam DCACHE_NUMWAYS = 32'd4;
-localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
-localparam DCACHE_LINELENINBITS = 32'd512;
-localparam ICACHE_NUMWAYS = 32'd4;
-localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
-localparam ICACHE_LINELENINBITS = 32'd512;
-localparam CACHE_SRAMLEN = 32'd128;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam logic IDIV_ON_FPU = 0;
-
-// Legal number of PMP entries are 0, 16, or 64
-localparam PMP_ENTRIES = 32'd0;
-
-// Address space
-localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
-
-// WFI Timeout Wait
-localparam WFI_TIMEOUT_BIT = 32'd16;
-
-// Peripheral Physical Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam logic DTIM_SUPPORTED = 1;
-localparam logic [63:0] DTIM_BASE        = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE       = 64'h007FFFFF;
-localparam logic IROM_SUPPORTED = 1;
-localparam logic [63:0] IROM_BASE        = 64'h80000000;
-localparam logic [63:0] IROM_RANGE       = 64'h007FFFFF;
-localparam logic BOOTROM_SUPPORTED = 0;
-localparam logic [63:0] BOOTROM_BASE     = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE    = 64'h00000FFF;
-localparam logic BOOTROM_PRELOAD = 1'b0;
-localparam logic UNCORE_RAM_SUPPORTED = 0;
-localparam logic [63:0] UNCORE_RAM_BASE  = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
-localparam logic UNCORE_RAM_PRELOAD = 1'b0;
-localparam logic EXT_MEM_SUPPORTED = 0;
-localparam logic [63:0] EXT_MEM_BASE     = 64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE    = 64'h07FFFFFF;
-localparam logic CLINT_SUPPORTED = 0;
-localparam logic [63:0] CLINT_BASE       = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE      = 64'h0000FFFF;
-localparam logic GPIO_SUPPORTED = 0;
-localparam logic [63:0] GPIO_BASE        = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE       = 64'h000000FF;
-localparam logic UART_SUPPORTED = 0;
-localparam logic [63:0] UART_BASE        = 64'h10000000;
-localparam logic [63:0] UART_RANGE       = 64'h00000007;
-localparam logic PLIC_SUPPORTED = 0;
-localparam logic [63:0] PLIC_BASE        = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE       = 64'h03FFFFFF;
-localparam logic SDC_SUPPORTED = 0;
-localparam logic [63:0] SDC_BASE         = 64'h00013000;
-localparam logic [63:0] SDC_RANGE        = 64'h00000FFF;
-localparam logic SPI_SUPPORTED = 0;
-localparam logic [63:0] SPI_BASE         = 64'h10040000;
-localparam logic [63:0] SPI_RANGE        = 64'h00000FFF;
-
-// Bus Interface width
-localparam AHBW = (XLEN);
-
-// Test modes
-
-// AHB 
-localparam RAM_LATENCY = 32'b0;
-localparam logic BURST_EN = 1;
-
-// Tie GPIO outputs back to inputs
-localparam logic GPIO_LOOPBACK_TEST = 1;
-localparam logic SPI_LOOPBACK_TEST  = 1;
-
-// Hardware configuration
-localparam UART_PRESCALE = 32'd1;
-
-// Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10;
-// comment out the following if >=32 sources
-localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
-localparam PLIC_GPIO_ID = 32'd3;
-localparam PLIC_UART_ID = 32'd10;
-localparam PLIC_SPI_ID = 32'd6;
-localparam PLIC_SDC_ID = 32'd9;
-
-// Branch prediction
-localparam logic BPRED_SUPPORTED = 0;
-localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_SIZE = 32'd10;
-localparam BPRED_NUM_LHR = 32'd6;
-localparam BTB_SIZE = 32'd10;
-localparam RAS_SIZE = 32'd16;
-localparam INSTR_CLASS_PRED = 0;
-
-// FPU division architecture
-localparam RADIX = 32'd4;
-localparam DIVCOPIES = 32'd4;
-
-// Memory synthesis configuration
-localparam logic USE_SRAM = 0;
-
-`include "config-shared.vh"
diff --git a/config/shared/BranchPredictorType.vh b/config/shared/BranchPredictorType.vh
deleted file mode 100644
index 4b88574a8..000000000
--- a/config/shared/BranchPredictorType.vh
+++ /dev/null
@@ -1,8 +0,0 @@
-`define BP_TWOBIT       (32'd0)
-`define BP_GSHARE       (32'd1)
-`define BP_GLOBAL       (32'd2)
-`define BP_GSHARE_BASIC (32'd3)
-`define BP_GLOBAL_BASIC (32'd4)
-`define BP_LOCAL_BASIC  (32'd5)
-`define BP_LOCAL_AHEAD  (32'd6)
-`define BP_LOCAL_REPAIR (32'd7)
diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
deleted file mode 100644
index 4ccb24bf2..000000000
--- a/config/shared/config-shared.vh
+++ /dev/null
@@ -1,124 +0,0 @@
-//max function
-`define max(a,b) (((a) > (b)) ? (a) : (b))
-
-// constants defining different privilege modes
-// defined in Table 1.1 of the privileged spec
-localparam M_MODE  = (2'b11);
-localparam S_MODE  = (2'b01);
-localparam U_MODE  = (2'b00);
-
-// Virtual Memory Constants
-localparam VPN_SEGMENT_BITS = (XLEN == 32 ? 32'd10 : 32'd9);
-localparam VPN_BITS = (XLEN==32 ? (2*VPN_SEGMENT_BITS) : (4*VPN_SEGMENT_BITS));
-localparam PPN_BITS = (XLEN==32 ? 32'd22 : 32'd44);
-localparam PA_BITS = (XLEN==32 ? 32'd34 : 32'd56);
-localparam SVMODE_BITS = (XLEN==32 ? 32'd1 : 32'd4);
-localparam ASID_BASE = (XLEN==32 ? 32'd22 : 32'd44);
-localparam ASID_BITS = (XLEN==32 ? 32'd9 : 32'd16);
-
-// constants to check SATP_MODE against
-// defined in Table 4.3 of the privileged spec
-localparam NO_TRANSLATE = 4'd0;
-localparam SV32 = 4'd1;
-localparam SV39 = 4'd8;
-localparam SV48 = 4'd9;
-
-// macros to define supported modes
-localparam logic I_SUPPORTED = (!E_SUPPORTED);
-localparam logic A_SUPPORTED = (ZAAMO_SUPPORTED & ZALRSC_SUPPORTED);
-localparam logic B_SUPPORTED = ((ZBA_SUPPORTED & ZBB_SUPPORTED & ZBS_SUPPORTED));
-localparam logic C_SUPPORTED = ZCA_SUPPORTED & (D_SUPPORTED ? ZCD_SUPPORTED : 1) & (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
-localparam logic ZKN_SUPPORTED = (ZBKB_SUPPORTED & ZBKC_SUPPORTED & ZBKX_SUPPORTED & ZKND_SUPPORTED & ZKNE_SUPPORTED & ZKNH_SUPPORTED);
-
-// Configure MISA based on supported extensions
-localparam MISA = {6'b0, 5'b0, U_SUPPORTED, 1'b0, S_SUPPORTED, 1'b0, Q_SUPPORTED, 3'b0, M_SUPPORTED, 3'b0, I_SUPPORTED, 2'b0, 
-                   F_SUPPORTED, E_SUPPORTED, D_SUPPORTED, C_SUPPORTED, B_SUPPORTED, A_SUPPORTED};
-
-// logarithm of XLEN, used for number of index bits to select
-localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
-
-// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
-localparam PMPCFG_ENTRIES = (PMP_ENTRIES/32'd8);
-
-// Floating point constants for Quad, Double, Single, and Half precisions
-// Lim: I've made some of these 64 bit to avoid width warnings. 
-// If errors crop up, try downsizing back to 32.
-localparam Q_LEN = 32'd128;
-localparam Q_NE = 32'd15;
-localparam Q_NF = 32'd112;
-localparam Q_BIAS = 32'd16383;
-localparam Q_FMT = 2'd3;
-localparam D_LEN = 32'd64;
-localparam D_NE = 32'd11;
-localparam D_NF = 32'd52;
-localparam D_BIAS = 32'd1023;
-localparam D_FMT = 2'd1;
-localparam S_LEN = 32'd32;
-localparam S_NE = 32'd8;
-localparam S_NF = 32'd23;
-localparam S_BIAS = 32'd127;
-localparam S_FMT = 2'd0;
-localparam H_LEN = 32'd16;
-localparam H_NE = 32'd5;
-localparam H_NF = 32'd10;
-localparam H_BIAS = 32'd15;
-localparam H_FMT = 2'd2;
-
-// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits (for longest format supported)
-localparam FLEN = Q_SUPPORTED ? Q_LEN  : D_SUPPORTED ? D_LEN  : S_LEN;
-localparam NE   = Q_SUPPORTED ? Q_NE   : D_SUPPORTED ? D_NE   : S_NE;
-localparam NF   = Q_SUPPORTED ? Q_NF   : D_SUPPORTED ? D_NF   : S_NF;
-localparam FMT  = Q_SUPPORTED ? 2'd3   : D_SUPPORTED ? 2'd1   : 2'd0;
-localparam BIAS = Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS;
-localparam LOGFLEN = $clog2(FLEN);
-
-// Floating point constants needed for FPU paramerterization
-// LEN1/NE1/NF1/FNT1 is the size of the second longest supported format
-localparam FPSIZES = (32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED);
-localparam FMTBITS = (32)'(FPSIZES>=3)+1;
-localparam LEN1  = (FLEN > D_LEN) ? D_LEN  : (FLEN > S_LEN) ? S_LEN  : H_LEN;
-localparam NE1   = (FLEN > D_LEN) ? D_NE   : (FLEN > S_LEN) ? S_NE   : H_NE;
-localparam NF1   = (FLEN > D_LEN) ? D_NF   : (FLEN > S_LEN) ? S_NF   : H_NF;
-localparam FMT1  = (FLEN > D_LEN) ? 2'd1   : (FLEN > S_LEN) ? 2'd0   : 2'd2;
-localparam BIAS1 = (FLEN > D_LEN) ? D_BIAS : (FLEN > S_LEN) ? S_BIAS : H_BIAS;
-
-// LEN2 etc is the size of the third longest supported format
-localparam LEN2  = (LEN1 > S_LEN) ? S_LEN  : H_LEN;
-localparam NE2   = (LEN1 > S_LEN) ? S_NE   : H_NE;
-localparam NF2   = (LEN1 > S_LEN) ? S_NF   : H_NF;
-localparam FMT2  = (LEN1 > S_LEN) ? 2'd0   : 2'd2;
-localparam BIAS2 = (LEN1 > S_LEN) ? S_BIAS : H_BIAS;
-
-// divider r and rk (bits per digit, bits per cycle)
-localparam LOGR        = $clog2(RADIX);                             // r = log(R) bits per digit
-localparam RK          = LOGR*DIVCOPIES;                            // r*k bits per cycle generated
-
-// intermediate division parameters not directly used in fdivsqrt hardware
-localparam FPDIVMINb   = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
-localparam DIVMINb     = ((FPDIVMINb<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVMINb; // minimum fractional bits b = max(XLEN, FPDIVMINb)
-localparam RESBITS     = DIVMINb + LOGR; // number of bits in a result: r integer + b fractional
-                 
-// division constants
-localparam FPDUR       = (RESBITS-1)/RK + 1 ;                       // ceiling((r+b)/rk)
-localparam DIVb        = FPDUR*RK - LOGR;                           // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits
-localparam DURLEN      = $clog2(FPDUR);                             // enough bits to count the duration
-localparam DIVBLEN     = $clog2(DIVb+1);                            // enough bits to count number of fractional bits + 1 integer bit
-
-// integer division/remainder constants
-localparam INTRESBITS     = XLEN + LOGR; // number of bits in a result: r integer + XLEN fractional
-localparam INTFPDUR       = (INTRESBITS-1)/RK + 1 ;                 
-localparam INTDIVb        = INTFPDUR*RK - LOGR;                     
-
-// largest length in IEU/FPU
-localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d
-localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
-localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
-localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
-
-// size of FMA output in U(NF+4).(3NF+2) format
-localparam FMALEN = 3*NF + 6;
-
-// NORMSHIFTSIZE is the bits out of the normalization shifter
-localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
-
-localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
diff --git a/config/shared/imperas-shared.ic b/config/shared/imperas-shared.ic
deleted file mode 100644
index 6578c2890..000000000
--- a/config/shared/imperas-shared.ic
+++ /dev/null
@@ -1,32 +0,0 @@
-# imperas.ic
-# Standard initialization file for ImperasDV lock step simulation
-# jcarlin@hmc.edu 19 March 2025
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# Spec versions
---override cpu/priv_version=1.12
---override cpu/user_version=20191213
-
-# arch
---override cpu/mimpid=0x100
---override cpu/mvendorid=0x602
---override cpu/marchid=0x24
---override refRoot/cpu/tvec_align=64
-
-# MISA not writable
---override cpu/misa_Extensions_mask=0x0
-
-# disable CSRs 7a0-7a8
---override cpu/trigger_num=0
-
-# Reset address
---override cpu/reset_address=0x80000000
-
-# For code coverage, don't produce pseudoinstructions
---override no_pseudo_inst=T
-
-# Show "c." with compressed instructions
---override show_c_prefix=T
-
-# Store simulator output to logfile
---output imperas.log
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
deleted file mode 100644
index 88de34afc..000000000
--- a/config/shared/parameter-defs.vh
+++ /dev/null
@@ -1,201 +0,0 @@
-
-// Populate parameter structure with values specific to the current configuration
-
-`include "BranchPredictorType.vh"
-
-localparam cvw_t P = '{ 
-  XLEN :                 XLEN,  
-  IEEE754 :              IEEE754, 
-  MISA :                 MISA, 
-  AHBW :                 AHBW, 
-  RAM_LATENCY :          RAM_LATENCY,
-  BURST_EN :             BURST_EN,
-  ZICSR_SUPPORTED :      ZICSR_SUPPORTED,
-  ZIFENCEI_SUPPORTED :   ZIFENCEI_SUPPORTED,
-  COUNTERS :             COUNTERS,
-  ZICNTR_SUPPORTED :     ZICNTR_SUPPORTED,
-  ZIHPM_SUPPORTED :      ZIHPM_SUPPORTED,
-  ZFH_SUPPORTED :        ZFH_SUPPORTED,
-  ZFA_SUPPORTED :        ZFA_SUPPORTED,
-  SSTC_SUPPORTED :       SSTC_SUPPORTED,
-  VIRTMEM_SUPPORTED :    VIRTMEM_SUPPORTED,
-  VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
-  BIGENDIAN_SUPPORTED :  BIGENDIAN_SUPPORTED,
-  SVADU_SUPPORTED :      SVADU_SUPPORTED,
-  ZMMUL_SUPPORTED :      ZMMUL_SUPPORTED,
-  ZICBOM_SUPPORTED :     ZICBOM_SUPPORTED,
-  ZICBOZ_SUPPORTED :     ZICBOZ_SUPPORTED,
-  ZICBOP_SUPPORTED :     ZICBOP_SUPPORTED,
-  ZICCLSM_SUPPORTED :    ZICCLSM_SUPPORTED,
-  ZICOND_SUPPORTED :     ZICOND_SUPPORTED,
-  SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
-  SVNAPOT_SUPPORTED :    SVNAPOT_SUPPORTED,
-  SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
-  ZAAMO_SUPPORTED :      ZAAMO_SUPPORTED,
-  ZALRSC_SUPPORTED :     ZALRSC_SUPPORTED, 
-  BUS_SUPPORTED :        BUS_SUPPORTED,
-  DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
-  ICACHE_SUPPORTED :     ICACHE_SUPPORTED,
-  ITLB_ENTRIES :         ITLB_ENTRIES,
-  DTLB_ENTRIES :         DTLB_ENTRIES,
-  DCACHE_NUMWAYS :       DCACHE_NUMWAYS,
-  DCACHE_WAYSIZEINBYTES :        DCACHE_WAYSIZEINBYTES,
-  DCACHE_LINELENINBITS :        DCACHE_LINELENINBITS,
-  ICACHE_NUMWAYS :        ICACHE_NUMWAYS,
-  ICACHE_WAYSIZEINBYTES :        ICACHE_WAYSIZEINBYTES,
-  ICACHE_LINELENINBITS :        ICACHE_LINELENINBITS,
-  CACHE_SRAMLEN : CACHE_SRAMLEN,
-  IDIV_BITSPERCYCLE :        IDIV_BITSPERCYCLE,
-  IDIV_ON_FPU :        IDIV_ON_FPU,
-  PMP_ENTRIES :        PMP_ENTRIES,
-  RESET_VECTOR :        RESET_VECTOR,
-  WFI_TIMEOUT_BIT :        WFI_TIMEOUT_BIT,
-  DTIM_SUPPORTED :        DTIM_SUPPORTED,
-  DTIM_BASE :        DTIM_BASE,
-  DTIM_RANGE :        DTIM_RANGE,
-  IROM_SUPPORTED :        IROM_SUPPORTED,
-  IROM_BASE :        IROM_BASE,
-  IROM_RANGE :        IROM_RANGE,
-  BOOTROM_SUPPORTED :        BOOTROM_SUPPORTED,
-  BOOTROM_BASE :        BOOTROM_BASE,
-  BOOTROM_RANGE :        BOOTROM_RANGE,
-  BOOTROM_PRELOAD : BOOTROM_PRELOAD,
-  UNCORE_RAM_SUPPORTED :        UNCORE_RAM_SUPPORTED,
-  UNCORE_RAM_BASE :        UNCORE_RAM_BASE,
-  UNCORE_RAM_RANGE :        UNCORE_RAM_RANGE,
-  UNCORE_RAM_PRELOAD : UNCORE_RAM_PRELOAD,
-  EXT_MEM_SUPPORTED :        EXT_MEM_SUPPORTED,
-  EXT_MEM_BASE :        EXT_MEM_BASE,
-  EXT_MEM_RANGE :        EXT_MEM_RANGE,
-  CLINT_SUPPORTED :        CLINT_SUPPORTED,
-  CLINT_BASE :        CLINT_BASE,
-  CLINT_RANGE :        CLINT_RANGE,
-  GPIO_SUPPORTED :        GPIO_SUPPORTED,
-  GPIO_BASE :        GPIO_BASE,
-  GPIO_RANGE :        GPIO_RANGE,
-  UART_SUPPORTED :        UART_SUPPORTED,
-  UART_BASE :        UART_BASE,
-  UART_RANGE :        UART_RANGE,
-  PLIC_SUPPORTED :        PLIC_SUPPORTED,
-  PLIC_BASE :        PLIC_BASE,
-  PLIC_RANGE :        PLIC_RANGE,
-  SDC_SUPPORTED :        SDC_SUPPORTED,
-  SDC_BASE :        SDC_BASE,
-  SDC_RANGE :        SDC_RANGE,
-  SPI_SUPPORTED :        SPI_SUPPORTED,
-  SPI_BASE :        SPI_BASE,
-  SPI_RANGE :        SPI_RANGE,
-  GPIO_LOOPBACK_TEST :        GPIO_LOOPBACK_TEST,
-  SPI_LOOPBACK_TEST :        SPI_LOOPBACK_TEST,
-  UART_PRESCALE :        UART_PRESCALE ,
-  PLIC_NUM_SRC :        PLIC_NUM_SRC,
-  PLIC_NUM_SRC_LT_32 :        PLIC_NUM_SRC_LT_32,
-  PLIC_GPIO_ID :        PLIC_GPIO_ID,
-  PLIC_UART_ID :        PLIC_UART_ID,
-  PLIC_SPI_ID :        PLIC_SPI_ID,
-  PLIC_SDC_ID :        PLIC_SDC_ID,
-  BPRED_SUPPORTED :        BPRED_SUPPORTED,
-  BPRED_TYPE :        BPRED_TYPE,
-  BPRED_SIZE :        BPRED_SIZE,
-  BPRED_NUM_LHR : BPRED_NUM_LHR,                       
-  BTB_SIZE :        BTB_SIZE,
-  RAS_SIZE :        RAS_SIZE,
-  INSTR_CLASS_PRED :  INSTR_CLASS_PRED,
-  RADIX :        RADIX,
-  DIVCOPIES :        DIVCOPIES,
-  ZBA_SUPPORTED :        ZBA_SUPPORTED,
-  ZBB_SUPPORTED :        ZBB_SUPPORTED,
-  ZBC_SUPPORTED :        ZBC_SUPPORTED,
-  ZBS_SUPPORTED :        ZBS_SUPPORTED,
-  ZCA_SUPPORTED :        ZCA_SUPPORTED,
-  ZCB_SUPPORTED :        ZCB_SUPPORTED,
-  ZCD_SUPPORTED :        ZCD_SUPPORTED,
-  ZCF_SUPPORTED :        ZCF_SUPPORTED,
-  ZBKB_SUPPORTED:        ZBKB_SUPPORTED,
-  ZBKC_SUPPORTED:        ZBKC_SUPPORTED,
-  ZBKX_SUPPORTED:        ZBKX_SUPPORTED,
-  ZKND_SUPPORTED:        ZKND_SUPPORTED,
-  ZKNE_SUPPORTED:        ZKNE_SUPPORTED,
-  ZKNH_SUPPORTED:        ZKNH_SUPPORTED,
-  ZKN_SUPPORTED :        ZKN_SUPPORTED,
-  USE_SRAM :        USE_SRAM,
-  M_MODE  : M_MODE, 
-  S_MODE  : S_MODE, 
-  U_MODE  : U_MODE, 
-  VPN_SEGMENT_BITS : VPN_SEGMENT_BITS,
-  VPN_BITS : VPN_BITS,
-  PPN_BITS : PPN_BITS,
-  PA_BITS : PA_BITS,
-  SVMODE_BITS : SVMODE_BITS,
-  ASID_BASE : ASID_BASE,
-  ASID_BITS : ASID_BITS,
-  NO_TRANSLATE : NO_TRANSLATE,
-  SV32 : SV32,
-  SV39 : SV39,
-  SV48 : SV48,
-  A_SUPPORTED : A_SUPPORTED,
-  B_SUPPORTED : B_SUPPORTED,
-  C_SUPPORTED : C_SUPPORTED,
-  D_SUPPORTED : D_SUPPORTED,
-  E_SUPPORTED : E_SUPPORTED,
-  F_SUPPORTED : F_SUPPORTED,
-  I_SUPPORTED : I_SUPPORTED,
-  M_SUPPORTED : M_SUPPORTED,
-  Q_SUPPORTED : Q_SUPPORTED,
-  S_SUPPORTED : S_SUPPORTED,
-  U_SUPPORTED : U_SUPPORTED,
-  LOG_XLEN : LOG_XLEN,
-  PMPCFG_ENTRIES : PMPCFG_ENTRIES,
-  Q_LEN : Q_LEN,
-  Q_NE : Q_NE,
-  Q_NF : Q_NF,
-  Q_BIAS : Q_BIAS,
-  Q_FMT : Q_FMT,
-  D_LEN : D_LEN,
-  D_NE : D_NE,
-  D_NF : D_NF,
-  D_BIAS : D_BIAS,
-  D_FMT : D_FMT,
-  S_LEN : S_LEN,
-  S_NE : S_NE,
-  S_NF : S_NF,
-  S_BIAS : S_BIAS,
-  S_FMT : S_FMT,
-  H_LEN : H_LEN,
-  H_NE : H_NE,
-  H_NF : H_NF,
-  H_BIAS : H_BIAS,
-  H_FMT : H_FMT,
-  FLEN : FLEN,
-  LOGFLEN : LOGFLEN,
-  NE   : NE  ,
-  NF   : NF  ,
-  FMT  : FMT ,
-  BIAS : BIAS,
-  FPSIZES : FPSIZES,
-  FMTBITS : FMTBITS,
-  LEN1  : LEN1 ,
-  NE1   : NE1  ,
-  NF1   : NF1  ,
-  FMT1  : FMT1 ,
-  BIAS1 : BIAS1,
-  LEN2  : LEN2 ,
-  NE2   : NE2  ,
-  NF2   : NF2  ,
-  FMT2  : FMT2 ,
-  BIAS2 : BIAS2,
-  CVTLEN : CVTLEN,
-  LLEN : LLEN,
-  LOGCVTLEN : LOGCVTLEN,
-  FMALEN : FMALEN,
-  NORMSHIFTSZ : NORMSHIFTSZ,
-  LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
-  LOGR        : LOGR,
-  RK          : RK,
-  FPDUR       : FPDUR,
-  DURLEN      : DURLEN,
-  DIVb        : DIVb,
-  DIVBLEN     : DIVBLEN,
-  INTDIVb     : INTDIVb
-};
-
diff --git a/docs/D-Docker-Install.md b/docs/D-Docker-Install.md
deleted file mode 100644
index 25fb3c4d1..000000000
--- a/docs/D-Docker-Install.md
+++ /dev/null
@@ -1,206 +0,0 @@
-D Wally Toolchain Docker Container
-
-Installing RISC-V tools from source gives you maximum control, but has several disadvantages:
-
-* Building the executables takes several hours.
-* Linux is poorly standardized, and the build steps might not work on your version
-* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
-
-Docker is a tools to run applications in a prepackaged container including all of the operating system support required.  Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux.  It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository.
-
-Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io).
-
-Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat.  Both Docker and Podman run the same containers.  
-
-D.3.1	Podman Installation on Linux
-
-A system administrator must install Podman if it is not already present.
-
-For Ubuntu 20.10 or later:
-
-$ sudo apt-get -y install podman
-
-For RedHat / Rocky:
-
-$ sudo yum -y install podman
-
-D.3.2	Pulling the Wally Container
-
-Once Podman is installed, a user can pull the Wally container image.  The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login.
-
-$ podman login docker.io
-$ podman pull docker.io/wallysoc/wally-docker:latest
-
-D.3.3	Running the Docker Container in Podman
-
-To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below.  For example, the user ben is on port X51.  
-
-$ ls -la /tmp/.X11-unix/
-drwxrwxrwt   2 root    root     4096 Jan  6 05:01 .
-drwxrwxrwt 122 root    root    40960 Jan 17 08:09 ..
-srwxrwxrwx   1 root    root        0 Jan  5 08:48 X0
-srwxrwxrwx   1 xwalter xwalter     0 Jan  5 09:21 X50
-srwxrwxrwx   1 ben     ben         0 Jan  6 05:01 X51
-
-Then run podman with the display number after the X (51 in this case).  The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container.  Change these as necessary based on your local system configuration.
-
-$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker
-
-Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously.  This shared directory is called $RISCV.  This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run.  It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container.
-
-To have permission to write to your mounted home directory, you must become root inside the Wally container.  This is an acceptable practice as the security will be maintained within podman for the user that runs podman.  To become root once inside your container:
-  
-$ su			# when prompted for password, enter wally
-
-D.3.4	Cleaning up a Podman Container
-
-The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore.
-The images that are loaded can be examined, once you pull the Wally container, by typing:
-
-$ podman images 
-
-To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the  podman images command (this command also works equally well using the <Image_ID> instead of the <Image_name>, as well). 
-
-$ podman rmi -f <Image_name> 
-
-D.3.5	Running the Docker Container on Windows or MacOS
-
-Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com.  Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily.  
-
-*** with Questa
-*** questa unavailable native on Mac
-
-
-D.3.6	Regenerating the Docker File
-
-We use the following steps to generate the Docker file.  You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment.
-
-*** how to use this
-
-# Compliance Development Environment Image
-FROM debian
-
-# UPDATE / UPGRADE
-RUN apt update
-
-# INSTALL
-RUN apt install -y git gawk make texinfo bison flex build-essential python libz-
-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build
--essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-
-dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zl
-ib1g-dev verilator cpio bc vim emacs gedit nano
-
-RUN pip3 install chardet==3.0.4
-RUN pip3 install urllib3==1.22
-RUN pip3 install testresources
-RUN pip3 install riscof --ignore-installed PyYAML
-RUN echo "root:wally" | chpasswd
-
-# ADD RISCV
-WORKDIR /opt/riscv
-
-# Create a user group 'xyzgroup'
-ARG USERNAME=cad
-ARG USER_UID=1000
-ARG USER_GID=$USER_UID
-
-# Create the user
-RUN groupadd --gid $USER_GID $USERNAME \
-    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
-    # [Optional] Add sudo support. Omit if you don't need to install software af
-ter connecting.
-    && apt-get update \
-    && apt-get install -y sudo \
-    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
-    && chmod 0440 /etc/sudoers.d/$USERNAME
-
-# Change RISCV user
-run chown -Rf cad:cad /opt
-
-# Add cad user
-USER $USERNAME
-
-# SET ENVIRONMENT VARIABLES
-ENV RISCV=/opt/riscv
-ENV PATH=$PATH:$RISCV/bin
-
-# TOOLCHAIN
-RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
-    cd riscv-gnu-toolchain && \
-    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r
-v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32
-imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6
-4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
-    make --jobs && \
-    make install
-
-# elf2hex
-ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
-WORKDIR /opt/riscv
-RUN git clone https://github.com/sifive/elf2hex.git && \
-  cd elf2hex && \
-  autoreconf -i && \
-  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
-  make && \
-  make install
-
-# QEMU
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
-  cd qemu && \
-  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
-  make --jobs && \
-  make install
-
-# Spike
-WORKDIR /opt/riscv
-RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
-  mkdir riscv-isa-sim/build && \
-  cd riscv-isa-sim/build && \
-  ../configure --prefix=$RISCV --enable-commitlog && \
-  make --jobs && \
-  make install  && \
-  cd ../arch_test_target/spike/device && \
-  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
-  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
-
-# SAIL
-WORKDIR /opt/riscv
-RUN opam init -y --disable-sandboxing
-RUN opam switch create ocaml-base-compiler.4.06.1
-RUN opam install sail -y
-RUN eval $(opam config env) && \
- cd $RISCV && \
- git clone https://github.com/riscv/sail-riscv.git && \
- cd sail-riscv && \
- make && \
- ARCH=RV32 make && \
- ARCH=RV64 make && \
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && 
-\
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
-
-# Buildroot
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh
-3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git
-ENV export WALLY=/opt/riscv/riscv-wally
-RUN git clone https://github.com/buildroot/buildroot.git && \
-  cd buildroot && \
-  git checkout 2021.05 && \
-  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
-  cp ./board/wally/main.config .config && \
-  make --jobs
-
-# change to cad's hometown
-WORKDIR /home/cad
-
-
-D.3.7	Integrating Commercial CAD Tools into a Local Docker Container
-
-
-
-RISC-V System-on-Chip Design Lecture Notes 
-© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris
-These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.
-
diff --git a/docs/Dockerfile b/docs/Dockerfile
deleted file mode 100755
index 8df933363..000000000
--- a/docs/Dockerfile
+++ /dev/null
@@ -1,133 +0,0 @@
-###########################################
-## Dockerfile
-##
-## Written: james.stine@okstate.edu 28 January 2023
-## Modified: 
-##
-## Purpose: Dockerfile for Wally docker container creation
-## 
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-## 
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org#licenses#SHL-2.1#
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-# Compliance Development Environment Image
-FROM debian
-
-# UPDATE / UPGRADE
-RUN apt update
-
-# INSTALL
-RUN apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam  build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
-
-RUN pip3 install chardet==3.0.4
-RUN pip3 install urllib3==1.22
-RUN pip3 install testresources
-RUN pip3 install riscof --ignore-installed PyYAML
-RUN echo "root:wally" | chpasswd
-
-# ADD RISCV
-WORKDIR /opt/riscv
-
-# Create a user group 'xyzgroup'
-ARG USERNAME=cad
-ARG USER_UID=1000
-ARG USER_GID=$USER_UID
-
-# Create the user
-RUN groupadd --gid $USER_GID $USERNAME \
-    && useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
-    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
-    && apt-get update \
-    && apt-get install -y sudo \
-    && echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
-    && chmod 0440 /etc/sudoers.d/$USERNAME
-
-# Change RISCV user
-run chown -Rf cad:cad /opt
-
-# Add cad user
-USER $USERNAME
-
-# SET ENVIRONMENT VARIABLES
-ENV RISCV=/opt/riscv
-ENV PATH=$PATH:$RISCV/bin
-
-# TOOLCHAIN
-RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
-    cd riscv-gnu-toolchain && \
-    ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
-    make --jobs && \
-    make install
-
-# elf2hex
-ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
-WORKDIR /opt/riscv
-RUN git clone https://github.com/sifive/elf2hex.git && \
-  cd elf2hex && \
-  autoreconf -i && \
-  ./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
-  make && \
-  make install
-
-# QEMU
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
-  cd qemu && \
-  ./configure --target-list=riscv64-softmmu --prefix=$RISCV  && \
-  make --jobs && \
-  make install
-
-# Spike
-WORKDIR /opt/riscv
-RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
-  mkdir riscv-isa-sim/build && \
-  cd riscv-isa-sim/build && \
-  ../configure --prefix=$RISCV --enable-commitlog && \
-  make --jobs && \
-  make install  && \
-  cd ../arch_test_target/spike/device && \
-  sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
-  sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
-
-# SAIL
-WORKDIR /opt/riscv
-RUN opam init -y --disable-sandboxing
-RUN opam switch create ocaml-base-compiler.4.06.1
-RUN opam install sail -y
-RUN eval $(opam config env) && \
- cd $RISCV && \
- git clone https://github.com/riscv/sail-riscv.git && \
- cd sail-riscv && \
- make && \
- ARCH=RV32 make && \
- ARCH=RV64 make && \
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \
- ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
-
-# Buildroot
-WORKDIR /opt/riscv
-RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git
-ENV export WALLY=/opt/riscv/riscv-wally
-RUN git clone https://github.com/buildroot/buildroot.git && \
-  cd buildroot && \
-  git checkout 2021.05 && \
-  cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
-  cp ./board/wally/main.config .config && \
-  make --jobs
-
-# change to cad's hometown
-WORKDIR /home/cad
diff --git a/docs/divsqrt_tex/div2.tex b/docs/divsqrt_tex/div2.tex
deleted file mode 100644
index 03daaf1a8..000000000
--- a/docs/divsqrt_tex/div2.tex
+++ /dev/null
@@ -1,123 +0,0 @@
-\documentclass[12pt]{article}
-
-\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
-
-\usepackage{arydshln}
-
-\parindent  = 0in
-
-\pagestyle{empty}
-
-%==========
-%==========
-
-\begin{document}
-
-\begin{center}
-\begin{tabular}{cccc}
-    Initialization&$D$&$0001.1010\ 000$&\\
-    &$-D=\overline{D}+1$&$1110.0101\ 111$&(+ 1 ulp)\\
-    &&&\\
-    &$WS_{-1}=X$&$0001.0000\ 010$&\\
-    &$WC_{-1}$&$0000.0000\ 000$&\\
-    \hdashline\\
-    Step 0:&$WS_{-1}$&$0001.0000\ 010$&\\
-    &$WC_{-1}$&$0000.0000\ 00\mathbf{1}$&($W_{msbs}=0001\ \text{so}\ q_0=1$)\\
-    &$-q_0D$&$1110.0101\ 111$&\\
-    \cline{2-3}
-    &$sum$&$1111.0101\ 100$&$\ll1$\\
-    &$carry$&$0000.0000\ 110$&$\ll1$\\
-    \hdashline\\
-    Step 1:&$WS_0$&$1110.1011\ 000$&\\
-    &$WC_0$&$0000.0001\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_1=-1$)\\
-    &$-q_1D$&$0001.1010\ 000$&\\
-    \cline{2-3}
-    &$sum$&$1111.0000\ 100$&$\ll1$\\
-    &$carry$&$0001.0110\ 000$&$\ll1$\\
-    \hdashline\\
-    Step 2:&$WS_1$&$1110.0001\ 000$&\\
-    &$WC_1$&$0010.1100\ 00\mathbf{1}$&($W_{msbs}=0000\ \text{so}\ q_2=1$)\\
-    &$-q_2D$&$1110.0101\ 111$&\\
-    \cline{2-3}
-    &$sum$&$0010.1000\ 110$&$\ll1$\\
-    &$carry$&$1100.1010\ 010$&$\ll1$\\
-    \hdashline\\
-    Step 3:&$WS_2$&$0101.0001\ 100$&\\
-    &$WC_2$&$1001.0100\ 10\mathbf{0}$&($W_{msbs}=1110\ \text{so}\ q_3=-1$)\\
-    &$-q_3D$&$0001.1010\ 000$&\\
-    \cline{2-3}
-    &$sum$&$1101.1111\ 000$&\\
-    &$carry$&$0010.0001\ 000$&$sum+carry=0$, terminate.\\
-    \hdashline\\
-    Terminate&Quotient&0.101
-\end{tabular}
-\end{center}
-
-\vfill
-\eject
-
-X = 1.0110\ 011 (179/128)
-
-D = 1.0011\ 000 (152/128)
-
-Q = 1.0010\ 1101\ 0
-
-D[1.3] = 1.001, so we use the ``"1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
-\begin{center}
-\begin{tabular}{cccc}
-    Initialization&$D$&$0001.0011\ 000$&\\
-    &$2D$&$0010.0110\ 000$&\\
-    &$-D=\overline{D}+1$&$1110.1100\ 111$&(+ 1 ulp)\\
-    &$-2D=\overline{2D}+1$&$1101.1001\ 111$&(+ 1 ulp)\\
-    &&&\\
-    &$X=WS$&$0001.0110\ 011$&\\
-    &$WC$&$0000.0000\ 000$&\\
-    \hdashline\\
-    Step 4:&$WS$&$0001.0110\ 011$&\\
-    &$WC$&$0000.0000\ 00\mathbf{1}$&($RW_{msbs}=0001.010\ \text{so}\ q_4=1$)\\
-    &$-q_7D$&$1110.1100\ 111$&\\
-    \cline{2-3}
-    &$WS$&$1111.1010\ 101$&$\ll2$\\
-    &$WC$&$0000.1000\ 110$&$\ll2$\\
-    \hdashline\\
-    Step 3:&$WS$&$1110.1010\ 100$&\\
-    &$WC$&$0010.0011\ 000$&($RW_{msbs}=0000.110\ \text{so}\ q_3=1$)\\
-    &$-q_6D$&$0000.0000\ 000$&\\
-    \cline{2-3}
-    &$WS$&$1100.1001\ 100$&$\ll2$\\
-    &$WC$&$0100.0100\ 000$&$\ll2$\\
-    \hdashline\\
-    Step 2:&$WS$&$0010.0110\ 000$&\\
-    &$WC$&$0001.0000\ 00\mathbf{1}$&($RW_{msbs}=0011.010\ \text{so}\ q_2=-1$)\\
-    &$-q_5D$&$1110.0101\ 111$&\\
-    \cline{2-3}
-\end{tabular}
-\end{center}
-
-page 269 306
-
-\vfill 
-\eject
-
-\large{\bf{
-Math for the recurrence relation}}
-
-**going to have to change notation for sure, change the subscripts for steps and might have to get rid of some exponents**
-\begin{align*}
-    w[j+1] &= r^{j+1}\big(x-S[j+1]^2\big)\\
-    &= r^{j+1}\big(x-(S[j]+s_{j+1}r^{-(j+1)})^2\big)\\
-    &= r^{j+1}x-r^{j+1}\big(S[j]^2+2S[j]s_{j+1}r^{-(j+1)}+s^2_{j+1}r^{-2(j+1)}\big)\\
-    &= r^{j+1}\big(x-S[j]^2\big)-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
-    &= rw[j]-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)\\
-    &= rw[j]+F[j]
-\end{align*}
-where
-\begin{align*}
-    F[j]=-\big(2S[j]s_{j+1}+s_{j+1}^2r^{-(j+1)}\big)
-\end{align*}
-
-Since there is a term of $S$ in the expression of $F$, we must come up with a way to represent $S$ using only zeros and ones, rather than using the bit set $\{-a,\ldots,a\}$. This is done using on-the-fly conversion just as we did to compute the quotient for the divider. We keep a running copy of $S$, but we also keep the value $SM=S-1$. The logic is still the same for computing $S$ and $SM$ on the next step; see figure 13.15. 
-
-Now that $S$ is in a form such that we can use it in a CSA, we need to compute $F$. To do so, 
-
-\end{document}
diff --git a/docs/divsqrt_tex/div4.tex b/docs/divsqrt_tex/div4.tex
deleted file mode 100644
index a5b95dda1..000000000
--- a/docs/divsqrt_tex/div4.tex
+++ /dev/null
@@ -1,84 +0,0 @@
-\documentclass[12pt]{article}
-
-\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
-
-\usepackage{arydshln}
-
-\parskip = .2in
-\parindent  = 0in
-
-\pagestyle{empty}
-
-%==========
-%==========
-
-\begin{document}
-
-
-X = 1.0000\ 1101 (269/256)
-
-D = 1.0011\ 0110 (310/256)
-
-Q = 0.1101\ 1110 (222/256)
-
-D[1.3] = 1.001, so we use the ``1.001" column of chart 13.X. This means we select a quotient bit of 2 if the partial remainder is greater than or equal to 3.5, a quotient bit of 1 if the partial is greater or equal to than 1.0, a zero if the partial is greater than or equal to -1.5, -1 if the partial is greater than or equal to -3.75, and a -2 otherwise.
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Initialization&$D$&$0001.0011\ 0110\ 00$&\\
-    &$2D$&$0010.0110\ 1100\ 00$&\\
-    &$-D=\overline{D}+1$&$1110.1100\ 1001\ 11$&(+ 1 ulp)\\
-    &$-2D=\overline{2D}+1$&$1101.1001\ 0011\ 11$&(+ 1 ulp)\\
-    &&&\\
-    &$WS_{-1}=X$&$0001.0000\ 1101\ 00$&\\
-    &$WC_{-1}$&$0000.0000\ 0000\ 00$&\\
-    \hdashline\\
-    Step 0: &$WS_{-1}   $&$0001.0000\ 1101\ 00$&\\
-            &$WC_{-1}   $&$0000.0000\ 0000\ 0\mathbf{1}$&($W_{msbs}=0001.000\ \text{so}\ q_0=1$)\\
-            &$-q_0D     $&$1110.1100\ 1001\ 11$&\\
-    \cline{2-3}
-            &$sum       $&$1111.1100\ 0100\ 10$&$\ll2$\\
-            &$carry     $&$0000.0001\ 0010\ 10$&$\ll2$\\
-    \hdashline\\
-    Step 1: &$WS_0      $&$1111.0001\ 0010\ 00$&\\
-            &$WC_0      $&$0000.0100\ 1010\ 0\mathbf{0}$&($W_{msbs}=1111.010\ \text{so}\ q_1=-1$)\\
-            &$-q_1D     $&$0001.0011\ 0110\ 00$&\\
-    \cline{2-3}
-            &$sum       $&$1110.0110\ 1110\ 00$&$\ll2$\\
-            &$carry     $&$0010.0010\ 0100\ 00$&$\ll2$\\
-    \hdashline\\
-    Step 2: &$WS_1      $&$1001.1011\ 1000\ 00$&\\
-            &$WC_1      $&$1000.1001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.010\ \text{so}\ q_2=2$)\\
-            &$-q_2D     $&$1101.1001\ 0011\ 11$\\
-    \cline{2-3}
-            &$sum       $&$1100.1011\ 1011\ 10$&$\ll2$\\
-            &$carry     $&$0011.0010\ 0000\ 10$&$\ll2$\\
-    \hdashline\\
-    Step 3: &$WS_2      $&$0010.1110\ 1110\ 00$&\\
-            &$WC_2      $&$1100.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=1111.011\ \text{so}\ q_3=-1$)\\
-            &$-q_3D     $&$0001.0011\ 0110\ 00$\\
-    \cline{2-3}
-            &$sum       $&$1111.0101\ 1010\ 00$&$\ll2$\\
-            &$carry     $&$0001.0100\ 0100\ 00$&$\ll2$\\
-    \hdashline\\
-    Step 4: &$WS_3      $&$1101.0110\ 1000\ 00$&\\
-            &$WC_3      $&$0101.0001\ 0000\ 0\mathbf{1}$&($W_{msbs}=0010.011\ \text{so}\ q_4=2$)\\
-            &$-q_4D     $&$1101.1001\ 0011\ 11$\\
-    \cline{2-3}
-            &$sum       $&$0101.1110\ 1011\ 10$&$\ll2$\\
-            &$carry     $&$1010.0010\ 0000\ 10$&$\ll2$\\
-    \hdashline\\
-    Step 5: &$WS_4      $&$0111.1010\ 1110\ 00$&\\
-            &$WC_4      $&$1000.1000\ 0010\ 0\mathbf{0}$&($W_{msbs}=0000.001\ \text{so}\ q_5=0$)\\
-            &$-q_5D     $&$0000.0000\ 0000\ 00$\\
-    \cline{2-3}
-            &$sum       $&$1111.0010\ 1100\ 00$&$\ll2$\\
-            &$carry     $&$0001.0000\ 0100\ 00$&$\ll2$\\
-    \hdashline\\
-    Terminate&Quotient&$00.11\ 01\ 11\ 10\ (00\ 1)$
-\end{tabular}
-\end{center}
-}
-
-\end{document}
diff --git a/docs/divsqrt_tex/sqrt2.tex b/docs/divsqrt_tex/sqrt2.tex
deleted file mode 100644
index 3c40b037c..000000000
--- a/docs/divsqrt_tex/sqrt2.tex
+++ /dev/null
@@ -1,385 +0,0 @@
-\documentclass[12pt]{article}
-\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
-\usepackage{arydshln}
-
-\parskip = .2in
-\parindent  = 0in
-
-\pagestyle{empty}
-
-%==========
-%==========
-
-\begin{document}
-
-X = 0.0111 0011 1001 (1849/4096)
-
-S = 0.1010 1100 0000 (2752/4096)
-{\small
-\begin{center}
-\begin{tabular}{ccccc}
-            &$X             $&$         0000.0111\ 0011\ 1001   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
-            &$WS_0=2(X-1)   $&$         1110.1110\ 0111\ 0010   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
-            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 1: &$WS_0          $&$         1110.1110\ 0111\ 0010   $&          &\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_1=-1$)\\
-            &$F_1=2S_0-K_1 $&${\color{blue}0001.1}000\ 0000\ 0000$&          &$S_1={\color{blue}0000.1}000\ 0000\ 0000$\\
-            &                &                                   &          &$SM_1={\color{blue}0000.0}000\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0110\ 0111\ 0010   $&$\ll1    $&$K_1=0000.1000\ 0000\ 0000\ $\\
-            &$carry         $&$         0001.0000\ 0000\ 0000   $&$\ll1    $&$C_1=1111.1000\ 0000\ 0000\,$\\
-    \hdashline\\    
-    Step 2: &$WS_1          $&$         1110.1100\ 1110\ 0100   $&          &\\
-            &$WC_1          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=0000\ \text{so}\ s_2=1$)\\
-            &$F_2=-2S_1-K_2$&${\color{blue}1110.11}00\ 0000\ 0000$&          &$S_2={\color{blue}0000.11}00\ 0000\ 0000$\\
-            &                &                                   &          &$SM_2={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0010.0000\ 1110\ 0100   $&$\ll1    $&$K_2=0000.0100\ 0000\ 0000\ $\\
-            &$carry         $&$         1101.1000\ 0000\ 0000   $&$\ll1    $&$C_2=1111.1100\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 3: &$WS_2          $&$         0100.0001\ 1100\ 1000   $&          &\\
-            &$WC_2          $&$         1011.0000\ 0000\ 0000   $&          &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
-            &$F_3=0       $&${\color{blue}0000.000}0\ 0000\ 0000$&          &$S_3={\color{blue}0000.110}0\ 0000\ 0000$\\
-            &                &                                   &          &$SM_3={\color{blue}0000.101}0\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0001\ 1100\ 1000   $&$\ll1    $&$K_3=0000.0010\ 0000\ 0000\ $\\
-            &$carry         $&$         0000.0000\ 0000\ 0000   $&$\ll1    $&$C_3=1111.1110\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 4: &$WS_3          $&$         1110.0011\ 1001\ 0000   $&          &\\
-            &$WC_3          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
-            &$F_4=2S_3-K_4 $&${\color{blue}0001.0111}\ 0000\ 0000$&          &$S_4={\color{blue}0000.1011}\ 0000\ 0000$\\
-            &                &                                   &          &$SM_4={\color{blue}0000.1010}\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0100\ 1001\ 0000   $&$\ll1    $&$K_4=0000.0001\ 0000\ 0000\ $\\
-            &$carry         $&$         0000.0110\ 0000\ 0000   $&$\ll1    $&$C_4=1111.1111\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 5: &$WS_4          $&$         1110.1001\ 0010\ 0000   $&          &\\
-            &$WC_4          $&$         0000.1100\ 0000\ 0000   $&          &($W_{msbs}=1110\ \text{so}\ s_5=-1$)\\
-            &$F_5=2S_4-K_5 $&${\color{blue}0001.0101\ 1}000\ 0000$&          &$S_5={\color{blue}0000.1010\ 1}000\ 0000$\\
-            &                &                                   &          &$SM_5={\color{blue}0000.1010\ 0}000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0000\ 1010\ 0000   $&$\ll1    $&$K_5=0000.0000\ 1000\ 0000\ $\\
-            &$carry         $&$         0001.1010\ 0000\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1000\ 0000\,$\\
-    \hdashline\\
-    Step 6: &$WS_5          $&$         1110.0001\ 0100\ 0000   $&          &\\
-            &$WC_5          $&$         0011.0100\ 0000\ 0000   $&          &($W_{msbs}=0001\ \text{so}\ s_6=1$)\\
-            &$F_6=-2S_5-K_6$&${\color{blue}1110.1010\ 11}00\ 0000$&          &$S_6={\color{blue}0000.1010\ 11}00\ 0000$\\
-            &                &                                   &          &$SM_6={\color{blue}0000.1010\ 10}00\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0011.1111\ 1000\ 0000   $&$\ll1    $&$K_6=0000.0000\ 0100\ 0000\ $\\
-            &$carry         $&$         1100.0000\ 1000\ 0000   $&$\ll1    $&$C_6=1111.1111\ 1100\ 0000\,$\\
-            &                &                                   &          &$sum+carry=0$, terminate\\
-    \hdashline\\
-    Terminate&Square Root&0.101011
-\end{tabular}
-\end{center}
-}
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    \hdashline\\
-    Step 6: &$WS    $&$0111.1111\ 0000\ 00$&\\
-            &$WC    $&$1000.0001\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_6=0$)\\
-            &$F     $&$0000.0000\ 0000\ 00$&$S_6=\mathbf{1.0101\ 10}00\ 00$\\
-            &        &                     &$SM_6=\mathbf{1.0101\ 01}00\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1111.1110\ 0000\ 00$&$\ll1$\\
-            &$WC    $&$0000.0010\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 7: &$WS    $&$1111.1100\ 0000\ 00$&\\
-            &$WC    $&$0000.0100\ 0000\ 00$&($W_{msbs}=1111\ \text{so}\ s_7=0$)\\
-            &$F     $&$0000.0000\ 0000\ 00$&$S_7=\mathbf{1.0101\ 100}0\ 00$\\
-            &        &                     &$SM_7=\mathbf{1.0101\ 011}0\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1111.1000\ 0000\ 00$&$\ll1$\\
-            &$WC    $&$0000.1000\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 8: &$WS    $&$1111.0000\ 0000\ 00$&\\
-            &$WC    $&$0001.0000\ 0000\ 00$&($W_{msbs}=0000\ \text{so}\ s_8=1$)\\
-            &$F     $&$1110.1010\ 0111\ 10$&$S_8=\mathbf{1.0101\ 1001}\ 00$\\
-            &        &                     &$SM_8=\mathbf{1.0101\ 1000}\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$0000.1010\ 0111\ 10$&$\ll1$\\
-            &$WC    $&$1110.0000\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 9: &$WS    $&$0001.0100\ 1111\ 00$&\\
-            &$WC    $&$1100.0000\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_9=-1$)\\
-            &$F     $&$0001.0101\ 1000\ 11$&$S_9=\mathbf{1.0101\ 1000\ 1}0$\\
-            &        &                     &$SM_9=\mathbf{1.0101\ 1000\ 0}0\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1100.0001\ 0111\ 11$&$\ll1$\\
-            &$WC    $&$0010.1001\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 10:&$WS    $&$1000.0010\ 1111\ 10$&\\
-            &$WC    $&$0101.0010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{10}=-1$)\\
-            &$F     $&$0001.0101\ 1000\ 01$&$S_{10}=\mathbf{1.0101\ 1000\ 01}$\\
-            &        &                     &$SM_{10}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1100.0001\ 0111\ 11$&$\ll1$\\
-            &$WC    $&$0010.0101\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 11:&$WS    $&$1000.0010\ 1111\ 10$&\\
-            &$WC    $&$0100.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{11}=-1$)\\
-            &$F     $&$0001.0101\ 1000\ 00$&$S_{11}=\mathbf{1.0101\ 1000\ 00}$\\
-            &        &                     &$SM_{11}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1101.1101\ 0111\ 10$&$\ll1$\\
-            &$WC    $&$0000.0101\ 0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 12:&$WS    $&$1101.1000\ 0111\ 10$&\\
-            &$WC    $&$0000.1010\ 0000\ 00$&($W_{msbs}=1101\ \text{so}\ s_{12}=-1$)\\
-            &$F     $&$0001.0101\ 1000\ 00$&$S_{12}=\mathbf{1.0101\ 1000\ 00}$\\
-            &        &                     &$SM_{12}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1100.0111\ 1111\ 10$&$\ll1$\\
-            &$WC    $&$0011.0000\ 0000\ 00$&$\ll1$\\
-\end{tabular}
-\end{center}
-}
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Step 13:&$WS    $&$1000.1111\ 1111\ 00$&\\
-            &$WC    $&$0110.0000\ 0000\ 00$&($W_{msbs}=1110\ \text{so}\ s_{13}=-1$)\\
-            &$F     $&$0001.0101\ 1000\ 00$&$S_{13}=\mathbf{1.0101\ 1000\ 00}$\\
-            &        &                     &$SM_{13}=\mathbf{1.0101\ 1000\ 00}\phantom{M}$\\
-    \cline{2-3}
-            &$WS    $&$1111.1010\ 0111\ 10$&$\ll1$\\
-            &$WC    $&$0000.1011\ 0000\ 00$&$\ll1$\\
-\end{tabular}
-\end{center}
-}
-
-\vfill
-\eject
-
-{\small
-\begin{center}
-\begin{tabular}{ccccc}
-            &$X             $&$         0000.1100\ 0000     $&          &$S_0={\color{blue}0001}.0000\ 0000\ 00$\\
-            &$WS=X-1        $&$         1111.1100\ 0000     $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 00\phantom{M}$\\
-            &$WC            $&$         0000.0000\ 0000     $&          &$K_0=0000.0100\ 0000\ 00\ $\\
-            &                &                               &          &$C_0=1111.1100\ 0000\ 00\,$\\
-    \hdashline\\
-    Step 1: &$WS            $&$         1111.1100\ 0000     $&          &\\
-            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
-            &$F_1=0         $&${\color{blue}0000.00}00\ 0000$&          &$S_1={\color{blue}0001.0}000\ 0000\ 00$\\
-            &                &                               &          &$SM_1={\color{blue}0000.1}000\ 0000\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS            $&$         1111.1100\ 0000     $&$\ll1    $&$K_1=0000.0010\ 0000\ 00\ $\\
-            &$WC            $&$         0000.0000\ 0000     $&$\ll1    $&$C_1=1111.1110\ 0000\ 00\,$\\
-    \hdashline\\    
-    Step 2: &$WS            $&$         1111.1000\ 0000     $&          &\\
-            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_2=0$)\\
-            &$F_2=0         $&${\color{blue}0000.000}0\ 0000$&          &$S_2={\color{blue}0001.00}00\ 0000\ 00$\\
-            &                &                               &          &$SM_2={\color{blue}0000.11}00\ 0000\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS            $&$         1111.1000\ 0000     $&$\ll1    $&$K_2=0000.0001\ 0000\ 00\ $\\
-            &$WC            $&$         0000.0000\ 0000     $&$\ll1    $&$C_2=1111.1111\ 0000\ 00\,$\\
-    \hdashline\\
-    Step 3: &$WS            $&$         1111.0000\ 0000     $&          &\\
-            &$WC            $&$         0000.0000\ 0000     $&          &($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
-            &$F_3=0         $&${\color{blue}0000.0000}\ 0000$&          &$S_3={\color{blue}0001.000}0\ 0000\ 00$\\
-            &                &                               &          &$SM_3={\color{blue}0000.111}0\ 0000\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS            $&$1111.0000\ 0000              $&$\ll1    $&$K_3=0000.0000\ 1000\ 00\ $\\
-            &$WC            $&$0000.0000\ 0000              $&$\ll1    $&$C_3=1111.1111\ 1000\ 00\,$\\
-    \hdashline\\
-    Step 4: &$WS            $&$1110.0000\ 0000              $&          &\\
-            &$WC            $&$0000.0000\ 0000              $&          &($W_{msbs}=1110\ \text{so}\ s_4=-1$)\\
-            &$F_4=S_3-K_3   $&${\color{blue}0000.1111\ 1}000$&          &$S_4={\color{blue}0000.1111}\ 0000\ 00$\\
-            &                &                               &          &$SM_4={\color{blue}0000.1110}\ 0000\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS            $&$1110.1111\ 1000              $&$\ll1    $&$K_4=0000.0000\ 0100\ 00\ $\\
-            &$WC            $&$0000.0000\ 0000              $&$\ll1    $&$C_4=1111.1111\ 1100\ 00\,$\\
-    \hdashline\\
-    Step 5: &$WS            $&$1101.1111\ 0000              $&          &\\
-            &$WC            $&$0000.0000\ 0000              $&          &($W_{msbs}=1101\ \text{so}\ s_5=-1$)\\
-            &$F_5=S_4-K_4   $&${\color{blue}0000.1110\ 11}00$&          &$S_5={\color{blue}0000.1110\ 1}000\ 00$\\
-            &                &                                   &          &$SM_5={\color{blue}0001.1110\ 0}000\ 00\phantom{M}$\\
-    \cline{2-3}
-            &$WS            $&$1101.0001\ 1100              $&$\ll1    $&$K_5=0000.0000\ 0010\ 00\ $\\
-            &$WC            $&$0001.1100\ 0000              $&$\ll1    $&$C_5=1111.1111\ 1110\ 00\,$\\
-    Terminate
-\end{tabular}
-\end{center}
-}
-
-\vfill
-\eject
-
-X = 0.1010101101(685/1024)
-
-S = 0.1101000110(838/1024)
-
-once R4 sslc gets here i can fill this in
-
-\vfill 
-\eject
-
-X = 1.1001 (25/16)
-
-S = 1.0100 (20/16)
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Attempt 1:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q4.0\\
-    &&&\\
-            &$X     $&$0001.1001$&\\
-            &$WS=X-1$&$0000.1001$& $s_0=1$\\
-            &$WC    $&$0000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
-    \hdashline\\
-    Step 1: &$WS    $&$0000.1001$&\\
-            &$WC    $&$0000.0000$&($W_{msbs}=0000\ \text{so}\ s_1=1$)\\
-            &$F     $&$1110.1100$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
-    \cline{2-3}
-            &$WS    $&$1110.0101$&$\ll1$\\
-            &$WC    $&$0001.0000$&$\ll1$\\
-    \hdashline\\
-    Step 2: &$WS    $&$1100.1010$&\\
-            &$WC    $&$0010.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
-            &$F     $&$0001.0110$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
-    \cline{2-3}
-            &$WS    $&$1111.1110$&$\ll1$\\
-            &$WC    $&$0000.0010$&$\ll1$\\
-    \hdashline\\
-    Step 3: &$WS    $&$1111.1100$&\\
-            &$WC    $&$0000.0100$&($W_{msbs}=1111\ \text{so}\ s_3=0$)\\
-            &$-q_3D $&$0000.0000$&$S_3=\mathbf{1.010}0,\quad SM_3=\mathbf{1.001}0$\\
-    \cline{2-3}
-            &$WS    $&$1111.1000$&$\ll1$\\
-            &$WC    $&$0000.1000$&$\ll1$\\
-    \hdashline\\
-    Step 4: &$WS    $&$1111.0000$&\\
-            &$WC    $&$0001.0000$&($W_{msbs}=0000\ \text{so}\ s_4=1$)\\
-            &$F     $&$0000.0000$&$S_4=\mathbf{1.0101},\quad SM_4=\mathbf{1.0100}$\\
-    Terminate&&&
-\end{tabular}
-\end{center}
-}
-
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Attempt 2:& $X$ is normalized& to $1/2<X<2$&$W_{msbs}$ looks at Q3.1\\
-    &&&\\
-            &$X     $&$001.1001$&\\
-            &$WS=X-1$&$000.1001$& $s_0=1$\\
-            &$WC    $&$000.0000$&$S_0=\mathbf{1}.0000,\quad SM_0=\mathbf{0}.0000$ \\
-    \hdashline\\
-    Step 1: &$WS    $&$000.1001$&\\
-            &$WC    $&$000.0000$&($W_{msbs}=000.1\ \text{so}\ s_1=1$)\\
-            &$F     $&$110.1000$&$S_1=\mathbf{1.1}000,\quad SM_1=\mathbf{1.0}000$\\
-    \cline{2-3}
-            &$WS    $&$110.0001$&$\ll1$\\
-            &$WC    $&$001.0000$&$\ll1$\\
-    \hdashline\\
-    Step 2: &$WS    $&$100.0010$&\\
-            &$WC    $&$010.0000$&($W_{msbs}=110.0\ \text{so}\ s_2=-1$)\\
-            &$F     $&$001.0100$&$S_2=\mathbf{1.01}00,\quad SM_2=\mathbf{1.00}00$\\
-    \cline{2-3}
-            &$WS    $&$111.0110$&$\ll1$\\
-            &$WC    $&$000.0000$&$\ll1$\\
-    \hdashline\\
-    Step 3: &$WS    $&$110.1100$&\\
-            &$WC    $&$000.0000$&($W_{msbs}=110.1\ \text{so}\ s_3=-1$)\\
-            &$-q_3D $&$001.0010$&$S_3=\mathbf{1.001}0,\quad SM_3=\mathbf{1.000}0$\\
-    \cline{2-3}
-            &$WS    $&$111.1110$&$\ll1$\\
-            &$WC    $&$000.0000$&$\ll1$\\
-    \hdashline\\
-    Step 4: &$WS    $&$111.1110$&\\
-            &$WC    $&$000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
-            &$F     $&$000.0000$&$S_4=\mathbf{1.0010},\quad SM_4=\mathbf{1.0001}$\\
-    Terminate&&&
-\end{tabular}
-\end{center}
-}
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Attempt 3:& $X$ is normalized& to $1<X<4$&$W_{msbs}$ looks at Q4.0\\
-    &&&\\
-            &$X     $&$0001.1001$&\\
-            &$WS=X-2$&$1111.1001$& $s_{-1}=10$\\
-            &$WC    $&$0000.0000$&$S_{-1}=\mathbf{1}0.0000,\quad SM_{-1}=\mathbf{0}0.0000$ \\
-    \hdashline\\
-    Step 0: &$WS    $&$1111.1001$&\\
-            &$WC    $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_0=0$)\\
-            &$F     $&$0000.0000$&$S_0=\mathbf{10}.0000,\quad SM_0=\mathbf{01}.0000$\\
-    \cline{2-3}
-            &$WS    $&$1111.1001$&$\ll1$\\
-            &$WC    $&$0000.0000$&$\ll1$\\
-    \hdashline\\
-    Step 1: &$WS    $&$1111.0010$&\\
-            &$WC    $&$0000.0000$&($W_{msbs}=1111\ \text{so}\ s_1=0$)\\
-            &$F     $&$0000.0000$&$S_1=\mathbf{10.0}000,\quad SM_1=\mathbf{01.1}000$\\
-    \cline{2-3}
-            &$WS    $&$1111.0010$&$\ll1$\\
-            &$WC    $&$0000.0000$&$\ll1$\\
-    \hdashline\\
-    Step 2: &$WS    $&$1110.0100$&\\
-            &$WC    $&$0000.0000$&($W_{msbs}=1110\ \text{so}\ s_2=-1$)\\
-            &$-q_3D $&$0001.1100$&$S_2=\mathbf{01.01}00,\quad SM_2=\mathbf{01.00}00$\\
-    \cline{2-3}
-            &$WS    $&$1111.1000$&$\ll1$\\
-            &$WC    $&$0000.1000$&$\ll1$\\
-    Terminate&&&
-\end{tabular}
-\end{center}
-}
-
-\vfill
-\eject
-
-X = 0.011001 (25/64)
-
-S = 0.101000 (40/64)
-
-{\small
-\begin{center}
-\begin{tabular}{cccc}
-    Attempt 4:& $X$ is normalized& to $1/4<X<1$&$W_{msbs}$ looks at Q3.1\\
-    &&&\\
-            &$X     $&$000.0110\ 01$&\\
-            &$WS=X-1$&$111.0110\ 01$& $s_0=1$\\
-            &$WC    $&$000.0000\ 00$&$S_0=\mathbf{1}.000000,\quad SM_0=\mathbf{0}.000000$ \\
-    \hdashline\\
-    Step 1: &$WS    $&$111.0110\ 01$&\\
-            &$WC    $&$000.0000\ 00$&($W_{msbs}=111.0\ \text{so}\ s_1=-1$)\\
-            &$F     $&$000.1000\ 00$&$S_1=\mathbf{0.1}00000,\quad SM_1=\mathbf{0.0}00000$\\
-    \cline{2-3}
-            &$WS    $&$111.1110\ 01$&$\ll1$\\
-            &$WC    $&$000.0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 2: &$WS    $&$111.1100\ 10$&\\
-            &$WC    $&$000.0000\ 00$&($W_{msbs}=111.1\ \text{so}\ s_2=0$)\\
-            &$F     $&$000.0000\ 00$&$S_2=\mathbf{0.10}0000,\quad SM_2=\mathbf{0.01}0000$\\
-    \cline{2-3}
-            &$WS    $&$111.1100\ 10$&$\ll1$\\
-            &$WC    $&$000.0000\ 00$&$\ll1$\\
-    \hdashline\\
-    Step 3: &$WS    $&$111.1001\ 00$&\\
-            &$WC    $&$000.0000\ 00$&($W_{msbs}=010.0\ \text{so}\ s_3=1$)\\
-            &$-q_3D $&$111.0010\ 00$&$S_3=\mathbf{0.111}000,\quad SM_3=\mathbf{0.110}000$\\
-    \cline{2-3}
-            &$WS    $&$1111.1110$&$\ll1$\\
-            &$WC    $&$0000.0000$&$\ll1$\\
-    \hdashline\\
-    Step 4: &$WS    $&$1111.1110$&\\
-            &$WC    $&$0000.0000$&($W_{msbs}=111.1\ \text{so}\ s_4=0$)\\
-            &$F     $&$0000.0000$&$S_4=\mathbf{1.0010}00,\quad SM_4=\mathbf{1.0001}00$\\
-    Terminate&&&
-\end{tabular}
-\end{center}
-}
-
-
-\end{document}
diff --git a/docs/divsqrt_tex/sqrt4.tex b/docs/divsqrt_tex/sqrt4.tex
deleted file mode 100644
index 1d40864eb..000000000
--- a/docs/divsqrt_tex/sqrt4.tex
+++ /dev/null
@@ -1,147 +0,0 @@
-\documentclass[12pt]{article}
-
-\usepackage{amssymb, amsmath, amsfonts, amsthm, graphicx, tcolorbox}
-
-\usepackage{arydshln}
-
-\parskip = .2in
-\parindent  = 0in
-
-\pagestyle{empty}
-
-%==========
-%==========
-
-\begin{document}
-
-
-
-X = 0.1011 0111 10 (734/1024)
-
-S = 0.1101 1000 11\ 00 (3468/4096), negative sticky bit
-{\small
-\begin{center}
-\begin{tabular}{ccccc}
-            &$X             $&$         0000.1011\ 0111\ 1000   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
-            &$WS_0=4(X-1)   $&$         1110.1101\ 1110\ 0000   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
-            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 1: &$WS_0          $&$         1110.1101\ 1110\ 0000   $&          &\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.110\ \text{so}\ s_1=-1$)\\
-            &$F_1=2S_0-K_1$&${\color{blue}0001.11}00\ 0000\ 0000$&          &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
-            &                &                                   &          &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0001\ 1110\ 0000   $&$\ll2    $&$K_1=0000.0100\ 0000\ 0000\ $\\
-            &$carry         $&$         0001.1000\ 0000\ 0000   $&$\ll2    $&$C_1=1111.1100\ 0000\ 0000\,$\\
-    \hdashline\\    
-    Step 2: &$WS_1          $&$         1100.0111\ 1000\ 0000   $&          &\\
-            &$WC_1          $&$         0110.0000\ 0000\ 0000   $&          &($W_{msbs}=0010.011\ \text{so}\ s_2=2$)\\
-            &$F_2=-4S_1-4K_2$&${\color{blue}1100.1100}\ 0000\ 0000$&        &$S_2={\color{blue}0000.1110}\ 0000\ 0000$\\
-            &                &                                   &          &$SM_2={\color{blue}0000.1101}\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0110.1011\ 1000\ 0000   $&$\ll2    $&$K_2=0000.0001\ 0000\ 0000\ $\\
-            &$carry         $&$         1000.1000\ 0000\ 0000   $&$\ll2    $&$C_2=1111.1111\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 3: &$WS_2          $&$         1010.1110\ 0000\ 0000   $&          &\\
-            &$WC_2          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1100.111\ \text{so}\ s_3=-2$)\\
-            &$F_3=4S_2-4K_3$&${\color{blue}0011.0111\ 00}00\ 0000$&         &$S_3={\color{blue}0000.1101\ 10}00\ 0000$\\
-            &                &                                   &          &$SM_3={\color{blue}0000.1101\ 01}00\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1011.1001\ 0000\ 0000   $&$\ll2    $&$K_3=0000.0000\ 0100\ 0000\ $\\
-            &$carry         $&$         0100.1100\ 0000\ 0000   $&$\ll2    $&$C_3=1111.1111\ 1100\ 0000\,$\\
-    \hdashline\\
-    Step 4: &$WS_3          $&$         1110.0100\ 0000\ 0000   $&          &\\
-            &$WC_3          $&$         0011.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_4=1$)\\
-            &$F_4=-2S_3-K_4$&${\color{blue}1110.0100\ 1111}\ 0000$&        &$S_4={\color{blue}0000.1101\ 1001}\ 0000$\\
-            &                &                                   &          &$SM_4={\color{blue}0000.1101\ 1000}\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0011.0000\ 1111\ 0000   $&$\ll2    $&$K_4=0000.0000\ 0001\ 0000\ $\\
-            &$carry         $&$         1100.1000\ 0000\ 0000   $&$\ll2    $&$C_4=1111.1111\ 1111\ 0000\,$\\
-    \hdashline\\
-    Step 5: &$WS_4          $&$         1100.0011\ 1100\ 0000   $&          &\\
-            &$WC_4          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.001\ \text{so}\ s_5=-1$)\\
-            &$F_5=2S_4-K_5 $&${\color{blue}0001.1011\ 0001\ 11}00$&        &$S_5={\color{blue}0000.1101\ 1000\ 11}00$\\
-            &                &                                   &          &$SM_5={\color{blue}0000.1101\ 1000\ 10}00\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.1000\ 1101\ 1100   $&$\ll2    $&$K_5=0000.0000\ 0000\ 0100\ $\\
-            &$carry         $&$         0000.0110\ 0000\ 0000   $&$\ll2    $&$C_5=1111.1111\ 1111\ 1100\,$\\
-    \hdashline\\
-    Step 6: &$WS_5          $&$         1110.0011\ 0111\ 0000   $&          &\\
-            &$WC_5          $&$         0001.1000\ 0000\ 0000   $&          &($W_{msbs}=1111.101\ \text{so}\ s_6=0$)\\
-            &$F_6=0        $&${\color{blue}0000.0000\ 0000\ 0000}$&         &$S_6={\color{blue}0000.1101\ 1000\ 1100}$\\
-            &                &                                   &          &$SM_6={\color{blue}0000.1101\ 1000\ 1011}\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.1011\ 0111\ 0111   $&$\ll2    $&$K_6=0000.0000\ 0000\ 0001\ $\\
-            &$carry         $&$         0000.0000\ 0000\ 0000   $&$\ll2    $&$C_6=1111.1111\ 1111\ 1111\,$\\
-    \hdashline\\
-    Terminate&Square Root&0000.11 01\ 10 00\ 10 (11)
-\end{tabular}
-\end{center}
-}
-
-X = 0.1001\ 0101\ 00 (596/1024)
-
-S = 0.1100 0011 01\ 01 (3125/4096)
-{\small
-\begin{center}
-\begin{tabular}{ccccc}
-            &$X             $&$         0000.1001\ 0101\ 0000   $&          &$S_0={\color{blue}0001}.0000\ 0000\ 0000$\\
-            &$WS_0=4(X-1)   $&$         1110.0101\ 0100\ 0000   $&          &$SM_0={\color{blue}0000}.0000\ 0000\ 0000\phantom{M}$\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &$K_0=0001.0000\ 0000\ 0000\ $\\
-            &                &                                   &          &$C_0=1111.0000\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 1: &$WS_0          $&$         1110.0101\ 0100\ 0000   $&          &\\
-            &$WC_0          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.010\ \text{so}\ s_1=-1$)\\
-            &$F_1=2S_0-K_1  $&${\color{blue}0001.11}00\ 0000\ 0000$&        &$S_1={\color{blue}0000.11}00\ 0000\ 0000$\\
-            &                &                                   &          &$SM_1={\color{blue}0000.10}00\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.1001\ 0100\ 0000   $&$\ll2    $&$K_1=0000.0100\ 0000\ 0000\ $\\
-            &$carry         $&$         0000.1000\ 0000\ 0000   $&$\ll2    $&$C_1=1111.1100\ 0000\ 0000\,$\\
-    \hdashline\\    
-    Step 2: &$WS_1          $&$         1110.0101\ 0000\ 0000   $&          &\\
-            &$WC_2          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=0000.010\ \text{so}\ s_2=0$)\\
-            &$F_2=0       $&${\color{blue}0000.0000}\ 0000\ 0000$&          &$S_2={\color{blue}0000.1100}\ 0000\ 0000$\\
-            &                &                                   &          &$SM_2={\color{blue}0000.1110}\ 0000\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1100.0101\ 0000\ 0000   $&$\ll2    $&$K_2=0000.0001\ 0000\ 0000\ $\\
-            &$carry         $&$         0100.0000\ 0000\ 0000   $&$\ll2    $&$C_2=1111.1111\ 0000\ 0000\,$\\
-    \hdashline\\
-    Step 3: &$WS_2          $&$         0001.0100\ 0000\ 0000   $&          &\\
-            &$WC_2          $&$         0000.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_3=1$)\\
-            &$F_3=-2S_2-K_3$&${\color{blue}1110.0111\ 11}00\ 0000$&         &$S_3={\color{blue}0000.1100\ 01}00\ 0000$\\
-            &                &                                   &          &$SM_3={\color{blue}0000.1100\ 00}00\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0011\ 1100\ 0000   $&$\ll2    $&$K_3=0000.0000\ 0100\ 0000\ $\\
-            &$carry         $&$         1000.1000\ 0000\ 0000   $&$\ll2    $&$C_3=1111.1111\ 1100\ 0000\,$\\
-    \hdashline\\
-    Step 4: &$WS_3          $&$         1100.1111\ 0000\ 0000   $&          &\\
-            &$WC_3          $&$         0010.0000\ 0000\ 0000   $&          &($W_{msbs}=1110.111\ \text{so}\ s_4=-1$)\\
-            &$F_4=2S_3-K_3  $&${\color{blue}0001.1000\ 0111}\ 0000$&        &$S_4={\color{blue}0000.1100\ 0011}\ 0000$\\
-            &                &                                   &          &$SM_4={\color{blue}0000.1100\ 0010}\ 0000\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         1111.0111\ 0111\ 0000   $&$\ll2    $&$K_4=0000.0000\ 0001\ 0000\ $\\
-            &$carry         $&$         0001.0000\ 0000\ 0000   $&$\ll2    $&$C_4=1111.1111\ 1111\ 0000\,$\\
-    \hdashline\\
-    Step 5: &$WS_4          $&$         1101.1101\ 1100\ 0000   $&          &\\
-            &$WC_4          $&$         0100.0000\ 0000\ 0000   $&          &($W_{msbs}=0001.110\ \text{so}\ s_5=1$)\\
-            &$F_5=-2S_4-K_4 $&${\color{blue}1110.0111\ 1001\ 11}00$&        &$S_5={\color{blue}0000.1100\ 0011\ 01}00$\\
-            &                &                                   &          &$SM_5={\color{blue}0000.1100\ 0011\ 00}00\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0111.1010\ 0101\ 1100   $&$\ll1    $&$K_5=0000.0000\ 0000\ 0100\ $\\
-            &$carry         $&$         1000.1011\ 0000\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1111\ 1100\,$\\
-    \hdashline\\
-    Step 6: &$WS_5          $&$         1110.1001\ 0111\ 0000   $&          &\\
-            &$WC_5          $&$         0010.1100\ 0000\ 0000   $&          &($W_{msbs}=0001.010\ \text{so}\ s_6=1$)\\
-            &$F_6=          $&$                                 $&          &$S_5={\color{blue}0000.1100\ 0011\ 0101}$\\
-            &                &                                   &          &$SM_5={\color{blue}0000.1100\ 0011\ 0100}\phantom{M}$\\
-    \cline{2-3}
-            &$sum           $&$         0001.1110\ 1001\ 0111   $&$\ll1    $&$K_5=0000.0000\ 0000\ 0001\ $\\
-            &$carry         $&$         1110.0010\ 1100\ 0000   $&$\ll1    $&$C_5=1111.1111\ 1111\ 1111\,$\\
-    \hdashline\\
-    Terminate
-\end{tabular}
-\end{center}
-}
-
-\end{document}
diff --git a/docs/docker/Dockerfile.builds b/docs/docker/Dockerfile.builds
deleted file mode 100644
index ec157de07..000000000
--- a/docs/docker/Dockerfile.builds
+++ /dev/null
@@ -1,104 +0,0 @@
-FROM wallysoc/ubuntu_wally
-
-# SET ENVIRONMENT VARIABLES
-# assume 4 threads are available to speed up
-ARG NUM_THREADS=4
-ENV RISCV=/opt/riscv
-ENV PATH="$PATH:${RISCV}/bin"
-ENV MANPATH="$MANPATH:${RISCV}/share/man"
-
-# this is required by podman
-USER root
-WORKDIR /opt/riscv
-
-# TOOLCHAIN
-RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
-    cd riscv-gnu-toolchain && \
-    sed -i 's/https/git/' .gitmodules && git submodule sync && \
-    ./configure --prefix=${RISCV} --enable-multilib \
-        --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
-    make --jobs ${NUM_THREADS} && \
-    make install && cd ${RISCV} && \
-    rm -rf ${RISCV}/riscv-gnu-toolchain
-
-# elf2hex
-RUN git clone https://github.com/sifive/elf2hex.git && \
-    cd elf2hex && \
-    autoreconf -i && \
-    ./configure --target=riscv64-unknown-elf --prefix=${RISCV} && \
-    make && \
-    make install && cd ${RISCV} && \
-    rm -rf ${RISCV}/elf2hex
-
-# QEMU
-RUN git clone --recursive https://github.com/qemu/qemu && \
-    cd qemu && \
-    ./configure --target-list=riscv64-softmmu --prefix=${RISCV}  && \
-    make --jobs ${NUM_THREADS} && \
-    make install && cd ${RISCV} && \
-    rm -rf ${RISCV}/qemu
-
-# Spike
-RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
-    mkdir riscv-isa-sim/build && \
-    cd riscv-isa-sim/build && \
-    ../configure --prefix=$RISCV --enable-commitlog && \
-    make --jobs ${NUM_THREADS} && \
-    make install && cd ${RISCV} && \
-    rm -rf ${RISCV}/riscv-isa-sim
-
-# SAIL
-RUN opam init -y --disable-sandboxing && \
-    opam switch create 5.1.0 && \
-    opam install sail -y && \
-    eval $(opam config env) && \
-    git clone https://github.com/riscv/sail-riscv.git && \
-    cd sail-riscv && \
-    ARCH=RV32 make c_emulator/riscv_sim_RV32 && \
-    ARCH=RV64 make c_emulator/riscv_sim_RV64 && \
-    cp ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV64 ${RISCV}/bin/riscv_sim_RV64 && \
-    cp ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV32 ${RISCV}/bin/riscv_sim_RV32 && \
-    rm -rf ${RISCV}/sail-riscv
-
-COPY ./buildroot-config-src /opt/riscv/buildroot-config-src
-COPY ./testvector-generation /opt/riscv/testvector-generation
-
-# # Buildroot
-RUN git clone https://github.com/buildroot/buildroot.git && \
-    cd buildroot && \
-    git checkout 2021.05 && \
-    cp -r /opt/riscv/buildroot-config-src ./board/wally && \
-    cp ./board/wally/main.config .config && \
-    make --jobs ${NUM_THREADS} && \
-    # generate files for buildroot regression
-    mkdir -p ${RISCV}/linux-testvectors && \
-    cd /opt/riscv/testvector-generation && \
-    curl https://raw.githubusercontent.com/openhwgroup/cvw/main/linux/devicetree/wally-virt.dts --output ${RISCV}/buildroot/output/images/wally-virt.dts && \
-    dtc -I dts -O dtb ${RISCV}/buildroot/output/images/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb && \
-    make && ./genInitMem.sh && \
-    chmod -R a+rw ${RISCV}/linux-testvectors && \
-    rm -rf ${RISCV}/buildroot
-
-RUN pip3 install --no-cache-dir \
-    testresources riscv_config \
-    git+https://github.com/riscv/riscof.git
-
-# Wally needs Verilator 5.021 or later.
-# Verilator needs to be built from scratch to get the latest version
-# apt-get install verilator installs version 4.028 as of 6/8/23
-RUN apt-get install -y \
-    perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g \
-    libfl2  libfl-dev && \
-    apt-get clean
-RUN git clone https://github.com/verilator/verilator && \
-    cd verilator && \
-    git pull && \
-    git checkout v5.022 && \
-    autoconf && \
-    ./configure --prefix=${RISCV} && \
-    make -j ${NUM_THREADS} && \
-    make install && \
-    cd ${RISCV} && rm -rf ${RISCV}/verilator
-
-USER ${USERNAME}
-WORKDIR /home/${USERNAME}/cvw
\ No newline at end of file
diff --git a/docs/docker/Dockerfile.regression b/docs/docker/Dockerfile.regression
deleted file mode 100644
index 1bcda8baf..000000000
--- a/docs/docker/Dockerfile.regression
+++ /dev/null
@@ -1,17 +0,0 @@
-FROM wallysoc/toolchains_wally
-
-ENV QUESTA=/cad/mentor/questa_sim-xxxx.x_x
-ENV RUN_QUESTA=false
-ENV USERNAME=cad
-
-VOLUME [ "/home/${USERNAME}/cvw" ]
-USER root
-
-COPY --chown=${USERNAME}:${USERNAME} . /home/${USERNAME}
-RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}
-RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}/cvw
-
-USER ${USERNAME}
-WORKDIR /home/${USERNAME}/cvw
-
-CMD [ "/bin/sh", "-c", "/home/${USERNAME}/run_regression.sh" ]
\ No newline at end of file
diff --git a/docs/docker/Dockerfile.ubuntu b/docs/docker/Dockerfile.ubuntu
deleted file mode 100644
index cc98bd5c5..000000000
--- a/docs/docker/Dockerfile.ubuntu
+++ /dev/null
@@ -1,33 +0,0 @@
-FROM ubuntu:22.04@sha256:aa772c98400ef833586d1d517d3e8de670f7e712bf581ce6053165081773259d
-
-RUN apt update && \
-    apt install -y \
-        git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils verilator cpio bc vim emacs gedit nano && \
-    apt-get clean
-
-# COPY requirements.txt /root
-RUN pip3 install --no-cache-dir \
-    sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief
-
-RUN ln -s /usr/bin/python3 /usr/bin/python
-
-# Create a user group 'xyzgroup'
-ENV USERNAME=cad
-ARG USER_UID=1000
-ARG USER_GID=$USER_UID
-
-# Create the user
-RUN groupadd --gid $USER_GID ${USERNAME} \
-    && useradd --uid $USER_UID --gid $USER_GID -m ${USERNAME} \
-    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
-    && apt-get update \
-    && apt-get install -y sudo \
-    && echo ${USERNAME} ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/${USERNAME} \
-    && chmod 0440 /etc/sudoers.d/${USERNAME}
-
-# Change RISCV user
-RUN chown -Rf cad:cad /opt
-
-# Add cad user
-USER ${USERNAME}
-WORKDIR /home/${USERNAME}
\ No newline at end of file
diff --git a/docs/docker/Makefile b/docs/docker/Makefile
deleted file mode 100644
index 82560d8cb..000000000
--- a/docs/docker/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-QUESTA_HOME?=/cad/mentor/questa_sim-2023.4
-CVW_GIT?=""
-
-commanline:
-	podman run -it --rm \
-	-v cvw_temp:/home/cad/cvw \
-	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-	--privileged --network=host \
-	wallysoc/regression_wally /bin/bash
-
-regression_openhw_cvw:
-	podman run \
-	-e CVW_GIT=$(CVW_GIT) \
-	-e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
-	-v cvw_temp:/home/cad/cvw \
-	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
-	--privileged --network=host \
-	--rm wallysoc/regression_wally
-
-push_hub:
-	podman push wallysoc/ubuntu_wally:latest
-	podman push wallysoc/toolchains_wally:latest
-	podman push wallysoc/regression_wally:latest
-
-update_ubuntu:
-	podman build -t wallysoc/ubuntu_wally -f Dockerfile.ubuntu .
-
-update_toolchains:
-	podman build -t wallysoc/toolchains_wally -f Dockerfile.builds .
-
-update_regression:
-	podman build -t wallysoc/regression_wally -f Dockerfile.regression .
\ No newline at end of file
diff --git a/docs/docker/README.md b/docs/docker/README.md
deleted file mode 100644
index e21e53211..000000000
--- a/docs/docker/README.md
+++ /dev/null
@@ -1,333 +0,0 @@
-# Consistant Build of Toolchain for Wally
-
-`Dockerfile.*` contains a ~~multi-stage~~ build for all the toolchains that are required for Wally's open-source features.
-
-Hazards:
-
-- If there is any change in `${CVW_HOME}/linux/buildroot-config-src` folder with main.config, you have to copy it to the current folder to `buildroot-config-src`
-- If there is any change in `${CVW_HOME}/linux/testvector-generation` folder with main.config, you have to copy it to the current folder to `testvector-generation`
-
-If you have any other questions, please read the [troubleshooting]() first.
-
-## TODOs
-
-- [ ] Pinning the tools version
-    - As for the consistent tool build, should we use specific versions of tools in order to avoid bugs at the master branch?
-    - And we will upgrade the versions of tool after a certain period of time to get the latest features and patches while verifying it won’t cause any problem.
-- [x] Mount the ~~EDA Tools~~QuestaSIM and Path
-    - USE_QUESTA and QUESTA for path
-- [x] Enable X11 forwarding for docker
-    - `--network=host` for docker run
-    - `xhost +localhost:${USER}` for host
-- [x] Regression Script
-- [x] Configure the license for Questa
-- [x] Change the condition from empty string to 1
-- [x] Add linux testvector-generation
-    - [x] Estimate the useless building intermediate files
-
-## TL;DR
-
-Steps:
-
-1. Install either Docker Engine or Podman for container support
-2. Run start-up script `docs/docker/start.sh` to start a stateless container to run the toolchains and EDA tool
-
-### Docker Engine or Podman
-
-First and foremost, install either Docker Engine or Podman:
-
-- Docker Engine (More Popular, default): https://docs.docker.com/engine/install/
-- Podman: https://podman.io/docs/installation
-
-Here are some common installation commands (not guarantee to be up to date)
-
-```shell
-# For Ubuntu
-# Add Docker's official GPG key:
-sudo apt-get update
-sudo apt-get install ca-certificates curl
-sudo install -m 0755 -d /etc/apt/keyrings
-sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
-sudo chmod a+r /etc/apt/keyrings/docker.asc
-
-# Add the repository to Apt sources:
-echo \
-  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
-  $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
-  sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
-sudo apt-get update
-# Installation
-sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
-# Hello-World Example
-docker run hello-world
-```
-
-### Use of Start-up Script
-
-Files at this folder can help you to build/fetch environment you need to run wally with the help of Docker.
-
-Here are some common use cases, it will **provides you an environment with RISC-V toolchains** that required by this project:
-
-```shell
-# By default, we assume that you have cloned the cvw respository and running the script at relative path `docs/docker`
-
-# For HMC students, /opt/riscv is available and nothing needs to be built
-TOOLCHAINS_MOUNT=/opt/riscv QUESTA=/cad/mentor/questa_sim-2023.4 ./start.sh
-
-# For those with all the toolchains installed, simply mount the toolchains
-TOOLCHAINS_MOUNT=<path-to-toolchains> ./start.sh
-
-# For those have nothing, fetching the builds are easiest thing
-CVW_MOUNT=<path-to-cvw> ./start.sh
-# if you want to use Podman instead of Docker Engine
-USE_PODMAN=1 ./start.sh
-
-# For other cases, checkout start-up script for building option
-```
-For further usage, please consult the following configuration.
-
-### Regression on Master Branch
-
-The regression script is used by image `wallysoc/regression_wally` to run regressions on the master branch of a specific repository.
-
-If you are using docker, then replace the following podman with docker.
-
-```shell
-# create volume for permanent storage
-podman volume create cvw_temp
-
-# run regression on the OpenHW/cvw
-podman run \
-    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
-    -v cvw_temp:/home/cad/cvw \
-    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    --rm wallysoc/regression_wally
-
-# run regression on the Karl-Han/cvw
-podman run \
-    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
-    -e CVW_GIT=https://github.com/Karl-Han/cvw \
-    -v cvw_temp:/home/cad/cvw \
-    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    --rm wallysoc/regression_wally
-
-# get into the container command line to debug or reading files
-podman run -it \
-    -e RUN_QUESTA=1 \
-    -v cvw_temp:/home/cad/cvw \
-    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
-    --privileged --network=host \
-    wallysoc/regression_wally /bin/bash
-```
-
-## Conventions
-
-- In the container
-    - default user is `cad`
-    - RISCV is defined as `/opt/riscv`
-    - QUESTA is defined as `/cad/mentor/questa_sim-xxxx.x_x`
-        - bin location is in `$QUESTA/questasim/bin`
-    - cvw folder should be mounted on `/home/${USERNAME}/cvw`
-        - as for `cad`, it is `/home/cad/cvw`
-- In the current shell environment: checkout the constants in the following script section
-
-## New Dockerfile Design
-
-There are two parts of the new docker-related design:
-
-- build proper image(s)
-- scripts for different purposes
-
-### Problem Statement
-
-The following 3 problems are to be resolved:
-
-- remove storage of useless files with `Dockerfile`
-    - git build: clean up
-    - packages info
-        - apt: `apt-get clean`
-        - pip: `--no-cache-dir`
-- reuse storage
-    - read-only $RISCV volume across different users with `docker image`
-    - local-built RISCV with `start-up script`
-- use commercial EDA tools: optional environment variable configuration with `start-up script`
-
-### Dockerfiles
-
-There are two Dockerfiles:
-
-- `Dockerfile.ubuntu`: basic ubuntu system setup and produce `ubuntu_wally` image in docker
-    - corresponds to `wallysoc/ubuntu_wally`
-- `Dockerfile.builds`: all the required toolchains are built
-    - corresponds to `wallysoc/toolchains_wally`
-
-Because we are going to use the whole environment of ubuntu to get both executables and python packages, we are not going to use multi-stage builds, which runs only executables.
-
-### Scripts
-
-There are four scripts:
-
-- `start.sh` (most often used): start running the container
-    - if you don't care about toolchains and running regression automatically, this script is only thing you need to know
-- `get_images.sh`: get docker image `wallysoc/ubuntu_wally` or `wallysoc/toolchains_wally`
-- `get_buildroot_testvector.py`: copy buildroot and testvector configuration required by building
-- `run_regression.sh`: run regressions with Verilator (and QuestaSIM) on specific CVW
-    - this script is not intended to be run directly, but inside the container
-    - However, it is a good resource to look into to know what is happening
-- `test.sh`: a test script to facilitate the above three
-
-All the following options in the corresponding scripts should be set by either:
-
-- define it right before the command: `USE_PODMAN=1 ./start.sh` with USE_PODMAN on start-up script
-    - the variable is only effective for the current command, not the following environment
-- declare it globally and use it any time afterwards:
-
-```shell
-# declare it globally in the environment
-export DOCKER_EXEC=$(which docker)
-export UBUNTU_BUILD=1
-
-# run the script with all the above variables
-./get_images.sh
-```
-
-#### Start-up Script: start.sh
-
-There are two settings:
-
-- build/fetch both ubuntu_wally and toolchains in docker image and use it
-- build/fetch only ubuntu_wally and use local toolchains folder
-
-Options:
-
-- USE_PODMAN:
-    - by default, docker is used
-    - set USE_PODMAN=1 otherwise
-- UBUNTU_BUILD:
-    - fetch by default
-    - set UBUNTU_BUILD=1 if you want to build with Dockerfile.ubuntu
-- TOOLCHAINS_BUILD:
-    - fetch by default
-    - set TOOLCHAINS_BUILD=1 if you want to build with Dockerfile.build
-
-#### Image Building Script: get_images.sh
-
-Options (if you want to build the images):
-
-- DOCKER_EXEC:
-    - docker by default
-    - if you want to use podman, then set it to $(which podman)
-- UBUNTU_BUILD:
-    - fetch by default
-    - set it to 1 if you want to build it instead of fetching it
-- TOOLCHAINS_BUILD:
-    - fetch by default
-    - set it to 1 if you want to build it instead of fetching it
-
-#### Regression Script: run_regression.sh
-
-There are two parts for regression:
-
-- Verilator: must be able to run as it is open-sourced
-- Questa: OPTIONAL as it is commercial EDA Tool
-
-
-There are three main knobs:
-
-1. CLEAN_CVW: remove the `/home/${USERNAME}/cvw` inside the container (it can be a volume) and clone the `${CVW_GIT}`.
-2. BUILD_RISCOF: build RISCOF in the `/home/${USERNAME}/cvw`, sometimes you don't want to rebuild if there is no change in the test suite.
-3. RUN_QUESTA: enable the QuestaSIM in regression
-
-Options:
-
-- CVW_GIT: git clone address
-- CLEAN_CVW: clone CVW_GIT if enabled with `-e CLEAN_CVW=1`
-- BUILD_RISCOF: rebuild RISCOF if enabled with `-e BUILD_RISCOF=1`
-- RUN_QUESTA: run vsim to check if enabled with `-e RUN_QUESTA=1`
-    - QUESTA: home folder for mounted QuestaSIM `/cad/mentor/questa_sim-xxxx.x_x` if enabled
-    - for example, if your vsim is in `/cad/mentor/questa_sim-2023.4/questasim/bin/vsim` then your local QuestaSIM folder is `/cad/mentor/questa_sim-2023.4`, so you have to add `-v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x -e RUN_QUESTA=1`
-
-### Commercial EDA Tools
-
-This is kind of tricky, because Docker network is a different network from the host. Therefore, it should be carefully handled in order to use the host's license server while minimizing the access of docker container.
-
-There are at least two ways to solve this problem:
-
-- use `--network=host` in docker-run to use the same network
-- (NOT WORKING) use bridge in docker-run while forwarding docker network's traffic to localhost without setting `X11UseLocalhost no`
-    - this idea is from https://stackoverflow.com/a/64284364/10765798
-
-## Old Dockerfile Analysis
-
-> Refer to https://github.com/openhwgroup/cvw/blob/91919150a94ccf8e750cf7c9eec1c400efaef7f5/docs/Dockerfile
-
-There are stages in the old Dockerfile:
-
-- debian-based package installtion
-    - apt package
-    - python3 package
-- user and its group configuration
-- clone and build toolchain with prefix=$RISCV
-    - riscv-gnu-toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain
-    - elf2hex: https://github.com/sifive/elf2hex
-    - qemu: https://github.com/qemu/qemu
-    - spike: https://github.com/riscv-software-src/riscv-isa-sim
-    - sail: https://github.com/riscv/sail-riscv/commits/master/
-    - buildroot: https://github.com/buildroot/buildroot
-    - verilator: https://github.com/verilator/verilator
-
-### Tool Versions till 20240331
-
-- riscv-gnu-toolchain: `2024.03.01`
-- elf2hex: `f28a3103c06131ed3895052b1341daf4ca0b1c9c`
-- qemu: not tested
-- spike: `3427b459f88d2334368a1abbdf5a3000957f08e8`
-- sail: `f601c866153c79a7ae8404f939dc2d66aa2e41f9`
-- buildroot: `2021.05`
-- verilator: `v5.022`
-
-## Troubleshooting
-
-### Permission Denied for .git
-
-Description: permission problem in `/home/$USERNAME/cvw`.
-
-```text
-$ podman run -v cvw_temp:/home/cad/cvw -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --rm wallysoc/regression_wally                          
-No CVW_GIT is provided                                                                                 
-rm: cannot remove '/home/cad/cvw': Device or resource busy                                             
-Cloning into '/home/cad/cvw'...                                                                        
-/home/cad/cvw/.git: Permission denied                                                                  
-chmod: cannot access '/home/cad/cvw/setup.sh': No such file or directory                               
-chmod: cannot access '/home/cad/cvw/site-setup.sh': No such file or directory                          
-make: *** No rule to make target 'install'.  Stop.                                                     
-make: *** No rule to make target 'verify'.  Stop.                                                      
-make: *** No rule to make target 'coverage'.  Stop.                                                    
-make: *** No rule to make target 'benchmarks'.  Stop.                                                  
-/home/cad/run_regression.sh: line 64: cd: /home/cad/cvw/sim: No such file or directory                 
-/home/cad/run_regression.sh: line 65: /home/cad/cvw/sim/regression_verilator.out: No such file or direc
-tory       
-```
-
-It may be caused by podman and I am not sure why it happens.
-
-Solution: get into the container with interaction as root and change the permission of the folder/volume `/home/$USERNAME/cvw`
-
-```shell
-podman run -it --user root -v cvw_temp:/home/cad/cvw -e RUN_QUESTA= -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --net=host --rm --privileged wallysoc/regression_wally /bin/bash
-
-chown -R $USERNAME:$USERNAME /home/$USERNAME
-```
-
-## References
-
-- Dockerfile Docs: https://docs.docker.com/reference/dockerfile/
-- Multi-stage builds: https://docs.docker.com/build/building/multi-stage/
-- Best Practices: https://docs.docker.com/develop/develop-images/guidelines/
-- Chinese Reference: https://yeasy.gitbook.io/docker_practice/
-- Clean Cache
-    - apt cache: https://gist.github.com/marvell/7c812736565928e602c4
-    - pip cache: https://stackoverflow.com/questions/50333650/install-python-package-in-docker-file
-- Docker Network: https://docs.docker.com/network/
diff --git a/docs/docker/get_buildroot_testvector.py b/docs/docker/get_buildroot_testvector.py
deleted file mode 100644
index 5c8103778..000000000
--- a/docs/docker/get_buildroot_testvector.py
+++ /dev/null
@@ -1,14 +0,0 @@
-import os
-import shutil
-
-# if WALLY is defined, then get it
-WALLY_HOME = os.getenv("WALLY")
-if WALLY_HOME is None or WALLY_HOME == "":
-    # otherwise, it is assumed as ../../
-    WALLY_HOME = "../../"
-
-BUILDROOT_SRC = "linux/buildroot-config-src/wally"
-TESTVECTOR_SRC = "linux/testvector-generation"
-
-shutil.copytree(os.path.join(WALLY_HOME, BUILDROOT_SRC), "./buildroot-config-src")
-shutil.copytree(os.path.join(WALLY_HOME, TESTVECTOR_SRC), "./testvector-generation")
diff --git a/docs/docker/get_images.sh b/docs/docker/get_images.sh
deleted file mode 100755
index 2e7b43c0c..000000000
--- a/docs/docker/get_images.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-UBUNTU_BUILD=${UBUNTU_BUILD:-0}
-TOOLCHAINS_BUILD=${TOOLCHAINS_BUILD:-0}
-
-if [ -n "$USE_PODMAN" ]; then
-    DOCKER_EXEC=$(which podman)
-else
-    DOCKER_EXEC=$(which docker)
-fi
-
-if [ $UBUNTU_BUILD -eq 1 ]; then
-    ${DOCKER_EXEC} build -t ubuntu_wally -f Dockerfile.ubuntu .
-    ${DOCKER_EXEC} tag ubuntu_wally:latest wallysoc/ubuntu_wally:latest
-else
-    ${DOCKER_EXEC} pull wallysoc/ubuntu_wally
-fi
-
-if [ $TOOLCHAINS_BUILD -eq 1 ]; then
-    `which python` get_buildroot_testvector.py
-    ${DOCKER_EXEC} build -t toolchains_wally -f Dockerfile.builds .
-    ${DOCKER_EXEC} tag toolchains_wally:latest wallysoc/toolchains_wally:latest
-else
-    ${DOCKER_EXEC} pull wallysoc/toolchains_wally
-fi
\ No newline at end of file
diff --git a/docs/docker/run_regression.sh b/docs/docker/run_regression.sh
deleted file mode 100755
index 6d125bc7e..000000000
--- a/docs/docker/run_regression.sh
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/bin/bash
-# this script is used to run regression inside the Dockerfile.regression
-# of course, you can run it in the current environment as soon as
-#   - RISCV is defined
-#   - QUESTA is defined
-# declare with empty string: export ABC=
-
-# Options:
-# - CVW_GIT: git clone address, only main branch supported
-# - CLEAN_CVW: declared with empty string to clone
-# - BUILD_RISCOF: declared with empty string to rebuild RISCOF
-# - RUN_QUESTA: declared with empty string to run vsim to check
-
-# now only main branch is supported
-if [ -z "${CVW_GIT}" ]; then
-    echo "No CVW_GIT is provided"
-    export CVW_GIT="https://github.com/openhwgroup/cvw"
-else
-    echo "Using customized CVW_GIT: ${CVW_GIT}"
-    # support specific branch now
-    export CVW_GIT=$(echo ${CVW_GIT} | sed -E "s/tree\// -b /g")
-fi
-
-git config --global http.version HTTP/1.1
-
-# if cvw is not available or CLEAN_CVW(empty string) is defined
-if [[ ! -f "/home/${USERNAME}/cvw/setup.sh" ]] || [[ "${CLEAN_CVW}" -eq 1 ]]; then
-    cd /home/${USERNAME} && rm -rf /home/${USERNAME}/cvw
-    git clone --recurse-submodules  ${CVW_GIT} /home/${USERNAME}/cvw
-    # if failed to clone submodules for some reason, please run `git submodule update`
-fi
-
-# Preset Environment Variable
-export PATH="${RISCV}/bin:${PATH}"
-export CVW_HOME="/home/${USERNAME}/cvw"
-export QUESTA="/cad/mentor/questa_sim-xxxx.x_x"
-export PATH="${QUESTA}/questasim/bin:${PATH}"
-
-# cd /home/${USERNAME}/cvw && chmod +x ./setup.sh && ./setup.sh
-chmod +x ${CVW_HOME}/setup.sh && source ${CVW_HOME}/setup.sh
-chmod +x ${CVW_HOME}/site-setup.sh && source ${CVW_HOME}/site-setup.sh
-
-# Overwriting
-export QUESTAPATH=/cad/mentor/questa_sim-xxxx.x_x/questasim/bin
-
-# # if you are making it alone, it works
-# make
-
-cd ${CVW_HOME}
-# build it only if BUILD_RISCOF is defined with empty string
-if [[ "${BUILD_RISCOF}" -eq 1 ]]; then
-    make install && make riscof && make testfloat
-fi
-
-if [[ "${RUN_QUESTA}" -eq 1 ]] ; then
-    if [ ! -f "${QUESTA}/questasim/bin/vsim" ]; then
-        echo "Cannot find vsim with ${QUESTA}/questasim/bin/vsim"
-    else
-        # cd sim && ./regression-wally 2>&1 > ./regression_questa.out && cd ..
-        # make verify
-        regression-wally
-    fi
-fi
-
-make coverage
-make benchmarks
-
-if [[ ! NO_VERILATOR -eq 1 ]]; then
-    make -C sim/verilator run
-    # by default it runs the arch64i on rv64gc
-    cat ${CVW_HOME}/sim/verilator/logs/rv64gc_arch64i.log
-fi
diff --git a/docs/docker/start.sh b/docs/docker/start.sh
deleted file mode 100755
index ce3076574..000000000
--- a/docs/docker/start.sh
+++ /dev/null
@@ -1,37 +0,0 @@
-if [ -n "$USE_PODMAN" ]; then
-    DOCKER_EXEC=$(which podman)
-else
-    DOCKER_EXEC=$(which docker)
-fi
-if [ -n "$USE_PODMAN" ]; then
-       CVW_MOUNT=$(pwd)/../../
-fi
-echo ${CVW_MOUNT}
-USERNAME="cad"
-
-UBUNTU_WALLY_HASH=$(${DOCKER_EXEC} images --quiet wallysoc/ubuntu_wally)
-TOOLCHAINS_HASH=$(${DOCKER_EXEC} images --quiet wallysoc/toolchains_wally)
-TOOLCHAINS_MOUNT=${TOOLCHAINS_MOUNT}
-
-if [ -z $UBUNTU_WALLY_HASH ]; then
-    echo "CANNOT FIND wallysoc/ubuntu_wally, please get the image first with \`get_image.sh\`";
-    exit 1
-else
-    echo "Get ${UBUNTU_WALLY_HASH} for ubuntu_wally"
-fi
-
-if [ ! -z $TOOLCHAINS_MOUNT ]; then
-    if [ -n "$QUESTA" ]; then
-        ${DOCKER_EXEC} run -it --rm -v ${TOOLCHAINS_MOUNT}:/opt/riscv -v ${CVW_MOUNT}:/home/${USERNAME}/cvw -v ${QUESTA}:/cad/mentor/questa_sim-xxxx.x_x wallysoc/ubuntu_wally
-    else
-        ${DOCKER_EXEC} run -it --rm -v ${TOOLCHAINS_MOUNT}:/opt/riscv -v ${CVW_MOUNT}:/home/${USERNAME}/cvw wallysoc/ubuntu_wally
-    fi
-elif [ -z $TOOLCHAINS_HASH ]; then
-    echo "CANNOT FIND wallysoc/toolchains_wally, please get the image first with \`get_image.sh\`";
-    exit 1
-else
-    echo "Get ${TOOLCHAINS_HASH} for toolchains_wally"
-    ${DOCKER_EXEC} run --user root -it --rm -v ${CVW_MOUNT}:/home/${USERNAME}/cvw wallysoc/toolchains_wally
-fi
-
-echo "Successfully reach the end"
diff --git a/docs/docker/test.sh b/docs/docker/test.sh
deleted file mode 100644
index fdd4eec85..000000000
--- a/docs/docker/test.sh
+++ /dev/null
@@ -1,22 +0,0 @@
-# There are three parts in testing as there are three scripts
-# It is fine to use either docker or podman as they are equivalent in the context
-export USE_PODMAN=1
-
-## build either one of them
-UBUNTU_BUILD=1 ./get_image.sh
-echo "get images is $?"
-
-## mount toolchian and questa
-TOOLCHAINS_MOUNT=/opt/riscv QUESTA=/cad/mentor/questa_sim-2023.4 ./start.sh
-# then run 
-# - `file ${QUESTA}/questasim/vsim` to check if it is properly mount
-# - `file $RISCV/bin/riscv64-unknown-elf-gcc` to check the toolchain
-
-## use internal toolchain
-./start.sh
-# then run 
-# - `file $RISCV/bin/riscv64-unknown-elf-gcc` to check the toolchain
-# - `which verilator | grep riscv` to check the verilator
-
-## mount questa
-RUN_QUESTA=true QUESTA=/cad/mentor/questa_sim-2023.4 ./run_regression.sh
\ No newline at end of file
diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md
deleted file mode 100644
index c77156842..000000000
--- a/docs/testplans/testplan.md
+++ /dev/null
@@ -1,19 +0,0 @@
-# CORE-V Wally Design Verification Test Plan
-
-CORE-V Wally is functionally tested in the following ways.  Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
-
-| Tests               | Section        | TRL3         | TRL5   | Coverage Method       | Status | Command | 
-| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- |
-| Verilator Lint      | 5.3            | All configs  | rv64gc | lint-wally            | PASS   | regression-wally --nightly |
-| Instructions        | 3.7            | All configs  | rv64gc | riscv-arch-test       | PASS   | regression-wally --nightly |
-| Privileged          | 3.7            | All configs  | rv64gc | wally-riscv-arch-test | PASS   | regression-wally --nightly |
-| Floating-point      | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc    | TestFloat | FAIL   | regression-wally --nightly |
-| CoreMark            | 21.1           | Many configs | rv64gc | CoreMark              |        | regression-wally --nightly |
-| Embench             | 21.2           | rv32*        | n/a    | Embench               |        | regression-wally --nightly |
-| Cache PV            | 21.3.1         | rv{32/64}gc  | rv64gc | TBD                   | TBD    | TBD |
-| Cache PV            | 21.3.2         | rv{32/64}gc  | rv64gc | TBD                   | TBD    | TBD |
-| Linux Boot          | 22.3.2         | rv64gc       | rv64gc | TBD                   | TBD    | TBD |
-| FPGA Linux Boot     | 23.2           |              | rv64gc | TBD                   | TBD    | TBD |
-| Code Coverage       | 5.11.10        |              | rv64gc | TBD                   | TBD    | TBD |
-| Functional Coverage | 5.11.11        |              | rv64gc | TBD                   | TBD    | TBD |
-
diff --git a/examples/C/common/syscalls.c b/examples/C/common/syscalls.c
index 6f57475bc..39547b3d0 100644
--- a/examples/C/common/syscalls.c
+++ b/examples/C/common/syscalls.c
@@ -15,44 +15,6 @@
 extern volatile uint64_t tohost;
 extern volatile uint64_t fromhost;
 
-/////////////////////////////
-// Start of code added for Wally
-//   Use UART rather than syscall host interface for printing
-//////////////////////////////
-
-#include <stdint.h>
-
-void uartInit(void) {
-  volatile uint8_t *UART_LCR = (uint8_t*)0x10000003;
-	*UART_LCR = 0b0000011; // 8-bit characters, 1 stop bit, no parity
-}
-
-void uartSend(char c) {
-  volatile uint8_t *UART_THR = (uint8_t*)0x10000000;
-  volatile uint8_t *UART_LSR = (uint8_t*)0x10000005;
-
-	while (!(*UART_LSR & (1<<5))); // wait for THRE (trans hold reg empty)
-	*UART_THR = c;
-}
-
-char uartReceive(void) {
-  volatile uint8_t *UART_RBR = (uint8_t*)0x10000000;
-  volatile uint8_t *UART_LSR = (uint8_t*)0x10000005;
-
-	while (!(*UART_LSR & (1<<0))); // wait for DR (Data Ready)
-	return *UART_RBR;
-}
-
-char uartPutStr(const char *str) {
-    while (*str) {
-        uartSend(*str++);
-    }
-}
-
-/////////////////////////////
-// End of code added for Wally
-//////////////////////////////
-
 static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2)
 {
   volatile uint64_t magic_mem[8] __attribute__((aligned(64)));
@@ -114,19 +76,7 @@ void abort()
 
 void printstr(const char* s)
 {
-  // david_harris@hmc.edu 11/30/24 switch to printing via UART rather than syscall
-  // This works on both Spike and Wally simulations
-  //syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
-  uartPutStr(s);
-}
-
-// Added 30 November 2024 David_Harris@hmc.edu
-// The compiler encountering printf with a pure string argument tries to invoke puts
-// rather than the usual printf, so puts must be defined.
-int puts(const char* s)
-{
-  printstr(s);
-  return 0;
+  syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
 }
 
 void __attribute__((weak)) thread_entry(int cid, int nc)
@@ -157,7 +107,6 @@ void _init(int cid, int nc)
 {
   init_tls();
   thread_entry(cid, nc);
-  uartInit(); // added 11/30/2024 David_Harris@hmc.edu for printing via UART
 
   // only single-threaded programs should ever get here.
   int ret = main(0, 0);
@@ -176,11 +125,6 @@ void _init(int cid, int nc)
 #undef putchar
 int putchar(int ch)
 {
-  // David_Harris@hmc.edu 11/30/2024
-  // Replaced syscall with uartSend
-  uartSend(ch);
- 
-  /*
   static __thread char buf[64] __attribute__((aligned(64)));
   static __thread int buflen = 0;
 
@@ -190,7 +134,7 @@ int putchar(int ch)
   {
     syscall(SYS_write, 1, (uintptr_t)buf, buflen);
     buflen = 0;
-  } */
+  }
 
   return 0;
 }
diff --git a/examples/C/common/test.ld b/examples/C/common/test.ld
index 5eccb434c..a50b017e8 100644
--- a/examples/C/common/test.ld
+++ b/examples/C/common/test.ld
@@ -28,8 +28,8 @@ SECTIONS
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
 
-/*  . = ALIGN(0x1000);
-  .text : { *(.text) } */
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
 
   /* data segment */
   .data : { *(.data) }
diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile
index 4e3991e46..c27e423a5 100644
--- a/examples/C/fir/Makefile
+++ b/examples/C/fir/Makefile
@@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET)
 	spike $(TARGET)
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \
diff --git a/examples/C/fir/fir.S b/examples/C/fir/fir.S
new file mode 100644
index 000000000..a96339ba7
--- /dev/null
+++ b/examples/C/fir/fir.S
@@ -0,0 +1,35 @@
+// fir.s
+// mmasserfrye@hmc.edu 30 January 2022
+// FIR filter
+
+// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y
+
+.global fir
+
+fir:
+    li t0, 0          # n = 0 = t0
+    slli t6, a0, 3    # N*8
+    slli t5, a1, 3    # M*8
+    addi t4, t5, -8   # (M-1)*8
+for1:
+    bge t0, t6, end   # exit outer for if n >= N
+    fmv.d.x f3, zero  # sum = 0 = f3
+    li t2, 0          # i = 0 = t2
+    add t1, t4, t0    # [(M-1) + n]*8
+for2:
+    bge t2, t5, for1end  # exit inner for if i >= M
+    sub t3, t1, t2    # [(M-1) + n - i]*8  
+    add t3, t3, a2    # t3 = offset + &X
+    fld f0, 0(t3)     # X[n-i+(M-1)] 
+    add t3, t2, a3    # t3 = offset + &c
+    fld f1, 0(t3)     # c[i] 
+    fmadd.d f3, f0, f1, f3  # sum += c[i]*X[n-i+(M-1)]
+    addi t2, t2, 8    # i++
+    j for2
+for1end:
+    add t3, t0, a4    # t3 = offset + &Y
+    fsd f3, 0(t3)     # Y[n] = sum
+    addi t0, t0, 8    # n++
+    j for1
+end:
+    ret
\ No newline at end of file
diff --git a/examples/C/gpio/gpio.c b/examples/C/gpio/gpio.c
deleted file mode 100644
index e2af967e2..000000000
--- a/examples/C/gpio/gpio.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// gpio.c
-// David_Harris@hmc.edu 30 November 2024
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-// General-Purpose I/O (GPIO) example program illustrating compiled C code
-// compile with make
-// simulate with: wsim rv64gc --elf gpio --sim verilator
-
-#include <stdio.h>  
-#include "gpiolib.h"
-
-int main(void) {
-    printf("GPIO Example!\n\r");
-    pinMode(0, INPUT);
-    pinMode(1, OUTPUT);
-    pinMode(2, OUTPUT);
-
-    for (int i=0; i<10; i++) {
-        // Read pin 0 and write it to pin 1
-        int val = digitalRead(0);
-        printf("Pin 0: %d\n", val);
-        digitalWrite(1, val);
-        
-        // Toggle pin 2
-        printf("Pin 2: %d\n", i%2);
-        digitalWrite(2, i%2);
-    }
-}
diff --git a/examples/C/gpio/gpiolib.h b/examples/C/gpio/gpiolib.h
deleted file mode 100644
index 819089554..000000000
--- a/examples/C/gpio/gpiolib.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// gpiolib.h
-// Basic Arduino-compatible functions for general-purpose input/output
-
-// Assumes GPIO0_BASE is set to the memory-mapped GPIO address from
-// config/rv64gc/config.vh.  
-
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-#include <stdint.h>
-
-///////////////////////////////////////////////////////////////////////////////
-// Bitfield Structs
-///////////////////////////////////////////////////////////////////////////////
-
-typedef struct
-{
-    volatile uint32_t   input_val;      // (GPIO offset 0x00) Pin value
-    volatile uint32_t   input_en;       // (GPIO offset 0x04) Pin input enable*
-    volatile uint32_t   output_en;      // (GPIO offset 0x08) Pin output enable*
-    volatile uint32_t   output_val;     // (GPIO offset 0x0C) Output value
-    volatile uint32_t   pue;            // (GPIO offset 0x10) Internal pull-up enable*
-    volatile uint32_t   ds;             // (GPIO offset 0x14) Pin drive strength
-    volatile uint32_t   rise_ie;        // (GPIO offset 0x18) Rise interrupt enable
-    volatile uint32_t   rise_ip;        // (GPIO offset 0x1C) Rise interrupt pending
-    volatile uint32_t   fall_ie;        // (GPIO offset 0x20) Fall interrupt enable
-    volatile uint32_t   fall_ip;        // (GPIO offset 0x24) Fall interrupt pending
-    volatile uint32_t   high_ie;        // (GPIO offset 0x28) High interrupt enable
-    volatile uint32_t   high_ip;        // (GPIO offset 0x2C) High interrupt pending
-    volatile uint32_t   low_ie;         // (GPIO offset 0x30) Low interrupt enable
-    volatile uint32_t   low_ip;         // (GPIO offset 0x34) Low interrupt pending
-    volatile uint32_t   iof_en;         // (GPIO offset 0x38) HW-Driven functions enable
-    volatile uint32_t   iof_sel;        // (GPIO offset 0x3C) HW-Driven functions selection
-    volatile uint32_t   out_xor;        // (GPIO offset 0x40) Output XOR (invert)
-    // Registers marked with * are asynchronously reset to 0. All others are synchronously reset to 0.
-} GPIO;
-
-///////////////////////////////////////////////////////////////////////////////
-// GPIO Constant Definitions
-///////////////////////////////////////////////////////////////////////////////
-
-#define GPIO0_BASE  (0x10060000U)   // GPIO memory-mapped base address
-
-#define GPIO0 ((GPIO*) GPIO0_BASE)  // Set up pointer to struct of type GPIO aligned at the base GPIO0 memory-mapped address
-
-#define LOW 0
-#define HIGH 1
-
-#define INPUT 0
-#define OUTPUT 1
-#define GPIO_IOF0 2
-
-///////////////////////////////////////////////////////////////////////////////
-// GPIO Functions
-///////////////////////////////////////////////////////////////////////////////
-
-void pinMode(int pin, int function)
-{
-    switch(function) {
-        case INPUT:
-            GPIO0->input_en     |= (1 << pin);   // Sets a pin as an input
-            break;
-        case OUTPUT:
-            GPIO0->output_en    |= (1 << pin);   // Set pin as an output
-            GPIO0->iof_en       &= ~(1 << pin);
-            break;
-        case GPIO_IOF0:
-            GPIO0->iof_sel      &= ~(1 << pin);
-            GPIO0->iof_en       |= (1 << pin);
-    }
-}
-
-void digitalWrite(int pin, int val)
-{
-    if (val) GPIO0->output_val |= (1 << pin);
-    else     GPIO0->output_val &= ~(1 << pin);
-}
-
-int digitalRead(int pin)
-{
-    return (GPIO0->input_val >> pin) & 0x1;
-}
diff --git a/examples/C/hello/Makefile b/examples/C/hello/Makefile
deleted file mode 100644
index b6003d5c0..000000000
--- a/examples/C/hello/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-TARGET = hello
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../common/test.ld -I../common \
-	  $(TARGET).c ../common/crt.S ../common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile
diff --git a/examples/C/hello/hello.c b/examples/C/hello/hello.c
deleted file mode 100644
index 77c562369..000000000
--- a/examples/C/hello/hello.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// hello.c
-// David_Harris@hmc.edu 30 November 2024
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-// Hello World program illustrating compiled C code printing via the UART
-// The Wally team has modified the Berkeley syscalls.c (in examples/C/common)
-// to print via UART rather than the syscall interface.  This is supported
-// on both Spike and Wally.  It assumes the PC16550-compatible UART is at 
-// the default SiFive address of 0x10000000.
-// Note that there seem to be some discrepancies between the UART and Spike
-// such that using \n\r for new lines works best.
-
-// compile with make
-// simulate Wally with: wsim rv64gc --elf hello --sim verilator
-// simulate in Spike with: spike hello
-
-#include <stdio.h>  
-
-int main(void) {
-    printf("Hello Wally!\n\r");
-    for (int i = 0; i < 10; i++) {
-        printf("%d ", i);
-    }
-    printf("\n\r");
-}
\ No newline at end of file
diff --git a/examples/C/inline/inline b/examples/C/inline/inline
new file mode 100755
index 000000000..29b5b8bff
Binary files /dev/null and b/examples/C/inline/inline differ
diff --git a/examples/C/gpio/Makefile b/examples/C/lab1matrix/Makefile
similarity index 92%
rename from examples/C/gpio/Makefile
rename to examples/C/lab1matrix/Makefile
index 237578a46..18c011f4f 100644
--- a/examples/C/gpio/Makefile
+++ b/examples/C/lab1matrix/Makefile
@@ -1,10 +1,11 @@
-TARGET = gpio
+TARGET = matMult
 
 $(TARGET).objdump: $(TARGET)
 	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
+	spike $(TARGET)
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \
@@ -29,4 +30,4 @@ $(TARGET): $(TARGET).c Makefile
 #     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
 
 clean:
-	rm -f $(TARGET) $(TARGET).objdump* $(TARGET).memfile
+	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult
new file mode 100755
index 000000000..e3d3b25dd
Binary files /dev/null and b/examples/C/lab1matrix/matMult differ
diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c
new file mode 100644
index 000000000..b794819f9
--- /dev/null
+++ b/examples/C/lab1matrix/matMult.c
@@ -0,0 +1,87 @@
+// matMult.c
+// mmasserfrye@hmc.edu 30 January 2022
+
+#include <stdio.h>  // supports printf
+#include <math.h>   // supports fabs
+#include "util.h"   // supports verify
+
+// puts the indicated row of length n from matrix mat into array arr
+void getRow(int n, int row, double *mat, double *arr){
+    int ind;
+    for (int i=0; i<n; i++){
+        ind = i+row*n;
+        arr[i] = mat[ind];
+    }
+}
+
+// computes the dot product of arrays a and b of length n
+double dotproduct(int n, double a[], double b[]) {
+
+    volatile int i;
+    double sum;
+    sum = 0;
+
+    for (i=0; i<n; i++) {
+        if (i==0) sum=0;
+        sum += a[i]*b[i];
+    }
+    return sum;
+}
+
+// multiplies matrices A (m1 x n1m2) and B (n1m2 x n2) and puts the result in Y
+void mult(int m1, int n1m2, int n2, double *A, double *B, double *Y) {
+
+    // transpose B into Bt so we can dot product matching rows
+    double Bt[n2*n1m2];
+    int ind;
+    int indt;
+    for (int i=0; i<n1m2; i++){
+        for (int j=0; j<n2; j++){
+            ind = i*n2+j;
+            indt = j*n1m2+i;
+            Bt[indt] = B[ind];
+        }
+    }
+
+    int indY;
+    double Arow[n1m2];
+    double Bcol[n1m2];
+
+    for (int i=0; i<m1; i++){
+        for (int j=0; j<n2; j++){
+            indY = i*n2+j;
+            getRow(n1m2, i, A, Arow);
+            getRow(n1m2, j, Bt, Bcol);
+            Y[indY] = dotproduct(n1m2, Arow, Bcol);
+        }
+    }
+}
+
+int main(void) {
+
+    // change these bits to test stuff
+    int m = 20;
+    int n = 1;
+    double X[20]; // change to m*n
+    double Y[400]; // change to m^2
+
+    // fill in some numbers so the test feels legit
+    for (int i=0; i<n; i++){
+        X[i] = i;
+    }
+ 
+    setStats(1);
+    mult(m, n, m, X, X, Y);
+    setStats(0);
+
+    /*
+    // use this code from Harris's fir.c to print matrix one element at a time
+    // library linked doesn't support printing doubles, so convert to integers to print
+    for (int i=0; i<m*m; i++)  {
+        int tmp = Y[i];
+        printf("Y[%d] = %d\n", i, tmp);
+    }
+    */
+    return 0;
+    
+}
\ No newline at end of file
diff --git a/examples/C/mcmodel/Makefile b/examples/C/mcmodel/Makefile
deleted file mode 100644
index ab2287877..000000000
--- a/examples/C/mcmodel/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-all:
-	riscv64-unknown-elf-gcc -O3 -march=rv64gc -mcmodel=medlow mcmodel.c -o mcmodel_medlow
-	riscv64-unknown-elf-objdump -d mcmodel_medlow > mcmodel_medlow.objdump
-	riscv64-unknown-elf-gcc -O3 -march=rv64gc -mcmodel=medany mcmodel.c -o mcmodel_medany
-	riscv64-unknown-elf-objdump -d mcmodel_medany > mcmodel_medany.objdump
-
-clean:
-	rm mcmodel_*
diff --git a/examples/C/mcmodel/mcmodel.c b/examples/C/mcmodel/mcmodel.c
deleted file mode 100644
index f44981184..000000000
--- a/examples/C/mcmodel/mcmodel.c
+++ /dev/null
@@ -1,10 +0,0 @@
-// mcmodel.c
-// Demonstrate different code generation with mcmodel = medany vs. medlow
-
-long a;
-long b[2000];
-
-int main(void)
-{
-    return a + b[1000];
-}
\ No newline at end of file
diff --git a/examples/C/sum/Makefile b/examples/C/sum/Makefile
index a302309ff..7c21cce23 100644
--- a/examples/C/sum/Makefile
+++ b/examples/C/sum/Makefile
@@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
 	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \
diff --git a/examples/C/sum_mixed/sum_mixed b/examples/C/sum_mixed/sum_mixed
new file mode 100755
index 000000000..62ac4022a
Binary files /dev/null and b/examples/C/sum_mixed/sum_mixed differ
diff --git a/examples/asm/etc/Makefile b/examples/asm/etc/Makefile
deleted file mode 100644
index 72f99e975..000000000
--- a/examples/asm/etc/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-TARGET = pause
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump
-    
-pause: pause.S Makefile
-	riscv64-unknown-elf-gcc -o pause -march=rv32ia_zihintpause -mabi=ilp32 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld  pause.S
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/asm/etc/pause.S b/examples/asm/etc/pause.S
deleted file mode 100644
index 4e0aacfb4..000000000
--- a/examples/asm/etc/pause.S
+++ /dev/null
@@ -1,25 +0,0 @@
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-
-
-la a0, lock
-
-spinlock:				# address of lock is in a0
-	lr.w t0, (a0)		# read the lock
-	bnez t0, retry	    # spin until free
-	li   t1, 1          
-	sc.w t0, t1, (a0)	# try to write a 1 to take lock
-	bnez t0, retry	    # spin until successful
-	ret				    # got the lock!
-retry:				    # no lock yet
-	pause				# pause hint to reduce spin power
-	j spinlock			# try again
-
-
-self_loop:
-    j self_loop
-
-.data
-lock:   
-    .word 1
\ No newline at end of file
diff --git a/examples/asm/trap/trap b/examples/asm/trap/trap
new file mode 100755
index 000000000..1d7d3bbc6
Binary files /dev/null and b/examples/asm/trap/trap differ
diff --git a/examples/crypto/aes/Makefile b/examples/crypto/aes/Makefile
deleted file mode 100644
index 54ac33052..000000000
--- a/examples/crypto/aes/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-CC = gcc
-CFLAGS = -g
-
-all: aes
-
-aes:	aes.c
-	$(CC) $(CFLAGS) aes.c -o aes
-
-clean:
-	rm -rf aes
-	rm -f *~
-
-.PHONY: all clean
diff --git a/examples/crypto/aes/aes.c b/examples/crypto/aes/aes.c
deleted file mode 100644
index 6744169b3..000000000
--- a/examples/crypto/aes/aes.c
+++ /dev/null
@@ -1,641 +0,0 @@
-//
-// aes.c 
-// Modified based on ideas from https://github.com/m3y54m/aes-in-c.git and FIPS 197
-// james.stine@okstate.edu 11 October 2024
-//
-
-#include <stdio.h>  
-#include <stdlib.h> 
-
-enum errorCode {
-    SUCCESS = 0,
-    ERROR_AES_UNKNOWN_KEYSIZE,
-    ERROR_MEMORY_ALLOCATION_FAILED,
-};
-
-// Implementation: S-Box (page 14 FIPS 197 Table 4)
-unsigned char sbox[256] = {
-  // 0     1    2      3     4    5     6     7      8    9     A      B    C     D     E     F
-  0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,  // 0
-  0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,  // 1
-  0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,  // 2
-  0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,  // 3
-  0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,  // 4
-  0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,  // 5
-  0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,  // 6
-  0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,  // 7
-  0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,  // 8
-  0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,  // 9
-  0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,  // A
-  0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,  // B
-  0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,  // C
-  0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,  // D
-  0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,  // E
-  0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16}; // F
-
-// inverse S-box used in the InvSubBytes() (page 23 FIPS 197 Table 6)
-unsigned char rsbox[256] =
-  // 0     1    2      3     4    5     6     7      8    9     A      B    C     D     E     F  
-  {0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,  // 0
-   0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,  // 1
-   0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,  // 2
-   0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,  // 3
-   0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,  // 4
-   0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,  // 5
-   0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,  // 6
-   0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,  // 7
-   0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,  // 8
-   0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,  // 9
-   0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,  // A
-   0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,  // B
-   0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,  // C
-   0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,  // D
-   0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,  // E
-   0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d}; // F
-
-// Implementation: Rcon (Round constants) - help introduce non-linearity and prevent symmetries
-// Rcon[i] = 0x02^(i-1) mod x^8 + x^4 + x^3 + x + 1
-unsigned char Rcon[255] = {
-  0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8,
-  0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3,
-  0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f,
-  0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d,
-  0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab,
-  0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d,
-  0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25,
-  0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01,
-  0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d,
-  0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa,
-  0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a,
-  0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02,
-  0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a,
-  0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef,
-  0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94,
-  0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04,
-  0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f,
-  0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5,
-  0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33,
-  0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb};
-
-unsigned char getRconValue(unsigned char num);
-
-// Implementation: Key Expansion
-enum keySize {
-  SIZE_16 = 16,
-  SIZE_24 = 24,
-  SIZE_32 = 32
-};
-
-// AES Encryption Function Prototypes
-void subBytes(unsigned char *state);
-void shiftRows(unsigned char *state);
-void shiftRow(unsigned char *state, unsigned char nbr);
-void addRoundKey(unsigned char *state, unsigned char *roundKey);
-unsigned char galois_multiplication(unsigned char a, unsigned char b);
-void mixColumns(unsigned char *state);
-void mixColumn(unsigned char *column);
-void aes_cipher(unsigned char *state, unsigned char *roundKey);
-void createRoundKey(unsigned char *expandedKey, unsigned char *roundKey);
-void aes_main(unsigned char *state, unsigned char *expandedKey, int nbrRounds);
-char aes_encrypt(unsigned char *input, unsigned char *output, unsigned char *key, enum keySize size);
-// AES Decryption Function Prototypes
-void invSubBytes(unsigned char *state);
-void invShiftRows(unsigned char *state);
-void invShiftRow(unsigned char *state, unsigned char nbr);
-void invMixColumns(unsigned char *state);
-void invMixColumn(unsigned char *column);
-void aes_invRound(unsigned char *state, unsigned char *roundKey);
-void aes_invCipher(unsigned char *state, unsigned char *expandedKey, int nbrRounds);
-char aes_decrypt(unsigned char *input, unsigned char *output, unsigned char *key, enum keySize size);
-
-// Helper function to print AES state
-void printState(const unsigned char *state) {
-  for (int col = 0; col < 4; col++) {
-    printf("%02x %02x %02x %02x ",
-           state[col], state[col + 4], state[col + 8], state[col + 12]);
-  }
-  printf("\n");
-}
-
-unsigned char getSBoxValue(unsigned char num) {
-  return sbox[num];
-}
-
-unsigned char getSBoxInvert(unsigned char num) {
-  return rsbox[num];
-}
-
-// left circular rotation (i.e., byte-wise rotate left) on a 4-byte word
-void rotate(unsigned char *word) {
-  unsigned char temp = word[0];
-  word[0] = word[1];
-  word[1] = word[2];
-  word[2] = word[3];
-  word[3] = temp;
-}
-
-unsigned char getRconValue(unsigned char num) {  
-  return Rcon[num];
-}
-
-void KeySchedule(unsigned char *word, int iteration) {
-  int i;
-
-  // Key Schedule: RotWord → SubWord → XOR with Rcon
-  // used during key expansion to transform the input word before XORing it with a
-  // word from earlier in the expanded key array.
-  
-  // rotate the 32-bit word 8 bits to the left
-  rotate(word);
-  // apply S-Box substitution on all 4 parts of the 32-bit word
-  for (i = 0; i < 4; ++i) {
-    word[i] = getSBoxValue(word[i]);
-  }
-  // XOR the output of the rcon operation with i to the first part (leftmost) only
-  word[0] = word[0] ^ getRconValue(iteration);
-}
-
-// Rijndael's key expansion:  expands an 128, 192, 256 key into an 176, 208, 240 bytes key 
-void KeyExpansion(unsigned char *expandedKey, unsigned char *key,
-		  enum keySize size, size_t expandedKeySize) {
-  
-  // current expanded keySize, in bytes
-  int currentSize = 0;
-  int rconIteration = 1;
-  int i;
-  unsigned char t[4] = {0}; // temporary 4-byte variable
-
-  // set the 16, 24,32 bytes of the expanded key to the input key
-  for (i = 0; i < size; i++)
-    expandedKey[i] = key[i];
-  currentSize += size;
-  while (currentSize < expandedKeySize) {
-    // assign the previous 4 bytes to the temporary value t
-    for (i = 0; i < 4; i++) {
-      t[i] = expandedKey[(currentSize - 4) + i];
-    }    
-    // every 16, 24, 32 bytes we apply the core schedule to t
-    // and increment rconIteration afterwards
-    if (currentSize % size == 0) {
-      KeySchedule(t, rconIteration++);
-    }    
-    // For 256-bit keys, we add an extra sbox to the calculation
-    if (size == SIZE_32 && ((currentSize % size) == 16)) {
-      for (i = 0; i < 4; i++)
-	t[i] = getSBoxValue(t[i]);
-    }
-    
-    // We XOR t with the four-byte block 16, 24, 32 bytes before the new expanded key.
-    // This becomes the next four bytes in the expanded key.
-    for (i = 0; i < 4; i++) {
-      expandedKey[currentSize] = expandedKey[currentSize - size] ^ t[i];
-      currentSize++;
-    }
-  }
-}
-
-void subBytes(unsigned char *state) {
-  for (int i = 0; i < 16; i++) {
-    state[i] = getSBoxValue(state[i]);
-  }
-}
-
-void shiftRows(unsigned char *state) {
-  for (int row = 0; row < 4; row++) {
-    shiftRow(state + row * 4, row);
-  }
-}
-
-void shiftRow(unsigned char *state, unsigned char nbr) {
-  unsigned char temp[4];
-
-  // Perform rotation directly
-  for (int i = 0; i < 4; i++) {
-    temp[i] = state[(i + nbr) % 4];
-  }
-
-  // Copy result back to state
-  for (int i = 0; i < 4; i++) {
-    state[i] = temp[i];
-  }
-}
-
-void addRoundKey(unsigned char *state, unsigned char *roundKey) {
-  int i;
-  for (i = 0; i < 16; i++)
-    state[i] = state[i] ^ roundKey[i];
-}
-
-// Based on work by Tom St. Denis/Simon Johnson
-// https://www.amazon.com/Cryptography-Developers-Tom-St-Denis/dp/1597491047
-unsigned char gfmul(unsigned char a, unsigned char b) {
-  unsigned char p = 0;
-  for (unsigned char counter = 0; counter < 8; counter++) {
-    if (b & 1)
-      p ^= a;
-    a = (a << 1) ^ ((a & 0x80) ? 0x1b : 0);
-    b >>= 1;
-  }
-  return p;
-}
-
-// Section 5.1.3 of FIPS 197
-void mixColumns(unsigned char *state) {
-  unsigned char column[4];
-
-  for (int col = 0; col < 4; col++) {
-    // Extract the column from the state
-    for (int row = 0; row < 4; row++) {
-      column[row] = state[row * 4 + col];
-    }
-
-    // Mix the column
-    mixColumn(column);
-
-    // Store the mixed column back into the state
-    for (int row = 0; row < 4; row++) {
-      state[row * 4 + col] = column[row];
-    }
-  }
-}
-
-void mixColumn(unsigned char *column) {
-  unsigned char a[4], b[4];
-
-  for (int i = 0; i < 4; i++) {
-    a[i] = column[i];
-    b[i] = gfmul(column[i], 2);
-  }
-
-  column[0] = b[0] ^ a[3] ^ a[2] ^ gfmul(a[1], 3);
-  column[1] = b[1] ^ a[0] ^ a[3] ^ gfmul(a[2], 3);
-  column[2] = b[2] ^ a[1] ^ a[0] ^ gfmul(a[3], 3);
-  column[3] = b[3] ^ a[2] ^ a[1] ^ gfmul(a[0], 3);
-}
-
-// The rounds in the specifcation of CIPHER() are composed of the following 4 byte-oriented
-// transformations on the state (Section 5.1 of FIPS 197) - outputs hex after each step
-void aes_cipher(unsigned char *state, unsigned char *roundKey) {
-  subBytes(state);
-  printState(state);
-
-  shiftRows(state);
-  printState(state);
-
-  mixColumns(state);
-  printState(state);
-
-  addRoundKey(state, roundKey);
-  printf("\n");  // Optional: for spacing
-}
-
-void createRoundKey(unsigned char *expandedKey, unsigned char *roundKey) {
-  int i, j;
-  // iterate over the columns
-  for (i = 0; i < 4; i++) {
-    // iterate over the rows
-    for (j = 0; j < 4; j++)
-      roundKey[(i + (j * 4))] = expandedKey[(i * 4) + j];
-  }
-}
-
-
-void aes_main(unsigned char *state, unsigned char *expandedKey, int nbrRounds) {
-  unsigned char roundKey[16];
-
-  // Initial round key
-  createRoundKey(expandedKey, roundKey);
-  printState(state);
-  printf("\n");
-
-  addRoundKey(state, roundKey);
-
-  for (int i = 1; i < nbrRounds; i++) {
-    createRoundKey(expandedKey + 16 * i, roundKey);
-    printState(state);
-    aes_cipher(state, roundKey);  // includes printState calls inside if in debug mode
-  }
-
-  // Final round (no MixColumns)
-  printState(state);
-  createRoundKey(expandedKey + 16 * nbrRounds, roundKey);
-
-  subBytes(state);
-  printState(state);
-
-  shiftRows(state);
-  printState(state);
-
-  addRoundKey(state, roundKey);
-  printState(state);
-}
-
-char aes_encrypt(unsigned char *input, unsigned char *output,
-                 unsigned char *key, enum keySize size) {
-  int nbrRounds;
-  int expandedKeySize;
-  unsigned char block[16];
-  unsigned char *expandedKey = NULL;
-
-  // Determine number of rounds based on key size
-  switch (size) {
-    case SIZE_16: nbrRounds = 10; break;
-    case SIZE_24: nbrRounds = 12; break;
-    case SIZE_32: nbrRounds = 14; break;
-    default: return ERROR_AES_UNKNOWN_KEYSIZE;
-  }
-
-  expandedKeySize = 16 * (nbrRounds + 1);
-
-  expandedKey = (unsigned char *)malloc(expandedKeySize);
-  if (expandedKey == NULL) {
-    return ERROR_MEMORY_ALLOCATION_FAILED;
-  }
-
-  // Map input (row-major to column-major for AES)
-  for (int row = 0; row < 4; row++) {
-    for (int col = 0; col < 4; col++) {
-      block[row + 4 * col] = input[4 * row + col];
-    }
-  }
-
-  // Expand the key
-  KeyExpansion(expandedKey, key, size, expandedKeySize);
-
-  // Encrypt the block
-  aes_main(block, expandedKey, nbrRounds);
-
-  // Map block back to output (column-major to row-major)
-  for (int row = 0; row < 4; row++) {
-    for (int col = 0; col < 4; col++) {
-      output[4 * row + col] = block[row + 4 * col];
-    }
-  }
-
-  // de-allocate memory for expandedKey  
-  free(expandedKey);
-  return SUCCESS;
-}
-
-void invSubBytes(unsigned char *state) {
-  for (int i = 0; i < 16; i++) {
-    state[i] = getSBoxInvert(state[i]);
-  }
-}
-
-void invShiftRows(unsigned char *state) {
-  for (int row = 0; row < 4; row++) {
-    invShiftRow(state + row * 4, row);
-  }
-}
-
-void invShiftRow(unsigned char *state, unsigned char nbr) {
-  unsigned char temp[4];
-
-  // Perform rotation to the right by `nbr` positions
-  for (int i = 0; i < 4; i++) {
-    temp[i] = state[(i - nbr + 4) % 4];
-  }
-
-  // Copy back the rotated values
-  for (int i = 0; i < 4; i++) {
-    state[i] = temp[i];
-  }
-}
-
-void invMixColumns(unsigned char *state) {
-  unsigned char column[4];
-
-  for (int col = 0; col < 4; col++) {
-    // Extract one column (4 bytes from each row)
-    for (int row = 0; row < 4; row++) {
-      column[row] = state[row * 4 + col];
-    }
-
-    // Apply inverse MixColumn transformation
-    invMixColumn(column);
-
-    // Store transformed column back into the state
-    for (int row = 0; row < 4; row++) {
-      state[row * 4 + col] = column[row];
-    }
-  }
-}
-
-void invMixColumn(unsigned char *column) {
-  unsigned char a[4];
-
-  for (int i = 0; i < 4; i++)
-    a[i] = column[i];
-
-  unsigned char a0_14 = gfmul(a[0], 14);
-  unsigned char a1_11 = gfmul(a[1], 11);
-  unsigned char a2_13 = gfmul(a[2], 13);
-  unsigned char a3_9  = gfmul(a[3],  9);
-
-  unsigned char a0_9  = gfmul(a[0],  9);
-  unsigned char a1_14 = gfmul(a[1], 14);
-  unsigned char a2_11 = gfmul(a[2], 11);
-  unsigned char a3_13 = gfmul(a[3], 13);
-
-  unsigned char a0_13 = gfmul(a[0], 13);
-  unsigned char a1_9  = gfmul(a[1],  9);
-  unsigned char a2_14 = gfmul(a[2], 14);
-  unsigned char a3_11 = gfmul(a[3], 11);
-
-  unsigned char a0_11 = gfmul(a[0], 11);
-  unsigned char a1_13 = gfmul(a[1], 13);
-  unsigned char a2_9  = gfmul(a[2],  9);
-  unsigned char a3_14 = gfmul(a[3], 14);
-
-  column[0] = a0_14 ^ a1_11 ^ a2_13 ^ a3_9;
-  column[1] = a0_9  ^ a1_14 ^ a2_11 ^ a3_13;
-  column[2] = a0_13 ^ a1_9  ^ a2_14 ^ a3_11;
-  column[3] = a0_11 ^ a1_13 ^ a2_9  ^ a3_14;
-}
-
-void aes_invRound(unsigned char *state, unsigned char *roundKey) {
-
-  invShiftRows(state);
-  invSubBytes(state);
-  addRoundKey(state, roundKey);
-  invMixColumns(state);
-}
-
-void aes_invCipher(unsigned char *state, unsigned char *expandedKey, int nbrRounds) {
-  unsigned char roundKey[16];
-
-  // Initial round key for final round
-  createRoundKey(expandedKey + 16 * nbrRounds, roundKey);
-  addRoundKey(state, roundKey);
-
-  // Inverse rounds (excluding final round)
-  for (int round = nbrRounds - 1; round > 0; round--) {
-    createRoundKey(expandedKey + 16 * round, roundKey);
-    aes_invRound(state, roundKey);
-  }
-
-  // Final inverse round (no invMixColumns)
-  createRoundKey(expandedKey, roundKey);
-  invShiftRows(state);
-  invSubBytes(state);
-  addRoundKey(state, roundKey);
-}
-
-char aes_decrypt(unsigned char *input, unsigned char *output,
-                 unsigned char *key, enum keySize size) {
-  int nbrRounds;
-  int expandedKeySize;
-  unsigned char block[16];
-  unsigned char *expandedKey = NULL;
-
-  // Determine the number of rounds based on key size
-  switch (size) {
-    case SIZE_16: nbrRounds = 10; break;
-    case SIZE_24: nbrRounds = 12; break;
-    case SIZE_32: nbrRounds = 14; break;
-    default: return ERROR_AES_UNKNOWN_KEYSIZE;
-  }
-
-  expandedKeySize = 16 * (nbrRounds + 1);
-
-  expandedKey = (unsigned char *)malloc(expandedKeySize);
-  if (expandedKey == NULL) {
-    return ERROR_MEMORY_ALLOCATION_FAILED;
-  }
-
-  // Transpose input (column-major block for AES)
-  for (int row = 0; row < 4; row++) {
-    for (int col = 0; col < 4; col++) {
-      block[row + 4 * col] = input[4 * row + col];
-    }
-  }
-
-  // Key expansion
-  KeyExpansion(expandedKey, key, size, expandedKeySize);
-
-  // Decrypt
-  aes_invCipher(block, expandedKey, nbrRounds);
-
-  // Transpose back into output (row-major)
-  for (int row = 0; row < 4; row++) {
-    for (int col = 0; col < 4; col++) {
-      output[4 * row + col] = block[row + 4 * col];
-    }
-  }
-
-  // de-allocate memory for expandedKey  
-  free(expandedKey);
-  return SUCCESS;
-}
-
-int main(int argc, char *argv[]) {
-
-  // Rounds: Number of AES rounds
-  // Words/Key: Number of 32-bit words per round key (Nb = 4 for AES)
-  // Round Keys: Total words in expanded key = Nb × (Rounds + 1)
-  // KeyExp (B): Key expansion size in bytes = Round Keys × 4
-  // Block (B): Block size in bytes = 128 bits / 8 = 16
-  
-  //+-----------+ Block Size | Rounds | Words/Key | Round Keys | KeyExp (B) | Block (B) |
-  //|-----------|------------|--------|-----------|------------|------------|-----------|
-  //| AES-128   | 128 bits   | 10     | 4         | 44         | 176        | 16        |
-  //| AES-192   | 128 bits   | 12     | 4         | 52         | 208        | 16        |
-  //| AES-256   | 128 bits   | 14     | 4         | 60         | 240        | 16        |
-  //+-----------+------------+--------+-----------+------------+------------+-----------+
-  
-  // the expanded keySize to store full set of round keys
-  int expandedKeySize = 240;
-  unsigned char expandedKey[expandedKeySize];
-
-  // the cipher key (FIPS 197 example (page 28) 128-bit Cipher Key in Appendix A)
-  //unsigned char key[16] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6,
-  //                         0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c};
-  // (FIPS 197 example (page 34) in Appendix B)
-
-  // AES uses an internal structure called the state, which is a 4x4 byte matrix (16 bytes total).
-  // AES operates on 128-bit blocks (16 bytes), always — regardless of key size (128, 192, 256).
-  //unsigned char plaintext[16] = {0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d,
-  //                               0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34};
-  
-  // the cipher key size defined on Line 86
-  enum keySize size = SIZE_32;
-
-  // These examples are in Appendix C of FIPS 197 starting on page 35 (2001 version)
-  // AES 128-bit key and plaintext input
-  unsigned char key[16] = {
-    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-    0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
-  };
-  
-  unsigned char plaintext[16] = {
-    0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-    0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-  };
-
-  // AES-192 key and plaintext input 
-  unsigned char key192[24] = {
-    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-    0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17
-  };
-  
-  unsigned char plaintext192[16] = {
-    0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-    0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-  };
-  
-  // AES-256 key and plaintext input
-  unsigned char key256[32] = {
-    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-    0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-    0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
-  };
-  
-  unsigned char plaintext256[16] = {
-    0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-    0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-  };
-
-  // the ciphertext
-  unsigned char ciphertext[16];
-  // the decrypted text
-  unsigned char decryptedtext[16];
-  int i;
-
-  printf("Implementation of the AES algorithm in C\n");
-  printf("\nCipher Key (hex format):\n");
-  for (i = 0; i < 16; i++) {
-    // Print characters in hex format, 16 chars per line
-    printf("%2.2x%c", key[i], ((i + 1) % 16) ? ' ' : '\n');
-  }
-
-  // Test the Key Expansion
-  KeyExpansion(expandedKey, key, size, expandedKeySize);
-  printf("\nExpanded Key (hex format):\n");
-  for (i = 0; i < expandedKeySize; i++) {
-    printf("%2.2x%c", expandedKey[i], ((i + 1) % 16) ? ' ' : '\n');
-  }  
-  
-  printf("\nPlaintext (hex format):\n");
-  for (i = 0; i < 16; i++) {
-    printf("%2.2x%c", plaintext[i], ((i + 1) % 16) ? ' ' : '\n');
-  }
-
-  // AES Encryption
-  aes_encrypt(plaintext, ciphertext, key, SIZE_32);  
-  printf("\nCiphertext (hex format):\n");
-  for (i = 0; i < 16; i++) {
-      printf("%02x%c", ciphertext[i], ((i + 1) % 16) ? ' ' : '\n');
-    }
-    
-  // AES Decryption
-  aes_decrypt(ciphertext, decryptedtext, key, SIZE_32);
-  printf("\nDecrypted text (hex format):\n");
-  for (i = 0; i < 16; i++) {
-      printf("%2.2x%c", decryptedtext[i], ((i + 1) % 16) ? ' ' : '\n');
-    }
-
-  return 0;
-}
diff --git a/examples/crypto/eea/gf_inverse.py b/examples/crypto/eea/gf_inverse.py
deleted file mode 100644
index 65c6392d4..000000000
--- a/examples/crypto/eea/gf_inverse.py
+++ /dev/null
@@ -1,79 +0,0 @@
-# gf_inverse.py
-# Extended Euclidean Algorithm
-# james.stine@okstate.edu 8 April 2025
-
-def gf_mul(a, b, modulus):
-    result = 0
-    while b:
-        if b & 1:
-            result ^= a
-        b >>= 1
-        a <<= 1
-        if a & (1 << 8):
-            a ^= modulus
-    return result & 0xFF
-
-def gf_mul_poly(a, b):
-    result = 0
-    while b:
-        if b & 1:
-            result ^= a
-        a <<= 1
-        b >>= 1
-    return result
-
-def gf_divmod(a, b):
-    if b == 0:
-        raise ZeroDivisionError()
-    deg_a = a.bit_length() - 1
-    deg_b = b.bit_length() - 1
-    quotient = 0
-    while deg_a >= deg_b:
-        shift = deg_a - deg_b
-        quotient ^= 1 << shift
-        a ^= b << shift
-        deg_a = a.bit_length() - 1
-    return quotient, a
-
-def gf_inverse(a, modulus):
-    if a == 0:
-        raise ValueError("No inverse for 0 in GF(2^n)")
-
-    r0, r1 = modulus, a
-    s0, s1 = 0, 1
-    loop_count = 0
-
-    print(f"{'Loop':<5} {'r0':>6} {'r1':>6} {'q':>6} {'s0':>6} {'s1':>6}")
-
-    while r1 != 0:
-        q, _ = gf_divmod(r0, r1)
-        new_r = r0 ^ gf_mul_poly(q, r1)
-        new_s = s0 ^ gf_mul_poly(q, s1)
-
-        print(f"{loop_count:<5} {r0:06X} {r1:06X} {q:06X} {s0:06X} {s1:06X}")
-
-        r0, r1 = r1, new_r
-        s0, s1 = s1, new_s
-        loop_count += 1
-
-    print(f"{loop_count:<5} {r0:06X} {' '*6} {' '*6} {s0:06X}")
-
-    if r0 != 1:
-        raise ValueError(f"No inverse for {a:#02x} mod {modulus:#04x}")
-
-    return s0 & 0xFF
-
-# Example usage
-if __name__ == "__main__":
-    import sys
-    if len(sys.argv) != 3:
-        print("Usage: python gf_inverse.py <value> <modulus>")
-        print("Example: python gf_inverse.py 0x53 0x11B")
-        sys.exit(1)
-
-    value = int(sys.argv[1], 0)
-    modulus = int(sys.argv[2], 0)
-
-    inv = gf_inverse(value, modulus)
-    print(f"\nMultiplicative inverse of {value:#02x} in GF(2^8) mod {modulus:#04x} is {inv:#02x}")
-    assert gf_mul(value, inv, modulus) == 1, "Verification failed!"
diff --git a/examples/crypto/gfmul/Makefile b/examples/crypto/gfmul/Makefile
deleted file mode 100644
index a501c3775..000000000
--- a/examples/crypto/gfmul/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# Makefile
-
-CC     = gcc
-CFLAGS = -O3
-LIBS   = 
-SRCS   = $(wildcard *.c)
-
-PROGS = $(patsubst %.c,%,$(SRCS))
-
-all:	$(PROGS)
-
-%: %.c
-	$(CC) $(CFLAGS) $(IFLAGS) -o $@ $< $(LIBS)
-
-clean: 
-	rm -f $(PROGS)
diff --git a/examples/crypto/gfmul/gfmul.c b/examples/crypto/gfmul/gfmul.c
deleted file mode 100644
index 3c4f585f1..000000000
--- a/examples/crypto/gfmul/gfmul.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// gfmul.c - Galois Field multiplication
-// James Stine and David Harris 16 May 2024
-
-#include <stdio.h>
-
-/* return ab mod m(x) - long multiplication in GF(2^n) with polynomial m */
-int gfmul(int a, int b, int n, int m) {
-   int result = 0;
-   while (b) {
-     if (b & 1) result = result ^ a; /* if bit of b is set add a */
-     a = a << 1;                     /* multiply a by x */
-     if (a & 1 << n)
-       a = a ^ m;                    /* reduce/sub modulo AES m(x) = 100011011 */
-     //printf("a = %x, b = %x, result = %x\n", a, b, result);
-     b = b >> 1;                     /* get next bit of b */
-   }
-   return result;
-}
-
-void inverses(void) {
-    int i, j, k, num;
-
-    printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
-    for (i=0; i<16; i++) {
-        for (j=0; j<16; j++) {
-            num = i*16+j;
-            if (num ==0) printf ("00 ");
-            else for (k=1; k<256; k++) {
-                if (gfmul(num, k, 8, 0b100011011) == 1) {
-                    printf("%02x ", k);
-                    break;
-                }
-            }
-        }
-        printf("\n");
-    }
-}
-
-void inverses3(void) {
-    int k, num;
-
-    printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
-    for (num=0; num<8; num++) {
-        if (num == 0) printf ("0 ");
-        else for (k=1; k<8; k++) {
-            if (gfmul(num, k, 3, 0b1011) == 1) {
-                printf("%d ", k);
-                break;
-            }
-        }
-    }
-    printf("\n");
-}
-
-
-int main() {
-  int a = 0xC5;
-  int b = 0xA1;
-
-  printf("The GF(2^8) result is %x\n", gfmul(a,b, 8, 0b100011011));
-  printf("The GF(2^8) result is %x\n", gfmul(0xC1, 0x28, 8, 0b100011011));
-  inverses();
-
-  // tabulate inverses for GF(2^3)
-  inverses3();
-  // check worked examples
-    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
-    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b010, 3, 0b1011));
-    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b100, 3, 0b1011));
-    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
- 
-}
diff --git a/examples/exercises/16p1/antimul.sh b/examples/exercises/16p1/antimul.sh
deleted file mode 100755
index d6ea108e8..000000000
--- a/examples/exercises/16p1/antimul.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-sed -i 's/assign MFunctD.*/assign MFunctD = 0; \/\/ *** Replace with your logic/' $WALLY/src/ieu/controller.sv
-sed -i 's/ControlsD.*Divide/assign ControlsD = 0; \/\/ *** Replace with your logic/' $WALLY/src/ieu/controller.sv
-sed -zi 's/\/\/ Number systems.*logic/  logic/' $WALLY/src/mdu/mul.sv
-sed -zi 's/assign Aprime.*Memory/\/\/ Memory/' $WALLY/src/mdu/mul.sv
diff --git a/examples/exercises/17p1/17p1.c b/examples/exercises/17p1/17p1.c
deleted file mode 100644
index 719407483..000000000
--- a/examples/exercises/17p1/17p1.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <string.h>
-
-int main(void) {
-    char str[] = "Hello Wally!";
-    return strlen(str);
-}
diff --git a/examples/exercises/17p1/Makefile b/examples/exercises/17p1/Makefile
deleted file mode 100644
index dc50ce2fa..000000000
--- a/examples/exercises/17p1/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-TARGET = 17p1
-
-$(TARGET).objdump: $(TARGET).elf
-	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
-    
-$(TARGET).elf: $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc_zbb -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).c -o $(TARGET).elf
-
-clean:
-	rm -f $(TARGET).elf $(TARGET).objdump
diff --git a/examples/exercises/18p5/Makefile b/examples/exercises/18p5/Makefile
deleted file mode 100644
index fc3c3c04e..000000000
--- a/examples/exercises/18p5/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-TARGET = gf_inv
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -Dls $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).S Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32gc -mabi=ilp32 -mcmodel=medany \
-	    -nostartfiles -nostdlib -T../../link/link.ld $(TARGET).S
-
-sim:
-	spike --isa=rv32gc_zicsr_zicntr +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET)
-	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
-	echo "Signature matches! Success!"
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump $(TARGET).signature.output
-	rm -f *~
-
-
-
-
diff --git a/examples/exercises/18p5/README.md b/examples/exercises/18p5/README.md
deleted file mode 100644
index 4d958ceb6..000000000
--- a/examples/exercises/18p5/README.md
+++ /dev/null
@@ -1,83 +0,0 @@
-Extended Euclidean Algorithm
-
-EEA Cycle Estimates
-
-Main loop body: 25 (N times)
-swap_and_negate: 22 (S times)
-gf_degree: 10 (twice per loop)
-Number of Loops: N
-
-\ext{Total Cycles} = N \times (25 + 2 \times 10) + S \times 22
-
-Pseuo-Code
-
-r0 := m
-r1 := a
-s0 := 0
-s1 := 1
-
-while r1 \neq 0:
-    deg_r0 = degree(r0)
-    deg_r1 = degree(r1)
-    shift = deg_r0 - deg_r1
-
-    if shift < 0:
-        swap(r0, r1)
-        swap(s0, s1)
-        shift := -shift
-
-    r0 = r0 ^ (r1 << shift)
-    s0 = s0 ^ (s1 << shift)
-
-if r0 \neq 1:
-    return "No inverse"
-else:
-    return s0
-
-
-LaTeX
-------
-\documentclass{article}
-\usepackage{algorithm}
-\usepackage{algpseudocode}
-\usepackage{amsmath}
-
-\begin{document}
-
-\begin{algorithm}
-\caption{Extended Euclidean Algorithm in GF(2\textsuperscript{8})}
-\begin{algorithmic}[1]
-\Require Input value $a$, modulus $m$ (usually $0x11B$)
-\Ensure Return $s_0$ such that $s_0 \cdot a \equiv 1 \pmod{m}$ if inverse exists
-
-\State $r_0 \gets m$
-\State $r_1 \gets a$
-\State $s_0 \gets 0$
-\State $s_1 \gets 1$
-
-\While{$r_1 \ne 0$}
-    \State $d_0 \gets \text{deg}(r_0)$
-    \State $d_1 \gets \text{deg}(r_1)$
-    \State $\text{shift} \gets d_0 - d_1$
-    
-    \If{$\text{shift} < 0$}
-        \State Swap $r_0 \leftrightarrow r_1$
-        \State Swap $s_0 \leftrightarrow s_1$
-        \State $\text{shift} \gets -\text{shift}$
-    \EndIf
-    
-    \State $r_0 \gets r_0 \oplus (r_1 \ll \text{shift})$
-    \State $s_0 \gets s_0 \oplus (s_1 \ll \text{shift})$
-    
-    \State Mask $r_0$ and $s_0$ to 9 bits: $r_0 \gets r_0 \mathbin{\&} 0x1FF$, $s_0 \gets s_0 \mathbin{\&} 0x1FF$
-\EndWhile
-
-\If{$r_0 = 1$}
-    \State \Return $s_0$ \Comment{Inverse found}
-\Else
-    \State \Return \textbf{error} \Comment{No inverse exists}
-\EndIf
-\end{algorithmic}
-\end{algorithm}
-
-\end{document}
diff --git a/examples/exercises/18p5/gf_inv.S b/examples/exercises/18p5/gf_inv.S
deleted file mode 100644
index bb8eb822d..000000000
--- a/examples/exercises/18p5/gf_inv.S
+++ /dev/null
@@ -1,182 +0,0 @@
-// gf_inv.S
-// james.stine@okstate.edu 9 April 2025
-	
-.text
-	
-.global rvtest_entry_point
-rvtest_entry_point:
-	
-    li a0, 0x32        # Input value to invert in GF(2^8)
-    li t0, 0x11B       # Modulus: irreducible poly x^8 + x^4 + x^3 + x + 1
-
-    # Initialize Extended Euclidean variables: a*x+b*y=gcd(a,b)
-    li t1, 0           # s0 = 0 (old x)
-    li t2, 1           # s1 = 1 (new x)
-    mv t3, t0          # r0 = modulus
-    mv t4, a0          # r1 = input value
-
-    csrr s8, instret   # count instructions at beginning
-
-    # --- Register usage ---
-    # a0: Input / Final result (return value)
-    # t0: Modulus (0x11B)
-    # t1: s0 (previous x value)
-    # t2: s1 (current x value)
-    # t3: r0 (previous remainder)
-    # t4: r1 (current remainder)
-    # t5: degree(r0)
-    # t6: degree(r1)
-    # a1: argument to gf_degree
-    # a2: shift amount
-    # a3: temporary for SLT result
-    # a4/a5: shift results, temporaries
-    # s8: initial seed of instruction count (instret)
-    # s9: final value of instruction count (instret)	
-	
-# --------------------------------------
-# Main loop: Extended Euclidean Division
-# --------------------------------------
-inv_loop:
-    beqz t4, fail          	# If r1 == 0, input is not invertible → fail
-
-    # Compute degree of r0
-    mv a1, t3              	# Set a1 = r0 = (modulus m)
-    call gf_degree         	# Compute deg(r0)
-    mv t5, a0			# degree(r0)
-
-    # Compute degree of r1
-    mv a1, t4              	# Set a1 = r1 = (input a)
-    call gf_degree         	# Compute deg(r1)
-    mv t6, a0			# degree (r1)
-
-    # Compute shift = deg(r0) - deg(r1)
-    sub a2, t5, t6		# alignment r1 with highest term in r0
-    slt a3, a2, zero       	# Check if shift < 0
-    bnez a3, swap_and_negate
-
-    # Perform r0 ^= r1 << shift 
-    # Polynomial subtraction in GF(2)
-    sll a4, t4, a2
-    xor t3, t3, a4
-    andi t3, t3, 0x1FF     	# Mask off 9 bits to stay in GF(2^8)
-
-    # Update s0: s0 ^= s1 << shift - Update Bezout coefficient
-    sll a5, t2, a2		
-    xor t1, t1, a5
-    andi t1, t1, 0x1FF		# Mask off 9 bits to stay in GF(2^8)
-
-    # Swap (r0, r1)
-    mv a4, t3
-    mv t3, t4
-    mv t4, a4
-
-    # Swap (s0, s1)
-    mv a4, t1
-    mv t1, t2
-    mv t2, a4
-
-    # Check if r0 == 1, then we are done
-    li t5, 1
-    beq t3, t5, done
-
-    j inv_loop
-
-# -------------------------------------------
-# Case: shift < 0 → negate, then apply shift
-# -------------------------------------------
-swap_and_negate:
-    # Swap r0 <-> r1
-    mv a4, t3
-    mv t3, t4
-    mv t4, a4
-
-    # Swap s0 <-> s1
-    mv a4, t1
-    mv t1, t2
-    mv t2, a4
-
-    # shift = -shift
-    sub a2, zero, a2
-
-    # r0 ^= r1 << shift
-    sll a4, t4, a2
-    xor t3, t3, a4
-    andi t3, t3, 0x1FF		# Mask off to 9 bits again
-
-    # s0 ^= s1 << shift
-    sll a5, t2, a2
-    xor t1, t1, a5
-    andi t1, t1, 0x1FF
-
-    # Final swap to maintain invariant
-    mv a4, t3
-    mv t3, t4
-    mv t4, a4
-
-    mv a4, t1
-    mv t1, t2
-    mv t2, a4
-
-    # Check if r0 == 1
-    li t5, 1
-    beq t3, t5, done
-
-    j inv_loop
-
-# -------------------------------------
-# Helper: compute degree of a1 (MSB set)
-# -------------------------------------
-gf_degree:
-    li t0, 8              	# Start checking from MSB down
-deg_loop:
-    srl a0, a1, t0        	# Right shift a1 by t0
-    andi a0, a0, 1        	# Isolate LSB
-    bnez a0, done_deg     	# If bit is set, we're done
-    addi t0, t0, -1
-    bgez t0, deg_loop     	# Check next bit
-    li a0, 0              	# Nothing set
-    ret
-done_deg:
-    mv a0, t0
-    ret
-
-# ---------------------
-# Finalize inverse
-# ---------------------
-done:
-    mv a0, t1             	# Result is a0
-    andi a0, a0, 0xFF     	# Mask to 8 bits
-    csrr s9, instret		# count instructions at end	
-    sub s9, s9, s8	        # get number of #instructions executed	
-
-write_tohost:			# HTIF stuff
-    la t1, tohost
-    li t0, 1            	# 1 for success, 3 for failure
-    sw t0, 0(t1)        	# send success code
-    
-    la t0, begin_signature	# Address of signature
-    sw a0, 0(t0)            	# Store result (i.e., a0)
-    sw s9, 4(t0)            	# record #instructions executed
-    
-fail:
-    li a0, 0xff			# Signal failure: no inverse exists
-	
-self_loop:
-    j self_loop
-
-.section .tohost 
-tohost:                 	# write to HTIF
-    .word 0
-fromhost:
-    .word 0
-
-.data
-.EQU XLEN,32
-begin_signature:
-    .fill 2*(XLEN/32),4,0xdeadbeef     
-end_signature:
-
-	
-.bss
-    .space 512
-
diff --git a/examples/exercises/18p5/gf_inv.reference_output b/examples/exercises/18p5/gf_inv.reference_output
deleted file mode 100644
index 89b5c6395..000000000
--- a/examples/exercises/18p5/gf_inv.reference_output
+++ /dev/null
@@ -1,2 +0,0 @@
-00000092
-00000398
diff --git a/examples/exercises/3p1/3p1.S b/examples/exercises/3p1/3p1.S
deleted file mode 100644
index f17ba2718..000000000
--- a/examples/exercises/3p1/3p1.S
+++ /dev/null
@@ -1,10 +0,0 @@
-.section .text.init
-.globl rvtest_entry_point
-
-rvtest_entry_point:
-    li t0, 0x42
-    li t1, 0xED
-    add t2, t0, t1
-
-self_loop:
-    j self_loop
diff --git a/examples/exercises/3p1/Makefile b/examples/exercises/3p1/Makefile
deleted file mode 100644
index a93771689..000000000
--- a/examples/exercises/3p1/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-TARGET = 3p1
-
-$(TARGET).objdump: $(TARGET).elf
-	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
-    
-$(TARGET).elf: $(TARGET).S Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).S -o $(TARGET).elf
-
-clean:
-	rm -f $(TARGET).elf $(TARGET).objdump
-
-
diff --git a/examples/exercises/3p13/3p13.c b/examples/exercises/3p13/3p13.c
deleted file mode 100644
index 719407483..000000000
--- a/examples/exercises/3p13/3p13.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <string.h>
-
-int main(void) {
-    char str[] = "Hello Wally!";
-    return strlen(str);
-}
diff --git a/examples/exercises/3p13/Makefile b/examples/exercises/3p13/Makefile
deleted file mode 100644
index 85ed5d3c6..000000000
--- a/examples/exercises/3p13/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-TARGET = 3p13
-
-$(TARGET).objdump: $(TARGET).elf
-	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
-    
-$(TARGET).elf: $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv32gc -mabi=ilp32 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).c -o $(TARGET).elf
-
-clean:
-	rm -f $(TARGET).elf $(TARGET).objdump
diff --git a/examples/exercises/3p15/Makefile b/examples/exercises/3p15/Makefile
deleted file mode 100644
index cec51f09a..000000000
--- a/examples/exercises/3p15/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-TARGET = sumtest
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).S sum.S Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).S sum.S
-
-sim:
-	riscv_sim_RV64 -T $(TARGET).signature.output --signature-granularity 8 $(TARGET) 
-	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
-	echo "Signature matches! Success!"
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump $(TARGET).signature.output
-
-
-
diff --git a/examples/exercises/3p15/sum.S b/examples/exercises/3p15/sum.S
deleted file mode 100644
index ab87eb0ec..000000000
--- a/examples/exercises/3p15/sum.S
+++ /dev/null
@@ -1,32 +0,0 @@
-// sum.s
-// David_Harris@hmc.edu 24 December 2021
-// Add up numbers from 1 to N.
-
-// result in s0, i in s1, N in a0, return answer in a0
-//
-// long sum(long N) {
-//   long result, i;
-//   result = 0;
-//   for (i=1; i<=N; i++) result = result + i;
-//   return result;
-// }
-
-.global sum
-sum:
-    addi sp, sp, -16    # make room to save s0 and s1 on the stack
-    sd s0, 0(sp)
-    sd s1, 8(sp)
-
-    li s0, 0            # result = 0
-    li s1, 1            # i = 1
-for: bgt s1, a0, done   # exit loop if i > n
-    add s0, s0, s1      # result = result + i
-    addi s1, s1, 1      # i++
-    j for               # repeat
-
-done:
-    mv a0, s0           # put result in a0 to return
-    ld s0, 0(sp)        # restore s0 and s1 from stack
-    ld s1, 8(sp)
-    addi sp, sp, 16  
-    ret                 # return from function
diff --git a/examples/exercises/3p15/sumtest.S b/examples/exercises/3p15/sumtest.S
deleted file mode 100644
index a1b57689f..000000000
--- a/examples/exercises/3p15/sumtest.S
+++ /dev/null
@@ -1,43 +0,0 @@
-// sumtest.S
-// David_Harris@hmc.edu 24 December 2021
-
-.global rvtest_entry_point
-rvtest_entry_point:
-    la sp, topofstack   # Initialize stack pointer
-    la t0, N            # get address of N in data
-    ld a0, 0(t0)        # load N
-    csrr s8, instret    # count instructions before call
-    jal sum             # call sum(N)
-    csrr s9, instret    # count instructions after call
-    sub s9, s9, s8      # length of call
-    la t0, begin_signature  # address of signature
-    sd a0, 0(t0)        # store sum(N) in signature
-    sd s9, 8(t0)        # record performance
-
-write_tohost:
-    la t1, tohost
-    li t0, 1            # 1 for success, 3 for failure
-    sd t0, 0(t1)        # send success code
-
-self_loop:
-    j self_loop         # wait
-    
-.section .tohost 
-tohost:                 # write to HTIF
-    .dword 0
-fromhost:
-    .dword 0
-
-.data
-N:
-    .dword 6
-
-.EQU XLEN,64
-begin_signature:
-    .fill 2*(XLEN/32),4,0xdeadbeef    # 
-end_signature:
-
-# Initialize stack with room for 512 bytes
-.bss
-    .space 512
-topofstack:
diff --git a/examples/exercises/3p15/sumtest.reference_output b/examples/exercises/3p15/sumtest.reference_output
deleted file mode 100644
index 34200f638..000000000
--- a/examples/exercises/3p15/sumtest.reference_output
+++ /dev/null
@@ -1,2 +0,0 @@
-0000000000000015
-0000000000000025
diff --git a/examples/exercises/3p3/Makefile b/examples/exercises/3p3/Makefile
deleted file mode 100644
index ba7734ca1..000000000
--- a/examples/exercises/3p3/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-TARGET = sumtest
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).S sum.S Makefile
-	riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).S sum.S
-
-sim:
-	spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET)
-	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
-	echo "Signature matches! Success!"
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump $(TARGET).signature.output
-
-
-
diff --git a/examples/exercises/3p3/sum.S b/examples/exercises/3p3/sum.S
deleted file mode 100644
index ab87eb0ec..000000000
--- a/examples/exercises/3p3/sum.S
+++ /dev/null
@@ -1,32 +0,0 @@
-// sum.s
-// David_Harris@hmc.edu 24 December 2021
-// Add up numbers from 1 to N.
-
-// result in s0, i in s1, N in a0, return answer in a0
-//
-// long sum(long N) {
-//   long result, i;
-//   result = 0;
-//   for (i=1; i<=N; i++) result = result + i;
-//   return result;
-// }
-
-.global sum
-sum:
-    addi sp, sp, -16    # make room to save s0 and s1 on the stack
-    sd s0, 0(sp)
-    sd s1, 8(sp)
-
-    li s0, 0            # result = 0
-    li s1, 1            # i = 1
-for: bgt s1, a0, done   # exit loop if i > n
-    add s0, s0, s1      # result = result + i
-    addi s1, s1, 1      # i++
-    j for               # repeat
-
-done:
-    mv a0, s0           # put result in a0 to return
-    ld s0, 0(sp)        # restore s0 and s1 from stack
-    ld s1, 8(sp)
-    addi sp, sp, 16  
-    ret                 # return from function
diff --git a/examples/exercises/3p3/sumtest.S b/examples/exercises/3p3/sumtest.S
deleted file mode 100644
index a1b57689f..000000000
--- a/examples/exercises/3p3/sumtest.S
+++ /dev/null
@@ -1,43 +0,0 @@
-// sumtest.S
-// David_Harris@hmc.edu 24 December 2021
-
-.global rvtest_entry_point
-rvtest_entry_point:
-    la sp, topofstack   # Initialize stack pointer
-    la t0, N            # get address of N in data
-    ld a0, 0(t0)        # load N
-    csrr s8, instret    # count instructions before call
-    jal sum             # call sum(N)
-    csrr s9, instret    # count instructions after call
-    sub s9, s9, s8      # length of call
-    la t0, begin_signature  # address of signature
-    sd a0, 0(t0)        # store sum(N) in signature
-    sd s9, 8(t0)        # record performance
-
-write_tohost:
-    la t1, tohost
-    li t0, 1            # 1 for success, 3 for failure
-    sd t0, 0(t1)        # send success code
-
-self_loop:
-    j self_loop         # wait
-    
-.section .tohost 
-tohost:                 # write to HTIF
-    .dword 0
-fromhost:
-    .dword 0
-
-.data
-N:
-    .dword 6
-
-.EQU XLEN,64
-begin_signature:
-    .fill 2*(XLEN/32),4,0xdeadbeef    # 
-end_signature:
-
-# Initialize stack with room for 512 bytes
-.bss
-    .space 512
-topofstack:
diff --git a/examples/exercises/3p3/sumtest.reference_output b/examples/exercises/3p3/sumtest.reference_output
deleted file mode 100644
index 34200f638..000000000
--- a/examples/exercises/3p3/sumtest.reference_output
+++ /dev/null
@@ -1,2 +0,0 @@
-0000000000000015
-0000000000000025
diff --git a/examples/exercises/3p5/Makefile b/examples/exercises/3p5/Makefile
deleted file mode 100644
index d93502ee6..000000000
--- a/examples/exercises/3p5/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-TARGET = matvecmul
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../../C/common/test.ld -I../../C/common \
-	  $(TARGET).c ../../C/common/crt.S ../../C/common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/exercises/3p5/matvecmul.c b/examples/exercises/3p5/matvecmul.c
deleted file mode 100644
index 424c27ab0..000000000
--- a/examples/exercises/3p5/matvecmul.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <stdio.h>  // supports printf
-#include "util.h"   // supports verify
-
-// Matrix-vector multiplication y = Ax.  
-// A is an m rows x n columns matrix.
-void matvecmul(int A[], int x[], int y[], int m, int n) {
- 	int i, j, sum;
-	for (i=0; i<m; i = i + 1) {
-		sum = 0;
-		for (j=0; j<n; j = j + 1) 
-			sum = sum + A[i*n+j] * x[j];
-		y[i] = sum;
-	}
-}
-
-void main(void) {
-  int A[6] = {1, 2, 3, 4, 5, 6};
-  int x[3] = {7, 8, 9};
-  int y[2];
-  
-  matvecmul(A, x, y, 2, 3);
-}
diff --git a/examples/exercises/3p7/Makefile b/examples/exercises/3p7/Makefile
deleted file mode 100644
index 153636b34..000000000
--- a/examples/exercises/3p7/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-TARGET = fir
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O2\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../../C/common/test.ld -I../../C/common \
-	  $(TARGET).c ../../C/common/crt.S ../../C/common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/exercises/3p7/fir.c b/examples/exercises/3p7/fir.c
deleted file mode 100644
index 05e969732..000000000
--- a/examples/exercises/3p7/fir.c
+++ /dev/null
@@ -1,83 +0,0 @@
-#include <stdio.h>  // supports printf
-#include "util.h"   // supports verify
-
-// Add two Q1.31 fixed point numbers
-int add_q31(int a, int b) {
-	return a + b;
-}
-
-// Multiplly two Q1.31 fixed point numbers
-int mul_q31(int a, int b) {
-	long res = (long)a * (long)b;
-	int result = res >> 31; // shift right to get the 32-bit result; this is equivalent to shifting left by 1 and discarding the bottom 32 bits
-	//printf("mul_q31: a = %x, b = %x, res = %lx, result = %x\n", a, b, res, result);
-	return result; 
-}
-
-
-// low pass filter x with coefficients c, result in y
-// n is the length of x, m is the length of c
-// y[i] = c[0]*x[i] + c[1]*x[i+1] + ... + c[m-1]*x[i+m-1]
-// inputs in Q1.31 format
-void fir(int x[], int c[], int y[], int n, int m) {
-	int i, j;
-	for (j=0; j<n-m+1; j++) {
-		y[j] = 0;
-		for (i=0; i<m; i++) 
-			y[j] = add_q31(y[j], mul_q31(c[i], x[j-i+(m-1)]));
-	}
-}
-
-int main(void) {
-	int32_t sin_table[20] = { // in Q1.31 format
-		0x00000000, // sin(0*2pi/10)
-		0x4B3C8C12, // sin(1*2pi/10)
-		0x79BC384D, // sin(2*2pi/10)
-		0x79BC384D, // sin(3*2pi/10)
-		0x4B3C8C12, // sin(4*2pi/10)
-		0x00000000, // sin(5*2pi/10)
-		0xB4C373EE, // sin(6*2pi/10)
-		0x8643C7B3, // sin(7*2pi/10)
-		0x8643C7B3, // sin(8*2pi/10)
-		0xB4C373EE, // sin(9*2pi/10)
-		0x00000000, // sin(10*2pi/10)
-		0x4B3C8C12, // sin(11*2pi/10)
-		0x79BC384D, // sin(12*2pi/10)
-		0x79BC384D, // sin(13*2pi/10)
-		0x4B3C8C12, // sin(14*2pi/10)
-		0x00000000, // sin(15*2pi/10)
-		0xB4C373EE, // sin(16*2pi/10)
-		0x8643C7B3, // sin(17*2pi/10)
-		0x8643C7B3, // sin(18*2pi/10)
-		0xB4C373EE  // sin(19*2pi/10)
-	};  
-	int lowpass[4] = {0x20000001, 0x20000002, 0x20000003, 0x20000004}; // 1/4 in Q1.31 format
-	int y[17];
-  	int expected[17] = { // in Q1.31 format
-		0x4fad3f2f,
-		0x627c6236,
-		0x4fad3f32,
-		0x1e6f0e17,
-		0xe190f1eb,
-		0xb052c0ce,
-		0x9d839dc6,
-		0xb052c0cb,
-		0xe190f1e6,
-		0x1e6f0e12,
-		0x4fad3f2f,
-		0x627c6236,
-		0x4fad3f32,
-		0x1e6f0e17,
-		0xe190f1eb,
-		0xb052c0ce,
-		0x9d839dc6
-	};
-
-  	setStats(1);		// record initial mcycle and minstret
-	fir(sin_table, lowpass, y, 20, 4);
-	setStats(0);		// record elapsed mcycle and minstret
-	for (int i=0; i<17; i++) {
-		printf("y[%d] = %x\n", i, y[i]);
-	}
-  	return verify(16, y, expected); // check the 1 element of s matches expected. 0 means success
-}
diff --git a/examples/exercises/3p9/Makefile b/examples/exercises/3p9/Makefile
deleted file mode 100644
index db81ca1d7..000000000
--- a/examples/exercises/3p9/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-TARGET = inline
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../../C/common/test.ld -I../../C/common \
-	  $(TARGET).c ../../C/common/crt.S ../../C/common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/exercises/3p9/inline.c b/examples/exercises/3p9/inline.c
deleted file mode 100644
index 03787eb09..000000000
--- a/examples/exercises/3p9/inline.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <stdio.h>  // supports printf
-int main(void) {
-	int a = 3;
-	int b = 4;
-	int c;
-	// compute c = a + 2*b using inline assembly
-	asm volatile("slli %0, %1, 1" : "=r" (c) : "r" (b));	      // c = b << 1
-	asm volatile("add %0, %1, %2" : "=r" (c) : "r" (a), "r" (c)); // c = a + c
-
-	printf("c = %d\n", c);
-}
diff --git a/examples/exercises/7p12/buga.sh b/examples/exercises/7p12/buga.sh
deleted file mode 100755
index 85cdf144a..000000000
--- a/examples/exercises/7p12/buga.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/sh
-sed -i 's/logic \[`CTRLW-1:0] ControlsD/logic        ControlsD/' $WALLY/src/ieu/controller.sv
-
diff --git a/examples/exercises/7p12/bugall.sh b/examples/exercises/7p12/bugall.sh
deleted file mode 100755
index ba18943a9..000000000
--- a/examples/exercises/7p12/bugall.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-$WALLY/examples/exercises/7p12/buga.sh
-$WALLY/examples/exercises/7p12/bugb.sh
-$WALLY/examples/exercises/7p12/bugc.sh
-$WALLY/examples/exercises/7p12/bugd.sh
diff --git a/examples/exercises/7p12/bugb.sh b/examples/exercises/7p12/bugb.sh
deleted file mode 100755
index fc90f3019..000000000
--- a/examples/exercises/7p12/bugb.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/sh
-sed -i 's/R2D, R2E/R2D, R1E/' $WALLY/src/ieu/datapath.sv
-
diff --git a/examples/exercises/7p12/bugc.sh b/examples/exercises/7p12/bugc.sh
deleted file mode 100755
index 8d8fb55d5..000000000
--- a/examples/exercises/7p12/bugc.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/sh
-sed -i 's/assign reset_ext = /assign reset_ext = 1 | /' $WALLY/testbench/testbench.sv
-
diff --git a/examples/exercises/7p12/bugd.sh b/examples/exercises/7p12/bugd.sh
deleted file mode 100755
index 3fe5dcd48..000000000
--- a/examples/exercises/7p12/bugd.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/sh
-sed -i 's/LTU}/LT}/' $WALLY/src/ieu/alu.sv
-
diff --git a/examples/exercises/fma16/Makefile b/examples/exercises/fma16/Makefile
deleted file mode 100644
index 3c2da67f5..000000000
--- a/examples/exercises/fma16/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-
-
-CC     = gcc
-CFLAGS = -O3 -Wno-format-overflow
-IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
-LIBS   = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
-SRCS   = $(wildcard *.c)
-PROGS = $(patsubst %.c,%,$(SRCS))
-
-all:	$(PROGS)
-
-%: %.c
-	$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
-
-clean:
-	rm -f $(PROGS)
diff --git a/examples/exercises/fma16/fma.do b/examples/exercises/fma16/fma.do
deleted file mode 100644
index 111b393ca..000000000
--- a/examples/exercises/fma16/fma.do
+++ /dev/null
@@ -1,23 +0,0 @@
-# fma.do 
-#
-# run with vsim -do "do fma.do"
-# add -c before -do for batch simulation
-
-onbreak {resume}
-
-# create library
-vlib worklib
-
-vlog -lint -sv -work worklib fma16.sv testbench.sv
-vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
-vsim -lib worklib testbenchopt
-
-add wave sim:/testbench_fma16/clk
-add wave sim:/testbench_fma16/reset
-add wave sim:/testbench_fma16/x
-add wave sim:/testbench_fma16/y
-add wave sim:/testbench_fma16/z
-add wave sim:/testbench_fma16/result
-add wave sim:/testbench_fma16/rexpected
-
-run -all
diff --git a/examples/exercises/fma16/fma16_testgen.c b/examples/exercises/fma16/fma16_testgen.c
deleted file mode 100644
index 86279e7e2..000000000
--- a/examples/exercises/fma16/fma16_testgen.c
+++ /dev/null
@@ -1,153 +0,0 @@
-// fma16_testgen.c
-// David_Harris 8 February 2025
-// Generate tests for 16-bit FMA
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include "softfloat.h"
-#include "softfloat_types.h"
-
-typedef union sp {
-  float32_t v;
-  float f;
-} sp;
-
-// lists of tests, terminated with 0x8000
-uint16_t easyExponents[] = {15, 0x8000};
-uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
-
-void softfloatInit(void) {
-    softfloat_roundingMode = softfloat_round_minMag; 
-    softfloat_exceptionFlags = 0;
-    softfloat_detectTininess = softfloat_tininess_beforeRounding;
-}
-
-float convFloat(float16_t f16) {
-    float32_t f32;
-    float res;
-    sp r;
-
-    // convert half to float for printing
-    f32 = f16_to_f32(f16);
-    r.v = f32;
-    res = r.f;
-    return res;
-}
-
-void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
-    float16_t result;
-    int op, flagVals;
-    char calc[80], flags[80];
-    float32_t x32, y32, z32, r32;
-    float xf, yf, zf, rf;
-    float16_t x2, z2;
-    float16_t smallest;
-
-    if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
-    if (!add) z.v = 0x0000; // force z to 0 to avoid add
-
-    // Negated versions of x and z are used in the mulAdd call where necessary
-    x2 = x;
-    z2 = z;
-    if (negp) x2.v ^= 0x8000; // flip sign of x to negate p
-    if (negz) z2.v ^= 0x8000; // flip sign of z to negate z
-
-    op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz;
-//    printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz);
-    softfloat_exceptionFlags = 0; // clear exceptions
-    result = f16_mulAdd(x2, y, z2); // call SoftFloat to compute expected result
-
-    // Extract expected flags from SoftFloat
-    sprintf(flags, "NV: %d OF: %d UF: %d NX: %d", 
-        (softfloat_exceptionFlags >> 4) % 2,
-        (softfloat_exceptionFlags >> 2) % 2,
-        (softfloat_exceptionFlags >> 1) % 2,
-        (softfloat_exceptionFlags) % 2);
-    // pack these four flags into one nibble, discarding DZ flag
-    flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8);
-
-    // convert to floats for printing
-    xf = convFloat(x);
-    yf = convFloat(y);
-    zf = convFloat(z);
-    rf = convFloat(result);
-    if (mul)
-        if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf);
-        else     sprintf(calc, "%f * %f = %f", xf, yf, rf);
-    else         sprintf(calc, "%f + %f = %f", xf, zf, rf);
-
-    // omit denorms, which aren't required for this project
-    smallest.v = 0x0400;
-    float16_t resultmag = result;
-    resultmag.v &= 0x7FFF; // take absolute value
-    if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
-    if ((softfloat_exceptionFlags >> 1) % 2) fprintf(fptr, "// skip underflow: ");
-
-    // skip special cases if requested
-    if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
-    if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed)  fprintf(fptr, "// Skip inf: ");
-    if (resultmag.v >  0x7C00 && !nanAllowed)  fprintf(fptr, "// Skip NaN: ");
-
-    // print the test case
-    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags);
-}
-
-void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, 
-               FILE *fptr, int *numCases) {
-    int i, j;
-
-    // Loop over all of the exponents and fractions, generating and counting all cases
-    fprintf(fptr, "%s", desc); fprintf(fptr, "\n");
-    *numCases=0;
-    for (i=0; e[i] != 0x8000; i++)
-        for (j=0; f[j] != 0x8000; j++) {
-            cases[*numCases].v = f[j] | e[i]<<10;
-            *numCases = *numCases + 1;
-        }
-}
-
-void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
-    int i, j, k, numCases;
-    float16_t x, y, z;
-    float16_t cases[100000];
-    FILE *fptr;
-    char fn[80];
- 
-    sprintf(fn, "work/%s.tv", testName);
-    if ((fptr = fopen(fn, "w")) == 0) {
-        printf("Error opening to write file %s.  Does directory exist?\n", fn);
-        exit(1);
-    }
-    prepTests(e, f, testName, desc, cases, fptr, &numCases);
-    z.v = 0x0000;
-    for (i=0; i < numCases; i++) { 
-        x.v = cases[i].v;
-        for (j=0; j<numCases; j++) {
-            y.v = cases[j].v;
-            for (k=0; k<=sgn; k++) {
-                y.v ^= (k<<15);
-                genCase(fptr, x, y, z, 1, 0, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
-            }
-        }
-    }
-    fclose(fptr);
-}
-
-int main()
-{
-    if (system("mkdir -p work") != 0) exit(1); // create work directory if it doesn't exist
-    softfloatInit(); // configure softfloat modes
- 
-    // Test cases: multiplication
-    genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
-
-/*  // example of how to generate tests with a different rounding mode
-    softfloat_roundingMode = softfloat_round_near_even; 
-    genMulTests(easyExponents, easyFracts, 0, "fmul_0_rne", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RNE", 1, 0, 0, 0); */
-
-    // Add your cases here
-  
-    return 0;
-}
diff --git a/examples/exercises/fma16/lint-fma b/examples/exercises/fma16/lint-fma
deleted file mode 100755
index e69fa3279..000000000
--- a/examples/exercises/fma16/lint-fma
+++ /dev/null
@@ -1,12 +0,0 @@
-#!/bin/bash
-# check for warnings in Verilog code
-# The verilator lint tool is faster and better than Questa so it is best to run this first.
-verilator=`which verilator`
-
-basepath=$(dirname $0)/..
-if ($verilator --lint-only --top-module fma16 fma16.sv); then
-    echo "fma16 passed lint"
-else
-    echo "fma16 failed lint"
-fi
-
diff --git a/examples/exercises/fma16/sim-fma b/examples/exercises/fma16/sim-fma
deleted file mode 100755
index bf55614c5..000000000
--- a/examples/exercises/fma16/sim-fma
+++ /dev/null
@@ -1,2 +0,0 @@
-vsim -do "do fma.do"
-
diff --git a/examples/exercises/fma16/sim-fma-batch b/examples/exercises/fma16/sim-fma-batch
deleted file mode 100755
index 01c2472e9..000000000
--- a/examples/exercises/fma16/sim-fma-batch
+++ /dev/null
@@ -1 +0,0 @@
-vsim -c -do "do fma.do"
diff --git a/examples/exercises/fma16/testbench.sv b/examples/exercises/fma16/testbench.sv
deleted file mode 100644
index ffc566b72..000000000
--- a/examples/exercises/fma16/testbench.sv
+++ /dev/null
@@ -1,52 +0,0 @@
-/* verilator lint_off STMTDLY */
-module testbench_fma16;
-  logic        clk, reset;
-  logic [15:0] x, y, z, rexpected, result;
-  logic [7:0]  ctrl;
-  logic        mul, add, negp, negz;
-  logic [1:0]  roundmode;
-  logic [31:0] vectornum, errors;
-  logic [75:0] testvectors[10000:0];
-  logic [3:0]  flags, flagsexpected; // Invalid, Overflow, Underflow, Inexact
-
-  // instantiate device under test
-  fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result, flags);
-
-  // generate clock
-  always 
-    begin
-      clk = 1; #5; clk = 0; #5;
-    end
-
-  // at start of test, load vectors and pulse reset
-  initial
-    begin
-      $readmemh("tests/fmul_0.tv", testvectors);
-      vectornum = 0; errors = 0;
-      reset = 1; #22; reset = 0;
-    end
-
-  // apply test vectors on rising edge of clk
-  always @(posedge clk)
-    begin
-      #1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
-      {roundmode, mul, add, negp, negz} = ctrl[5:0];
-    end
-
-  // check results on falling edge of clk
-  always @(negedge clk)
-    if (~reset) begin // skip during reset
-      if (result !== rexpected /* | flags !== flagsexpected */) begin  // check result
-        $display("Error: inputs %h * %h + %h", x, y, z);
-        $display("  result = %h (%h expected) flags = %b (%b expected)", 
-          result, rexpected, flags, flagsexpected);
-        errors = errors + 1;
-      end
-      vectornum = vectornum + 1;
-      if (testvectors[vectornum] === 'x) begin 
-        $display("%d tests completed with %d errors", 
-	           vectornum, errors);
-        $stop;
-      end
-    end
-endmodule
diff --git a/examples/exercises/fma16/tests/fmul_0.tv b/examples/exercises/fma16/tests/fmul_0.tv
deleted file mode 100644
index b139db2a3..000000000
--- a/examples/exercises/fma16/tests/fmul_0.tv
+++ /dev/null
@@ -1,5 +0,0 @@
-// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ
-3c00_3c00_0000_08_3c00_0 // 1.000000 * 1.000000 = 1.000000 NV: 0 OF: 0 UF: 0 NX: 0
-3c00_3e00_0000_08_3e00_0 // 1.000000 * 1.500000 = 1.500000 NV: 0 OF: 0 UF: 0 NX: 0
-3e00_3c00_0000_08_3e00_0 // 1.500000 * 1.000000 = 1.500000 NV: 0 OF: 0 UF: 0 NX: 0
-3e00_3e00_0000_08_4080_0 // 1.500000 * 1.500000 = 2.250000 NV: 0 OF: 0 UF: 0 NX: 0
diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile
index f3fc4bdcf..196fdf3d2 100644
--- a/examples/fp/fpcalc/Makefile
+++ b/examples/fp/fpcalc/Makefile
@@ -1,16 +1,23 @@
-# fpcalc Makefile
+# Makefile
 
 CC     = gcc
 CFLAGS = -O3 -Wno-format-overflow
-IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
-LIBS   = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
+LIBS   = -lm
+LFLAGS = -L. 
+# Link against the riscv-isa-sim version of SoftFloat rather than 
+# the regular version to get RISC-V NaN behavior
+IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
+LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
+#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
 SRCS   = $(wildcard *.c)
+
 PROGS = $(patsubst %.c,%,$(SRCS))
 
 all:	$(PROGS)
 
 %: %.c
-	$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
+	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
 
-clean:
+clean: 
 	rm -f $(PROGS)
diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c
index e4638a64b..94bfc9ac1 100644
--- a/examples/fp/fpcalc/fpcalc.c
+++ b/examples/fp/fpcalc/fpcalc.c
@@ -7,8 +7,6 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
-#include <inttypes.h>
-#include <quadmath.h> // GCC Quad-Math Library
 #include "softfloat.h"
 #include "softfloat_types.h"
 
@@ -28,12 +26,6 @@ typedef union dp {
   double d;
 } dp;
 
-typedef union qp {
-  uint64_t v64[2];
-  __uint128_t v;
-  __float128 q;
-} qp;
-
 
 int opSize = 0;
 
@@ -148,45 +140,6 @@ void printF64(char *msg, float64_t f) {
   //  msg, conv.v, conv.d, sci, exp, fract); 
 }
 
-void printF128 (char *msg, float128_t q) {
-  qp conv;
-  //__int128_t v128;
-  int i, j;
-  char buf[64];
-  //v128 = q.v[1];
-  //v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
-  //conv.v = v128;
-  conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
-  conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
-  printf("%s: ", msg);  // print out nicely
-
-  // Some compilers can understand %Q for printf on quad precision instead of the
-  // API call of quadmath_snprintf
-  // printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
-  quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
-  //printf("0x%032" PRIx12 " = %s\n", q.v, buf);  
-  printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);  
-
-}
-
-void printF128val(float128_t q) {
-  qp conv;
-  //__int128_t v128;
-  int i, j;
-  char buf[64];
-  //v128 = q.v[1];
-  //v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
-  //conv.v = v128;
-  conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
-  conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
-
-  // Some compilers can understand %Q for printf on quad precision instead of the
-  // API call of quadmath_snprintf
-  // printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
-  //quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
-  printf("%016" PRIx64 "%016" PRIx64 "\n", q.v[1], q.v[0]);  
-}
-
 void printFlags(void) {
   int NX = softfloat_exceptionFlags % 2;
   int UF = (softfloat_exceptionFlags >> 1) % 2;
@@ -207,71 +160,26 @@ void softfloatInit(void) {
     softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
 }
 
-__uint128_t strtoul128(char *num, int base) {
-  __uint128_t result = 0;
-  int i;
-  for (i=0; i<strlen(num); i++) {
-    result = result * base;
-    if (num[i] >= '0' && num[i] <= '9') result += num[i] - '0';
-    else if (num[i] >= 'a' && num[i] <= 'f') result += num[i] - 'a' + 10;
-    else if (num[i] >= 'A' && num[i] <= 'F') result += num[i] - 'A' + 10;
-    else {
-      printf("Error: bad character %c in number %s\n", num[i], num);
-      exit(1);
-    }
-  }
-  return result;
-}
-
-__uint128_t parseNum(char *num) {
-  __uint128_t result = 0;
-
-  // Ensure input is in correct form
-  if (num[0] == '0' && num[1] == 'x') {
-    num += 2; // Skip "0x"
-  } else if (num[0] == 'x') {
-    num += 1; // Skip "x"
-  }
-  
-  int size; // size of operands in bytes (2= half, 4=single, 8 = double)                                                                                                                          
+uint64_t parseNum(char *num) {
+  uint64_t result;
+  int size; // size of operands in bytes (2= half, 4=single, 8 = double)
   if (strlen(num) < 8) size = 2;
   else if (strlen(num) < 16) size = 4;
-  else if (strlen(num) < 32) size = 8;
-  else if (strlen(num) < 35) size = 16;                                                                                                                          
+  else if (strlen(num) < 19) size = 8;
   else {
-    printf("Error: only half, single, double, or quad precision supported");
+    printf("Error: only half, single, and double precision supported");
     exit(1);
   }
   if (opSize != 0) {
     if (size != opSize) {
       printf("Error: inconsistent operand sizes %d and %d\n", size, opSize);
       exit(1);
-    }
+    } 
   } else {
     opSize = size;
+    //printf ("Operand size is %d\n", opSize);
   }
-
-  if (strlen(num) <= 16) {
-    result = (__uint128_t)strtoull(num, NULL, 16);
-  }
-  else {
-    while (*num) {
-      int value;
-      if (*num >= '0' && *num <= '9')
-        value = *num - '0';
-      else if (*num >= 'a' && *num <= 'f')
-        value = *num - 'a' + 10;
-      else if (*num >= 'A' && *num <= 'F')
-        value = *num - 'A' + 10;
-      else {
-        printf("Error: invalid character in input\n");
-        exit(1);
-      }
-      result = (result << 4) | value;
-      num++;
-    }
-  }
-  
+  result = (uint64_t)strtoul(num, NULL, 16);
   //printf("Parsed %s as 0x%lx\n", num, result);
   return result;
 }
@@ -296,9 +204,9 @@ char parseRound(char *rnd) {
   }
 }
 
-int main(int argc, char *argv[]) {
-    //uint64_t xn, yn, zn;
-    __uint128_t xn, yn, zn;
+int main(int argc, char *argv[])
+{
+    uint64_t xn, yn, zn;
     char op1, op2;
     char cmd[200];
 
@@ -309,7 +217,6 @@ int main(int argc, char *argv[]) {
       exit(1);
     } else {
       softfloat_roundingMode = softfloat_round_near_even;
-      //printf("argv[0] = %s arvg[1] = %s argv[2] = %s argv[3] = %s\n", argv[0], argv[1], argv[2], argv[3]);
       xn = parseNum(argv[1]);
       yn = parseNum(argv[3]);
       op1 = parseOp(argv[2]);
@@ -334,22 +241,12 @@ int main(int argc, char *argv[]) {
             r = f32_mulAdd(x, y, z);
             printF32("X", x); printF32("Y", y); printF32("Z", z);
             printF32("result = X*Y+Z", r); printFlags();
-          } else if (opSize == 8) { 
+          } else { // opSize = 8
             float64_t x, y, z, r;
             x.v = xn; y.v = yn; z.v = zn;
             r = f64_mulAdd(x, y, z);
             printF64("X", x); printF64("Y", y); printF64("Z", z);
             printF64("result = X*Y+Z", r); printFlags();
-          } else { // opSize = 16
-            float128_t x, y, z, r;
-            qp xc, yc, zc;
-            xc.v = xn; yc.v = yn; zc.v = zn;
-            x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
-            y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
-            z.v[0] = zc.v64[0]; z.v[1] = zc.v64[1];
-            r = f128_mulAdd(x, y, z);
-            printF128("X", x); printF128("Y", y); printF128("Z", z);
-            printF128("result = X*Y+Z", r); printFlags();
           }
         }
       } else {
@@ -382,7 +279,7 @@ int main(int argc, char *argv[]) {
           sprintf(cmd, "0x%08x %c 0x%08x", x.v, op1, y.v);
           printF32(cmd, r); printFlags();
 
-        } else if (opSize == 8) { // opSize = 8
+        } else { // opSize = 8
           float64_t x, y, r;
           x.v = xn; y.v = yn;
           switch (op1) {
@@ -396,27 +293,7 @@ int main(int argc, char *argv[]) {
           printF64("X", x); printF64("Y", y); 
           sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
           printF64(cmd, r); printFlags();
-        } else { // opSize = 16
-          float128_t x, y, r;
-          qp xc, yc;
-          xc.v = xn; yc.v = yn;
-          x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
-          y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
-          //x.v = xn; y.v = yn;
-          switch (op1) {
-            case 'x': r = f128_mul(x, y); break;
-            case '+': r = f128_add(x, y); break;
-            case '-': r = f128_sub(x, y); break;
-            case '/': r = f128_div(x, y); break;
-            case '%': r = f128_rem(x, y); break;
-            default: printf("Unknown op %c\n", op1); exit(1);
-          }
-          printF128("X", x); printF128("Y", y); 
-          //sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
-          printf("0x%016" PRIx64 "_%016" PRIx64 " %c ", x.v[1], x.v[0], op1);
-          printf("0x%016" PRIx64 "_%016" PRIx64 " ", y.v[1], y.v[0]);
-          printF128(cmd, r); printFlags();
-          // printF128val(r); 
+
         }
       }
     }
diff --git a/examples/fp/softfloat_demo/Makefile b/examples/fp/softfloat_demo/Makefile
index 009a08e17..4d0efe20e 100644
--- a/examples/fp/softfloat_demo/Makefile
+++ b/examples/fp/softfloat_demo/Makefile
@@ -1,17 +1,23 @@
-# softfloat_demo Makefile
+# Makefile
 
 CC     = gcc
 CFLAGS = -O3
-LFLAGS = -L.
-IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
-LIBS   = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
+LIBS   = -lm
+LFLAGS = -L. 
+# Link against the riscv-isa-sim version of SoftFloat rather than 
+# the regular version to get RISC-V NaN behavior
+IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
+LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
+#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
 SRCS   = $(wildcard *.c)
-PROGS  = $(patsubst %.c,%,$(SRCS))
+
+PROGS = $(patsubst %.c,%,$(SRCS))
 
 all:	$(PROGS)
 
 %: %.c
-	$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
+	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
 
-clean:
+clean: 
 	rm -f $(PROGS)
diff --git a/examples/fp/softfloat_demo/softfloat_demoDP.c b/examples/fp/softfloat_demo/softfloat_demoDP.c
deleted file mode 100644
index b46103eed..000000000
--- a/examples/fp/softfloat_demo/softfloat_demoDP.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// softfloat_demo3.c
-// james.stine@okstate.edu 15 August 2023
-// 
-// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
-
-#include <stdio.h>
-#include <stdint.h>
-#include <inttypes.h>
-#include <quadmath.h> // GCC Quad-Math Library
-#include "softfloat.h"
-#include "softfloat_types.h"
-typedef union sp {
-  uint32_t v;
-  float f;
-} sp;
-
-typedef union dp {
-  uint64_t v;
-  double d;
-} dp;
-
-typedef union qp {
-  uint64_t v[2];
-  __float128 q;
-} qp;
-
-
-void printF32 (char *msg, float32_t f) {
-  sp conv;
-  int i, j;
-  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
-}
-
-void printF64 (char *msg, float64_t d) {
-  dp conv;
-  int i, j;
-  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
-}
-
-void printF128 (char *msg, float128_t q) {
-  qp conv;
-  int i, j;
-  char buf[64];
-  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
-  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
-  printf("%s: ", msg);  // print out nicely
-  //printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
-  quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
-  printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);    
-}
-
-void printFlags(void) {
-  int NX = softfloat_exceptionFlags % 2;
-  int UF = (softfloat_exceptionFlags >> 1) % 2;
-  int OF = (softfloat_exceptionFlags >> 2) % 2;
-  int DZ = (softfloat_exceptionFlags >> 3) % 2;
-  int NV = (softfloat_exceptionFlags >> 4) % 2;
-  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
-          NX, UF, OF, DZ, NV);
-}
-
-void softfloatInit(void) {
-    // rounding modes: RNE: softfloat_round_near_even
-    //                 RZ:  softfloat_round_minMag
-    //                 RP:  softfloat_round_max
-    //                 RM:  softfloat_round_min
-    softfloat_roundingMode = softfloat_round_near_even; 
-    softfloat_exceptionFlags = 0; // clear exceptions
-    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
-}
-
-int main() {
-  
-  float64_t x, y, z;
-  float64_t r;
-
-  x.v = 0xBFFF988ECE97DFEB;
-  y.v = 0x3F8EFFFFFFFFFFFF;
-  z.v = 0x4001000000000000;
-
-  softfloatInit();
-  printF64("X", x); printF64("Y", y); printF64("Z", z);
-  r = f64_mulAdd(x, y, z);
-  printf("\n");
-  printF64("r", r);
-  
-}
diff --git a/examples/fp/softfloat_demo/softfloat_demoQP.c b/examples/fp/softfloat_demo/softfloat_demoQP.c
deleted file mode 100644
index 0f97d3bf6..000000000
--- a/examples/fp/softfloat_demo/softfloat_demoQP.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// softfloat_demo3.c
-// james.stine@okstate.edu 15 August 2023
-// 
-// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
-
-#include <stdio.h>
-#include <stdint.h>
-#include <inttypes.h>
-#include <quadmath.h> // GCC Quad-Math Library
-#include "softfloat.h"
-#include "softfloat_types.h"
-typedef union sp {
-  uint32_t v;
-  float f;
-} sp;
-
-typedef union dp {
-  uint64_t v;
-  double d;
-} dp;
-
-typedef union qp {
-  uint64_t v[2];
-  __float128 q;
-} qp;
-
-
-void printF32 (char *msg, float32_t f) {
-  sp conv;
-  int i, j;
-  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
-}
-
-void printF64 (char *msg, float64_t d) {
-  dp conv;
-  int i, j;
-  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
-}
-
-void printF128 (char *msg, float128_t q) {
-  qp conv;
-  int i, j;
-  char buf[64];
-  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
-  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
-  printf("%s: ", msg);  // print out nicely
-
-  // Some compilers can understand %Q for printf on quad precision instead of the
-  // API call of quadmath_snprintf
-  // printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
-  quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
-  printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);  
-
-}
-
-void printFlags(void) {
-  int NX = softfloat_exceptionFlags % 2;
-  int UF = (softfloat_exceptionFlags >> 1) % 2;
-  int OF = (softfloat_exceptionFlags >> 2) % 2;
-  int DZ = (softfloat_exceptionFlags >> 3) % 2;
-  int NV = (softfloat_exceptionFlags >> 4) % 2;
-  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
-          NX, UF, OF, DZ, NV);
-}
-
-void softfloatInit(void) {
-    // rounding modes: RNE: softfloat_round_near_even
-    //                 RZ:  softfloat_round_minMag
-    //                 RP:  softfloat_round_max
-    //                 RM:  softfloat_round_min
-    softfloat_roundingMode = softfloat_round_near_even; 
-    softfloat_exceptionFlags = 0; // clear exceptions
-    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
-}
-
-int main() {
-  
-  float128_t x, y, z;
-  float128_t r;
-  uint32_t u, v, w;
-  int32_t a, b, c;
-
-  x.v[1] = 0xBFFF988ECE97DFEB;
-  x.v[0] = 0xC3BBA082445B4836;
-  y.v[1] = 0x3F8EFFFFFFFFFFFF;
-  y.v[0] = 0xFFFFFFFFFFFFFFFF;
-  z.v[1] = 0x4001000000000000;
-  z.v[0] = 0x0000000000000000;
-
-  softfloatInit();
-  printF128("X", x); printF128("Y", y); printF128("Z", z);
-  r = f128_mulAdd(x, y, z);
-  printf("\n");
-  printF128("r", r);
-  
-}
diff --git a/examples/fp/softfloat_demo/softfloat_demoSP.c b/examples/fp/softfloat_demo/softfloat_demoSP.c
deleted file mode 100644
index bbc39438e..000000000
--- a/examples/fp/softfloat_demo/softfloat_demoSP.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// softfloat_demo3.c
-// james.stine@okstate.edu 15 August 2023
-// 
-// Demonstrate using SoftFloat do compute a floating-point for quad, then print results
-
-#include <stdio.h>
-#include <stdint.h>
-#include <inttypes.h>
-#include <quadmath.h> // GCC Quad-Math Library
-#include "softfloat.h"
-#include "softfloat_types.h"
-typedef union sp {
-  uint32_t v;
-  float f;
-} sp;
-
-typedef union dp {
-  uint64_t v;
-  double d;
-} dp;
-
-typedef union qp {
-  uint64_t v[2];
-  __float128 q;
-} qp;
-
-
-void printF32 (char *msg, float32_t f) {
-  sp conv;
-  int i, j;
-  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
-}
-
-void printF64 (char *msg, float64_t d) {
-  dp conv;
-  int i, j;
-  conv.v = d.v; // use union to convert between hexadecimal and floating-point views
-  printf("%s: ", msg);  // print out nicely
-  printf("0x%08lx_%08lx = %g\n", (conv.v >> 32),(conv.v & 0xFFFFFFFF), conv.d);
-}
-
-void printF128 (char *msg, float128_t q) {
-  qp conv;
-  int i, j;
-  char buf[64];
-  conv.v[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
-  conv.v[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
-  printf("%s: ", msg);  // print out nicely
-  //printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
-  quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
-  printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);    
-}
-
-void printFlags(void) {
-  int NX = softfloat_exceptionFlags % 2;
-  int UF = (softfloat_exceptionFlags >> 1) % 2;
-  int OF = (softfloat_exceptionFlags >> 2) % 2;
-  int DZ = (softfloat_exceptionFlags >> 3) % 2;
-  int NV = (softfloat_exceptionFlags >> 4) % 2;
-  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
-          NX, UF, OF, DZ, NV);
-}
-
-void softfloatInit(void) {
-    // rounding modes: RNE: softfloat_round_near_even
-    //                 RZ:  softfloat_round_minMag
-    //                 RP:  softfloat_round_max
-    //                 RM:  softfloat_round_min
-    softfloat_roundingMode = softfloat_round_near_even; 
-    softfloat_exceptionFlags = 0; // clear exceptions
-    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
-}
-
-int main() {
-  
-  float32_t x, y, z;
-  float32_t r;
-
-  x.v = 0xBFFF988E;
-  y.v = 0x3F8EFFFF;
-  z.v = 0x40010000;
-
-  softfloatInit();
-  printF32("X", x); printF32("Y", y); printF32("Z", z);
-  r = f32_mulAdd(x, y, z);
-  printf("\n");
-  printF32("r", r);
-  
-}
diff --git a/examples/fp/sqrttest/Makefile b/examples/fp/sqrttest/Makefile
index bc07f2939..4d0efe20e 100644
--- a/examples/fp/sqrttest/Makefile
+++ b/examples/fp/sqrttest/Makefile
@@ -3,10 +3,15 @@
 CC     = gcc
 CFLAGS = -O3
 LIBS   = -lm
-LFLAGS = -L.
-IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
-LIBS   = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
+LFLAGS = -L. 
+# Link against the riscv-isa-sim version of SoftFloat rather than 
+# the regular version to get RISC-V NaN behavior
+IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
+LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
+#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
 SRCS   = $(wildcard *.c)
+
 PROGS = $(patsubst %.c,%,$(SRCS))
 
 all:	$(PROGS)
diff --git a/examples/link/link.ld b/examples/link/link.ld
index d5539f7ef..d84c332a1 100644
--- a/examples/link/link.ld
+++ b/examples/link/link.ld
@@ -4,16 +4,14 @@ ENTRY(rvtest_entry_point)
 SECTIONS
 {
   . = 0x80000000;
-  .text : { *(.text.init) *(.text) }
+  .text : { *(.text.init) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
-  . = ALIGN(0x4000);
+  . = ALIGN(0x1000);
   .data : { *(.data) }
   .data.string : { *(.data.string)}
   . = ALIGN(0x1000);
   .bss : { *(.bss) }
-  . = ALIGN(0x1000);
-  .text : { *(.text.main) }
   _end = .;
 }
 
diff --git a/examples/verilog/fulladder/fulladder-batch-coverage.do b/examples/verilog/fulladder/fulladder-batch-coverage.do
deleted file mode 100644
index 324ac9142..000000000
--- a/examples/verilog/fulladder/fulladder-batch-coverage.do
+++ /dev/null
@@ -1,8 +0,0 @@
-# fulladder-batch-coverage.do 
-# David_Harris@hmc.edu 22 May 2023
-vlog fulladder.sv 
-vopt +acc work.testbench -o workopt +cover=sbecf
-vsim workopt -coverage
-run -all
-coverage save -instance /testbench/dut fulladder.ucdb
-quit
\ No newline at end of file
diff --git a/examples/verilog/fulladder/fulladder.sv b/examples/verilog/fulladder/fulladder.sv
index 156bec3f9..4122b4978 100644
--- a/examples/verilog/fulladder/fulladder.sv
+++ b/examples/verilog/fulladder/fulladder.sv
@@ -3,7 +3,6 @@ module testbench();
   logic        a, b, c, s, cout, sexpected, coutexpected;
   logic [31:0] vectornum, errors;
   logic [4:0]  testvectors[10000:0];
-  integer cycle;
 
   // instantiate device under test
   fulladder dut(a, b, c, s, cout);
@@ -12,17 +11,12 @@ module testbench();
   always 
     begin
       clk = 1; #5; clk = 0; #5;
-      cycle = cycle + 1;
-      $display("cycle: %x vectornum %x testvectors[vectornum]: %b", cycle, vectornum, testvectors[vectornum]);
     end
 
   // at start of test, load vectors and pulse reset
   initial
     begin
-      $dumpfile("fulladder.vcd");
-      $dumpvars;
       $readmemb("fulladder.tv", testvectors);
-      cycle = 0;
       vectornum = 0; errors = 0;
       reset = 1; #22; reset = 0;
     end
@@ -42,14 +36,12 @@ module testbench();
         errors = errors + 1;
       end
       vectornum = vectornum + 1;
-      //if (testvectors[vectornum] === 5'bx) begin 
-      if (vectornum === 10) begin 
+      if (testvectors[vectornum] === 5'bx) begin 
         $display("%d tests completed with %d errors", 
 	           vectornum, errors);
-        $finish;
+        $stop;
       end
     end
-
 endmodule
 
 module fulladder(input  logic a, b, c,
diff --git a/examples/verilog/fulladder/verilate b/examples/verilog/fulladder/verilate
deleted file mode 100755
index f1efcc74c..000000000
--- a/examples/verilog/fulladder/verilate
+++ /dev/null
@@ -1,3 +0,0 @@
-verilator --binary --top-module testbench --trace fulladder.sv
-obj_dir/Vtestbench
-
diff --git a/fpga/README.md b/fpga/README.md
index 249df565b..3f9853c72 100644
--- a/fpga/README.md
+++ b/fpga/README.md
@@ -1,71 +1,46 @@
-Wally supports the following boards
+The FPGA currently only targets the VCU118 board.
 
-1. ArtyA7
-2. vcu108
-3. vcu118 (Do not recommend.)
+* Build Process
 
-# Quick Start
-
-## Build FPGA
-
-```bash
 cd generator
-make <board name>
-```
+make 
 
-Example:
-```bash
-make vcu108
-```
+* Description
 
-## Make flash card image
-`ls /dev/sd*` or `ls /dev/mmc*` to see which flash card devices you have.
-Insert the flash card into the reader and `ls /dev/sd*` or `/dev/mmc*` again.  The new device is the one you want to use.  Make sure you select the root device (i.e. `/dev/sdb`) not the partition (i.e. `/dev/sdb1`).
+The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
+axi_clock_converter, and ahblite_axi_bridge.  Then it reads in the 4 IP blocks
+and builds wally.  fpga/src/fpgaTop.v is the top level which instanciates
+wallypipelinedsoc.sv and the 4 IP blocks.  The FPGA include and ILA (In logic
+analyzer) which provides the current instruction PCM, instrM, etc along with
+a large number of debuging signals.
 
-```bash
-cd $WALLY/linux/sd-card
-```
+* Programming the flash card
+You'll need to write the linux image to the flash card.  Use the convert2bin.py 
+script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
+file from QEMU's preload to generate the binary.  Then to copy
+ sudo dd if=ram.bin of=<path to flash card>.
 
-This following script requires root.
+* Loading the FPGA
 
-```bash
-./flash-sd.sh -b <path to buildroot> -d <path to compiled device tree file> <flash card device>
-```
+After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
+gui and open the WallyFPGA.xpr project file.  Open the hardware manager under
+program and debug. Open target and then program with the bit file.
 
-Example with vcu108, buildroot installed to `/opt/riscv/buildroot`, and the flash card is device `/dev/sdc`
+* Test Run
 
-```bash
-./flash-sd.sh -b /opt/riscv/buildroot -d /opt/riscv/buildroot/output/images/wally-vcu108.dtb /dev/sdc
-```
+Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
+status of the reset and ddr4 calibration.  LED 7 should always be lit.
+LED 6 will light if the DDR4 is not calibrated.  LED 6 will be lit once
+wally begins running.
 
-Wait until the the script completes then remove the card.
+Next the bootloader program will copy the flash card into the DDR4 memory.
+When this done the lower 5 LEDs will blink 5 times and then try to boot
+the program loaded in the DDR4 memory at physical address 0x8000_0000.
 
-## FPGA setup
+* Connecting uart
+You'll need to connect both usb cables.  The first connects the FPGA programer
+while the connect connects UART.  UART is configured to use 57600 baud with 
+no parity, 8 data bits, and 1 stop bit.  sudo screen /dev/ttyUSB1 57600 should
+let you view the com port.
 
-For the Arty A7 insert the PMOD daughter board into the right most slot and insert the sd card.
-
-For the VCU108 and VCU118 boards insert the PMOD daughter board into the only PMOD slot on the right side of the boards.
-
-Power on the boards. For Arty A7 just plug in the USB connector. For the VCU boards make sure the power supply is connected and the two usb cables are connected. Flip on the switch.
-The VCU118's on board UART converter does not work. Use a spark fun FTDI usb to UART adapter and plug into the mail PMOD on the right side of the board.  Also the level sifters on the
-VCU118 do not work correctly with the digilent sd PMOD board.  We have a custom board which works instead.
-
-```bash
-cd $WALLY/fpga/generator
-vivado &
-```
-
-Open the design in the current directory `WallyFPGA.xpr`.
-
-Then click "Open Target" under "PROGRAM AND DEBUG".  Then Program the device.
-
-## Connect to UART
-
-In another terminal `ls /dev/ttyUSB*`. One of these devices will be the UART connected to Wally. You may have to experiment by the running the following command multiple times.
-
-```bash
-screen /dev/ttyUSB1 115200
-```
-
-Swap out the `USB1` for `USB0` or `USB1` as needed.
 
diff --git a/fpga/comport.setup b/fpga/comport.setup
index 462d0be99..cb4108b56 100644
--- a/fpga/comport.setup
+++ b/fpga/comport.setup
@@ -1,3 +1,3 @@
-sudo chown rose:rose /dev/ttyUSB1
+sudo chown ross:ross /dev/ttyUSB1
 stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
 cat /dev/ttyUSB1
diff --git a/fpga/constraints/artyddr3.ucf b/fpga/constraints/artyddr3.ucf
deleted file mode 100644
index 2cba768f8..000000000
--- a/fpga/constraints/artyddr3.ucf
+++ /dev/null
@@ -1,48 +0,0 @@
-NET "ddr3_dq[0]"                             LOC = "K5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[1]"                             LOC = "L3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[2]"                             LOC = "K3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[3]"                             LOC = "L6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[4]"                             LOC = "M3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[5]"                             LOC = "M1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[6]"                             LOC = "L4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[7]"                             LOC = "M2"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[8]"                             LOC = "V4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[9]"                             LOC = "T5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[10]"                            LOC = "U4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[11]"                            LOC = "V5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[12]"                            LOC = "V1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[13]"                            LOC = "T3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[14]"                            LOC = "U3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dq[15]"                            LOC = "R3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dm[0]"                             LOC = "L1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dm[1]"                             LOC = "U1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_dqs_p[0]"                          LOC = "N2"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_dqs_n[0]"                          LOC = "N1"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_dqs_p[1]"                          LOC = "U2"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_dqs_n[1]"                          LOC = "V2"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_addr[13]"                          LOC = "T8"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[12]"                          LOC = "T6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[11]"                          LOC = "U6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[10]"                          LOC = "R6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[9]"                           LOC = "V7"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[8]"                           LOC = "R8"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[7]"                           LOC = "U7"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[6]"                           LOC = "V6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[5]"                           LOC = "R7"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[4]"                           LOC = "N6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[3]"                           LOC = "T1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[2]"                           LOC = "N4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[1]"                           LOC = "M6"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_addr[0]"                           LOC = "R2"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_ba[2]"                             LOC = "P2"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_ba[1]"                             LOC = "P4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_ba[0]"                             LOC = "R1"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_ck_p[0]"                           LOC = "U9"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_ck_n[0]"                           LOC = "V9"      |   IOSTANDARD = DIFF_SSTL15          ;                                 
-NET "ddr3_ras_n"                             LOC = "P3"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_cas_n"                             LOC = "M4"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_we_n"                              LOC = "P5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_reset_n"                           LOC = "K6"      |   IOSTANDARD = LVCMOS15               ;                                 
-NET "ddr3_cke[0]"                            LOC = "N5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_odt[0]"                            LOC = "R5"      |   IOSTANDARD = SSTL15               ;                                 
-NET "ddr3_cs_n[0]"                           LOC = "U8"      |   IOSTANDARD = SSTL15               ;                        
diff --git a/fpga/constraints/big-debug-spi.xdc b/fpga/constraints/big-debug-spi.xdc
deleted file mode 100644
index 4584d7d0d..000000000
--- a/fpga/constraints/big-debug-spi.xdc
+++ /dev/null
@@ -1,263 +0,0 @@
-create_debug_core u_ila_0 ila
-
-
-
-
-set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCLK}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCIn}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCS[0]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/InterruptPending[1]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteInc}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOEmpty}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadInc}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/SDCCmd}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitReg[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitLoad}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SCLKenable} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/EndOfFrame}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/NextState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/BitNum[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/ContinueTransmit}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptrnext[3]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitRegLoaded}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/SPICLK}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 9 [get_debug_ports u_ila_0/probe33]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteInc}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadInc}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe36]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe37]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveWatermark[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe38]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveReadWatermarkLevel[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe39]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOFull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOEmpty}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe42]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/raddr[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe43]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/waddr[2]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe44]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptr[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe45]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[3]} ]]
-
-
-
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
-
diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
deleted file mode 100644
index 924cd1aea..000000000
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ /dev/null
@@ -1,296 +0,0 @@
-# The main clocks are all autogenerated by the Xilinx IP
-# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
-# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
-# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
-
-#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
-create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
-
-##### clock #####
-set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
-set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
-
-##### RVVI Ethernet ####
-# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
-set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
-set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
-set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
-set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
-set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
-set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
-set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
-set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
-set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
-set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
-set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
-set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
-set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
-set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
-set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
-set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
-set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
-
-create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
-create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
-
-set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
-set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
-
-##### GPI ####
-set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
-set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
-set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
-set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
-set_max_delay -from [get_ports {GPI[*]}] 20.000
-
-##### GPO ####
-set_property PACKAGE_PIN G6 [get_ports {GPO[0]}]
-set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
-set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
-set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
-set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
-set_max_delay -to [get_ports {GPO[*]}] 20.000
-
-set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
-set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
-
-
-##### UART #####
-# *** IOSTANDARD is probably wrong
-set_property PACKAGE_PIN A9 [get_ports UARTSin]
-set_property PACKAGE_PIN D10 [get_ports UARTSout]
-set_max_delay -from [get_ports UARTSin] 20.000
-set_max_delay -to [get_ports UARTSout] 20.000
-set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
-set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
-set_property DRIVE 4 [get_ports UARTSout]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
-set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
-set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
-
-
-##### reset #####
-#************** reset is inverted
-set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
-set_max_delay -from [get_ports resetn] 20.000
-set_false_path -from [get_ports resetn]
-set_property PACKAGE_PIN C2 [get_ports resetn]
-set_property IOSTANDARD LVCMOS33 [get_ports resetn]
-
-
-set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
-set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
-set_max_delay -from [get_ports south_reset] 20.000
-set_false_path -from [get_ports south_reset]
-set_property PACKAGE_PIN D9 [get_ports south_reset]
-set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
-
-
-
-##### SD Card I/O #####
-#***** may have to switch to Pmod JB or JC.
-#set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
-#set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
-#set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
-#set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
-#set_property PACKAGE_PIN F3 [get_ports SDCCLK]
-#set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
-#set_property PACKAGE_PIN H2 [get_ports {SDCCD}]
-
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}]
-#set_property PULLUP true [get_ports {SDCDat[3]}]
-#set_property PULLUP true [get_ports {SDCDat[2]}]
-#set_property PULLUP true [get_ports {SDCDat[1]}]
-#set_property PULLUP true [get_ports {SDCDat[0]}]
-#set_property PULLUP true [get_ports {SDCCmd}]
-#set_property PULLUP true [get_ports {SDCCD}]
-
-# SDCDat[3]
-set_property PACKAGE_PIN D4 [get_ports SDCCS]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
-set_property PULLTYPE PULLUP [get_ports SDCCS]
-# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
-# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
-# SDCDat[0]
-set_property PACKAGE_PIN F4 [get_ports SDCIn]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
-set_property PULLTYPE PULLUP [get_ports SDCIn]
-set_property PACKAGE_PIN F3 [get_ports SDCCLK]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
-set_property PULLTYPE PULLUP [get_ports SDCCLK]
-set_property PACKAGE_PIN D3 [get_ports SDCCmd]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
-set_property PULLTYPE PULLUP [get_ports SDCCmd]
-set_property PACKAGE_PIN H2 [get_ports SDCCD]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
-set_property PULLTYPE PULLUP [get_ports SDCCD]
-set_property PACKAGE_PIN G2 [get_ports SDCWP]
-set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
-set_property PULLTYPE PULLUP [get_ports SDCWP]
-
-
-set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
-set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
-
-set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
-set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
-
-set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
-set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
-
-set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
-
-
-#set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10
-
-set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
-
-# *********************************
-#set_property DCI_CASCADE {64} [get_iobanks 65]
-#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
-
-# ddr3
-
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
-set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
-set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
-set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
-set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
-set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
-set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
-set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
-set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
-set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
-set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
-set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
-
-
-set_property PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
-set_property PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
-set_property PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
-set_property PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
-set_property PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
-set_property PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
-set_property PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
-set_property PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
-set_property PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
-set_property PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
-set_property PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
-set_property PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
-set_property PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
-set_property PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
-set_property PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
-set_property PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
-set_property PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
-set_property PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
-set_property PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
-set_property PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
-set_property PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
-set_property PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
-set_property PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
-set_property PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
-set_property PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
-set_property PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
-set_property PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
-set_property PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
-set_property PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
-set_property PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
-set_property PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
-set_property PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
-set_property PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
-set_property PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
-set_property PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
-set_property PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
-set_property PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
-set_property PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
-set_property PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
-set_property PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
-set_property PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
-set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]
-set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]
-set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]
-set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]
-set_property PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
-set_property PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
-set_property PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
-
-
-#create_clock -period 50.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 25.000}
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
-#set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
-#create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
-#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]
diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc
index 2fb191e6c..cbb70db92 100644
--- a/fpga/constraints/constraints-vcu108.xdc
+++ b/fpga/constraints/constraints-vcu108.xdc
@@ -1,14 +1,16 @@
 # The main clocks are all autogenerated by the Xilinx IP
-# mmcm_clkout1 is the 50Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
+# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
 # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
 # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
 
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
 ##### GPI ####
 set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
 set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
 set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
-#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
-#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
+set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
@@ -55,7 +57,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port
 set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
 set_max_delay -from [get_ports reset] 15.000
 set_false_path -from [get_ports reset]
-set_property PACKAGE_PIN A10 [get_ports {reset}]
+set_property PACKAGE_PIN E34 [get_ports {reset}]
 set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
 
 
@@ -66,6 +68,15 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
 set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
 
+
+##### calib #####
+set_property PACKAGE_PIN BA37 [get_ports calib]
+set_property IOSTANDARD LVCMOS12 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
+set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
+
+
 ##### ahblite_resetn #####
 set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
 set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
@@ -81,40 +92,40 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
 
 
 ##### SD Card I/O #####
-
-# create the generated SPICLK
-create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
-
-set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCS}]
-set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCS}]
-set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCIn}]
-set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCIn}]
-set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCD}]
-set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCD}]
-set_input_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCWP}]
-set_input_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCWP}]
-set_output_delay -clock [get_clocks SPISDCClock] -max 5.0 [get_ports {SDCCmd}]
-set_output_delay -clock [get_clocks SPISDCClock] -min -5.0 [get_ports {SDCCmd}]
-set_output_delay -clock [get_clocks SPISDCClock] -max 2.000 [get_ports SDCCLK]
-set_output_delay -clock [get_clocks SPISDCClock] -min -2.000 [get_ports SDCCLK]
+set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
+set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
+set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
+set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
+set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
+set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
+set_property PULLUP true [get_ports {SDCDat[3]}]
+set_property PULLUP true [get_ports {SDCDat[2]}]
+set_property PULLUP true [get_ports {SDCDat[1]}]
+set_property PULLUP true [get_ports {SDCDat[0]}]
+set_property PULLUP true [get_ports {SDCCmd}]
 
 
-set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
-set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}]
-set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}]
-set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}]
-set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
 
-set_property PACKAGE_PIN AW12 [get_ports SDCCD]
-set_property IOSTANDARD LVCMOS18 [get_ports SDCCD]
-set_property PULLTYPE PULLUP [get_ports SDCCD]
-set_property PACKAGE_PIN BC16 [get_ports SDCWP]
-set_property IOSTANDARD LVCMOS18 [get_ports SDCWP]
-set_property PULLTYPE PULLUP [get_ports SDCWP]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
+
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
 
 
 
-#set_property DCI_CASCADE {64} [get_iobanks 65]
+set_property DCI_CASCADE {64} [get_iobanks 65]
 set_property INTERNAL_VREF 0.9 [get_iobanks 65]
 
 
@@ -243,8 +254,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
 set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
 
 
-#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
-#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
 
 
 
diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc
index 5de479951..3bd9db8b3 100644
--- a/fpga/constraints/constraints-vcu118.xdc
+++ b/fpga/constraints/constraints-vcu118.xdc
@@ -3,6 +3,8 @@
 # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
 # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
 
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
 ##### GPI ####
 set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
 set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}]
@@ -14,7 +16,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports {GPI[1]}]
 set_property IOSTANDARD LVCMOS18 [get_ports {GPI[0]}]
 set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
 set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
-set_max_delay -from [get_ports {GPI[*]}] 20.000
+set_max_delay -from [get_ports {GPI[*]}] 10.000
 
 ##### GPO ####
 set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
@@ -27,7 +29,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
 set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
-set_max_delay -to [get_ports {GPO[*]}] 20.000
+set_max_delay -to [get_ports {GPO[*]}] 10.000
 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
 set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
 
@@ -37,8 +39,8 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por
 set_property PACKAGE_PIN L31 [get_ports UARTSin]
 #set_property PACKAGE_PIN BB21 [get_ports UARTSout]
 set_property PACKAGE_PIN P29 [get_ports UARTSout]
-set_max_delay -from [get_ports UARTSin] 20.000
-set_max_delay -to [get_ports UARTSout] 20.000
+set_max_delay -from [get_ports UARTSin] 10.000
+set_max_delay -to [get_ports UARTSout] 10.000
 set_property IOSTANDARD LVCMOS12 [get_ports UARTSin]
 set_property IOSTANDARD LVCMOS12 [get_ports UARTSout]
 set_property DRIVE 6 [get_ports UARTSout]
@@ -55,7 +57,7 @@ set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_port
 set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
 set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
 set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
-set_max_delay -from [get_ports reset] 20.000
+set_max_delay -from [get_ports reset] 15.000
 set_false_path -from [get_ports reset]
 set_property PACKAGE_PIN L19 [get_ports {reset}]
 set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
@@ -104,11 +106,6 @@ set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
 set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
 set_property PACKAGE_PIN AV15 [get_ports SDCCLK]
 set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}]
-
-set_property PACKAGE_PIN AT15 [get_ports {SDCCD}]
-set_property IOSTANDARD LVCMOS18 [get_ports {SDCCD}]
-set_property PULLUP true [get_ports {SDCCD}]
-
 set_property PULLUP true [get_ports {SDCDat[3]}]
 set_property PULLUP true [get_ports {SDCDat[2]}]
 set_property PULLUP true [get_ports {SDCDat[1]}]
@@ -116,17 +113,17 @@ set_property PULLUP true [get_ports {SDCDat[0]}]
 set_property PULLUP true [get_ports {SDCCmd}]
 
 
-set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
-set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
 
-set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}]
-set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
 
 
-set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}]
-set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 6.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
 
-set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
 
 
 
@@ -256,7 +253,7 @@ set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
 
 
 
-set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
 
 
 set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 327d8dd7c..69d295f85 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -17,1228 +17,1134 @@ endgroup
 connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe6]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe10]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe11]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe12]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe13]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe14]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe15]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe16]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SCAUSE_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 5 [get_debug_ports u_ila_0/probe17]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe18]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe19]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 63 [get_debug_ports u_ila_0/probe20]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe21]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 6 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe23]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe24]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
+connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe25]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]]
+connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe26]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe27]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe28]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
+connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe29]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
+connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe30]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
+connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe31]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
+connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe34]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe35]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe36]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe37]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe38]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe39]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe40]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe41]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe42]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe43]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe44]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe45]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe46]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe47]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe48]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe49]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe50]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe51]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPPredWrongE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe52]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe53]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe54]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe55]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]]
+connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe56]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]]
+connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe57]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe58]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]]
+connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe59]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]]
+connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe60]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]]
+connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe61]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]]
+connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe62]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
+connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe63]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
+connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe64]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe65]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe66]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe67]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe68]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]]
+connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe69]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause08_in]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe70]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe71]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
 
 # StallW is StallM.  trying to connect to StallW causes issues.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe72]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe73]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
+connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe74]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]]
+connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe75]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe76]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]]
+connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe77]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]]
+connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe78]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
+connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe79]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe80]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe81]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
+connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe82]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
+connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe83]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 53 [get_debug_ports u_ila_0/probe84]
+set_property port_width 64 [get_debug_ports u_ila_0/probe84]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
-
+connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWDATA[0]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[1]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[2]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[3]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[4]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[5]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[6]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[7]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[8]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[9]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[10]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[11]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[12]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[13]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[14]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[15]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[16]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[17]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[18]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[19]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[20]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[21]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[22]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[23]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[24]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[25]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[26]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[27]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[28]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[29]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[30]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[31]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[32]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[33]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[34]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[35]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[36]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[37]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[38]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[39]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[40]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[41]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[42]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[43]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[44]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[45]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[46]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[47]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[48]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[49]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[50]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[51]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[52]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[53]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[54]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[55]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[56]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[57]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[58]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[59]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[60]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[61]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[62]} {wallypipelinedsoc/core/ebu.ebu/HWDATA[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe85]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
+connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe86]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]]
+connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe87]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]]
+connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe88]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
+connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe89]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
+connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe90]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
+connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe91]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
+connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe92]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
+connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe93]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]]
+connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe94]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]]
+connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe95]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]]
+connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe96]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]]
+connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe97]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]]
+connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe98]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
+connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 56 [get_debug_ports u_ila_0/probe100]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
 
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe101]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe102]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
+connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.spillsupport/CurrState[0] ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe103]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 7 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe105]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe106]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
-connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe107]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
-connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe108]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
-connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]]
+connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe109]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
-connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
+connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe110]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
-connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
+connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe111]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
-connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]]
+connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe112]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
-connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
+connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe113]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
-connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
+connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe114]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
-connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
+connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe115]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
-connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
+connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe116]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
-connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
+connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe117]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
-connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
+connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe118]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
-connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
+connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe119]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
-connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
+connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe120]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
-connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
+connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 11 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe122]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
-connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
+connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 2 [get_debug_ports u_ila_0/probe123]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
-connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
+connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe124]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
-connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe125]
+set_property port_width 64 [get_debug_ports u_ila_0/probe125]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
-connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
+connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe126]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
-connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe130]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
-connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/csrs.SSCRATCH_REGW[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe131]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
-connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
+connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe132]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
-connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
+connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe133]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
-connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
+connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe134]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
-connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
+connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe135]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
-connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
+connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe136]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
-connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
+connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
-connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
+connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe138]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
-connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+
+# UART Signals -------------------------------------------------------
 
-# ============== AXI SDC STUFF ================
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe139]
+set_property port_width 8 [get_debug_ports u_ila_0/probe139]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
-connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe140]
+set_property port_width 8 [get_debug_ports u_ila_0/probe140]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
-connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 25 [get_debug_ports u_ila_0/probe141]
+set_property port_width 3 [get_debug_ports u_ila_0/probe141]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
-connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 28 [get_debug_ports u_ila_0/probe142]
+set_property port_width 1 [get_debug_ports u_ila_0/probe142]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
-connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe143]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
-connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe144]
+set_property port_width 1 [get_debug_ports u_ila_0/probe144]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
-connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe145]
+set_property port_width 2 [get_debug_ports u_ila_0/probe145]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
-connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe146]
+set_property port_width 2 [get_debug_ports u_ila_0/probe146]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
-connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe147]
+set_property port_width 8 [get_debug_ports u_ila_0/probe147]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
-connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe148]
+set_property port_width 8 [get_debug_ports u_ila_0/probe148]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
-connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe149]
+set_property port_width 8 [get_debug_ports u_ila_0/probe149]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
-connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 5 [get_debug_ports u_ila_0/probe150]
+set_property port_width 8 [get_debug_ports u_ila_0/probe150]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150]
-connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]]
+connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe151]
+set_property port_width 8 [get_debug_ports u_ila_0/probe151]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151]
-connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]]
+connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe152]
+set_property port_width 8 [get_debug_ports u_ila_0/probe152]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152]
-connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]]
+connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 5 [get_debug_ports u_ila_0/probe153]
+set_property port_width 11 [get_debug_ports u_ila_0/probe153]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153]
-connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]]
+connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe154]
+set_property port_width 4 [get_debug_ports u_ila_0/probe154]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
-connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]]
+connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 16 [get_debug_ports u_ila_0/probe155]
+set_property port_width 4 [get_debug_ports u_ila_0/probe155]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
-connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]]
+connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe156]
+set_property port_width 5 [get_debug_ports u_ila_0/probe156]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
-connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]]
+connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe157]
+set_property port_width 8 [get_debug_ports u_ila_0/probe157]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
-connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]]
+connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe158]
+set_property port_width 8 [get_debug_ports u_ila_0/probe158]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
-connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]]
+connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe159]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
-connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]]
+connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe160]
+set_property port_width 8 [get_debug_ports u_ila_0/probe160]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
-connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]]
+connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe161]
+set_property port_width 8 [get_debug_ports u_ila_0/probe161]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
-connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]]
+connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe162]
+set_property port_width 8 [get_debug_ports u_ila_0/probe162]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
-connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]]
+connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe163]
+set_property port_width 8 [get_debug_ports u_ila_0/probe163]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
-connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]]
+connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe164]
+set_property port_width 8 [get_debug_ports u_ila_0/probe164]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
-connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]]
+connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe165]
+set_property port_width 8 [get_debug_ports u_ila_0/probe165]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
-connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]]
+connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 8 [get_debug_ports u_ila_0/probe166]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
-connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]]
+connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe167]
+set_property port_width 8 [get_debug_ports u_ila_0/probe167]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
-connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]]
+connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe168]
+set_property port_width 8 [get_debug_ports u_ila_0/probe168]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
-connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]]
+connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe169]
+set_property port_width 8 [get_debug_ports u_ila_0/probe169]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
-connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]]
+connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe170]
+set_property port_width 8 [get_debug_ports u_ila_0/probe170]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
-connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]]
+connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe171]
+set_property port_width 8 [get_debug_ports u_ila_0/probe171]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
-connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]]
+connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe172]
+set_property port_width 8 [get_debug_ports u_ila_0/probe172]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
-connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]]
+connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe173]
+set_property port_width 1 [get_debug_ports u_ila_0/probe173]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173]
-connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]]
+connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe174]
+set_property port_width 1 [get_debug_ports u_ila_0/probe174]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174]
-connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]]
+connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe175]
+set_property port_width 1 [get_debug_ports u_ila_0/probe175]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175]
-connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]]
+connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe176]
+set_property port_width 1 [get_debug_ports u_ila_0/probe176]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176]
-connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]]
+connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe177]
+set_property port_width 4 [get_debug_ports u_ila_0/probe177]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177]
-connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]]
+connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe178]
+set_property port_width 4 [get_debug_ports u_ila_0/probe178]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178]
-connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]]
+connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe179]
+set_property port_width 12 [get_debug_ports u_ila_0/probe179]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179]
-connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]]
+connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe180]
+set_property port_width 7 [get_debug_ports u_ila_0/probe180]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180]
-connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]]
+connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe181]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181]
-connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]]
+connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe182]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182]
-connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]]
+connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe183]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183]
-connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]]
+connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe184]
+set_property port_width 1 [get_debug_ports u_ila_0/probe184]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184]
-connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]]
+connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe185]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185]
-connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]]
+connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe186]
+set_property port_width 4 [get_debug_ports u_ila_0/probe186]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186]
-connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]]
+connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 4 [get_debug_ports u_ila_0/probe187]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187]
-connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]]
+connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe188]
+set_property port_width 3 [get_debug_ports u_ila_0/probe188]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188]
-connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]]
+connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe189]
+set_property port_width 31 [get_debug_ports u_ila_0/probe189]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189]
-connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]]
+connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe190]
+set_property port_width 16 [get_debug_ports u_ila_0/probe190]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190]
-connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]]
+connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe191]
+set_property port_width 16 [get_debug_ports u_ila_0/probe191]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191]
-connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]]
+connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe192]
+set_property port_width 8 [get_debug_ports u_ila_0/probe192]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192]
-connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]]
+connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe193]
+set_property port_width 1 [get_debug_ports u_ila_0/probe193]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193]
-connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
+connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe194]
+set_property port_width 1 [get_debug_ports u_ila_0/probe194]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194]
-connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
+connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe195]
+set_property port_width 1 [get_debug_ports u_ila_0/probe195]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195]
-connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]]
+connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe196]
+set_property port_width 1 [get_debug_ports u_ila_0/probe196]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196]
-connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]]
+connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe197]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197]
-connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]]
+connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe198]
+set_property port_width 11 [get_debug_ports u_ila_0/probe198]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198]
-connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]]
+connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe199]
+set_property port_width 11 [get_debug_ports u_ila_0/probe199]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199]
-connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]]
+connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe200]
+set_property port_width 11 [get_debug_ports u_ila_0/probe200]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200]
-connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]]
+connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe201]
+set_property port_width 11 [get_debug_ports u_ila_0/probe201]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201]
-connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]]
+connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe202]
+set_property port_width 11 [get_debug_ports u_ila_0/probe202]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202]
-connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]]
+connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe203]
+set_property port_width 11 [get_debug_ports u_ila_0/probe203]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203]
-connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]]
+connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe204]
+set_property port_width 11 [get_debug_ports u_ila_0/probe204]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204]
-connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]]
+connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe205]
+set_property port_width 11 [get_debug_ports u_ila_0/probe205]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205]
-connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]]
+connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe206]
+set_property port_width 11 [get_debug_ports u_ila_0/probe206]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206]
-connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]]
+connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe207]
+set_property port_width 11 [get_debug_ports u_ila_0/probe207]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207]
-connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]]
+connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe208]
+set_property port_width 11 [get_debug_ports u_ila_0/probe208]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208]
-connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]]
+connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe209]
+set_property port_width 1 [get_debug_ports u_ila_0/probe209]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209]
-connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]]
+connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe210]
+set_property port_width 1 [get_debug_ports u_ila_0/probe210]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210]
-connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]]
+connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe211]
+set_property port_width 12 [get_debug_ports u_ila_0/probe211]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211]
-connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]]
+connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe212]
+set_property port_width 12 [get_debug_ports u_ila_0/probe212]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212]
-connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]]
+connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe213]
+set_property port_width 12 [get_debug_ports u_ila_0/probe213]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213]
-connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]]
+connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe214]
+set_property port_width 70 [get_debug_ports u_ila_0/probe214]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214]
-connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]]
+connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 3 [get_debug_ports u_ila_0/probe215]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215]
-connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]]
+connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe216]
+set_property port_width 10 [get_debug_ports u_ila_0/probe216]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216]
-connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][10]} ]]
+connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe217]
+set_property port_width 6 [get_debug_ports u_ila_0/probe217]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217]
-connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]]
+connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe218]
+set_property port_width 6 [get_debug_ports u_ila_0/probe218]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218]
-connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]]
+connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe219]
+set_property port_width 7 [get_debug_ports u_ila_0/probe219]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219]
-connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]]
+connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe220]
+set_property port_width 7 [get_debug_ports u_ila_0/probe220]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220]
-connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]]
+connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe221]
+set_property port_width 3 [get_debug_ports u_ila_0/probe221]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221]
-connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][2]} ]]
+connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe222]
+set_property port_width 3 [get_debug_ports u_ila_0/probe222]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222]
-connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][2]} ]]
+connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe223]
+set_property port_width 53 [get_debug_ports u_ila_0/probe223]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223]
-connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]]
+connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe224]
+set_property port_width 53 [get_debug_ports u_ila_0/probe224]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe224]
-connect_debug_port u_ila_0/probe224 [get_nets [list {m01_axi_rvalid}]]
+connect_debug_port u_ila_0/probe224 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
 
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe225]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe225]
-connect_debug_port u_ila_0/probe225 [get_nets [list {m01_axi_rready}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe226]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe226]
-connect_debug_port u_ila_0/probe226 [get_nets [list {SDCout_axi_awaddr[0]} {SDCout_axi_awaddr[1]} {SDCout_axi_awaddr[2]} {SDCout_axi_awaddr[3]} {SDCout_axi_awaddr[4]} {SDCout_axi_awaddr[5]} {SDCout_axi_awaddr[6]} {SDCout_axi_awaddr[7]} {SDCout_axi_awaddr[8]} {SDCout_axi_awaddr[9]} {SDCout_axi_awaddr[10]} {SDCout_axi_awaddr[11]} {SDCout_axi_awaddr[12]} {SDCout_axi_awaddr[13]} {SDCout_axi_awaddr[14]} {SDCout_axi_awaddr[15]} {SDCout_axi_awaddr[16]} {SDCout_axi_awaddr[17]} {SDCout_axi_awaddr[18]} {SDCout_axi_awaddr[19]} {SDCout_axi_awaddr[20]} {SDCout_axi_awaddr[21]} {SDCout_axi_awaddr[22]} {SDCout_axi_awaddr[23]} {SDCout_axi_awaddr[24]} {SDCout_axi_awaddr[25]} {SDCout_axi_awaddr[26]} {SDCout_axi_awaddr[27]} {SDCout_axi_awaddr[28]} {SDCout_axi_awaddr[29]} {SDCout_axi_awaddr[30]} {SDCout_axi_awaddr[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe227]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe227]
-connect_debug_port u_ila_0/probe227 [get_nets [list {SDCout_axi_awlen[0]} {SDCout_axi_awlen[1]} {SDCout_axi_awlen[2]} {SDCout_axi_awlen[3]} {SDCout_axi_awlen[4]} {SDCout_axi_awlen[5]} {SDCout_axi_awlen[6]} {SDCout_axi_awlen[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe228]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe228]
-connect_debug_port u_ila_0/probe228 [get_nets [list {SDCout_axi_awvalid}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe229]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe229]
-connect_debug_port u_ila_0/probe229 [get_nets [list {SDCout_axi_awready}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe230]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe230]
-connect_debug_port u_ila_0/probe230 [get_nets [list {SDCout_axi_wdata[0]} {SDCout_axi_wdata[1]} {SDCout_axi_wdata[2]} {SDCout_axi_wdata[3]} {SDCout_axi_wdata[4]} {SDCout_axi_wdata[5]} {SDCout_axi_wdata[6]} {SDCout_axi_wdata[7]} {SDCout_axi_wdata[8]} {SDCout_axi_wdata[9]} {SDCout_axi_wdata[10]} {SDCout_axi_wdata[11]} {SDCout_axi_wdata[12]} {SDCout_axi_wdata[13]} {SDCout_axi_wdata[14]} {SDCout_axi_wdata[15]} {SDCout_axi_wdata[16]} {SDCout_axi_wdata[17]} {SDCout_axi_wdata[18]} {SDCout_axi_wdata[19]} {SDCout_axi_wdata[20]} {SDCout_axi_wdata[21]} {SDCout_axi_wdata[22]} {SDCout_axi_wdata[23]} {SDCout_axi_wdata[24]} {SDCout_axi_wdata[25]} {SDCout_axi_wdata[26]} {SDCout_axi_wdata[27]} {SDCout_axi_wdata[28]} {SDCout_axi_wdata[29]} {SDCout_axi_wdata[30]} {SDCout_axi_wdata[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe231]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe231]
-connect_debug_port u_ila_0/probe231 [get_nets [list {SDCout_axi_wlast}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe232]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe232]
-connect_debug_port u_ila_0/probe232 [get_nets [list {SDCout_axi_wvalid}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe233]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe233]
-connect_debug_port u_ila_0/probe233 [get_nets [list {SDCout_axi_wready}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe234]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe234]
-connect_debug_port u_ila_0/probe234 [get_nets [list {SDCout_axi_bresp[0]} {SDCout_axi_bresp[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe235]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe235]
-connect_debug_port u_ila_0/probe235 [get_nets [list {SDCout_axi_bvalid}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe236]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe236]
-connect_debug_port u_ila_0/probe236 [get_nets [list {SDCout_axi_bready}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 28 [get_debug_ports u_ila_0/probe237]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe237]
-connect_debug_port u_ila_0/probe237 [get_nets [list {axiSDC/sd_data_master0/watchdog[0]} {axiSDC/sd_data_master0/watchdog[1]} {axiSDC/sd_data_master0/watchdog[2]} {axiSDC/sd_data_master0/watchdog[3]} {axiSDC/sd_data_master0/watchdog[4]} {axiSDC/sd_data_master0/watchdog[5]} {axiSDC/sd_data_master0/watchdog[6]} {axiSDC/sd_data_master0/watchdog[7]} {axiSDC/sd_data_master0/watchdog[8]} {axiSDC/sd_data_master0/watchdog[9]} {axiSDC/sd_data_master0/watchdog[10]} {axiSDC/sd_data_master0/watchdog[11]} {axiSDC/sd_data_master0/watchdog[12]} {axiSDC/sd_data_master0/watchdog[13]} {axiSDC/sd_data_master0/watchdog[14]} {axiSDC/sd_data_master0/watchdog[15]} {axiSDC/sd_data_master0/watchdog[16]} {axiSDC/sd_data_master0/watchdog[17]} {axiSDC/sd_data_master0/watchdog[18]} {axiSDC/sd_data_master0/watchdog[19]} {axiSDC/sd_data_master0/watchdog[20]} {axiSDC/sd_data_master0/watchdog[21]} {axiSDC/sd_data_master0/watchdog[22]} {axiSDC/sd_data_master0/watchdog[23]} {axiSDC/sd_data_master0/watchdog[24]} {axiSDC/sd_data_master0/watchdog[25]} {axiSDC/sd_data_master0/watchdog[26]} {axiSDC/sd_data_master0/watchdog[27]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe238]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe238]
-connect_debug_port u_ila_0/probe238 [get_nets [list {axiSDC/data_busy}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe239]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe239]
-connect_debug_port u_ila_0/probe239 [get_nets [list {axiSDC/sd_data_master0/en_tx_fifo}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe240]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe240]
-connect_debug_port u_ila_0/probe240 [get_nets [list {axiSDC/sd_data_master0/fifo_empty}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe241]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe241]
-connect_debug_port u_ila_0/probe241 [get_nets [list {axiSDC/sd_data_master0/bus_cycle}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe242]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe242]
-connect_debug_port u_ila_0/probe242 [get_nets [list {axiSDC/sd_data_serial_host0/blkcnt_reg[0]} {axiSDC/sd_data_serial_host0/blkcnt_reg[1]} {axiSDC/sd_data_serial_host0/blkcnt_reg[2]} {axiSDC/sd_data_serial_host0/blkcnt_reg[3]} {axiSDC/sd_data_serial_host0/blkcnt_reg[4]} {axiSDC/sd_data_serial_host0/blkcnt_reg[5]} {axiSDC/sd_data_serial_host0/blkcnt_reg[6]} {axiSDC/sd_data_serial_host0/blkcnt_reg[7]} {axiSDC/sd_data_serial_host0/blkcnt_reg[8]} {axiSDC/sd_data_serial_host0/blkcnt_reg[9]} {axiSDC/sd_data_serial_host0/blkcnt_reg[10]} {axiSDC/sd_data_serial_host0/blkcnt_reg[11]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe243]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe243]
-connect_debug_port u_ila_0/probe243 [get_nets [list {SDCIntr}]]
diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc
deleted file mode 100644
index e8a7e061f..000000000
--- a/fpga/constraints/debug4.xdc
+++ /dev/null
@@ -1,749 +0,0 @@
-create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 5 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe36]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe37]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe38]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe39]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe42]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe43]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe44]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe45]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe46]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe47]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe48]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe49]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe50]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe51]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe52]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe53]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe54]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe55]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe56]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe57]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe58]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe59]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe60]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe61]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe62]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 7 [get_debug_ports u_ila_0/probe63]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe64]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe65]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe66]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe67]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe68]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe69]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe70]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe71]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
-
-# StallW is StallM.  trying to connect to StallW causes issues.
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe72]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe73]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe74]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe75]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe76]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe77]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe78]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe79]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe80]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe81]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe82]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe83]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 53 [get_debug_ports u_ila_0/probe84]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe85]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe86]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe87]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe88]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe89]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe90]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe91]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe92]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe93]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe94]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe95]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe96]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe97]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe98]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe99]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 56 [get_debug_ports u_ila_0/probe100]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe101]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe102]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe103]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 7 [get_debug_ports u_ila_0/probe104]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe105]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe106]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
-connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe107]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
-connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe108]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
-connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe109]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
-connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe110]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
-connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe111]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
-connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe112]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
-connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe113]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
-connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe114]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
-connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe115]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
-connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe116]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
-connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe117]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
-connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe118]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
-connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe119]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
-connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe120]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
-connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 11 [get_debug_ports u_ila_0/probe121]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe122]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
-connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe123]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
-connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe124]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
-connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe125]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
-connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe126]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
-connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe127]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe128]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe129]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe130]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
-connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe131]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
-connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe132]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
-connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe133]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
-connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe134]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
-connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe135]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
-connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe136]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
-connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe137]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
-connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe138]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
-connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 49 [get_debug_ports u_ila_0/probe139]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
-connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[0]}  {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/PTE[53]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe140]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
-connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidNonLeafPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe141]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
-connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidLeafPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe142]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
-connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/ValidPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe143]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
-connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/LeafPTE}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 48 [get_debug_ports u_ila_0/probe144]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
-connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]}  {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]]
diff --git a/fpga/constraints/debug6.xdc b/fpga/constraints/debug6.xdc
deleted file mode 100644
index 88ae08ef8..000000000
--- a/fpga/constraints/debug6.xdc
+++ /dev/null
@@ -1,549 +0,0 @@
-create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 6 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe36]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe37]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe38]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe39]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe42]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe43]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 7 [get_debug_ports u_ila_0/probe44]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe45]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe46]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe47]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe48]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe49]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
-
-# StallW is StallM.  trying to connect to StallW causes issues.
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe50]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe51]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe52]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe53]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe54]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe55]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe56]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe57]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe58]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe59]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe60]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
-connect_debug_port u_ila_0/probe60 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 53 [get_debug_ports u_ila_0/probe61]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
-connect_debug_port u_ila_0/probe61 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe62]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
-connect_debug_port u_ila_0/probe62 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe63]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
-connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe64]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
-connect_debug_port u_ila_0/probe64 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe65]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
-connect_debug_port u_ila_0/probe65 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe66]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
-connect_debug_port u_ila_0/probe66 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe67]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
-connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe68]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
-connect_debug_port u_ila_0/probe68 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe69]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
-connect_debug_port u_ila_0/probe69 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe70]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe71]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
-connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe72]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
-connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe73]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
-connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe74]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
-connect_debug_port u_ila_0/probe74 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe75]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
-connect_debug_port u_ila_0/probe75 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 56 [get_debug_ports u_ila_0/probe76]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
-connect_debug_port u_ila_0/probe76 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
-
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe77]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
-connect_debug_port u_ila_0/probe77 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe78]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
-connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe79]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
-connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 7 [get_debug_ports u_ila_0/probe80]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
-connect_debug_port u_ila_0/probe80 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe81]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
-connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe82]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
-connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe83]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
-connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe84]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
-connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe85]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
-connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe86]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
-connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe87]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
-connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe88]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe89]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
-connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe90]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
-connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe91]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
-connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe92]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
-connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe93]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe94]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
-connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe95]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
-connect_debug_port u_ila_0/probe95 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe96]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
-connect_debug_port u_ila_0/probe96 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe97]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
-connect_debug_port u_ila_0/probe97 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe98]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
-connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe99]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
-connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 49 [get_debug_ports u_ila_0/probe100]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
-connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/lsu/PTE[0]}  {wallypipelinedsoc/core/lsu/PTE[3]} {wallypipelinedsoc/core/lsu/PTE[4]} {wallypipelinedsoc/core/lsu/PTE[5]} {wallypipelinedsoc/core/lsu/PTE[6]} {wallypipelinedsoc/core/lsu/PTE[10]} {wallypipelinedsoc/core/lsu/PTE[11]} {wallypipelinedsoc/core/lsu/PTE[12]} {wallypipelinedsoc/core/lsu/PTE[13]} {wallypipelinedsoc/core/lsu/PTE[14]} {wallypipelinedsoc/core/lsu/PTE[15]} {wallypipelinedsoc/core/lsu/PTE[16]} {wallypipelinedsoc/core/lsu/PTE[17]} {wallypipelinedsoc/core/lsu/PTE[18]} {wallypipelinedsoc/core/lsu/PTE[19]} {wallypipelinedsoc/core/lsu/PTE[20]} {wallypipelinedsoc/core/lsu/PTE[21]} {wallypipelinedsoc/core/lsu/PTE[22]} {wallypipelinedsoc/core/lsu/PTE[23]} {wallypipelinedsoc/core/lsu/PTE[24]} {wallypipelinedsoc/core/lsu/PTE[25]} {wallypipelinedsoc/core/lsu/PTE[26]} {wallypipelinedsoc/core/lsu/PTE[27]} {wallypipelinedsoc/core/lsu/PTE[28]} {wallypipelinedsoc/core/lsu/PTE[29]} {wallypipelinedsoc/core/lsu/PTE[30]} {wallypipelinedsoc/core/lsu/PTE[31]} {wallypipelinedsoc/core/lsu/PTE[32]} {wallypipelinedsoc/core/lsu/PTE[33]} {wallypipelinedsoc/core/lsu/PTE[34]} {wallypipelinedsoc/core/lsu/PTE[35]} {wallypipelinedsoc/core/lsu/PTE[36]} {wallypipelinedsoc/core/lsu/PTE[37]} {wallypipelinedsoc/core/lsu/PTE[38]} {wallypipelinedsoc/core/lsu/PTE[39]} {wallypipelinedsoc/core/lsu/PTE[40]} {wallypipelinedsoc/core/lsu/PTE[41]} {wallypipelinedsoc/core/lsu/PTE[42]} {wallypipelinedsoc/core/lsu/PTE[43]} {wallypipelinedsoc/core/lsu/PTE[44]} {wallypipelinedsoc/core/lsu/PTE[45]} {wallypipelinedsoc/core/lsu/PTE[46]} {wallypipelinedsoc/core/lsu/PTE[47]} {wallypipelinedsoc/core/lsu/PTE[48]} {wallypipelinedsoc/core/lsu/PTE[49]} {wallypipelinedsoc/core/lsu/PTE[50]} {wallypipelinedsoc/core/lsu/PTE[51]} {wallypipelinedsoc/core/lsu/PTE[52]} {wallypipelinedsoc/core/lsu/PTE[53]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe101]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
-connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidNonLeafPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe102]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
-connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidLeafPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe103]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
-connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidPTE}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe104]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/LeafPTE}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 48 [get_debug_ports u_ila_0/probe105]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
-connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]}  {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]]
diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt
deleted file mode 100644
index 9df1e86c3..000000000
--- a/fpga/constraints/marked_debug.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic                 InstrM
-lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic       MemRWM
-mmu/hptw.sv: logic	   SATP_REGW
-uncore/uartPC16550D.sv : logic MCR
-uncore/uartPC16550D.sv : logic FCR
-uncore/uartPC16550D.sv : logic MSR
-uncore/uartPC16550D.sv : logic DTRb
-uncore/uartPC16550D.sv : logic INTR
-uncore/uartPC16550D.sv : logic RXRDYb
-uncore/uartPC16550D.sv : logic TXRDYb
-uncore/uartPC16550D.sv : logic RXerrIP
-uncore/uartPC16550D.sv : logic IER
-uncore/uartPC16550D.sv : logic LSR
-uncore/uartPC16550D.sv : logic SCR
-uncore/uartPC16550D.sv : statetype txstate
-uncore/uartPC16550D.sv : logic RBR
-uncore/uartPC16550D.sv : logic rxparityerr
-uncore/uartPC16550D.sv : logic LCR
-uncore/uartPC16550D.sv : logic intrID
-uncore/uartPC16550D.sv : logic rxdataavailintr
-uncore/uartPC16550D.sv : logic fifoenabled
-uncore/uartPC16550D.sv : logic rxfifoentries
-uncore/uartPC16550D.sv : logic txsrfull
-uncore/uartPC16550D.sv : logic txhrfull
-uncore/uartPC16550D.sv : logic txfifofull
-uncore/uartPC16550D.sv : logic txfifotail
-uncore/uartPC16550D.sv : logic txfifohead
-uncore/uartPC16550D.sv : logic rxfifotriggered
-uncore/uartPC16550D.sv : logic rxdataready
-privileged/privdec.sv : logic wfiM
-privileged/privdec.sv : logic wfiW
-privileged/privdec.sv : logic WFITimeoutM
-uncore/plic_apb.sv : logic requests
-uncore/plic_apb.sv : logic intInProgress
-uncore/plic_apb.sv : logic intPending
-uncore/plic_apb.sv : logic intClaim
diff --git a/fpga/constraints/marked_debug_all.txt b/fpga/constraints/marked_debug_all.txt
deleted file mode 100644
index 1ddec51c9..000000000
--- a/fpga/constraints/marked_debug_all.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-lsu/lsu.sv: logic      IEUAdrM
-lsu/lsu.sv: logic      WriteDataM
-lsu/lsu.sv: logic        LSUHADDR
-lsu/lsu.sv: logic        HRDATA
-lsu/lsu.sv: logic        LSUHWDATA
-lsu/lsu.sv: logic       LSUHREADY
-lsu/lsu.sv: logic       LSUHWRITE
-lsu/lsu.sv: logic        LSUHSIZE
-lsu/lsu.sv: logic        LSUHBURST
-lsu/lsu.sv: logic        LSUHTRANS
-lsu/lsu.sv: logic        LSUHWSTRB
-lsu/lsu.sv: logic      IHAdrM
-ieu/regfile.sv: logic    rf
-ieu/datapath.sv: logic                 RegWriteW
-hazard/hazard.sv: logic	         BPPredWrongE
-hazard/hazard.sv: logic	         LoadStallD
-hazard/hazard.sv: logic          FCvtIntStallD
-hazard/hazard.sv: logic	         DivBusyE
-hazard/hazard.sv: logic	         EcallFaultM
-hazard/hazard.sv: logic          WFIStallM
-hazard/hazard.sv: logic	        StallF
-hazard/hazard.sv: logic	        FlushD
-cache/cachefsm.sv:   statetype CurrState
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic            SrcAM
-wally/wallypipelinedcore.sv: logic                 InstrM
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic           MemRWM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic     WriteDataM
-wally/wallypipelinedcore.sv: logic     IEUAdrM
-wally/wallypipelinedcore.sv: logic   HRDATA
-ifu/spill.sv:    statetype CurrState
-ifu/ifu.sv: logic    				IFUStallF
-ifu/ifu.sv: logic     IFUHADDR
-ifu/ifu.sv: logic     	HRDATA
-ifu/ifu.sv: logic      IFUHREADY
-ifu/ifu.sv: logic     IFUHWRITE
-ifu/ifu.sv: logic      IFUHSIZE
-ifu/ifu.sv: logic      IFUHBURST
-ifu/ifu.sv: logic      IFUHTRANS
-ifu/ifu.sv: logic     PCF
-ifu/ifu.sv: logic                 PCNextF
-ifu/ifu.sv: logic            PCPF
-ifu/ifu.sv: logic     PostSpillInstrRawF
-mmu/hptw.sv: logic	   ITLBWriteF
-mmu/hptw.sv:	 statetype WalkerState
-mmu/hptw.sv: logic  ValidPTE
-privileged/csrs.sv: logic        CSRSReadValM
-privileged/csrs.sv: logic        SEPC_REGW
-privileged/csrs.sv: logic        MIP_REGW
-privileged/csrs.sv: logic      SSCRATCH_REGW
-privileged/csrs.sv: logic     SCAUSE_REGW      
-privileged/csr.sv: logic    CSRReadValM  
-privileged/csr.sv: logic    CSRSrcM
-privileged/csr.sv: logic    CSRWriteValM
-privileged/csr.sv: logic    MSTATUS_REGW
-privileged/trap.sv: logic      		   InstrMisalignedFaultM
-privileged/trap.sv: logic      		   BreakpointFaultM
-privileged/trap.sv: logic      		   LoadAccessFaultM
-privileged/trap.sv: logic      		   LoadPageFaultM
-privileged/trap.sv: logic      		   mretM
-privileged/trap.sv: logic      MIP_REGW
-privileged/trap.sv: logic           PendingIntsM
-privileged/privileged.sv: logic      CSRReadM
-privileged/privileged.sv: logic    InterruptM
-privileged/csrc.sv: logic      HPMCOUNTER_REGW
-privileged/csri.sv: logic       MExtInt
-privileged/csri.sv: logic        MIP_REGW_writeabl
-privileged/csrm.sv: logic        	     MIP_REGW
-privileged/csrm.sv: logic       MEPC_REGW
-privileged/csrm.sv: logic     MEDELEG_REGW
-privileged/csrm.sv: logic          MIDELEG_REGW
-privileged/csrm.sv: logic      MSCRATCH_REGW
-privileged/csrm.sv: logic       MCAUSE_REGW
-uncore/uart_apb.sv: logic                  SIN
-uncore/uart_apb.sv: logic                 SOUT
-uncore/uart_apb.sv: logic                 OUT1b
-uncore/uartPC16550D.sv: logic       RBR
-uncore/uartPC16550D.sv: logic        FCR
-uncore/uartPC16550D.sv: logic        IER
-uncore/uartPC16550D.sv: logic        MCR
-uncore/uartPC16550D.sv: logic    	   baudpulse
-uncore/uartPC16550D.sv:     statetype rxstate
-uncore/uartPC16550D.sv: logic     					rxfifo
-uncore/uartPC16550D.sv: logic     					txfifo
-uncore/uartPC16550D.sv: logic    					rxfifohead
-uncore/uartPC16550D.sv: logic    					rxfifoentries
-uncore/uartPC16550D.sv: logic       					RXBR
-uncore/uartPC16550D.sv: logic     					rxtimeoutcnt
-uncore/uartPC16550D.sv: logic      						rxparityerr
-uncore/uartPC16550D.sv: logic   						rxdataready
-uncore/uartPC16550D.sv: logic   						rxfifoempty
-uncore/uartPC16550D.sv: logic     					rxdata
-uncore/uartPC16550D.sv: logic     					RXerrbit
-uncore/uartPC16550D.sv: logic     					rxfullbitunwrapped
-uncore/uartPC16550D.sv: logic     					txdata
-uncore/uartPC16550D.sv: logic    						txnextbit
-uncore/uartPC16550D.sv: logic    						txfifoempty
-uncore/uartPC16550D.sv: logic   						fifoenabled
-uncore/uartPC16550D.sv: logic   						RXerr
-uncore/uartPC16550D.sv: logic   						THRE
-uncore/uartPC16550D.sv: logic   						rxdataavailintr
-uncore/uartPC16550D.sv: logic    					intrID
-uncore/uncore.sv: logic HSELEXTSDCD
-uncore/plic_apb.sv: logic                    MExtInt
-uncore/plic_apb.sv: logic     Din
-uncore/plic_apb.sv: logic             requests
-uncore/plic_apb.sv: logic        intPriority
-uncore/plic_apb.sv: logic             intInProgress
-uncore/plic_apb.sv: logic           intThreshold
-uncore/plic_apb.sv: logic             intEn
-uncore/plic_apb.sv: logic           intClaim
-uncore/plic_apb.sv: logic        irqMatrix
-uncore/plic_apb.sv: logic           priorities_with_irqs
-uncore/plic_apb.sv: logic           max_priority_with_irqs
-uncore/plic_apb.sv: logic          irqs_at_max_priority
-uncore/plic_apb.sv: logic           threshMask
-uncore/clint_apb.sv: logic      MTIME
-uncore/clint_apb.sv: logic         MTIMECMP
-ebu/ebu.sv: logic     HCLK
-ebu/ebu.sv: logic      HREADY
-ebu/ebu.sv: logic      HRESP
-ebu/ebu.sv: logic      HADDR
-ebu/ebu.sv: logic     HWRITE
-ebu/ebu.sv: logic      HSIZE
-ebu/ebu.sv: logic      HBURST
-ebu/ebu.sv: logic      HPROT
-ebu/ebu.sv: logic      HTRANS
-ebu/ebu.sv: logic     HMASTLOC
-ebu/buscachefsm.sv:   busstatetype CurrState
-ebu/busfsm.sv:   busstatetype CurrState
diff --git a/fpga/constraints/marked_debug_rvvi.txt b/fpga/constraints/marked_debug_rvvi.txt
deleted file mode 100644
index afed3dd23..000000000
--- a/fpga/constraints/marked_debug_rvvi.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic                 InstrM
-lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic        PAdrM
-lsu/lsu.sv: logic        ReadDataM
-lsu/lsu.sv: logic        WriteDataM
-lsu/lsu.sv: logic       MemRWM
-privileged/csrc.sv: logic      HPMCOUNTER_REGW
diff --git a/fpga/constraints/marked_debug_small.txt b/fpga/constraints/marked_debug_small.txt
deleted file mode 100644
index 1d23c29a2..000000000
--- a/fpga/constraints/marked_debug_small.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic                 InstrM
-lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic       MemRWM
-mmu/hptw.sv: logic	   SATP_REGW
diff --git a/fpga/constraints/marked_debug_spi.txt b/fpga/constraints/marked_debug_spi.txt
deleted file mode 100644
index a5ffb3c83..000000000
--- a/fpga/constraints/marked_debug_spi.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic                 InstrM
-lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic       MemRWM
-mmu/hptw.sv: logic	   SATP_REGW
-uncore/uncore.sv: logic SDCCmd
-uncore/uncore.sv: logic SDCCLK
-uncore/uncore.sv: logic SDCIn
-uncore/uncore.sv: logic SDCCS
-uncore/spi_apb.sv: logic InterruptPending
-uncore/spi_apb.sv: logic TransmitFIFOWriteInc
-uncore/spi_apb.sv: logic TransmitFIFOEmpty
-uncore/spi_apb.sv: logic TransmitFIFOReadInc
-uncore/spi_apb.sv: logic TransmitLoad
-uncore/spi_apb.sv: logic ShiftEdge
-uncore/spi_apb.sv: logic SampleEdge
-uncore/spi_apb.sv: logic  ReceiveShiftReg
-uncore/spi_apb.sv: logic TransmitReg
-uncore/spi_apb.sv: logic ShiftIn
-uncore/spi_apb.sv: logic EndOfFrame
-uncore/spi_apb.sv: logic TransmitRegLoaded
-uncore/spi_apb.sv: logic TransmitData
-uncore/spi_apb.sv: logic ReceiveFIFOWriteInc
-uncore/spi_apb.sv: logic ReceiveFIFOReadInc
-uncore/spi_apb.sv: logic ReceiveShiftRegEndian
-uncore/spi_apb.sv: logic ReceiveWatermark
-uncore/spi_apb.sv: logic ReceiveReadWatermarkLevel
-uncore/spi_apb.sv: logic ReceiveData
-uncore/spi_apb.sv: logic ReceiveFIFOFull
-uncore/spi_apb.sv: logic ReceiveFIFOEmpty
-uncore/spi_controller.sv: logic  SCLKenable
-uncore/spi_controller.sv: statetype  CurrState
-uncore/spi_controller.sv: statetype  NextState
-uncore/spi_controller.sv: logic BitNum
-uncore/spi_controller.sv: logic ContinueTransmit
-uncore/spi_controller.sv: logic PhaseOneOffset
-uncore/spi_controller.sv: logic SPICLK
-uncore/spi_fifo.sv: logic rptr
-uncore/spi_fifo.sv: logic rptrnext
-uncore/spi_fifo.sv: logic raddr
-uncore/spi_fifo.sv: logic waddr
diff --git a/fpga/constraints/marked_debug_uart.txt b/fpga/constraints/marked_debug_uart.txt
deleted file mode 100644
index 4ac6b1bc6..000000000
--- a/fpga/constraints/marked_debug_uart.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic                 InstrM
-lsu/lsu.sv: logic        IEUAdrM
-lsu/lsu.sv: logic       MemRWM
-mmu/hptw.sv: logic	   SATP_REGW
-uncore/uartPC16550D.sv : logic MCR
-uncore/uartPC16550D.sv : logic FCR
-uncore/uartPC16550D.sv : logic MSR
-uncore/uartPC16550D.sv : logic DTRb
-uncore/uartPC16550D.sv : logic INTR
-uncore/uartPC16550D.sv : logic RXRDYb
-uncore/uartPC16550D.sv : logic TXRDYb
-uncore/uartPC16550D.sv : logic RXerrIP
-uncore/uartPC16550D.sv : logic IER
-uncore/uartPC16550D.sv : logic LSR
-uncore/uartPC16550D.sv : logic SCR
-uncore/uartPC16550D.sv : statetype txstate
-uncore/uartPC16550D.sv : logic RBR
-uncore/uartPC16550D.sv : logic rxparityerr
-uncore/uartPC16550D.sv : logic LCR
-uncore/uartPC16550D.sv : logic intrID
-uncore/uartPC16550D.sv : logic rxdataavailintr
-uncore/uartPC16550D.sv : logic fifoenabled
-uncore/uartPC16550D.sv : logic rxfifoentries
-uncore/uartPC16550D.sv : logic txsrfull
-uncore/uartPC16550D.sv : logic txhrfull
-uncore/uartPC16550D.sv : logic txfifofull
-uncore/uartPC16550D.sv : logic txfifotail
-uncore/uartPC16550D.sv : logic txfifohead
-uncore/uartPC16550D.sv : logic rxfifotriggered
-uncore/uartPC16550D.sv : logic rxdataready
diff --git a/fpga/constraints/small-debug-rvvi.xdc b/fpga/constraints/small-debug-rvvi.xdc
deleted file mode 100644
index 629cde561..000000000
--- a/fpga/constraints/small-debug-rvvi.xdc
+++ /dev/null
@@ -1,72 +0,0 @@
-create_debug_core u_ila_0 ila
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN true [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-create_debug_port u_ila_0  trig_in
-create_debug_port u_ila_0  trig_in_ack  
-#set_property port_width 1 [get_debug_ports u_ila_0/trig_in]
-#set_property port_width 1 [get_debug_ports u_ila_0/trig_in_ack]
-#set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/trig_in]
-connect_debug_port u_ila_0/trig_in [get_nets IlaTrigger]
-#connect_debug_port u_ila_0/trig_in_ack [get_nets IlaTriggerAck]
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {RVVIStall}]]
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
-
diff --git a/fpga/constraints/small-debug-spi.xdc b/fpga/constraints/small-debug-spi.xdc
deleted file mode 100644
index 5951bdcb8..000000000
--- a/fpga/constraints/small-debug-spi.xdc
+++ /dev/null
@@ -1,196 +0,0 @@
-create_debug_core u_ila_0 ila
-
-
-
-
-set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftIn} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftReg[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SCLKenable} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SampleEdge} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/Active} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/state[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPIOut} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICS[0]} ]] 
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[8]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[9]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[10]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckDiv[11]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SckMode[1]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 9 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftFullDelay} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftRegLoadSingleCycle} ]] 
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftEmpty} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteFull} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadIncrement} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadEmpty} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteIncrement} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadIncrement} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteFull} ]]  
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadEmpty} ]]  
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
diff --git a/fpga/constraints/small-debug-uart.xdc b/fpga/constraints/small-debug-uart.xdc
deleted file mode 100644
index 01e8f9199..000000000
--- a/fpga/constraints/small-debug-uart.xdc
+++ /dev/null
@@ -1,208 +0,0 @@
-create_debug_core u_ila_0 ila
-
-
-
-
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 33 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]}  ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]}  ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 5 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MCR[4]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/FCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/MSR[3]} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/DTRb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/TXRDYb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXerrIP} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LSR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/SCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 11 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[7]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[8]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[9]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RBR[10]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxparityerr} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[3]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[4]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[5]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[6]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/LCR[7]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataavailintr} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe33]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe35]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]]
-
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
diff --git a/fpga/constraints/small-debug-wfi.xdc b/fpga/constraints/small-debug-wfi.xdc
deleted file mode 100644
index e87f3bce9..000000000
--- a/fpga/constraints/small-debug-wfi.xdc
+++ /dev/null
@@ -1,191 +0,0 @@
-create_debug_core u_ila_0 ila
-
-
-
-
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 33 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} } ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]}  ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 8 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]}  ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe8]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiM} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/wfiW} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/INTR ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe13]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifohead[3]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txsrfull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txhrfull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/RXRDYb ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe17]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifofull}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifoempty}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/pmd/WFITimeoutM} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe20]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/requests[12]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe21]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/IER[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe22]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress[12]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 12 [get_debug_ports u_ila_0/probe23]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/intPending[12]}]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe24]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txstate[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxdataready} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe26]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/txfifotail[3]}]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe27]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxstate[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe28]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[2]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifoentries[3]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 3 [get_debug_ports u_ila_0/probe29]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[0]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[1]} {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/intrID[2]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/rxfifotriggered} ]]
-
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/uartgen.uart/uartPC/fifoenabled} ]]
-
-
-
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc
deleted file mode 100644
index b73581ab7..000000000
--- a/fpga/constraints/small-debug.xdc
+++ /dev/null
@@ -1,63 +0,0 @@
-create_debug_core u_ila_0 ila
-
-
-
-
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets CPUCLK]
-
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe7]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
-
-# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
-#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
-connect_debug_port dbg_hub/clk [get_nets CPUCLK]
diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc
deleted file mode 100644
index 0ce1152f3..000000000
--- a/fpga/constraints/vcu-small-debug.xdc
+++ /dev/null
@@ -1,52 +0,0 @@
-create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
-
-set_property port_width 64 [get_debug_ports u_ila_0/probe0]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe1]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 32 [get_debug_ports u_ila_0/probe4]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe5]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
-
-create_debug_port u_ila_0 probe
-set_property port_width 64 [get_debug_ports u_ila_0/probe6]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
-
diff --git a/fpga/debug_notes.org b/fpga/debug_notes.org
new file mode 100644
index 000000000..84952d8c5
--- /dev/null
+++ b/fpga/debug_notes.org
@@ -0,0 +1,16 @@
+* December 12, 2021
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = f884_3803
+PCM = ffff_ffff_8030_8004
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0207_ba03
+PCM = ffff_ffff_8034_89fe
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0016_c383
+PCM = ffff_ffff_8030_7504
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0006_a703
+PCM = ffff_ffff_8028_fa02
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 52e46ec38..b61c51ed5 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -1,101 +1,42 @@
 dst := IP
+sdc_src := ~/repos/sdc.tar.gz
+# vcu118
+#export XILINX_PART := xcvu9p-flga2104-2L-e
+#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
+#export board := vcu118
 
-all: ArtyA7
-
-.PHONY: ArtyA7 vcu118 vcu108
-
-ArtyA7: export XILINX_PART := xc7a100tcsg324-1
-ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
-ArtyA7: export board := ArtyA7
-ArtyA7: export SYSTEMCLOCK := 20000000
-ArtyA7: export MAXSDCCLOCK  :=  5000000
-ArtyA7: FPGA_Arty
-
-vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
-vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
-vcu118: export board := vcu118
-vcu118: export SYSTEMCLOCK := 71000000
-vcu118: export MAXSDCCLOCK  :=  1000000
-vcu118: FPGA_VCU
-
-vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
-vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
-vcu108: export board := vcu108
-vcu108: export SYSTEMCLOCK := 50000000
-vcu108: export MAXSDCCLOCK  := 12500000
-vcu108: FPGA_VCU
-
-# variables computed from config
-EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
-
-EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
+# vcu108
+export XILINX_PART := xcvu095-ffva2104-2-e
+export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
+export board := vcu108
 
 
-.PHONY: FPGA_Arty FPGA_VCU
-FPGA_Arty: PreProcessFiles IP_Arty zsbl
-	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
-FPGA_VCU: PreProcessFiles IP_VCU zsbl
+all: FPGA
+
+FPGA: IP SDC
 	vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
 
-# Generate IP Blocks
-.PHONY: IP_Arty IP_VCU
-IP_VCU: $(dst)/sysrst.log \
-	MEM_VCU \
-	$(dst)/clkconverter.log \
-	$(dst)/ahbaxibridge.log
-IP_Arty: $(dst)/sysrst.log \
-	MEM_Arty \
-	$(dst)/mmcm.log \
-	$(dst)/clkconverter.log \
-	$(dst)/ahbaxibridge.log
+IP: $(dst)/xlnx_proc_sys_reset.log \
+	$(dst)/xlnx_ddr4-$(board).log \
+	$(dst)/xlnx_axi_clock_converter.log \
+	 $(dst)/xlnx_ahblite_axi_bridge.log
 
-# Generate Memory IP Blocks
-.PHONY: MEM_VCU MEM_Arty
-MEM_VCU:
-	$(MAKE) $(dst)/ddr4-$(board).log
-MEM_Arty:
-	$(MAKE) $(dst)/ddr3-$(board).log
+SDC:
+	cp $(sdc_src) ../src/
+	tar xzf ../src/sdc.tar.gz -C ../src
 
-# Copy files and make necessary modifications
-.PHONY: PreProcessFiles
-PreProcessFiles:
-	$(MAKE) -C ../../sim deriv
-	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
-	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
-	cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
-	cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
-	mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
-	cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
-	./insert_debug_comment.sh
-	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
-	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
-
-# build the Zero stage boot loader (ZSBL)
-.PHONY: zsbl
-zsbl:
-	$(MAKE) -C ../zsbl clean
-	SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl 
-
-# Generate Individual IP Blocks
 $(dst)/%.log: %.tcl
 	mkdir -p IP
 	cd IP;\
 	vivado -mode batch -source ../$*.tcl | tee $*.log
 
-# Clean
-.PHONY: cleanIP cleanLogs cleanFPGA cleanAll
 cleanIP:
 	rm -rf IP
+
 cleanLogs:
 	rm -rf  *.jou *.log
+
 cleanFPGA:
 	rm -rf WallyFPGA.* reports sim .Xil
-cleanAll: cleanIP cleanLogs cleanFPGA
 
-# Aliases
-.PHONY: arty artya7 VCU118 VCU108
-arty artya7: ArtyA7
-VCU118: vcu118
-VCU108: vcu108
+cleanAll: cleanIP cleanLogs cleanFPGA
diff --git a/fpga/generator/bootrom.txt b/fpga/generator/bootrom.txt
new file mode 100644
index 000000000..b49f25c09
--- /dev/null
+++ b/fpga/generator/bootrom.txt
@@ -0,0 +1,42 @@
+94e1819300002197
+4281420141014081
+4481440143814301
+4681460145814501
+4881480147814701
+4a814a0149814901
+4c814c014b814b01
+4e814e014d814d01
+0110011b4f814f01
+059b45011161016e
+0004063705fe0010
+05a000ef8006061b
+0ff003930000100f
+4e952e3110060e37
+c602829b0053f2b7
+2023fe02dfe312fd
+829b0053f2b7007e
+fe02dfe312fdc602
+4de31efd000e2023
+059bf1402573fdd0
+0000061705e20870
+0010029b01260613
+11010002806702fe
+84b2842ae426e822
+892ee04aec064505
+06e000ef07e000ef
+979334fd02905563
+07930177d4930204
+4089093394be2004
+04138522008905b3
+19e3014000ef2004
+64a2644260e2fe94
+6749808261056902
+dfed8b8510472783
+2423479110a73823
+10472783674910f7
+20058693ffed8b89
+05a1118737836749
+fed59be3fef5bc23
+1047278367498082
+67c98082dfed8b85
+0000808210a7a023
diff --git a/fpga/generator/ddr3-ArtyA7.tcl b/fpga/generator/ddr3-ArtyA7.tcl
deleted file mode 100644
index 20aed4e9f..000000000
--- a/fpga/generator/ddr3-ArtyA7.tcl
+++ /dev/null
@@ -1,22 +0,0 @@
-
-set partNumber $::env(XILINX_PART)
-set boardName $::env(XILINX_BOARD)
-
-set ipName ddr3
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-# really just these two lines which change
-create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
-
-exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
-exec cp ../xlnx_ddr3-artya7-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
-
-set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/generator/debug/plic.tsm b/fpga/generator/debug/plic.tsm
deleted file mode 100644
index 13edad457..000000000
--- a/fpga/generator/debug/plic.tsm
+++ /dev/null
@@ -1,32 +0,0 @@
-##################################################
-#
-# For info on creating trigger state machines:
-#   1) In the main Vivado menu bar, select
-#      Window > Language Templates
-#   2) In the Templates window, select
-#      Debug > Trigger State Machine
-#   3) Refer to the entry 'Info' for an overview
-#      of the trigger state machine language.
-#
-# More information can be found in this document:
-#
-#   Vivado Design Suite User Guide: Programming
-#   and Debugging (UG908)
-#
-##################################################
-state state_reset:
-    if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h200) then
-        goto state_1;
-    else
-        goto state_reset;
-    endif
-    
-state state_1:
-    if(wallypipelinedsoc/uncoregen.uncore/plic.plic/intInProgress == 12'h000) then
-        goto state_trigger;
-    else
-        goto state_1;
-    endif
-    
-state state_trigger:
-    trigger;
diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh
deleted file mode 100755
index 5f8e3fce1..000000000
--- a/fpga/generator/insert_debug_comment.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/bash
-###########################################
-## insert_debug_comment.sh
-##
-## Written: Rose Thompson ross1728@gmail.com
-## Created: 20 January 2023
-## Modified: 22 April 2024
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org#licenses#SHL-2.1#
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-# This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo
-# Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
-copiedDir="../src/CopiedFiles_do_not_add_to_repo"
-while read line; do
-    readarray -d ":" -t StrArray <<< "$line"
-    file="${copiedDir}/${StrArray[0]}"
-    signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
-    readarray -d " " -t SigArray <<< $signal
-    sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
-    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"`
-    filepath=`find $copiedDir -wholename $file`
-    sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath
-done < ../constraints/marked_debug.txt
diff --git a/fpga/generator/mmcm.tcl b/fpga/generator/mmcm.tcl
deleted file mode 100644
index a791a60b6..000000000
--- a/fpga/generator/mmcm.tcl
+++ /dev/null
@@ -1,31 +0,0 @@
-set partNumber $::env(XILINX_PART)
-set boardName  $::env(XILINX_BOARD)
-set SYSTEMCLOCK $::env(SYSTEMCLOCK)
-set ipName mmcm
-
-set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
-
-create_project $ipName . -force -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
-                        CONFIG.NUM_OUT_CLKS {4} \
-                        CONFIG.CLKOUT2_USED {true} \
-                        CONFIG.CLKOUT3_USED {true} \
-                        CONFIG.CLKOUT4_USED {true} \
-                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
-                        CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
-			CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz \
-                        CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
-                        CONFIG.CLKIN1_JITTER_PS {10.0} \
-                       ] [get_ips $ipName]
-
-#set_property CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz [get_ips $ipName] 
-
-generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/generator/probe b/fpga/generator/probe
deleted file mode 100755
index 8bf807ee1..000000000
--- a/fpga/generator/probe
+++ /dev/null
@@ -1,96 +0,0 @@
-#!/usr/bin/env python3
-###########################################
-## fpgaTop.sv
-##
-## Written: jacob.pease@okstate.edu 06 April 2023
-## Modified: 
-##
-## Purpose: Generates 1 entry in a ILA debugger
-## 
-## A component of the Wally configurable RISC-V project.
-## 
-## Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-##
-## Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-## files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-## modify, merge, publish, distribute, sublicense, and#or sell copies of the Software, and to permit persons to whom the Software 
-## is furnished to do so, subject to the following conditions:
-##
-## The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-##
-## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-## OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-## OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-###########################################
-
-import sys
-
-
-def usage():
-  print("Usage: ./probes name width probenum")
-
-def header():
-  return """create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
-
-def convertLine(x):
-  temp = x.split()
-  temp[1] = int(temp[1])
-  return tuple(temp)
-
-def probeBits( probe ):
-  string = ''
-
-  if (probe[1] > 1):
-    for i in range(probe[1]):
-      if i != (probe[1]-1):
-        string = string + f"{{{probe[0]}[{i}]}} "
-      else:
-        string = string + f"{{{probe[0]}[{i}]}} "
-
-  else:
-    string = f'{{{probe[0]}}}'
-
-  return string
-
-def printProbe( probe, i ):
-  bits = probeBits(probe)
-
-  return (
-      f'create_debug_port u_ila_0 probe\n'
-      f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
-      f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
-      f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
-  )
-
-def main(args):
-  if (len(args) != 3):
-    usage()
-
-  name = args[0]
-  width = int(args[1])
-  probeNum = int(args[2])
-
-
-  probe = (name, width)
-
-  print(printProbe(probe, probeNum))
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 29e3a5a92..b2597f60d 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -3,88 +3,50 @@
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
 set boardSubName [lindex [split ${boardName} :] 1]
-set board $::env(board)
-
-#set partNumber xc7a100tcsg324-1
-#set boardName digilentinc.com:arty-a7-100:part0:1.1
-#set boardSubName arty-a7-100
-#set board ArtyA7
-
-#set partNumber xcvu095-ffva2104-2-e
-#set boardName xilinx.com:vcu108:part0:1.7
-#set boardSubName vcu108
-#set board FPU_VCU
 
 set ipName WallyFPGA
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
-    set_property board_part $boardName [current_project]
-}
+set_property board_part $boardName [current_project]
 
-# read package first
-add_files  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
-#read_verilog -sv  ../src/wallypipelinedsocwrapper.sv
-# then read top level
-if {$board=="ArtyA7"} {
-    add_files  {../src/fpgaTopArtyA7.sv}
-} else {
-    add_files  {../src/fpgaTop.sv}
-}
+read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
+read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
+read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
+read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 
-# read in ip
-import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
-import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
-import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
 
-if {$board=="ArtyA7"} {
-    import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
-    import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
-} else {
-    import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
-}
+read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
+read_verilog  {../src/fpgaTop.v}
+read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
-# read in all other rtl
-add_files [glob -type f  ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
+set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
 
-set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared} [current_fileset]
 
+add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
+set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$boardSubName.xdc]
 
 # define top level
 set_property top fpgaTop [current_fileset]
 
+
 update_compile_order -fileset sources_1
-# This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
+# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
 exec mkdir -p reports/
 exec rm -rf reports/*
 
-
 report_compile_order -constraints > reports/compile_order.rpt
 
 # this is elaboration not synthesis.
-#synth_design -rtl -name rtl_1  -flatten_hierarchy none
+synth_design -rtl -name rtl_1
 
-# apply timing constraint after elaboration
-if {$board=="ArtyA7"} {
-    add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
-    set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$board.xdc]
-} else {
-    add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
-    set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$boardSubName.xdc]
-}
+report_clocks -file reports/clocks.rpt
 
-
-# Temp
-set_param messaging.defaultLimit 100000
-
-# this does synthesis?
-
-launch_runs synth_1 -jobs 16
+# this does synthesis? wtf?
+launch_runs synth_1 -jobs 4
 
 wait_on_run synth_1
 open_run synth_1
 
-report_clocks -file reports/clocks.rpt
 
 check_timing -verbose                                                   -file reports/check_timing.rpt
 report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack   -file reports/timing_WORST_10.rpt
@@ -95,23 +57,15 @@ report_clock_interaction                                                -file re
 
 write_verilog -force -mode funcsim sim/syn-funcsim.v
 
-if {$board=="ArtyA7"} {
-    #source ../constraints/small-debug.xdc
-    #source ../constraints/small-debug-rvvi.xdc
-    source ../constraints/small-debug-wfi.xdc
-} else {
-    #source ../constraints/vcu-small-debug.xdc
-    #source ../constraints/small-debug.xdc
-    #source ../constraints/small-debug.xdc
-    source ../constraints/big-debug-spi.xdc
-}
+
+source ../constraints/debug2.xdc
 
 
 # set for RuntimeOptimized implementation
 #set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
 #set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
 
-launch_runs impl_1 -jobs 16
+launch_runs impl_1
 wait_on_run impl_1
 launch_runs impl_1 -to_step write_bitstream
 wait_on_run impl_1
diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
index 29302832d..0d36926cf 100644
--- a/fpga/generator/wave_config.wcfg
+++ b/fpga/generator/wave_config.wcfg
@@ -3,31 +3,34 @@
    <wave_state>
    </wave_state>
    <db_ref_list>
-      <db_ref>
+      <db_ref path="/home/ross/repos/riscv-wally/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
          <top_modules>
          </top_modules>
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="0"></ZoomStartTime>
-      <ZoomEndTime time="16,430"></ZoomEndTime>
-      <Cursor1Time time="8,209"></Cursor1Time>
+      <ZoomStartTime time="14962fs"></ZoomStartTime>
+      <ZoomEndTime time="14974fs"></ZoomEndTime>
+      <Cursor1Time time="14967fs"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
-      <NameColumnWidth column_width="506"></NameColumnWidth>
-      <ValueColumnWidth column_width="155"></ValueColumnWidth>
+      <NameColumnWidth column_width="400"></NameColumnWidth>
+      <ValueColumnWidth column_width="177"></ValueColumnWidth>
    </column_width_setting>
-   <WVObjectSize size="41" />
+   <WVObjectSize size="32" />
    <wave_markers>
    </wave_markers>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM">
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63:0]</obj_property>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/PCM[63:0]</obj_property>
       <obj_property name="ObjectShortName">PCM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/InstrM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrM[31:0]</obj_property>
       <obj_property name="ObjectShortName">InstrM[31:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -37,37 +40,37 @@
       <obj_property name="label">rd</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[11]">
          <obj_property name="ElementShortName">[11]</obj_property>
          <obj_property name="ObjectShortName">[11]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[10]">
          <obj_property name="ElementShortName">[10]</obj_property>
          <obj_property name="ObjectShortName">[10]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[9]">
          <obj_property name="ElementShortName">[9]</obj_property>
          <obj_property name="ObjectShortName">[9]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[8]">
          <obj_property name="ElementShortName">[8]</obj_property>
          <obj_property name="ObjectShortName">[8]</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[7]">
          <obj_property name="ElementShortName">[7]</obj_property>
          <obj_property name="ObjectShortName">[7]</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM">
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrValidM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrValidM</obj_property>
       <obj_property name="ObjectShortName">InstrValidM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM">
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/TrapM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/TrapM</obj_property>
       <obj_property name="ObjectShortName">TrapM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -75,67 +78,66 @@
    <wvobject type="group" fp_name="group468">
       <obj_property name="label">CPU to LSU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
          <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
          <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
          <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
          <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
       <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
       <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
       <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
       <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -148,49 +150,49 @@
    <wvobject type="group" fp_name="group471">
       <obj_property name="label">interrupts</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11:0]</obj_property>
-         <obj_property name="ObjectShortName">MEDELEG_REGW[11:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+         <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
          <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
          <obj_property name="ObjectShortName">InterruptM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11:0]</obj_property>
-      <obj_property name="ObjectShortName">MEDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
       <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM">
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
       <obj_property name="ObjectShortName">InterruptM</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -198,55 +200,55 @@
    <wvobject type="group" fp_name="group463">
       <obj_property name="label">LSU to Bus</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHADDR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHADDR[31:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHBURST">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHBURST[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHREADY">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
          <obj_property name="ObjectShortName">LSUHREADY</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHSIZE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHSIZE[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHWDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">LSUHWDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHWRITE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHWRITE</obj_property>
          <obj_property name="ObjectShortName">LSUHWRITE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -257,9 +259,9 @@
       <obj_property name="label">dcache</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -267,76 +269,75 @@
          <obj_property name="label">dcache fsm</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0]</obj_property>
-      <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-      <obj_property name="label">dcache fsm</obj_property>
-   </wvobject>
    <wvobject type="group" fp_name="group334">
       <obj_property name="label">EBU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HTRANS">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0]</obj_property>
          <obj_property name="ObjectShortName">HTRANS[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HWRITE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWRITE</obj_property>
          <obj_property name="ObjectShortName">HWRITE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HBURST">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HBURST[2:0]</obj_property>
          <obj_property name="ObjectShortName">HBURST[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HSIZE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0]</obj_property>
          <obj_property name="ObjectShortName">HSIZE[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HADDR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HADDR[31:0]</obj_property>
          <obj_property name="ObjectShortName">HADDR[31:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
          <obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ebu.ebu/HWDATA">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0]</obj_property>
+         <obj_property name="ObjectShortName">HWDATA[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HREADY">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HREADY</obj_property>
          <obj_property name="ObjectShortName">HREADY</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/ebu.ebu/HRESP">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ebu.ebu/HRESP</obj_property>
          <obj_property name="ObjectShortName">HRESP</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -345,225 +346,225 @@
    <wvobject type="group" fp_name="group2103">
       <obj_property name="label">uart</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/DTRb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/DTRb</obj_property>
          <obj_property name="ObjectShortName">DTRb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/INTR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/INTR</obj_property>
          <obj_property name="ObjectShortName">INTR</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b</obj_property>
          <obj_property name="ObjectShortName">OUT1b</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b</obj_property>
          <obj_property name="ObjectShortName">OUT2b</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/RTSb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/RTSb</obj_property>
          <obj_property name="ObjectShortName">RTSb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb</obj_property>
          <obj_property name="ObjectShortName">RXRDYb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/SIN">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/SIN</obj_property>
          <obj_property name="ObjectShortName">SIN</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/SOUT">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/SOUT</obj_property>
          <obj_property name="ObjectShortName">SOUT</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb</obj_property>
          <obj_property name="ObjectShortName">TXRDYb</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0]</obj_property>
          <obj_property name="ObjectShortName">DLL[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0]</obj_property>
          <obj_property name="ObjectShortName">DLM[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">FCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled</obj_property>
          <obj_property name="ObjectShortName">fifoenabled</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/IER">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0]</obj_property>
          <obj_property name="ObjectShortName">IER[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0]</obj_property>
          <obj_property name="ObjectShortName">intrID[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">LCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0]</obj_property>
          <obj_property name="ObjectShortName">LSR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0]</obj_property>
          <obj_property name="ObjectShortName">MCR[4:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0]</obj_property>
          <obj_property name="ObjectShortName">MSR[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0]</obj_property>
          <obj_property name="ObjectShortName">RBR[10:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr</obj_property>
          <obj_property name="ObjectShortName">rxdataavailintr</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready</obj_property>
          <obj_property name="ObjectShortName">rxdataready</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP</obj_property>
          <obj_property name="ObjectShortName">RXerrIP</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1</obj_property>
          <obj_property name="ObjectShortName">RXerrIP_1</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0]</obj_property>
          <obj_property name="ObjectShortName">rxfifoentries[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered</obj_property>
          <obj_property name="ObjectShortName">rxfifotriggered</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr</obj_property>
          <obj_property name="ObjectShortName">rxparityerr</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0]</obj_property>
          <obj_property name="ObjectShortName">rxstate[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0]</obj_property>
          <obj_property name="ObjectShortName">SCR[7:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate">
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0]</obj_property>
          <obj_property name="ObjectShortName">txstate[1:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
@@ -573,79 +574,79 @@
    <wvobject type="group" fp_name="group2207">
       <obj_property name="label">faults</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BreakpointFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
          <obj_property name="ObjectShortName">BreakpointFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/EcallFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
          <obj_property name="ObjectShortName">EcallFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM</obj_property>
          <obj_property name="ObjectShortName">IllegalInstrFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">InstrAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM</obj_property>
          <obj_property name="ObjectShortName">InstrPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadMisalignedFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM</obj_property>
          <obj_property name="ObjectShortName">LoadPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoAccessFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoMisalignedFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM</obj_property>
          <obj_property name="ObjectShortName">StoreAmoPageFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -654,65 +655,86 @@
    <wvobject type="group" fp_name="group1735">
       <obj_property name="label">hazards</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BPPredWrongE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BPPredWrongE</obj_property>
+         <obj_property name="ObjectShortName">BPPredWrongE</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/BreakpointFaultM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/BreakpointFaultM</obj_property>
          <obj_property name="ObjectShortName">BreakpointFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/CSRRdStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/CSRRdStallD</obj_property>
          <obj_property name="ObjectShortName">CSRRdStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM</obj_property>
+         <obj_property name="ObjectShortName">CSRWriteFencePendingDEM</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/DivBusyE">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/DivBusyE</obj_property>
+         <obj_property name="ObjectShortName">DivBusyE</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/EcallFaultM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/EcallFaultM</obj_property>
          <obj_property name="ObjectShortName">EcallFaultM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FDivBusyE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FDivBusyE</obj_property>
          <obj_property name="ObjectShortName">FDivBusyE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/IFUStallF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/IFUStallF</obj_property>
          <obj_property name="ObjectShortName">IFUStallF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/LoadStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/LoadStallD</obj_property>
          <obj_property name="ObjectShortName">LoadStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/LSUStallM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/LSUStallM</obj_property>
          <obj_property name="ObjectShortName">LSUStallM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/MDUStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/MDUStallD</obj_property>
          <obj_property name="ObjectShortName">MDUStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StoreStallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StoreStallD</obj_property>
          <obj_property name="ObjectShortName">StoreStallD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
@@ -721,59 +743,75 @@
    <wvobject type="group" fp_name="group1722">
       <obj_property name="label">flush/stall</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD">
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushD</obj_property>
          <obj_property name="ObjectShortName">FlushD</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushE">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushE</obj_property>
          <obj_property name="ObjectShortName">FlushE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushM</obj_property>
          <obj_property name="ObjectShortName">FlushM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushW">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushW</obj_property>
          <obj_property name="ObjectShortName">FlushW</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallD">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallD</obj_property>
+         <obj_property name="ObjectShortName">StallD</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallE">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallE</obj_property>
          <obj_property name="ObjectShortName">StallE</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallF</obj_property>
          <obj_property name="ObjectShortName">StallF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallM</obj_property>
          <obj_property name="ObjectShortName">StallM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">csrs.SCAUSE_REGW[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">MCAUSE_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
@@ -783,180 +821,120 @@
       <obj_property name="label">IFU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
       <obj_property name="isExpanded"></obj_property>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
-         <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="label">icache fsm</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
-         <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
          <obj_property name="ObjectShortName">CurrState[2:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="label">ifu bus fsm</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCNextF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
          <obj_property name="ObjectShortName">PCNextF[63:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF">
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCPF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
          <obj_property name="ObjectShortName">PCPF[55:0]</obj_property>
          <obj_property name="Radix">HEXRADIX</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
-      <obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="label">icache fsm</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
-      <obj_property name="ObjectShortName">CurrState[2:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="label">ifu bus fsm</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
-      <obj_property name="ObjectShortName">PCNextF[63:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
-      <obj_property name="ObjectShortName">PCPF[55:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
    <wvobject type="group" fp_name="group3443">
       <obj_property name="label">TLB</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM">
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBMissM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
          <obj_property name="ObjectShortName">DTLBMissM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBWriteM">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
          <obj_property name="ObjectShortName">DTLBWriteM</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBMissF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
          <obj_property name="ObjectShortName">ITLBMissF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
-      <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF">
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBWriteF">
          <obj_property name="DisplayName">FullPathName</obj_property>
-         <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
          <obj_property name="ObjectShortName">ITLBWriteF</obj_property>
          <obj_property name="LABELRADIX">true</obj_property>
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
-      <obj_property name="ObjectShortName">DTLBMissM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
-      <obj_property name="ObjectShortName">DTLBWriteM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
-      <obj_property name="ObjectShortName">ITLBMissF</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
-      <obj_property name="ObjectShortName">ITLBWriteF</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0]</obj_property>
       <obj_property name="ObjectShortName">MEPC_REGW[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">SEPC_REGW[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[2]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[4]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0">
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0">
       <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0]</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0]</obj_property>
       <obj_property name="ObjectShortName">rf[10]__0[63:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
       <obj_property name="LABELRADIX">true</obj_property>
       <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState">
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3:0]</obj_property>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0]</obj_property>
       <obj_property name="ObjectShortName">WalkerState[3:0]</obj_property>
       <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR">
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
-      <obj_property name="ObjectShortName">LSUHADDR[31:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM">
-      <obj_property name="ElementShortName">wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
-      <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
    </wvobject>
 </wave_config>
diff --git a/fpga/generator/ahbaxibridge.tcl b/fpga/generator/xlnx_ahblite_axi_bridge.tcl
similarity index 72%
rename from fpga/generator/ahbaxibridge.tcl
rename to fpga/generator/xlnx_ahblite_axi_bridge.tcl
index e41eed6ce..6bd252967 100644
--- a/fpga/generator/ahbaxibridge.tcl
+++ b/fpga/generator/xlnx_ahblite_axi_bridge.tcl
@@ -2,12 +2,18 @@
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
 
-set ipName ahbaxibridge
+# vcu118 board
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
+
+# kcu105 board
+#set partNumber  xcku040-ffva1156-2-e
+#set boardName  xilinx.com:kcu105:part0:1.7
+
+set ipName xlnx_ahblite_axi_bridge
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
-    set_property board_part $boardName [current_project]
-}
+set_property board_part $boardName [current_project]
 
 # really just these two lines which change
 create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName
diff --git a/fpga/generator/clkconverter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl
similarity index 89%
rename from fpga/generator/clkconverter.tcl
rename to fpga/generator/xlnx_axi_clock_converter.tcl
index 6a9746504..94303f3d0 100644
--- a/fpga/generator/clkconverter.tcl
+++ b/fpga/generator/xlnx_axi_clock_converter.tcl
@@ -4,12 +4,10 @@ set boardName $::env(XILINX_BOARD)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName clkconverter
+set ipName xlnx_axi_clock_converter
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
-    set_property board_part $boardName [current_project]
-}
+set_property board_part $boardName [current_project]
 
 create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
 
diff --git a/fpga/generator/xlnx_ddr3-artya7-mig.prj b/fpga/generator/xlnx_ddr3-artya7-mig.prj
deleted file mode 100644
index ab7a4252d..000000000
--- a/fpga/generator/xlnx_ddr3-artya7-mig.prj
+++ /dev/null
@@ -1,162 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project NoOfControllers="1">
-
-  
-
-<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
-
-  <ModuleName>mig_7series_0</ModuleName>
-
-  <dci_inouts_inputs>1</dci_inouts_inputs>
-
-  <dci_inputs>1</dci_inputs>
-
-  <Debug_En>OFF</Debug_En>
-
-  <DataDepth_En>1024</DataDepth_En>
-
-  <LowPower_En>ON</LowPower_En>
-
-  <XADC_En>Enabled</XADC_En>
-
-  <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
-
-  <Version>4.2</Version>
-
-  <SystemClock>Single-Ended</SystemClock>
-
-  <ReferenceClock>No Buffer</ReferenceClock>
-
-  <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
-
-  <BankSelectionFlag>FALSE</BankSelectionFlag>
-
-  <InternalVref>1</InternalVref>
-
-  <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
-
-  <dci_cascade>0</dci_cascade>
-
-  <FPGADevice>
-    <selected>7a/xc7a100ti-csg324</selected>
-  </FPGADevice>
-
-  <Controller number="0">
-    <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
-    <TimePeriod>3000</TimePeriod>
-    <VccAuxIO>1.8V</VccAuxIO>
-    <PHYRatio>4:1</PHYRatio>
-    <InputClkFreq>166.666</InputClkFreq>
-    <UIExtraClocks>0</UIExtraClocks>
-    <MMCM_VCO>666</MMCM_VCO>
-    <MMCMClkOut0> 1.000</MMCMClkOut0>
-    <MMCMClkOut1>1</MMCMClkOut1>
-    <MMCMClkOut2>1</MMCMClkOut2>
-    <MMCMClkOut3>1</MMCMClkOut3>
-    <MMCMClkOut4>1</MMCMClkOut4>
-    <DataWidth>16</DataWidth>
-    <DeepMemory>1</DeepMemory>
-    <DataMask>1</DataMask>
-    <ECC>Disabled</ECC>
-    <Ordering>Normal</Ordering>
-    <BankMachineCnt>4</BankMachineCnt>
-    <CustomPart>FALSE</CustomPart>
-    <NewPartName/>
-    <RowAddress>14</RowAddress>
-    <ColAddress>10</ColAddress>
-    <BankAddress>3</BankAddress>
-    <MemoryVoltage>1.35V</MemoryVoltage>
-    <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
-    <PinSelection>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
-      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
-    </PinSelection>
-    <System_Clock>
-      <Pin Bank="Select Bank" PADName="No connect" name="sys_clk_i"/>
-    </System_Clock>
-    <System_Control>
-      <Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
-      <Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
-      <Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
-    </System_Control>
-    <TimingParameters>
-      <Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
-    </TimingParameters>
-    <mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
-    <mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
-    <mrCasLatency name="CAS Latency">5</mrCasLatency>
-    <mrMode name="Mode">Normal</mrMode>
-    <mrDllReset name="DLL Reset">No</mrDllReset>
-    <mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
-    <emrDllEnable name="DLL Enable">Enable</emrDllEnable>
-    <emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
-    <emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
-    <emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
-    <emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
-    <emrPosted name="Additive Latency (AL)">0</emrPosted>
-    <emrOCD name="Write Leveling Enable">Disabled</emrOCD>
-    <emrDQS name="TDQS enable">Enabled</emrDQS>
-    <emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
-    <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
-    <mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
-    <mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
-    <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
-    <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
-    <PortInterface>AXI</PortInterface>
-    <AXIParameters>
-      <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
-      <C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
-      <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
-      <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
-      <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
-    </AXIParameters>
-  </Controller>
-
-
-</Project>
diff --git a/fpga/generator/ddr4-vcu108.tcl b/fpga/generator/xlnx_ddr4-vcu108.tcl
similarity index 93%
rename from fpga/generator/ddr4-vcu108.tcl
rename to fpga/generator/xlnx_ddr4-vcu108.tcl
index 2bd5b7ee0..71f8f06a4 100644
--- a/fpga/generator/ddr4-vcu108.tcl
+++ b/fpga/generator/xlnx_ddr4-vcu108.tcl
@@ -1,13 +1,10 @@
 
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
-set SYSTEMCLOCK $::env(SYSTEMCLOCK)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName ddr4
-
-set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000]
+set ipName xlnx_ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]
@@ -18,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.No_Controller {1} \
 			CONFIG.Phy_Only {Complete_Memory_Controller} \
 			CONFIG.C0.DDR4_PhyClockRatio {4:1} \
-			CONFIG.C0.DDR4_TimePeriod {833} \
+			CONFIG.C0.DDR4_TimePeriod {1200} \
 			CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
 			CONFIG.C0.DDR4_BurstLength {8} \
 			CONFIG.C0.DDR4_BurstType {Sequential} \
-			CONFIG.C0.DDR4_CasLatency {16} \
-			CONFIG.C0.DDR4_CasWriteLatency {12} \
+			CONFIG.C0.DDR4_CasLatency {13} \
+			CONFIG.C0.DDR4_CasWriteLatency {10} \
 			CONFIG.C0.DDR4_Slot {Single} \
 			CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
 			CONFIG.C0.DDR4_DataWidth {64} \
@@ -39,11 +36,14 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_AxiIDWidth {4} \
 			CONFIG.C0.DDR4_AxiAddressWidth {31} \
 			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
+			CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
+			CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
+			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
+			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
 			CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
@@ -106,7 +106,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
 			CONFIG.C0.DDR4_EN_PARITY {false} \
 			CONFIG.C0.DDR4_Enable_LVAUX {false} \
-			CONFIG.C0.DDR4_InputClockPeriod {3332} \
+			CONFIG.C0.DDR4_InputClockPeriod {3359} \
 			CONFIG.C0.DDR4_LR_SKEW_0 {0} \
 			CONFIG.C0.DDR4_LR_SKEW_1 {0} \
 			CONFIG.C0.DDR4_MemoryName {MainMemory} \
@@ -115,7 +115,6 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
 			CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
 			CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
-			CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
 			CONFIG.C0.DDR4_PAR_SKEW {0} \
 			CONFIG.C0.DDR4_Specify_MandD {false} \
 			CONFIG.C0.DDR4_TREFI {0} \
diff --git a/fpga/generator/ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl
similarity index 97%
rename from fpga/generator/ddr4-vcu118.tcl
rename to fpga/generator/xlnx_ddr4-vcu118.tcl
index 057c59c6f..2a0dc21fc 100644
--- a/fpga/generator/ddr4-vcu118.tcl
+++ b/fpga/generator/xlnx_ddr4-vcu118.tcl
@@ -1,13 +1,10 @@
 
 set partNumber $::env(XILINX_PART)
 set boardName $::env(XILINX_BOARD)
-set SYSTEMCLOCK $::env(SYSTEMCLOCK)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName ddr4
-
-set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
+set ipName xlnx_ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]
@@ -41,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ $SYSTEMCLOCK_MHz \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {38} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl
index 2b9d24e70..c3aac1f71 100644
--- a/fpga/generator/xlnx_ddr4.tcl
+++ b/fpga/generator/xlnx_ddr4.tcl
@@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e
 set boardName  xilinx.com:vcu108:part0:1.2
 
 
-set ipName ddr4
+set ipName xlnx_ddr4
 
 create_project $ipName . -force -part $partNumber
 set_property board_part $boardName [current_project]
diff --git a/fpga/generator/sysrst.tcl b/fpga/generator/xlnx_proc_sys_reset.tcl
similarity index 89%
rename from fpga/generator/sysrst.tcl
rename to fpga/generator/xlnx_proc_sys_reset.tcl
index 8225c02d5..c7674c7ec 100644
--- a/fpga/generator/sysrst.tcl
+++ b/fpga/generator/xlnx_proc_sys_reset.tcl
@@ -4,12 +4,10 @@ set boardName $::env(XILINX_BOARD)
 #set partNumber xcvu9p-flga2104-2L-e
 #set boardName  xilinx.com:vcu118:part0:2.4
 
-set ipName sysrst
+set ipName xlnx_proc_sys_reset
 
 create_project $ipName . -force -part $partNumber
-if {$boardName!="ArtyA7"} {
-    set_property board_part $boardName [current_project]
-}
+set_property board_part $boardName [current_project]
 
 # really just these two lines which change
 create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName
diff --git a/fpga/probe b/fpga/probe
deleted file mode 100755
index 1da2081f8..000000000
--- a/fpga/probe
+++ /dev/null
@@ -1,83 +0,0 @@
-#!/usr/bin/env python3
-###########################################
-## probe.sh
-##
-## Written: Jacob Pease jacobpease@protonmail.com
-## Created: 16 August 2023
-## Modified: 16 August 2023
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org#licenses#SHL-2.1#
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-import sys
-
-
-def usage():
-    print("Usage: ./probes name width probenum")
-    exit(1)
-
-def convertLine(x):
-    temp = x.split()
-    temp[1] = int(temp[1])
-    return tuple(temp)
-
-def probeBits( probe ):
-    string = ''
-
-    if (probe[1] > 1):
-        for i in range(probe[1]):
-            if i != (probe[1]-1):
-                string = string + f"{{{probe[0]}[{i}]}} "
-            else:
-                string = string + f"{{{probe[0]}[{i}]}} "
-
-    else:
-        string = f'{{{probe[0]}}}'
-
-    return string
-
-def printProbe( probe, i ):
-    bits = probeBits(probe)
-
-    print(bits)
-
-    return (
-        f'create_debug_port u_ila_0 probe\n'
-        f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
-        f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
-        f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
-    )
-
-def main(args):
-    if (len(args) != 3):
-        usage()
-
-    name = args[0]
-    width = int(args[1])
-    probeNum = int(args[2])
-
-
-    probe = (name, width)
-
-    print(printProbe(probe, probeNum))
-
-if __name__ == '__main__':
-    main(sys.argv[1:])
-
-        
diff --git a/fpga/proberange b/fpga/proberange
deleted file mode 100755
index 2008deee6..000000000
--- a/fpga/proberange
+++ /dev/null
@@ -1,104 +0,0 @@
-#!/usr/bin/env python3
-###########################################
-## proberange.sh
-##
-## Written: Jacob Pease jacobpease@protonmail.com
-## Created: 6 April 2023
-## Modified: 16 August 2023
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org#licenses#SHL-2.1#
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-import sys
-
-
-def usage():
-  print("Usage: ./probes list_of_probes outfile")
-
-def header():
-  return """create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
-
-def convertLine(x):
-  temp = x.split()
-  temp[1] = int(temp[1])
-  temp[2] = int(temp[2])
-  return tuple(temp)
-
-def probeBits( probe ):
-  string = ''
-
-  if (probe[1] > 1):
-    for i in range(probe[1]):
-      if i != (probe[1]-1):
-        string = string + f"{{{probe[0]}[{i}]}} "
-      else:
-        string = string + f"{{{probe[0]}[{i}]}} "
-
-  else:
-    string = f'{{{probe[0]}}}'
-
-  return string
-
-def printProbe( probe,):
-  bits = probeBits(probe)
-
-  return (
-    f'create_debug_port u_ila_0 probe\n'
-    f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{probe[2]}]\n'
-    f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{probe[2]}]\n'
-    f'connect_debug_port u_ila_0/probe{probe[2]} [get_nets [list {bits}]]\n\n'
-  )
-
-def main(args):
-  if (len(args) != 2):
-    usage()
-    exit()
-
-  probeList = []
-
-  with open(args[0]) as probeListFile:
-    probeList = list(map(convertLine, probeListFile.readlines()))
-
-  with open(args[1], 'w') as outfile:
-    # outfile.write(header())
-    # outfile.write("\n\n")
-    for i in range(len(probeList)):
-      outfile.write(printProbe(probeList[i]))
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
-
-
-  
diff --git a/fpga/probes b/fpga/probes
deleted file mode 100755
index c72c6557a..000000000
--- a/fpga/probes
+++ /dev/null
@@ -1,102 +0,0 @@
-#!/usr/bin/env python3
-###########################################
-## probe.sh
-##
-## Written: Jacob Pease jacobpease@protonmail.com
-## Created: 6 April 2023
-## Modified: 16 August 2023
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org#licenses#SHL-2.1#
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-import sys
-
-
-def usage():
-  print("Usage: ./probes list_of_probes outfile")
-
-def header():
-  return """create_debug_core u_ila_0 ila
-
-set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-startgroup 
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
-endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
-
-def convertLine(x):
-  temp = x.split()
-  temp[1] = int(temp[1])
-  return tuple(temp)
-
-def probeBits( probe ):
-  string = ''
-
-  if (probe[1] > 1):
-    for i in range(probe[1]):
-      if i != (probe[1]-1):
-        string = string + f"{{{probe[0]}[{i}]}} "
-      else:
-        string = string + f"{{{probe[0]}[{i}]}} "
-
-  else:
-    string = f'{{{probe[0]}}}'
-
-  return string
-
-def printProbe( probe, i ):
-  bits = probeBits(probe)
-
-  return (
-    f'create_debug_port u_ila_0 probe\n'
-    f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
-    f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
-    f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
-  )
-
-def main(args):
-  if (len(args) != 2):
-    usage()
-    exit()
-
-  probeList = []
-
-  with open(args[0]) as probeListFile:
-    probeList = list(map(convertLine, probeListFile.readlines()))
-
-  with open(args[1], 'w') as outfile:
-    outfile.write(header())
-    outfile.write("\n\n")
-    for i in range(len(probeList)):
-      outfile.write(printProbe(probeList[i], i))
-
-if __name__ == '__main__':
-  main(sys.argv[1:])
-
-
diff --git a/fpga/renumber.py b/fpga/renumber.py
deleted file mode 100755
index 7db8d22a4..000000000
--- a/fpga/renumber.py
+++ /dev/null
@@ -1,34 +0,0 @@
-#!/usr/bin/env python3
-import re
-import sys
-
-
-def usage():
-    print("Usage: ./renumber.py <input xdc file> <output xdc file>")
-
-def main(args):
-    if (len(args) != 2):
-        usage()
-        exit()
-
-    probenum = 0
-    countLines = 1
-        
-    with open(args[0]) as xdcfile, open(args[1], 'w') as outfile:
-        Lines = xdcfile.readlines()
-        for line in Lines:
-            t = re.sub("probe[0-9]+", f"probe{probenum}",line)
-            
-            if line.find("probe") >= 0:
-                countLines = countLines + 1
-                
-            if countLines == 4:
-                countLines = 0
-                probenum = probenum + 1
-
-            outfile.write(t)
-
-
-
-if __name__ == '__main__':
-    main(sys.argv[1:])
diff --git a/fpga/rvvidaemon/Makefile b/fpga/rvvidaemon/Makefile
deleted file mode 100644
index e7a40df63..000000000
--- a/fpga/rvvidaemon/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-all: rvvidaemon
-
-rvvidaemon: rvvidaemon.o
-	gcc $^ $(RISCV)/ImperasDV-OpenHW/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so  -o rvvidaemon
-
-%.o:%.c
-	gcc -I$(RISCV)/ImperasDV-OpenHW/ImpProprietary/include/host -I$(RISCV)/ImperasDV-OpenHW/ImpPublic/include/host/rvvi/ -c $^ -o $@
-
-clean:
-	rm *.o rvvidaemon
diff --git a/fpga/rvvidaemon/rvvidaemon.c b/fpga/rvvidaemon/rvvidaemon.c
deleted file mode 100644
index 3ac9c6f43..000000000
--- a/fpga/rvvidaemon/rvvidaemon.c
+++ /dev/null
@@ -1,443 +0,0 @@
-///////////////////////////////////////////
-// rvvi daemon
-//
-// Written: Rose Thomposn rose@rosethompson.net
-// Created: 31 May 2024
-// Modified: 31 May 2024
-//
-// Purpose: Converts raw socket into rvvi interface to connect into ImperasDV
-// 
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-#include <arpa/inet.h>
-#include <linux/if_packet.h>
-#include <linux/ip.h>
-#include <linux/udp.h>
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <sys/ioctl.h>
-#include <sys/socket.h>
-#include <net/if.h>
-#include <netinet/ether.h>
-#include "rvviApi.h" // *** bug fix me when this file gets included into the correct directory.
-#include "idv/idv.h"
-
-
-#define DEST_MAC0	0x43
-#define DEST_MAC1	0x68
-#define DEST_MAC2	0x11
-#define DEST_MAC3	0x11
-#define DEST_MAC4	0x02
-#define DEST_MAC5	0x45
-
-#define SRC_MAC0	0x54
-#define SRC_MAC1	0x16
-#define SRC_MAC2	0x00
-#define SRC_MAC3	0x00
-#define SRC_MAC4	0x54
-#define SRC_MAC5	0x8F
-
-#define BUF_SIZ		1024
-
-//#define ETHER_TYPE	0x0801  // The type defined in packetizer.sv
-#define ETHER_TYPE	0x5c00  // The type defined in packetizer.sv
-//#define ETHER_TYPE	0x0000  // The type defined in packetizer.sv
-#define DEFAULT_IF	"eno1"
-
-struct sockaddr_ll socket_address;
-uint8_t sendbuf[BUF_SIZ];
-struct ether_header *sendeh = (struct ether_header *) sendbuf;
-int tx_len = 0;
-int sockfd;
-
-typedef struct {
-  uint64_t PC;
-  uint32_t insn;
-  uint64_t Mcycle;
-  uint64_t Minstret;
-  uint8_t Trap : 1;
-  uint8_t PrivilegeMode : 2;
-  uint8_t GPREn : 1;
-  uint8_t FPREn : 1;
-  uint16_t CSRCount : 12;
-  uint8_t GPRReg : 5;
-  uint64_t GPRValue;
-  uint8_t FPRReg : 5;
-  uint64_t FPRValue;
-  uint8_t CSRWen[3];
-  uint16_t CSRReg[3];
-  uint64_t CSRValue[3];
-  
-} RequiredRVVI_t; // total size is 241 bits or 30.125 bytes
-
-typedef struct __attribute__((packed)) {
-  uint64_t PC;
-  uint32_t insn;
-  uint64_t Mcycle;
-  uint64_t Minstret;
-  uint8_t Trap : 1;
-  uint8_t PrivilegeMode : 2;
-  uint8_t GPREn : 1;
-  uint8_t FPREn : 1;
-  uint8_t Pad3: 3;
-  uint16_t CSRCount : 12;
-  uint16_t Pad4 : 4;
-  uint8_t GPRReg : 5;
-  uint8_t PadG3 : 3;
-  uint64_t GPRValue;
-  uint8_t FPRReg : 5;
-  uint8_t PadF3 : 3;
-  uint64_t FPRValue;
-  uint16_t CSR0Wen : 12;
-  uint16_t PadC04 : 4;
-  uint64_t CSR0Value;
-  uint16_t CSR1Wen : 12;
-  uint16_t PadC14 : 4;
-  uint64_t CSR1Value;
-  uint16_t CSR2Wen : 12;
-  uint16_t PadC24 : 4;
-  uint64_t CSR2Value;
-  uint16_t CSR3Wen : 12;
-  uint16_t PadC34 : 4;
-  uint64_t CSR3Value;
-  uint16_t CSR4Wen : 12;
-  uint16_t PadC44 : 4;
-  uint64_t CSR4Value;
-} FixedRequiredRVVI_t; // 904 bits
-
-typedef struct {
-  uint8_t RegAddress : 5;
-  uint64_t RegValue;
-} Reg_t;
-
-void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData);
-void PrintInstructionData(RequiredRVVI_t *InstructionData);
-int ProcessRvviAll(RequiredRVVI_t *InstructionData);
-void set_gpr(int hart, int reg, uint64_t value);
-void set_fpr(int hart, int reg, uint64_t value);
-int state_compare(int hart, uint64_t Minstret);
-
-int main(int argc, char **argv){
-  
-  if(argc != 2){
-    printf("Wrong number of arguments.\n");
-    printf("rvvidaemon <ethernet device>\n");
-    return -1;
-  }
-
-  uint8_t buf[BUF_SIZ];
-  int sockopt;
-  struct ifreq ifopts;	/* set promiscuous mode */
-  struct ether_header *eh = (struct ether_header *) buf;
-  ssize_t headerbytes, numbytes, payloadbytes;
-  
-  /* Open RAW socket to receive frames */
-  if ((sockfd = socket(AF_PACKET, SOCK_RAW, htons(ETHER_TYPE))) == -1) {
-    perror("socket");
-  }
-  printf("Here 0\n");
-
-  /* Set interface to promiscuous mode - do we need to do this every time? */
-  strncpy(ifopts.ifr_name, argv[1], IFNAMSIZ-1);
-  ioctl(sockfd, SIOCGIFFLAGS, &ifopts);
-  printf("Here 1\n");
-  ifopts.ifr_flags |= IFF_PROMISC;
-  ioctl(sockfd, SIOCSIFFLAGS, &ifopts);
-  printf("Here 2\n");
-  if (ioctl(sockfd, SIOCGIFINDEX, &ifopts) < 0)
-    perror("SIOCGIFINDEX");
-  
-  /* Allow the socket to be reused - incase connection is closed prematurely */
-  if (setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &sockopt, sizeof sockopt) == -1) {
-    perror("setsockopt");
-    close(sockfd);
-    exit(EXIT_FAILURE);
-  }
-  printf("Here 3\n");
-  
-  /* Bind to device */
-  if (setsockopt(sockfd, SOL_SOCKET, SO_BINDTODEVICE, argv[1], IFNAMSIZ-1) == -1)	{
-    perror("SO_BINDTODEVICE");
-    close(sockfd);
-    exit(EXIT_FAILURE);
-  }
-  printf("Here 4\n");
-
-  if(!rvviVersionCheck(RVVI_API_VERSION)){
-    printf("Bad RVVI_API_VERSION\n");
-  }
-
-  /* Construct the Ethernet header */
-  memset(sendbuf, 0, BUF_SIZ);
-  sendbuf[0] = DEST_MAC0;
-  sendbuf[1] = DEST_MAC1;
-  sendbuf[2] = DEST_MAC2;
-  sendbuf[3] = DEST_MAC3;
-  sendbuf[4] = DEST_MAC4;
-  sendbuf[5] = DEST_MAC5;
-  sendbuf[6] = SRC_MAC0;
-  sendbuf[7] = SRC_MAC1;
-  sendbuf[8] = SRC_MAC2;
-  sendbuf[9] = SRC_MAC3;
-  sendbuf[10] = SRC_MAC4;
-  sendbuf[11] = SRC_MAC5;
-
-  sendeh->ether_type = htons(ETHER_TYPE);
-  tx_len += sizeof(struct ether_header);
-  /* Packet data */
-  sendbuf[tx_len++] = 't';
-  sendbuf[tx_len++] = 'r';
-  sendbuf[tx_len++] = 'i';
-  sendbuf[tx_len++] = 'g';
-  sendbuf[tx_len++] = 'i';
-  sendbuf[tx_len++] = 'n';
-
-  rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org");
-  rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,"riscv");
-  rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC");
-  rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56);
-  rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6);
-
-  /* Index of the network device */
-  socket_address.sll_ifindex = ifopts.ifr_ifindex;
-  /* Address length*/
-  socket_address.sll_halen = ETH_ALEN;
-  /* Destination MAC */
-  socket_address.sll_addr[0] = DEST_MAC0;
-  socket_address.sll_addr[1] = DEST_MAC1;
-  socket_address.sll_addr[2] = DEST_MAC2;
-  socket_address.sll_addr[3] = DEST_MAC3;
-  socket_address.sll_addr[4] = DEST_MAC4;
-  socket_address.sll_addr[5] = DEST_MAC5;
-
-  int i;
-  printf("buffer: ");
-  for(i=0;i<tx_len;i++){
-    printf("%02hhx ", sendbuf[i]);
-  }
-  printf("\n");
-  printf("sockfd %x\n", sockfd);
-
-  // eventually we want to put the elffiles here
-  rvviRefInit(NULL);
-  rvviRefPcSet(0, 0x1000);
-  
-  // Volatile CSRs
-  rvviRefCsrSetVolatile(0, 0xC00);   // CYCLE
-  rvviRefCsrSetVolatile(0, 0xB00);   // MCYCLE
-  rvviRefCsrSetVolatile(0, 0xC02);   // INSTRET
-  rvviRefCsrSetVolatile(0, 0xB02);   // MINSTRET
-  rvviRefCsrSetVolatile(0, 0xC01);   // TIME
-
-  int iter;
-  for (iter = 0xC03; iter <= 0xC1F; iter++) {
-    rvviRefCsrSetVolatile(0, iter);   // HPMCOUNTERx
-  }
-  // Machine MHPMCOUNTER3 - MHPMCOUNTER31
-  for (iter = 0xB03; iter <= 0xB1F; iter++) {
-    rvviRefCsrSetVolatile(0, iter);   // MHPMCOUNTERx
-  }
-  // cannot predict this register due to latency between
-  // pending and taken
-  rvviRefCsrSetVolatile(0, 0x344);   // MIP
-  rvviRefCsrSetVolatile(0, 0x144);   // SIP
-
-  // set bootrom and bootram as volatile memory
-  rvviRefMemorySetVolatile(0x1000, 0x1FFF);
-  rvviRefMemorySetVolatile(0x2000, 0x2FFF);
-
-  // Privileges for PMA are set in the imperas.ic
-  // volatile (IO) regions are defined here
-  // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
-  rvviRefMemorySetVolatile(0x2000000, 0x2000000 + 0xFFFF);
-  rvviRefMemorySetVolatile(0x10060000, 0x10060000 + 0xFF);
-  rvviRefMemorySetVolatile(0x10000000, 0x10000000 + 0x7);
-  rvviRefMemorySetVolatile(0x0C000000, 0x0C000000 + 0x03FFFFFF);
-  rvviRefMemorySetVolatile(0x00013000, 0x00013000 + 0x7F);
-  rvviRefMemorySetVolatile(0x10040000, 0x10040000 + 0xFFF);
-
-  while(1) {
-    //printf("listener: Waiting to recvfrom...\n");
-    numbytes = recvfrom(sockfd, buf, BUF_SIZ, 0, NULL, NULL);
-    headerbytes = (sizeof(struct ether_header));
-    payloadbytes = numbytes - headerbytes;
-    int result;
-    //printf("listener: got frame %lu bytes\n", numbytes);
-    //printf("payload size: %lu bytes\n", payloadbytes);
-    if (eh->ether_dhost[0] == DEST_MAC0 &&
-        eh->ether_dhost[1] == DEST_MAC1 &&
-        eh->ether_dhost[2] == DEST_MAC2 &&
-        eh->ether_dhost[3] == DEST_MAC3 &&
-        eh->ether_dhost[4] == DEST_MAC4 &&
-        eh->ether_dhost[5] == DEST_MAC5) {
-      //printf("Correct destination MAC address\n");
-      uint64_t PC;
-      uint32_t insn;
-      RequiredRVVI_t InstructionData;
-      DecodeRVVI(buf + headerbytes, payloadbytes, &InstructionData);
-      // now let's drive IDV
-      // start simple just drive and compare PC.
-      PrintInstructionData(&InstructionData);
-      result = ProcessRvviAll(&InstructionData);
-      if(result == -1) break;
-    }
-  }
-
-  printf("Simulation halted due to mismatch\n");
-
-  close(sockfd);
-
-  
-
-  return 0;
-}
-
-int ProcessRvviAll(RequiredRVVI_t *InstructionData){
-  long int found;
-  uint64_t time = InstructionData->Mcycle;
-  uint8_t trap = InstructionData->Trap;
-  uint64_t order = InstructionData->Minstret;
-  int result;
-
-  result = 0;
-  if(InstructionData->GPREn) set_gpr(0, InstructionData->GPRReg, InstructionData->GPRValue);
-  if(InstructionData->FPREn) set_fpr(0, InstructionData->FPRReg, InstructionData->FPRValue);
-
-  if (trap) {
-    rvviDutTrap(0, InstructionData->PC, InstructionData->insn);
-  } else {
-    rvviDutRetire(0, InstructionData->PC, InstructionData->insn, 0);
-  }
-
-  if(!trap) result = state_compare(0, InstructionData->Minstret);
-  // *** set is for nets like interrupts  come back to this.
-  //found = rvviRefNetIndexGet("pc_rdata");
-  //rvviRefNetSet(found, InstructionData->PC, time);
-  return result;
-  
-}
-
-int state_compare(int hart, uint64_t Minstret){
-  uint8_t result = 1;
-  uint8_t stepOk = 0;
-  char buf[80];
-  rvviDutCycleCountSet(Minstret);
-  if(rvviRefEventStep(hart) != 0) {
-    stepOk = 1;
-    result &= rvviRefPcCompare(hart);
-    result &= rvviRefInsBinCompare(hart);
-    result &= rvviRefGprsCompare(hart);
-    result &= rvviRefFprsCompare(hart);
-    result &= rvviRefCsrsCompare(hart);
-  } else {
-    result = 0;
-  }
-
-  if (result == 0) {
-    /* Send packet */
-    if (sendto(sockfd, sendbuf, tx_len, 0, (struct sockaddr*)&socket_address, sizeof(struct sockaddr_ll)) < 0){
-      printf("Send failed\n");
-    }else {
-      printf("send success!\n");
-    }
-
-    sprintf(buf, "MISMATCH @ instruction # %ld\n", Minstret);
-    idvMsgError(buf);
-    return -1;
-  }
-  
-}
-
-void set_gpr(int hart, int reg, uint64_t value){
-  rvviDutGprSet(hart, reg, value);
-}
-
-void set_fpr(int hart, int reg, uint64_t value){
-  rvviDutFprSet(hart, reg, value);
-}
-
-void DecodeRVVI(uint8_t *payload, ssize_t payloadsize, RequiredRVVI_t *InstructionData){
-
-  FixedRequiredRVVI_t *FixedInstructionData = (FixedRequiredRVVI_t *) payload;
-  InstructionData->PC = FixedInstructionData->PC;
-  InstructionData->insn = FixedInstructionData->insn;
-  InstructionData->Mcycle = FixedInstructionData->Mcycle;
-  InstructionData->Minstret = FixedInstructionData->Minstret;
-  InstructionData->Trap = FixedInstructionData->Trap;
-  InstructionData->PrivilegeMode = FixedInstructionData->PrivilegeMode;
-  InstructionData->GPREn = FixedInstructionData->GPREn;
-  InstructionData->FPREn = FixedInstructionData->FPREn;
-  InstructionData->CSRCount = FixedInstructionData->CSRCount;
-  InstructionData->GPRReg = FixedInstructionData->GPRReg;
-  InstructionData->GPRValue = FixedInstructionData->GPRValue;
-  InstructionData->FPRReg = FixedInstructionData->FPRReg;
-  InstructionData->FPRValue = FixedInstructionData->FPRValue;
-
-  
-  InstructionData->CSRReg[0] = FixedInstructionData->CSR0Wen;
-  if(InstructionData->CSRReg[0] != 0) InstructionData->CSRWen[0] = 1;
-  else InstructionData->CSRWen[0] = 0;
-  InstructionData->CSRValue[0] = FixedInstructionData->CSR0Value;
-
-  InstructionData->CSRReg[1] = FixedInstructionData->CSR1Wen;
-  if(InstructionData->CSRReg[1] != 0) InstructionData->CSRWen[1] = 1;
-  else InstructionData->CSRWen[1] = 0;
-  InstructionData->CSRValue[1] = FixedInstructionData->CSR1Value;
-
-  InstructionData->CSRReg[2] = FixedInstructionData->CSR2Wen;
-  if(InstructionData->CSRReg[2] != 0) InstructionData->CSRWen[2] = 1;
-  else InstructionData->CSRWen[2] = 0;
-  InstructionData->CSRValue[2] = FixedInstructionData->CSR2Value;
-
-  //InstructionData->CSRReg[3] = FixedInstructionData->CSR3Wen;
-  InstructionData->CSRReg[3] = 0;
-  if(InstructionData->CSRReg[3] != 0) InstructionData->CSRWen[3] = 1;
-  else InstructionData->CSRWen[3] = 0;
-  InstructionData->CSRValue[3] = FixedInstructionData->CSR3Value;
-
-  //InstructionData->CSRReg[4] = FixedInstructionData->CSR4Wen;
-  InstructionData->CSRReg[4] = 0;
-  if(InstructionData->CSRReg[4] != 0) InstructionData->CSRWen[4] = 1;
-  else InstructionData->CSRWen[4] = 0;
-  InstructionData->CSRValue[4] = FixedInstructionData->CSR4Value;
-} 
-
-void PrintInstructionData(RequiredRVVI_t *InstructionData){
-  int CSRIndex;
-  printf("PC = %lx, insn = %x, Mcycle = %lx, Minstret = %lx, Trap = %hhx, PrivilegeMode = %hhx",
-	 InstructionData->PC, InstructionData->insn, InstructionData->Mcycle, InstructionData->Minstret, InstructionData->Trap, InstructionData->PrivilegeMode);
-  if(InstructionData->GPREn){
-    printf(", GPR[%d] = %lx", InstructionData->GPRReg, InstructionData->GPRValue);
-  }
-  if(InstructionData->FPREn){
-    printf(", FPR[%d] = %lx", InstructionData->FPRReg, InstructionData->FPRValue);
-  }
-  for(CSRIndex = 0; CSRIndex < 3; CSRIndex++){
-    if(InstructionData->CSRWen[CSRIndex]){
-      printf(", CSR[%x] = %lx", InstructionData->CSRReg[CSRIndex], InstructionData->CSRValue[CSRIndex]);
-    }
-  }
-  printf("\n");
-}
diff --git a/fpga/sim/bufgce.sv b/fpga/sim/bufgce.sv
new file mode 100644
index 000000000..becf25eba
--- /dev/null
+++ b/fpga/sim/bufgce.sv
@@ -0,0 +1,11 @@
+module BUFGCE (input logic I, input logic CE, output logic O);
+
+  logic 	CE_Q;
+  always_latch begin
+    if(~I) begin
+      CE_Q <= CE;
+    end
+  end
+  assign O = CE_Q & I;
+
+endmodule
diff --git a/fpga/sim/bufgce_div.sv b/fpga/sim/bufgce_div.sv
new file mode 100644
index 000000000..da2aa059c
--- /dev/null
+++ b/fpga/sim/bufgce_div.sv
@@ -0,0 +1,32 @@
+module BUFGCE_DIV #(parameter string DivideAmt = "1")
+  (input logic I, input logic CLR, input logic CE, output logic O);
+
+  integer PulseCount = 0;
+  logic   Q;
+  
+  always_ff @(posedge I, posedge CLR) begin
+    if(CLR) PulseCount <= 0;
+    else begin
+      if(PulseCount < (DivideAmt.atoi()/2 - 1))
+	PulseCount <= PulseCount + 1;
+      else
+	PulseCount <= 0;
+    end
+  end
+
+  assign zero = PulseCount == 0;
+  
+
+  flopenr #(1) ToggleFlipFLop
+    (.d(~Q),
+     .q(Q),
+     .clk(I),
+     .reset(CLR),                     // reset when told by outside
+     .en(zero));        // only update when counter overflows
+
+  if (DivideAmt != "1")
+    assign O = Q;
+  else
+    assign O = I;
+
+endmodule
diff --git a/fpga/sim/bufgmux.sv b/fpga/sim/bufgmux.sv
new file mode 100644
index 000000000..047a6e529
--- /dev/null
+++ b/fpga/sim/bufgmux.sv
@@ -0,0 +1,4 @@
+module BUFGMUX(input logic I1, input logic I0, input logic S, output logic O);
+
+  assign O = S ? I1 : I0;
+endmodule
diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.v
similarity index 66%
rename from fpga/src/fpgaTop.sv
rename to fpga/src/fpgaTop.v
index a1f4849ca..6a26be74e 100644
--- a/fpga/src/fpgaTop.sv
+++ b/fpga/src/fpgaTop.v
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fpgaTop.sv
 //
-// Written: rose@rosethompson.net November 17, 2021
+// Written: ross1728@gmail.com November 17, 2021
 // Modified: 
 //
 // Purpose: This is a top level for the fpga's implementation of wally.
@@ -24,32 +24,27 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "config.vh"
-
-import cvw::*;
+`include "wally-config.vh"
 
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
-   input           default_250mhz_clk1_0_p, 
-   input           reset,
-   input           south_rst,
+   input 		   default_250mhz_clk1_0_p, 
+   input 		   reset,
+   input 		   south_rst,
 
-   input [2:0]     GPI,
+   input [3:0] 	   GPI,
    output [4:0]    GPO,
 
-   input           UARTSin,
-   output          UARTSout,
+   input 		   UARTSin,
+   output 		   UARTSout,
 
-   // SDC Signals connecting to an SPI peripheral
-   input         SDCIn,
-   output        SDCCLK,
-   output        SDCCmd,
-   output        SDCCS,
-   input         SDCCD,
-   input         SDCWP,         
+   input [3:0] 	   SDCDat,
+   output 		   SDCCLK,
+   inout 		   SDCCmd,
 
-   output          cpu_reset,
-   output          ahblite_resetn,
+   output 		   calib,
+   output 		   cpu_reset,
+   output 		   ahblite_resetn,
 
    output [16 : 0] c0_ddr4_adr,
    output [1 : 0]  c0_ddr4_ba,
@@ -61,139 +56,148 @@ module fpgaTop
    inout [7 : 0]   c0_ddr4_dqs_t,
    output [0 : 0]  c0_ddr4_odt,
    output [0 : 0]  c0_ddr4_bg,
-   output          c0_ddr4_reset_n,
-   output          c0_ddr4_act_n,
+   output 		   c0_ddr4_reset_n,
+   output 		   c0_ddr4_act_n,
    output [0 : 0]  c0_ddr4_ck_c,
    output [0 : 0]  c0_ddr4_ck_t
    );
 
-  logic		   CPUCLK;
-  logic		   c0_ddr4_ui_clk_sync_rst;
-  logic		   bus_struct_reset;
-  logic		   peripheral_reset;
-  logic		   interconnect_aresetn;
-  logic		   peripheral_aresetn;
-  logic		   mb_reset;
+  wire 			   CPUCLK;
+  wire 			   c0_ddr4_ui_clk_sync_rst;
+  wire 			   bus_struct_reset;
+  wire 			   peripheral_reset;
+  wire 			   interconnect_aresetn;
+  wire 			   peripheral_aresetn;
+  wire 			   mb_reset;
+  
+  wire 			   HCLKOpen;
+  wire 			   HRESETnOpen;
+  wire [`AHBW-1:0] HRDATAEXT;
+  wire 			   HREADYEXT;
+  wire 			   HRESPEXT;
+  wire 			   HSELEXT;
+  wire [31:0] 	   HADDR;
+  wire [`AHBW-1:0] HWDATA;
+  wire 			   HWRITE;
+  wire [2:0] 	   HSIZE;
+  wire [2:0] 	   HBURST;
+  wire [1:0] 	   HTRANS;
+  wire 			   HREADY;
+  wire [3:0] 	   HPROT;
+  wire 			   HMASTLOCK;
+  
   
-  logic		   HCLKOpen;
-  logic		   HRESETnOpen;
-  logic [64-1:0]   HRDATAEXT;
-  logic		   HREADYEXT;
-  logic		   HRESPEXT;
-  logic		   HSELEXT;
-  logic [55:0]	   HADDR;
-  logic [64-1:0]   HWDATA;
-  logic [64/8-1:0] HWSTRB;
-  logic		   HWRITE;
-  logic [2:0]	   HSIZE;
-  logic [2:0]	   HBURST;
-  logic [1:0]	   HTRANS;
-  logic		   HREADY;
-  logic [3:0]	   HPROT;
-  logic		   HMASTLOCK;
 
-  logic		   RVVIStall;
+  wire [31:0] 	   GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
 
-  logic [31:0]	   GPIOIN, GPIOOUT, GPIOEN;
+  wire 			   SDCCmdIn;
+  wire 			   SDCCmdOE;
+  wire 			   SDCCmdOut;
 
-  logic [3:0]	   m_axi_awid;
-  logic [7:0]	   m_axi_awlen;
-  logic [2:0]	   m_axi_awsize;
-  logic [1:0]	   m_axi_awburst;
-  logic [3:0]	   m_axi_awcache;
-  logic [31:0]	   m_axi_awaddr;
-  logic [2:0]	   m_axi_awprot;
-  logic		   m_axi_awvalid;
-  logic		   m_axi_awready;
-  logic		   m_axi_awlock;
-  logic [63:0]	   m_axi_wdata;
-  logic [7:0]	   m_axi_wstrb;
-  logic		   m_axi_wlast;
-  logic		   m_axi_wvalid;
-  logic		   m_axi_wready;
-  logic [3:0]	   m_axi_bid;
-  logic [1:0]	   m_axi_bresp;
-  logic		   m_axi_bvalid;
-  logic		   m_axi_bready;
-  logic [3:0]	   m_axi_arid;
-  logic [7:0]	   m_axi_arlen;
-  logic [2:0]	   m_axi_arsize;
-  logic [1:0]	   m_axi_arburst;
-  logic [2:0]	   m_axi_arprot;
-  logic [3:0]	   m_axi_arcache;
-  logic		   m_axi_arvalid;
-  logic [31:0]	   m_axi_araddr;
-  logic		   m_axi_arlock;
-  logic		   m_axi_arready;
-  logic [3:0]	   m_axi_rid;
-  logic [63:0]	   m_axi_rdata;
-  logic [1:0]	   m_axi_rresp;
-  logic		   m_axi_rvalid;
-  logic		   m_axi_rlast;
-  logic		   m_axi_rready;
+  wire [3:0] 	   m_axi_awid;
+  wire [7:0] 	   m_axi_awlen;
+  wire [2:0] 	   m_axi_awsize;
+  wire [1:0] 	   m_axi_awburst;
+  wire [3:0] 	   m_axi_awcache;
+  wire [31:0] 	   m_axi_awaddr;
+  wire [2:0] 	   m_axi_awprot;
+  wire 		   m_axi_awvalid;
+  wire 		   m_axi_awready;
+  wire 		   m_axi_awlock;
+  wire [63:0] 	   m_axi_wdata;
+  wire [7:0] 	   m_axi_wstrb;
+  wire 		   m_axi_wlast;
+  wire 		   m_axi_wvalid;
+  wire 		   m_axi_wready;
+  wire [3:0] 	   m_axi_bid;
+  wire [1:0] 	   m_axi_bresp;
+  wire 		   m_axi_bvalid;
+  wire 		   m_axi_bready;
+  wire [3:0] 	   m_axi_arid;
+  wire [7:0] 	   m_axi_arlen;
+  wire [2:0] 	   m_axi_arsize;
+  wire [1:0] 	   m_axi_arburst;
+  wire [2:0] 	   m_axi_arprot;
+  wire [3:0] 	   m_axi_arcache;
+  wire 		   m_axi_arvalid;
+  wire [31:0] 	   m_axi_araddr;
+  wire 			   m_axi_arlock;
+  wire 		   m_axi_arready;
+  wire [3:0] 	   m_axi_rid;
+  wire [63:0] 	   m_axi_rdata;
+  wire [1:0] 	   m_axi_rresp;
+  wire 		   m_axi_rvalid;
+  wire 		   m_axi_rlast;
+  wire 		   m_axi_rready;
 
-  // Extra Bus signals
-  logic [3:0]	   BUS_axi_arregion;
-  logic [3:0]	   BUS_axi_arqos;
-  logic [3:0]	   BUS_axi_awregion;
-  logic [3:0]	   BUS_axi_awqos;
+  wire [3:0] 	   BUS_axi_arregion;
+  wire [3:0] 	   BUS_axi_arqos;
+  wire [3:0] 	   BUS_axi_awregion;
+  wire [3:0] 	   BUS_axi_awqos;
 
-  // Bus signals
-  logic [3:0]	   BUS_axi_awid;
-  logic [7:0]	   BUS_axi_awlen;
-  logic [2:0]	   BUS_axi_awsize;
-  logic [1:0]	   BUS_axi_awburst;
-  logic [3:0]	   BUS_axi_awcache;
-  logic [30:0]	   BUS_axi_awaddr;
-  logic [2:0]	   BUS_axi_awprot;
-  logic		   BUS_axi_awvalid;
-  logic		   BUS_axi_awready;
-  logic		   BUS_axi_awlock;
-  logic [63:0]	   BUS_axi_wdata;
-  logic [7:0]	   BUS_axi_wstrb;
-  logic		   BUS_axi_wlast;
-  logic		   BUS_axi_wvalid;
-  logic		   BUS_axi_wready;
-  logic [3:0]	   BUS_axi_bid;
-  logic [1:0]	   BUS_axi_bresp;
-  logic		   BUS_axi_bvalid;
-  logic		   BUS_axi_bready;
-  logic [3:0]	   BUS_axi_arid;
-  logic [7:0]	   BUS_axi_arlen;
-  logic [2:0]	   BUS_axi_arsize;
-  logic [1:0]	   BUS_axi_arburst;
-  logic [2:0]	   BUS_axi_arprot;
-  logic [3:0]	   BUS_axi_arcache;
-  logic		   BUS_axi_arvalid;
-  logic [30:0]	   BUS_axi_araddr;
-  logic		   BUS_axi_arlock;
-  logic		   BUS_axi_arready;
-  logic [3:0]	   BUS_axi_rid;
-  logic [63:0]	   BUS_axi_rdata;
-  logic [1:0]	   BUS_axi_rresp;
-  logic		   BUS_axi_rvalid;
-  logic		   BUS_axi_rlast;
-  logic		   BUS_axi_rready;
+  wire [3:0] 	   BUS_axi_awid;
+  wire [7:0] 	   BUS_axi_awlen;
+  wire [2:0] 	   BUS_axi_awsize;
+  wire [1:0] 	   BUS_axi_awburst;
+  wire [3:0] 	   BUS_axi_awcache;
+  wire [30:0] 	   BUS_axi_awaddr;
+  wire [2:0] 	   BUS_axi_awprot;
+  wire 			   BUS_axi_awvalid;
+  wire 			   BUS_axi_awready;
+  wire 			   BUS_axi_awlock;
+  wire [63:0] 	   BUS_axi_wdata;
+  wire [7:0] 	   BUS_axi_wstrb;
+  wire 			   BUS_axi_wlast;
+  wire 			   BUS_axi_wvalid;
+  wire 			   BUS_axi_wready;
+  wire [3:0] 	   BUS_axi_bid;
+  wire [1:0] 	   BUS_axi_bresp;
+  wire 			   BUS_axi_bvalid;
+  wire 			   BUS_axi_bready;
+  wire [3:0] 	   BUS_axi_arid;
+  wire [7:0] 	   BUS_axi_arlen;
+  wire [2:0] 	   BUS_axi_arsize;
+  wire [1:0] 	   BUS_axi_arburst;
+  wire [2:0] 	   BUS_axi_arprot;
+  wire [3:0] 	   BUS_axi_arcache;
+  wire 			   BUS_axi_arvalid;
+  wire [30:0] 	   BUS_axi_araddr;
+  wire 			   BUS_axi_arlock;
+  wire 			   BUS_axi_arready;
+  wire [3:0] 	   BUS_axi_rid;
+  wire [63:0] 	   BUS_axi_rdata;
+  wire [1:0] 	   BUS_axi_rresp;
+  wire 			   BUS_axi_rvalid;
+  wire 			   BUS_axi_rlast;
+  wire 			   BUS_axi_rready;
+  
+  wire 			   BUSCLK;
+  
 
-  logic		   BUSCLK;
+  wire 			   c0_init_calib_complete;
+  wire 			   dbg_clk;
+  wire [511 : 0]   dbg_bus;
 
-  logic		   c0_init_calib_complete;
-  logic		   dbg_clk;
-  logic [511 : 0]  dbg_bus;
+  wire 			   CLK208;
+  
 
-  logic		   CLK208;
+  
 
-  assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI};
-  assign GPO = GPIOOUT[4:0];
+  assign GPIOPinsIn = {28'b0, GPI};
+  assign GPO = GPIOPinsOut[4:0];
   assign ahblite_resetn = peripheral_aresetn;
   assign cpu_reset = bus_struct_reset;
+  assign calib = c0_init_calib_complete;
   
-  logic [3:0] SDCCSin;
-  assign SDCCS = SDCCSin[0];
+  
+  // SD Card Tristate
+  IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low
+				   .I(SDCCmdOut),
+				   .O(SDCCmdIn),
+				   .IO(SDCCmd));
 
-   
   // reset controller XILINX IP
-  sysrst sysrst
+  xlnx_proc_sys_reset xlnx_proc_sys_reset_0
     (.slowest_sync_clk(CPUCLK),
      .ext_reset_in(c0_ddr4_ui_clk_sync_rst),
      .aux_reset_in(south_rst),
@@ -204,22 +208,44 @@ module fpgaTop
      .peripheral_reset(peripheral_reset), //open
      .interconnect_aresetn(interconnect_aresetn), //open
      .peripheral_aresetn(peripheral_aresetn));
+  
 
-  `include "parameter-defs.vh"
-
-  // Wally 
-  wallypipelinedsoc  #(P) 
-  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
-                    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
-                    .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), 
-                    .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
-                    .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
-
+  // wally
+  wallypipelinedsoc wallypipelinedsoc
+    (.clk(CPUCLK),
+     .reset_ext(bus_struct_reset),
+     // bus interface
+     .HRDATAEXT(HRDATAEXT),
+     .HREADYEXT(HREADYEXT),
+     .HRESPEXT(HRESPEXT),
+     .HSELEXT(HSELEXT),
+     .HCLK(HCLKOpen), // open
+     .HRESETn(HRESETnOpen), // open
+     .HADDR(HADDR),
+     .HWDATA(HWDATA),
+     .HWRITE(HWRITE),
+     .HSIZE(HSIZE),
+     .HBURST(HBURST),
+     .HPROT(HPROT),
+     .HTRANS(HTRANS),
+     .HMASTLOCK(HMASTLOCK),
+     .HREADY(HREADY),
+     // GPIO
+     .GPIOPinsIn(GPIOPinsIn),
+     .GPIOPinsOut(GPIOPinsOut),
+     .GPIOPinsEn(GPIOPinsEn),
+     // UART
+     .UARTSin(UARTSin),
+     .UARTSout(UARTSout),  
+     // SD Card   
+     .SDCDatIn(SDCDat),
+     .SDCCmdIn(SDCCmdIn),     
+     .SDCCmdOut(SDCCmdOut),
+     .SDCCmdOE(SDCCmdOE),
+     .SDCCLK(SDCCLK));
 
   // ahb lite to axi bridge
-  ahbaxibridge ahbaxibridge
+  xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
     (.s_ahb_hclk(CPUCLK),
      .s_ahb_hresetn(peripheral_aresetn),
      .s_ahb_hsel(HSELEXT),
@@ -270,7 +296,7 @@ module fpgaTop
      .m_axi_rlast(m_axi_rlast),
      .m_axi_rready(m_axi_rready));
 
-  clkconverter clkconverter
+  xlnx_axi_clock_converter xlnx_axi_clock_converter_0
     (.s_axi_aclk(CPUCLK),
      .s_axi_aresetn(peripheral_aresetn),
      .s_axi_awid(m_axi_awid),
@@ -278,7 +304,7 @@ module fpgaTop
      .s_axi_awsize(m_axi_awsize),
      .s_axi_awburst(m_axi_awburst),
      .s_axi_awcache(m_axi_awcache),
-     .s_axi_awaddr(m_axi_awaddr[30:0] ),
+     .s_axi_awaddr(m_axi_awaddr[30:0]),
      .s_axi_awprot(m_axi_awprot),
      .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
      .s_axi_awqos(4'b0),    // this could be a bug. bridge does not have these outputs
@@ -354,8 +380,8 @@ module fpgaTop
      .m_axi_rvalid(BUS_axi_rvalid),
      .m_axi_rlast(BUS_axi_rlast),
      .m_axi_rready(BUS_axi_rready));
-   
-  ddr4 ddr4
+
+  xlnx_ddr4 xlnx_ddr4_c0
     (.c0_init_calib_complete(c0_init_calib_complete),
      .dbg_clk(dbg_clk), // open
      .c0_sys_clk_p(default_250mhz_clk1_0_p),
@@ -424,7 +450,8 @@ module fpgaTop
      .addn_ui_clkout1(CPUCLK),
      .addn_ui_clkout2(CLK208));
   
-  assign RVVIStall = '0;
+
+  
 
 endmodule
 
diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
deleted file mode 100644
index 07c66ff95..000000000
--- a/fpga/src/fpgaTopArtyA7.sv
+++ /dev/null
@@ -1,621 +0,0 @@
-///////////////////////////////////////////
-// fpgaTop.sv
-//
-// Written: rose@rosethompson.net November 17, 2021
-// Modified: 
-//
-// Purpose: This is a top level for the fpga's implementation of wally.
-//          Instantiates wallysoc, ddr4, abh lite to axi converters, pll, etc
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "config.vh"
-
-import cvw::*;
-
-module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
-  (input logic           default_100mhz_clk,
-   input logic           resetn,
-   input logic           south_reset,
-
-   // GPIO signals
-   input logic [3:0]   GPI,
-   output logic [4:0]  GPO,
-
-   // UART Signals
-   input logic         UARTSin,
-   output logic        UARTSout,
-
-   // SDC Signals connecting to an SPI peripheral
-   input logic         SDCIn,
-   output logic        SDCCLK,
-   output logic        SDCCmd,
-   output logic        SDCCS,
-   input logic         SDCCD,
-   input logic         SDCWP,         
- /*
-     * Ethernet: 100BASE-T MII
-     */
-    output logic       phy_ref_clk,
-    input logic        phy_rx_clk,
-    input logic  [3:0] phy_rxd,
-    input logic        phy_rx_dv,
-    input logic        phy_rx_er,
-    input logic        phy_tx_clk,
-    output logic [3:0] phy_txd,
-    output logic       phy_tx_en,
-    input logic        phy_col, // nc
-    input logic        phy_crs, // nc
-    output logic       phy_reset_n,
-
-   inout logic [15:0]    ddr3_dq,
-   inout logic [1:0]     ddr3_dqs_n,
-   inout logic [1:0]     ddr3_dqs_p,
-   output logic [13:0]   ddr3_addr,
-   output logic [2:0]    ddr3_ba,
-   output logic          ddr3_ras_n,
-   output logic          ddr3_cas_n,
-   output logic          ddr3_we_n,
-   output logic          ddr3_reset_n,
-   output logic [0:0]    ddr3_ck_p,
-   output logic [0:0]    ddr3_ck_n,
-   output logic [0:0]    ddr3_cke,
-   output logic [0:0]    ddr3_cs_n,
-   output logic [1:0]    ddr3_dm,
-   output logic [0:0]    ddr3_odt
-   );
-
-  // MMCM Signals
-  logic 			   CPUCLK;
-  logic 			   c0_ddr4_ui_clk_sync_rst;
-  logic 			   bus_struct_reset;
-  logic 			   peripheral_reset;
-  logic 			   interconnect_aresetn;
-  logic 			   peripheral_aresetn;
-  logic 			   mb_reset;
-  
-  // AHB Signals from Wally
-  logic 			   HCLKOpen;
-  logic 			   HRESETnOpen;
-  logic [63:0]      HRDATAEXT;
-  logic 			   HREADYEXT;
-  logic 			   HRESPEXT;
-  logic 			   HSELEXT;
-  logic [55:0] 	   HADDR;
-  logic [63:0]      HWDATA;
-  logic [64/8-1:0]  HWSTRB;
-  logic 			   HWRITE;
-  logic [2:0] 	   HSIZE;
-  logic [2:0] 	   HBURST;
-  logic [1:0] 	   HTRANS;
-  logic 			   HREADY;
-  logic [3:0] 	   HPROT;
-  logic 			   HMASTLOCK;
-
-  // GPIO Signals
-  logic [31:0] 	   GPIOIN, GPIOOUT, GPIOEN;
-
-  // AHB to AXI Bridge Signals
-  logic [3:0] 	   m_axi_awid;
-  logic [7:0] 	   m_axi_awlen;
-  logic [2:0] 	   m_axi_awsize;
-  logic [1:0] 	   m_axi_awburst;
-  logic [3:0] 	   m_axi_awcache;
-  logic [31:0] 	   m_axi_awaddr;
-  logic [2:0] 	   m_axi_awprot;
-  logic             m_axi_awvalid;
-  logic             m_axi_awready;
-  logic             m_axi_awlock;
-  logic [63:0] 	   m_axi_wdata;
-  logic [7:0] 	   m_axi_wstrb;
-  logic             m_axi_wlast;
-  logic             m_axi_wvalid;
-  logic             m_axi_wready;
-  logic [3:0] 	   m_axi_bid;
-  logic [1:0] 	   m_axi_bresp;
-  logic             m_axi_bvalid;
-  logic             m_axi_bready;
-  logic [3:0] 	   m_axi_arid;
-  logic [7:0] 	   m_axi_arlen;
-  logic [2:0] 	   m_axi_arsize;
-  logic [1:0] 	   m_axi_arburst;
-  logic [2:0] 	   m_axi_arprot;
-  logic [3:0] 	   m_axi_arcache;
-  logic             m_axi_arvalid;
-  logic [31:0] 	   m_axi_araddr;
-  logic 			   m_axi_arlock;
-  logic             m_axi_arready;
-  logic [3:0] 	   m_axi_rid;
-  logic [63:0] 	   m_axi_rdata;
-  logic [1:0] 	   m_axi_rresp;
-  logic             m_axi_rvalid;
-  logic             m_axi_rlast;
-  logic             m_axi_rready;
-
-  // AXI Signals going out of Clock Converter
-  logic [3:0] 	   BUS_axi_arregion;
-  logic [3:0] 	   BUS_axi_arqos;
-  logic [3:0] 	   BUS_axi_awregion;
-  logic [3:0] 	   BUS_axi_awqos;
-  logic [3:0] 	   BUS_axi_awid;
-  logic [7:0] 	   BUS_axi_awlen;
-  logic [2:0] 	   BUS_axi_awsize;
-  logic [1:0] 	   BUS_axi_awburst;
-  logic [3:0] 	   BUS_axi_awcache;
-  logic [31:0] 	   BUS_axi_awaddr;
-  logic [2:0] 	   BUS_axi_awprot;
-  logic 			   BUS_axi_awvalid;
-  logic 			   BUS_axi_awready;
-  logic 			   BUS_axi_awlock;
-  logic [63:0] 	   BUS_axi_wdata;
-  logic [7:0] 	   BUS_axi_wstrb;
-  logic 			   BUS_axi_wlast;
-  logic 			   BUS_axi_wvalid;
-  logic 			   BUS_axi_wready;
-  logic [3:0] 	   BUS_axi_bid;
-  logic [1:0] 	   BUS_axi_bresp;
-  logic 			   BUS_axi_bvalid;
-  logic 			   BUS_axi_bready;
-  logic [3:0] 	   BUS_axi_arid;
-  logic [7:0] 	   BUS_axi_arlen;
-  logic [2:0] 	   BUS_axi_arsize;
-  logic [1:0] 	   BUS_axi_arburst;
-  logic [2:0] 	   BUS_axi_arprot;
-  logic [3:0] 	   BUS_axi_arcache;
-  logic 			   BUS_axi_arvalid;
-  logic [31:0] 	   BUS_axi_araddr;
-  logic 			   BUS_axi_arlock;
-  logic 			   BUS_axi_arready;
-  logic [3:0] 	   BUS_axi_rid;
-  logic [63:0] 	   BUS_axi_rdata;
-  logic [1:0] 	   BUS_axi_rresp;
-  logic 			   BUS_axi_rvalid;
-  logic 			   BUS_axi_rlast;
-  logic 			   BUS_axi_rready;
-  
-  logic 			   BUSCLK;
-  logic             sdio_reset_open;
-  
-  logic             c0_init_calib_complete;
-  logic 			   dbg_clk;
-  logic [511 : 0]   dbg_bus;
-  logic             ui_clk_sync_rst;
-  
-  logic 			   CLK208;
-  logic             clk167;
-  logic             clk200;
-
-  logic             app_sr_active;
-  logic             app_ref_ack;
-  logic             app_zq_ack;
-  logic             mmcm_locked;
-  logic [11:0]      device_temp;
-  logic             mmcm1_locked;
-
-(* mark_debug = "true" *)  logic              RVVIStall;
-
-  assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI};
-  assign GPO = GPIOOUT[4:0];
-  assign ahblite_resetn = peripheral_aresetn;
-  assign cpu_reset = bus_struct_reset;
-  assign calib = c0_init_calib_complete;
-
-  logic [3:0] SDCCSin;
-  assign SDCCS = SDCCSin[0];
-
-  // mmcm
-
-  // the ddr3 mig7 requires 2 input clocks 
-  // 1. sys clock which is 167 MHz = ddr3 clock / 4
-  // 2. a second clock which is 200 MHz
-  // Wally requires a slower clock.  At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
-  // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
-  mmcm mmcm(.clk_out1(clk167),
-                     .clk_out2(clk200),
-                     .clk_out3(CPUCLK),
-                     .clk_out4(phy_ref_clk),
-                     .reset(1'b0),
-                     .locked(mmcm1_locked),
-                     .clk_in1(default_100mhz_clk));
-
-  
-
-  // reset controller XILINX IP
-  sysrst sysrst
-    (.slowest_sync_clk(CPUCLK),
-     .ext_reset_in(1'b0),
-     .aux_reset_in(south_reset),
-     .mb_debug_sys_rst(1'b0),
-     .dcm_locked(c0_init_calib_complete),
-     .mb_reset(mb_reset),  //open
-     .bus_struct_reset(bus_struct_reset),
-     .peripheral_reset(peripheral_reset), //open
-     .interconnect_aresetn(interconnect_aresetn), //open
-     .peripheral_aresetn(peripheral_aresetn));
-
-  `include "parameter-defs.vh"
-  
-  // Wally 
-  wallypipelinedsoc  #(P) 
-  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
-                    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
-                    .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), 
-                    .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
-                    .GPIOIN, .GPIOOUT, .GPIOEN,
-                    .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); 
-
-
-  // ahb lite to axi bridge
-  ahbaxibridge ahbaxibridge
-    (.s_ahb_hclk(CPUCLK),
-     .s_ahb_hresetn(peripheral_aresetn),
-     .s_ahb_hsel(HSELEXT),
-     .s_ahb_haddr(HADDR[31:0]),
-     .s_ahb_hprot(HPROT),
-     .s_ahb_htrans(HTRANS),
-     .s_ahb_hsize(HSIZE),
-     .s_ahb_hwrite(HWRITE),
-     .s_ahb_hburst(HBURST),
-     .s_ahb_hwdata(HWDATA),
-     .s_ahb_hready_out(HREADYEXT),
-     .s_ahb_hready_in(HREADY),
-     .s_ahb_hrdata(HRDATAEXT),
-     .s_ahb_hresp(HRESPEXT),
-     .m_axi_awid(m_axi_awid),
-     .m_axi_awlen(m_axi_awlen),
-     .m_axi_awsize(m_axi_awsize),
-     .m_axi_awburst(m_axi_awburst),
-     .m_axi_awcache(m_axi_awcache),
-     .m_axi_awaddr(m_axi_awaddr),
-     .m_axi_awprot(m_axi_awprot),
-     .m_axi_awvalid(m_axi_awvalid),
-     .m_axi_awready(m_axi_awready),
-     .m_axi_awlock(m_axi_awlock),
-     .m_axi_wdata(m_axi_wdata),
-     .m_axi_wstrb(m_axi_wstrb),
-     .m_axi_wlast(m_axi_wlast),
-     .m_axi_wvalid(m_axi_wvalid),
-     .m_axi_wready(m_axi_wready),
-     .m_axi_bid(m_axi_bid),
-     .m_axi_bresp(m_axi_bresp),
-     .m_axi_bvalid(m_axi_bvalid),
-     .m_axi_bready(m_axi_bready),
-     .m_axi_arid(m_axi_arid),
-     .m_axi_arlen(m_axi_arlen),
-     .m_axi_arsize(m_axi_arsize),
-     .m_axi_arburst(m_axi_arburst),
-     .m_axi_arprot(m_axi_arprot),
-     .m_axi_arcache(m_axi_arcache),
-     .m_axi_arvalid(m_axi_arvalid),
-     .m_axi_araddr(m_axi_araddr),
-     .m_axi_arlock(m_axi_arlock),
-     .m_axi_arready(m_axi_arready),
-     .m_axi_rid(m_axi_rid),
-     .m_axi_rdata(m_axi_rdata),
-     .m_axi_rresp(m_axi_rresp),
-     .m_axi_rvalid(m_axi_rvalid),
-     .m_axi_rlast(m_axi_rlast),
-     .m_axi_rready(m_axi_rready));
-
-  // AXI Clock Converter
-  clkconverter clkconverter
-    (.s_axi_aclk(CPUCLK),
-     .s_axi_aresetn(peripheral_aresetn),
-     .s_axi_awid(m_axi_awid),
-     .s_axi_awlen(m_axi_awlen),
-     .s_axi_awsize(m_axi_awsize),
-     .s_axi_awburst(m_axi_awburst),
-     .s_axi_awcache(m_axi_awcache),
-     .s_axi_awaddr(m_axi_awaddr[30:0] ),
-     .s_axi_awprot(m_axi_awprot),
-     .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
-     .s_axi_awqos(4'b0),    // this could be a bug. bridge does not have these outputs
-     .s_axi_awvalid(m_axi_awvalid),
-     .s_axi_awready(m_axi_awready),
-     .s_axi_awlock(m_axi_awlock),
-     .s_axi_wdata(m_axi_wdata),
-     .s_axi_wstrb(m_axi_wstrb),
-     .s_axi_wlast(m_axi_wlast),
-     .s_axi_wvalid(m_axi_wvalid),
-     .s_axi_wready(m_axi_wready),
-     .s_axi_bid(m_axi_bid),
-     .s_axi_bresp(m_axi_bresp),
-     .s_axi_bvalid(m_axi_bvalid),
-     .s_axi_bready(m_axi_bready),
-     .s_axi_arid(m_axi_arid),
-     .s_axi_arlen(m_axi_arlen),
-     .s_axi_arsize(m_axi_arsize),
-     .s_axi_arburst(m_axi_arburst),
-     .s_axi_arprot(m_axi_arprot),
-     .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs
-     .s_axi_arqos(4'b0),    // this could be a bug. bridge does not have these outputs
-     .s_axi_arcache(m_axi_arcache),
-     .s_axi_arvalid(m_axi_arvalid),
-     .s_axi_araddr(m_axi_araddr[30:0]),
-     .s_axi_arlock(m_axi_arlock),
-     .s_axi_arready(m_axi_arready),
-     .s_axi_rid(m_axi_rid),
-     .s_axi_rdata(m_axi_rdata),
-     .s_axi_rresp(m_axi_rresp),
-     .s_axi_rvalid(m_axi_rvalid),
-     .s_axi_rlast(m_axi_rlast),
-     .s_axi_rready(m_axi_rready),
-
-     .m_axi_aclk(BUSCLK),
-     .m_axi_aresetn(resetn),
-     .m_axi_awid(BUS_axi_awid),
-     .m_axi_awlen(BUS_axi_awlen),
-     .m_axi_awsize(BUS_axi_awsize),
-     .m_axi_awburst(BUS_axi_awburst),
-     .m_axi_awcache(BUS_axi_awcache),
-     .m_axi_awaddr(BUS_axi_awaddr),
-     .m_axi_awprot(BUS_axi_awprot),
-     .m_axi_awregion(BUS_axi_awregion),
-     .m_axi_awqos(BUS_axi_awqos),
-     .m_axi_awvalid(BUS_axi_awvalid),
-     .m_axi_awready(BUS_axi_awready),
-     .m_axi_awlock(BUS_axi_awlock),
-     .m_axi_wdata(BUS_axi_wdata),
-     .m_axi_wstrb(BUS_axi_wstrb),
-     .m_axi_wlast(BUS_axi_wlast),
-     .m_axi_wvalid(BUS_axi_wvalid),
-     .m_axi_wready(BUS_axi_wready),
-     .m_axi_bid(BUS_axi_bid),
-     .m_axi_bresp(BUS_axi_bresp),
-     .m_axi_bvalid(BUS_axi_bvalid),
-     .m_axi_bready(BUS_axi_bready),
-     .m_axi_arid(BUS_axi_arid),
-     .m_axi_arlen(BUS_axi_arlen),
-     .m_axi_arsize(BUS_axi_arsize),
-     .m_axi_arburst(BUS_axi_arburst),
-     .m_axi_arprot(BUS_axi_arprot),
-     .m_axi_arregion(BUS_axi_arregion),
-     .m_axi_arqos(BUS_axi_arqos),
-     .m_axi_arcache(BUS_axi_arcache),
-     .m_axi_arvalid(BUS_axi_arvalid),
-     .m_axi_araddr(BUS_axi_araddr),
-     .m_axi_arlock(BUS_axi_arlock),
-     .m_axi_arready(BUS_axi_arready),
-     .m_axi_rid(BUS_axi_rid),
-     .m_axi_rdata(BUS_axi_rdata),
-     .m_axi_rresp(BUS_axi_rresp),
-     .m_axi_rvalid(BUS_axi_rvalid),
-     .m_axi_rlast(BUS_axi_rlast),
-     .m_axi_rready(BUS_axi_rready));
-
-  // DDR3 Controller
-  ddr3 ddr3
-    (
-     // ddr3 I/O
-     .ddr3_dq(ddr3_dq),
-     .ddr3_dqs_n(ddr3_dqs_n),
-     .ddr3_dqs_p(ddr3_dqs_p),
-     .ddr3_addr(ddr3_addr),
-     .ddr3_ba(ddr3_ba),
-     .ddr3_ras_n(ddr3_ras_n),
-     .ddr3_cas_n(ddr3_cas_n),
-     .ddr3_we_n(ddr3_we_n),
-     .ddr3_reset_n(ddr3_reset_n),
-     .ddr3_ck_p(ddr3_ck_p),
-     .ddr3_ck_n(ddr3_ck_n),
-     .ddr3_cke(ddr3_cke),
-     .ddr3_cs_n(ddr3_cs_n),
-     .ddr3_dm(ddr3_dm),
-     .ddr3_odt(ddr3_odt),
-
-     .sys_clk_i(clk167),
-     .clk_ref_i(clk200),
-
-     .ui_clk(BUSCLK),
-     .ui_clk_sync_rst(ui_clk_sync_rst),
-     .aresetn(resetn),
-     .sys_rst(resetn),    // omg. this is active low?!?!?? 
-     .mmcm_locked(mmcm_locked),
-
-     .app_sr_req(1'b0),  // reserved command
-     .app_ref_req(1'b0), // refresh command
-     .app_zq_req(1'b0),  // recalibrate command
-     .app_sr_active(app_sr_active), // reserved response
-     .app_ref_ack(app_ref_ack),     // refresh ack
-     .app_zq_ack(app_zq_ack),       // recalibrate ack
-
-     // axi
-     .s_axi_awid(BUS_axi_awid),
-     .s_axi_awaddr(BUS_axi_awaddr[27:0]),
-     .s_axi_awlen(BUS_axi_awlen),
-     .s_axi_awsize(BUS_axi_awsize),
-     .s_axi_awburst(BUS_axi_awburst),
-     .s_axi_awlock(BUS_axi_awlock),
-     .s_axi_awcache(BUS_axi_awcache),
-     .s_axi_awprot(BUS_axi_awprot),
-     .s_axi_awqos(BUS_axi_awqos),
-     .s_axi_awvalid(BUS_axi_awvalid),
-     .s_axi_awready(BUS_axi_awready),
-     .s_axi_wdata(BUS_axi_wdata),
-     .s_axi_wstrb(BUS_axi_wstrb),
-     .s_axi_wlast(BUS_axi_wlast),
-     .s_axi_wvalid(BUS_axi_wvalid),
-     .s_axi_wready(BUS_axi_wready),
-     .s_axi_bready(BUS_axi_bready),
-     .s_axi_bid(BUS_axi_bid),
-     .s_axi_bresp(BUS_axi_bresp),
-     .s_axi_bvalid(BUS_axi_bvalid),
-     .s_axi_arid(BUS_axi_arid),
-     .s_axi_araddr(BUS_axi_araddr[27:0]),
-     .s_axi_arlen(BUS_axi_arlen),
-     .s_axi_arsize(BUS_axi_arsize),
-     .s_axi_arburst(BUS_axi_arburst),
-     .s_axi_arlock(BUS_axi_arlock),
-     .s_axi_arcache(BUS_axi_arcache),
-     .s_axi_arprot(BUS_axi_arprot),
-     .s_axi_arqos(BUS_axi_arqos),
-     .s_axi_arvalid(BUS_axi_arvalid),
-     .s_axi_arready(BUS_axi_arready),
-     .s_axi_rready(BUS_axi_rready),
-     .s_axi_rlast(BUS_axi_rlast),
-     .s_axi_rvalid(BUS_axi_rvalid),
-     .s_axi_rresp(BUS_axi_rresp),
-     .s_axi_rid(BUS_axi_rid),
-     .s_axi_rdata(BUS_axi_rdata),
-
-     .init_calib_complete(c0_init_calib_complete),
-     .device_temp(device_temp));
-
-  (* mark_debug = "true" *)  logic IlaTrigger;
-    
-   
-  if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
-    localparam MAX_CSRS = 3;
-    localparam TOTAL_CSRS = 36;
-    localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000;
-    localparam [31:0] RVVI_PACKET_DELAY = 32'd400;
-    
-    // pipeline controlls
-    logic                                             StallE, StallM, StallW, FlushE, FlushM, FlushW;
-    // required
-    logic [P.XLEN-1:0]                                PCM;
-    logic                                             InstrValidM;
-    logic [31:0]                                      InstrRawD;
-    logic [63:0]                                      Mcycle, Minstret;
-    logic                                             TrapM;
-    logic [1:0]                                       PrivilegeModeW;
-    // registers gpr and fpr
-    logic                                             GPRWen, FPRWen;
-    logic [4:0]                                       GPRAddr, FPRAddr;
-    logic [P.XLEN-1:0]                                GPRValue, FPRValue;
-    logic [P.XLEN-1:0]                                CSRArray [TOTAL_CSRS-1:0];
-
-    logic                                             valid;
-    logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
-
-    assign StallE         = fpgaTop.wallypipelinedsoc.core.StallE;
-    assign StallM         = fpgaTop.wallypipelinedsoc.core.StallM;
-    assign StallW         = fpgaTop.wallypipelinedsoc.core.StallW;
-    assign FlushE         = fpgaTop.wallypipelinedsoc.core.FlushE;
-    assign FlushM         = fpgaTop.wallypipelinedsoc.core.FlushM;
-    assign FlushW         = fpgaTop.wallypipelinedsoc.core.FlushW;
-    assign InstrValidM    = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
-    assign InstrRawD      = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
-    assign PCM            = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
-    assign Mcycle         = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
-    assign Minstret       = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-    assign TrapM          = fpgaTop.wallypipelinedsoc.core.TrapM;
-    assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
-    assign GPRAddr        = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
-    assign GPRWen         = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
-    assign GPRValue       = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
-    assign FPRAddr        = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
-    assign FPRWen         = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
-    assign FPRValue       = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
-
-    assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
-    assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
-    assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
-    assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
-    assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
-    assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
-    assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
-    assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
-    assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
-    assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
-    assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
-    assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
-    assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
-    assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
-    assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
-    assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
-    assign CSRArray[16] = 0; // 12'hF11
-    assign CSRArray[17] = 0; // 12'hF12
-    assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
-    assign CSRArray[19] = 0; // 12'hF15
-    assign CSRArray[20] = 0; // 12'h34A
-    // supervisor CSRs
-    assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
-    assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
-    assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
-    assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
-    assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
-    assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
-    assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
-    assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
-    assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
-    assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
-    assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
-    assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
-    // user CSRs
-    assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
-    assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
-    assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
-
-    rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
-      .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, 
-      .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
-      .valid, .rvvi);
-
-    // axi 4 write data channel
-    logic [31:0]                                      RvviAxiWdata;
-    logic [3:0]                                       RvviAxiWstrb;
-    logic                                             RvviAxiWlast;
-    logic                                             RvviAxiWvalid;
-    logic                                             RvviAxiWready;
-
-    logic [31:0] RvviAxiRdata;
-    logic [3:0]                                       RvviAxiRstrb;
-    logic RvviAxiRlast;
-    logic RvviAxiRvalid;
-
-    logic                                             tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
-    logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
-
-    packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
-      .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
-
-    eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),
-      .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
-      .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(RvviAxiRdata),
-      .rx_axis_tkeep(RvviAxiRstrb), .rx_axis_tvalid(RvviAxiRvalid), .rx_axis_tready(1'b1),
-      .rx_axis_tlast(RvviAxiRlast), .rx_axis_tuser(),
-
-      .mii_rx_clk(phy_rx_clk),
-      .mii_rxd(phy_rxd),
-      .mii_rx_dv(phy_rx_dv),
-      .mii_rx_er(phy_rx_er),
-      .mii_tx_clk(phy_tx_clk),
-      .mii_txd(phy_txd),
-      .mii_tx_en(phy_tx_en),
-      .mii_tx_er(),
-
-      // status
-      .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
-      .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, 
-      .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
-      );
-
-    triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata,
-      .RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger);
-  end else begin // if (P.RVVI_SYNTH_SUPPORTED)
-    assign IlaTrigger = '0;
-    assign RVVIStall = '0;
-  end
-   
-  //assign phy_reset_n = ~bus_struct_reset;
-   assign phy_reset_n = ~1'b0;
-  
-endmodule
-
diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv
deleted file mode 100644
index db382ade1..000000000
--- a/fpga/src/wallypipelinedsocwrapper.sv
+++ /dev/null
@@ -1,70 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedsocwrapper.sv
-//
-// Written: Rose Thompson rose@rosethompson.net 16 June 2023
-// Modified: 
-//
-// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
-//          not system verilog.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-//`include "BranchPredictorType.vh"
-`include "config.vh"
-
-import cvw::*;
-
-module wallypipelinedsocwrapper (
-  input  logic                clk, 
-  input  logic                reset_ext,        // external asynchronous reset pin
-  output logic                reset,            // reset synchronized to clk to prevent races on release
-  // AHB Interface
-  input  logic [64-1:0]     HRDATAEXT,
-  input  logic                HREADYEXT, HRESPEXT,
-  output logic                HSELEXT,
-  output logic                HSELEXTSDC,
-  // outputs to external memory, shared with uncore memory
-  output logic                HCLK, HRESETn,
-  output logic [55:0]         HADDR,
-  output logic [64-1:0]       HWDATA,
-  output logic [64/8-1:0]     HWSTRB,
-  output logic                HWRITE,
-  output logic [2:0]          HSIZE,
-  output logic [2:0]          HBURST,
-  output logic [3:0]          HPROT,
-  output logic [1:0]          HTRANS,
-  output logic                HMASTLOCK,
-  output logic                HREADY,
-  // I/O Interface
-  input  logic                TIMECLK,          // optional for CLINT MTIME counter
-  input  logic [31:0]         GPIOIN,           // inputs from GPIO
-  output logic [31:0]         GPIOOUT,          // output values for GPIO
-  output logic [31:0]         GPIOEN,           // output enables for GPIO
-  input  logic                UARTSin,          // UART serial data input
-  output logic                UARTSout,         // UART serial data output
-  input logic                 SDCIntr
-);
-  `include "parameter-defs.vh"
-
-  wallypipelinedsoc  #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT, .HSELEXT,
-    .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SDCIntr); 
-
-endmodule
diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c
deleted file mode 100644
index 7665b2df2..000000000
--- a/fpga/zsbl/boot.c
+++ /dev/null
@@ -1,230 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// boot.c
-//
-// Written: Jacob Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Main bootloader entry point
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include <stddef.h>
-#include "boot.h"
-#include "gpt.h"
-#include "uart.h"
-#include "spi.h"
-#include "sd.h"
-#include "time.h"
-#include "riscv.h"
-#include "fail.h"
-
-
-// Maximum SD card clock frequency is either 20MHz or half of the
-// system clock
-
-/*
-PSEUDOCODE:
-transmit 8 dummy bytes
-wait for receive fifo to get a byte.
-- as soon as a byte is in the receive fifo
-- process the byte and increment a byte counter.
-when 8 bytes are transferred
-
-
- */
-
-// crc16 table to reduce byte processing time
-static const uint16_t crctable[256] = {
-  0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 
-  0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 
-  0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, 
-  0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 
-  0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, 
-  0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, 
-  0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, 
-  0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 
-  0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, 
-  0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 
-  0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, 
-  0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, 
-  0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, 
-  0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, 
-  0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, 
-  0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 
-  0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, 
-  0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, 
-  0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 
-  0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, 
-  0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, 
-  0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, 
-  0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, 
-  0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, 
-  0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 
-  0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, 
-  0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, 
-  0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, 
-  0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 
-  0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, 
-  0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 
-  0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 
-};
-
-int disk_read(BYTE * buf, LBA_t sector, UINT count) {
-  uint64_t r;
-  UINT i, j;
-  volatile uint8_t *p = buf;
-
-  // Quarter of the Systemclock, divided by the number of bits in a block
-  // equals the number of blocks per second transferred.
-  UINT modulus = SDCCLOCK/(8*512);
-
-  uint8_t crc = 0;
-  crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE);
-  crc = crc7(crc, (sector >> 24) & 0xff);
-  crc = crc7(crc, (sector >> 16) & 0xff);
-  crc = crc7(crc, (sector >> 8) & 0xff);
-  crc = crc7(crc, sector & 0xff);
-  crc = crc | 1;
-  
-  if ((r = sd_cmd(18, sector & 0xffffffff, crc) & 0xff) != 0x00) {
-    print_uart("disk_read: CMD18 failed. r = 0x");
-    print_uart_byte(r);
-    print_uart("\r\n");
-    fail();
-    // return -1;
-  }
-
-  print_uart("\r          Blocks loaded: ");
-  print_uart("0");
-  print_uart("/");
-  print_uart_dec(count);
-  // write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD);
-  // Begin reading blocks
-  for (i = 0; i < count; i++) {
-    uint16_t crc, crc_exp;
-    uint64_t n = 0;
-    uint64_t readCount = 0;
-
-    // Wait for data token
-    while((r = spi_dummy()) != SD_DATA_TOKEN);
-
-    crc = 0;
-    /* n = 512; */
-    /* do { */
-    /*   uint8_t x = spi_dummy(); */
-    /*   *p++ = x; */
-    /*   crc = crc16(crc, x); */
-    /* } while (--n > 0); */
-
-    n = 512/8;
-    do {
-      // Send 8 dummy bytes (fifo should be empty)
-      for (j = 0; j < 8; j++) {
-        spi_sendbyte(0xff);
-      }
-
-      // Reset counter. Process bytes AS THEY COME IN.
-      for (j = 0; j < 8; j++) {
-        while (!(read_reg(SPI_IP) & 2)) {}
-        uint8_t x = spi_readbyte();
-        *p++ = x;
-        // crc = crc16(crc, x);
-        crc = ((crc << 8) ^ crctable[x ^ (crc >> 8)]) & 0xffff;
-      }
-    } while(--n > 0);
-
-    /* n = 512; */
-    /* // Initially fill the transmit fifo */
-    /* for (j = 0; j < 8; j++) { */
-    /*   spi_sendbyte(0xff); */
-    /* } */
-
-    
-    /* while (n > 0) { */
-    /*   // Wait for bytes to be received */
-    /*   while (!(read_reg(SPI_IP) & 2)) {} */
-    /*   // Read byte */
-    /*   uint8_t x = spi_readbyte(); */
-    /*   // Send another dummy byte */
-    /*   if (n > 8) { */
-    /*     spi_sendbyte(0xff); */
-    /*   } */
-    /*   // Place received byte into memory */
-    /*   *p++ = x; */
-    /*   // Update CRC16 with fast table based method */
-    /*   crc = ((crc << 8) ^ crctable[x ^ (crc >> 8)]) & 0xffff; */
-    /*   n = n - 1; */
-    /* } */
-    
-    // Read CRC16 and check
-    crc_exp = ((uint16_t)spi_dummy() << 8);
-    crc_exp |= spi_dummy();
-
-    if (crc != crc_exp) {
-      print_uart("Stinking CRC16 didn't match on block read.\r\n");
-      print_uart_int(i);
-      print_uart("\r\n");
-      //return -1;
-      fail();
-    }
-
-    if ( (i % modulus) == 0 ) {
-      print_uart("\r          Blocks loaded: ");
-      print_uart_dec(i);
-      print_uart("/");
-      print_uart_dec(count);
-    }
-
-  }
-
-  sd_cmd(SD_CMD_STOP_TRANSMISSION, 0, 0x01);
-
-  print_uart("\r          Blocks loaded: ");
-  print_uart_dec(count);
-  print_uart("/");
-  print_uart_dec(count);
-  print_uart("\r\n");
-  return 0;
-}
-
-// copyFlash: --------------------------------------------------------
-// A lot happens in this function:
-// * The Wally banner is printed
-// * The peripherals are initialized
-void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
-  int ret = 0;
-
-  // Initialize UART for messages
-  init_uart(SYSTEMCLOCK, 115200);
-  
-  // Print the wally banner
-  print_uart(BANNER);
-
-  /* print_uart("System clock speed: "); */
-  /* print_uart_dec(SYSTEMCLOCK); */
-  /* print_uart("\r\n"); */
-
-  // Intialize the SD card
-  init_sd(SYSTEMCLOCK, SDCCLOCK);
-  
-  ret = gpt_load_partitions();
-}
diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h
deleted file mode 100644
index 7d2dbf4b6..000000000
--- a/fpga/zsbl/boot.h
+++ /dev/null
@@ -1,73 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// boot.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header for boot.c, main bootloader entry point
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#ifndef WALLYBOOT
-#define WALLYBOOT 10000
-
-#include <stdint.h>
-#include "system.h"
-typedef unsigned int    UINT;   /* int must be 16-bit or 32-bit */
-typedef unsigned char   BYTE;   /* char must be 8-bit */
-typedef uint16_t        WORD;   /* 16-bit unsigned integer */
-typedef uint32_t        DWORD;  /* 32-bit unsigned integer */
-typedef uint64_t        QWORD;  /* 64-bit unsigned integer */
-typedef WORD            WCHAR;
-
-typedef QWORD LBA_t;
-
-// Define memory locations of boot images =====================
-// These locations are copied from the generic configuration
-// of OpenSBI. These addresses can be found in:
-// buildroot/output/build/opensbi-0.9/platform/generic/config.mk
-
-// FDT_ADDRESS now defined in system.h
-//#define FDT_ADDRESS 0xFF000000        // FW_JUMP_FDT_ADDR
-#define OPENSBI_ADDRESS EXT_MEM_BASE    // FW_TEXT_START
-#define KERNEL_ADDRESS 0x80200000       // FW_JUMP_ADDR
-
-#define BANNER " █▀█        █▀█        █▀█        █▀▀                 █ █\r\n" \
-" █          █ █        █▄▀        █▄▄       ▄▄▄       █ █\r\n" \
-" █▄█        █▄█        █ █        █▄▄                 ▀▄▀\r\n" \
-" ____          ____  ____      ___      ___   ____    ___\r\n"      \
-" \\   \\        /   / /    \\    |   |    |   |  \\   \\  /  /\r\n" \
-"  \\   \\  __  /   / /      \\   |   |    |   |   \\   \\/  /\r\n" \
-"   \\   \\/  \\/   / /   /\\   \\  |   |    |   |    \\     /\r\n" \
-"    \\          / /   ____   \\ |   |___ |   |___  |   |\r\n" \
-"     \\___/\\___/ /___/    \\___\\|_______||_______| |___|\r\n\r\n"
-
-// Export disk_read
-int disk_read(BYTE * buf, LBA_t sector, UINT count);
-
-// Maximum SDC speed is either the system clock divided by 2 (because
-// of the SPI peripheral clock division) or the maximum speed an SD
-// card can be pushed to.
-#define SDCCLOCK (SYSTEMCLOCK/2 > MAXSDCCLOCK ? MAXSDCCLOCK : SYSTEMCLOCK/2)
-
-#endif // WALLYBOOT
-
diff --git a/fpga/zsbl/fail.c b/fpga/zsbl/fail.c
deleted file mode 100644
index 4430c4a8f..000000000
--- a/fpga/zsbl/fail.c
+++ /dev/null
@@ -1,49 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// fail.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Prints information on the uart when a fatal bug is
-//          encountered. Will expand this later.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "fail.h"
-#include "uart.h"
-#include "riscv.h"
-#include "time.h"
-
-void fail() {
-  // Get address that led to failure
-  register uint64_t addr;
-  asm volatile ("mv %0, ra" : "=r"(addr) : : "memory"); 
-
-  // Print message
-  print_time();
-  println_with_addr("Failed at: 0x", addr);
-  
-  // Loop forever
-  while(1) {
-
-  }
-}
diff --git a/fpga/zsbl/fail.h b/fpga/zsbl/fail.h
deleted file mode 100644
index c965265d1..000000000
--- a/fpga/zsbl/fail.h
+++ /dev/null
@@ -1,33 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// fail.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Function prototype for fail,
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#include <stdint.h>
-
-void fail();
diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c
deleted file mode 100644
index e21176f05..000000000
--- a/fpga/zsbl/gpt.c
+++ /dev/null
@@ -1,90 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// gpt.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Code to read GPT Partitions off of an SD card.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "gpt.h"
-#include "boot.h"
-#include "uart.h"
-#include <stddef.h>
-
-int gpt_load_partitions() {
-  // size_t block_size = 512/8;
-  // long int lba1_buf[block_size];
-
-  BYTE lba1_buf[512];
-  
-  int ret = 0;
-  //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */);
-  print_time();
-  println("Getting GPT information.");
-  ret = disk_read(lba1_buf, 1, 1);
-
-  gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf;
-
-  print_time();
-  println("Getting partition entries.");
-  BYTE lba2_buf[512];
-  ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1);
-
-  // Load parition entries for the relevant boot partitions.
-  partition_entries_t *fdt = (partition_entries_t *)(lba2_buf);
-  partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128);
-  partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256);
-
-  // Load device tree
-  print_time();
-  println_with_int("Loading device tree at: 0x", FDT_ADDRESS);
-  ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1);
-  if (ret < 0) {
-    print_uart("Failed to load device tree!\r\n");
-    return -1;
-  }
-
-  // Load OpenSBI
-  print_time();
-  println_with_int("Loading OpenSBI at: 0x", OPENSBI_ADDRESS);
-  ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1);
-  if (ret < 0) {
-    print_uart("Failed to load OpenSBI!\r\n");
-    return -1;
-  }
-
-  // Load Linux
-  print_time();
-  println_with_int("Loading Linux Kernel at: 0x", KERNEL_ADDRESS);
-  ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1);
-  if (ret < 0) {
-    print_uart("Failed to load Linux!\r\n");
-    return -1;
-  }
-
-  print_time();
-  println("Done! Flashing LEDs and jumping to OpenSBI...");
-
-  return 0;
-}
diff --git a/fpga/zsbl/gpt.h b/fpga/zsbl/gpt.h
deleted file mode 100644
index 8cd3ecc11..000000000
--- a/fpga/zsbl/gpt.h
+++ /dev/null
@@ -1,69 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// gpt.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header for gpt.c, contains gpt structs
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-
-#include <stdint.h>
-#include "boot.h"
-
-// LBA 0: Protective MBR
-// ignored here
-
-// Partition Table Header (LBA 1)
-typedef struct gpt_pth
-{
-    uint64_t signature;
-    uint32_t revision;
-    uint32_t header_size; //! little endian, usually 0x5c = 92
-    uint32_t crc_header;
-    uint32_t reserved; //! must be 0
-    uint64_t current_lba;
-    uint64_t backup_lba;
-    uint64_t first_usable_lba;
-    uint64_t last_usable_lba;
-    uint8_t disk_guid[16];
-    uint64_t partition_entries_lba;
-    uint32_t nr_partition_entries;
-    uint32_t size_partition_entry; //! usually 0x80 = 128
-    uint32_t crc_partition_entry;
-} gpt_pth_t;
-
-// Partition Entries (LBA 2-33)
-typedef struct partition_entries
-{
-    uint8_t partition_type_guid[16];
-    uint8_t partition_guid[16];
-    uint64_t first_lba;
-    uint64_t last_lba; //! inclusive
-    uint64_t attributes;
-    uint8_t name[72]; //! utf16 encoded
-} partition_entries_t;
-
-// Find boot partition and load it to the destination
-int gpt_load_partitions();
diff --git a/fpga/zsbl/linker1000.x b/fpga/zsbl/linker1000.x
deleted file mode 100644
index b479e73dd..000000000
--- a/fpga/zsbl/linker1000.x
+++ /dev/null
@@ -1,244 +0,0 @@
-OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
-	      "elf64-littleriscv")
-OUTPUT_ARCH(riscv)
-ENTRY(_start)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  /* init segment to ensure we get a consistent start routine*/
-  . = 0x0000000000001000; 
-  . = ALIGN(0x0); 
-  .init : {  
-  	*(.init) 
-  } 
-  _start_end = .;
-  
-  PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0)); . = SEGMENT_START("text-segment", _start_end);
-  .interp         : { *(.interp) }
-  .note.gnu.build-id  : { *(.note.gnu.build-id) }
-  .hash           : { *(.hash) }
-  .gnu.hash       : { *(.gnu.hash) }
-  .dynsym         : { *(.dynsym) }
-  .dynstr         : { *(.dynstr) }
-  .gnu.version    : { *(.gnu.version) }
-  .gnu.version_d  : { *(.gnu.version_d) }
-  .gnu.version_r  : { *(.gnu.version_r) }
-  .rela.dyn       :
-    {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
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-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-      PROVIDE_HIDDEN (__rela_iplt_start = .);
-      *(.rela.iplt)
-      PROVIDE_HIDDEN (__rela_iplt_end = .);
-    }
-  .rela.plt       :
-    {
-      *(.rela.plt)
-    }
-  .init           :
-  {
-    KEEP (*(SORT_NONE(.init)))
-  }
-  .plt            : { *(.plt) }
-  .iplt           : { *(.iplt) }
-  .text           :
-  {
-    *(.text.unlikely .text.*_unlikely .text.unlikely.*)
-    *(.text.exit .text.exit.*)
-    *(.text.startup .text.startup.*)
-    *(.text.hot .text.hot.*)
-    *(.text .stub .text.* .gnu.linkonce.t.*)
-    /* .gnu.warning sections are handled specially by elf64.em.  */
-    *(.gnu.warning)
-  }
-  .fini           :
-  {
-    KEEP (*(SORT_NONE(.fini)))
-  }
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  . = 0x0000000000002000;
-  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
-  .rodata1        : { *(.rodata1) }
-  .sdata2         :
-  {
-    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
-  }
-  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
-  .eh_frame_hdr   : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
-  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }
-  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
-  .gnu_extab   : ONLY_IF_RO { *(.gnu_extab*) }
-  /* These sections are generated by the Sun/Oracle C++ compiler.  */
-  .exception_ranges   : ONLY_IF_RO { *(.exception_ranges*) }
-  /* Adjust the address for the data segment.  We want to adjust up to
-     the same address within the page on the next page up.  */
-  . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
-  /* Exception handling  */
-  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) }
-  .gnu_extab      : ONLY_IF_RW { *(.gnu_extab) }
-  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
-  .exception_ranges   : ONLY_IF_RW { *(.exception_ranges*) }
-  /* Thread Local Storage sections  */
-  .tdata	  :
-   {
-     PROVIDE_HIDDEN (__tdata_start = .);
-     *(.tdata .tdata.* .gnu.linkonce.td.*)
-   }
-  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
-  .preinit_array    :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  }
-  .init_array    :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  }
-  .fini_array    :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
-    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  }
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-       the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  }
-  .dtors          :
-  {
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  }
-  .jcr            : { KEEP (*(.jcr)) }
-  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
-  .dynamic        : { *(.dynamic) }
-  . = DATA_SEGMENT_RELRO_END (0, .);
-  .data           :
-  {
-    __DATA_BEGIN__ = .;
-    *(.data .data.* .gnu.linkonce.d.*)
-    SORT(CONSTRUCTORS)
-  }
-  .data1          : { *(.data1) }
-  .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata          :
-  {
-    __SDATA_BEGIN__ = .;
-    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
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-  _edata = .; PROVIDE (edata = .);
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-  .sbss           :
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-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
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-   *(.bss .bss.* .gnu.linkonce.b.*)
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-      _end.  Align after .bss to ensure correct alignment even if the
-      .bss section disappears because there are no input sections.
-      FIXME: Why do we need it? When there is no .bss section, we do not
-      pad the .data section.  */
-   . = ALIGN(. != 0 ? 64 / 8 : 1);
-  }
-  . = ALIGN(64 / 8);
-  . = SEGMENT_START("ldata-segment", .);
-  . = ALIGN(64 / 8);
-  __BSS_END__ = .;
-    __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
-		            MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
-  _end = .; PROVIDE (end = .);
-  . = DATA_SEGMENT_END (.);
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
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-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment       0 : { *(.comment) }
-  .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
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-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
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-  /* DWARF 3 */
-  .debug_pubtypes 0 : { *(.debug_pubtypes) }
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-  /* DWARF Extension.  */
-  .debug_macro    0 : { *(.debug_macro) }
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-  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
-  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-}
diff --git a/fpga/zsbl/riscv.S b/fpga/zsbl/riscv.S
deleted file mode 100644
index b2d86599c..000000000
--- a/fpga/zsbl/riscv.S
+++ /dev/null
@@ -1,58 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// riscv.S
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Basic utility functions for reading registers
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-.section .text
-.globl read_mcycle
-.type read_mcycle, @function
-read_mcycle:
-    csrr a0, mcycle
-    ret
-
-.section .text
-.globl get_ra
-.type get_ra, @function
-get_ra:
-    mv a0, ra
-    ret
-
-.section .text
-.globl set_status_fs
-.type set_status_fs, @function    
-set_status_fs:
-    lui t1, 0x6
-    csrs mstatus, t1
-    ret
-
-.section .text
-.globl clear_status_fs
-.type clear_status_fs, @function 
-clear_status_fs:
-    lui t1, 0x6
-    csrc mstatus, t1
-    ret
diff --git a/fpga/zsbl/riscv.h b/fpga/zsbl/riscv.h
deleted file mode 100644
index 543fe5cde..000000000
--- a/fpga/zsbl/riscv.h
+++ /dev/null
@@ -1,36 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// riscv.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Function prototypes for riscv utility functions
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#include <stdint.h>
-
-uint64_t read_mcycle();
-uint64_t get_ra();
-void set_status_fs();
-void clear_status_fs();
diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c
deleted file mode 100644
index 1f95d8477..000000000
--- a/fpga/zsbl/sd.c
+++ /dev/null
@@ -1,255 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// sd.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: SD Card protocol functions
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "sd.h"
-#include "spi.h"
-#include "uart.h"
-#include "fail.h"
-#include "time.h"
-
-// Parallel byte update CRC7-CCITT algorithm.
-// The result is the CRC7 result, left shifted over by 1
-// which is perfect, since we append a 1 at the end anyway
-uint8_t crc7(uint8_t prev, uint8_t in) {
-    // CRC polynomial 0x89
-    uint8_t remainder = prev ^ in;
-    remainder ^= (remainder >> 4) ^ (remainder >> 7);
-    remainder = (remainder << 1) ^ (remainder << 4);
-    return remainder & 0xff;
-}
-
-// Need to check this. This could be wrong as well.
-uint16_t crc16(uint16_t crc, uint8_t data) {
-    // CRC polynomial 0x11021
-    crc = (uint8_t)(crc >> 8) | (crc << 8);
-    crc ^= data;
-    crc ^= (uint8_t)(crc >> 4) & 0xf;
-    crc ^= crc << 12;
-    crc ^= (crc & 0xff) << 5;
-    return crc;
-}
-
-// sd_cmd ------------------------------------------------------------
-// Sends SD card command using SPI mode.
-// This function:
-// * Chooses the response length based on the input command
-// * Makes use of SPI's full duplex. For every byte sent,
-//   a byte is received. Thus for every byte sent as part of
-//   a command, a useless byte must be read from the receive
-//   FIFO.
-// * Takes advantage of the Sifive SPI peripheral spec's
-//   watermark and interrupt features to determine when a
-//   transfer is complete. This should save on cycles since
-//   no arbitrary delays need to be added.
-
-uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) {
-  uint8_t response_len;
-  uint8_t i;
-  uint8_t shiftAmnt;
-  uint64_t r;
-  uint8_t rbyte;
-
-  // Initialize the response with 0's.
-  r = 0;
-
-  // Choose response length based on cmd input.
-  // Most commands return an R1 format response.
-  switch (cmd) {
-    case 8:
-      response_len = R7_RESPONSE;
-      break;
-    case 12:
-      response_len = R1B_RESPONSE;
-      break;
-    default:
-      response_len = R1_RESPONSE;
-      break;
-  }
-
-  // Make interrupt pending after response fifo receives the correct
-  // response length.  Probably unecessary so let's wait and see what
-  // happens.
-  // write_reg(SPI_RXMARK, response_len);
-
-  // Chip select must remain asserted during transaction
-  if (cmd != SD_CMD_STOP_TRANSMISSION) {
-    write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD);
-  }
-  
-  // Write all 7 bytes into transfer fifo
-  // spi_sendbyte(0xff);
-  spi_dummy();
-  spi_sendbyte(0x40 | cmd);
-  spi_sendbyte(arg >> 24);
-  spi_sendbyte(arg >> 16);
-  spi_sendbyte(arg >> 8);
-  spi_sendbyte(arg);
-  spi_sendbyte(crc);
-
-  // Wait for command to send
-  // The Transfer IP bit should go high when the txFIFO is empty
-  // while(!(read_reg(SPI_IP) & 1)) {}
-  waittx();
-
-  // Read the dummy rxFIFO entries to move the head back to the tail
-  for (i = 0; i < 7; i++) {
-    spi_readbyte();
-  }
-
-  // Send "dummy signals". Since SPI is duplex,
-  // useless bytes must be transferred
-  /* for (i = 0; i < response_len; i++) { */
-  /*   spi_sendbyte(0xFF); */
-  /* } */
-
-  /* // Wait for transfer fifo again */
-  /* waittx(); */
-
-  // Wait for actual response from SD card
-  // All responses start with a 0. Output of SDCIn is high, unless
-  // a message is being transferred.
-  do {
-    rbyte = spi_dummy();
-  } while ( (rbyte & 0x80) != 0 );
-
-  // Note about the compiler. In order to compile as sll instead of
-  // sllw, the number to shift has to be a 64 bit number.
-  r = ((uint64_t)rbyte) << ((response_len - 1)*8);
-  
-  // Read rxfifo response
-  for (i = 1; i < response_len; i++) {
-    rbyte = spi_dummy();
-    r = r | (((uint64_t)rbyte) << ((response_len - 1 - i)*8));
-  }
-
-  if (cmd != 18) {
-    write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO);
-  } else {
-    spi_dummy();
-  }
-  return r;
-} // sd_cmd
-
-uint64_t sd_read64(uint16_t * crc) {
-  uint64_t r;
-  uint8_t rbyte;
-  int i;
-
-  /* for (i = 0; i < 8; i++) { */
-  /*   spi_sendbyte(0xFF); */
-  /* } */
-
-  /* waittx(); */
-
-  for (i = 0; i < 8; i++) {
-    rbyte = spi_dummy();
-    *crc = crc16(*crc, rbyte);
-    r = r | ((uint64_t)(rbyte) << ((8 - 1 - i)*8));
-  }
-
-  return r;
-}
-
-// Utility defines for CMD0, CMD8, CMD55, and ACMD41
-#define CMD0()   sd_cmd( 0, 0x00000000, 0x95) // Reset SD card into IDLE state
-#define CMD8()   sd_cmd( 8, 0x000001aa, 0x87) // 
-#define CMD55()  sd_cmd(55, 0x00000000, 0x65) //
-#define ACMD41() sd_cmd(41, 0x40000000, 0x77) //
-
-// init_sd: ----------------------------------------------------------
-// This first initializes the SPI peripheral then initializes the SD
-// card itself. We use the uart to display anything that goes wrong.
-int init_sd(uint32_t freq, uint32_t sdclk){
-  print_time();
-  println("Initializing SPI Controller.");
-  spi_init();
-
-  uint64_t r;
-  uint32_t newClockDiv;
-  int n;
-
-  print_time();
-  println("Initializing SD Card in SPI mode.");
-  // This is necessary. This is the card's pre-init state initialization.
-  write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_OFF);
-  for (int i = 0; i < 10; i++) {
-    spi_txrx(0xff);
-  }
-  write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO);
-  
-  // CMD0 --------------------------------------------------------------
-  // Reset SD Card command
-  // Initializes SD card into SPI mode if CS is asserted '0'
-  // We expect to get the R1 response 0x01 which means that the
-  // card has been put into the idle state.
-  print_time();
-  print_uart("CMD0: ");
-  n = 0;
-  do {
-    r = CMD0();
-    n++;
-    if (n == 1000) {
-      fail();
-    }
-  } while ( r != 0x01 );
-  println_with_r1("Success, r = 0x", r & 0xff);
-
-  // CMD8 -------------------------------------------------------------
-  //
-  print_time();
-  print_uart("CMD8: ");
-  r = CMD8();
-  if ((r & 0x000000ff0000ffff) != 0x01000001aa) {
-    println_with_r7("Failed, 0x", r);
-    fail();
-  }
-  println_with_r7("Success, 0x", r);
-
-  // ACMD41 -----------------------------------------------------------
-  print_time();
-  print_uart("ACMD41: ");
-  n = 0;
-  do {
-    CMD55();
-    r = ACMD41();
-    n++;
-    if (n == 1000) {
-      fail();
-    }
-  } while (r == 0x1);
-  println_with_r1("Success, r = 0x", r & 0xff);
-
-  print_time();
-  println_with_dec("New clock frequency: ", (uint64_t)sdclk);
-  spi_set_clock(freq, sdclk);
-  
-  print_time();
-  println("SD card is initialized.");
-}
-
diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h
deleted file mode 100644
index f66686560..000000000
--- a/fpga/zsbl/sd.h
+++ /dev/null
@@ -1,49 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// sd.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header file for SD card protocol functions. Defines some
-//          useful macros.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-
-#include <stdint.h>
-
-// Command names
-#define SD_CMD_STOP_TRANSMISSION 12
-#define SD_CMD_READ_BLOCK_MULTIPLE 18
-#define SD_DATA_TOKEN 0xfe
-
-// Response lengths in bytes
-#define R1_RESPONSE  1
-#define R7_RESPONSE  5
-#define R1B_RESPONSE 2
-
-uint8_t crc7(uint8_t prev, uint8_t in);
-uint16_t crc16(uint16_t crc, uint8_t data);
-uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc);
-uint64_t sd_read64(uint16_t * crc);
-int init_sd(uint32_t freq, uint32_t sdclk);
diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c
deleted file mode 100644
index 4e75086ad..000000000
--- a/fpga/zsbl/spi.c
+++ /dev/null
@@ -1,91 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// spi.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: SPI Controller API for bootloader
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "spi.h"
-
-uint8_t spi_txrx(uint8_t byte) {
-  spi_sendbyte(byte);
-  waitrx();
-  return spi_readbyte();
-}
-
-uint8_t spi_dummy() {
-  return spi_txrx(0xff);
-}
-
-uint64_t spi_read64() {
-  uint64_t r;
-  uint8_t rbyte;
-  int i;
-
-  for (i = 0; i < 8; i++) {
-    spi_sendbyte(0xFF);
-  }
-
-  waittx();
-
-  for (i = 0; i < 8; i++) {
-    rbyte = spi_readbyte();
-    r = r | (rbyte << ((8 - 1 - i)*8));
-  }
-
-  return r;
-}
-
-void spi_set_clock(uint32_t clkin, uint32_t clkout) {
-  uint32_t div = (clkin/(2*clkout)) - 1;
-  write_reg(SPI_SCKDIV, div);
-}
-
-// Initialize Sifive FU540 based SPI Controller
-void spi_init(uint32_t clkin) {
-  // Enable interrupts
-  write_reg(SPI_IE, 0x3);
-
-  // Set TXMARK to 1. If the number of entries is < 1
-  // IP's txwm field will go high.
-  // Set RXMARK to 0. If the number of entries is > 0
-  // IP's rwxm field will go high.
-  write_reg(SPI_TXMARK, 1);
-  write_reg(SPI_RXMARK, 0);
-
-  // Set Delay 0 to default
-  write_reg(SPI_DELAY0,
-            SIFIVE_SPI_DELAY0_CSSCK(1) |
-			SIFIVE_SPI_DELAY0_SCKCS(1));
-
-  // Set Delay 1 to default
-  write_reg(SPI_DELAY1,
-            SIFIVE_SPI_DELAY1_INTERCS(1) |
-            SIFIVE_SPI_DELAY1_INTERXFR(0));
-
-  // Initialize the SPI controller clock to 
-  // div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18 
-  write_reg(SPI_SCKDIV, 0x18); 
-}
diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h
deleted file mode 100644
index 5a472142f..000000000
--- a/fpga/zsbl/spi.h
+++ /dev/null
@@ -1,116 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// spi.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header file for interfaceing with the SPI peripheral
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#ifndef SPI_HEADER
-#define SPI_HEADER
-
-#include <stdint.h>
-
-#define SPI_BASE              0x13000 /* Base address of SPI device used for SDC */
-
-/* register offsets */
-#define SPI_SCKDIV            SPI_BASE + 0x00 /* Serial clock divisor */
-#define SPI_SCKMODE           SPI_BASE + 0x04 /* Serial clock mode */
-#define SPI_CSID              SPI_BASE + 0x10 /* Chip select ID */
-#define SPI_CSDEF             SPI_BASE + 0x14 /* Chip select default */
-#define SPI_CSMODE            SPI_BASE + 0x18 /* Chip select mode */
-#define SPI_DELAY0            SPI_BASE + 0x28 /* Delay control 0 */
-#define SPI_DELAY1            SPI_BASE + 0x2c /* Delay control 1 */
-#define SPI_FMT               SPI_BASE + 0x40 /* Frame format */
-#define SPI_TXDATA            SPI_BASE + 0x48 /* Tx FIFO data */
-#define SPI_RXDATA            SPI_BASE + 0x4c /* Rx FIFO data */
-#define SPI_TXMARK            SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */
-#define SPI_RXMARK            SPI_BASE + 0x54 /* Rx FIFO watermark */
-
-/* Non-implemented
-#define SPI_FCTRL             SPI_BASE + 0x60 // SPI flash interface control
-#define SPI_FFMT              SPI_BASE + 0x64 // SPI flash instruction format
-*/
-#define SPI_IE                SPI_BASE + 0x70 /* Interrupt Enable Register */
-#define SPI_IP                SPI_BASE + 0x74 /* Interrupt Pendings Register */
-
-/* delay0 bits */
-#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((uint32_t)(x))
-#define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
-#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((uint32_t)(x) << 16)
-#define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
-
-/* delay1 bits */
-#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((uint32_t)(x))
-#define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
-#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((uint32_t)(x) << 16)
-#define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
-
-/* csmode bits */
-#define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
-#define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
-#define SIFIVE_SPI_CSMODE_MODE_OFF       3U
-
-// inline void write_reg(uintptr_t addr, uint32_t value);
-//inline uint32_t read_reg(uintptr_t addr);
-//inline void spi_sendbyte(uint8_t byte);
-//inline void waittx();
-//inline void waitrx();
-uint8_t spi_txrx(uint8_t byte);
-uint8_t spi_dummy();
-//inline uint8_t spi_readbyte();
-uint64_t spi_read64();
-void spi_init();
-void spi_set_clock(uint32_t clkin, uint32_t clkout);
-
-static inline void write_reg(uintptr_t addr, uint32_t value) {
-  volatile uint32_t * loc = (volatile uint32_t *) addr;
-  *loc = value;
-}
-
-// Read a register
-static inline uint32_t read_reg(uintptr_t addr) {
-  return *(volatile uint32_t *) addr;
-}
-
-// Queues a single byte in the transfer fifo
-static inline void spi_sendbyte(uint8_t byte) {
-  // Write byte to transfer fifo
-  write_reg(SPI_TXDATA, byte);
-}
-
-static inline void waittx() {
-  while(!(read_reg(SPI_IP) & 1)) {}
-}
-
-static inline void waitrx() {
-  while(!(read_reg(SPI_IP) & 2)) {}
-}
-
-static inline uint8_t spi_readbyte() {
-  return read_reg(SPI_RXDATA);
-}
-
-#endif
diff --git a/fpga/zsbl/splitfile.sh b/fpga/zsbl/splitfile.sh
deleted file mode 100755
index fc943576c..000000000
--- a/fpga/zsbl/splitfile.sh
+++ /dev/null
@@ -1,48 +0,0 @@
-#######################################################################
-# splitfile.sh
-#
-# Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-#
-# Purpose: Used to split boot.mem into two sections for FPGA
-#
-# 
-#
-# A component of the Wally configurable RISC-V project.
-# 
-# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Licensed under the Solderpad Hardware License v 2.1 (the
-# “License”); you may not use this file except in compliance with the
-# License, or, at your option, the Apache License version 2.0. You
-# may obtain a copy of the License at
-#
-# https://solderpad.org/licenses/SHL-2.1/
-#
-# Unless required by applicable law or agreed to in writing, any work
-# distributed under the License is distributed on an “AS IS” BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-######################################################################
-
-
-# Acquired from here.
-# https:##stackoverflow.com#questions#3066948#how-to-file-split-at-a-line-number
-file_name=$1
-
-# set first K lines:
-K=512
-
-# line count (N): 
-N=$(wc -l < $file_name)
-
-# length of the bottom file:
-L=$(( $N - $K ))
-
-# create the top of file: 
-head -n $K $file_name > boot.mem
-
-# create bottom of file: 
-tail -n $L $file_name > data.mem
diff --git a/fpga/zsbl/system.h b/fpga/zsbl/system.h
deleted file mode 100644
index 02301e763..000000000
--- a/fpga/zsbl/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __system_H
-#define __system_H
-
-#ifndef SYSTEMCLOCK
-#define SYSTEMCLOCK  100000000
-#endif
-
-#ifndef MAXSDCCLOCK
-#define MAXSDCCLOCK  5000000
-#endif
-
-#ifndef EXT_MEM_BASE
-#define EXT_MEM_BASE 0x80000000
-#endif
-
-#ifndef EXT_MEM_RANGE
-#define EXT_MEM_RANGE  0x10000000
-#endif
-
-#define EXT_MEM_END (EXT_MEM_BASE + EXT_MEM_RANGE)
-#define FDT_ADDRESS (EXT_MEM_END - 0x1000000)
-
-#endif
diff --git a/fpga/zsbl/time.c b/fpga/zsbl/time.c
deleted file mode 100644
index c265eea05..000000000
--- a/fpga/zsbl/time.c
+++ /dev/null
@@ -1,49 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// time.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Gets and prints the current time.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "time.h"
-#include "boot.h"
-#include "riscv.h"
-#include "uart.h"
-
-float getTime() {
-  set_status_fs();
-  float numCycles = (float)read_mcycle();
-  float ret = numCycles/SYSTEMCLOCK;
-  // clear_status_fs();
-  return ret;
-}
-
-void print_time() {
-  print_uart("[");
-  set_status_fs();
-  print_uart_float(getTime(),5);
-  clear_status_fs();
-  print_uart("] ");
-}
diff --git a/fpga/zsbl/time.h b/fpga/zsbl/time.h
deleted file mode 100644
index 8bf7064af..000000000
--- a/fpga/zsbl/time.h
+++ /dev/null
@@ -1,34 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// spi.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Time function prototypes
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#include <stdint.h>
-
-float getTime();
-void print_time();
diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c
deleted file mode 100644
index 580265d98..000000000
--- a/fpga/zsbl/uart.c
+++ /dev/null
@@ -1,193 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// uart.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Uart printing functions, as well as functions for printing
-//          hex, decimal, and floating point numbers.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "uart.h"
-
-void write_reg_u8(uintptr_t addr, uint8_t value)
-{
-  volatile uint8_t *loc_addr = (volatile uint8_t *)addr;
-  *loc_addr = value;
-}
-
-uint8_t read_reg_u8(uintptr_t addr)
-{
-  return *(volatile uint8_t *)addr;
-}
-
-int is_transmit_empty()
-{
-  return read_reg_u8(UART_LSR) & 0x20;
-}
-
-int is_receive_empty()
-{
-  return !(read_reg_u8(UART_LSR) & 0x1);
-}
-
-void write_serial(char a)
-{
-  while (is_transmit_empty() == 0) {};
-
-  write_reg_u8(UART_THR, a);
-}
-
-void init_uart(uint32_t freq, uint32_t baud)
-{
-  // Alternative divisor calculation. From OpenSBI code.
-  // Reduces error for every possible frequency.
-  uint32_t divisor = (freq + 8 * baud) /(baud << 4);
-
-  write_reg_u8(UART_IER, 0x00);                   // Disable all interrupts
-  write_reg_u8(UART_LCR, 0x80);                   // Enable DLAB (set baud rate divisor)
-  write_reg_u8(UART_DLL, divisor & 0xFF);         // divisor (lo byte)
-  write_reg_u8(UART_DLM, (divisor >> 8) & 0xFF);  // divisor (hi byte)
-  write_reg_u8(UART_LCR, 0x03);                   // 8 bits, no parity, one stop bit
-  write_reg_u8(UART_FCR, 0xC7);                   // Enable FIFO, clear them, with 14-byte threshold
-}
-
-void print_uart(const char *str)
-{
-  const char *cur = &str[0];
-  while (*cur != '\0') {
-    write_serial((uint8_t)*cur);
-    ++cur;
-  }
-}
-
-uint8_t bin_to_hex_table[16] = {
-  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'};
-
-void bin_to_hex(uint8_t inp, uint8_t res[2])
-{
-  res[1] = bin_to_hex_table[inp & 0xf];
-  res[0] = bin_to_hex_table[(inp >> 4) & 0xf];
-  return;
-}
-
-void print_uart_hex(uint64_t addr, int n)
-{
-  int i;
-  for (i = n - 1; i > -1; i--) {
-    uint8_t cur = (addr >> (i * 8)) & 0xff;
-    uint8_t hex[2];
-    bin_to_hex(cur, hex);
-    write_serial(hex[0]);
-    write_serial(hex[1]);
-  }
-}
-
-void print_uart_dec(uint64_t addr) {
-
-  // floor(log(2^64)) = 19
-  char str[19] = {'\0'};
-  uint8_t length = 1;
-  
-  uint64_t cur = addr;
-  while (cur != 0) {
-    char digit = bin_to_hex_table[cur % 10];
-    // write_serial(digit);
-    str[length] = digit;
-    cur = cur/10;
-    length++;
-  }
-
-  for (int i = length; i > -1; i--) {
-    write_serial(str[i]);
-  }
-}
-
-// Print a floating point number on the UART 
-void print_uart_float(float num, int precision) {
-  char str[32] = {'\0'};
-  char digit;
-  uint8_t length = precision + 1;
-  int i;
-  uint64_t cur;
-  
-  str[precision] = '.';
-
-  int pow = 1;
-
-  // Calculate power for precision
-  for (i = 0; i < precision; i++) {
-    pow = pow * 10;
-  }
-  
-  cur = (uint64_t)(num * pow);
-  for (i = 0; i < precision; i++) {
-    digit = bin_to_hex_table[cur % 10];
-    str[i] = digit;
-    cur = cur / 10;
-  }
-
-  cur = (uint64_t)num;
-  do {
-    digit = bin_to_hex_table[cur % 10];
-    str[length] = digit;
-    cur = cur/10;
-    length++;
-  } while (cur != 0);
-  
-  for (i = length; i > -1; i--) {
-    write_serial(str[i]);
-  }
-}
-
-/* void print_uart_int(uint32_t addr) */
-/* { */
-/*   int i; */
-/*   for (i = 3; i > -1; i--)  { */
-/*     uint8_t cur = (addr >> (i * 8)) & 0xff; */
-/*     uint8_t hex[2]; */
-/*     bin_to_hex(cur, hex); */
-/*     write_serial(hex[0]); */
-/*     write_serial(hex[1]); */
-/*   } */
-/* } */
-
-/* void print_uart_addr(uint64_t addr) */
-/* { */
-/*   int i; */
-/*   for (i = 7; i > -1; i--) { */
-/*     uint8_t cur = (addr >> (i * 8)) & 0xff; */
-/*     uint8_t hex[2]; */
-/*     bin_to_hex(cur, hex); */
-/*     write_serial(hex[0]); */
-/*     write_serial(hex[1]); */
-/*   } */
-/* } */
-
-/* void print_uart_byte(uint8_t byte) */
-/* { */
-/*   uint8_t hex[2]; */
-/*   bin_to_hex(byte, hex); */
-/*   write_serial(hex[0]); */
-/*   write_serial(hex[1]); */
-/* } */
diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h
deleted file mode 100644
index 96c55ffe8..000000000
--- a/fpga/zsbl/uart.h
+++ /dev/null
@@ -1,87 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// uart.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header for the UART functions.
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#include <stdint.h>
-#include "riscv.h"
-#include "time.h"
-
-// UART register addresses
-#define UART_BASE 0x10000000
-
-#define UART_RBR UART_BASE + 0x00
-#define UART_THR UART_BASE + 0x00
-#define UART_IER UART_BASE + 0x01
-#define UART_IIR UART_BASE + 0x02
-#define UART_FCR UART_BASE + 0x02
-#define UART_LCR UART_BASE + 0x03
-#define UART_MCR UART_BASE + 0x04
-#define UART_LSR UART_BASE + 0x05
-#define UART_MSR UART_BASE + 0x06
-#define UART_SCR UART_BASE + 0x07
-#define UART_DLL UART_BASE + 0x00
-#define UART_DLM UART_BASE + 0x01
-
-// Primary function prototypes
-void init_uart(uint32_t freq, uint32_t baud);
-void write_reg_u8(uintptr_t addr, uint8_t value);
-uint8_t read_reg_u8(uintptr_t addr);
-int read_serial(uint8_t *res);
-void print_uart(const char* str);
-void print_uart_int(uint32_t addr);
-void print_uart_dec(uint64_t addr);
-void print_uart_addr(uint64_t addr);
-void print_uart_hex(uint64_t addr, int n);
-void print_uart_byte(uint8_t byte);
-void print_uart_float(float num, int precision);
-// void print_time();
-
-// Print numbers in hex with specified widths
-#define print_uart_int(addr) print_uart_hex(addr, 4)
-#define print_uart_addr(addr) print_uart_hex(addr, 8)
-#define print_uart_byte(addr) print_uart_hex(addr, 1)
-#define print_r7(addr) print_uart_hex(addr, 5)
-#define print_r1(addr) print_uart_byte(addr)
-
-// Print line with numbers utility macros
-#define println(msg) print_uart(msg "\r\n");
-#define println_with_dec(msg, num) print_uart(msg); print_uart_dec(num); print_uart("\r\n")
-#define println_with_byte(msg, num) print_uart(msg); print_uart_byte(num); print_uart("\r\n")
-#define println_with_int(msg, num) print_uart(msg); print_uart_int(num); print_uart("\r\n")
-#define println_with_addr(msg, num) print_uart(msg); print_uart_addr(num); print_uart("\r\n")
-#define println_with_r1(msg, num) print_uart(msg); print_r1(num); print_uart("\r\n")
-#define println_with_r7(msg, num) print_uart(msg); print_r7(num); print_uart("\r\n")
-#define println_with_float(msg, num) print_uart(msg); set_status_fs(); print_uart_float(num,5); clear_status_fs(); print_uart("\r\n")
-
-/* #define print_time() print_uart("["); \ */
-/*   set_status_fs();                    \ */
-/*   print_uart_float(getTime(),5);      \ */
-/*   clear_status_fs();                  \ */
-/*   print_uart("] ") */
-
diff --git a/linux/Makefile b/linux/Makefile
deleted file mode 100644
index 58cb6c69b..000000000
--- a/linux/Makefile
+++ /dev/null
@@ -1,138 +0,0 @@
-BUILDROOT         := buildroot
-IMAGE_DIR         := ${BUILDROOT}/output/images
-DISASSEMBLY_DIR   := ${IMAGE_DIR}/disassembly
-WALLYLINUX        := $(WALLY)/linux
-BR2_EXTERNAL_TREE := $(WALLYLINUX)/br2-external-tree
-LINUX_TESTVECTORS := $(RISCV)/linux-testvectors
-
-BUILDROOT_OUTPUTS := Image fw_jump.bin fw_jump.elf rootfs.cpio vmlinux busybox
-BUILDROOT_OUTPUTS := $(foreach name, $(BUILDROOT_OUTPUTS), $(IMAGE_DIR)/$(name))
-
-# Device tree files
-DTS ?= $(wildcard devicetree/*.dts)
-DTB := $(foreach name, $(DTS:%.dts=%.dtb), $(IMAGE_DIR)/$(notdir $(name)))
-
-# Disassembly files
-BINARIES := fw_jump.elf vmlinux busybox
-OBJDUMPS := $(foreach name, $(basename $(BINARIES) .elf), $(DISASSEMBLY_DIR)/$(name).objdump)
-
-# Testvector files
-RAW_RAM_FILE     := ${LINUX_TESTVECTORS}/ramGDB.bin
-RAM_FILE         := ${LINUX_TESTVECTORS}/ram.bin
-RAW_BOOTMEM_FILE := ${LINUX_TESTVECTORS}/bootmemGDB.bin
-BOOTMEM_FILE     := ${LINUX_TESTVECTORS}/bootmem.bin
-
-.PHONY: all check_environment check_write_permissions config build disassemble devicetrees install dumptvs clean cleanDTB
-
-# Default target
-all: check_write_permissions clean config build disassemble install dumptvs
-
-# Check if the environment variables are set correctly
-check_environment: $(RISCV) $(WALLY)
-ifeq ($(findstring :$(RISCV)/lib:,:$(LD_LIBRARY_PATH):),)
-	@(echo "ERROR: Your environment variables are not set correctly." >&2 \
-	&& echo "Make sure to source setup.sh or install buildroot using the wally-tool-chain-install.sh script." >&2 \
-	&& exit 1)
-endif
-
-# Check if the user has write permissions to the RISCV directory, potentially using sudo
-SUDO := $(shell mkdir -p $(RISCV)/.test > /dev/null 2>&1 || echo sudo)
-check_write_permissions: check_environment
-ifeq ($(SUDO), sudo)
-	@echo "Cannot write to '$(RISCV)'." \
-		"Using sudo (you may be prompted for your password several times throughout the install)"
-endif
-	@$(SUDO) mkdir -p $(RISCV)/.test || \
-		(echo "ERROR: Still unable to write to '$(RISCV)'." >&2 \
-		&& exit 1)
-	@$(SUDO) rm -r $(RISCV)/.test
-
-# Build buildroot and device tree binaries
-build: $(BUILDROOT_OUTPUTS) devicetrees
-
-# Build buildroot itself
-# LD_LIBRARY_PATH must be unset to avoid conflicts between the host and cross compiler
-$(BUILDROOT_OUTPUTS) $(IMAGE_DIR): check_environment $(BUILDROOT)
-	bash -c "unset LD_LIBRARY_PATH; $(MAKE) -C $(BUILDROOT)"
-
-# Install buildroot to $RISCV
-install: check_write_permissions
-	$(SUDO) rm -rf $(RISCV)/$(BUILDROOT)
-	$(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
-
-# Generate linux boot testvectors
-dumptvs: ${RAM_FILE} ${BOOTMEM_FILE}
-
-# Format QEMU memory dumps for use as testvectors
-${LINUX_TESTVECTORS}/%.bin: ${LINUX_TESTVECTORS}/%GDB.bin
-	truncate -s %8 $^ # Extend file to 8 byte multiple
-	objcopy --reverse-bytes=8 -F binary $^ $@ # Reverse bytes
-
-# Generate memory dumps from QEMU buildroot boot
-TCP_PORT := 1235
-${LINUX_TESTVECTORS}/%GDB.bin: | $(LINUX_TESTVECTORS)
-	${WALLYLINUX}/qemuBoot.sh --gdb ${TCP_PORT} &
-	riscv64-unknown-elf-gdb -batch \
-		-ex "target remote :${TCP_PORT}" \
-		-ex "maintenance packet Qqemu.PhyMemMode:1" \
-		-ex "printf \"Creating ${RAW_BOOTMEM_FILE}\n\"" \
-		-ex "dump binary memory ${RAW_BOOTMEM_FILE} 0x1000 0x1fff" \
-		-ex "printf \"Creating ${RAW_RAM_FILE}\n\"" \
-		-ex "dump binary memory ${RAW_RAM_FILE} 0x80000000 0x8fffffff" \
-		-ex "kill"
-
-# Generate device tree binaries
-devicetrees: $(DTB)
-$(IMAGE_DIR)/%.dtb: ${WALLYLINUX}/devicetree/%.dts | $(IMAGE_DIR)
-	dtc -I dts -O dtb $< > $@
-
-# Create disassembly files
-disassemble: check_environment $(OBJDUMPS) $(DISASSEMBLY_DIR)/rootfs
-
-# Extract rootfs
-$(DISASSEMBLY_DIR)/rootfs: $(IMAGE_DIR)/rootfs.cpio
-	@echo "Ignore error about dev/console when extracting rootfs from rootfs.cpio"
-	-cpio -id -D $(DISASSEMBLY_DIR)/rootfs -F $(IMAGE_DIR)/rootfs.cpio
-
-# Disassemble binaries
-$(DISASSEMBLY_DIR)/%.objdump: $(IMAGE_DIR)/% | $(DISASSEMBLY_DIR)
-	riscv64-unknown-elf-objdump -S $< >> $@
-	$(WALLY)/bin/extractFunctionRadix.sh $@
-
-# Disassemble binaries ending in .elf
-$(DISASSEMBLY_DIR)/%.objdump: $(IMAGE_DIR)/%.elf | $(DISASSEMBLY_DIR)
-	riscv64-unknown-elf-objdump -SD $< >> $@
-	$(WALLY)/bin/extractFunctionRadix.sh $@
-
-# Load wally buildroot configuration
-config: $(BUILDROOT) $(BR2_EXTERNAL_TREE)/configs/wally_defconfig
-	$(MAKE) -C $(BUILDROOT) wally_defconfig BR2_EXTERNAL=$(BR2_EXTERNAL_TREE)
-
-# Clone buildroot and checkout the correct version
-$(BUILDROOT):
-	git clone https://github.com/buildroot/buildroot.git $@
-	cd $@; git checkout 2024.11.x
-
-# Create directories
-$(LINUX_TESTVECTORS): check_write_permissions
-	$(SUDO) mkdir -p $@
-
-$(DISASSEMBLY_DIR):
-	mkdir -p $@
-
-# Remove device tree binaries
-cleanDTB:
-	rm -f $(IMAGE_DIR)/*.dtb
-
-# Remove buildroot directory
-clean:
-	rm -rf $(BUILDROOT)
-
-# Check if the RISCV environment variable is set
-$(RISCV):
-	@ echo "ERROR: No $(RISCV) directory. Make sure you have installed the Wally Toolchain."
-	@ echo "and sourced setup.sh"
-
-# Check if the WALLY environment variable is set
-$(WALLY):
-	@ echo "ERROR: $$WALLY is not set. Make sure you have sourced setup.sh"
diff --git a/linux/README.MD b/linux/README.MD
deleted file mode 100644
index 2e8405f70..000000000
--- a/linux/README.MD
+++ /dev/null
@@ -1,75 +0,0 @@
-# Linux for core-v-wally
-
-## Table of Contents
-
-1. [Setting up Buildroot](#buildroot)
-2. [Generating Device Tree Binaries](#devicetree)
-3. [Disassembling the Binaries for Debugging](#disassembly)
-4. [Generating test-vectors for regression](#testvectors)
-5. [Creating a Bootable SD Card](#sdcard)
-
-## Setting up Buildroot <a name="buildroot"></a>
-
-In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation.
-
-To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well.
-
-This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). The main Wally installation script (`bin/wally-tool-chain-install.sh`) runs this by default, so buildroot is likely already setup. Otherwise, to install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, and generate testvectors for simulation run:
-
-```bash
-$ make
-```
-
-This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISCV/buildroot` and the test-vectors are installed to `$RISCV/linux-testvectors`.
-
-Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory.
-
-```bash
-$ make install BUILDROOT=<path/to/buildroot>
-```
-
-## Generating Device Tree Binaries <a name="devicetree"></a>
-
-The device tree files for the various FPGAs Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process.
-
-They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using:
-
-```bash
-$ make devicetrees # optionally override BUILDROOT
-```
-
-The .dts files will end up in the `<BUILDROOT>/output/images` folder of your chosen buildroot directory.
-
-## Disassembling the Binaries for Debugging <a name="disassembly"></a>
-
-By using the `riscv64-unknown-elf-objdump` utility, we can disassemble the binaries in `<BUILDROOT>/output/images` so that we can explore the resulting machine code instructions and see what assembly or C code the instructions came from, along with the corresponding addresses. This is useful during debugging in order to trace how code is being executed.
-
-The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run:
-
-```bash
-$ make disassemble # optionally override BUILDROOT
-```
-
-You'll find the resulting disassembled files in `<BUILDROOT>/output/images/disassembly`.
-
-## Generate Memory Files for Linux Boot <a name="testvectors"></a>
-
-Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to `$RISCV/linux-testvectors`. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running
-
-```bash
-$ make dumptvs
-```
-
-## Creating a Bootable SD Card <a name="sdcard"></a>
-
-To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `<WALLY>/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type:
-
-```bash
-$ cd sdcard
-$ ./flash-sd.sh -b <path/to/buildroot> -d <device tree name> <DEVICE>
-```
-
-for example
-```bash
-$ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb
-```
diff --git a/linux/bootmem.txt b/linux/bootmem.txt
new file mode 100644
index 000000000..047cf5529
--- /dev/null
+++ b/linux/bootmem.txt
@@ -0,0 +1,12 @@
+00001000: 00000297		auipc t0, 0		# t0 = 0x00001000
+00001004: 02828613		addi a2, t0,0x28	# a2 = 0x00001028
+00001008: f1402573		csrr a0, mhartid	# a0 = mhartid
+0000100c: 0202b583		ld a1, 32(t0) 		# a1 = 87000000 - device tree address
+00001010: 0182b283		ld t0, 24(t0)		# t0 = 80000000 - start of firmware
+00001014: 00028067		jr t0			# jump to firmware
+00001018: 0000000080000000			# firmware start address
+00001020: 0000000087000000			# flattened device tree load address
+00001028: 000000004942534f			# a2 points to this 8 dword data structure
+00001030: 0000000000000002
+00001038: 0000000080200000
+00001040: 0000000000000001
diff --git a/linux/br2-external-tree/Config.in b/linux/br2-external-tree/Config.in
deleted file mode 100644
index 6e3475255..000000000
--- a/linux/br2-external-tree/Config.in
+++ /dev/null
@@ -1,2 +0,0 @@
-# required for buildroot external tree
-# delibarately empty
diff --git a/linux/br2-external-tree/board/wally/linux.config b/linux/br2-external-tree/board/wally/linux.config
deleted file mode 100644
index 53c2c1866..000000000
--- a/linux/br2-external-tree/board/wally/linux.config
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname"
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
-# CONFIG_RD_GZIP is not set
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-# CONFIG_RD_ZSTD is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSFS_SYSCALL is not set
-# CONFIG_RISCV_ISA_V is not set
-# CONFIG_SUSPEND is not set
-CONFIG_JUMP_LABEL=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-# CONFIG_GCC_PLUGINS is not set
-CONFIG_MODULES=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_SERIAL_SIFIVE_CONSOLE=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_SPI=y
-CONFIG_SPI_SIFIVE=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIOLIB_FASTPATH_LIMIT=32
-# CONFIG_GPIO_CDEV_V1 is not set
-CONFIG_GPIO_SIFIVE=y
-# CONFIG_HWMON is not set
-# CONFIG_HID is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-# CONFIG_VIRTIO_MENU is not set
-# CONFIG_VHOST_MENU is not set
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT4_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_PROC_CHILDREN=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_EFIVAR_FS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf"
-CONFIG_INIT_STACK_NONE=y
-# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
-CONFIG_CRYPTO_SHA256=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_READABLE_ASM=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_PAGEALLOC=y
-# CONFIG_SLUB_DEBUG is not set
-CONFIG_SCHED_STACK_END_CHECK=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_VM_PGFLAGS=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_SOFTLOCKUP_DETECTOR=y
-CONFIG_WQ_WATCHDOG=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_RWSEMS=y
-CONFIG_DEBUG_ATOMIC_SLEEP=y
-CONFIG_STACKTRACE=y
-CONFIG_DEBUG_LIST=y
-CONFIG_DEBUG_PLIST=y
-CONFIG_DEBUG_SG=y
-CONFIG_RCU_EQS_DEBUG=y
-# CONFIG_FTRACE is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=y
diff --git a/linux/br2-external-tree/board/wally/post_image.sh b/linux/br2-external-tree/board/wally/post_image.sh
deleted file mode 100755
index e3db7525b..000000000
--- a/linux/br2-external-tree/board/wally/post_image.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-
-# Copy linux and busybox binaries (with symbol info) to images directory
-cp "$BUILD_DIR"/linux-*/vmlinux "$BINARIES_DIR"/vmlinux
-cp "$BUILD_DIR"/busybox-*/busybox "$BINARIES_DIR"/busybox
diff --git a/linux/br2-external-tree/configs/wally_defconfig b/linux/br2-external-tree/configs/wally_defconfig
deleted file mode 100644
index bdae60a6f..000000000
--- a/linux/br2-external-tree/configs/wally_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-BR2_riscv=y
-BR2_RISCV_ISA_RVC=y
-BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_11=y
-BR2_BINUTILS_VERSION_2_43_X=y
-BR2_GCC_VERSION_14_X=y
-BR2_TOOLCHAIN_BUILDROOT_CXX=y
-BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
-BR2_BACKUP_SITE="http://sources.buildroot.net"
-BR2_GNU_MIRROR="http://ftpmirror.gnu.org"
-BR2_ENABLE_DEBUG=y
-BR2_DEBUG_3=y
-# BR2_STRIP_strip is not set
-BR2_PER_PACKAGE_DIRECTORIES=y
-# BR2_PIC_PIE is not set
-BR2_SSP_NONE=y
-BR2_RELRO_NONE=y
-BR2_FORTIFY_SOURCE_NONE=y
-BR2_TARGET_GENERIC_HOSTNAME="WallyHostname"
-BR2_TARGET_GENERIC_ISSUE="Greetings! This RISC-V Linux image was built for Wally on Buildroot!"
-BR2_ROOTFS_DEVICE_TABLE_SUPPORTS_EXTENDED_ATTRIBUTES=y
-BR2_SYSTEM_DHCP="eth0"
-BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_WALLY_PATH)/board/wally/rootfs_overlay"
-BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_WALLY_PATH)/board/wally/post_image.sh"
-BR2_LINUX_KERNEL=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.12.8"
-BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
-BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_WALLY_PATH)/board/wally/linux.config"
-BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_WALLY_PATH)/board/wally/busybox.config"
-BR2_PACKAGE_COREMARK=y
-BR2_PACKAGE_DHRYSTONE=y
-BR2_PACKAGE_RAMSPEED=y
-BR2_PACKAGE_WHETSTONE=y
-BR2_PACKAGE_SDL=y
-BR2_PACKAGE_ZSH=y
-# BR2_PACKAGE_UEMACS=y # temporarily disabled due to build issues with gcc 14
-BR2_TARGET_ROOTFS_INITRAMFS=y
-# BR2_TARGET_ROOTFS_TAR is not set
-BR2_TARGET_OPENSBI=y
-BR2_TARGET_OPENSBI_CUSTOM_VERSION=y
-BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.6"
-BR2_TARGET_OPENSBI_PLAT="generic"
-# BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG is not set
-BR2_PACKAGE_HOST_E2FSPROGS=y
-BR2_PACKAGE_HOST_QEMU=y
-BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y
diff --git a/linux/br2-external-tree/external.desc b/linux/br2-external-tree/external.desc
deleted file mode 100644
index f9a89b5c7..000000000
--- a/linux/br2-external-tree/external.desc
+++ /dev/null
@@ -1,2 +0,0 @@
-name: WALLY
-desc: Buildroot configuration for wally
diff --git a/linux/br2-external-tree/external.mk b/linux/br2-external-tree/external.mk
deleted file mode 100644
index 6e3475255..000000000
--- a/linux/br2-external-tree/external.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-# required for buildroot external tree
-# delibarately empty
diff --git a/linux/br2-external-tree/board/wally/busybox.config b/linux/buildroot-config-src/wally/busybox.config
similarity index 97%
rename from linux/br2-external-tree/board/wally/busybox.config
rename to linux/buildroot-config-src/wally/busybox.config
index 5d2d83a1d..48aa77ee6 100644
--- a/linux/br2-external-tree/board/wally/busybox.config
+++ b/linux/buildroot-config-src/wally/busybox.config
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Busybox version: 1.36.1
-# Fri Jan  3 15:38:08 2025
+# Busybox version: 1.33.1
+# Thu Jul 15 15:59:54 2021
 #
 CONFIG_HAVE_DOT_CONFIG=y
 
@@ -93,16 +93,10 @@ CONFIG_FEATURE_BUFFERS_USE_MALLOC=y
 # CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set
 CONFIG_PASSWORD_MINLEN=6
 CONFIG_MD5_SMALL=1
-CONFIG_SHA1_SMALL=3
-CONFIG_SHA1_HWACCEL=y
-CONFIG_SHA256_HWACCEL=y
 CONFIG_SHA3_SMALL=1
-# CONFIG_FEATURE_NON_POSIX_CP is not set
-CONFIG_FEATURE_VERBOSE_CP_MESSAGE=y
-# CONFIG_FEATURE_USE_SENDFILE is not set
-CONFIG_FEATURE_COPYBUF_KB=4
-# CONFIG_MONOTONIC_SYSCALL is not set
-# CONFIG_IOCTL_HEX2STR_ERROR is not set
+# CONFIG_FEATURE_FAST_TOP is not set
+# CONFIG_FEATURE_ETC_NETWORKS is not set
+# CONFIG_FEATURE_ETC_SERVICES is not set
 # CONFIG_FEATURE_EDITING is not set
 CONFIG_FEATURE_EDITING_MAX_LEN=0
 # CONFIG_FEATURE_EDITING_VI is not set
@@ -126,9 +120,14 @@ CONFIG_LAST_SUPPORTED_WCHAR=0
 # CONFIG_UNICODE_BIDI_SUPPORT is not set
 # CONFIG_UNICODE_NEUTRAL_TABLE is not set
 # CONFIG_UNICODE_PRESERVE_BROKEN is not set
-# CONFIG_LOOP_CONFIGURE is not set
-# CONFIG_NO_LOOP_CONFIGURE is not set
-CONFIG_TRY_LOOP_CONFIGURE=y
+# CONFIG_FEATURE_NON_POSIX_CP is not set
+CONFIG_FEATURE_VERBOSE_CP_MESSAGE=y
+# CONFIG_FEATURE_USE_SENDFILE is not set
+CONFIG_FEATURE_COPYBUF_KB=4
+CONFIG_FEATURE_SKIP_ROOTFS=y
+# CONFIG_MONOTONIC_SYSCALL is not set
+# CONFIG_IOCTL_HEX2STR_ERROR is not set
+# CONFIG_FEATURE_HWIB is not set
 
 #
 # Applets
@@ -163,8 +162,6 @@ CONFIG_BZIP2_SMALL=0
 CONFIG_CPIO=y
 # CONFIG_FEATURE_CPIO_O is not set
 # CONFIG_FEATURE_CPIO_P is not set
-# CONFIG_FEATURE_CPIO_IGNORE_DEVNO is not set
-# CONFIG_FEATURE_CPIO_RENUMBER_INODES is not set
 # CONFIG_DPKG is not set
 # CONFIG_DPKG_DEB is not set
 CONFIG_GZIP=y
@@ -200,22 +197,6 @@ CONFIG_FEATURE_UNZIP_CDF=y
 #
 # Coreutils
 #
-CONFIG_FEATURE_VERBOSE=y
-
-#
-# Common options for date and touch
-#
-# CONFIG_FEATURE_TIMEZONE is not set
-
-#
-# Common options for cp and mv
-#
-CONFIG_FEATURE_PRESERVE_HARDLINKS=y
-
-#
-# Common options for df, du, ls
-#
-CONFIG_FEATURE_HUMAN_READABLE=y
 CONFIG_BASENAME=y
 CONFIG_CAT=y
 CONFIG_FEATURE_CATN=y
@@ -226,13 +207,11 @@ CONFIG_CHOWN=y
 # CONFIG_FEATURE_CHOWN_LONG_OPTIONS is not set
 CONFIG_CHROOT=y
 CONFIG_CKSUM=y
-CONFIG_CRC32=y
 # CONFIG_COMM is not set
 CONFIG_CP=y
 # CONFIG_FEATURE_CP_LONG_OPTIONS is not set
 # CONFIG_FEATURE_CP_REFLINK is not set
 CONFIG_CUT=y
-CONFIG_FEATURE_CUT_REGEX=y
 CONFIG_DATE=y
 CONFIG_FEATURE_DATE_ISOFMT=y
 # CONFIG_FEATURE_DATE_NANO is not set
@@ -244,7 +223,6 @@ CONFIG_FEATURE_DD_IBS_OBS=y
 CONFIG_FEATURE_DD_STATUS=y
 CONFIG_DF=y
 # CONFIG_FEATURE_DF_FANCY is not set
-CONFIG_FEATURE_SKIP_ROOTFS=y
 CONFIG_DIRNAME=y
 # CONFIG_DOS2UNIX is not set
 # CONFIG_UNIX2DOS is not set
@@ -338,13 +316,13 @@ CONFIG_TEST2=y
 CONFIG_FEATURE_TEST_64=y
 # CONFIG_TIMEOUT is not set
 CONFIG_TOUCH=y
+# CONFIG_FEATURE_TOUCH_NODEREF is not set
 # CONFIG_FEATURE_TOUCH_SUSV3 is not set
 CONFIG_TR=y
 CONFIG_FEATURE_TR_CLASSES=y
 CONFIG_FEATURE_TR_EQUIV=y
 CONFIG_TRUE=y
 CONFIG_TRUNCATE=y
-CONFIG_TSORT=y
 CONFIG_TTY=y
 CONFIG_UNAME=y
 CONFIG_UNAME_OSNAME="GNU/Linux for Wally"
@@ -358,12 +336,27 @@ CONFIG_BASE64=y
 CONFIG_UUENCODE=y
 CONFIG_WC=y
 # CONFIG_FEATURE_WC_LARGE is not set
+CONFIG_WHOAMI=y
 # CONFIG_WHO is not set
 # CONFIG_W is not set
 # CONFIG_USERS is not set
-CONFIG_WHOAMI=y
 CONFIG_YES=y
 
+#
+# Common options
+#
+CONFIG_FEATURE_VERBOSE=y
+
+#
+# Common options for cp and mv
+#
+CONFIG_FEATURE_PRESERVE_HARDLINKS=y
+
+#
+# Common options for df, du, ls
+#
+CONFIG_FEATURE_HUMAN_READABLE=y
+
 #
 # Console Utilities
 #
@@ -427,7 +420,6 @@ CONFIG_VI=y
 CONFIG_FEATURE_VI_MAX_LEN=4096
 CONFIG_FEATURE_VI_8BIT=y
 CONFIG_FEATURE_VI_COLON=y
-CONFIG_FEATURE_VI_COLON_EXPAND=y
 CONFIG_FEATURE_VI_YANKMARK=y
 CONFIG_FEATURE_VI_SEARCH=y
 # CONFIG_FEATURE_VI_REGEX_SEARCH is not set
@@ -441,7 +433,6 @@ CONFIG_FEATURE_VI_ASK_TERMINAL=y
 CONFIG_FEATURE_VI_UNDO=y
 CONFIG_FEATURE_VI_UNDO_QUEUE=y
 CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=256
-CONFIG_FEATURE_VI_VERBOSE_STATUS=y
 # CONFIG_FEATURE_ALLOW_EXEC is not set
 
 #
@@ -450,11 +441,7 @@ CONFIG_FEATURE_VI_VERBOSE_STATUS=y
 CONFIG_FIND=y
 CONFIG_FEATURE_FIND_PRINT0=y
 CONFIG_FEATURE_FIND_MTIME=y
-CONFIG_FEATURE_FIND_ATIME=y
-CONFIG_FEATURE_FIND_CTIME=y
 CONFIG_FEATURE_FIND_MMIN=y
-CONFIG_FEATURE_FIND_AMIN=y
-CONFIG_FEATURE_FIND_CMIN=y
 CONFIG_FEATURE_FIND_PERM=y
 CONFIG_FEATURE_FIND_TYPE=y
 CONFIG_FEATURE_FIND_EXECUTABLE=y
@@ -462,7 +449,6 @@ CONFIG_FEATURE_FIND_XDEV=y
 CONFIG_FEATURE_FIND_MAXDEPTH=y
 CONFIG_FEATURE_FIND_NEWER=y
 # CONFIG_FEATURE_FIND_INUM is not set
-CONFIG_FEATURE_FIND_SAMEFILE=y
 CONFIG_FEATURE_FIND_EXEC=y
 CONFIG_FEATURE_FIND_EXEC_PLUS=y
 CONFIG_FEATURE_FIND_USER=y
@@ -524,10 +510,10 @@ CONFIG_FEATURE_SHADOWPASSWDS=y
 # CONFIG_USE_BB_SHADOW is not set
 CONFIG_USE_BB_CRYPT=y
 CONFIG_USE_BB_CRYPT_SHA=y
-# CONFIG_ADD_SHELL is not set
-# CONFIG_REMOVE_SHELL is not set
 CONFIG_ADDGROUP=y
 # CONFIG_FEATURE_ADDUSER_TO_GROUP is not set
+# CONFIG_ADD_SHELL is not set
+# CONFIG_REMOVE_SHELL is not set
 CONFIG_ADDUSER=y
 # CONFIG_FEATURE_CHECK_NAMES is not set
 CONFIG_LAST_ID=60000
@@ -753,7 +739,6 @@ CONFIG_FEATURE_VOLUMEID_FAT=y
 # Miscellaneous Utilities
 #
 # CONFIG_ADJTIMEX is not set
-CONFIG_ASCII=y
 # CONFIG_BBCONFIG is not set
 # CONFIG_FEATURE_COMPRESS_BBCONFIG is not set
 # CONFIG_BC is not set
@@ -787,10 +772,10 @@ CONFIG_CRONTAB=y
 # CONFIG_FEATURE_DEVFS is not set
 CONFIG_DEVMEM=y
 # CONFIG_FBSPLASH is not set
+# CONFIG_FLASHCP is not set
 # CONFIG_FLASH_ERASEALL is not set
 # CONFIG_FLASH_LOCK is not set
 # CONFIG_FLASH_UNLOCK is not set
-# CONFIG_FLASHCP is not set
 # CONFIG_HDPARM is not set
 # CONFIG_FEATURE_HDPARM_GET_IDENTITY is not set
 # CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set
@@ -834,24 +819,21 @@ CONFIG_PARTPROBE=y
 # CONFIG_RFKILL is not set
 # CONFIG_RUNLEVEL is not set
 # CONFIG_RX is not set
-CONFIG_SEEDRNG=y
 CONFIG_SETFATTR=y
 CONFIG_SETSERIAL=y
 CONFIG_STRINGS=y
 CONFIG_TIME=y
-CONFIG_TREE=y
 CONFIG_TS=y
 # CONFIG_TTYSIZE is not set
+CONFIG_UBIRENAME=y
 # CONFIG_UBIATTACH is not set
 # CONFIG_UBIDETACH is not set
 # CONFIG_UBIMKVOL is not set
 # CONFIG_UBIRMVOL is not set
 # CONFIG_UBIRSVOL is not set
 # CONFIG_UBIUPDATEVOL is not set
-CONFIG_UBIRENAME=y
 # CONFIG_VOLNAME is not set
 CONFIG_WATCHDOG=y
-# CONFIG_FEATURE_WATCHDOG_OPEN_TWICE is not set
 
 #
 # Networking Utilities
@@ -860,9 +842,6 @@ CONFIG_WATCHDOG=y
 # CONFIG_FEATURE_UNIX_LOCAL is not set
 # CONFIG_FEATURE_PREFER_IPV4_ADDRESS is not set
 # CONFIG_VERBOSE_RESOLUTION_ERRORS is not set
-# CONFIG_FEATURE_ETC_NETWORKS is not set
-# CONFIG_FEATURE_ETC_SERVICES is not set
-# CONFIG_FEATURE_HWIB is not set
 # CONFIG_FEATURE_TLS_SHA1 is not set
 # CONFIG_ARP is not set
 # CONFIG_ARPING is not set
@@ -881,7 +860,6 @@ CONFIG_WATCHDOG=y
 CONFIG_HOSTNAME=y
 # CONFIG_DNSDOMAINNAME is not set
 # CONFIG_HTTPD is not set
-CONFIG_FEATURE_HTTPD_PORT_DEFAULT=0
 # CONFIG_FEATURE_HTTPD_RANGES is not set
 # CONFIG_FEATURE_HTTPD_SETUID is not set
 # CONFIG_FEATURE_HTTPD_BASIC_AUTH is not set
@@ -974,7 +952,6 @@ CONFIG_FEATURE_IP_ROUTE_DIR=""
 # CONFIG_FEATURE_TELNET_WIDTH is not set
 # CONFIG_TELNETD is not set
 # CONFIG_FEATURE_TELNETD_STANDALONE is not set
-CONFIG_FEATURE_TELNETD_PORT_DEFAULT=0
 # CONFIG_FEATURE_TELNETD_INETD_WAIT is not set
 # CONFIG_TFTP is not set
 # CONFIG_FEATURE_TFTP_PROGRESS_BAR is not set
@@ -995,7 +972,6 @@ CONFIG_FEATURE_TELNETD_PORT_DEFAULT=0
 # CONFIG_WGET is not set
 # CONFIG_FEATURE_WGET_LONG_OPTIONS is not set
 # CONFIG_FEATURE_WGET_STATUSBAR is not set
-# CONFIG_FEATURE_WGET_FTP is not set
 # CONFIG_FEATURE_WGET_AUTHENTICATION is not set
 # CONFIG_FEATURE_WGET_TIMEOUT is not set
 # CONFIG_FEATURE_WGET_HTTPS is not set
@@ -1012,13 +988,11 @@ CONFIG_DHCPD_LEASES_FILE=""
 # CONFIG_FEATURE_UDHCPC_ARPING is not set
 # CONFIG_FEATURE_UDHCPC_SANITIZEOPT is not set
 CONFIG_UDHCPC_DEFAULT_SCRIPT=""
-CONFIG_UDHCPC6_DEFAULT_SCRIPT=""
 # CONFIG_UDHCPC6 is not set
 # CONFIG_FEATURE_UDHCPC6_RFC3646 is not set
 # CONFIG_FEATURE_UDHCPC6_RFC4704 is not set
 # CONFIG_FEATURE_UDHCPC6_RFC4833 is not set
 # CONFIG_FEATURE_UDHCPC6_RFC5970 is not set
-CONFIG_UDHCPC_DEFAULT_INTERFACE=""
 # CONFIG_FEATURE_UDHCP_PORT is not set
 CONFIG_UDHCP_DEBUG=0
 CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=0
@@ -1036,19 +1010,17 @@ CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS=""
 #
 # Mail Utilities
 #
-CONFIG_FEATURE_MIME_CHARSET=""
 # CONFIG_MAKEMIME is not set
 # CONFIG_POPMAILDIR is not set
 # CONFIG_FEATURE_POPMAILDIR_DELIVERY is not set
 # CONFIG_REFORMIME is not set
 # CONFIG_FEATURE_REFORMIME_COMPAT is not set
 # CONFIG_SENDMAIL is not set
+CONFIG_FEATURE_MIME_CHARSET=""
 
 #
 # Process Utilities
 #
-# CONFIG_FEATURE_FAST_TOP is not set
-# CONFIG_FEATURE_SHOW_THREADS is not set
 CONFIG_FREE=y
 CONFIG_FUSER=y
 # CONFIG_IOSTAT is not set
@@ -1087,6 +1059,7 @@ CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y
 CONFIG_UPTIME=y
 # CONFIG_FEATURE_UPTIME_UTMP_SUPPORT is not set
 CONFIG_WATCH=y
+# CONFIG_FEATURE_SHOW_THREADS is not set
 
 #
 # Runit Utilities
@@ -1143,7 +1116,6 @@ CONFIG_ASH_IDLE_TIMEOUT=y
 CONFIG_ASH_ECHO=y
 CONFIG_ASH_PRINTF=y
 CONFIG_ASH_TEST=y
-CONFIG_ASH_SLEEP=y
 CONFIG_ASH_HELP=y
 CONFIG_ASH_GETOPTS=y
 CONFIG_ASH_CMDCMD=y
@@ -1152,8 +1124,8 @@ CONFIG_ASH_CMDCMD=y
 # CONFIG_SHELL_HUSH is not set
 # CONFIG_HUSH_BASH_COMPAT is not set
 # CONFIG_HUSH_BRACE_EXPANSION is not set
-# CONFIG_HUSH_BASH_SOURCE_CURDIR is not set
 # CONFIG_HUSH_LINENO_VAR is not set
+# CONFIG_HUSH_BASH_SOURCE_CURDIR is not set
 # CONFIG_HUSH_INTERACTIVE is not set
 # CONFIG_HUSH_SAVEHISTORY is not set
 # CONFIG_HUSH_JOB is not set
diff --git a/linux/buildroot-config-src/wally/linux.config b/linux/buildroot-config-src/wally/linux.config
new file mode 100644
index 000000000..3c8503dd6
--- /dev/null
+++ b/linux/buildroot-config-src/wally/linux.config
@@ -0,0 +1,1312 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/riscv 5.10.7 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot -g8d5e37d-dirty) 10.3.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=100300
+CONFIG_LD_VERSION=235020000
+CONFIG_CLANG_VERSION=0
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_IRQ_WORK=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BUILD_SALT=""
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="WallyDefaultHostname"
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_USELIB is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+# end of Timers subsystem
+
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT_COUNT=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TINY_SRCU=y
+# end of RCU Subsystem
+
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+CONFIG_GENERIC_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# end of Scheduler features
+
+CONFIG_CC_HAS_INT128=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_RD_ZSTD is not set
+CONFIG_INITRAMFS_COMPRESSION_GZIP=y
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+# CONFIG_BOOT_CONFIG is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_EXPERT=y
+CONFIG_MULTIUSER=y
+# CONFIG_SGETMASK_SYSCALL is not set
+# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_HAVE_FUTEX_CMPXCHG=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_IO_URING=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_BASE_RELATIVE=y
+# CONFIG_BPF_SYSCALL is not set
+# CONFIG_USERFAULTFD is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# end of Kernel Performance Events And Counters
+
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_64BIT=y
+CONFIG_RISCV=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_RISCV_SBI=y
+CONFIG_MMU=y
+CONFIG_ZONE_DMA32=y
+CONFIG_VA_BITS=39
+CONFIG_PA_BITS=56
+CONFIG_PAGE_OFFSET=0xffffffff80000000
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_LOCKDEP_SUPPORT=y
+
+#
+# SoC selection
+#
+# CONFIG_SOC_SIFIVE is not set
+# CONFIG_SOC_VIRT is not set
+# end of SoC selection
+
+#
+# Platform type
+#
+# CONFIG_ARCH_RV32I is not set
+CONFIG_ARCH_RV64I=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_CMODEL_MEDANY=y
+CONFIG_MAXPHYSMEM_2GB=y
+# CONFIG_MAXPHYSMEM_128GB is not set
+# CONFIG_SMP is not set
+CONFIG_TUNE_GENERIC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_FPU=y
+# end of Platform type
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_RISCV_SBI_V01 is not set
+# end of Kernel features
+
+#
+# Boot options
+#
+CONFIG_CMDLINE=""
+# CONFIG_EFI is not set
+# end of Boot options
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+# end of Power management options
+
+#
+# Firmware Drivers
+#
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+#
+# General architecture-dependent options
+#
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP=y
+CONFIG_HAVE_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
+CONFIG_CLONE_BACKWARDS=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGINS is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+# CONFIG_BLOCK is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_HAS_MMIOWB=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_ARCH_HAS_BINFMT_FLAT=y
+# CONFIG_BINFMT_FLAT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_CMA is not set
+# CONFIG_ZPOOL is not set
+# CONFIG_ZBUD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_IDLE_PAGE_TRACKING is not set
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_BENCHMARK is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+# end of Memory Management options
+
+# CONFIG_NET is not set
+CONFIG_HAVE_EBPF_JIT=y
+
+#
+# Device Drivers
+#
+CONFIG_HAVE_PCI=y
+# CONFIG_PCI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# end of Firmware loader
+
+CONFIG_ALLOW_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_MHI_BUS is not set
+# end of Bus devices
+
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+# CONFIG_OF_UNITTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+# CONFIG_OF_OVERLAY is not set
+# CONFIG_PARPORT is not set
+
+#
+# NVME Support
+#
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_SRAM is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_PVPANIC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# end of EEPROM support
+
+#
+# Texas Instruments shared transport line discipline
+#
+# end of Texas Instruments shared transport line discipline
+
+#
+# Altera FPGA firmware download module (requires I2C)
+#
+# CONFIG_ECHO is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# end of SCSI device support
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LDISC_AUTOLOAD=y
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_16550A_VARIANTS=y
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_RT288X is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+CONFIG_SERIAL_MCTRL_GPIO=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NULL_TTY is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_SERIAL_DEV_BUS is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_BA431 is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+# CONFIG_HW_RANDOM_CCTRNG is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_XILLYBUS is not set
+# end of Character devices
+
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+# end of I2C support
+
+# CONFIG_I3C is not set
+# CONFIG_SPI is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# end of PTP clock support
+
+# CONFIG_PINCTRL is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_FASTPATH_LIMIT=32
+CONFIG_OF_GPIO=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_CDEV=y
+# CONFIG_GPIO_CDEV_V1 is not set
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers
+#
+# CONFIG_GPIO_74XX_MMIO is not set
+# CONFIG_GPIO_ALTERA is not set
+# CONFIG_GPIO_CADENCE is not set
+# CONFIG_GPIO_DWAPB is not set
+# CONFIG_GPIO_FTGPIO010 is not set
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_GRGPIO is not set
+# CONFIG_GPIO_HLWD is not set
+# CONFIG_GPIO_MB86S7X is not set
+CONFIG_GPIO_SIFIVE=y
+# CONFIG_GPIO_XILINX is not set
+# CONFIG_GPIO_AMD_FCH is not set
+# end of Memory mapped GPIO drivers
+
+#
+# MFD GPIO expanders
+#
+# end of MFD GPIO expanders
+
+# CONFIG_GPIO_AGGREGATOR is not set
+# CONFIG_GPIO_MOCKUP is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_ATMEL_FLEXCOM is not set
+# CONFIG_MFD_ATMEL_HLCDC is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_MFD_HI6421_PMIC is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_TQMX86 is not set
+# end of Multifunction device drivers
+
+# CONFIG_REGULATOR is not set
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+
+#
+# ARM devices
+#
+# end of ARM devices
+
+#
+# Frame buffer Devices
+#
+# CONFIG_FB is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# end of Backlight & LCD device support
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+# end of Console display driver support
+# end of Graphics support
+
+# CONFIG_SOUND is not set
+
+#
+# HID support
+#
+# CONFIG_HID is not set
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# DMABUF options
+#
+# CONFIG_SYNC_FILE is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_HEAPS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+CONFIG_VIRTIO=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VDPA is not set
+# CONFIG_VHOST_MENU is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_STAGING is not set
+# CONFIG_GOLDFISH is not set
+CONFIG_HAVE_CLK=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_FIXED_MMIO is not set
+# CONFIG_CLK_SIFIVE is not set
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_RISCV_TIMER=y
+# CONFIG_MICROCHIP_PIT64B is not set
+# end of Clock Source drivers
+
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Aspeed SoC drivers
+#
+# end of Aspeed SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# CONFIG_XILINX_VCU is not set
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_PWM is not set
+
+#
+# IRQ chip support
+#
+CONFIG_IRQCHIP=y
+# CONFIG_AL_FIC is not set
+CONFIG_RISCV_INTC=y
+CONFIG_SIFIVE_PLIC=y
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+
+#
+# PHY Subsystem
+#
+# CONFIG_GENERIC_PHY is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_PHY_CADENCE_TORRENT is not set
+# CONFIG_PHY_CADENCE_DPHY is not set
+# CONFIG_PHY_CADENCE_SALVO is not set
+# CONFIG_PHY_FSL_IMX8MQ_USB is not set
+# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+# CONFIG_RAS is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_DAX is not set
+# CONFIG_NVMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_FSI is not set
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTOFS_FS=y
+# CONFIG_FUSE_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_INODE64 is not set
+# CONFIG_HUGETLBFS is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+# end of Pseudo filesystems
+
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NLS is not set
+# CONFIG_UNICODE is not set
+CONFIG_IO_WQ=y
+# end of File systems
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Public-key cryptography
+#
+# CONFIG_CRYPTO_RSA is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+# CONFIG_CRYPTO_ESSIV is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CRC32 is not set
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_AES_TI is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+
+#
+# Crypto library routines
+#
+# CONFIG_CRYPTO_LIB_BLAKE2S is not set
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+# CONFIG_CRYPTO_LIB_CURVE25519 is not set
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+# CONFIG_CRYPTO_LIB_POLY1305 is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Certificates for signature checking
+#
+# end of Certificates for signature checking
+
+#
+# Library routines
+#
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+# CONFIG_CORDIC is not set
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+# CONFIG_CRC8 is not set
+# CONFIG_RANDOM32_SELFTEST is not set
+CONFIG_ZLIB_INFLATE=y
+# CONFIG_XZ_DEC is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_DMA_DECLARE_COHERENT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_IRQ_POLL is not set
+CONFIG_LIBFDT=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+# CONFIG_STRING_SELFTEST is not set
+# end of Library routines
+
+CONFIG_GENERIC_IOREMAP=y
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+# CONFIG_DEBUG_INFO_COMPRESSED is not set
+# CONFIG_DEBUG_INFO_SPLIT is not set
+# CONFIG_DEBUG_INFO_DWARF4 is not set
+# CONFIG_DEBUG_INFO_BTF is not set
+CONFIG_GDB_SCRIPTS=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_READABLE_ASM=y
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_SECTION_MISMATCH_WARN_ONLY=y
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y
+# CONFIG_KGDB is not set
+# CONFIG_UBSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MISC=y
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+CONFIG_DEBUG_PAGEALLOC=y
+# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_DEBUG_RODATA_TEST is not set
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_VM_VMACACHE is not set
+# CONFIG_DEBUG_VM_RB is not set
+CONFIG_DEBUG_VM_PGFLAGS=y
+CONFIG_DEBUG_VM_PGTABLE=y
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_WQ_WATCHDOG=y
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+CONFIG_DEBUG_TIMEKEEPING=y
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+CONFIG_DEBUG_RWSEMS=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+CONFIG_STACKTRACE=y
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_PLIST=y
+CONFIG_DEBUG_SG=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_EQS_DEBUG=y
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+
+#
+# riscv Debugging
+#
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_KCOV is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_MEMTEST=y
+# end of Kernel Testing and Coverage
+# end of Kernel hacking
diff --git a/linux/buildroot-config-src/wally/main.config b/linux/buildroot-config-src/wally/main.config
new file mode 100644
index 000000000..7e5f68df7
--- /dev/null
+++ b/linux/buildroot-config-src/wally/main.config
@@ -0,0 +1,3807 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Buildroot 2021.05 Configuration
+#
+BR2_HAVE_DOT_CONFIG=y
+BR2_HOST_GCC_AT_LEAST_4_9=y
+BR2_HOST_GCC_AT_LEAST_5=y
+BR2_HOST_GCC_AT_LEAST_6=y
+BR2_HOST_GCC_AT_LEAST_7=y
+BR2_HOST_GCC_AT_LEAST_8=y
+BR2_HOST_GCC_AT_LEAST_9=y
+
+#
+# Target options
+#
+BR2_ARCH_IS_64=y
+BR2_ARCH_HAS_MMU_MANDATORY=y
+# BR2_arcle is not set
+# BR2_arceb is not set
+# BR2_arm is not set
+# BR2_armeb is not set
+# BR2_aarch64 is not set
+# BR2_aarch64_be is not set
+# BR2_csky is not set
+# BR2_i386 is not set
+# BR2_m68k is not set
+# BR2_microblazeel is not set
+# BR2_microblazebe is not set
+# BR2_mips is not set
+# BR2_mipsel is not set
+# BR2_mips64 is not set
+# BR2_mips64el is not set
+# BR2_nds32 is not set
+# BR2_nios2 is not set
+# BR2_or1k is not set
+# BR2_powerpc is not set
+# BR2_powerpc64 is not set
+# BR2_powerpc64le is not set
+BR2_riscv=y
+# BR2_s390x is not set
+# BR2_sh is not set
+# BR2_sparc is not set
+# BR2_sparc64 is not set
+# BR2_x86_64 is not set
+# BR2_xtensa is not set
+BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT=y
+BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8=y
+BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9=y
+BR2_ARCH_NEEDS_GCC_AT_LEAST_5=y
+BR2_ARCH_NEEDS_GCC_AT_LEAST_6=y
+BR2_ARCH_NEEDS_GCC_AT_LEAST_7=y
+BR2_ARCH="riscv64"
+BR2_ENDIAN="LITTLE"
+BR2_GCC_TARGET_ABI="lp64d"
+BR2_BINFMT_SUPPORTS_SHARED=y
+BR2_READELF_ARCH_NAME="RISC-V"
+BR2_BINFMT_ELF=y
+BR2_RISCV_ISA_RVI=y
+BR2_RISCV_ISA_RVM=y
+BR2_RISCV_ISA_RVA=y
+BR2_RISCV_ISA_RVF=y
+BR2_RISCV_ISA_RVD=y
+BR2_riscv_g=y
+# BR2_riscv_custom is not set
+# BR2_RISCV_32 is not set
+BR2_RISCV_64=y
+# BR2_RISCV_ABI_LP64 is not set
+# BR2_RISCV_ABI_LP64F is not set
+BR2_RISCV_ABI_LP64D=y
+
+#
+# Build options
+#
+
+#
+# Commands
+#
+BR2_WGET="wget --passive-ftp -nd -t 3"
+BR2_SVN="svn --non-interactive"
+BR2_BZR="bzr"
+BR2_GIT="git"
+BR2_CVS="cvs"
+BR2_LOCALFILES="cp"
+BR2_SCP="scp"
+BR2_HG="hg"
+BR2_ZCAT="gzip -d -c"
+BR2_BZCAT="bzcat"
+BR2_XZCAT="xzcat"
+BR2_LZCAT="lzip -d -c"
+BR2_TAR_OPTIONS=""
+BR2_DEFCONFIG="./board/wally/main.config"
+BR2_DL_DIR="$(TOPDIR)/dl"
+BR2_HOST_DIR="$(BASE_DIR)/host"
+
+#
+# Mirrors and Download locations
+#
+BR2_PRIMARY_SITE=""
+BR2_BACKUP_SITE="http://sources.buildroot.net"
+BR2_KERNEL_MIRROR="https://cdn.kernel.org/pub"
+BR2_GNU_MIRROR="http://ftpmirror.gnu.org"
+BR2_LUAROCKS_MIRROR="http://rocks.moonscript.org"
+BR2_CPAN_MIRROR="http://cpan.metacpan.org"
+BR2_JLEVEL=0
+# BR2_CCACHE is not set
+BR2_ENABLE_DEBUG=y
+# BR2_DEBUG_1 is not set
+# BR2_DEBUG_2 is not set
+BR2_DEBUG_3=y
+# BR2_STRIP_strip is not set
+# BR2_OPTIMIZE_0 is not set
+# BR2_OPTIMIZE_1 is not set
+# BR2_OPTIMIZE_2 is not set
+# BR2_OPTIMIZE_3 is not set
+# BR2_OPTIMIZE_G is not set
+BR2_OPTIMIZE_S=y
+# BR2_OPTIMIZE_FAST is not set
+# BR2_STATIC_LIBS is not set
+BR2_SHARED_LIBS=y
+# BR2_SHARED_STATIC_LIBS is not set
+BR2_PACKAGE_OVERRIDE_FILE="$(CONFIG_DIR)/local.mk"
+BR2_GLOBAL_PATCH_DIR=""
+
+#
+# Advanced
+#
+BR2_COMPILER_PARANOID_UNSAFE_PATH=y
+# BR2_FORCE_HOST_BUILD is not set
+# BR2_REPRODUCIBLE is not set
+# BR2_PER_PACKAGE_DIRECTORIES is not set
+
+#
+# Security Hardening Options
+#
+# BR2_PIC_PIE is not set
+BR2_SSP_NONE=y
+# BR2_SSP_REGULAR is not set
+# BR2_SSP_STRONG is not set
+# BR2_SSP_ALL is not set
+BR2_RELRO_NONE=y
+# BR2_RELRO_PARTIAL is not set
+# BR2_RELRO_FULL is not set
+BR2_FORTIFY_SOURCE_NONE=y
+# BR2_FORTIFY_SOURCE_1 is not set
+# BR2_FORTIFY_SOURCE_2 is not set
+
+#
+# Toolchain
+#
+BR2_TOOLCHAIN=y
+BR2_TOOLCHAIN_USES_GLIBC=y
+BR2_TOOLCHAIN_BUILDROOT=y
+# BR2_TOOLCHAIN_EXTERNAL is not set
+
+#
+# Toolchain Buildroot Options
+#
+BR2_TOOLCHAIN_BUILDROOT_VENDOR="buildroot"
+# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set
+BR2_TOOLCHAIN_BUILDROOT_GLIBC=y
+# BR2_TOOLCHAIN_BUILDROOT_MUSL is not set
+BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc"
+
+#
+# Kernel Header Options
+#
+BR2_KERNEL_HEADERS_AS_KERNEL=y
+# BR2_KERNEL_HEADERS_4_19 is not set
+# BR2_KERNEL_HEADERS_5_4 is not set
+# BR2_KERNEL_HEADERS_5_10 is not set
+# BR2_KERNEL_HEADERS_5_11 is not set
+# BR2_KERNEL_HEADERS_5_12 is not set
+# BR2_KERNEL_HEADERS_VERSION is not set
+# BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set
+# BR2_KERNEL_HEADERS_CUSTOM_GIT is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_11 is not set
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_10=y
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_9 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_8 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_7 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_6 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_5 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_3 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_2 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_1 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_0 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_20 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_19 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_18 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_17 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_16 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_15 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_14 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_13 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_12 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_11 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_10 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_8 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_7 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_6 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_5 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_4 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_3 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_2 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_1 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_0 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_19 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_18 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_17 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_16 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_15 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_14 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_13 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_12 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_11 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_10 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_9 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_8 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_7 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_6 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_5 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_4 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_3 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_2 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_1 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_0 is not set
+# BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_REALLY_OLD is not set
+BR2_PACKAGE_LINUX_HEADERS=y
+
+#
+# Glibc Options
+#
+BR2_PACKAGE_GLIBC=y
+# BR2_PACKAGE_GLIBC_UTILS is not set
+
+#
+# Binutils Options
+#
+BR2_PACKAGE_HOST_BINUTILS_SUPPORTS_CFI=y
+# BR2_BINUTILS_VERSION_2_32_X is not set
+# BR2_BINUTILS_VERSION_2_34_X is not set
+BR2_BINUTILS_VERSION_2_35_X=y
+# BR2_BINUTILS_VERSION_2_36_X is not set
+BR2_BINUTILS_VERSION="2.35.2"
+BR2_BINUTILS_EXTRA_CONFIG_OPTIONS=""
+
+#
+# GCC Options
+#
+# BR2_GCC_VERSION_8_X is not set
+# BR2_GCC_VERSION_9_X is not set
+BR2_GCC_VERSION_10_X=y
+BR2_GCC_VERSION="10.3.0"
+BR2_EXTRA_GCC_CONFIG_OPTIONS=""
+# BR2_TOOLCHAIN_BUILDROOT_CXX is not set
+# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set
+# BR2_GCC_ENABLE_LTO is not set
+# BR2_GCC_ENABLE_OPENMP is not set
+# BR2_GCC_ENABLE_GRAPHITE is not set
+
+#
+# Toolchain Generic Options
+#
+BR2_TOOLCHAIN_SUPPORTS_ALWAYS_LOCKFREE_ATOMIC_INTS=y
+BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y
+BR2_USE_WCHAR=y
+BR2_ENABLE_LOCALE=y
+BR2_TOOLCHAIN_HAS_THREADS=y
+BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y
+BR2_TOOLCHAIN_HAS_THREADS_NPTL=y
+BR2_TOOLCHAIN_HAS_SSP=y
+BR2_TOOLCHAIN_HAS_SSP_STRONG=y
+BR2_TOOLCHAIN_HAS_UCONTEXT=y
+BR2_TOOLCHAIN_SUPPORTS_PIE=y
+# BR2_TOOLCHAIN_GLIBC_GCONV_LIBS_COPY is not set
+BR2_TOOLCHAIN_EXTRA_LIBS=""
+BR2_TOOLCHAIN_HAS_FULL_GETTEXT=y
+BR2_USE_MMU=y
+BR2_TARGET_OPTIMIZATION=""
+BR2_TARGET_LDFLAGS=""
+# BR2_ECLIPSE_REGISTER is not set
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_0=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_1=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_2=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_3=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_4=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_5=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_6=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_7=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_8=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_9=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_10=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_11=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_12=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_13=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_14=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_15=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_16=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_17=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_18=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_19=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_1=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_2=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_3=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_4=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_5=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_6=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_7=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_8=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_11=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_12=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_13=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_14=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_15=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_16=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_17=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_18=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_19=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_20=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_0=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_1=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_2=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_3=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_4=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_5=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_6=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_7=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_8=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_9=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_10=y
+BR2_TOOLCHAIN_HEADERS_AT_LEAST="5.10"
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_3=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_4=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_5=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_6=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_5=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_6=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_7=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_8=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_9=y
+BR2_TOOLCHAIN_GCC_AT_LEAST_10=y
+BR2_TOOLCHAIN_GCC_AT_LEAST="10"
+BR2_TOOLCHAIN_HAS_MNAN_OPTION=y
+BR2_TOOLCHAIN_HAS_SYNC_1=y
+BR2_TOOLCHAIN_HAS_SYNC_2=y
+BR2_TOOLCHAIN_HAS_SYNC_4=y
+BR2_TOOLCHAIN_HAS_SYNC_8=y
+BR2_TOOLCHAIN_HAS_LIBATOMIC=y
+BR2_TOOLCHAIN_HAS_ATOMIC=y
+
+#
+# System configuration
+#
+BR2_ROOTFS_SKELETON_DEFAULT=y
+# BR2_ROOTFS_SKELETON_CUSTOM is not set
+BR2_TARGET_GENERIC_HOSTNAME="WallyHostname"
+BR2_TARGET_GENERIC_ISSUE="Greetings! This RISC-V Linux image was built for Wally on Buildroot!"
+BR2_TARGET_GENERIC_PASSWD_SHA256=y
+# BR2_TARGET_GENERIC_PASSWD_SHA512 is not set
+BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256"
+BR2_INIT_BUSYBOX=y
+# BR2_INIT_SYSV is not set
+# BR2_INIT_OPENRC is not set
+# BR2_INIT_SYSTEMD is not set
+# BR2_INIT_NONE is not set
+# BR2_ROOTFS_DEVICE_CREATION_STATIC is not set
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y
+# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV is not set
+# BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV is not set
+BR2_ROOTFS_DEVICE_TABLE="system/device_table.txt"
+# BR2_ROOTFS_DEVICE_TABLE_SUPPORTS_EXTENDED_ATTRIBUTES is not set
+# BR2_ROOTFS_MERGED_USR is not set
+BR2_TARGET_ENABLE_ROOT_LOGIN=y
+BR2_TARGET_GENERIC_ROOT_PASSWD=""
+BR2_SYSTEM_BIN_SH_BUSYBOX=y
+
+#
+# bash, dash, mksh, zsh need BR2_PACKAGE_BUSYBOX_SHOW_OTHERS
+#
+# BR2_SYSTEM_BIN_SH_NONE is not set
+BR2_TARGET_GENERIC_GETTY=y
+BR2_TARGET_GENERIC_GETTY_PORT="console"
+BR2_TARGET_GENERIC_GETTY_BAUDRATE_KEEP=y
+# BR2_TARGET_GENERIC_GETTY_BAUDRATE_9600 is not set
+# BR2_TARGET_GENERIC_GETTY_BAUDRATE_19200 is not set
+# BR2_TARGET_GENERIC_GETTY_BAUDRATE_38400 is not set
+# BR2_TARGET_GENERIC_GETTY_BAUDRATE_57600 is not set
+# BR2_TARGET_GENERIC_GETTY_BAUDRATE_115200 is not set
+BR2_TARGET_GENERIC_GETTY_BAUDRATE="0"
+BR2_TARGET_GENERIC_GETTY_TERM="vt100"
+BR2_TARGET_GENERIC_GETTY_OPTIONS=""
+BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y
+BR2_SYSTEM_DHCP="eth0"
+BR2_SYSTEM_DEFAULT_PATH="/bin:/sbin:/usr/bin:/usr/sbin"
+BR2_ENABLE_LOCALE_PURGE=y
+BR2_ENABLE_LOCALE_WHITELIST="C en_US"
+BR2_GENERATE_LOCALE=""
+# BR2_SYSTEM_ENABLE_NLS is not set
+# BR2_TARGET_TZ_INFO is not set
+BR2_ROOTFS_USERS_TABLES=""
+BR2_ROOTFS_OVERLAY="./board/wally/rootfs_overlay"
+BR2_ROOTFS_POST_BUILD_SCRIPT=""
+BR2_ROOTFS_POST_FAKEROOT_SCRIPT=""
+BR2_ROOTFS_POST_IMAGE_SCRIPT=""
+
+#
+# Kernel
+#
+BR2_LINUX_KERNEL=y
+# BR2_LINUX_KERNEL_LATEST_VERSION is not set
+# BR2_LINUX_KERNEL_LATEST_CIP_VERSION is not set
+# BR2_LINUX_KERNEL_LATEST_CIP_RT_VERSION is not set
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+# BR2_LINUX_KERNEL_CUSTOM_TARBALL is not set
+# BR2_LINUX_KERNEL_CUSTOM_GIT is not set
+# BR2_LINUX_KERNEL_CUSTOM_HG is not set
+# BR2_LINUX_KERNEL_CUSTOM_SVN is not set
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.10.7"
+BR2_LINUX_KERNEL_VERSION="5.10.7"
+BR2_LINUX_KERNEL_PATCH=""
+# BR2_LINUX_KERNEL_USE_DEFCONFIG is not set
+# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="./board/wally/linux.config"
+BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES=""
+BR2_LINUX_KERNEL_CUSTOM_LOGO_PATH=""
+BR2_LINUX_KERNEL_IMAGE=y
+# BR2_LINUX_KERNEL_IMAGEGZ is not set
+# BR2_LINUX_KERNEL_VMLINUX is not set
+# BR2_LINUX_KERNEL_IMAGE_TARGET_CUSTOM is not set
+BR2_LINUX_KERNEL_GZIP=y
+# BR2_LINUX_KERNEL_LZ4 is not set
+# BR2_LINUX_KERNEL_LZMA is not set
+# BR2_LINUX_KERNEL_LZO is not set
+# BR2_LINUX_KERNEL_XZ is not set
+# BR2_LINUX_KERNEL_ZSTD is not set
+# BR2_LINUX_KERNEL_DTS_SUPPORT is not set
+# BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL is not set
+# BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF is not set
+
+#
+# Linux Kernel Extensions
+#
+# BR2_LINUX_KERNEL_EXT_RTAI is not set
+# BR2_LINUX_KERNEL_EXT_EV3DEV_LINUX_DRIVERS is not set
+# BR2_LINUX_KERNEL_EXT_FBTFT is not set
+# BR2_LINUX_KERNEL_EXT_AUFS is not set
+
+#
+# Linux Kernel Tools
+#
+# BR2_PACKAGE_LINUX_TOOLS_CPUPOWER is not set
+# BR2_PACKAGE_LINUX_TOOLS_GPIO is not set
+# BR2_PACKAGE_LINUX_TOOLS_IIO is not set
+# BR2_PACKAGE_LINUX_TOOLS_PCI is not set
+# BR2_PACKAGE_LINUX_TOOLS_PERF is not set
+
+#
+# selftests needs BR2_PACKAGE_BUSYBOX_SHOW_OTHERS and a toolchain w/ dynamic library
+#
+# BR2_PACKAGE_LINUX_TOOLS_TMON is not set
+
+#
+# Target packages
+#
+BR2_PACKAGE_BUSYBOX=y
+BR2_PACKAGE_BUSYBOX_CONFIG="./board/wally/busybox.config"
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES=""
+# BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set
+# BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set
+# BR2_PACKAGE_BUSYBOX_WATCHDOG is not set
+BR2_PACKAGE_SKELETON=y
+BR2_PACKAGE_HAS_SKELETON=y
+BR2_PACKAGE_PROVIDES_SKELETON="skeleton-init-sysv"
+BR2_PACKAGE_SKELETON_INIT_COMMON=y
+BR2_PACKAGE_SKELETON_INIT_SYSV=y
+
+#
+# Audio and video applications
+#
+# BR2_PACKAGE_ALSA_UTILS is not set
+# BR2_PACKAGE_ATEST is not set
+# BR2_PACKAGE_AUMIX is not set
+# BR2_PACKAGE_BLUEZ_ALSA is not set
+# BR2_PACKAGE_DVBLAST is not set
+# BR2_PACKAGE_DVDAUTHOR is not set
+
+#
+# dvdrw-tools needs a toolchain w/ threads, C++, wchar
+#
+
+#
+# espeak needs a toolchain w/ C++, wchar, threads, dynamic library
+#
+# BR2_PACKAGE_FAAD2 is not set
+BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y
+# BR2_PACKAGE_FFMPEG is not set
+# BR2_PACKAGE_FLAC is not set
+# BR2_PACKAGE_FLITE is not set
+# BR2_PACKAGE_FLUID_SOUNDFONT is not set
+# BR2_PACKAGE_FLUIDSYNTH is not set
+# BR2_PACKAGE_GMRENDER_RESURRECT is not set
+# BR2_PACKAGE_GSTREAMER1 is not set
+# BR2_PACKAGE_JACK1 is not set
+
+#
+# jack2 needs a toolchain w/ threads, C++, dynamic library
+#
+BR2_PACKAGE_KODI_ARCH_SUPPORTS=y
+
+#
+# kodi needs python3 w/ .py modules, a uClibc or glibc toolchain w/ C++, threads, wchar, dynamic library, gcc >= 4.9
+#
+
+#
+# kodi needs an OpenGL EGL backend with OpenGL or GLES support
+#
+# BR2_PACKAGE_LAME is not set
+# BR2_PACKAGE_MADPLAY is not set
+# BR2_PACKAGE_MIMIC is not set
+# BR2_PACKAGE_MINIMODEM is not set
+
+#
+# miraclecast needs systemd and a glibc toolchain w/ threads and wchar
+#
+
+#
+# mjpegtools needs a toolchain w/ C++, threads
+#
+
+#
+# modplugtools needs a toolchain w/ C++
+#
+# BR2_PACKAGE_MOTION is not set
+
+#
+# mpd needs a toolchain w/ C++, threads, wchar, gcc >= 7, host gcc >= 7
+#
+# BR2_PACKAGE_MPD_MPC is not set
+# BR2_PACKAGE_MPG123 is not set
+
+#
+# mpv needs a toolchain w/ C++, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_MULTICAT is not set
+# BR2_PACKAGE_MUSEPACK is not set
+
+#
+# ncmpc needs a toolchain w/ C++, wchar, threads, gcc >= 7
+#
+# BR2_PACKAGE_OPUS_TOOLS is not set
+BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y
+# BR2_PACKAGE_PULSEAUDIO is not set
+# BR2_PACKAGE_SOX is not set
+# BR2_PACKAGE_SQUEEZELITE is not set
+
+#
+# tovid needs a toolchain w/ threads, C++, wchar, gcc >= 4.9
+#
+# BR2_PACKAGE_TSTOOLS is not set
+# BR2_PACKAGE_TWOLAME is not set
+# BR2_PACKAGE_UDPXY is not set
+
+#
+# upmpdcli needs a toolchain w/ C++, NPTL, gcc >= 4.9
+#
+
+#
+# v4l2grab needs a toolchain w/ threads, dynamic library, C++ and headers >= 3.0
+#
+# BR2_PACKAGE_V4L2LOOPBACK is not set
+
+#
+# vlc needs a toolchain w/ C++, dynamic library, wchar, threads, gcc >= 4.9, headers >= 3.7
+#
+# BR2_PACKAGE_VORBIS_TOOLS is not set
+# BR2_PACKAGE_WAVPACK is not set
+# BR2_PACKAGE_YAVTA is not set
+# BR2_PACKAGE_YMPD is not set
+
+#
+# Compressors and decompressors
+#
+# BR2_PACKAGE_BROTLI is not set
+# BR2_PACKAGE_BZIP2 is not set
+
+#
+# lrzip needs a toolchain w/ wchar, threads, C++
+#
+
+#
+# lzip needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LZOP is not set
+
+#
+# p7zip needs a toolchain w/ threads, wchar, C++
+#
+# BR2_PACKAGE_PIGZ is not set
+# BR2_PACKAGE_PIXZ is not set
+
+#
+# unrar needs a toolchain w/ C++, wchar, threads
+#
+# BR2_PACKAGE_XZ is not set
+# BR2_PACKAGE_ZIP is not set
+# BR2_PACKAGE_ZSTD is not set
+
+#
+# Debugging, profiling and benchmark
+#
+# BR2_PACKAGE_BABELTRACE2 is not set
+# BR2_PACKAGE_BLKTRACE is not set
+
+#
+# bonnie++ needs a toolchain w/ C++
+#
+# BR2_PACKAGE_CACHE_CALIBRATOR is not set
+
+#
+# clinfo needs an OpenCL provider
+#
+# BR2_PACKAGE_COREMARK is not set
+# BR2_PACKAGE_COREMARK_PRO is not set
+
+#
+# dacapo needs OpenJDK
+#
+# BR2_PACKAGE_DHRYSTONE is not set
+# BR2_PACKAGE_DIEHARDER is not set
+# BR2_PACKAGE_DMALLOC is not set
+# BR2_PACKAGE_DROPWATCH is not set
+# BR2_PACKAGE_DSTAT is not set
+# BR2_PACKAGE_DT is not set
+
+#
+# duma needs a toolchain w/ C++, threads, dynamic library
+#
+# BR2_PACKAGE_FIO is not set
+BR2_PACKAGE_GDB_ARCH_SUPPORTS=y
+
+#
+# gdb/gdbserver >= 8.x needs a toolchain w/ C++, gcc >= 4.8
+#
+# BR2_PACKAGE_IOZONE is not set
+# BR2_PACKAGE_KTAP is not set
+# BR2_PACKAGE_LATENCYTOP is not set
+# BR2_PACKAGE_LMBENCH is not set
+BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y
+# BR2_PACKAGE_LTP_TESTSUITE is not set
+# BR2_PACKAGE_LTTNG_BABELTRACE is not set
+# BR2_PACKAGE_LTTNG_MODULES is not set
+# BR2_PACKAGE_LTTNG_TOOLS is not set
+# BR2_PACKAGE_MEMSTAT is not set
+# BR2_PACKAGE_NETPERF is not set
+# BR2_PACKAGE_NETSNIFF_NG is not set
+# BR2_PACKAGE_NMON is not set
+# BR2_PACKAGE_PAX_UTILS is not set
+# BR2_PACKAGE_PV is not set
+# BR2_PACKAGE_RAMSMP is not set
+# BR2_PACKAGE_RAMSPEED is not set
+# BR2_PACKAGE_RT_TESTS is not set
+# BR2_PACKAGE_SPIDEV_TEST is not set
+# BR2_PACKAGE_STRACE is not set
+# BR2_PACKAGE_STRESS is not set
+# BR2_PACKAGE_STRESS_NG is not set
+
+#
+# sysdig needs a glibc or uclibc toolchain w/ C++, threads, gcc >= 4.8, dynamic library, a Linux kernel, and luajit or lua 5.1 to be built
+#
+# BR2_PACKAGE_TINYMEMBENCH is not set
+# BR2_PACKAGE_TRACE_CMD is not set
+# BR2_PACKAGE_UCLIBC_NG_TEST is not set
+# BR2_PACKAGE_VMTOUCH is not set
+# BR2_PACKAGE_WHETSTONE is not set
+
+#
+# Development tools
+#
+# BR2_PACKAGE_BINUTILS is not set
+# BR2_PACKAGE_BITWISE is not set
+# BR2_PACKAGE_BSDIFF is not set
+# BR2_PACKAGE_CHECK is not set
+
+#
+# cppunit needs a toolchain w/ C++, dynamic library
+#
+# BR2_PACKAGE_CUKINIA is not set
+# BR2_PACKAGE_CUNIT is not set
+# BR2_PACKAGE_CVS is not set
+
+#
+# cxxtest needs a toolchain w/ C++ support
+#
+# BR2_PACKAGE_FLEX is not set
+# BR2_PACKAGE_GETTEXT is not set
+BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny"
+# BR2_PACKAGE_GIT is not set
+
+#
+# git-crypt needs a toolchain w/ C++, gcc >= 4.9
+#
+
+#
+# gperf needs a toolchain w/ C++
+#
+# BR2_PACKAGE_JO is not set
+# BR2_PACKAGE_JQ is not set
+# BR2_PACKAGE_LIBTOOL is not set
+# BR2_PACKAGE_MAKE is not set
+# BR2_PACKAGE_MAWK is not set
+# BR2_PACKAGE_PKGCONF is not set
+# BR2_PACKAGE_SUBVERSION is not set
+# BR2_PACKAGE_TREE is not set
+
+#
+# Filesystem and flash utilities
+#
+# BR2_PACKAGE_ABOOTIMG is not set
+# BR2_PACKAGE_AUFS_UTIL is not set
+# BR2_PACKAGE_AUTOFS is not set
+# BR2_PACKAGE_BTRFS_PROGS is not set
+# BR2_PACKAGE_CIFS_UTILS is not set
+# BR2_PACKAGE_CPIO is not set
+# BR2_PACKAGE_CRAMFS is not set
+# BR2_PACKAGE_CURLFTPFS is not set
+# BR2_PACKAGE_DAVFS2 is not set
+# BR2_PACKAGE_DOSFSTOOLS is not set
+# BR2_PACKAGE_E2FSPROGS is not set
+# BR2_PACKAGE_E2TOOLS is not set
+# BR2_PACKAGE_ECRYPTFS_UTILS is not set
+# BR2_PACKAGE_EROFS_UTILS is not set
+# BR2_PACKAGE_EXFAT is not set
+# BR2_PACKAGE_EXFAT_UTILS is not set
+# BR2_PACKAGE_EXFATPROGS is not set
+# BR2_PACKAGE_F2FS_TOOLS is not set
+# BR2_PACKAGE_FLASHBENCH is not set
+# BR2_PACKAGE_FSCRYPTCTL is not set
+# BR2_PACKAGE_FUSE_OVERLAYFS is not set
+# BR2_PACKAGE_FWUP is not set
+# BR2_PACKAGE_GENEXT2FS is not set
+# BR2_PACKAGE_GENPART is not set
+# BR2_PACKAGE_GENROMFS is not set
+# BR2_PACKAGE_IMX_USB_LOADER is not set
+# BR2_PACKAGE_MMC_UTILS is not set
+# BR2_PACKAGE_MTD is not set
+# BR2_PACKAGE_MTOOLS is not set
+# BR2_PACKAGE_NFS_UTILS is not set
+# BR2_PACKAGE_NILFS_UTILS is not set
+# BR2_PACKAGE_NTFS_3G is not set
+# BR2_PACKAGE_SP_OOPS_EXTRACT is not set
+# BR2_PACKAGE_SQUASHFS is not set
+# BR2_PACKAGE_SSHFS is not set
+# BR2_PACKAGE_UDFTOOLS is not set
+# BR2_PACKAGE_UNIONFS is not set
+# BR2_PACKAGE_XFSPROGS is not set
+
+#
+# zfs needs udev /dev management
+#
+
+#
+# Fonts, cursors, icons, sounds and themes
+#
+
+#
+# Cursors
+#
+# BR2_PACKAGE_COMIX_CURSORS is not set
+# BR2_PACKAGE_OBSIDIAN_CURSORS is not set
+
+#
+# Fonts
+#
+# BR2_PACKAGE_BITSTREAM_VERA is not set
+# BR2_PACKAGE_CANTARELL is not set
+# BR2_PACKAGE_DEJAVU is not set
+# BR2_PACKAGE_FONT_AWESOME is not set
+# BR2_PACKAGE_GHOSTSCRIPT_FONTS is not set
+# BR2_PACKAGE_INCONSOLATA is not set
+# BR2_PACKAGE_LIBERATION is not set
+# BR2_PACKAGE_WQY_ZENHEI is not set
+
+#
+# Icons
+#
+# BR2_PACKAGE_GOOGLE_MATERIAL_DESIGN_ICONS is not set
+# BR2_PACKAGE_HICOLOR_ICON_THEME is not set
+
+#
+# Sounds
+#
+# BR2_PACKAGE_SOUND_THEME_BOREALIS is not set
+# BR2_PACKAGE_SOUND_THEME_FREEDESKTOP is not set
+
+#
+# Themes
+#
+
+#
+# Games
+#
+# BR2_PACKAGE_ASCII_INVADERS is not set
+# BR2_PACKAGE_CHOCOLATE_DOOM is not set
+
+#
+# flare-engine needs a toolchain w/ C++, dynamic library
+#
+# BR2_PACKAGE_FROTZ is not set
+
+#
+# gnuchess needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LBREAKOUT2 is not set
+# BR2_PACKAGE_LTRIS is not set
+# BR2_PACKAGE_OPENTYRIAN is not set
+# BR2_PACKAGE_PRBOOM is not set
+# BR2_PACKAGE_SL is not set
+
+#
+# solarus needs OpenGL and a toolchain w/ C++, gcc >= 4.9, NPTL, dynamic library, and luajit or lua 5.1
+#
+
+#
+# stella needs a toolchain w/ dynamic library, C++, threads, gcc >= 6
+#
+# BR2_PACKAGE_XORCURSES is not set
+
+#
+# Graphic libraries and applications (graphic/text)
+#
+
+#
+# Graphic applications
+#
+
+#
+# cage needs udev, EGL w/ Wayland backend and OpenGL ES support
+#
+
+#
+# cog needs wpewebkit and a toolchain w/ threads
+#
+# BR2_PACKAGE_FSWEBCAM is not set
+# BR2_PACKAGE_GHOSTSCRIPT is not set
+
+#
+# glmark2 needs a toolchain w/ C++, gcc >= 4.9
+#
+
+#
+# glslsandbox-player needs a toolchain w/ threads and an openGL ES and EGL driver
+#
+# BR2_PACKAGE_GNUPLOT is not set
+# BR2_PACKAGE_JHEAD is not set
+
+#
+# libva-utils needs a toolchain w/ C++, threads, dynamic library
+#
+BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y
+# BR2_PACKAGE_NETSURF is not set
+# BR2_PACKAGE_PNGQUANT is not set
+# BR2_PACKAGE_RRDTOOL is not set
+
+#
+# stellarium needs Qt5 and an OpenGL provider
+#
+
+#
+# tesseract-ocr needs a toolchain w/ threads, C++, gcc >= 4.8, dynamic library, wchar
+#
+
+#
+# Graphic libraries
+#
+
+#
+# cegui needs a toolchain w/ C++, threads, dynamic library, wchar
+#
+
+#
+# directfb needs a glibc or uClibc toolchain w/ C++, NPTL, gcc >= 4.5, dynamic library
+#
+
+#
+# efl needs a toolchain w/ C++, dynamic library, gcc >= 4.9, host gcc >= 4.9, threads, wchar
+#
+# BR2_PACKAGE_FB_TEST_APP is not set
+# BR2_PACKAGE_FBDUMP is not set
+# BR2_PACKAGE_FBGRAB is not set
+
+#
+# fbterm needs a toolchain w/ C++, wchar, locale
+#
+# BR2_PACKAGE_FBV is not set
+
+#
+# freerdp needs a toolchain w/ wchar, dynamic library, threads, C++
+#
+# BR2_PACKAGE_GRAPHICSMAGICK is not set
+# BR2_PACKAGE_IMAGEMAGICK is not set
+# BR2_PACKAGE_LINUX_FUSION is not set
+
+#
+# mesa3d needs a toolchain w/ C++, NPTL, dynamic library
+#
+
+#
+# ocrad needs a toolchain w/ C++
+#
+
+#
+# ogre needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads, wchar
+#
+# BR2_PACKAGE_PSPLASH is not set
+# BR2_PACKAGE_SDL is not set
+# BR2_PACKAGE_SDL2 is not set
+
+#
+# Other GUIs
+#
+
+#
+# Qt5 needs host g++ >= 5.0, and a toolchain w/ gcc >= 5.0, wchar, NPTL, C++, dynamic library
+#
+
+#
+# tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library
+#
+
+#
+# weston needs udev and a toolchain w/ locale, threads, dynamic library, headers >= 3.0
+#
+# BR2_PACKAGE_XORG7 is not set
+
+#
+# apitrace needs a toolchain w/ C++, wchar, dynamic library, threads, gcc >= 4.9
+#
+
+#
+# vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8
+#
+
+#
+# vte needs an OpenGL or an OpenGL-EGL/wayland backend
+#
+# BR2_PACKAGE_XKEYBOARD_CONFIG is not set
+
+#
+# Hardware handling
+#
+
+#
+# Firmware
+#
+# BR2_PACKAGE_ARMBIAN_FIRMWARE is not set
+# BR2_PACKAGE_B43_FIRMWARE is not set
+# BR2_PACKAGE_LINUX_FIRMWARE is not set
+# BR2_PACKAGE_MURATA_CYW_FW is not set
+# BR2_PACKAGE_ODROIDC2_FIRMWARE is not set
+# BR2_PACKAGE_QCOM_DB410C_FIRMWARE is not set
+# BR2_PACKAGE_RCW_SMARC_SAL28 is not set
+# BR2_PACKAGE_UX500_FIRMWARE is not set
+# BR2_PACKAGE_WILC1000_FIRMWARE is not set
+# BR2_PACKAGE_WILINK_BT_FIRMWARE is not set
+# BR2_PACKAGE_ZD1211_FIRMWARE is not set
+# BR2_PACKAGE_18XX_TI_UTILS is not set
+# BR2_PACKAGE_ACPICA is not set
+# BR2_PACKAGE_ACPID is not set
+
+#
+# acpitool needs a toolchain w/ threads, C++, dynamic library
+#
+# BR2_PACKAGE_AER_INJECT is not set
+# BR2_PACKAGE_ALTERA_STAPL is not set
+
+#
+# apcupsd needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_AVRDUDE is not set
+
+#
+# bcache-tools needs udev /dev management
+#
+
+#
+# brickd needs udev /dev management, a toolchain w/ threads, wchar
+#
+# BR2_PACKAGE_BRLTTY is not set
+
+#
+# cc-tool needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 
+#
+# BR2_PACKAGE_CDRKIT is not set
+# BR2_PACKAGE_CRYPTSETUP is not set
+# BR2_PACKAGE_CWIID is not set
+# BR2_PACKAGE_DAHDI_LINUX is not set
+# BR2_PACKAGE_DAHDI_TOOLS is not set
+# BR2_PACKAGE_DBUS is not set
+# BR2_PACKAGE_DFU_UTIL is not set
+# BR2_PACKAGE_DMRAID is not set
+
+#
+# dt-utils needs udev /dev management
+#
+# BR2_PACKAGE_DTV_SCAN_TABLES is not set
+# BR2_PACKAGE_DUMP1090 is not set
+# BR2_PACKAGE_DVB_APPS is not set
+# BR2_PACKAGE_DVBSNOOP is not set
+
+#
+# eudev needs eudev /dev management
+#
+# BR2_PACKAGE_EVEMU is not set
+# BR2_PACKAGE_EVTEST is not set
+# BR2_PACKAGE_FAN_CTRL is not set
+# BR2_PACKAGE_FCONFIG is not set
+BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y
+# BR2_PACKAGE_FLASHROM is not set
+# BR2_PACKAGE_FMTOOLS is not set
+# BR2_PACKAGE_FXLOAD is not set
+# BR2_PACKAGE_GPM is not set
+# BR2_PACKAGE_GPSD is not set
+
+#
+# gptfdisk needs a toolchain w/ C++
+#
+# BR2_PACKAGE_GVFS is not set
+# BR2_PACKAGE_HWDATA is not set
+# BR2_PACKAGE_HWLOC is not set
+# BR2_PACKAGE_INPUT_EVENT_DAEMON is not set
+# BR2_PACKAGE_IPMITOOL is not set
+# BR2_PACKAGE_IRDA_UTILS is not set
+# BR2_PACKAGE_KBD is not set
+# BR2_PACKAGE_LCDPROC is not set
+
+#
+# libiec61850 needs a toolchain w/ C++, threads, dynamic library
+#
+# BR2_PACKAGE_LIBUBOOTENV is not set
+# BR2_PACKAGE_LIBUIO is not set
+# BR2_PACKAGE_LINUX_BACKPORTS is not set
+# BR2_PACKAGE_LINUX_SERIAL_TEST is not set
+# BR2_PACKAGE_LINUXCONSOLETOOLS is not set
+
+#
+# lirc-tools needs a toolchain w/ threads, dynamic library, C++
+#
+# BR2_PACKAGE_LM_SENSORS is not set
+
+#
+# lshw needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_LSSCSI is not set
+# BR2_PACKAGE_LSUIO is not set
+# BR2_PACKAGE_LUKSMETA is not set
+# BR2_PACKAGE_LVM2 is not set
+# BR2_PACKAGE_MBPFAN is not set
+# BR2_PACKAGE_MDADM is not set
+# BR2_PACKAGE_MDEVD is not set
+# BR2_PACKAGE_MEMTESTER is not set
+# BR2_PACKAGE_MEMTOOL is not set
+# BR2_PACKAGE_MINICOM is not set
+# BR2_PACKAGE_NANOCOM is not set
+# BR2_PACKAGE_NEARD is not set
+# BR2_PACKAGE_NVIDIA_MODPROBE is not set
+# BR2_PACKAGE_NVME is not set
+# BR2_PACKAGE_OFONO is not set
+# BR2_PACKAGE_OPEN2300 is not set
+
+#
+# openfpgaloader needs a toolchain w/ threads, C++, gcc >= 4.9
+#
+# BR2_PACKAGE_OPENIPMI is not set
+# BR2_PACKAGE_OPENOCD is not set
+# BR2_PACKAGE_PARTED is not set
+# BR2_PACKAGE_PCIUTILS is not set
+# BR2_PACKAGE_PDBG is not set
+# BR2_PACKAGE_PICOCOM is not set
+
+#
+# powertop needs a toolchain w/ C++, threads, wchar
+#
+# BR2_PACKAGE_PPS_TOOLS is not set
+# BR2_PACKAGE_RASPI_GPIO is not set
+# BR2_PACKAGE_READ_EDID is not set
+# BR2_PACKAGE_RNG_TOOLS is not set
+# BR2_PACKAGE_RS485CONF is not set
+# BR2_PACKAGE_RTC_TOOLS is not set
+# BR2_PACKAGE_RTL8188EU is not set
+# BR2_PACKAGE_RTL8189FS is not set
+# BR2_PACKAGE_RTL8723BS is not set
+# BR2_PACKAGE_RTL8723BU is not set
+# BR2_PACKAGE_RTL8821AU is not set
+# BR2_PACKAGE_SANE_BACKENDS is not set
+# BR2_PACKAGE_SDPARM is not set
+# BR2_PACKAGE_SETSERIAL is not set
+# BR2_PACKAGE_SG3_UTILS is not set
+# BR2_PACKAGE_SIGROK_CLI is not set
+# BR2_PACKAGE_SISPMCTL is not set
+
+#
+# smartmontools needs a toolchain w/ C++
+#
+# BR2_PACKAGE_SMSTOOLS3 is not set
+# BR2_PACKAGE_SPI_TOOLS is not set
+# BR2_PACKAGE_SREDIRD is not set
+# BR2_PACKAGE_STATSERIAL is not set
+# BR2_PACKAGE_STM32FLASH is not set
+# BR2_PACKAGE_SYSSTAT is not set
+
+#
+# targetcli-fb depends on Python
+#
+
+#
+# ti-sgx-um needs the ti-sgx-km driver
+#
+
+#
+# ti-sgx-um needs udev and a glibc toolchain w/ threads
+#
+# BR2_PACKAGE_TI_UIM is not set
+# BR2_PACKAGE_TI_UTILS is not set
+# BR2_PACKAGE_TIO is not set
+# BR2_PACKAGE_TRIGGERHAPPY is not set
+# BR2_PACKAGE_UBOOT_TOOLS is not set
+# BR2_PACKAGE_UBUS is not set
+# BR2_PACKAGE_UCCP420WLAN is not set
+
+#
+# udisks needs udev /dev management
+#
+
+#
+# udisks needs a glibc or musl toolchain with locale, C++, wchar, dynamic library, NPTL, gcc >= 4.9
+#
+# BR2_PACKAGE_UHUBCTL is not set
+# BR2_PACKAGE_UMTPRD is not set
+
+#
+# upower needs udev /dev management
+#
+# BR2_PACKAGE_USB_MODESWITCH is not set
+# BR2_PACKAGE_USB_MODESWITCH_DATA is not set
+
+#
+# usbmount requires udev to be enabled
+#
+
+#
+# usbutils needs udev /dev management and toolchain w/ threads, gcc >= 4.9
+#
+# BR2_PACKAGE_W_SCAN is not set
+# BR2_PACKAGE_WIPE is not set
+# BR2_PACKAGE_XORRISO is not set
+# BR2_PACKAGE_XR819_XRADIO is not set
+
+#
+# Interpreter languages and scripting
+#
+# BR2_PACKAGE_4TH is not set
+# BR2_PACKAGE_ENSCRIPT is not set
+BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y
+# BR2_PACKAGE_EXECLINE is not set
+# BR2_PACKAGE_FICL is not set
+# BR2_PACKAGE_HASERL is not set
+# BR2_PACKAGE_JANET is not set
+# BR2_PACKAGE_JIMTCL is not set
+# BR2_PACKAGE_LUA is not set
+BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua"
+# BR2_PACKAGE_MICROPYTHON is not set
+BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y
+# BR2_PACKAGE_PERL is not set
+# BR2_PACKAGE_PHP is not set
+# BR2_PACKAGE_PYTHON is not set
+# BR2_PACKAGE_PYTHON3 is not set
+# BR2_PACKAGE_QUICKJS is not set
+# BR2_PACKAGE_RUBY is not set
+# BR2_PACKAGE_TCL is not set
+
+#
+# Libraries
+#
+
+#
+# Audio/Sound
+#
+# BR2_PACKAGE_ALSA_LIB is not set
+
+#
+# alure needs a toolchain w/ C++, gcc >= 4.9, NPTL, wchar
+#
+# BR2_PACKAGE_AUBIO is not set
+# BR2_PACKAGE_BCG729 is not set
+
+#
+# caps needs a toolchain w/ C++, dynamic library
+#
+# BR2_PACKAGE_LIBAO is not set
+
+#
+# asplib needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBBROADVOICE is not set
+# BR2_PACKAGE_LIBCDAUDIO is not set
+# BR2_PACKAGE_LIBCDDB is not set
+# BR2_PACKAGE_LIBCDIO is not set
+# BR2_PACKAGE_LIBCDIO_PARANOIA is not set
+# BR2_PACKAGE_LIBCODEC2 is not set
+# BR2_PACKAGE_LIBCUE is not set
+# BR2_PACKAGE_LIBCUEFILE is not set
+# BR2_PACKAGE_LIBEBUR128 is not set
+# BR2_PACKAGE_LIBG7221 is not set
+# BR2_PACKAGE_LIBGSM is not set
+# BR2_PACKAGE_LIBID3TAG is not set
+# BR2_PACKAGE_LIBILBC is not set
+# BR2_PACKAGE_LIBLO is not set
+# BR2_PACKAGE_LIBMAD is not set
+
+#
+# libmodplug needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBMPD is not set
+# BR2_PACKAGE_LIBMPDCLIENT is not set
+# BR2_PACKAGE_LIBREPLAYGAIN is not set
+# BR2_PACKAGE_LIBSAMPLERATE is not set
+
+#
+# libsidplay2 needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBSILK is not set
+# BR2_PACKAGE_LIBSNDFILE is not set
+
+#
+# libsoundtouch needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBSOXR is not set
+# BR2_PACKAGE_LIBVORBIS is not set
+
+#
+# mp4v2 needs a toolchain w/ C++
+#
+BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y
+
+#
+# openal needs a toolchain w/ NPTL, C++, gcc >= 4.9
+#
+
+#
+# opencore-amr needs a toolchain w/ C++
+#
+# BR2_PACKAGE_OPUS is not set
+# BR2_PACKAGE_OPUSFILE is not set
+# BR2_PACKAGE_PORTAUDIO is not set
+# BR2_PACKAGE_SBC is not set
+# BR2_PACKAGE_SPANDSP is not set
+# BR2_PACKAGE_SPEEX is not set
+# BR2_PACKAGE_SPEEXDSP is not set
+
+#
+# taglib needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_TINYALSA is not set
+# BR2_PACKAGE_TREMOR is not set
+# BR2_PACKAGE_VO_AACENC is not set
+
+#
+# Compression and decompression
+#
+# BR2_PACKAGE_LIBARCHIVE is not set
+# BR2_PACKAGE_LIBMSPACK is not set
+
+#
+# libsquish needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBZIP is not set
+# BR2_PACKAGE_LZ4 is not set
+# BR2_PACKAGE_LZO is not set
+# BR2_PACKAGE_MINIZIP is not set
+
+#
+# snappy needs a toolchain w/ C++
+#
+# BR2_PACKAGE_SZIP is not set
+# BR2_PACKAGE_ZLIB is not set
+BR2_PACKAGE_PROVIDES_HOST_ZLIB="host-libzlib"
+# BR2_PACKAGE_ZZIPLIB is not set
+
+#
+# Crypto
+#
+# BR2_PACKAGE_BEARSSL is not set
+# BR2_PACKAGE_BEECRYPT is not set
+BR2_PACKAGE_BOTAN_ARCH_SUPPORTS=y
+
+#
+# botan needs a toolchain w/ C++, threads, gcc >= 4.8
+#
+# BR2_PACKAGE_CA_CERTIFICATES is not set
+# BR2_PACKAGE_CRYPTODEV is not set
+# BR2_PACKAGE_GCR is not set
+# BR2_PACKAGE_GNUTLS is not set
+# BR2_PACKAGE_LIBARGON2 is not set
+# BR2_PACKAGE_LIBASSUAN is not set
+# BR2_PACKAGE_LIBGCRYPT is not set
+BR2_PACKAGE_LIBGPG_ERROR_ARCH_SUPPORTS=y
+# BR2_PACKAGE_LIBGPG_ERROR is not set
+BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="riscv64-unknown-linux-gnu"
+# BR2_PACKAGE_LIBGPGME is not set
+# BR2_PACKAGE_LIBKCAPI is not set
+# BR2_PACKAGE_LIBKSBA is not set
+# BR2_PACKAGE_LIBMCRYPT is not set
+# BR2_PACKAGE_LIBMHASH is not set
+# BR2_PACKAGE_LIBNSS is not set
+
+#
+# libolm needs a toolchain w/ C++, gcc >= 4.8
+#
+# BR2_PACKAGE_LIBP11 is not set
+# BR2_PACKAGE_LIBSCRYPT is not set
+# BR2_PACKAGE_LIBSECRET is not set
+# BR2_PACKAGE_LIBSHA1 is not set
+# BR2_PACKAGE_LIBSODIUM is not set
+# BR2_PACKAGE_LIBSSH is not set
+# BR2_PACKAGE_LIBSSH2 is not set
+# BR2_PACKAGE_LIBTOMCRYPT is not set
+# BR2_PACKAGE_LIBUECC is not set
+# BR2_PACKAGE_LIBXCRYPT is not set
+# BR2_PACKAGE_MBEDTLS is not set
+# BR2_PACKAGE_NETTLE is not set
+# BR2_PACKAGE_OPENSSL is not set
+BR2_PACKAGE_PROVIDES_HOST_OPENSSL="host-libopenssl"
+# BR2_PACKAGE_PKCS11_HELPER is not set
+# BR2_PACKAGE_RHASH is not set
+# BR2_PACKAGE_TINYDTLS is not set
+# BR2_PACKAGE_TPM2_PKCS11 is not set
+# BR2_PACKAGE_TPM2_TSS is not set
+# BR2_PACKAGE_TROUSERS is not set
+# BR2_PACKAGE_USTREAM_SSL is not set
+# BR2_PACKAGE_WOLFSSL is not set
+
+#
+# Database
+#
+# BR2_PACKAGE_BERKELEYDB is not set
+# BR2_PACKAGE_GDBM is not set
+# BR2_PACKAGE_HIREDIS is not set
+
+#
+# kompexsqlite needs a toolchain w/ C++, wchar, threads, dynamic library
+#
+
+#
+# leveldb needs a toolchain w/ C++, threads, gcc >= 4.8
+#
+# BR2_PACKAGE_LIBGIT2 is not set
+# BR2_PACKAGE_LIBMDBX is not set
+
+#
+# libodb needs a toolchain w/ C++, threads
+#
+
+#
+# mysql needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_POSTGRESQL is not set
+# BR2_PACKAGE_REDIS is not set
+# BR2_PACKAGE_SQLCIPHER is not set
+# BR2_PACKAGE_SQLITE is not set
+# BR2_PACKAGE_UNIXODBC is not set
+
+#
+# Filesystem
+#
+# BR2_PACKAGE_GAMIN is not set
+# BR2_PACKAGE_LIBCONFIG is not set
+# BR2_PACKAGE_LIBCONFUSE is not set
+# BR2_PACKAGE_LIBFUSE is not set
+# BR2_PACKAGE_LIBFUSE3 is not set
+# BR2_PACKAGE_LIBLOCKFILE is not set
+# BR2_PACKAGE_LIBNFS is not set
+# BR2_PACKAGE_LIBSYSFS is not set
+# BR2_PACKAGE_LOCKDEV is not set
+
+#
+# physfs needs a toolchain w/ C++, threads
+#
+
+#
+# Graphics
+#
+
+#
+# assimp needs libzlib
+#
+
+#
+# at-spi2-atk depends on X.org
+#
+
+#
+# at-spi2-core depends on X.org
+#
+# BR2_PACKAGE_ATK is not set
+
+#
+# atkmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
+#
+
+#
+# bullet needs a toolchain w/ C++, dynamic library, threads, wchar
+#
+# BR2_PACKAGE_CAIRO is not set
+
+#
+# cairomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.8
+#
+
+#
+# chipmunk needs an OpenGL backend
+#
+
+#
+# exempi needs a toolchain w/ C++, dynamic library, threads, wchar
+#
+
+#
+# exiv2 needs a uClibc or glibc toolchain w/ C++, wchar, dynamic library, threads
+#
+# BR2_PACKAGE_FONTCONFIG is not set
+# BR2_PACKAGE_FREETYPE is not set
+# BR2_PACKAGE_GD is not set
+# BR2_PACKAGE_GDK_PIXBUF is not set
+# BR2_PACKAGE_GIFLIB is not set
+
+#
+# granite needs libgtk3 and a toolchain w/ wchar, threads
+#
+
+#
+# graphite2 needs a toolchain w/ C++
+#
+
+#
+# gtkmm3 needs libgtk3 and a toolchain w/ C++, wchar, threads, gcc >= 4.9
+#
+
+#
+# harfbuzz needs a toolchain w/ C++, gcc >= 4.8
+#
+# BR2_PACKAGE_IJS is not set
+# BR2_PACKAGE_IMLIB2 is not set
+
+#
+# irrlicht needs a toolchain w/ C++
+#
+# BR2_PACKAGE_JASPER is not set
+# BR2_PACKAGE_JBIG2DEC is not set
+# BR2_PACKAGE_JPEG is not set
+
+#
+# kms++ needs a toolchain w/ threads, C++, gcc >= 4.8, headers >= 4.11, wchar
+#
+# BR2_PACKAGE_LCMS2 is not set
+
+#
+# lensfun needs a toolchain w/ C++, threads, wchar
+#
+# BR2_PACKAGE_LEPTONICA is not set
+# BR2_PACKAGE_LIBART is not set
+# BR2_PACKAGE_LIBDMTX is not set
+# BR2_PACKAGE_LIBDRM is not set
+
+#
+# libepoxy needs an OpenGL and/or OpenGL EGL backend
+#
+# BR2_PACKAGE_LIBEXIF is not set
+
+#
+# libfm needs X.org and a toolchain w/ wchar, threads, C++, gcc >= 4.8
+#
+# BR2_PACKAGE_LIBFM_EXTRA is not set
+
+#
+# libfreeglut depends on X.org and needs an OpenGL backend
+#
+
+#
+# libfreeimage needs a toolchain w/ C++, dynamic library, wchar
+#
+
+#
+# libgeotiff needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
+#
+
+#
+# libglew depends on X.org and needs an OpenGL backend
+#
+
+#
+# libglfw depends on X.org and needs an OpenGL backend
+#
+
+#
+# libglu needs an OpenGL backend
+#
+# BR2_PACKAGE_LIBGTA is not set
+
+#
+# libgtk3 needs a toolchain w/ wchar, threads, C++, gcc >= 4.8
+#
+
+#
+# libgtk3 needs an OpenGL or an OpenGL-EGL/wayland backend
+#
+# BR2_PACKAGE_LIBMEDIAART is not set
+# BR2_PACKAGE_LIBMNG is not set
+# BR2_PACKAGE_LIBPNG is not set
+# BR2_PACKAGE_LIBQRENCODE is not set
+
+#
+# libraw needs a toolchain w/ C++
+#
+
+#
+# libsoil needs an OpenGL backend and a toolchain w/ dynamic library
+#
+# BR2_PACKAGE_LIBSVG is not set
+# BR2_PACKAGE_LIBSVG_CAIRO is not set
+# BR2_PACKAGE_LIBSVGTINY is not set
+# BR2_PACKAGE_LIBVA is not set
+
+#
+# libvips needs a toolchain w/ wchar, threads, C++
+#
+
+#
+# libwpe needs a toolchain w/ C++, dynamic library and an OpenEGL-capable backend
+#
+# BR2_PACKAGE_MENU_CACHE is not set
+
+#
+# opencv3 needs a toolchain w/ C++, NPTL, wchar, dynamic library
+#
+# BR2_PACKAGE_OPENJPEG is not set
+
+#
+# pango needs a toolchain w/ wchar, threads, C++, gcc >= 4.8
+#
+
+#
+# pangomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_PIPEWIRE is not set
+# BR2_PACKAGE_PIXMAN is not set
+
+#
+# poppler needs a toolchain w/ wchar, C++, threads, dynamic library, gcc >= 5
+#
+# BR2_PACKAGE_TIFF is not set
+# BR2_PACKAGE_WAYLAND is not set
+# BR2_PACKAGE_WEBP is not set
+
+#
+# wlroots needs udev, EGL w/ Wayland backend and OpenGL ES support
+#
+
+#
+# woff2 needs a toolchain w/ C++
+#
+
+#
+# wpebackend-fdo needs a toolchain w/ C++, wchar, threads, dynamic library and an OpenEGL-capable Wayland backend
+#
+
+#
+# zbar needs a toolchain w/ threads, C++ and headers >= 3.0
+#
+
+#
+# zxing-cpp needs a toolchain w/ C++, dynamic library
+#
+
+#
+# Hardware handling
+#
+# BR2_PACKAGE_ACSCCID is not set
+# BR2_PACKAGE_C_PERIPHERY is not set
+# BR2_PACKAGE_CCID is not set
+# BR2_PACKAGE_DTC is not set
+# BR2_PACKAGE_HACKRF is not set
+
+#
+# hidapi needs udev /dev management and a toolchain w/ NPTL, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_JITTERENTROPY_LIBRARY is not set
+
+#
+# lcdapi needs a toolchain w/ C++, threads
+#
+
+#
+# let-me-create needs a toolchain w/ C++, threads, dynamic library
+#
+# BR2_PACKAGE_LIBAIO is not set
+
+#
+# libatasmart requires udev to be enabled
+#
+
+#
+# libblockdev needs udev /dev management and a toolchain w/ wchar, threads, dynamic library
+#
+
+#
+# libcec needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 4.7
+#
+# BR2_PACKAGE_LIBFREEFARE is not set
+# BR2_PACKAGE_LIBFTDI is not set
+# BR2_PACKAGE_LIBFTDI1 is not set
+# BR2_PACKAGE_LIBGPHOTO2 is not set
+# BR2_PACKAGE_LIBGPIOD is not set
+
+#
+# libgudev needs udev /dev handling and a toolchain w/ wchar, threads
+#
+# BR2_PACKAGE_LIBHID is not set
+# BR2_PACKAGE_LIBIIO is not set
+
+#
+# libinput needs udev /dev management
+#
+# BR2_PACKAGE_LIBIQRF is not set
+# BR2_PACKAGE_LIBLLCP is not set
+# BR2_PACKAGE_LIBMBIM is not set
+# BR2_PACKAGE_LIBNFC is not set
+# BR2_PACKAGE_LIBPCIACCESS is not set
+# BR2_PACKAGE_LIBPHIDGET is not set
+# BR2_PACKAGE_LIBPRI is not set
+# BR2_PACKAGE_LIBQMI is not set
+# BR2_PACKAGE_LIBQRTR_GLIB is not set
+# BR2_PACKAGE_LIBRAW1394 is not set
+# BR2_PACKAGE_LIBRTLSDR is not set
+
+#
+# libserial needs a toolchain w/ C++, gcc >= 5, threads, wchar
+#
+# BR2_PACKAGE_LIBSERIALPORT is not set
+# BR2_PACKAGE_LIBSIGROK is not set
+# BR2_PACKAGE_LIBSIGROKDECODE is not set
+# BR2_PACKAGE_LIBSOC is not set
+# BR2_PACKAGE_LIBSS7 is not set
+# BR2_PACKAGE_LIBUSB is not set
+# BR2_PACKAGE_LIBUSBGX is not set
+
+#
+# libv4l needs a toolchain w/ threads, C++ and headers >= 3.0
+#
+# BR2_PACKAGE_LIBXKBCOMMON is not set
+# BR2_PACKAGE_MTDEV is not set
+# BR2_PACKAGE_NEARDAL is not set
+# BR2_PACKAGE_OWFS is not set
+# BR2_PACKAGE_PCSC_LITE is not set
+# BR2_PACKAGE_TSLIB is not set
+
+#
+# uhd needs a toolchain w/ C++, NPTL, wchar, dynamic library
+#
+
+#
+# urg needs a toolchain w/ C++
+#
+
+#
+# Javascript
+#
+# BR2_PACKAGE_ANGULARJS is not set
+# BR2_PACKAGE_BOOTSTRAP is not set
+# BR2_PACKAGE_CHARTJS is not set
+# BR2_PACKAGE_DATATABLES is not set
+# BR2_PACKAGE_DUKTAPE is not set
+# BR2_PACKAGE_EXPLORERCANVAS is not set
+# BR2_PACKAGE_FLOT is not set
+# BR2_PACKAGE_JQUERY is not set
+# BR2_PACKAGE_JSMIN is not set
+# BR2_PACKAGE_JSON_JAVASCRIPT is not set
+# BR2_PACKAGE_JSZIP is not set
+# BR2_PACKAGE_OPENLAYERS is not set
+# BR2_PACKAGE_POPPERJS is not set
+BR2_PACKAGE_SPIDERMONKEY_ARCH_SUPPORTS=y
+
+#
+# spidermonkey needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9
+#
+# BR2_PACKAGE_VUEJS is not set
+
+#
+# JSON/XML
+#
+
+#
+# benejson needs a toolchain w/ C++
+#
+# BR2_PACKAGE_CJSON is not set
+# BR2_PACKAGE_EXPAT is not set
+# BR2_PACKAGE_JANSSON is not set
+# BR2_PACKAGE_JOSE is not set
+# BR2_PACKAGE_JSMN is not set
+# BR2_PACKAGE_JSON_C is not set
+
+#
+# json-for-modern-cpp needs a toolchain w/ C++, gcc >= 4.9
+#
+# BR2_PACKAGE_JSON_GLIB is not set
+
+#
+# jsoncpp needs a toolchain w/ C++, gcc >= 4.7
+#
+# BR2_PACKAGE_LIBBSON is not set
+# BR2_PACKAGE_LIBFASTJSON is not set
+
+#
+# libjson needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBROXML is not set
+# BR2_PACKAGE_LIBUCL is not set
+# BR2_PACKAGE_LIBXML2 is not set
+
+#
+# libxml++ needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_LIBXMLRPC is not set
+# BR2_PACKAGE_LIBXSLT is not set
+# BR2_PACKAGE_LIBYAML is not set
+# BR2_PACKAGE_MXML is not set
+
+#
+# pugixml needs a toolchain w/ C++
+#
+
+#
+# rapidjson needs a toolchain w/ C++
+#
+# BR2_PACKAGE_RAPIDXML is not set
+# BR2_PACKAGE_RAPTOR is not set
+
+#
+# tinyxml needs a toolchain w/ C++
+#
+
+#
+# tinyxml2 needs a toolchain w/ C++
+#
+
+#
+# valijson needs a toolchain w/ C++, threads, wchar  support
+#
+
+#
+# xerces-c++ needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_YAJL is not set
+
+#
+# yaml-cpp needs a toolchain w/ C++, gcc >= 4.7
+#
+
+#
+# Logging
+#
+
+#
+# glog needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBLOG4C_LOCALTIME is not set
+# BR2_PACKAGE_LIBLOGGING is not set
+
+#
+# log4cplus needs a toolchain w/ C++, wchar, threads, gcc >= 4.8
+#
+
+#
+# log4cpp needs a toolchain w/ C++, threads
+#
+
+#
+# log4cxx needs a toolchain w/ C++, threads, dynamic library
+#
+
+#
+# log4qt needs qt5
+#
+
+#
+# opentracing-cpp needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
+#
+
+#
+# spdlog needs a toolchain w/ C++, threads, wchar
+#
+# BR2_PACKAGE_ZLOG is not set
+
+#
+# Multimedia
+#
+# BR2_PACKAGE_BITSTREAM is not set
+# BR2_PACKAGE_DAV1D is not set
+
+#
+# kvazaar needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBAACS is not set
+
+#
+# libass needs a toolchain w/ C++, gcc >= 4.8
+#
+# BR2_PACKAGE_LIBBDPLUS is not set
+# BR2_PACKAGE_LIBBLURAY is not set
+BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
+
+#
+# libcamera needs a toolchain w/ C++, threads, wchar, dynamic library, gcc >= 7
+#
+# BR2_PACKAGE_LIBDCADEC is not set
+# BR2_PACKAGE_LIBDVBCSA is not set
+# BR2_PACKAGE_LIBDVBPSI is not set
+
+#
+# libdvbsi++ needs a toolchain w/ C++, wchar, threads
+#
+# BR2_PACKAGE_LIBDVDCSS is not set
+# BR2_PACKAGE_LIBDVDNAV is not set
+# BR2_PACKAGE_LIBDVDREAD is not set
+
+#
+# libebml needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_LIBHDHOMERUN is not set
+
+#
+# libmatroska needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_LIBMMS is not set
+# BR2_PACKAGE_LIBMPEG2 is not set
+# BR2_PACKAGE_LIBOGG is not set
+# BR2_PACKAGE_LIBOPUSENC is not set
+# BR2_PACKAGE_LIBTHEORA is not set
+# BR2_PACKAGE_LIBUDFREAD is not set
+# BR2_PACKAGE_LIBVPX is not set
+
+#
+# libyuv needs a toolchain w/ C++, dynamic library
+#
+
+#
+# live555 needs a toolchain w/ C++
+#
+
+#
+# mediastreamer needs a toolchain w/ threads, C++, dynamic library, gcc >= 5
+#
+# BR2_PACKAGE_X264 is not set
+
+#
+# x265 needs a toolchain w/ C++, threads, dynamic library
+#
+
+#
+# Networking
+#
+
+#
+# agent++ needs a toolchain w/ threads, C++, dynamic library
+#
+
+#
+# azmq needs a toolchain w/ C++11, wchar and NPTL
+#
+
+#
+# azure-iot-sdk-c needs a toolchain w/ C++, NPTL and wchar
+#
+# BR2_PACKAGE_BATMAN_ADV is not set
+
+#
+# belle-sip needs a toolchain w/ threads, C++, dynamic library, wchar
+#
+# BR2_PACKAGE_C_ARES is not set
+# BR2_PACKAGE_CGIC is not set
+
+#
+# cppzmq needs a toolchain w/ C++, threads
+#
+
+#
+# curlpp needs a toolchain w/ C++, dynamic library
+#
+
+#
+# czmq needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_DAQ is not set
+# BR2_PACKAGE_DAVICI is not set
+# BR2_PACKAGE_ENET is not set
+
+#
+# filemq needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_FLICKCURL is not set
+# BR2_PACKAGE_FREERADIUS_CLIENT is not set
+# BR2_PACKAGE_GENSIO is not set
+# BR2_PACKAGE_GEOIP is not set
+# BR2_PACKAGE_GLIB_NETWORKING is not set
+
+#
+# grpc needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.9, host gcc >= 4.9
+#
+# BR2_PACKAGE_GSSDP is not set
+# BR2_PACKAGE_GUPNP is not set
+# BR2_PACKAGE_GUPNP_AV is not set
+# BR2_PACKAGE_GUPNP_DLNA is not set
+
+#
+# ibrcommon needs a toolchain w/ C++, threads
+#
+
+#
+# ibrdtn needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBCGI is not set
+
+#
+# libcgicc needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LIBCOAP is not set
+
+#
+# libcpprestsdk needs a toolchain w/ NPTL, C++, wchar, locale
+#
+# BR2_PACKAGE_LIBCURL is not set
+# BR2_PACKAGE_LIBDNET is not set
+# BR2_PACKAGE_LIBEXOSIP2 is not set
+# BR2_PACKAGE_LIBFCGI is not set
+# BR2_PACKAGE_LIBGSASL is not set
+# BR2_PACKAGE_LIBHTP is not set
+# BR2_PACKAGE_LIBHTTPPARSER is not set
+
+#
+# libhttpserver needs a toolchain w/ C++, threads, gcc >= 5
+#
+# BR2_PACKAGE_LIBIDN is not set
+# BR2_PACKAGE_LIBIDN2 is not set
+# BR2_PACKAGE_LIBISCSI is not set
+# BR2_PACKAGE_LIBKRB5 is not set
+# BR2_PACKAGE_LIBLDNS is not set
+# BR2_PACKAGE_LIBMAXMINDDB is not set
+# BR2_PACKAGE_LIBMBUS is not set
+
+#
+# libmemcached needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBMICROHTTPD is not set
+# BR2_PACKAGE_LIBMINIUPNPC is not set
+# BR2_PACKAGE_LIBMNL is not set
+# BR2_PACKAGE_LIBMODBUS is not set
+
+#
+# libmodsecurity needs a toolchain w/ C++, dynamic library, threads
+#
+# BR2_PACKAGE_LIBNATPMP is not set
+# BR2_PACKAGE_LIBNDP is not set
+# BR2_PACKAGE_LIBNET is not set
+# BR2_PACKAGE_LIBNETCONF2 is not set
+# BR2_PACKAGE_LIBNETFILTER_ACCT is not set
+# BR2_PACKAGE_LIBNETFILTER_CONNTRACK is not set
+# BR2_PACKAGE_LIBNETFILTER_CTHELPER is not set
+# BR2_PACKAGE_LIBNETFILTER_CTTIMEOUT is not set
+# BR2_PACKAGE_LIBNETFILTER_LOG is not set
+# BR2_PACKAGE_LIBNETFILTER_QUEUE is not set
+# BR2_PACKAGE_LIBNFNETLINK is not set
+# BR2_PACKAGE_LIBNFTNL is not set
+# BR2_PACKAGE_LIBNICE is not set
+# BR2_PACKAGE_LIBNIDS is not set
+# BR2_PACKAGE_LIBNL is not set
+
+#
+# libnpupnp needs a toolchain w/ C++, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_LIBOAUTH is not set
+# BR2_PACKAGE_LIBOPING is not set
+# BR2_PACKAGE_LIBOSIP2 is not set
+# BR2_PACKAGE_LIBPAGEKITE is not set
+# BR2_PACKAGE_LIBPCAP is not set
+
+#
+# libpjsip needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBRELP is not set
+# BR2_PACKAGE_LIBRSYNC is not set
+# BR2_PACKAGE_LIBSHAIRPLAY is not set
+# BR2_PACKAGE_LIBSHOUT is not set
+# BR2_PACKAGE_LIBSOCKETCAN is not set
+# BR2_PACKAGE_LIBSOUP is not set
+# BR2_PACKAGE_LIBSRTP is not set
+# BR2_PACKAGE_LIBSTROPHE is not set
+# BR2_PACKAGE_LIBTELNET is not set
+# BR2_PACKAGE_LIBTIRPC is not set
+
+#
+# libtorrent needs a toolchain w/ C++, threads
+#
+
+#
+# libtorrent-rasterbar needs a toolchain w/ C++, threads, wchar, gcc >= 4.9
+#
+# BR2_PACKAGE_LIBUEV is not set
+# BR2_PACKAGE_LIBUHTTPD is not set
+# BR2_PACKAGE_LIBUPNP is not set
+
+#
+# libupnpp needs a toolchain w/ C++, threads, gcc >= 4.9
+#
+# BR2_PACKAGE_LIBURIPARSER is not set
+# BR2_PACKAGE_LIBUWSC is not set
+# BR2_PACKAGE_LIBVNCSERVER is not set
+# BR2_PACKAGE_LIBWEBSOCK is not set
+# BR2_PACKAGE_LIBWEBSOCKETS is not set
+# BR2_PACKAGE_LIBYANG is not set
+# BR2_PACKAGE_LKSCTP_TOOLS is not set
+# BR2_PACKAGE_MBUFFER is not set
+# BR2_PACKAGE_MONGOOSE is not set
+# BR2_PACKAGE_NANOMSG is not set
+# BR2_PACKAGE_NEON is not set
+
+#
+# netopeer2 needs a toolchain w/ gcc >= 4.8, C++, threads, dynamic library
+#
+# BR2_PACKAGE_NGHTTP2 is not set
+
+#
+# norm needs a toolchain w/ C++, threads, dynamic library
+#
+# BR2_PACKAGE_NSS_MYHOSTNAME is not set
+# BR2_PACKAGE_NSS_PAM_LDAPD is not set
+
+#
+# omniORB needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_OPEN62541 is not set
+# BR2_PACKAGE_OPENLDAP is not set
+
+#
+# openmpi needs a toolchain w/ dynamic library, NPTL, wchar, C++
+#
+# BR2_PACKAGE_OPENPGM is not set
+
+#
+# openzwave needs a toolchain w/ C++, dynamic library, NPTL, wchar
+#
+
+#
+# ortp needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_PAHO_MQTT_C is not set
+
+#
+# paho-mqtt-cpp needs a toolchain w/ threads, C++
+#
+
+#
+# pistache needs a glibc toolchain w/ C++, gcc >= 4.9, threads, wchar
+#
+# BR2_PACKAGE_QDECODER is not set
+# BR2_PACKAGE_QPID_PROTON is not set
+# BR2_PACKAGE_RABBITMQ_C is not set
+
+#
+# resiprocate needs a toolchain w/ C++, threads, wchar
+#
+
+#
+# restclient-cpp needs a toolchain w/ C++, gcc >= 4.8
+#
+# BR2_PACKAGE_RTMPDUMP is not set
+# BR2_PACKAGE_SIPROXD is not set
+# BR2_PACKAGE_SLIRP is not set
+
+#
+# snmp++ needs a toolchain w/ threads, C++, dynamic library
+#
+# BR2_PACKAGE_SOFIA_SIP is not set
+
+#
+# sysrepo needs a toolchain w/ C++, NPTL, dynamic library, gcc >= 4.8
+#
+
+#
+# thrift needs a toolchain w/ C++, wchar, threads
+#
+# BR2_PACKAGE_USBREDIR is not set
+
+#
+# wampcc needs a toolchain w/ C++, NPTL, dynamic library
+#
+
+#
+# websocketpp needs a toolchain w/ C++ and gcc >= 4.8
+#
+
+#
+# zeromq needs a toolchain w/ C++, threads
+#
+
+#
+# zmqpp needs a toolchain w/ C++, threads, gcc >= 4.7
+#
+
+#
+# zyre needs a toolchain w/ C++, threads
+#
+
+#
+# Other
+#
+# BR2_PACKAGE_APR is not set
+# BR2_PACKAGE_APR_UTIL is not set
+
+#
+# armadillo needs a toolchain w/ C++
+#
+
+#
+# atf needs a toolchain w/ C++
+#
+# BR2_PACKAGE_AVRO_C is not set
+
+#
+# bctoolbox needs a toolchain w/ C++, threads
+#
+
+#
+# belr needs a toolchain w/ threads, C++
+#
+
+#
+# boost needs a toolchain w/ C++, threads, wchar
+#
+
+#
+# c-capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735
+#
+
+#
+# capnproto needs host and target gcc >= 5 w/ C++14, threads, atomic, ucontext and not gcc bug 64735
+#
+
+#
+# cctz needs a toolchain w/ C++, threads, gcc >= 4.8
+#
+
+#
+# cereal needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
+#
+# BR2_PACKAGE_CLAPACK is not set
+# BR2_PACKAGE_CMOCKA is not set
+
+#
+# cppcms needs a toolchain w/ C++, NPTL, wchar, dynamic library
+#
+# BR2_PACKAGE_CRACKLIB is not set
+
+#
+# dawgdic needs a toolchain w/ C++, gcc >= 4.6
+#
+# BR2_PACKAGE_DING_LIBS is not set
+
+#
+# eigen needs a toolchain w/ C++
+#
+# BR2_PACKAGE_ELFUTILS is not set
+# BR2_PACKAGE_ELL is not set
+# BR2_PACKAGE_FFTW is not set
+
+#
+# flann needs a toolchain w/ C++, dynamic library
+#
+
+#
+# flatbuffers needs a toolchain w/ C++, gcc >= 4.7
+#
+# BR2_PACKAGE_FLATCC is not set
+# BR2_PACKAGE_GCONF is not set
+
+#
+# gflags needs a toolchain w/ C++
+#
+
+#
+# gli needs a toolchain w/ C++
+#
+
+#
+# glibmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9
+#
+
+#
+# glm needs a toolchain w/ C++
+#
+# BR2_PACKAGE_GMP is not set
+BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y
+
+#
+# gobject-introspection needs python3
+#
+# BR2_PACKAGE_GSL is not set
+
+#
+# gtest needs a toolchain w/ C++, wchar, threads
+#
+BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y
+# BR2_PACKAGE_JEMALLOC is not set
+
+#
+# lapack/blas needs a toolchain w/ fortran
+#
+BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y
+
+#
+# libabseil-cpp needs a toolchain w/ gcc >= 4.9, C++, threads, dynamic library
+#
+# BR2_PACKAGE_LIBARGTABLE2 is not set
+# BR2_PACKAGE_LIBAVL is not set
+# BR2_PACKAGE_LIBB64 is not set
+# BR2_PACKAGE_LIBBACKTRACE is not set
+BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y
+# BR2_PACKAGE_LIBBSD is not set
+# BR2_PACKAGE_LIBBYTESIZE is not set
+# BR2_PACKAGE_LIBCAP is not set
+# BR2_PACKAGE_LIBCAP_NG is not set
+
+#
+# libcgroup needs a glibc toolchain w/ C++
+#
+# BR2_PACKAGE_LIBCORRECT is not set
+
+#
+# libcrossguid needs a toolchain w/ C++, gcc >= 4.7
+#
+# BR2_PACKAGE_LIBCSV is not set
+# BR2_PACKAGE_LIBDAEMON is not set
+# BR2_PACKAGE_LIBEE is not set
+# BR2_PACKAGE_LIBEV is not set
+# BR2_PACKAGE_LIBEVDEV is not set
+# BR2_PACKAGE_LIBEVENT is not set
+# BR2_PACKAGE_LIBFFI is not set
+# BR2_PACKAGE_LIBGEE is not set
+
+#
+# libgeos needs a toolchain w/ C++, wchar, not binutils bug 21464, 27597
+#
+# BR2_PACKAGE_LIBGLIB2 is not set
+# BR2_PACKAGE_LIBGLOB is not set
+
+#
+# libical needs a toolchain w/ C++, dynamic library, wchar
+#
+# BR2_PACKAGE_LIBITE is not set
+
+#
+# liblinear needs a toolchain w/ C++
+#
+
+#
+# libloki needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBNPTH is not set
+BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y
+# BR2_PACKAGE_LIBNSPR is not set
+# BR2_PACKAGE_LIBPFM4 is not set
+
+#
+# libplist needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_LIBPTHREAD_STUBS is not set
+# BR2_PACKAGE_LIBPTHSEM is not set
+# BR2_PACKAGE_LIBPWQUALITY is not set
+
+#
+# libsigc++ needs a toolchain w/ C++, gcc >= 4.8
+#
+BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y
+# BR2_PACKAGE_LIBSIGSEGV is not set
+
+#
+# libspatialindex needs a toolchain w/ C++, gcc >= 4.7
+#
+# BR2_PACKAGE_LIBTASN1 is not set
+# BR2_PACKAGE_LIBTOMMATH is not set
+# BR2_PACKAGE_LIBTPL is not set
+# BR2_PACKAGE_LIBUBOX is not set
+# BR2_PACKAGE_LIBUCI is not set
+BR2_PACKAGE_LIBURCU_ARCH_SUPPORTS=y
+# BR2_PACKAGE_LIBURCU is not set
+# BR2_PACKAGE_LIBUV is not set
+# BR2_PACKAGE_LIGHTNING is not set
+# BR2_PACKAGE_LINUX_PAM is not set
+# BR2_PACKAGE_LIQUID_DSP is not set
+# BR2_PACKAGE_LTTNG_LIBUST is not set
+# BR2_PACKAGE_MATIO is not set
+# BR2_PACKAGE_MPC is not set
+# BR2_PACKAGE_MPDECIMAL is not set
+# BR2_PACKAGE_MPFR is not set
+# BR2_PACKAGE_MPIR is not set
+
+#
+# msgpack needs a toolchain w/ C++
+#
+# BR2_PACKAGE_ORC is not set
+# BR2_PACKAGE_P11_KIT is not set
+BR2_PACKAGE_POCO_ARCH_SUPPORTS=y
+
+#
+# poco needs a toolchain w/ wchar, NPTL, C++, dynamic library, gcc >= 5 w/ C++14
+#
+BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y
+
+#
+# protobuf needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
+#
+
+#
+# protobuf-c needs a toolchain w/ C++, threads
+#
+
+#
+# protozero needs a toolchain w/ C++,  gcc >= 4.7
+#
+
+#
+# qhull needs a toolchain w/ C++, gcc >= 4.4
+#
+# BR2_PACKAGE_QLIBC is not set
+
+#
+# riemann-c-client needs a toolchain w/ C++, threads
+#
+
+#
+# shapelib needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_SKALIBS is not set
+# BR2_PACKAGE_SPHINXBASE is not set
+# BR2_PACKAGE_TINYCBOR is not set
+
+#
+# uvw needs a toolchain w/ NPTL, dynamic library, C++, gcc >= 7
+#
+
+#
+# xapian needs a toolchain w/ C++
+#
+
+#
+# Security
+#
+# BR2_PACKAGE_LIBAPPARMOR is not set
+# BR2_PACKAGE_LIBSELINUX is not set
+# BR2_PACKAGE_LIBSEPOL is not set
+# BR2_PACKAGE_SAFECLIB is not set
+
+#
+# Text and terminal handling
+#
+# BR2_PACKAGE_AUGEAS is not set
+
+#
+# enchant needs a toolchain w/ C++, threads, wchar
+#
+
+#
+# fmt needs a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_FSTRCMP is not set
+
+#
+# icu needs a toolchain w/ C++, wchar, threads, gcc >= 4.9, host gcc >= 4.9
+#
+# BR2_PACKAGE_INIH is not set
+# BR2_PACKAGE_LIBCLI is not set
+# BR2_PACKAGE_LIBEDIT is not set
+# BR2_PACKAGE_LIBENCA is not set
+# BR2_PACKAGE_LIBESTR is not set
+# BR2_PACKAGE_LIBFRIBIDI is not set
+# BR2_PACKAGE_LIBUNISTRING is not set
+# BR2_PACKAGE_LINENOISE is not set
+# BR2_PACKAGE_NCURSES is not set
+# BR2_PACKAGE_NEWT is not set
+# BR2_PACKAGE_ONIGURUMA is not set
+# BR2_PACKAGE_PCRE is not set
+# BR2_PACKAGE_PCRE2 is not set
+# BR2_PACKAGE_POPT is not set
+
+#
+# re2 needs a toolchain w/ C++, threads, gcc >= 4.8
+#
+# BR2_PACKAGE_READLINE is not set
+# BR2_PACKAGE_SLANG is not set
+
+#
+# tclap needs a toolchain w/ C++
+#
+# BR2_PACKAGE_UTF8PROC is not set
+
+#
+# Mail
+#
+# BR2_PACKAGE_DOVECOT is not set
+# BR2_PACKAGE_EXIM is not set
+# BR2_PACKAGE_FETCHMAIL is not set
+# BR2_PACKAGE_HEIRLOOM_MAILX is not set
+# BR2_PACKAGE_LIBESMTP is not set
+# BR2_PACKAGE_MSMTP is not set
+# BR2_PACKAGE_MUTT is not set
+
+#
+# Miscellaneous
+#
+# BR2_PACKAGE_AESPIPE is not set
+# BR2_PACKAGE_BC is not set
+BR2_PACKAGE_BITCOIN_ARCH_SUPPORTS=y
+
+#
+# bitcoin needs a toolchain w/ C++, threads, wchar
+#
+
+#
+# clamav needs a toolchain w/ C++, dynamic library, threads, wchar
+#
+# BR2_PACKAGE_COLLECTD is not set
+# BR2_PACKAGE_COLLECTL is not set
+
+#
+# domoticz needs lua 5.3 and a toolchain w/ C++, gcc >= 6, NPTL, wchar, dynamic library
+#
+# BR2_PACKAGE_EMPTY is not set
+
+#
+# gnuradio needs a toolchain w/ C++, NPTL, wchar, dynamic library
+#
+# BR2_PACKAGE_GOOGLEFONTDIRECTORY is not set
+
+#
+# gqrx needs a toolchain w/ C++, threads, wchar, dynamic library
+#
+
+#
+# gqrx needs qt5
+#
+# BR2_PACKAGE_GSETTINGS_DESKTOP_SCHEMAS is not set
+# BR2_PACKAGE_HAVEGED is not set
+# BR2_PACKAGE_LINUX_SYSCALL_SUPPORT is not set
+# BR2_PACKAGE_MCRYPT is not set
+# BR2_PACKAGE_MOBILE_BROADBAND_PROVIDER_INFO is not set
+# BR2_PACKAGE_NETDATA is not set
+
+#
+# proj needs a toolchain w/ C++, gcc >= 4.7, threads, wchar
+#
+
+#
+# qpdf needs a toolchain w/ C++, wchar, gcc >= 4.7
+#
+# BR2_PACKAGE_SHARED_MIME_INFO is not set
+
+#
+# sunwait needs a toolchain w/ C++
+#
+
+#
+# taskd needs a toolchain w/ C++, wchar, dynamic library
+#
+# BR2_PACKAGE_XUTIL_UTIL_MACROS is not set
+
+#
+# Networking applications
+#
+
+#
+# aircrack-ng needs a toolchain w/ dynamic library, threads, C++
+#
+# BR2_PACKAGE_AOETOOLS is not set
+# BR2_PACKAGE_APACHE is not set
+# BR2_PACKAGE_ARGUS is not set
+# BR2_PACKAGE_ARP_SCAN is not set
+# BR2_PACKAGE_ARPTABLES is not set
+
+#
+# asterisk needs a glibc or uClibc toolchain w/ C++, dynamic library, threads, wchar
+#
+# BR2_PACKAGE_ATFTP is not set
+# BR2_PACKAGE_AVAHI is not set
+# BR2_PACKAGE_AXEL is not set
+# BR2_PACKAGE_BABELD is not set
+# BR2_PACKAGE_BANDWIDTHD is not set
+# BR2_PACKAGE_BATCTL is not set
+
+#
+# bcusdk needs a toolchain w/ C++
+#
+# BR2_PACKAGE_BIND is not set
+# BR2_PACKAGE_BIRD is not set
+# BR2_PACKAGE_BLUEZ5_UTILS is not set
+# BR2_PACKAGE_BMON is not set
+
+#
+# boinc needs a toolchain w/ dynamic library, C++, threads
+#
+# BR2_PACKAGE_BRCM_PATCHRAM_PLUS is not set
+# BR2_PACKAGE_BRIDGE_UTILS is not set
+# BR2_PACKAGE_BWM_NG is not set
+# BR2_PACKAGE_C_ICAP is not set
+# BR2_PACKAGE_CAN_UTILS is not set
+
+#
+# cannelloni needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8
+#
+# BR2_PACKAGE_CASYNC is not set
+# BR2_PACKAGE_CHRONY is not set
+# BR2_PACKAGE_CIVETWEB is not set
+# BR2_PACKAGE_CONNMAN is not set
+
+#
+# connman-gtk needs libgtk3 and a glibc or uClibc toolchain w/ wchar, threads, resolver, dynamic library
+#
+# BR2_PACKAGE_CONNTRACK_TOOLS is not set
+# BR2_PACKAGE_CORKSCREW is not set
+# BR2_PACKAGE_CRDA is not set
+
+#
+# ctorrent needs a toolchain w/ C++
+#
+
+#
+# cups needs a toolchain w/ C++, threads
+#
+
+#
+# cups-filters needs a toolchain w/ wchar, C++, threads and dynamic library, gcc >= 4.8
+#
+# BR2_PACKAGE_DANTE is not set
+# BR2_PACKAGE_DARKHTTPD is not set
+# BR2_PACKAGE_DEHYDRATED is not set
+# BR2_PACKAGE_DHCPCD is not set
+# BR2_PACKAGE_DHCPDUMP is not set
+# BR2_PACKAGE_DNSMASQ is not set
+# BR2_PACKAGE_DRBD_UTILS is not set
+# BR2_PACKAGE_DROPBEAR is not set
+# BR2_PACKAGE_EASYFRAMES is not set
+# BR2_PACKAGE_EBTABLES is not set
+
+#
+# ejabberd needs erlang, toolchain w/ C++
+#
+# BR2_PACKAGE_ETHTOOL is not set
+# BR2_PACKAGE_FAIFA is not set
+# BR2_PACKAGE_FASTD is not set
+# BR2_PACKAGE_FCGIWRAP is not set
+# BR2_PACKAGE_FPING is not set
+
+#
+# freeswitch needs a toolchain w/ C++, dynamic library, threads, wchar
+#
+# BR2_PACKAGE_FRR is not set
+
+#
+# gerbera needs a toolchain w/ C++, dynamic library, threads, wchar, gcc >= 8
+#
+# BR2_PACKAGE_GESFTPSERVER is not set
+
+#
+# gloox needs a toolchain w/ C++
+#
+# BR2_PACKAGE_GLORYTUN is not set
+
+#
+# gupnp-tools needs libgtk3
+#
+
+#
+# hans needs a toolchain w/ C++
+#
+BR2_PACKAGE_HAPROXY_ARCH_SUPPORTS=y
+# BR2_PACKAGE_HAPROXY is not set
+# BR2_PACKAGE_HIAWATHA is not set
+# BR2_PACKAGE_HOSTAPD is not set
+# BR2_PACKAGE_HTPDATE is not set
+# BR2_PACKAGE_HTTPING is not set
+
+#
+# i2pd needs a toolchain w/ C++, NPTL, wchar
+#
+
+#
+# ibrdtn-tools needs a toolchain w/ C++, threads
+#
+
+#
+# ibrdtnd needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_IFMETRIC is not set
+# BR2_PACKAGE_IFTOP is not set
+# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set
+# BR2_PACKAGE_IGD2_FOR_LINUX is not set
+# BR2_PACKAGE_IGH_ETHERCAT is not set
+# BR2_PACKAGE_IGMPPROXY is not set
+# BR2_PACKAGE_INADYN is not set
+# BR2_PACKAGE_IODINE is not set
+
+#
+# iperf needs a toolchain w/ C++
+#
+# BR2_PACKAGE_IPERF3 is not set
+# BR2_PACKAGE_IPROUTE2 is not set
+# BR2_PACKAGE_IPSET is not set
+# BR2_PACKAGE_IPTABLES is not set
+# BR2_PACKAGE_IPTRAF_NG is not set
+# BR2_PACKAGE_IPUTILS is not set
+# BR2_PACKAGE_IRSSI is not set
+# BR2_PACKAGE_IW is not set
+# BR2_PACKAGE_IWD is not set
+# BR2_PACKAGE_JANUS_GATEWAY is not set
+# BR2_PACKAGE_KEEPALIVED is not set
+
+#
+# kismet needs a toolchain w/ threads, C++
+#
+# BR2_PACKAGE_KNOCK is not set
+# BR2_PACKAGE_LEAFNODE2 is not set
+# BR2_PACKAGE_LFT is not set
+
+#
+# lftp requires a toolchain w/ C++, wchar
+#
+# BR2_PACKAGE_LIGHTTPD is not set
+
+#
+# linknx needs a toolchain w/ C++
+#
+# BR2_PACKAGE_LINKS is not set
+
+#
+# linphone needs a toolchain w/ threads, C++, dynamic library, wchar, gcc >= 5
+#
+# BR2_PACKAGE_LINUX_ZIGBEE is not set
+# BR2_PACKAGE_LINUXPTP is not set
+# BR2_PACKAGE_LLDPD is not set
+# BR2_PACKAGE_LRZSZ is not set
+# BR2_PACKAGE_LYNX is not set
+# BR2_PACKAGE_MACCHANGER is not set
+# BR2_PACKAGE_MEMCACHED is not set
+# BR2_PACKAGE_MII_DIAG is not set
+# BR2_PACKAGE_MINI_SNMPD is not set
+# BR2_PACKAGE_MINIDLNA is not set
+# BR2_PACKAGE_MINISSDPD is not set
+# BR2_PACKAGE_MJPG_STREAMER is not set
+# BR2_PACKAGE_MODEM_MANAGER is not set
+BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y
+
+#
+# mongrel2 needs a uClibc or glibc toolchain w/ C++, threads, dynamic library
+#
+
+#
+# mosh needs a toolchain w/ C++, threads, dynamic library, wchar, gcc >= 4.8
+#
+# BR2_PACKAGE_MOSQUITTO is not set
+# BR2_PACKAGE_MROUTED is not set
+# BR2_PACKAGE_MRP is not set
+# BR2_PACKAGE_MTR is not set
+# BR2_PACKAGE_NBD is not set
+# BR2_PACKAGE_NCFTP is not set
+# BR2_PACKAGE_NDISC6 is not set
+# BR2_PACKAGE_NETATALK is not set
+# BR2_PACKAGE_NETCALC is not set
+# BR2_PACKAGE_NETPLUG is not set
+# BR2_PACKAGE_NETSNMP is not set
+# BR2_PACKAGE_NETSTAT_NAT is not set
+
+#
+# NetworkManager needs udev /dev management and a glibc toolchain w/ headers >= 3.2, dynamic library, wchar, threads
+#
+# BR2_PACKAGE_NFACCT is not set
+# BR2_PACKAGE_NFTABLES is not set
+# BR2_PACKAGE_NGINX is not set
+# BR2_PACKAGE_NGIRCD is not set
+# BR2_PACKAGE_NGREP is not set
+
+#
+# nload needs a toolchain w/ C++
+#
+
+#
+# nmap-nmap needs a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_NOIP is not set
+# BR2_PACKAGE_NTP is not set
+# BR2_PACKAGE_NUTTCP is not set
+# BR2_PACKAGE_ODHCP6C is not set
+# BR2_PACKAGE_ODHCPLOC is not set
+# BR2_PACKAGE_OLSR is not set
+# BR2_PACKAGE_OPEN_LLDP is not set
+# BR2_PACKAGE_OPEN_PLC_UTILS is not set
+# BR2_PACKAGE_OPENNTPD is not set
+# BR2_PACKAGE_OPENOBEX is not set
+# BR2_PACKAGE_OPENRESOLV is not set
+# BR2_PACKAGE_OPENSSH is not set
+# BR2_PACKAGE_OPENSWAN is not set
+# BR2_PACKAGE_OPENVPN is not set
+# BR2_PACKAGE_P910ND is not set
+# BR2_PACKAGE_PARPROUTED is not set
+# BR2_PACKAGE_PHIDGETWEBSERVICE is not set
+# BR2_PACKAGE_PHYTOOL is not set
+# BR2_PACKAGE_PIMD is not set
+# BR2_PACKAGE_PIXIEWPS is not set
+# BR2_PACKAGE_POUND is not set
+# BR2_PACKAGE_PPPD is not set
+# BR2_PACKAGE_PPTP_LINUX is not set
+# BR2_PACKAGE_PRIVOXY is not set
+# BR2_PACKAGE_PROFTPD is not set
+
+#
+# prosody needs the lua interpreter, dynamic library
+#
+# BR2_PACKAGE_PROXYCHAINS_NG is not set
+# BR2_PACKAGE_PTPD is not set
+# BR2_PACKAGE_PTPD2 is not set
+# BR2_PACKAGE_PURE_FTPD is not set
+# BR2_PACKAGE_PUTTY is not set
+# BR2_PACKAGE_QUAGGA is not set
+
+#
+# rabbitmq-server needs erlang
+#
+# BR2_PACKAGE_RADVD is not set
+# BR2_PACKAGE_REAVER is not set
+# BR2_PACKAGE_REDIR is not set
+# BR2_PACKAGE_RP_PPPOE is not set
+# BR2_PACKAGE_RPCBIND is not set
+# BR2_PACKAGE_RSH_REDONE is not set
+# BR2_PACKAGE_RSYNC is not set
+
+#
+# rtorrent needs a toolchain w/ C++, threads, wchar, gcc >= 4.9
+#
+# BR2_PACKAGE_RTPTOOLS is not set
+# BR2_PACKAGE_RYGEL is not set
+# BR2_PACKAGE_S6_DNS is not set
+# BR2_PACKAGE_S6_NETWORKING is not set
+# BR2_PACKAGE_SAMBA4 is not set
+
+#
+# sconeserver needs a toolchain with dynamic library, C++, NPTL
+#
+# BR2_PACKAGE_SER2NET is not set
+# BR2_PACKAGE_SHADOWSOCKS_LIBEV is not set
+
+#
+# shairport-sync needs a toolchain w/ C++, NPTL
+#
+# BR2_PACKAGE_SHELLINABOX is not set
+# BR2_PACKAGE_SMCROUTE is not set
+# BR2_PACKAGE_SNGREP is not set
+# BR2_PACKAGE_SNORT is not set
+# BR2_PACKAGE_SOCAT is not set
+# BR2_PACKAGE_SOCKETCAND is not set
+# BR2_PACKAGE_SOFTETHER is not set
+# BR2_PACKAGE_SPAWN_FCGI is not set
+# BR2_PACKAGE_SPICE_PROTOCOL is not set
+
+#
+# squid needs a toolchain w/ C++, gcc >= 4.8 not affected by bug 64735
+#
+# BR2_PACKAGE_SSDP_RESPONDER is not set
+# BR2_PACKAGE_SSHGUARD is not set
+# BR2_PACKAGE_SSHPASS is not set
+# BR2_PACKAGE_SSLH is not set
+# BR2_PACKAGE_STRONGSWAN is not set
+# BR2_PACKAGE_STUNNEL is not set
+# BR2_PACKAGE_TCPDUMP is not set
+# BR2_PACKAGE_TCPING is not set
+# BR2_PACKAGE_TCPREPLAY is not set
+# BR2_PACKAGE_THTTPD is not set
+# BR2_PACKAGE_TINC is not set
+# BR2_PACKAGE_TINYPROXY is not set
+# BR2_PACKAGE_TINYSSH is not set
+# BR2_PACKAGE_TOR is not set
+# BR2_PACKAGE_TRACEROUTE is not set
+# BR2_PACKAGE_TRANSMISSION is not set
+# BR2_PACKAGE_TUNCTL is not set
+# BR2_PACKAGE_TVHEADEND is not set
+# BR2_PACKAGE_UACME is not set
+# BR2_PACKAGE_UDPCAST is not set
+# BR2_PACKAGE_UFTP is not set
+# BR2_PACKAGE_UHTTPD is not set
+# BR2_PACKAGE_ULOGD is not set
+# BR2_PACKAGE_UNBOUND is not set
+# BR2_PACKAGE_UREDIR is not set
+# BR2_PACKAGE_USHARE is not set
+# BR2_PACKAGE_USSP_PUSH is not set
+# BR2_PACKAGE_VDE2 is not set
+
+#
+# vdr needs a glibc toolchain w/ C++, dynamic library, NPTL, wchar, headers >= 3.9
+#
+# BR2_PACKAGE_VNSTAT is not set
+# BR2_PACKAGE_VPNC is not set
+# BR2_PACKAGE_VSFTPD is not set
+# BR2_PACKAGE_VTUN is not set
+# BR2_PACKAGE_WAVEMON is not set
+# BR2_PACKAGE_WIREGUARD_TOOLS is not set
+# BR2_PACKAGE_WIRELESS_REGDB is not set
+# BR2_PACKAGE_WIRELESS_TOOLS is not set
+# BR2_PACKAGE_WIRESHARK is not set
+# BR2_PACKAGE_WPA_SUPPLICANT is not set
+# BR2_PACKAGE_WPAN_TOOLS is not set
+# BR2_PACKAGE_XINETD is not set
+# BR2_PACKAGE_XL2TP is not set
+# BR2_PACKAGE_XTABLES_ADDONS is not set
+
+#
+# znc needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads
+#
+
+#
+# Package managers
+#
+
+#
+# -------------------------------------------------------
+#
+
+#
+# Please note:                                           
+#
+
+#
+# - Buildroot does *not* generate binary packages,       
+#
+
+#
+# - Buildroot does *not* install any package database.   
+#
+
+#
+# *                                                      
+#
+
+#
+# It is up to you to provide those by yourself if you    
+#
+
+#
+# want to use any of those package managers.             
+#
+
+#
+# *                                                      
+#
+
+#
+# See the manual:                                        
+#
+
+#
+# http://buildroot.org/manual.html#faq-no-binary-packages
+#
+
+#
+# -------------------------------------------------------
+#
+# BR2_PACKAGE_OPKG is not set
+# BR2_PACKAGE_OPKG_UTILS is not set
+
+#
+# Real-Time
+#
+# BR2_PACKAGE_XENOMAI is not set
+
+#
+# Security
+#
+
+#
+# apparmor needs a toolchain w/ headers >= 3.16, threads, C++
+#
+# BR2_PACKAGE_CHECKPOLICY is not set
+# BR2_PACKAGE_IMA_EVM_UTILS is not set
+# BR2_PACKAGE_OPTEE_BENCHMARK is not set
+# BR2_PACKAGE_OPTEE_CLIENT is not set
+# BR2_PACKAGE_PAXTEST is not set
+# BR2_PACKAGE_REFPOLICY is not set
+# BR2_PACKAGE_RESTORECOND is not set
+# BR2_PACKAGE_SELINUX_PYTHON is not set
+# BR2_PACKAGE_SEMODULE_UTILS is not set
+
+#
+# setools needs python3
+#
+# BR2_PACKAGE_URANDOM_SCRIPTS is not set
+
+#
+# Shell and utilities
+#
+
+#
+# Shells
+#
+# BR2_PACKAGE_MKSH is not set
+# BR2_PACKAGE_ZSH is not set
+
+#
+# Utilities
+#
+# BR2_PACKAGE_AT is not set
+# BR2_PACKAGE_CCRYPT is not set
+# BR2_PACKAGE_DIALOG is not set
+# BR2_PACKAGE_DTACH is not set
+# BR2_PACKAGE_EASY_RSA is not set
+# BR2_PACKAGE_FILE is not set
+# BR2_PACKAGE_GNUPG is not set
+# BR2_PACKAGE_GNUPG2 is not set
+# BR2_PACKAGE_INOTIFY_TOOLS is not set
+# BR2_PACKAGE_LOCKFILE_PROGS is not set
+# BR2_PACKAGE_LOGROTATE is not set
+# BR2_PACKAGE_LOGSURFER is not set
+# BR2_PACKAGE_PDMENU is not set
+# BR2_PACKAGE_PINENTRY is not set
+# BR2_PACKAGE_QPRINT is not set
+# BR2_PACKAGE_RANGER is not set
+# BR2_PACKAGE_RTTY is not set
+# BR2_PACKAGE_SCREEN is not set
+# BR2_PACKAGE_SUDO is not set
+# BR2_PACKAGE_TINI is not set
+# BR2_PACKAGE_TMUX is not set
+# BR2_PACKAGE_TTYD is not set
+# BR2_PACKAGE_XMLSTARLET is not set
+# BR2_PACKAGE_XXHASH is not set
+# BR2_PACKAGE_YTREE is not set
+
+#
+# System tools
+#
+# BR2_PACKAGE_ACL is not set
+# BR2_PACKAGE_ANDROID_TOOLS is not set
+# BR2_PACKAGE_ATOP is not set
+# BR2_PACKAGE_ATTR is not set
+# BR2_PACKAGE_BUBBLEWRAP is not set
+# BR2_PACKAGE_CGROUPFS_MOUNT is not set
+
+#
+# circus needs Python 3 and a toolchain w/ C++, threads
+#
+# BR2_PACKAGE_CPULOAD is not set
+# BR2_PACKAGE_DAEMON is not set
+# BR2_PACKAGE_DC3DD is not set
+
+#
+# ddrescue needs a toolchain w/ C++
+#
+
+#
+# docker-compose needs a toolchain w/ C++, wchar, threads, dynamic library
+#
+# BR2_PACKAGE_EARLYOOM is not set
+# BR2_PACKAGE_EMLOG is not set
+# BR2_PACKAGE_FTOP is not set
+# BR2_PACKAGE_GETENT is not set
+# BR2_PACKAGE_GKRELLM is not set
+# BR2_PACKAGE_HTOP is not set
+# BR2_PACKAGE_IBM_SW_TPM2 is not set
+BR2_PACKAGE_INITSCRIPTS=y
+
+#
+# iotop depends on python or python3
+#
+# BR2_PACKAGE_IPRUTILS is not set
+# BR2_PACKAGE_IRQBALANCE is not set
+# BR2_PACKAGE_KEYUTILS is not set
+# BR2_PACKAGE_KMOD is not set
+# BR2_PACKAGE_LIBOSTREE is not set
+# BR2_PACKAGE_LXC is not set
+# BR2_PACKAGE_MFOC is not set
+# BR2_PACKAGE_MONIT is not set
+
+#
+# multipath-tools needs udev and a uClibc or glibc toolchain w/ threads, dynamic library
+#
+# BR2_PACKAGE_NCDU is not set
+
+#
+# netifrc needs openrc as init system
+#
+# BR2_PACKAGE_NUMACTL is not set
+
+#
+# nut needs a toolchain w/ C++
+#
+
+#
+# pamtester depends on linux-pam
+#
+
+#
+# polkit needs a glibc or musl toolchain with C++, wchar, dynamic library, NPTL, gcc >= 4.9
+#
+# BR2_PACKAGE_PROCRANK_LINUX is not set
+# BR2_PACKAGE_PWGEN is not set
+# BR2_PACKAGE_QUOTA is not set
+# BR2_PACKAGE_QUOTATOOL is not set
+# BR2_PACKAGE_RAUC is not set
+# BR2_PACKAGE_S6 is not set
+# BR2_PACKAGE_S6_LINUX_INIT is not set
+# BR2_PACKAGE_S6_LINUX_UTILS is not set
+# BR2_PACKAGE_S6_PORTABLE_UTILS is not set
+# BR2_PACKAGE_S6_RC is not set
+# BR2_PACKAGE_SCRUB is not set
+# BR2_PACKAGE_SCRYPT is not set
+
+#
+# sdbusplus needs systemd and a toolchain w/ C++, gcc >= 7
+#
+# BR2_PACKAGE_SMACK is not set
+
+#
+# supervisor needs a python interpreter
+#
+# BR2_PACKAGE_SWUPDATE is not set
+BR2_PACKAGE_SYSTEMD_ARCH_SUPPORTS=y
+# BR2_PACKAGE_TPM_TOOLS is not set
+# BR2_PACKAGE_TPM2_ABRMD is not set
+# BR2_PACKAGE_TPM2_TOOLS is not set
+# BR2_PACKAGE_TPM2_TOTP is not set
+# BR2_PACKAGE_UNSCD is not set
+# BR2_PACKAGE_UTIL_LINUX is not set
+# BR2_PACKAGE_WATCHDOG is not set
+# BR2_PACKAGE_XDG_DBUS_PROXY is not set
+
+#
+# Text editors and viewers
+#
+# BR2_PACKAGE_ED is not set
+# BR2_PACKAGE_JOE is not set
+# BR2_PACKAGE_MC is not set
+# BR2_PACKAGE_MG is not set
+# BR2_PACKAGE_MOST is not set
+# BR2_PACKAGE_NANO is not set
+# BR2_PACKAGE_UEMACS is not set
+
+#
+# Filesystem images
+#
+# BR2_TARGET_ROOTFS_AXFS is not set
+# BR2_TARGET_ROOTFS_BTRFS is not set
+# BR2_TARGET_ROOTFS_CLOOP is not set
+BR2_TARGET_ROOTFS_CPIO=y
+BR2_TARGET_ROOTFS_CPIO_NONE=y
+# BR2_TARGET_ROOTFS_CPIO_GZIP is not set
+# BR2_TARGET_ROOTFS_CPIO_BZIP2 is not set
+# BR2_TARGET_ROOTFS_CPIO_LZ4 is not set
+# BR2_TARGET_ROOTFS_CPIO_LZMA is not set
+# BR2_TARGET_ROOTFS_CPIO_LZO is not set
+# BR2_TARGET_ROOTFS_CPIO_XZ is not set
+# BR2_TARGET_ROOTFS_CPIO_ZSTD is not set
+# BR2_TARGET_ROOTFS_CPIO_UIMAGE is not set
+# BR2_TARGET_ROOTFS_CRAMFS is not set
+# BR2_TARGET_ROOTFS_EROFS is not set
+# BR2_TARGET_ROOTFS_EXT2 is not set
+# BR2_TARGET_ROOTFS_F2FS is not set
+BR2_TARGET_ROOTFS_INITRAMFS=y
+# BR2_TARGET_ROOTFS_JFFS2 is not set
+# BR2_TARGET_ROOTFS_ROMFS is not set
+# BR2_TARGET_ROOTFS_SQUASHFS is not set
+# BR2_TARGET_ROOTFS_TAR is not set
+# BR2_TARGET_ROOTFS_UBI is not set
+# BR2_TARGET_ROOTFS_UBIFS is not set
+# BR2_TARGET_ROOTFS_YAFFS2 is not set
+
+#
+# Bootloaders
+#
+# BR2_TARGET_BAREBOX is not set
+# BR2_TARGET_BEAGLEV_DDRINIT is not set
+# BR2_TARGET_BEAGLEV_SECONDBOOT is not set
+BR2_TARGET_OPENSBI=y
+BR2_TARGET_OPENSBI_LATEST_VERSION=y
+# BR2_TARGET_OPENSBI_CUSTOM_VERSION is not set
+# BR2_TARGET_OPENSBI_CUSTOM_TARBALL is not set
+# BR2_TARGET_OPENSBI_CUSTOM_GIT is not set
+BR2_TARGET_OPENSBI_VERSION="0.9"
+BR2_TARGET_OPENSBI_PLAT="generic"
+BR2_TARGET_OPENSBI_INSTALL_DYNAMIC_IMG=y
+BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG=y
+# BR2_TARGET_OPENSBI_INSTALL_PAYLOAD_IMG is not set
+# BR2_TARGET_OPENSBI_LINUX_PAYLOAD is not set
+# BR2_TARGET_UBOOT is not set
+
+#
+# Host utilities
+#
+# BR2_PACKAGE_HOST_ABOOTIMG is not set
+# BR2_PACKAGE_HOST_AESPIPE is not set
+# BR2_PACKAGE_HOST_ANDROID_TOOLS is not set
+# BR2_PACKAGE_HOST_ASN1C is not set
+# BR2_PACKAGE_HOST_BABELTRACE2 is not set
+# BR2_PACKAGE_HOST_BTRFS_PROGS is not set
+# BR2_PACKAGE_HOST_CHECKPOLICY is not set
+# BR2_PACKAGE_HOST_CHECKSEC is not set
+# BR2_PACKAGE_HOST_CMAKE is not set
+# BR2_PACKAGE_HOST_CRAMFS is not set
+# BR2_PACKAGE_HOST_CRYPTSETUP is not set
+# BR2_PACKAGE_HOST_DBUS_PYTHON is not set
+# BR2_PACKAGE_HOST_DFU_UTIL is not set
+# BR2_PACKAGE_HOST_DOS2UNIX is not set
+# BR2_PACKAGE_HOST_DOSFSTOOLS is not set
+# BR2_PACKAGE_HOST_DOXYGEN is not set
+# BR2_PACKAGE_HOST_DTC is not set
+BR2_PACKAGE_HOST_E2FSPROGS=y
+# BR2_PACKAGE_HOST_E2TOOLS is not set
+# BR2_PACKAGE_HOST_ENVIRONMENT_SETUP is not set
+# BR2_PACKAGE_HOST_EROFS_UTILS is not set
+# BR2_PACKAGE_HOST_EXFATPROGS is not set
+# BR2_PACKAGE_HOST_F2FS_TOOLS is not set
+# BR2_PACKAGE_HOST_FAKETIME is not set
+# BR2_PACKAGE_HOST_FATCAT is not set
+# BR2_PACKAGE_HOST_FWUP is not set
+# BR2_PACKAGE_HOST_GENEXT2FS is not set
+# BR2_PACKAGE_HOST_GENIMAGE is not set
+# BR2_PACKAGE_HOST_GENPART is not set
+# BR2_PACKAGE_HOST_GNUPG is not set
+BR2_PACKAGE_HOST_GO_HOST_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_GO_BOOTSTRAP_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y
+# BR2_PACKAGE_HOST_GPTFDISK is not set
+# BR2_PACKAGE_HOST_IMAGEMAGICK is not set
+# BR2_PACKAGE_HOST_IMX_MKIMAGE is not set
+# BR2_PACKAGE_HOST_JH71XX_TOOLS is not set
+# BR2_PACKAGE_HOST_JQ is not set
+# BR2_PACKAGE_HOST_JSMIN is not set
+BR2_PACKAGE_HOST_KMOD=y
+# BR2_PACKAGE_HOST_KMOD_GZ is not set
+# BR2_PACKAGE_HOST_KMOD_ZSTD is not set
+# BR2_PACKAGE_HOST_KMOD_XZ is not set
+# BR2_PACKAGE_HOST_LIBP11 is not set
+# BR2_PACKAGE_HOST_LPC3250LOADER is not set
+# BR2_PACKAGE_HOST_LTTNG_BABELTRACE is not set
+# BR2_PACKAGE_HOST_MENDER_ARTIFACT is not set
+# BR2_PACKAGE_HOST_MESON_TOOLS is not set
+# BR2_PACKAGE_HOST_MKPASSWD is not set
+# BR2_PACKAGE_HOST_MTD is not set
+# BR2_PACKAGE_HOST_MTOOLS is not set
+# BR2_PACKAGE_HOST_ODB is not set
+# BR2_PACKAGE_HOST_OPENOCD is not set
+# BR2_PACKAGE_HOST_OPKG_UTILS is not set
+# BR2_PACKAGE_HOST_PARTED is not set
+BR2_PACKAGE_HOST_PATCHELF=y
+# BR2_PACKAGE_HOST_PIGZ is not set
+# BR2_PACKAGE_HOST_PKGCONF is not set
+# BR2_PACKAGE_HOST_PWGEN is not set
+# BR2_PACKAGE_HOST_PYTHON is not set
+# BR2_PACKAGE_HOST_PYTHON_CYTHON is not set
+# BR2_PACKAGE_HOST_PYTHON_LXML is not set
+# BR2_PACKAGE_HOST_PYTHON_SIX is not set
+# BR2_PACKAGE_HOST_PYTHON_XLRD is not set
+# BR2_PACKAGE_HOST_PYTHON3 is not set
+BR2_PACKAGE_HOST_QEMU_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_QEMU_SYSTEM_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_QEMU_USER_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_QEMU=y
+
+#
+# Emulators selection
+#
+BR2_PACKAGE_HOST_QEMU_SYSTEM_MODE=y
+# BR2_PACKAGE_HOST_QEMU_LINUX_USER_MODE is not set
+# BR2_PACKAGE_HOST_QEMU_VDE2 is not set
+# BR2_PACKAGE_HOST_QEMU_VIRTFS is not set
+# BR2_PACKAGE_HOST_QEMU_USB is not set
+# BR2_PACKAGE_HOST_QORIQ_RCW is not set
+# BR2_PACKAGE_HOST_RAUC is not set
+BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y
+BR2_PACKAGE_HOST_RUSTC_ARCH="riscv64"
+# BR2_PACKAGE_HOST_RUSTC is not set
+BR2_PACKAGE_PROVIDES_HOST_RUSTC="host-rust-bin"
+# BR2_PACKAGE_HOST_SAM_BA is not set
+# BR2_PACKAGE_HOST_SDBUSPLUS is not set
+# BR2_PACKAGE_HOST_SENTRY_CLI is not set
+# BR2_PACKAGE_HOST_SQUASHFS is not set
+# BR2_PACKAGE_HOST_SWIG is not set
+# BR2_PACKAGE_HOST_UBOOT_TOOLS is not set
+BR2_PACKAGE_HOST_UTIL_LINUX=y
+# BR2_PACKAGE_HOST_UTP_COM is not set
+# BR2_PACKAGE_HOST_VBOOT_UTILS is not set
+# BR2_PACKAGE_HOST_XORRISO is not set
+# BR2_PACKAGE_HOST_ZIP is not set
+# BR2_PACKAGE_HOST_ZSTD is not set
+
+#
+# Legacy config options
+#
+
+#
+# Legacy options removed in 2021.05
+#
+# BR2_PACKAGE_UDISKS_LVM2 is not set
+# BR2_PACKAGE_LVM2_APP_LIBRARY is not set
+# BR2_PACKAGE_LVM2_LVMETAD is not set
+# BR2_PACKAGE_MONKEY is not set
+# BR2_PACKAGE_DOCKER_CONTAINERD is not set
+# BR2_PACKAGE_IOSTAT is not set
+# BR2_PACKAGE_SCONESERVER_HTTP_SCONESITE_IMAGE is not set
+# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_EVDEV is not set
+# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_KBD is not set
+# BR2_PACKAGE_XSERVER_XORG_SERVER_KDRIVE_MOUSE is not set
+# BR2_PACKAGE_MESA3D_OSMESA_CLASSIC is not set
+# BR2_PACKAGE_MESA3D_DRI_DRIVER_SWRAST is not set
+# BR2_PACKAGE_KODI_SCREENSAVER_CRYSTALMORPH is not set
+
+#
+# Legacy options removed in 2021.02
+#
+# BR2_PACKAGE_MPD_AUDIOFILE is not set
+# BR2_PACKAGE_AUDIOFILE is not set
+# BR2_BINUTILS_VERSION_2_33_X is not set
+# BR2_PACKAGE_LIBUPNP18 is not set
+# BR2_PACKAGE_BOA is not set
+# BR2_PACKAGE_LINUX_FIRMWARE_IMX_SDMA is not set
+# BR2_GDB_VERSION_8_2 is not set
+# BR2_PACKAGE_HOST_RCW is not set
+# BR2_KERNEL_HEADERS_5_9 is not set
+# BR2_KERNEL_HEADERS_5_8 is not set
+# BR2_powerpc_601 is not set
+# BR2_PACKAGE_TI_SGX_LIBGBM is not set
+# BR2_PACKAGE_IPSEC_TOOLS is not set
+
+#
+# Legacy options removed in 2020.11
+#
+# BR2_PACKAGE_OPENCV is not set
+# BR2_PACKAGE_LIBCROCO is not set
+# BR2_PACKAGE_BELLAGIO is not set
+# BR2_PACKAGE_SYSTEMD_JOURNAL_GATEWAY is not set
+# BR2_TARGET_UBOOT_BOOT_SCRIPT is not set
+# BR2_TARGET_UBOOT_ENVIMAGE is not set
+# BR2_PACKAGE_KISMET_CLIENT is not set
+# BR2_PACKAGE_KISMET_DRONE is not set
+# BR2_GCC_VERSION_7_X is not set
+# BR2_PACKAGE_GST1_VALIDATE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_YADIF is not set
+# BR2_PACKAGE_GQVIEW is not set
+# BR2_PACKAGE_WESTON_IMX is not set
+# BR2_KERNEL_HEADERS_5_7 is not set
+# BR2_PACKAGE_TINYHTTPD is not set
+# BR2_PACKAGE_XSERVER_XORG_SERVER_AIGLX is not set
+# BR2_PACKAGE_AMD_CATALYST is not set
+# BR2_PACKAGE_NVIDIA_TEGRA23 is not set
+# BR2_GDB_VERSION_8_1 is not set
+
+#
+# Legacy options removed in 2020.08
+#
+# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_AMD64 is not set
+# BR2_KERNEL_HEADERS_5_6 is not set
+# BR2_KERNEL_HEADERS_5_5 is not set
+# BR2_BINUTILS_VERSION_2_31_X is not set
+# BR2_PACKAGE_KODI_PERIPHERAL_STEAMCONTROLLER is not set
+
+#
+# Legacy options removed in 2020.05
+#
+# BR2_PACKAGE_WIRINGPI is not set
+# BR2_PACKAGE_PYTHON_PYCRYPTO is not set
+# BR2_PACKAGE_MTDEV2TUIO is not set
+# BR2_PACKAGE_EZXML is not set
+# BR2_PACKAGE_COLLECTD_LVM is not set
+# BR2_PACKAGE_PYTHON_PYASN is not set
+# BR2_PACKAGE_PYTHON_PYASN_MODULES is not set
+# BR2_PACKAGE_LINUX_FIRMWARE_ATHEROS_10K_QCA6174 is not set
+# BR2_PACKAGE_QT5CANVAS3D is not set
+# BR2_PACKAGE_KODI_LIBTHEORA is not set
+# BR2_PACKAGE_CEGUI06 is not set
+# BR2_GCC_VERSION_5_X is not set
+
+#
+# Legacy options removed in 2020.02
+#
+# BR2_PACKAGE_JAMVM is not set
+# BR2_PACKAGE_CLASSPATH is not set
+# BR2_PACKAGE_QT5_VERSION_5_6 is not set
+# BR2_PACKAGE_CURL is not set
+# BR2_PACKAGE_GSTREAMER is not set
+# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_GSTREAMER_PLUGINS is not set
+# BR2_PACKAGE_NVIDIA_TEGRA23_BINARIES_NV_SAMPLE_APPS is not set
+# BR2_PACKAGE_FREERDP_GSTREAMER is not set
+# BR2_PACKAGE_OPENCV3_WITH_GSTREAMER is not set
+# BR2_PACKAGE_OPENCV_WITH_GSTREAMER is not set
+# BR2_PACKAGE_LIBPLAYER is not set
+# BR2_GCC_VERSION_OR1K is not set
+# BR2_PACKAGE_BLUEZ_UTILS is not set
+# BR2_PACKAGE_GADGETFS_TEST is not set
+# BR2_PACKAGE_FIS is not set
+BR2_PACKAGE_REFPOLICY_POLICY_VERSION=""
+# BR2_PACKAGE_CELT051 is not set
+# BR2_PACKAGE_WIREGUARD is not set
+# BR2_PACKAGE_PERL_NET_PING is not set
+# BR2_PACKAGE_PERL_MIME_BASE64 is not set
+# BR2_PACKAGE_PERL_DIGEST_MD5 is not set
+# BR2_PACKAGE_ERLANG_P1_ICONV is not set
+# BR2_KERNEL_HEADERS_5_3 is not set
+# BR2_PACKAGE_PYTHON_SCAPY3K is not set
+# BR2_BINUTILS_VERSION_2_30_X is not set
+# BR2_PACKAGE_RPI_USERLAND_START_VCFILED is not set
+
+#
+# Legacy options removed in 2019.11
+#
+# BR2_PACKAGE_OPENVMTOOLS_PROCPS is not set
+# BR2_PACKAGE_ALLJOYN is not set
+# BR2_PACKAGE_ALLJOYN_BASE is not set
+# BR2_PACKAGE_ALLJOYN_BASE_CONTROLPANEL is not set
+# BR2_PACKAGE_ALLJOYN_BASE_NOTIFICATION is not set
+# BR2_PACKAGE_ALLJOYN_BASE_ONBOARDING is not set
+# BR2_PACKAGE_ALLJOYN_TCL_BASE is not set
+# BR2_PACKAGE_ALLJOYN_TCL is not set
+BR2_TOOLCHAIN_EXTRA_EXTERNAL_LIBS=""
+# BR2_PACKAGE_PYTHON_PYSNMP_APPS is not set
+# BR2_KERNEL_HEADERS_5_2 is not set
+# BR2_TARGET_RISCV_PK is not set
+# BR2_PACKAGE_SQLITE_STAT3 is not set
+# BR2_KERNEL_HEADERS_5_1 is not set
+# BR2_PACKAGE_DEVMEM2 is not set
+# BR2_PACKAGE_USTR is not set
+# BR2_PACKAGE_KODI_SCREENSAVER_PLANESTATE is not set
+# BR2_PACKAGE_KODI_VISUALISATION_WAVEFORHUE is not set
+# BR2_PACKAGE_KODI_AUDIODECODER_OPUS is not set
+# BR2_PACKAGE_MESA3D_OSMESA is not set
+# BR2_PACKAGE_HOSTAPD_DRIVER_RTW is not set
+# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_NEW is not set
+# BR2_PACKAGE_WPA_SUPPLICANT_DBUS_OLD is not set
+
+#
+# Legacy options removed in 2019.08
+#
+# BR2_TARGET_TS4800_MBRBOOT is not set
+# BR2_PACKAGE_LIBAMCODEC is not set
+# BR2_PACKAGE_ODROID_SCRIPTS is not set
+# BR2_PACKAGE_ODROID_MALI is not set
+# BR2_PACKAGE_KODI_PLATFORM_AML is not set
+# BR2_GCC_VERSION_6_X is not set
+# BR2_GCC_VERSION_4_9_X is not set
+# BR2_GDB_VERSION_7_12 is not set
+# BR2_PACKAGE_XAPP_MKFONTDIR is not set
+# BR2_GDB_VERSION_8_0 is not set
+# BR2_KERNEL_HEADERS_4_20 is not set
+# BR2_KERNEL_HEADERS_5_0 is not set
+
+#
+# Legacy options removed in 2019.05
+#
+# BR2_CSKY_DSP is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_COMPOSITOR is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_IQA is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_OPENCV is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_STEREO is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VCD is not set
+# BR2_PACKAGE_LUNIT is not set
+# BR2_PACKAGE_FFMPEG_FFSERVER is not set
+# BR2_PACKAGE_LIBUMP is not set
+# BR2_PACKAGE_SUNXI_MALI is not set
+# BR2_BINUTILS_VERSION_2_29_X is not set
+# BR2_BINUTILS_VERSION_2_28_X is not set
+# BR2_PACKAGE_GST_PLUGINS_BAD_PLUGIN_APEXSINK is not set
+
+#
+# Legacy options removed in 2019.02
+#
+# BR2_PACKAGE_QT is not set
+# BR2_PACKAGE_QTUIO is not set
+# BR2_PACKAGE_PINENTRY_QT4 is not set
+# BR2_PACKAGE_POPPLER_QT is not set
+# BR2_PACKAGE_OPENCV3_WITH_QT is not set
+# BR2_PACKAGE_OPENCV_WITH_QT is not set
+# BR2_PACKAGE_AMD_CATALYST_CCCLE is not set
+# BR2_PACKAGE_SDL_QTOPIA is not set
+# BR2_PACKAGE_PYTHON_PYQT is not set
+# BR2_PACKAGE_LUACRYPTO is not set
+# BR2_PACKAGE_TN5250 is not set
+# BR2_PACKAGE_BOOST_SIGNALS is not set
+# BR2_PACKAGE_FFTW_PRECISION_SINGLE is not set
+# BR2_PACKAGE_FFTW_PRECISION_DOUBLE is not set
+# BR2_PACKAGE_FFTW_PRECISION_LONG_DOUBLE is not set
+# BR2_PACKAGE_LUA_5_2 is not set
+# BR2_TARGET_GENERIC_PASSWD_MD5 is not set
+
+#
+# Legacy options removed in 2018.11
+#
+# BR2_TARGET_XLOADER is not set
+# BR2_PACKAGE_TIDSP_BINARIES is not set
+# BR2_PACKAGE_DSP_TOOLS is not set
+# BR2_PACKAGE_GST_DSP is not set
+# BR2_PACKAGE_BOOTUTILS is not set
+# BR2_PACKAGE_EXPEDITE is not set
+# BR2_PACKAGE_MESA3D_OPENGL_TEXTURE_FLOAT is not set
+# BR2_KERNEL_HEADERS_4_10 is not set
+# BR2_KERNEL_HEADERS_4_11 is not set
+# BR2_KERNEL_HEADERS_4_12 is not set
+# BR2_KERNEL_HEADERS_4_13 is not set
+# BR2_KERNEL_HEADERS_4_15 is not set
+# BR2_KERNEL_HEADERS_4_17 is not set
+# BR2_PACKAGE_LIBNFTNL_XML is not set
+# BR2_KERNEL_HEADERS_3_2 is not set
+# BR2_KERNEL_HEADERS_4_1 is not set
+# BR2_KERNEL_HEADERS_4_16 is not set
+# BR2_KERNEL_HEADERS_4_18 is not set
+
+#
+# Legacy options removed in 2018.08
+#
+# BR2_PACKAGE_DOCKER_ENGINE_STATIC_CLIENT is not set
+# BR2_PACKAGE_XPROTO_APPLEWMPROTO is not set
+# BR2_PACKAGE_XPROTO_BIGREQSPROTO is not set
+# BR2_PACKAGE_XPROTO_COMPOSITEPROTO is not set
+# BR2_PACKAGE_XPROTO_DAMAGEPROTO is not set
+# BR2_PACKAGE_XPROTO_DMXPROTO is not set
+# BR2_PACKAGE_XPROTO_DRI2PROTO is not set
+# BR2_PACKAGE_XPROTO_DRI3PROTO is not set
+# BR2_PACKAGE_XPROTO_FIXESPROTO is not set
+# BR2_PACKAGE_XPROTO_FONTCACHEPROTO is not set
+# BR2_PACKAGE_XPROTO_FONTSPROTO is not set
+# BR2_PACKAGE_XPROTO_GLPROTO is not set
+# BR2_PACKAGE_XPROTO_INPUTPROTO is not set
+# BR2_PACKAGE_XPROTO_KBPROTO is not set
+# BR2_PACKAGE_XPROTO_PRESENTPROTO is not set
+# BR2_PACKAGE_XPROTO_RANDRPROTO is not set
+# BR2_PACKAGE_XPROTO_RECORDPROTO is not set
+# BR2_PACKAGE_XPROTO_RENDERPROTO is not set
+# BR2_PACKAGE_XPROTO_RESOURCEPROTO is not set
+# BR2_PACKAGE_XPROTO_SCRNSAVERPROTO is not set
+# BR2_PACKAGE_XPROTO_VIDEOPROTO is not set
+# BR2_PACKAGE_XPROTO_WINDOWSWMPROTO is not set
+# BR2_PACKAGE_XPROTO_XCMISCPROTO is not set
+# BR2_PACKAGE_XPROTO_XEXTPROTO is not set
+# BR2_PACKAGE_XPROTO_XF86BIGFONTPROTO is not set
+# BR2_PACKAGE_XPROTO_XF86DGAPROTO is not set
+# BR2_PACKAGE_XPROTO_XF86DRIPROTO is not set
+# BR2_PACKAGE_XPROTO_XF86VIDMODEPROTO is not set
+# BR2_PACKAGE_XPROTO_XINERAMAPROTO is not set
+# BR2_PACKAGE_XPROTO_XPROTO is not set
+# BR2_PACKAGE_XPROTO_XPROXYMANAGEMENTPROTOCOL is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_OPENGL is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLES2 is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLX is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_EGL is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_X11 is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_WAYLAND is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_DISPMANX is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_AUDIOMIXER is not set
+# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_LAME is not set
+# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MPG123 is not set
+# BR2_GDB_VERSION_7_11 is not set
+# BR2_GDB_VERSION_7_10 is not set
+
+#
+# Legacy options removed in 2018.05
+#
+# BR2_PACKAGE_MEDIAART_BACKEND_NONE is not set
+# BR2_PACKAGE_MEDIAART_BACKEND_GDK_PIXBUF is not set
+# BR2_PACKAGE_TI_SGX_AM335X is not set
+# BR2_PACKAGE_TI_SGX_AM437X is not set
+# BR2_PACKAGE_TI_SGX_AM4430 is not set
+# BR2_PACKAGE_TI_SGX_AM5430 is not set
+# BR2_PACKAGE_JANUS_AUDIO_BRIDGE is not set
+# BR2_PACKAGE_JANUS_ECHO_TEST is not set
+# BR2_PACKAGE_JANUS_RECORDPLAY is not set
+# BR2_PACKAGE_JANUS_SIP_GATEWAY is not set
+# BR2_PACKAGE_JANUS_STREAMING is not set
+# BR2_PACKAGE_JANUS_TEXT_ROOM is not set
+# BR2_PACKAGE_JANUS_VIDEO_CALL is not set
+# BR2_PACKAGE_JANUS_VIDEO_ROOM is not set
+# BR2_PACKAGE_JANUS_MQTT is not set
+# BR2_PACKAGE_JANUS_RABBITMQ is not set
+# BR2_PACKAGE_JANUS_REST is not set
+# BR2_PACKAGE_JANUS_UNIX_SOCKETS is not set
+# BR2_PACKAGE_JANUS_WEBSOCKETS is not set
+# BR2_PACKAGE_IPSEC_SECCTX_DISABLE is not set
+# BR2_PACKAGE_IPSEC_SECCTX_ENABLE is not set
+# BR2_PACKAGE_IPSEC_SECCTX_KERNEL is not set
+# BR2_PACKAGE_LIBTFDI_CPP is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_BLACK_TIE is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_BLITZER is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_CUPERTINO is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_DARK_HIVE is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_DOT_LUV is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_EGGPLANT is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_EXCITE_BIKE is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_FLICK is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_HOT_SNEAKS is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_HUMANITY is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_LE_FROG is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_MINT_CHOC is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_OVERCAST is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_PEPPER_GRINDER is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_REDMOND is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_SMOOTHNESS is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_SOUTH_STREET is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_START is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_SUNNY is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_SWANKY_PURSE is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_TRONTASTIC is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_UI_DARKNESS is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_UI_LIGHTNESS is not set
+# BR2_PACKAGE_JQUERY_UI_THEME_VADER is not set
+# BR2_PACKAGE_BLUEZ5_PLUGINS_HEALTH is not set
+# BR2_PACKAGE_BLUEZ5_PLUGINS_MIDI is not set
+# BR2_PACKAGE_BLUEZ5_PLUGINS_NFC is not set
+# BR2_PACKAGE_BLUEZ5_PLUGINS_SAP is not set
+# BR2_PACKAGE_BLUEZ5_PLUGINS_SIXAXIS is not set
+# BR2_PACKAGE_TRANSMISSION_REMOTE is not set
+# BR2_PACKAGE_LIBKCAPI_APPS is not set
+# BR2_PACKAGE_MPLAYER is not set
+# BR2_PACKAGE_MPLAYER_MPLAYER is not set
+# BR2_PACKAGE_MPLAYER_MENCODER is not set
+# BR2_PACKAGE_LIBPLAYER_MPLAYER is not set
+# BR2_PACKAGE_IQVLINUX is not set
+# BR2_BINFMT_FLAT_SEP_DATA is not set
+# BR2_bfin is not set
+# BR2_PACKAGE_KODI_ADSP_BASIC is not set
+# BR2_PACKAGE_KODI_ADSP_FREESURROUND is not set
+
+#
+# Legacy options removed in 2018.02
+#
+# BR2_KERNEL_HEADERS_3_4 is not set
+# BR2_KERNEL_HEADERS_3_10 is not set
+# BR2_KERNEL_HEADERS_3_12 is not set
+# BR2_BINUTILS_VERSION_2_27_X is not set
+# BR2_PACKAGE_EEPROG is not set
+# BR2_PACKAGE_GNUPG2_GPGV2 is not set
+# BR2_PACKAGE_IMX_GPU_VIV_APITRACE is not set
+# BR2_PACKAGE_IMX_GPU_VIV_G2D is not set
+
+#
+# Legacy options removed in 2017.11
+#
+# BR2_PACKAGE_RFKILL is not set
+# BR2_PACKAGE_UTIL_LINUX_RESET is not set
+# BR2_PACKAGE_POLICYCOREUTILS_AUDIT2ALLOW is not set
+# BR2_PACKAGE_POLICYCOREUTILS_RESTORECOND is not set
+# BR2_PACKAGE_SEPOLGEN is not set
+# BR2_PACKAGE_OPENOBEX_BLUEZ is not set
+# BR2_PACKAGE_OPENOBEX_LIBUSB is not set
+# BR2_PACKAGE_OPENOBEX_APPS is not set
+# BR2_PACKAGE_OPENOBEX_SYSLOG is not set
+# BR2_PACKAGE_OPENOBEX_DUMP is not set
+# BR2_PACKAGE_AICCU is not set
+# BR2_PACKAGE_UTIL_LINUX_LOGIN_UTILS is not set
+
+#
+# Legacy options removed in 2017.08
+#
+# BR2_TARGET_GRUB is not set
+# BR2_PACKAGE_SIMICSFS is not set
+# BR2_BINUTILS_VERSION_2_26_X is not set
+BR2_XTENSA_OVERLAY_DIR=""
+BR2_XTENSA_CUSTOM_NAME=""
+# BR2_PACKAGE_HOST_MKE2IMG is not set
+BR2_TARGET_ROOTFS_EXT2_BLOCKS=0
+BR2_TARGET_ROOTFS_EXT2_EXTRA_INODES=0
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_CDXAPARSE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DATAURISRC is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DCCP is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_HDVPARSE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MVE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_NUVDEMUX is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_PATCHDETECT is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDI is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_TTA is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VIDEOMEASURE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_APEXSINK is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDL is not set
+# BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MAD is not set
+# BR2_STRIP_none is not set
+# BR2_PACKAGE_BEECRYPT_CPP is not set
+# BR2_PACKAGE_SPICE_CLIENT is not set
+# BR2_PACKAGE_SPICE_GUI is not set
+# BR2_PACKAGE_SPICE_TUNNEL is not set
+# BR2_PACKAGE_INPUT_TOOLS is not set
+# BR2_PACKAGE_INPUT_TOOLS_INPUTATTACH is not set
+# BR2_PACKAGE_INPUT_TOOLS_JSCAL is not set
+# BR2_PACKAGE_INPUT_TOOLS_JSTEST is not set
+# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_SH is not set
+# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86 is not set
+# BR2_GCC_VERSION_4_8_X is not set
+
+#
+# Legacy options removed in 2017.05
+#
+# BR2_PACKAGE_SUNXI_MALI_R2P4 is not set
+# BR2_PACKAGE_NODEJS_MODULES_COFFEESCRIPT is not set
+# BR2_PACKAGE_NODEJS_MODULES_EXPRESS is not set
+# BR2_PACKAGE_BLUEZ5_UTILS_GATTTOOL is not set
+# BR2_PACKAGE_OPENOCD_FT2XXX is not set
+# BR2_PACKAGE_KODI_RTMPDUMP is not set
+# BR2_PACKAGE_KODI_VISUALISATION_FOUNTAIN is not set
+# BR2_PACKAGE_PORTMAP is not set
+# BR2_BINUTILS_VERSION_2_25_X is not set
+# BR2_TOOLCHAIN_BUILDROOT_INET_RPC is not set
+BR2_TARGET_ROOTFS_EXT2_EXTRA_BLOCKS=0
+# BR2_PACKAGE_SYSTEMD_KDBUS is not set
+# BR2_PACKAGE_POLARSSL is not set
+# BR2_NBD_CLIENT is not set
+# BR2_NBD_SERVER is not set
+# BR2_PACKAGE_GMOCK is not set
+# BR2_KERNEL_HEADERS_4_8 is not set
+# BR2_KERNEL_HEADERS_3_18 is not set
+# BR2_GLIBC_VERSION_2_22 is not set
+
+#
+# Legacy options removed in 2017.02
+#
+# BR2_PACKAGE_PERL_DB_FILE is not set
+# BR2_KERNEL_HEADERS_4_7 is not set
+# BR2_KERNEL_HEADERS_4_6 is not set
+# BR2_KERNEL_HEADERS_4_5 is not set
+# BR2_KERNEL_HEADERS_3_14 is not set
+# BR2_TOOLCHAIN_EXTERNAL_MUSL_CROSS is not set
+# BR2_UCLIBC_INSTALL_TEST_SUITE is not set
+# BR2_TOOLCHAIN_EXTERNAL_BLACKFIN_UCLINUX is not set
+# BR2_PACKAGE_MAKEDEVS is not set
+# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV7A is not set
+# BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV5TE is not set
+# BR2_PACKAGE_SNOWBALL_HDMISERVICE is not set
+# BR2_PACKAGE_SNOWBALL_INIT is not set
+# BR2_GDB_VERSION_7_9 is not set
+
+#
+# Legacy options removed in 2016.11
+#
+# BR2_PACKAGE_PHP_SAPI_CLI_CGI is not set
+# BR2_PACKAGE_PHP_SAPI_CLI_FPM is not set
+# BR2_PACKAGE_WVSTREAMS is not set
+# BR2_PACKAGE_WVDIAL is not set
+# BR2_PACKAGE_WEBKITGTK24 is not set
+# BR2_PACKAGE_TORSMO is not set
+# BR2_PACKAGE_SSTRIP is not set
+# BR2_KERNEL_HEADERS_4_3 is not set
+# BR2_KERNEL_HEADERS_4_2 is not set
+# BR2_PACKAGE_KODI_ADDON_XVDR is not set
+# BR2_PACKAGE_IPKG is not set
+# BR2_GCC_VERSION_4_7_X is not set
+# BR2_BINUTILS_VERSION_2_24_X is not set
+# BR2_PACKAGE_WESTON_RPI is not set
+# BR2_LINUX_KERNEL_TOOL_CPUPOWER is not set
+# BR2_LINUX_KERNEL_TOOL_PERF is not set
+# BR2_LINUX_KERNEL_TOOL_SELFTESTS is not set
+# BR2_GCC_VERSION_4_8_ARC is not set
+# BR2_KERNEL_HEADERS_4_0 is not set
+# BR2_KERNEL_HEADERS_3_19 is not set
+# BR2_PACKAGE_LIBEVAS_GENERIC_LOADERS is not set
+# BR2_PACKAGE_ELEMENTARY is not set
+# BR2_LINUX_KERNEL_CUSTOM_LOCAL is not set
+
+#
+# Legacy options removed in 2016.08
+#
+# BR2_PACKAGE_EFL_JP2K is not set
+# BR2_PACKAGE_SYSTEMD_COMPAT is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_LIVEADDER is not set
+# BR2_PACKAGE_LIBFSLVPUWRAP is not set
+# BR2_PACKAGE_LIBFSLPARSER is not set
+# BR2_PACKAGE_LIBFSLCODEC is not set
+# BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE_FIT_SIGNATURE_SUPPORT is not set
+# BR2_PTHREADS_OLD is not set
+# BR2_BINUTILS_VERSION_2_23_X is not set
+# BR2_TOOLCHAIN_BUILDROOT_EGLIBC is not set
+# BR2_GDB_VERSION_7_8 is not set
+
+#
+# Legacy options removed in 2016.05
+#
+# BR2_PACKAGE_OPENVPN_CRYPTO_POLARSSL is not set
+# BR2_PACKAGE_NGINX_HTTP_SPDY_MODULE is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_RTP is not set
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MPG123 is not set
+# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC is not set
+# BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC_E500V2 is not set
+# BR2_x86_i386 is not set
+# BR2_PACKAGE_QT5QUICK1 is not set
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR=""
+# BR2_PACKAGE_XDRIVER_XF86_INPUT_VOID is not set
+# BR2_KERNEL_HEADERS_3_17 is not set
+# BR2_GDB_VERSION_7_7 is not set
+# BR2_PACKAGE_FOOMATIC_FILTERS is not set
+# BR2_PACKAGE_SAMBA is not set
+# BR2_PACKAGE_KODI_WAVPACK is not set
+# BR2_PACKAGE_KODI_RSXS is not set
+# BR2_PACKAGE_KODI_GOOM is not set
+# BR2_PACKAGE_SYSTEMD_ALL_EXTRAS is not set
+# BR2_GCC_VERSION_4_5_X is not set
+# BR2_PACKAGE_SQLITE_READLINE is not set
+
+#
+# Legacy options removed in 2016.02
+#
+# BR2_PACKAGE_DOVECOT_BZIP2 is not set
+# BR2_PACKAGE_DOVECOT_ZLIB is not set
+# BR2_PACKAGE_E2FSPROGS_FINDFS is not set
+# BR2_PACKAGE_OPENPOWERLINK_DEBUG_LEVEL is not set
+# BR2_PACKAGE_OPENPOWERLINK_KERNEL_MODULE is not set
+# BR2_PACKAGE_OPENPOWERLINK_LIBPCAP is not set
+# BR2_LINUX_KERNEL_SAME_AS_HEADERS is not set
+# BR2_PACKAGE_CUPS_PDFTOPS is not set
+# BR2_KERNEL_HEADERS_3_16 is not set
+# BR2_PACKAGE_PYTHON_PYXML is not set
+# BR2_ENABLE_SSP is not set
+# BR2_PACKAGE_DIRECTFB_CLE266 is not set
+# BR2_PACKAGE_DIRECTFB_UNICHROME is not set
+# BR2_PACKAGE_LIBELEMENTARY is not set
+# BR2_PACKAGE_LIBEINA is not set
+# BR2_PACKAGE_LIBEET is not set
+# BR2_PACKAGE_LIBEVAS is not set
+# BR2_PACKAGE_LIBECORE is not set
+# BR2_PACKAGE_LIBEDBUS is not set
+# BR2_PACKAGE_LIBEFREET is not set
+# BR2_PACKAGE_LIBEIO is not set
+# BR2_PACKAGE_LIBEMBRYO is not set
+# BR2_PACKAGE_LIBEDJE is not set
+# BR2_PACKAGE_LIBETHUMB is not set
+# BR2_PACKAGE_INFOZIP is not set
+# BR2_BR2_PACKAGE_NODEJS_0_10_X is not set
+# BR2_BR2_PACKAGE_NODEJS_0_12_X is not set
+# BR2_BR2_PACKAGE_NODEJS_4_X is not set
+
+#
+# Legacy options removed in 2015.11
+#
+# BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_REAL is not set
+# BR2_PACKAGE_MEDIA_CTL is not set
+# BR2_PACKAGE_SCHIFRA is not set
+# BR2_PACKAGE_ZXING is not set
+# BR2_PACKAGE_BLACKBOX is not set
+# BR2_KERNEL_HEADERS_3_0 is not set
+# BR2_KERNEL_HEADERS_3_11 is not set
+# BR2_KERNEL_HEADERS_3_13 is not set
+# BR2_KERNEL_HEADERS_3_15 is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_ANDI is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_BLTLOAD is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_CPULOAD is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_DATABUFFER is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_DIOLOAD is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_DOK is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_DRIVERTEST is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_FIRE is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_FLIP is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_FONTS is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_INPUT is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_JOYSTICK is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_KNUCKLES is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_LAYER is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX_WATER is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_NEO is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_NETLOAD is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_PALETTE is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_PARTICLE is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_PORTER is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_STRESS is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_TEXTURE is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO_PARTICLE is not set
+# BR2_PACKAGE_DIRECTFB_EXAMPLES_WINDOW is not set
+# BR2_PACKAGE_KOBS_NG is not set
+# BR2_PACKAGE_SAWMAN is not set
+# BR2_PACKAGE_DIVINE is not set
+
+#
+# Legacy options removed in 2015.08
+#
+# BR2_PACKAGE_KODI_PVR_ADDONS is not set
+# BR2_BINUTILS_VERSION_2_23_2 is not set
+# BR2_BINUTILS_VERSION_2_24 is not set
+# BR2_BINUTILS_VERSION_2_25 is not set
+# BR2_PACKAGE_PERF is not set
+# BR2_BINUTILS_VERSION_2_22 is not set
+# BR2_PACKAGE_GPU_VIV_BIN_MX6Q is not set
+# BR2_TARGET_UBOOT_NETWORK is not set
diff --git a/linux/br2-external-tree/board/wally/rootfs_overlay/.profile b/linux/buildroot-config-src/wally/rootfs_overlay/.profile
similarity index 100%
rename from linux/br2-external-tree/board/wally/rootfs_overlay/.profile
rename to linux/buildroot-config-src/wally/rootfs_overlay/.profile
diff --git a/linux/br2-external-tree/board/wally/rootfs_overlay/etc/inittab b/linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab
similarity index 100%
rename from linux/br2-external-tree/board/wally/rootfs_overlay/etc/inittab
rename to linux/buildroot-config-src/wally/rootfs_overlay/etc/inittab
diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile
new file mode 100644
index 000000000..41ceacb41
--- /dev/null
+++ b/linux/buildroot-scripts/Makefile
@@ -0,0 +1,44 @@
+BUILDROOT := ${RISCV}/buildroot
+IMAGES := ${BUILDROOT}/output/images
+DIS := ${IMAGES}/disassembly
+
+all:
+	make disassemble
+	make generate
+
+generate:
+	# generating device tree binary
+	dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${IMAGES}/wally-virt.dtb
+
+disassemble:
+	mkdir -p ${DIS}
+	# disassemblies
+	make -j ${DIS}/fw_jump.objdump ${DIS}/vmlinux.objdump ${DIS}/busybox.objdump ${DIS}/vmlinux.objdump.addr
+	# filesystem
+	make ${DIS}/rootfs/bin/busybox
+	# mkdir -p ${DIS}/rootfs
+	# -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
+
+${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
+	riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
+
+${IMAGES}/vmlinux: ${BUILDROOT}/output/build/linux-5.10.7/vmlinux
+	cp ${BUILDROOT}/output/build/linux-5.10.7/vmlinux ${IMAGES}/vmlinux
+
+${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
+	riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
+
+${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump
+	-cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump
+
+${DIS}/busybox.objdump: ${DIS}/rootfs/bin/busybox
+	riscv64-unknown-elf-objdump -S ${DIS}/rootfs/bin/busybox >> ${DIS}/busybox.objdump
+
+${DIS}/rootfs/bin/busybox:
+	mkdir -p ${DIS}/rootfs
+	-cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
+
+
+clean:
+	rm -f ${IMAGES}/wally-virt.dtb
+	rm -rf ${DIS}
diff --git a/linux/buildroot-scripts/start-buildroot-session.sh b/linux/buildroot-scripts/start-buildroot-session.sh
new file mode 100755
index 000000000..f93815b6c
--- /dev/null
+++ b/linux/buildroot-scripts/start-buildroot-session.sh
@@ -0,0 +1,80 @@
+script_dir=$(readlink -f ./)
+personal_config=$(readlink -f ../buildroot-config-src)
+shared_config=$RISCV/buildroot-config-src
+
+if [ -d "$shared_config" ]; then
+    echo "Hold the horses, friend!" >&2
+    echo "There is already a buildroot-config-src folder in \$RISCV" >&2
+    if [ ! -f "$shared_config/.owner" ]; then
+        echo "Oy vey -- it was improperly created too!" >&2
+        echo "I see no .owner file in it!" >&2
+        echo "Maybe just delete it." >&2
+        exit 1
+    fi
+    owner=$(cat $shared_config/.owner)
+    echo "It was created by $owner." >&2
+    echo "Please contact them before overwriting their source files." >&2
+    exit 1
+fi
+echo "Starting new buildroot session"
+# Copy configs to shared location
+echo "Elevate permissions to copy ../buildroot-config-src to \$RISCV"
+sudo cp -r "$personal_config" "$shared_config"
+sudo chown -R cad $shared_config
+# Document who created these configs
+whoami>.owner
+sudo mv .owner $shared_config
+# Copy over main.config
+echo "Copying main.config to buildroot/.config."
+sudo cp $shared_config/main.config $RISCV/buildroot/.config
+sudo chown cad $RISCV/buildroot/.config
+
+echo "=============================================="
+echo "I'm about to sign you in as cad."
+echo ""
+echo "You can go straight to the \$RISCV/buildroot"
+echo "and run \`make\` if you want."
+echo ""
+echo "You can also run:"
+echo "  * \`make menuconfig\`"
+echo "  * \`make linux-menuconfig\`"
+echo "  * \`make busybox-menuconfig\`"
+echo "but if you do, you have to make extra certain" 
+echo "that you LOAD and SAVE configs from/to "
+echo "\$RISCV/buildroot-config-src."
+echo ""
+echo "Run \`exit\` to sign out when you are done."
+echo "And then any configs that were modified in"
+echo "\$RISCV/buildroot-config-src will be copied"
+echo "back to ../buildroot-config-src."
+echo "=============================================="
+read -p "Press any key to sign in as cad" -n1 -s
+echo ""
+cd $RISCV
+sudo su cad
+cd $script_dir
+
+echo ""
+echo "Ending buildroot session"
+if [ ! -d "$shared_config" ]; then
+    echo "Warning: $shared_config has already been deleted."
+    exit 0
+fi
+if [ ! -f "$shared_config/.owner" ]; then
+    echo "Oy vey -- no .owner file found.">&2
+    echo "Not sure whether to delete $shared_config.">&2
+    exit 1
+fi
+owner=$(cat "$shared_config"/.owner)
+if [ $owner != $(whoami) ]; then
+    echo "Whoah there! It seems $owner created $shared_config.">&2
+    echo "Ask them before deleting their work.">&2
+    exit 1
+fi
+echo "Copying modified configs from \$RISCV/buildroot-config-src back to ../buildroot-config-src."
+for file in $personal_config/*; do
+    file=$(basename $file)
+    cp $shared_config/$file $personal_config/$file
+done
+echo "Elevate permissions to remove personal configs from shared location."
+sudo rm -r $shared_config
diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts
deleted file mode 100644
index 56a12de31..000000000
--- a/linux/devicetree/wally-artya7.dts
+++ /dev/null
@@ -1,118 +0,0 @@
-/dts-v1/;
-
-/ {
-	#address-cells = <0x02>;
-	#size-cells = <0x02>;
-	compatible = "wally-virt";
-	model = "wally-virt,qemu";
-
-	chosen {
-		linux,initrd-end = <0x85c43a00>;
-		linux,initrd-start = <0x84200000>;
-		bootargs = "root=/dev/vda ro  console=ttyS0,115200 loglevel=7";
-		stdout-path = "/soc/uart@10000000";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x00 0x80000000 0x00 0x10000000>;
-	};
-
-	cpus {
-		#address-cells = <0x01>;
-		#size-cells = <0x00>;
-		clock-frequency = <20000000>;
-		timebase-frequency = <20000000>;
-
-		cpu@0 {
-			phandle = <0x01>;
-			device_type = "cpu";
-			reg = <0x00>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svade", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm";
-			riscv,cboz-block-size = <64>;
-			riscv,cbom-block-size = <64>;
-			mmu-type = "riscv,sv48";
-
-			interrupt-controller {
-				#interrupt-cells = <0x01>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-				phandle = <0x02>;
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <0x02>;
-		#size-cells = <0x02>;
-		compatible = "simple-bus";
-		ranges;
-
-		refclk: refclk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <20000000>;
-			clock-output-names = "xtal";
-		};
-
-		gpio0: gpio@10060000 {
-			compatible = "sifive,gpio0";
-			interrupt-parent = <0x03>;
-			interrupts = <3>;
-			reg = <0x00 0x10060000 0x00 0x1000>;
-			reg-names = "control";
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		uart@10000000 {
-			interrupts = <0x0a>;
-			interrupt-parent = <0x03>;
-			clock-frequency = <20000000>;
-			reg = <0x00 0x10000000 0x00 0x100>;
-			compatible = "ns16550a";
-		};
-
-		plic@c000000 {
-			phandle = <0x03>;
-			riscv,ndev = <0x35>;
-			reg = <0x00 0xc000000 0x00 0x210000>;
-			interrupts-extended = <0x02 0x0b 0x02 0x09>;
-			interrupt-controller;
-			compatible = "sifive,plic-1.0.0\0riscv,plic0";
-			#interrupt-cells = <0x01>;
-			#address-cells = <0x00>;
-		};
-
-		spi@13000 {
-			compatible = "sifive,spi0";
-			interrupt-parent = <0x03>;
-			interrupts = <0x14>;
-			reg = <0x0 0x13000 0x0 0x1000>;
-			reg-names = "control";
-			clocks = <&refclk>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-			mmc@0 {
-				compatible = "mmc-spi-slot";
-				reg = <0>;
-				spi-max-frequency = <1000000>;
-				voltage-ranges = <3300 3300>;
-				disable-wp;
-				// gpios = <&gpio0 6 1>;
-			};
-		};
-
-		clint@2000000 {
-			interrupts-extended = <0x02 0x03 0x02 0x07>;
-			reg = <0x00 0x2000000 0x00 0x10000>;
-			compatible = "sifive,clint0\0riscv,clint0";
-		};
-	};
-};
diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts
index 57e236c9c..a8093042e 100644
--- a/linux/devicetree/wally-vcu108.dts
+++ b/linux/devicetree/wally-vcu108.dts
@@ -9,20 +9,20 @@
 	chosen {
 		linux,initrd-end = <0x85c43a00>;
 		linux,initrd-start = <0x84200000>;
-		bootargs = "root=/dev/vda ro  console=ttyS0,115200 loglevel=7";
+		bootargs = "root=/dev/vda ro";
 		stdout-path = "/soc/uart@10000000";
 	};
 
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x00 0x80000000 0x00 0x80000000>;
+		reg = <0x00 0x80000000 0x00 0x08000000>;
 	};
 
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		clock-frequency = <0x2FAF080>;
-		timebase-frequency = <0x2FAF080>;
+		clock-frequency = <0x14FB180>;
+		timebase-frequency = <0x14FB180>;
 
 		cpu@0 {
 			phandle = <0x01>;
@@ -30,10 +30,7 @@
 			reg = <0x00>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svade", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm";
-			riscv,cboz-block-size = <64>;
-			riscv,cbom-block-size = <64>;
+			riscv,isa = "rv64imafdcsu";
 			mmu-type = "riscv,sv48";
 
 			interrupt-controller {
@@ -51,29 +48,10 @@
 		compatible = "simple-bus";
 		ranges;
 
-		refclk: refclk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <0x2FAF080>;
-			clock-output-names = "xtal";
-		};
-
-		gpio0: gpio@10060000 {
-			compatible = "sifive,gpio0";
-			interrupt-parent = <0x03>;
-			interrupts = <3>;
-			reg = <0x00 0x10060000 0x00 0x1000>;
-			reg-names = "control";
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <0x03>;
-			clock-frequency = <0x2FAF080>;
+			clock-frequency = <0x14FB180>;
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};
@@ -89,26 +67,6 @@
 			#address-cells = <0x00>;
 		};
 
-		spi@13000 {
-			compatible = "sifive,spi0";
-			interrupt-parent = <0x03>;
-			interrupts = <0x14>;
-			reg = <0x0 0x13000 0x0 0x1000>;
-			reg-names = "control";
-			clocks = <&refclk>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-			mmc@0 {
-				compatible = "mmc-spi-slot";
-				reg = <0>;
-				spi-max-frequency = <400000>;
-				voltage-ranges = <3300 3300>;
-				disable-wp;
-				// gpios = <&gpio0 6 1>;
-			};
-		};
-
 		clint@2000000 {
 			interrupts-extended = <0x02 0x03 0x02 0x07>;
 			reg = <0x00 0x2000000 0x00 0x10000>;
diff --git a/linux/devicetree/wally-vcu118.dts b/linux/devicetree/wally-vcu118.dts
index bdfafa2d0..224d4570f 100644
--- a/linux/devicetree/wally-vcu118.dts
+++ b/linux/devicetree/wally-vcu118.dts
@@ -9,20 +9,20 @@
 	chosen {
 		linux,initrd-end = <0x85c43a00>;
 		linux,initrd-start = <0x84200000>;
-		bootargs = "root=/dev/vda ro  console=ttyS0,115200";
+		bootargs = "root=/dev/vda ro";
 		stdout-path = "/soc/uart@10000000";
 	};
 
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x00 0x80000000 0x00 0x10000000>;
+		reg = <0x00 0x80000000 0x00 0x08000000>;
 	};
 
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		clock-frequency = <0x43B5FC0>;
-		timebase-frequency = <0x43B5FC0>;
+		clock-frequency = <0x24AE230>;
+		timebase-frequency = <0x24AE230>;
 
 		cpu@0 {
 			phandle = <0x01>;
@@ -30,10 +30,7 @@
 			reg = <0x00>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svade", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm";
-			riscv,cboz-block-size = <64>;
-			riscv,cbom-block-size = <64>;
+			riscv,isa = "rv64imafdcsu";
 			mmu-type = "riscv,sv48";
 
 			interrupt-controller {
@@ -54,7 +51,7 @@
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <0x03>;
-			clock-frequency = <0x43B5FC0>;
+			clock-frequency = <0x24AE230>;
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};
@@ -70,18 +67,6 @@
 			#address-cells = <0x00>;
 		};
 
-		mmc@13000 {
-			interrupts = <0x14>;
-			compatible = "riscv,axi-sd-card-1.0";
-			reg = <0x00 0x13000 0x00 0x7F>;
-			fifo-depth = <256>;
-			bus-width = <4>;
-			interrupt-parent = <0x03>;
-			clock = <0x43B5FC0>;
-			max-frequency = <0xF4240>;
-			no-sdio;
-		};
-
 		clint@2000000 {
 			interrupts-extended = <0x02 0x03 0x02 0x07>;
 			reg = <0x00 0x2000000 0x00 0x10000>;
diff --git a/linux/devicetree/wally-virt.dts b/linux/devicetree/wally-virt.dts
index b23d31015..b2fa1e81c 100644
--- a/linux/devicetree/wally-virt.dts
+++ b/linux/devicetree/wally-virt.dts
@@ -15,7 +15,7 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x00 0x80000000 0x00 0x10000000>;
+		reg = <0x00 0x80000000 0x00 0x08000000>;
 	};
 
 	cpus {
@@ -30,10 +30,7 @@
 			reg = <0x00>;
 			status = "okay";
 			compatible = "riscv";
-			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svade", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm";
-			riscv,cboz-block-size = <64>;
-			riscv,cbom-block-size = <64>;
+			riscv,isa = "rv64imafdcsu";
 			mmu-type = "riscv,sv48";
 
 			interrupt-controller {
diff --git a/linux/qemuBoot.sh b/linux/qemuBoot.sh
deleted file mode 100755
index 9cef11bc5..000000000
--- a/linux/qemuBoot.sh
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/bash
-###########################################
-## Boot linux on QEMU configured to match Wally
-##
-## Written: Jordan Carlin, jcarlin@hmc.edu
-## Created: 20 January 2025
-## Modified:
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-25 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-BUILDROOT="${BUILDROOT:-$RISCV/buildroot}"
-IMAGES="$BUILDROOT"/output/images
-
-if [[ "$1" == "--gdb" && -n "$2" ]]; then
-    GDB_FLAG="-gdb tcp::$2 -S"
-fi
-
-qemu-system-riscv64 \
-	-M virt -m 256M -nographic \
-	-bios "$IMAGES"/fw_jump.bin \
-	-kernel "$IMAGES"/Image \
-	-initrd "$IMAGES"/rootfs.cpio \
-	-dtb "$IMAGES"/wally-virt.dtb \
-	-cpu rva22s64,zicond=true,zfa=true,zfh=true,zcb=true,zbc=true,zkn=true,sstc=true,svadu=true,svnapot=true \
-	$GDB_FLAG
diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh
deleted file mode 100755
index 4616d3748..000000000
--- a/linux/sdcard/flash-sd.sh
+++ /dev/null
@@ -1,212 +0,0 @@
-#!/bin/bash
-###########################################
-## flash-sd.sh
-##
-## Written: Jacob Pease jacobpease@protonmail.com
-## Created: August 22, 2023
-##
-## Purpose: A script to flash an sd card with a bootable linux image.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-# Exit on any error (return code != 0)
-# set -e
-
-usage() { echo "Usage: $0 [-zh] [-b <path/to/buildroot>] <device>" 1>&2; exit 1; }
-
-help() {
-    echo "Usage: $0 [OPTIONS] <device>"
-    echo "  -z                          wipes card with zeros"
-    echo "  -b <path/to/buildroot>      get images from given buildroot"
-    echo "  -d <device tree name>       specify device tree to use"
-    exit 0;
-}
-
-# Output colors
-GREEN="\e[32m"
-RED="\e[31m"
-BOLDRED="\e[1;91m"
-BOLDGREEN="\e[1;32m"
-BOLDYELLOW="\e[1;33m"
-NC="\e[0m"
-NAME="$BOLDGREEN"${0:2}:"$NC"
-ERRORTEXT="$BOLDRED"ERROR:"$NC"
-WARNINGTEXT="$BOLDYELLOW"Warning:"$NC"
-
-# Default values for buildroot and device tree
-BUILDROOT=$RISCV/buildroot
-DEVICE_TREE=wally-vcu108.dtb
-MNT_DIR=wallyimg
-
-# Process options and arguments. The following code grabs the single
-# sdcard device argument no matter where it is in the positional
-# parameters list.
-ARGS=()
-while [ $OPTIND -le "$#" ] ; do
-    if getopts "hzb:d:" arg ; then
-        case "${arg}" in
-            h) help
-               ;;
-            z) WIPECARD=y
-               ;;
-            b) BUILDROOT=${OPTARG}
-               ;;
-            d) DEVICE_TREE=${OPTARG}
-               ;;
-        esac
-    else
-        ARGS+=("${!OPTIND}")
-        ((OPTIND++))
-    fi
-done
-
-# File location variables
-IMAGES=$BUILDROOT/output/images
-FW_JUMP=$IMAGES/fw_jump.bin
-LINUX_KERNEL=$IMAGES/Image
-#DEVICE_TREE=$IMAGES/$DEVICE_TREE
-
-SDCARD=${ARGS[0]}
-
-# User Error Checks ===================================================
-
-if [ "$#" -eq "0" ] ; then
-    usage
-fi
-
-# Check to make sure sd card device exists
-if [ ! -e "$SDCARD" ] ; then
-    echo -e "$NAME $ERRORTEXT SD card device does not exist."
-    exit 1
-fi
-
-# Prefix partition with "p" for non-SCSI disks (mmcblk, nvme)
-if [[ $SDCARD == "/dev/sd"* ]]; then
-    PART_PREFIX=""
-else
-    PART_PREFIX="p"
-fi
-
-# If no images directory, images have not been built
-if [ ! -d $IMAGES ] ; then
-    echo -e "$ERRORTEXT Buildroot images directory does not exist"
-    echo '       Make sure you have built the images before'
-    echo '       running this script.'
-    exit 1
-else
-    # If images are not built, exit
-    if [ ! -e $FW_JUMP ] || [ ! -e $LINUX_KERNEL ] ; then
-        echo -e '$ERRORTEXT Missing images in buildroot output directory.'
-        echo '       Build images before running this script.'
-        exit 1
-    fi
-fi
-
-# Ensure device tree binaries exist
-if [ ! -e $DEVICE_TREE ] ; then
-    echo -e "$NAME $ERRORTEXT Missing device tree files"
-    echo -e "$NAME generating all device tree files into buildroot"
-    make -C ../ generate BUILDROOT=$BUILDROOT
-fi
-
-# Calculate partition information =====================================
-
-# Size of OpenSBI and the Kernel in 512B blocks
-DST_SIZE=$(ls -la --block-size=512 $DEVICE_TREE | cut -d' ' -f 5 ) 
-FW_JUMP_SIZE=$(ls -la --block-size=512 $FW_JUMP | cut -d' ' -f 5 )
-KERNEL_SIZE=$(ls -la --block-size=512 $LINUX_KERNEL | cut -d' ' -f 5 )
-
-# Start sectors of OpenSBI and Kernel Partitions
-FW_JUMP_START=$(( 34 + $DST_SIZE ))
-KERNEL_START=$(( $FW_JUMP_START + $FW_JUMP_SIZE ))
-FS_START=$(( $KERNEL_START + $KERNEL_SIZE ))
-
-# Print out the sizes of the binaries in 512B blocks
-echo -e "$NAME Device tree block size:     $DST_SIZE"
-echo -e "$NAME OpenSBI FW_JUMP block size: $FW_JUMP_SIZE"
-echo -e "$NAME Kernel block size:          $KERNEL_SIZE"
-
-read -p $'\e[1;33mWarning:\e[0m Doing this will replace all data on this card. Continue? y/n: ' -n 1 -r
-echo
-if [[ $REPLY =~ ^[Yy]$ ]] ; then
-    DEVBASENAME=$(basename $SDCARD)
-    CHECKMOUNT=$(lsblk | grep "$DEVBASENAME"4 | tr -s ' ' | cut -d' ' -f 7)
-    
-    if [ ! -z $CHECKMOUNT ] ; then
-        sudo umount -v $CHECKMOUNT
-    fi
-
-    #Make empty image
-    if [ ! -z $WIPECARD ] ; then
-        echo -e "$NAME Wiping SD card. This could take a while."
-        sudo dd if=/dev/zero of=$SDCARD bs=64k status=progress && sync
-    fi
-
-    # GUID Partition Tables (GPT)
-    # ===============================================
-    # -g Converts any existing mbr record to a gpt record
-    # --clear clears any GPT partition table that already exists.
-    # --set-alignment=1 that we want to align partition starting sectors
-    # to 1 sector boundaries I think? This would normally be set to 2048
-    # apparently.
-
-    sudo sgdisk -z $SDCARD
-
-    sleep 1
-    
-    echo -e "$NAME Creating GUID Partition Table"
-    sudo sgdisk -g --clear --set-alignment=1 \
-         --new=1:34:+$DST_SIZE: --change-name=1:'fdt' \
-         --new=2:$FW_JUMP_START:+$FW_JUMP_SIZE --change-name=2:'opensbi' --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985 \
-         --new=3:$KERNEL_START:+$KERNEL_SIZE --change-name=3:'kernel' \
-         --new=4:$FS_START:-0 --change-name=4:'filesystem' \
-         $SDCARD
-
-    sudo partprobe $SDCARD
-
-    sleep 3
-
-    echo -e "$NAME Copying binaries into their partitions."
-    DD_FLAGS="bs=4k iflag=direct,fullblock oflag=dsync conv=fsync status=progress"
-
-    echo -e "$NAME Copying device tree"
-    sudo dd if=$DEVICE_TREE of="$SDCARD""$PART_PREFIX"1 $DD_FLAGS && sync
-
-    echo -e "$NAME Copying OpenSBI"
-    sudo dd if=$FW_JUMP of="$SDCARD""$PART_PREFIX"2 $DD_FLAGS && sync
-
-    echo -e "$NAME Copying Kernel"
-    sudo dd if=$LINUX_KERNEL of="$SDCARD""$PART_PREFIX"3 $DD_FLAGS && sync
-
-    sudo mkfs.ext4 -E lazy_itable_init=0,lazy_journal_init=0 "$SDCARD""$PART_PREFIX"4
-    sudo fsck -fv "$SDCARD""$PART_PREFIX"4
-    sudo mkdir /mnt/$MNT_DIR
-
-    sudo mount -o init_itable=0 -v "$SDCARD""$PART_PREFIX"4 /mnt/$MNT_DIR 
-
-    sudo umount -v /mnt/$MNT_DIR
-
-    sudo rmdir /mnt/$MNT_DIR
-    #sudo losetup -d $LOOPDEVICE
-fi
-
-echo
-echo "GPT Information for $SDCARD ==================================="
-sudo sgdisk -p $SDCARD
diff --git a/linux/sdcard/write-bytes.sh b/linux/sdcard/write-bytes.sh
deleted file mode 100755
index b9c312ceb..000000000
--- a/linux/sdcard/write-bytes.sh
+++ /dev/null
@@ -1,80 +0,0 @@
-#!/bin/bash
-###########################################
-## write-bytes.sh
-##
-## Written: Jacob Pease jacobpease@protonmail.com
-## Created: November 2nd, 2024
-## Modified: 
-##
-## Purpose: Write a sequence of bytes from text file to an output file and a flash card.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-
-
-# This file writes a bunch of bytes to the flash card based on a text
-# file input with bytes written in hexadecimal.
-
-usage() { echo "Usage: $0 [-zh] [-b <path/to/buildroot>] <device>" 1>&2; exit 1; }
-
-help() {
-    echo "Usage: $0 [OPTIONS] <device>"
-    echo "  -i                          Input text file with hex bytes."
-    echo "  -b <path/to/buildroot>      Output binary file."
-    exit 0;
-}
-
-INPUTFILE=""
-OUTPUTFILE=""
-
-ARGS=()
-while [ $OPTIND -le "$#" ] ; do
-    if getopts "hi:o:" arg ; then
-        case "${arg}" in
-            h) help
-               ;;
-            i) INPUTFILE=${OPTARG}
-               ;;
-            o) OUTPUTFILE=${OPTARG}
-               ;;
-        esac
-    else
-        ARGS+=("${!OPTIND}")
-        ((OPTIND++))
-    fi
-done
-
-SDCARD=${ARGS[0]}
-
-if [ ! -e $INPUTFILE ] ; then
-    echo -e "Error: Input file $INPUTFILE does not exist."
-    exit 1
-fi
-
-if [ -e $OUTPUTFILE ] ; then
-    echo -e "Error: Output file $OUTPUTFILE already exists."
-    exit 1
-fi
-
-for word in $(cat "$INPUTFILE")
-do
-    echo -en "\x$word" >> $OUTPUTFILE
-done
-
-dd if=$OUTPUTFILE of="$SDCARD"
diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile
new file mode 100644
index 000000000..c31aae39d
--- /dev/null
+++ b/linux/testvector-generation/Makefile
@@ -0,0 +1,13 @@
+SHELL = /bin/sh
+
+CFLAG = -Wall -g
+CC = gcc
+
+all: fixBinMem
+
+fixBinMem: fixBinMem.c
+	${CC} ${CFLAGS} fixBinMem.c -o fixBinMem
+	chmod +x fixBinMem
+
+clean:
+	-rm -f fixBinMem
diff --git a/linux/testvector-generation/checkpointSweep.sh b/linux/testvector-generation/checkpointSweep.sh
new file mode 100755
index 000000000..075ca253c
--- /dev/null
+++ b/linux/testvector-generation/checkpointSweep.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+for index in {450..500};
+do 
+    instrs=$(($index*1000000))
+    echo "y" | nice -n 5 ./genCheckpoint.sh $instrs
+done
diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh
new file mode 100755
index 000000000..7ca3e9b15
--- /dev/null
+++ b/linux/testvector-generation/debug.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+imageDir=$RISCV/buildroot/output/images
+tvDir=$RISCV/linux-testvectors
+tcpPort=1239
+
+# QEMU Simulation
+qemu-system-riscv64 \
+-M virt -dtb $imageDir/wally-virt.dtb \
+-nographic \
+-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on 
+# > ./qemu-serial \
+# -gdb tcp::$tcpPort -S) \
+# & riscv64-unknown-elf-gdb -quiet \
+# -ex "set pagination off" \
+# -ex "set logging overwrite on" \
+# -ex "set logging redirect on" \
+# -ex "set confirm off" \
+# -ex "target extended-remote :$tcpPort" \
+# -ex "maintenance packet Qqemu.PhyMemMode:1" \
+# -ex "file $imageDir/vmlinux"
diff --git a/linux/testvector-generation/filterTrapsToInterrupts.py b/linux/testvector-generation/filterTrapsToInterrupts.py
new file mode 100755
index 000000000..de0553098
--- /dev/null
+++ b/linux/testvector-generation/filterTrapsToInterrupts.py
@@ -0,0 +1,68 @@
+#! /usr/bin/python3
+import sys, os
+from functools import reduce
+
+################
+# Helper Funcs #
+################
+
+def tokenize(string):
+    tokens = []
+    token = ''
+    whitespace = 0
+    prevWhitespace = 0
+    for char in string:
+        prevWhitespace = whitespace
+        whitespace = char in ' \t\n'
+        if (whitespace):
+            if ((not prevWhitespace) and (token != '')): 
+                tokens.append(token)
+            token = ''
+        else:
+            token = token + char
+    return tokens
+
+def strip0x(num):
+    return num[2:]
+
+def stripZeroes(num):
+    num = num.strip('0')
+    if num=='':
+        return '0'
+    else:
+        return num
+
+#############
+# Main Code #
+#############
+print("Begin filtering traps down to just external interrupts.")
+
+# Parse Args
+if len(sys.argv) != 2:
+    sys.exit('Error filterTrapsToInterrupts.py expects 1 arg: <path_to_testvector_dir>')
+tvDir = sys.argv[1]+'/'
+trapsFilePath = tvDir+'traps.txt'
+if not os.path.exists(trapsFilePath):
+    sys.exit('Error input file '+trapsFilePath+'not found')
+
+with open(tvDir+'interrupts.txt', 'w') as interruptsFile:
+    with open(trapsFilePath, 'r') as trapsFile:
+        while True:
+            trap = trapsFile.readline()
+            if trap == '':
+                break
+            trapType = trap.split(' ')[-1]
+            if ('interrupt' in trap) and (('external' in trapType) or ('m_timer' in trapType)): # no s_timer because that is not controlled by CLINT
+                interruptsFile.write(trap) # overall line
+                interruptsFile.write(trapsFile.readline()) # attempted instr count
+                interruptsFile.write(trapsFile.readline()) # hart #
+                interruptsFile.write(trapsFile.readline()) # asynchronous
+                interruptsFile.write(trapsFile.readline()) # cause
+                interruptsFile.write(trapsFile.readline()) # epc
+                interruptsFile.write(trapsFile.readline()) # tval
+                interruptsFile.write(trapsFile.readline()) # description
+            else:
+                for i in range(7):
+                    trapsFile.readline()
+        
+print("Finished filtering traps down to just external interrupts.")
diff --git a/linux/testvector-generation/fixBinMem.c b/linux/testvector-generation/fixBinMem.c
new file mode 100644
index 000000000..fe071008b
--- /dev/null
+++ b/linux/testvector-generation/fixBinMem.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+int main(int argc, char *argv[]) {
+    if (argc < 3){
+        fprintf(stderr, "Expected 2 arguments: <raw GDB dump> <output binary>\n");
+        exit(1);
+    }
+    char* rawGDBfilePath = argv[1];
+    FILE* rawGDBfile;
+    if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) {
+        fprintf(stderr, "File not found: %s\n",rawGDBfilePath);
+        exit(1);
+    }
+    char* outFilePath = argv[2];
+    FILE* outFile = fopen(outFilePath,"w");
+    uint64_t qemuWord;
+    uint64_t verilogWord;
+    int bytesReturned=0;
+    do {
+        bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile);
+        verilogWord = (((qemuWord>>0 )&0xff)<<56 | 
+                       ((qemuWord>>8 )&0xff)<<48 | 
+                       ((qemuWord>>16)&0xff)<<40 | 
+                       ((qemuWord>>24)&0xff)<<32 | 
+                       ((qemuWord>>32)&0xff)<<24 | 
+                       ((qemuWord>>40)&0xff)<<16 | 
+                       ((qemuWord>>48)&0xff)<<8  | 
+                       ((qemuWord>>56)&0xff)<<0);
+        fwrite(&verilogWord, 8, 1, outFile);
+    } while(bytesReturned!=0);
+    return 0;
+}
diff --git a/linux/testvector-generation/genCheckpoint.sh b/linux/testvector-generation/genCheckpoint.sh
new file mode 100755
index 000000000..f12223f54
--- /dev/null
+++ b/linux/testvector-generation/genCheckpoint.sh
@@ -0,0 +1,146 @@
+#!/bin/bash
+tcpPort=1238
+imageDir=$RISCV/buildroot/output/images
+tvDir=$RISCV/linux-testvectors
+recordFile="$tvDir/all.qemu"
+traceFile="$tvDir/all.txt"
+
+# Parse Commandline Arg
+if [ "$#" -ne 1 ]; then
+    echo "genCheckpoint requires 1 argument: <num instrs>" >&2
+    exit 1
+fi
+instrs=$1
+if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null
+then
+    echo "Error expected integer number of instructions, got $instrs" >&2
+    exit 1
+fi
+
+checkPtDir="$tvDir/checkpoint$instrs"
+outTraceFile="$checkPtDir/all.txt"
+rawStateFile="$checkPtDir/stateGDB.txt"
+rawUartStateFile="$checkPtDir/uartStateGDB.txt"
+uartStateFile="$checkPtDir/checkpoint-UART"
+rawPlicStateFile="$checkPtDir/plicStateGDB.txt"
+plicStateFile="$checkPtDir/checkpoint-PLIC"
+rawRamFile="$checkPtDir/ramGDB.bin"
+ramFile="$checkPtDir/ram.bin"
+
+read -p "This scripts is going to create a checkpoint at $instrs instrs.
+Is that what you wanted? (y/n) " -n 1 -r
+echo
+if [[ $REPLY =~ ^[Yy]$ ]]
+then
+    echo "Creating checkpoint at $instrs instructions!"
+    if [ ! -d "$tvDir" ]; then
+        echo "Error: linux testvector directory $tvDir not found!">&2
+        echo "Please create it. For example:">&2
+        echo "    sudo mkdir -p $tvDir">&2
+        exit 1
+    fi
+    test -w $tvDir
+    if [ ! $? -eq 0 ]; then
+        echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
+        echo "Please chmod it. For example:">&2
+        echo "    sudo chmod -R a+rw $tvDir">&2
+        exit 1
+    fi
+
+    mkdir -p $checkPtDir
+
+    # Identify instruction in trace
+    instr=$(sed "${instrs}q;d" "$traceFile")
+    echo "Found ${instrs}th instr: ${instr}"
+    pc=$(echo $instr | cut -d " " -f1)
+    asm=$(echo $instr | cut -d " " -f2)
+    occurences=$(($(head -$instrs "$traceFile" | grep -c "${pc} ${asm}")-1))
+    echo "It occurs ${occurences} times before the ${instrs}th instr." 
+
+    # Create GDB script because GDB is terrible at handling arguments / variables
+    cat > genCheckpoint.gdb <<- end_of_script 
+    set pagination off
+    set logging overwrite on
+    set logging redirect on
+    set confirm off
+    target extended-remote :$tcpPort
+    maintenance packet Qqemu.PhyMemMode:1
+    file $imageDir/vmlinux
+    # Step over reset vector into actual code
+    stepi 100
+    shell echo \"GDB proceeding to checkpoint at $instrs instrs, pc $pc\"
+    b *0x$pc
+    ignore 1 $occurences
+    c
+    shell echo \"Reached checkpoint at $instrs instrs\"
+    shell echo \"GDB storing CPU state to $rawStateFile\"
+    set logging file $rawStateFile
+    set logging on
+    info all-registers
+    set logging off
+    shell echo \"GDB storing UART state to $rawUartStateFile\"
+    # Save value of LCR
+    set \$LCR=*0x10000003 & 0xff
+    set logging file $rawUartStateFile
+    set logging on
+    # Change LCR to set DLAB=0 to be able to read RBR and IER
+    set {char}0x10000003 &= ~0x80
+    x/1xb 0x10000000
+    x/1xb 0x10000001
+    x/1xb 0x10000002
+    # But log original value of LCR
+    printf "0x10000003:\t0x%02x\n", \$LCR
+    x/1xb 0x10000004
+    x/1xb 0x10000005
+    x/1xb 0x10000006
+    x/1xb 0x10000007
+    set logging off
+    shell echo \"GDB storing PLIC state to $rawPlicStateFile\"
+    shell echo \"Note: this dumping assumes a maximum of 63 PLIC sources\"
+    set logging file $rawPlicStateFile
+    set logging on
+    # Priority Levels for sources 1 thru 63
+    x/63xw 0x0C000004
+    # Interrupt Enables for sources 1 thru 63 for contexts 0 and 1
+    x/2xw 0x0C002000
+    x/2xw 0x0C002080
+    # Global Priority Threshold for contexts 0 and 1
+    x/1xw 0x0C200000
+    x/1xw 0x0C201000
+    set logging off
+    shell echo \"GDB storing RAM to $rawRamFile\"
+    dump binary memory $rawRamFile 0x80000000 0x87ffffff
+    kill
+    q
+end_of_script
+
+    # GDB+QEMU
+    echo "Starting QEMU in replay mode with attached GDB script at $(date +%H:%M:%S)"
+    (qemu-system-riscv64 \
+    -M virt -dtb $imageDir/wally-virt.dtb \
+    -nographic \
+    -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+    -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \
+    -gdb tcp::$tcpPort -S \
+     1>./qemu-serial) \
+    & riscv64-unknown-elf-gdb --quiet -x genCheckpoint.gdb
+
+    echo "Completed GDB script at $(date +%H:%M:%S)"
+
+    # Post-Process GDB outputs
+    ./parseState.py "$checkPtDir"
+    ./parseUartState.py "$checkPtDir"
+    ./parsePlicState.py "$checkPtDir"
+    echo "Changing Endianness at $(date +%H:%M:%S)"
+    make fixBinMem
+    ./fixBinMem "$rawRamFile" "$ramFile"
+    echo "Copying over a truncated trace"
+    tail -n+$instrs $traceFile > $outTraceFile
+
+    echo "Checkpoint completed at $(date +%H:%M:%S)"
+    echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
+    echo "Run the following:"
+    echo "    sudo chown -R cad:cad $tvDir"
+    echo "    sudo chmod -R go-w $tvDir"
+fi
+
diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh
new file mode 100755
index 000000000..8c16ee330
--- /dev/null
+++ b/linux/testvector-generation/genInitMem.sh
@@ -0,0 +1,71 @@
+#!/bin/bash
+tcpPort=1235
+imageDir=$RISCV/buildroot/output/images
+tvDir=$RISCV/linux-testvectors
+rawRamFile="$tvDir/ramGDB.bin"
+ramFile="$tvDir/ram.bin"
+rawBootmemFile="$tvDir/bootmemGDB.bin"
+bootmemFile="$tvDir/bootmem.bin"
+rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin"
+untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin"
+
+read -p "Warning: running this script will overwrite the contents of:
+  * $rawRamFile
+  * $ramFile
+  * $rawBootmemFile
+  * $bootmemFile
+  * $rawUntrimmedBootmemFile
+  * $untrimmedBootmemFile
+Would you like to proceed? (y/n) " -n 1 -r
+echo
+if [[ $REPLY =~ ^[Yy]$ ]]
+then
+    if [ ! -d "$tvDir" ]; then
+        echo "Error: linux testvector directory $tvDir not found!">&2
+        echo "Please create it. For example:">&2
+        echo "    sudo mkdir -p $tvDir">&2
+        exit 1
+    fi
+    test -w $tvDir
+    if [ ! $? -eq 0 ]; then
+        echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
+        echo "Please chmod it. For example:">&2
+        echo "    sudo chmod -R a+rw $tvDir">&2
+        exit 1
+    fi
+
+    echo "Launching QEMU in replay mode!"
+    (qemu-system-riscv64 \
+    -M virt -dtb $RISCV/buildroot/output/images/wally-virt.dtb \
+    -nographic \
+    -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+    -gdb tcp::$tcpPort -S) \
+    & riscv64-unknown-elf-gdb --quiet \
+    -ex "set pagination off" \
+    -ex "set logging overwrite on" \
+    -ex "set logging redirect on" \
+    -ex "set confirm off" \
+    -ex "target extended-remote :$tcpPort" \
+    -ex "maintenance packet Qqemu.PhyMemMode:1" \
+    -ex "printf \"Creating $rawBootmemFile\n\"" \
+    -ex "dump binary memory $rawBootmemFile 0x1000 0x1fff" \
+    -ex "printf \"Creating $rawUntrimmedBootmemFile\n\"" \
+    -ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \
+    -ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \
+    -ex "printf \"Creating $rawRamFile\n\"" \
+    -ex "dump binary memory $rawRamFile 0x80000000 0x87ffffff" \
+    -ex "kill" \
+    -ex "q"
+
+    echo "Changing Endianness"
+    make fixBinMem
+    ./fixBinMem "$rawRamFile" "$ramFile"
+    ./fixBinMem "$rawBootmemFile" "$bootmemFile"
+    ./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile"
+
+    echo "genInitMem.sh completed!"
+    echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
+    echo "Run the following:"
+    echo "    sudo chown -R cad:cad $tvDir"
+    echo "    sudo chmod -R go-w $tvDir"
+fi
diff --git a/linux/testvector-generation/genRecording.sh b/linux/testvector-generation/genRecording.sh
new file mode 100755
index 000000000..f9538e145
--- /dev/null
+++ b/linux/testvector-generation/genRecording.sh
@@ -0,0 +1,37 @@
+#!/bin/bash
+imageDir=$RISCV/buildroot/output/images
+tvDir=$RISCV/linux-testvectors
+recordFile="$tvDir/all.qemu"
+
+read -p "Warning: running this script will overwrite $recordFile
+Would you like to proceed? (y/n) " -n 1 -r
+echo
+if [[ $REPLY =~ ^[Yy]$ ]]
+then
+    if [ ! -d "$tvDir" ]; then
+        echo "Error: linux testvector directory $tvDir not found!">&2
+        echo "Please create it. For example:">&2
+        echo "    sudo mkdir -p $tvDir">&2
+        exit 1
+    fi
+    test -w $tvDir
+    if [ ! $? -eq 0 ]; then
+        echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
+        echo "Please chmod it. For example:">&2
+        echo "    sudo chmod -R a+rw $tvDir">&2
+        exit 1
+    fi
+
+    echo "Launching QEMU in record mode!"
+    qemu-system-riscv64 \
+    -M virt -dtb $imageDir/wally-virt.dtb \
+    -nographic \
+    -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+    -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile
+
+    echo "genRecording.sh completed!"
+    echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
+    echo "Run the following:"
+    echo "    sudo chown -R cad:cad $tvDir"
+    echo "    sudo chmod -R go-w $tvDir"
+fi
diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh
new file mode 100755
index 000000000..76a6a10c6
--- /dev/null
+++ b/linux/testvector-generation/genTrace.sh
@@ -0,0 +1,53 @@
+#!/bin/bash
+tcpPort=1234
+imageDir=$RISCV/buildroot/output/images
+tvDir=$RISCV/linux-testvectors
+recordFile="$tvDir/all.qemu"
+traceFile="$tvDir/all.txt"
+trapsFile="$tvDir/traps.txt"
+interruptsFile="$tvDir/interrupts.txt"
+
+read -p "Warning: running this script will overwrite the contents of:
+  * $traceFile
+  * $trapsFile
+  * $interruptsFile
+Would you like to proceed? (y/n) " -n 1 -r
+echo
+if [[ $REPLY =~ ^[Yy]$ ]]
+then
+    if [ ! -d "$tvDir" ]; then
+        echo "Error: linux testvector directory $tvDir not found!">&2
+        echo "Please create it. For example:">&2
+        echo "    sudo mkdir -p $tvDir">&2
+        exit 1
+    fi
+    test -w $tvDir
+    if [ ! $? -eq 0 ]; then
+        echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2
+        echo "Please chmod it. For example:">&2
+        echo "    sudo chmod -R a+rw $tvDir">&2
+        exit 1
+    fi
+
+    touch $traceFile 
+    touch $trapsFile 
+    touch $interruptsFile 
+
+    # QEMU Simulation
+    echo "Launching QEMU in replay mode!"
+    (qemu-system-riscv64 \
+    -M virt -dtb $imageDir/wally-virt.dtb \
+    -nographic \
+    -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
+    -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \
+    -d nochain,cpu,in_asm,int \
+    2>&1 >./qemu-serial | ./parseQEMUtoGDB.py | ./parseGDBtoTrace.py $trapsFile > $traceFile)
+
+    ./filterTrapsToInterrupts.py $tvDir
+
+    echo "genTrace.sh completed!"
+    echo "You may want to restrict write access to $tvDir now and give cad ownership of it."
+    echo "Run the following:"
+    echo "    sudo chown -R cad:cad $tvDir"
+    echo "    sudo chmod -R go-w $tvDir"
+fi
diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py
new file mode 100755
index 000000000..9a467e3e2
--- /dev/null
+++ b/linux/testvector-generation/parseGDBtoTrace.py
@@ -0,0 +1,243 @@
+#! /usr/bin/python3
+import sys, fileinput, re
+
+# Ross Thompson
+# July 27, 2021
+# Rewrite of the linux trace parser.
+
+
+InstrStartDelim = '=>'
+InstrEndDelim = '-----'
+
+#InputFile = 'noparse.txt'
+#InputFile = sys.stdin
+#InputFile = 'temp.txt'
+#OutputFile = 'parsedAll.txt'
+
+HUMAN_READABLE = False
+
+def toDict(lst):
+    'Converts the list of register values to a dictionary'
+    dct= {}
+    for item in lst:
+        regTup = item.split()
+        dct[regTup[0]] = int(regTup[2], 10)
+    del dct['pc']
+    return dct
+
+def whichClass(text, Regs):
+    'Which instruction class?'
+    #print(text, Regs)
+    if text[0:2] == 'ld' or text[0:2] == 'lw' or text[0:2] == 'lh' or text[0:2] == 'lb':
+        return ('load', WhatAddr(text, Regs), None, WhatMemDestSource(text))
+    elif text[0:2] == 'sd' or text[0:2] == 'sw' or text[0:2] == 'sh' or text[0:2] == 'sb':
+        return ('store', WhatAddr(text, Regs), WhatMemDestSource(text), None)
+    elif text[0:3] == 'amo':
+        return ('amo', WhatAddrAMO(text, Regs), WhatMemDestSource(text), WhatMemDestSource(text))
+    elif text[0:2] == 'lr':
+        return ('lr', WhatAddrLR(text, Regs), None, WhatMemDestSource(text))
+    elif text[0:2] == 'sc':
+        return ('sc', WhatAddrSC(text, Regs), WhatMemDestSource(text), None)
+    else:
+        return ('other', None, None, None)
+
+def whatChanged(dct0, dct1):
+    'Compares two dictionaries of instrution registers and indicates which registers changed'
+    dct = {}
+    for key in dct0:
+        if (dct1[key] != dct0[key]):
+            dct[key] = dct1[key]
+    return dct
+
+def WhatMemDestSource(text):
+    ''''What is the destination register. Used to compute where the read data is 
+    on a load or the write data on a store.'''
+    return text.split()[1].split(',')[0]
+
+def WhatAddr(text, Regs):
+    'What is the data memory address?'
+    Imm = text.split(',')[1]
+    (Imm, Src) = Imm.split('(')
+    Imm = int(Imm.strip(), 10)
+    Src = Src.strip(')').strip()
+    RegVal = Regs[Src]
+    return Imm + RegVal
+
+def WhatAddrAMO(text, Regs):
+    'What is the data memory address?'
+    Src = text.split('(')[1]
+    Src = Src.strip(')').strip()
+    return Regs[Src]
+
+def WhatAddrLR(text, Regs):
+    'What is the data memory address?'
+    Src = text.split('(')[1]
+    Src = Src.strip(')').strip()
+    return Regs[Src]
+
+def WhatAddrSC(text, Regs):
+    'What is the data memory address?'
+    Src = text.split('(')[1]
+    Src = Src.strip(')').strip()
+    return Regs[Src]
+
+def PrintInstr(instr):
+    if instr[2] == None:
+        return
+    ChangedRegisters = instr[4]
+    GPR = ''
+    CSR = []
+    for key in ChangedRegisters:
+        # filter out csr which are not checked.
+        if(key in RegNumber):
+            if(RegNumber[key] < 32):
+                # GPR
+                if(HUMAN_READABLE):
+                    GPR = '{:-2d} {:016x}'.format(RegNumber[key], ChangedRegisters[key])
+                else:
+                    GPR = '{:d} {:x}'.format(RegNumber[key], ChangedRegisters[key])
+            else:
+                if(HUMAN_READABLE):
+                    CSR.extend([key, '{:016x}'.format(ChangedRegisters[key])])
+                else:
+                    CSR.extend([key, '{:x}'.format(ChangedRegisters[key])])                
+
+    CSRStr = ' '.join(CSR)
+
+    #print(instr)
+
+    if (HUMAN_READABLE == True):
+        outString='{:016x} {:08x} {:25s}'.format(instr[0], instr[1], instr[2])
+        if(len(GPR) != 0):
+            outString+=' GPR {}'.format(GPR)
+        if(instr[3] == 'load' or instr[3] == 'lr'):
+            outString+=' MemR {:016x} {:016x} {:016x}'.format(instr[5], 0, instr[7])
+        if(instr[3] == 'store'):
+            outString+='\t\t\t    MemW {:016x} {:016x} {:016x}'.format(instr[5], instr[6], 0)
+        if(len(CSR) != 0):
+            outString+=' CSR {}'.format(CSRStr)
+    else:
+        outString='{:x} {:x} {:s}'.format(instr[0], instr[1], instr[2].replace(' ', '_'))
+        if(len(GPR) != 0):
+            outString+=' GPR {}'.format(GPR)
+        if(instr[3] == 'load' or instr[3] == 'lr'):
+            outString+=' MemR {:x} {:x} {:x}'.format(instr[5], 0, instr[7])
+        if(instr[3] == 'store'):
+            outString+=' MemW {:x} {:x} {:x}'.format(instr[5], instr[6], 0)
+        if(len(CSR) != 0):
+            outString+=' CSR {}'.format(CSRStr)
+    outString+='\n'
+    return outString
+
+# =========
+# Main Code
+# =========
+# Parse argument for interrupt file
+if len(sys.argv) != 2:
+    sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n <interrupt filename>>')
+interruptFname = sys.argv[1]
+# reg number
+RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'mscratch': 46, 'sscratch': 47, 'satp': 48}
+# initial state
+CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'mscratch': 0, 'sscratch': 0, 'satp': 0}, {}, None, None, None]
+
+#with open (InputFile, 'r') as InputFileFP:
+#lines = InputFileFP.readlines()
+lineNum = 0
+StartLine = 0
+EndLine = 0
+numInstrs = 0
+#instructions = []
+MemAdr = 0
+lines = []
+interrupts=open(interruptFname,'w')
+interrupts.close()
+
+prevInstrOutString=''
+currInstrOutString=''
+for line in fileinput.input('-'):
+    if line.startswith('riscv_cpu_do_interrupt'):
+        with open(interruptFname,'a') as interrupts:
+            # Write line
+            # Example line: hart:0, async:0, cause:0000000000000002, epc:0x0000000080008548, tval:0x0000000000000000, desc=illegal_instruction
+            interrupts.write(line)
+            # Write instruction count
+            interrupts.write(str(numInstrs)+'\n')
+            # Convert line to rows of info for easier Verilog parsing
+            vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',')
+            vals=[val.split(':')[-1].strip(' ') for val in vals]
+            vals=[val.split('=')[-1].strip(' ') for val in vals]
+            for val in vals:
+                interrupts.write(val+'\n')
+        continue
+    lines.insert(lineNum, line)
+    if InstrStartDelim in line:
+        lineNum = 0
+        StartLine = lineNum
+    elif InstrEndDelim in line:
+        EndLine = lineNum
+        (InstrBits, text) = lines[StartLine].split(':')
+        InstrBits = int(InstrBits.strip('=> '), 16)
+        text = text.strip()
+        PC = int(lines[StartLine+1].split(':')[0][2:], 16)
+        Regs = toDict(lines[StartLine+2:EndLine])
+        (Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs)
+        #print("CWR", Class, WriteReg, ReadReg)
+        PreviousInstr = CurrentInstr
+
+        Changed = whatChanged(PreviousInstr[4], Regs)
+
+        if (ReadReg !=None): ReadData = ReadReg
+        else: ReadData = None
+
+        if (WriteReg !=None): WriteData = WriteReg
+        else: WriteData = None
+
+        CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData]
+
+        #print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8])
+
+        # pc, instrbits, text and class come from the last line.
+        MoveInstrToRegWriteLst = PreviousInstr[0:4]
+        # updated registers come from the current line.
+        MoveInstrToRegWriteLst.append(CurrentInstr[5])   # destination regs
+        # memory address if present comes from the last line.
+        MoveInstrToRegWriteLst.append(PreviousInstr[6])  # MemAdrM
+        # write data from the previous line
+        #MoveInstrToRegWriteLst.append(PreviousInstr[7])   # WriteDataM
+
+        if (PreviousInstr[7] != None):
+            MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]])   # WriteDataM
+        else:
+            MoveInstrToRegWriteLst.append(None)
+
+        # read data from the current line
+        #MoveInstrToRegWriteLst.append(PreviousInstr[8])   # ReadDataM
+        if (PreviousInstr[8] != None):
+            MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]])   # ReadDataM
+        else:
+            MoveInstrToRegWriteLst.append(None)
+
+        lines.clear()
+        #instructions.append(MoveInstrToRegWriteLst)
+
+        prevInstrOutString = currInstrOutString
+        currInstrOutString = PrintInstr(MoveInstrToRegWriteLst)
+        # Remove duplicates
+        if (PreviousInstr[0] != CurrentInstr[0]) and (currInstrOutString != None):
+            sys.stdout.write(currInstrOutString)
+            numInstrs += 1
+            if (numInstrs % 1e5 == 0):
+                sys.stderr.write('GDB trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
+                sys.stderr.flush()
+    lineNum += 1
+
+
+#for instruction in instructions[1::]:
+
+
+#with open(OutputFile, 'w') as OutputFileFP:
+#    print('opened file')
+
+
+
diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py
new file mode 100755
index 000000000..49f2a558e
--- /dev/null
+++ b/linux/testvector-generation/parsePlicState.py
@@ -0,0 +1,106 @@
+#! /usr/bin/python3
+import sys, os
+from functools import reduce
+
+################
+# Helper Funcs #
+################
+
+def tokenize(string):
+    tokens = []
+    token = ''
+    whitespace = 0
+    prevWhitespace = 0
+    for char in string:
+        prevWhitespace = whitespace
+        whitespace = char in ' \t\n'
+        if (whitespace):
+            if ((not prevWhitespace) and (token != '')): 
+                tokens.append(token)
+            token = ''
+        else:
+            token = token + char
+    return tokens
+
+def strip0x(num):
+    return num[2:]
+
+def stripZeroes(num):
+    num = int(num,16)
+    return hex(num)[2:]
+
+#############
+# Main Code #
+#############
+print("Begin parsing PLIC state.")
+
+# Parse Args
+if len(sys.argv) != 2:
+    sys.exit('Error parsePlicState.py expects 1 arg: <path_to_checkpoint_dir>')
+outDir = sys.argv[1]+'/'
+rawPlicStateFile = outDir+'plicStateGDB.txt'
+if not os.path.exists(rawPlicStateFile):
+    sys.exit('Error input file '+rawPlicStateFile+'not found')
+
+with open(rawPlicStateFile, 'r') as rawPlicStateFile:
+    plicIntPriorityArray = [] # iterates over number of different sources
+    # 0x0C000004 thru 0x0C000010
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000014 thru 0x0C000020
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000024 thru 0x0C000030
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000034 thru 0x0C000040
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000044 thru 0x0C000050
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000054 thru 0x0C000060
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000064 thru 0x0C000070
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000074 thru 0x0C000080
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000084 thru 0x0C000090
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C000094 thru 0x0C0000a0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000a4 thru 0x0C0000b0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000b4 thru 0x0C0000c0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000c4 thru 0x0C0000d0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000d4 thru 0x0C0000e0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000e4 thru 0x0C0000f0
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C0000f4 thru 0x0C0000fc
+    plicIntPriorityArray += tokenize(rawPlicStateFile.readline())[1:]
+
+    plicIntEnableArray = [] # iterates over number of different contexts
+    # 0x0C020000 thru 0x0C020004
+    plicIntEnable = tokenize(rawPlicStateFile.readline())[1:]
+    plicIntEnable = map(strip0x,plicIntEnable)
+    plicIntEnableArray.append(reduce(lambda x,y: y+x,plicIntEnable))
+    # 0x0C020080 thru 0x0C020084
+    plicIntEnable = tokenize(rawPlicStateFile.readline())[1:]
+    plicIntEnable = map(strip0x,plicIntEnable)
+    plicIntEnableArray.append(reduce(lambda x,y: y+x,plicIntEnable))
+
+    plicIntPriorityThresholdArray = [] # iterates over number of different contexts
+    # 0x0C200000
+    plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:]
+    # 0x0C201000
+    plicIntPriorityThresholdArray += tokenize(rawPlicStateFile.readline())[1:]
+
+with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile:
+    for word in plicIntPriorityArray:
+        outFile.write(stripZeroes(word[2:])+'\n')
+with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile:
+    for word in plicIntEnableArray:
+        outFile.write(stripZeroes(word[2:])+'\n')
+with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile:
+    for word in plicIntPriorityThresholdArray:
+        outFile.write(stripZeroes(word[2:])+'\n')
+
+print("Finished parsing PLIC state!")
diff --git a/linux/testvector-generation/parseQEMUtoGDB.py b/linux/testvector-generation/parseQEMUtoGDB.py
new file mode 100755
index 000000000..aea5e057e
--- /dev/null
+++ b/linux/testvector-generation/parseQEMUtoGDB.py
@@ -0,0 +1,145 @@
+#! /usr/bin/python3
+import fileinput, sys
+
+parseState = "idle"
+beginPageFault = 0
+inPageFault = 0
+endPageFault = 0
+CSRs = {}
+pageFaultCSRs = {}
+regs = {}
+pageFaultRegs = {}
+instrs = {}
+instrCount = 0
+returnAdr = 0
+sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n")
+
+def printPC(l):
+    global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, instrCount
+    if not inPageFault:
+        inst = l.split()
+        if len(inst) > 3:
+            print(f'=> {inst[1]}:\t{inst[2]} {inst[3]}')
+        else:
+            print(f'=> {inst[1]}:\t{inst[2]}')
+        print(f'{inst[0]} 0x{inst[1]}')
+        instrCount += 1
+        if ((instrCount % 100000) == 0):
+            sys.stderr.write("QEMU parser reached "+str(instrCount)+" instrs\n")
+
+def printCSRs():
+    global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
+    global interrupt_line
+    if not inPageFault:
+        for (csr,val) in CSRs.items():
+            print('{}{}{:#x}  {}'.format(csr, ' '*(15-len(csr)), val, val))
+        print('-----') # end of current instruction
+        if len(interrupt_line)>0: # squish interrupts in between instructions
+            print(interrupt_line)
+            interrupt_line=""
+
+def parseCSRs(l):
+    global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs
+    if l.strip() and (not l.startswith("Disassembler")) and (not l.startswith("Please")):
+        # If we've hit the register file
+        if l.startswith(' x0/zero'): 
+            parseState = "regFile"
+            if not inPageFault:
+                instr = instrs[CSRs["pc"]]
+                printPC(instr)
+            parseRegs(l)
+        # If we've hit a CSR
+        else:
+            csr = l.split()[0]
+            val = int(l.split()[1],16)
+            # Commented out this conditional because the pageFault instrs don't corrupt CSRs
+            #if inPageFault:
+                # Not sure if these CSRs should be updated or not during page fault.
+                #if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
+                    # We do update some CSRs
+                #    CSRs[csr] = val
+                #else:
+                    # Others we preserve until changed later
+                #    pageFaultCSRs[csr] = val
+            #elif pageFaultCSRs and (csr in pageFaultCSRs):
+            #    if (val != pageFaultCSRs[csr]):
+            #        del pageFaultCSRs[csr]
+            #        CSRs[csr] = val
+            #else:
+            #    CSRs[csr] = val
+            #
+            # However SEPC and STVAL do get corrupted upon exiting
+            if endPageFault and ((csr == 'sepc') or (csr == 'stval')):
+                CSRs[csr] = returnAdr
+                pageFaultCSRs[csr] = val
+            elif pageFaultCSRs and (csr in pageFaultCSRs):
+                if (val != pageFaultCSRs[csr]):
+                    del pageFaultCSRs[csr]
+                    CSRs[csr] = val
+            else:
+                CSRs[csr] = val
+
+def parseRegs(l):
+    global parseState, inPageFault, CSRs, pageFaultCSRs, regs, pageFaultCSRs, instrs, pageFaultRegs
+    if "pc" in l:
+        printCSRs()
+        # New non-disassembled instruction
+        parseState = "CSRs"
+        parseCSRs(l)
+    elif l.startswith('--------'):
+        # End of disassembled instruction
+        printCSRs()
+        parseState = "idle"
+    else:
+        s = l.split()
+        for i in range(0,len(s),2):
+            if '/' in s[i]:
+                reg = s[i].split('/')[1]
+                val = int(s[i+1], 16)
+                if inPageFault:
+                    pageFaultRegs[reg] = val
+                else:
+                    if pageFaultRegs and (reg in pageFaultRegs):
+                        if (val != pageFaultRegs[reg]):
+                            del pageFaultRegs[reg]
+                            regs[reg] = val
+                    else:
+                        regs[reg] = val
+                    val = regs[reg]
+                    print('{}{}{:#x}  {}'.format(reg, ' '*(15-len(reg)), val, val))
+            else:
+                sys.stderr.write("Whoops. Expected a list of reg file regs; got:\n"+l)
+
+#############
+# Main Code #
+#############
+interrupt_line=""
+for l in fileinput.input():
+    #sys.stderr.write(l)
+    if l.startswith('riscv_cpu_do_interrupt'):
+        sys.stderr.write(l)
+        interrupt_line = l.strip('\n')
+    elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'):
+        break
+    elif l.startswith('IN:'):
+        # New disassembled instr
+        parseState = "instr"
+    elif (parseState == "instr") and l.startswith('0x'):
+        # New instruction
+        if "out of bounds" in l:
+            sys.stderr.write("Detected QEMU page fault error\n")
+            beginPageFault = not inPageFault
+            if beginPageFault:
+                returnAdr = int(l.split()[0][2:-1], 16)
+                sys.stderr.write('Saving SEPC of '+hex(returnAdr)+'\n')
+            inPageFault = 1
+        else: 
+            endPageFault = inPageFault
+            inPageFault = 0
+            adr = int(l.split()[0][2:-1], 16)
+            instrs[adr] = l
+        parseState = "CSRs"
+    elif parseState == "CSRs":
+        parseCSRs(l)
+    elif parseState == "regFile":
+        parseRegs(l)
diff --git a/linux/testvector-generation/parseState.py b/linux/testvector-generation/parseState.py
new file mode 100755
index 000000000..1f7e93c09
--- /dev/null
+++ b/linux/testvector-generation/parseState.py
@@ -0,0 +1,99 @@
+#! /usr/bin/python3
+import sys, os
+
+################
+# Helper Funcs #
+################
+
+def tokenize(string):
+    tokens = []
+    token = ''
+    whitespace = 0
+    prevWhitespace = 0
+    for char in string:
+        prevWhitespace = whitespace
+        whitespace = char in ' \t\n'
+        if (whitespace):
+            if ((not prevWhitespace) and (token != '')): 
+                tokens.append(token)
+            token = ''
+        else:
+            token = token + char
+    return tokens
+
+#############
+# Main Code #
+#############
+print("Begin parsing CPU state.")
+
+# Parse Args
+if len(sys.argv) != 2:
+    sys.exit('Error parseState.py expects 1 arg:\n parseState.py <path_to_checkpoint_dir>')
+outDir = sys.argv[1]+'/'
+stateGDBpath = outDir+'stateGDB.txt'
+if not os.path.exists(stateGDBpath):
+    sys.exit('Error input file '+stateGDBpath+'not found')
+
+singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv','sie','sip','sstatus']
+# priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery
+thirtyTwoBitCSRs = ['mcounteren','scounteren']
+listCSRs = ['hpmcounter','pmpaddr']
+pmpcfg = ['pmpcfg']
+
+# Initialize List CSR files to empty
+# (because later we'll open them in append mode)
+for csr in listCSRs+pmpcfg:
+    outFileName = 'checkpoint-'+csr.upper() 
+    outFile = open(outDir+outFileName, 'w')
+    outFile.close()
+
+# Initial State for Main Loop
+currState = 'regFile'
+regFileIndex = 0
+outFileName = 'checkpoint-RF'
+outFile = open(outDir+outFileName, 'w')
+
+# Main Loop
+with open(stateGDBpath, 'r') as stateGDB:
+    for line in stateGDB:
+        line = tokenize(line)
+        name = line[0]
+        val = line[1][2:]
+        if (currState == 'regFile'):
+            if (regFileIndex == 0 and name != 'zero'):
+                print('Whoops! Expected regFile registers to come first, starting with zero')
+                exit(1)
+            if (name != 'zero'):
+                # Wally doesn't need to know zero=0
+                outFile.write(val+'\n')
+            regFileIndex += 1
+            if (regFileIndex == 32):
+                outFile.close()
+                currState = 'CSRs'
+        elif (currState == 'CSRs'):
+            if name in singleCSRs: 
+                outFileName = 'checkpoint-'+name.upper() 
+                outFile = open(outDir+outFileName, 'w')
+                outFile.write(val+'\n')
+                outFile.close()
+            elif name in thirtyTwoBitCSRs: 
+                outFileName = 'checkpoint-'+name.upper() 
+                outFile = open(outDir+outFileName, 'w')
+                val = int(val,16) & 0xffffffff
+                outFile.write(hex(val)[2:]+'\n')
+                outFile.close()
+            elif name.strip('0123456789') in listCSRs:
+                outFileName = 'checkpoint-'+name.upper().strip('0123456789')
+                outFile = open(outDir+outFileName, 'a')
+                outFile.write(val+'\n')
+                outFile.close()
+            elif name.strip('0123456789') in pmpcfg:
+                outFileName = 'checkpoint-'+name.upper().strip('0123456789')
+                outFile = open(outDir+outFileName, 'a')
+                fourPmp = int(val,16)
+                for i in range(0,4):
+                    byte = (fourPmp >> 8*i) & 0xff
+                    outFile.write(hex(byte)[2:]+'\n')
+                outFile.close()
+
+print("Finished parsing CPU state!")
diff --git a/linux/testvector-generation/parseUartState.py b/linux/testvector-generation/parseUartState.py
new file mode 100755
index 000000000..611937054
--- /dev/null
+++ b/linux/testvector-generation/parseUartState.py
@@ -0,0 +1,50 @@
+#! /usr/bin/python3
+import sys, os
+
+################
+# Helper Funcs #
+################
+
+def tokenize(string):
+    tokens = []
+    token = ''
+    whitespace = 0
+    prevWhitespace = 0
+    for char in string:
+        prevWhitespace = whitespace
+        whitespace = char in ' \t\n'
+        if (whitespace):
+            if ((not prevWhitespace) and (token != '')): 
+                tokens.append(token)
+            token = ''
+        else:
+            token = token + char
+    return tokens
+
+#############
+# Main Code #
+#############
+print("Begin parsing UART state.")
+
+# Parse Args
+if len(sys.argv) != 2:
+    sys.exit('Error parseUartState.py expects 1 arg: <path_to_checkpoint_dir>')
+outDir = sys.argv[1]+'/'
+rawUartStateFile = outDir+'uartStateGDB.txt'
+if not os.path.exists(rawUartStateFile):
+    sys.exit('Error input file '+rawUartStateFile+'not found')
+
+with open(rawUartStateFile, 'r') as rawUartStateFile:
+    uartBytes = []
+    for i in range(0,8):
+        uartBytes += tokenize(rawUartStateFile.readline())[1:]
+with open(outDir+'checkpoint-UART_IER', 'w') as outFile:
+    outFile.write(uartBytes[1][2:])
+with open(outDir+'checkpoint-UART_LCR', 'w') as outFile:
+    outFile.write(uartBytes[3][2:])
+with open(outDir+'checkpoint-UART_MCR', 'w') as outFile:
+    outFile.write(uartBytes[4][2:])
+with open(outDir+'checkpoint-UART_SCR', 'w') as outFile:
+    outFile.write(uartBytes[7][2:])
+
+print("Finished parsing UART state!")
diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
new file mode 100644
index 000000000..56292c842
--- /dev/null
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -0,0 +1,136 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 1
+`define QEMU 1
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+`define MISA (32'h0014112D)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+`define COUNTERS 32
+`define DESIGN_COMPILER 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 1
+`define ICACHE 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 1
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
+// Address space
+`define RESET_VECTOR 64'h0000000000001000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       56'h80000000
+`define DTIM_RANGE      56'h00001FFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       56'h80000000
+`define IROM_RANGE      56'h00001FFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b1
+`define UNCORE_RAM_BASE       56'h80000000
+`define UNCORE_RAM_RANGE      56'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Bus Interface width
+`define AHBW 64
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 0
+
+// Hardware configuration
+`define UART_PRESCALE 0
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 53
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+
+`define HPTW_WRITES_SUPPORTED 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
new file mode 100644
index 000000000..16f7ca45d
--- /dev/null
+++ b/pipelined/config/fpga/wally-config.vh
@@ -0,0 +1,148 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 1
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+`define MISA (32'h0014112D)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+`define COUNTERS 32
+`define DESIGN_COMPILER 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 1
+`define ICACHE 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 1
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 64'h0000000000001000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       56'h80000000
+`define DTIM_RANGE      56'h00001FFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       56'h80000000
+`define IROM_RANGE      56'h00001FFF
+
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
+
+`define UNCORE_RAM_SUPPORTED 1'b0
+`define UNCORE_RAM_BASE       56'h100000000
+`define UNCORE_RAM_RANGE      56'h07FFFFFF
+
+`define EXT_MEM_SUPPORTED 1'b1
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+
+`define EXT_SUPPORTED 1'b0
+`define EXT_BASE       56'h80000000
+`define EXT_RANGE      56'h07FFFFFF
+
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b1
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Bus Interface width
+`define AHBW 64
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 0
+
+// Hardware configuration
+`define UART_PRESCALE 0
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 53
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define TESTSBP 1
+`define BPRED_SIZE 10
+
+
+`define HPTW_WRITES_SUPPORTED 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
new file mode 100644
index 000000000..f029e0e68
--- /dev/null
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -0,0 +1,140 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// E
+`define MISA (32'h00000010) 
+`define ZICSR_SUPPORTED 0
+`define ZIFENCEI_SUPPORTED 0
+`define COUNTERS 0
+`define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 0
+`define ICACHE 0
+`define VIRTMEM_SUPPORTED 0
+`define VECTORED_INTERRUPTS_SUPPORTED 0 
+`define BIGENDIAN_SUPPORTED 0
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 0
+`define DTLB_ENTRIES 0
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 1
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 0
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       34'h80000000
+`define DTIM_RANGE      34'h007FFFFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       34'h80000000
+`define IROM_RANGE      34'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b1
+`define UNCORE_RAM_BASE       34'h80000000
+`define UNCORE_RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b0
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b0
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 0
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
new file mode 100644
index 000000000..4d346e5a6
--- /dev/null
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -0,0 +1,139 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 1
+`define ICACHE 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 1
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       34'h80000000
+`define DTIM_RANGE      34'h007FFFFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       34'h80000000
+`define IROM_RANGE      34'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b1
+`define UNCORE_RAM_BASE       34'h80000000
+`define UNCORE_RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
new file mode 100644
index 000000000..7fb355c57
--- /dev/null
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -0,0 +1,140 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// I
+`define MISA (32'h00000104)
+`define ZICSR_SUPPORTED 0
+`define ZIFENCEI_SUPPORTED 0
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 0
+`define DCACHE 0
+`define ICACHE 0
+`define VIRTMEM_SUPPORTED 0
+`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define BIGENDIAN_SUPPORTED 0
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b1
+`define DTIM_BASE       34'h80000000
+`define DTIM_RANGE      34'h007FFFFF
+`define IROM_SUPPORTED 1'b1
+`define IROM_BASE       34'h80000000
+`define IROM_RANGE      34'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b0
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b0
+`define UNCORE_RAM_BASE       34'h80000000
+`define UNCORE_RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b0
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b0
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
new file mode 100644
index 000000000..311ce8ab2
--- /dev/null
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -0,0 +1,139 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+`define MISA (32'h00000104 | 1 << 20 | 1 << 18 )
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 0
+`define ICACHE 0
+`define VIRTMEM_SUPPORTED 0
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 0
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 0
+`define DTLB_ENTRIES 0
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 0
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define DTIM_SUPPORTED 1'b1
+`define DTIM_BASE       34'h80000000
+`define DTIM_RANGE      34'h007FFFFF
+`define IROM_SUPPORTED 1'b1
+`define IROM_BASE       34'h80000000
+`define IROM_RANGE      34'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b0
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b0
+`define UNCORE_RAM_BASE       34'h80000000
+`define UNCORE_RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
new file mode 100644
index 000000000..2df9867fa
--- /dev/null
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -0,0 +1,142 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification
+`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 1
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 1
+`define ICACHE 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 1
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW 64
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       56'h80000000
+`define DTIM_RANGE      56'h007FFFFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       56'h80000000
+`define IROM_RANGE      56'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b1
+`define UNCORE_RAM_BASE       56'h80000000
+`define UNCORE_RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
new file mode 100644
index 000000000..29148944f
--- /dev/null
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -0,0 +1,144 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification
+`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 1
+`define DCACHE 1
+`define ICACHE 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 1
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW 64
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Physical Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define DTIM_SUPPORTED 1'b0
+`define DTIM_BASE       56'h80000000
+`define DTIM_RANGE      56'h007FFFFF
+`define IROM_SUPPORTED 1'b0
+`define IROM_BASE       56'h80000000
+`define IROM_RANGE      56'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b1
+`define UNCORE_RAM_BASE       56'h80000000
+`define UNCORE_RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 1
+//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
new file mode 100644
index 000000000..c7304c724
--- /dev/null
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -0,0 +1,142 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification
+`define MISA (32'h00000104)
+`define ZICSR_SUPPORTED 0
+`define ZIFENCEI_SUPPORTED 0
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 0
+`define ZFH_SUPPORTED 0
+
+// LSU microarchitectural Features
+`define BUS 0
+`define DCACHE 0
+`define ICACHE 0
+`define VIRTMEM_SUPPORTED 0
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+`define BIGENDIAN_SUPPORTED 0
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 0
+`define DTLB_ENTRIES 0
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 512
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 512
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+`define IDIV_BITSPERCYCLE 4
+`define IDIV_ON_FPU 1
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 0
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW (`XLEN)
+
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 16
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define DTIM_SUPPORTED 1'b1
+`define DTIM_BASE       56'h80000000
+`define DTIM_RANGE      56'h007FFFFF
+`define IROM_SUPPORTED 1'b1
+`define IROM_BASE       56'h80000000
+`define IROM_RANGE      56'h007FFFFF
+`define BOOTROM_SUPPORTED 1'b0
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define UNCORE_RAM_SUPPORTED 1'b0
+`define UNCORE_RAM_BASE       56'h80000000
+`define UNCORE_RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b0
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b0
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define BPRED_ENABLED 0
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+`define BPRED_SIZE 10
+
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/config/shared/README b/pipelined/config/shared/README
similarity index 100%
rename from config/shared/README
rename to pipelined/config/shared/README
diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh
new file mode 100644
index 000000000..0acc12b86
--- /dev/null
+++ b/pipelined/config/shared/wally-constants.vh
@@ -0,0 +1,147 @@
+//////////////////////////////////////////
+// wally-constants.vh
+//
+// Written: tfleming@hmc.edu 4 March 2021
+// Modified: Kmacsaigoren@hmc.edu 31 May 2021
+//              Added constants for checking sv mode and changed existing constants to accomodate
+//              both sv48 and sv39
+//
+// Purpose: Specify constants nexessary for different memory virtualization modes.
+//              These are specific to sv49, defined in section 4.5 of the privileged spec.
+//              However, despite different constants for different modes, the hardware helps distinguish between
+//              each mode.
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// constants defining different privilege modes
+// defined in Table 1.1 of the privileged spec
+`define M_MODE (2'b11)
+`define S_MODE (2'b01)
+`define U_MODE (2'b00)
+
+// Virtual Memory Constants
+`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
+`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
+`define PPN_BITS (`XLEN==32 ? 22 : 44)
+`define PA_BITS (`XLEN==32 ? 34 : 56)
+`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
+`define ASID_BASE (`XLEN==32 ? 22 : 44)
+`define ASID_BITS (`XLEN==32 ? 9 : 16)
+
+// constants to check SATP_MODE against
+// defined in Table 4.3 of the privileged spec
+`define NO_TRANSLATE 0
+`define SV32 1
+`define SV39 8
+`define SV48 9
+
+// macros to define supported modes
+`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
+`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
+`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
+`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
+`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
+`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
+`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
+`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
+`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
+`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
+`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
+// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+
+// logarithm of XLEN, used for number of index bits to select
+`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
+
+// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
+
+// Floating point constants for Quad, Double, Single, and Half precisions
+`define Q_LEN 32'd128
+`define Q_NE 32'd15
+`define Q_NF 32'd112
+`define Q_BIAS 32'd16383
+`define Q_FMT 2'd3
+`define D_LEN 32'd64
+`define D_NE 32'd11
+`define D_NF 32'd52
+`define D_BIAS 32'd1023
+`define D_FMT 2'd1
+`define S_LEN 32'd32
+`define S_NE 32'd8
+`define S_NF 32'd23
+`define S_BIAS 32'd127
+`define S_FMT 2'd0
+`define H_LEN 32'd16
+`define H_NE 32'd5
+`define H_NF 32'd10
+`define H_BIAS 32'd15
+`define H_FMT 2'd2
+
+// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
+`define FLEN (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `S_LEN)
+`define NE   (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `S_NE)
+`define NF   (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `S_NF)
+`define FMT  (`Q_SUPPORTED ? 2'd3    : `D_SUPPORTED ? 2'd1    : 2'd0)
+`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
+/* Delete once tested dh 10/10/22
+
+`define FLEN (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `F_SUPPORTED ? `S_LEN  : `H_LEN)
+`define NE   (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `F_SUPPORTED ? `S_NE   : `H_NE)
+`define NF   (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `F_SUPPORTED ? `S_NF   : `H_NF) 
+`define FMT  (`Q_SUPPORTED ? 2'd3       : `D_SUPPORTED ? 2'd1       : `F_SUPPORTED ? 2'd0       : 2'd2)
+`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
+
+// Floating point constants needed for FPU paramerterization
+`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
+`define FMTBITS ((32)'(`FPSIZES>=3)+1)
+`define LEN1  ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN  : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN  : `H_LEN)
+`define NE1   ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE   : `H_NE)
+`define NF1   ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF   : `H_NF)
+`define FMT1  ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1    : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0    : 2'd2)
+`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
+`define LEN2  ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN  : `H_LEN)
+`define NE2   ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE   : `H_NE)
+`define NF2   ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF   : `H_NF)
+`define FMT2  ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0    : 2'd2)
+`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
+
+// largest length in IEU/FPU
+`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
+`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
+`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
+`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
+`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
+`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
+
+// division constants
+
+`define DIVN        (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
+`define LOGR        ($clog2(`RADIX))            // r = log(R)
+`define RK          (`LOGR*`DIVCOPIES)          // r*k used for intdiv preproc
+`define LOGRK       ($clog2(`RK))               // log2(r*k)
+`define FPDUR       ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
+`define DURLEN      ($clog2(`FPDUR+1))
+`define DIVb        (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
+`define DIVBLEN     ($clog2(`DIVb+1)-1)
+`define DIVa        (`DIVb+1-`XLEN)             // used for idiv on fpu
+
+// Disable spurious Verilator warnings
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off ASSIGNDLY */
+/* verilator lint_off PINCONNECTEMPTY */
diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
new file mode 100644
index 000000000..2fcb3af7a
--- /dev/null
+++ b/pipelined/config/shared/wally-shared.vh
@@ -0,0 +1,40 @@
+//////////////////////////////////////////
+// wally-shared.vh
+//
+// Written: david_harris@hmc.edu 7 June 2021
+//
+// Purpose: Shared and default configuration values common to all designs
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// division constants
+`define RADIX 32'h4
+`define DIVCOPIES 32'h4
+
+// eventually move to each config
+`define ZBA_SUPPORTED 0
+`define ZBB_SUPPORTED 0
+`define ZBC_SUPPORTED 0
+`define ZBS_SUPPORTED 0
+
+// Memory synthesis configuration
+`define USE_SRAM 0
+
+// shared constants
+`include "wally-constants.vh"
+
diff --git a/pipelined/misc/lzd.sv b/pipelined/misc/lzd.sv
new file mode 100644
index 000000000..5ca99bae1
--- /dev/null
+++ b/pipelined/misc/lzd.sv
@@ -0,0 +1,136 @@
+// V. G. Oklobdzija, "Algorithmic design of a hierarchical and modular
+//   leading zero detector circuit," in Electronics Letters, vol. 29,
+//   no. 3, pp. 283-284, 4 Feb. 1993, doi: 10.1049/el:19930193.
+      
+module lz2 (P, V, B0, B1);
+   
+   input logic B0;
+   input logic B1;
+
+   output logic P;
+   output logic V;
+
+   assign V = B0 | B1;
+   assign P = B0 & ~B1;
+   
+endmodule // lz2
+
+// Note: This module is not made out of two lz2's - why not? (MJS)
+
+module lz4 (ZP, ZV, B0, B1, V0, V1);
+
+   output logic [1:0] ZP;
+   output logic       ZV;
+   
+   input logic 	      B0;
+   input logic 	      B1;
+   input logic 	      V0;
+   input logic 	      V1;   
+
+   assign ZP[0] = V0 ? B0 : B1;
+   assign ZP[1] = ~V0;
+   assign ZV = V0 | V1;
+
+endmodule // lz4
+
+// Note: This module is not made out of two lz4's - why not? (MJS)
+
+module lz8 (ZP, ZV, B);
+   
+   input logic [7:0]  B;
+   
+   output logic [2:0] ZP;
+   output logic       ZV;
+   
+   logic        s1p0;
+   logic        s1v0;
+   logic        s1p1;
+   logic        s1v1;
+   logic        s2p0;
+   logic        s2v0;
+   logic        s2p1;
+   logic        s2v1;
+   logic [1:0]  ZPa;
+   logic [1:0]  ZPb;
+   logic        ZVa;
+   logic        ZVb;   
+   
+   lz2 l1(s1p0, s1v0, B[2], B[3]);
+   lz2 l2(s1p1, s1v1, B[0], B[1]);
+   lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1);
+
+   lz2 l4(s2p0, s2v0, B[6], B[7]);
+   lz2 l5(s2p1, s2v1, B[4], B[5]);
+   lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1);
+
+   assign ZP[1:0] = ZVb ? ZPb : ZPa;
+   assign ZP[2]   = ~ZVb;
+   assign ZV = ZVa | ZVb;
+
+endmodule // lz8
+
+module lz16 (ZP, ZV, B);
+
+   input logic [15:0]  B;
+   
+   output logic [3:0]  ZP;
+   output logic        ZV;
+   
+   logic [2:0] 	       ZPa;
+   logic [2:0] 	       ZPb;
+   logic 	       ZVa;
+   logic 	       ZVb;      
+
+   lz8 l1(ZPa, ZVa, B[7:0]);
+   lz8 l2(ZPb, ZVb, B[15:8]);
+
+   assign ZP[2:0] = ZVb ? ZPb : ZPa;
+   assign ZP[3]   = ~ZVb;
+   assign ZV = ZVa | ZVb;
+
+endmodule // lz16
+
+module lz32 (ZP, ZV, B);
+
+   input logic [31:0]  B;
+   
+   output logic [4:0]  ZP;
+   output logic        ZV;
+   
+   logic [3:0] 	       ZPa;
+   logic [3:0] 	       ZPb;
+   logic 	       ZVa;
+   logic 	       ZVb;
+   
+   lz16 l1(ZPa, ZVa, B[15:0]);
+   lz16 l2(ZPb, ZVb, B[31:16]);
+
+   assign ZP[3:0] = ZVb ? ZPb : ZPa;
+   assign ZP[4]   = ~ZVb;
+   assign ZV = ZVa | ZVb;
+
+endmodule // lz32
+
+// This module returns the number of leading zeros ZP in the 64-bit 
+// number B. If there are no ones in B, then ZP and ZV are both 0.
+
+module lz64 (ZP, ZV, B);
+
+   input logic [63:0]  B;
+   
+   output logic [5:0]  ZP;
+   output logic        ZV;
+   
+   logic [4:0] 	       ZPa;
+   logic [4:0] 	       ZPb;
+   logic 	       ZVa;
+   logic 	       ZVb;         
+
+   lz32 l1(ZPa, ZVa, B[31:0]);
+   lz32 l2(ZPb, ZVb, B[63:32]);
+
+   assign ZV = ZVa | ZVb;
+   assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}};
+   assign ZP[5]   = ~ZVb & ZV;
+
+endmodule // lz64
diff --git a/pipelined/radixcopiesmultiregression.sh b/pipelined/radixcopiesmultiregression.sh
new file mode 100755
index 000000000..1953b1da4
--- /dev/null
+++ b/pipelined/radixcopiesmultiregression.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+
+configFile=config/shared/wally-shared.vh
+
+searchRadix="define RADIX 32'"..
+searchCopies="define DIVCOPIES 32'"..
+
+currRadix="define RADIX 32'h2"
+currCopies="define DIVCOPIES 32'h1"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
+
+currRadix="define RADIX 32'h2"
+currCopies="define DIVCOPIES 32'h2"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
+
+currRadix="define RADIX 32'h2"
+currCopies="define DIVCOPIES 32'h4"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
+
+currRadix="define RADIX 32'h4"
+currCopies="define DIVCOPIES 32'h1"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
+
+currRadix="define RADIX 32'h4"
+currCopies="define DIVCOPIES 32'h2"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
+
+currRadix="define RADIX 32'h4"
+currCopies="define DIVCOPIES 32'h4"
+sed -i "s/$searchRadix/$currRadix/" $configFile
+sed -i "s/$searchCopies/$currCopies/" $configFile
+echo regression on Radix :$currRadix: and Copies :$currCopies:
+./regression/regression-wally
\ No newline at end of file
diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile
new file mode 100644
index 000000000..adc7bc718
--- /dev/null
+++ b/pipelined/regression/Makefile
@@ -0,0 +1,28 @@
+all: riscoftests memfiles
+	# *** Build old tests/imperas-riscv-tests for now;
+	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
+	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
+	#make -C ../../tests/imperas-riscv-tests --jobs
+	#make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs
+	# Only compile Imperas tests if they are installed locally.  
+	# They are usually a symlink to $RISCV/imperas-riscv-tests and only 
+	# get compiled there manually during installation
+	#make -C ../../addins/imperas-riscv-tests
+	#make -C ../../addins/imperas-riscv-tests XLEN=64
+	#cd ../../addins/imperas-riscv-tests; elf2hex.sh
+	#cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
+	# Link Linux test vectors 
+	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
+
+allclean: clean all
+
+clean:
+	make clean -C ../../tests/riscof
+#   make clean -C ../../tests/wally-riscv-arch-test
+#	make allclean -C ../../tests/imperas-riscv-tests
+
+riscoftests: 
+# 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
+	make -C ../../tests/riscof/ 
+memfiles:
+	make -f makefile-memfile wally-sim-files --jobs
diff --git a/pipelined/regression/buildrootBugFinder.py b/pipelined/regression/buildrootBugFinder.py
new file mode 100755
index 000000000..89a838d2f
--- /dev/null
+++ b/pipelined/regression/buildrootBugFinder.py
@@ -0,0 +1,41 @@
+#!/usr/bin/python3
+import sys, os, subprocess
+
+def main():
+    maxGoodCount = 400e6 # num instrs that execute sucessfully starting from 0
+    currInstrCount = maxGoodCount
+    linuxTestvectors = "/opt/riscv/linux-testvectors"
+    if not os.path.exists(linuxTestvectors):
+        sys.stderr.write("Error: Linux testvectors not found at "+linuxTestvectors+"\n")
+        exit(1)
+    checkpointList = [int(fileName.strip('checkpoint')) for fileName in os.listdir(linuxTestvectors) if 'checkpoint' in fileName]
+    checkpointList.sort()
+    
+    logDir = "./logs/buildrootBugFinderLogs/"
+    os.system("mkdir -p "+logDir)
+    summaryLogFilePath = logDir+"summary.log"
+    summaryLogFile = open(summaryLogFilePath,'w')
+    summaryLogFile.close()
+    while True:
+        checkpointList = [checkpoint for checkpoint in checkpointList if checkpoint > currInstrCount]
+        if len(checkpointList)==0:
+            break
+        checkpoint = checkpointList[0]
+        logFile = logDir+"checkpoint"+str(checkpoint)+".log"
+        runCommand="{\nvsim -c <<!\ndo wally-pipelined-batch.do buildroot buildroot /opt/riscv 0 "+str(checkpoint+1)+" "+str(checkpoint)+"\n!\n} | tee "+logFile 
+        print(runCommand)
+        os.system(runCommand)
+        try:
+            logOutput = subprocess.check_output(["grep","-e","Reached",logFile])
+            currInstrCount = int(str(logOutput).strip('b').strip('\'').strip('\\n').split(' ')[-2])
+        except subprocess.CalledProcessError:
+            currInstrCount = checkpoint
+        summaryStr="Checkpoint "+str(checkpoint)+" reached "+str(currInstrCount)+" instrs\n"
+        summaryLogFile = open(summaryLogFilePath,'a')
+        summaryLogFile.write(summaryStr)
+        summaryLogFile.close()
+
+    return 0
+
+if __name__ == '__main__':
+    exit(main())
diff --git a/sim/questa/fpga-wave.do b/pipelined/regression/fpga-wave.do
similarity index 99%
rename from sim/questa/fpga-wave.do
rename to pipelined/regression/fpga-wave.do
index ebff54cd3..e95443fbe 100644
--- a/sim/questa/fpga-wave.do
+++ b/pipelined/regression/fpga-wave.do
@@ -53,7 +53,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
 add wave -noupdate -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
-add wave -noupdate -group {Execution Stage} /testbench/functionName/functionName/FunctionName
+add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally
new file mode 100755
index 000000000..000b63402
--- /dev/null
+++ b/pipelined/regression/lint-wally
@@ -0,0 +1,22 @@
+#!/bin/bash
+# check for warnings in Verilog code
+# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
+export PATH=$PATH:/usr/local/bin/
+verilator=`which verilator`
+
+basepath=$(dirname $0)/..
+for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
+#for config in  rv64gc; do
+    echo "$config linting..."
+    if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+        echo "Exiting after $config lint due to errors or warnings"
+        exit 1
+    fi
+done
+echo "All lints run with no errors or warnings"
+
+# --lint-only just runs lint rather than trying to compile and simulate
+# -I points to the include directory where files such as `include wally-config.vh  are found
+
+# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
+# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do
new file mode 100644
index 000000000..d8bb0f3db
--- /dev/null
+++ b/pipelined/regression/linux-wave.do
@@ -0,0 +1,432 @@
+onerror {resume}
+quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/core/lsu/bus { &{/testbench/dut/core/lsu/LSUHTRANS[1], /testbench/dut/core/lsu/LSUHADDR }} test
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate -expand -group Testbench /testbench/reset_ext
+add wave -noupdate -expand -group Testbench -radix unsigned /testbench/InstrCountW
+add wave -noupdate -expand -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
+add wave -noupdate -expand -group Testbench -radix decimal /testbench/interruptInstrCount
+add wave -noupdate -expand -group Testbench /testbench/interruptCauseVal
+add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal
+add wave -noupdate -expand -group Testbench /testbench/interruptTVal
+add wave -noupdate -expand -group Testbench /testbench/interruptDesc
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {Decode Stage} /testbench/InstrDName
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -group {Execution Stage} /testbench/textE
+add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
+add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -expand -group {Memory Stage} /testbench/textM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
+add wave -noupdate -group {WriteBack stage} /testbench/PCW
+add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
+add wave -noupdate -group {WriteBack stage} /testbench/textW
+add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
+add wave -noupdate -group PCS /testbench/PCW
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
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+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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+add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
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+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
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+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
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+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
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+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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+add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
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+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
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+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
+add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
+add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
+add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F
+add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
+add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/funct
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/result
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srca
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srcb
+add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/width
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
+add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
+add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
+add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
+add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
+add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN
+add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb
+add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb
+add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb
+add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb
+add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
+add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
+add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate /testbench/dut/core/lsu/test
+add wave -noupdate {/testbench/dut/core/lsu/LSUHTRANS[1]}
+add wave -noupdate /testbench/dut/core/lsu/LSUHADDR
+add wave -noupdate /testbench/dut/core/lsu/LSUHTRANS
+add wave -noupdate /testbench/dut/core/lsu/HRDATA
+add wave -noupdate /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
+add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {15300495 ns} 1} {{Cursor 4} {4919381 ns} 1} {{Cursor 5} {4934568 ns} 0}
+quietly wave cursor active 5
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 314
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {4934554 ns} {4934778 ns}
diff --git a/pipelined/regression/make-tests.sh b/pipelined/regression/make-tests.sh
new file mode 100755
index 000000000..fe4555ff2
--- /dev/null
+++ b/pipelined/regression/make-tests.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+rm -r work*
+make allclean
+make
+# cd ../../tests/imperas-riscv-tests/
+# make allclean
+# make
+# cd ../wally-riscv-arch-test
+# make allclean
+# make
+# make XLEN=32
+# exe2memfile.pl work/*/*/*.elf
+# cd ../linux-testgen/linux-testvectors
+# ./tvLinker.sh
+# cd ../../../pipelined/regression
diff --git a/pipelined/regression/makefile-memfile b/pipelined/regression/makefile-memfile
new file mode 100644
index 000000000..646da5ac3
--- /dev/null
+++ b/pipelined/regression/makefile-memfile
@@ -0,0 +1,41 @@
+ROOT	:= ../..
+SUFFIX	:= work
+ARCHDIR	:= $(ROOT)/tests/riscof
+WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
+# IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
+# ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX)
+IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
+#ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) 
+ALLDIRS := $(ARCHDIR)/$(SUFFIX)
+
+ELFFILES	?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf")
+OBJDUMPFILES	?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf.objdump")
+MEMFILES ?= $(ELFFILES:.elf=.elf.memfile)
+ADDRFILES ?= $(OBJDUMPFILES:.objdump=.objdump.addr)
+
+print:
+	echo "files in $(ALLDIRS) are $(ELFFILES)."
+	echo "memfiles are $(MEMFILES)"
+
+.PHONY: all wally-sim-files
+all: wally-sim-files
+
+wally-sim-files: $(MEMFILES) $(ADDRFILES) 
+	echo "$@"
+
+# notes to self on how this works.
+# The find command locates all of the *.elf files in directory DIR1.  A list of .memfiles and
+# .addr files are generated from the .elf.  These are used as targets.
+# % is a wildcard in a make target which is then referenced as % in the depenecies and $*
+# in the recipe.
+# because elf2hex requires a bit width we use findstring to figure out if the compiled directory
+# is XLEN=64 or 32. This is hacky and will likely break in the future.
+# the .addr is a separate target so make can split into more jobs and more parallism.
+%.elf.memfile: %.elf
+	riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@
+
+%.elf.objdump.addr: %.elf.objdump
+	extractFunctionRadix.sh $<
+
+.PHONY: clean
+clean:
diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
new file mode 100755
index 000000000..6bbaa04b9
--- /dev/null
+++ b/pipelined/regression/regression-wally
@@ -0,0 +1,215 @@
+#!/usr/bin/python3
+##################################
+#
+# regression-wally
+# David_Harris@Hmc.edu 25 January 2021
+# Modified by Jarred Allen <jaallen@g.hmc.edu>
+#
+# Run a regression with multiple configurations in parallel and exit with
+# non-zero status code if an error happened, as well as printing human-readable
+# output.
+#
+##################################
+import sys,os,shutil
+
+class bcolors:
+    HEADER = '\033[95m'
+    OKBLUE = '\033[94m'
+    OKCYAN = '\033[96m'
+    OKGREEN = '\033[92m'
+    WARNING = '\033[93m'
+    FAIL = '\033[91m'
+    ENDC = '\033[0m'
+    BOLD = '\033[1m'
+    UNDERLINE = '\033[4m'
+
+from collections import namedtuple
+regressionDir = os.path.dirname(os.path.abspath(__file__))
+os.chdir(regressionDir)
+
+TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
+# name:     the name of this test configuration (used in printing human-readable
+#           output and picking logfile names)
+# cmd:      the command to run to test (should include the logfile as '{}', and
+#           the command needs to write to that file)
+# grepstr:  the string to grep through the log file for. The test succeeds iff
+#           grep finds that string in the logfile (is used by grep, so it may
+#           be any pattern grep accepts, see `man 1 grep` for more info).
+
+# edit this list to add more test cases
+configs = [
+    TestCase(
+        name="lints",
+        variant="all",
+        cmd="./lint-wally | tee {}",
+        grepstr="All lints run with no errors or warnings"
+    )
+]
+def getBuildrootTC(boot):
+    INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
+    MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
+    if boot:
+        name="buildrootboot"
+        BRcmd="vsim > {} -c <<!\ndo wally-pipelined.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
+        BRgrepstr="WallyHostname login:"
+    else:
+        name="buildroot"
+        BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
+        BRgrepstr=str(INSTR_LIMIT)+" instructions"
+    return  TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
+
+tc = TestCase(
+      name="buildroot-checkpoint",
+      variant="rv64gc",
+      cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
+      grepstr="400100000 instructions")
+configs.append(tc)
+
+tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
+tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
+for test in tests64gc:
+  tc = TestCase(
+        name=test,
+        variant="rv64gc",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+tests64i = ["arch64i"] 
+for test in tests64i:
+  tc = TestCase(
+        name=test,
+        variant="rv64i",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64i "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
+tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32zi", "wally32a",  "wally32priv", "wally32periph"]  
+for test in tests32gc:
+  tc = TestCase(
+        name=test,
+        variant="rv32gc",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32gc "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+tests32icimperas = ["imperas32i", "imperas32c"] # unused
+tests32ic = ["arch32i", "arch32c", "wally32periph"] 
+for test in tests32ic:
+  tc = TestCase(
+        name=test,
+        variant="rv32ic",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32ic "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+tests32i = ["arch32i"] 
+for test in tests32i:
+  tc = TestCase(
+        name=test,
+        variant="rv32i",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32i "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+
+tests32e = ["wally32e"] 
+for test in tests32e:
+  tc = TestCase(
+        name=test,
+        variant="rv32e",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32e "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+ahbTests = [("0", "0"), ("0", "1"), ("1", "0"), ("1", "1"), ("2", "0"), ("2", "1")] 
+for test in ahbTests:
+  tc = TestCase(
+        name="ram_latency_" + test[0] + "_burst_en_" + test[1],
+        variant="ahb",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+  
+
+import os
+from multiprocessing import Pool, TimeoutError
+
+def search_log_for_text(text, logfile):
+    """Search through the given log file for text, returning True if it is found or False if it is not"""
+    grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
+    return os.system(grepcmd) == 0
+
+def run_test_case(config):
+    """Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
+    logname = "logs/"+config.variant+"_"+config.name+".log"
+    cmd = config.cmd.format(logname)
+    print(cmd)
+    os.chdir(regressionDir)
+    os.system(cmd)
+    if search_log_for_text(config.grepstr, logname):
+        print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
+        return 0
+    else:
+        print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
+        print("  Check %s" % logname)
+        return 1
+
+def main():
+    """Run the tests and count the failures"""
+    global configs
+    try:
+        os.chdir(regressionDir)
+        os.mkdir("logs")
+        #print(os.getcwd())
+        #print(regressionDir)
+    except:
+        pass
+    try:
+        shutil.rmtree("wkdir")
+    except:
+        pass
+    finally:
+        os.mkdir("wkdir")
+ 
+    if '-makeTests' in sys.argv:
+        os.chdir(regressionDir)
+        os.system('./make-tests.sh | tee ./logs/make-tests.log')
+
+    if '-all' in sys.argv:
+        TIMEOUT_DUR = 30*7200 # seconds
+        configs.append(getBuildrootTC(boot=True))
+    elif '-buildroot' in sys.argv:
+        TIMEOUT_DUR = 30*7200 # seconds
+        configs=[getBuildrootTC(boot=True)]
+    else:
+        TIMEOUT_DUR = 10*60 # seconds
+        configs.append(getBuildrootTC(boot=False))
+
+    # Scale the number of concurrent processes to the number of test cases, but
+    # max out at a limited number of concurrent processes to not overwhelm the system
+    with Pool(processes=min(len(configs),40)) as pool:
+       num_fail = 0
+       results = {}
+       for config in configs:
+           results[config] = pool.apply_async(run_test_case,(config,))
+       for (config,result) in results.items():
+           try:
+             num_fail+=result.get(timeout=TIMEOUT_DUR)
+           except TimeoutError:
+             num_fail+=1
+             print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
+
+    # Count the number of failures
+    if num_fail:
+        print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
+        # Remind the user to try `make allclean`, since it may be needed if test
+        # cases have changed
+        print("Reminder: have you run `make allclean`?")
+    else:
+        print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
+    return num_fail
+
+if __name__ == '__main__':
+    exit(main())
diff --git a/pipelined/regression/sim-buildroot b/pipelined/regression/sim-buildroot
new file mode 100755
index 000000000..938bff866
--- /dev/null
+++ b/pipelined/regression/sim-buildroot
@@ -0,0 +1,33 @@
+#!/bin/bash
+
+# Defaults
+INSTR_LIMIT=0
+INSTR_WAVEON=1
+CHECKPOINT=0
+
+# Arg Parsing
+for i in "$@"; do
+  case $i in
+    --INSTR_LIMIT=*)
+      INSTR_LIMIT="${i#*=}"
+      shift # past argument=value
+      ;;
+    --INSTR_WAVEON=*)
+      INSTR_WAVEON="${i#*=}"
+      shift # past argument=value
+      ;;
+    --CHECKPOINT=*)
+      CHECKPOINT="${i#*=}"
+      shift # past argument=value
+      ;;
+    *)
+      # unknown option
+      ;;
+  esac
+done
+
+echo "INSTR_LIMIT  = ${INSTR_LIMIT}"
+echo "INSTR_WAVEON = ${INSTR_WAVEON}"
+echo "CHECKPOINT   = ${CHECKPOINT}"
+
+vsim -do "do ./wally-pipelined.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
diff --git a/pipelined/regression/sim-buildroot-batch b/pipelined/regression/sim-buildroot-batch
new file mode 100755
index 000000000..a8d4038ef
--- /dev/null
+++ b/pipelined/regression/sim-buildroot-batch
@@ -0,0 +1,36 @@
+#!/bin/bash
+
+# Defaults
+INSTR_LIMIT=0
+INSTR_WAVEON=1
+CHECKPOINT=0
+
+# Arg Parsing
+for i in "$@"; do
+  case $i in
+    --INSTR_LIMIT=*)
+      INSTR_LIMIT="${i#*=}"
+      shift # past argument=value
+      ;;
+    --INSTR_WAVEON=*)
+      INSTR_WAVEON="${i#*=}"
+      shift # past argument=value
+      ;;
+    --CHECKPOINT=*)
+      CHECKPOINT="${i#*=}"
+      shift # past argument=value
+      ;;
+    *)
+      # unknown option
+      ;;
+  esac
+done
+
+echo "INSTR_LIMIT  = ${INSTR_LIMIT}"
+echo "INSTR_WAVEON = ${INSTR_WAVEON}"
+echo "CHECKPOINT   = ${CHECKPOINT}"
+
+# *** change config from buildroot to rv64gc
+vsim -c <<!
+do wally-pipelined-batch.do buildroot buildroot-no-trace $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
+!
diff --git a/pipelined/regression/sim-testfloat b/pipelined/regression/sim-testfloat
new file mode 100755
index 000000000..7f22690c0
--- /dev/null
+++ b/pipelined/regression/sim-testfloat
@@ -0,0 +1,12 @@
+
+# cvtint - test integer conversion unit (fcvtint)
+# cvtfp  - test floating-point conversion unit (fcvtfp)
+# cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+# add    - test addition
+# fma    - test fma
+# sub    - test subtraction
+# div    - test division
+# sqrt   - test square root
+# all    - test everything
+
+vsim -do "do testfloat.do rv64fpquad $1"
diff --git a/pipelined/regression/sim-testfloat-batch b/pipelined/regression/sim-testfloat-batch
new file mode 100755
index 000000000..c7f28a55e
--- /dev/null
+++ b/pipelined/regression/sim-testfloat-batch
@@ -0,0 +1,12 @@
+
+# cvtint - test integer conversion unit (fcvtint)
+# cvtfp  - test floating-point conversion unit (fcvtfp)
+# cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+# add    - test addition
+# fma    - test fma
+# sub    - test subtraction
+# div    - test division
+# sqrt   - test square root
+# all    - test everything
+
+vsim -c -do "do testfloat.do rv64fpquad $1"
\ No newline at end of file
diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally
new file mode 100755
index 000000000..51c8b3edc
--- /dev/null
+++ b/pipelined/regression/sim-wally
@@ -0,0 +1,2 @@
+vsim -do "do wally-pipelined.do rv64gc arch64d"
+
diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch
new file mode 100755
index 000000000..e9a387d0a
--- /dev/null
+++ b/pipelined/regression/sim-wally-batch
@@ -0,0 +1 @@
+vsim -c -do "do wally-pipelined-batch.do rv32gc wally32priv"
diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/pipelined/regression/slack-notifier/slack-notifier.py
new file mode 100755
index 000000000..273299d23
--- /dev/null
+++ b/pipelined/regression/slack-notifier/slack-notifier.py
@@ -0,0 +1,32 @@
+#!/usr/bin/python3
+import os,sys,subprocess
+from datetime import datetime, timezone, timedelta
+
+if not os.path.isfile(sys.path[0]+'/slack-webhook-url.txt'):
+    print('==============================================================')
+    print('                             HOWDY!                           ')
+    print('slack-notifier.py can help let you know when your sim is done.')
+    print('To make it work, please supply your Slack bot webhook URL in:')
+    print(sys.path[0]+'/slack-webhook-url.txt')
+    print('Tutorial for slack webhook urls: https://bit.ly/BenSlackNotifier')
+    print('==============================================================')
+else:
+    urlFile = open(sys.path[0]+'/slack-webhook-url.txt','r')
+    url = urlFile.readline().strip('\n')
+
+    # Traverse 3 parents up the process tree
+    result = subprocess.check_output('ps -o ppid -p $PPID',shell=True)
+    PPID2 = str(result).split('\\n')[1]
+    result = subprocess.check_output('ps -o ppid -p '+PPID2,shell=True)
+    PPID3 = str(result).split('\\n')[1]
+    # Get command name
+    result = subprocess.check_output('ps -o cmd -p '+PPID3,shell=True)
+    cmdName = str(result).split('\\n')[1]
+    # Get current time
+    timezone_offset = -8.0  # Pacific Standard Time (UTC−08:00)
+    tzinfo = timezone(timedelta(hours=timezone_offset))
+    time = datetime.now(tzinfo).strftime('%I:%M %p')
+    # Send message
+    message = 'Command `'+cmdName+'` completed at '+time+' PST'
+    result = subprocess.run('curl -X POST -H \'Content-type: application/json\' --data \'{"text":"'+message+'"}\' '+url,shell=True,stdout=subprocess.DEVNULL,stderr=subprocess.DEVNULL)
+    print('Simulation stopped. Sending Slack message.')
diff --git a/pipelined/regression/testfloat.do b/pipelined/regression/testfloat.do
new file mode 100644
index 000000000..9b2c2b16d
--- /dev/null
+++ b/pipelined/regression/testfloat.do
@@ -0,0 +1,52 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+# $num = the added words after the call
+vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+
+vsim -voptargs=+acc work.testbenchfp -G TEST=$2
+
+view wave
+#-- display input and output signals as hexidecimal values
+#do ./wave-dos/peripheral-waves.do
+add log -recursive /*
+#do wave.do deal with when ready
+
+do wave-fpu.do
+
+#-- Run the Simulation 
+#run 3600 
+run -all
+noview testbench-fp.sv
+view wave
+
diff --git a/pipelined/regression/wally-harvard.do b/pipelined/regression/wally-harvard.do
new file mode 100644
index 000000000..e6050d2c7
--- /dev/null
+++ b/pipelined/regression/wally-harvard.do
@@ -0,0 +1,56 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
+# do wally-pipelined.do ../config/rv32ic
+#switch $argc {
+#    0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+#    1 {vlog +incdir+$1  +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+#}
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+vopt +acc work.testbench -G TEST=$2 -o workopt 
+vsim workopt
+
+view wave
+-- display input and output signals as hexidecimal values
+#do ./wave-dos/peripheral-waves.do
+add log -recursive /*
+do wave.do
+
+-- Run the Simulation 
+#run 3600 
+run -all
+#quit
+#noview ../testbench/testbench-imperas.sv
+noview ../testbench/testbench.sv
+view wave
diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do
new file mode 100644
index 000000000..1e70e2348
--- /dev/null
+++ b/pipelined/regression/wally-pipelined-batch.do
@@ -0,0 +1,99 @@
+# wally-pipelined-batch.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# Usage: do wally-pipelined-batch.do <config> <testcases>
+# Example: do wally-pipelined-batch.do rv32ic imperas-32i
+
+# Use this wally-pipelined-batch.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined-batch.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined-batch.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if {$2 eq "ahb"} {
+    if [file exists wkdir/work_${1}_${2}_${3}_${4}] {
+        vdel -lib wkdir/work_${1}_${2}_${3}_${4} -all
+    }
+    vlib wkdir/work_${1}_${2}_${3}_${4}
+} else {
+    if [file exists wkdir/work_${1}_${2}] {
+        vdel -lib wkdir/work_${1}_${2} -all
+    }
+    vlib wkdir/work_${1}_${2}
+}
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
+# do wally-pipelined-batch.do ../config/rv32ic rv32ic
+if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
+    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    # start and run simulation
+    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+    vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691  -fatal 7
+
+    run -all
+    run -all
+    exec ./slack-notifier/slack-notifier.py
+} elseif {$2 eq "buildroot-no-trace"} {
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    # start and run simulation
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt 
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+
+    #-- Run the Simulation
+    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
+    echo "Don't forget to change DEBUG_LEVEL = 0."
+    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
+    run -all
+    run -all
+    exec ./slack-notifier/slack-notifier.py
+
+} elseif {$2 eq "ahb"} {
+    vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596  +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    # start and run simulation
+    # remove +acc flag for faster sim during regressions if there is no need to access internal signals
+    vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt
+    vsim -lib wkdir/work_${1}_${2}_${3}_${4} testbenchopt  -fatal 7
+    # Adding coverage increases runtime from 2:00 to 4:29.  Can't run it all the time
+    #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
+    #vsim -coverage -lib work_$2 workopt_$2
+
+    # power add generates the logging necessary for said generation.
+    # power add -r /dut/core/*
+    run -all
+    # power off -r /dut/core/*
+} else {
+    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596
+    # start and run simulation
+    # remove +acc flag for faster sim during regressions if there is no need to access internal signals
+    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
+    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7
+    # Adding coverage increases runtime from 2:00 to 4:29.  Can't run it all the time
+    #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf
+    #vsim -coverage -lib work_$2 workopt_$2
+
+    # power add generates the logging necessary for said generation.
+    # power add -r /dut/core/*
+    run -all
+    # power off -r /dut/core/*
+} 
+
+#coverage report -file wally-pipelined-coverage.txt
+# These aren't doing anything helpful
+#coverage report -memory 
+#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
+#power report -all -bsaif power.saif
+quit
diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do
new file mode 100644
index 000000000..9d61511b7
--- /dev/null
+++ b/pipelined/regression/wally-pipelined.do
@@ -0,0 +1,124 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    # start and run simulation
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt 
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+
+    #-- Run the Simulation
+    #run -all
+    add log -recursive /*
+    do linux-wave.do
+    run -all
+
+    exec ./slack-notifier/slack-notifier.py
+    
+} elseif {$2 eq "buildroot-no-trace"} {
+    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    # start and run simulation
+    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt 
+    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829  -fatal 7
+
+    #-- Run the Simulation
+    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
+    echo "Don't forget to change DEBUG_LEVEL = 0."
+    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
+    #run 100 ns
+    #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
+    #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
+    run 14000 ms
+    #add log -recursive /*
+    #do linux-wave.do
+    #run -all
+
+    exec ./slack-notifier/slack-notifier.py
+
+} elseif {$2 eq "fpga"} {
+    echo "hello"
+    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063
+    vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
+    vsim workopt +nowarn3829  -fatal 7
+    
+    do fpga-wave.do
+    add log -r /*
+    run 20 ms
+
+} else {
+    if {$2 eq "ahb"} {
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
+    } else {
+        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
+        vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 
+    }
+    vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
+
+    vsim workopt +nowarn3829  -fatal 7
+
+    view wave
+    #-- display input and output signals as hexidecimal values
+    #do ./wave-dos/peripheral-waves.do
+    add log -recursive /*
+    do wave.do
+    #do wave-bus.do
+
+    # power add generates the logging necessary for saif generation.
+    #power add -r /dut/core/*
+    #-- Run the Simulation 
+
+    run -all
+    #power off -r /dut/core/*
+    #power report -all -bsaif power.saif
+    noview ../testbench/testbench.sv
+    view wave
+}
+
+
+
+#elseif {$2 eq "buildroot-no-trace""} {
+#    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
+    # start and run simulation
+#    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt 
+#    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
+
+    #-- Run the Simulation
+#    run 100 ns
+#    force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
+#    force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
+#    add log -recursive /*
+#    do linux-wave.do
+#    run -all
+
+#    exec ./slack-notifier/slack-notifier.py
+#} 
diff --git a/pipelined/regression/wave-all.do b/pipelined/regression/wave-all.do
new file mode 100644
index 000000000..f151680f3
--- /dev/null
+++ b/pipelined/regression/wave-all.do
@@ -0,0 +1,1606 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/memfilename
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/dut/core/ebu/ebu/IReadF
+add wave -noupdate /testbench/dut/core/DataStall
+add wave -noupdate /testbench/dut/core/InstrStall
+add wave -noupdate /testbench/dut/core/StallF
+add wave -noupdate /testbench/dut/core/StallD
+add wave -noupdate /testbench/dut/core/FlushD
+add wave -noupdate /testbench/dut/core/FlushE
+add wave -noupdate /testbench/dut/core/FlushM
+add wave -noupdate /testbench/dut/core/FlushW
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrF
+add wave -noupdate /testbench/InstrFName
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
+add wave -noupdate /testbench/InstrDName
+add wave -noupdate -divider <NULL>
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/InstrD
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate /testbench/dut/core/ieu/dp/PCSrcE
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/InstrMName
+add wave -noupdate /testbench/dut/uncore/uncore/ram/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/PCW
+add wave -noupdate /testbench/InstrWName
+add wave -noupdate /testbench/dut/core/ieu/dp/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdW
+add wave -noupdate -divider <NULL>
+add wave -noupdate -radix hexadecimal /testbench/clk
+add wave -noupdate -radix hexadecimal /testbench/reset
+add wave -noupdate -radix hexadecimal /testbench/test
+add wave -noupdate -radix hexadecimal /testbench/i
+add wave -noupdate -radix hexadecimal /testbench/errors
+add wave -noupdate -radix hexadecimal /testbench/totalerrors
+add wave -noupdate -radix hexadecimal /testbench/testadr
+add wave -noupdate -radix hexadecimal /testbench/InstrW
+add wave -noupdate -radix hexadecimal /testbench/meminit
+add wave -noupdate -radix hexadecimal /testbench/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/HADDR
+add wave -noupdate -radix hexadecimal /testbench/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/HBURST
+add wave -noupdate -radix hexadecimal /testbench/HPROT
+add wave -noupdate -radix hexadecimal /testbench/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/HCLK
+add wave -noupdate -radix hexadecimal /testbench/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/dut/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/core/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/FRegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/MemRWAlignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ReadDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrAckD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/UnalignedPCNextF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/misaligned
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/TrapMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallExceptResolveBranchesF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalCompInstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlusUpperF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
+add wave -noupdate -radix hexadecimal /testbench/PCW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/CompressedF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrRawD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/nop
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/InstrRawD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/IllegalCompInstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/instr16
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rds1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs1p
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs2p
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rds1p
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rdp
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILSP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILSPD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSSD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCL
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCLD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCI
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCB
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCIASP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCIW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCJ
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILUI
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immSH
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/op
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/OpD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct7b5D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/IllegalBaseInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/JumpD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/JumpE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUOpD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUControlD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcAD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcBD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/TargetSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/W64D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ControlsD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/aluc3D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/subD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sraD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltuD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchTakenE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/zeroE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltuE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUControlE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TargetSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCTargetE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCLinkW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardedSrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TargetBaseE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/IntResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/i
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmSrcD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmExtD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/Result
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/FlagsE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/a
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/amt
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/right
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/arith
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/w64
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/z
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/zshift
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/ylower
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/yupper
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/offset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/amt6
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d0
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d1
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d2
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d3
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/s
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/y
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/Funct3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWAlignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataMisalignedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/UnsignedLoadM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrPAdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReadF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IRData
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReadM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DSizeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DRData
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrAckD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemAckW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/GrantData
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/ISize
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATAMasked
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReady
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReady
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/UnsignedLoadM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATAMasked
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/ByteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HalfwordM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/genblk1/WordM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/InstrStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/DataStall
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/BranchFlushDE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallDCause
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallFCause
+add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallWCause
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ecallM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ebreakM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/wfiM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sfencevmaM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/BreakpointFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/EcallFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StorePageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/md
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sd
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegedM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalIEUInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ecallM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ebreakM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/wfiM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sfencevmaM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalPrivilegedInstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FlushW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SrcAM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRNReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRCReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSrcM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRWM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UnalignedNextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRCAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRMAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRSAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRUAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRNAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InsufficientCSRPrivilegeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/ExtIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IntInM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_WRITE_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_WRITE_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIPM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIPM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/FRegWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPP
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TSR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TVM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MXR
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SXL
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UXL
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_XS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS_INT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP_NEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UPIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/LoadStallD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRCReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/IllegalCSRCAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLEPlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRETPlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3PlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4PlusM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextCYCLEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextINSTRETM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER4M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteCYCLEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteINSTRETM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER3M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER4M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CounterNumM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/IllegalCSRMAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG01_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG23_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/allones
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVECM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMIDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSCRATCHM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCAUSEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVALM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTERENM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTINHIBITM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG0M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG2M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPADDR0M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISAbits
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SSTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/WriteSSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/IllegalCSRSAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/zero
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/allones
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_MASK
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVECM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSIDELEGM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSSCRATCHM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCAUSEM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVALM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSATPM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCOUNTERENM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCH_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVAL_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/load
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/val
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextEPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextCauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/USTATUS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/WriteUSTATUSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/IllegalCSRNAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUWriteM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSCAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRWriteValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUReadValM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/SetFflagsM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/IllegalCSRUAccessM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGS_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFFLAGSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFRMM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFCSRM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFRMM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFFLAGSM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/en
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clk
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clear
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/d
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/q
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/reset
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/IllegalInstrFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/BreakpointFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/EcallFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadPageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StorePageFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/mretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/sretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/uretM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegeModeW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextPrivilegeModeM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UEPC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTVEC_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIP_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIE_REGW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_MIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_SIE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MemAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/TrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTrapM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/RetM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegedNextPCM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/CauseM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextFaultMtvalM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIntGlobalEnM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SIntGlobalEnM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PendingIntsM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InterruptM
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/AdrF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd
+add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATAIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWRITE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HBURST
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HPROT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HTRANS
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HMASTLOCK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATAEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPEXT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADY
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/DataAccessFaultM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSin
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/PreHSELUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRW
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWtim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWclint
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWgpio
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWuart
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTIntr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Base
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Range
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HSEL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/match
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HRDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HSIZE
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATAIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HalfwordM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/WriteDataSubwordDuplicated
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteMaskM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/MemRWtim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HSELTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESPTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADYTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/busycount
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MemRWclint
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESPCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADYCLINT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/TimerIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/SwIntM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIMECMP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIME
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MSIP
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/MemRWgpio
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESPGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADYGPIO
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsIn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsOut
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsEn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_VAL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_EN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_EN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_VAL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MemRWuart
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESPUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADYUART
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DSRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DCDb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/CTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RIb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SOUT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DTRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT1b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT2b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/INTR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/TXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/A
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMWb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Din
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Dout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/BAUDOUTb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/A
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Din
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Dout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMWb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/INTR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXRDYb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/BAUDOUTb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SIN
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUT
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RTSb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DTRb
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT1b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT2b
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RBR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/FCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LSR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLL
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLM
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/IER
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MSR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MCR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbd
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbsync
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb2
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUTbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/loop
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLAB
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbaudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbaudpulse
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudcount
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoversampledcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txoversampledcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsreceived
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitssent
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstate
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txstate
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxshiftreg
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohead
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotail
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifohead
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifotail
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggerlevel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoentries
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoentries
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsexpected
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitsexpected
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXBR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxtimeoutcnt
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxcentered
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparity
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparitybit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstopbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparityerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoverrunerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxframingerr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbreak
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohaserr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoempty
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggered
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotimeout
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifodmaready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata9
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxerrbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfullbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXHR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/nexttxdata
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txnextbit
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhrfull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsrfull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txparity
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoempty
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifofull
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifodmaready
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifoenabled
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifodmamodesel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/evenparitysel
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxlinestatusintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataavailintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhremptyintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/modemstatusintr
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrpending
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrid
+add wave -noupdate -radix hexadecimal /testbench/it/clk
+add wave -noupdate -radix hexadecimal /testbench/it/reset
+add wave -noupdate -radix hexadecimal /testbench/it/FlushE
+add wave -noupdate -radix hexadecimal /testbench/it/InstrD
+add wave -noupdate -radix hexadecimal /testbench/it/InstrE
+add wave -noupdate -radix hexadecimal /testbench/it/InstrM
+add wave -noupdate -radix hexadecimal /testbench/it/InstrW
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/clk
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/reset
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/d
+add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/q
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/op
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/ddec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/edec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/edec/op
+add wave -noupdate -radix hexadecimal /testbench/it/edec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/edec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/edec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/op
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/mdec/imm
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/instr
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/op
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct3
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct7
+add wave -noupdate -radix hexadecimal /testbench/it/wdec/imm
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {330314 ns} 0} {{Cursor 3} {330384 ns} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 168
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {330283 ns} {330427 ns}
diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/pipelined/regression/wave-dos/ahb-muldiv.do
new file mode 100644
index 000000000..3170bc969
--- /dev/null
+++ b/pipelined/regression/wave-dos/ahb-muldiv.do
@@ -0,0 +1,100 @@
+restart -f
+delete wave /*
+view wave
+
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+
+# new
+#add wave /testbench/dut/core/ebu/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
+
+add wave -noupdate -divider -height 32 "MulDiv"
+add wave -hex /testbench/dut/core/mdu/*
+
+add wave -noupdate -divider -height 32 "Integer Divider"
+add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/CURRENT_STATE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/NEXT_STATE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/*
+
+add wave -noupdate -divider -height 32 "RF"
+add wave -hex /testbench/dut/core/ieu/dp/regf/*
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf
+
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+add wave /testbench/InstrDName
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/uncore/ram/memwrite
+add wave -hex /testbench/dut/uncore/uncore/HADDR
+add wave -hex /testbench/dut/uncore/uncore/HWDATA
+add wave -divider
+
+add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/ebu/HBURST
+add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/uncore/ram/*
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
+add wave /testbench/InstrWName
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/uncore/ram/*
+add wave -divider
+
+# appearance
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {100 ps}
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 250
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+set DefaultRadix hexadecimal
diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/pipelined/regression/wave-dos/ahb-waves.do
new file mode 100644
index 000000000..37a397d04
--- /dev/null
+++ b/pipelined/regression/wave-dos/ahb-waves.do
@@ -0,0 +1,89 @@
+# ahb-waves.do
+restart -f
+delete wave /*
+view wave
+
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+
+#add wave /testbench/dut/core/ebu/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
+
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+add wave /testbench/InstrDName
+add wave -hex /testbench/dut/core/ifu/ic/InstrRawD
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/uncore/ram/memwrite
+add wave -hex /testbench/dut/uncore/uncore/HADDR
+add wave -hex /testbench/dut/uncore/uncore/HWDATA
+add wave -divider
+
+add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/uncore/ram/*
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
+add wave /testbench/InstrWName
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
+add wave -divider
+
+add wave -hex /testbench/dut/uncore/uncore/ram/*
+add wave -divider
+
+add wave -hex -r /testbench/*
+
+# appearance
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {100 ps}
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 150
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+set DefaultRadix hexadecimal
diff --git a/pipelined/regression/wave-dos/cache-waves.do b/pipelined/regression/wave-dos/cache-waves.do
new file mode 100644
index 000000000..ff6e855ec
--- /dev/null
+++ b/pipelined/regression/wave-dos/cache-waves.do
@@ -0,0 +1,76 @@
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+
+#add wave /testbench/dut/core/ebu/ebu/IReadF
+add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
+
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+
+add wave /testbench/InstrDName
+add wave -divider
+
+
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/uncore/ram/memwrite
+add wave -hex /testbench/dut/uncore/uncore/HADDR
+add wave -hex /testbench/dut/uncore/uncore/HWDATA
+add wave -divider
+
+add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
+add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
+add wave -hex /testbench/dut/core/ebu/ebu/BusState
+add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
+add wave -hex /testbench/dut/core/ebu/ebu/HADDR
+add wave -hex /testbench/dut/core/ebu/ebu/HREADY
+add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
+add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
+add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
+add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM
+add wave -divider
+
+add wave /testbench/dut/core/ebu/ebu/CaptureDataM
+add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable
+add wave /testbench/dut/core/StallW
+add wave -hex /testbench/dut/core/ebu/ebu/CapturedData
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ifu/PCW
+add wave -hex /testbench/dut/core/ifu/InstrW
+add wave /testbench/InstrWName
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
+add wave -divider
+
+add wave -hex /testbench/dut/core/dmem/*
+add wave -hex /testbench/dut/core/dmem/genblk1/*
+add wave -divider
+
+add wave -hex -r /testbench/*
diff --git a/pipelined/regression/wave-dos/default-waves.do b/pipelined/regression/wave-dos/default-waves.do
new file mode 100644
index 000000000..2c7f0f755
--- /dev/null
+++ b/pipelined/regression/wave-dos/default-waves.do
@@ -0,0 +1,65 @@
+# default-waves.do
+restart -f
+delete wave /*
+view wave
+
+# Diplays All Signals recursively
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+#add wave /testbench/dut/core/ebu/ebu/IReadF
+#add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/ICacheStallF
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
+
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+add wave /testbench/InstrDName
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/uncore/ram/memwrite
+add wave -hex /testbench/dut/uncore/uncore/HADDR
+add wave -hex /testbench/dut/uncore/uncore/HWDATA
+add wave -divider
+add wave -hex /testbench/PCW
+add wave -hex /testbench/InstrW
+add wave /testbench/InstrWName
+add wave /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
+add wave -divider
+
+add wave -hex -r /testbench/*
+
+# appearance
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {100 ps}
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 150
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+set DefaultRadix hexadecimal
diff --git a/pipelined/regression/wave-dos/generic.do b/pipelined/regression/wave-dos/generic.do
new file mode 100644
index 000000000..1d59f3fbe
--- /dev/null
+++ b/pipelined/regression/wave-dos/generic.do
@@ -0,0 +1,23 @@
+# default-waves.do
+restart -f
+delete wave /*
+view wave
+
+# Diplays All Signals recursively
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+add wave -hex -r /testbench/*
+
+# appearance
+TreeUpdate [SetDefaultTree]
+WaveRestoreZoom {0 ps} {300 ps}
+configure wave -namecolwidth 350
+configure wave -valuecolwidth 150
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+set DefaultRadix hexadecimal
diff --git a/pipelined/regression/wave-dos/linux-waves.do b/pipelined/regression/wave-dos/linux-waves.do
new file mode 100644
index 000000000..102cfe24f
--- /dev/null
+++ b/pipelined/regression/wave-dos/linux-waves.do
@@ -0,0 +1,207 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider <NULL>
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate -radix decimal /testbench/errorCount
+add wave -noupdate -radix decimal /testbench/InstrCountW
+add wave -noupdate -divider Stalls_and_Flushes
+add wave -noupdate /testbench/dut/core/StallF
+add wave -noupdate /testbench/dut/core/StallD
+add wave -noupdate /testbench/dut/core/StallE
+add wave -noupdate /testbench/dut/core/StallM
+add wave -noupdate /testbench/dut/core/StallW
+add wave -noupdate /testbench/dut/core/FlushD
+add wave -noupdate /testbench/dut/core/FlushE
+add wave -noupdate /testbench/dut/core/FlushM
+add wave -noupdate /testbench/dut/core/FlushW
+add wave -noupdate -divider F
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
+add wave -noupdate -divider D
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
+add wave -noupdate /testbench/InstrDName
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidD
+add wave -noupdate -divider E
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
+add wave -noupdate /testbench/InstrEName
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -divider M
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
+add wave -noupdate /testbench/InstrMName
+add wave -noupdate /testbench/textM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemPAdrM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemRWM
+add wave -noupdate /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/ReadDataM
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/DTLBWalk
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/BasePageTablePPN
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/CurrentPPN
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MemWrite
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Executable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Writable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Readable
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Valid
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Misaligned
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MegapageMisaligned
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/LeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidLeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidNonLeafPTE
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/StartWalk
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TLBMiss
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/PRegEn
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextPageType
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/SvMode
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalkerState
+add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState
+add wave -noupdate -group LSU -r /testbench/dut/core/lsu/*
+add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/*
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState
+add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState
+add wave -noupdate -divider W
+add wave -noupdate -radix hexadecimal /testbench/PCW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW
+add wave -noupdate /testbench/textM
+add wave -noupdate /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group RF /testbench/dut/core/ieu/dp/RegWriteW
+add wave -noupdate -group RF -radix unsigned /testbench/dut/core/ieu/dp/RdW
+add wave -noupdate -group RF /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[2]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[3]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[4]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[5]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[6]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[7]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[8]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[9]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[10]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[11]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[12]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[13]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[14]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[15]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[16]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[17]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[18]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[19]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[20]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[21]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[22]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[23]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[24]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[25]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[26]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[27]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[28]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[29]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[30]}
+add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[31]}
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SATP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
+add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
+add wave -noupdate -divider <NULL>
+add wave -hex -r /testbench/*
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 8} {42752672 ns} 1} {{Cursor 2} {42752634 ns} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 297
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {42752559 ns} {42752771 ns}
diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/pipelined/regression/wave-dos/peripheral-waves.do
new file mode 100644
index 000000000..3f3974dc2
--- /dev/null
+++ b/pipelined/regression/wave-dos/peripheral-waves.do
@@ -0,0 +1,118 @@
+# peripheral-waves.do 
+
+restart -f
+delete wave /*
+view wave
+
+# general stuff
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider
+
+#add wave /testbench/dut/core/DataStall
+add wave /testbench/dut/core/StallF
+add wave /testbench/dut/core/StallD
+add wave /testbench/dut/core/StallE
+add wave /testbench/dut/core/StallM
+add wave /testbench/dut/core/StallW
+add wave /testbench/dut/core/FlushD
+add wave /testbench/dut/core/FlushE
+add wave /testbench/dut/core/FlushM
+add wave /testbench/dut/core/FlushW
+add wave -divider
+
+add wave -hex /testbench/dut/core/ifu/PCF
+add wave -hex /testbench/dut/core/ifu/PCD
+add wave -hex /testbench/dut/core/ifu/InstrD
+add wave -hex /testbench/dut/core/ieu/c/InstrValidD
+add wave /testbench/InstrDName
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCE
+add wave -hex /testbench/dut/core/ifu/InstrE
+add wave -hex /testbench/dut/core/ieu/c/InstrValidE
+add wave /testbench/InstrEName
+add wave -hex /testbench/dut/core/ieu/dp/SrcAE
+add wave -hex /testbench/dut/core/ieu/dp/SrcBE
+add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
+#add wave /testbench/dut/core/ieu/dp/PCSrcE
+add wave /testbench/dut/core/mdu/genblk1/div/DivStartE
+add wave /testbench/dut/core/mdu/DivBusyE
+add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM
+add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM
+
+add wave -divider
+add wave -hex /testbench/dut/core/ifu/PCM
+add wave -hex /testbench/dut/core/ifu/InstrM
+add wave -hex /testbench/dut/core/ieu/c/InstrValidM
+add wave /testbench/InstrMName
+add wave /testbench/dut/uncore/uncore/ram/memwrite
+add wave -hex /testbench/dut/core/WriteDataM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
+add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM
+add wave -divider
+add wave -hex /testbench/PCW
+#add wave -hex /testbench/InstrW
+#add wave -hex /testbench/dut/core/ieu/c/InstrValidW
+#add wave /testbench/InstrWName
+add wave -hex /testbench/dut/core/ReadDataW
+add wave -hex /testbench/dut/core/ieu/dp/ResultW
+add wave -hex /testbench/dut/core/ieu/dp/RegWriteW
+add wave -hex /testbench/dut/core/ieu/dp/WriteDataW
+add wave -hex /testbench/dut/core/ieu/dp/RdW
+add wave -divider
+add wave -hex /testbench/dut/core/priv/csr/TrapM
+add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM
+add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
+add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
+
+add wave -divider RegFile
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]
+add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]
+
+# peripherals
+add wave -divider PLIC
+add wave -hex /testbench/dut/core/priv/csr/TrapM
+add wave -hex /testbench/dut/uncore/uncore/plic/plic/*
+add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority
+add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray
+add wave -divider UART
+add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*
+add wave -divider GPIO
+add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*
+#add wave -divider
+#add wave -hex /testbench/dut/core/ebu/ebu/*
+#add wave -divider
+#add wave -divider
+
+# everything else
+add wave -hex -r /testbench/*
diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do
new file mode 100644
index 000000000..05ccb2154
--- /dev/null
+++ b/pipelined/regression/wave-fpu.do
@@ -0,0 +1,23 @@
+
+add wave -noupdate /testbenchfp/clk
+add wave -noupdate -radix decimal /testbenchfp/VectorNum
+add wave -noupdate /testbenchfp/FrmNum
+add wave -noupdate /testbenchfp/X
+add wave -noupdate /testbenchfp/Y
+add wave -noupdate /testbenchfp/Z
+add wave -noupdate /testbenchfp/Res
+add wave -noupdate /testbenchfp/Ans
+add wave -noupdate /testbenchfp/DivStart
+add wave -noupdate /testbenchfp/FDivBusyE
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/*
+add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/*
+add wave -group {Testbench} -noupdate /testbenchfp/*
+add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*
diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
new file mode 100644
index 000000000..be29ed870
--- /dev/null
+++ b/pipelined/regression/wave.do
@@ -0,0 +1,623 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/reset_ext
+add wave -noupdate /testbench/memfilename
+add wave -noupdate /testbench/dut/core/SATP_REGW
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
+add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
+add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
+add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {Decode Stage} /testbench/InstrDName
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group {WriteBack stage} /testbench/PCW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
+add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
+add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
+add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
+add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
+add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
+add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
+add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
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+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CaptureEn
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
+add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CacheBusAck
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE
+add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z
+add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
+add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
+quietly wave cursor active 5
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 194
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {118528 ns} {128752 ns}
diff --git a/src/ieu/bmu/ext.sv b/pipelined/src/bmu/bmu.sv
similarity index 56%
rename from src/ieu/bmu/ext.sv
rename to pipelined/src/bmu/bmu.sv
index c5dcbf531..ba6ab0b08 100644
--- a/src/ieu/bmu/ext.sv
+++ b/pipelined/src/bmu/bmu.sv
@@ -1,16 +1,17 @@
 ///////////////////////////////////////////
-// ext.sv
+// bmu.sv
 //
-// Written: Kevin Kim <kekim@hmc.edu>
-// Created: 4 February 2023
+// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023
 // Modified: 
 //
-// Purpose: Sign/Zero Extension Submodule
-//
-// Documentation: RISC-V System on Chip Design
+// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs
+//          Single-cycle operation in Execute stage
 // 
+// Documentation: n/a
+// See RISC-V Bit-Manipulation ISA-extensions
+//     Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,16 +29,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ext #(parameter WIDTH = 32) (
-  input  logic [15:0]      A,            // Operand to extend
-  input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
-  output logic [WIDTH-1:0] ExtResult);   // Extend Result
+`include "wally-config.vh"
 
-  logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult;
+module bmu(
+	input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
+  input  logic [31:0] 			InstrD,                           // instruction        
+  output logic              BMUE,                             // bit manipulation instruction  								
+	output logic [`XLEN-1:0] 	BMUResultE												// bit manipulation result
+);
+
+
+
+endmodule // mdu
 
-  assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]};
-  assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]};
-  assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
 
-  mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult);
-endmodule
diff --git a/src/cache/cache.sv b/pipelined/src/cache/cache.sv
similarity index 51%
rename from src/cache/cache.sv
rename to pipelined/src/cache/cache.sv
index b74ecdcff..72b97a313 100644
--- a/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -1,16 +1,15 @@
 ///////////////////////////////////////////
-// cache.sv
+// cache 
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Created: 7 July 2021
 // Modified: 20 January 2023
 //
 // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface
 //
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,21 +27,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module cache import cvw::*; #(parameter cvw_t P,
-                              parameter PA_BITS, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+`include "wally-config.vh"
+
+module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, DCACHE) (
   input  logic                   clk,
   input  logic                   reset,
   input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
   input  logic                   FlushStage,        // Pipeline flush of second stage (prevent writes and bus operations)
   // cpu side
   input  logic [1:0]             CacheRW,           // [1] Read, [0] Write 
+  input  logic [1:0]             CacheAtomic,       // Atomic operation
   input  logic                   FlushCache,        // Flush all dirty lines back to memory
   input  logic                   InvalidateCache,   // Clear all valid bits
-  input  logic [3:0]             CMOpM,              // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  input  logic [11:0]            NextSet,           // Virtual address, but we only use the lower 12 bits.
-  input  logic [PA_BITS-1:0]     PAdr,              // Physical address
+  input  logic [11:0]            NextAdr,           // Virtual address, but we only use the lower 12 bits.
+  input  logic [`PA_BITS-1:0]    PAdr,              // Physical address
   input  logic [(WORDLEN-1)/8:0] ByteMask,          // Which bytes to write (D$ only)
-  input  logic [WORDLEN-1:0]     WriteData,    // Data to write to cache (D$ only)
+  input  logic [WORDLEN-1:0]     CacheWriteData,    // Data to write to cache (D$ only)
   output logic                   CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
   output logic                   CacheStall,        // Cache stalls pipeline during multicycle operation
   output logic [WORDLEN-1:0]     ReadDataWord,      // Word read from cache (goes to CPU and bus)
@@ -50,90 +50,86 @@ module cache import cvw::*; #(parameter cvw_t P,
   output logic                   CacheMiss,         // Cache miss
   output logic                   CacheAccess,       // Cache access
   // lsu control
-  input  logic                   SelHPTW,           // Use PAdr from Hardware Page Table Walker rather than NextSet
+  input  logic                   SelHPTW,           // Use PAdr from Hardware Page Table Walker rather than NextAdr
   // Bus fsm interface
   input  logic                   CacheBusAck,       // Bus operation completed
   input  logic                   SelBusBeat,        // Word in cache line comes from BeatCount
   input  logic [LOGBWPL-1:0]     BeatCount,         // Beat in burst
   input  logic [LINELEN-1:0]     FetchBuffer,       // Buffer long enough to hold entire cache line arriving from bus
   output logic [1:0]             CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
-  output logic [PA_BITS-1:0]     CacheBusAdr        // Address for bus access
+  output logic [`PA_BITS-1:0]    CacheBusAdr        // Address for bus access
 );
 
   // Cache parameters
   localparam                     LINEBYTELEN = LINELEN/8;            // Line length in bytes
   localparam                     OFFSETLEN = $clog2(LINEBYTELEN);    // Number of bits in offset field
-  localparam                     SETLEN = $clog2(NUMSETS);          // Number of set bits
+  localparam                     SETLEN = $clog2(NUMLINES);          // Number of set bits
   localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
-  localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
-  localparam                     FLUSHADRTHRESHOLD = NUMSETS - 1;   // Used to determine when flush is complete
+  localparam                     TAGLEN = `PA_BITS - SETTOP;         // Number of tag bits
+  localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
+  localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
+  localparam                     FLUSHADRTHRESHOLD = NUMLINES - 1;   // Used to determine when flush is complete
+  localparam                     LOGLLENBYTES = $clog2(WORDLEN/8);   // Number of bits to address a word
 
-  logic                          SelAdrData;
-  logic                          SelAdrTag;
-  logic [1:0]                    AdrSelMuxSelData;
-  logic [1:0]                    AdrSelMuxSelTag, AdrSelMuxSelLRU;
-  logic [SETLEN-1:0]             CacheSetData;
-  logic [SETLEN-1:0]             CacheSetTag, CacheSetLRU;
+
+  logic                          SelAdr;
+  logic [1:0]                    AdrSelMuxSel;
+  logic [SETLEN-1:0]             CAdr;
   logic [LINELEN-1:0]            LineWriteData;
-  logic                          ClearDirty, SetDirty, SetValid, ClearValid;
+  logic                          ClearValid, ClearDirty, SetDirty, SetValid;
   logic [LINELEN-1:0]            ReadDataLineWay [NUMWAYS-1:0];
   logic [NUMWAYS-1:0]            HitWay, ValidWay;
-  logic                          Hit;
-  logic [NUMWAYS-1:0]            VictimWay, DirtyWay, HitDirtyWay;
-  logic                          LineDirty, HitLineDirty;
+  logic                          CacheHit;
+  logic [NUMWAYS-1:0]            VictimWay, DirtyWay;
+  logic                          LineDirty;
   logic [TAGLEN-1:0]             TagWay [NUMWAYS-1:0];
   logic [TAGLEN-1:0]             Tag;
-  logic [SETLEN-1:0]             FlushAdr;
+  logic [SETLEN-1:0]             FlushAdr, NextFlushAdr, FlushAdrP1;
   logic                          FlushAdrCntEn, FlushCntRst;
   logic                          FlushAdrFlag, FlushWayFlag;
   logic [NUMWAYS-1:0]            FlushWay, NextFlushWay;
   logic                          FlushWayCntEn;
   logic                          SelWriteback;
   logic                          LRUWriteEn;
+  logic                          SelFlush;
+  logic                          ResetOrFlushCntRst;
   logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
   logic                          SelFetchBuffer;
   logic                          CacheEn;
-  logic                          SelVictim;
-  logic [LINELEN/8-1:0]          LineByteMask;
-  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
-  genvar                         index;
+  logic [CACHEWORDSPERLINE-1:0]  MemPAdrDecoded;
+  logic [LINELEN/8-1:0]          LineByteMask, DemuxedByteMask, FetchBufferByteSel;
+  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0]          WordOffsetAddr;
+
+  genvar                      index;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Read Path
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  // Choose read address (CacheSet).  Normally use NextSet, but use PAdr during stalls
+  // Choose read address (CAdr).  Normally use NextAdr, but use PAdr during stalls
   // and FlushAdr when handling D$ flushes
   // The icache must update to the newest PCNextF on flush as it is probably a trap.  Trap
   // sets PCNextF to XTVEC and the icache must start reading the instruction.
-  assign AdrSelMuxSelData = {FlushCache, ((SelAdrData | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
-  mux3 #(SETLEN) AdrSelMuxData(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
-    AdrSelMuxSelData, CacheSetData);
-  assign AdrSelMuxSelTag = {FlushCache, ((SelAdrTag | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
-  mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
-    AdrSelMuxSelTag, CacheSetTag);
-
-  assign AdrSelMuxSelLRU = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
-  mux3 #(SETLEN) AdrSelMuxLRU(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
-    AdrSelMuxSelLRU, CacheSetLRU);
+  assign AdrSelMuxSel = {SelFlush, ((SelAdr | SelHPTW) & ~((DCACHE == 0) & FlushStage))};
+  mux3 #(SETLEN) AdrSelMux(NextAdr[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
+    AdrSelMuxSel, CAdr);
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
-    .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
-    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
-    .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
+  cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE) CacheWays[NUMWAYS-1:0](
+    .clk, .reset, .CacheEn, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
+    .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelWriteback, .VictimWay,
+    .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
-    cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU(
-      .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
-      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
+    cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
+      .clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage),
+      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
   end else 
     assign VictimWay = 1'b1; // one hot.
 
-  assign Hit = |HitWay;
+  assign CacheHit = |HitWay;
   assign LineDirty = |DirtyWay;
-  assign HitLineDirty = |HitDirtyWay;
 
   // ReadDataLineWay is a 2d array of cache line len by number of ways.
   // Need to OR together each way in a bitwise manner.
@@ -142,7 +138,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   or_rows #(NUMWAYS, TAGLEN) TagAOMux(.a(TagWay), .y(Tag));
 
   // Data cache needs to choose word offset from PAdr or BeatCount to writeback dirty lines
-  if(!READ_ONLY_CACHE) 
+  if(DCACHE) 
     mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), 
       .d1(BeatCount), .s(SelBusBeat),
       .y(WordOffsetAddr)); 
@@ -157,78 +153,56 @@ module cache import cvw::*; #(parameter cvw_t P,
     .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
   
   // Bus address for fetch, writeback, or flush writeback
-  mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
-    .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
-    .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
-    .s({FlushCache, SelWriteback}), .y(CacheBusAdr));
+  mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
+		.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
+		.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
+		.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path
   /////////////////////////////////////////////////////////////////////////////////////////////
-  if(!READ_ONLY_CACHE) begin:WriteSelLogic
-    logic [LINELEN/8-1:0]          DemuxedByteMask, FetchBufferByteSel;
 
-    // Adjust byte mask from word to cache line    
-    logic [LINELEN/8-1:0]          BlankByteMask;
-    assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
-    assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0;
-
-    assign DemuxedByteMask = BlankByteMask << ((MUXINTERVAL/8) * WordOffsetAddr);
-
-    assign FetchBufferByteSel = SetDirty ? ~DemuxedByteMask : '1;  // If load miss set all muxes to 1.
-
-    // Merge write data into fetched cache line for store miss
-    for(index = 0; index < LINELEN/8; index++) begin
-      mux2 #(8) WriteDataMux(.d0(WriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
-        .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index] & ~CMOpM[3]), .y(LineWriteData[8*index+7:8*index]));
-    end
-    assign LineByteMask = SetDirty ? DemuxedByteMask : '1;
+  // Adjust byte mask from word to cache line
+  onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
+  for(index = 0; index < 2**LOGCWPL; index++) begin
+    assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
   end
-  else
-    begin:WriteSelLogic
-      // No need for this mux if the cache does not handle writes.
-      assign LineWriteData = FetchBuffer;
-      assign LineByteMask = '1;
-    end
-  
+  assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
+  assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
+
+  // Merge write data into fetched cache line for store miss
+  for(index = 0; index < LINELEN/8; index++) begin
+    mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
+      .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
+  end
+   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed
-    logic                          ResetOrFlushCntRst;
-    logic [SETLEN-1:0]             NextFlushAdr, FlushAdrP1;
+  // Flush address (line number)
+  assign ResetOrFlushCntRst = reset | FlushCntRst;
+  flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
+  mux2    #(SETLEN) FlushAdrMux(NextFlushAdr, FlushAdrP1, FlushAdrCntEn, FlushAdr);
+  assign FlushAdrP1 = NextFlushAdr + 1'b1;
+  assign FlushAdrFlag = (NextFlushAdr == FLUSHADRTHRESHOLD[SETLEN-1:0]);
 
-    // Flush address (line number)
-    assign ResetOrFlushCntRst = reset | FlushCntRst;
-    flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
-    mux2    #(SETLEN) FlushAdrMux(NextFlushAdr, FlushAdrP1, FlushAdrCntEn, FlushAdr);
-    assign FlushAdrP1 = NextFlushAdr + 1'b1;
-    assign FlushAdrFlag = (NextFlushAdr == FLUSHADRTHRESHOLD[SETLEN-1:0]);
+  // Flush way
+  flopenl #(NUMWAYS) FlushWayReg(clk, FlushWayCntEn, ResetOrFlushCntRst, {{NUMWAYS-1{1'b0}}, 1'b1}, NextFlushWay, FlushWay);
+  if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
+  else            assign NextFlushWay = FlushWay[NUMWAYS-1];
+  assign FlushWayFlag = FlushWay[NUMWAYS-1];
 
-    // Flush way
-    flopenl #(NUMWAYS) FlushWayReg(clk, FlushWayCntEn, ResetOrFlushCntRst, {{NUMWAYS-1{1'b0}}, 1'b1}, NextFlushWay, FlushWay);
-    if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
-    else            assign NextFlushWay = FlushWay[NUMWAYS-1];
-    assign FlushWayFlag = FlushWay[NUMWAYS-1];
-  end // block: flushlogic
-  else begin:flushlogic // I$ is never flushed because it is never dirty
-    assign FlushWay = '0;
-    assign FlushWayFlag = 1'b0;
-    assign FlushAdrFlag = 1'b0;
-    assign FlushAdr = '0;
-  end
-   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Cache FSM
   /////////////////////////////////////////////////////////////////////////////////////////////
-  
-  cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
-    .FlushStage, .CacheRW, .Stall,
-    .Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, 
-    .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,
-    .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback,
-    .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
-    .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
-    .InvalidateCache, .CMOpM, .CacheEn, .LRUWriteEn);
+
+  cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
+		.FlushStage, .CacheRW, .CacheAtomic, .Stall,
+ 		.CacheHit, .LineDirty, .CacheStall, .CacheCommitted, 
+		.CacheMiss, .CacheAccess, .SelAdr, 
+		.ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush,
+		.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
+		.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
+    .InvalidateCache, .CacheEn, .LRUWriteEn);
 endmodule 
diff --git a/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv
similarity index 51%
rename from src/cache/cacheLRU.sv
rename to pipelined/src/cache/cacheLRU.sv
index 2ab3bac8d..be42036e0 100644
--- a/src/cache/cacheLRU.sv
+++ b/pipelined/src/cache/cacheLRU.sv
@@ -1,16 +1,15 @@
 ///////////////////////////////////////////
-// cacheLRU.sv
+// dcache (data cache)
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Created: 20 July 2021
 // Modified: 20 January 2023
 //
 // Purpose: Implements Pseudo LRU. Tested for Powers of 2.
 //
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,124 +27,121 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module cacheLRU
-  #(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) (
+  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
   input  logic                clk, 
-  input  logic                reset,
-  input  logic                FlushStage,
+  input  logic                reset, 
+  input  logic                FlushStage,      // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                CacheEn,         // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [NUMWAYS-1:0]  HitWay,          // Which way is valid and matches PAdr's tag
   input  logic [NUMWAYS-1:0]  ValidWay,        // Which ways for a particular set are valid, ignores tag
-  input  logic [SETLEN-1:0]   CacheSetLRU,     // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [SETLEN-1:0]   CAdr,            // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [SETLEN-1:0]   PAdr,            // Physical address 
   input  logic                LRUWriteEn,      // Update the LRU state
   input  logic                SetValid,        // Set the dirty bit in the selected way and set
   input  logic                InvalidateCache, // Clear all valid bits
+  input  logic                FlushCache,      // Flush all dirty lines back to memory
   output logic [NUMWAYS-1:0]  VictimWay        // LRU selects a victim to evict
 );
 
   localparam                           LOGNUMWAYS = $clog2(NUMWAYS);
 
-  logic [NUMWAYS-2:0]                  LRUMemory [NUMSETS-1:0];
-  logic [NUMWAYS-2:0]                  CurrLRU, NextLRU, ReadLRU, BypassedLRU;
-  logic [LOGNUMWAYS-1:0]               HitWayEncoded, Way;
+  logic [NUMWAYS-2:0]                  LRUMemory [NUMLINES-1:0];
+  logic [NUMWAYS-2:0]                  CurrLRU;
+  logic [NUMWAYS-2:0]                  NextLRU;
+  logic [NUMWAYS-1:0]                  Way;
+  logic [LOGNUMWAYS-1:0]               WayEncoded;
   logic [NUMWAYS-2:0]                  WayExpanded;
   logic                                AllValid;
-  logic                                ForwardLRU;
- 
+  
   genvar                               row;
 
   /* verilator lint_off UNOPTFLAT */
-  // Rose: For some reason verilator does not like this.  I checked and it is not a circular path.
+  // Ross: For some reason verilator does not like this.  I checked and it is not a circular path.
   logic [NUMWAYS-2:0]                  LRUUpdate;
   logic [LOGNUMWAYS-1:0] Intermediate [NUMWAYS-2:0];
   /* verilator lint_on UNOPTFLAT */
 
-  logic [NUMWAYS-1:0] FirstZero;
-  logic [LOGNUMWAYS-1:0] FirstZeroWay;
-  logic [LOGNUMWAYS-1:0] VictimWayEnc;
-
-  binencoder #(NUMWAYS) hitwayencoder(HitWay, HitWayEncoded);
-
   assign AllValid = &ValidWay;
 
   ///// Update replacement bits.
-  // coverage off
-  // Excluded from coverage b/c it is untestable without varying NUMWAYS.
   function integer log2 (integer value);
-    int val;
-    val = value;
-    for (log2 = 0; val > 0; log2 = log2+1)
-      val = val >> 1;
+    for (log2=0; value>0; log2=log2+1)
+      value = value>>1;
     return log2;
   endfunction // log2
-  // coverage on
 
   // On a miss we need to ignore HitWay and derive the new replacement bits with the VictimWay.
-  mux2 #(LOGNUMWAYS) WayMuxEnc(HitWayEncoded, VictimWayEnc, SetValid, Way);
+  mux2 #(NUMWAYS) WayMux(HitWay, VictimWay, SetValid, Way);
+  binencoder #(NUMWAYS) encoder(Way, WayEncoded);
 
   // bit duplication
   // expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
   for(row = 0; row < LOGNUMWAYS; row++) begin
     localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
-    localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
-    localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
-    assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{Way[row]}};
+    localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
+    localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
+    assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
   end
 
-  genvar               node;
+  genvar               r, a, s;
   assign LRUUpdate[NUMWAYS-2] = '1;
-  for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin : enables
-    localparam ctr = NUMWAYS - node - 1;
-    localparam ctr_depth = log2(ctr);
-    localparam lchild = node - ctr;
-    localparam rchild = lchild - 1;
-    localparam r = LOGNUMWAYS - ctr_depth;
-
-    // the child node will be updated if its parent was updated and
-    // the Way bit was the correct value.
-    // The if statement is only there for coverage since LRUUpdate[root] is always 1.
-    if (node == NUMWAYS-2) begin
-      assign LRUUpdate[lchild] = ~Way[r];
-      assign LRUUpdate[rchild] = Way[r];
-    end else begin
-      assign LRUUpdate[lchild] = LRUUpdate[node] & ~Way[r];
-      assign LRUUpdate[rchild] = LRUUpdate[node] & Way[r];
-    end
+  for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
+    localparam p = NUMWAYS - s - 1;
+    localparam g = log2(p);
+    localparam t0 = s - p;
+    localparam t1 = t0 - 1;
+    localparam r = LOGNUMWAYS - g;
+    assign LRUUpdate[t0] = LRUUpdate[s] & ~WayEncoded[r];
+    assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r];
   end
 
-  // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
-  assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2];
-  if (NUMWAYS > 2) mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
+  mux2 #(1) LRUMuxes[NUMWAYS-2:0](CurrLRU, ~WayExpanded, LRUUpdate, NextLRU);
 
   // Compute next victim way.
-  for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin
-    localparam t0 = 2*node - NUMWAYS;
+  for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin
+    localparam t0 = 2*s - NUMWAYS;
     localparam t1 = t0 + 1;
-    assign Intermediate[node] = CurrLRU[node] ? Intermediate[t0] : Intermediate[t1];
+    assign Intermediate[s] = CurrLRU[s] ? Intermediate[t0] : Intermediate[t1];
   end
-  for(node = NUMWAYS/2-1; node >= 0; node--) begin
-    localparam int0 = (NUMWAYS/2-1-node)*2;
+  for(s = NUMWAYS/2-1; s >= 0; s--) begin
+    localparam int0 = (NUMWAYS/2-1-s)*2;
     localparam int1 = int0 + 1;
-    assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
+	//localparam int0 = s*2;
+	//localparam int1 = int0 + 1;	
+    assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
   end
 
+  logic [NUMWAYS-1:0] FirstZero;
+  logic [LOGNUMWAYS-1:0] FirstZeroWay;
+  logic [LOGNUMWAYS-1:0] VictimWayEnc;
+  
   priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero);
   binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay);
   mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc);
+  //decoder #(LOGNUMWAYS) decoder (Intermediate[NUMWAYS-2], VictimWay);
   decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay);
 
-  // LRU memory must be reset for Questa to run. The reset value does not matter but it is best to be deterministc.
-  always_ff @(posedge clk)
-    if (reset | (InvalidateCache & ~FlushStage)) 
-      for (int set = 0; set < NUMSETS; set++) LRUMemory[set] <= '0; // exclusion-tag: initialize
-    else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU;
+  // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice.
+  // This is a two port memory.
+  // Every cycle must read from CAdr and each load/store must write the new LRU.
+  // this is still wrong.***************************
+  always_ff @(posedge clk) begin
+    if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
+    if(CacheEn) begin
+      if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
+      else if (LRUWriteEn & ~FlushStage) begin 
+        LRUMemory[PAdr] <= NextLRU;
+      end
+      if(LRUWriteEn & ~FlushStage & (PAdr == CAdr))
+        CurrLRU <= #1 NextLRU;
+      else 
+        CurrLRU <= #1 LRUMemory[CAdr];
+    end
+  end
 
-  // LRU read path with write forwarding
-  assign ReadLRU = LRUMemory[CacheSetLRU];
-  assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetLRU);
-  mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU);
-  flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU);
 endmodule
 
 
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
new file mode 100644
index 000000000..bc9982e59
--- /dev/null
+++ b/pipelined/src/cache/cachefsm.sv
@@ -0,0 +1,184 @@
+///////////////////////////////////////////
+// dcache (data cache) fsm
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 25 August 2021
+// Modified: 20 January 2023
+//
+// Purpose: Controller for the dcache fsm
+//
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+//
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module cachefsm (
+  input  logic       clk,
+  input  logic       reset,
+  // hazard and privilege unit
+  input  logic       Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
+  input  logic       FlushStage,        // Pipeline flush of second stage (prevent writes and bus operations)
+  output logic       CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
+  output logic       CacheStall,        // Cache stalls pipeline during multicycle operation
+  // inputs from IEU
+  input  logic [1:0] CacheRW,           // [1] Read, [0] Write 
+  input  logic [1:0] CacheAtomic,       // Atomic operation
+  input  logic       FlushCache,        // Flush all dirty lines back to memory
+  input  logic       InvalidateCache,   // Clear all valid bits
+  // Bus controls
+  input  logic       CacheBusAck,       // Bus operation completed
+  output logic [1:0] CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
+  // performance counter outputs
+  output logic       CacheMiss,         // Cache miss  
+  output logic       CacheAccess,		// Cache access
+
+  // cache internals
+  input  logic       CacheHit,          // Exactly 1 way hits
+  input  logic       LineDirty,         // The selected line and way is dirty
+  input  logic       FlushAdrFlag,      // On last set of a cache flush
+  input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
+  output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
+  output logic       ClearValid,        // Clear the valid bit in the selected way and set
+  output logic       SetValid,          // Set the dirty bit in the selected way and set
+  output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
+  output logic       SetDirty,          // Set the dirty bit in the selected way and set
+  output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback
+  output logic       LRUWriteEn,        // Update the LRU state
+  output logic       SelFlush,          // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
+  output logic       FlushAdrCntEn,     // Enable the counter for Flush Adr
+  output logic       FlushWayCntEn,     // Enable the way counter during a flush
+  output logic       FlushCntRst,       // Reset both flush counters
+  output logic       SelFetchBuffer,    // Bypass the SRAM for a load hit by directly using the read data from the ahbcacheinterface's FetchBuffer
+  output logic       CacheEn            // Enable the cache memory arrays.  Disable hold read data constant
+);
+  
+  logic               resetDelay;
+  logic               AMO, StoreAMO;
+  logic               AnyUpdateHit, AnyHit;
+  logic               AnyMiss;
+  logic               FlushFlag;
+    
+  typedef enum logic [3:0]{STATE_READY, // hit states
+                                   // miss states
+					               STATE_FETCH,
+					               STATE_WRITEBACK,
+					               STATE_WRITE_LINE,
+                                   STATE_READ_HOLD,  // required for back to back reads. structural hazard on writting SRAM
+                                   // flush cache 
+					               STATE_FLUSH,
+					               STATE_FLUSH_WRITEBACK} statetype;
+
+  (* mark_debug = "true" *) statetype CurrState, NextState;
+
+  assign AMO = CacheAtomic[1] & (&CacheRW);
+  assign StoreAMO = AMO | CacheRW[0];
+
+  assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache;
+  assign AnyUpdateHit = (StoreAMO) & CacheHit;
+  assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);  
+  assign FlushFlag = FlushAdrFlag & FlushWayFlag;
+
+  // outputs for the performance counters.
+  assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY;
+  assign CacheMiss = CacheAccess & ~CacheHit;
+
+  // special case on reset. When the fsm first exists reset the
+  // PCNextF will no longer be pointing to the correct address.
+  // But PCF will be the reset vector.
+  flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
+
+  always_ff @(posedge clk)
+    if (reset | FlushStage)    CurrState <= #1 STATE_READY;
+    else CurrState <= #1 NextState;  
+  
+  always_comb begin
+    NextState = STATE_READY;
+    case (CurrState)
+      STATE_READY: if(InvalidateCache)                      NextState = STATE_READY;
+                   else if(FlushCache)                      NextState = STATE_FLUSH;
+                   else if(AnyMiss & ~LineDirty)            NextState = STATE_FETCH;
+                   else if(AnyMiss & LineDirty)             NextState = STATE_WRITEBACK;
+                   else                                     NextState = STATE_READY;
+      STATE_FETCH: if(CacheBusAck)                          NextState = STATE_WRITE_LINE;
+                            else                            NextState = STATE_FETCH;
+      STATE_WRITE_LINE:                                     NextState = STATE_READ_HOLD;
+      STATE_READ_HOLD: if(Stall)                            NextState = STATE_READ_HOLD;
+                             else                           NextState = STATE_READY;
+      STATE_WRITEBACK: if(CacheBusAck)                      NextState = STATE_FETCH;
+                              else                          NextState = STATE_WRITEBACK;
+      // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
+      STATE_FLUSH: if(LineDirty)                            NextState = STATE_FLUSH_WRITEBACK;
+	               else if (FlushFlag)                      NextState = STATE_READ_HOLD;
+	               else                                     NextState = STATE_FLUSH;
+	  STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)   NextState = STATE_FLUSH;
+	                          else if(CacheBusAck)          NextState = STATE_READ_HOLD;
+	                          else                          NextState = STATE_FLUSH_WRITEBACK;
+      default:                                              NextState = STATE_READY;
+    endcase
+  end
+
+  // com back to CPU
+  assign CacheCommitted = CurrState != STATE_READY;
+  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | 
+                      (CurrState == STATE_FETCH) |
+                      (CurrState == STATE_WRITEBACK) |
+                      (CurrState == STATE_WRITE_LINE) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
+                      (CurrState == STATE_FLUSH) |
+                      (CurrState == STATE_FLUSH_WRITEBACK);
+  // write enables internal to cache
+  assign SetValid = CurrState == STATE_WRITE_LINE;
+  assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
+                    (CurrState == STATE_WRITE_LINE & (StoreAMO));
+  assign ClearValid = '0;
+  assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |
+                      (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
+  assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
+                      (CurrState == STATE_WRITE_LINE);
+  // Flush and eviction controls
+  assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
+                    (CurrState == STATE_READY & AnyMiss & LineDirty);
+
+  assign SelFlush = (CurrState == STATE_READY & FlushCache) |
+					(CurrState == STATE_FLUSH) | 
+					(CurrState == STATE_FLUSH_WRITEBACK);
+  assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
+						 (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
+  assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
+						 (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
+  assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
+						  (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
+  // Bus interface controls
+  assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | 
+                         (CurrState == STATE_FETCH & ~CacheBusAck) | 
+                         (CurrState == STATE_WRITEBACK & CacheBusAck);
+  assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
+                          (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
+                     (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
+
+  assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
+                  (CurrState == STATE_FETCH) |
+                  (CurrState == STATE_WRITEBACK) |
+                  (CurrState == STATE_WRITE_LINE) |
+                  resetDelay;
+
+  assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
+  assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache;
+                       
+endmodule // cachefsm
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
new file mode 100644
index 000000000..d3e996729
--- /dev/null
+++ b/pipelined/src/cache/cacheway.sv
@@ -0,0 +1,180 @@
+///////////////////////////////////////////
+// cacheway
+//
+// Written: Ross Thompson ross1728@gmail.com 
+// Created: 7 July 2021
+// Modified: 20 January 2023
+//
+// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
+// 
+// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
+				          OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) (
+  input  logic                        clk,
+  input  logic                        reset,
+  input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
+  input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
+  input  logic [$clog2(NUMLINES)-1:0] CAdr,           // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [`PA_BITS-1:0]         PAdr,           // Physical address 
+  input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
+  input  logic                        SetValid,       // Set the dirty bit in the selected way and set
+  input  logic                        ClearValid,     // Clear the valid bit in the selected way and set
+  input  logic                        SetDirty,       // Set the dirty bit in the selected way and set
+  input  logic                        ClearDirty,     // Clear the dirty bit in the selected way and set
+  input  logic                        SelWriteback,   // Overrides cached tag check to select a specific way and set for writeback
+  input  logic                        SelFlush,       // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
+  input  logic                        VictimWay,      // LRU selected this way as victim to evict
+  input  logic                        FlushWay,       // This way is selected for flush and possible writeback if dirty
+  input  logic                        InvalidateCache,//Clear all valid bits
+  input  logic [LINELEN/8-1:0]        LineByteMask,   // Final byte enables to cache (D$ only)
+
+  output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
+  output logic                        HitWay,         // This way hits
+  output logic                        ValidWay,       // This way is valid
+  output logic                        DirtyWay,       // This way is dirty
+  output logic [TAGLEN-1:0]           TagWay);        // THis way's tag if valid
+
+  localparam integer                  WORDSPERLINE = LINELEN/`XLEN;
+  localparam integer                  BYTESPERLINE = LINELEN/8;
+  localparam                          LOGWPL = $clog2(WORDSPERLINE);
+  localparam                          LOGXLENBYTES = $clog2(`XLEN/8);
+  localparam integer                  BYTESPERWORD = `XLEN/8;
+
+  logic [NUMLINES-1:0]                ValidBits;
+  logic [NUMLINES-1:0]                DirtyBits;
+  logic [LINELEN-1:0]                 ReadDataLine;
+  logic [TAGLEN-1:0]                  ReadTag;
+  logic                               Dirty;
+  logic                               SelTag;
+  logic                               SelectedWriteWordEn;
+  logic [LINELEN/8-1:0]               FinalByteMask;
+  logic                               SetValidEN;
+  logic                               SetValidWay;
+  logic                               ClearValidWay;
+  logic                               SetDirtyWay;
+  logic                               ClearDirtyWay;
+  logic                               SelNonHit;
+  logic                               SelData;
+  logic                               FlushWayEn, VictimWayEn;
+
+  // FlushWay and VictimWay are part of a one hot way selection.  Must clear them if FlushWay not selected
+  // or VictimWay not selected.
+  assign FlushWayEn = FlushWay & SelFlush;
+  assign VictimWayEn = VictimWay & SelWriteback;
+  
+  assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
+  
+  mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
+  //assign SelTag = VictimWay | FlushWay;
+  //assign SelData = HitWay | FlushWayEn | VictimWayEn;
+  
+  mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Write Enable demux
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  // RT: Can we merge these two muxes?  This is also shared in cacheLRU.
+  //mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelData);
+  //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData);
+
+  assign SetValidWay = SetValid & SelData;
+  assign ClearValidWay = ClearValid & SelData;
+  assign SetDirtyWay = SetDirty & SelData;
+  assign ClearDirtyWay = ClearDirty & SelData;
+  
+  // If writing the whole line set all write enables to 1, else only set the correct word.
+  assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
+  assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
+  assign SetValidEN = SetValidWay & ~FlushStage;
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Tag Array
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
+    .addr(CAdr), .dout(ReadTag), .bwe('1),
+    .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
+
+  
+
+  // AND portion of distributed tag multiplexer
+  assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
+  assign DirtyWay = SelTag & Dirty & ValidWay;
+  assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Data Array
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  genvar                             words;
+
+  localparam integer           SRAMLEN = 128;
+  localparam integer           NUMSRAM = LINELEN/SRAMLEN;
+  localparam integer           SRAMLENINBYTES = SRAMLEN/8;
+  localparam integer           LOGNUMSRAM = $clog2(NUMSRAM);
+  
+  for(words = 0; words < NUMSRAM; words++) begin: word
+    ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr),
+      .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
+  end
+
+  // AND portion of distributed read multiplexers
+  assign ReadDataLineWay = SelData ? ReadDataLine : '0;  // AND part of AO mux.
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Valid Bits
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  
+  always_ff @(posedge clk) begin // Valid bit array, 
+    if (reset) ValidBits        <= #1 '0;
+    if(CacheEn) begin 
+	  ValidWay <= #1 ValidBits[CAdr];
+	  if(InvalidateCache)                    ValidBits <= #1 '0;
+      else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CAdr] <= #1 SetValidWay;
+    end
+  end
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Dirty Bits
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  // Dirty bits
+  if (DIRTY_BITS) begin:dirty
+    always_ff @(posedge clk) begin
+      // reset is optional.  Consider merging with TAG array in the future.
+      //if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; 
+      if(CacheEn) begin
+        Dirty <= #1 DirtyBits[CAdr];
+        if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CAdr] <= #1 SetDirtyWay;
+      end
+    end
+  end else assign Dirty = 1'b0;
+
+
+endmodule
+
+
diff --git a/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv
similarity index 66%
rename from src/cache/subcachelineread.sv
rename to pipelined/src/cache/subcachelineread.sv
index 262992b52..346ec710e 100644
--- a/src/cache/subcachelineread.sv
+++ b/pipelined/src/cache/subcachelineread.sv
@@ -1,16 +1,15 @@
 ///////////////////////////////////////////
-// subcachelineread.sv
+// subcachelineread
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Created: 4 February 2022
 // Modified: 20 January 2023
 //
-// Purpose: Muxes the cache line down to the word size.  Also include possible save/restore registers/muxes.
+// Purpose: Muxes the cache line downto the word size.  Also include possilbe save/restore registers/muxes.
 //
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 7
 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,11 +27,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module subcachelineread #(parameter LINELEN, WORDLEN, 
-  parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
+  parameter MUXINTERVAL                                                        // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
+)(
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
-  input  logic [LINELEN-1:0]                     ReadDataLine,// Read data of the whole cacheline
-  output logic [WORDLEN-1:0]                     ReadDataWord // read data of selected word.
+  input  logic [LINELEN-1:0] 									  ReadDataLine,// Read data of the whole cacheline
+  output logic [WORDLEN-1:0] 									  ReadDataWord // read data of selected word.
 );
 
   localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
@@ -42,12 +44,13 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
   logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0]   ReadDataLinePad;
   logic [WORDLEN-1:0]                         ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
 
-  if (PADLEN > 0) assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
-  else            assign ReadDataLinePad = ReadDataLine;
+  if (PADLEN > 0) begin
+    assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
+  end else assign ReadDataLinePad = ReadDataLine;
 
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
-    assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
+	  assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
   end
   
   // variable input mux
diff --git a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v
new file mode 120000
index 000000000..c81975209
--- /dev/null
+++ b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v
@@ -0,0 +1 @@
+/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v
\ No newline at end of file
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv
new file mode 100644
index 000000000..a127e0fab
--- /dev/null
+++ b/pipelined/src/ebu/ahbcacheinterface.sv
@@ -0,0 +1,122 @@
+///////////////////////////////////////////
+// ahbcacheinterface.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: August 29, 2022
+// Modified: 18 January 2023
+//
+// Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
+//
+// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ahbcacheinterface #(
+  parameter integer BEATSPERLINE,  // Number of AHBW words (beats) in cacheline
+  parameter integer AHBWLOGBWPL,   // Log2 of ^
+  parameter integer LINELEN,       // Number of bits in cacheline
+  parameter integer LLENPOVERAHBW  // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+)(
+  input  logic                 HCLK, HRESETn,
+  // bus interface controls
+  input logic                 HREADY,                  // AHB peripheral ready
+  output logic [1:0]          HTRANS,                  // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic                HWRITE,                  // AHB 0: Read operation 1: Write operation 
+  output logic [2:0]          HSIZE,                   // AHB transaction width
+  output logic [2:0]          HBURST,                  // AHB burst length
+  // bus interface buses
+  input logic [`AHBW-1:0]     HRDATA,                  // AHB read data
+  output logic [`PA_BITS-1:0] HADDR,                   // AHB address
+  output logic [`AHBW-1:0]    HWDATA,                  // AHB write data
+  output logic [`AHBW/8-1:0]  HWSTRB,                  // AHB byte mask
+  
+  // cache interface
+  input logic [`PA_BITS-1:0]  CacheBusAdr,             // Address of cache line
+  input logic [`LLEN-1:0]     CacheReadDataWordM,      // one word of cache line during a writeback
+  input logic                 CacheableOrFlushCacheM,  // Memory operation is cacheable or flushing D$
+  input logic                 Cacheable,               // Memory operation is cachable
+  input logic [1:0]           CacheBusRW,              // Cache bus operation, 01: writeback, 10: fetch
+  output logic                CacheBusAck,             // Handshack to $ indicating bus transaction completed
+  output logic [LINELEN-1:0]  FetchBuffer,             // Register to hold beats of cache line as the arrive from bus
+  output logic [AHBWLOGBWPL-1:0]   BeatCount,               // Beat position within the cache line in the Address Phase
+  output logic                SelBusBeat,              // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
+
+  // uncached interface 
+  input logic [`PA_BITS-1:0]  PAdr,                    // Physical address of uncached memory operation
+  input logic [`LLEN-1:0]     WriteDataM,              // IEU write data for uncached store
+  input logic [1:0]           BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
+  input logic [2:0]           Funct3,                  // Size of uncached memory operation
+
+  // lsu/ifu interface
+  input logic                 Stall,                   // Core pipeline is stalled
+  input logic                 Flush,                   // Pipeline stage flush. Prevents bus transaction from starting
+  output logic                BusStall,                // Bus is busy with an in flight memory operation
+  output logic                BusCommitted);           // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
+  
+
+  localparam integer           BeatCountThreshold = BEATSPERLINE - 1;  // Largest beat index
+  logic [`PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
+  logic [AHBWLOGBWPL-1:0]           BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
+  logic                        CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
+  logic [`AHBW/8-1:0] 		   BusByteMaskM;                           // Byte enables within a word.  For cache request all 1s
+  logic [`AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
+
+  genvar                       index;
+
+  // fetch buffer is made of BEATSPERLINE flip-flops
+  for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
+    logic [BEATSPERLINE-1:0] CaptureBeat;
+    assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
+    flopen #(`AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
+      .q(FetchBuffer[(index+1)*`AHBW-1:index*`AHBW]));
+  end
+
+  mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR);
+  assign HADDR = ({{`PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(`AHBW/8)) + LocalHADDR;
+
+  mux2 #(3) sizemux(.d0(Funct3), .d1(`AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE));
+
+  // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
+  logic [`AHBW-1:0]          CacheReadDataWordAHB;
+  if(LLENPOVERAHBW > 1) begin
+    logic [`AHBW-1:0]          AHBWordSets [(LLENPOVERAHBW)-1:0];
+    genvar                     index;
+    for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
+	    assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)];
+    end
+    assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
+  end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];      
+  
+  mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
+     .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
+  flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
+
+  // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
+  // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
+  swbytemask #(`AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(`AHBW/8)-1:0]), .ByteMask(BusByteMaskM));
+  
+  flopen #(`AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[`AHBW/8-1:0], HWSTRB);
+  
+  buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm(
+    .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
+    .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
+	  .HREADY, .HTRANS, .HWRITE, .HBURST);
+endmodule
diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv
new file mode 100644
index 000000000..ff50f54f5
--- /dev/null
+++ b/pipelined/src/ebu/ahbinterface.sv
@@ -0,0 +1,73 @@
+///////////////////////////////////////////
+// ahbinterface.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: August 29, 2022
+// Modified: 18 January 2023
+//
+// Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
+// 
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ahbinterface #(
+  parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
+)( 
+  input logic 							HCLK, HRESETn,
+  // bus interface
+  input logic 							HREADY,       // AHB peripheral ready
+  output logic [1:0] 					HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic 							HWRITE,       // AHB 0: Read operation 1: Write operation 
+  input logic [`XLEN-1:0] 				HRDATA,       // AHB read data
+  output logic [`XLEN-1:0] 				HWDATA,       // AHB write data
+  output logic [`XLEN/8-1:0] 			HWSTRB,       // AHB byte mask
+  
+  // lsu/ifu interface
+  input logic 							Stall,        // Core pipeline is stalled
+  input logic 							Flush,        // Pipeline stage flush. Prevents bus transaction from starting
+  input logic [1:0] 					BusRW,        // Memory operation read/write control: 10: read, 01: write
+  input logic [`XLEN/8-1:0] 			ByteMask,     // Bytes enables within a word
+  input logic [`XLEN-1:0] 				WriteData,    // IEU write data for a store
+  output logic 							BusStall,     // Bus is busy with an in flight memory operation
+  output logic 							BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
+  output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus
+);
+  
+  logic                       CaptureEn;
+
+  localparam                  LEN = (LSU ? `XLEN : 32);   // 32 bits for IFU, XLEN for LSU
+  
+  flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
+
+  if(LSU) begin
+    // delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN    
+    flop #(`XLEN)   wdreg(HCLK, WriteData, HWDATA); 
+    flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
+  end else begin
+    assign HWDATA = '0;
+    assign HWSTRB = '0;
+  end    
+
+  busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
+    .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
+    .HTRANS, .HWRITE);
+endmodule
diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv
new file mode 100644
index 000000000..97002cabc
--- /dev/null
+++ b/pipelined/src/ebu/buscachefsm.sv
@@ -0,0 +1,151 @@
+///////////////////////////////////////////
+// busfsm.sv
+//
+// Written: Ross Thompson ross1728@gmail.com 
+// Created: December 29, 2021
+// Modified: 18 January 2023 
+//
+// Purpose: Controller for cache to AHB bus interface
+// 
+// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+`define BURST_EN 1         // Enables burst mode.  Disable to show the lost performance.
+
+// HCLK and clk must be the same clock!
+module buscachefsm #(
+  parameter integer BeatCountThreshold,              // Largest beat index
+  parameter integer AHBWLOGBWPL                      // Log2 of BEATSPERLINE
+)(
+  input  logic              HCLK,
+  input  logic              HRESETn,
+
+  // IEU interface
+  input  logic              Stall,                   // Core pipeline is stalled
+  input  logic              Flush,                   // Pipeline stage flush. Prevents bus transaction from starting
+  input  logic [1:0]        BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
+  output logic              BusStall,                // Bus is busy with an in flight memory operation
+  output logic              BusCommitted,            // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
+												    
+  // ahb cache interface locals.				    
+  output logic              CaptureEn,               // Enable updating the Fetch buffer with valid data from HRDATA
+												    
+  // cache interface							    
+  input  logic [1:0]        CacheBusRW,              // Cache bus operation, 01: writeback, 10: fetch
+  output logic              CacheBusAck,             // Handshack to $ indicating bus transaction completed
+  
+  // lsu interface
+  output logic [AHBWLOGBWPL-1:0] BeatCount,          // Beat position within the cache line in the Address Phase
+  output logic [AHBWLOGBWPL-1:0] BeatCountDelayed,   // Beat within the cache line in the second (Data) cache stage
+  output logic              SelBusBeat,              // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
+
+  // BUS interface
+  input  logic              HREADY,                  // AHB peripheral ready
+  output logic [1:0]        HTRANS,                  // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic              HWRITE,                  // AHB 0: Read operation 1: Write operation 
+  output logic [2:0]        HBURST                   // AHB burst length
+);
+  
+  typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK}               busstatetype;
+  typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
+
+  (* mark_debug = "true" *) busstatetype CurrState, NextState;
+
+  logic [AHBWLOGBWPL-1:0] NextBeatCount;
+  logic              FinalBeatCount;
+  logic [2:0]        LocalBurstType;
+  logic              BeatCntEn;
+  logic              BeatCntReset;
+  logic              CacheAccess;
+  
+  always_ff @(posedge HCLK)
+    if (~HRESETn | Flush)    CurrState <= #1 ADR_PHASE;
+    else CurrState <= #1 NextState;  
+  
+  always_comb begin
+	  case(CurrState)
+	    ADR_PHASE:  if (HREADY & |BusRW)                            NextState = DATA_PHASE;
+                  else if (HREADY & CacheBusRW[0])                  NextState = CACHE_WRITEBACK;
+                  else if (HREADY & CacheBusRW[1])                  NextState = CACHE_FETCH;
+                  else                                              NextState = ADR_PHASE;
+      DATA_PHASE: if(HREADY)                                        NextState = MEM3;
+		              else                                          NextState = DATA_PHASE;
+      MEM3: if(Stall)                                               NextState = MEM3;
+		           else                                             NextState = ADR_PHASE;
+      CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0])      NextState = CACHE_WRITEBACK;
+                   else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
+                   else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
+                   else                                             NextState = CACHE_FETCH;
+      CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0])  NextState = CACHE_WRITEBACK;
+                   else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
+                   else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
+                   else                                             NextState = CACHE_WRITEBACK;
+	    default:                                                    NextState = ADR_PHASE;
+	  endcase
+  end
+
+  // IEU, LSU, and IFU controls
+  // Used to store data from data phase of AHB.
+  flopenr #(AHBWLOGBWPL) BeatCountReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, NextBeatCount, BeatCount);  
+  flopenr #(AHBWLOGBWPL) BeatCountDelayedReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, BeatCount, BeatCountDelayed);
+  assign NextBeatCount = BeatCount + 1'b1;
+
+  assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[AHBWLOGBWPL-1:0];
+  assign BeatCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
+                     (NextState == ADR_PHASE & |CacheBusRW & HREADY);
+  assign BeatCntReset = NextState == ADR_PHASE;
+
+  assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
+  assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
+
+  assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
+					//(CurrState == DATA_PHASE & ~BusRW[0]) |  // *** replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
+					(CurrState == DATA_PHASE) | 
+          (CurrState == CACHE_FETCH & ~HREADY) |
+          (CurrState == CACHE_WRITEBACK & ~HREADY);
+  assign BusCommitted = CurrState != ADR_PHASE;
+
+  // AHB bus interface
+  assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) |
+                  (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
+                  (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
+
+  assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |BeatCount);
+  assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;  
+  
+  always_comb begin
+    case(BeatCountThreshold)
+      0:        LocalBurstType = 3'b000;
+      3:        LocalBurstType = 3'b011; // INCR4
+      7:        LocalBurstType = 3'b101; // INCR8
+      15:       LocalBurstType = 3'b111; // INCR16
+      default:  LocalBurstType = 3'b001; // INCR without end.
+    endcase
+  end
+
+  // communication to cache
+  assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount);
+  assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
+					            (CurrState == DATA_PHASE & BusRW[0]) |
+                      (CurrState == CACHE_WRITEBACK) |
+                      (CurrState == CACHE_FETCH);
+
+endmodule
diff --git a/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv
similarity index 54%
rename from src/ebu/busfsm.sv
rename to pipelined/src/ebu/busfsm.sv
index fbd6fe3f6..830253227 100644
--- a/src/ebu/busfsm.sv
+++ b/pipelined/src/ebu/busfsm.sv
@@ -1,16 +1,15 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Created: December 29, 2021
 // Modified: 18 January 2023
 //
 // Purpose: Simple NON_SEQ (no burst) AHB controller.
 //
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,10 +27,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 // HCLK and clk must be the same clock!
-module busfsm #(
-  parameter logic READ_ONLY
-)(
+module busfsm (
   input  logic       HCLK,
   input  logic       HRESETn,
 
@@ -39,7 +38,6 @@ module busfsm #(
   input  logic       Stall,        // Core pipeline is stalled
   input  logic       Flush,        // Pipeline stage flush. Prevents bus transaction from starting
   input  logic [1:0] BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input  logic       BusAtomic,    // Uncache atomic memory operation
   output logic       CaptureEn,    // Enable updating the Fetch buffer with valid data from HRDATA
   output logic       BusStall,     // Bus is busy with an in flight memory operation
   output logic       BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
@@ -49,44 +47,35 @@ module busfsm #(
   output logic       HWRITE        // AHB 0: Read operation 1: Write operation 
 );
   
-  typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, ATOMIC_READ_DATA_PHASE, ATOMIC_PHASE} busstatetype;
+  typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3}                                             busstatetype;
   typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
 
-  busstatetype CurrState, NextState;
+  (* mark_debug = "true" *) busstatetype CurrState, NextState;
 
   always_ff @(posedge HCLK)
-    if (~HRESETn | Flush) CurrState <= ADR_PHASE;
-    else                  CurrState <= NextState;  
+    if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
+    else                  CurrState <= #1 NextState;  
   
   always_comb begin
-      case(CurrState)
-        ADR_PHASE:  if(HREADY & |BusRW)          NextState = DATA_PHASE;
-                    else                         NextState = ADR_PHASE;
-        DATA_PHASE: if(HREADY & BusAtomic)       NextState = ATOMIC_READ_DATA_PHASE;
-                    else if(HREADY & ~BusAtomic) NextState = MEM3;
-                    else                         NextState = DATA_PHASE;
-        ATOMIC_READ_DATA_PHASE: if(HREADY)       NextState = ATOMIC_PHASE;
-                    else                         NextState = ATOMIC_READ_DATA_PHASE;
-        ATOMIC_PHASE: if(HREADY)                 NextState = MEM3;
-                      else                       NextState = ATOMIC_PHASE;
-        MEM3:       if(Stall)                    NextState = MEM3;
-                    else                         NextState = ADR_PHASE;
-        default:                                 NextState = ADR_PHASE;
-      endcase
+	  case(CurrState)
+	    ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
+                 else                  NextState = ADR_PHASE;
+      DATA_PHASE: if(HREADY)           NextState = MEM3;
+		          else                 NextState = DATA_PHASE;
+      MEM3: if(Stall)                  NextState = MEM3;
+		    else                       NextState = ADR_PHASE;
+	    default:                       NextState = ADR_PHASE;
+	  endcase
   end
 
   assign BusStall = (CurrState == ADR_PHASE & |BusRW) |
-//                  (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here.  fails uart test, but i'm not sure the failure is valid.
-                    (CurrState == ATOMIC_PHASE) |
-                    (CurrState == ATOMIC_READ_DATA_PHASE) |
-                    (CurrState == DATA_PHASE); 
+//					(CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here.  fails uart test, but i'm not sure the failure is valid.
+					(CurrState == DATA_PHASE); 
   
-  assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3);
-
-  assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) | 
-                  (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) ? AHB_NONSEQ : AHB_IDLE;
-  assign HWRITE = (BusRW[0] & ~BusAtomic) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic);
+  assign BusCommitted = CurrState != ADR_PHASE;
 
+  assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
+  assign HWRITE = BusRW[0];
   assign CaptureEn = CurrState == DATA_PHASE;
   
 endmodule
diff --git a/src/ebu/controllerinput.sv b/pipelined/src/ebu/controllerinputstage.sv
similarity index 52%
rename from src/ebu/controllerinput.sv
rename to pipelined/src/ebu/controllerinputstage.sv
index 9f644e1d3..681f12bc9 100644
--- a/src/ebu/controllerinput.sv
+++ b/pipelined/src/ebu/controllerinputstage.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
-// controllerinput.sv
+// controller input stage
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Created:  August 31, 2022
 // Modified: 18 January 2023
 //
@@ -11,10 +11,9 @@
 //          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -32,43 +31,44 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module controllerinput #(
-  parameter PA_BITS, 
+`include "wally-config.vh"
+
+module controllerinputstage #(
   parameter SAVE_ENABLED = 1           // 1: Save manager inputs if Save = 1, 0: Don't save inputs
 )(
-  input  logic                HCLK, 
-  input  logic                HRESETn,
-  input  logic                Save,     // Two or more managers requesting (HTRANS != 00) at the same time.  Save the non-granted manager inputs
-  input  logic                Restore,  // Restore a saved manager inputs when it is finally granted
-  input  logic                Disable,  // Suppress HREADY to the non-granted manager
-  output logic                Request,  // This manager is making a request
+  input logic 				  HCLK, 
+  input logic 				  HRESETn,
+  input logic 				  Save,     // Two or more managers requesting (HTRANS != 00) at the same time.  Save the non-granted manager inputs
+  input logic 				  Restore,  // Restore a saved manager inputs when it is finally granted
+  input logic 				  Disable,  // Supress HREADY to the non-granted manager
+  output logic 				  Request,  // This manager is making a request
   // controller input
-  input  logic [1:0]          HTRANSIn,  // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  input  logic                HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
-  input  logic [2:0]          HSIZEIn,   // Manager input. AHB transaction width
-  input  logic [2:0]          HBURSTIn,  // Manager input. AHB burst length
-  input  logic [PA_BITS-1:0]  HADDRIn,   // Manager input. AHB address
-  output logic                HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
+  input logic [1:0] 		  HTRANSIn,  // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  input logic 				  HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
+  input logic [2:0] 		  HSIZEIn,   // Manager input. AHB transaction width
+  input logic [2:0] 		  HBURSTIn,  // Manager input. AHB burst length
+  input logic [`PA_BITS-1:0]  HADDRIn,   // Manager input. AHB address
+  output logic 				  HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority
   // controller output
-  output logic [1:0]          HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation 
-  output logic [2:0]          HSIZEOut,  // Arbitrated manager transaction. AHB transaction width
-  output logic [2:0]          HBURSTOut, // Arbitrated manager transaction. AHB burst length 
-  output logic [PA_BITS-1:0]  HADDROut,  // Arbitrated manager transaction. AHB address
-  input  logic                HREADYIn   // Peripheral ready
+  output logic [1:0] 		  HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic 				  HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation 
+  output logic [2:0] 		  HSIZEOut,  // Aribrated manager transaction. AHB transaction width
+  output logic [2:0] 		  HBURSTOut, // Aribrated manager transaction. AHB burst length 
+  output logic [`PA_BITS-1:0] HADDROut,  // Aribrated manager transaction. AHB address
+  input logic 				  HREADYIn   // Peripherial ready
 );
 
   logic                       HWRITESave;
   logic [2:0]                 HSIZESave;
   logic [2:0]                 HBURSTSave;
   logic [1:0]                 HTRANSSave;
-  logic [PA_BITS-1:0]         HADDRSave;
+  logic [`PA_BITS-1:0]        HADDRSave;
 
   if (SAVE_ENABLED) begin
-    flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
+    flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
       {HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
-    mux2 #(1+3+3+2+PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
+    mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
       Restore,
       {HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});
@@ -84,3 +84,6 @@ module controllerinput #(
   assign HREADYOut = HREADYIn & ~Disable;
 
 endmodule
+  
+  
+   
diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv
new file mode 100644
index 000000000..bc162e08e
--- /dev/null
+++ b/pipelined/src/ebu/ebu.sv
@@ -0,0 +1,202 @@
+///////////////////////////////////////////
+// abhmulticontroller
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: August 29, 2022
+// Modified: 18 January 2023
+//
+// Purpose: AHB multi controller interface to merge LSU and IFU controls.
+//          See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
+//          Arbitrates requests from instruction and data streams
+//          Connects core to peripherals and I/O pins on SOC
+//          Bus width presently matches XLEN
+// 
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ebu (
+  input  logic                clk, reset,
+  // Signals from IFU
+  input  logic [1:0]          IFUHTRANS, // IFU AHB transaction request
+  input  logic [2:0]          IFUHSIZE,  // IFU AHB transaction size
+  input  logic [2:0]          IFUHBURST, // IFU AHB burst length
+  input  logic [`PA_BITS-1:0] IFUHADDR,  // IFU AHB address
+  output logic                IFUHREADY, // AHB peripheral ready gated by possible non-grant
+  // Signals from LSU
+  input  logic [1:0]          LSUHTRANS, // LSU AHB transaction request
+  input  logic                LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
+  input  logic [2:0]          LSUHSIZE,  // LSU AHB size
+  input  logic [2:0]          LSUHBURST, // LSU AHB burst length
+  input  logic [`PA_BITS-1:0] LSUHADDR,  // LSU AHB address
+  input  logic [`XLEN-1:0]    LSUHWDATA, // initially support AHBW = XLEN
+  input  logic [`XLEN/8-1:0]  LSUHWSTRB, // AHB byte mask
+  output logic                LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
+
+  // AHB-Lite external signals
+  (* mark_debug = "true" *) output logic HCLK, HRESETn, 
+  (* mark_debug = "true" *) input  logic HREADY,               // AHB peripheral ready
+  (* mark_debug = "true" *) input  logic HRESP,                // AHB peripheral response. 0: OK 1: Error
+  (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
+  (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,   // AHB Write data after arbitration
+  (* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
+  (* mark_debug = "true" *) output logic HWRITE,               // AHB transaction direction after arbitration
+  (* mark_debug = "true" *) output logic [2:0] HSIZE,          // AHB transaction size after arbitration
+  (* mark_debug = "true" *) output logic [2:0] HBURST,         // AHB burst length after arbitration
+  (* mark_debug = "true" *) output logic [3:0] HPROT,          // AHB protection.  Wally does not use
+  (* mark_debug = "true" *) output logic [1:0] HTRANS,         // AHB transaction request after arbitration
+  (* mark_debug = "true" *) output logic HMASTLOCK             // AHB master lock.  Wally does not use
+);
+
+  typedef enum                logic [1:0] {IDLE, ARBITRATE} statetype;
+  statetype                   CurrState, NextState;
+
+  logic                       LSUDisable;
+  logic 					  LSUSelect;
+  logic                       IFUSave;
+  logic 					  IFURestore;
+  logic 					  IFUDisable;
+  logic 					  IFUSelect;
+  logic                       both;                       // Both the LSU and IFU request at the same time
+
+  logic [`PA_BITS-1:0]        IFUHADDROut;
+  logic [1:0]                 IFUHTRANSOut;
+  logic [2:0]                 IFUHBURSTOut;
+  logic [2:0]                 IFUHSIZEOut;
+  logic                       IFUHWRITEOut;
+  
+  logic [`PA_BITS-1:0]        LSUHADDROut;
+  logic [1:0]                 LSUHTRANSOut;
+  logic [2:0]                 LSUHBURSTOut;
+  logic [2:0]                 LSUHSIZEOut;
+  logic                       LSUHWRITEOut;
+
+  logic                       IFUReq;
+  logic 					  LSUReq;
+
+  logic                       BeatCntEn;
+  logic [4-1:0]               NextBeatCount, BeatCount;   // Position within a burst transfer
+  logic                       FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
+  logic                       CntReset;
+  logic [3:0]                 Threshold;                  // Number of beats derived from HBURST
+  logic                       IFUReqD;                    // 1 cycle delayed IFU request. Part of arbitration
+  
+  
+  assign HCLK = clk;
+  assign HRESETn = ~reset;
+
+  // if two requests come in at once pick one to select and save the others Address phase
+  // inputs.  Abritration scheme is LSU always goes first.
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // input stages and muxing for IFU and LSU
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
+    .Request(IFUReq),
+    .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
+    .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
+    .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
+
+  // LSU always has priority so there should never be a need to save and restore the address phase inputs.
+  controllerinputstage #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
+    .Request(LSUReq),
+    .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
+    .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
+    .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
+
+  // output mux //*** switch to structural implementation
+  assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;
+  assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; 
+  assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
+  assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
+  assign HWRITE = LSUSelect ? LSUHWRITEOut : IFUSelect ? 1'b0 : '0;
+  assign HPROT = 4'b0011; // not used; see Section 3.7
+  assign HMASTLOCK = 0; // no locking supported
+
+  // data phase muxing.  This would be a mux if IFU wrote data.
+  assign HWDATA = LSUHWDATA;
+  assign HWSTRB = LSUHWSTRB;
+  // HRDATA is sent to all controllers at the core level.
+
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Aribtration scheme
+  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
+  // a burst is completed.
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  assign both = LSUReq & IFUReq;
+  flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
+  always_comb 
+    case (CurrState) 
+      IDLE: if (both)                                           NextState = ARBITRATE; 
+            else                                                NextState = IDLE;
+      ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq))  NextState = IDLE;
+                 else                                           NextState = ARBITRATE;
+      default:                                                  NextState = IDLE;
+    endcase
+
+  // basic arb always selects LSU when both
+  // replace this block for more sophisticated arbitration as needed.
+  // Controller 0 (IFU)
+  assign IFUSave = CurrState == IDLE & both;
+  assign IFURestore = CurrState == ARBITRATE;
+  assign IFUDisable = CurrState == ARBITRATE;
+  assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
+  // Controller 1 (LSU)
+  // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
+  // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
+  // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
+  // This is necessary because the pipeline is stalled for the entire duration of both transactions,
+  // and the LSU memory request will stil be active.
+  flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD);
+  assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
+  assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq;
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Burst mode logic
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount);  
+  assign NextBeatCount = BeatCount + 1'b1;
+
+  assign CntReset = NextState == IDLE;
+  assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
+  assign BeatCntEn = (NextState == ARBITRATE & HREADY);
+
+  // Used to store data from data phase of AHB.
+  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
+
+  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
+  always_comb begin
+    case(HBURST)
+      0:        Threshold = 4'b0000;
+      3:        Threshold = 4'b0011; // INCR4
+      5:        Threshold = 4'b0111; // INCR8
+      7:        Threshold = 4'b1111; // INCR16
+      default:  Threshold = 4'b0000; // INCR without end.
+    endcase
+  end
+  
+
+  
+endmodule
diff --git a/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv
similarity index 85%
rename from src/fpu/fclassify.sv
rename to pipelined/src/fpu/fclassify.sv
index 6f52b0eae..af159878f 100644
--- a/src/fpu/fclassify.sv
+++ b/pipelined/src/fpu/fclassify.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Floating-point classify unit
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,19 +25,20 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
 
-module fclassify import cvw::*;  #(parameter cvw_t P) (
+module fclassify (
   input  logic                Xs,         // sign bit
   input  logic                XNaN,       // is NaN
   input  logic                XSNaN,      // is signaling NaN
   input  logic                XSubnorm,   // is Subnormal
   input  logic                XZero,      // is zero
   input  logic                XInf,       // is infinity
-  output logic [P.XLEN-1:0]   ClassRes    // classify result
+  output logic [`XLEN-1:0]    ClassRes    // classify result
 );
 
   logic PInf, PZero, PNorm, PSubnorm;     // is the input a positive infinity/zero/normal/subnormal
-  logic NInf, NZero, NNorm, NSubnorm;     // is the input a negative infinity/zero/normal/subnormal
+  logic NInf, NZero, NNorm, NSubnorm;     // is the input a negitive infinity/zero/normal/subnormal
   logic XNorm;                            // is the input normal
   
   // determine the sub categories
@@ -63,6 +63,6 @@ module fclassify import cvw::*;  #(parameter cvw_t P) (
   //  bit 7 - +Inf
   //  bit 8 - signaling NaN
   //  bit 9 - quiet NaN
-  assign ClassRes = {{P.XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
+  assign ClassRes = {{`XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
 
 endmodule
diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv
new file mode 100755
index 000000000..3be33d997
--- /dev/null
+++ b/pipelined/src/fpu/fcmp.sv
@@ -0,0 +1,160 @@
+
+///////////////////////////////////////////
+// fcmp.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: Floating-point comparison unit
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+// OpCtrl values
+//    110   min
+//    101   max
+//    010   equal
+//    001   less than
+//    011   less than or equal
+
+module fcmp (   
+  input  logic [`FMTBITS-1:0]   Fmt,           // format of fp number
+  input  logic [2:0]            OpCtrl,        // see above table
+  input  logic                  Xs, Ys,        // input signs
+  input  logic [`NE-1:0]        Xe, Ye,        // input exponents
+  input  logic [`NF:0]          Xm, Ym,        // input mantissa
+  input  logic                  XZero, YZero,  // is zero
+  input  logic                  XNaN, YNaN,    // is NaN
+  input  logic                  XSNaN, YSNaN,  // is signaling NaN
+  input  logic [`FLEN-1:0]      X, Y,          // original inputs (before unpacker)
+  output logic                  CmpNV,         // invalid flag
+  output logic [`FLEN-1:0]      CmpFpRes,      // compare floating-point result
+  output logic [`XLEN-1:0]      CmpIntRes      // compare integer result
+);
+
+  logic LTabs, LT, EQ;         // is X < or > or = Y
+  logic [`FLEN-1:0] NaNRes;    // NaN result
+  logic BothZero;              // are both inputs zero
+  logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN
+  
+  assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
+  assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
+  assign EQ = (X == Y);
+
+  assign BothZero = XZero&YZero;
+  assign EitherNaN = XNaN|YNaN;
+  assign EitherSNaN = XSNaN|YSNaN;
+
+
+  // flags
+  //    Min/Max - if an input is a signaling NaN set invalid flag
+  //    LT/LE - signaling - sets invalid if NaN input
+  //    EQ - quiet - sets invalid if signaling NaN input
+  always_comb begin
+    case (OpCtrl[2:0])
+        3'b110: CmpNV = EitherSNaN;//min 
+        3'b101: CmpNV = EitherSNaN;//max
+        3'b010: CmpNV = EitherSNaN;//equal
+        3'b001: CmpNV = EitherNaN;//less than
+        3'b011: CmpNV = EitherNaN;//less than or equal
+        default: CmpNV = 1'bx;
+    endcase
+  end 
+
+  // fmin/fmax of two NaNs returns a quiet NaN of the appropriate size
+  // for IEEE, return the payload of X
+  // for RISC-V, return the canonical NaN
+
+  // select the NaN result
+  if (`FPSIZES == 1)
+    if(`IEEE754) assign NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+    else         assign NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+
+  else if (`FPSIZES == 2) 
+    if(`IEEE754) assign NaNRes = Fmt ? {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
+    else         assign NaNRes = Fmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+  
+  else if (`FPSIZES == 3)
+    always_comb
+          case (Fmt)
+              `FMT:  
+                if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+                else         NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+              `FMT1:
+                if(`IEEE754) NaNRes = {{`FLEN-`LEN1{1'b1}}, Xs, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
+                else         NaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+              `FMT2:
+                if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, Xs, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
+                else         NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
+              default:        NaNRes = {`FLEN{1'bx}};
+          endcase
+
+  else if (`FPSIZES == 4)
+    always_comb
+          case (Fmt)
+              2'h3:  
+                if(`IEEE754) NaNRes = {Xs, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+                else         NaNRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+              2'h1:  
+                if(`IEEE754) NaNRes = {{`FLEN-`D_LEN{1'b1}}, Xs, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
+                else         NaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+              2'h0: 
+                if(`IEEE754) NaNRes = {{`FLEN-`S_LEN{1'b1}}, Xs, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
+                else         NaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+              2'h2:
+                if(`IEEE754) NaNRes = {{`FLEN-`H_LEN{1'b1}}, Xs, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
+                else         NaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+          endcase
+
+
+  // Min/Max
+  //    - outputs the min/max of X and Y
+  //    - -0 < 0
+  //    - if both are NaN return quiet X
+  //    - if one is a NaN output the non-NaN
+  always_comb
+    if(OpCtrl[0]) // MAX
+        if(XNaN)
+          if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
+          else        CmpFpRes = Y;        // X = NaN Y != NaN
+        else
+          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          else // X,Y != NaN
+              if(LT)   CmpFpRes = Y; // X < Y
+              else     CmpFpRes = X; // X > Y
+    else  // MIN
+        if(XNaN)
+          if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
+          else        CmpFpRes = Y;        // X = NaN Y != NaN
+        else
+          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          else // X,Y != NaN
+              if(LT)   CmpFpRes = X; // X < Y
+              else     CmpFpRes = Y; // X > Y
+                                  
+  // LT/LE/EQ
+  //    - -0 = 0
+  //    - inf = inf and -inf = -inf
+  //    - return 0 if comparison with NaN (unordered)
+  assign CmpIntRes = {(`XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
+  
+endmodule
diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv
new file mode 100755
index 000000000..563206134
--- /dev/null
+++ b/pipelined/src/fpu/fctrl.sv
@@ -0,0 +1,309 @@
+///////////////////////////////////////////
+// fctrl.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: floating-point control unit
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
+
+module fctrl (
+  input  logic                clk,
+  input  logic                reset,
+  // input control signals
+  input  logic                StallE, StallM, StallW, // stall signals
+  input  logic                FlushE, FlushM, FlushW, // flush signals
+  input  logic                IntDivE,                // is inteteger division
+  input  logic [2:0]          FRM_REGW,               // rounding mode from CSR
+  input  logic [1:0]          STATUS_FS,              // is FPU enabled?
+  input  logic                FDivBusyE,              // is the divider busy
+  // intruction
+  input  logic [31:0]         InstrD,                 // the full instruction
+  input  logic [6:0]          Funct7D,                // bits 31:25 of instruction - may contain percision
+  input  logic [6:0]          OpD,                    // bits 6:0 of instruction
+  input  logic [4:0]          Rs2D,                   // bits 24:20 of instruction
+  input  logic [2:0]          Funct3D, Funct3E,       // bits 14:12 of instruction - may contain rounding mode
+  // input mux selections
+  output logic                XEnD, YEnD, ZEnD,       // enable inputs
+  output logic                XEnE, YEnE, ZEnE,       // enable inputs
+  // opperation mux selections
+  output logic 		            FCvtIntE, FCvtIntW,     // convert to integer opperation
+  output logic [2:0] 	        FrmM,                   // FP rounding mode
+  output logic [`FMTBITS-1:0] FmtE, FmtM,             // FP format
+  output logic [2:0] 	        OpCtrlE, OpCtrlM,       // Select which opperation to do in each component
+  output logic                FpLoadStoreM,           // FP load or store instruction
+  output logic [1:0] 	        PostProcSelE, PostProcSelM,         // select result in the post processing unit
+  output logic [1:0] 	        FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
+  // register control signals
+  output logic 		            FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
+  output logic 		            FWriteIntE, FWriteIntM,             // Write to integer register
+  output logic [4:0] 	        Adr1D, Adr2D, Adr3D,                // adresses of each input
+  output logic [4:0] 	        Adr1E, Adr2E, Adr3E,                // adresses of each input
+  // other control signals
+  output logic                IllegalFPUInstrM,                   // Is the instruction an illegal fpu instruction
+  output logic 		            FDivStartE, IDivStartE              // Start division or squareroot
+  );
+
+  `define FCTRLW 12
+
+  logic [`FCTRLW-1:0]   ControlsD;    // control signals
+  logic                 IllegalFPUInstrD, IllegalFPUInstrE; // is the intruction an illegal fpu instruction
+  logic 		            FRegWriteD;   // FP register write enable
+  logic 		            FDivStartD;   // start division/sqrt
+  logic 		            FWriteIntD;   // integer register write enable
+  logic [2:0] 	        OpCtrlD;      // Select which opperation to do in each component
+  logic [1:0] 	        PostProcSelD; // select result in the post processing unit
+  logic [1:0] 	        FResSelD;     // Select one of the results that finish in the memory stage
+  logic [2:0]           FrmD, FrmE;   // FP rounding mode
+  logic [`FMTBITS-1:0]  FmtD;         // FP format
+  logic [1:0]           Fmt;          // format - before possible reduction
+  logic                 SupportedFmt; // is the format supported
+  logic                 FCvtIntD, FCvtIntM; // convert to integer opperation
+
+  // FPU Instruction Decoder
+  assign Fmt = Funct7D[1:0];
+
+  // Note: only Fmt is checked; fcvt does not check destination format
+  assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) |
+                         (Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
+
+  // decode the instruction                       
+  always_comb
+    if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
+      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
+    else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) 
+      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
+    else case(OpD)
+    // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
+      7'b0000111: case(Funct3D)
+                    3'b010:                      ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw
+                    3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fld not supported
+                    3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flq not supported
+                    3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // flh not supported
+                    default:                     ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                  endcase
+      7'b0100111: case(Funct3D)
+                    3'b010:                      ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
+                    3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsd not supported
+                    3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsq not supported
+                    3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
+                             else                ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // fsh not supported
+                    default:                     ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                  endcase
+      7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
+      7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
+      7'b1001011:   ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0; // fnmsub
+      7'b1001111:   ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0; // fnmadd
+      7'b1010011: casez(Funct7D)
+                    7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0; // fadd
+                    7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0; // fsub
+                    7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0; // fmul
+                    7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
+                    7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
+                    7'b00100??: case(Funct3D)
+                                  3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
+                                  3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
+                                  3'b010:  ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
+                                  default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                                endcase
+                    7'b00101??: case(Funct3D)
+                                  3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
+                                  3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
+                                  default: ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                                endcase
+                    7'b10100??: case(Funct3D)
+                                  3'b010:  ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
+                                  3'b001:  ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
+                                  3'b000:  ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
+                                  default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction
+                                endcase
+                    7'b11100??: if (Funct3D == 3'b001)          ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
+                                else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w   to int reg
+                                else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d   to int reg
+                                else                            ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                    7'b1101000: case(Rs2D[1:0])
+                                  2'b00:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w   w->s
+                                  2'b01:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
+                                  2'b10:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.s.l   l->s
+                                  2'b11:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.s.lu lu->s
+                                endcase
+                    7'b1100000: case(Rs2D[1:0])
+                                  2'b00:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.s   s->w
+                                  2'b01:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.s  s->wu
+                                  2'b10:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.s   s->l
+                                  2'b11:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.s  s->lu
+                                endcase
+                    7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x   to fp reg
+                    7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.d
+                    7'b1101001: case(Rs2D[1:0])
+                                  2'b00:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.d.w   w->d
+                                  2'b01:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.d.wu wu->d
+                                  2'b10:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0; // fcvt.d.l   l->d
+                                  2'b11:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0; // fcvt.d.lu lu->d
+                                endcase
+                    7'b1100001: case(Rs2D[1:0])
+                                  2'b00:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1; // fcvt.w.d   d->w
+                                  2'b01:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.d  d->wu
+                                  2'b10:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d   d->l
+                                  2'b11:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d  d->lu
+                                endcase
+                    7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.d.x   to fp reg
+                    7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.s
+                    default:    ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+                  endcase
+      default:      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction
+    endcase
+
+  // unswizzle control bits
+  assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD;
+  
+  // rounding modes:
+  //    000 - round to nearest, ties to even
+  //    001 - round twords 0 - round to min magnitude
+  //    010 - round down - round twords negitive infinity
+  //    011 - round up - round twords positive infinity
+  //    100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
+  //    111 - dynamic - choose FRM_REGW as rounding mode
+  assign FrmD = &Funct3D ? FRM_REGW : Funct3D;
+
+  // Precision
+  //    00 - single
+  //    01 - double
+  //    10 - half
+  //    11 - quad
+  
+    if (`FPSIZES == 1)
+      assign FmtD = 0;
+    else if (`FPSIZES == 2)begin
+      logic [1:0] FmtTmp;
+      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
+      assign FmtD = (`FMT == FmtTmp);
+    end
+    else if (`FPSIZES == 3|`FPSIZES == 4)
+      assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
+
+  // Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
+  // When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic.
+  
+  //    X - all except int->fp, store, load, mv int->fp
+  assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)|                                                 // load/store
+                  ((FResSelD==2'b11)&FRegWriteD)|                                                  // mv int to float
+                  ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2]));                           // cvt int to float
+
+  //    Y - all except cvt, mv, load, class, sqrt
+  assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|                                     // load or class
+                  (FResSelD==2'b11)|                                                               // mv both ways
+                  ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
+
+  //    Z - fma ops only
+  assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]);                  // fma, add, sub
+  
+
+  //  Final Res Sel:
+  //        fp      int
+  //  00  other     cmp
+  //  01  postproc  cvt
+  //  10  store     class
+  //  11            mv
+
+  //  post processing Sel:
+  //  00  cvt
+  //  01  div
+  //  10  fma
+
+  //  Other Sel:
+  //    Ctrl signal = {OpCtrl[2], &FOpctrl[1:0]}
+  //        000 - sign            00
+  //        001 - negate sign     00
+  //        010 - xor sign        00
+  //        011 - mv to fp        01
+  //        110 - min             10
+  //        101 - max             10
+
+  //  OpCtrl:
+  //    Fma: {not multiply-add?, negate prod?, negate Z?}
+  //        000 - fmadd
+  //        001 - fmsub
+  //        010 - fnmsub
+  //        011 - fnmadd
+  //        100 - mul
+  //        110 - add
+  //        111 - sub
+  //    Div: 
+  //        0 - div
+  //        1 - sqrt
+  //    Cvt Int: {Int to Fp?, 64 bit int?, signed int?}
+  //    Cvt Fp: output format
+  //        10 - to half
+  //        00 - to single
+  //        01 - to double
+  //        11 - to quad
+  //    Cmp: {equal?, less than?}
+  //        010 - eq
+  //        001 - lt
+  //        011 - le
+  //        110 - min
+  //        101 - max
+  //    Sgn:
+  //        00 - sign
+  //        01 - negate sign
+  //        10 - xor sign
+
+  // rename input adresses for readability
+  assign Adr1D = InstrD[19:15];
+  assign Adr2D = InstrD[24:20];
+  assign Adr3D = InstrD[31:27];
+ 
+  // D/E pipleine register
+  flopenrc #(14+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD, FCvtIntD},
+              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE});
+  flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
+  flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
+  flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
+
+  // Integer division on FPU divider
+  if (`M_SUPPORTED & `IDIV_ON_FPU) assign IDivStartE = IntDivE;
+  else                             assign IDivStartE = 0; 
+
+  // E/M pipleine register
+  flopenrc #(14+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
+              {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE},
+              {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM, FCvtIntM});
+  
+  // renameing for readability
+  assign FpLoadStoreM = FResSelM[1];
+
+  // M/W pipleine register
+  flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
+          {FRegWriteM, FResSelM, FCvtIntM},
+          {FRegWriteW, FResSelW, FCvtIntW});
+  
+  //assign FCvtIntW = (FResSelW == 2'b01);
+
+endmodule
diff --git a/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv
similarity index 58%
rename from src/fpu/fcvt.sv
rename to pipelined/src/fpu/fcvt.sv
index 90e8d7a23..2f121a75a 100644
--- a/src/fpu/fcvt.sv
+++ b/pipelined/src/fpu/fcvt.sv
@@ -1,3 +1,4 @@
+
 ///////////////////////////////////////////
 // fcvt.sv
 //
@@ -6,7 +7,7 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // Int component of the Wally configurable RISC-V project.
 // 
@@ -26,21 +27,23 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fcvt import cvw::*;  #(parameter cvw_t P) (
-  input  logic                    Xs,           // input's sign
-  input  logic [P.NE-1:0]         Xe,           // input's exponent
-  input  logic [P.NF:0]           Xm,           // input's fraction
-  input  logic [P.XLEN-1:0]       Int,          // integer input - from IEU
-  input  logic [2:0]              OpCtrl,       // choose which operation (look below for values)
-  input  logic                    ToInt,        // is fp->int (since it's writting to the integer register)
-  input  logic                    XZero,        // is the input zero
-  input  logic [P.FMTBITS-1:0]    Fmt,          // the input's precision (11=quad 01=double 00=single 10=half)
-  output logic [P.NE:0]           Ce,           // the calculated expoent
-  output logic [P.LOGCVTLEN-1:0]  ShiftAmt,     // how much to shift by
-  output logic                    ResSubnormUf, // does the result underflow or is subnormal
-  output logic                    Cs,           // the result's sign
-  output logic                    IntZero,      // is the integer zero?
-  output logic [P.CVTLEN-1:0]     LzcIn         // input to the Leading Zero Counter (priority encoder)
+`include "wally-config.vh"
+
+module fcvt (
+  input  logic                    Xs,         // input's sign
+  input  logic [`NE-1:0]          Xe,         // input's exponent
+  input  logic [`NF:0]            Xm,         // input's fraction
+  input  logic [`XLEN-1:0]        Int,        // integer input - from IEU
+  input  logic [2:0]              OpCtrl,     // choose which opperation (look below for values)
+  input  logic                    ToInt,      // is fp->int (since it's writting to the integer register)
+  input  logic                    XZero,      // is the input zero
+  input  logic [`FMTBITS-1:0]     Fmt,        // the input's precision (11=quad 01=double 00=single 10=half)
+  output logic [`NE:0]            Ce,         // the calculated expoent
+  output logic [`LOGCVTLEN-1:0]   ShiftAmt,   // how much to shift by
+  output logic                    ResSubnormUf,// does the result underflow or is subnormal
+  output logic                    Cs,         // the result's sign
+  output logic                    IntZero,    // is the integer zero?
+  output logic [`CVTLEN-1:0]      LzcIn       // input to the Leading Zero Counter (priority encoder)
   );
 
   // OpCtrls:
@@ -53,38 +56,40 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //                            bit 2              bit 1                   bit 0
   //      for example: signed long -> single floating point has the OpCode 101
 
-  logic [P.FMTBITS-1:0]           OutFmt;       // format of the output
-  logic [P.XLEN-1:0]              PosInt;       // the positive integer input
-  logic [P.XLEN-1:0]              TrimInt;      // integer trimmed to the correct size
-  logic [P.NE-2:0]                NewBias;      // the bias of the final result
-  logic [P.NE-1:0]                OldExp;       // the old exponent
-  logic                           Signed;       // is the operation with a signed integer?
-  logic                           Int64;        // is the integer 64 bits?
-  logic                           IntToFp;      // is the operation an int->fp conversion?
-  logic [P.CVTLEN:0]              LzcInFull;    // input to the Leading Zero Counter (priority encoder)
-  logic [P.LOGCVTLEN-1:0]         LeadingZeros; // output from the LZC
+  logic [`FMTBITS-1:0]    OutFmt;     // format of the output
+  logic [`XLEN-1:0]       PosInt;     // the positive integer input
+  logic [`XLEN-1:0]       TrimInt;    // integer trimmed to the correct size
+  logic [`NE-2:0]         NewBias;    // the bias of the final result
+  logic [`NE-1:0]	        OldExp;     // the old exponent
+  logic                   Signed;     // is the opperation with a signed integer?
+  logic                   Int64;      // is the integer 64 bits?
+  logic                   IntToFp;    // is the opperation an int->fp conversion?
+  logic [`CVTLEN:0]       LzcInFull;  // input to the Leading Zero Counter (priority encoder)
+  logic [`LOGCVTLEN-1:0]  LeadingZeros; // output from the LZC
+
 
   // seperate OpCtrl for code readability
   assign Signed =  OpCtrl[0];
   assign Int64 =   OpCtrl[1];
   assign IntToFp = OpCtrl[2];
 
-  // choose the output format depending on the operation
-  //      - fp -> fp: OpCtrl contains the precision of the output
-  //      - int -> fp: Fmt contains the precision of the output
-  if (P.FPSIZES == 2) 
-      assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == P.FMT); 
-  else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
+  // choose the ouptut format depending on the opperation
+  //      - fp -> fp: OpCtrl contains the percision of the output
+  //      - int -> fp: Fmt contains the percision of the output
+  if (`FPSIZES == 2) 
+      assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == `FMT); 
+  else if (`FPSIZES == 3 | `FPSIZES == 4) 
       assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0]; 
 
+
   ///////////////////////////////////////////////////////////////////////////
   // negation
   ///////////////////////////////////////////////////////////////////////////
-  // 1) negate the input if the input is a negative singed integer
+  // 1) negate the input if the input is a negitive singed integer
   // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed)
 
   assign PosInt = Cs ? -Int : Int;
-  assign TrimInt = {{P.XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
+  assign TrimInt = {{`XLEN-32{Int64}}, {32{1'b1}}} & PosInt;
   assign IntZero = ~|TrimInt;
 
   ///////////////////////////////////////////////////////////////////////////
@@ -94,13 +99,13 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   // choose the input to the leading zero counter i.e. priority encoder
   //             int -> fp : | positive integer | 00000... (if needed) | 
   //             fp  -> fp : | fraction         | 00000... (if needed) | 
-  assign LzcInFull = IntToFp ? {TrimInt, {P.CVTLEN-P.XLEN+1{1'b0}}} :
-                               {Xm, {P.CVTLEN-P.NF{1'b0}}};
+  assign LzcInFull = IntToFp ? {TrimInt, {`CVTLEN-`XLEN+1{1'b0}}} :
+                            {Xm, {`CVTLEN-`NF{1'b0}}};
 
   // used as shifter input in postprocessor
-  assign LzcIn = LzcInFull[P.CVTLEN-1:0];
+  assign LzcIn = LzcInFull[`CVTLEN-1:0];
   
-  lzc #(P.CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
+  lzc #(`CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
   
   ///////////////////////////////////////////////////////////////////////////
   // exp calculations
@@ -109,41 +114,42 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   // Select the bias of the output
   //      fp -> int : select 1
   //      ??? -> fp : pick the new bias depending on the output format 
-  if (P.FPSIZES == 1) begin
-      assign NewBias = ToInt ? (P.NE-1)'(1) : (P.NE-1)'(P.BIAS); 
+  if (`FPSIZES == 1) begin
+      assign NewBias = ToInt ? (`NE-1)'(1) : (`NE-1)'(`BIAS); 
 
-  end else if (P.FPSIZES == 2) begin
-      logic [P.NE-2:0] NewBiasToFp;
-      assign NewBiasToFp = OutFmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
-      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
+  end else if (`FPSIZES == 2) begin
+      logic [`NE-2:0] NewBiasToFp;
+      assign NewBiasToFp = OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
+      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
 
-  end else if (P.FPSIZES == 3) begin
-      logic [P.NE-2:0] NewBiasToFp;
+  end else if (`FPSIZES == 3) begin
+      logic [`NE-2:0] NewBiasToFp;
       always_comb
           case (OutFmt)
-              P.FMT: NewBiasToFp =  (P.NE-1)'(P.BIAS);
-              P.FMT1: NewBiasToFp = (P.NE-1)'(P.BIAS1);
-              P.FMT2: NewBiasToFp = (P.NE-1)'(P.BIAS2);
-              default: NewBiasToFp = {P.NE-1{1'bx}};
+              `FMT: NewBiasToFp =  (`NE-1)'(`BIAS);
+              `FMT1: NewBiasToFp = (`NE-1)'(`BIAS1);
+              `FMT2: NewBiasToFp = (`NE-1)'(`BIAS2);
+              default: NewBiasToFp = {`NE-1{1'bx}};
           endcase
-      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
+      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
 
-  end else if (P.FPSIZES == 4) begin        
-      logic [P.NE-2:0] NewBiasToFp;
+  end else if (`FPSIZES == 4) begin        
+      logic [`NE-2:0] NewBiasToFp;
       always_comb
           case (OutFmt)
-              2'h3: NewBiasToFp =  (P.NE-1)'(P.Q_BIAS);
-              2'h1: NewBiasToFp =  (P.NE-1)'(P.D_BIAS);
-              2'h0: NewBiasToFp =  (P.NE-1)'(P.S_BIAS);
-              2'h2: NewBiasToFp =  (P.NE-1)'(P.H_BIAS);
+              2'h3: NewBiasToFp =  (`NE-1)'(`Q_BIAS);
+              2'h1: NewBiasToFp =  (`NE-1)'(`D_BIAS);
+              2'h0: NewBiasToFp =  (`NE-1)'(`S_BIAS);
+              2'h2: NewBiasToFp =  (`NE-1)'(`H_BIAS);
           endcase
-      assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; 
+      assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
   end
 
+
   // select the old exponent
   //      int -> fp : largest bias + XLEN-1
   //      fp -> ??? : XExp
-  assign OldExp = IntToFp ? (P.NE)'(P.BIAS)+(P.NE)'(P.XLEN-1) : Xe;
+  assign OldExp = IntToFp ? (`NE)'(`BIAS)+(`NE)'(`XLEN-1) : Xe;
   
   // calculate CalcExp
   //      fp -> fp : 
@@ -153,13 +159,13 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //              - correct the expoent when there is a normalization shift ( + LeadingZeros+1) 
   //              - the plus 1 is built into the leading zeros by counting the leading zeroes in the mantissa rather than the fraction
   //      fp -> int : XExp - Largest Bias + 1 - (LeadingZeros+1)
-  //          |  P.XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
+  //          |  `XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
   //          process:
   //              - start
-  //                  |  P.XLEN  zeros     |     Mantissa      | 0's if nessisary |
+  //                  |  `XLEN  zeros     |     Mantissa      | 0's if nessisary |
   //
   //              - shift left 1 (1)
-  //                  | P.XLEN-1 zeros |bit|     frac      | 0's if nessisary |
+  //                  | `XLEN-1 zeros |bit|     frac      | 0's if nessisary |
   //                                      . <- binary point
   //
   //              - shift left till unbiased exponent is 0 (XExp - Largest Bias)
@@ -179,18 +185,20 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //                  - newBias to make the biased exponent
   //
   //          oldexp         - biasold         - LeadingZeros                               + newbias
-  assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
+  assign Ce = {1'b0, OldExp} - (`NE+1)'(`BIAS) - {{`NE-`LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
+
 
   // find if the result is dnormal or underflows
-  //      - if Calculated expoenent is 0 or negative (and the input/result is not exactaly 0)
+  //      - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
   //      - can't underflow an integer to Fp conversion
-  assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
+  assign ResSubnormUf = (~|Ce | Ce[`NE])&~XZero&~IntToFp;
+
 
   ///////////////////////////////////////////////////////////////////////////
   // shifter
   ///////////////////////////////////////////////////////////////////////////
 
-  // kill the shift if it is negative
+  // kill the shift if it's negitive
   // select the amount to shift by
   //      fp -> int: 
   //          - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
@@ -201,11 +209,12 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //          - shift left by LeadingZeros - to shift till the result is normalized
   //              - only shift fp -> fp if the intital value is subnormal
   //                  - this is a problem because the input to the lzc was the fraction rather than the mantissa
-  //                  - rather have a few and-gates than an extra bit in the priority encoder???
+  //                  - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
   always_comb
-      if(ToInt)                       ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
-      else if (ResSubnormUf)          ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
+      if(ToInt)                       ShiftAmt = Ce[`LOGCVTLEN-1:0]&{`LOGCVTLEN{~Ce[`NE]}};
+      else if (ResSubnormUf)  ShiftAmt = (`LOGCVTLEN)'(`NF-1)+Ce[`LOGCVTLEN-1:0];
       else                            ShiftAmt = LeadingZeros;
+
       
   ///////////////////////////////////////////////////////////////////////////
   // sign
@@ -218,7 +227,9 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //      - otherwise: the floating point input's sign
   always_comb
       if(IntToFp)
-          if(Int64)   Cs = Int[P.XLEN-1]&Signed;
+          if(Int64)   Cs = Int[`XLEN-1]&Signed;
           else        Cs = Int[31]&Signed;
       else            Cs = Xs;
+
 endmodule
+
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
new file mode 100644
index 000000000..c69618f43
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -0,0 +1,103 @@
+///////////////////////////////////////////
+// fdivsqrt.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrt(
+  input  logic clk, 
+  input  logic reset, 
+  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic XsE,
+  input  logic [`NF:0] XmE, YmE,
+  input  logic [`NE-1:0] XeE, YeE,
+  input  logic XInfE, YInfE, 
+  input  logic XZeroE, YZeroE, 
+  input  logic XNaNE, YNaNE, 
+  input  logic FDivStartE, IDivStartE,
+  input  logic StallM,
+  input  logic FlushE,
+  input  logic SqrtE, SqrtM,
+	input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+	input  logic [2:0] 	Funct3E, Funct3M,
+	input  logic IntDivE, W64E,
+  output logic DivStickyM,
+  output logic FDivBusyE, IFDivStartE, FDivDoneE,
+  output logic [`NE+1:0] QeM,
+  output logic [`DIVb:0] QmM,
+  output logic [`XLEN-1:0] FIntDivResultM
+);
+
+  // Floating-point division and square root module, with optional integer division and remainder
+  // Computes X/Y, sqrt(X), A/B, or A%B
+
+  logic [`DIVb+3:0] WS, WC;           // Partial remainder components
+  logic [`DIVb+3:0] X;                // Iterator Initial Value (from dividend)
+  logic [`DIVb-1:0] DPreproc, D;      // Iterator Divisor
+  logic [`DIVb:0]   FirstU, FirstUM;  // Intermediate result values
+  logic [`DIVb+1:0] FirstC;           // Step tracker
+  logic Firstun;                      // Quotient selection
+  logic WZeroE;                       // Early termination flag
+  logic SpecialCaseM;                 // Divide by zero, square root of negative, etc.
+  logic DivStartE;                    // Enable signal for flops during stall
+
+  // Integer div/rem signals
+  logic BZeroM;                       // Denominator is zero
+  logic IntDivM;                         // Integer operation
+  logic [`DIVBLEN:0] nE, nM, mM;      // Shift amounts
+  logic NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
+  logic [`XLEN-1:0] AM;               // Original Numerator for postprocessor
+  logic ISpecialCaseE;                // Integer div/remainder special cases
+
+  fdivsqrtpreproc fdivsqrtpreproc(                        // Preprocessor
+    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), 
+    .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, 
+    .QeM, .X, .DPreproc, 
+    // Int-specific 
+    .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
+    .nE, .BZeroM, .nM, .mM, .AM, 
+    .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
+
+  fdivsqrtfsm fdivsqrtfsm(                                // FSM
+    .clk, .reset, .FmtE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
+    .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
+    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, 
+    // Int-specific 
+    .IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
+
+  fdivsqrtiter fdivsqrtiter(                              // CSA Iterator
+    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc, 
+    .D, .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+
+  fdivsqrtpostproc fdivsqrtpostproc(                      // Postprocessor
+    .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
+    .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
+    .QmM, .WZeroE, .DivStickyM, 
+    // Int-specific 
+    .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, 
+    .FIntDivResultM);
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
new file mode 100644
index 000000000..07cffa268
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
@@ -0,0 +1,74 @@
+///////////////////////////////////////////
+// fdivsqrtpreproc.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: Exponent caclulation for divide and square root
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtexpcalc(
+  input  logic [`FMTBITS-1:0] Fmt,
+  input  logic [`NE-1:0] Xe, Ye,
+  input  logic Sqrt,
+  input  logic XZero, 
+  input  logic [`DIVBLEN:0] ell, m,
+  output logic [`NE+1:0] Qe
+  );
+  logic [`NE-2:0] Bias;
+  logic [`NE+1:0] SXExp;
+  logic [`NE+1:0] SExp;
+  logic [`NE+1:0] DExp;
+  
+  if (`FPSIZES == 1) begin
+      assign Bias = (`NE-1)'(`BIAS); 
+
+  end else if (`FPSIZES == 2) begin
+      assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
+
+  end else if (`FPSIZES == 3) begin
+      always_comb
+          case (Fmt)
+              `FMT: Bias  =  (`NE-1)'(`BIAS);
+              `FMT1: Bias = (`NE-1)'(`BIAS1);
+              `FMT2: Bias = (`NE-1)'(`BIAS2);
+              default: Bias = 'x;
+          endcase
+
+  end else if (`FPSIZES == 4) begin        
+    always_comb
+        case (Fmt)
+            2'h3: Bias =  (`NE-1)'(`Q_BIAS);
+            2'h1: Bias =  (`NE-1)'(`D_BIAS);
+            2'h0: Bias =  (`NE-1)'(`S_BIAS);
+            2'h2: Bias =  (`NE-1)'(`H_BIAS);
+        endcase
+  end
+  assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
+  assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
+  
+  // correct exponent for subnormal input's normalization shifts
+  assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
+  assign Qe = Sqrt ? SExp : DExp;
+endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
similarity index 76%
rename from src/fpu/fdivsqrt/fdivsqrtfgen2.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
index 799ded999..9c13a91da 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,18 +26,21 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fdivsqrtfgen2 import cvw::*;  #(parameter cvw_t P) (
-  input  logic              up, uz,
-  input  logic [P.DIVb+3:0] C, U, UM,   // Q4.DIVb (extended from shorter forms)
-  output logic [P.DIVb+3:0] F           // Q4.DIVb
-);
-  logic [P.DIVb+3:0]        FP, FN, FZ;  // Q4.DIVb
+`include "wally-config.vh"
 
-  // Generate for both positive and negative quotient digits
+module fdivsqrtfgen2 (
+  input  logic up, uz,
+  input  logic [`DIVb+3:0] C, U, UM,
+  output logic [`DIVb+3:0] F
+);
+  logic [`DIVb+3:0] FP, FN, FZ;
+
+  // Generate for both positive and negative bits
   assign FP = ~(U << 1) & C;
   assign FN = (UM << 1) | (C & ~(C << 2));
   assign FZ = '0;
 
+
   always_comb     // Choose which adder input will be used
     if (up)       F = FP;
     else if (uz)  F = FZ;
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
similarity index 73%
rename from src/fpu/fdivsqrt/fdivsqrtfgen4.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index 90af95643..975d58ebd 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,15 +26,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fdivsqrtfgen4 import cvw::*;  #(parameter cvw_t P) (
-  input  logic [3:0]        udigit,           // {2, 1, -1, -2}; all cold for zero
-  input  logic [P.DIVb+3:0] C, U, UM,         // Q4.DIVb (extended from shorter forms)
-  output logic [P.DIVb+3:0] F                 // Q4.DIVb
+`include "wally-config.vh"
+
+module fdivsqrtfgen4 (
+  input  logic [3:0] udigit,
+  input  logic [`DIVb+3:0] C, U, UM,
+  output logic [`DIVb+3:0] F
 );
-  logic [P.DIVb+3:0]        F2, F1, F0, FN1, FN2; // Q4.DIVb
+  logic [`DIVb+3:0] F2, F1, F0, FN1, FN2;
   
-  // Generate for both positive and negative digits
-  assign F2  = (~U << 2) & (C << 2);              // 
+  // Generate for both positive and negative bits
+  assign F2  = (~U << 2) & (C << 2);
   assign F1  = ~(U << 1) & C;
   assign F0  = '0;
   assign FN1 = (UM << 1) | (C & ~(C << 3));
@@ -48,4 +49,4 @@ module fdivsqrtfgen4 import cvw::*;  #(parameter cvw_t P) (
     else if (udigit[1])  F = FN1;
     else if (udigit[0])  F = FN2;
     else                 F = F0;
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
new file mode 100644
index 000000000..81f6a5eed
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -0,0 +1,126 @@
+///////////////////////////////////////////
+// fdivsqrtfsm.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: divsqrt state machine for multi-cycle operations
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtfsm(
+  input  logic clk, 
+  input  logic reset, 
+  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic XInfE, YInfE, 
+  input  logic XZeroE, YZeroE, 
+  input  logic XNaNE, YNaNE, 
+  input  logic FDivStartE, IDivStartE,
+  input  logic XsE,
+  input  logic SqrtE,
+  input  logic StallM,
+  input  logic FlushE,
+  input  logic WZeroE,
+  input  logic IntDivE,
+  input  logic [`DIVBLEN:0] nE,
+  input  logic ISpecialCaseE,
+  output logic IFDivStartE,
+  output logic FDivBusyE, FDivDoneE,
+  output logic SpecialCaseM
+);
+  
+  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
+  statetype state;
+
+  logic [`DURLEN-1:0] step;
+  logic [`DURLEN-1:0] cycles;
+  logic SpecialCaseE, FSpecialCaseE;
+
+  // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
+  assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
+  assign FDivDoneE = (state == DONE);
+  assign FDivBusyE = (state == BUSY) | IFDivStartE; 
+
+  // terminate immediately on special cases
+  assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
+  if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
+  else              assign SpecialCaseE = FSpecialCaseE;
+  flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
+
+// DIVN = `NF+3
+// NS = NF + 1
+// N = NS or NS+2 for div/sqrt.  
+
+/* verilator lint_off WIDTH */
+  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
+  if (`FPSIZES == 1)
+    assign Nf = `NF;
+  else if (`FPSIZES == 2)
+    always_comb
+      case (FmtE)
+        1'b0: Nf = `NF1;
+        1'b1: Nf = `NF;
+      endcase
+  else if (`FPSIZES == 3)
+    always_comb
+      case (FmtE)
+        `FMT: Nf = `NF;
+        `FMT1: Nf = `NF1;
+        `FMT2: Nf = `NF2; 
+      endcase
+  else if (`FPSIZES == 4)  
+    always_comb
+      case(FmtE)
+        `S_FMT: Nf = `S_NF;
+        `D_FMT: Nf = `D_NF;
+        `H_FMT: Nf = `H_NF;
+        `Q_FMT: Nf = `Q_NF;
+      endcase 
+
+
+  always_comb begin 
+    if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
+    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
+    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+  end 
+
+  /* verilator lint_on WIDTH */
+
+  always_ff @(posedge clk) begin
+      if (reset | FlushE) begin
+          state <= #1 IDLE; 
+      end else if (IFDivStartE) begin 
+          step <= cycles; 
+          if (SpecialCaseE) state <= #1 DONE;
+          else              state <= #1 BUSY;
+      end else if (state == BUSY) begin 
+          if (step == 1 | WZeroE) state <= #1 DONE; // finished steps or terminate early on zero residual
+          step <= step - 1;
+      end else if (state == DONE) begin
+        if (StallM) state <= #1 DONE;
+        else        state <= #1 IDLE;
+      end 
+  end
+
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
new file mode 100644
index 000000000..d1cf24354
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -0,0 +1,140 @@
+///////////////////////////////////////////
+// fdivsqrtiter.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
+// Modified:13 January 2022
+//
+// Purpose: k stages of divsqrt logic, plus registers
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtiter(
+  input  logic clk,
+  input  logic IFDivStartE, 
+  input  logic FDivBusyE, 
+  input  logic SqrtE,
+  input  logic [`DIVb+3:0] X,
+  input  logic [`DIVb-1:0] DPreproc,
+  output logic [`DIVb-1:0] D,
+  output logic [`DIVb:0]   FirstU, FirstUM,
+  output logic [`DIVb+1:0] FirstC,
+  output logic             Firstun,
+  output logic [`DIVb+3:0] FirstWS, FirstWC
+);
+
+  /* verilator lint_off UNOPTFLAT */
+  logic [`DIVb+3:0]      WSNext[`DIVCOPIES-1:0]; // Q4.b
+  logic [`DIVb+3:0]      WCNext[`DIVCOPIES-1:0]; // Q4.b
+  logic [`DIVb+3:0]      WS[`DIVCOPIES:0];       // Q4.b
+  logic [`DIVb+3:0]      WC[`DIVCOPIES:0];       // Q4.b
+  logic [`DIVb:0]        U[`DIVCOPIES:0];        // U1.b
+  logic [`DIVb:0]        UM[`DIVCOPIES:0];       // U1.b
+  logic [`DIVb:0]        UNext[`DIVCOPIES-1:0];  // U1.b
+  logic [`DIVb:0]        UMNext[`DIVCOPIES-1:0]; // U1.b
+  logic [`DIVb+1:0]      C[`DIVCOPIES:0];        // Q2.b
+  logic [`DIVb+1:0]      initC;                  // Q2.b
+  logic [`DIVCOPIES-1:0] un; 
+
+  logic [`DIVb+3:0]      WSN, WCN;               // Q4.b
+  logic [`DIVb+3:0]      DBar, D2, DBar2;        // Q4.b
+  logic [`DIVb+1:0]      NextC;
+  logic [`DIVb:0]        UMux, UMMux;
+  logic [`DIVb:0]        initU, initUM;
+  /* verilator lint_on UNOPTFLAT */
+
+  // Top Muxes and Registers
+  // When start is asserted, the inputs are loaded into the divider.
+  // Otherwise, the divisor is retained and the residual and result
+  // are fed back for the next iteration.
+ 
+  // Residual WS/SC registers/initializaiton mux
+  mux2   #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, IFDivStartE, WSN);
+  mux2   #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, IFDivStartE, WCN);
+  flopen #(`DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
+  flopen #(`DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
+
+  // UOTFC Result U and UM registers/initialization mux
+  // Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 otherwise
+  assign initU  = {SqrtE, {(`DIVb){1'b0}}};
+  assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
+  mux2   #(`DIVb+1)  Umux(UNext[`DIVCOPIES-1],  initU,  IFDivStartE, UMux);
+  mux2   #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
+  flopen #(`DIVb+1)  UReg(clk, IFDivStartE|FDivBusyE, UMux,  U[0]);
+  flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
+
+  // C register/initialization mux
+  // Initialize C to -1 for sqrt and -R for division
+  logic [1:0] initCUpper;
+  if(`RADIX == 4) begin
+    mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
+  end else begin
+    mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
+  end
+  
+  assign initC = {initCUpper, {`DIVb{1'b0}}};
+  mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
+  flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
+
+   // Divisior register
+  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
+
+  // Divisor Selections
+  //  - choose the negitive version of what's being selected
+  //  - D is a 0.b mantissa
+  assign DBar    = {3'b111, 1'b0, ~D};
+  if(`RADIX == 4) begin : d2
+    assign DBar2 = {2'b11, 1'b0, ~D, 1'b1};
+    assign D2    = {2'b0, 1'b1, D, 1'b0};
+  end
+
+  // k=DIVCOPIES of the recurrence logic
+  genvar i;
+  generate
+    for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : iterations
+      if (`RADIX == 2) begin: stage
+        fdivsqrtstage2 fdivsqrtstage(.D, .DBar, .SqrtE,
+        .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
+        .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
+      end else begin: stage
+        logic j1;
+        assign j1 = (i == 0 & ~C[0][`DIVb-1]);
+        fdivsqrtstage4 fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, .j1,
+        .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), 
+        .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
+      end
+      assign WS[i+1] = WSNext[i];
+      assign WC[i+1] = WCNext[i];
+      assign U[i+1]  = UNext[i];
+      assign UM[i+1] = UMNext[i];
+    end
+  endgenerate
+
+  // Send values from start of cycle for postprocessing
+  assign FirstWS = WS[0];
+  assign FirstWC = WC[0];
+  assign FirstU  = U[0];
+  assign FirstUM = UM[0];
+  assign FirstC  = C[0];
+  assign Firstun = un[0];
+endmodule
+
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
new file mode 100644
index 000000000..44b269355
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -0,0 +1,138 @@
+///////////////////////////////////////////
+// fdivsqrtpostproc.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: Divide/Square root postprocessing
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtpostproc(
+  input  logic              clk, reset,
+  input  logic              StallM,
+  input  logic [`DIVb+3:0]  WS, WC,
+  input  logic [`DIVb-1:0]  D, 
+  input  logic [`DIVb:0]    FirstU, FirstUM, 
+  input  logic [`DIVb+1:0]  FirstC,
+  input  logic              SqrtE,
+  input  logic              Firstun, SqrtM, SpecialCaseM, NegQuotM,
+	input  logic [`XLEN-1:0]  AM,
+  input  logic              RemOpM, ALTBM, BZeroM, AsM, W64M,
+  input  logic [`DIVBLEN:0] nM, mM,
+  output logic [`DIVb:0]    QmM, 
+  output logic              WZeroE,
+  output logic              DivStickyM,
+  output logic [`XLEN-1:0]  FIntDivResultM
+);
+  
+  logic [`DIVb+3:0] W, Sum, DM;
+  logic [`DIVb:0] PreQmM;
+  logic NegStickyM;
+  logic weq0E, weq0M, WZeroM;
+  logic [`XLEN-1:0] IntDivResultM;
+
+  //////////////////////////
+  // Execute Stage: Detect early termination for an exact result
+  //////////////////////////
+
+  // check for early termination on an exact result. 
+  aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0E);
+
+  if (`RADIX == 2) begin: R2EarlyTerm
+    logic [`DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
+    logic [`DIVb+2:0] FirstK;
+    logic wfeq0E;
+    logic [`DIVb+3:0] WCF, WSF;
+
+    assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
+    assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
+    assign FZeroDivE =  {3'b001,D,1'b0};                                    // F for divide
+    mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
+    csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
+    aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
+    assign WZeroE = weq0E|(wfeq0E & Firstun);
+  end else begin
+    assign WZeroE = weq0E;
+  end 
+
+  //////////////////////////
+  // E/M Pipeline register
+  //////////////////////////
+ 
+  flopenr #(1) WZeroMReg(clk, reset, ~StallM, WZeroE, WZeroM);
+  flopenr #(1) WeqZeroMReg(clk, reset, ~StallM, weq0E, weq0M);
+
+  //////////////////////////
+  // Memory Stage: Postprocessing
+  //////////////////////////
+
+  //  If the result is not exact, the sticky should be set
+  assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
+
+  // Determine if sticky bit is negative  // *** look for ways to optimize this.  Shift shouldn't be needed.
+  assign Sum = WC + WS;
+  assign NegStickyM = Sum[`DIVb+3];
+  mux2 #(`DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
+  mux2 #(`DIVb+1)    qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
+
+  // Integer quotient or remainder correctoin, normalization, and special cases
+  if (`IDIV_ON_FPU) begin:intpostproc // Int supported
+    logic [`DIVBLEN:0] NormShiftM;
+    logic [`DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
+    logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
+
+    assign W = $signed(Sum) >>> `LOGR;
+    assign DM = {4'b0001, D};
+    assign UnsignedQuotM = {3'b000, PreQmM};
+
+    // Integer remainder: sticky and sign correction muxes
+    mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
+    mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
+    mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
+
+    // Select quotient or remainder and do normalization shift
+    mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
+    mux2 #(`DIVb+4)   presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
+    assign PreIntResultM = $signed(PreResultM >>> NormShiftM); 
+
+    // special case logic
+    // terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B|
+    always_comb
+      if (BZeroM) begin         // Divide by zero
+        if (RemOpM) IntDivResultM = AM;  
+        else        IntDivResultM = {(`XLEN){1'b1}};
+     end else if (ALTBM) begin // Numerator is zero
+        if (RemOpM) IntDivResultM = AM;
+        else        IntDivResultM = '0;
+     end else       IntDivResultM = PreIntResultM[`XLEN-1:0];
+
+    // sign extend result for W64
+    if (`XLEN==64) begin
+      mux2 #(64) resmux(IntDivResultM[`XLEN-1:0], 
+        {{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
+        W64M, FIntDivResultM);
+    end else 
+      assign FIntDivResultM = IntDivResultM[`XLEN-1:0];
+  end
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
new file mode 100644
index 000000000..5d490df28
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -0,0 +1,172 @@
+///////////////////////////////////////////
+// fdivsqrtpreproc.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtpreproc (
+  input  logic clk,
+  input  logic IFDivStartE, 
+  input  logic [`NF:0] Xm, Ym,
+  input  logic [`NE-1:0] Xe, Ye,
+  input  logic [`FMTBITS-1:0] Fmt,
+  input  logic Sqrt,
+  input  logic XZeroE,
+	input  logic [2:0] 	Funct3E,
+  output logic [`NE+1:0] QeM,
+  output logic [`DIVb+3:0] X,
+  output logic [`DIVb-1:0] DPreproc,
+  // Int-specific
+  input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+	input  logic IntDivE, W64E,
+  output logic ISpecialCaseE,
+  output logic [`DIVBLEN:0] nE, nM, mM,
+  output logic NegQuotM, ALTBM, IntDivM, W64M,
+  output logic AsM, BZeroM,
+  output logic [`XLEN-1:0] AM
+);
+
+  logic  [`DIVb-1:0] XPreproc;
+  logic  [`DIVb:0] PreSqrtX;
+  logic  [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX;  // Variations of dividend, to be muxed
+  logic  [`NE+1:0] QeE;                       // Quotient Exponent (FP only)
+  logic  [`DIVb-1:0] IFNormLenX, IFNormLenD;  // Correctly-sized inputs for iterator
+  logic  [`DIVBLEN:0] mE, ell;                // Leading zeros of inputs
+  logic  NumerZeroE;                          // Numerator is zero (X or A)
+  logic  AZeroE, BZeroE;                      // A or B is Zero for integer division
+
+  if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
+    logic signedDiv, NegQuotE;
+    logic AsBit, BsBit, AsE, BsE, ALTBE;
+    logic [`XLEN-1:0] AE, BE, PosA, PosB;
+    logic [`DIVBLEN:0] ZeroDiff, p;
+
+    // Extract inputs, signs, zero, depending on W64 mode if applicable
+    assign signedDiv = ~Funct3E[0];
+    assign NegQuotE = AsE ^ BsE; // Quotient is negative
+
+    // Source handling
+    if (`XLEN==64) begin // 64-bit, supports W64
+      mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
+      mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
+      mux2 #(1)  abitmux(ForwardedSrcAE[63], ForwardedSrcAE[31], W64E, AsBit);
+      mux2 #(1)  bbitmux(ForwardedSrcBE[63], ForwardedSrcBE[31], W64E, BsBit);
+      mux2 #(64)    amux(ForwardedSrcAE, {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]}, W64E, AE);
+      mux2 #(64)    bmux(ForwardedSrcBE, {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]}, W64E, BE);
+      assign AsE = signedDiv & AsBit;
+      assign BsE = signedDiv & BsBit;
+    end else begin // 32 bits only
+      assign AsE = signedDiv & ForwardedSrcAE[31];
+      assign BsE = signedDiv & ForwardedSrcBE[31];
+      assign AE = ForwardedSrcAE;
+      assign BE = ForwardedSrcBE;
+      assign AZeroE = ~(|ForwardedSrcAE);
+      assign BZeroE = ~(|ForwardedSrcBE);
+    end
+
+    // Force integer inputs to be postiive
+    mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
+    mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
+
+    // Select integer or floating point inputs
+    mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenX);
+    mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenD);
+
+    // calculate number of fractional bits p
+    assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
+    assign ALTBE = ZeroDiff[`DIVBLEN];  // A less than B (A has more leading zeros)
+    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p);            // *** is there a more graceful way to write these constants    
+
+    // Integer special cases (terminate immediately)
+    assign ISpecialCaseE = BZeroE | ALTBE;
+
+  /* verilator lint_off WIDTH */
+    // calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
+
+    if (`LOGRK > 0) begin // more than 1 bit per cycle
+      logic [`LOGRK-1:0] IntTrunc, RightShiftX;
+      logic [`DIVBLEN:0] TotalIntBits, IntSteps;
+
+      assign TotalIntBits = `LOGR + p;                            // Total number of result bits (r integer bits plus p fractional bits)
+      assign IntTrunc = TotalIntBits % `RK;                       // Truncation check for ceiling operator
+      assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc;     // Number of steps for int div
+      assign nE = (IntSteps * `DIVCOPIES) - 1;                    // Fractional digits
+      assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK);  // Right shift amount
+      assign DivXShifted = DivX >> RightShiftX;                   // shift X by up to R*K-1 to complete in nE steps
+    end else begin // radix 2 1 copy doesn't require shifting
+      assign nE = p; 
+      assign DivXShifted = DivX;
+    end
+  /* verilator lint_on WIDTH */
+
+    // Selet integer or floating-point operands
+    mux2 #(1)    numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
+    mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
+
+    // pipeline registers
+    flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,     IntDivM);
+    flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
+    flopen #(1)       altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
+    flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
+    flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
+    flopen #(1)      asignreg(clk, IFDivStartE, AsE,      AsM);
+    flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE,       nM);
+    flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE,       mM);
+    flopen #(`XLEN)   srcareg(clk, IFDivStartE, AE,       AM);
+
+  end else begin // Int not supported
+    assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
+    assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
+    assign NumerZeroE = XZeroE;
+    assign X = PreShiftX;
+  end
+
+  // count leading zeros for Subnorm FP and to normalize integer inputs
+  lzc #(`DIVb) lzcX (IFNormLenX, ell);
+  lzc #(`DIVb) lzcY (IFNormLenD, mE);
+
+  // Normalization shift
+  assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); 
+  assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
+
+  // append leading 1 (for normal inputs)
+  // shift square root to be in range [1/4, 1)
+  // Normalized numbers are shifted right by 1 if the exponent is odd
+  // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
+  mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
+  assign DivX = {3'b000, ~NumerZeroE, XPreproc};
+
+  // Sqrt is initialized on step one as R(X-1), so depends on Radix
+  if (`RADIX == 2)  assign SqrtX = {3'b111, PreSqrtX};
+  else              assign SqrtX = {2'b11, PreSqrtX, 1'b0};
+  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, Sqrt, PreShiftX);
+ 
+  // Floating-point exponent
+  fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
+  flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
+endmodule
+
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
similarity index 54%
rename from src/fpu/fdivsqrt/fdivsqrtuslc2.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
index 193231eea..f18b31f1b 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
@@ -1,15 +1,14 @@
 ///////////////////////////////////////////
-// fdivsqrtuslc2.sv
+// fdivsqrtqsel2.sv
 //
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
 // Modified:13 January 2022
 //
-// Purpose: Radix 2 Unified Quotient/Square Root Digit Selection
+// Purpose: Radix 2 Quotient Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -19,7 +18,7 @@
 // except in compliance with the License, or, at your option, the Apache License version 2.0. You 
 // may obtain a copy of the License at
 //
-// httWS://solderpad.org/licenses/SHL-2.1/
+// https://solderpad.org/licenses/SHL-2.1/
 //
 // Unless required by applicable law or agreed to in writing, any work distributed under the 
 // License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
@@ -27,26 +26,33 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fdivsqrtuslc2 ( 
-  input  logic [3:0] WS, WC,      // Q4.0 most significant bits of redundant residual
-  output logic       up, uz, un   // {+1, 0, -1}
+`include "wally-config.vh"
+
+module fdivsqrtqsel2 ( 
+  input  logic [3:0] ps, pc, 
+  output logic  up, uz, un
 );
  
-  logic        sign;
-
-  // Carry chain logic determines if W = WS + WC = -1, < -1, > -1 to choose 0, -1, 1 respectively
+  logic [3:0]  p, g;
+  logic        magnitude, sign;
  
-  //if p2 * p1 * p0, W = -1 and choose digit of 0
-  assign uz = ((WS[2]^WC[2]) & (WS[1]^WC[1]) & 
-        (WS[0]^WC[0]));
+  // The quotient selection logic is presented for simplicity, not
+  // for efficiency.  You can probably optimize your logic to
+  // select the proper divisor with less delay.
 
-  // Otherwise determine sign using carry chain: sign = p3 ^ g_2:0
-  assign sign = (WS[3]^WC[3])^
-      (WS[2] & WC[2] | ((WS[2]^WC[2]) &
-          (WS[1]&WC[1] | ((WS[1]^WC[1]) &
-            (WS[0]&WC[0])))));
+  // Quotient equations from EE371 lecture notes 13-20
+  assign p = ps ^ pc;
+  assign g = ps & pc;
+
+  assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & 
+			  (ps[0]^pc[0]));
+  assign sign = (ps[3]^pc[3])^
+      (ps[2] & pc[2] | ((ps[2]^pc[2]) &
+			    (ps[1]&pc[1] | ((ps[1]^pc[1]) &
+						(ps[0]&pc[0])))));
 
   // Produce digit = +1, 0, or -1
-  assign up = ~uz & ~sign;
-  assign un = ~uz & sign;
+  assign up = magnitude & ~sign;
+  assign uz = ~magnitude;
+  assign un = magnitude & sign;
 endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
similarity index 67%
rename from src/fpu/fdivsqrt/fdivsqrtuslc4.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
index 840215c28..3a8a110f0 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
@@ -1,15 +1,14 @@
 ///////////////////////////////////////////
-// fdivsqrtuslc4.sv
+// fdivsqrtqsel4.sv
 //
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
 // Modified:13 January 2022
 //
-// Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection
+// Purpose: Radix 4 Quotient Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,25 +26,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fdivsqrtuslc4 (
-  input  logic [2:0] Dmsbs,             // U0.3 fractional bits after implicit leading 1
-  input  logic [4:0] Smsbs,             // U1.4 leading bits of square root approximation
-  input  logic [7:0] WSmsbs, WCmsbs,    // Q4.4 redundant residual most significant bits
-  input  logic       Sqrt, j0, j1,
-  output logic [3:0] udigit             // {2, 1, -1, -2} digit is 0 if none are hot
+`include "wally-config.vh"
+
+module fdivsqrtqsel4 (
+  input  logic [2:0] Dmsbs,
+  input  logic [4:0] Smsbs,
+  input  logic [7:0] WSmsbs, WCmsbs,
+  input  logic Sqrt, j1,
+  output logic [3:0] udigit
 );
-  logic [7:0] PreWmsbs;                 // Q4.4 nonredundant residual msbs
-  logic [6:0] Wmsbs;                    // Q4.3 truncated nonredundant residual
-  logic [2:0] A;                        // U0.3 upper bits of D or Smsbs, discarding integer bit
+	logic [6:0] Wmsbs;
+	logic [7:0] PreWmsbs;
+	logic [2:0] A;
 
-  assign PreWmsbs = WCmsbs + WSmsbs;    // add redundant residual to find msbs
-  assign Wmsbs = PreWmsbs[7:1];         // truncate least significant bit to Q4.3 to index table
-  // D = 0001.xxx...
-  // Dmsbs = |   |
+	assign PreWmsbs = WCmsbs + WSmsbs;
+	assign Wmsbs = PreWmsbs[7:1];
+	// D = 0001.xxx...
+	// Dmsbs = |   |
   // W =      xxxx.xxx...
-  // Wmsbs = |        |
+	// Wmsbs = |        |
 
-  logic [3:0] USel4[1023:0];            // 1024-bit table indexed with 3 bits of A and 7 bits of Wmsbs
+	logic [3:0] USel4[1023:0];
 
   // Prepopulate selection table; this is constant at compile time
   always_comb begin 
@@ -102,12 +103,11 @@ module fdivsqrtuslc4 (
   // Select A
   always_comb
     if (Sqrt) begin 
-      if (j1)                 A = 3'b101;     // on first sqrt iteration        A = .101
-      else if (Smsbs[4] == 1) A = 3'b111;     // if S = 1.0000, use             A = .111
-      else                    A = Smsbs[2:0]; // otherwise use                  A = 2S (in U0.3 format)
-    end else                  A = Dmsbs;      // division                       A = D (IN U0.3 format, dropping leading 1)
+      if (j1) A = 3'b101;
+      else if (Smsbs == 5'b10000) A = 3'b111;
+      else A = Smsbs[2:0];
+    end else A = Dmsbs;
 
   // Select quotient digit from lookup table based on A and W
-  // On step j = 0 for square root, always select u_0 = 1
-  assign udigit = (Sqrt & j0) ? 4'b0100 : USel4[{A,Wmsbs}];
+	assign udigit = USel4[{A,Wmsbs}];
 endmodule
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
new file mode 100644
index 000000000..882458106
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
@@ -0,0 +1,91 @@
+///////////////////////////////////////////
+// fdivsqrtqsel4cmp.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
+// Modified:13 January 2022
+//
+// Purpose: Comparator-based Radix 4 Quotient Digit Selection
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtqsel4cmp (
+  input  logic [2:0] Dmsbs,
+  input  logic [4:0] Smsbs,
+  input  logic [7:0] WSmsbs, WCmsbs,
+  input  logic SqrtE, j1,
+  output logic [3:0] udigit
+);
+	logic [6:0] Wmsbs;
+	logic [7:0] PreWmsbs;
+	logic [2:0] A;
+
+	assign PreWmsbs = WCmsbs + WSmsbs;
+	assign Wmsbs = PreWmsbs[7:1];
+	// D = 0001.xxx...
+	// Dmsbs = |   |
+  // W =      xxxx.xxx...
+	// Wmsbs = |        |
+
+  logic [6:0] mk2, mk1, mk0, mkm1;
+  logic [6:0] mks2[7:0], mks1[7:0]; 
+
+  // Prepopulate table of mks0
+  assign mks2[0] = 12;
+  assign mks2[1] = 14;
+  assign mks2[2] = 16;
+  assign mks2[3] = 17;
+  assign mks2[4] = 18;
+  assign mks2[5] = 20;
+  assign mks2[6] = 22;
+  assign mks2[7] = 23;
+  assign mks1[0] = 4;
+  assign mks1[1] = 4;
+  assign mks1[2] = 6;
+  assign mks1[3] = 6;
+  assign mks1[4] = 6;
+  assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
+  assign mks1[6] = 8;
+  assign mks1[7] = 8;
+
+  // Choose A for current operation
+ always_comb
+    if (SqrtE) begin 
+      if (j1) A = 3'b101;
+      else if (Smsbs == 5'b10000) A = 3'b111;
+      else A = Smsbs[2:0];
+    end else A = Dmsbs;
+
+  // Choose selection constants based on a
+  assign mk2 = mks2[A];
+  assign mk1 = mks1[A];
+  assign mk0 = -mks1[A];
+  assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table
+ 
+  // Compare residual W to selection constants to choose digit
+  always_comb 
+    if ($signed(Wmsbs) >= $signed(mk2)) udigit = 4'b1000; // choose 2
+    else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1
+    else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0
+    else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1
+    else udigit = 4'b0001; // choose -2	
+endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
similarity index 53%
rename from src/fpu/fdivsqrt/fdivsqrtstage2.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index 06ac4ec82..63ab6c059 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: radix-2 divsqrt recurrence stage
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,50 +26,60 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
 
-module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.DIVb+3:0] D, DBar,        // Q4.DIVb
-  input  logic [P.DIVb:0]   U, UM,          // U1.DIVb
-  input  logic [P.DIVb+3:0] WS, WC,         // Q4.DIVb
-  input  logic [P.DIVb+1:0] C,              // Q2.DIVb
-  input  logic              SqrtE,
-  output logic              un,
-  output logic [P.DIVb+1:0] CNext,          // Q2.DIVb
-  output logic [P.DIVb:0]   UNext, UMNext,  // U1.DIVb
-  output logic [P.DIVb+3:0] WSNext, WCNext  // Q4.DIVb
+/* verilator lint_off UNOPTFLAT */
+module fdivsqrtstage2 (
+  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0]  DBar, 
+  input  logic [`DIVb:0] U, UM,
+  input  logic [`DIVb+3:0]  WS, WC,
+  input  logic [`DIVb+1:0] C,
+  input  logic SqrtE,
+  output logic un,
+  output logic [`DIVb+1:0] CNext,
+  output logic [`DIVb:0] UNext, UMNext, 
+  output logic [`DIVb+3:0]  WSNext, WCNext
 );
+ /* verilator lint_on UNOPTFLAT */
 
-  logic [P.DIVb+3:0]        Dsel;     // Q4.DIVb
-  logic                     up, uz;
-  logic [P.DIVb+3:0]        F;        // Q4.DIVb
-  logic [P.DIVb+3:0]        AddIn;    // Q4.DIVb
-  logic [P.DIVb+3:0]        WSA, WCA; // Q4.DIVb
+  logic [`DIVb+3:0]  Dsel;
+  logic up, uz;
+  logic [`DIVb+3:0] F;
+  logic [`DIVb+3:0] AddIn;
+  logic [`DIVb+3:0]  WSA, WCA;
 
-  // Quotient Selection logic
+  // Qmient Selection logic
   // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un)
-  fdivsqrtuslc2 uslc2(.WS(WS[P.DIVb+3:P.DIVb]), .WC(WC[P.DIVb+3:P.DIVb]), .up, .uz, .un);
+  // q encoding:
+	// 1000 = +2
+	// 0100 = +1
+	// 0000 =  0
+	// 0010 = -1
+	// 0001 = -2
+  fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
 
   // Sqrt F generation.  Extend C, U, UM to Q4.k
-  fdivsqrtfgen2 #(P) fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
+  fdivsqrtfgen2 fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
 
   // Divisor multiple
   always_comb
     if      (up) Dsel = DBar;
     else if (uz) Dsel = '0;
-    else         Dsel = D; // un
+    else         Dsel = {4'b0001, D}; // un
 
-  // Residual Update
+  // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
-  mux2 #(P.DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
-  csa #(P.DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
+  mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
+  csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
   assign WSNext = WSA << 1;
   assign WCNext = WCA << 1;
 
   // Shift thermometer code C
-  assign CNext = {1'b1, C[P.DIVb+1:1]};
+  assign CNext = {1'b1, C[`DIVb+1:1]};
 
   // Unified On-The-Fly Converter to accumulate result
-  fdivsqrtuotfc2 #(P) uotfc2(.up, .un, .C(CNext), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc2 uotfc2(.up, .un, .C(CNext), .U, .UM, .UNext, .UMNext);
 endmodule
 
 
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
new file mode 100644
index 000000000..007dd18bb
--- /dev/null
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -0,0 +1,98 @@
+///////////////////////////////////////////
+// fdivsqrtstage4.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
+// Modified:13 January 2022
+//
+// Purpose: radix-4 divsqrt recurrence stage
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtstage4 (
+  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0]  DBar, D2, DBar2,
+  input  logic [`DIVb:0] U, UM,
+  input  logic [`DIVb+3:0]  WS, WC,
+  input  logic [`DIVb+1:0] C,
+  input  logic SqrtE, j1,
+  output logic [`DIVb+1:0] CNext,
+  output logic un,
+  output logic [`DIVb:0] UNext, UMNext, 
+  output logic [`DIVb+3:0]  WSNext, WCNext
+);
+
+  logic [`DIVb+3:0]  Dsel;
+  logic [3:0]     udigit;
+  logic [`DIVb+3:0] F;
+  logic [`DIVb+3:0] AddIn;
+  logic [4:0] Smsbs;
+  logic [2:0] Dmsbs;
+  logic [7:0] WCmsbs, WSmsbs;
+  logic CarryIn;
+  logic [`DIVb+3:0]  WSA, WCA;
+
+  // Digit Selection logic
+  // u encoding:
+	// 1000 = +2
+	// 0100 = +1
+	// 0000 =  0
+	// 0010 = -1
+	// 0001 = -2
+  assign Smsbs = U[`DIVb:`DIVb-4];
+  assign Dmsbs = D[`DIVb-1:`DIVb-3];
+  assign WCmsbs = WC[`DIVb+3:`DIVb-4];
+  assign WSmsbs = WS[`DIVb+3:`DIVb-4];
+
+  fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit);
+  assign un = 1'b0; // unused for radix 4
+
+  // F generation logic
+  fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
+
+  // Divisor multiple logic
+  always_comb
+    case (udigit)
+      4'b1000: Dsel = DBar2;
+      4'b0100: Dsel = DBar;
+      4'b0000: Dsel = '0;
+      4'b0010: Dsel = {3'b0, 1'b1, D};
+      4'b0001: Dsel = D2;
+      default: Dsel = 'x;
+    endcase
+
+  // Residual Update
+  //  {WS, WC}}Next = (WS + WC - qD or F) << 2
+  assign AddIn = SqrtE ? F : Dsel;
+  assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D 
+  csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
+  assign WSNext = WSA << 2;
+  assign WCNext = WCA << 2;
+
+  // Shift thermometer code C
+  assign CNext = {2'b11, C[`DIVb+1:2]};
+ 
+  // On-the-fly converter to accumulate result
+  fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
+endmodule
+
+
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
similarity index 72%
rename from src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
index db858cb0b..65b8940ac 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,20 +26,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 ///////////////////////////////
 // Unified OTFC, Radix 2 //
 ///////////////////////////////
-module fdivsqrtuotfc2 import cvw::*;  #(parameter cvw_t P) (
-  input  logic             up, un,
-  input  logic [P.DIVb+1:0] C,                // Q2.DIVb
-  input  logic [P.DIVb:0]   U, UM,            // U1.DIVb  UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer
-  output logic [P.DIVb:0]   UNext, UMNext     // U1.DIVb
+module fdivsqrtuotfc2(
+  input  logic         up, un,
+  input  logic [`DIVb+1:0] C,
+  input logic [`DIVb:0] U, UM,
+  output logic [`DIVb:0] UNext, UMNext
 );
   //  The on-the-fly converter transfers the divsqrt
   //  bits to the quotient as they come.
-  logic [P.DIVb:0] K;                         // U1.DIVb one-hot 
+  logic [`DIVb:0] K;
 
-  assign K = (C[P.DIVb:0] & ~(C[P.DIVb:0] << 1)); // Thermometer to one hot encoding  
+  assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); // Thermometer to one hot encoding
 
   always_comb begin
     if (up) begin
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
similarity index 79%
rename from src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
rename to pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
index 3d842f9a8..a1416384b 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,17 +26,19 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fdivsqrtuotfc4 import cvw::*;  #(parameter cvw_t P) (
-  input  logic [3:0]     udigit,
-  input  logic [P.DIVb:0] U, UM,          // U1.DIVb  UM is actually U - 1 ulp and starts negative, but this representation still produces the right answer
-  input  logic [P.DIVb:0] C,              // Q1.DIVb
-  output logic [P.DIVb:0] UNext, UMNext   // U1.DIVb
+`include "wally-config.vh"
+
+module fdivsqrtuotfc4(
+  input  logic [3:0]   udigit,
+  input  logic [`DIVb:0] U, UM,
+  input  logic [`DIVb:0] C,
+  output logic [`DIVb:0] UNext, UMNext
 );
   //  The on-the-fly converter transfers the square root 
   //  bits to the quotient as they come.
   //  Use this otfc for division and square root.
 
-  logic [P.DIVb:0] K1, K2, K3;            // U1.DIVb
+  logic [`DIVb:0] K1, K2, K3;       
   assign K1 = (C&~(C << 1));        // K
   assign K2 = ((C << 1)&~(C << 2)); // 2K
   assign K3 = (C & ~(C << 2));      // 3K
diff --git a/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv
similarity index 97%
rename from src/fpu/fhazard.sv
rename to pipelined/src/fpu/fhazard.sv
index c31324ad1..dadbf6d4f 100644
--- a/src/fpu/fhazard.sv
+++ b/pipelined/src/fpu/fhazard.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,6 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module fhazard(
   input  logic [4:0]  Adr1D, Adr2D, Adr3D,                // read data adresses
   input  logic [4:0]  Adr1E, Adr2E, Adr3E,                // read data adresses
@@ -57,6 +58,7 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
   
+
     // if the needed value is in the memory stage - input 2
     if ((Adr2E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -64,6 +66,7 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
 
+
     // if the needed value is in the memory stage - input 3
     if ((Adr3E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -71,4 +74,5 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
   end 
+
 endmodule
diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv
new file mode 100644
index 000000000..437c698ec
--- /dev/null
+++ b/pipelined/src/fpu/fma/fma.sv
@@ -0,0 +1,97 @@
+///////////////////////////////////////////
+// fma.sv
+//
+// Written:  6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
+// Modified: 
+//
+// Purpose: Floating point multiply-accumulate of configurable size
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fma(
+  input  logic                        Xs, Ys, Zs,             // input's signs
+  input  logic [`NE-1:0]              Xe, Ye, Ze,             // input's biased exponents in B(NE.0) format
+  input  logic [`NF:0]                Xm, Ym, Zm,             // input's significands in U(0.NF) format
+  input  logic                        XZero, YZero, ZZero,    // is the input zero
+  input  logic [2:0]                  OpCtrl,                 // operation control
+  output logic                        ASticky,                // sticky bit that is calculated during alignment
+  output logic [3*`NF+3:0]            Sm,                     // the positive sum's significand
+  output logic                        InvA,                   // Was A inverted for effective subtraction (P-A or -P+A)
+  output logic                        As,                     // the aligned addend's sign (modified Z sign for other opperations)
+  output logic                        Ps,                     // the product's sign
+  output logic                        Ss,                     // the sum's sign
+  output logic [`NE+1:0]              Se,                     // the sum's exponent
+  output logic [$clog2(3*`NF+5)-1:0]  SCnt                    // normalization shift count
+);
+
+  //  OpCtrl:
+  //    Fma: {not multiply-add?, negate prod?, negate Z?}
+  //        000 - fmadd
+  //        001 - fmsub
+  //        010 - fnmsub
+  //        011 - fnmadd
+  //        100 - mul
+  //        110 - add
+  //        111 - sub
+
+  logic [2*`NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
+  logic [3*`NF+3:0]   Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
+  logic [3*`NF+3:0]   AmInv;      // aligned addend's mantissa possibly inverted
+  logic [2*`NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
+  logic               KillProd;   // set the product to zero before addition if the product is too small to matter
+  logic [`NE+1:0]     Pe;         // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Calculate the product
+  //      - When multipliying two fp numbers, add the exponents
+  //      - Subtract the bias (XExp + YExp has two biases, one from each exponent)
+  //      - If the product is zero then kill the exponent
+  //      - Multiply the mantissas
+  ///////////////////////////////////////////////////////////////////////////////
+  
+
+  // calculate the product's exponent 
+  fmaexpadd expadd(.Xe, .Ye, .XZero, .YZero, .Pe);
+
+  // multiplication of the mantissa's
+  fmamult mult(.Xm, .Ym, .Pm);
+  
+  // calculate the signs and take the opperation into account
+  fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA);
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Alignment shifter
+  ///////////////////////////////////////////////////////////////////////////////
+  fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ASticky, .KillProd);
+                      
+  // ///////////////////////////////////////////////////////////////////////////////
+  // // Addition/LZA
+  // ///////////////////////////////////////////////////////////////////////////////
+      
+  fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
+
+  fmalza #(3*`NF+4) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
+  
+endmodule
+
+
diff --git a/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv
similarity index 55%
rename from src/fpu/fma/fmaadd.sv
rename to pipelined/src/fpu/fma/fmaadd.sv
index 4942f9d9f..b8b61bd6e 100644
--- a/src/fpu/fma/fmaadd.sv
+++ b/pipelined/src/fpu/fma/fmaadd.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: FMA significand adder
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,50 +26,52 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fmaadd import cvw::*;  #(parameter cvw_t P) (
-  input  logic [3*P.NF+5:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
-  input  logic [P.NE-1:0]      Ze,         // exponent of Z
-  input  logic                 Ps,         // the product sign and the alligend addeded's sign (Modified Z sign for other operations)
-  input  logic [P.NE+1:0]      Pe,         // product's exponet
-  input  logic [2*P.NF+1:0]    Pm,         // the product's mantissa
-  input  logic                 InvA,       // invert the aligned addend
-  input  logic                 KillProd,   // should the product be set to 0
-  input  logic                 ASticky,    // Alighed addend's sticky bit
-  output logic [3*P.NF+5:0]    AmInv,      // aligned addend possibly inverted
-  output logic [2*P.NF+1:0]    PmKilled,   // the product's mantissa possibly killed
-  output logic                 Ss,         // sum's sign    
-  output logic [P.NE+1:0]      Se,         // sum's exponent
-  output logic [3*P.NF+5:0]    Sm          // the positive sum
+`include "wally-config.vh"
+
+module fmaadd(
+  input  logic [3*`NF+3:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
+  input  logic [`NE-1:0]      Ze,         // exponent of Z
+  input  logic                Ps,         // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
+  input  logic [`NE+1:0]      Pe,         // product's exponet
+  input  logic [2*`NF+1:0]    Pm,         // the product's mantissa
+  input  logic                InvA,       // invert the aligned addend
+  input  logic                KillProd,   // should the product be set to 0
+  input  logic                ASticky,    // Alighed addend's sticky bit
+  output logic [3*`NF+3:0]    AmInv,      // aligned addend possibly inverted
+  output logic [2*`NF+1:0]    PmKilled,   // the product's mantissa possibly killed
+  output logic                Ss,         // sum's sign    
+  output logic [`NE+1:0]      Se,         // sum's exponent
+  output logic [3*`NF+3:0]    Sm          // the positive sum
 );
 
-  logic [3*P.NF+5:0]    PreSum, NegPreSum; // possibly negative sum
-  logic                 NegSum;            // was the sum negative
+  logic [3*`NF+3:0]    PreSum, NegPreSum; // possibly negitive sum
+  logic                NegSum;            // was the sum negitive
 
   ///////////////////////////////////////////////////////////////////////////////
   // Addition
   ///////////////////////////////////////////////////////////////////////////////
   
   // Choose an inverted or non-inverted addend.  Put carry into adder/LZA for addition
-  assign AmInv = InvA ? ~Am : Am;
+  assign AmInv = {3*`NF+4{InvA}}^Am;
   // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
-  assign PmKilled = KillProd ? 0 : Pm;
+  assign PmKilled = {2*`NF+2{~KillProd}}&Pm;
   // Do the addition
-  //      - calculate a positive and negative sum in parallel
-  // if there was a small negative number killed in the alignment stage one needs to be subtracted from the sum
+  //      - calculate a positive and negitive sum in parallel
+  // if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum
   //      prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation 
   //          ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA
   //      addend - prod where product is killed (and not exactly zero) then don't add +1 from negation 
   //          ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA
   //          in this case this result is only ever selected when InvA=1 so we can remove &InvA
-  assign {NegSum, PreSum} = {{P.NF+3{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*P.NF+5{1'b0}}, (~ASticky|KillProd)&InvA};
-  assign NegPreSum = Am + {{P.NF+2{1'b1}}, ~PmKilled, 2'b0} + {(3*P.NF+3)'(0), ~ASticky|~KillProd, 2'b0};
+  assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*`NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
+  assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*`NF+2)'(0), ~ASticky|~KillProd, 1'b0};
     
   // Choose the positive sum and accompanying LZA result.
   assign Sm = NegSum ? NegPreSum : PreSum;
-  // is the result negative
-  //  if p - z is the Sum negative
+  // is the result negitive
+  //  if p - z is the Sum negitive
   //  if -p + z is the Sum positive
-  //  if -p - z then the Sum is negative
+  //  if -p - z then the Sum is negitive
   assign Ss = NegSum^Ps; 
   assign Se = KillProd ? {2'b0, Ze} : Pe;
 endmodule
diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv
new file mode 100644
index 000000000..b51c2a7f1
--- /dev/null
+++ b/pipelined/src/fpu/fma/fmaalign.sv
@@ -0,0 +1,97 @@
+
+///////////////////////////////////////////
+// fmaalign.sv
+//
+// Written:  6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
+// Modified: 
+//
+// Purpose: FMA alginment shift
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fmaalign(
+  input  logic [`NE-1:0]      Xe, Ye, Ze,         // biased exponents in B(NE.0) format
+  input  logic [`NF:0]        Zm,                 // significand in U(0.NF) format]
+  input  logic                XZero, YZero, ZZero,// is the input zero
+  output logic [3*`NF+3:0]    Am,                 // addend aligned for addition in U(NF+5.2NF+1)
+  output logic                ASticky,            // Sticky bit calculated from the aliged addend
+  output logic                KillProd            // should the product be set to zero
+);
+
+  logic [`NE+1:0]             ACnt;           // how far to shift the addend to align with the product in Q(NE+2.0) format
+  logic [4*`NF+3:0]           ZmShifted;      // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
+  logic [4*`NF+3:0]           ZmPreshifted;   // input to the alignment shifter U(NF+5.3NF+1)
+  logic                       KillZ;          // should the addend be killed
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Alignment shifter
+  ///////////////////////////////////////////////////////////////////////////////
+
+  // determine the shift count for alignment
+  //      - negitive means Z is larger, so shift Z left
+  //      - positive means the product is larger, so shift Z right
+  // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
+  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+2) - {2'b0, Ze};
+
+  // Defualt Addition with only inital left shift
+  //          |   53'b0    |  106'b(product)  | 1'b0 |
+  //          | addnend |
+
+  assign ZmPreshifted = {Zm,(3*`NF+3)'(0)};
+  
+  assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
+  assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(3));
+
+  always_comb begin
+    // If the product is too small to effect the sum, kill the product
+
+    //          |   53'b0    |  106'b(product)  | 1'b0 |
+    //  | addnend |
+    if (KillProd) begin
+        ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+1)'(0)};
+        ASticky = ~(XZero|YZero);
+
+    // If the addend is too small to effect the addition        
+    //      - The addend has to shift two past the end of the product to be considered too small
+    //      - The 2 extra bits are needed for rounding
+
+    //          |   53'b0    |  106'b(product)  | 1'b0 |
+    //                                                      | addnend |
+    end else if (KillZ)  begin
+        ZmShifted = 0;
+        ASticky = ~ZZero;
+
+    // If the Addend is shifted right
+    //          |   53'b0    |  106'b(product)  | 1'b0 |
+    //                                    | addnend |
+    end else begin
+        ZmShifted = ZmPreshifted >> ACnt;
+        ASticky = |(ZmShifted[`NF-1:0]); 
+
+    end
+  end
+
+  assign Am = ZmShifted[4*`NF+3:`NF];
+
+endmodule
+
diff --git a/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv
similarity index 70%
rename from src/fpu/fma/fmaexpadd.sv
rename to pipelined/src/fpu/fma/fmaexpadd.sv
index 4ad254f79..3c615274f 100644
--- a/src/fpu/fma/fmaexpadd.sv
+++ b/pipelined/src/fpu/fma/fmaexpadd.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: FMA exponent addition
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,16 +26,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fmaexpadd import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.NE-1:0]      Xe, Ye,         // input's exponents
-  input  logic                 XZero, YZero,   // are the inputs zero
-  output logic [P.NE+1:0]      Pe              // product's exponent B^(1023)NE+2
+`include "wally-config.vh"
+
+module fmaexpadd(    
+  input  logic [`NE-1:0]      Xe, Ye,         // input's exponents
+  input  logic                XZero, YZero,   // are the inputs zero
+  output logic [`NE+1:0]      Pe              // product's exponent B^(1023)NE+2
 );
 
-  logic                        PZero;          // is the product zero?
+  logic                       PZero;          // is the product zero?
   
   // kill the exponent if the product is zero - either X or Y is 0
   assign PZero = XZero | YZero;
-  assign Pe    = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)});
+  assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)});
 
 endmodule
diff --git a/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv
similarity index 63%
rename from src/fpu/fma/fmalza.sv
rename to pipelined/src/fpu/fma/fmalza.sv
index 417b9de28..640e4ed80 100644
--- a/src/fpu/fma/fmalza.sv
+++ b/pipelined/src/fpu/fma/fmalza.sv
@@ -6,11 +6,10 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
 //    See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,32 +27,34 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fmalza #(WIDTH, NF) ( 
-  input logic [WIDTH-1:0]             A,              // addend
-  input logic [2*NF+1:0]              Pm,             // product
-  input logic                         Cin,            // carry in
-  input logic                         sub,            // subtraction
-  output logic [$clog2(WIDTH+1)-1:0]  SCnt            // normalization shift count for the positive result
+`include "wally-config.vh"
+
+module fmalza #(WIDTH) ( 
+  input logic [WIDTH-1:0]             A,      // addend
+  input logic [2*`NF+1:0]             Pm,     // product
+  input logic 		                    Cin,    // carry in
+  input logic                         sub,    // subtraction
+  output logic [$clog2(WIDTH+1)-1:0]  SCnt    // normalization shift count for the positive result
 ); 
 
-  logic [WIDTH:0]                     F;              // most significant bit of F indicates leading digit
+  logic [WIDTH:0] 	                  F;              // most significant bit of F indicates leading digit
   logic [WIDTH-1:0]                   B;              // zero-extended product with same size as aligned A
   logic [WIDTH-1:0]                   P, G, K;        // propagate, generate, kill for each column
   logic [WIDTH-1:0]                   Pp1, Gm1, Km1;  // propagate shifted right by 1, generate/kill shifted left 1
 
-  assign B = {{(NF+2){1'b0}}, Pm, 2'b0};              // Zero extend product
+  assign B = {{(`NF+1){1'b0}}, Pm, 1'b0}; // Zero extend product
 
   assign P = A^B;
   assign G = A&B;
-  assign K = ~A&~B;
+  assign K= ~A&~B;
 
-  assign Pp1 = {sub, P[WIDTH-1:1]};                   // shift P right by 1 (for P_i+1) , use subtract flag in most significant bit
-  assign Gm1 = {G[WIDTH-2:0], Cin};                   // shift G left by 1 (for G_i-1) and bring in Cin
-  assign Km1 = {K[WIDTH-2:0], ~Cin};                  // shift K left by 1 (for K_i-1) and bring in Cin
+  assign Pp1 = {sub, P[WIDTH-1:1]};   // shift P right by 1 (for P_i+1) , use subtract flag in most significant bit
+  assign Gm1 = {G[WIDTH-2:0], Cin};   // shift G left by 1 (for G_i-1) and bring in Cin
+  assign Km1 = {K[WIDTH-2:0], ~Cin};  // shift K left by 1 (for K_i-1) and bring in Cin
   
   // Apply function to determine Leading pattern
   //      - note: Schmookler01 uses the numbering system where 0 is the most significant bit
-  assign F[WIDTH]     = ~sub&P[WIDTH-1];
+  assign F[WIDTH] = ~sub&P[WIDTH-1];
   assign F[WIDTH-1:0] = (Pp1&(G&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | G&~Gm1));
 
   lzc #(WIDTH+1) lzc (.num(F), .ZeroCnt(SCnt));
diff --git a/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv
similarity index 81%
rename from src/fpu/fma/fmamult.sv
rename to pipelined/src/fpu/fma/fmamult.sv
index ea0ea2238..541ba3687 100644
--- a/src/fpu/fma/fmamult.sv
+++ b/pipelined/src/fpu/fma/fmamult.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,10 +26,13 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fmamult import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.NF:0]     Xm, Ym, // x and y significand
-  output logic [2*P.NF+1:0] Pm      // product's significand
+`include "wally-config.vh"
+
+module fmamult(
+  input  logic [`NF:0]     Xm, Ym, // x and y significand
+  output logic [2*`NF+1:0] Pm      // product's significand
 );
 
   assign Pm = Xm * Ym;
 endmodule
+
diff --git a/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv
similarity index 73%
rename from src/fpu/fma/fmasign.sv
rename to pipelined/src/fpu/fma/fmasign.sv
index 8220f0aad..a2308da7f 100644
--- a/src/fpu/fma/fmasign.sv
+++ b/pipelined/src/fpu/fma/fmasign.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: FMA Sign Logic
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,15 +26,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module fmasign(    
-  input  logic [2:0]  OpCtrl,     // operation contol
+  input  logic [2:0]  OpCtrl,     // opperation contol
   input  logic        Xs, Ys, Zs, // sign of the inputs
-  output logic        Ps,         // the product's sign - takes operation into account
-  output logic        As,         // aligned addend sign used in fma - takes operation into account
+  output logic        Ps,         // the product's sign - takes opperation into account
+  output logic        As,         // aligned addend sign used in fma - takes opperation into account
   output logic        InvA        // Effective subtraction: invert addend
 );
 
-  assign Ps   = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]); // product sign.  Negate for FMNADD or FNMSUB
-  assign As   = Zs^OpCtrl[0];                     // flip addend sign for subtraction
-  assign InvA = As ^ Ps;                          // Effective subtraction when product and addend have opposite signs
+  assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]); // product sign.  Negate for FMNADD or FNMSUB
+  assign As = Zs^OpCtrl[0];                     // flip addend sign for subtraction
+  assign InvA = As ^ Ps;                        // Effective subtraction when product and addend have opposite signs
 endmodule
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
new file mode 100755
index 000000000..6abb76b0b
--- /dev/null
+++ b/pipelined/src/fpu/fpu.sv
@@ -0,0 +1,355 @@
+///////////////////////////////////////////
+// fpu.sv
+//
+// Written: me@KatherineParry.com, James Stine, Brett Mathis, David Harris
+// Modified: 6/23/2021
+//
+// Purpose: Floating Point Unit Top-Level Interface
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fpu (
+  input  logic 		          clk,
+  input  logic 		          reset,
+  // Hazards
+  input  logic 		          StallE, StallM, StallW, // stall signals (from HZU)
+  input  logic 		          FlushE, FlushM, FlushW, // flush signals (from HZU)
+  output logic 		          FPUStallD,     // Stall the decode stage (To HZU)
+  output logic 		          FDivBusyE,     // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
+  // CSRs
+  input  logic [1:0]        STATUS_FS,     // Is floating-point enabled? (From privileged unit)
+  input  logic [2:0] 	      FRM_REGW,      // Rounding mode (from CSR)
+  // Decode stage 
+  input  logic [31:0] 	    InstrD,        // instruction (from IFU)
+  // Execute stage 
+  input  logic [2:0] 	      Funct3E,       // Funct fields of instruction specify type of operations
+  input  logic 		          IntDivE, W64E, // Integer division on FPU
+  input  logic [`XLEN-1:0]  ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
+  input  logic [4:0] 	      RdE,           // which FP register to write to (from IEU)
+  output logic 		          FWriteIntE,    // integer register write enable (to IEU)
+  output logic              FCvtIntE,      // Convert to int (to IEU)
+  // Memory stage 
+  input  logic [2:0] 	      Funct3M,       // Funct fields of instruction specify type of operations
+  input  logic [4:0] 	      RdM,           // which FP register to write to (from IEU)
+  output logic 		          FRegWriteM,    // FP register write enable (to privileged unit)
+  output logic 		          FpLoadStoreM,  // Fp load instruction? (to LSU)
+  output logic [`FLEN-1:0]  FWriteDataM,   // Data to be written to memory (to LSU) 
+  output logic [`XLEN-1:0]  FIntResM,      // data to be written to integer register (to IEU)
+  output logic 		          IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
+  output logic [4:0] 	      SetFflagsM,    // FPU flags (to privileged unit)
+  // Writeback stage 
+  input  logic [4:0] 	      RdW,           // which FP register to write to (from IEU)
+  input  logic [`FLEN-1:0]  ReadDataW,     // Read data (from LSU)
+  output logic [`XLEN-1:0]  FCvtIntResW,   // convert result to to be written to integer register (to IEU)
+  output logic              FCvtIntW,      // select FCvtIntRes (to IEU)
+  output logic [`XLEN-1:0]  FIntDivResultW // Result from integer division (to IEU)
+);
+
+  // RISC-V FPU specifics:
+  //    - multiprecision support uses NAN-boxing, putting 1's in unused msbs
+  //    - RISC-V detects underflow after rounding
+
+  // control signals
+  logic 		            FRegWriteW;                        // FP register write enable
+  logic [2:0] 	        FrmM;                              // FP rounding mode
+  logic [`FMTBITS-1:0]  FmtE, FmtM;                        // FP precision 0-single 1-double
+  logic 		            FDivStartE, IDivStartE;            // Start division or squareroot
+  logic 		            FWriteIntM;                        // Write to integer register
+  logic [1:0] 	        ForwardXE, ForwardYE, ForwardZE;   // forwarding mux control signals
+  logic [2:0] 	        OpCtrlE, OpCtrlM;                  // Select which opperation to do in each component
+  logic [1:0] 	        FResSelE, FResSelM, FResSelW;      // Select one of the results that finish in the memory stage
+  logic [1:0] 	        PostProcSelE, PostProcSelM;        // select result in the post processing unit
+  logic [4:0] 	        Adr1D, Adr2D, Adr3D;               // register adresses of each input
+  logic [4:0] 	        Adr1E, Adr2E, Adr3E;                // register adresses of each input
+  logic                 XEnD, YEnD, ZEnD;                  // X, Y, Z inputs used for current operation
+  logic                 XEnE, YEnE, ZEnE;                  // X, Y, Z inputs used for current operation
+  logic                 FRegWriteE;                        // Write floating-point register
+
+  // regfile signals
+  logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D;                  // Read Data from FP register - decode stage
+  logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E;                  // Read Data from FP register - execute stage
+  logic [`FLEN-1:0] XE;                                   // Input 1 to the various units (after forwarding)
+  logic [`XLEN-1:0] IntSrcXE;                             // Input 1 to the various units (after forwarding)
+  logic [`FLEN-1:0] PreYE, YE;                            // Input 2 to the various units (after forwarding)
+  logic [`FLEN-1:0] PreZE, ZE;                            // Input 3 to the various units (after forwarding)
+
+  // unpacking signals
+  logic 		        XsE, YsE, ZsE;                        // input's sign - execute stage
+  logic 		        XsM, YsM;                             // input's sign - memory stage
+  logic [`NE-1:0]   XeE, YeE, ZeE;                        // input's exponent - execute stage
+  logic [`NE-1:0] 	ZeM;                                  // input's exponent - memory stage
+  logic [`NF:0] 	  XmE, YmE, ZmE;                        // input's significand - execute stage
+  logic [`NF:0] 	  XmM, YmM, ZmM;                        // input's significand - memory stage
+  logic 		        XNaNE, YNaNE, ZNaNE;                  // is the input a NaN - execute stage
+  logic 		        XNaNM, YNaNM, ZNaNM;                  // is the input a NaN - memory stage
+  logic 		        XSNaNE, YSNaNE, ZSNaNE;               // is the input a signaling NaN - execute stage
+  logic 		        XSNaNM, YSNaNM, ZSNaNM;               // is the input a signaling NaN - memory stage
+  logic 		        XSubnormE;                            // is the input subnormal
+  logic 		        XZeroE, YZeroE, ZZeroE;               // is the input zero - execute stage
+  logic 		        XZeroM, YZeroM;                       // is the input zero - memory stage
+  logic 		        XInfE, YInfE, ZInfE;                  // is the input infinity - execute stage
+  logic 		        XInfM, YInfM, ZInfM;                  // is the input infinity - memory stage
+  logic 		        XExpMaxE;                             // is the exponent all ones (max value)
+
+  // Fma Signals
+  logic             FmaAddSubE;                           // Multiply by 1.0 when adding or subtracting
+  logic [1:0]       FmaZSelE;                             // Select Z = Y when adding or subtracting, 0 when multiplying
+  logic [3*`NF+3:0] SmE, SmM;                             // Sum significand
+  logic 			      FmaAStickyE, FmaAStickyM;             // FMA addend sticky bit output
+  logic [`NE+1:0]   SeE,SeM;                              // Sum exponent
+  logic 			      InvAE, InvAM;                         // Invert addend
+  logic 			      AsE, AsM;                             // Addend sign
+  logic 			      PsE, PsM;                             // Product sign
+  logic 			      SsE, SsM;                             // Sum sign
+  logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;               // LZA sum leading zero count
+  
+  // Cvt Signals
+  logic [`NE:0]           CeE, CeM;                       // convert intermediate expoent
+  logic [`LOGCVTLEN-1:0]  CvtShiftAmtE, CvtShiftAmtM;     // how much to shift by
+  logic                   CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
+  logic                   CsE, CsM;                       // convert result sign
+  logic                   IntZeroE, IntZeroM;             // is the integer zero?
+  logic [`CVTLEN-1:0]     CvtLzcInE, CvtLzcInM;           // input to the Leading Zero Counter (priority encoder)
+  logic [`XLEN-1:0]       FCvtIntResM;                    // fcvt integer result (for IEU)
+  
+  // divide signals
+  logic [`DIVb:0]      QmM;                               // fdivsqrt signifcand
+  logic [`NE+1:0]      QeM;                               // fdivsqrt exponent
+  logic                DivStickyM;                        // fdivsqrt sticky bit
+  logic                FDivDoneE, IFDivStartE;            // fdivsqrt control signals
+  logic [`XLEN-1:0]    FIntDivResultM;                    // fdivsqrt integer division result (for IEU)
+
+  // result and flag signals
+  logic [`XLEN-1:0] ClassResE;                            // classify result
+  logic [`FLEN-1:0] CmpFpResE;                            // compare result to FPU (min/max)
+  logic [`XLEN-1:0] CmpIntResE;                           // compare result to IEU (eq/lt/le)
+  logic 		        CmpNVE;                               // compare invalid flag (Not Valid)     
+  logic [`FLEN-1:0] SgnResE;                              // sign injection result
+  logic [`XLEN-1:0] FIntResE;                             // FPU to IEU E-stage result (classify, compare, move)
+  logic [`FLEN-1:0] PostProcResM;                         // Postprocessor output
+  logic [4:0] 	    PostProcFlgM;                         // Postprocessor flags
+  logic  	          PreNVE, PreNVM;                       // selected flag that is ready in the memory stage     
+  logic [`FLEN-1:0] FpResM, FpResW;                       // FPU preliminary result
+  logic [`FLEN-1:0] PreFpResE, PreFpResM;                 // selected result that is ready in the memory stage
+  logic [`FLEN-1:0] FResultW;                             // final FP result being written to the FP register   
+
+  // other signals
+  logic [`FLEN-1:0] AlignedSrcAE;                         // align SrcA from IEU to the floating point format for fmv
+  logic [`FLEN-1:0] BoxedZeroE;                           // Zero value for Z for multiplication, with NaN boxing if needed
+  logic [`FLEN-1:0] BoxedOneE;                            // One value for Z for multiplication, with NaN boxing if needed
+  logic             StallUnpackedM;                       // Stall unpacker outputs during multicycle fdivsqrt
+  logic [`FLEN-1:0] SgnExtXE;                             // Sign-extended X input for move to integer
+
+  //////////////////////////////////////////////////////////////////////////////////////////
+  // Decode Stage: fctrl decoder, read register file
+  //////////////////////////////////////////////////////////////////////////////////////////
+
+  // calculate FP control signals
+  fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
+              .Funct3E, .IntDivE, .InstrD,
+              .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
+              .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
+              .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
+              .IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
+              .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
+              .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
+
+  // FP register file
+  fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
+    .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
+    .a4(RdW), .wd4(FResultW),
+    .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));	
+
+  // D/E pipeline registers  
+  flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
+  flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
+  flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
+
+  //////////////////////////////////////////////////////////////////////////////////////////
+  // Execute Stage: hazards, forwarding, unpacking, execution units
+  //////////////////////////////////////////////////////////////////////////////////////////
+
+  // Hazard unit for FPU: determines if any forwarding or stalls are needed
+  fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, 
+    .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, 
+    .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
+
+  // forwarding muxs
+  mux3  #(`FLEN)  fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
+  mux3  #(`FLEN)  fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
+  mux3  #(`FLEN)  fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
+
+  // Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z
+  generate
+    if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
+    else if(`FPSIZES == 2) 
+        mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
+    else if(`FPSIZES == 3 | `FPSIZES == 4) 
+        mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}, 
+                            {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}, 
+                            {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, 
+                            {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
+  endgenerate
+  assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
+  mux2  #(`FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
+  
+  // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
+  // For add and subtract, Z comes from second source operand
+  generate
+  if(`FPSIZES == 1) assign BoxedZeroE = 0;
+  else if(`FPSIZES == 2) 
+    mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
+  else if(`FPSIZES == 3 | `FPSIZES == 4)
+    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}, 
+                                {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, 
+                                {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, 
+                                (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
+  endgenerate
+  assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]};
+  mux3  #(`FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
+
+  // unpack unit: splits FP inputs into their parts and classifies SNaN, NaN, Subnorm, Norm, Zero, Infifnity
+  unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), 
+    .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
+    .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
+    .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
+    .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
+    .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE));
+  
+  // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
+  fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
+    .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), 
+    .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), .ASticky(FmaAStickyE)); 
+
+  // divide and square root: fdiv, fsqrt, optionally integer division
+  fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
+    .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
+    .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
+    .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
+    .QmM, .FIntDivResultM);
+
+  // compare: fmin/fmax, flt/fle/feq
+  fcmp fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), 
+    .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), 
+    .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), 
+    .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
+
+  // sign injection: fsgnj/fsgnjx/fsgnjn
+  fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XE), .Fmt(FmtE), .SgnRes(SgnResE));
+
+  // classify: fclass
+  fclassify fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), 
+    .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
+
+  // convert: fcvt.*.*
+  fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
+    .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
+    .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
+
+
+  // NaN Box SrcA to convert integer to requested FP size
+  generate
+  if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
+  else if(`FPSIZES == 2) 
+    mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
+  else if(`FPSIZES == 3 | `FPSIZES == 4)
+    mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]}, 
+                            {{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]}, 
+                            {{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]}, 
+                            {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
+  endgenerate
+
+  // select a result that may be written to the FP register
+  mux3  #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
+  assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
+
+  // select the result that may be written to the integer register - to IEU
+  generate
+  if(`FPSIZES == 1)
+    assign SgnExtXE = XE;
+  else if(`FPSIZES == 2) 
+    mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
+  else if(`FPSIZES == 3 | `FPSIZES == 4)
+    mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]}, 
+                                {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, 
+                                {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, 
+                                XE, FmtE, SgnExtXE); 
+  endgenerate
+  if (`FLEN>`XLEN)
+    assign IntSrcXE = SgnExtXE[`XLEN-1:0];
+  else 
+    assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
+  mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
+
+  // E/M pipe registers
+
+  // Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
+  assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE); 
+
+  flopenrc #(`NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
+  flopenrc #(`NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
+  flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
+  flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
+  flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
+  flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM, 
+    {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
+    {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
+  flopenrc #(1)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);      
+  flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
+  flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
+    {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
+    {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
+  flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
+    {CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
+    {CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
+  flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
+
+  //////////////////////////////////////////////////////////////////////////////////////////
+  // Memory Stage: postprocessor and result muxes
+  //////////////////////////////////////////////////////////////////////////////////////////
+
+  postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
+    .FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
+    .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), 
+    .FmaSm(SmM), .DivQe(QeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
+    .CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), 
+    .ToInt(FWriteIntM), .DivSticky(DivStickyM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), 
+    .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
+
+  // FPU flag selection - to privileged
+  mux2  #(5)      FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
+  mux2  #(`FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
+
+  // M/W pipe registers
+  flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); 
+  flopenrc #(`XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); 
+  flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); 
+
+  //////////////////////////////////////////////////////////////////////////////////////////
+  // Writeback Stage: result mux
+  //////////////////////////////////////////////////////////////////////////////////////////
+
+  // select the result to be written to the FP register
+  mux2  #(`FLEN)  FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
+
+endmodule // fpu
diff --git a/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv
similarity index 73%
rename from src/fpu/fregfile.sv
rename to pipelined/src/fpu/fregfile.sv
index 40933de17..1a5a2eecf 100644
--- a/src/fpu/fregfile.sv
+++ b/pipelined/src/fpu/fregfile.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,15 +26,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module fregfile #(parameter FLEN) (
-  input logic              clk, reset,
-  input logic              we4,             // write enable
+`include "wally-config.vh"
+
+module fregfile (
+  input logic 	           clk, reset,
+  input logic 	           we4,             // write enable
   input logic [4:0]        a1, a2, a3, a4,  // adresses
-  input logic [FLEN-1:0]   wd4,             // write data
-  output logic [FLEN-1:0]  rd1, rd2, rd3    // read data
+  input logic [`FLEN-1:0]  wd4,             // write data
+  output logic [`FLEN-1:0] rd1, rd2, rd3    // read data
 );
    
-   logic [FLEN-1:0] rf[31:0];
+   logic [`FLEN-1:0] rf[31:0];
    integer i;
    
    // three ported register file
@@ -44,11 +45,12 @@ module fregfile #(parameter FLEN) (
    // write occurs on falling edge of clock   
    
    always_ff @(negedge clk) // or posedge reset)
-     if (reset) for(i=0; i<32; i++) rf[i] <= '0;
-     else if (we4) rf[a4] <= wd4;  
+     if (reset) for(i=0; i<32; i++) rf[i] <= 0;
+     else if (we4) rf[a4] <= wd4;	
    
-   assign rd1 = rf[a1];
-   assign rd2 = rf[a2];
-   assign rd3 = rf[a3];
+   assign #2 rd1 = rf[a1];
+   assign #2 rd2 = rf[a2];
+   assign #2 rd3 = rf[a3];
    
 endmodule // regfile
+
diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv
new file mode 100755
index 000000000..d5568cabe
--- /dev/null
+++ b/pipelined/src/fpu/fsgninj.sv
@@ -0,0 +1,79 @@
+///////////////////////////////////////////
+// fsgninj.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 6/23/2021
+//
+// Purpose: FPU Sign Injection instructions
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fsgninj (  
+	input  logic        		Xs, Ys,	// X and Y sign bits
+	input  logic [`FLEN-1:0] 	X,		// X
+	input  logic [`FMTBITS-1:0]	Fmt,	// format
+	input  logic [1:0]  		OpCtrl,	// operation control
+	output logic [`FLEN-1:0] 	SgnRes	// result
+);
+
+	logic ResSgn;	// result sign
+
+	// OpCtrl:
+	// 		00 - fsgnj  - directly copy over sign value of Y
+	// 		01 - fsgnjn - negate sign value of Y
+	// 		10 - fsgnjx - XOR sign values of X and Y
+	
+	// calculate the result's sign
+	assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys;
+	
+	// format final result based on precision
+	//    - uses NaN-blocking format
+	//        - if there are any unsused bits the most significant bits are filled with 1s
+	
+  if (`FPSIZES == 1)
+		assign SgnRes = {ResSgn, X[`FLEN-2:0]};
+  else if (`FPSIZES == 2)
+		assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
+  else if (`FPSIZES == 3) begin
+		logic [2:0] SgnBits;
+    always_comb
+      case (Fmt)
+        `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
+        `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
+        `FMT2: SgnBits = {2'b11, ResSgn};
+        default: SgnBits = {3{1'bx}};
+      endcase
+		assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
+	end else if (`FPSIZES == 4) begin
+		logic [3:0] SgnBits;
+    always_comb
+      case (Fmt)
+        `Q_FMT: SgnBits = {ResSgn, X[`D_LEN-1], X[`S_LEN-1], X[`H_LEN-1]};
+        `D_FMT: SgnBits = {1'b1, ResSgn, X[`S_LEN-1], X[`H_LEN-1]};
+        `S_FMT: SgnBits = {2'b11, ResSgn, X[`H_LEN-1]};
+        `H_FMT: SgnBits = {3'b111, ResSgn};
+      endcase
+		assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]};
+	end
+
+endmodule
diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv
similarity index 50%
rename from src/fpu/postproc/cvtshiftcalc.sv
rename to pipelined/src/fpu/postproc/cvtshiftcalc.sv
index 84f5120a0..7297824f3 100644
--- a/src/fpu/postproc/cvtshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Conversion shift calculation
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,20 +26,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic                     XZero,              // is the input zero?
-  input  logic                     ToInt,              // to integer conversion?
-  input  logic                     IntToFp,            // interger to floating point conversion?
-  input  logic [P.FMTBITS-1:0]     OutFmt,             // output format
-  input  logic [P.NE:0]            CvtCe,              // the calculated expoent
-  input  logic [P.NF:0]            Xm,                 // input mantissas
-  input  logic [P.CVTLEN-1:0]      CvtLzcIn,           // input to the Leading Zero Counter (without msb)
-  input  logic                     CvtResSubnormUf,    // is the conversion result subnormal or underlows
-  output logic                     CvtResUf,           // does the cvt result unerflow
-  output logic [P.CVTLEN+P.NF:0]   CvtShiftIn          // number to be shifted
+`include "wally-config.vh"
+
+module cvtshiftcalc(
+  input  logic                    XZero,              // is the input zero?
+  input  logic                    ToInt,              // to integer conversion?
+  input  logic                    IntToFp,            // interger to floating point conversion?
+  input  logic [`FMTBITS-1:0]     OutFmt,             // output format
+  input  logic [`NE:0]            CvtCe,              // the calculated expoent
+  input  logic [`NF:0]            Xm,                 // input mantissas
+  input  logic [`CVTLEN-1:0]      CvtLzcIn,           // input to the Leading Zero Counter (without msb)
+  input  logic                    CvtResSubnormUf,    // is the conversion result subnormal or underlows
+  output logic                    CvtResUf,           // does the cvt result unerflow
+  output logic [`CVTLEN+`NF:0]    CvtShiftIn          // number to be shifted
 );
 
-  logic [$clog2(P.NF):0]           ResNegNF;           // the result's fraction length negated (-NF)
+  logic [$clog2(`NF):0]           ResNegNF;           // the result's fraction length negated (-NF)
 
   ///////////////////////////////////////////////////////////////////////////
   // shifter
@@ -48,7 +49,7 @@ module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
 
   // seclect the input to the shifter
   //      fp  -> int:
-  //          |  P.XLEN  zeros |     mantissa      | 0's if necessary |
+  //          |  `XLEN  zeros |     mantissa      | 0's if nessisary |
   //                          .
   //          Other problems:
   //              - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding)
@@ -56,49 +57,51 @@ module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
   //                  - ex: for the case 0010000.... (double)
   //      ??? -> fp:
   //          - if result is subnormal or underflowed then we want to shift right i.e. shift right then shift left:
-  //              |  P.NF-1  zeros   |     mantissa      | 0's if nessisary | 
+  //              |  `NF-1  zeros   |     mantissa      | 0's if nessisary | 
   //              .
   //          - otherwise:
-  //              |      LzcInM      |  0's if necessary | 
+  //              |     LzcInM      | 0's if nessisary | 
   //              .
   // change to int shift to the left one
   always_comb 
   //                                                        get rid of round bit if needed
   //                                                        |                    add sticky bit if needed
   //                                                        |                    |
-      if (ToInt)                CvtShiftIn = {{P.XLEN{1'b0}}, Xm[P.NF]&~CvtCe[P.NE], Xm[P.NF-1]|(CvtCe[P.NE]&Xm[P.NF]), Xm[P.NF-2:0], {P.CVTLEN-P.XLEN{1'b0}}};
-      else if (CvtResSubnormUf) CvtShiftIn = {{P.NF-1{1'b0}}, Xm, {P.CVTLEN-P.NF+1{1'b0}}};
-      else                      CvtShiftIn = {CvtLzcIn, {P.NF+1{1'b0}}};
+      if (ToInt)               CvtShiftIn = {{`XLEN{1'b0}}, Xm[`NF]&~CvtCe[`NE], Xm[`NF-1]|(CvtCe[`NE]&Xm[`NF]), Xm[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}};
+      else if (CvtResSubnormUf) CvtShiftIn = {{`NF-1{1'b0}}, Xm, {`CVTLEN-`NF+1{1'b0}}};
+      else                     CvtShiftIn = {CvtLzcIn, {`NF+1{1'b0}}};
   
   // choose the negative of the fraction size
-  if (P.FPSIZES == 1) begin
-      assign ResNegNF = -($clog2(P.NF)+1)'(P.NF); 
+  if (`FPSIZES == 1) begin
+      assign ResNegNF = -($clog2(`NF)+1)'(`NF); 
 
-  end else if (P.FPSIZES == 2) begin
-      assign ResNegNF = OutFmt ? -($clog2(P.NF)+1)'(P.NF) : -($clog2(P.NF)+1)'(P.NF1);
+  end else if (`FPSIZES == 2) begin
+      assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1);
 
-  end else if (P.FPSIZES == 3) begin
+  end else if (`FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              P.FMT:  ResNegNF  = -($clog2(P.NF)+1)'(P.NF);
-              P.FMT1: ResNegNF  = -($clog2(P.NF)+1)'(P.NF1);
-              P.FMT2: ResNegNF  = -($clog2(P.NF)+1)'(P.NF2);
-              default: ResNegNF = '0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11.
+              `FMT:  ResNegNF = -($clog2(`NF)+1)'(`NF);
+              `FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1);
+              `FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2);
+              default: ResNegNF = 1'bx;
           endcase
 
-  end else if (P.FPSIZES == 4) begin        
+  end else if (`FPSIZES == 4) begin        
       always_comb
           case (OutFmt)
-              2'h3: ResNegNF = -($clog2(P.NF)+1)'(P.Q_NF);
-              2'h1: ResNegNF = -($clog2(P.NF)+1)'(P.D_NF);
-              2'h0: ResNegNF = -($clog2(P.NF)+1)'(P.S_NF);
-              2'h2: ResNegNF = -($clog2(P.NF)+1)'(P.H_NF);
+              2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF);
+              2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF);
+              2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF);
+              2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF);
           endcase
   end
 
+
+  
   // determine if the result underflows ??? -> fp
   //      - if the first 1 is shifted out of the result then the result underflows
   //      - can't underflow an integer to fp conversions
-  assign CvtResUf = ($signed(CvtCe) < $signed({{P.NE-$clog2(P.NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; 
+  assign CvtResUf = ($signed(CvtCe) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp;
   
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
new file mode 100644
index 000000000..76668516c
--- /dev/null
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -0,0 +1,74 @@
+///////////////////////////////////////////
+// divshiftcalc.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: Division shift calculation
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh"
+
+`include "wally-config.vh"
+
+module divshiftcalc(
+  input  logic [`DIVb:0]              DivQm,              // divsqrt significand
+  input  logic [`NE+1:0]              DivQe,              // divsqrt exponent
+  output logic [`LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
+  output logic [`NORMSHIFTSZ-1:0]     DivShiftIn,         // divsqrt shift input
+  output logic                        DivResSubnorm,      // is the divsqrt result subnormal
+  output logic                        DivSubnormShiftPos  // is the subnormal shift amount positive
+);
+
+  logic [`LOGNORMSHIFTSZ-1:0]         NormShift;          // normalized result shift amount
+  logic [`LOGNORMSHIFTSZ-1:0]         DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
+  logic [`NE+1:0]                     DivSubnormShift;    // subnormal result shift amount
+
+  // is the result subnormal
+  // if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
+  assign DivResSubnorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
+
+  // if the result is subnormal
+  //  00000000x.xxxxxx...                     Exp = DivQe
+  //  .00000000xxxxxxx... >> NF+1             Exp = DivQe+NF+1
+  //  .00xxxxxxxxxxxxx... << DivQe+NF+1  Exp = +1
+  //  .0000xxxxxxxxxxx... >> 1                Exp = 1
+  // Left shift amount  = DivQe+NF+1-1
+  assign DivSubnormShift = (`NE+2)'(`NF)+DivQe;
+  assign DivSubnormShiftPos = ~DivSubnormShift[`NE+1];
+
+  // if the result is normalized
+  //  00000000x.xxxxxx...                     Exp = DivQe
+  //  .00000000xxxxxxx... >> NF+1             Exp = DivQe+NF+1
+  //  00000000.xxxxxxx... << NF               Exp = DivQe+1
+  //  00000000x.xxxxxx... << NF               Exp = DivQe (extra shift done afterwards)
+  //  00000000xx.xxxxx... << 1?               Exp = DivQe-1 (determined after)
+  // inital Left shift amount  = NF
+  // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
+  assign NormShift = (`LOGNORMSHIFTSZ)'(`NF);
+
+  // if the shift amount is negitive then don't shift (keep sticky bit)
+  // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
+  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[`LOGNORMSHIFTSZ-1:0] : '0;
+  assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
+
+  // pre-shift the divider result for normalization
+  assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb-1-`NF{1'b0}}};
+endmodule
diff --git a/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv
similarity index 56%
rename from src/fpu/postproc/flags.sv
rename to pipelined/src/fpu/postproc/flags.sv
index be28a490c..701cf0524 100644
--- a/src/fpu/postproc/flags.sv
+++ b/pipelined/src/fpu/postproc/flags.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,52 +25,53 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
 
-module flags import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 Xs,                     // X sign
-  input  logic [P.FMTBITS-1:0] OutFmt,                 // output format
-  input  logic                 InfIn,                  // is a Inf input being used
-  input  logic                 XInf, YInf, ZInf,       // inputs are infinity
-  input  logic                 NaNIn,                  // is a NaN input being used
-  input  logic                 XSNaN, YSNaN, ZSNaN,    // inputs are signaling NaNs
-  input  logic                 XZero, YZero,           // inputs are zero
-  input  logic [P.NE+1:0]      FullRe,                 // Re with bits to determine sign and overflow
-  input  logic [P.NE+1:0]      Me,                     // exponent of the normalized sum
+module flags(
+  input  logic                Xs,                     // X sign
+  input  logic [`FMTBITS-1:0] OutFmt,                 // output format
+  input  logic                InfIn,                  // is a Inf input being used
+  input  logic                XInf, YInf, ZInf,       // inputs are infinity
+  input  logic                NaNIn,                  // is a NaN input being used
+  input  logic                XSNaN, YSNaN, ZSNaN,    // inputs are signaling NaNs
+  input  logic                XZero, YZero,           // inputs are zero
+  input  logic [`NE+1:0]      FullRe,                 // Re with bits to determine sign and overflow
+  input  logic [`NE+1:0]      Me,                     // exponent of the normalized sum
   // rounding
-  input  logic                 Plus1,                  // do you add one for rounding
-  input  logic                 Round, Guard, Sticky,   // bits used to determine rounding
-  input  logic                 UfPlus1,                // do you add one for rounding for the unbounded exponent result
+  input  logic                Plus1,                  // do you add one for rounding
+  input  logic                Round, Guard, Sticky,   // bits used to determine rounding
+  input  logic                UfPlus1,                // do you add one for rounding for the unbounded exponent result
   // convert
-  input  logic                 CvtOp,                  // conversion operation?
-  input  logic                 ToInt,                  // convert to integer
-  input  logic                 IntToFp,                // convert integer to floating point
-  input  logic                 Int64,                  // convert to 64 bit integer
-  input  logic                 Signed,                 // convert to a signed integer
-  input  logic [P.NE:0]        CvtCe,                  // the calculated expoent - Cvt
-  input  logic [1:0]           CvtNegResMsbs,          // the negative integer result's most significant bits
+  input  logic                CvtOp,                  // conversion opperation?
+  input  logic                ToInt,                  // convert to integer
+  input  logic                IntToFp,                // convert integer to floating point
+  input  logic                Int64,                  // convert to 64 bit integer
+  input  logic                Signed,                 // convert to a signed integer
+  input  logic [`NE:0]        CvtCe,                  // the calculated expoent - Cvt
+  input  logic [1:0]          CvtNegResMsbs,          // the negitive integer result's most significant bits
   // divsqrt
-  input  logic                 DivOp,                  // conversion operation?
-  input  logic                 Sqrt,                   // Sqrt?
+  input  logic                DivOp,                  // conversion opperation?
+  input  logic                Sqrt,                   // Sqrt?
   // fma
-  input  logic                 FmaOp,                  // Fma operation?
-  input  logic                 FmaAs, FmaPs,           // the product and modified Z signs
+  input  logic                FmaOp,                  // Fma opperation?
+  input  logic                FmaAs, FmaPs,           // the product and modified Z signs
   // flags
-  output logic                 DivByZero,              // divide by zero flag
-  output logic                 Overflow,               // overflow flag to select result
-  output logic                 Invalid,                // invalid flag to select the result
-  output logic                 IntInvalid,             // invalid integer result to select
-  output logic [4:0]           PostProcFlg             // flags
+  output logic                DivByZero,              // divide by zero flag
+  output logic                Overflow,               // overflow flag to select result
+  output logic                Invalid,                // invalid flag to select the result
+  output logic                IntInvalid,             // invalid integer result to select
+  output logic [4:0]          PostProcFlg             // flags
 );
 
-  logic                        SigNaN;                 // is an input a signaling NaN
-  logic                        Inexact;                // final inexact flag
-  logic                        FpInexact;              // floating point inexact flag
-  logic                        IntInexact;             // integer inexact flag
-  logic                        FmaInvalid;             // integer invalid flag
-  logic                        DivInvalid;             // integer invalid flag
-  logic                        Underflow;              // Underflow flag
-  logic                        ResExpGteMax;           // is the result greater than or equal to the maximum floating point expoent
-  logic                        ShiftGtIntSz;           // is the shift greater than the the integer size (use Re to account for possible rounding "shift")
+  logic               SigNaN;         // is an input a signaling NaN
+  logic               Inexact;        // final inexact flag
+  logic               FpInexact;      // floating point inexact flag
+  logic               IntInexact;     // integer inexact flag
+  logic               FmaInvalid;     // integer invalid flag
+  logic               DivInvalid;     // integer invalid flag
+  logic               Underflow;      // Underflow flag
+  logic               ResExpGteMax;   // is the result greater than or equal to the maximum floating point expoent
+  logic               ShiftGtIntSz;   // is the shift greater than the the integer size (use Re to account for possible roundning "shift")
 
   ///////////////////////////////////////////////////////////////////////////////
   // Overflow
@@ -87,60 +87,62 @@ module flags import cvw::*;  #(parameter cvw_t P) (
   //      65 = ...0 0 0 0   0 1 0 0   0 0 0 1
   //          |     or      | |     or      |
   //      33 = ...0 0 0 0   0 0 1 0   0 0 0 1
-  //          |     or      | |     or      |
+  //          |     or        | |     or    |
   //      larger or equal if:
   //          - any of the bits after the most significan 1 is one
   //          - the most signifcant in 65 or 33 is still a one in the number and
   //            one of the later bits is one
-  if (P.FPSIZES == 1) begin
-      assign ResExpGteMax = &FullRe[P.NE-1:0] | FullRe[P.NE];
-      assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+  if (`FPSIZES == 1) begin
+      assign ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE];
+      assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
 
-  end else if (P.FPSIZES == 2) begin    
-      assign ResExpGteMax = OutFmt ? &FullRe[P.NE-1:0] | FullRe[P.NE] : &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
+  end else if (`FPSIZES == 2) begin    
+      assign ResExpGteMax = OutFmt ? &FullRe[`NE-1:0] | FullRe[`NE] : &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]);
 
-      assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
-  end else if (P.FPSIZES == 3) begin
+      assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+  end else if (`FPSIZES == 3) begin
       always_comb
           case (OutFmt)
-              P.FMT: ResExpGteMax   = &FullRe[P.NE-1:0]  | FullRe[P.NE];
-              P.FMT1: ResExpGteMax  = &FullRe[P.NE1-1:0] | (|FullRe[P.NE:P.NE1]);
-              P.FMT2: ResExpGteMax  = &FullRe[P.NE2-1:0] | (|FullRe[P.NE:P.NE2]);
+              `FMT: ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE];
+              `FMT1: ResExpGteMax = &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]);
+              `FMT2: ResExpGteMax = &FullRe[`NE2-1:0] | (|FullRe[`NE:`NE2]);
               default: ResExpGteMax = 1'bx;
           endcase
-          assign ShiftGtIntSz = (|FullRe[P.NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+          assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
 
-  end else if (P.FPSIZES == 4) begin        
+  end else if (`FPSIZES == 4) begin        
       always_comb
           case (OutFmt)
-              P.Q_FMT: ResExpGteMax = &FullRe[P.Q_NE-1:0] | FullRe[P.Q_NE];
-              P.D_FMT: ResExpGteMax = &FullRe[P.D_NE-1:0] | (|FullRe[P.Q_NE:P.D_NE]);
-              P.S_FMT: ResExpGteMax = &FullRe[P.S_NE-1:0] | (|FullRe[P.Q_NE:P.S_NE]);
-              P.H_FMT: ResExpGteMax = &FullRe[P.H_NE-1:0] | (|FullRe[P.Q_NE:P.H_NE]);
+              `Q_FMT: ResExpGteMax = &FullRe[`Q_NE-1:0] | FullRe[`Q_NE];
+              `D_FMT: ResExpGteMax = &FullRe[`D_NE-1:0] | (|FullRe[`Q_NE:`D_NE]);
+              `S_FMT: ResExpGteMax = &FullRe[`S_NE-1:0] | (|FullRe[`Q_NE:`S_NE]);
+              `H_FMT: ResExpGteMax = &FullRe[`H_NE-1:0] | (|FullRe[`Q_NE:`H_NE]);
           endcase
-          assign ShiftGtIntSz = (|FullRe[P.Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
+          assign ShiftGtIntSz = (|FullRe[`Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
   end
-  
+
+
   // calulate overflow flag:
   //                 if the result is greater than or equal to the max exponent(not taking into account sign)
-  //                 |           and the exponent isn't negative
+  //                 |           and the exponent isn't negitive
   //                 |           |                   if the input isnt infinity or NaN
   //                 |           |                   |            
-  assign Overflow = ResExpGteMax & ~FullRe[P.NE+1]&~(InfIn|NaNIn|DivByZero);
+  assign Overflow = ResExpGteMax & ~FullRe[`NE+1]&~(InfIn|NaNIn|DivByZero);
 
   ///////////////////////////////////////////////////////////////////////////////
   // Underflow
   ///////////////////////////////////////////////////////////////////////////////
 
   // calculate underflow flag: detecting tininess after rounding
-  //                  the exponent is negative
+  //                  the exponent is negitive
   //                  |                    the result is subnormal
   //                  |                    |                    the result is normal and rounded from a Subnorm
   //                  |                    |                    |                                      and if given an unbounded exponent the result does not round
   //                  |                    |                    |                                      |                     and if the result is not exact
   //                  |                    |                    |                                      |                     |               and if the input isnt infinity or NaN
   //                  |                    |                    |                                      |                     |               |
-  assign Underflow = ((FullRe[P.NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
+  assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
+
 
   ///////////////////////////////////////////////////////////////////////////////
   // Inexact
@@ -149,11 +151,12 @@ module flags import cvw::*;  #(parameter cvw_t P) (
   // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
   //      - Don't set the underflow flag if an underflowed res isn't outputed
   assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid);
-  
+  //assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
+
   //                  if the res is too small to be represented and not 0
   //                  |                                     and if the res is not invalid (outside the integer bounds)
   //                  |                                     |
-  assign IntInexact = ((CvtCe[P.NE]&~XZero)|Sticky|Round|Guard)&~IntInvalid;
+  assign IntInexact = ((CvtCe[`NE]&~XZero)|Sticky|Round|Guard)&~IntInvalid;
 
   // select the inexact flag to output
   assign Inexact = ToInt ? IntInexact : FpInexact;
@@ -170,12 +173,12 @@ module flags import cvw::*;  #(parameter cvw_t P) (
   // invalid flag for integer result
   //                  if the input is NaN or infinity
   //                  |           if the integer res overflows (out of range) 
-  //                  |           |                                  if the input was negative but ouputing to a unsigned number
+  //                  |           |                                  if the input was negitive but ouputing to a unsigned number
   //                  |           |                                  |                    the res doesn't round to zero
   //                  |           |                                  |                    |               or the res rounds up out of bounds
   //                  |           |                                  |                    |                       and the res didn't underflow
   //                  |           |                                  |                    |                       |
-  assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[P.NE+1])|((Xs&~Signed)&(~((CvtCe[P.NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
+  assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
   //                                                                                                     |
   //                                                                                                     or when the positive res rounds up out of range
   
@@ -197,6 +200,7 @@ module flags import cvw::*;  #(parameter cvw_t P) (
   //  - don't set flag if an input is NaN or Inf(IEEE says has to be a finite numerator)
   assign DivByZero = YZero&DivOp&~Sqrt&~(XZero|NaNIn|InfIn);  
 
+
   ///////////////////////////////////////////////////////////////////////////////
   // final flags
   ///////////////////////////////////////////////////////////////////////////////
@@ -206,3 +210,7 @@ module flags import cvw::*;  #(parameter cvw_t P) (
   assign PostProcFlg = {Invalid|(IntInvalid&CvtOp&ToInt), DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact};
 
 endmodule
+
+
+
+
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv
new file mode 100644
index 000000000..dabf0dfde
--- /dev/null
+++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv
@@ -0,0 +1,137 @@
+///////////////////////////////////////////
+// fmashiftcalc.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: FMA shift calculation
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fmashiftcalc(
+  input  logic [`FMTBITS-1:0]         Fmt,            // precision 1 = double 0 = single
+  input  logic [`NE+1:0]              FmaSe,          // sum's exponent
+  input  logic [3*`NF+3:0]            FmaSm,          // the positive sum
+  input  logic [$clog2(3*`NF+5)-1:0]  FmaSCnt,        // normalization shift count
+  output logic [`NE+1:0]              NormSumExp,     // exponent of the normalized sum not taking into account Subnormal or zero results
+  output logic                        FmaSZero,       // is the result subnormal - calculated before LZA corection
+  output logic                        FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
+  output logic [$clog2(3*`NF+5)-1:0]  FmaShiftAmt,    // normalization shift count
+  output logic [3*`NF+5:0]            FmaShiftIn      // is the sum zero
+);
+  logic [`NE+1:0] PreNormSumExp;  // the exponent of the normalized sum with the `FLEN bias
+  logic [`NE+1:0] BiasCorr;       // correction for bias
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Normalization
+  ///////////////////////////////////////////////////////////////////////////////
+
+  // Determine if the sum is zero
+  assign FmaSZero = ~(|FmaSm);
+
+  // calculate the sum's exponent
+  assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+5)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);
+
+  //convert the sum's exponent into the proper percision
+  if (`FPSIZES == 1) begin
+    assign NormSumExp = PreNormSumExp;
+  end else if (`FPSIZES == 2) begin
+    assign BiasCorr = Fmt ? (`NE+2)'(0) : (`NE+2)'(`BIAS1-`BIAS);
+    assign NormSumExp = PreNormSumExp+BiasCorr;
+  end else if (`FPSIZES == 3) begin
+    always_comb begin
+        case (Fmt)
+            `FMT: BiasCorr =  '0;
+            `FMT1: BiasCorr = (`NE+2)'(`BIAS1-`BIAS);
+            `FMT2: BiasCorr = (`NE+2)'(`BIAS2-`BIAS);
+            default: BiasCorr = 'x;
+        endcase
+    end
+    assign NormSumExp = PreNormSumExp+BiasCorr;
+  end else if (`FPSIZES == 4) begin
+    always_comb begin
+        case (Fmt)
+            2'h3: BiasCorr = '0;
+            2'h1: BiasCorr = (`NE+2)'(`D_BIAS-`Q_BIAS);
+            2'h0: BiasCorr = (`NE+2)'(`S_BIAS-`Q_BIAS);
+            2'h2: BiasCorr = (`NE+2)'(`H_BIAS-`Q_BIAS);
+        endcase
+    end
+    assign NormSumExp = PreNormSumExp+BiasCorr;
+  end
+  
+  // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero
+  if (`FPSIZES == 1) begin
+    logic Sum0LEZ, Sum0GEFL;
+    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
+    assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
+  end else if (`FPSIZES == 2) begin
+    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
+    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp;
+    assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
+  end else if (`FPSIZES == 3) begin
+    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
+    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp;
+    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS2));
+    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF2-2+`BIAS-`BIAS2)) | ~|PreNormSumExp;
+    always_comb begin
+      case (Fmt)
+        `FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
+        `FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero;
+        `FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero;
+        default: FmaPreResultSubnorm = 1'bx;
+      endcase
+    end
+  end else if (`FPSIZES == 4) begin
+    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
+    assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
+    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
+    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`D_BIAS));
+    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`D_NF-2+`BIAS-`D_BIAS)) | ~|PreNormSumExp;
+    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`S_BIAS));
+    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`S_NF-2+`BIAS-`S_BIAS)) | ~|PreNormSumExp;
+    assign Sum3LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`H_BIAS));
+    assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`H_NF-2+`BIAS-`H_BIAS)) | ~|PreNormSumExp;
+    always_comb begin
+      case (Fmt)
+        2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
+        2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero;
+        2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero;
+        2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL & ~FmaSZero;
+      endcase
+    end
+  end
+
+  // set and calculate the shift input and amount
+  //  - shift once if killing a product and the result is subnormal
+  assign FmaShiftIn = {2'b0, FmaSm};
+  if (`FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;
+  else               assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2)+BiasCorr[$clog2(3*`NF+5)-1:0]: FmaSCnt+1;
+endmodule
diff --git a/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv
similarity index 51%
rename from src/fpu/postproc/negateintres.sv
rename to pipelined/src/fpu/postproc/negateintres.sv
index b9cb038a4..939bcc335 100644
--- a/src/fpu/postproc/negateintres.sv
+++ b/pipelined/src/fpu/postproc/negateintres.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Negate integer result
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,25 +25,26 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
 
-module negateintres import cvw::*;  #(parameter cvw_t P) (
-  input  logic                     Signed,         // is the integer input signed
-  input  logic                     Int64,          // is the integer input 64-bits
-  input  logic                     Plus1,          // should one be added for rounding?
-  input  logic                     Xs,             // X sign
-  input  logic [P.NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
-  output logic [1:0]               CvtNegResMsbs,  // most signigficant bits of possibly negated result
-  output logic [P.XLEN+1:0]        CvtNegRes       // possibly negated integer result
+module negateintres(
+  input  logic                    Signed,         // is the integer input signed
+  input  logic                    Int64,          // is the integer input 64-bits
+  input  logic                    Plus1,          // should one be added for rounding?
+  input  logic                    Xs,             // X sign
+  input  logic [`NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
+  output logic [1:0]              CvtNegResMsbs,  // most signigficant bits of possibly negated result
+  output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
 );
 
-  logic [P.XLEN+1:0]               CvtPreRes;      // integer result with rounding
-  logic [2:0]                      CvtNegResMsbs3; // first three msbs of possibly negated result
+  logic [`XLEN+1:0]               CvtPreRes;      // integer result with rounding
+  logic [2:0]                     CvtNegResMsbs3; // first three msbs of possibly negated result
     
   // round and negate the positive res if needed
-  assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
-  mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
+  assign CvtPreRes =  {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
     
   // select 2 most significant bits
-  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[P.XLEN+1:P.XLEN-1], Int64, CvtNegResMsbs3);
+  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
   mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv
similarity index 69%
rename from src/fpu/postproc/normshift.sv
rename to pipelined/src/fpu/postproc/normshift.sv
index d0a14cbfd..44469e316 100644
--- a/src/fpu/postproc/normshift.sv
+++ b/pipelined/src/fpu/postproc/normshift.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: normalization shifter
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,56 +25,58 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
+
 
     // convert shift
-    //      fp -> int:  | `XLEN  zeros      |     Mantissa      | 0's if necessary | << CalcExp
+    //      fp -> int: |  `XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
     //          process:
     //              - start - CalcExp = 1 + XExp - Largest Bias
-    //                  | `XLEN  zeros      |     Mantissa      | 0's if necessary |
+    //                  |  `XLEN  zeros     |     Mantissa      | 0's if nessisary |
     //
     //              - shift left 1 (1)
-    //                  | `XLEN-1 zeros |bit|     frac          | 0's if necessary |
+    //                  | `XLEN-1 zeros |bit|     frac      | 0's if nessisary |
     //                                      . <- binary point
     //
     //              - shift left till unbiased exponent is 0 (XExp - Largest Bias)
-    //                  |  0's |     Mantissa      |      0's if necessary     |
+    //                  |  0's |     Mantissa      |      0's if nessisary     |
     //                  |     keep          |
     //
     //      fp -> fp:
     //          - if result is subnormal or underflowed:
-    //              |  `NF-1  zeros   |     Mantissa      | 0's if necessary | << NF+CalcExp-1
+    //              |  `NF-1  zeros   |     Mantissa      | 0's if nessisary | << NF+CalcExp-1
     //          process:
     //             - start
     //                 |     mantissa      | 0's |
     //
     //             - shift right by NF-1 (NF-1)
-    //                 |    `NF-1  zeros   |     mantissa      | 0's |
+    //                 |  `NF-1  zeros   |     mantissa      | 0's |
     //
     //             - shift left by CalcExp = XExp - Largest bias + new bias
     //                 |   0's  |     mantissa      |     0's      |
     //                 |       keep      |
     //
     //          - if the input is subnormal:
-    //                 |     lzcIn      | 0's if necessary | << ZeroCnt+1
+    //              |     lzcIn      | 0's if nessisary | << ZeroCnt+1
     //              - plus 1 to shift out the first 1
     //
-    //      int -> fp: |     lzcIn      | 0's if necessary | << ZeroCnt+1
+    //      int -> fp: |     lzcIn      | 0's if nessisary | << ZeroCnt+1
     //              - plus 1 to shift out the first 1
 
     // fma shift
-    //      |   00   |           Sm           | << LZA output
+    //      | 00 |           Sm           | << LZA output
     //             .
     //      - two extra bits so we can correct for an LZA error of 1 or 2
 
     // divsqrt shift
-    //      | Nf 0's |           Qm           | << calculated shift amount
+    //      | Nf 0's |      Qm       | << calculated shift amount
     //        .
 
-module normshift import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.LOGNORMSHIFTSZ-1:0]  ShiftAmt,   // shift amount
-  input  logic [P.NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
-  output logic [P.NORMSHIFTSZ-1:0]     Shifted     // shifted result
+module normshift(
+  input  logic [`LOGNORMSHIFTSZ-1:0]  ShiftAmt,   // shift amount
+  input  logic [`NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
+  output logic [`NORMSHIFTSZ-1:0]     Shifted     // shifted result
 );
    
   assign Shifted = ShiftIn << ShiftAmt;
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv
new file mode 100644
index 000000000..07723d7f1
--- /dev/null
+++ b/pipelined/src/fpu/postproc/postprocess.sv
@@ -0,0 +1,226 @@
+///////////////////////////////////////////
+// postprocess.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module postprocess (
+  // general signals
+  input logic                             Xs, Ys,     // input signs
+  input logic  [`NF:0]                    Xm, Ym, Zm, // input mantissas
+  input logic  [2:0]                      Frm,        // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
+  input logic  [`FMTBITS-1:0]             Fmt,        // precision 1 = double 0 = single
+  input logic  [2:0]                      OpCtrl,     // choose which opperation (look below for values)
+  input logic                             XZero, YZero,        // inputs are zero
+  input logic                             XInf, YInf, ZInf,    // inputs are infinity
+  input logic                             XNaN, YNaN, ZNaN,    // inputs are NaN
+  input logic                             XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
+  input logic  [1:0]                      PostProcSel,         // select result to be written to fp register
+  //fma signals
+  input logic                             FmaAs,      // the modified Z sign - depends on instruction
+  input logic                             FmaPs,      // the product's sign
+  input logic                             FmaSs,      // Sum sign
+  input logic  [`NE+1:0]                  FmaSe,      // the sum's exponent
+  input logic  [3*`NF+3:0]                FmaSm,      // the positive sum
+  input logic                             FmaASticky, // sticky bit that is calculated during alignment
+  input logic  [$clog2(3*`NF+5)-1:0]      FmaSCnt,    // the normalization shift count
+  //divide signals
+  input logic                             DivSticky,  // divider sticky bit
+  input logic  [`NE+1:0]                  DivQe,      // divsqrt exponent
+  input logic  [`DIVb:0]                  DivQm,      // divsqrt significand
+  // conversion signals
+  input logic                             CvtCs,      // the result's sign
+  input logic  [`NE:0]                    CvtCe,      // the calculated expoent
+  input logic                             CvtResSubnormUf, // the convert result is subnormal or underflows
+  input logic  [`LOGCVTLEN-1:0]           CvtShiftAmt,// how much to shift by
+  input logic                             ToInt,      // is fp->int (since it's writting to the integer register)
+  input logic  [`CVTLEN-1:0]              CvtLzcIn,   // input to the Leading Zero Counter (without msb)
+  input logic                             IntZero,    // is the integer input zero
+  // final results
+  output logic [`FLEN-1:0]                PostProcRes,// postprocessor final result
+  output logic [4:0]                      PostProcFlg,// postprocesser flags
+  output logic [`XLEN-1:0]                FCvtIntRes  // the integer conversion result
+  );
+  
+  // general signals
+  logic                       Rs;         // result sign
+  logic [`NF-1:0]             Rf;         // Result fraction
+  logic [`NE-1:0]             Re;         // Result exponent
+  logic                       Ms;         // norMalized sign
+  logic [`CORRSHIFTSZ-1:0]    Mf;         // norMalized fraction
+  logic [`NE+1:0]             Me;         // normalized exponent
+  logic [`NE+1:0]             FullRe;     // Re with bits to determine sign and overflow
+  logic                       UfPlus1;    // do you add one (for determining underflow flag)
+  logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift amount
+  logic [`NORMSHIFTSZ-1:0]    ShiftIn;    // input to normalization shift
+  logic [`NORMSHIFTSZ-1:0]    Shifted;    // the ouput of the normalized shifter (before shift correction)
+  logic                       Plus1;      // add one to the final result?
+  logic                       Overflow;   // overflow flag used to select results
+  logic                       Invalid;    // invalid flag used to select results
+  logic                       Guard, Round, Sticky; // bits needed to determine rounding
+  logic [`FMTBITS-1:0]        OutFmt;     // output format
+  // fma signals
+  logic [`NE+1:0]             FmaMe;      // exponent of the normalized sum
+  logic                       FmaSZero;   // is the sum zero
+  logic [3*`NF+5:0]           FmaShiftIn; // fma shift input
+  logic [`NE+1:0]             NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
+  logic                       FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
+  logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
+  // division singals
+  logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;        // divsqrt shif amount
+  logic [`NORMSHIFTSZ-1:0]    DivShiftIn;         // divsqrt shift input
+  logic [`NE+1:0]             Qe;                 // divsqrt corrected exponent after corretion shift
+  logic                       DivByZero;          // divide by zero flag
+  logic                       DivResSubnorm;      // is the divsqrt result subnormal
+  logic                       DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
+  // conversion signals
+  logic [`CVTLEN+`NF:0]       CvtShiftIn;         // number to be shifted for converter
+  logic [1:0]                 CvtNegResMsbs;      // most significant bits of possibly negated int result
+  logic [`XLEN+1:0]           CvtNegRes;          // possibly negated integer result
+  logic                       CvtResUf;           // did the convert result underflow
+  logic                       IntInvalid;         // invalid integer flag
+  // readability signals
+  logic                       Mult;       // multiply opperation
+  logic                       Sqrt;       // is the divsqrt opperation sqrt
+  logic                       Int64;      // is the integer 64 bits?
+  logic                       Signed;     // is the opperation with a signed integer?
+  logic                       IntToFp;    // is the opperation an int->fp conversion?
+  logic                       CvtOp;      // convertion opperation
+  logic                       FmaOp;      // fma opperation
+  logic                       DivOp;      // divider opperation
+  logic                       InfIn;      // are any of the inputs infinity
+  logic                       NaNIn;      // are any of the inputs NaN
+
+  // signals to help readability
+  assign Signed =  OpCtrl[0];
+  assign Int64 =   OpCtrl[1];
+  assign IntToFp = OpCtrl[2];
+  assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
+  assign CvtOp = (PostProcSel == 2'b00);
+  assign FmaOp = (PostProcSel == 2'b10);
+  assign DivOp = (PostProcSel == 2'b01);
+  assign Sqrt =  OpCtrl[0];
+
+  // is there an input of infinity or NaN being used
+  assign InfIn = XInf|YInf|ZInf;
+  assign NaNIn = XNaN|YNaN|ZNaN;
+
+  // choose the ouptut format depending on the opperation
+  //      - fp -> fp: OpCtrl contains the percision of the output
+  //      - otherwise: Fmt contains the percision of the output
+  if (`FPSIZES == 2) 
+      assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == `FMT); 
+  else if (`FPSIZES == 3 | `FPSIZES == 4) 
+      assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; 
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Normalization
+  ///////////////////////////////////////////////////////////////////////////////
+
+  // final claulations before shifting
+  cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
+      .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
+
+  fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
+      .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
+
+  divshiftcalc divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
+
+  // select which unit's output to shift
+  always_comb
+    case(PostProcSel)
+      2'b10: begin // fma
+        ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(3*`NF+5){1'b0}}, FmaShiftAmt};
+        ShiftIn =  {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+6){1'b0}}};
+      end
+      2'b00: begin // cvt
+        ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
+        ShiftIn =  {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}};
+      end
+      2'b01: begin //divsqrt
+        ShiftAmt = DivShiftAmt;
+        ShiftIn =  DivShiftIn;
+      end
+      default: begin 
+        ShiftAmt = {`LOGNORMSHIFTSZ{1'bx}}; 
+        ShiftIn = {`NORMSHIFTSZ{1'bx}}; 
+      end
+    endcase
+  
+  // main normalization shift
+  normshift normshift (.ShiftIn, .ShiftAmt, .Shifted);
+
+  // correct for LZA/divsqrt error
+  shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
+      .DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivQe, .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Rounding
+  ///////////////////////////////////////////////////////////////////////////////
+
+  // round to nearest even
+  // round to zero
+  // round to -infinity
+  // round to infinity
+  // round to nearest max magnitude
+
+  // calulate result sign used in rounding unit
+  roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
+
+  round round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
+      .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt,  .CvtResUf,
+      .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Sign calculation
+  ///////////////////////////////////////////////////////////////////////////////
+
+  resultsign resultsign(.Frm, .FmaPs, .FmaAs, .Round, .Sticky, .Guard,
+      .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Rs);
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Flags
+  ///////////////////////////////////////////////////////////////////////////////
+
+  flags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero, 
+              .Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
+              .NaNIn, .FmaAs, .FmaPs, .Round, .IntInvalid, .DivByZero,
+              .Guard, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
+              .Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg);
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Select the result
+  ///////////////////////////////////////////////////////////////////////////////
+
+  negateintres negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
+
+  specialcase specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid,
+      .IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf, 
+      .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes,
+      .XInf, .YInf, .DivOp, .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
+
+endmodule
diff --git a/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv
similarity index 84%
rename from src/fpu/postproc/resultsign.sv
rename to pipelined/src/fpu/postproc/resultsign.sv
index 9425ec7ee..7eeba9e8a 100644
--- a/src/fpu/postproc/resultsign.sv
+++ b/pipelined/src/fpu/postproc/resultsign.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: calculating the result's sign
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,10 +26,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module resultsign(
   input  logic [2:0]  Frm,        // rounding mode
   input  logic        FmaOp,      // is the operation an Fma
-  input  logic        Mult,       // is the fma operation multipy
+  input  logic        Mult,       // is the fma opperation multipy
   input  logic        ZInf,       // is Z infinity
   input  logic        InfIn,      // are any of the inputs infinity
   input  logic        FmaSZero,   // is the fma sum zero
@@ -48,8 +49,8 @@ module resultsign(
 
   // determine the sign for a result of 0
   //  The IEEE754-2019 standard specifies: 
-  //      - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negative infinity
-  //      - when the exact result of an FMA operation is non-zero, but is zero due to rounding, use the sign of the exact result
+  //      - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity
+  //      - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result
   //      - if x = +0 or -0 then x+x=x and x-(-x)=x 
   //      - the sign of a product is the exclisive or or the opperand's signs
   //  Zero sign will only be selected if:
@@ -58,16 +59,16 @@ module resultsign(
   //      - P is killed and Z is zero - Psgn
   //      - Z is killed and P is zero - impossible
   //  Zero sign calculation:
-  //      - if a multiply operation is done, then use the products sign(Ps)
+  //      - if a multiply opperation is done, then use the products sign(Ps)
   //      - if the zero sum is not exactly zero i.e. Round|Sticky use the sign of the exact result (which is the product's sign)
   //      - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign
   assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
 
   // determine the sign of an infinity result
-  //  is the result negative
-  //      if p - z is the Sum negative
+  //  is the result negitive
+  //      if p - z is the Sum negitive
   //      if -p + z is the Sum positive
-  //      if -p - z then the Sum is negative
+  //      if -p - z then the Sum is negitive
   assign Infs = ZInf ? FmaAs : FmaPs;
 
   // select the result sign
@@ -76,4 +77,4 @@ module resultsign(
     else if(FmaSZero&FmaOp) Rs = Zeros;
     else                    Rs = Ms;
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv
new file mode 100644
index 000000000..ee5a44751
--- /dev/null
+++ b/pipelined/src/fpu/postproc/round.sv
@@ -0,0 +1,331 @@
+///////////////////////////////////////////
+// round.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: Rounder
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+// what position is XLEN in?
+//  options: 
+//     1: XLEN > NF   > NF1
+//     2: NF   > XLEN > NF1
+//     3: NF   > NF1  > XLEN
+//  single and double will always be smaller than XLEN
+`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
+
+module round(
+  input  logic [`FMTBITS-1:0]     OutFmt,             // output format
+  input  logic [2:0]              Frm,                // rounding mode
+  input  logic [1:0]              PostProcSel,        // select the postprocessor output
+  input  logic                    Ms,                 // normalized sign
+  input  logic [`CORRSHIFTSZ-1:0] Mf,                 // normalized fraction
+  // fma
+  input  logic                    FmaOp,              // is an fma opperation being done?
+  input  logic [`NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
+  input  logic                    FmaASticky,         // addend's sticky bit
+  // divsqrt
+  input  logic                    DivOp,              // is a division opperation being done
+  input  logic                    DivSticky,          // divsqrt sticky bit
+  input  logic [`NE+1:0]          Qe,                 // the divsqrt calculated expoent
+  // cvt
+  input  logic                    CvtOp,              // is a convert opperation being done
+  input  logic                    ToInt,              // is the cvt op a cvt to integer
+  input  logic                    CvtResSubnormUf,    // is the cvt result subnormal or underflow
+  input  logic                    CvtResUf,           // does the cvt result underflow
+  input  logic [`NE:0]            CvtCe,              // the cvt calculated expoent
+  // outputs
+  output logic [`NE+1:0]          Me,                 // normalied fraction
+  output logic                    UfPlus1,            // do you add one to the result if given an unbounded exponent
+  output logic [`NE+1:0]          FullRe,             // Re with bits to determine sign and overflow
+  output logic [`NE-1:0]          Re,                 // Result exponent
+  output logic [`NF-1:0]          Rf,                 // Result fractionNormS
+  output logic                    Sticky,             // sticky bit
+  output logic                    Plus1,              // do you add one to the final result
+  output logic                    Round, Guard        // bits needed to calculate rounding
+);
+
+  logic           UfCalcPlus1;        // calculated plus one for unbounded exponent
+  logic           NormSticky;         // normalized sum's sticky bit
+  logic [`NF-1:0] RoundFrac;          // rounded fraction
+  logic           FpRes;              // is the result a floating point
+  logic           IntRes;             // is the result an integer
+  logic           FpGuard, FpRound;   // floating point round/guard bits
+  logic           FpLsbRes;           // least significant bit of floating point result
+  logic           LsbRes;             // lsb of result
+  logic           CalcPlus1;          // calculated plus1
+  logic           FpPlus1;            // do you add one to the fp result 
+  logic [`FLEN:0] RoundAdd;           // how much to add to the result
+
+  ///////////////////////////////////////////////////////////////////////////////
+  // Rounding
+  ///////////////////////////////////////////////////////////////////////////////
+
+  // round to nearest even
+  //      {Round, Sticky}
+  //      0x - do nothing
+  //      10 - tie - Plus1 if result is odd  (LSBNormSum = 1)
+  //          - don't add 1 if a small number was supposed to be subtracted
+  //      11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
+  //         - plus 1 otherwise
+
+  //  round to zero - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0
+
+  //  round to -infinity
+  //          - Plus1 if negative unless a small number was supposed to be subtracted from a result with guard and round bits of 0
+  //          - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0
+
+  //  round to infinity
+  //          - Plus1 if positive unless a small number was supposed to be subtracted from a result with guard and round bits of 0
+  //          - subtract 1 if a small number was supposed to be subtracted from a negative result with guard and round bits of 0
+
+  //  round to nearest max magnitude
+  //      {Guard, Round, Sticky}
+  //      0x - do nothing
+  //      10 - tie - Plus1
+  //          - don't add 1 if a small number was supposed to be subtracted
+  //      11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
+  //         - Plus 1 otherwise
+
+
+  // determine what format the final result is in: int or fp
+  assign IntRes = CvtOp & ToInt;
+  assign FpRes = ~IntRes;
+
+  // sticky bit calculation
+  if (`FPSIZES == 1) begin
+
+      //     1: XLEN > NF
+      //      |         XLEN          |
+      //      |    NF     |1|1|
+      //                     ^    ^ if floating point result
+      //                     ^ if not an FMA result
+      if (`XLENPOS == 1)assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      //     2: NF > XLEN
+      if (`XLENPOS == 2)assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&IntRes) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+
+  end else if (`FPSIZES == 2) begin
+      // XLEN is either 64 or 32
+      // so half and single are always smaller then XLEN
+
+      // 1: XLEN > NF   > NF1
+      if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~OutFmt) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      // 2: NF   > XLEN > NF1
+      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~OutFmt) | 
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~OutFmt)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      // 3: NF   > NF1  > XLEN
+      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&IntRes) |
+                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~OutFmt|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+
+  end else if (`FPSIZES == 3) begin
+      // 1: XLEN > NF   > NF1
+      if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~(OutFmt==`FMT)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
+      // 2: NF   > XLEN > NF1
+      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`FMT)) | 
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~(OutFmt==`FMT))) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+      // 3: NF   > NF1  > XLEN
+      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&(OutFmt==`FMT1)) |
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&((OutFmt==`FMT1)|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~(OutFmt==`FMT)|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`NF-2:0]);
+
+  end else if (`FPSIZES == 4) begin
+      // Quad precision will always be greater than XLEN
+      // 2: NF   > XLEN > NF1
+      if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
+                                                (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`D_NF-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) | 
+                                                (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`Q_FMT)) | 
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]);
+      // 3: NF   > NF1  > XLEN
+      // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
+      if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
+                                                (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) |
+                                                (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`D_NF-1]&((OutFmt==`S_FMT)|(OutFmt==`H_FMT)|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
+                                                (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]);
+
+  end
+  
+
+
+  // only add the Addend sticky if doing an FMA opperation
+  //      - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
+  assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivSticky&DivOp;
+  
+
+
+
+  // determine round and LSB of the rounded value
+  //      - underflow round bit is used to determint the underflow flag
+  if (`FPSIZES == 1) begin
+      assign FpGuard = Mf[`CORRSHIFTSZ-`NF-1];
+      assign FpLsbRes = Mf[`CORRSHIFTSZ-`NF];
+      assign FpRound = Mf[`CORRSHIFTSZ-`NF-2];
+
+  end else if (`FPSIZES == 2) begin
+      assign FpGuard = OutFmt ? Mf[`CORRSHIFTSZ-`NF-1] : Mf[`CORRSHIFTSZ-`NF1-1];
+      assign FpLsbRes = OutFmt ? Mf[`CORRSHIFTSZ-`NF] : Mf[`CORRSHIFTSZ-`NF1];
+      assign FpRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-2] : Mf[`CORRSHIFTSZ-`NF1-2];
+
+  end else if (`FPSIZES == 3) begin
+      always_comb
+          case (OutFmt)
+              `FMT: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`NF-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF];
+                  FpRound = Mf[`CORRSHIFTSZ-`NF-2];
+              end
+              `FMT1: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`NF1-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF1];
+                  FpRound = Mf[`CORRSHIFTSZ-`NF1-2];
+              end
+              `FMT2: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`NF2-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`NF2];
+                  FpRound = Mf[`CORRSHIFTSZ-`NF2-2];
+              end
+              default: begin
+                  FpGuard = 1'bx;
+                  FpLsbRes = 1'bx;
+                  FpRound = 1'bx;
+              end
+          endcase
+  end else if (`FPSIZES == 4) begin
+      always_comb
+          case (OutFmt)
+              2'h3: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`Q_NF-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`Q_NF];
+                  FpRound = Mf[`CORRSHIFTSZ-`Q_NF-2];
+              end
+              2'h1: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`D_NF-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`D_NF];
+                  FpRound = Mf[`CORRSHIFTSZ-`D_NF-2];
+              end
+              2'h0: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`S_NF-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`S_NF];
+                  FpRound = Mf[`CORRSHIFTSZ-`S_NF-2];
+              end
+              2'h2: begin
+                  FpGuard = Mf[`CORRSHIFTSZ-`H_NF-1];
+                  FpLsbRes = Mf[`CORRSHIFTSZ-`H_NF];
+                  FpRound = Mf[`CORRSHIFTSZ-`H_NF-2];
+              end
+          endcase
+  end
+
+  assign Guard = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-1] : FpGuard;
+  assign LsbRes = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN] : FpLsbRes;
+  assign Round = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-2] : FpRound;
+
+
+  always_comb begin
+      // Determine if you add 1
+      case (Frm)
+          3'b000: CalcPlus1 = Guard & (Round|Sticky|LsbRes);//round to nearest even
+          3'b001: CalcPlus1 = 0;//round to zero
+          3'b010: CalcPlus1 = Ms;//round down
+          3'b011: CalcPlus1 = ~Ms;//round up
+          3'b100: CalcPlus1 = Guard;//round to nearest max magnitude
+          default: CalcPlus1 = 1'bx;
+      endcase
+      // Determine if you add 1 (for underflow flag)
+      case (Frm)
+          3'b000: UfCalcPlus1 = Round & (Sticky|Guard);//round to nearest even
+          3'b001: UfCalcPlus1 = 0;//round to zero
+          3'b010: UfCalcPlus1 = Ms;//round down
+          3'b011: UfCalcPlus1 = ~Ms;//round up
+          3'b100: UfCalcPlus1 = Round;//round to nearest max magnitude
+          default: UfCalcPlus1 = 1'bx;
+      endcase
+  
+  end
+
+  // If an answer is exact don't round
+  assign Plus1 = CalcPlus1 & (Sticky|Round|Guard);
+  assign FpPlus1 = Plus1&~(ToInt&CvtOp);
+  assign UfPlus1 = UfCalcPlus1 & (Sticky|Round);
+
+
+
+
+  // place Plus1 into the proper position for the format
+  if (`FPSIZES == 1) begin
+      assign RoundAdd = {{`FLEN{1'b0}}, FpPlus1};
+
+  end else if (`FPSIZES == 2) begin
+      // \/FLEN+1
+      //  | NE+2 |        NF      |
+      //  '-NE+2-^----NF1----^
+      // `FLEN+1-`NE-2-`NF1 = FLEN-1-NE-NF1
+      assign RoundAdd = {(`NE+1+`NF1)'(0), FpPlus1&~OutFmt, (`NF-`NF1-1)'(0), FpPlus1&OutFmt};
+
+  end else if (`FPSIZES == 3) begin
+      assign RoundAdd = {(`NE+1+`NF2)'(0), FpPlus1&(OutFmt==`FMT2), (`NF1-`NF2-1)'(0), FpPlus1&(OutFmt==`FMT1), (`NF-`NF1-1)'(0), FpPlus1&(OutFmt==`FMT)};
+
+  end else if (`FPSIZES == 4)      
+      assign RoundAdd = {(`Q_NE+1+`H_NF)'(0), FpPlus1&(OutFmt==`H_FMT), (`S_NF-`H_NF-1)'(0), FpPlus1&(OutFmt==`S_FMT), (`D_NF-`S_NF-1)'(0), FpPlus1&(OutFmt==`D_FMT), (`Q_NF-`D_NF-1)'(0), FpPlus1&(OutFmt==`Q_FMT)};
+
+
+
+  // trim unneeded bits from fraction
+  assign RoundFrac = Mf[`CORRSHIFTSZ-1:`CORRSHIFTSZ-`NF];
+  
+
+
+  // select the exponent
+  always_comb
+      case(PostProcSel)
+          2'b10: Me = FmaMe; // fma
+          2'b00: Me = {CvtCe[`NE], CvtCe}&{`NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
+          // 2'b01: Me = DivDone ? Qe : '0; // divide
+          2'b01: Me = Qe; // divide
+          default: Me = '0; 
+      endcase
+
+
+
+  // round the result
+  //      - if the fraction overflows one should be added to the exponent
+  assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd;
+  assign Re = FullRe[`NE-1:0];
+
+
+endmodule
\ No newline at end of file
diff --git a/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv
similarity index 86%
rename from src/fpu/postproc/roundsign.sv
rename to pipelined/src/fpu/postproc/roundsign.sv
index fe422b98c..8809f0a4b 100644
--- a/src/fpu/postproc/roundsign.sv
+++ b/pipelined/src/fpu/postproc/roundsign.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Sign calculation for rounding
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,6 +25,7 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
 
 module roundsign(
   input logic         Xs,     // x sign
@@ -33,9 +33,9 @@ module roundsign(
   input logic         CvtCs,  // convert result sign
   input logic         FmaSs,  // fma sum sign
   input logic         Sqrt,   // sqrt oppertion? (when using divsqrt unit)
-  input logic         FmaOp,  // is fma operation
-  input logic         DivOp,  // is divsqrt operation
-  input logic         CvtOp,  // is cvt operation
+  input logic         FmaOp,  // is fma opperation
+  input logic         DivOp,  // is divsqrt opperation
+  input logic         CvtOp,  // is cvt opperation
   output logic        Ms      // normalized result sign
 );
 
@@ -47,4 +47,4 @@ module roundsign(
   // Select sign for rounding calulation
   assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv
new file mode 100644
index 000000000..2fb0b5d7e
--- /dev/null
+++ b/pipelined/src/fpu/postproc/shiftcorrection.sv
@@ -0,0 +1,93 @@
+///////////////////////////////////////////
+// shiftcorrection.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: shift correction
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module shiftcorrection(
+  input logic  [`NORMSHIFTSZ-1:0] Shifted,                // the shifted sum before LZA correction
+  // divsqrt
+  input logic                     DivOp,                  // is it a divsqrt opperation
+  input logic                     DivResSubnorm,          // is the divsqrt result subnormal
+  input logic  [`NE+1:0]          DivQe,                  // the divsqrt result's exponent
+  input logic                     DivSubnormShiftPos,     // is the subnorm divider shift amount positive (ie not underflowed)
+  //fma
+  input logic                     FmaOp,                  // is it an fma opperation
+  input logic  [`NE+1:0]          NormSumExp,             // exponent of the normalized sum not taking into account Subnormal or zero results
+  input logic                     FmaPreResultSubnorm,    // is the result subnormal - calculated before LZA corection
+  input logic                     FmaSZero,
+  // output
+  output logic [`NE+1:0]          FmaMe,                  // exponent of the normalized sum
+  output logic [`CORRSHIFTSZ-1:0] Mf,                     // the shifted sum before LZA correction
+  output logic [`NE+1:0]          Qe                      // corrected exponent for divider
+);
+
+  logic [3*`NF+3:0]           CorrSumShifted;             // the shifted sum after LZA correction
+  logic [`CORRSHIFTSZ-1:0]    CorrQm0, CorrQm1;           // portions of Shifted to select for CorrQmShifted
+  logic [`CORRSHIFTSZ-1:0]    CorrQmShifted;              // the shifted divsqrt result after one bit shift
+  logic                       ResSubnorm;                 // is the result Subnormal
+  logic                       LZAPlus1;                   // add one or two to the sum's exponent due to LZA correction
+  logic                       LeftShiftQm;                // should the divsqrt result be shifted one to the left
+
+  // LZA correction
+  assign LZAPlus1 = Shifted[`NORMSHIFTSZ-1];
+
+  // correct the shifting error caused by the LZA
+  //  - the only possible mantissa for a plus two is all zeroes 
+  //      - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
+  mux2 #(`NORMSHIFTSZ-2) lzacorrmux(Shifted[`NORMSHIFTSZ-3:0], Shifted[`NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
+
+  // correct the shifting of the divsqrt caused by producing a result in (2, .5] range
+  //    condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
+  assign LeftShiftQm = (LZAPlus1|(DivQe==1&~LZAPlus1));
+  assign CorrQm0 = Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
+  assign CorrQm1 = Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1];
+  mux2 #(`CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
+  
+  // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
+  always_comb
+    if(FmaOp)                       Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+4){1'b0}}};
+    else if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
+    else                            Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
+    
+  // Determine sum's exponent
+  //  main exponent issues: 
+  //      - LZA was one too large
+  //      - LZA was two too large
+  //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 1
+  //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 2
+  //                          if plus1                    If plus2                               kill if the result Zero or actually subnormal
+  //                          |                           |                                      |
+  assign FmaMe = (NormSumExp+{{`NE+1{1'b0}}, LZAPlus1} +{{`NE+1{1'b0}}, FmaPreResultSubnorm}) & {`NE+2{~(FmaSZero|ResSubnorm)}};
+  
+  // recalculate if the result is subnormal after LZA correction
+  assign ResSubnorm = FmaPreResultSubnorm&~Shifted[`NORMSHIFTSZ-2]&~Shifted[`NORMSHIFTSZ-1];
+
+  // the quotent is in the range [.5,2) if there is no early termination
+  // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
+  assign Qe = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivQe - {(`NE+1)'(0), ~LZAPlus1};
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv
new file mode 100644
index 000000000..6b2985c07
--- /dev/null
+++ b/pipelined/src/fpu/postproc/specialcase.sv
@@ -0,0 +1,309 @@
+///////////////////////////////////////////
+// specialcase.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: special case selection
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module specialcase(
+  input  logic                Xs,         // X sign
+  input  logic [`NF:0]        Xm, Ym, Zm, // input significand's
+  input  logic                XNaN, YNaN, ZNaN, // are the inputs NaN
+  input  logic [2:0]          Frm,        // rounding mode
+  input  logic [`FMTBITS-1:0] OutFmt,     // output format
+  input  logic                InfIn,      // are any inputs infinity
+  input  logic                NaNIn,      // are any input NaNs
+  input  logic                XInf, YInf, // are X or Y inifnity
+  input  logic                XZero,      // is X zero
+  input  logic                Plus1,      // do you add one for rounding
+  input  logic                Rs,         // the result's sign
+  input  logic                Invalid, Overflow,  // flags to choose the result
+  input  logic [`NE-1:0]      Re,         // Result exponent
+  input  logic [`NE+1:0]      FullRe,     // Result full exponent
+  input  logic [`NF-1:0]      Rf,         // Result fraction
+  // fma
+  input  logic                FmaOp,      // is it a fma opperation
+  // divsqrt
+  input  logic                DivOp,      // is it a divsqrt opperation
+  input  logic                DivByZero,  // divide by zero flag
+  // cvt
+  input  logic                CvtOp,      // is it a conversion opperation
+  input  logic                IntZero,    // is the integer input zero
+  input  logic                IntToFp,    // is cvt int -> fp opperation
+  input  logic                Int64,      // is the integer 64 bits
+  input  logic                Signed,     // is the integer signed
+  input  logic [`NE:0]        CvtCe,      // the calculated expoent for cvt
+  input  logic                IntInvalid, // integer invalid flag to choose the result
+  input  logic                CvtResUf,   // does the convert result underflow
+  input  logic [`XLEN+1:0]    CvtNegRes,  // the possibly negated of the integer result
+  // outputs
+  output logic [`FLEN-1:0]    PostProcRes,// final result
+  output logic [`XLEN-1:0]    FCvtIntRes  // final integer result
+);
+
+  logic [`FLEN-1:0]   XNaNRes;    // X is NaN result
+  logic [`FLEN-1:0]   YNaNRes;    // Y is NaN result
+  logic [`FLEN-1:0]   ZNaNRes;    // Z is NaN result
+  logic [`FLEN-1:0]   InvalidRes; // Invalid result result
+  logic [`FLEN-1:0]   UfRes;      // underflowed result result
+  logic [`FLEN-1:0]   OfRes;      // overflowed result result
+  logic [`FLEN-1:0]   NormRes;    // normal result
+  logic [`XLEN-1:0]   OfIntRes;   // the overflow result for integer output
+  logic               OfResMax;   // does the of result output maximum norm fp number
+  logic               KillRes;    // kill the result for underflow
+  logic               SelOfRes;   // should the overflow result be selected
+
+
+  // does the overflow result output the maximum normalized floating point number
+  //                output infinity if the input is infinity
+  assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Rs) | (Frm[1:0]==2'b11&Rs));
+
+  // select correct outputs for special cases
+  if (`FPSIZES == 1) begin
+      //NaN res selection depending on standard
+      if(`IEEE754) begin
+          assign XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+          assign YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
+          assign ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
+          assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+      end else begin
+          assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+      end
+
+      assign OfRes =  OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
+      assign UfRes = {Rs, {`FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)};
+      assign NormRes = {Rs, Re, Rf};
+
+  end else if (`FPSIZES == 2) begin
+      if(`IEEE754) begin
+          assign XNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
+          assign YNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
+          assign ZNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
+          assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+      end else begin 
+          assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+      end
+
+      always_comb
+          if(OutFmt)
+              if(OfResMax)    OfRes = {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}};
+              else            OfRes = {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
+          else
+              if(OfResMax)    OfRes = {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}};
+              else            OfRes = {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1{1'b1}}, (`NF1)'(0)};
+      assign UfRes = OutFmt ? {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)} : {{`FLEN-`LEN1{1'b1}}, Rs, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+      assign NormRes = OutFmt ? {Rs, Re, Rf} : {{`FLEN-`LEN1{1'b1}}, Rs, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]};
+
+  end else if (`FPSIZES == 3) begin
+      always_comb
+          case (OutFmt)
+              `FMT: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+                      YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
+                      ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
+                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                  end else begin 
+                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                  end
+                  
+                  OfRes = OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
+                  UfRes = {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {Rs, Re, Rf};
+              end
+              `FMT1: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
+                      YNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
+                      ZNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]};
+                      InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+                  end else begin 
+                      InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)};
+                  end
+                  OfRes = OfResMax ? {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, Rs, {`NE1{1'b1}}, (`NF1)'(0)};
+                  UfRes = {{`FLEN-`LEN1{1'b1}}, Rs, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{`FLEN-`LEN1{1'b1}}, Rs, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]};
+              end
+              `FMT2: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]};
+                      YNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF2]};
+                      ZNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF2]};
+                      InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
+                  end else begin 
+                      InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)};
+                  end
+                  
+                  OfRes = OfResMax ? {{`FLEN-`LEN2{1'b1}}, Rs, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, Rs, {`NE2{1'b1}}, (`NF2)'(0)};
+                  UfRes = {{`FLEN-`LEN2{1'b1}}, Rs, (`LEN2-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{`FLEN-`LEN2{1'b1}}, Rs, Re[`NE2-1:0], Rf[`NF-1:`NF-`NF2]};
+              end
+              default: begin
+                  if(`IEEE754) begin
+                      XNaNRes = (`FLEN)'(0);
+                      YNaNRes = (`FLEN)'(0);
+                      ZNaNRes = (`FLEN)'(0);
+                      InvalidRes = (`FLEN)'(0);
+                  end else begin 
+                      InvalidRes = (`FLEN)'(0);
+                  end
+                  OfRes = (`FLEN)'(0);
+                  UfRes = (`FLEN)'(0);
+                  NormRes = (`FLEN)'(0);
+              end
+          endcase
+
+  end else if (`FPSIZES == 4) begin 
+      always_comb
+          case (OutFmt)
+              2'h3: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
+                      YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]};
+                      ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]};
+                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                  end else begin 
+                      InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}};
+                  end
+                  
+                  OfRes = OfResMax ? {Rs, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Rs, {`NE{1'b1}}, {`NF{1'b0}}};
+                  UfRes = {Rs, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {Rs, Re, Rf};
+              end
+              2'h1: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]};
+                      YNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`D_NF]};
+                      ZNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`D_NF]};
+                      InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+                  end else begin 
+                      InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)};
+                  end
+                  OfRes = OfResMax ? {{`FLEN-`D_LEN{1'b1}}, Rs, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, Rs, {`D_NE{1'b1}}, (`D_NF)'(0)};
+                  UfRes = {{`FLEN-`D_LEN{1'b1}}, Rs, (`D_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{`FLEN-`D_LEN{1'b1}}, Rs, Re[`D_NE-1:0], Rf[`NF-1:`NF-`D_NF]};
+              end
+              2'h0: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]};
+                      YNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`S_NF]};
+                      ZNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`S_NF]};
+                      InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+                  end else begin 
+                      InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)};
+                  end
+                  
+                  OfRes = OfResMax ? {{`FLEN-`S_LEN{1'b1}}, Rs, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, Rs, {`S_NE{1'b1}}, (`S_NF)'(0)};
+                  UfRes = {{`FLEN-`S_LEN{1'b1}}, Rs, (`S_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{`FLEN-`S_LEN{1'b1}}, Rs, Re[`S_NE-1:0], Rf[`NF-1:`NF-`S_NF]};
+              end
+              2'h2: begin  
+                  if(`IEEE754) begin
+                      XNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]};
+                      YNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`H_NF]};
+                      ZNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`H_NF]};
+                      InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+                  end else begin 
+                      InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)};
+                  end
+                  
+                  OfRes = OfResMax ? {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE{1'b1}}, (`H_NF)'(0)};      
+                // zero is exact if dividing by infinity so don't add 1
+                  UfRes = {{`FLEN-`H_LEN{1'b1}}, Rs, (`H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
+                  NormRes = {{`FLEN-`H_LEN{1'b1}}, Rs, Re[`H_NE-1:0], Rf[`NF-1:`NF-`H_NF]};
+              end
+          endcase
+  end
+
+  // determine if you shoould kill the res - Cvt
+  //      - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0
+  //      - dont set to zero if fp input is zero but not using the fp input
+  //      - dont set to zero if int input is zero but not using the int input
+  assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[`NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResSubnorm & (Re!=1);
+  
+  // calculate if the overflow result should be selected
+  assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp));
+  
+  // output infinity with result sign if divide by zero
+  if(`IEEE754)
+    always_comb
+      if(XNaN&~(IntToFp&CvtOp))   PostProcRes = XNaNRes;
+      else if(YNaN&~CvtOp)        PostProcRes = YNaNRes;
+      else if(ZNaN&FmaOp)         PostProcRes = ZNaNRes;
+      else if(Invalid)            PostProcRes = InvalidRes;
+      else if(SelOfRes)           PostProcRes = OfRes;
+      else if(KillRes)            PostProcRes = UfRes;
+      else                        PostProcRes = NormRes;
+  else
+    always_comb
+      if(NaNIn|Invalid)           PostProcRes = InvalidRes;
+      else if(SelOfRes)           PostProcRes = OfRes;
+      else if(KillRes)            PostProcRes = UfRes;
+      else                        PostProcRes = NormRes;
+
+  ///////////////////////////////////////////////////////////////////////////////////////
+  // integer result selection        
+  ///////////////////////////////////////////////////////////////////////////////////////        
+
+  // select the overflow integer res
+  //      - negitive infinity and out of range negitive input
+  //                 |  int  |  long  |
+  //          signed | -2^31 | -2^63  |
+  //        unsigned |   0   |    0   |
+  //
+  //      - positive infinity and out of range positive input and NaNs
+  //                 |   int  |  long  |
+  //          signed | 2^31-1 | 2^63-1 |
+  //        unsigned | 2^32-1 | 2^64-1 |
+  //
+  //      other: 32 bit unsinged res should be sign extended as if it were a signed number
+  always_comb
+    if(Signed)
+      if(Xs&~NaNIn) // signed negitive
+        if(Int64)   OfIntRes = {1'b1, {`XLEN-1{1'b0}}};
+        else        OfIntRes = {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
+      else          // signed positive
+        if(Int64)   OfIntRes = {1'b0, {`XLEN-1{1'b1}}};
+        else        OfIntRes = {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
+    else
+      if(Xs&~NaNIn) OfIntRes = {`XLEN{1'b0}}; // unsigned negitive
+      else          OfIntRes = {`XLEN{1'b1}}; // unsigned positive
+
+
+  // select the integer output
+  //      - if the input is invalid (out of bounds NaN or Inf) then output overflow res
+  //      - if the input underflows
+  //          - if rounding and signed opperation and negitive input, output -1
+  //          - otherwise output a rounded 0
+  //      - otherwise output the normal res (trmined and sign extended if nessisary)
+  always_comb
+    if(IntInvalid)          FCvtIntRes = OfIntRes;
+    else if(CvtCe[`NE]) 
+      if(Xs&Signed&Plus1)   FCvtIntRes = {{`XLEN{1'b1}}};
+      else                  FCvtIntRes = {{`XLEN-1{1'b0}}, Plus1};
+    else if(Int64)          FCvtIntRes = CvtNegRes[`XLEN-1:0];
+    else                    FCvtIntRes = {{`XLEN-32{CvtNegRes[31]}}, CvtNegRes[31:0]};
+endmodule
\ No newline at end of file
diff --git a/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv
similarity index 57%
rename from src/fpu/unpack.sv
rename to pipelined/src/fpu/unpack.sv
index e0e35312f..13addc2e3 100644
--- a/src/fpu/unpack.sv
+++ b/pipelined/src/fpu/unpack.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,44 +25,38 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
 
-module unpack import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FLEN-1:0]       X, Y, Z,              // inputs from register file
-  input  logic [P.FMTBITS-1:0]    Fmt,                  // format signal 00 - single 01 - double 11 - quad 10 - half
+module unpack ( 
+  input  logic [`FLEN-1:0]        X, Y, Z,              // inputs from register file
+  input  logic [`FMTBITS-1:0]     Fmt,                  // format signal 00 - single 01 - double 11 - quad 10 - half
   input  logic                    XEn, YEn, ZEn,        // input enables
-  input  logic                    FPUActive,            // Kill inputs when FPU is not active
   output logic                    Xs, Ys, Zs,           // sign bits of XYZ
-  output logic [P.NE-1:0]         Xe, Ye, Ze,           // exponents of XYZ (converted to largest supported precision)
-  output logic [P.NF:0]           Xm, Ym, Zm,           // mantissas of XYZ (converted to largest supported precision)
+  output logic [`NE-1:0]          Xe, Ye, Ze,           // exponents of XYZ (converted to largest supported precision)
+  output logic [`NF:0]            Xm, Ym, Zm,           // mantissas of XYZ (converted to largest supported precision)
   output logic                    XNaN, YNaN, ZNaN,     // is XYZ a NaN
   output logic                    XSNaN, YSNaN, ZSNaN,  // is XYZ a signaling NaN
   output logic                    XSubnorm,             // is X subnormal
   output logic                    XZero, YZero, ZZero,  // is XYZ zero
   output logic                    XInf, YInf, ZInf,     // is XYZ infinity
-  output logic                    XExpMax,              // does X have the maximum exponent (NaN or Inf)
-  output logic [P.FLEN-1:0]       XPostBox,             // X after being properly NaN-boxed
-  output logic [P.NE-2:0]         Bias,                 // Exponent bias
-  output logic [P.LOGFLEN-1:0]    Nf                    // Number of fractional bits
+  output logic                    XExpMax               // does X have the maximum exponent (NaN or Inf)
 );
 
+  logic XExpNonZero, YExpNonZero, ZExpNonZero;          // is the exponent of XYZ non-zero
+  logic XFracZero, YFracZero, ZFracZero;                // is the fraction zero
   logic YExpMax, ZExpMax;                               // is the exponent all 1s
+  
+  unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
+                          .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
+                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
 
-  unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive,
-                          .NaN(XNaN), .SNaN(XSNaN),
-                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax),
-                          .Subnorm(XSubnorm), .PostBox(XPostBox));
+  unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
+                          .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
+                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
 
-  unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive,
-                          .NaN(YNaN), .SNaN(YSNaN),
-                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax),
-                          .Subnorm(), .PostBox());
-
-  unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive,
-                          .NaN(ZNaN), .SNaN(ZSNaN),
-                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax),
-                          .Subnorm(), .PostBox());
- 
-  // look up bias and fractional bits for the given format
-  fmtparams #(P) fmtparams(Fmt, Bias, Nf);
-
- endmodule
+  unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
+                          .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
+                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
+  // is the input subnormal
+  assign XSubnorm = ~XExpNonZero & ~XFracZero;
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv
new file mode 100644
index 000000000..34663bd8c
--- /dev/null
+++ b/pipelined/src/fpu/unpackinput.sv
@@ -0,0 +1,270 @@
+///////////////////////////////////////////
+// unpackinput.sv
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: unpack input: extract sign, exponent, significand, characteristics
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
+
+module unpackinput ( 
+  input  logic [`FLEN-1:0]        In,         // inputs from register file
+  input  logic                    En,         // enable the input
+  input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
+  output logic                    Sgn,        // sign bits of XYZ
+  output logic [`NE-1:0]          Exp,        // exponents of XYZ (converted to largest supported precision)
+  output logic [`NF:0]            Man,        // mantissas of XYZ (converted to largest supported precision)
+  output logic                    NaN,        // is XYZ a NaN
+  output logic                    SNaN,       // is XYZ a signaling NaN
+  output logic                    Zero,       // is XYZ zero
+  output logic                    Inf,        // is XYZ infinity
+  output logic                    ExpNonZero, // is the exponent not zero
+  output logic                    FracZero,   // is the fraction zero
+  output logic                    ExpMax      // does In have the maximum exponent (NaN or Inf)
+);
+
+  logic [`NF-1:0] Frac;       // Fraction of XYZ
+  logic           BadNaNBox;  // is the NaN boxing bad
+  
+  if (`FPSIZES == 1) begin        // if there is only one floating point format supported
+      assign BadNaNBox = 0;
+      assign Sgn = In[`FLEN-1];  // sign bit
+      assign Frac = In[`NF-1:0];  // fraction (no assumed 1)
+      assign ExpNonZero = |In[`FLEN-2:`NF];  // is the exponent non-zero
+      assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};  // exponent.  subnormal numbers have effective biased exponent of 1
+      assign ExpMax = &In[`FLEN-2:`NF];  // is the exponent all 1's
+  
+  end else if (`FPSIZES == 2) begin   // if there are 2 floating point formats supported
+      //***need better names for these constants
+      // largest format | smaller format
+      //----------------------------------
+      //      `FLEN     |     `LEN1       length of floating point number
+      //      `NE       |     `NE1        length of exponent
+      //      `NF       |     `NF1        length of fraction
+      //      `BIAS     |     `BIAS1      exponent's bias value
+      //      `FMT      |     `FMT1       precision's format value - Q=11 D=01 Sticky=00 H=10
+
+      // Possible combinantions specified by spec:
+      //      double and single
+      //      single and half
+
+      // Not needed but can also handle:
+      //      quad   and double
+      //      quad   and single
+      //      quad   and half
+      //      double and half
+
+      assign BadNaNBox = ~(Fmt|(&In[`FLEN-1:`LEN1])); // Check NaN boxing
+
+      // choose sign bit depending on format - 1=larger precsion 0=smaller precision
+      assign Sgn = Fmt ? In[`FLEN-1] : In[`LEN1-1];
+
+      // extract the fraction, add trailing zeroes to the mantissa if nessisary
+      assign Frac = Fmt ? In[`NF-1:0] : {In[`NF1-1:0], (`NF-`NF1)'(0)};
+
+      // is the exponent non-zero
+      assign ExpNonZero = Fmt ? |In[`FLEN-2:`NF] : |In[`LEN1-2:`NF1]; 
+
+      // example double to single conversion:
+      // 1023 = 0011 1111 1111
+      // 127  = 0000 0111 1111 (subtract this)
+      // 896  = 0011 1000 0000
+      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
+      // dexp = 0bdd dbbb bbbb 
+      // also need to take into account possible zero/Subnorm/inf/NaN values
+
+      // extract the exponent, converting the smaller exponent into the larger precision if nessisary
+      //      - if the original precision had a Subnormal number convert the exponent value 1
+      assign Exp = Fmt ? {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero} : {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; 
+
+      // is the exponent all 1's
+      assign ExpMax = Fmt ? &In[`FLEN-2:`NF] : &In[`LEN1-2:`NF1];
+  
+
+  end else if (`FPSIZES == 3) begin       // three floating point precsions supported
+
+      //***need better names for these constants
+      // largest format | larger format  | smallest format
+      //---------------------------------------------------
+      //      `FLEN     |     `LEN1      |    `LEN2       length of floating point number
+      //      `NE       |     `NE1       |    `NE2        length of exponent
+      //      `NF       |     `NF1       |    `NF2        length of fraction
+      //      `BIAS     |     `BIAS1     |    `BIAS2      exponent's bias value
+      //      `FMT      |     `FMT1      |    `FMT2       precision's format value - Q=11 D=01 Sticky=00 H=10
+
+      // Possible combinantions specified by spec:
+      //      quad   and double and single
+      //      double and single and half
+
+      // Not needed but can also handle:
+      //      quad   and double and half
+      //      quad   and single and half
+
+      // Check NaN boxing
+      always_comb
+          case (Fmt)
+              `FMT:  BadNaNBox = 0;
+              `FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1];
+              `FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2];
+              default: BadNaNBox = 1'bx;
+          endcase
+
+      // extract the sign bit
+      always_comb
+          case (Fmt)
+              `FMT:  Sgn = In[`FLEN-1];
+              `FMT1: Sgn = In[`LEN1-1];
+              `FMT2: Sgn = In[`LEN2-1];
+              default: Sgn = 1'bx;
+          endcase
+
+      // extract the fraction
+      always_comb
+          case (Fmt)
+              `FMT: Frac = In[`NF-1:0];
+              `FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)};
+              `FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)};
+              default: Frac = {`NF{1'bx}};
+          endcase
+
+      // is the exponent non-zero
+      always_comb
+          case (Fmt)
+              `FMT:  ExpNonZero = |In[`FLEN-2:`NF];     // if input is largest precision (`FLEN - ie quad or double)
+              `FMT1: ExpNonZero = |In[`LEN1-2:`NF1];  // if input is larger precsion (`LEN1 - double or single)
+              `FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half)
+              default: ExpNonZero = 1'bx; 
+          endcase
+          
+      // example double to single conversion:
+      // 1023 = 0011 1111 1111
+      // 127  = 0000 0111 1111 (subtract this)
+      // 896  = 0011 1000 0000
+      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
+      // dexp = 0bdd dbbb bbbb 
+      // also need to take into account possible zero/Subnorm/inf/NaN values
+
+      // convert the larger precision's exponent to use the largest precision's bias
+      always_comb 
+          case (Fmt)
+              `FMT:  Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};
+              `FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; 
+              `FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero}; 
+              default: Exp = {`NE{1'bx}};
+          endcase
+
+      // is the exponent all 1's
+      always_comb
+          case (Fmt)
+              `FMT:  ExpMax = &In[`FLEN-2:`NF];
+              `FMT1: ExpMax = &In[`LEN1-2:`NF1];
+              `FMT2: ExpMax = &In[`LEN2-2:`NF2];
+              default: ExpMax = 1'bx;
+          endcase
+
+  end else if (`FPSIZES == 4) begin      // if all precsisons are supported - quad, double, single, and half
+  
+      //    quad   |  double  |  single  |  half    
+      //-------------------------------------------------------------------
+      //   `Q_LEN  |  `D_LEN  |  `S_LEN  |  `H_LEN     length of floating point number
+      //   `Q_NE   |  `D_NE   |  `S_NE   |  `H_NE      length of exponent
+      //   `Q_NF   |  `D_NF   |  `S_NF   |  `H_NF      length of fraction
+      //   `Q_BIAS |  `D_BIAS |  `S_BIAS |  `H_BIAS    exponent's bias value
+      //   `Q_FMT  |  `D_FMT  |  `S_FMT  |  `H_FMT     precision's format value - Q=11 D=01 Sticky=00 H=10
+
+      // Check NaN boxing
+      always_comb
+          case (Fmt)
+              2'b11:  BadNaNBox = 0;
+              2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN];
+              2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN];
+              2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN];
+          endcase
+
+      // extract sign bit
+      always_comb
+          case (Fmt)
+              2'b11: Sgn = In[`Q_LEN-1];
+              2'b01: Sgn = In[`D_LEN-1];
+              2'b00: Sgn = In[`S_LEN-1];
+              2'b10: Sgn = In[`H_LEN-1];
+          endcase
+          
+
+      // extract the fraction
+      always_comb
+          case (Fmt)
+              2'b11: Frac = In[`Q_NF-1:0];
+              2'b01: Frac = {In[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
+              2'b00: Frac = {In[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
+              2'b10: Frac = {In[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
+          endcase
+
+      // is the exponent non-zero
+      always_comb
+          case (Fmt)
+              2'b11: ExpNonZero = |In[`Q_LEN-2:`Q_NF];
+              2'b01: ExpNonZero = |In[`D_LEN-2:`D_NF];
+              2'b00: ExpNonZero = |In[`S_LEN-2:`S_NF]; 
+              2'b10: ExpNonZero = |In[`H_LEN-2:`H_NF]; 
+          endcase
+
+
+      // example double to single conversion:
+      // 1023 = 0011 1111 1111
+      // 127  = 0000 0111 1111 (subtract this)
+      // 896  = 0011 1000 0000
+      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
+      // dexp = 0bdd dbbb bbbb 
+      // also need to take into account possible zero/Subnorm/inf/NaN values
+      
+      // convert the double precsion exponent into quad precsion
+      // 1 is added to the exponent if the input is zero or subnormal
+      always_comb
+          case (Fmt)
+              2'b11: Exp = {In[`Q_LEN-2:`Q_NF+1], In[`Q_NF]|~ExpNonZero};
+              2'b01: Exp = {In[`D_LEN-2], {`Q_NE-`D_NE{~In[`D_LEN-2]}}, In[`D_LEN-3:`D_NF+1], In[`D_NF]|~ExpNonZero};
+              2'b00: Exp = {In[`S_LEN-2], {`Q_NE-`S_NE{~In[`S_LEN-2]}}, In[`S_LEN-3:`S_NF+1], In[`S_NF]|~ExpNonZero};
+              2'b10: Exp = {In[`H_LEN-2], {`Q_NE-`H_NE{~In[`H_LEN-2]}}, In[`H_LEN-3:`H_NF+1], In[`H_NF]|~ExpNonZero}; 
+          endcase
+
+
+      // is the exponent all 1's
+      always_comb 
+          case (Fmt)
+              2'b11: ExpMax = &In[`Q_LEN-2:`Q_NF];
+              2'b01: ExpMax = &In[`D_LEN-2:`D_NF];
+              2'b00: ExpMax = &In[`S_LEN-2:`S_NF];
+              2'b10: ExpMax = &In[`H_LEN-2:`H_NF];
+          endcase
+
+  end
+
+  // Output logic
+  assign FracZero = ~|Frac; // is the fraction zero?
+  assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
+  assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
+  assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
+  assign Inf = ExpMax & FracZero &En; // is the input infinity?
+  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
+endmodule
\ No newline at end of file
diff --git a/src/generic/adder.sv b/pipelined/src/generic/adder.sv
similarity index 96%
rename from src/generic/adder.sv
rename to pipelined/src/generic/adder.sv
index f499eca88..7acd20df0 100644
--- a/src/generic/adder.sv
+++ b/pipelined/src/generic/adder.sv
@@ -7,7 +7,6 @@
 // Purpose: Adder
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module adder #(parameter WIDTH=8) (
   input  logic [WIDTH-1:0] a, b,
   output logic [WIDTH-1:0] y
@@ -32,3 +33,5 @@ module adder #(parameter WIDTH=8) (
 
   assign y = a + b;
 endmodule 
+
+
diff --git a/src/generic/aplusbeq0.sv b/pipelined/src/generic/aplusbeq0.sv
similarity index 87%
rename from src/generic/aplusbeq0.sv
rename to pipelined/src/generic/aplusbeq0.sv
index 91e01c7ab..d322216b3 100644
--- a/src/generic/aplusbeq0.sv
+++ b/pipelined/src/generic/aplusbeq0.sv
@@ -7,7 +7,6 @@
 // Purpose: Determine if A+B = 0.  Used in FP divider.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module aplusbeq0 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a, b,
   output logic             zero
@@ -34,9 +35,9 @@ module aplusbeq0 #(parameter WIDTH = 8) (
   logic [WIDTH-1:0] orshift;
 
   // The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns
-  // See J. A. Prabhu and G. Zyner, "167 MHz radix-8 divide and square root using overlapped radix-2 stages," IEEE Symp. Computer Arithmetic, 1995, pp. 155-162.
+  // *** explain, cite book
 
   assign x = a ^ b;
   assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};
   assign zero = (x == orshift);
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/generic/arrs.sv b/pipelined/src/generic/arrs.sv
similarity index 89%
rename from src/generic/arrs.sv
rename to pipelined/src/generic/arrs.sv
index 9fa09f4b6..0bb30c96a 100644
--- a/src/generic/arrs.sv
+++ b/pipelined/src/generic/arrs.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // arrs.sv
 //
-// Written: Rose Thompson rose@rosethompson.net
+// Written: Ross Thompson ross1728@gmail.com
 // Modified: November 12, 2021
 //
 // Purpose: resets are typically asynchronous but need to be synchronized to
@@ -10,7 +10,6 @@
 //          rising edge, but then syncs the falling edge to the posedge clk.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,14 +27,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module arrs(
-  input  logic  clk,
-  input  logic  areset,
+  input  logic 	clk,
+  input  logic 	areset,
   output logic  reset
 );
 
-  logic         metaStable;
-  logic         resetB;
+  logic 	      metaStable;
+  logic 	      resetB;
   
   always_ff @(posedge clk , posedge areset) begin
     if (areset) begin
diff --git a/src/generic/binencoder.sv b/pipelined/src/generic/binencoder.sv
similarity index 94%
rename from src/generic/binencoder.sv
rename to pipelined/src/generic/binencoder.sv
index 558eb759a..89093ea5b 100644
--- a/src/generic/binencoder.sv
+++ b/pipelined/src/generic/binencoder.sv
@@ -1,12 +1,11 @@
 ///////////////////////////////////////////
 // binencoder.sv
 //
-// Written: rose@rosethompson.net November 14, 2022
+// Written: ross1728@gmail.com November 14, 2022
 //
 // Purpose: one-hot to binary encoding.
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
@@ -34,7 +33,7 @@ module binencoder #(parameter N = 8) (
   // this is coded as a priority encoder
   // consider redesigning to take advanteage of one-hot nature of input
   always_comb  begin
-    Y = '0;
+    Y = 0;
     for(index = 0; index < N; index++) 
       if(A[index] == 1'b1) Y = index[$clog2(N)-1:0];
   end
diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/pipelined/src/generic/clockgater.sv
old mode 100755
new mode 100644
similarity index 59%
rename from src/generic/mem/ram1p1rwbe_64x128.sv
rename to pipelined/src/generic/clockgater.sv
index 64ddec259..55f02cff5
--- a/src/generic/mem/ram1p1rwbe_64x128.sv
+++ b/pipelined/src/generic/clockgater.sv
@@ -1,13 +1,12 @@
 ///////////////////////////////////////////
-// ram1p1rwbe_64x128.sv
+// clockgater.sv
 //
-// Written: james.stine@okstate.edu 28 January 2023
+// Written: Ross Thompson 9 January 2021
 // Modified: 
 //
-// Purpose: RAM wrapper for instantiating RAM IP
+// Purpose: Clock gater model. Must use standard cell for synthesis.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,18 +24,28 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ram1p1rwbe_64x128( 
-  input  logic          CLK, 
-  input  logic          CEB, 
-  input  logic          WEB,
-  input  logic [5:0]    A, 
-  input  logic [127:0]  D,
-  input  logic [127:0]  BWEB, 
-  output logic [127:0]  Q
+`include "wally-config.vh"
+
+module clockgater (
+  input logic 	E,
+  input logic 	SE,
+  input logic 	CLK,
+  output logic ECLK
 );
 
-   // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
-   //generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
-   TS1N28HPCPSVTB64X128M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+  if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
+  else begin
+    // *** BUG 
+    // VERY IMPORTANT.
+    // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
+    // Do not use this in synthesis!
+    logic 	enable_q;
+    always_latch begin
+      if(~CLK) begin
+	      enable_q <= E | SE;
+      end
+    end
+    assign ECLK = enable_q & CLK;
+  end    
 
 endmodule
diff --git a/src/generic/counter.sv b/pipelined/src/generic/counter.sv
similarity index 97%
rename from src/generic/counter.sv
rename to pipelined/src/generic/counter.sv
index cc20ae71e..1480dc929 100644
--- a/src/generic/counter.sv
+++ b/pipelined/src/generic/counter.sv
@@ -7,7 +7,6 @@
 // Purpose: Counter with reset and enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module counter #(parameter WIDTH=8) (
   input  logic             clk, reset, en,
   output logic [WIDTH-1:0] q
@@ -35,3 +36,5 @@ module counter #(parameter WIDTH=8) (
   assign qnext = q + 1;
   flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
 endmodule 
+
+
diff --git a/src/generic/csa.sv b/pipelined/src/generic/csa.sv
similarity index 97%
rename from src/generic/csa.sv
rename to pipelined/src/generic/csa.sv
index ac9dfe098..91aef44dd 100644
--- a/src/generic/csa.sv
+++ b/pipelined/src/generic/csa.sv
@@ -7,7 +7,6 @@
 // Purpose: 3:2 carry-save adder
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
diff --git a/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv
similarity index 88%
rename from src/generic/decoder.sv
rename to pipelined/src/generic/decoder.sv
index 8af273fc5..807a6d6ca 100644
--- a/src/generic/decoder.sv
+++ b/pipelined/src/generic/decoder.sv
@@ -7,7 +7,6 @@
 // Purpose: Binary encoding to one-hot decoder
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
@@ -24,10 +23,15 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module decoder #(parameter BINARY_BITS = 3) (
   input  logic [BINARY_BITS-1:0]      binary,
   output logic [(2**BINARY_BITS)-1:0] onehot
 );
 
+  // *** Double check whether this synthesizes as expected
+  //     -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
   assign onehot = 1 << binary;
+
 endmodule
diff --git a/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv
similarity index 96%
rename from src/generic/flop/flop.sv
rename to pipelined/src/generic/flop/flop.sv
index 662b9865e..1e906dca8 100644
--- a/src/generic/flop/flop.sv
+++ b/pipelined/src/generic/flop/flop.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,12 +24,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    q <= d;
+    q <= #1 d;
 endmodule
 
diff --git a/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv
similarity index 95%
rename from src/generic/flop/flopen.sv
rename to pipelined/src/generic/flop/flopen.sv
index e56488a90..32e0d7dd3 100644
--- a/src/generic/flop/flopen.sv
+++ b/pipelined/src/generic/flop/flopen.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop with enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,12 +24,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    if (en) q <= d;
+    if (en) q <= #1 d;
 endmodule
 
diff --git a/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv
similarity index 93%
rename from src/generic/flop/flopenl.sv
rename to pipelined/src/generic/flop/flopenl.sv
index 310be2426..094779c74 100644
--- a/src/generic/flop/flopenl.sv
+++ b/pipelined/src/generic/flop/flopenl.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop with enable and synchronous load
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,
@@ -32,7 +33,7 @@ module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   output TYPE q);
 
   always_ff @(posedge clk)
-    if (load)    q <= val;
-    else if (en) q <= d;
+    if (load)    q <= #1 val;
+    else if (en) q <= #1 d;
 endmodule
 
diff --git a/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv
similarity index 93%
rename from src/generic/flop/flopenr.sv
rename to pipelined/src/generic/flop/flopenr.sv
index 1e92ac513..3b8129e40 100644
--- a/src/generic/flop/flopenr.sv
+++ b/pipelined/src/generic/flop/flopenr.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop with enable, synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,13 +24,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    if (reset)   q <= '0;
-    else if (en) q <= d;
+    if (reset)   q <= #1 0;
+    else if (en) q <= #1 d;
 endmodule
 
diff --git a/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv
similarity index 92%
rename from src/generic/flop/flopenrc.sv
rename to pipelined/src/generic/flop/flopenrc.sv
index 45811db6e..b3d5a1e8e 100644
--- a/src/generic/flop/flopenrc.sv
+++ b/pipelined/src/generic/flop/flopenrc.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop with enable, synchronous reset, enabled clear
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,15 +24,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk) 
-    if (reset)   q <= '0;
+    if (reset)   q <= #1 0;
     else if (en) 
-      if (clear) q <= '0;
-      else       q <= d;
+      if (clear) q <= #1 0;
+      else       q <= #1 d;
 endmodule
 
diff --git a/src/generic/mem/rom1p1r_128x32.sv b/pipelined/src/generic/flop/flopens.sv
old mode 100755
new mode 100644
similarity index 68%
rename from src/generic/mem/rom1p1r_128x32.sv
rename to pipelined/src/generic/flop/flopens.sv
index 0854f1557..1f4c18051
--- a/src/generic/mem/rom1p1r_128x32.sv
+++ b/pipelined/src/generic/flop/flopens.sv
@@ -1,13 +1,12 @@
 ///////////////////////////////////////////
-// rom1p1r_128x32.sv
+// flopens.sv
 //
-// Written: james.stine@okstate.edu 28 January 2023
+// Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: ROM wrapper for instantiating ROM IP
+// Purpose: D flip-flop with enable, synchronous set
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,15 +24,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module rom1p1r_128x32( 
-  input  logic          CLK, 
-  input  logic           CEB, 
-  input  logic [6:0]    A, 
-  output logic [31:0]   Q
-);
+`include "wally-config.vh"
 
-   // replace "generic128x32ROM" with "TS3N..128X32.." module from your memory vendor
-   generic64x128ROM sramIP (.CLK, .CEB, .A, .Q);
+module flopens #(parameter WIDTH = 8) (
+  input  logic             clk, set, en,
+  input  logic [WIDTH-1:0] d, 
+  output logic [WIDTH-1:0] q);
+
+  always_ff @(posedge clk) 
+    if (set)   q <= #1 1;
+    else if (en) q <= #1 d;
+endmodule
 
-endmodule 
 
diff --git a/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv
similarity index 93%
rename from src/generic/flop/flopr.sv
rename to pipelined/src/generic/flop/flopr.sv
index 15deb5d54..b2f99b3cd 100644
--- a/src/generic/flop/flopr.sv
+++ b/pipelined/src/generic/flop/flopr.sv
@@ -7,7 +7,6 @@
 // Purpose: D flip-flop with synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,13 +24,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    if (reset) q <= '0;
-    else       q <= d;
+    if (reset) q <= #1 0;
+    else       q <= #1 d;
 endmodule
 
diff --git a/src/rvvi/regchangedetect.sv b/pipelined/src/generic/flop/floprc.sv
similarity index 69%
rename from src/rvvi/regchangedetect.sv
rename to pipelined/src/generic/flop/floprc.sv
index 31d4ea1ec..8275a8f96 100644
--- a/src/rvvi/regchangedetect.sv
+++ b/pipelined/src/generic/flop/floprc.sv
@@ -1,16 +1,13 @@
 ///////////////////////////////////////////
-// regchangedetect.sv
+// floprc.sv
 //
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 24 January 2024
-// Modified: 24 January 2024
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
 //
-// Purpose: 
-//
-// Documentation: 
+// Purpose: D flip-flop with synchronous reset and clear
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-//
+// 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
@@ -27,15 +24,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module regchangedetect #(parameter XLEN = 64) (
-  input clk, reset,
-  input logic [XLEN-1:0] Value,
-  output logic           Change);
+`include "wally-config.vh"
 
-  logic [XLEN-1:0]           ValueD;
+module floprc #(parameter WIDTH = 8) (
+  input  logic clk,
+  input  logic reset,
+  input  logic clear,
+  input  logic [WIDTH-1:0] d, 
+  output logic [WIDTH-1:0] q);
 
-  flopr #(XLEN) register(clk, reset, Value, ValueD);
-  assign Change = |(Value ^ ValueD);
-  
+  always_ff @(posedge clk)
+    if (reset | clear ) q <= #1 0;
+    else                q <= #1 d;
 endmodule
-  
diff --git a/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv
similarity index 94%
rename from src/generic/flop/synchronizer.sv
rename to pipelined/src/generic/flop/synchronizer.sv
index 35df909b7..f10efaeaf 100644
--- a/src/generic/flop/synchronizer.sv
+++ b/pipelined/src/generic/flop/synchronizer.sv
@@ -7,7 +7,6 @@
 // Purpose: Two-stage flip-flop synchronizer
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module synchronizer ( 
   input  logic clk,
   input  logic d, 
@@ -33,8 +34,8 @@ module synchronizer (
   logic mid;
 
   always_ff @(posedge clk) begin
-    mid <= d;
-    q <= mid;
+    mid <= #1 d;
+    q <= #1 mid;
   end
 endmodule
 
diff --git a/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv
similarity index 86%
rename from src/generic/lzc.sv
rename to pipelined/src/generic/lzc.sv
index 855b64d88..60719c494 100644
--- a/src/generic/lzc.sv
+++ b/pipelined/src/generic/lzc.sv
@@ -6,7 +6,6 @@
 // Purpose: Leading Zero Counter
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,7 +24,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module lzc #(parameter WIDTH = 1) (
-  input  logic [WIDTH-1:0]            num,    // number to count the leading zeroes of
+  input logic  [WIDTH-1:0]            num,    // number to count the leading zeroes of
   output logic [$clog2(WIDTH+1)-1:0]  ZeroCnt // the number of leading zeroes
 );
 
@@ -33,7 +32,7 @@ module lzc #(parameter WIDTH = 1) (
   
   always_comb begin
     i = 0;
-    while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i+1;  // search for leading one
-    ZeroCnt = i[$clog2(WIDTH+1)-1:0];
+    while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1;  // search for leading one
+    ZeroCnt = i[$clog2(WIDTH)-1:0];
   end
 endmodule
diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv
new file mode 100644
index 000000000..7b79eb35c
--- /dev/null
+++ b/pipelined/src/generic/mem/ram1p1rwbe.sv
@@ -0,0 +1,89 @@
+///////////////////////////////////////////
+// 1 port sram.
+//
+// Written: ross1728@gmail.com
+// Created: 3 May 2021
+// Modified: 20 January 2023
+//
+// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
+//          Basic sram with 1 read write port.
+//          When clk rises Addr and LineWriteData are sampled.
+//          Following the clk edge read data is output from the sampled Addr.
+// 
+// Documentation: 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
+
+`include "wally-config.vh"
+
+module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
+  input logic                     clk,
+  input logic                     ce,
+  input logic [$clog2(DEPTH)-1:0] addr,
+  input logic [WIDTH-1:0]         din,
+  input logic                     we,
+  input logic [(WIDTH-1)/8:0]     bwe,
+  output logic [WIDTH-1:0]        dout
+);
+
+  logic [WIDTH-1:0]               RAM[DEPTH-1:0];
+
+  // ***************************************************************************
+  // TRUE SRAM macro
+  // ***************************************************************************
+  if (`USE_SRAM == 1) begin
+    genvar index;
+    // 64 x 128-bit SRAM
+    // check if the size is ok, complain if not***
+    logic [WIDTH-1:0] BitWriteMask;
+    for (index=0; index < WIDTH; index++) 
+      assign BitWriteMask[index] = bwe[index/8];
+    TS1N28HPCPSVTB64X128M4SW sram(
+      .CLK(clk), .CEB(~ce), .WEB(~we),
+      .A(addr), .D(din), 
+      .BWEB(~BitWriteMask), .Q(dout));
+    
+  // ***************************************************************************
+  // READ first SRAM model
+  // ***************************************************************************
+  end else begin: ram
+    integer i;
+
+    // Read
+    always_ff @(posedge clk) 
+      if(ce) dout <= #1 RAM[addr];
+ 
+    // Write divided into part for bytes and part for extra msbs
+	// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
+	// Therefore these always blocks use the older always @(posedge clk) 
+    if(WIDTH >= 8) 
+      always @(posedge clk) 
+        if (ce & we) 
+          for(i = 0; i < WIDTH/8; i++) 
+            if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
+          
+    if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
+      always @(posedge clk) 
+        if (ce & we & bwe[WIDTH/8])
+          RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
+  end
+
+endmodule
diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv
new file mode 100644
index 000000000..5e79d5e24
--- /dev/null
+++ b/pipelined/src/generic/mem/ram2p1r1wb.sv
@@ -0,0 +1,86 @@
+///////////////////////////////////////////
+// ram2p1r1wb
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 14, 2021
+// Modified: 
+//
+// Purpose: Behavioral model of two port SRAM.  While this is synthesizable it will produce a flip flop based memory which
+//          behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm.
+//          
+// 
+// to preload this memory we can use the following command
+// in modelsim's do file.
+// mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
+// example
+// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
+  input  logic              clk,
+  input  logic              reset,
+
+  // port 1 is read only
+  input  logic [DEPTH-1:0]  ra1,
+  output logic [WIDTH-1:0]  rd1,
+  input  logic              ren1,
+
+  // port 2 is write only
+  input  logic [DEPTH-1:0]  wa2,
+  input  logic [WIDTH-1:0]  wd2,
+  input  logic              wen2,
+  input  logic [WIDTH-1:0]  bwe2
+);
+  
+
+  logic [DEPTH-1:0]         ra1q, wa2q;
+  logic                     wen2q;
+  logic [WIDTH-1:0]         wd2q;
+
+  logic [WIDTH-1:0]         mem[2**DEPTH-1:0];
+  logic [WIDTH-1:0]         bwe;
+
+  
+  // SRAMs address busses are always registered first
+  // *** likely issued DH and RT 12/20/22
+  //   wrong enable for write port registers
+  //  prefer to code read like ram1p1rw
+  //  prefer not to have two-cycle write latency
+  //  will require branch predictor changes
+  
+  flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q);
+  flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q);
+  flopr   #(1)     wen2Reg(clk, reset, wen2, wen2q);
+  flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q);
+
+  // read port
+  assign rd1 = mem[ra1q];
+  
+  // write port
+  assign bwe = {WIDTH{wen2q}} & bwe2;
+  always_ff @(posedge clk)
+    mem[wa2q] <= wd2q & bwe | mem[wa2q] & ~bwe;
+ 
+endmodule  
+
+
diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv
new file mode 100644
index 000000000..9b9beaf9b
--- /dev/null
+++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv
@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// 1 port sram.
+//
+// Written: ross1728@gmail.com May 3, 2021
+//          Basic sram with 1 read write port.
+//          When clk rises Addr and LineWriteData are sampled.
+//          Following the clk edge read data is output from the sampled Addr.
+//          Write 
+//
+// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
+
+`include "wally-config.vh"
+
+module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
+  input  logic                     clk,
+  input  logic                     ce1, ce2,
+  input  logic [$clog2(DEPTH)-1:0] ra1,
+  input  logic [WIDTH-1:0]         wd2,
+  input  logic [$clog2(DEPTH)-1:0] wa2,
+  input  logic                     we2,
+  input  logic [(WIDTH-1)/8:0]     bwe2,
+  output logic [WIDTH-1:0]         rd1
+);
+
+  logic [WIDTH-1:0]               mem[DEPTH-1:0];
+
+  // ***************************************************************************
+  // TRUE Smem macro
+  // ***************************************************************************
+
+  // ***************************************************************************
+  // READ first SRAM model
+  // ***************************************************************************
+    integer i;
+
+  // Read
+  always_ff @(posedge clk) 
+    if(ce1) rd1 <= #1 mem[ra1];
+  
+  // Write divided into part for bytes and part for extra msbs
+  if(WIDTH >= 8) 
+    always_ff @(posedge clk) 
+      if (ce2 & we2) 
+        for(i = 0; i < WIDTH/8; i++) 
+          if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
+  
+  if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
+    always_ff @(posedge clk) 
+      if (ce2 & we2 & bwe2[WIDTH/8])
+        mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
+
+endmodule
diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv
new file mode 100644
index 000000000..90bb87f9e
--- /dev/null
+++ b/pipelined/src/generic/mem/rom1p1r.sv
@@ -0,0 +1,100 @@
+///////////////////////////////////////////
+// rom1p1r
+//
+// Written: David_Harris@hmc.edu 8/24/22
+//
+// Purpose: Single-ported ROM
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// This model actually works correctly with vivado.
+
+`include "wally-config.vh"
+
+module rom1p1r
+  #(
+	//--------------------------------------------------------------------------
+	parameter ADDR_WIDTH = 8,
+	// Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth
+	parameter DATA_WIDTH = 32, // Data Width in bits
+    parameter PRELOAD_ENABLED = 0
+	//----------------------------------------------------------------------
+	) (
+	   input logic 					 clk,
+	   input logic 					 ce,
+	   input logic [ADDR_WIDTH-1:0]  addr,
+	   output logic [DATA_WIDTH-1:0] dout
+	   );
+  // Core Memory
+  logic [DATA_WIDTH-1:0] 			 ROM [(2**ADDR_WIDTH)-1:0];
+
+  always @ (posedge clk) begin
+    if(ce) dout <= ROM[addr];    
+  end
+
+  // for FPGA, initialize with zero-stage bootloader
+  if(PRELOAD_ENABLED) begin
+    initial begin
+      ROM[0] =  64'h9581819300002197; 
+      ROM[1] =  64'h4281420141014081; 
+      ROM[2] =  64'h4481440143814301; 
+      ROM[3] =  64'h4681460145814501; 
+      ROM[4] =  64'h4881480147814701; 
+      ROM[5] =  64'h4a814a0149814901; 
+      ROM[6] =  64'h4c814c014b814b01; 
+      ROM[7] =  64'h4e814e014d814d01; 
+      ROM[8] =  64'h0110011b4f814f01; 
+      ROM[9] =  64'h059b45011161016e; 
+      ROM[10] = 64'h0004063705fe0010; 
+      ROM[11] = 64'h05a000ef8006061b; 
+      ROM[12] = 64'h0ff003930000100f; 
+      ROM[13] = 64'h4e952e3110060e37; 
+      ROM[14] = 64'hc602829b0053f2b7; 
+      ROM[15] = 64'h2023fe02dfe312fd; 
+      ROM[16] = 64'h829b0053f2b7007e; 
+      ROM[17] = 64'hfe02dfe312fdc602; 
+      ROM[18] = 64'h4de31efd000e2023; 
+      ROM[19] = 64'h059bf1402573fdd0; 
+      ROM[20] = 64'h0000061705e20870; 
+      ROM[21] = 64'h0010029b01260613; 
+      ROM[22] = 64'h11010002806702fe; 
+      ROM[23] = 64'h84b2842ae426e822; 
+      ROM[24] = 64'h892ee04aec064511; 
+      ROM[25] = 64'h06e000ef07e000ef; 
+      ROM[26] = 64'h979334fd02905563; 
+      ROM[27] = 64'h07930177d4930204; 
+      ROM[28] = 64'h4089093394be2004; 
+      ROM[29] = 64'h04138522008905b3; 
+      ROM[30] = 64'h19e3014000ef2004; 
+      ROM[31] = 64'h64a2644260e2fe94; 
+      ROM[32] = 64'h6749808261056902; 
+      ROM[33] = 64'hdfed8b8510472783; 
+      ROM[34] = 64'h2423479110a73823; 
+      ROM[35] = 64'h10472783674910f7; 
+      ROM[36] = 64'h20058693ffed8b89; 
+      ROM[37] = 64'h05a1118737836749; 
+      ROM[38] = 64'hfed59be3fef5bc23; 
+      ROM[39] = 64'h1047278367498082; 
+      ROM[40] = 64'h47858082dfed8b85; 
+      ROM[41] = 64'h40a7853b4015551b;   
+	  ROM[42] = 64'h808210a7a02367c9;
+	end				
+end
+  
+endmodule // bytewrite_tdp_ram_rf
diff --git a/src/generic/mux.sv b/pipelined/src/generic/mux.sv
similarity index 85%
rename from src/generic/mux.sv
rename to pipelined/src/generic/mux.sv
index f07efeb5c..636c19c9f 100644
--- a/src/generic/mux.sv
+++ b/pipelined/src/generic/mux.sv
@@ -7,7 +7,6 @@
 // Purpose: Various flavors of multiplexers
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
 /* verilator lint_off DECLFILENAME */
 
 module mux2 #(parameter WIDTH = 8) (
@@ -40,7 +40,7 @@ module mux3 #(parameter WIDTH = 8) (
   input  logic [1:0]       s, 
   output logic [WIDTH-1:0] y);
 
-  assign y = s[1] ? d2 : (s[0] ? d1 : d0); // exclusion-tag: mux3
+  assign y = s[1] ? d2 : (s[0] ? d1 : d0); 
 endmodule
 
 module mux4 #(parameter WIDTH = 8) (
@@ -65,15 +65,6 @@ module mux6 #(parameter WIDTH = 8) (
   output logic [WIDTH-1:0] y);
 
   assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
-endmodule // mux6
-
-module mux7 #(parameter WIDTH = 8) (
-  input  logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6,
-  input  logic [2:0]       s,
-  output logic [WIDTH-1:0] y);
-
-  assign y = s[2] ? (s[1] ? d6 : (s[0] ? d5 : d4)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
-
 endmodule
 
 /* verilator lint_on DECLFILENAME */
diff --git a/src/generic/neg.sv b/pipelined/src/generic/neg.sv
similarity index 96%
rename from src/generic/neg.sv
rename to pipelined/src/generic/neg.sv
index 8621e510e..66be9e073 100644
--- a/src/generic/neg.sv
+++ b/pipelined/src/generic/neg.sv
@@ -7,7 +7,6 @@
 // Purpose: 2's complement negator
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,9 +24,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module neg #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] a,
   output logic [WIDTH-1:0] y);
 
   assign y = ~a + 1;
 endmodule
+
diff --git a/src/generic/onehotdecoder.sv b/pipelined/src/generic/onehotdecoder.sv
similarity index 92%
rename from src/generic/onehotdecoder.sv
rename to pipelined/src/generic/onehotdecoder.sv
index 91873c8e8..6334e91f8 100644
--- a/src/generic/onehotdecoder.sv
+++ b/pipelined/src/generic/onehotdecoder.sv
@@ -1,13 +1,12 @@
 ///////////////////////////////////////////
-// onehotdecoder.sv
+// oneHotDecoder.sv
 //
-// Written: rose@rosethompson.net July 09, 2021
+// Written: ross1728@gmail.com July 09, 2021
 // Modified: 
 //
 // Purpose: Bin to one hot decoder. Power of 2 only.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module onehotdecoder #(parameter WIDTH = 2) (
   input  logic [WIDTH-1:0]    bin,
   output logic [2**WIDTH-1:0] decoded
diff --git a/src/generic/or_rows.sv b/pipelined/src/generic/or_rows.sv
similarity index 97%
rename from src/generic/or_rows.sv
rename to pipelined/src/generic/or_rows.sv
index 56e693abb..160bc7447 100644
--- a/src/generic/or_rows.sv
+++ b/pipelined/src/generic/or_rows.sv
@@ -7,7 +7,6 @@
 // Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -25,6 +24,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 // perform an OR of all the rows in an array, producing one output for each column
 // equivalent to assign y = a.or
 module or_rows #(parameter ROWS = 8, COLS=2) (
@@ -47,3 +48,5 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
     /* verilator lint_on UNOPTFLAT */
   end
 endmodule
+
+
diff --git a/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv
similarity index 98%
rename from src/generic/priorityonehot.sv
rename to pipelined/src/generic/priorityonehot.sv
index 65882dd75..ba5ebb90f 100644
--- a/src/generic/priorityonehot.sv
+++ b/pipelined/src/generic/priorityonehot.sv
@@ -17,7 +17,6 @@
 //        out 00000000000100000
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
@@ -34,6 +33,8 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module priorityonehot #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
diff --git a/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv
similarity index 95%
rename from src/generic/prioritythermometer.sv
rename to pipelined/src/generic/prioritythermometer.sv
index ecf37e80e..d1970a805 100644
--- a/src/generic/prioritythermometer.sv
+++ b/pipelined/src/generic/prioritythermometer.sv
@@ -13,7 +13,6 @@
 //        out 00000000000011111
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
@@ -30,6 +29,8 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module prioritythermometer #(parameter N = 8) (
   input  logic  [N-1:0] a,
   output logic  [N-1:0] y
@@ -39,9 +40,14 @@ module prioritythermometer #(parameter N = 8) (
   //  Rather than linear.
 
   // create thermometer code mask
+  /* verilator lint_off UNOPTFLAT */
   genvar i;
   assign y[0] = ~a[0];
   for (i=1; i<N; i++) begin:therm
     assign y[i] = y[i-1] & ~a[i];
   end
+  /* verilator lint_on UNOPTFLAT */
 endmodule
+
+
+
diff --git a/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv
similarity index 67%
rename from src/hazard/hazard.sv
rename to pipelined/src/hazard/hazard.sv
index c15ff208f..ba9e7e21f 100644
--- a/src/hazard/hazard.sv
+++ b/pipelined/src/hazard/hazard.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Determine stalls and flushes
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,27 +26,25 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module hazard ( 
-  input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
-  input  logic  StructuralStallD,
-  input  logic  LSUStallM, IFUStallF,
-  input  logic  FPUStallD, ExternalStall,
-  input  logic  DivBusyE, FDivBusyE,
-  input  logic  wfiM, IntPendingM,
+`include "wally-config.vh"
+
+module hazard(
+  // Detect hazards
+(* mark_debug = "true" *)	      input logic  BPPredWrongE, CSRWriteFenceM, RetM, TrapM,   
+(* mark_debug = "true" *)	      input logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
+(* mark_debug = "true" *)	      input logic  LSUStallM, IFUStallF,
+(* mark_debug = "true" *)       input logic  FCvtIntStallD, FPUStallD,
+(* mark_debug = "true" *)	      input logic  DivBusyE, FDivBusyE,
+(* mark_debug = "true" *)	      input logic  EcallFaultM, BreakpointFaultM,
+(* mark_debug = "true" *)       input logic  WFIStallM,
   // Stall & flush outputs
-  output logic StallF, StallD, StallE, StallM, StallW,
-  output logic FlushD, FlushE, FlushM, FlushW
+(* mark_debug = "true" *)	      output logic StallF, StallD, StallE, StallM, StallW,
+(* mark_debug = "true" *)	      output logic FlushD, FlushE, FlushM, FlushW
 );
 
   logic                                       StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
-  logic                                       LatestUnstalledD, LatestUnstalledE, LatestUnstalledM, LatestUnstalledW;
+  logic                                       FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
   logic                                       FlushDCause, FlushECause, FlushMCause, FlushWCause;
-
-  logic WFIStallM, WFIInterruptedM;
-
-  // WFI logic
-  assign WFIStallM = wfiM & ~IntPendingM;         // WFI waiting for an interrupt or timeout
-  assign WFIInterruptedM = wfiM & IntPendingM;    // WFI detects a pending interrupt.  Retire WFI; trap if interrupt is enabled.
   
   // stalls and flushes
   // loads: stall for one cycle if the subsequent instruction depends on the load
@@ -68,11 +65,10 @@ module hazard (
   // Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
   // Branch misprediction is found in the Execute stage and must flush the next two instructions.
   //   However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
-  // When a WFI is interrupted and causes a trap, it flushes the rest of the pipeline but not the W stage, because the WFI needs to commit
-  assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE;
-  assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
+  assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE;
+  assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE));
   assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
-  assign FlushWCause = TrapM & ~WFIInterruptedM;
+  assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM);
 
   // Stall causes
   //  Most data depenency stalls are identified in the decode stage
@@ -82,34 +78,31 @@ module hazard (
   //  The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.  
   //    The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
   //    A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
-  assign StallFCause = 1'b0;
-  assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
+  assign StallFCause = '0;
+  assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause;
   assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; 
-  assign StallMCause = WFIStallM & ~FlushMCause;
+  assign StallMCause = WFIStallM & ~FlushMCause; 
   // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
   // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
   // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
-  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | ExternalStall;
+  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
 
   // Stall each stage for cause or if the next stage is stalled
-  // coverage off: StallFCause is always 0
-  assign StallF = StallFCause | StallD;
-  // coverage on
-  assign StallD = StallDCause | StallE;
-  assign StallE = StallECause | StallM;
-  assign StallM = StallMCause | StallW;
-  assign StallW = StallWCause;
+  assign #1 StallF = StallFCause | StallD;
+  assign #1 StallD = StallDCause | StallE;
+  assign #1 StallE = StallECause | StallM;
+  assign #1 StallM = StallMCause | StallW;
+  assign #1 StallW = StallWCause;
 
   // detect the first stage that is not stalled
-
-  assign LatestUnstalledD = ~StallD & StallF; // coverage tag: StallD always equals StallF
-  assign LatestUnstalledE = ~StallE & StallD;
-  assign LatestUnstalledM = ~StallM & StallE;
-  assign LatestUnstalledW = ~StallW & StallM;
+  assign FirstUnstalledD = ~StallD & StallF;
+  assign FirstUnstalledE = ~StallE & StallD;
+  assign FirstUnstalledM = ~StallM & StallE;
+  assign FirstUnstalledW = ~StallW & StallM;
   
   // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
-  assign FlushD = LatestUnstalledD | FlushDCause; // coverage tag: LatestUnstalledD always 0
-  assign FlushE = LatestUnstalledE | FlushECause;
-  assign FlushM = LatestUnstalledM | FlushMCause;
-  assign FlushW = LatestUnstalledW | FlushWCause;
+  assign #1 FlushD = FirstUnstalledD | FlushDCause; 
+  assign #1 FlushE = FirstUnstalledE | FlushECause;
+  assign #1 FlushM = FirstUnstalledM | FlushMCause;
+  assign #1 FlushW = FirstUnstalledW | FlushWCause;
 endmodule
diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv
new file mode 100644
index 000000000..ccd55779c
--- /dev/null
+++ b/pipelined/src/ieu/alu.sv
@@ -0,0 +1,90 @@
+///////////////////////////////////////////
+// alu.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
+// Created: 9 January 2021
+// Modified: 
+//
+// Purpose: RISC-V Arithmetic/Logic Unit
+//
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module alu #(parameter WIDTH=32) (
+  input  logic [WIDTH-1:0] A, B,       // Operands
+  input  logic [2:0]       ALUControl, // With Funct3, indicates operation to perform
+  input  logic [2:0]       Funct3,     // With ALUControl, indicates operation to perform
+  output logic [WIDTH-1:0] Result,     // ALU result
+  output logic [WIDTH-1:0] Sum);       // Sum of operands
+
+  // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
+  // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
+  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;  // Intermediate results
+  logic             Carry, Neg;                              // Flags: carry out, negative
+  logic             LT, LTU;                                 // Less than, Less than unsigned
+  logic             W64;                                     // RV64 W-type instruction
+  logic             SubArith;                                // Performing subtraction or arithmetic right shift
+  logic             ALUOp;                                   // 0 for address generation addition or 1 for regular ALU ops
+  logic             Asign, Bsign;                            // Sign bits of A, B
+
+  // Extract control signals from ALUControl.
+  assign {W64, SubArith, ALUOp} = ALUControl;
+
+  // Addition
+  assign CondInvB = SubArith ? ~B : B;
+  assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
+  
+  // Shifts
+  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
+
+  // Condition code flags are based on subtraction output Sum = A-B.
+  // Overflow occurs when the numbers being subtracted have the opposite sign 
+  // and the result has the opposite sign of A.
+  // LT is simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
+  assign Neg  = Sum[WIDTH-1];
+  assign Asign = A[WIDTH-1];
+  assign Bsign = B[WIDTH-1];
+  assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; 
+  assign LTU = ~Carry;
+ 
+  // SLT
+  assign SLT = {{(WIDTH-1){1'b0}}, LT};
+  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
+ 
+  // Select appropriate ALU Result
+  always_comb
+    if (~ALUOp) FullResult = Sum;     // Always add for ALUOp = 0 (address generation)
+    else casez (Funct3)               // Otherwise check Funct3
+      3'b000: FullResult = Sum;       // add or sub
+      3'b?01: FullResult = Shift;     // sll, sra, or srl
+      3'b010: FullResult = SLT;       // slt
+      3'b011: FullResult = SLTU;      // sltu
+      3'b100: FullResult = A ^ B;     // xor
+      3'b110: FullResult = A | B;     // or 
+      3'b111: FullResult = A & B;     // and
+    endcase
+
+  // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
+  if (WIDTH == 64)  assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+  else              assign Result = FullResult;
+endmodule
+
diff --git a/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv
similarity index 95%
rename from src/ieu/comparator.sv
rename to pipelined/src/ieu/comparator.sv
index 175e7df08..5f504dced 100644
--- a/src/ieu/comparator.sv
+++ b/pipelined/src/ieu/comparator.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: Branch comparison
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,6 +27,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 // This comparator is best
 module comparator #(parameter WIDTH=64) (
   input  logic [WIDTH-1:0] a, b,    // Operands
diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv
new file mode 100644
index 000000000..e875c99fa
--- /dev/null
+++ b/pipelined/src/ieu/controller.sv
@@ -0,0 +1,253 @@
+///////////////////////////////////////////
+// controller.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu 
+// Created: 9 January 2021
+// Modified: 
+//
+// Purpose: Top level controller module
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+
+module controller(
+  input  logic		    clk, reset,
+  // Decode stage control signals
+  input  logic        StallD, FlushD,          // Stall, flush Decode stage
+  input  logic [31:0] InstrD,                  // Instruction in Decode stage
+  output logic [2:0]  ImmSrcD,                 // Type of immediate extension
+  input  logic        IllegalIEUInstrFaultD,   // Illegal IEU instruction
+  output logic        IllegalBaseInstrFaultD,  // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  // Execute stage control signals             
+  input  logic 	      StallE, FlushE,          // Stall, flush Execute stage
+  input  logic [1:0]  FlagsE,                  // Comparison flags ({eq, lt})
+  input  logic        FWriteIntE,              // Write integer register, coming from FPU controller
+  output logic        PCSrcE,                  // Select signal to choose next PC (for datapath and Hazard unit)
+  output logic [2:0]  ALUControlE,             // ALU operation to perform
+  output logic 	      ALUSrcAE, ALUSrcBE,      // ALU operands
+  output logic        ALUResultSrcE,           // Selects result to pass on to Memory stage
+  output logic        MemReadE, CSRReadE,      // Instruction reads memory, reads a CSR (needed for Hazard unit)
+  output logic [2:0]  Funct3E,                 // Instruction's funct3 field
+  output logic        IntDivE,                 // Integer divide
+  output logic        MDUE,                    // MDU (multiply/divide) operatio
+  output logic        W64E,                    // RV64 W-type operation
+  output logic        JumpE,	                 // jump instruction
+  output logic        SCE,                     // Store Conditional instruction
+  output logic        BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
+  // Memory stage control signals
+  input  logic        StallM, FlushM,          // Stall, flush Memory stage
+  output logic [1:0]  MemRWM,                  // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write 
+  output logic        CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction
+  output logic [1:0]  AtomicM,                 // Atomic (AMO) instruction
+  output logic [2:0]  Funct3M,                 // Instruction's funct3 field
+  output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
+  output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
+  output logic        InstrValidM,             // Instruction is valid
+  output logic        FWriteIntM,              // FPU controller writes integer register file
+  // Writeback stage control signals
+  input  logic        StallW, FlushW,          // Stall, flush Writeback stage
+  output logic 	      RegWriteW, IntDivW,      // Instruction writes a register, is an integer divide
+  output logic [2:0]  ResultSrcW,              // Select source of result to write back to register file
+  // Stall during CSRs
+  output logic        CSRWriteFenceM,          // CSR write or fence instruction; needs to flush the following instructions
+  output logic        StoreStallD              // Store (memory write) causes stall
+);
+
+  logic [6:0] OpD;                             // Opcode in Decode stage
+  logic [2:0] Funct3D;                         // Funct3 field in Decode stage
+  logic [6:0] Funct7D;                         // Funct7 field in Decode stage
+  logic [4:0] Rs1D;                            // Rs1 source register in Decode stage
+
+  `define CTRLW 23
+
+  // pipelined control signals
+  logic 	     RegWriteD, RegWriteE;           // RegWrite (register will be written)
+  logic [2:0]  ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
+  logic [1:0]  MemRWD, MemRWE;                 // Store (write to memory)
+  logic		     JumpD;                          // Jump instruction
+  logic		     BranchD, BranchE;               // Branch instruction
+  logic	       ALUOpD;                         // 0 for address generation, 1 for all other operations (must use Funct3)
+  logic [2:0]  ALUControlD;                    // Determines ALU operation
+  logic 	     ALUSrcAD, ALUSrcBD;             // ALU inputs
+  logic        ALUResultSrcD, W64D, MDUD;      // ALU result, is RV64 W-type, is multiply/divide instruction
+  logic        CSRZeroSrcD;                    // Ignore setting and clearing zeros to CSR
+  logic        CSRReadD;                       // CSR read instruction
+  logic [1:0]  AtomicD;                        // Atomic (AMO) instruction
+  logic        FenceXD;                        // Fence instruction
+  logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
+  logic        CSRWriteD, CSRWriteE;           // CSR write
+  logic        InstrValidD, InstrValidE;       // Instruction is valid
+  logic        PrivilegedD, PrivilegedE;       // Privileged instruction
+  logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
+  logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
+  logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu
+  logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
+  logic        BranchTakenE;                   // Branch is taken
+  logic        eqE, ltE;                       // Comparator outputs
+  logic        unused; 
+	logic        BranchFlagE;                    // Branch flag to use (chosen between eq or lt)
+  logic        IEURegWriteE;                   // Register write 
+  logic        IllegalERegAdrD;                // RV32E attempts to write upper 16 registers
+  logic [1:0]  AtomicE;                        // Atomic instruction 
+  logic        FenceD, FenceE, FenceM;         // Fence instruction
+  logic        SFenceVmaD;                     // sfence.vma instruction
+  logic        IntDivM;                        // Integer divide instruction
+   
+
+  // Extract fields
+  assign OpD = InstrD[6:0];
+  assign Funct3D = InstrD[14:12];
+  assign Funct7D = InstrD[31:25];
+  assign Rs1D = InstrD[19:15];
+
+  // Main Instruction Decoder
+  always_comb
+    case(OpD)
+    // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
+      7'b0000000:     ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
+      7'b0000011:     ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
+      7'b0000111:     ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw - only legal if FP supported
+      7'b0001111: if (`ZIFENCEI_SUPPORTED)
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
+              	  else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
+      7'b0010011:     ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
+      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
+      7'b0011011: if (`XLEN == 64)
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
+                  else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
+      7'b0100011:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
+      7'b0100111:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // fsw - only legal if FP supported
+      7'b0101111: if (`A_SUPPORTED) begin
+                    if (InstrD[31:27] == 5'b00010)
+                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
+                    else if (InstrD[31:27] == 5'b00011)
+                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
+                    else 
+                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
+                  end else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
+      7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type 
+                  else if (Funct7D == 7'b0000001 & `M_SUPPORTED)
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
+                  else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
+      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
+      7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64)
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
+                  else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64)
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
+                  else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
+      7'b1100011:     ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
+      7'b1100111:     ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
+      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
+      7'b1110011: if (`ZICSR_SUPPORTED) begin
+                   if (Funct3D == 3'b000)
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
+                   else
+                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
+                  end else
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+      default:        ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+    endcase
+
+  // Unswizzle control bits
+  // Squash control signals if coming from an illegal compressed instruction
+  // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
+  assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
+  assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD;
+  assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
+          ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, 
+          PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
+  
+
+  assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
+  assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]);            // Don't write if setting or clearing zeros
+  assign SFenceVmaD = PrivilegedD & (InstrD[31:25] ==  7'b0001001);
+  assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
+
+  // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
+  assign sltD = (Funct3D == 3'b010);
+  assign sltuD = (Funct3D == 3'b011);
+  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed to distinguish sub from addi
+  assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
+  assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
+  assign ALUControlD = {W64D, SubArithD, ALUOpD};
+
+  // Fences
+  // Ordinary fence is presently a nop
+  // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
+  if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei
+    logic FenceID;
+    assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
+    assign InvalidateICacheD = FenceID;
+    assign FlushDCacheD = FenceID;
+  end else begin:fencei
+    assign InvalidateICacheD = 0;
+    assign FlushDCacheD = 0;
+  end
+ 
+  // Decocde stage pipeline control register
+  flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
+
+  // Execute stage pipeline control register and logic
+  flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE,
+                           {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
+                           {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
+
+  // Branch Logic
+  //  The comparator handles both signed and unsigned branches using BranchSignedE
+  //  Hence, only eq and lt flags are needed
+  assign BranchSignedE = ~(Funct3E[2:1] == 2'b11);
+  assign {eqE, ltE} = FlagsE;
+  mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
+  assign BranchTakenE = BranchFlagE ^ Funct3E[0];
+  assign PCSrcE = JumpE | BranchE & BranchTakenE;
+
+  // Other execute stage controller signals
+  assign MemReadE = MemRWE[1];
+  assign SCE = (ResultSrcE == 3'b100);
+  assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
+  assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
+  
+  // Memory stage pipeline control register
+  flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM,
+                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE},
+                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM});
+  
+  // Writeback stage pipeline control register
+  flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
+                         {RegWriteM, ResultSrcM, IntDivM},
+                         {RegWriteW, ResultSrcW, IntDivW});  
+
+  // Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
+  assign CSRWriteFenceM = CSRWriteM | FenceM;
+  //  assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FenceD | FenceE | FenceM;
+
+  // the synchronous DTIM cannot read immediately after write
+  // a cache cannot read or write immediately after a write
+  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
+endmodule
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
new file mode 100644
index 000000000..84e3dc9cb
--- /dev/null
+++ b/pipelined/src/ieu/datapath.sv
@@ -0,0 +1,150 @@
+///////////////////////////////////////////
+// datapath.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
+// Created: 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Integer Datapath
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module datapath (
+  input  logic             clk, reset,
+  // Decode stage signals
+  input  logic [2:0]       ImmSrcD,                 // Selects type of immediate extension
+  input  logic [31:0]      InstrD,                  // Instruction in Decode stage
+  // Execute stage signals
+  input  logic [`XLEN-1:0] PCE,                     // PC in Execute stage  
+  input  logic [`XLEN-1:0] PCLinkE,                 // PC + 4 (of instruction in Execute stage)
+  input  logic [2:0]       Funct3E,                 // Funct3 field of instruction in Execute stage
+  input  logic             StallE, FlushE,          // Stall, flush Execute stage
+  input  logic [1:0]       ForwardAE, ForwardBE,    // Forward ALU operands from later stages
+  input  logic [2:0]       ALUControlE,             // Indicate operation ALU performs
+  input  logic             ALUSrcAE, ALUSrcBE,      // ALU operands
+  input  logic             ALUResultSrcE,           // Selects result to pass on to Memory stage
+  input  logic             JumpE,                   // Is a jump (j) instruction
+  input  logic             BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
+  output logic [1:0]       FlagsE,                  // Comparison flags ({eq, lt})
+  output logic [`XLEN-1:0] IEUAdrE,                 // Address computed by ALU
+  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
+  input  logic             BMUE,                    // Bit manipulation instruction
+  // Memory stage signals
+  input  logic             StallM, FlushM,          // Stall, flush Memory stage
+  input  logic             FWriteIntM, FCvtIntW,    // FPU writes integer register file, FPU converts float to int
+  input  logic [`XLEN-1:0] FIntResM,                // FPU integer result
+  output logic [`XLEN-1:0] SrcAM,                   // ALU's Source A in Memory stage to privilege unit for CSR writes
+  output logic [`XLEN-1:0] WriteDataM,              // Write data in Memory stage
+  // Writeback stage signals
+  input  logic             StallW, FlushW,          // Stall, flush Writeback stage
+(* mark_debug = "true" *)  input  logic             RegWriteW, IntDivW,  // Write register file, integer divide instruction
+  input  logic             SquashSCW,               // Squash a store conditional when a conflict arose
+  input  logic [2:0]       ResultSrcW,              // Select source of result to write back to register file
+  input  logic [`XLEN-1:0] FCvtIntResW,             // FPU convert fp to integer result
+  input  logic [`XLEN-1:0] ReadDataW,               // Read data from LSU
+  input  logic [`XLEN-1:0] CSRReadValW,             // CSR read result
+  input  logic [`XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
+  input  logic [`XLEN-1:0] BMUResultE,              // bit manipulation unit result
+  input  logic [`XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
+   // Hazard Unit signals 
+  output logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E,  // Register sources to read in Decode or Execute stage
+  output logic [4:0]       RdE, RdM, RdW            // Register destinations in Execute, Memory, or Writeback stage
+);
+
+  // Fetch stage signals
+  // Decode stage signals
+  logic [`XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
+  logic [`XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
+  logic [4:0]       RdD;                            // Destination register in Decode stage
+  // Execute stage signals
+  logic [`XLEN-1:0] R1E, R2E;                       // Source operands read from register file
+  logic [`XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
+  logic [`XLEN-1:0] SrcAE, SrcBE;                   // ALU operands
+  logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
+  logic [`XLEN-1:0] IEUBResultE;                    // IEUResultE before optional bit manipulation mux
+  // Memory stage signals
+  logic [`XLEN-1:0] IEUResultM;                     // Result from execution stage
+  logic [`XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
+  // Writeback stage signals
+  logic [`XLEN-1:0] SCResultW;                      // Store Conditional result
+  logic [`XLEN-1:0] ResultW;                        // Result to write to register file
+  logic [`XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
+  logic [`XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
+  logic [`XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
+
+  // Decode stage
+  assign Rs1D      = InstrD[19:15];
+  assign Rs2D      = InstrD[24:20];
+  assign RdD       = InstrD[11:7];
+  regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
+  extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
+ 
+  // Execute stage pipeline register and logic
+  flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
+  flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
+  flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
+  flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
+  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
+  flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
+	
+  mux3  #(`XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
+  mux3  #(`XLEN)  fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
+  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
+  mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
+  mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
+  mux2 #(`XLEN)   altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
+  mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE);
+  if (`B_SUPPORTED)
+    mux2 #(`XLEN)   bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE);
+  else assign IEUResultE = IEUBResultE;
+
+  // Memory stage pipeline register
+  flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
+  flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
+  flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
+  flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
+  
+  // Writeback stage pipeline register and logic
+  flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
+  flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
+
+  // floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt
+  if (`F_SUPPORTED) begin:fpmux
+    mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
+    mux2  #(`XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
+    if (`IDIV_ON_FPU) begin
+      mux2  #(`XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
+    end else begin 
+      assign MulDivResultW = MDUResultW;
+    end
+  end else begin:fpmux
+    assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
+    assign MulDivResultW = MDUResultW;
+  end
+  mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
+ 
+  // handle Store Conditional result if atomic extension supported
+  if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
+  else              assign SCResultW = 0;
+endmodule
diff --git a/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv
similarity index 55%
rename from src/ieu/extend.sv
rename to pipelined/src/ieu/extend.sv
index cbe567ae3..51a10a46c 100644
--- a/src/ieu/extend.sv
+++ b/pipelined/src/ieu/extend.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: Produce sign-extended immediates from various formats
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,29 +27,30 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module extend import cvw::*;  #(parameter cvw_t P) (
-  input  logic [31:7]       InstrD,       // All instruction bits except opcode (lower 7 bits)
-  input  logic [2:0]        ImmSrcD,      // Select what kind of extension to perform
-  output logic [P.XLEN-1:0] ImmExtD);     // Extended immediate
+`include "wally-config.vh"
 
-  localparam [P.XLEN-1:0] undefined = {(P.XLEN){1'bx}}; // could change to 0 after debug
+module extend (
+  input  logic [31:7]       InstrD,      // All instruction bits except opcode (lower 7 bits)
+  input  logic [2:0]        ImmSrcD,     // Select what kind of extension to perform
+  output logic [`XLEN-1:0 ] ImmExtD);    // Extended immediate
+
+  localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
  
   always_comb
-    case (ImmSrcD) 
+    case(ImmSrcD) 
       // I-type 
-      3'b000:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:20]};  
+      3'b000:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:20]};  
       // S-type (stores)
-      3'b001:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]};
+      3'b001:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; 
       // B-type (branches)
-      3'b010:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
+      3'b010:   ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
       // J-type (jal)
-      3'b011:   ImmExtD = {{(P.XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
+      3'b011:   ImmExtD = {{(`XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
       // U-type (lui, auipc)
-      3'b100:   ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
+      3'b100:  ImmExtD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
       // Store Conditional: zero offset
-      3'b101:  if (P.ZALRSC_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0;
-               else             ImmExtD = undefined;
+      3'b101:  if (`A_SUPPORTED) ImmExtD = 0;
+               else              ImmExtD = undefined;
       default: ImmExtD = undefined; // undefined
     endcase  
-
 endmodule
diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv
new file mode 100644
index 000000000..8bfaa51c6
--- /dev/null
+++ b/pipelined/src/ieu/forward.sv
@@ -0,0 +1,64 @@
+///////////////////////////////////////////
+// forward.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
+// Created: 9 January 2021
+// Modified: 
+//
+// Purpose: Determine datapath forwarding
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module forward(
+  // Detect hazards
+  input  logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
+  input  logic        MemReadE, MDUE, CSRReadE,              // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE)
+  input  logic        RegWriteM, RegWriteW,                  // Instruction in Memory or Writeback stage writes register file
+  input  logic	      FCvtIntE,                              // FPU convert float to int
+  input  logic        SCE,                                   // Store Conditional instruction
+  // Forwarding controls
+  output logic [1:0]  ForwardAE, ForwardBE,                  // Select signals for forwarding multiplexers
+  output logic        FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD // Stall due to conversion, load, multiply/divide, CSR read
+);
+
+  logic MatchDE;                                             // Match between a source register in Decode stage and destination register in Execute stage
+  
+  always_comb begin
+    ForwardAE = 2'b00;
+    ForwardBE = 2'b00;
+    if (Rs1E != 5'b0)
+      if      ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
+      else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
+ 
+    if (Rs2E != 5'b0)
+      if      ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
+      else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
+  end
+
+  // Stall on dependent operations that finish in Mem Stage and can't bypass in time
+  assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
+  assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
+  assign LoadStallD = (MemReadE|SCE) & MatchDE;  
+  assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
+  assign CSRRdStallD = CSRReadE & MatchDE;
+endmodule
diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv
new file mode 100644
index 000000000..fd8a74c2b
--- /dev/null
+++ b/pipelined/src/ieu/ieu.sv
@@ -0,0 +1,119 @@
+///////////////////////////////////////////
+// ieu.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Integer Execution Unit: datapath and controller
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ieu (
+  input  logic 		          clk, reset,
+  // Decode stage signals
+  input  logic [31:0] 	    InstrD,                          // Instruction
+  input  logic 		          IllegalIEUInstrFaultD,           // Illegal instruction
+  output logic 		          IllegalBaseInstrFaultD,          // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  // Execute stage signals
+  input  logic [`XLEN-1:0]  PCE,                             // PC
+  input  logic [`XLEN-1:0]  PCLinkE,                         // PC + 4
+  output logic 		          PCSrcE,                          // Select next PC (between PC+4 and IEUAdrE)
+  input  logic 		          FWriteIntE, FCvtIntE,            // FPU writes to integer register file, FPU converts float to int
+  output logic [`XLEN-1:0]  IEUAdrE,                         // Memory address
+  output logic 		          IntDivE, W64E,                   // Integer divide, RV64 W-type instruction 
+  output logic [2:0] 	      Funct3E,                         // Funct3 instruction field
+  output logic [`XLEN-1:0]  ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
+  input  logic              BMUE,                            // This is a bit manipulation instruction
+  output logic [4:0]        RdE,                             // Destination register
+  // Memory stage signals
+  input  logic 		          SquashSCW,                       // Squash store conditional, from LSU
+  output logic [1:0] 	      MemRWM,                          // Read/write control goes to LSU
+  output logic [1:0] 	      AtomicM,                         // Atomic control goes to LSU
+  output logic [`XLEN-1:0]  WriteDataM,                      // Write data to LSU
+  output logic [2:0] 	      Funct3M,                         // Funct3 (size and signedness) to LSU
+  output logic [`XLEN-1:0]  SrcAM,                           // ALU SrcA to Privileged unit and FPU
+  output logic [4:0]        RdM,                             // Destination register
+  input  logic [`XLEN-1:0]  FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
+  output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
+  output logic 		          InstrValidM,                     // Instruction is valid
+  // Writeback stage signals
+  input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
+  input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
+  input  logic [`XLEN-1:0]  MDUResultW,                      // multiply/divide unit result
+  input  logic [`XLEN-1:0]  BMUResultE,                      // bit manipulation unit result
+  input  logic [`XLEN-1:0]  FCvtIntResW,                     // FPU's float to int conversion result
+  input  logic              FCvtIntW,                        // FPU converts float to int
+  output logic [4:0]        RdW,                             // Destination register
+  input  logic [`XLEN-1:0]  ReadDataW,                       // LSU's read data
+  // Hazard unit signals
+  input  logic 		          StallD, StallE, StallM, StallW,  // Stall signals from hazard unit
+  input  logic 		          FlushD, FlushE, FlushM, FlushW,  // Flush signals
+  output logic 		          FCvtIntStallD, LoadStallD,       // Stall causes from IEU to hazard unit
+  output logic              MDUStallD, CSRRdStallD, StoreStallD,
+  output logic 		          CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
+  output logic 		          CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
+);
+
+  logic [2:0] ImmSrcD;                                       // Select type of immediate extension 
+  logic [1:0] FlagsE;                                        // Comparison flags ({eq, lt})
+  logic [2:0] ALUControlE;                                   // ALU control indicates function to perform
+  logic       ALUSrcAE, ALUSrcBE;                            // ALU source operands
+  logic [2:0] ResultSrcW;                                    // Selects result in Writeback stage
+  logic       ALUResultSrcE;                                 // Selects ALU result to pass on to Memory stage
+  logic       SCE;                                           // Store Conditional instruction
+  logic       FWriteIntM;                                    // FPU writing to integer register file
+  logic       IntDivW;                                       // Integer divide instruction
+
+  // Forwarding signals
+  logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E;                        // Source and destination registers
+  logic [1:0] ForwardAE, ForwardBE;                          // Select signals for forwarding multiplexers
+  logic       RegWriteM, RegWriteW;                          // Register will be written in Memory, Writeback stages
+  logic       MemReadE, CSRReadE;                            // Load, CSRRead instruction
+  logic       JumpE;                                         // Jump instruction
+  logic       BranchSignedE;                                 // Branch does signed comparison on operands
+  logic       MDUE;                                          // Multiply/divide instruction
+           
+  controller c(
+    .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
+    .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
+    .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
+    .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
+    .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
+    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
+    .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
+
+  datapath   dp(
+    .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
+    .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, 
+    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
+    .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
+    .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
+    .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
+  
+  forward    fw(
+    .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
+    .MemReadE, .MDUE, .CSRReadE, .RegWriteM, .RegWriteW,
+    .FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
+    .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
+endmodule
+
diff --git a/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv
similarity index 73%
rename from src/ieu/regfile.sv
rename to pipelined/src/ieu/regfile.sv
index 48359d3ca..6ff506ef5 100644
--- a/src/ieu/regfile.sv
+++ b/pipelined/src/ieu/regfile.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: 3-port register file
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,16 +27,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module regfile #(parameter XLEN, E_SUPPORTED) (
+`include "wally-config.vh"
+
+module regfile (
   input  logic             clk, reset,
   input  logic             we3,                 // Write enable
-  input  logic [4:0]       a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
-  input  logic [XLEN-1:0]  wd3,                 // Write data for port 3
-  output logic [XLEN-1:0]  rd1, rd2);           // Read data for ports 1, 2
+  input  logic [ 4:0]      a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
+  input  logic [`XLEN-1:0] wd3,                 // Write data for port 3
+  output logic [`XLEN-1:0] rd1, rd2);           // Read data for ports 1, 2
 
-  localparam NUMREGS = E_SUPPORTED ? 16 : 32;   // only 16 registers in E mode
+  localparam NUMREGS = `E_SUPPORTED ? 16 : 32;  // only 16 registers in E mode
 
-  logic [XLEN-1:0] rf[NUMREGS-1:1];
+(* mark_debug = "true" *)  logic [`XLEN-1:0] rf[NUMREGS-1:1];
   integer i;
 
   // Three ported register file
@@ -50,9 +51,9 @@ module regfile #(parameter XLEN, E_SUPPORTED) (
   // can logic be adjusted to not need resettable registers?
     
   always_ff @(negedge clk)
-    if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= '0;
-    else       if (we3)                 rf[a3] <= wd3;  
+    if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
+    else       if (we3)            rf[a3] <= wd3;	
 
-  assign rd1 = (a1 != 0) ? rf[a1] : 0;
-  assign rd2 = (a2 != 0) ? rf[a2] : 0;
+  assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
+  assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;
 endmodule
diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv
new file mode 100644
index 000000000..77e4dab38
--- /dev/null
+++ b/pipelined/src/ieu/shifter.sv
@@ -0,0 +1,77 @@
+///////////////////////////////////////////
+// shifter.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
+// Created: 9 January 2021
+// Modified: 
+//
+// Purpose: RISC-V 32/64 bit shifter
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module shifter (
+  input  logic [`XLEN-1:0]     A,                     // Source
+  input  logic [`LOG_XLEN-1:0] Amt,                   // Shift amount
+  input  logic                 Right, Arith, W64,     // Shift right, arithmetic, RV64 W-type shift
+  output logic [`XLEN-1:0]     Y);                    // Shifted result
+
+  logic [2*`XLEN-2:0]      z, zshift;                 // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [`LOG_XLEN-1:0]    amttrunc, offset;          // Shift amount adjusted for RV64, right-shift amount
+
+  // Handle left and right shifts with a funnel shifter.
+  // For RV32, only 32-bit shifts are needed.   
+  // For RV64, 32- and 64-bit shifts are needed, with sign extension.
+
+  // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
+  if (`XLEN==32) begin:shifter // RV32
+    always_comb  // funnel mux
+      if (Right) 
+        if (Arith) z = {{31{A[31]}}, A};
+        else       z = {31'b0, A};
+      else         z = {A, 31'b0};
+    assign amttrunc = Amt; // shift amount
+  end else begin:shifter  // RV64
+    always_comb  // funnel mux
+      if (W64) begin // 32-bit shifts
+        if (Right)
+          if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
+          else       z = {95'b0, A[31:0]};
+        else         z = {32'b0, A[31:0], 63'b0};
+      end else begin
+        if (Right)
+          if (Arith) z = {{63{A[63]}}, A};
+          else       z = {63'b0, A};
+        else         z = {A, 63'b0};         
+      end
+    assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
+  end
+
+  // Opposite offset for right shifts
+  assign offset = Right ? amttrunc : ~amttrunc;
+  
+  // Funnel operation
+  assign zshift = z >> offset;
+  assign Y = zshift[`XLEN-1:0];    
+endmodule
+
+
diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv
new file mode 100644
index 000000000..ba5fe374a
--- /dev/null
+++ b/pipelined/src/ifu/BTBPredictor.sv
@@ -0,0 +1,114 @@
+///////////////////////////////////////////
+// ram2p1r1wb
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 15, 2021
+// Modified: 
+//
+// Purpose: BTB model.  Outputs type of instruction (currently 1 hot encoded. Probably want 
+// to encode to reduce storage), valid, target PC.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module BTBPredictor
+  #(parameter int Depth = 10
+    )
+  (input  logic             clk,
+   input logic              reset,
+   input logic              StallF, StallE,
+   input logic [`XLEN-1:0]  LookUpPC,
+   output logic [`XLEN-1:0] TargetPC,
+   output logic [3:0]       InstrClass,
+   output logic             Valid,
+   // update
+   input logic              UpdateEN,
+   input logic [`XLEN-1:0]  UpdatePC,
+   input logic [`XLEN-1:0]  UpdateTarget,
+   input logic [3:0]        UpdateInstrClass,
+   input logic              UpdateInvalid
+   );
+
+  localparam TotalDepth = 2 ** Depth;
+  logic [TotalDepth-1:0]    ValidBits;
+  logic [Depth-1:0]         LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
+  logic                     UpdateENQ;
+  
+
+  // hashing function for indexing the PC
+  // We have Depth bits to index, but XLEN bits as the input.
+  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
+  // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
+  assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};  
+  
+
+  flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
+        .reset(reset),
+        .en(~StallE),
+        .d(UpdatePCIndex),
+        .q(UpdatePCIndexQ));
+  
+  // The valid bit must be resetable.
+  always_ff @ (posedge clk) begin
+    if (reset) begin
+      ValidBits <= #1 {TotalDepth{1'b0}};
+    end else 
+    if (UpdateENQ) begin
+      ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid;
+    end
+  end
+  assign Valid = ValidBits[LookUpPCIndexQ];
+
+
+  flopenr #(1) UpdateENReg(.clk(clk),
+     .reset(reset),
+     .en(~StallF),
+     .d(UpdateEN),
+     .q(UpdateENQ));
+
+
+  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
+        .reset(reset),
+        .en(~StallF),
+        .d(LookUpPCIndex),
+        .q(LookUpPCIndexQ));
+
+
+
+  // the BTB contains the target address.
+  // Another optimization may be using a PC relative address.
+  // *** need to add forwarding.
+
+  // *** optimize for byte write enables
+  // *** switch to ram2p1r1wbefix
+  ram2p1r1wb #(Depth, `XLEN+4) memory(.clk(clk),
+          .reset(reset),
+          .ra1(LookUpPCIndex),
+          .rd1({{InstrClass, TargetPC}}),
+          .ren1(~StallF),
+          .wa2(UpdatePCIndex),
+          .wd2({UpdateInstrClass, UpdateTarget}),
+          .wen2(UpdateEN),
+          .bwe2({4'hF, {`XLEN{1'b1}}})); // *** definitely not right.
+
+
+endmodule
diff --git a/pipelined/src/ifu/CodeAligner.py b/pipelined/src/ifu/CodeAligner.py
new file mode 100644
index 000000000..579fd6237
--- /dev/null
+++ b/pipelined/src/ifu/CodeAligner.py
@@ -0,0 +1,112 @@
+import os
+
+# Kevin Wan kewan@hmc.edu 10/27/2021
+def read_input(filename):  #1
+    """Takes in a string filename and outputs the parsed verilog code by line into a list
+    such that each element of the list is one line of verilog code as a string."""
+    lineOfCode = []
+    input_file = open(filename, 'r')
+    for line in input_file:
+        lineOfCode.append(line)
+    return lineOfCode
+###################################################################################
+def ID_start(GiantString):#2
+    """takes in the list of sv file lines, outputs the location that variable names should start"""
+    VarLoc = 0 
+    VarLineNum = None
+    for lines in GiantString:
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines:# need to account for these space
+                NowLoc = lines.find(']') + 3# column number in sv code when 1st char of the var name should appear. 
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines) # Update this number if new record is made. 
+            else:   
+                NowLoc = lines.find('logic') + 7 # same as before.
+                if NowLoc>VarLoc: 
+                    VarLoc = NowLoc
+                    VarLineNum = GiantString.index(lines)
+    #print("Furthest variable appears on line", VarLineNum + 1,VarLoc)   # Disable this line after debugging. 
+    return VarLoc
+##################################################################################
+def modified_logNew(GS,SOV): #3
+    Ind = SOV - 1 # SOV is for human readability, Ind is the character's index in computer, since computers count from 0's we need to correct it. 
+    Out = []
+    for l in GS:
+        lines = l.replace('\t',' ')
+
+        if ' logic ' in lines and (lines.find("//") == -1 or lines.find("//") > lines.find(' logic ')): # // logic does not proceed. logic proceeds. logic // proceeds. 
+            if "[" in lines and "]" in lines: # the line is an extended declaration. 
+                EditLoc = lines.find("]") # Re-finds the string index number of ]. 
+                VarLoc = FindCharRel(lines[EditLoc+1::]) + EditLoc + 1  # Checks where variable declaration currently is at. 
+                #print(VarLoc,lines[VarLoc])# VERIFIED
+                NewLine = Mod_Space_at(lines,VarLoc,VarLoc-Ind) 
+                Out.append(NewLine)# Verified0957 10272021
+            else:
+                EditLoc1 = lines.find('c') # Hopefully sees the c in 'logic'
+
+                VarLoc1 = FindCharRel(lines[EditLoc1+1::]) + EditLoc1 + 1
+                NewLine1 = Mod_Space_at(lines,VarLoc1,VarLoc1-Ind)
+
+                Out.append(NewLine1)# Verified 1005 10272021
+        else:
+            Out.append(lines)
+    return Out   
+################################################################################
+def write_to_output(filename,GiantString,OW=True,Lines_editted=None):   #4
+ """Filename is preferrably passed from the early function calls"""
+ """GiantString has all the corrected features in the code, each line is a good verilog code line"""
+ newname = filename
+ if not OW or OW =='f':   #which means no overwrite (create a new file)
+  Decomposed=filename.split('.')
+  newname = Decomposed[0] + "_AL." + Decomposed[1] # AL for aligned. 
+  
+ OutFile = open(newname,'w') # This step should create a new file. 
+ OutFile.writelines(GiantString)
+ OutFile.close()
+ print("Success! " + newname + " Now contains an aligned file!")
+ return newname
+#################################################################################
+
+def FindCharRel(Ln):
+    #returns the computer location of a character's first occurence
+    for num in range(len(Ln)):
+        if Ln[num] != " ":
+            return num 
+
+
+def Mod_Space_at(Ln,loc,diff):
+    #loc is the varLoc from mln, diff is varLoc - Ind
+    if diff > 0: # to delete
+        NewString = Ln[:(loc-diff)] + Ln[loc:]
+        
+    if diff < 0: # to add
+        NewString = Ln[:loc] + (-diff)*" " + Ln[loc:]
+    if diff == 0:
+        NewString = Ln
+    
+    return NewString
+
+'''def main_filehandler(overwrite=False):
+    for filename in os.listdir():
+        if ".sv" in filename:
+            GiantString = read_input(filename)
+            SOV = ID_start(GiantString)
+            ModifiedGS = modified_logNew(GiantString,SOV)
+            Newname = write_to_output(filename,ModifiedGS,overwrite)'''
+def root_filehandler(path,overwrite=False):
+    for f in os.listdir(path):
+        if os.path.isdir(f):
+            root_filehandler(path+"/"+f)
+        else:
+            if ".sv" in f:
+                GiantString = read_input(f)
+                SOV = ID_start(GiantString)
+                ModifiedGS = modified_logNew(GiantString,SOV)
+                Newname = write_to_output(f,ModifiedGS,overwrite)
+                
+                
+def driver(overwrite=False):
+    root_filehandler(os.getcwd())
+ 
+driver(True)
\ No newline at end of file
diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv
new file mode 100644
index 000000000..c71ff2966
--- /dev/null
+++ b/pipelined/src/ifu/RAsPredictor.sv
@@ -0,0 +1,86 @@
+///////////////////////////////////////////
+// RASPredictor.sv
+//
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
+// Created: February 15, 2021
+// Modified: 
+//
+// Purpose: 2 bit saturating counter predictor with parameterized table depth.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module RASPredictor
+  #(parameter int StackSize = 16
+    )
+  (input logic              clk,
+   input logic 				reset,
+   input logic 				PopF,
+   output logic [`XLEN-1:0] RASPCF,
+   input logic [3:0] 		WrongPredInstrClassD,
+   input logic [3:0] 		InstrClassD,
+   input logic 				PushE,
+   input logic 				incr,
+   input logic [`XLEN-1:0] 	PCLinkE
+   );
+
+  // *** need to update so it either doesn't push until the memory stage
+  // or need to repair flushed push.
+  // *** need to repair popped and then flushed returns.
+  logic                     CounterEn;
+  localparam Depth = $clog2(StackSize);
+
+  logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
+  logic [StackSize-1:0]     [`XLEN-1:0] memory;
+  integer        index;
+  
+  assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2];
+
+  assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
+
+  assign PtrM1 = PtrQ - 1'b1;
+  assign PtrP1 = PtrQ + 1'b1;
+  // may have to handle a PushE and an incr at the same time.
+  // *** what happens if jal is executing and there is a return being flushed in Decode?
+
+  flopenr #(Depth) PTR(.clk(clk),
+      .reset(reset),
+      .en(CounterEn),
+      .d(PtrD),
+      .q(PtrQ));
+
+  // RAS must be reset. 
+  always_ff @ (posedge clk) begin
+    if(reset) begin
+      for(index=0; index<StackSize; index++)
+ memory[index] <= {`XLEN{1'b0}};
+    end else if(PushE) begin
+      memory[PtrP1] <= #1 PCLinkE;
+    end
+  end
+
+  assign RASPCF = memory[PtrQ];
+  
+  
+endmodule
+
+
+
diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
new file mode 100644
index 000000000..ab47d678f
--- /dev/null
+++ b/pipelined/src/ifu/bpred.sv
@@ -0,0 +1,237 @@
+///////////////////////////////////////////
+// bpred.sv
+//
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: 12 February 2021
+// Modified: 19 January 2023
+//
+// Purpose: Branch direction prediction and jump/branch target prediction.
+//          Prediction made during the fetch stage and corrected in the execution stage.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module bpred (
+   input logic              clk, reset,
+   input logic              StallF, StallD, StallE, StallM, StallW,
+   input logic              FlushD, FlushE, FlushM, FlushW,
+   // Fetch stage
+   // the prediction
+   input logic [31:0]       InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
+   input logic [`XLEN-1:0]  PCNextF,                   // Next Fetch Address
+   input logic [`XLEN-1:0]  PCPlus2or4F,               // PCF+2/4
+   output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
+   output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
+
+   // Update Predictor
+   input logic [`XLEN-1:0]  PCF,                       // Fetch stage instruction address
+   input logic [`XLEN-1:0]  PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+   input logic [`XLEN-1:0]  PCE,                       // Execution stage instruction address
+   input logic [`XLEN-1:0]  PCM,                       // Memory stage instruction address
+
+   // Branch and jump outcome
+   input logic              PCSrcE,                    // Executation stage branch is taken
+   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+
+   // Report branch prediction status
+   output logic             BPPredWrongE,              // Prediction is wrong
+   output logic             DirPredictionWrongM,       // Prediction direction is wrong
+   output logic             BTBPredPCWrongM,           // Prediction target wrong
+   output logic             RASPredPCWrongM,           // RAS prediction is wrong
+   output logic             PredictionInstrClassWrongM // Class prediction is wrong
+   );
+
+  logic                     BTBValidF;
+  logic [1:0]               DirPredictionF;
+
+  logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
+  logic [`XLEN-1:0]         BTBPredPCF, RASPCF;
+  logic                     TargetWrongE;
+  logic                     FallThroughWrongE;
+  logic                     PredictionPCWrongE;
+  logic                     PredictionInstrClassWrongE;
+  logic [3:0]               InstrClassD, InstrClassE, InstrClassW;
+  logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
+  
+  logic                     SelBPPredF;
+  logic [`XLEN-1:0]         BPPredPCF;
+  logic                     BPPredWrongM;
+  logic [`XLEN-1:0]         PCNext0F;
+  logic [`XLEN-1:0] 		PCCorrectE;
+  logic [3:0] 				WrongPredInstrClassD;
+  
+  // Part 1 branch direction prediction
+  // look into the 2 port Sram model. something is wrong. 
+  if (`BPTYPE == "BPTWOBIT") begin:Predictor
+    twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+  end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
+    globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+  end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
+    speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
+      .BranchInstrW(InstrClassW[0]), .PCSrcE);
+    
+  end else if (`BPTYPE == "BPGSHARE") begin:Predictor
+    gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+  end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
+    speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
+      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
+
+  end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
+    // *** Fix me
+/* -----\/----- EXCLUDED -----\/-----
+    localHistoryPredictor DirPredictor(.clk,
+      .reset, .StallF, .StallE,
+      .LookUpPC(PCNextF),
+      .Prediction(DirPredictionF),
+      // update
+      .UpdatePC(PCE),
+      .UpdateEN(InstrClassE[0] & ~StallE),
+      .PCSrcE,
+      .UpdatePrediction(InstrClassE[0]));
+ -----/\----- EXCLUDED -----/\----- */
+  end 
+
+
+  // this predictor will have two pieces of data,
+  // 1) A direction (1 = Taken, 0 = Not Taken)
+  // 2) Any information which is necessary for the predictor to build its next state.
+  // For a 2 bit table this is the prediction count.
+  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | 
+         PredInstrClassF[2] |
+         (PredInstrClassF[1] & BTBValidF) ;
+
+  // Part 2 Branch target address prediction
+  // *** For now the BTB will house the direct and indirect targets
+
+  // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
+  BTBPredictor TargetPredictor(.clk(clk),
+          .reset(reset),
+          .*, // Stalls and flushes
+          .LookUpPC(PCNextF),
+          .TargetPC(BTBPredPCF),
+          .InstrClass(PredInstrClassF),
+          .Valid(BTBValidF),
+          // update
+          .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
+          .UpdatePC(PCE),
+          .UpdateTarget(IEUAdrE),
+          .UpdateInvalid(PredictionInstrClassWrongE),
+          .UpdateInstrClass(InstrClassE));
+
+  // Part 3 RAS
+  // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
+  // *** needs to include flushX
+  RASPredictor RASPredictor(.clk(clk),
+       .reset(reset),
+       .PopF(PredInstrClassF[2] & ~StallF),
+							.WrongPredInstrClassD,
+							.InstrClassD,
+       .RASPCF,
+       .PushE(InstrClassE[3] & ~StallE),
+       .incr(1'b0),
+       .PCLinkE);
+
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF;
+
+  // the branch predictor needs a compact decoding of the instruction class.
+  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
+  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
+  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+  flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
+  flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
+  flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
+  flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
+
+  // branch predictor
+  flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
+    {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
+    {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
+
+  // pipeline the class
+  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
+  flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
+
+  // Check the prediction
+  // first check if the target or fallthrough address matches what was predicted.
+  assign TargetWrongE = IEUAdrE != PCD;
+  assign FallThroughWrongE = PCLinkE != PCD;
+  // If the target is taken check the target rather than fallthrough.  The instruction needs to be a branch if PCSrcE is selected
+  // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken.  If the real instruction is non cfi
+  // it must have selected the fall through.
+  assign PredictionPCWrongE = (PCSrcE  & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
+
+  // The branch direction also need to checked.
+  // However if the direction is wrong then the pc will be wrong.  This is only relavent to checking the
+  // accuracy of the direciton prediction.
+  //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
+  
+  // Finally we need to check if the class is wrong.  When the class is wrong the BTB needs to be updated.
+  // Also we want to track this in a performance counter.
+  assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
+
+  // We want to output to the instruction fetch if the PC fetched was wrong.  If by chance the predictor was wrong about
+  // the direction or class, but correct about the target we don't have the flush the pipeline.  However we still
+  // need this information to verify the accuracy of the predictors.
+  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
+
+  // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
+  assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE;
+  // similar with RAS
+  assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE;
+  // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
+  assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
+
+  // branch class prediction wrong.
+  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
+  
+  
+  // Selects the BP or PC+2/4.
+  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
+  // If the prediction is wrong select the correct address.
+  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
+  // Correct branch/jump target.
+  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
+  
+  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
+  // Effectively this is PCM+4 or the non-existant PCLinkM
+  //  if(`BPCLASS) begin
+  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
+  //  end else begin
+  //	assign NextValidPCE = PCE;
+  //  end
+  
+endmodule
diff --git a/pipelined/src/ifu/decompress.sv b/pipelined/src/ifu/decompress.sv
new file mode 100644
index 000000000..190ff77f0
--- /dev/null
+++ b/pipelined/src/ifu/decompress.sv
@@ -0,0 +1,178 @@
+///////////////////////////////////////////
+// decompress.sv
+//
+// Written: David_Harris@hmc.edu
+// Created: 9 January 2021
+// Modified: 18 January 2023
+//
+// Purpose: Expand 16-bit compressed instructions to 32 bits
+//
+// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1)
+//                RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97
+// *** probably need more documentation in this file since the book is very light on decompression.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module decompress (
+  input  logic [31:0] InstrRawD,         // 32-bit instruction or raw un decompress instruction
+  output logic [31:0] InstrD,            // Decompressed instruction
+  output logic        IllegalCompInstrD  // Invalid decompressed instruction
+);
+                        
+  logic [15:0]        instr16;
+  logic [4:0]         rds1, rs2, rs1p, rs2p, rds1p, rdp;
+  logic [11:0]        immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
+  logic [19:0]        immCJ, immCILUI;
+  logic [5:0]         immSH;
+  logic [1:0]         op;
+    
+  // Extrac op and register source/destination fields
+  assign instr16 = InstrRawD[15:0]; // instruction is already aligned
+  assign op = instr16[1:0];
+  assign rds1 = instr16[11:7];
+  assign rs2 = instr16[6:2];
+  assign rs1p = {2'b01, instr16[9:7]};
+  assign rds1p = {2'b01, instr16[9:7]};
+  assign rs2p = {2'b01, instr16[4:2]};
+  assign rdp = {2'b01, instr16[4:2]};
+  
+  // extract compressed immediate formats
+  assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
+  assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
+  assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00}; 
+  assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000}; 
+  assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
+  assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
+  assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
+  assign immCSD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
+  assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
+  assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
+  assign immCI = {{7{instr16[12]}}, instr16[6:2]};
+  assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};
+  assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};
+  assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
+  assign immSH = {instr16[12], instr16[6:2]};
+
+// only for RV128  
+//      assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
+//      assign immCSSQ = {2{instr16[10]}, instr16[10:7], instr16[12:11], 4'b0000};
+//      assign immCLQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
+//      assign immCSQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
+
+  always_comb
+    if (op == 2'b11) begin // noncompressed instruction
+      InstrD = InstrRawD; 
+      IllegalCompInstrD = 0;
+    end else begin  // convert compressed instruction into uncompressed
+      IllegalCompInstrD = 0;
+      case ({op, instr16[15:13]})
+        5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
+                  else begin // illegal instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
+        5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
+        5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
+        5'b00011: if (`XLEN==32)
+                    InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
+                  else
+                    InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
+        5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
+        5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
+        5'b00111: if (`XLEN==32)
+                    InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
+                  else
+                    InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
+        5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
+        5'b01001: if (`XLEN==32) 
+                    InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
+                  else
+                    InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
+        5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
+        5'b01011: if (rds1 != 5'b00010)
+                    InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui
+                  else 
+                    InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
+        5'b01100: if (instr16[11:10] == 2'b00)
+                    InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli
+                  else if (instr16[11:10] == 2'b01)
+                    InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai
+                  else if (instr16[11:10] == 2'b10) 
+                    InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
+                  else if (instr16[12:10] == 3'b011)
+                    if (instr16[6:5] == 2'b00) 
+                      InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
+                    else if (instr16[6:5] == 2'b01) 
+                      InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
+                    else if (instr16[6:5] == 2'b10) 
+                      InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
+                    else // if (instr16[6:5] == 2'b11) 
+                      InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
+                  else if (instr16[12:10] == 3'b111 & `XLEN > 32)
+                    if (instr16[6:5] == 2'b00)
+                      InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
+                    else if (instr16[6:5] == 2'b01)
+                      InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
+                    else begin // reserved  
+                      IllegalCompInstrD = 1;
+                      InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                    end
+                  else begin // illegal instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
+        5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
+        5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
+        5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
+        5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
+        5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
+        5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
+        5'b10011: if (`XLEN == 32)
+                    InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
+                  else 
+                    InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
+        5'b10100: if (instr16[12] == 0)
+                    if (instr16[6:2] == 5'b00000) 
+                      InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
+                    else
+                      InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
+                  else
+                    if (rs2 == 5'b00000)
+                      if (rds1 == 5'b00000) 
+                        InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
+                      else
+                        InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
+                    else
+                      InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
+        5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
+        5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
+        5'b10111: if (`XLEN==32)
+                    InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
+                  else
+                    InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
+        default: begin // illegal instruction
+                    IllegalCompInstrD = 1;
+                    InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
+                  end
+      endcase
+    end
+endmodule
+    
diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/foldedgshare.sv
new file mode 100644
index 000000000..38e0fe610
--- /dev/null
+++ b/pipelined/src/ifu/foldedgshare.sv
@@ -0,0 +1,149 @@
+///////////////////////////////////////////
+// gsharePredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module foldedgshare
+  #(parameter int k = 16,
+	parameter int depth = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+   input logic             PCSrcE
+   );
+
+  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
+
+  logic [k-1:0]            GHRF;
+  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0]            GHRNextF;
+  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0]            IndexNextF, IndexF;
+  logic [k-1:0]            IndexD, IndexE, IndexM, IndexW;
+  logic [depth-1:0] 	   FinalIndexNextF, FinalIndexW;
+  
+  logic                    PCSrcM, PCSrcW;
+  logic [`XLEN-1:0]        PCW;
+
+  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
+  localparam int 		   delta = 2 * depth - k;
+  
+  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
+  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
+  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
+
+  // just be dumb for now.
+  //localparam int kToDepthRatio = (k+depth) / depth;
+  assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
+  assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
+        
+  ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk),
+    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ra1(FinalIndexNextF),
+    .rd1(TableDirPredictionF),
+    .wa2(FinalIndexW),
+    .wd2(NewDirPredictionW),
+    .we2(BranchInstrW & ~StallW & ~FlushW),
+    .bwe2(1'b1));
+
+  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
+  //  and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
+  assign MatchW = BranchInstrW & (IndexNextF == IndexW);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
+                                   MatchD ? NewDirPredictionD :
+                                   MatchE ? NewDirPredictionE :
+                                   MatchM ? NewDirPredictionM :
+                                   NewDirPredictionW;
+
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
+  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
+  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
+
+  // PCSrc pipeline
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
+  
+  // GHR pipeline
+  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
+                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+                    GHRF;
+
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
+  
+  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
+  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+
+  assign GHRNextE = FlushE ? GHRNextM : GHRD;
+  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
+  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+
+  assign GHRNextM = FlushM ? GHRNextW : GHRE;
+  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+
+  assign GHRNextW = FlushW ? GHRW : GHRM;
+  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv
new file mode 100644
index 000000000..92a3f9a1a
--- /dev/null
+++ b/pipelined/src/ifu/globalHistoryPredictor.sv
@@ -0,0 +1,123 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module globalHistoryPredictor
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallE,
+   input logic [`XLEN-1:0] PCNextF,
+   output logic [1:0]      BPPredF,
+   // update
+   input logic [4:0]       InstrClassE,
+   input logic [4:0]       BPInstrClassE,
+   input logic [4:0]       BPInstrClassD,
+   input logic [4:0]       BPInstrClassF, 
+   input logic             BPPredDirWrongE,
+
+   input logic [`XLEN-1:0] PCE,
+   input logic             PCSrcE,
+   input logic [1:0]       UpdateBPPredE
+  
+   );
+  logic [k+1:0]            GHR, GHRNext;
+  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic                    PHTUpdateEN;
+  logic                    BPClassWrongNonCFI;
+  logic                    BPClassWrongCFI;
+  logic                    BPClassRightNonCFI;
+  logic                    BPClassRightBPWrong;
+  logic                    BPClassRightBPRight;
+
+  logic [6:0]              GHRMuxSel;
+  logic                    GHRUpdateEN;
+  logic [k-1:0]            GHRLookup;
+
+  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
+  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE;
+  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE;
+  
+  
+  // GHR update selection, 1 hot encoded.
+  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
+  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
+  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
+  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
+  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
+  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
+
+  // hoping this created a AND-OR mux.
+  always_comb begin
+    case (GHRMuxSel) 
+      7'b000_0001: GHRNext = GHR[k-1+2:0];  // no change
+      7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
+      7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
+      7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
+      7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
+      7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
+      7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
+      default: GHRNext = GHR[k-1+2:0];
+    endcase
+  end
+
+  flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
+           .reset(reset),
+           .en((GHRUpdateEN)),
+           .d(GHRNext),
+           .q(GHR));
+
+  // if actively updating the GHR at the time of prediction we want to us
+  // GHRNext as the lookup rather than GHR.
+
+  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
+  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];  
+  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
+  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
+
+  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
+  
+  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
+  ram2p1r1wb #(k, 2) PHT(.clk(clk),
+    .reset(reset),
+    //.RA1(GHR[k-1:0]),
+    .ra1(GHRLookup),
+    .rd1(BPPredF),
+    .ren1(~StallF),
+    .wa2(PHTUpdateAdr),
+    .wd2(UpdateBPPredE),
+    .wen2(PHTUpdateEN),
+    .bwe2(2'b11));
+
+endmodule
diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/globalhistory.sv
new file mode 100644
index 000000000..86c48f6b5
--- /dev/null
+++ b/pipelined/src/ifu/globalhistory.sv
@@ -0,0 +1,82 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module globalhistory
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM,
+   input logic             FlushD, FlushE, FlushM,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCM,
+   input logic             BranchInstrE, BranchInstrM, PCSrcE
+   );
+
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
+
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRNext;
+  logic                    PCSrcM;
+  
+      
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallM & ~FlushM),
+    .ra1(GHR),
+    .rd1(DirPredictionF),
+    .wa2(GHRM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
+
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+
+  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
+  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
+  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
+  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
+
+
+endmodule
diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/gshare.sv
new file mode 100644
index 000000000..ca801a27c
--- /dev/null
+++ b/pipelined/src/ifu/gshare.sv
@@ -0,0 +1,84 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module gshare
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, 
+   input logic             FlushD, FlushE, FlushM,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCM,
+   input logic             BranchInstrE, BranchInstrM, PCSrcE
+   );
+
+  logic [k-1:0]            IndexNextF, IndexM;
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
+
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRNext;
+  logic                    PCSrcM;
+
+  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallM & ~FlushM),
+    .ra1(IndexNextF),
+    .rd1(DirPredictionF),
+    .wa2(IndexM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
+
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
+  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
+  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
+  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
+
+
+endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
new file mode 100644
index 000000000..1101e6dd4
--- /dev/null
+++ b/pipelined/src/ifu/ifu.sv
@@ -0,0 +1,380 @@
+///////////////////////////////////////////
+// ifu.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified:
+//
+// Purpose: Instrunction Fetch Unit
+//           PC, branch prediction, instruction cache
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ifu (
+  input logic 				clk, reset,
+  input logic 				StallF, StallD, StallE, StallM, StallW,
+  input logic 				FlushD, FlushE, FlushM, FlushW, 
+(* mark_debug = "true" *)  output logic 				IFUStallF,    // IFU stalsl pipeline during a multicycle operation
+  // Command from CPU
+  input logic               InvalidateICacheM,                        // Clears all instruction cache valid bits
+  input logic         	    CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
+	// Bus interface
+(* mark_debug = "true" *)  output logic [`PA_BITS-1:0] IFUHADDR,      // Bus address from IFU to EBU
+(* mark_debug = "true" *)  input logic [`XLEN-1:0] 	HRDATA,           // Bus read data from IFU to EBU
+(* mark_debug = "true" *)  input logic   IFUHREADY,                   // Bus ready from IFU to EBU
+(* mark_debug = "true" *)  output logic  IFUHWRITE,                   // Bus write operation from IFU to EBU
+(* mark_debug = "true" *)  output logic [2:0]  IFUHSIZE,              // Bus operation size from IFU to EBU
+(* mark_debug = "true" *)  output logic [2:0]  IFUHBURST,             // Bus burst from IFU to EBU
+(* mark_debug = "true" *)  output logic [1:0]  IFUHTRANS,             // Bus transaction type from IFU to EBU
+
+(* mark_debug = "true" *)  output logic [`XLEN-1:0] PCF,              // Fetch stage instruction address
+	// Execute
+  output logic [`XLEN-1:0] 	PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
+  input logic 				PCSrcE,                                   // Executation stage branch is taken
+  input logic [`XLEN-1:0] 	IEUAdrE,                                  // The branch/jump target address
+  output logic [`XLEN-1:0] 	PCE,                                      // Execution stage instruction address
+  output logic 				BPPredWrongE,                             // Prediction is wrong
+	// Mem
+  output logic              CommittedF,                               // I$ or bus memory operation started, delay interrupts
+  input logic [`XLEN-1:0] 	UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
+  output logic [`XLEN-1:0]  PCNext2F,                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
+  output logic [31:0] 		InstrD,                                   // The decoded instruction in Decode stage
+  output logic [31:0]       InstrM,                                   // The decoded instruction in Memory stage
+  output logic [`XLEN-1:0] 	PCM,                                      // Memory stage instruction address
+  // branch predictor
+  output logic [3:0] 		InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic 				DirPredictionWrongM,                      // Prediction direction is wrong
+  output logic 				BTBPredPCWrongM,                          // Prediction target wrong
+  output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
+  output logic 				PredictionInstrClassWrongM,               // Class prediction is wrong
+  // Faults
+  input logic 				IllegalBaseInstrFaultD,                   // Illegal non-compressed instruction
+  output logic 				InstrPageFaultF,                          // Instruction page fault 
+  output logic 				IllegalIEUInstrFaultD,                    // Illegal instruction including compressed
+  output logic 				InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
+  // mmu management
+  input logic [1:0] 		PrivilegeModeW,                           // Priviledge mode in Writeback stage
+  input logic [`XLEN-1:0] 	PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
+  input logic [1:0] 		PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
+  input logic 				ITLBWriteF,                               // Writes PTE and PageType to ITLB
+  input logic [`XLEN-1:0] 	SATP_REGW,                                // Location of the root page table and page table configuration
+  input logic 				STATUS_MXR,                               // Status CSR: make executable page readable 
+  input logic               STATUS_SUM,                               // Status CSR: Supervisor access to user memory
+  input logic               STATUS_MPRV,                              // Status CSR: modify machine privilege
+  input logic [1:0] 		STATUS_MPP,                               // Status CSR: previous machine privilege level
+  input logic               sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
+  output logic 				ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
+  output logic              InstrDAPageFaultF,                        // ITLB hit needs to update dirty or access bits
+  input  var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],         // PMP configuration from privileged unit
+  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],  // PMP address from privileged unit
+  output logic 				InstrAccessFaultF,                        // Instruction access fault 
+  output logic              ICacheAccess,                             // Report I$ read to performance counters
+  output logic              ICacheMiss                                // Report I$ miss to performance counters
+);
+
+  localparam [31:0]            nop = 32'h00000013;                    // instruction for NOP
+
+  (* mark_debug = "true" *)  logic [`XLEN-1:0]            PCNextF;    // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
+  logic                        BranchMisalignedFaultE;                // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
+  logic [`XLEN-1:0] 		   PCPlus2or4F;                           // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
+  logic [`XLEN-1:0]			   PCNextFSpill;                          // Next PCF after possible + 2 to handle spill
+  logic [`XLEN-1:0] 		   PCFSpill;                              // PCF with possible + 2 to handle spill
+  logic [`XLEN-1:0]            PCLinkD;                               // PCF2or4F delayed 1 cycle.  This is next PC after a control flow instruction (br or j)
+  logic [`XLEN-1:2]            PCPlus4F;                              // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
+  logic [`XLEN-1:0]            PCD;                                   // Decode stage instruction address
+  logic [`XLEN-1:0] 		   NextValidPCE;                          // The PC of the next valid instruction in the pipeline after  csr write or fence
+(* mark_debug = "true" *)  logic [`PA_BITS-1:0]         PCPF;         // Physical address after address translation
+  logic [`XLEN+1:0]            PCFExt;                                //
+
+  logic [31:0] 				   IROMInstrF;                            // Instruction from the IROM
+  logic [31:0] 				   ICacheInstrF;                          // Instruction from the I$
+  logic [31:0] 				   InstrRawF;                             // Instruction from the IROM, I$, or bus
+  logic                        CompressedF;                           // The fetched instruction is compressed
+(* mark_debug = "true" *)  logic [31:0]  PostSpillInstrRawF;          // Fetch instruction after merge two halves of spill
+  logic [31:0] 				   InstrRawD;                             // Non-decompressed instruction in the Decode stage
+  
+  logic [1:0]                  IFURWF;                                // IFU alreays read IFURWF = 10
+  logic [31:0]                 InstrE;                                // Instruction in the Execution stage
+  logic [31:0] NextInstrD, NextInstrE;                                // Instruction into the next stage after possible stage flush
+
+
+  logic 					   CacheableF;                            // PMA indicates isntruction address is cacheable
+  logic 					   SelNextSpillF;                         // In a spill, stall pipeline and gate local stallF
+  logic 					   BusStall;                              // Bus interface busy with multicycle operation
+  logic 					   ICacheStallF;                          // I$ busy with multicycle operation
+  logic 					   IFUCacheBusStallD;                     // EIther I$ or bus busy with multicycle operation
+  logic 					   GatedStallD;                           // StallD gated by selected next spill
+  // branch predictor signal
+  logic [`XLEN-1:0] 		   PCNext1F;                              // Branch predictor next PCF
+  logic                        BusCommittedF;                         // Bus memory operation in flight, delay interrupts
+  logic 					   CacheCommittedF;                       // I$ memory operation started, delay interrupts
+  logic                        SelIROM;                               // PMA indicates instruction address is in the IROM
+  
+  assign PCFExt = {2'b00, PCFSpill};
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Spill Support
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  if(`C_SUPPORTED) begin : Spill
+    spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
+      .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
+  end else begin : NoSpill
+    assign PCNextFSpill = PCNextF;
+    assign PCFSpill = PCF;
+    assign PostSpillInstrRawF = InstrRawF;
+    assign {SelNextSpillF, CompressedF} = 0;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // Memory management
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+
+  if(`ZICSR_SUPPORTED == 1) begin : immu
+    ///////////////////////////////////////////
+    // sfence.vma causes TLB flushes
+    ///////////////////////////////////////////
+    // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
+    // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
+    // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and 
+    // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush 
+    // after a cycle AND pulse it for another cycle on any further back-to-back sfences. 
+    logic StallMQ, TLBFlush;
+    flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
+    assign TLBFlush = sfencevmaM & ~StallMQ;
+
+    mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
+    immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+         .PrivilegeModeW, .DisableTranslation(1'b0),
+         .VAdr(PCFExt),
+         .Size(2'b10),
+         .PTE(PTE),
+         .PageTypeWriteVal(PageType),
+         .TLBWrite(ITLBWriteF),
+         .TLBFlush,
+         .PhysicalAddress(PCPF),
+         .TLBMiss(ITLBMissF),
+         .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
+         .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
+         .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
+         .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
+         .DAPageFault(InstrDAPageFaultF),
+         .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
+         .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
+
+  end else begin
+    assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrDAPageFaultF} = '0;
+    assign PCPF = PCFExt[`PA_BITS-1:0];
+    assign CacheableF = '1;
+    assign SelIROM = '0;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // Memory 
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // CommittedM tells the CPU's privileged unit the current instruction
+  // in the memory stage is a memory operaton and that memory operation is either completed
+  // or is partially executed. Partially completed memory operations need to prevent an interrupts.
+  // There is not a clean way to restore back to a partial executed instruction.  CommiteedM will
+  // delay the interrupt until the LSU is in a clean state.
+  assign CommittedF = CacheCommittedF | BusCommittedF;
+
+  logic 			   IgnoreRequest;
+  assign IgnoreRequest = ITLBMissF | FlushD;
+
+  // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
+  if (`IROM_SUPPORTED) begin : irom
+	logic IROMce;
+	assign IROMce = ~GatedStallD | reset;
+    assign IFURWF = 2'b10;
+    irom irom(.clk, .ce(IROMce), .Adr(PCNextFSpill[`XLEN-1:0]), .IROMInstrF);
+  end else begin
+    assign IFURWF = 2'b10;
+  end
+  if (`BUS) begin : bus
+    // **** must fix words per line vs beats per line as in lsu.
+    localparam integer   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
+    localparam integer   LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
+    if(`ICACHE) begin : icache
+      localparam integer   LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
+      localparam integer   LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+      logic [LINELEN-1:0]  FetchBuffer;
+      logic [`PA_BITS-1:0] ICacheBusAdr;
+      logic                ICacheBusAck;
+      logic [1:0]          CacheBusRW, BusRW, CacheRWF;
+      
+      assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
+      assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
+      cache #(.LINELEN(`ICACHE_LINELENINBITS),
+              .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
+              .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
+      icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
+             .FetchBuffer, .CacheBusAck(ICacheBusAck),
+             .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
+             .CacheBusRW,
+             .ReadDataWord(ICacheInstrF),
+             .SelHPTW('0),
+             .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
+             .ByteMask('0), .BeatCount('0), .SelBusBeat('0),
+             .CacheWriteData('0),
+             .CacheRW(CacheRWF), 
+             .CacheAtomic('0), .FlushCache('0),
+             .NextAdr(PCNextFSpill[11:0]),
+             .PAdr(PCPF),
+             .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));
+      ahbcacheinterface #(WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW) 
+      ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
+            .HRDATA,
+            .Flush(FlushD), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
+            .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
+            .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0),
+             .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
+            .FetchBuffer, .PAdr(PCPF),
+            .BusRW, .Stall(GatedStallD),
+            .BusStall, .BusCommitted(BusCommittedF));
+
+      mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
+                                 .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
+    end else begin : passthrough
+      assign IFUHADDR = PCPF;
+      logic [31:0]  FetchBuffer;
+      logic [1:0] BusRW;
+      assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
+      assign IFUHSIZE = 3'b010;
+
+      ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
+        .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
+        .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
+        .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
+
+      assign CacheCommittedF = '0;
+      if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF);
+      else assign InstrRawF = FetchBuffer;
+      assign IFUHBURST = 3'b0;
+      assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
+    end
+  end else begin : nobus // block: bus
+    assign {BusStall, CacheCommittedF} = '0;   
+    assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
+    assign InstrRawF = IROMInstrF;
+  end
+  
+  assign IFUCacheBusStallD = ICacheStallF | BusStall;
+  assign IFUStallF = IFUCacheBusStallD | SelNextSpillF;
+  assign GatedStallD = StallD & ~SelNextSpillF;
+  
+  flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // PCNextF logic
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+
+  if(`ZICSR_SUPPORTED | `ZIFENCEI_SUPPORTED)
+    mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F));
+  else assign PCNext2F = PCNext1F;
+
+  assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
+  flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
+
+  // pcadder
+  // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
+  assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC
+  // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
+  // Speeds up critical path as compared to selecting adder input based on CompressedF
+  // *** consider gating PCPlus4F to provide the reset.
+/* -----\/----- EXCLUDED -----\/-----
+  assign PCPlus2or4F[0] = '0;
+  assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
+  assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F;
+ -----/\----- EXCLUDED -----/\----- */
+/* -----\/----- EXCLUDED -----\/-----
+  assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
+ -----/\----- EXCLUDED -----/\----- */
+
+  // *** There is actually a bug in the regression test.  We fetched an address which returns data with
+  // an X.  This version of the code does not die because if CompressedF is an X it just defaults to the last
+  // option.  The above code would work, but propagates the x.
+  always_comb
+    if(reset) PCPlus2or4F = '0;
+    else if (CompressedF) // add 2
+      if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
+      else        PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
+    else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
+
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // Branch and Jump Predictor
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  if (`BPRED_ENABLED) begin : bpred
+    bpred bpred(.clk, .reset,
+                .StallF, .StallD, .StallE, .StallM, .StallW,
+                .FlushD, .FlushE, .FlushM, .FlushW,
+                .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
+                .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
+
+  end else begin : bpred
+    mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F));    
+    assign BPPredWrongE = PCSrcE;
+    assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0;
+    assign NextValidPCE = PCE;
+  end      
+
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // Decode stage pipeline register and compressed instruction decoding.
+  ////////////////////////////////////////////////////////////////////////////////////////////////
+  // Decode stage pipeline register and logic
+  flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
+   
+  // expand 16-bit compressed instructions to 32 bits
+  if (`C_SUPPORTED) begin
+    logic IllegalCompInstrD;
+    decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
+    assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
+  end else begin  
+    assign InstrD = InstrRawD;
+    assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
+  end
+
+  // Misaligned PC logic
+  // Instruction address misalignement only from br/jal(r) instructions.
+  // instruction address misalignment is generated by the target of control flow instructions, not
+  // the fetch itself.
+  // xret and Traps both cannot produce instruction misaligned.
+  // xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21. 
+  // The low bit of mepc (mepc[0]) is always zero. On implementations that support
+  // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
+  // Spec 3.1.14
+  // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
+  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
+  flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
+
+  // Instruction and PC/PCLink pipeline registers
+  // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
+  mux2    #(32)    FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
+  mux2    #(32)    FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
+  flopenr #(32)    InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
+  flopenr #(32)    InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
+  flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
+  flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
+  flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
+  flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+endmodule
diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv
new file mode 100644
index 000000000..ba23cf23b
--- /dev/null
+++ b/pipelined/src/ifu/irom.sv
@@ -0,0 +1,56 @@
+///////////////////////////////////////////
+// irom.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 30 January 2022
+// Modified: 18 January 2023
+//
+// Purpose: simple instruction ROM
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module irom(
+  input logic 			  clk, 
+  input logic 			  ce,        // Chip Enable.  0: Holds IROMInstrF constant
+  input logic [`XLEN-1:0] Adr,       // PCNextFSpill
+  output logic [31:0] 	  IROMInstrF // Instruction read data
+);
+
+  localparam ADDR_WDITH = $clog2(`IROM_RANGE/8); 
+  localparam OFFSET = $clog2(`XLEN/8);
+
+  logic [`XLEN-1:0] IROMInstrFFull;
+  logic [31:0] 		RawIROMInstrF;
+
+  logic [1:0] 			AdrD;
+  flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
+
+  rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
+  if (`XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
+  else             begin
+	// IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two
+	// haves.  Adr is the Next PCF not PCF so we delay 1 cycle.
+    assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
+  end
+  // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
+  // The spill logic will handle merging the two together.
+  assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
+endmodule  
+  
diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv
new file mode 100644
index 000000000..1709772dd
--- /dev/null
+++ b/pipelined/src/ifu/localHistoryPredictor.sv
@@ -0,0 +1,133 @@
+///////////////////////////////////////////
+// locallHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module localHistoryPredictor
+  #(  parameter int m = 6, // 2^m = number of local history branches
+      parameter int k = 10 // number of past branches stored
+      )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF,  StallE,
+   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      Prediction,
+   // update
+   input logic [`XLEN-1:0] UpdatePC,
+   input logic             UpdateEN, PCSrcE, 
+   input logic [1:0]       UpdatePrediction
+  
+   );
+
+  logic [2**m-1:0]         [k-1:0]  LHRNextF;
+  logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
+  logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
+  logic [1:0]              PredictionMemory;
+  logic                    DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
+  logic [1:0]              UpdatePredictionF;
+
+  assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; 
+  assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
+  assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};  
+
+  // INCASE we do ahead pipelining
+  //    ram2p1r1wb #(m,k) LHR(.clk(clk)),
+  //                 .reset(reset),
+  //                 .RA1(LookUpPCIndex), // need hashing function to get correct PC address 
+  //                 .RD1(LHRF),
+  //                 .REN1(~StallF),
+  //                 .WA1(UpdatePCIndex),
+  //                 .WD1(LHRENExt),
+  //                 .WEN1(UpdateEN),
+  //                 .BitWEN1(2'b11));  
+
+  genvar      index;
+  for (index = 0; index < 2**m; index = index +1) begin:localhist
+    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
+                                      .d(LHRFNext), .q(LHRNextF[index]));
+  end 
+
+  // need to forward when updating to the same address as reading.
+  // first we compare to see if the update and lookup addreses are the same
+  assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
+  assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex]; 
+
+  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
+  // LHR referes to the address that the past k branches points to in the prediction stage 
+  // LHRE refers to the address that the past k branches points to in the exectution stage
+  ram2p1r1wb #(k, 2) PHT(.clk(clk), 
+    .reset(reset),
+    .ra1(ForwardLHRNext),
+    .rd1(PredictionMemory),
+    .ren1(~StallF),
+    .wa2(LHRFNext),
+    .wd2(UpdatePrediction),
+    .wen2(UpdateEN),
+    .bwe2(2'b11));
+
+
+  
+  assign DoForwardingPHT = LHRFNext == ForwardLHRNext; 
+
+  // register the update value and the forwarding signal into the Fetch stage
+  // TODO: add stall logic ***
+  flopr #(1) DoForwardingReg(.clk(clk),
+        .reset(reset),
+        .d(DoForwardingPHT),
+        .q(DoForwardingPHTF));
+  
+  flopr #(2) UpdatePredictionReg(.clk(clk),
+     .reset(reset),
+     .d(UpdatePrediction),
+     .q(UpdatePredictionF));
+
+  assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
+  
+  //pipeline for LHR
+  flopenrc #(k) LHRFReg(.clk(clk),
+   .reset(reset),
+   .en(~StallF),
+   .clear(1'b0),
+   .d(ForwardLHRNext),
+   .q(LHRF));
+  /*
+   flopenrc #(k) LHRDReg(.clk(clk),
+   .reset(reset),
+   .en(~StallD),
+   .clear(FlushD),
+   .d(LHRF),
+   .q(LHRD));
+   
+   flopenrc #(k) LHREReg(.clk(clk),
+   .reset(reset),
+   .en(~StallE),
+   .clear(FlushE),
+   .d(LHRD),
+   .q(LHRE));
+   */
+endmodule
diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/oldgsharepredictor.sv
new file mode 100644
index 000000000..29a622517
--- /dev/null
+++ b/pipelined/src/ifu/oldgsharepredictor.sv
@@ -0,0 +1,130 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Gshare predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+module oldgsharepredictor
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   output logic [1:0]      DirPredictionF,
+   // update
+   input logic [4:0]       InstrClassE,
+   input logic [4:0]       BPInstrClassE,
+   input logic [4:0]       BPInstrClassD,
+   input logic [4:0]       BPInstrClassF, 
+   output logic            DirPredictionWrongE,
+
+   input logic             PCSrcE
+  
+   );
+  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
+  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic                    PHTUpdateEN;
+  logic                    BPClassWrongNonCFI;
+  logic                    BPClassWrongCFI;
+  logic                    BPClassRightNonCFI;
+  logic                    BPClassRightBPWrong;
+  logic                    BPClassRightBPRight;
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE;
+
+  logic [6:0]              GHRMuxSel;
+  logic                    GHRUpdateEN;
+  logic [`BPRED_SIZE-1:0]            GHRLookup;
+
+  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
+  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
+  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
+  
+  
+  // GHR update selection, 1 hot encoded.
+  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
+  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
+  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
+  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
+  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
+  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
+
+  // hoping this created a AND-OR mux.
+  always_comb begin
+    case (GHRMuxSel) 
+      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
+      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
+      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
+      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
+      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
+      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
+      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
+      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
+    endcase
+  end
+
+  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
+           .reset(reset),
+           .en((GHRUpdateEN)),
+           .d(GHRNext),
+           .q(GHR));
+
+  // if actively updating the GHR at the time of prediction we want to us
+  // GHRNext as the lookup rather than GHR.
+
+  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
+  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
+  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
+  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
+
+  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
+  
+  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
+  ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
+    .reset(reset),
+    //.RA1(GHR[`BPRED_SIZE-1:0]),
+    .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
+    .rd1(DirPredictionF),
+    .ren1(~StallF),
+    .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
+    .wd2(NewDirPredictionE),
+    .wen2(PHTUpdateEN),
+    .bwe2(2'b11));
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
+
+endmodule // gsharePredictor
diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/oldgsharepredictor2.sv
new file mode 100644
index 000000000..679358e37
--- /dev/null
+++ b/pipelined/src/ifu/oldgsharepredictor2.sv
@@ -0,0 +1,130 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Gshare predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+module oldgsharepredictor2
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   output logic [1:0]      DirPredictionF,
+   // update
+   input logic [4:0]       InstrClassE,
+   input logic [4:0]       BPInstrClassE,
+   input logic [4:0]       BPInstrClassD,
+   input logic [4:0]       BPInstrClassF, 
+   output logic            DirPredictionWrongE,
+
+   input logic             PCSrcE
+  
+   );
+  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
+  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic                    PHTUpdateEN;
+  logic                    BPClassWrongNonCFI;
+  logic                    BPClassWrongCFI;
+  logic                    BPClassRightNonCFI;
+  logic                    BPClassRightBPWrong;
+  logic                    BPClassRightBPRight;
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE;
+
+  logic [6:0]              GHRMuxSel;
+  logic                    GHRUpdateEN;
+  logic [`BPRED_SIZE-1:0]            GHRLookup;
+
+  assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
+  assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
+  assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
+  assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
+  
+  
+  // GHR update selection, 1 hot encoded.
+  assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
+  assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
+  assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
+  assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
+  assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
+  assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
+  assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
+
+  // hoping this created a AND-OR mux.
+  always_comb begin
+    case (GHRMuxSel) 
+      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
+      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
+      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
+      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
+      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
+      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
+      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
+      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
+    endcase
+  end
+
+  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
+           .reset(reset),
+           .en((GHRUpdateEN)),
+           .d(GHRNext),
+           .q(GHR));
+
+  // if actively updating the GHR at the time of prediction we want to us
+  // GHRNext as the lookup rather than GHR.
+
+  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
+  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
+  assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
+  assign PHTUpdateEN = InstrClassE[0] & ~StallE;
+
+  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
+  
+  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
+  ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
+    .reset(reset),
+    //.RA1(GHR[`BPRED_SIZE-1:0]),
+    .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
+    .rd1(DirPredictionF),
+    .ren1(~StallF),
+    .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
+    .wd2(NewDirPredictionE),
+    .wen2(PHTUpdateEN),
+    .bwe2(2'b11));
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
+
+endmodule // gsharePredictor
diff --git a/pipelined/src/ifu/optgshare.sv b/pipelined/src/ifu/optgshare.sv
new file mode 100644
index 000000000..d911ec03e
--- /dev/null
+++ b/pipelined/src/ifu/optgshare.sv
@@ -0,0 +1,225 @@
+///////////////////////////////////////////
+// gsharePredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module optgshare
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+   input logic             PCSrcE
+   );
+
+  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
+
+  logic [k-1:0]            GHRF;
+  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0]            GHRNextF;
+  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0]            IndexNextF, IndexF;
+  logic [k-1:0]            IndexD, IndexE, IndexM, IndexW;
+  
+  logic                    PCSrcM, PCSrcW;
+  logic [`XLEN-1:0]        PCW;
+
+  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
+
+  logic [k+4:0]            GHRNext, GHR;
+  logic                    GHRUpdateEn;
+  
+  assign GHRUpdateEn = BranchInstrF | (DirPredictionWrongE & BranchInstrE) |
+                       FlushD | FlushE | FlushM | FlushW;
+
+  // it doesn't work this way.  Instead we need to see how many branch instructions are flushed.
+  // then shift over by that amount.
+  logic                    RemoveBrW, RemoveBrM, RemoveBrE, RemoveBrD, RemoveBrF, RemoveBrNextF;
+  
+  assign RemoveBrW = '0;
+  assign RemoveBrM = BranchInstrM & FlushW;
+  assign RemoveBrE = BranchInstrE & FlushM;
+  assign RemoveBrD = BranchInstrD & FlushE;
+  assign RemoveBrF = BranchInstrF & FlushD;
+  assign RemoveBrNextF = BranchInstrF & FlushD;
+  
+  always_comb begin
+    casez ({BranchInstrF, DirPredictionWrongE, RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM}) 
+      6'b00_0000: GHRNext = GHR;  // no change
+      6'b00_0001: GHRNext = {GHR[k+4:k+1], GHR[k-1:0], 1'b0}; // RemoveBrM
+      6'b0?_0010: GHRNext = {GHR[k+4:k+2], GHR[k:0], 1'b0};   // RemoveBrE
+      6'b0?_0011: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0};   // RemoveBrE, RemoveBrM
+
+      6'b00_0100: GHRNext = {GHR[k+4:k+2], GHR[k-1:0], 2'b0}; // RemoveBrD
+      6'b00_0101: GHRNext = {GHR[k+4:k+3], GHR[k+1:0], 1'b0}; // RemoveBrD, RemoveBrM
+      6'b0?_0110: GHRNext = {GHR[k+4:k+3], GHR[k+1], GHR[k-1:0], 2'b0}; // RemoveBrD, RemoveBrE
+      6'b0?_0111: GHRNext = {GHR[k+4:k+3], GHR[k-1:0], 3'b0}; // RemoveBrD, RemoveBrE, RemoveBrM
+
+      6'b?0_1000: GHRNext = {GHR[k+2:0],   2'b0}; // RemoveBrF, 
+      6'b?0_1001: GHRNext = {GHR[k+2:k+1], GHR[k-1:0],  3'b0}; // RemoveBrF, RemoveBrM
+      6'b??_1010: GHRNext = {GHR[k+2], GHR[k:0],  3'b0}; // RemoveBrF, RemoveBrE
+      6'b??_1011: GHRNext = {GHR[k+2], GHR[k-1:0],  4'b0}; // RemoveBrF, RemoveBrE, RemoveBrM
+
+      6'b?0_1100: GHRNext = {GHR[k+1:0],  3'b0}; // RemoveBrF, RemoveBrD
+      6'b?0_1101: GHRNext = {GHR[k+1], GHR[k-1:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrM
+      6'b??_1110: GHRNext = {GHR[k:0], 4'b0}; // RemoveBrF, RemoveBrD, RemoveBrE
+      6'b??_1111: GHRNext = {GHR[k-1:0], 5'b0}; // RemoveBrF, RemoveBrD, RemoveBrE, RemoveBrM
+
+      6'b?1_0000: GHRNext = {PCSrcE, GHR[k+3:0]}; // Miss prediction, no branches to flushes
+      6'b?1_0001: GHRNext = {PCSrcE, GHR[k+3:k], GHR[k-1:1], 1'b0}; // Miss prediction, branch in Memory stage dropped
+
+      6'b?1_1100: GHRNext = {PCSrcE, GHR[k+1:0], 2'b00}; // Miss prediction, cannot have RemoveBrE
+      6'b?1_1101: GHRNext = {PCSrcE, GHR[k+1], GHR[k-1:0], 3'b0}; // Miss prediction, cannot have RemoveBrE
+      6'b10_0000: GHRNext = {DirPredictionF[1], GHR[k+4:1]};
+      6'b10_0001: GHRNext = {DirPredictionF[1], GHR[k+4:k+1], GHR[k-1:1], 1'b0};
+      6'b10_0010: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k:1], 1'b0};
+      6'b10_0011: GHRNext = {DirPredictionF[1], GHR[k+4:k+2], GHR[k-1:1], 2'b0};
+      6'b10_0100: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1:1], 1'b0};
+      6'b10_0101: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k+1], GHR[k-1:1], 2'b0};
+      6'b10_0110: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k], GHR[k-1:1], 2'b0};
+      6'b10_0111: GHRNext = {DirPredictionF[1], GHR[k+4:k+3], GHR[k-1:1], 3'b0};
+      
+      default: GHRNext = GHR;
+    endcase
+  end
+
+  flopenr  #(k+5) GHRReg(clk, reset, GHRUpdateEn,  GHRNext, GHR);
+  logic [k-1:0] GHRNextF_temp, GHRF_temp;
+  logic [k:0]   GHRD_temp, GHRE_temp, GHRM_temp, GHRW_temp;
+  logic         GHRFExtra_temp;
+
+  // these are also in the ieu controller.  should create inputs.
+  logic         InstrValidF, InstrValidD, InstrValidE, InstrValidM, InstrValidW;
+  flopenrc #(1)  InstrValidFReg(clk, reset, FlushD, ~StallF, 1'b1, InstrValidF);
+  flopenrc #(1)  InstrValidDReg(clk, reset, FlushD, ~StallD, InstrValidF, InstrValidD);
+  flopenrc #(1)  InstrValidEReg(clk, reset, FlushE, ~StallE, InstrValidD, InstrValidE);
+  flopenrc #(1)  InstrValidMReg(clk, reset, FlushM, ~StallM, InstrValidE, InstrValidM);
+  flopenrc #(1)  InstrValidWReg(clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
+
+  
+  assign GHRNextF_temp = GHRNext[k+4:5];
+  assign GHRF_temp = InstrValidF ? GHR[k+3:4] : GHRNextF_temp;
+  assign GHRFExtra_temp = InstrValidF ? 1'b0 : GHR[k+4];
+  assign GHRD_temp = InstrValidD ? GHR[k+3:3] : {GHRFExtra_temp, GHRF_temp};
+  assign GHRE_temp = InstrValidE ?  GHR[k+2:2] : GHRD_temp;
+  assign GHRM_temp = InstrValidM ? GHR[k+1:1] : GHRE_temp;
+  assign GHRW_temp = InstrValidW ? GHR[k:0] : GHRM_temp;
+  
+  
+  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
+  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
+  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
+      
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ra1(IndexNextF),
+    .rd1(TableDirPredictionF),
+    .wa2(IndexW),
+    .wd2(NewDirPredictionW),
+    .we2(BranchInstrW & ~StallW & ~FlushW),
+    .bwe2(1'b1));
+
+  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
+  //  and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
+  assign MatchW = BranchInstrW & (IndexNextF == IndexW);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
+                                   MatchD ? NewDirPredictionD :
+                                   MatchE ? NewDirPredictionE :
+                                   MatchM ? NewDirPredictionM :
+                                   NewDirPredictionW;
+
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
+  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
+  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
+
+  // PCSrc pipeline
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
+  
+  // GHR pipeline
+  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
+                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+                    GHRF;
+
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
+  
+  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
+  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+
+  assign GHRNextE = FlushE ? GHRNextM : GHRD;
+  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
+  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+
+  assign GHRNextM = FlushM ? GHRNextW : GHRE;
+  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+
+  assign GHRNextW = FlushW ? GHRW : GHRM;
+  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/src/ifu/bpred/satCounter2.sv b/pipelined/src/ifu/satCounter2.sv
similarity index 94%
rename from src/ifu/bpred/satCounter2.sv
rename to pipelined/src/ifu/satCounter2.sv
index 90cdf4f58..514a29564 100644
--- a/src/ifu/bpred/satCounter2.sv
+++ b/pipelined/src/ifu/satCounter2.sv
@@ -1,15 +1,14 @@
 ///////////////////////////////////////////
 // satCounter2.sv
 //
-// Written: Rose Thomposn
-// Email: rose@rosethompson.net
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
 // Created: February 13, 2021
 // Modified: 
 //
 // Purpose: 2 bit starting counter
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,6 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
+
 module satCounter2
   (input logic        BrDir,
    input logic [1:0]  OldState,
diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv
new file mode 100644
index 000000000..6a4e3da04
--- /dev/null
+++ b/pipelined/src/ifu/speculativeglobalhistory.sv
@@ -0,0 +1,132 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module speculativeglobalhistory
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+   input logic             PCSrcE
+   );
+
+  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
+
+  logic [k-1:0]            GHRF;
+  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0]            GHRNextF;
+  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
+  logic                    PCSrcM, PCSrcW;
+  logic [`XLEN-1:0]        PCW;
+
+  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
+  
+      
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ra1(GHRNextF),
+    .rd1(TableDirPredictionF),
+    .wa2(GHRW[k-1:0]),
+    .wd2(NewDirPredictionW),
+    .we2(BranchInstrW & ~StallW & ~FlushW),
+    .bwe2(1'b1));
+
+  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
+  //  and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF);
+  assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]);
+  assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]);
+  assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]);
+  assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
+                                   MatchD ? NewDirPredictionD :
+                                   MatchE ? NewDirPredictionE :
+                                   MatchM ? NewDirPredictionM :
+                                   NewDirPredictionW;
+
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
+  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
+  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
+
+  // PCSrc pipeline
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
+  
+  // GHR pipeline
+  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
+                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+                    GHRF;
+
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
+  
+  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
+  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+
+  assign GHRNextE = FlushE ? GHRNextM : GHRD;
+  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
+  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+
+  assign GHRNextM = FlushM ? GHRNextW : GHRE;
+  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+
+  assign GHRNextW = FlushW ? GHRW : GHRM;
+  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv
new file mode 100644
index 000000000..3dd66366e
--- /dev/null
+++ b/pipelined/src/ifu/speculativegshare.sv
@@ -0,0 +1,143 @@
+///////////////////////////////////////////
+// gsharePredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module speculativegshare
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM, StallW, 
+   input logic             FlushD, FlushE, FlushM, FlushW,
+//   input logic [`XLEN-1:0] LookUpPC,
+   output logic [1:0]      DirPredictionF, 
+   output logic            DirPredictionWrongE,
+   // update
+   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+   input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+   input logic [3:0]       WrongPredInstrClassD, 
+   input logic             PCSrcE
+   );
+
+  logic                    MatchF, MatchD, MatchE, MatchM;
+  logic                    MatchNextX, MatchXF;
+
+  logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM;
+
+  logic [k-1:0]            GHRF;
+  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
+  logic [k-1:0]            GHRNextF;
+  logic [k:-1] 			   GHRNextD, OldGHRD;
+  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0]            IndexNextF, IndexF;
+  logic [k-1:0]            IndexD, IndexE, IndexM;
+  
+  logic                    PCSrcM, PCSrcW;
+  logic [`XLEN-1:0]        PCW;
+
+  logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
+  
+  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
+  assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
+  assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
+      
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ra1(IndexNextF),
+    .rd1(TableDirPredictionF),
+    .wa2(IndexM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .bwe2(1'b1));
+
+  // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
+  // and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
+  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
+
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
+                                   MatchD ? NewDirPredictionD :
+                                   MatchE ? NewDirPredictionE :
+                                   NewDirPredictionM;
+  
+  flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
+
+  assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
+
+  // DirPrediction pipeline
+  flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
+  flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
+
+  // New prediction pipeline
+  assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]};
+  
+  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
+
+  // PCSrc pipeline
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
+  
+  // GHR pipeline
+  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
+                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+                    GHRF;
+
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
+  
+  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
+  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
+				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
+				OldGHRD[k:0];
+
+  assign GHRNextE = FlushE ? GHRNextM : GHRD;
+  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
+  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+
+  assign GHRNextM = FlushM ? GHRNextW : GHRE;
+  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+
+  assign GHRNextW = FlushW ? GHRW : GHRM;
+  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv
new file mode 100644
index 000000000..c1a1d8fac
--- /dev/null
+++ b/pipelined/src/ifu/spill.sv
@@ -0,0 +1,112 @@
+///////////////////////////////////////////
+// spill.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 28 January 2022
+// Modified: 19 January 2023
+//
+// Purpose: allows the IFU to make extra memory request if instruction address crosses
+//          cache line boundaries or if instruction address without a cache crosses
+//          XLEN/8 boundary.
+//
+// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module spill #(
+  parameter CACHE_ENABLED                     // Changes spill threshold to 1 if there is no cache
+)(input logic              clk,               
+  input logic 			   reset,
+  input logic 			   StallD, FlushD,
+  input logic [`XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
+  input logic [`XLEN-1:2]  PCPlus4F,          // PCF + 4
+  input logic [`XLEN-1:0]  PCNextF,           // The next PCF
+  input logic [31:0] 	   InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
+  input logic 			   IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
+  input logic 			   ITLBMissF,         // ITLB miss, ignore memory request
+  input logic 			   InstrDAPageFaultF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
+  output logic [`XLEN-1:0] PCNextFSpill,      // The next PCF for one of the two memory addresses of the spill
+  output logic [`XLEN-1:0] PCFSpill,          // PCF for one of the two memory addresses of the spill
+  output logic 			   SelNextSpillF,     // During the transition between the two spill operations, the IFU should stall the pipeline
+  output logic [31:0] 	   PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
+  output logic 			   CompressedF);      // The fetched instruction is compressed
+
+  // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
+  localparam integer   SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; 
+  logic [`XLEN-1:0]    PCPlus2F;         
+  logic                TakeSpillF;
+  logic                SpillF;
+  logic                SelSpillF;
+  logic 			   SpillSaveF;
+  logic [15:0]         InstrFirstHalf;
+  typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
+  (* mark_debug = "true" *)  statetype CurrState, NextState;
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // PC logic 
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  
+  // compute PCF+2 from the raw PC+4
+  mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
+  // select between PCNextF and PCF+2
+  mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~FlushD), .y(PCNextFSpill));
+  // select between PCF and PCF+2
+  mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
+
+  
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Detect spill
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
+  assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
+  
+  always_ff @(posedge clk)
+    if (reset | FlushD)    CurrState <= #1 STATE_READY;
+    else CurrState <= #1 NextState;
+
+  always_comb begin
+    case (CurrState)
+      STATE_READY: if (TakeSpillF)                NextState = STATE_SPILL;
+                   else                           NextState = STATE_READY;
+      STATE_SPILL: if(IFUCacheBusStallD | StallD) NextState = STATE_SPILL;
+                   else                           NextState = STATE_READY;
+      default:                                    NextState = STATE_READY;
+    endcase
+  end
+
+  assign SelSpillF = (CurrState == STATE_SPILL);
+  assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
+  assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
+
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Merge spilled instruction
+  ////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  // save the first 2 bytes
+  flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalf);
+
+  // merge together
+  mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalf}, SpillF, PostSpillInstrRawF);
+
+  assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
+
+endmodule
diff --git a/src/ifu/bpred/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv
similarity index 58%
rename from src/ifu/bpred/twoBitPredictor.sv
rename to pipelined/src/ifu/twoBitPredictor.sv
index 2277f8b9b..3e41dfc4e 100644
--- a/src/ifu/bpred/twoBitPredictor.sv
+++ b/pipelined/src/ifu/twoBitPredictor.sv
@@ -1,15 +1,14 @@
 ///////////////////////////////////////////
 // twoBitPredictor.sv
 //
-// Written: Rose Thomposn
-// Email: rose@rosethompson.net
+// Written: Ross Thomposn
+// Email: ross1728@gmail.com
 // Created: February 14, 2021
 // Modified: 
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,24 +26,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
-                         parameter k = 10) (
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-  input  logic [XLEN-1:0]  PCNextF, PCM,
-  output logic [1:0]       BPDirF,
-  output logic             BPDirWrongE,
-  input  logic             BranchE, BranchM,
-  input  logic             PCSrcE
-);
+`include "wally-config.vh"
+
+module twoBitPredictor
+  #(parameter int k = 10
+    )
+  (input logic             clk,
+   input logic             reset,
+   input logic             StallF, StallD, StallE, StallM,
+   input logic             FlushD, FlushE, FlushM,
+   input logic [`XLEN-1:0] PCNextF, PCM,
+   output logic [1:0]      DirPredictionF,
+   output logic            DirPredictionWrongE,
+   input logic             BranchInstrE, BranchInstrM,
+   input logic             PCSrcE
+   );
 
   logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              PredictionMemory;
   logic                    DoForwarding, DoForwardingF;
-  logic [1:0]              BPDirD, BPDirE;
-  logic [1:0]              NewBPDirE, NewBPDirM;
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
   // hashing function for indexing the PC
   // We have k bits to index, but XLEN bits as the input.
@@ -54,22 +56,22 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
   assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};  
 
 
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) BHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+  ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
-    .rd1(BPDirF),
+    .rd1(DirPredictionF),
     .wa2(IndexM),
-    .wd2(NewBPDirM),
-    .we2(BranchM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallM & ~FlushM),
     .bwe2(1'b1));
   
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
 
-  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
   
 
 endmodule
diff --git a/pipelined/src/lsu/amoalu.sv b/pipelined/src/lsu/amoalu.sv
new file mode 100644
index 000000000..eda3576be
--- /dev/null
+++ b/pipelined/src/lsu/amoalu.sv
@@ -0,0 +1,77 @@
+///////////////////////////////////////////
+// amoalu.sv
+//
+// Written: David_Harris@hmc.edu
+// Created: 10 March 2021
+// Modified: 18 January 2023 
+//
+// Purpose: Performs AMO operations
+// 
+// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module amoalu (
+  input  logic [`XLEN-1:0] ReadDataM,    // LSU's ReadData
+  input  logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData
+  input  logic [6:0]       LSUFunct7M,   // ALU Operation
+  input  logic [2:0]       LSUFunct3M,   // Memoy access width
+  output logic [`XLEN-1:0] AMOResult     // ALU output
+);
+
+  logic [`XLEN-1:0] a, b, y;
+
+  // *** see how synthesis generates this and optimize more structurally if necessary to share hardware
+  // a single carry chain should be shared for + and the four min/max
+  // and the same mux can be used to select b for swap.
+  always_comb 
+    case (LSUFunct7M[6:2])
+      5'b00001: y = b;                                      // amoswap
+      5'b00000: y = a + b;                                  // amoadd
+      5'b00100: y = a ^ b;                                  // amoxor
+      5'b01100: y = a & b;                                  // amoand
+      5'b01000: y = a | b;                                  // amoor
+      5'b10000: y = ($signed(a) < $signed(b)) ? a : b;      // amomin
+      5'b10100: y = ($signed(a) >= $signed(b)) ? a : b;     // amomax
+      5'b11000: y = ($unsigned(a) < $unsigned(b)) ? a : b;  // amominu
+      5'b11100: y = ($unsigned(a) >= $unsigned(b)) ? a : b; // amomaxu
+      default:  y = `XLEN'bx;                               // undefined; *** could change to b for efficiency
+    endcase
+
+  // sign extend if necessary
+  if (`XLEN == 32) begin:sext
+    assign a = ReadDataM;
+    assign b = IHWriteDataM;
+    assign AMOResult = y;
+  end else begin:sext // `XLEN = 64
+    always_comb 
+      if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations
+        a = {{32{ReadDataM[31]}}, ReadDataM[31:0]};
+        b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]};
+        AMOResult = {{32{y[31]}}, y[31:0]};
+      end else begin
+        a = ReadDataM;
+        b = IHWriteDataM;
+        AMOResult = y;
+      end
+  end
+endmodule
+
diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv
new file mode 100644
index 000000000..fc9ede119
--- /dev/null
+++ b/pipelined/src/lsu/atomic.sv
@@ -0,0 +1,59 @@
+///////////////////////////////////////////
+// atomic.sv
+//
+// Written: Ross Thompson ross1728@gmail.com
+// Created: 31 January 2022
+// Modified: 18 January 2023
+//
+// Purpose: Wrapper for amoalu and lrsc
+//
+// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module atomic (
+  input logic                clk,
+  input logic                reset, 
+  input logic                StallW,
+  input logic [`XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [`XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
+  input logic [`PA_BITS-1:0] PAdrM,          // Physical memory address
+  input logic [6:0]          LSUFunct7M,     // AMO alu operation gated by HPTW
+  input logic [2:0]          LSUFunct3M,     // IEU or HPTW memory operation size
+  input logic [1:0]          LSUAtomicM,     // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation
+  input logic [1:0]          PreLSURWM,      // IEU or HPTW Read/Write signal
+  input logic                IgnoreRequest,  // On FlushM or TLB miss ignore memory operation
+  output logic [`XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
+  output logic               SquashSCW,      // Store conditional failed disable write to GPR
+  output logic [1:0]         LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
+);
+
+  logic [`XLEN-1:0]          AMOResult;
+  logic                      MemReadM;
+
+  amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult);
+
+  mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
+  assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
+
+  lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+
+endmodule  
diff --git a/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv
similarity index 53%
rename from src/lsu/dtim.sv
rename to pipelined/src/lsu/dtim.sv
index f6530edc8..4a5cba1f2 100644
--- a/src/lsu/dtim.sv
+++ b/pipelined/src/lsu/dtim.sv
@@ -1,16 +1,15 @@
 ///////////////////////////////////////////
 // dtim.sv
 //
-// Written: Rose Thompson rose@rosethompson.net 
+// Written: Ross Thompson ross1728@gmail.com 
 // Created: 30 January 2022
 // Modified: 18 January 2023
 //
 // Purpose: tightly integrated memory into the LSU.
 //
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,28 +27,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module dtim import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk, reset,
-  input  logic                 FlushW,        
-  input  logic                 ce,            // Chip Enable.  0: Holds ReadDataWordM
-  input  logic [1:0]           MemRWM,        // Read/Write control
-  input  logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
-  input  logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
-  input  logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
-  output logic [P.LLEN-1:0]    ReadDataWordM  // Read data before subword selection
+`include "wally-config.vh"
+
+module dtim(
+  input logic 				 clk, 
+  input logic 				 FlushW,        
+  input logic 				 ce,            // Chip Enable.  0: Holds ReadDataWordM
+  input logic [1:0] 		 MemRWM,        // Read/Write control
+  input logic [`PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
+  input logic [`LLEN-1:0] 	 WriteDataM,    // Write data from IEU
+  input logic [`LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
+  output logic [`LLEN-1:0] 	 ReadDataWordM  // Read data before subword selection
   );
 
-  logic                       we;
+  logic                      we;
  
-  localparam LLENBYTES  = P.LLEN/8;
-  // verilator  lint_off WIDTH 
-  localparam DEPTH      = P.DTIM_RANGE/LLENBYTES;
-  // verilator  lint_on WIDTH 
-  localparam ADDR_WDITH = $clog2(DEPTH);
-  localparam OFFSET     = $clog2(LLENBYTES);
+  localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
+  localparam OFFSET     = $clog2(`LLEN/8);
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(DEPTH), .WIDTH(P.LLEN)) 
+  ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
+  
diff --git a/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv
similarity index 94%
rename from src/lsu/endianswap.sv
rename to pipelined/src/lsu/endianswap.sv
index 3634e2322..97846d97e 100644
--- a/src/lsu/endianswap.sv
+++ b/pipelined/src/lsu/endianswap.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: Swap byte order for Big-Endian accesses
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,7 +27,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module endianswap #(parameter LEN) (
+`include "wally-config.vh"
+
+module endianswap #(parameter LEN=`XLEN) (
   input  logic            BigEndianM,
   input  logic [LEN-1:0]  a,
   output logic [LEN-1:0]  y
diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv
new file mode 100644
index 000000000..7edae6b81
--- /dev/null
+++ b/pipelined/src/lsu/lrsc.sv
@@ -0,0 +1,65 @@
+///////////////////////////////////////////
+// lrsc.sv
+//
+// Written: David_Harris@hmc.edu
+// Created: 17 July 2021
+// Modified: 18 January 2023
+//
+// Purpose: Load Reserved / Store Conditional unit
+//          Track the reservation and squash the store if it fails
+//
+// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module lrsc(
+  input  logic                clk, reset,
+  input  logic                StallW,
+  input  logic                MemReadM,
+  input  logic [1:0]          PreLSURWM,
+  output logic [1:0]          LSURWM,
+  input  logic [1:0] 	        LSUAtomicM,
+  input  logic [`PA_BITS-1:0] PAdrM,  // from mmu to dcache
+  output logic                SquashSCW
+);
+
+  // Handle atomic load reserved / store conditional
+  logic [`PA_BITS-1:2] 			  ReservationPAdrW;
+  logic 						          ReservationValidM, ReservationValidW; 
+  logic 						          lrM, scM, WriteAdrMatchM;
+  logic 						          SquashSCM;
+
+  assign lrM = MemReadM & LSUAtomicM[0];
+  assign scM = PreLSURWM[0] & LSUAtomicM[0]; 
+  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
+  assign SquashSCM = scM & ~WriteAdrMatchM;
+  assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
+  always_comb begin // ReservationValidM (next value of valid reservation)
+    if (lrM) ReservationValidM = 1;  // set valid on load reserve
+	// if we implement multiple harts invalidate reservation if another hart stores to this reservation.
+    else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
+    else ReservationValidM = ReservationValidW; // otherwise don't change valid
+  end
+  
+  flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
+  flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
+  flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
+endmodule
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
new file mode 100644
index 000000000..d84334a85
--- /dev/null
+++ b/pipelined/src/lsu/lsu.sv
@@ -0,0 +1,365 @@
+/////////////////////////////////////////////////////////////////////////////////////////////////////////
+// lsu.sv
+//
+// Written: David_Harris@hmc.edu, ross1728@gmail.com
+// Created: 9 January 2021
+// Modified: 11 January 2023 
+//
+// Purpose: Load/Store Unit 
+//          HPTW, DMMU, data cache, interface to external bus
+//          Atomic, Endian swap, and subword read/write logic
+//  
+// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+/////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module lsu (
+  input  logic             clk, reset,
+  input  logic             StallM, FlushM, StallW, FlushW,
+  output logic             LSUStallM,                               // LSU stalls pipeline during a multicycle operation
+  // connected to cpu (controls)
+  input  logic [1:0]       MemRWM,                                  // Read/Write control
+  input  logic [2:0]       Funct3M,                                 // Size of memory operation
+  input  logic [6:0]       Funct7M,                                 // Atomic memory operation function
+  input  logic [1:0]       AtomicM,                                 // Atomic memory operation
+  input  logic             FlushDCacheM,                            // Flush D cache to next level of memory
+  output logic             CommittedM,                              // Delay interrupts while memory operation in flight
+  output logic             SquashSCW,                               // Store conditional failed disable write to GPR
+  output logic             DCacheMiss,                              // D cache miss for performance counters
+  output logic             DCacheAccess,                            // D cache memory access for performance counters
+  // address and write data
+  input  logic [`XLEN-1:0] IEUAdrE,                                 // Execution stage memory address
+  (* mark_debug = "true" *) output logic [`XLEN-1:0] IEUAdrM,       // Memory stage memory address
+  (* mark_debug = "true" *) input logic [`XLEN-1:0] WriteDataM,     // Write data from IEU
+  output logic [`LLEN-1:0] ReadDataW,                               // Read data to IEU or FPU
+  // cpu privilege
+  input  logic [1:0]       PrivilegeModeW,                          // Current privilege mode
+  input  logic             BigEndianM,                              // Swap byte order to big endian
+  input  logic             sfencevmaM,                              // Virtual memory address fence, invalidate TLB entries
+  // fpu
+  input  logic [`FLEN-1:0] FWriteDataM,                             // Write data from FPU
+  input  logic             FpLoadStoreM,                            // Selects FPU as store for write data
+  // faults
+  output logic             LoadPageFaultM, StoreAmoPageFaultM,      // Page fault exceptions
+  output logic             LoadMisalignedFaultM,                    // Load address misaligned fault
+  output logic             LoadAccessFaultM,                        // Load access fault (PMA)
+  output logic             HPTWInstrAccessFaultM,                   // HPTW generated access fault during instruction fetch
+  // cpu hazard unit (trap)
+  output logic             StoreAmoMisalignedFaultM,                // Store or AMO address misaligned fault
+  output logic             StoreAmoAccessFaultM,                    // Store or AMO access fault
+          // connect to ahb
+  (* mark_debug = "true" *)   output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
+  (* mark_debug = "true" *)   input logic [`XLEN-1:0] HRDATA,       // Bus read data from LSU to EBU
+  (* mark_debug = "true" *)   output logic [`XLEN-1:0] LSUHWDATA,   // Bus write data from LSU to EBU
+  (* mark_debug = "true" *)   input logic LSUHREADY,                // Bus ready from LSU to EBU
+  (* mark_debug = "true" *)   output logic LSUHWRITE,               // Bus write operation from LSU to EBU
+  (* mark_debug = "true" *)   output logic [2:0] LSUHSIZE,          // Bus operation size from LSU to EBU
+  (* mark_debug = "true" *)   output logic [2:0] LSUHBURST,         // Bus burst from LSU to EBU
+  (* mark_debug = "true" *)   output logic [1:0] LSUHTRANS,         // Bus transaction type from LSU to EBU
+  (* mark_debug = "true" *)   output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
+          // page table walker
+  input  logic [`XLEN-1:0] SATP_REGW,                               // SATP (supervisor address translation and protection) CSR
+  input  logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,     // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
+  input  logic [1:0]       STATUS_MPP,                              // Machine previous privilege mode
+  input  logic [`XLEN-1:0] PCF,                                     // Fetch PC 
+  input  logic             ITLBMissF,                               // ITLB miss causes HPTW (hardware pagetable walker) walk
+  input  logic             InstrDAPageFaultF,                       // ITLB hit needs to update dirty or access bits
+  output logic [`XLEN-1:0] PTE,                                     // Page table entry write to ITLB
+  output logic [1:0]       PageType,                                // Type of page table entry to write to ITLB
+  output logic             ITLBWriteF,                              // Write PTE to ITLB
+  output logic             SelHPTW,                                 // During a HPTW walk the effective privilege mode becomes S_MODE
+  input var logic [7:0]    PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
+  input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]  // PMP address from privileged unit
+);
+
+  logic [`XLEN+1:0]         IEUAdrExtM;                              // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [`XLEN+1:0]         IEUAdrExtE;                              // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
+  logic [`PA_BITS-1:0]      PAdrM;                                   // Physical memory address
+  (* mark_debug = "true" *)  logic [`XLEN+1:0] IHAdrM;               // Either IEU or HPTW memory address
+
+  logic [1:0] 				PreLSURWM;                               // IEU or HPTW Read/Write signal
+  logic [1:0] 				LSURWM;                                  // IEU or HPTW Read/Write signal gated by LR/SC
+  logic [2:0]               LSUFunct3M;                              // IEU or HPTW memory operation size
+  logic [6:0]               LSUFunct7M;                              // AMO function gated by HPTW
+  logic [1:0]               LSUAtomicM;                              // AMO signal gated by HPTW
+
+  logic                     GatedStallW;                             // Hazard unit StallW gated when SelHPTW = 1
+ 
+  logic                     DCacheStallM;                            // D$ busy with multicycle operation
+  logic                     BusStall;                                // Bus interface busy with multicycle operation
+  logic                     HPTWStall;                               // HPTW busy with multicycle operation
+
+  logic                     CacheableM;                              // PMA indicates memory address is cacheable
+  logic                     BusCommittedM;                           // Bus memory operation in flight, delay interrupts
+  logic 					DCacheCommittedM;                        // D$ memory operation started, delay interrupts
+
+  logic [`LLEN-1:0] 		DTIMReadDataWordM;                       // DTIM read data
+  logic [`LLEN-1:0] 		DCacheReadDataWordM;                     // D$ read data
+  logic [`LLEN-1:0] 		ReadDataWordMuxM;                        // DTIM or D$ read data
+  logic [`LLEN-1:0] 		LittleEndianReadDataWordM;               // Endian-swapped read data
+  logic [`LLEN-1:0] 		ReadDataWordM;                           // Read data before subword selection
+  logic [`LLEN-1:0]         ReadDataM;                               // Final read data
+
+  logic [`XLEN-1:0] 		IHWriteDataM;                            // IEU or HPTW write data
+  logic [`XLEN-1:0] 		IMAWriteDataM;                           // IEU, HPTW, or AMO write data
+  logic [`LLEN-1:0]         IMAFWriteDataM;                          // IEU, HPTW, AMO, or FPU write data
+  logic [`LLEN-1:0] 		LittleEndianWriteDataM;                  // Ending-swapped write data 
+  logic [`LLEN-1:0] 		LSUWriteDataM;                           // Final write data
+  logic [(`LLEN-1)/8:0]     ByteMaskM;                               // Selects which bytes within a word to write
+
+  logic                     DTLBMissM;                               // DTLB miss causes HPTW walk
+  logic                     DTLBWriteM;                              // Writes PTE and PageType to DTLB
+  logic                     DataDAPageFaultM;                        // DTLB hit needs to update dirty or access bits
+  logic                     LSULoadAccessFaultM;                     // Load acces fault
+  logic 					LSUStoreAmoAccessFaultM;                 // Store access fault
+  logic                     IgnoreRequestTLB;                        // On either ITLB or DTLB miss, ignore miss so HPTW can handle
+  logic 					IgnoreRequest;                           // On FlushM or TLB miss ignore memory operation
+  logic                     SelDTIM;                                 // Select DTIM rather than bus or D$
+
+  
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Pipeline for IEUAdr E to M
+  // Zero-extend address to 34 bits for XLEN=32
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
+  assign IEUAdrExtM = {2'b00, IEUAdrM}; 
+  assign IEUAdrExtE = {2'b00, IEUAdrE};
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // HPTW (only needed if VM supported)
+  // MMU include PMP and is needed if any privileged supported
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
+    hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
+      .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
+      .FlushW, .DCacheStallM, .SATP_REGW, .PCF,
+      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
+      .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
+      .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
+      .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
+      .IHAdrM, .HPTWStall, .SelHPTW,
+      .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, 
+      .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM);
+  end else begin // No HPTW, so signals are not multiplexed
+    assign PreLSURWM = MemRWM; 
+    assign IHAdrM = IEUAdrExtM;
+    assign LSUFunct3M = Funct3M;
+	assign LSUFunct7M = Funct7M; 
+	assign LSUAtomicM = AtomicM;
+    assign IHWriteDataM = WriteDataM;
+    assign LoadAccessFaultM = LSULoadAccessFaultM;
+    assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;   
+    assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
+    assign HPTWInstrAccessFaultM = '0;
+   end
+
+  // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
+  // CommittedM is 1 after the first cycle and until the last cycle.  Partially completed memory 
+  // operations delay interrupts until the next instruction by suppressing pending interrupts in 
+  // the trap module.
+  assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
+  assign GatedStallW = StallW & ~SelHPTW;
+  assign LSUStallM = DCacheStallM | HPTWStall | BusStall;
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // MMU and misalignment fault logic required if privileged unit exists
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  if(`ZICSR_SUPPORTED == 1) begin : dmmu
+    logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
+    assign DisableTranslation = SelHPTW | FlushDCacheM;
+    mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
+    dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+      .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
+      .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
+      .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), 
+      .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), 
+      .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM, 
+	  .StoreAmoPageFaultM,
+      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,   // *** these faults need to be supressed during hptw.
+      .DAPageFault(DataDAPageFaultM),
+      .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), 
+      .WriteAccessM(PreLSURWM[0]), .ReadAccessM(PreLSURWM[1]),
+      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
+
+  end else begin  // No MMU, so no PMA/page faults and no address translation
+    assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
+    assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
+    assign PAdrM = IHAdrM[`PA_BITS-1:0];
+    assign CacheableM = 1'b1;
+    assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM.  If there is 
+    // a bus then this is always 0. Cannot have both without PMA.
+  end
+  
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Memory System (options)
+  // 1. DTIM
+  // 2. DTIM and bus
+  // 3. Bus
+  // 4. Cache and bus
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  // Pause IEU memory request if TLB miss.  After TLB fill, replay request.
+  // Discard memory request on pipeline flush
+  assign IgnoreRequest = IgnoreRequestTLB | FlushW;
+  
+  if (`DTIM_SUPPORTED) begin : dtim
+    logic [`PA_BITS-1:0] DTIMAdr;
+    logic [1:0]          DTIMMemRWM;
+    
+    // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
+	mux2 #(`PA_BITS) DTIMAdrMux(IEUAdrExtE[`PA_BITS-1:0], IEUAdrExtM[`PA_BITS-1:0], MemRWM[0], DTIMAdr);
+    assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
+    // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
+    // **** create config to support DTIM with floating point.
+    dtim dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
+              .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
+              .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
+  end else begin
+  end
+  if (`BUS) begin : bus              
+    if(`DCACHE) begin : dcache
+      localparam integer   LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN;             // Number of LLEN words in cacheline
+      localparam integer   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                     // Log2 of ^
+      localparam integer   BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW;                 // Number of AHBW words (beats) in cacheline
+      localparam integer   AHBWLOGBWPL = $clog2(BEATSPERLINE);                         // Log2 of ^
+      localparam integer   LINELEN = `DCACHE_LINELENINBITS;                            // Number of bits in cacheline
+      localparam integer   LLENPOVERAHBW = `LLEN / `AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
+
+      logic [LINELEN-1:0]  FetchBuffer;                                                // Temporary buffer to hold partially fetched cacheline
+      logic [`PA_BITS-1:0] DCacheBusAdr;                                               // Cacheline address to fetch or writeback.
+      logic [AHBWLOGBWPL-1:0]  BeatCount;                                              // Position within a cacheline.  ahbcacheinterface to cache
+      logic                DCacheBusAck;                                               // ahbcacheinterface completed fetch or writeback
+      logic                SelBusBeat;                                                 // ahbcacheinterface selects postion in cacheline with BeatCount
+      logic [1:0] 		   CacheBusRW;                                                 // Cache sends request to ahbcacheinterface
+	  logic [1:0] 		   BusRW;                                                      // Uncached bus memory access
+      logic                CacheableOrFlushCacheM;                                     // Memory address is cacheable or operation is a cache flush
+      logic [1:0] 		   CacheRWM;                                                   // Cache read (10), write (01), AMO (11)
+	  logic [1:0] 		   CacheAtomicM;                                               // Cache AMO
+      
+      assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
+      assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
+      assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
+      assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
+      
+      cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
+              .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
+        .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
+        .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), 
+        .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
+        .CacheWriteData(LSUWriteDataM), .SelHPTW,
+        .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
+        .CacheCommitted(DCacheCommittedM), 
+        .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), 
+        .FetchBuffer, .CacheBusRW, 
+        .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
+
+      ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW)) ahbcacheinterface(
+        .HCLK(clk), .HRESETn(~reset), .Flush(FlushW),
+        .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
+        .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
+        .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM),
+        .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM,
+        .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
+        .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
+        .BusStall, .BusCommitted(BusCommittedM));
+
+	  // Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
+	  // Uncache bus access may be smaller width than LLEN.  Duplicate LLENPOVERAHBW times.
+      // *** DTIMReadDataWordM should be increased to LLEN.
+      // pma should generate exception for LLEN read to periph.
+      mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
+                                    .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
+                                    .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
+    end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
+      logic [1:0] BusRW;                    // Non-DTIM memory access, ignore cacheableM
+      logic [`XLEN-1:0] FetchBuffer;
+      assign BusRW = ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
+      
+      assign LSUHADDR = PAdrM;
+      assign LSUHSIZE = LSUFunct3M;
+
+      ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
+        .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
+        .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM),
+        .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
+
+	  // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
+      if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM);
+      else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0];
+      assign LSUHBURST = 3'b0;
+      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
+ end
+  end else begin: nobus // block: bus, only DTIM
+    assign LSUHWDATA = '0; 
+    assign ReadDataWordMuxM = DTIMReadDataWordM;
+    assign {BusStall, BusCommittedM} = '0;   
+    assign {DCacheMiss, DCacheAccess} = '0;
+    assign {DCacheStallM, DCacheCommittedM} = '0;
+  end
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Atomic operations
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  if (`A_SUPPORTED) begin:atomic
+    atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .IHWriteDataM, .PAdrM, 
+      .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
+      .IMAWriteDataM, .SquashSCW, .LSURWM);
+  end else begin:lrsc
+    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM;
+  end
+
+  if (`F_SUPPORTED) 
+    mux2 #(`LLEN) datamux({{{`LLEN-`XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
+  else assign IMAFWriteDataM = IMAWriteDataM;
+  
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Subword Accesses
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  subwordread subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
+		.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
+  subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
+
+  // Compute byte masks
+  swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // MW Pipeline Register
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
+
+  /////////////////////////////////////////////////////////////////////////////////////////////
+  // Big Endian Byte Swapper
+  //  hart works little-endian internally
+  //  swap the bytes when read from big-endian memory
+  /////////////////////////////////////////////////////////////////////////////////////////////
+
+  if (`BIGENDIAN_SUPPORTED) begin:endian
+    endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
+    endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
+  end else begin
+    assign LSUWriteDataM = LittleEndianWriteDataM;
+    assign LittleEndianReadDataWordM = ReadDataWordMuxM;
+  end
+
+endmodule
diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv
new file mode 100644
index 000000000..784db694d
--- /dev/null
+++ b/pipelined/src/lsu/subwordread.sv
@@ -0,0 +1,125 @@
+///////////////////////////////////////////
+// subwordread.sv
+//
+// Written: David_Harris@hmc.edu 
+// Created: 9 January 2021
+// Modified: 18 January 2023 
+//
+// Purpose: Extract subwords and sign extend for reads
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module subwordread 
+  (
+   input logic [`LLEN-1:0] 	ReadDataWordMuxM,
+   input logic [2:0] 		PAdrM,
+   input logic [2:0] 		Funct3M,
+   input logic              FpLoadStoreM, 
+   input logic              BigEndianM, 
+   output logic [`LLEN-1:0] ReadDataM
+);
+
+  logic [7:0] 				ByteM; 
+  logic [15:0] 				HalfwordM;
+  logic [2:0]               PAdrSwap;
+  // Funct3M[2] is the unsigned bit. mask upper bits.
+  // Funct3M[1:0] is the size of the memory access.
+  assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
+
+  if (`LLEN == 64) begin:swrmux
+    // ByteMe mux
+    always_comb
+    case(PAdrSwap[2:0])
+      3'b000: ByteM = ReadDataWordMuxM[7:0];
+      3'b001: ByteM = ReadDataWordMuxM[15:8];
+      3'b010: ByteM = ReadDataWordMuxM[23:16];
+      3'b011: ByteM = ReadDataWordMuxM[31:24];
+      3'b100: ByteM = ReadDataWordMuxM[39:32];
+      3'b101: ByteM = ReadDataWordMuxM[47:40];
+      3'b110: ByteM = ReadDataWordMuxM[55:48];
+      3'b111: ByteM = ReadDataWordMuxM[63:56];
+    endcase
+  
+    // halfword mux
+    always_comb
+    case(PAdrSwap[2:1])
+      2'b00: HalfwordM = ReadDataWordMuxM[15:0];
+      2'b01: HalfwordM = ReadDataWordMuxM[31:16];
+      2'b10: HalfwordM = ReadDataWordMuxM[47:32];
+      2'b11: HalfwordM = ReadDataWordMuxM[63:48];
+    endcase
+    
+    logic [31:0] WordM;
+    
+    always_comb
+      case(PAdrSwap[2])
+        1'b0: WordM = ReadDataWordMuxM[31:0];
+        1'b1: WordM = ReadDataWordMuxM[63:32];
+      endcase
+
+    logic [63:0] DblWordM;
+    assign DblWordM = ReadDataWordMuxM[63:0];
+
+    // sign extension/ NaN boxing
+    always_comb
+    case(Funct3M)
+      3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                              // lb
+      3'b001:  ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
+      3'b010:  ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};         // lw/flw
+      3'b011:  ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};   // ld/fld
+      3'b100:  ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq
+      3'b101:  ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]};   // lhu
+      3'b110:  ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]};       // lwu
+      default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
+    endcase
+
+  end else begin:swrmux // 32-bit
+    // byte mux
+    always_comb
+    case(PAdrSwap[1:0])
+      2'b00: ByteM = ReadDataWordMuxM[7:0];
+      2'b01: ByteM = ReadDataWordMuxM[15:8];
+      2'b10: ByteM = ReadDataWordMuxM[23:16];
+      2'b11: ByteM = ReadDataWordMuxM[31:24];
+    endcase
+  
+    // halfword mux
+    always_comb
+    case(PAdrSwap[1])
+      1'b0: HalfwordM = ReadDataWordMuxM[15:0];
+      1'b1: HalfwordM = ReadDataWordMuxM[31:16];
+    endcase
+
+    // sign extension
+    always_comb
+    case(Funct3M)
+      3'b000:  ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM};                              // lb
+      3'b001:  ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
+      3'b010:  ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]};         // lw/flw
+      3'b011:  ReadDataM = ReadDataWordMuxM;                      // fld
+      3'b100:  ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]};         // lbu
+      3'b101:  ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]};   // lhu
+      default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
+    endcase
+  end
+endmodule
diff --git a/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv
similarity index 74%
rename from src/lsu/subwordwrite.sv
rename to pipelined/src/lsu/subwordwrite.sv
index 4ae097cc3..ee26b78fd 100644
--- a/src/lsu/subwordwrite.sv
+++ b/pipelined/src/lsu/subwordwrite.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: Masking and muxing for subword writes
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,15 +27,16 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module subwordwrite #(parameter LLEN) (
-  input logic  [2:0]        LSUFunct3M,
-  input logic  [LLEN-1:0]   IMAFWriteDataM,
-  output logic [LLEN-1:0]   LittleEndianWriteDataM
+`include "wally-config.vh"
+
+module subwordwrite (
+  input logic [2:0]          LSUFunct3M,
+  input logic [`LLEN-1:0]    IMAFWriteDataM,
+  output logic [`LLEN-1:0]   LittleEndianWriteDataM
 );
 
   // Replicate data for subword writes
-
-  if (LLEN == 128) begin:sww
+  if (`LLEN == 128) begin:sww
     always_comb 
       case(LSUFunct3M[2:0])
         3'b000:  LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
@@ -45,21 +45,21 @@ module subwordwrite #(parameter LLEN) (
         3'b011:  LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
         default: LittleEndianWriteDataM = IMAFWriteDataM;            // sq
       endcase
-  end else if (LLEN == 64) begin:sww
+  end else if (`LLEN == 64) begin:sww
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}};   // sb
-        2'b01:  LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}};  // sh
-        2'b10:  LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}};  // sw
-        2'b11:  LittleEndianWriteDataM = IMAFWriteDataM;             // sd
+        2'b00:  LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}};  // sb
+        2'b01:  LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}}; // sh
+        2'b10:  LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}}; // sw
+        2'b11:  LittleEndianWriteDataM = IMAFWriteDataM;            // sd
       endcase
   end else begin:sww // 32-bit
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:   LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}};  // sb
-        2'b01:   LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh
-        2'b10:   LittleEndianWriteDataM = IMAFWriteDataM;            // sw
-        default: LittleEndianWriteDataM = IMAFWriteDataM;            // shouldn't happen
+        2'b00:  LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}};  // sb
+        2'b01:  LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh
+        2'b10:  LittleEndianWriteDataM = IMAFWriteDataM;            // sw
+        default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen
       endcase
   end
 endmodule
diff --git a/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv
similarity index 67%
rename from src/lsu/swbytemask.sv
rename to pipelined/src/lsu/swbytemask.sv
index cbe4070cc..17eedd4c4 100644
--- a/src/lsu/swbytemask.sv
+++ b/pipelined/src/lsu/swbytemask.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: On-chip RAM, external to core
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,30 +27,22 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module swbytemask #(parameter WORDLEN, EXTEND = 0)(
-  input logic  [2:0]                   Size,
-  input logic  [$clog2(WORDLEN/8)-1:0] Adr,
-  output logic [WORDLEN/8-1:0]         ByteMask,
-  output logic [WORDLEN/8-1:0]         ByteMaskExtended
-);
+`include "wally-config.vh"
 
-  if(EXTEND) begin
-    logic [WORDLEN*2/8-1:0]              ExtendedByteMask;
-    // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion    
-    assign ExtendedByteMask = (('d2**('d2**Size))-'d1) << Adr;
-    assign ByteMask = ExtendedByteMask[WORDLEN/8-1:0];
-    assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
-  end else begin    
-    assign ByteMask = (('d2**('d2**Size))-'d1) << Adr;
-    assign ByteMaskExtended = '0;
-  end
+module swbytemask #(parameter WORDLEN = `XLEN)(
+  input logic [2:0]              Size,
+  input logic [$clog2(WORDLEN/8)-1:0] Adr,
+  output logic [WORDLEN/8-1:0]   ByteMask
+);
+  
+  assign ByteMask = ((2**(2**Size))-1) << Adr;
 
 /* Equivalent to the following
 
-  if(WORDLEN == 64) begin
+  if(`XLEN == 64) begin
     always_comb begin
       case(Size[1:0])
-        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1'b1; end // sb
+        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
         2'b01: case (Adr[2:1])
                   2'b00: ByteMask = 8'b0000_0011;
                   2'b01: ByteMask = 8'b0000_1100;
@@ -66,7 +57,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
   end else begin
     always_comb begin
       case(Size[1:0])
-        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1'b1; end // sb
+        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
         2'b01: if (Adr[1]) ByteMask = 4'b1100;
                else        ByteMask = 4'b0011;
         2'b10: ByteMask = 4'b1111;
diff --git a/pipelined/src/mdu/intdivrestoring.sv b/pipelined/src/mdu/intdivrestoring.sv
new file mode 100644
index 000000000..0d95233ca
--- /dev/null
+++ b/pipelined/src/mdu/intdivrestoring.sv
@@ -0,0 +1,145 @@
+///////////////////////////////////////////
+// intdivrestoring.sv
+//
+// Written: David_Harris@hmc.edu 12 September 2021
+// Modified: 
+//
+// Purpose: Restoring integer division using a shift register and subtractor
+// 
+// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module intdivrestoring(
+  input  logic             clk,
+  input  logic             reset,
+  input  logic             StallM,
+  input  logic             FlushE,
+  input  logic             IntDivE,                       // integer division/remainder instruction of any type
+  input  logic             DivSignedE,                    // signed division 
+  input  logic             W64E,                          // W-type instructions (divw, divuw, remw, remuw)
+	input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
+  output logic             DivBusyE,                      // Divide is busy - stall pipeline
+  output logic [`XLEN-1:0] QuotM, RemM                    // Quotient and remainder outputs
+ );
+
+  localparam STEPBITS = $clog2(`XLEN/`IDIV_BITSPERCYCLE); // Number of steps
+
+  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;  // division FSM state
+  statetype state;
+
+  logic [`XLEN-1:0]   W[`IDIV_BITSPERCYCLE:0];            // Residual for each of k steps
+  logic [`XLEN-1:0]   XQ[`IDIV_BITSPERCYCLE:0];           // dividend/quotient for each of k steps
+  logic [`XLEN-1:0]   WNext, XQNext;                      // initialized W and XQ going into registers
+  logic [`XLEN-1:0]   DinE, XinE;                         // divisor & dividend, possibly truncated to 32 bits
+  logic [`XLEN-1:0]   DnE;                                // DnE = ~DinE
+  logic [`XLEN-1:0]   DAbsBE;                             // absolute value of D
+  logic [`XLEN-1:0]   DAbsB;                              // registered absolute value of D, constant during division
+  logic [`XLEN-1:0]   XnE;                                // DXnE = ~XinE
+  logic [`XLEN-1:0]   XInitE;                             // |X|, or original X for divide by 0
+  logic [`XLEN-1:0]   WnM, XQnM;                          // negated residual W and quotient XQ for postprocessing sign correction
+  logic [STEPBITS:0]  step;                               // division step
+  logic               Div0E, Div0M;                       // divide by 0
+  logic               DivStartE;                          // start integer division
+  logic               SignXE, SignDE;                     // sign of dividend and divisor
+  logic               NegQE, NegWM, NegQM;                // negate quotient or residual during postprocessing
+ 
+  //////////////////////////////
+  // Execute Stage: prepare for division calculation with control logic, W logic and absolute values, initialize W and XQ
+  //////////////////////////////
+
+  // Divider control signals
+  assign DivStartE = IntDivE & (state == IDLE) & ~StallM; 
+  assign DivBusyE = (state == BUSY) | DivStartE;
+
+  // Handle sign extension for W-type instructions
+  if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions
+    mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
+    mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
+  end else begin // RV32 has no W-type instructions
+    assign XinE = ForwardedSrcAE;
+    assign DinE = ForwardedSrcBE;	    
+    end   
+
+  // Extract sign bits and check fo division by zero
+  assign SignDE = DivSignedE & DinE[`XLEN-1]; 
+  assign SignXE = DivSignedE & XinE[`XLEN-1];
+  assign NegQE = SignDE ^ SignXE;
+  assign Div0E = (DinE == 0);
+
+  // Take absolute value for signed operations, and negate D to handle subtraction in divider stages
+  neg #(`XLEN) negd(DinE, DnE);
+  mux2 #(`XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE);  // take absolute value for signed operations, and negate for subtraction setp
+  neg #(`XLEN) negx(XinE, XnE);
+  mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
+
+  //////////////////////////////
+  // Division Iterations (effectively stalled execute stage, no suffix)
+  //////////////////////////////
+
+  // initialization multiplexers on first cycle of operation
+  mux2 #(`XLEN) wmux(W[`IDIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext);
+  mux2 #(`XLEN) xmux(XQ[`IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
+
+  // registers before division steps
+  flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]); 
+  flopen #(`XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
+  flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
+
+  // one copy of divstep for each bit produced per cycle
+  genvar i;
+  for (i=0; i<`IDIV_BITSPERCYCLE; i = i+1)
+    intdivrestoringstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
+
+  //////////////////////////////
+  // Memory Stage: output sign correction and special cases
+  //////////////////////////////
+
+  flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
+  
+  // On final setp of signed operations, negate outputs as needed to get correct sign
+  neg #(`XLEN) qneg(XQ[0], XQnM);
+  neg #(`XLEN) wneg(W[0], WnM);
+  // Select appropriate output: normal, negated, or for divide by zero
+  mux3 #(`XLEN) qmux(XQ[0], XQnM, {`XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
+  mux3 #(`XLEN) remmux(W[0], WnM, XQ[0], {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
+
+  //////////////////////////////
+  // Divider FSM to sequence Busy and Done
+  //////////////////////////////
+
+ always_ff @(posedge clk) 
+    if (reset | FlushE) begin
+        state <= IDLE; 
+    end else if (DivStartE) begin 
+        step <= 1;
+        if (Div0E) state <= DONE;
+        else       state <= BUSY;
+     end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
+        if (step[STEPBITS] | (`XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
+            state <= DONE;
+        end
+        step <= step + 1;
+    end else if (state == DONE) begin
+      if (StallM) state <= DONE;
+      else        state <= IDLE;
+    end 
+endmodule 
diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/pipelined/src/mdu/intdivrestoringstep.sv
new file mode 100644
index 000000000..cc27a7d5b
--- /dev/null
+++ b/pipelined/src/mdu/intdivrestoringstep.sv
@@ -0,0 +1,51 @@
+///////////////////////////////////////////
+// intdivrestoringstep.sv
+//
+// Written: David_Harris@hmc.edu 2 October 2021
+// Modified: 
+//
+// Purpose: Restoring integer division step.  k steps are used in intdivrestoring
+// 
+// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+/* verilator lint_off UNOPTFLAT */
+
+module intdivrestoringstep(
+  input  logic [`XLEN-1:0] W,     // Residual in
+  input  logic [`XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
+  input  logic [`XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
+  output logic [`XLEN-1:0] WOut,  // Residual out
+  output logic [`XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
+);
+
+  logic [`XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
+  logic [`XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
+  logic qi, qib;                  // Quotient digit and its complement
+  
+  assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
+  adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
+  assign qi = ~qib;
+  mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
+endmodule
+
+/* verilator lint_on UNOPTFLAT */
diff --git a/pipelined/src/mdu/mdu.sv b/pipelined/src/mdu/mdu.sv
new file mode 100644
index 000000000..4a85bf478
--- /dev/null
+++ b/pipelined/src/mdu/mdu.sv
@@ -0,0 +1,88 @@
+///////////////////////////////////////////
+// mdu.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: M extension multiply and divide
+// 
+// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module mdu(
+  input  logic 							clk, reset,
+  input  logic 							StallM, StallW, 
+  input  logic							FlushE, FlushM, FlushW,
+	input  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, 	// inputs A and B from IEU forwarding mux output
+	input  logic [2:0] 				Funct3E, Funct3M,									// type of MDU operation
+	input  logic 							IntDivE, W64E, 										// Integer division/remainder, and W-type instrutions
+	output logic [`XLEN-1:0] 	MDUResultW,												// multiply/divide result
+	output logic 							DivBusyE													// busy signal to stall pipeline in Execute stage
+);
+
+	logic [`XLEN*2-1:0] 			ProdM; 														// double-width product from mul
+	logic [`XLEN-1:0] 				QuotM, RemM;											// quotient and remainder from intdivrestoring
+	logic [`XLEN-1:0] 				PrelimResultM;										// selected result before W truncation
+	logic [`XLEN-1:0] 				MDUResultM;												// result after W truncation
+	logic           					W64M; 														// W-type instruction
+
+	// Multiplier
+	mul mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
+
+	// Divider
+	// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
+	// When IDIV_ON_FPU is set, use the FPU divider instead
+	if (`IDIV_ON_FPU) begin  
+	  assign QuotM = 0;
+	  assign RemM = 0;
+	  assign DivBusyE = 0;
+	end else begin
+		intdivrestoring div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, 
+							.ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
+	end
+		
+	// Result multiplexer
+	always_comb
+		case (Funct3M)	   
+			3'b000: PrelimResultM = ProdM[`XLEN-1:0];					// mul
+			3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];		// mulh
+			3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];		// mulhsu
+			3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];		// mulhu
+			3'b100: PrelimResultM = QuotM;										// div
+			3'b101: PrelimResultM = QuotM;										// divu
+			3'b110: PrelimResultM = RemM;											// rem
+			3'b111: PrelimResultM = RemM;											// remu
+		endcase 
+
+	// Handle sign extension for W-type instructions
+	flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
+	if (`XLEN == 64) begin:resmux // RV64 has W-type instructions
+		assign MDUResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
+	end else begin:resmux // RV32 has no W-type instructions
+		assign MDUResultM = PrelimResultM;
+	end
+
+	// Writeback stage pipeline register
+	flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);	 
+endmodule // mdu
+
+
diff --git a/src/mdu/mul.sv b/pipelined/src/mdu/mul.sv
similarity index 64%
rename from src/mdu/mul.sv
rename to pipelined/src/mdu/mul.sv
index 7c3f13a85..952b4daf2 100644
--- a/src/mdu/mul.sv
+++ b/pipelined/src/mdu/mul.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Integer multiplication
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,12 +26,14 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module mul #(parameter XLEN) (
+`include "wally-config.vh"
+
+module mul(
   input  logic                clk, reset,
   input  logic                StallM, FlushM,
-  input  logic [XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
+  input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // source A and B from after Forwarding mux
   input  logic [2:0]          Funct3E,                        // type of multiply
-  output logic [XLEN*2-1:0]   ProdM                           // double-widthproduct
+  output logic [`XLEN*2-1:0]  ProdM                           // double-widthproduct
 );
 
   // Number systems
@@ -49,45 +50,46 @@ module mul #(parameter XLEN) (
   // Signed * Unsigned   = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
   // Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
 
-  logic [XLEN-1:0]    Aprime, Bprime;                       // lower bits of source A and B
+  logic [`XLEN-1:0]   Aprime, Bprime;                       // lower bits of source A and B
   logic               MULH, MULHSU;                         // type of multiply
-  logic [XLEN-2:0]    PA, PB;                               // product of msb and lsbs
+  logic [`XLEN-2:0]   PA, PB;                               // product of msb and lsbs
   logic               PP;                                   // product of msbs
-  logic [XLEN*2-1:0]  PP1E, PP2E, PP3E, PP4E;               // partial products
-  logic [XLEN*2-1:0]  PP1M, PP2M, PP3M, PP4M;               // registered partial proudcts
+  logic [`XLEN*2-1:0] PP1E, PP2E, PP3E, PP4E;               // partial products
+  logic [`XLEN*2-1:0] PP1M, PP2M, PP3M, PP4M;               // registered partial proudcts
  
   //////////////////////////////
   // Execute Stage: Compute partial products
   //////////////////////////////
 
-  assign Aprime = {1'b0, ForwardedSrcAE[XLEN-2:0]};
-  assign Bprime = {1'b0, ForwardedSrcBE[XLEN-2:0]};
+  assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]};
+  assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]};
   assign PP1E = Aprime * Bprime;
-  assign PA = {(XLEN-1){ForwardedSrcAE[XLEN-1]}} & ForwardedSrcBE[XLEN-2:0];  
-  assign PB = {(XLEN-1){ForwardedSrcBE[XLEN-1]}} & ForwardedSrcAE[XLEN-2:0];
-  assign PP = ForwardedSrcAE[XLEN-1] & ForwardedSrcBE[XLEN-1];
+  assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0];  
+  assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0];
+  assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1];
 
   // flavor of multiplication
   assign MULH   = (Funct3E == 3'b001);
   assign MULHSU = (Funct3E == 3'b010);
 
   // Select partial products, handling signed multiplication
-  assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(XLEN-1){1'b0}}};
-  assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(XLEN-1){1'b0}}};
+  assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
+  assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
   always_comb 
-  if (MULH)        PP4E = {1'b1, PP, {(XLEN-3){1'b0}}, 1'b1, {(XLEN){1'b0}}}; 
-  else if (MULHSU) PP4E = {1'b1, ~PP, {(XLEN-2){1'b0}}, 1'b1, {(XLEN-1){1'b0}}};
-  else             PP4E = {1'b0, PP, {(XLEN*2-2){1'b0}}};
+  if (MULH)        PP4E = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}}; 
+  else if (MULHSU) PP4E = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
+  else             PP4E = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
 
   //////////////////////////////
   // Memory Stage: Sum partial proudcts
   //////////////////////////////
 
-  flopenrc #(XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M); 
-  flopenrc #(XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M); 
-  flopenrc #(XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); 
-  flopenrc #(XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); 
+  flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M); 
+  flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M); 
+  flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); 
+  flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); 
 
   // add up partial products; this multi-input add implies CSAs and a final CPA
   assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
  endmodule
+
diff --git a/src/mmu/adrdec.sv b/pipelined/src/mmu/adrdec.sv
similarity index 86%
rename from src/mmu/adrdec.sv
rename to pipelined/src/mmu/adrdec.sv
index f4de5a7b7..ddb8423b6 100644
--- a/src/mmu/adrdec.sv
+++ b/pipelined/src/mmu/adrdec.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Address decoder
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,9 +26,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module adrdec #(parameter PA_BITS) (
-  input  logic [PA_BITS-1:0]  PhysicalAddress,  // Physical address to decode
-  input  logic [PA_BITS-1:0]  Base, Range,      // Base and range of peripheral addresses
+`include "wally-config.vh"
+
+module adrdec (
+  input  logic [`PA_BITS-1:0] PhysicalAddress,  // Physical address to decode
+  input  logic [`PA_BITS-1:0] Base, Range,      // Base and range of peripheral addresses
   input  logic                Supported,        // Is this peripheral supported?
   input  logic                AccessValid,      // Is the access type valid?
   input  logic [1:0]          Size,             // Size of access
@@ -49,5 +50,6 @@ module adrdec #(parameter PA_BITS) (
   assign SizeValid = SizeMask[Size]; 
   
   // Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
-  assign Sel = Match & Supported & AccessValid & SizeValid; // exclusion-tag: adrdecSel
+  assign Sel = Match & Supported & AccessValid & SizeValid;
 endmodule
+
diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv
new file mode 100644
index 000000000..679bd185d
--- /dev/null
+++ b/pipelined/src/mmu/adrdecs.sv
@@ -0,0 +1,56 @@
+///////////////////////////////////////////
+// adrdecs.sv
+//
+// Written: David_Harris@hmc.edu 22 June 2021
+// Modified: 
+//
+// Purpose: All the address decoders for peripherals
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+  // verilator lint_off UNOPTFLAT 
+
+module adrdecs (
+  input  logic [`PA_BITS-1:0] PhysicalAddress,
+  input  logic                AccessRW, AccessRX, AccessRWX,
+  input  logic [1:0]          Size,
+  output logic [10:0]         SelRegions
+);
+
+  localparam logic [3:0]          SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111);
+ // Determine which region of physical memory (if any) is being accessed
+  adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[10]);  
+  adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[9]);  
+  adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[8]);  
+  adrdec bootromdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[7]);
+  adrdec uncoreramdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[6]);
+  adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[5]);
+  adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[4]);
+  adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]);
+  adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
+  adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); 
+
+  assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected
+
+endmodule
+
+  // verilator lint_on UNOPTFLAT 
diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv
new file mode 100644
index 000000000..5e798eed4
--- /dev/null
+++ b/pipelined/src/mmu/hptw.sv
@@ -0,0 +1,303 @@
+///////////////////////////////////////////
+// hptw.sv
+//
+// Written: tfleming@hmc.edu 2 March 2021
+// Modified:  david_harris@hmc.edu 18 July 2021 cleanup and simplification
+//            kmacsaigoren@hmc.edu 1 June 2021
+//            implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
+//            adding support for terapage encoding, and for setting the HPTWAdr using the new level,
+//            adding the internal SvMode signal
+//
+// Purpose: Hardware Page Table Walker
+//
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module hptw (
+	input  logic                clk, reset,
+	input  logic [`XLEN-1:0]    SATP_REGW, 					// includes SATP.MODE to determine number of levels in page table
+	input  logic [`XLEN-1:0]    PCF,  							// addresses to translate
+	input  logic [`XLEN+1:0]    IEUAdrExtM, 				// addresses to translate
+	input  logic [1:0]          MemRWM, AtomicM,
+	// system status
+	input  logic                STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+	input  logic [1:0]          STATUS_MPP,
+	input  logic [1:0]          PrivilegeModeW,
+	input  logic [`XLEN-1:0]    ReadDataM, 					// page table entry from LSU 
+	input  logic [`XLEN-1:0]    WriteDataM,
+	input  logic                DCacheStallM, 			// stall from LSU
+	input  logic [2:0]          Funct3M,
+	input  logic [6:0]          Funct7M,
+	input  logic                ITLBMissF,
+	input  logic                DTLBMissM,
+	input  logic                FlushW,
+	input  logic                InstrDAPageFaultF,
+	input  logic                DataDAPageFaultM,
+	output logic [`XLEN-1:0]    PTE, 								// page table entry to TLBs
+	output logic [1:0]          PageType, 					// page type to TLBs
+	(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
+	output logic [1:0]          PreLSURWM,
+	output logic [`XLEN+1:0]    IHAdrM,
+	output logic [`XLEN-1:0]    IHWriteDataM,
+	output logic [1:0]          LSUAtomicM,
+	output logic [2:0]          LSUFunct3M,
+	output logic [6:0]          LSUFunct7M,
+	output logic 								IgnoreRequestTLB,
+	output logic 								SelHPTW,
+	output logic 								HPTWStall,
+	input  logic  							LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, 
+	output logic 								LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM
+);
+
+	typedef enum logic [3:0] {L0_ADR, L0_RD, 
+					L1_ADR, L1_RD, 
+					L2_ADR, L2_RD, 
+					L3_ADR, L3_RD, 
+					LEAF, IDLE, UPDATE_PTE} statetype;
+
+	logic			    							DTLBWalk; // register TLBs translation miss requests
+	logic [`PPN_BITS-1:0]	    	BasePageTablePPN;
+	logic [`PPN_BITS-1:0]	    	CurrentPPN;
+	logic			    							Executable, Writable, Readable, Valid, PTE_U;
+	logic 											Misaligned, MegapageMisaligned;
+	logic			    							ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
+	logic			    							StartWalk;
+	logic     									TLBMiss;
+	logic			    							PRegEn;
+	logic [1:0]       					NextPageType;
+	logic [`SVMODE_BITS-1:0]	  SvMode;
+	logic [`XLEN-1:0] 	    		TranslationVAdr;
+  logic [`XLEN-1:0]         	NextPTE;
+  logic                     	UpdatePTE;
+  logic                     	DAPageFault;
+  logic [`PA_BITS-1:0]      	HPTWReadAdr;
+	logic                     	SelHPTWAdr;
+  logic [`XLEN+1:0]           HPTWAdrExt;
+  logic                       ITLBMissOrDAFaultF;
+  logic                       DTLBMissOrDAFaultM;
+  logic [`PA_BITS-1:0]        HPTWAdr;
+  logic [1:0]                 HPTWRW;
+  logic [2:0]                 HPTWSize; // 32 or 64 bit access
+	(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
+
+  // map hptw access faults onto either the original LSU load/store fault or instruction access fault
+  assign LoadAccessFaultM 		 = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0];
+  assign StoreAmoAccessFaultM	 = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[0];
+  assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: (LSUStoreAmoAccessFaultM | LSULoadAccessFaultM) & ~DTLBWalk;
+
+	// Extract bits from CSRs and inputs
+	assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
+	assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
+	assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF);
+
+	// Determine which address to translate
+	mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
+	assign CurrentPPN = PTE[`PPN_BITS+9:10];
+
+	// State flops
+	flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
+	assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE;
+	flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
+
+	// Assign PTE descriptors common across all XLEN values
+	// For non-leaf PTEs, D, A, U bits are reserved and ignored.  They do not cause faults while walking the page table
+	assign {PTE_U, Executable, Writable, Readable, Valid} = PTE[4:0];
+	assign LeafPTE = Executable | Writable | Readable; 
+	assign ValidPTE = Valid & ~(Writable & ~Readable);
+	assign ValidLeafPTE = ValidPTE & LeafPTE;
+	assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
+
+  if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
+    logic                     ReadAccess, WriteAccess;
+    logic                     InvalidRead, InvalidWrite;
+    logic                     UpperBitsUnequalPageFault; 
+    logic                     OtherPageFault;
+    logic [1:0]               EffectivePrivilegeMode;
+    logic                     ImproperPrivilege;
+    logic                     SaveHPTWAdr, SelHPTWWriteAdr;
+    logic [`PA_BITS-1:0]      HPTWWriteAdr;  
+    logic                     SetDirty;
+    logic                     Dirty, Accessed;
+		logic [`XLEN-1:0]		  AccessedPTE;
+
+		assign AccessedPTE = {PTE[`XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
+		mux2 #(`XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE);
+    flopenr #(`PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
+	
+    assign SaveHPTWAdr = WalkerState == L0_ADR;
+    assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
+    mux2 #(`PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); 
+
+    assign {Dirty, Accessed} = PTE[7:6];
+    assign WriteAccess = MemRWM[0] | (|AtomicM);
+    assign SetDirty = ~Dirty & DTLBWalk & WriteAccess;
+    assign ReadAccess = MemRWM[1];
+
+    assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
+                               ((EffectivePrivilegeMode == `S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
+
+    // Check for page faults
+		vm64check vm64check(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]), .VAdr(TranslationVAdr), 
+	  	.SV39Mode(), .UpperBitsUnequalPageFault);
+    assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
+    assign InvalidWrite = WriteAccess & ~Writable;
+    assign OtherPageFault = DTLBWalk? ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~Valid :
+                            ImproperPrivilege | ~Executable | UpperBitsUnequalPageFault | Misaligned | ~Valid;
+
+    // hptw needs to know if there is a Dirty or Access fault occuring on this
+    // memory access.  If there is the PTE needs to be updated seting Access
+    // and possibly also Dirty.  Dirty is set if the operation is a store/amo.
+    // However any other fault should not cause the update.
+    assign DAPageFault = ValidLeafPTE & (~Accessed | SetDirty) & ~OtherPageFault;
+
+    assign HPTWRW[0] = (WalkerState == UPDATE_PTE);
+    assign UpdatePTE = (WalkerState == LEAF) & DAPageFault;
+  end else begin // block: hptwwrites
+    assign NextPTE = ReadDataM;
+    assign HPTWAdr = HPTWReadAdr;
+    assign DAPageFault = '0;
+    assign UpdatePTE = '0;
+    assign HPTWRW[0] = '0;
+  end
+
+	// Enable and select signals based on states
+	assign StartWalk = (WalkerState == IDLE) & TLBMiss;
+	assign HPTWRW[1] = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
+	assign DTLBWriteM = (WalkerState == LEAF & ~DAPageFault) & DTLBWalk;
+	assign ITLBWriteF = (WalkerState == LEAF & ~DAPageFault) & ~DTLBWalk;
+  
+	// FSM to track PageType based on the levels of the page table traversed
+	flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
+	always_comb 
+		case (WalkerState)
+			L3_RD:  NextPageType = 2'b11; // terapage
+			L2_RD:  NextPageType = 2'b10; // gigapage
+			L1_RD:  NextPageType = 2'b01; // megapage
+			L0_RD:  NextPageType = 2'b00; // kilopage
+			default: NextPageType = PageType;
+		endcase
+
+	// HPTWAdr muxing
+	if (`XLEN==32) begin // RV32
+		logic [9:0] VPN;
+		logic [`PPN_BITS-1:0] PPN;
+		assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
+		assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
+		assign HPTWReadAdr = {PPN, VPN, 2'b00};
+		assign HPTWSize = 3'b010;
+	end else begin // RV64
+		logic [8:0] VPN;
+		logic [`PPN_BITS-1:0] PPN;
+		always_comb
+			case (WalkerState) // select VPN field based on HPTW state
+				L3_ADR, L3_RD:  VPN = TranslationVAdr[47:39];
+				L2_ADR, L2_RD:  VPN = TranslationVAdr[38:30];
+				L1_ADR, L1_RD: 	VPN = TranslationVAdr[29:21];
+				default:		VPN = TranslationVAdr[20:12];
+			endcase
+		assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
+						(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
+		assign HPTWReadAdr = {PPN, VPN, 3'b000};
+		assign HPTWSize = 3'b011;
+	end
+
+	// Initial state and misalignment for RV32/64
+	if (`XLEN == 32) begin
+		assign InitialWalkerState = L1_ADR;
+		assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
+		assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
+	end else begin
+		logic  GigapageMisaligned, TerapageMisaligned;
+		assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
+		assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
+		assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
+		assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0		  
+		assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
+	end
+
+	// Page Table Walker FSM
+  // there is a bug here.  Each memory access needs to be potentially flushed if the PMA/P checkers
+  // generate an access fault.  Specially the store on UDPATE_PTE needs to check for access violation.
+  // I think the solution is to do 1 of the following
+  // 1. Allow the HPTW to generate exceptions and stop walking immediately.
+  // 2. If the store would generate an exception don't store to dcache but still write the TLB.  When we go back
+  // to LEAF then the PMA/P.  Wait this does not work.  The PMA/P won't be looking a the address in the table, but
+  // rather than physical address of the translated instruction/data.  So we must generate the exception.
+	flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
+	always_comb 
+		case (WalkerState)
+			IDLE: if (TLBMiss)	 																				NextWalkerState = InitialWalkerState;
+				  	else 																									NextWalkerState = IDLE;
+			L3_ADR:                     																NextWalkerState = L3_RD; // first access in SV48
+			L3_RD: if (DCacheStallM)    																NextWalkerState = L3_RD;
+				   else     																							NextWalkerState = L2_ADR;
+			L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
+					else 				                 														NextWalkerState = LEAF;
+			L2_RD: if (DCacheStallM)                     								NextWalkerState = L2_RD;
+				else                                     									NextWalkerState = L1_ADR;
+			L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
+					else if (ValidNonLeafPTE)            										NextWalkerState = L1_RD;
+					else 				                														NextWalkerState = LEAF;	
+			L1_RD: if (DCacheStallM)                     								NextWalkerState = L1_RD;
+				else                                     									NextWalkerState = L0_ADR;
+			L0_ADR: if (ValidNonLeafPTE)                 								NextWalkerState = L0_RD;
+					else                                 										NextWalkerState = LEAF;
+			L0_RD: if (DCacheStallM)                     								NextWalkerState = L0_RD;
+				   else                                     							NextWalkerState = LEAF;
+			LEAF: if (`HPTW_WRITES_SUPPORTED & DAPageFault)             NextWalkerState = UPDATE_PTE;
+				  else 																										NextWalkerState = IDLE;
+			UPDATE_PTE: if(DCacheStallM) 		                        		NextWalkerState = UPDATE_PTE;
+						else 																									NextWalkerState = LEAF;
+			default: 																										NextWalkerState = IDLE; // should never be reached
+		endcase // case (WalkerState)
+
+  assign IgnoreRequestTLB = WalkerState == IDLE & TLBMiss;
+  assign SelHPTW = WalkerState != IDLE;
+  assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss);
+
+  assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
+  assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);  
+
+  // HTPW address/data/control muxing
+
+  // Once the walk is done and it is time to update the TLB we need to switch back 
+  // to the orignal data virtual address.
+  assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
+  // always block interrupts when using the hardware page table walker.
+
+  // multiplex the outputs to LSU
+  if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
+  else            assign HPTWAdrExt = HPTWAdr;
+  mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
+  mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
+  mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);    
+  mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
+  mux2 #(`XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
+  if(`HPTW_WRITES_SUPPORTED)
+    mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
+  else assign IHWriteDataM = WriteDataM;
+
+endmodule
+
+// another idea.  We keep gating the control by ~FlushW, but this adds considerable length to the critical path.
+// should we do this differently?  For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives
+// the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit.
diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv
new file mode 100644
index 000000000..8a440c39d
--- /dev/null
+++ b/pipelined/src/mmu/mmu.sv
@@ -0,0 +1,136 @@
+///////////////////////////////////////////
+// mmu.sv
+//
+// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
+// Modified: 
+//
+// Purpose: Memory management unit, including TLB, PMA, PMP
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
+  input  logic                clk, reset,
+  input  logic [`XLEN-1:0]    SATP_REGW,          // Current value of satp CSR (from privileged unit)
+  input  logic                STATUS_MXR,         // Status CSR: make executable page readable
+  input  logic                STATUS_SUM,         // Status CSR: Supervisor access to user memory
+  input  logic                STATUS_MPRV,        // Status CSR: modify machine privilege
+  input  logic [1:0]          STATUS_MPP,         // Status CSR: previous machine privilege level
+  input  logic [1:0]          PrivilegeModeW,     // Current privilege level of the processeor
+  input  logic                DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
+  input  logic [`XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
+  input  logic [1:0]          Size,               // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
+  input  logic [`XLEN-1:0]    PTE,                // page table entry
+  input  logic [1:0]          PageTypeWriteVal,   // page type
+  input  logic                TLBWrite,           // write TLB entry
+  input  logic                TLBFlush,           // Invalidate all TLB entries
+  output logic [`PA_BITS-1:0] PhysicalAddress,    // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
+  output logic                TLBMiss,            // Miss TLB
+  output logic                Cacheable,          // PMA indicates memory address is cachable
+  output logic                Idempotent,         // PMA indicates memory address is idempotent
+  output logic                SelTIM,             // Select a tightly integrated memory
+  // Faults
+  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,  // access fault sources
+  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,        // page fault sources
+  output logic                DAPageFault,                                                // page fault due to setting dirty or access bit
+  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,             // misaligned fault sources
+  // PMA checker signals
+  input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                        // PMP configuration
+  input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                        // PMP addresses
+);
+
+  logic [`PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
+  logic                       PMAInstrAccessFaultF;     // Instruction access fault from PMA
+  logic                       PMPInstrAccessFaultF;     // Instruction access fault from PMP
+  logic                       PMALoadAccessFaultM;      // Load access fault from PMA
+  logic                       PMPLoadAccessFaultM;      // Load access fault from PMP
+  logic                       PMAStoreAmoAccessFaultM;  // Store or AMO access fault from PMA
+  logic                       PMPStoreAmoAccessFaultM;  // Store or AMO access fault from PMP
+  logic                       DataMisalignedM;          // load or store misaligned
+  logic                       Translate;                // Translation occurs when virtual memory is active and DisableTranslation is off
+  logic                       TLBHit;                   // Hit in TLB
+  logic                       TLBPageFault;             // Page fault from TLB
+  
+  // only instantiate TLB if Virtual Memory is supported
+  if (`VIRTMEM_SUPPORTED) begin:tlb
+    logic ReadAccess, WriteAccess;
+    assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read.  Execute and Read are never active for the same MMU, so safe to mix pipestages
+    assign WriteAccess = WriteAccessM;
+    tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
+          .clk, .reset,
+          .SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
+          .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
+          .VAdr(VAdr[`XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+          .PrivilegeModeW, .ReadAccess, .WriteAccess,
+          .DisableTranslation, .PTE, .PageTypeWriteVal,
+          .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
+          .Translate, .TLBPageFault, .DAPageFault);
+  end else begin:tlb// just pass address through as physical
+    assign Translate = 0;
+    assign TLBMiss = 0;
+    assign TLBHit = 1; // *** is this necessary
+    assign TLBPageFault = 0;
+  end
+
+  // If translation is occuring, select translated physical address from TLB
+  // the lower 12 bits are the page offset. These are never changed from the orginal
+  // non translated address.
+  mux2 #(`PA_BITS-12) addressmux(VAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
+  assign PhysicalAddress[11:0] = VAdr[11:0];
+  
+  ///////////////////////////////////////////
+  // Check physical memory accesses
+  ///////////////////////////////////////////
+
+  pmachecker pmachecker(.PhysicalAddress, .Size,
+    .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
+    .Cacheable, .Idempotent, .SelTIM,
+    .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
+ 
+  pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
+    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+    .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
+    .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+
+  // Access faults
+  // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
+  assign InstrAccessFaultF    = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
+  assign LoadAccessFaultM     = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
+  assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
+
+  // Misaligned faults
+   always_comb
+    case(Size[1:0]) 
+      2'b00:  DataMisalignedM = 0;                 // lb, sb, lbu
+      2'b01:  DataMisalignedM = VAdr[0];           // lh, sh, lhu
+      2'b10:  DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
+      2'b11:  DataMisalignedM = |VAdr[2:0];        // ld, sd, fld, fsd
+    endcase 
+  assign LoadMisalignedFaultM     = DataMisalignedM & ReadAccessM;
+  assign StoreAmoMisalignedFaultM = DataMisalignedM & (WriteAccessM | AtomicAccessM);
+
+  // Specify which type of page fault is occurring
+  assign InstrPageFaultF    = TLBPageFault & ExecuteAccessF;
+  assign LoadPageFaultM     = TLBPageFault & ReadAccessM;
+  assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | AtomicAccessM);
+endmodule
diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv
new file mode 100644
index 000000000..e46cfe8b9
--- /dev/null
+++ b/pipelined/src/mmu/pmachecker.sv
@@ -0,0 +1,71 @@
+///////////////////////////////////////////
+// pmachecker.sv
+//
+// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
+// Modified: 
+//
+// Purpose: Examines all physical memory accesses and identifies attributes of
+//          the memory region accessed.
+//          Can report illegal accesses to the trap unit and cause a fault.
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module pmachecker (
+  input  logic [`PA_BITS-1:0] PhysicalAddress,
+  input  logic [1:0]          Size,
+  input  logic                AtomicAccessM,  // Atomic access
+  input  logic                ExecuteAccessF, // Execute access 
+  input  logic                WriteAccessM,   // Write access 
+  input  logic                ReadAccessM,    // Read access
+  output logic                Cacheable, Idempotent, SelTIM,
+  output logic                PMAInstrAccessFaultF,
+  output logic                PMALoadAccessFaultM,
+  output logic                PMAStoreAmoAccessFaultM
+);
+
+  logic                       PMAAccessFault;
+  logic                       AccessRW, AccessRWX, AccessRX;
+  logic [10:0]                SelRegions;
+  logic                       AtomicAllowed;
+
+  // Determine what type of access is being made
+  assign AccessRW = ReadAccessM | WriteAccessM;
+  assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
+  assign AccessRX = ReadAccessM | ExecuteAccessF;
+
+  // Determine which region of physical memory (if any) is being accessed
+  adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
+
+  // Only non-core RAM/ROM memory regions are cacheable
+  assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6];
+  assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
+  assign AtomicAllowed = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[6];
+  assign SelTIM = SelRegions[10] | SelRegions[9];
+
+  // Detect access faults
+  assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;  
+  assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault;
+  assign PMALoadAccessFaultM  = ReadAccessM    & PMAAccessFault;
+  assign PMAStoreAmoAccessFaultM = WriteAccessM   & PMAAccessFault;
+endmodule
+
diff --git a/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv
similarity index 65%
rename from src/mmu/pmpadrdec.sv
rename to pipelined/src/mmu/pmpadrdec.sv
index 6ba4b85da..4aeea116a 100644
--- a/src/mmu/pmpadrdec.sv
+++ b/pipelined/src/mmu/pmpadrdec.sv
@@ -10,10 +10,9 @@
 //          naturally aligned power-of-two region/NAPOT), then selects the
 //          output based on which mode is input.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -31,16 +30,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.PA_BITS-1:0]  PhysicalAddress,
-  input  logic [1:0]            Size,
+`include "wally-config.vh"
+
+module pmpadrdec (
+  input  logic [`PA_BITS-1:0]   PhysicalAddress,
   input  logic [7:0]            PMPCfg,
-  input  logic [P.PA_BITS-3:0]  PMPAdr,
-  input  logic                  FirstMatch,
+  input  logic [`XLEN-1:0]      PMPAdr,
   input  logic                  PAgePMPAdrIn,
   output logic                  PAgePMPAdrOut,
-  output logic                  Match, 
-  output logic [P.PA_BITS-1:0]  PMPTop,
+  output logic                  Match, Active, 
   output logic                  L, X, W, R
 );
   
@@ -51,10 +49,9 @@ module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
 
   logic                         TORMatch, NAMatch;
   logic                         PAltPMPAdr;
-  logic [P.PA_BITS-1:0]         CurrentAdrFull;
+  logic [`PA_BITS-1:0]          CurrentAdrFull;
   logic [1:0]                   AdrMode;
-  logic [P.PA_BITS-1:0]         PMPTop1, PMPTopTOR, PMPTopNaturallyAligned;
- 
+
   assign AdrMode = PMPCfg[4:3];
 
   // The two lsb of the physical address don't matter for this checking.
@@ -63,36 +60,30 @@ module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
  
   // Top-of-range (TOR)
   // Append two implicit trailing 0's to PMPAdr value
-  assign CurrentAdrFull  = {PMPAdr,  2'b00};
+  assign CurrentAdrFull  = {PMPAdr[`PA_BITS-3:0],  2'b00};
   assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison
   assign PAgePMPAdrOut = ~PAltPMPAdr;
-  assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn
+  assign TORMatch = PAgePMPAdrIn & PAltPMPAdr;
 
   // Naturally aligned regions
-  logic [P.PA_BITS-1:0] NAMask, NABase;
+  logic [`PA_BITS-1:0] NAMask, NABase;
 
   assign NAMask[1:0] = {2'b11};
-  assign NAMask[P.PA_BITS-1:2] = (PMPAdr + {{(P.PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr;
+  assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0];
   // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. 
   // This assumes we're using at least an NA4 region, but works for any size NAPOT region.
-  assign NABase = {(PMPAdr & ~NAMask[P.PA_BITS-1:2]), 2'b00}; // base physical address of the pmp region
+  assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. 
+  
   assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range
 
-  // finally pick the appropriate match for the access type
   assign Match = (AdrMode == TOR) ? TORMatch : 
                  (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
-                 1'b0;
-
-  // Report top of region for first matching region
-  // PMP should match but fail if the size is too big (8-byte accesses spanning to TOR or NA4 region)
-  assign PMPTopTOR = {PMPAdr-1,  2'b11}; // TOR goes to (pmpaddr << 2) - 1
-  assign PMPTopNaturallyAligned = {PMPAdr,2'b00} | NAMask; // top of the pmp region for NA4 and NAPOT.  All 1s in the lower bits.  Used to check the address doesn't pass the top
-  assign PMPTop1 = (AdrMode == TOR) ? PMPTopTOR : PMPTopNaturallyAligned;
-  assign PMPTop = FirstMatch ? PMPTop1 : '0; // AND portion of distributed AND-OR mux (OR portion in pmpchhecker)
+                 0;
 
   assign L = PMPCfg[7];
   assign X = PMPCfg[2];
   assign W = PMPCfg[1];
   assign R = PMPCfg[0];
+  assign Active = |PMPCfg[4:3];
+ endmodule
 
-endmodule
diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv
new file mode 100644
index 000000000..a57961365
--- /dev/null
+++ b/pipelined/src/mmu/pmpchecker.sv
@@ -0,0 +1,82 @@
+///////////////////////////////////////////
+// pmpchecker.sv
+//
+// Written: tfleming@hmc.edu & jtorrey@hmc.edu 28 April 2021
+// Modified: 
+//
+// Purpose: Examines all physical memory accesses and checks them against the
+//          current values of the physical memory protection (PMP) registers.
+//          Can raise an access fault on illegal reads, writes, and instruction
+//          fetches.
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module pmpchecker (
+  input  logic [`PA_BITS-1:0]      PhysicalAddress,  
+  input  logic [1:0]               PrivilegeModeW,
+  // ModelSim has a switch -svinputport which controls whether input ports
+  // are nets (wires) or vars by default. The default setting of this switch is
+  // `relaxed`, which means that signals are nets if and only if they are
+  // scalars or one-dimensional vectors. Since this is a two-dimensional vector,
+  // this will be understood as a var. However, if we don't supply the `var`
+  // keyword, the compiler warns us that it's interpreting the signal as a var,
+  // which we might not intend.
+  input  var logic [7:0]           PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
+  input  var logic [`XLEN-1:0]     PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
+  input  logic                     ExecuteAccessF, WriteAccessM, ReadAccessM,
+  output logic                     PMPInstrAccessFaultF,
+  output logic                     PMPLoadAccessFaultM,
+  output logic                     PMPStoreAmoAccessFaultM
+);
+
+  if (`PMP_ENTRIES > 0) begin
+    // Bit i is high when the address falls in PMP region i
+    logic                    EnforcePMP;
+    logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
+    logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
+    logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
+    logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
+    logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
+
+    pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
+      .PhysicalAddress, 
+      .PMPCfg(PMPCFG_ARRAY_REGW),
+      .PMPAdr(PMPADDR_ARRAY_REGW),
+      .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
+      .PAgePMPAdrOut(PAgePMPAdr),
+      .Match, .Active, .L, .X, .W, .R);
+
+    priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
+
+    // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
+    assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
+
+    assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
+    assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
+    assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
+  end else begin
+    assign PMPInstrAccessFaultF     = 0;
+    assign PMPStoreAmoAccessFaultM  = 0;
+    assign PMPLoadAccessFaultM      = 0;
+  end
+ endmodule
diff --git a/pipelined/src/mmu/tlb.sv b/pipelined/src/mmu/tlb.sv
new file mode 100644
index 000000000..f8bf0d178
--- /dev/null
+++ b/pipelined/src/mmu/tlb.sv
@@ -0,0 +1,121 @@
+///////////////////////////////////////////
+// tlb.sv
+//
+// Written: jtorrey@hmc.edu 16 February 2021
+// Modified: kmacsaigoren@hmc.edu 1 June 2021
+//            Implemented SV48 on top of SV39. This included adding the SvMode signal,
+//            and using it to decide the translate signal and get the virtual page number
+//
+// Purpose: Translation lookaside buffer
+//          Cache of virtural-to-physical address translations
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+/**
+ * SV32 specs
+ * ----------
+ * Virtual address [31:0] (32 bits)
+ *    [________________________________]
+ *     |--VPN1--||--VPN0--||----OFF---|
+ *         10        10         12
+ * 
+ * Physical address [33:0] (34 bits)
+ *  [__________________________________]
+ *   |---PPN1---||--PPN0--||----OFF---|
+ *        12         10         12
+ * 
+ * Page Table Entry [31:0] (32 bits)
+ *    [________________________________]
+ *     |---PPN1---||--PPN0--|||DAGUXWRV
+ *          12         10    ^^
+ *                         RSW(2) -- for OS
+ */
+
+`include "wally-config.vh"
+
+// The TLB will have 2**ENTRY_BITS total entries
+module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) (
+  input logic                     clk, reset,
+  input  logic [`SVMODE_BITS-1:0] SATP_MODE,        // Current address translation mode
+  input  logic [`ASID_BITS-1:0]   SATP_ASID,
+  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input  logic [1:0]              STATUS_MPP,
+  input  logic [1:0]              PrivilegeModeW,   // Current privilege level of the processeor
+  input  logic                    ReadAccess, 
+  input  logic                    WriteAccess,
+  input  logic                    DisableTranslation,
+  input  logic [`XLEN-1:0]        VAdr,             // address input before translation (could be physical or virtual)
+  input  logic [`XLEN-1:0]        PTE,
+  input  logic [1:0]              PageTypeWriteVal,
+  input  logic                    TLBWrite,
+  input  logic                    TLBFlush,
+  output logic [`PA_BITS-1:0]     TLBPAdr,
+  output logic                    TLBMiss,
+  output logic                    TLBHit,
+  output logic                    Translate,
+  output logic                    TLBPageFault,
+  output logic                    DAPageFault
+);
+
+  logic [TLB_ENTRIES-1:0]         Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
+  // Sections of the virtual and physical addresses
+  logic [`VPN_BITS-1:0]           VPN;
+  logic [`PPN_BITS-1:0]           PPN;
+  // Sections of the page table entry
+  logic [7:0]                     PTEAccessBits;
+  logic [1:0]                     HitPageType;
+  logic                           CAMHit;
+  logic                           SV39Mode;
+  logic 				                  Misaligned;
+  logic 				                  MegapageMisaligned;
+
+  if(`XLEN == 32) begin
+    assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
+    assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
+  end else begin // 64-bit
+    logic  GigapageMisaligned, TerapageMisaligned;
+    assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0
+    assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0
+    assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0		  
+    assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) | 
+              ((HitPageType == 2'b10) & GigapageMisaligned) | 
+              ((HitPageType == 2'b01) & MegapageMisaligned);
+  end
+
+  assign VPN = VAdr[`VPN_BITS+11:12];
+
+  tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+    .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
+    .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, 
+    .DAPageFault, .SV39Mode, .Translate);
+
+  tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
+  tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) 
+  tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, 
+           .SATP_ASID, .Matches, .HitPageType, .CAMHit);
+  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
+
+  // Replace segments of the virtual page number with segments of the physical
+  // page number. For 4 KB pages, the entire virtual page number is replaced.
+  // For superpages, some segments are considered offsets into a larger page.
+  tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
+
+endmodule
diff --git a/src/mmu/tlb/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv
similarity index 81%
rename from src/mmu/tlb/tlbcam.sv
rename to pipelined/src/mmu/tlbcam.sv
index 06b66efcc..449411e20 100644
--- a/src/mmu/tlb/tlbcam.sv
+++ b/pipelined/src/mmu/tlbcam.sv
@@ -9,10 +9,9 @@
 // Purpose: Stores virtual page numbers with cached translations.
 //          Determines whether a given virtual page number is in the TLB.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -30,17 +29,17 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module tlbcam  import cvw::*;  #(parameter cvw_t P,
-                                 parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
+`include "wally-config.vh"
+
+module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                    clk, reset,
-  input  logic [P.VPN_BITS-1:0]    VPN,
+  input  logic [`VPN_BITS-1:0]    VPN,
   input  logic [1:0]              PageTypeWriteVal,
   input  logic                    SV39Mode,
   input  logic                    TLBFlush,
   input  logic [TLB_ENTRIES-1:0]  WriteEnables,
   input  logic [TLB_ENTRIES-1:0]  PTE_Gs,
-  input  logic [TLB_ENTRIES-1:0]  PTE_NAPOTs,  // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
-  input  logic [P.ASID_BITS-1:0]  SATP_ASID,
+  input  logic [`ASID_BITS-1:0]   SATP_ASID,
   output logic [TLB_ENTRIES-1:0]  Matches,
   output logic [1:0]              HitPageType,
   output logic                    CAMHit
@@ -54,8 +53,8 @@ module tlbcam  import cvw::*;  #(parameter cvw_t P,
   // of page type. However, matches are determined based on a subset of the
   // page number segments.
 
-  tlbcamline #(P, KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
-    .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PTE_NAPOT(PTE_NAPOTs), .PageTypeWriteVal, .TLBFlush,
+  tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
+    .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
     .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
   assign CAMHit = |Matches & ~TLBFlush;
   or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType);
diff --git a/src/mmu/tlb/tlbcamline.sv b/pipelined/src/mmu/tlbcamline.sv
similarity index 81%
rename from src/mmu/tlb/tlbcamline.sv
rename to pipelined/src/mmu/tlbcamline.sv
index e66c22da2..9f7a68e81 100644
--- a/src/mmu/tlb/tlbcamline.sv
+++ b/pipelined/src/mmu/tlbcamline.sv
@@ -9,10 +9,9 @@
 // Purpose: CAM line for the translation lookaside buffer (TLB)
 //          Determines whether a virtual page number matches the stored key.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -30,18 +29,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module tlbcamline import cvw::*;  #(parameter cvw_t P, 
-                                    parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
+`include "wally-config.vh"
+
+module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
   input  logic                  clk, reset,
-  input  logic [P.VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
-  input  logic [P.ASID_BITS-1:0] SATP_ASID,
+  input  logic [`VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
+  input  logic [`ASID_BITS-1:0] SATP_ASID,
   input  logic                  SV39Mode,
   input  logic                  WriteEnable,  // Write a new entry to this line
   input  logic                  PTE_G,
-  input  logic                  PTE_NAPOT,  // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
   input  logic [1:0]            PageTypeWriteVal,
   input  logic                  TLBFlush,   // Flush this line (set valid to 0)
-  output logic [1:0]            PageTypeRead,  
+  output logic [1:0]            PageTypeRead,  // *** should this be the stored version or the always updated one?
   output logic                  Match
 );
 
@@ -57,13 +56,13 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
   logic [1:0]          PageType;
   
   // Split up key and query into sections for each page table level.
-  logic [P.ASID_BITS-1:0] Key_ASID;
+  logic [`ASID_BITS-1:0] Key_ASID;
   logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
   logic MatchASID, Match0, Match1;
 
   assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; 
 
-  if (P.XLEN == 32) begin: match
+  if (`XLEN == 32) begin: match
 
     assign {Key_ASID, Key1, Key0} = Key;
     assign {Query1, Query0} = VPN;
@@ -78,7 +77,7 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
   end else begin: match
 
     logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
-    logic Match2, Match3, MatchNAPOT;
+    logic Match2, Match3;
 
     assign {Query3, Query2, Query1, Query0} = VPN;
     assign {Key_ASID, Key3, Key2, Key1, Key0} = Key;
@@ -86,9 +85,7 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
     // Calculate the actual match value based on the input vpn and the page type.
     // For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
     // should automatically match.
-    // In Svnapot, if N bit is set and bottom 4 bits of PPN = 1000, then these bits don't need to match
-    assign MatchNAPOT = P.SVNAPOT_SUPPORTED & PTE_NAPOT & (Query0[SEGMENT_BITS-1:4] == Key0[SEGMENT_BITS-1:4]);
-    assign Match0 = (Query0 == Key0) | (PageType > 2'd0) | MatchNAPOT; // least significant section
+    assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section
     assign Match1 = (Query1 == Key1) | (PageType > 2'd1);
     assign Match2 = (Query2 == Key2) | (PageType > 2'd2);
     assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used
@@ -102,6 +99,8 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
 
   // On a write, set the valid bit high and update the stored key.
   // On a flush, zero the valid bit and leave the key unchanged.
+  // *** Might we want to update stored key right away to output match on the
+  // write cycle? (using a mux)
   flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
   flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
 endmodule
diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv
new file mode 100644
index 000000000..abbdba8f6
--- /dev/null
+++ b/pipelined/src/mmu/tlbcontrol.sv
@@ -0,0 +1,113 @@
+///////////////////////////////////////////
+// tlbcontrol.sv
+//
+// Written: David_Harris@hmc.edu 5 July 2021
+// Modified: 
+//
+// Purpose: Control signals for TLB
+// 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module tlbcontrol #(parameter ITLB = 0) (
+  input  logic [`SVMODE_BITS-1:0] SATP_MODE,
+  input  logic [`XLEN-1:0]        VAdr,
+  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+  input  logic [1:0]              STATUS_MPP,
+  input  logic [1:0]              PrivilegeModeW, // Current privilege level of the processeor
+  input  logic                    ReadAccess, WriteAccess,
+  input  logic                    DisableTranslation,
+  input  logic                    TLBFlush, // Invalidate all TLB entries
+  input  logic [7:0]              PTEAccessBits,
+  input  logic                    CAMHit,
+  input  logic                    Misaligned,
+  output logic                    TLBMiss,
+  output logic                    TLBHit,
+  output logic                    TLBPageFault,
+  output logic                    DAPageFault,
+  output logic                    SV39Mode,
+  output logic                    Translate
+);
+
+  // Sections of the page table entry
+  logic [1:0]                     EffectivePrivilegeMode;
+
+  logic                           PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
+  logic                           UpperBitsUnequalPageFault;
+  logic                           TLBAccess;
+  logic                           ImproperPrivilege;
+
+  // Grab the sv mode from SATP and determine whether translation should occur
+  assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
+  assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; 
+
+  // Determine whether TLB is being used
+  assign TLBAccess = ReadAccess | WriteAccess;
+
+  // Check that upper bits are legal (all 0s or all 1s)
+  vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
+
+  // unswizzle useful PTE bits
+  assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
+  assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0];
+ 
+  // Check whether the access is allowed, page faulting if not.
+  if (ITLB == 1) begin:itlb // Instruction TLB fault checking
+    // User mode may only execute user mode pages, and supervisor mode may
+    // only execute non-user mode pages.
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
+      ((EffectivePrivilegeMode == `S_MODE) & PTE_U);
+    if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
+      assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault;
+      assign TLBPageFault = (Translate  & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
+    end else begin
+      // fault for software handling if access bit is off
+      assign DAPageFault = ~PTE_A;
+      assign TLBPageFault = (Translate  & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
+    end
+  end else begin:dtlb // Data TLB fault checking
+    logic InvalidRead, InvalidWrite;
+
+    // User mode may only load/store from user mode pages, and supervisor mode
+    // may only access user mode pages when STATUS_SUM is low.
+    assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
+      ((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM);
+    // Check for read error. Reads are invalid when the page is not readable
+    // (and executable pages are not readable) or when the page is neither
+    // readable nor executable (and executable pages are readable).
+    assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
+    // Check for write error. Writes are invalid when the page's write bit is
+    // low.
+    assign InvalidWrite = WriteAccess & ~PTE_W;
+    if(`HPTW_WRITES_SUPPORTED) begin : hptwwrites
+      assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; 
+      assign TLBPageFault =  (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
+    end else begin
+      // Fault for software handling if access bit is off or writing a page with dirty bit off
+      assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; 
+      assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
+    end
+  end
+
+  assign TLBHit = CAMHit & TLBAccess;
+  assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess;
+endmodule
diff --git a/src/mmu/tlb/tlblru.sv b/pipelined/src/mmu/tlblru.sv
similarity index 87%
rename from src/mmu/tlb/tlblru.sv
rename to pipelined/src/mmu/tlblru.sv
index 6700ddcd0..6cdb475e3 100644
--- a/src/mmu/tlb/tlblru.sv
+++ b/pipelined/src/mmu/tlblru.sv
@@ -7,10 +7,9 @@
 // Purpose: Implementation of bit pseudo least-recently-used algorithm for
 //          cache evictions. Outputs the index of the next entry to be written.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -31,8 +30,9 @@
 module tlblru #(parameter TLB_ENTRIES = 8) (
   input  logic                    clk, reset,
   input  logic                    TLBWrite,
+  input  logic                    TLBFlush,
   input  logic [TLB_ENTRIES-1:0]  Matches,
-  input  logic                    TLBHit,
+  input  logic                    CAMHit,
   output logic [TLB_ENTRIES-1:0]  WriteEnables
 );
 
@@ -50,5 +50,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
   assign RUBitsAccessed = AccessLines | RUBits;
   assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
   assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; 
-  flopenr #(TLB_ENTRIES) lrustate(clk, reset, (TLBHit | TLBWrite), RUBitsNext, RUBits);
+
+  // enable must be ORd with TLBFlush to ensure flop fires on a flush.  DH 7/8/21
+  flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
 endmodule
diff --git a/src/mmu/tlb/tlbmixer.sv b/pipelined/src/mmu/tlbmixer.sv
similarity index 50%
rename from src/mmu/tlb/tlbmixer.sv
rename to pipelined/src/mmu/tlbmixer.sv
index 502d3ef83..f5555c2a1 100644
--- a/src/mmu/tlb/tlbmixer.sv
+++ b/pipelined/src/mmu/tlbmixer.sv
@@ -9,10 +9,9 @@
 //          number with segments from the second, based on the page type.
 //          NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -30,23 +29,24 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module tlbmixer import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.VPN_BITS-1:0] VPN,
-  input  logic [P.PPN_BITS-1:0] PPN,
-  input  logic [1:0]            HitPageType,
-  input  logic [11:0]           Offset,
-  input  logic                  TLBHit,
-  input  logic                  PTE_N,         // NAPOT page table entry
-  output logic [P.PA_BITS-1:0]  TLBPAdr
+`include "wally-config.vh"
+
+module tlbmixer (
+    input  logic [`VPN_BITS-1:0]   VPN,
+    input  logic [`PPN_BITS-1:0]   PPN,
+    input  logic [1:0]             HitPageType,
+    input  logic [11:0]            Offset,
+    input  logic                   TLBHit,
+    output logic [`PA_BITS-1:0]    TLBPAdr
 );
 
-  localparam EXTRA_BITS = P.PPN_BITS - P.VPN_BITS;
-  logic [P.PPN_BITS-1:0] ZeroExtendedVPN;
-  logic [P.PPN_BITS-1:0] PageNumberMask;
-  logic [P.PPN_BITS-1:0] PPNMixed, PPNMixed2;
+  localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS;
+  logic [`PPN_BITS-1:0] ZeroExtendedVPN;
+  logic [`PPN_BITS-1:0] PageNumberMask;
+  logic [`PPN_BITS-1:0] PPNMixed;
 
   // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages
-  if (P.XLEN == 32)
+  if (`XLEN == 32)
     // kilopage: 22 bits of PPN, 0 bits of VPN
     // megapage: 12 bits of PPN, 10 bits of VPN
     mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask);
@@ -59,45 +59,11 @@ module tlbmixer import cvw::*;  #(parameter cvw_t P) (
  
   // merge low segments of VPN with high segments of PPN decided by the pagetype.
   assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.
-  assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // low bits of PPN are already zero
-
-  // In Svnapot, when N=1, use bottom bits of VPN for contiugous translations
-  if (P.SVNAPOT_SUPPORTED) begin
-    // 64 KiB contiguous NAPOT translations suported
-    logic [3:0] PPNMixedBot;
-    mux2 #(4) napotmux(PPNMixed[3:0], VPN[3:0], PTE_N, PPNMixedBot);
-    assign PPNMixed2 = {PPNMixed[P.PPN_BITS-1:4], PPNMixedBot};
-
-    /* // Generalized NAPOT implementation supporting various sized contiguous regions
-    // This would also require a priority encoder in the tlbcam
-    // Not yet tested
-    logic [8:0] NAPOTMask, NAPOTPN, PPNMixedBot;
-    always_comb begin
-      casez(PPN[8:0]) 
-        9'b100000000: NAPOTMask = 9'b111111111;
-        9'b?10000000: NAPOTMask = 9'b011111111;
-        9'b??1000000: NAPOTMask = 9'b001111111;
-        9'b???100000: NAPOTMask = 9'b000111111;
-        9'b????10000: NAPOTMask = 9'b000011111;
-        9'b?????1000: NAPOTMask = 9'b000001111;
-        9'b??????100: NAPOTMask = 9'b000000111;
-        9'b???????10: NAPOTMask = 9'b000000011;
-        9'b????????1: NAPOTMask = 9'b000000001;
-        default:      NAPOTMask = 9'b000000000;
-      endcase
-    end
-    // check malformed NAPOT PPN, which should cause page fault
-    // Replace PPN with VPN in lower bits of page number based on mask
-    assign NAPOTPN = VPN & NAPOTMask | PPN & ~NAPOTMask;
-    mux2 #(9) napotmux(PPNMixed[8:0], NAPOTPN, PTE_N, PPNMixedBot);
-    assign PPNMixed2 = {PPNMixed[PPN_BITS-1:9], PPNMixedBot}; */
-    
-  end else begin // no Svnapot
-    assign PPNMixed2 = PPNMixed;
-  end
-
+  assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // 
+  //mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed);
+  //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
   // Output the hit physical address if translation is currently on.
   // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
-  assign TLBPAdr = TLBHit ? {PPNMixed2, Offset} : 0;
+  mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
 
 endmodule
diff --git a/src/mmu/tlb/tlbram.sv b/pipelined/src/mmu/tlbram.sv
similarity index 60%
rename from src/mmu/tlb/tlbram.sv
rename to pipelined/src/mmu/tlbram.sv
index a252bbd23..febb8b6f6 100644
--- a/src/mmu/tlb/tlbram.sv
+++ b/pipelined/src/mmu/tlbram.sv
@@ -8,10 +8,9 @@
 //          Outputs the physical page number and access bits of the current
 //          virtual address on a TLB hit.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -29,28 +28,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
 
-module tlbram import cvw::*;  #(parameter cvw_t P, 
-                                parameter TLB_ENTRIES = 8) (
+module tlbram #(parameter TLB_ENTRIES = 8) (
   input  logic                      clk, reset,
-  input  logic [P.XLEN-1:0]         PTE,
+  input  logic [`XLEN-1:0]          PTE,
   input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,
-  output logic [P.PPN_BITS-1:0]     PPN,
-  output logic [11:0]               PTEAccessBits,
-  output logic [TLB_ENTRIES-1:0]    PTE_Gs,
-  output logic [TLB_ENTRIES-1:0]    PTE_NAPOTs // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
+  output logic [`PPN_BITS-1:0]      PPN,
+  output logic [7:0]                PTEAccessBits,
+  output logic [TLB_ENTRIES-1:0]    PTE_Gs
 );
 
-  logic [P.XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; // stores the page table entries
-  logic [P.XLEN-1:0] PageTableEntry;
+  logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
+  logic [`PPN_BITS+9:0] PageTableEntry;
 
   // RAM implemented with array of flops and AND/OR read logic
-  tlbramline #(P) tlbramline[TLB_ENTRIES-1:0]
+  tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
      (.clk, .reset, .re(Matches), .we(WriteEnables), 
-      .d(PTE), .q(RamRead), .PTE_G(PTE_Gs), .PTE_NAPOT(PTE_NAPOTs));
-  or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
+      .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
+  or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
 
   // Rename the bits read from the TLB RAM
-  assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
-  assign PPN = PageTableEntry[P.PPN_BITS+9:10];
+  assign PTEAccessBits = PageTableEntry[7:0];
+  assign PPN = PageTableEntry[`PPN_BITS+9:10];
 endmodule
diff --git a/src/ieu/bmu/bitreverse.sv b/pipelined/src/mmu/tlbramline.sv
similarity index 59%
rename from src/ieu/bmu/bitreverse.sv
rename to pipelined/src/mmu/tlbramline.sv
index 5fc4e8b49..035c58d58 100644
--- a/src/ieu/bmu/bitreverse.sv
+++ b/pipelined/src/mmu/tlbramline.sv
@@ -1,16 +1,14 @@
 ///////////////////////////////////////////
-// bitreverse.sv
+// tlbramline.sv
 //
-// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
-// Created: 1 February 2023
-// Modified: 6 March 2023
+// Written: David_Harris@hmc.edu 4 July 2021
+// Modified:
 //
-// Purpose: Bit reverse submodule
-//
-// Documentation: RISC-V System on Chip Design
+// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
 // 
+// Documentation: RISC-V System on Chip Design Chapter 8
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,14 +26,18 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module bitreverse #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] A,
-  output logic [WIDTH-1:0] RevA);
+`include "wally-config.vh"
 
-  genvar i;
-  for (i=0; i<WIDTH;i++) begin:loop
-    assign RevA[WIDTH-i-1] = A[i];
-  end
+module tlbramline #(parameter WIDTH = 22)
+  (input  logic             clk, reset,
+   input  logic             re, we,
+   input  logic [WIDTH-1:0] d,
+   output logic [WIDTH-1:0] q,
+   output logic             PTE_G);
+
+   logic [WIDTH-1:0] line;
+
+   flopenr #(WIDTH) pteflop(clk, reset, we, d, line);
+   assign q = re ? line : 0;
+   assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching
 endmodule
-
-
diff --git a/src/mmu/tlb/vm64check.sv b/pipelined/src/mmu/vm64check.sv
similarity index 71%
rename from src/mmu/tlb/vm64check.sv
rename to pipelined/src/mmu/vm64check.sv
index 6f2d3c2d4..a78b853e1 100644
--- a/src/mmu/tlb/vm64check.sv
+++ b/pipelined/src/mmu/vm64check.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Check for good upper address bits in RV64 mode
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 8
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,23 +26,25 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module vm64check import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.SVMODE_BITS-1:0]  SATP_MODE,
-  input  logic [P.XLEN-1:0]         VAdr,
-  output logic                      SV39Mode, 
-  output logic                      UpperBitsUnequal
+`include "wally-config.vh"
+
+module vm64check (
+  input  logic [`SVMODE_BITS-1:0] SATP_MODE,
+  input  logic [`XLEN-1:0]        VAdr,
+  output logic                    SV39Mode, 
+  output logic                    UpperBitsUnequalPageFault
 );
 
-  if (P.XLEN == 64) begin
-    assign SV39Mode = (SATP_MODE == P.SV39);
+  if (`XLEN == 64) begin
+    assign SV39Mode = (SATP_MODE == `SV39);
 
     // page fault if upper bits aren't all the same
     logic                           eq_63_47, eq_46_38;
     assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
     assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
-    assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
+    assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
   end else begin
-    assign SV39Mode = 1'b0;
-    assign UpperBitsUnequal = 1'b0;
+    assign SV39Mode = 0;
+    assign UpperBitsUnequalPageFault = 0;
   end
 endmodule
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
new file mode 100644
index 000000000..289e09aef
--- /dev/null
+++ b/pipelined/src/privileged/csr.sv
@@ -0,0 +1,278 @@
+///////////////////////////////////////////
+// csr.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//          dottolia@hmc.edu 7 April 2021
+//
+// Purpose: Counter Control and Status Registers
+//          See RISC-V Privileged Mode Specification 20190608 
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module csr #(parameter
+    MIP = 12'h344,
+    SIP = 12'h144) (
+  input  logic             clk, reset,
+  input  logic             FlushM, FlushW,
+  input  logic             StallE, StallM, StallW,
+  input  logic [31:0]      InstrM,                    // current instruction
+  input  logic [`XLEN-1:0] PCM, PCNext2F,             // program counter, next PC going to trap/return logic
+  input  logic [`XLEN-1:0] SrcAM, IEUAdrM,            // SrcA and memory address from IEU
+  input  logic             CSRReadM, CSRWriteM,       // read or write CSR
+  input  logic             TrapM,                     // trap is occurring
+  input  logic             mretM, sretM, wfiM,        // return or WFI instruction
+  input  logic             IntPendingM,               // at least one interrupt is pending and could occur if enabled
+  input  logic             InterruptM,                // interrupt is occurring
+  input  logic             MTimerInt,                 // timer interrupt
+  input  logic             MExtInt, SExtInt,          // external interrupt (from PLIC) 
+  input  logic             MSwInt,                    // software interrupt
+  input  logic [63:0]      MTIME_CLINT,               // TIME value from CLINT
+  input  logic             InstrValidM,               // current instruction is valid
+  input  logic             FRegWriteM,                // writes to floating point registers change STATUS.FS
+  input  logic [4:0]       SetFflagsM,                // Set floating point flag bits in FCSR
+  input  logic [1:0]       NextPrivilegeModeM,        // STATUS bits updated based on next privilege mode
+  input  logic [1:0]       PrivilegeModeW,            // current privilege mode
+  input  logic [`LOG_XLEN-1:0] CauseM,                // Trap cause
+  input  logic             SelHPTW,                   // hardware page table walker active, so base endianness on supervisor mode
+  // inputs for performance counters
+  input  logic             LoadStallD,
+  input  logic             DirPredictionWrongM,
+  input  logic             BTBPredPCWrongM,
+  input  logic             RASPredPCWrongM,
+  input  logic             PredictionInstrClassWrongM,
+  input  logic [3:0]       InstrClassM,
+  input  logic             DCacheMiss,
+  input  logic             DCacheAccess,
+  input  logic             ICacheMiss,
+  input  logic             ICacheAccess,
+  // outputs from CSRs
+  output logic [1:0]       STATUS_MPP,
+  output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
+  output logic [`XLEN-1:0] MEDELEG_REGW, 
+  output logic [`XLEN-1:0] SATP_REGW,
+  output logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
+  output logic             STATUS_MIE, STATUS_SIE,
+  output logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
+  output logic [1:0]       STATUS_FS,
+  output var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
+  output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
+  output logic [2:0]       FRM_REGW, 
+  //
+  output logic [`XLEN-1:0] CSRReadValW,               // value read from CSR
+  output logic [`XLEN-1:0] UnalignedPCNextF,          // Next PC, accounting for traps and returns
+  output logic             IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
+  output logic             BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
+);
+
+  logic [`XLEN-1:0]        CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRReadValM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRSrcM;
+  logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRWriteValM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
+  logic [`XLEN-1:0]        STVEC_REGW, MTVEC_REGW;
+  logic [`XLEN-1:0]        MEPC_REGW, SEPC_REGW;
+  logic [31:0]             MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
+  logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
+  logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
+  logic                    WriteFRMM, WriteFFLAGSM;
+  logic [`XLEN-1:0]        UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
+  logic [11:0]             CSRAdrM;
+  logic                    IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
+  logic                    InsufficientCSRPrivilegeM;
+  logic                    IllegalCSRMWriteReadonlyM;
+  logic [`XLEN-1:0]        CSRReadVal2M;
+  logic [11:0]             MIP_REGW_writeable;
+  logic [`XLEN-1:0]        TVecM, TrapVectorM, NextFaultMtvalM;
+  logic                    MTrapM, STrapM;
+  logic [`XLEN-1:0]        EPC;
+  logic 			             RetM;
+  logic                    SelMtvecM;
+  logic [`XLEN-1:0]        TVecAlignedM;
+  logic                    InstrValidNotFlushedM;
+
+  // only valid unflushed instructions can access CSRs
+  assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
+
+  ///////////////////////////////////////////
+  // MTVAL: gets value from PC, Instruction, or load/store address
+  ///////////////////////////////////////////
+
+  always_comb
+    if (InterruptM)           NextFaultMtvalM = 0;
+    else case (CauseM)
+      12, 1, 3:               NextFaultMtvalM = PCM;  // Instruction page/access faults, breakpoint
+      2:                      NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault
+      0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
+      default:                NextFaultMtvalM = 0; // Ecall, interrupts
+    endcase
+
+  ///////////////////////////////////////////
+  // Trap Vectoring & Returns; vectored traps must be aligned to 64-byte address boundaries
+  ///////////////////////////////////////////
+
+  // Select trap vector from STVEC or MTVEC and word-align
+  assign SelMtvecM = (NextPrivilegeModeM == `M_MODE);
+  mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM);
+  assign TVecAlignedM = {TVecM[`XLEN-1:2], 2'b00};
+
+  // Support vectored interrupts
+  if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
+    logic VectoredM;
+    logic [`XLEN-1:0] TVecPlusCauseM;
+    assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
+	  assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; // 64-byte alignment allows concatenation rather than addition
+    mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
+  end else 
+    assign TrapVectorM = TVecAlignedM;
+
+  // Trap Returns
+  // A trap sets the PC to TrapVector
+  // A return sets the PC to MEPC or SEPC
+  assign RetM = mretM | sretM;
+  mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
+  mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
+
+  ///////////////////////////////////////////
+  // CSRWriteValM
+  ///////////////////////////////////////////
+
+  always_comb begin
+    // Choose either rs1 or uimm[4:0] as source
+    CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+
+    // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
+    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, MIP_REGW_writeable};
+    else                                 CSRReadVal2M = CSRReadValM;
+
+    // Compute AND/OR modification
+    CSRRWM = CSRSrcM;
+    CSRRSM = CSRReadVal2M | CSRSrcM;
+    CSRRCM = CSRReadVal2M & ~CSRSrcM;
+    case (InstrM[13:12])
+      2'b01:  CSRWriteValM = CSRRWM;
+      2'b10:  CSRWriteValM = CSRRSM;
+      2'b11:  CSRWriteValM = CSRRCM;
+      default: CSRWriteValM = CSRReadValM;
+    endcase
+  end
+
+  ///////////////////////////////////////////
+  // CSR Write values
+  ///////////////////////////////////////////
+
+  assign CSRAdrM = InstrM[31:20];
+  assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM;
+  assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM;
+  assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
+  assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
+  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
+  assign CSRUWriteM = CSRWriteM;  
+  assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
+  assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
+
+  ///////////////////////////////////////////
+  // CSRs
+  ///////////////////////////////////////////
+
+  csri   csri(.clk, .reset, .InstrValidNotFlushedM,  
+    .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
+    .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
+    .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
+
+  csrsr csrsr(.clk, .reset, .StallW, 
+    .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
+    .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
+    .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
+    .MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
+    .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
+    .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
+    .STATUS_FS, .BigEndianM);
+
+  csrm  csrm(.clk, .reset, .InstrValidNotFlushedM, 
+    .CSRMWriteM, .MTrapM, .CSRAdrM,
+    .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
+    .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
+    .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, 
+    .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+    .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
+    .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
+
+
+  if (`S_SUPPORTED) begin:csrs
+    csrs  csrs(.clk, .reset,  .InstrValidNotFlushedM,
+      .CSRSWriteM, .STrapM, .CSRAdrM,
+      .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
+      .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
+      .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
+      .SCOUNTEREN_REGW,
+      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
+      .WriteSSTATUSM, .IllegalCSRSAccessM);
+  end else begin
+    assign WriteSSTATUSM = 0;
+    assign CSRSReadValM = 0;
+    assign SEPC_REGW = 0;
+    assign STVEC_REGW = 0;
+    assign SCOUNTEREN_REGW = 0;
+    assign SATP_REGW = 0;
+    assign IllegalCSRSAccessM = 1;
+  end
+
+  // Floating Point CSRs in User Mode only needed if Floating Point is supported
+  if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
+    csru  csru(.clk, .reset, .InstrValidNotFlushedM, 
+      .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
+      .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
+      .IllegalCSRUAccessM);
+  end else begin
+    assign FRM_REGW = 0;
+    assign CSRUReadValM = 0;
+    assign IllegalCSRUAccessM = 1;
+  end
+  
+  if (`ZICOUNTERS_SUPPORTED) begin:counters
+    csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
+      .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
+      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
+      .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
+      .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
+      .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
+  end else begin
+    assign CSRCReadValM = 0;
+    assign IllegalCSRCAccessM = 1; // counters aren't enabled
+  end
+
+  // merge CSR Reads
+  assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; 
+  flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
+
+  // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
+  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != `M_MODE) |
+                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == `U_MODE);
+  assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & 
+    IllegalCSRSAccessM & IllegalCSRUAccessM |
+    InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
+endmodule
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
new file mode 100644
index 000000000..5d5bb5c96
--- /dev/null
+++ b/pipelined/src/privileged/csrc.sv
@@ -0,0 +1,161 @@
+
+
+///////////////////////////////////////////
+// csrc.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Counter CSRs
+//          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5
+//    MHPMEVENT is not supported
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+module csrc #(parameter 
+  MHPMCOUNTERBASE = 12'hB00,
+  MHPMCOUNTERHBASE = 12'hB80,
+  MHPMEVENTBASE = 12'h320,
+  HPMCOUNTERBASE = 12'hC00,
+  HPMCOUNTERHBASE = 12'hC80,
+  TIME  = 12'hC01,
+  TIMEH = 12'hC81
+) (
+  input  logic 	            clk, reset,
+  input  logic 	            StallE, StallM, 
+  input  logic              FlushM, 
+  input  logic 	            InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
+  input  logic 	            DirPredictionWrongM,
+  input  logic 	            BTBPredPCWrongM,
+  input  logic 	            RASPredPCWrongM,
+  input  logic 	            PredictionInstrClassWrongM,
+  input  logic [3:0]        InstrClassM,
+  input  logic 	            DCacheMiss,
+  input  logic 	            DCacheAccess,
+  input  logic 	            ICacheMiss,
+  input  logic 	            ICacheAccess,
+  input  logic [11:0] 	    CSRAdrM,
+  input  logic [1:0] 	      PrivilegeModeW,
+  input  logic [`XLEN-1:0]  CSRWriteValM,
+  input  logic [31:0] 	    MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
+  input  logic [63:0] 	    MTIME_CLINT, 
+  output logic [`XLEN-1:0]  CSRCReadValM,
+  output logic 	            IllegalCSRCAccessM
+);
+
+  logic [4:0]               CounterNumM;
+  (* mark_debug = "true" *)  logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
+  logic [`XLEN-1:0]         HPMCOUNTERH_REGW[`COUNTERS-1:0];
+  logic                     LoadStallE, LoadStallM;
+  logic [`COUNTERS-1:0]     WriteHPMCOUNTERM;
+  logic [`COUNTERS-1:0]     CounterEvent;
+  logic [63:0]              HPMCOUNTERPlusM[`COUNTERS-1:0];
+  logic [`XLEN-1:0]         NextHPMCOUNTERM[`COUNTERS-1:0];
+  genvar i;
+
+  // Interface signals
+  flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE));  // don't flush the load stall during a load stall.
+  flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));	
+  
+  // Determine when to increment each counter
+  assign CounterEvent[0] = 1'b1;                                                        // MCYCLE always increments
+  assign CounterEvent[1] = 1'b0;                                                        // Counter 1 doesn't exist
+  assign CounterEvent[2] = InstrValidNotFlushedM;                                       // MINSTRET instructions retired
+  if(`QEMU) begin: cevent // No other performance counters in QEMU
+    assign CounterEvent[`COUNTERS-1:3] = 0;
+  end else begin: cevent                                                                // User-defined counters
+    assign CounterEvent[3] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
+    assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;               // Branch predictor wrong direction
+    assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
+    assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
+    assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions
+    assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
+    assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
+    assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
+    assign CounterEvent[11] = DCacheAccess;                                             // data cache access
+    assign CounterEvent[12] = DCacheMiss;                                               // data cache miss
+    assign CounterEvent[13] = ICacheAccess;                                             // instruction cache access
+    assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss
+    assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+  end
+  
+  // Counter update and write logic
+  for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
+      assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
+      assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
+      always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
+        if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
+        else       HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
+
+      if (`XLEN==32) begin // write high and low separately
+        logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
+        logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
+        assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
+        assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
+        assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
+        always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
+            if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
+            else       HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
+      end else begin // XLEN=64; write entire register
+          assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
+      end
+  end
+
+  // Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
+  assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
+  always_comb 
+    if (PrivilegeModeW == `M_MODE | 
+        MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
+      IllegalCSRCAccessM = 0;
+      if (`XLEN==64) begin // 64-bit counter reads
+        // Veri lator doesn't realize this only occurs for XLEN=64
+        /* verilator lint_off WIDTH */  
+        if      (CSRAdrM == TIME)  CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
+        /* verilator lint_on WIDTH */  
+        else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
+        else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM  < HPMCOUNTERBASE+`COUNTERS)  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
+        else begin
+            CSRCReadValM = 0;
+            IllegalCSRCAccessM = 1;  // requested CSR doesn't exist
+        end
+      end else begin // 32-bit counter reads
+        // Veri lator doesn't realize this only occurs for XLEN=32
+        /* verilator lint_off WIDTH */  
+        if      (CSRAdrM == TIME)  CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
+        else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
+        /* verilator lint_on WIDTH */  
+        else if (CSRAdrM >= MHPMCOUNTERBASE  & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS)   CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
+        else if (CSRAdrM >= HPMCOUNTERBASE   & CSRAdrM < HPMCOUNTERBASE+`COUNTERS)    CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
+        else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS)  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
+        else if (CSRAdrM >= HPMCOUNTERHBASE  & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS)   CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
+        else begin
+          CSRCReadValM = 0;
+          IllegalCSRCAccessM = 1; // requested CSR doesn't exist
+        end            
+      end
+    end else begin 
+      CSRCReadValM = 0;
+      IllegalCSRCAccessM = 1; // no privileges for this csr
+    end
+endmodule
+
+//  mounteren should only exist if u-mode exists
diff --git a/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv
similarity index 53%
rename from src/privileged/csri.sv
rename to pipelined/src/privileged/csri.sv
index 41f018e91..1e68f15fd 100644
--- a/src/privileged/csri.sv
+++ b/pipelined/src/privileged/csri.sv
@@ -7,10 +7,9 @@
 // Purpose: Interrupt Control & Status Registers (IP, EI)
 //          See RISC-V Privileged Mode Specification 20190608 & 20210108 draft
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 5
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,63 +27,53 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module csri import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset, 
-  input  logic              CSRMWriteM, CSRSWriteM,
-  input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic [11:0]       CSRAdrM,
-  input  logic              MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
-  input  logic [11:0]       MIDELEG_REGW,
-  input  logic              ENVCFG_STCE,
-  output logic [11:0]       MIP_REGW, MIE_REGW,
-  output logic [11:0]       MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
+`include "wally-config.vh"
+
+module csri #(parameter 
+  MIE = 12'h304,
+  MIP = 12'h344,
+  SIE = 12'h104,
+  SIP = 12'h144) (
+  input  logic 			        clk, reset, 
+  input  logic 			        InstrValidNotFlushedM,
+  input  logic 			        CSRMWriteM, CSRSWriteM,
+  input  logic [`XLEN-1:0]  CSRWriteValM,
+  input  logic [11:0] 		  CSRAdrM,
+  (* mark_debug = "true" *)  input  logic MExtInt, SExtInt, MTimerInt, MSwInt,
+  output logic [11:0] 	    MIP_REGW, MIE_REGW,
+  (* mark_debug = "true" *) output logic [11:0]   MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
 );
 
   logic [11:0]              MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
   logic                     WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
-  logic                     STIP;
-
-  localparam MIE = 12'h304;
-  localparam MIP = 12'h344;
-  localparam SIE = 12'h104;
-  localparam SIP = 12'h144;
 
   // Interrupt Write Enables
-  assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
-  assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);
-  assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP);
-  assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE);
+  assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM;
+  assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM;
+  assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM;
+  assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM;
 
   // Interrupt Pending and Enable Registers
   // MEIP, MTIP, MSIP are read-only
   // SEIP, STIP, SSIP is writable in MIP if S mode exists
   // SSIP is writable in SIP if S mode exists
-  if (P.S_SUPPORTED) begin:mask
-    if (P.SSTC_SUPPORTED) begin
-      assign MIP_WRITE_MASK = ENVCFG_STCE ? 12'h202 : 12'h222; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
-      assign STIP = ENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
-    end else begin
-      assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
-      assign STIP = MIP_REGW_writeable[5];
-    end
-    assign SIP_WRITE_MASK = 12'h002 & MIDELEG_REGW; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) 
+  if (`S_SUPPORTED) begin:mask
+    assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
+    assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) 
     assign MIE_WRITE_MASK = 12'hAAA;
   end else begin:mask
     assign MIP_WRITE_MASK = 12'h000;
     assign SIP_WRITE_MASK = 12'h000;
     assign MIE_WRITE_MASK = 12'h888;
-    assign STIP = '0;
   end
-  always_ff @(posedge clk)
+  always @(posedge clk)
     if (reset)          MIP_REGW_writeable <= 12'b0;
     else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK);
     else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK);
-  always_ff @(posedge clk)
+  always @(posedge clk)
     if (reset)          MIE_REGW <= 12'b0;
     else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
-    else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
+    else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields
 
-  assign MIP_REGW = {MExtInt,   1'b0, SExtInt|MIP_REGW_writeable[9],  1'b0,
-                     MTimerInt, 1'b0, STIP,                           1'b0,
-                     MSwInt,    1'b0, MIP_REGW_writeable[1],          1'b0};
+  assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0};
 endmodule
diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv
new file mode 100644
index 000000000..b221fb006
--- /dev/null
+++ b/pipelined/src/privileged/csrm.sv
@@ -0,0 +1,214 @@
+///////////////////////////////////////////
+// csrm.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//          dottolia@hmc.edu 7 April 2021
+//
+// Purpose: Machine-Mode Control and Status Registers
+//          See RISC-V Privileged Mode Specification 20190608 
+// Note: the CSRs do not support the following optional features
+//   - Disabling portions of the instruction set with bits of the MISA register
+//   - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+//
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module csrm #(parameter 
+  // Machine CSRs
+  MVENDORID = 12'hF11,
+  MARCHID = 12'hF12,
+  MIMPID = 12'hF13,
+  MHARTID = 12'hF14,
+  MCONFIGPTR = 12'hF15,
+  MSTATUS = 12'h300,
+  MISA_ADR = 12'h301,
+  MEDELEG = 12'h302,
+  MIDELEG = 12'h303,
+  MIE = 12'h304,
+  MTVEC = 12'h305,
+  MCOUNTEREN = 12'h306,
+  MSTATUSH = 12'h310,
+  MCOUNTINHIBIT = 12'h320,
+  MSCRATCH = 12'h340,
+  MEPC = 12'h341,
+  MCAUSE = 12'h342,
+  MTVAL = 12'h343,
+  MIP = 12'h344,
+  MTINST = 12'h34A,
+  PMPCFG0 = 12'h3A0,
+  // .. up to 15 more at consecutive addresses
+  PMPADDR0 = 12'h3B0,
+  // ... up to 63 more at consecutive addresses
+  TSELECT = 12'h7A0,
+  TDATA1 = 12'h7A1,
+  TDATA2 = 12'h7A2,
+  TDATA3 = 12'h7A3,
+  DCSR = 12'h7B0,
+  DPC = 12'h7B1,
+  DSCRATCH0 = 12'h7B2,
+  DSCRATCH1 = 12'h7B3,
+  // Constants
+  ZERO = {(`XLEN){1'b0}},
+  MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11),
+  MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
+) (
+  input  logic 	            clk, reset, 
+  input  logic 	            InstrValidNotFlushedM, 
+  input  logic 	            CSRMWriteM, MTrapM,
+  input  logic [11:0] 	    CSRAdrM,
+  input  logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
+  input  logic [`XLEN-1:0]  CSRWriteValM,
+  (* mark_debug = "true" *)   input logic [11:0] 	     MIP_REGW, MIE_REGW,
+  output logic [`XLEN-1:0]  CSRMReadValM, MTVEC_REGW,
+  (* mark_debug = "true" *)  output logic [`XLEN-1:0] MEPC_REGW,    
+  output logic [31:0]       MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
+(* mark_debug = "true" *)  output logic [`XLEN-1:0] MEDELEG_REGW,
+(* mark_debug = "true" *)  output logic [11:0]      MIDELEG_REGW,
+  output var logic [7:0]    PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
+  output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
+  output logic 	            WriteMSTATUSM, WriteMSTATUSHM,
+  output logic 	            IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
+);
+
+  logic [`XLEN-1:0]         MISA_REGW, MHARTID_REGW;
+  (* mark_debug = "true" *)  logic [`XLEN-1:0] MSCRATCH_REGW;
+  (* mark_debug = "true" *)   logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
+  logic                     WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
+  logic                     WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
+  logic                     WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
+
+ // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
+  genvar i;
+  if (`PMP_ENTRIES > 0) begin:pmp
+    logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
+    logic [`PMP_ENTRIES-1:0] WritePMPADDRM ; 
+    logic [`PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
+    for(i=0; i<`PMP_ENTRIES; i++) begin
+      // when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
+      // also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
+      assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
+      if (i == `PMP_ENTRIES-1) 
+        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
+      else
+        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
+      
+      assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i];
+      flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
+      if (`XLEN==64) begin
+        assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i];
+        flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
+      end else begin
+        assign WritePMPCFGM[i]  = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i];
+        flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
+      end
+    end
+  end
+
+  localparam MISA_26 = (`MISA) & 32'h03ffffff;
+
+  // MISA is hardwired.  Spec says it could be written to disable features, but this is not supported by Wally
+  assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
+
+  // MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
+  assign MHARTID_REGW = 0;
+
+  // Write machine Mode CSRs 
+  assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM;
+  assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH) & InstrValidNotFlushedM & (`XLEN==32);
+  assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM;
+  assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM;
+  assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM;
+  assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM;
+  assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM;
+  assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM;
+  assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM;
+  assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM;
+  assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM;
+
+  assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
+
+  // CSRs
+  flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); 
+  if (`S_SUPPORTED) begin:deleg // DELEG registers should exist
+    flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, MEDELEG_REGW);
+    flopenr #(12)    MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW);
+  end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
+
+  flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
+  flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
+  flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
+  if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration
+  else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
+  flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
+  if (`U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
+    flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
+  end else assign MCOUNTEREN_REGW = '0;
+
+  // Read machine mode CSRs
+  // verilator lint_off WIDTH
+  logic [5:0] entry;
+  always_comb begin
+    entry = '0;
+    IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
+    if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
+      CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
+    else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
+      if (`XLEN==64) begin
+        entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
+        CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],
+                        PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
+      end else begin
+        entry = (CSRAdrM - PMPCFG0)*4;
+        CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
+      end
+    end
+    else case (CSRAdrM) 
+      MISA_ADR:  CSRMReadValM = MISA_REGW;
+      MVENDORID: CSRMReadValM = 0;
+      MARCHID:   CSRMReadValM = 0;
+      MIMPID:    CSRMReadValM = `XLEN'h100; // pipelined implementation
+      MHARTID:   CSRMReadValM = MHARTID_REGW; // hardwired to 0 
+      MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0
+      MSTATUS:   CSRMReadValM = MSTATUS_REGW;
+      MSTATUSH:  CSRMReadValM = MSTATUSH_REGW; 
+      MTVEC:     CSRMReadValM = MTVEC_REGW;
+      MEDELEG:   CSRMReadValM = MEDELEG_REGW;
+      MIDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
+      MIP:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
+      MIE:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
+      MSCRATCH:  CSRMReadValM = MSCRATCH_REGW;
+      MEPC:      CSRMReadValM = MEPC_REGW;
+      MCAUSE:    CSRMReadValM = MCAUSE_REGW;
+      MTVAL:     CSRMReadValM = MTVAL_REGW;
+      MTINST:    CSRMReadValM = 0; // implemented as trivial zero
+      MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
+      MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
+
+      default: begin
+                 CSRMReadValM = 0;
+                 IllegalCSRMAccessM = 1;
+      end
+    endcase
+  end
+  // verilator lint_on WIDTH
+endmodule
diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv
new file mode 100644
index 000000000..438aca977
--- /dev/null
+++ b/pipelined/src/privileged/csrs.sv
@@ -0,0 +1,118 @@
+///////////////////////////////////////////
+// csrs.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//          dottolia@hmc.edu 3 May 2021 - fix bug with stvec getting wrong value
+//
+// Purpose: Supervisor-Mode Control and Status Registers
+//          See RISC-V Privileged Mode Specification 20190608 
+//
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module csrs #(parameter 
+  // Supervisor CSRs
+  SSTATUS = 12'h100,
+  SIE = 12'h104,
+  STVEC = 12'h105,
+  SCOUNTEREN = 12'h106,
+  SSCRATCH = 12'h140,
+  SEPC = 12'h141,
+  SCAUSE = 12'h142,
+  STVAL = 12'h143,
+  SIP= 12'h144,
+  SATP = 12'h180) (
+    input logic 	     clk, reset, 
+    input logic 	     InstrValidNotFlushedM, 
+    input logic 	     CSRSWriteM, STrapM,
+    input logic [11:0] 	     CSRAdrM,
+    input logic [`XLEN-1:0]  NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, 
+    input logic 	     STATUS_TVM,
+    input logic [`XLEN-1:0]  CSRWriteValM,
+    input logic [1:0] 	     PrivilegeModeW,
+    (* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
+    (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW,      
+    output logic [31:0]      SCOUNTEREN_REGW, 
+    output logic [`XLEN-1:0] SATP_REGW,
+    (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
+    output logic 	     WriteSSTATUSM,
+    output logic 	     IllegalCSRSAccessM
+);
+
+  // Constants
+  localparam ZERO = {(`XLEN){1'b0}};
+  localparam SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9);
+
+  logic               WriteSTVECM;
+  logic               WriteSSCRATCHM, WriteSEPCM;
+  logic               WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
+  (* mark_debug = "true" *)  logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
+  (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;      
+  
+  // write enables
+  assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS)  & InstrValidNotFlushedM;
+  assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
+  assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
+  assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM;
+  assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM;
+  assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM;
+  assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM;
+  assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM;
+
+  // CSRs
+  flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); 
+  flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
+  flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
+  flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW);
+  flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
+  if (`VIRTMEM_SUPPORTED)
+    flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
+  else
+    assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
+  flopens #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
+
+  // CSR Reads
+  always_comb begin:csrr
+    IllegalCSRSAccessM = 0;
+    case (CSRAdrM) 
+      SSTATUS:   CSRSReadValM = SSTATUS_REGW;
+      STVEC:     CSRSReadValM = STVEC_REGW;
+      SIP:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  
+      SIE:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields
+      SSCRATCH:  CSRSReadValM = SSCRATCH_REGW;
+      SEPC:      CSRSReadValM = SEPC_REGW;
+      SCAUSE:    CSRSReadValM = SCAUSE_REGW;
+      STVAL:     CSRSReadValM = STVAL_REGW;
+      SATP:      if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
+                  else begin
+                    CSRSReadValM = 0;
+                    if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;
+                  end
+      SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW};
+      default: begin
+                  CSRSReadValM = 0; 
+                  IllegalCSRSAccessM = 1;  
+      end       
+    endcase
+  end
+endmodule
diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv
new file mode 100644
index 000000000..10e69b69e
--- /dev/null
+++ b/pipelined/src/privileged/csrsr.sv
@@ -0,0 +1,215 @@
+///////////////////////////////////////////
+// crsr.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Status register
+//          See RISC-V Privileged Mode Specification 20190608 
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module csrsr (
+  input  logic             clk, reset, StallW,
+  input  logic             WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM, 
+  input  logic             TrapM, FRegWriteM,
+  input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
+  input  logic             mretM, sretM, 
+  input  logic             WriteFRMM, WriteFFLAGSM,
+  input  logic [`XLEN-1:0] CSRWriteValM,
+  input  logic             SelHPTW,
+  output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
+  output logic [1:0]       STATUS_MPP,
+  output logic             STATUS_SPP, STATUS_TSR, STATUS_TW,
+  output logic             STATUS_MIE, STATUS_SIE,
+  output logic             STATUS_MXR, STATUS_SUM,
+  output logic             STATUS_MPRV, STATUS_TVM,
+  output logic [1:0]       STATUS_FS,
+  output logic             BigEndianM
+);
+  
+  logic STATUS_SD, STATUS_TW_INT, STATUS_TSR_INT, STATUS_TVM_INT, STATUS_MXR_INT, STATUS_SUM_INT, STATUS_MPRV_INT;
+  logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS_INT, STATUS_MPP_NEXT;
+  logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE;
+  logic nextMBE, nextSBE;
+
+  // STATUS REGISTER FIELD
+  // See Privileged Spec Section 3.1.6
+  // Lower privilege status registers are a subset of the full status register
+  // *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable
+  if (`XLEN==64) begin: csrsr64 // RV64
+    assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
+                          STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+                          STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
+                          STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0,
+                          STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
+    assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {`QEMU ? 2'b0 : STATUS_UXL}, /*9'b0, */ 12'b0,
+                          /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
+                          STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
+                          STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
+                          /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
+  end else begin: csrsr32 // RV32
+    assign MSTATUS_REGW = {STATUS_SD, 8'b0,
+                          STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+                          STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
+                          STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0, STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
+    assign MSTATUSH_REGW = {26'b0, STATUS_MBE, STATUS_SBE, 4'b0}; 
+    assign SSTATUS_REGW = {STATUS_SD, 11'b0,
+                          /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
+                          STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
+                          STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
+                          /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
+  end
+
+  // extract values to write to upper status register on 64/32-bit access
+  if (`XLEN==64) begin:upperstatus
+    assign nextMBE = CSRWriteValM[37] & `BIGENDIAN_SUPPORTED;
+    assign nextSBE = CSRWriteValM[36] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
+  end else begin:upperstatus
+    assign nextMBE = STATUS_MBE;
+    assign nextSBE = STATUS_SBE;
+  end
+
+  // harwired STATUS bits
+  assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
+  assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
+/*  assign STATUS_UBE = 0; // little-endian
+  assign STATUS_SBE = 0; // little-endian
+  assign STATUS_MBE = 0; // little-endian */
+  // SXL and UXL bits only matter for RV64.  Set to 10 for RV64 if mode is supported, or 0 if not
+  assign STATUS_SXL = `S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
+  assign STATUS_UXL = `U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
+  assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
+  assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
+  assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP  
+  assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
+  assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty
+
+  always_comb
+    if      (CSRWriteValM[12:11] == `U_MODE & `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
+    else if (CSRWriteValM[12:11] == `S_MODE & `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
+    else                                                    STATUS_MPP_NEXT = `M_MODE;
+
+  ///////////////////////////////////////////
+  // Endianness logic Privileged Spec 3.1.6.4
+  ///////////////////////////////////////////
+
+  if (`BIGENDIAN_SUPPORTED) begin: endianmux
+    // determine whether big endian accesses should be made
+    logic [1:0] EndiannessPrivMode;
+    always_comb begin
+      if      (SelHPTW)                                  EndiannessPrivMode = `S_MODE;
+      else if (PrivilegeModeW == `M_MODE & STATUS_MPRV)  EndiannessPrivMode = STATUS_MPP;
+      else                                               EndiannessPrivMode = PrivilegeModeW;
+
+      case (EndiannessPrivMode) 
+        `M_MODE: BigEndianM = STATUS_MBE;
+        `S_MODE: BigEndianM = STATUS_SBE;
+        default: BigEndianM = STATUS_UBE;
+      endcase
+    end
+  end else begin: endianmux
+    assign BigEndianM = 0;
+  end
+
+  // registers for STATUS bits
+  // complex register with reset, write enable, and the ability to update other bits in certain cases
+  always_ff @(posedge clk) //, posedge reset)
+    if (reset) begin
+      STATUS_TSR_INT <= #1 0;
+      STATUS_TW_INT <= #1 0;
+      STATUS_TVM_INT <= #1 0;
+      STATUS_MXR_INT <= #1 0;
+      STATUS_SUM_INT <= #1 0;
+      STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
+      STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00;
+      STATUS_MPP <= #1 0; 
+      STATUS_SPP <= #1 0; 
+      STATUS_MPIE <= #1 0; 
+      STATUS_SPIE <= #1 0; 
+      STATUS_MIE <= #1 0; 
+      STATUS_SIE <= #1 0; 
+      STATUS_MBE <= #1 0;
+      STATUS_SBE <= #1 0;
+      STATUS_UBE <= #1 0;
+    end else if (~StallW) begin
+      if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty  *** this should happen in M stage, be part of if/else;
+ 
+      if (TrapM) begin
+        // Update interrupt enables per Privileged Spec p. 21
+        // y = PrivilegeModeW
+        // x = NextPrivilegeModeM
+        // Modes: 11 = Machine, 01 = Supervisor, 00 = User
+        if (NextPrivilegeModeM == `M_MODE) begin
+          STATUS_MPIE <= #1 STATUS_MIE;
+          STATUS_MIE <= #1 0;
+          STATUS_MPP <= #1 PrivilegeModeW;
+        end else begin // supervisor mode
+          STATUS_SPIE <= #1 STATUS_SIE;
+          STATUS_SIE <= #1 0;
+          STATUS_SPP <= #1 PrivilegeModeW[0];
+       end
+      end else if (mretM) begin // Privileged 3.1.6.1
+        STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable
+        STATUS_MPIE <= #1 1; // 
+        STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level
+        // STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU
+        STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec.
+      end else if (sretM) begin
+        STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable
+        STATUS_SPIE <= #1 `S_SUPPORTED; 
+        STATUS_SPP <= #1 0; // set SPP to lowest supported privilege level to catch bugs
+        STATUS_MPRV_INT <= #1 0; // always clear MPRV
+      end else if (WriteMSTATUSM) begin
+        STATUS_TSR_INT <= #1 CSRWriteValM[22];
+        STATUS_TW_INT <= #1 CSRWriteValM[21];
+        STATUS_TVM_INT <= #1 CSRWriteValM[20];
+        STATUS_MXR_INT <= #1 CSRWriteValM[19];
+        STATUS_SUM_INT <= #1 CSRWriteValM[18];
+        STATUS_MPRV_INT <= #1 CSRWriteValM[17];
+        STATUS_FS_INT <= #1 CSRWriteValM[14:13];
+        STATUS_MPP <= #1 STATUS_MPP_NEXT;
+        STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
+        STATUS_MPIE <= #1 CSRWriteValM[7];
+        STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
+        STATUS_MIE <= #1 CSRWriteValM[3];
+        STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
+        STATUS_UBE <= #1 CSRWriteValM[6]  & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
+        STATUS_MBE <= #1 nextMBE;
+        STATUS_SBE <= #1 nextSBE;
+      end else if (WriteMSTATUSHM) begin
+        STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED;
+        STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
+      end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
+        STATUS_MXR_INT <= #1 CSRWriteValM[19];
+        STATUS_SUM_INT <= #1 CSRWriteValM[18];
+        STATUS_FS_INT <= #1 CSRWriteValM[14:13];
+        STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
+        STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
+        STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
+        STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
+     end 
+    end
+endmodule
diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv
new file mode 100644
index 000000000..08e2035d9
--- /dev/null
+++ b/pipelined/src/privileged/csru.sv
@@ -0,0 +1,83 @@
+///////////////////////////////////////////
+// csru.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: User-Mode Control and Status Registers for Floating Point
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module csru #(parameter 
+  FFLAGS = 12'h001,
+  FRM = 12'h002,
+  FCSR = 12'h003) (
+  input  logic             clk, reset, 
+  input  logic             InstrValidNotFlushedM,
+  input  logic             CSRUWriteM,
+  input  logic [11:0]      CSRAdrM,
+  input  logic [`XLEN-1:0] CSRWriteValM,
+  input  logic [1:0]       STATUS_FS,
+  output logic [`XLEN-1:0] CSRUReadValM,  
+  input  logic [4:0]       SetFflagsM,
+  output logic [2:0]       FRM_REGW,
+  output logic             WriteFRMM, WriteFFLAGSM,
+  output logic             IllegalCSRUAccessM
+);
+
+  logic [4:0]              FFLAGS_REGW;
+  logic [2:0]              NextFRMM;
+  logic [4:0]              NextFFLAGSM;
+    
+  // Write enables
+  //assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR)  & InstrValidNotFlushedM;
+  assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR))  & InstrValidNotFlushedM;
+  assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR))  & InstrValidNotFlushedM;
+
+  // Write Values
+  assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
+  assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
+
+  // CSRs
+  flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW);
+  flopr   #(5) FFLAGSreg(clk, reset, NextFFLAGSM, FFLAGS_REGW); 
+
+  // CSR Reads
+  always_comb begin
+    if (STATUS_FS == 2'b00) begin // fpu disabled, trap
+      IllegalCSRUAccessM = 1;
+      CSRUReadValM = 0;
+    end else begin
+      IllegalCSRUAccessM = 0;
+      case (CSRAdrM) 
+        FFLAGS:    CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW};
+        FRM:       CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW};
+        FCSR:      CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
+        default: begin
+                   CSRUReadValM = 0; 
+                   IllegalCSRUAccessM = 1;
+        end         
+      endcase
+    end
+  end
+endmodule
diff --git a/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv
similarity index 56%
rename from src/privileged/privdec.sv
rename to pipelined/src/privileged/privdec.sv
index 6b4ba92f1..fe73ebbf7 100644
--- a/src/privileged/privdec.sv
+++ b/pipelined/src/privileged/privdec.sv
@@ -7,10 +7,9 @@
 // Purpose: Decode Privileged & related instructions 
 //          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 5
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,67 +27,51 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module privdec import cvw::*;  #(parameter cvw_t P) (
+`include "wally-config.vh"
+
+module privdec (
   input  logic         clk, reset,
-  input  logic         StallW, FlushW, 
-  input  logic [31:15] InstrM,                              // privileged instruction function field
+  input  logic         StallM,
+  input  logic [31:20] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
-  input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction
+  input  logic         IllegalIEUInstrFaultM,               // Not a legal IEU instruction
+  input  logic         IllegalFPUInstrM,                    // Not a legal FPU instruction
   input  logic         IllegalCSRAccessM,                   // Not a legal CSR access
   input  logic [1:0]   PrivilegeModeW,                      // current privilege level
   input  logic         STATUS_TSR, STATUS_TVM, STATUS_TW,   // status bits
   output logic         IllegalInstrFaultM,                  // Illegal instruction
   output logic         EcallFaultM, BreakpointFaultM,       // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
-  output logic         sretM, mretM, RetM,                  // return instructions
-  output logic         wfiM, wfiW, sfencevmaM               // wfi / sfence.vma / sinval.vma instructions
+  output logic         sretM, mretM,                        // return instructions
+  output logic         wfiM, sfencevmaM                     // wfi / sfence.fma instructions
 );
 
-  logic                rs1zeroM;                            // rs1 field = 0
   logic                IllegalPrivilegedInstrM;             // privileged instruction isn't a legal one or in legal mode
   logic                WFITimeoutM;                         // WFI reaches timeout threshold
   logic                ebreakM, ecallM;                     // ebreak / ecall instructions
-  logic                sinvalvmaM;                          // sinval.vma
-  logic                sfencewinvalM, sfenceinvalirM;       // sfence.w.inval, sfence.inval.ir
-  logic                invalM;                              // any of the svinval instructions
 
   ///////////////////////////////////////////
   // Decode privileged instructions
   ///////////////////////////////////////////
 
-  assign rs1zeroM =    InstrM[19:15] == 5'b0;
-  
-  // svinval instructions
-  // any svinval instruction is treated as sfence.vma on Wally
-  assign sinvalvmaM =     (InstrM[31:25] ==  7'b0001011);
-  assign sfencewinvalM  = (InstrM[31:20] == 12'b000110000000) & rs1zeroM;
-  assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM;
-  assign invalM =         P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); 
-
-  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED & 
-                      (PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR); 
-  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
-  assign RetM =       sretM | mretM;
-  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
-  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
-  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;
-  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001 | invalM) & 
-                      (PrivilegeModeW == P.M_MODE | (PrivilegeModeW == P.S_MODE & ~STATUS_TVM)) & P.VIRTMEM_SUPPORTED; 
+  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & 
+                      (PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR); 
+  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
+  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000);
+  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001);
+  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101);
+  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001) & 
+                      (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); 
 
   ///////////////////////////////////////////
   // WFI timeout Privileged Spec 3.1.6.5
   ///////////////////////////////////////////
 
-  if (P.U_SUPPORTED) begin:wfi
-    logic [P.WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
-    assign WFICountPlus1 = wfiM ? WFICount + 1 : '0; // restart counting on WFI
-    flopr #(P.WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, WFICountPlus1, WFICount);  // count while in WFI
-  // coverage off -item e 1 -fecexprrow 1
-  // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout.
-    assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; 
-  // coverage on
-  end else assign WFITimeoutM = 1'b0;
-
-  flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW);
+  if (`U_SUPPORTED) begin:wfi
+    logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
+    assign WFICountPlus1 = WFICount + 1;
+    floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount);  // count while in WFI
+    assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; 
+  end else assign WFITimeoutM = 0;
 
   ///////////////////////////////////////////
   // Extract exceptions by name and handle them 
@@ -102,6 +85,6 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   ///////////////////////////////////////////
   
   assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
-  assign IllegalInstrFaultM = IllegalIEUFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | 
-                              WFITimeoutM; 
+  assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | 
+                               WFITimeoutM; 
 endmodule
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
new file mode 100644
index 000000000..0e5076033
--- /dev/null
+++ b/pipelined/src/privileged/privileged.sv
@@ -0,0 +1,156 @@
+///////////////////////////////////////////
+// privileged.sv
+//
+// Written: David_Harris@hmc.edu 5 January 2021
+// Modified: 
+//
+// Purpose: Implements the CSRs, Exceptions, and Privileged operations
+//          See RISC-V Privileged Mode Specification 20190608 
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module privileged (
+  input  logic             clk, reset,
+  input  logic             StallD, StallE, StallM, StallW,
+  input  logic             FlushD, FlushE, FlushM, FlushW, 
+  // CSR Reads and Writes, and values needed for traps
+(* mark_debug = "true" *)  input  logic  CSRReadM, CSRWriteM,         // Read or write CSRs
+  input  logic [`XLEN-1:0] SrcAM,                                     // GPR register to write
+  input  logic [31:0]      InstrM,                                    // Instruction
+  input  logic [`XLEN-1:0] IEUAdrM,                                   // address from IEU
+  input  logic [`XLEN-1:0] PCM, PCNext2F,                             // program counter, next PC going to trap/return PC logic
+  // control signals
+  input  logic             InstrValidM,                               // Current instruction is valid (not flushed)
+  input  logic             CommittedM, CommittedF,                    // current instruction is using bus; don't interrupt
+  input  logic             PrivilegedM,                               // privileged instruction
+  // processor events for performance counter logging
+  input  logic             FRegWriteM,                                // instruction will write floating-point registers
+  input  logic             LoadStallD,                                // load instruction is stalling
+  input  logic 		         DirPredictionWrongM,                       // branch predictor guessed wrong directoin
+  input  logic 		         BTBPredPCWrongM,                           // branch predictor guessed wrong target
+  input  logic 		         RASPredPCWrongM,                           // return adddress stack guessed wrong target
+  input  logic 		         PredictionInstrClassWrongM,                // branch predictor guessed wrong instruction class
+  input  logic [3:0]       InstrClassM,                               // actual instruction class
+  input  logic             DCacheMiss,                                // data cache miss
+  input  logic             DCacheAccess,                              // data cache accessed (hit or miss)
+  input  logic             ICacheMiss,                                // instruction cache miss
+  input  logic             ICacheAccess,                              // instruction cache access
+  // fault sources
+  input  logic             InstrAccessFaultF,                         // instruction access fault
+  input  logic             LoadAccessFaultM, StoreAmoAccessFaultM,    // load or store access fault
+  input  logic             HPTWInstrAccessFaultM,                     // hardware page table access fault while fetching instruction PTE
+  input  logic             InstrPageFaultF,                           // page faults
+  input  logic             LoadPageFaultM, StoreAmoPageFaultM,        // page faults
+  input  logic             InstrMisalignedFaultM,                     // misaligned instruction fault
+  input  logic             LoadMisalignedFaultM, StoreAmoMisalignedFaultM,  // misaligned data fault
+  input  logic             IllegalIEUInstrFaultD, IllegalFPUInstrM,   // illegal instruction faults
+  input  logic             MTimerInt, MExtInt, SExtInt, MSwInt,       // interrupt sources
+  input  logic [63:0]      MTIME_CLINT,                               // timer value from CLINT
+  input  logic [4:0]       SetFflagsM,                                // set FCSR flags from FPU
+  input  logic             SelHPTW,                                   // HPTW in use.  Causes system to use S-mode endianness for accesses
+  // CSR outputs
+  output logic [`XLEN-1:0] CSRReadValW,                               // Value read from CSR
+  output logic [1:0]       PrivilegeModeW,                            // current privilege mode
+  output logic [`XLEN-1:0] SATP_REGW,                                 // supervisor address translation register
+  output logic             STATUS_MXR, STATUS_SUM, STATUS_MPRV,       // status register bits
+  output logic [1:0]       STATUS_MPP, STATUS_FS,                     // status register bits
+  output var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],       // PMP configuration entries to MMU
+  output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU
+  output logic [2:0]       FRM_REGW,                                  // FPU rounding mode
+  // PC logic output in privileged unit
+  output logic [`XLEN-1:0] UnalignedPCNextF,                          // Next PC from trap/return PC logic
+  // control outputs  
+  output logic             RetM, TrapM,                               // return instruction, or trap
+  output logic             sfencevmaM,                                // sfence.vma instruction
+  output logic             BigEndianM,                                // Use big endian in current privilege mode
+  // Fault outputs
+  output logic             BreakpointFaultM, EcallFaultM,             // breakpoint and Ecall traps should retire
+  output logic             WFIStallM                                  // Stall in Memory stage for WFI until interrupt or timeout
+);
+
+  logic [`LOG_XLEN-1:0]    CauseM;                                    // trap cause
+  logic [`XLEN-1:0]        MEDELEG_REGW;                              // exception delegation CSR
+  logic [11:0]             MIDELEG_REGW;                              // interrupt delegation CSR
+  logic                    sretM, mretM;                              // supervisor / machine return instruction
+  logic                    IllegalCSRAccessM;                         // Illegal access to CSR
+  logic                    IllegalIEUInstrFaultM;                     // Illegal IEU instruction, delayed to Mem stage
+  logic                    InstrPageFaultM;                           // Instruction page fault, delayed to Mem stage
+  logic                    InstrAccessFaultM;                         // Instruction access fault, delayed to Mem stages
+  logic                    IllegalInstrFaultM;                        // Illegal instruction fault
+  logic                    STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; // Status bits needed within privileged unit
+  logic                    STATUS_MIE, STATUS_SIE;                    // status bits: interrupt enables
+  logic [11:0]             MIP_REGW, MIE_REGW;                        // interrupt pending and enable bits
+  logic [1:0]              NextPrivilegeModeM;                        // next privilege mode based on trap or return
+  logic                    DelegateM;                                 // trap should be delegated
+  logic                    wfiM;                                      // wait for interrupt instruction
+  logic                    IntPendingM;                               // interrupt is pending, even if not enabled.  ends wfi
+  (* mark_debug = "true" *) logic InterruptM;                         // interrupt occuring
+
+
+  // track the current privilege level
+  privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
+    .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
+
+  // decode privileged instructions
+  privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
+    .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, 
+    .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
+    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
+
+  // Control and Status Registers
+  csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
+    .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F,
+    .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
+    .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
+    .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
+    .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
+    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
+    .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
+    .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
+    .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
+    .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
+    .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+    .SetFflagsM, .FRM_REGW, 
+    .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
+
+  // pipeline early-arriving trap sources
+  privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+    .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, 
+    .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM);
+
+  // trap logic
+  trap trap(.reset,
+    .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
+    .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
+    .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
+    .LoadPageFaultM, .StoreAmoPageFaultM,
+    .mretM, .sretM, .PrivilegeModeW, 
+    .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
+    .InstrValidM, .CommittedM, .CommittedF,
+    .TrapM, .RetM, .wfiM, .InterruptM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM);
+endmodule
+
+
+
+
+
diff --git a/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv
similarity index 75%
rename from src/privileged/privmode.sv
rename to pipelined/src/privileged/privmode.sv
index f9a38d501..615f30439 100644
--- a/src/privileged/privmode.sv
+++ b/pipelined/src/privileged/privmode.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: Track privilege mode.  Change on traps and returns.
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 5
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,7 +26,9 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module privmode import cvw::*;  #(parameter cvw_t P) (
+`include "wally-config.vh"
+
+module privmode (
   input  logic             clk, reset,
   input  logic             StallW, 
   input  logic             TrapM,               // Trap 
@@ -39,20 +40,20 @@ module privmode import cvw::*;  #(parameter cvw_t P) (
   output logic [1:0]       PrivilegeModeW       // current privilege mode
 ); 
   
-  if (P.U_SUPPORTED) begin:privmode
+  if (`U_SUPPORTED) begin:privmode
     // PrivilegeMode FSM
     always_comb begin
       if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
-        if (P.S_SUPPORTED & DelegateM) NextPrivilegeModeM = P.S_MODE;
-        else                           NextPrivilegeModeM = P.M_MODE;
-      end else if (mretM)              NextPrivilegeModeM = STATUS_MPP;
-      else     if (sretM)              NextPrivilegeModeM = {1'b0, STATUS_SPP};
-      else                             NextPrivilegeModeM = PrivilegeModeW;
+        if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE;
+        else                          NextPrivilegeModeM = `M_MODE;
+      end else if (mretM)             NextPrivilegeModeM = STATUS_MPP;
+      else     if (sretM)             NextPrivilegeModeM = {1'b0, STATUS_SPP};
+      else                            NextPrivilegeModeM = PrivilegeModeW;
     end
 
-    flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, P.M_MODE, PrivilegeModeW);
+    flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
   end else begin  // only machine mode supported
-    assign NextPrivilegeModeM = P.M_MODE;
-    assign PrivilegeModeW = P.M_MODE;
+    assign NextPrivilegeModeM = `M_MODE;
+    assign PrivilegeModeW = `M_MODE;
   end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv
new file mode 100644
index 000000000..03e1d6213
--- /dev/null
+++ b/pipelined/src/privileged/privpiperegs.sv
@@ -0,0 +1,56 @@
+///////////////////////////////////////////
+// privpiperegs.sv
+//
+// Written: David_Harris@hmc.edu 12 May 2022
+// Modified: 
+//
+// Purpose: Pipeline registers for early exceptions
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module privpiperegs (
+  input  logic         clk, reset,  
+  input  logic         StallD, StallE, StallM,
+  input  logic         FlushD, FlushE, FlushM,
+  input  logic         InstrPageFaultF, InstrAccessFaultF,  // instruction faults
+  input  logic         IllegalIEUInstrFaultD,               // illegal IEU instruction decoded
+  output logic         InstrPageFaultM, InstrAccessFaultM,  // delayed instruction faults
+  output logic         IllegalIEUInstrFaultM                // delayed illegal IEU instruction
+);
+
+  // Delayed fault signals
+  logic                InstrPageFaultD, InstrAccessFaultD;
+  logic                InstrPageFaultE, InstrAccessFaultE;
+  logic                IllegalIEUInstrFaultE; 
+
+  // pipeline fault signals
+  flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
+                  {InstrPageFaultF, InstrAccessFaultF},
+                  {InstrPageFaultD, InstrAccessFaultD});
+  flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE,
+                  {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, 
+                  {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE});
+  flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM,
+                  {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE},
+                  {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM});
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
new file mode 100644
index 000000000..4ca281567
--- /dev/null
+++ b/pipelined/src/privileged/trap.sv
@@ -0,0 +1,120 @@
+///////////////////////////////////////////
+// trap.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts
+//
+// Purpose: Handle Traps: Exceptions and Interrupts
+// 
+// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module trap (
+  input  logic 		                             reset, 
+  (* mark_debug = "true" *) input  logic 		   InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, IllegalInstrFaultM,
+  (* mark_debug = "true" *) input  logic 		   BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
+  (* mark_debug = "true" *) input  logic 		   LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
+  (* mark_debug = "true" *) input  logic 		   LoadPageFaultM, StoreAmoPageFaultM,              // various trap sources
+  (* mark_debug = "true" *) input  logic 		   mretM, sretM,                                    // return instructions
+  input  logic                                 wfiM,                                            // wait for interrupt instruction
+  input  logic [1:0] 	                         PrivilegeModeW,                                  // current privilege mode
+  (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,                // interrupt pending, enabled, and delegate CSRs
+  input  logic [`XLEN-1:0]                     MEDELEG_REGW,                                    // exception delegation SR
+  input  logic 		                             STATUS_MIE, STATUS_SIE,                          // machine/supervisor interrupt enables
+  input  logic 		                             InstrValidM,                                     // current instruction is valid, not flushed
+  input  logic                                 CommittedM, CommittedF,                          // LSU/IFU has committed to a bus operation that can't be interrupted
+  output logic 		                             TrapM,                                           // Trap is occurring
+  output logic 		                             RetM,                                            // Return instruction being executed
+  output logic 		                             InterruptM,                                      // Interrupt is occurring
+  output logic 		                             IntPendingM,                                     // Interrupt is pending, might occur if enabled
+  output logic 		                             DelegateM,                                       // Delegate trap to supervisor handler
+  output logic 		                             WFIStallM,                                       // Stall due to WFI instruction
+  output logic [`LOG_XLEN-1:0]                 CauseM                                           // trap cause
+);
+
+  logic                                        MIntGlobalEnM, SIntGlobalEnM;                    // Global interupt enables
+  logic                                        ExceptionM;                                      // exception is occurring
+  logic                                        Committed;                                       // LSU or IFU has committed to a bus operation that can't be interrupted
+  logic                                        BothInstrAccessFaultM;                           // instruction or HPTW ITLB fill caused an Instruction Access Fault
+  (* mark_debug = "true" *) logic [11:0]       PendingIntsM, ValidIntsM, EnabledIntsM;          // interrupts are pending, valid, or enabled
+
+  ///////////////////////////////////////////
+  // Determine pending enabled interrupts
+  // interrupt if any sources are pending
+  // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
+  // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
+  ///////////////////////////////////////////
+
+  assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
+  assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
+  assign PendingIntsM = MIP_REGW & MIE_REGW;
+  assign IntPendingM = |PendingIntsM;
+  assign Committed = CommittedM | CommittedF;
+  assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
+  assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
+  assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
+  assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & 
+                     (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
+  assign WFIStallM = wfiM & ~IntPendingM;
+
+  ///////////////////////////////////////////
+  // Trigger Traps and RET
+  // According to RISC-V Spec Section 1.6, exceptions are caused by instructions.  Interrupts are external asynchronous.
+  // Traps are the union of exceptions and interrupts.
+  ///////////////////////////////////////////
+  
+  assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM;
+  assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM |
+                      LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
+                      InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
+                      BreakpointFaultM | EcallFaultM |
+                      LoadAccessFaultM | StoreAmoAccessFaultM;
+  assign TrapM = ExceptionM | InterruptM; 
+  assign RetM = mretM | sretM;
+
+  ///////////////////////////////////////////
+  // Cause priority defined in table 3.7 of 20190608 privileged spec
+  // Exceptions are of lower priority than all interrupts (3.1.9)
+  ///////////////////////////////////////////
+
+  always_comb
+    if      (reset)                    CauseM = 0; // hard reset 3.3
+    else if (ValidIntsM[11])           CauseM = 11; // Machine External Int
+    else if (ValidIntsM[3])            CauseM = 3;  // Machine Sw Int
+    else if (ValidIntsM[7])            CauseM = 7;  // Machine Timer Int
+    else if (ValidIntsM[9])            CauseM = 9;  // Supervisor External Int 
+    else if (ValidIntsM[1])            CauseM = 1;  // Supervisor Sw Int       
+    else if (ValidIntsM[5])            CauseM = 5;  // Supervisor Timer Int    
+    else if (InstrPageFaultM)          CauseM = 12;
+    else if (BothInstrAccessFaultM)    CauseM = 1;
+    else if (IllegalInstrFaultM)       CauseM = 2;
+    else if (InstrMisalignedFaultM)    CauseM = 0;
+    else if (BreakpointFaultM)         CauseM = 3;
+    else if (EcallFaultM)              CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW};
+    else if (LoadMisalignedFaultM)     CauseM = 4;
+    else if (StoreAmoMisalignedFaultM) CauseM = 6;
+    else if (LoadPageFaultM)           CauseM = 13;
+    else if (StoreAmoPageFaultM)       CauseM = 15;
+    else if (LoadAccessFaultM)         CauseM = 5;
+    else if (StoreAmoAccessFaultM)     CauseM = 7;
+    else                               CauseM = 0;
+endmodule
diff --git a/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv
similarity index 72%
rename from src/uncore/ahbapbbridge.sv
rename to pipelined/src/uncore/ahbapbbridge.sv
index 84979ddee..011356ba2 100644
--- a/src/uncore/ahbapbbridge.sv
+++ b/pipelined/src/uncore/ahbapbbridge.sv
@@ -5,10 +5,9 @@
 //
 // Purpose: AHB to APB bridge
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 6
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -26,30 +25,31 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ahbapbbridge import cvw::*;  #(parameter cvw_t P, 
-                                      parameter PERIPHS = 2) (
-  input  logic                 HCLK, HRESETn,
-  input  logic [PERIPHS-1:0]   HSEL,  
-  input  logic [P.PA_BITS-1:0] HADDR, 
-  input  logic [P.XLEN-1:0]    HWDATA,
-  input  logic [P.XLEN/8-1:0]  HWSTRB,
-  input  logic                 HWRITE,
-  input  logic [1:0]           HTRANS,
-  input  logic                 HREADY,
+`include "wally-config.vh"
+
+module ahbapbbridge #(PERIPHS = 2) (
+  input  logic                HCLK, HRESETn,
+  input  logic [PERIPHS-1:0]  HSEL,  
+  input  logic [`PA_BITS-1:0] HADDR, 
+  input  logic [`XLEN-1:0]    HWDATA,
+  input  logic [`XLEN/8-1:0]  HWSTRB,
+  input  logic                HWRITE,
+  input  logic [1:0]          HTRANS,
+  input  logic                HREADY,
 //  input  logic [3:0]        HPROT, // not used
-  output logic [P.XLEN-1:0]    HRDATA,
-  output logic                 HRESP, HREADYOUT,
-  output logic                 PCLK, PRESETn,
-  output logic [PERIPHS-1:0]   PSEL,
-  output logic                 PWRITE,
-  output logic                 PENABLE,
-  output logic [31:0]          PADDR,
-  output logic [P.XLEN-1:0]    PWDATA,
+  output logic [`XLEN-1:0]    HRDATA,
+  output logic                HRESP, HREADYOUT,
+  output logic                PCLK, PRESETn,
+  output logic [PERIPHS-1:0]  PSEL,
+  output logic                PWRITE,
+  output logic                PENABLE,
+  output logic [31:0]         PADDR,
+  output logic [`XLEN-1:0]    PWDATA,
 //  output logic [2:0]        PPROT, // not used
-  output logic [P.XLEN/8-1:0]  PSTRB,
+  output logic [`XLEN/8-1:0]  PSTRB,
 //  output logic              PWAKEUP // not used
-  input  logic [PERIPHS-1:0]   PREADY,
-  input  var   [PERIPHS-1:0][P.XLEN-1:0] PRDATA
+  input  logic [PERIPHS-1:0]  PREADY,
+  input  var   [PERIPHS-1:0][`XLEN-1:0] PRDATA
 );
 
   logic                       initTrans, initTransSel, initTransSelD;
@@ -57,15 +57,15 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
   logic                       PREADYOUT;
 
   // convert AHB to APB signals
-  assign PCLK    = HCLK;
+  assign PCLK = HCLK;
   assign PRESETn = HRESETn;
 
   // identify start of a transaction
-  assign initTrans    = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
+  assign initTrans = HTRANS[1] & HREADY;  // start a transaction when the bus is ready and an active transaction is requested
   assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected
 
   // delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time
-  flopen  #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
+  flopen #(32) addrreg(HCLK, HREADY, HADDR[31:0], PADDR);
   flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE); 
   flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL); 
   // PPROT[2:0] = {Data/InstrB, Secure, Privileged};
@@ -74,7 +74,7 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
 
   // AHB Data phase signal doesn't need delay.  Note that they are guaranteed to remain stable until READY is asserted
   assign PWDATA = HWDATA;
-  assign PSTRB  = HWSTRB;
+  assign PSTRB = HWSTRB;
 
   // enable logic: goes high a cycle after initTrans, then back low on cycle after desired PREADY is asserted
   // cycle1: AHB puts HADDR, HWRITE, HSEL on bus.  initTrans is 1, and these are captured
@@ -89,7 +89,8 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
   int i;
   always_comb begin
     // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
-    HRDATA = '0;
+    // *** also could assert ready right away
+    HRDATA = 0;
     PREADYOUT = 1'b1; 
     for (i=0; i<PERIPHS; i++)  begin
       if (PSEL[i]) begin // highest numbered peripheral has priority, but multiple PSEL should never be asserted
@@ -101,5 +102,6 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
 assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before access phase
 
   // resp logic
-  assign HRESP = 1'b0; // bridge never indicates errors
+  assign HRESP = 0; // bridge never indicates errors
 endmodule
+
diff --git a/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv
similarity index 71%
rename from src/uncore/clint_apb.sv
rename to pipelined/src/uncore/clint_apb.sv
index e03745194..6784a2a3e 100644
--- a/src/uncore/clint_apb.sv
+++ b/pipelined/src/uncore/clint_apb.sv
@@ -7,10 +7,9 @@
 // Purpose: Core-Local Interruptor
 //   See FE310-G002-Manual-v19p05 for specifications
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 15
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,37 +27,34 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module clint_apb import cvw::*;  #(parameter cvw_t P) (
+`include "wally-config.vh"
+
+module clint_apb (
   input  logic                PCLK, PRESETn,
   input  logic                PSEL,
   input  logic [15:0]         PADDR, 
-  input  logic [P.XLEN-1:0]   PWDATA,
-  input  logic [P.XLEN/8-1:0] PSTRB,
+  input  logic [`XLEN-1:0]    PWDATA,
+  input  logic [`XLEN/8-1:0]  PSTRB,
   input  logic                PWRITE,
   input  logic                PENABLE,
-  output logic [P.XLEN-1:0]   PRDATA,
+  output logic [`XLEN-1:0]    PRDATA,
   output logic                PREADY,
-  output logic [63:0] MTIME, 
-  output logic                MTimerInt, MSwInt
+  (* mark_debug = "true" *) output logic [63:0] MTIME, 
+  output logic 			          MTimerInt, MSwInt
 );
 
-  // register map
-  localparam CLINT_MSIP     = 16'h0000;
-  localparam CLINT_MTIMECMP = 16'h4000;
-  localparam CLINT_MTIME    = 16'hBFF8;
-
   logic                       MSIP;
   logic [15:0]                entry;
   logic                       memwrite;
-  logic [63:0] MTIMECMP;
+   (* mark_debug = "true" *)    logic [63:0] MTIMECMP;
   integer                     i, j;
   
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign PREADY   = 1'b1;                     // CLINT never takes >1 cycle to respond
+  assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
 
   // word aligned reads
-  if (P.XLEN==64) assign entry = {PADDR[15:3], 3'b000};
-  else            assign entry = {PADDR[15:2], 2'b00}; 
+  if (`XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000};
+  else           assign #2 entry = {PADDR[15:2], 2'b00}; 
   
   // DH 2/20/21: Eventually allow MTIME to run off a separate clock
   // This will require synchronizing MTIME to the system clock
@@ -67,63 +63,64 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
   // Use req and ack signals synchronized across the clock domains.
 
   // register access
-  if (P.XLEN==64) begin:clint // 64-bit
-    always_ff @(posedge PCLK) begin
+  if (`XLEN==64) begin:clint // 64-bit
+    always @(posedge PCLK) begin
       case(entry)
-        CLINT_MSIP:     PRDATA <= {63'b0, MSIP};
-        CLINT_MTIMECMP: PRDATA <= MTIMECMP;
-        CLINT_MTIME:    PRDATA <= MTIME;
-        default:        PRDATA <= '0;
+        16'h0000: PRDATA <= {63'b0, MSIP};
+        16'h4000: PRDATA <= MTIMECMP;
+        16'hBFF8: PRDATA <= MTIME;
+        default:  PRDATA <= 0;
       endcase
     end 
-    always_ff @(posedge PCLK) 
+    always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) begin
-        MSIP <= 1'b0;
+        MSIP <= 0;
         MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
       end else if (memwrite) begin
-        if (entry == CLINT_MSIP) MSIP <= PWDATA[0];
-        if (entry == CLINT_MTIMECMP) begin
-          for(i=0;i<P.XLEN/8;i++)
+        if (entry == 16'h0000) MSIP <= PWDATA[0];
+        if (entry == 16'h4000) begin
+          for(i=0;i<`XLEN/8;i++)
             if(PSTRB[i])
-              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8];
+              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
         end
       end
 
 // eventually replace MTIME logic below with timereg
 //    timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), 1'b0, PWDATA, MTIME, done);
 
-    always_ff @(posedge PCLK) 
+    always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) begin
-        MTIME <= '0;
+        MTIME <= 0;
       end else if (memwrite & entry == 16'hBFF8) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        for(j=0;j<P.XLEN/8;j++)
+        for(j=0;j<`XLEN/8;j++)
           if(PSTRB[j])
             MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8];
       end else MTIME <= MTIME + 1; 
   end else begin:clint // 32-bit
-    always_ff @(posedge PCLK) begin
+    always @(posedge PCLK) begin
       case(entry)
         16'h0000: PRDATA <= {31'b0, MSIP};
         16'h4000: PRDATA <= MTIMECMP[31:0];
         16'h4004: PRDATA <= MTIMECMP[63:32];
         16'hBFF8: PRDATA <= MTIME[31:0];
         16'hBFFC: PRDATA <= MTIME[63:32];
-        default:  PRDATA <= '0;
+        default:  PRDATA <= 0;
       endcase
     end 
-    always_ff @(posedge PCLK) 
+    always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) begin
-        MSIP <= 1'b0;
-        MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
+        MSIP <= 0;
+        MTIMECMP <= 0;
+        // MTIMECMP is not reset ***?
       end else if (memwrite) begin
         if (entry == 16'h0000) MSIP <= PWDATA[0];
         if (entry == 16'h4000) 
-          for(j=0;j<P.XLEN/8;j++)
+          for(j=0;j<`XLEN/8;j++)
             if(PSTRB[j])
               MTIMECMP[j*8 +: 8] <= PWDATA[j*8 +: 8];
         if (entry == 16'h4004) 
-          for(j=0;j<P.XLEN/8;j++)
+          for(j=0;j<`XLEN/8;j++)
             if(PSTRB[j])
               MTIMECMP[32 + j*8 +: 8] <= PWDATA[j*8 +: 8];
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
@@ -131,17 +128,17 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
 
 // eventually replace MTIME logic below with timereg
 //     timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done);
-    always_ff @(posedge PCLK) 
+    always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) begin
-        MTIME <= '0;
+        MTIME <= 0;
         // MTIMECMP is not reset
       end else if (memwrite & (entry == 16'hBFF8)) begin
-        for(i=0;i<P.XLEN/8;i++)
+        for(i=0;i<`XLEN/8;i++)
           if(PSTRB[i])
             MTIME[i*8 +: 8] <= PWDATA[i*8 +: 8];
       end else if (memwrite & (entry == 16'hBFFC)) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        for(i=0;i<P.XLEN/8;i++)
+        for(i=0;i<`XLEN/8;i++)
           if(PSTRB[i])
             MTIME[32 + i*8 +: 8]<= PWDATA[i*8 +: 8];
       end else MTIME <= MTIME + 1;
@@ -154,39 +151,37 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
 
 endmodule
 
-/*
-module timeregsync  import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, resetn, 
-  input  logic              we0, we1,
-  input  logic [P.XLEN-1:0] wd,
-  output logic [63:0]       q);
+module timeregsync(
+  input  logic clk, resetn, 
+  input  logic             we0, we1,
+  input  logic [`XLEN-1:0] wd,
+  output logic [63:0]      q);
 
-  if (P.XLEN==64) 
+  if (`XLEN==64) 
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn)  q <= '0;
+      if (~resetn) q <= 0;
       else if (we0) q <= wd;
       else          q <= q + 1;
   else
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn)  q <= '0;
+      if (~resetn) q <= 0;
       else if (we0) q[31:0] <= wd;
       else if (we1) q[63:32] <= wd;
       else          q <= q + 1;
 endmodule
 
+module timereg(
+  input  logic PCLK, PRESETn, TIMECLK,
+  input  logic             we0, we1,
+  input  logic [`XLEN-1:0] PWDATA,
+  output logic [63:0]      MTIME,
+  output logic             done);
 
-module timereg  import cvw::*;  #(parameter cvw_t P) (
-  input  logic              PCLK, PRESETn, TIMECLK,
-  input  logic              we0, we1,
-  input  logic [P.XLEN-1:0] PWDATA,
-  output logic [63:0]       MTIME,
-  output logic              done);
-
-//  if (P.TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
+//  if (`TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
   if (1) begin:timereg // use PCLK for MTIME
     timregsync timeregsync(.clk(PCLK), .resetn(PRESETn), .we0, .we1, .wd(PWDATA), .q(MTIME));
-    assign done = 1;   // immediately completes
-  end else begin       // use asynchronous TIMECLK 
+    assign done = 1; // immediately completes
+  end else begin // use asynchronous TIMECLK 
     // TIME counter runs on TIMECLK but bus interface runs on PCLK
     // Need to synchronize reads and writes
     // This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits
@@ -194,15 +189,15 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
     // Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
     // Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
     // The handshake signals are synchronized in each direction across the interface
-    // There is no back pressure on instructions, so if multiple counter writes occur too close together, the results are unpredictable.
+    // There is no back pressure on instructions, so if multiple counter writes occur ***
 
     logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
-    logic [P.XLEN-1:0] wd_stored;
+    logic [`XLEN-1:0] wd_stored;
     logic [63:0] time_int, time_int_gc, time_gc, MTIME_GC;
 
     // When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
     // When the acknowledge falls, the transaction is done and the system is ready for another write.
-    // When adding asynchronous timebase, look at redoing this assuming write enable and data are held rather than pulsed.
+    // ***look at redoing this assuming write enable and data are held rather than pulsed.
     always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) 
         req <= 0; // don't bother resetting wd
@@ -221,7 +216,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
     // synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered
     sync async(PCLK, req_sync, ack);
 
-    timeregsync #(P) timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
+    timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
     binarytogray b2g(time_int, time_int_gc);
     flop gcreg(TIMECLK, time_int_gc, time_gc);
 
@@ -230,7 +225,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
   end
 endmodule
 
-module binarytogray #(parameter N) (
+module binarytogray #(parameter N = `XLEN) (
   input  logic [N-1:0] b,
   output logic [N-1:0] g);
 
@@ -239,7 +234,7 @@ module binarytogray #(parameter N) (
   assign g = b ^ {1'b0, b[N-1:1]};
 endmodule
 
-module graytobinary #(parameter N) (
+module graytobinary #(parameter N = `XLEN) (
   input  logic [N-1:0] g,
   output logic [N-1:0] b);
 
@@ -251,4 +246,3 @@ module graytobinary #(parameter N) (
       assign b[i] = g[i] ^ b[i+1];
     end
 endmodule
-*/
diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv
new file mode 100644
index 000000000..7a8ac3c14
--- /dev/null
+++ b/pipelined/src/uncore/gpio_apb.sv
@@ -0,0 +1,156 @@
+///////////////////////////////////////////
+// gpio_apb.sv
+//
+// Written: David_Harris@hmc.edu 14 January 2021
+// Modified: bbracker@hmc.edu 15 Apr. 2021
+//
+// Purpose: General Purpose I/O peripheral
+//   See FE310-G002-Manual-v19p05 for specifications
+//   No interrupts, drive strength, or pull-ups supported
+// 
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module gpio_apb (
+  input  logic              PCLK, PRESETn,
+  input  logic              PSEL,
+  input  logic [7:0]        PADDR, 
+  input  logic [`XLEN-1:0]  PWDATA,
+  input  logic [`XLEN/8-1:0] PSTRB,
+  input  logic              PWRITE,
+  input  logic              PENABLE,
+  output logic [`XLEN-1:0]  PRDATA,
+  output logic              PREADY,
+  input  logic [31:0]       iof0, iof1,
+  input  logic [31:0]       GPIOPinsIn,
+  output logic [31:0]       GPIOPinsOut, GPIOPinsEn,
+  output logic              GPIOIntr
+);
+
+  logic [31:0]              input0d, input1d, input2d, input3d;
+  logic [31:0]              input_val, input_en, output_en, output_val;
+  logic [31:0]              rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; 
+  logic [31:0]              out_xor, iof_en, iof_sel, iof_out, gpio_out;
+  logic [7:0]               entry;
+  logic [31:0]              Din, Dout;
+  logic                     memwrite;
+  
+  // APB I/O
+  assign entry = {PADDR[7:2],2'b00};  // 32-bit word-aligned accesses
+  assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
+  assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
+
+  // account for subword read/write circuitry
+  // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
+  //    (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
+  if (`XLEN == 64) begin
+    assign Din =    entry[2] ? PWDATA[63:32] : PWDATA[31:0];
+    assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
+  end else begin // 32-bit
+    assign Din = PWDATA[31:0];
+    assign PRDATA = Dout;
+  end
+
+  // register access
+  always_ff @(posedge PCLK, negedge PRESETn)
+    if (~PRESETn) begin // asynch reset
+      input_en <= 0;
+      output_en <= 0;
+      // *** synch reset not yet implemented [DH: can we delete this comment?  Check if a sync reset is required]
+      output_val <= #1 0;
+      rise_ie <= #1 0;
+      rise_ip <= #1 0;
+      fall_ie <= #1 0;
+      fall_ip <= #1 0;
+      high_ie <= #1 0;
+      high_ip <= #1 0;
+      low_ie <= #1 0;
+      low_ip <= #1 0;
+      iof_en <= #1 0;
+      iof_sel <= #1 0;
+      out_xor <= #1 0;
+    end else begin     // writes
+        // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
+        /* verilator lint_off CASEINCOMPLETE */
+      if (memwrite) 
+        case(entry)
+          8'h04: input_en <= #1 Din;
+          8'h08: output_en <= #1 Din;
+          8'h0C: output_val <= #1 Din;
+          8'h18: rise_ie <= #1 Din;
+          8'h20: fall_ie <= #1 Din;
+          8'h28: high_ie <= #1 Din;
+          8'h30: low_ie  <= #1 Din;
+          8'h38: iof_en  <= #1 Din;
+          8'h3C: iof_sel <= #1 Din;
+          8'h40: out_xor <= #1 Din;
+        endcase
+        /* verilator lint_on CASEINCOMPLETE */
+
+      // interrupts can be cleared by writing corresponding bits to a register
+      if (memwrite & entry == 8'h1C)   rise_ip <= rise_ip & ~Din;
+      else                             rise_ip <= rise_ip | (input2d & ~input3d);
+      if (memwrite & (entry == 8'h24)) fall_ip <= fall_ip & ~Din;
+      else                             fall_ip <= fall_ip | (~input2d & input3d);
+      if (memwrite & (entry == 8'h2C)) high_ip <= high_ip & ~Din;
+      else                             high_ip <= high_ip | input3d;
+      if (memwrite & (entry == 8'h34)) low_ip  <= low_ip  & ~Din;
+      else                             low_ip  <= low_ip  | ~input3d;
+
+      case(entry) // flop to sample inputs
+        8'h00: Dout <= #1 input_val;
+        8'h04: Dout <= #1 input_en;
+        8'h08: Dout <= #1 output_en;
+        8'h0C: Dout <= #1 output_val;
+        8'h18: Dout <= #1 rise_ie;
+        8'h1C: Dout <= #1 rise_ip;
+        8'h20: Dout <= #1 fall_ie;
+        8'h24: Dout <= #1 fall_ip;
+        8'h28: Dout <= #1 high_ie;
+        8'h2C: Dout <= #1 high_ip;
+        8'h30: Dout <= #1 low_ie;
+        8'h34: Dout <= #1 low_ip;
+        8'h38: Dout <= #1 iof_en;
+        8'h3C: Dout <= #1 iof_sel;
+        8'h40: Dout <= #1 out_xor; 
+        default: Dout <= #1 0;
+      endcase
+    end
+
+  // chip i/o
+  // connect OUT to IN for loopback testing
+  if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en;
+  else                     assign input0d = GPIOPinsIn & input_en;
+
+  // synchroninzer for inputs
+  flop #(32) sync1(PCLK,input0d,input1d);
+  flop #(32) sync2(PCLK,input1d,input2d);
+  flop #(32) sync3(PCLK,input2d,input3d);
+  assign input_val = input3d;
+  assign iof_out = iof_sel & iof1 | ~iof_sel & iof0;         // per-bit mux between iof1 and iof0
+  assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
+  assign GPIOPinsOut = gpio_out ^ out_xor;                   // per-bit flip output polarity
+  assign GPIOPinsEn = output_en;
+
+  assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
+endmodule
+
diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv
new file mode 100644
index 000000000..ad9e6f0c1
--- /dev/null
+++ b/pipelined/src/uncore/plic_apb.sv
@@ -0,0 +1,252 @@
+///////////////////////////////////////////
+// plic_apb.sv
+//
+// Written: bbracker@hmc.edu 18 January 2021
+// Modified: 
+//
+// Purpose: Platform-Level Interrupt Controller
+//   Based on RISC-V spec (https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
+//   With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
+//   Supports only 1 target core and only a global threshold.
+//   This PLIC implementation serves as both the PLIC Gateways and PLIC Core.
+//   It assumes interrupt sources are level-triggered wires.
+//
+// Documentation: RISC-V System on Chip Design Chapter 15
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+`define N `PLIC_NUM_SRC
+// number of interrupt sources
+// does not include source 0, which does not connect to anything according to spec
+// up to 63 sources supported; in the future, allow up to 1023 sources
+
+`define C 2
+// number of conexts
+// hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts
+
+module plic_apb (
+  input  logic             PCLK, PRESETn,
+  input  logic             PSEL,
+  input  logic [27:0]      PADDR, 
+  input  logic [`XLEN-1:0] PWDATA,
+  input  logic [`XLEN/8-1:0] PSTRB,
+  input  logic             PWRITE,
+  input  logic             PENABLE,
+  output logic [`XLEN-1:0] PRDATA,
+  output logic             PREADY,
+  input  logic             UARTIntr,GPIOIntr,
+    (* mark_debug = "true" *)  output logic             MExtInt, SExtInt
+);
+
+  logic memwrite, memread;
+  logic [23:0] entry;
+  (* mark_debug = "true" *) logic [31:0] Din, Dout;
+
+  // context-independent signals
+    (* mark_debug = "true" *)  logic [`N:1]      requests;
+    (* mark_debug = "true" *)  logic [`N:1][2:0] intPriority;
+    (* mark_debug = "true" *)  logic [`N:1]      intInProgress, intPending, nextIntPending;
+  
+  // context-dependent signals
+  (* mark_debug = "true" *) logic [`C-1:0][2:0]       intThreshold;
+    (* mark_debug = "true" *)  logic [`C-1:0][`N:1]      intEn;
+  (* mark_debug = "true" *) logic [`C-1:0][5:0]       intClaim; // ID's are 6 bits if we stay within 63 sources
+    (* mark_debug = "true" *)  logic [`C-1:0][7:1][`N:1] irqMatrix;
+  (* mark_debug = "true" *) logic [`C-1:0][7:1]       priorities_with_irqs;
+  (* mark_debug = "true" *) logic [`C-1:0][7:1]       max_priority_with_irqs;
+  (* mark_debug = "true" *) logic [`C-1:0][`N:1]      irqs_at_max_priority;
+  (* mark_debug = "true" *) logic [`C-1:0][7:1]       threshMask;
+
+  // =======
+  // AHB I/O
+  // =======
+
+  assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
+  assign memread  = ~PWRITE & PSEL;  // read at start of access phase.  PENABLE hasn't set up before this
+  assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond
+  assign entry = {PADDR[23:2],2'b0};
+
+  // account for subword read/write circuitry
+  // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
+  if (`XLEN == 64) begin
+    assign Din    = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
+    assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
+  end else begin // 32-bit
+    assign PRDATA = Dout;
+    assign Din    = PWDATA[31:0];
+  end
+
+  // ==================
+  // Register Interface
+  // ==================
+  always @(posedge PCLK,negedge PRESETn) begin
+    // resetting
+    if (~PRESETn) begin
+      intPriority   <= #1 {`N{3'b0}};
+      intEn         <= #1 {2{`N'b0}};
+      intThreshold  <= #1 {2{3'b0}};
+      intInProgress <= #1 `N'b0;
+    // writing
+    end else begin
+      if (memwrite)
+        casez(entry)
+          24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0];
+          `ifdef PLIC_NUM_SRC_LT_32 // eventually switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources
+          24'h002000: intEn[0][`N:1] <= #1 Din[`N:1];
+          24'h002080: intEn[1][`N:1] <= #1 Din[`N:1];
+          `endif
+          `ifndef PLIC_NUM_SRC_LT_32
+          24'h002000: intEn[0][31:1] <= #1 Din[31:1];
+          24'h002004: intEn[0][`N:32] <= #1 Din[31:0];
+          24'h002080: intEn[1][31:1] <= #1 Din[31:1];
+          24'h002084: intEn[1][`N:32] <= #1 Din[31:0];
+          `endif
+          24'h200000: intThreshold[0] <= #1 Din[2:0];
+          24'h200004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h201000: intThreshold[1] <= #1 Din[2:0];
+          24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+        endcase
+      // Read synchronously because a read can have side effect of changing intInProgress
+      if (memread)
+        casez(entry)
+          24'h000000: Dout <= #1 32'b0;  // there is no intPriority[0]
+          24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};		  
+          `ifdef PLIC_NUM_SRC_LT_32
+          24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
+          24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};
+          24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0};
+          `endif
+          `ifndef PLIC_NUM_SRC_LT_32
+          24'h001000: Dout <= #1 {intPending[31:1],1'b0};
+          24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]};
+          24'h002000: Dout <= #1 {intEn[0][31:1],1'b0};
+          24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]};
+          24'h002080: Dout <= #1 {intEn[0][31:1],1'b0};
+          24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]};
+          `endif
+          24'h200000: Dout <= #1 {29'b0,intThreshold[0]};
+          24'h200004: begin
+            Dout <= #1 {26'b0,intClaim[0]};
+            intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
+          end
+          24'h201000: Dout <= #1 {29'b0,intThreshold[1]};
+          24'h201004: begin
+            Dout <= #1 {26'b0,intClaim[1]};
+            intInProgress <= #1 intInProgress | (`N'b1 << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
+          end
+          default: Dout <= #1 32'h0; // invalid access
+        endcase
+      else Dout <= #1 32'h0;
+   end
+  end
+
+  // connect sources to requests
+  always_comb begin
+    requests = `N'b0;
+    `ifdef PLIC_GPIO_ID
+      requests[`PLIC_GPIO_ID] = GPIOIntr;
+    `endif
+    `ifdef PLIC_UART_ID
+      requests[`PLIC_UART_ID] = UARTIntr;
+    `endif
+  end
+
+  // pending interrupt requests
+  assign nextIntPending = (intPending | requests) & ~intInProgress; 
+  flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
+
+  // context-dependent signals
+  genvar ctx;
+  for (ctx=0; ctx<`C; ctx++) begin
+    // request matrix 
+    //   priority level (rows) X source ID (columns)
+    //
+    //   irqMatrix[ctx][pri][src] is high if source <src>
+    //   has priority level <pri> and has an "active" interrupt request
+    //   ("active" meaning it is enabled in context <ctx> and is pending)
+    genvar src, pri;
+    for (pri=1; pri<=7; pri++) begin
+      for (src=1; src<=`N; src++) begin
+        assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src];
+      end
+    end
+
+    // which prority levels have one or more active requests?
+    assign priorities_with_irqs[ctx][7:1] = {
+      |irqMatrix[ctx][7],
+      |irqMatrix[ctx][6],
+      |irqMatrix[ctx][5],
+      |irqMatrix[ctx][4],
+      |irqMatrix[ctx][3],
+      |irqMatrix[ctx][2],
+      |irqMatrix[ctx][1]
+    }; 
+
+    // get the highest priority level that has active requests
+    assign max_priority_with_irqs[ctx][7:1] = {
+      priorities_with_irqs[ctx][7],
+      priorities_with_irqs[ctx][6] & ~|priorities_with_irqs[ctx][7],
+      priorities_with_irqs[ctx][5] & ~|priorities_with_irqs[ctx][7:6],
+      priorities_with_irqs[ctx][4] & ~|priorities_with_irqs[ctx][7:5],
+      priorities_with_irqs[ctx][3] & ~|priorities_with_irqs[ctx][7:4],
+      priorities_with_irqs[ctx][2] & ~|priorities_with_irqs[ctx][7:3],
+      priorities_with_irqs[ctx][1] & ~|priorities_with_irqs[ctx][7:2]
+    };
+
+    // of the sources at the highest priority level that has active requests,
+    // which sources have active requests?
+    assign irqs_at_max_priority[ctx][`N:1] =
+      ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
+      ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
+      ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
+      ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
+      ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
+      ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
+      ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
+
+    // of the sources at the highest priority level that has active requests,
+    // choose the source with the lowest source ID to be the most urgent
+    // and set intClaim to the source ID of the most urgent active request
+    integer k;
+    always_comb begin
+      intClaim[ctx] = 6'b0;
+      for (k=`N; k>0; k--) begin
+        if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0];
+      end
+    end
+    
+    // create threshold mask
+    always_comb begin
+      threshMask[ctx][7] = (intThreshold[ctx] != 7);
+      threshMask[ctx][6] = (intThreshold[ctx] != 6) & threshMask[ctx][7];
+      threshMask[ctx][5] = (intThreshold[ctx] != 5) & threshMask[ctx][6];
+      threshMask[ctx][4] = (intThreshold[ctx] != 4) & threshMask[ctx][5];
+      threshMask[ctx][3] = (intThreshold[ctx] != 3) & threshMask[ctx][4];
+      threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3];
+      threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2];
+    end
+  end
+  // is the max priority > threshold?
+  // would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
+  assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
+  assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
+endmodule
+
diff --git a/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv
similarity index 56%
rename from src/uncore/ram_ahb.sv
rename to pipelined/src/uncore/ram_ahb.sv
index 60c870138..09d1d6a1e 100644
--- a/src/uncore/ram_ahb.sv
+++ b/pipelined/src/uncore/ram_ahb.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: On-chip RAM, external to core, with AHB interface
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 6
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,54 +26,57 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ram_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter RANGE = 65535, PRELOAD = 0) (
-  input  logic                 HCLK, HRESETn, 
-  input  logic                 HSELRam,
-  input  logic [P.PA_BITS-1:0] HADDR,
-  input  logic                 HWRITE,
-  input  logic                 HREADY,
-  input  logic [1:0]           HTRANS,
-  input  logic [P.XLEN-1:0]    HWDATA,
-  input  logic [P.XLEN/8-1:0]  HWSTRB,
-  output logic [P.XLEN-1:0]    HREADRam,
-  output logic                 HRESPRam, HREADYRam
+`include "wally-config.vh"
+`define RAM_LATENCY 0
+
+module ram_ahb #(parameter BASE=0, RANGE = 65535) (
+  input  logic             HCLK, HRESETn, 
+  input  logic             HSELRam,
+  input  logic [`PA_BITS-1:0]      HADDR,
+  input  logic             HWRITE,
+  input  logic             HREADY,
+  input  logic [1:0]       HTRANS,
+  input  logic [`XLEN-1:0] HWDATA,
+  input  logic [`XLEN/8-1:0] HWSTRB,
+  output logic [`XLEN-1:0] HREADRam,
+  output logic             HRESPRam, HREADYRam
 );
 
-  localparam                   ADDR_WIDTH = $clog2(RANGE/8);
-  localparam                   OFFSET = $clog2(P.XLEN/8);   
+  localparam               ADDR_WIDTH = $clog2(RANGE/8);
+  localparam               OFFSET = $clog2(`XLEN/8);   
 
-  logic [P.XLEN/8-1:0]         ByteMask;
-  logic [P.PA_BITS-1:0]        HADDRD, RamAddr;
-  logic                        initTrans;
-  logic                        memwrite, memwriteD, memread;
-  logic                        nextHREADYRam;
-  logic                        DelayReady;
+  logic [`XLEN/8-1:0] 	   ByteMask;
+  logic [`PA_BITS-1:0]     HADDRD, RamAddr;
+  logic				             initTrans;
+  logic				             memwrite, memwriteD, memread;
+  logic                    nextHREADYRam;
+  logic                    DelayReady;
 
   // a new AHB transactions starts when HTRANS requests a transaction, 
   // the peripheral is selected, and the previous transaction is completing
   assign initTrans = HREADY & HSELRam & HTRANS[1] ; 
-  assign memwrite  = initTrans & HWRITE;  
-  assign memread   = initTrans & ~HWRITE;
+  assign memwrite = initTrans & HWRITE;  
+  assign memread = initTrans & ~HWRITE;
  
   flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); 
-  flopenr #(P.PA_BITS)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
+  flopenr #(`PA_BITS)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
 
   // Stall on a read after a write because the RAM can't take both adddresses on the same cycle
   assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady;
   flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
 
-  assign HRESPRam = 1'b0; // OK
+  assign HRESPRam = 0; // OK
 
   // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
-  mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
+  mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
 
   // single-ported RAM
-  ram1p1rwbe #(P.USE_SRAM, RANGE/8, P.XLEN, PRELOAD) memory(.clk(HCLK), .ce(1'b1), 
+  ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), 
     .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
   
+
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
-  if(P.RAM_LATENCY > 0) begin
+  if(`RAM_LATENCY > 0) begin
     logic [7:0]       NextCycle, Cycle;
     logic             CntEn, CntRst;
     logic             CycleFlag;
@@ -86,25 +88,27 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
     statetype CurrState, NextState;
     
     always_ff @(posedge HCLK)
-      if (~HRESETn)    CurrState <= READY;
-      else             CurrState <= NextState;  
+      if (~HRESETn)    CurrState <= #1 READY;
+      else CurrState <= #1 NextState;  
 
     always_comb begin
-    case(CurrState)
-      READY: if(initTrans & ~CycleFlag) NextState = DELAY;
-        else                            NextState = READY;
-        DELAY: if(CycleFlag)            NextState = READY;
-    else                                NextState = DELAY;
-      default:                          NextState = READY;
-    endcase
+	  case(CurrState)
+	    READY: if(initTrans & ~CycleFlag) NextState = DELAY;
+        else                          NextState = READY;
+        DELAY: if(CycleFlag)                  NextState = READY;
+		else                          NextState = DELAY;
+	    default:                                      NextState = READY;
+	  endcase
     end
 
-    assign CycleFlag = Cycle == P.RAM_LATENCY[7:0];
+    assign CycleFlag = Cycle == `RAM_LATENCY;
     assign CntEn = NextState == DELAY;
     assign DelayReady = NextState == DELAY;
     assign CntRst = NextState == READY;
   end else begin
-    assign DelayReady = 1'b0;
+    assign DelayReady = 0;
   end
-
+  
+  
 endmodule
+  
diff --git a/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv
similarity index 67%
rename from src/uncore/rom_ahb.sv
rename to pipelined/src/uncore/rom_ahb.sv
index 63f6e9716..b009185ba 100644
--- a/src/uncore/rom_ahb.sv
+++ b/pipelined/src/uncore/rom_ahb.sv
@@ -6,10 +6,9 @@
 //
 // Purpose: On-chip ROM, external to core
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 6
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -27,25 +26,27 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module rom_ahb import cvw::*;  #(parameter cvw_t P, 
-                                 parameter RANGE = 65535, PRELOAD = 0) (
-  input  logic                 HCLK, HRESETn, 
-  input  logic                 HSELRom,
-  input  logic [P.PA_BITS-1:0] HADDR,
-  input  logic                 HREADY,
-  input  logic [1:0]           HTRANS,
-  output logic [P.XLEN-1:0]    HREADRom,
-  output logic                 HRESPRom, HREADYRom
+`include "wally-config.vh"
+
+module rom_ahb #(parameter BASE=0, RANGE = 65535) (
+  input  logic             HCLK, HRESETn, 
+  input  logic             HSELRom,
+  input  logic [`PA_BITS-1:0]  HADDR,
+  input  logic             HREADY,
+  input  logic [1:0]       HTRANS,
+  output logic [`XLEN-1:0] HREADRom,
+  output logic             HRESPRom, HREADYRom
 );
 
   localparam ADDR_WIDTH = $clog2(RANGE/8);
-  localparam OFFSET     = $clog2(P.XLEN/8);   
+  localparam OFFSET = $clog2(`XLEN/8);   
  
   // Never stalls
   assign HREADYRom = 1'b1;
-  assign HRESPRom  = 1'b0; // OK
+  assign HRESPRom = 0; // OK
 
   // single-ported ROM
-  rom1p1r #(ADDR_WIDTH, P.XLEN, PRELOAD)
+  rom1p1r #(ADDR_WIDTH, `XLEN, `FPGA)
     memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule
+  
diff --git a/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
similarity index 51%
rename from src/uncore/uartPC16550D.sv
rename to pipelined/src/uncore/uartPC16550D.sv
index 3639fe8d5..3666a4493 100644
--- a/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -7,16 +7,15 @@
 // Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs
 //          Emulates interface of Texas Instruments PC16550D
 //          https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf
-//          Compatible with UART in Imperas Virtio model
+//          Compatible with UART in Imperas Virtio model ***
 //
 //  Compatible with most of PC16550D with the following known exceptions:
 //   Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
-//   Timeout not yet implemented
+//   Timeout not yet implemented***
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 15
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -34,181 +33,170 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+`include "wally-config.vh"
 /* verilator lint_off UNOPTFLAT */
 
-module uartPC16550D #(parameter UART_PRESCALE) (
-  // Processor Interface
-  input  logic       PCLK, PRESETn,                  // UART clock and active low reset
-  input  logic [2:0] A,                              // address input (8 registers)
-  input  logic [7:0] Din,                            // 8-bit WriteData
-  output logic [7:0] Dout,                           // 8-bit ReadData
-  input  logic       MEMRb, MEMWb,                   // Active low memory read/write
-  output logic       INTR, TXRDYb, RXRDYb,           // interrupt and ready lines
-  // Clocks
-  output logic       BAUDOUTb,                       // active low baud clock
-  input logic        RCLK,                           // usually BAUDOUTb tied to RCLK externally
-  // E1A Driver
-  input  logic       SIN, DSRb, DCDb, CTSb, RIb,     // UART external serial and flow-control inputs
-  output logic       SOUT, RTSb, DTRb, OUT1b, OUT2b  // UART external serial and flow-control outputs
+module uartPC16550D(
+	// Processor Interface
+	input  logic 	      PCLK, PRESETn,                  // UART clock and active low reset
+	input  logic [2:0]  A,                              // address input (8 registers)
+	input  logic [7:0]  Din,                            // 8-bit WriteData
+	output logic [7:0]  Dout,                           // 8-bit ReadData
+	input  logic 	      MEMRb, MEMWb,                   // Active low memory read/write
+	output logic 	      INTR, TXRDYb, RXRDYb,           // interrupt and ready lines
+	// Clocks
+	output logic 	      BAUDOUTb,                       // active low baud clock
+	input logic 	      RCLK,                           // usually BAUDOUTb tied to RCLK externally
+	// E1A Driver
+	input  logic 	      SIN, DSRb, DCDb, CTSb, RIb,     // UART external serial and flow-control inputs
+	output logic 	      SOUT, RTSb, DTRb, OUT1b, OUT2b  // UART external serial and flow-control outputs
 );
 
-  // register map
-  localparam UART_DLL_RBR = 3'b000;
-  localparam UART_DLM_IER = 3'b001;
-  localparam UART_IIR = 3'b010;
-  localparam UART_LCR = 3'b011;
-  localparam UART_MCR = 3'b100;
-  localparam UART_LSR = 3'b101;
-  localparam UART_MSR = 3'b110;
-  localparam UART_SCR = 3'b111;
-  
   // transmit and receive states 
   typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
   // Registers
-  logic [10:0] RBR;
-  logic [7:0]  FCR, LCR, LSR, SCR, DLL, DLM;
-  logic [3:0]  IER, MSR;
-  logic [4:0]  MCR;
+   (* mark_debug = "true" *)  logic [10:0] RBR;
+   (* mark_debug = "true" *)  logic [7:0]  FCR, LCR, LSR, SCR, DLL, DLM;
+   (* mark_debug = "true" *)  logic [3:0]  IER, MSR;
+   (* mark_debug = "true" *)  logic [4:0]  MCR;
 
   // Syncrhonized and delayed UART signals
-  logic        SINd, DSRbd, DCDbd, CTSbd, RIbd;
-  logic        SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync;
-  logic        DSRb2, DCDb2, CTSb2, RIb2;
-  logic        SOUTbit;
+  logic 	   SINd, DSRbd, DCDbd, CTSbd, RIbd;
+  logic 	   SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync;
+  logic 	   DSRb2, DCDb2, CTSb2, RIb2;
+  logic 	   SOUTbit;
 
   // Control signals
-  logic        loop; // loopback mode
-  logic        DLAB; // Divisor Latch Access Bit (LCR bit 7)
+  logic 	   loop; // loopback mode
+  logic 	   DLAB; // Divisor Latch Access Bit (LCR bit 7)
 
   // Baud and rx/tx timing
-  logic                         baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
-  logic [16+UART_PRESCALE-1:0]  baudcount;
-  logic [3:0]                   rxoversampledcnt, txoversampledcnt;  // count oversampled-by-16
-  logic [3:0]                   rxbitsreceived, txbitssent;
-  statetype rxstate, txstate;
+  (* mark_debug = "true" *) logic 	   baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
+  logic [16+`UART_PRESCALE-1:0] baudcount;
+  logic [3:0] 					rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
+  logic [3:0] 					rxbitsreceived, txbitssent;
+   (* mark_debug = "true" *)  statetype rxstate, txstate;
 
   // shift registrs and FIFOs
-  logic [9:0]                   rxshiftreg;
-  logic [10:0]                  rxfifo[15:0];
-  logic [7:0]                   txfifo[15:0];
-  logic [4:0]                   rxfifotailunwrapped;
-  logic [3:0]                   rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
-  logic [3:0]                   rxfifoentries;
-  logic [3:0]                   rxbitsexpected, txbitsexpected;
+  logic [9:0] 					rxshiftreg;
+  (* mark_debug = "true" *) logic [10:0] 					rxfifo[15:0];
+  (* mark_debug = "true" *) logic [7:0] 					txfifo[15:0];
+  logic [4:0] 					rxfifotailunwrapped;
+(* mark_debug = "true" *)  logic [3:0] 					rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
+(* mark_debug = "true" *)  logic [3:0] 					rxfifoentries, txfifoentries;
+  logic [3:0] 					rxbitsexpected, txbitsexpected;
 
   // receive data
-  logic [10:0]                  RXBR;
-  logic [9:0]                   rxtimeoutcnt;
-  logic                         rxcentered;
-  logic                         rxparity, rxparitybit, rxstopbit;
-  logic                         rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
-  logic                         rxdataready;
-  logic                         rxfifoempty, rxfifotriggered, rxfifotimeout;
-  logic                         rxfifodmaready;
-  logic [8:0]                   rxdata9;
-  logic [7:0]                   rxdata;
-  logic [15:0]                  RXerrbit, rxfullbit;
-  logic [31:0]                  rxfullbitunwrapped;
+   (* mark_debug = "true" *)  logic [10:0] 					RXBR;
+  (* mark_debug = "true" *) logic [9:0] 					rxtimeoutcnt;
+  logic 						rxcentered;
+  logic 						rxparity, rxparitybit, rxstopbit;
+   (* mark_debug = "true" *)  logic 						rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
+(* mark_debug = "true" *)  logic 						rxdataready;
+(* mark_debug = "true" *)  logic 						rxfifoempty, rxfifotriggered, rxfifotimeout;
+  logic 						rxfifodmaready;
+  logic [8:0] 					rxdata9;
+  (* mark_debug = "true" *) logic [7:0] 					rxdata;
+  (* mark_debug = "true" *) logic [15:0] 					RXerrbit, rxfullbit;
+  (* mark_debug = "true" *) logic [31:0] 					rxfullbitunwrapped;
 
   // transmit data
-  logic [7:0]                   TXHR, nexttxdata;
-  logic [11:0]                  txdata, txsr;
-  logic                         txnextbit, txhrfull, txsrfull;
-  logic                         txparity;
-  logic                         txfifoempty, txfifofull, txfifodmaready;
+  logic [7:0] 					TXHR, nexttxdata;
+  (* mark_debug = "true" *) logic [11:0] 					txdata, txsr;
+  (* mark_debug = "true" *) logic 						txnextbit, txhrfull, txsrfull;
+  logic 						txparity;
+  (* mark_debug = "true" *) logic 						txfifoempty, txfifofull, txfifodmaready;
 
   // control signals
-  logic                         fifoenabled, fifodmamodesel, evenparitysel;
+(* mark_debug = "true" *)  logic 						fifoenabled, fifodmamodesel, evenparitysel;
 
   // interrupts
-  logic                         RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
-  logic                         THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
-  logic                         rxdataavailintr, modemstatusintr, intrpending;
-  logic [2:0]                   intrID;
+(* mark_debug = "true" *)  logic 						RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
+(* mark_debug = "true" *)  logic 						THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
+(* mark_debug = "true" *)  logic 						rxdataavailintr, modemstatusintr, intrpending;
+(* mark_debug = "true" *)  logic [2:0] 					intrID;
 
-  logic                         baudpulseComb;
-  logic                         HeadPointerLastMove;
+  logic 						baudpulseComb;
+  logic 						HeadPointerLastMove;
 
   ///////////////////////////////////////////
   // Input synchronization: 2-stage synchronizer
   ///////////////////////////////////////////
-  
   always_ff @(posedge PCLK) begin
-    {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb};
-    {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
-                            {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
-    {DSRb2, DCDb2, CTSb2, RIb2} <= {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
+    {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
+    {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
+														{SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
+    {DSRb2, DCDb2, CTSb2, RIb2} <= #1 {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
   end
 
   ///////////////////////////////////////////
   // Register interface (Table 1, note some are read only and some write only)
   ///////////////////////////////////////////
-  
-  always_ff @(posedge PCLK) 
+  always_ff @(posedge PCLK, negedge PRESETn) 
     if (~PRESETn) begin // Table 3 Reset Configuration
-      IER <= 4'b0;
-      FCR <= 8'b0;
-      LCR <= 8'b11; // PC16550D datasheet resets to 0, but all modern systems will use 8-bit data.  Wally resets to 3 for 8-bit data.
-      MCR <= 5'b0;
-      LSR <= 8'b0110_0000;
-      MSR <= 4'b0;
-      DLL <= 8'd1; // this cannot be zero with DLM also zero.
-      DLM <= 8'b0;
-      SCR <= 8'b0; // not strictly necessary to reset
+      IER <= #1 4'b0;
+      FCR <= #1 8'b0;
+      if (`QEMU) LCR <= #1 8'b0; else LCR <= #1 8'b11; // fpga only **** BUG
+      MCR <= #1 5'b0;
+      LSR <= #1 8'b01100000;
+      MSR <= #1 4'b0;
+	    DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
+	    DLM <= #1 8'b0;
+      SCR <= #1 8'b0; // not strictly necessary to reset
     end else begin
       if (~MEMWb) begin
         /* verilator lint_off CASEINCOMPLETE */
         case (A)
-          UART_DLL_RBR: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section
-          UART_DLM_IER: if (DLAB) DLM <= Din; else IER <= Din[3:0];
-          UART_IIR: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
-          UART_LCR: LCR <= Din;
-          UART_MCR: MCR <= Din[4:0];
-          UART_SCR: SCR <= Din;
+          3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
+          3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
+          3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
+          3'b011: LCR <= #1 Din;
+          3'b100: MCR <= #1 Din[4:0];
+          3'b111: SCR <= #1 Din;
         endcase
         /* verilator lint_on CASEINCOMPLETE */
       end
 
       // Line Status Register (8.6.3)
       // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay.
-      if (~MEMWb & (A == UART_LSR))
-        LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3
+      if (~MEMWb & (A == 3'b101))
+        LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3
       else begin
-        LSR[0]   <= rxdataready; // Data ready
-        LSR[1]   <= (LSR[1] | RXBR[10]) & ~squashRXerrIP; // overrun error
-        LSR[2]   <= (LSR[2] | RXBR[9])  & ~squashRXerrIP; // parity error
-        LSR[3]   <= (LSR[3] | RXBR[8])  & ~squashRXerrIP; // framing error
-        LSR[4]   <= (LSR[4] | rxbreak)  & ~squashRXerrIP; // break indicator
-        LSR[5]   <= THRE; // THRE
-        LSR[6]   <= ~txsrfull & THRE; //  TEMT
-        if (rxfifohaserr) LSR[7] <= 1'b1; // any bits in FIFO have error
+        LSR[0] <= #1 rxdataready; // Data ready
+        LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error
+        LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error
+        LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error
+        LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator
+        LSR[5] <= #1 THRE; // THRE
+        LSR[6] <= #1 ~txsrfull & THRE; //  TEMT
+        if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error
       end
 
       // Modem Status Register (8.6.8)
-      if (~MEMWb & (A == UART_MSR))
-        MSR <= Din[3:0];
-      else if (~MEMRb & (A == UART_MSR)) 
-        MSR <= 4'b0; // Reading MSR clears the flags in MSR bits 3:0
+      if (~MEMWb & (A == 3'b110))
+        MSR <= #1 Din[3:0];
+      else if (~MEMRb & (A == 3'b110)) 
+        MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0
       else begin
-        MSR[0] <= MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
-        MSR[1] <= MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready
-        MSR[2] <= MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator
-        MSR[3] <= MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
+        MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
+        MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready
+        MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator
+        MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
       end
     end
-  
   always_comb
     if (~MEMRb)
       case (A)
-        UART_DLL_RBR: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
-        UART_DLM_IER: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
-        UART_IIR: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
-        UART_LCR: Dout = LCR;
-        UART_MCR: Dout = {3'b000, MCR};
-        UART_LSR: Dout = LSR;
-        UART_MSR: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]};
-        UART_SCR: Dout = SCR;      
+        3'b000: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
+        3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
+        3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
+        3'b011: Dout = LCR;
+        3'b100: Dout = {3'b000, MCR};
+        3'b101: Dout = LSR;
+        // 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; 
+        3'b110: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]};
+        3'b111: Dout = SCR;      
       endcase
     else Dout = 8'b0;
 
@@ -217,28 +205,27 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // consider switching to same fixed-frequency reference clock used for TIME register
   // prescale by factor of 2^UART_PRESCALE to allow for high-frequency reference clock
   // Unlike PC16550D, this unit is hardwired with same rx and tx baud clock
-  // For example, with PCLK = 320 MHz, UART_PRESCALE = 5, DLM = 0, DLL = 65, 
-  // 320 MHz system clock is divided by 65 x 2^5.  The UART clock 16x oversamples
-  // the data, so the baud rate is 320x10^6 / (65 x 2^5 x 16) = 9615 Hz, which is
-  // close enough to 9600 baud to stay synchronized over the duration of one character.
+  // *** add table of scale factors to get 16x uart clk
   ///////////////////////////////////////////
-  always_ff @(posedge PCLK) 
+  // Ross Thompson: Found a bug.  If the baud rate dividers DLM, and DLL are reloaded
+  // the baudcount is not reset to  {DLM, DLL, UART_PRESCALE}
+  always_ff @(posedge PCLK, negedge PRESETn) 
     if (~PRESETn) begin
-      baudcount <= 1;
-      baudpulse <= 1'b0;
+      baudcount <= #1 1;
+      baudpulse <= #1 0;
     end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin
-      baudcount <= 1;
+      baudcount <= #1 1;
     end else begin
       // the baudpulse is too long by 2 clock cycles.
       // This is cause baudpulse is registered adding 1 cycle and
       // baudcount is reset when baudcount equals the threshold {DLM, DLL, UART_PRESCALE}
       // rather than 1 less than that value.  Alternatively the reset value could be 1 rather 
       // than 0.
-      baudpulse <= baudpulseComb;
-      baudcount <= baudpulseComb ? 1 :  baudcount +1;
+      baudpulse <= #1 baudpulseComb;
+      baudcount <= #1 baudpulseComb ? 1 :  baudcount +1;
     end
 
-  assign baudpulseComb = (baudcount == {DLM, DLL, {(UART_PRESCALE){1'b0}}});
+  assign baudpulseComb = (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}});
   
   assign txbaudpulse = baudpulse;
   assign BAUDOUTb = ~baudpulse;
@@ -247,43 +234,43 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   ///////////////////////////////////////////
   // receive timing and control
   ///////////////////////////////////////////
-  
-  always_ff @(posedge PCLK)
+  always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
-      rxoversampledcnt   <= '0;
-      rxstate            <= UART_IDLE;
-      rxbitsreceived     <= '0;
-      rxtimeoutcnt       <= '0;
+      rxoversampledcnt <= #1 0;
+      rxstate <= #1 UART_IDLE;
+      rxbitsreceived <= #1 0;
+      rxtimeoutcnt <= #1 0;
     end else begin
       if (rxstate == UART_IDLE & ~SINsync) begin // got start bit
-        rxstate          <= UART_ACTIVE;
-        rxoversampledcnt <= '0;
-        rxbitsreceived   <= '0;
-        if (~rxfifotimeout) rxtimeoutcnt <= '0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf
+        rxstate <= #1 UART_ACTIVE;
+        rxoversampledcnt <= #1 0;
+        rxbitsreceived <= #1 0;
+        if (~rxfifotimeout) rxtimeoutcnt <= #1 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf
       end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin
-        rxoversampledcnt <= rxoversampledcnt + 4'b1;  // 16x oversampled counter
-        if (rxcentered) rxbitsreceived <= rxbitsreceived + 1;
-        if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle
+        rxoversampledcnt <= #1 rxoversampledcnt + 1;  // 16x oversampled counter
+        if (rxcentered) rxbitsreceived <= #1 rxbitsreceived + 1;
+        if (rxbitsreceived == rxbitsexpected) rxstate <= #1 UART_DONE; // pulse rxdone for a cycle
       end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin
-        if (rxbreak & ~SINsync) rxstate <= UART_BREAK;
-        else rxstate <= UART_IDLE;
+        if (rxbreak & ~SINsync) rxstate <= #1 UART_BREAK;
+        else rxstate <= #1 UART_IDLE;
       end
       // timeout counting
-      if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= '0; // reset timeout on read
-      else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // may not be right
+      if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= #1 0; // reset timeout on read
+      else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
     end
 
-  assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000);     // implies rxstate = UART_ACTIVE      
+  // ***explain why
+  if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10);  // implies rxstate = UART_ACTIVE
+  else      assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000);     // implies rxstate = UART_ACTIVE      
  
   assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit 
   
   ///////////////////////////////////////////
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
-  
-  always_ff @(posedge PCLK)
-    if (~PRESETn) rxshiftreg <= 10'b0000000001; // initialize so that there is a valid stop bit
-    else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit
+  always_ff @(posedge PCLK, negedge PRESETn)
+    if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
+    else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
   assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
   assign rxstopbit = rxshiftreg[0];
   always_comb
@@ -296,51 +283,51 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit
 
   // ERROR CONDITIONS
-  assign rxparity     = ^rxdata;
-  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity
+  assign rxparity = ^rxdata;
+  assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
   assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full 
   assign rxframingerr = ~rxstopbit; // framing error if no stop bit
-  assign rxbreak      = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
+  assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
 
   // receive FIFO and register
-  always_ff @(posedge PCLK)
+  always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
-      rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0; RXBR <= '0;
+      rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
     end else begin
       if (~MEMWb & (A == 3'b010) & Din[1]) begin
-        rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0;
+        rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0;
       end else if (rxstate == UART_DONE) begin
-        RXBR <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
-//        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
-//        if (rxparityerr)  $warning("UART RX Parity Err\n");
-//        if (rxframingerr) $warning("UART RX Framing Err\n");
+        RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
+        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
+        if (rxparityerr) $warning("UART RX Parity Err\n");
+        if (rxframingerr) $warning("UART RX Framing Err\n");
         if (fifoenabled) begin
-          rxfifo[rxfifohead] <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
-          rxfifohead <= rxfifohead + 1'b1;
+          rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
+          rxfifohead <= #1 rxfifohead + 1;
         end
-        rxdataready <= 1'b1;
+        rxdataready <= #1 1;
       end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo 
         if (fifoenabled) begin
-          if (~rxfifoempty) rxfifotail <= rxfifotail + 1;
-          // if (rxfifoempty) rxdataready <= 1'b0;
-          if (rxfifoentries == 1) rxdataready <= 1'b0; // When reading the last entry, data ready becomes zero
+          if (~rxfifoempty) rxfifotail <= #1 rxfifotail + 1;
+          // if (rxfifoempty) rxdataready <= #1 0;
+          if (rxfifoentries == 1) rxdataready <= #1 0; // When reading the last entry, data ready becomes zero
         end else begin
-          rxdataready <= 1'b0;
-          RXBR <= {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
+          rxdataready <= #1 0;
+          RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
         end
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register
         if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
-          rxfifohead <= '0; rxfifotail <= '0;
+          rxfifohead <= #1 0; rxfifotail <= #1 0;
         end
     end
 
   assign rxfifoempty = (rxfifohead == rxfifotail);
-  /* verilator lint_off WIDTH */
+  // verilator lint_off WIDTH
   assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : 
                          (rxfifohead + 16 - rxfifotail);
-  /* verilator lint_on WIDTH */
+  // verilator lint_on WIDTH
   assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
-  assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; probably not right yet
+  assign rxfifotimeout = rxtimeoutcnt == {rxbitsexpected, 6'b0}; // time out after 4 character periods; *** probably not right yet
   //assign rxfifotimeout = 0; // disabled pending fix
 
   // detect any errors in rx fifo
@@ -353,20 +340,20 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     else        assign rxfullbitunwrapped[i] = ({1'b0,rxfifohead}==i | rxfullbitunwrapped[i-1]) & (rxfifotailunwrapped != i);
   end
   for (i=0; i<16; i++) begin:rx
-    assign RXerrbit[i]  = |rxfifo[i][10:8]; // are any of the error conditions set?
+    assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
     assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
   /*      if (i > 0)
       assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
       else
       assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
   end
-  assign rxfifohaserr   = |(RXerrbit & rxfullbit);
+  assign rxfifohaserr = |(RXerrbit & rxfullbit);
 
   // receive buffer register and ready bit
-  always_ff @(posedge PCLK) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (~PRESETn) rxfifodmaready <= 1'b0;
-    else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1'b1;
-    else if (rxfifoempty) rxfifodmaready <= 1'b0;
+  always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
+    if (~PRESETn) rxfifodmaready <= #1 0;
+    else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= #1 1;
+    else if (rxfifoempty) rxfifodmaready <= #1 0;
 
   always_comb
     if (fifoenabled) begin
@@ -375,44 +362,44 @@ module uartPC16550D #(parameter UART_PRESCALE) (
       if (fifodmamodesel) RXRDYb = ~rxfifodmaready;
       else                RXRDYb = rxfifoempty;
     end else begin
-      RBR    = RXBR;
+      RBR = RXBR;
       RXRDYb = ~rxdataready;
     end
 
   ///////////////////////////////////////////
-  // transmit timing and control
+	// transmit timing and control
   ///////////////////////////////////////////
-  
-  always_ff @(posedge PCLK)
+  always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
-      txoversampledcnt <= '0;
-      txstate          <= UART_IDLE;
-      txbitssent       <= '0;
+      txoversampledcnt <= #1 0;
+      txstate <= #1 UART_IDLE;
+      txbitssent <= #1 0;
     end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting
-      txstate          <= UART_ACTIVE;
-      txoversampledcnt <= 4'b1;
-      txbitssent       <= '0;
+      txstate <= #1 UART_ACTIVE;
+      txoversampledcnt <= #1 1;
+      txbitssent <= #1 0;
     end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
-      txoversampledcnt <= txoversampledcnt + 1'b1; 
+      txoversampledcnt <= #1 txoversampledcnt + 1; 
       if (txnextbit) begin // transmit at end of phase
-        txbitssent <= txbitssent + 1'b1;
-        if (txbitssent == txbitsexpected) txstate <= UART_DONE;
+        txbitssent <= #1 txbitssent+1;
+        if (txbitssent == txbitsexpected) txstate <= #1 UART_DONE;
       end
     end else if (txstate == UART_DONE) begin
-      txstate <= UART_IDLE;
+      txstate <= #1 UART_IDLE;
     end
 
   assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) - 1
-  assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
+  // *** explain; is this necessary?
+  if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00);  // implies txstate = UART_ACTIVE
+  else       assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
 
   ///////////////////////////////////////////
   // transmit holding register, shift register, FIFO
   ///////////////////////////////////////////
-  
   always_comb begin // compute value for parity and tx holding register
     nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
     case (LCR[1:0]) // compute parity from appropriate number of bits
-      2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; 
+      2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; // *** check polarity
       2'b01: txparity = ^nexttxdata[5:0] ^ ~evenparitysel; 
       2'b10: txparity = ^nexttxdata[6:0] ^ ~evenparitysel; 
       2'b11: txparity = ^nexttxdata[7:0] ^ ~evenparitysel; 
@@ -431,67 +418,72 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   end
   
   // registers & FIFO
-  always_ff @(posedge PCLK)
+  always_ff @(posedge PCLK, negedge PRESETn)
     if (~PRESETn) begin
-      txfifohead <= '0; txfifotail <= '0; txhrfull <= 1'b0; txsrfull <= 1'b0; TXHR <= '0; txsr <= 12'hfff;
+      txfifohead <= #1 0; txfifotail <= #1 0; txhrfull <= #1 0; txsrfull <= #1 0; TXHR <= #1 0; txsr <= #1 12'hfff;
     end else if (~MEMWb & (A == 3'b010) & Din[2]) begin
-      txfifohead <= '0; txfifotail <= '0;
+      txfifohead <= #1 0; txfifotail <= #1 0;
     end else begin
       if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo
         if (fifoenabled) begin
-          txfifo[txfifohead] <= Din;
-          txfifohead         <= txfifohead + 4'b1;          
+          txfifo[txfifohead] <= #1 Din;
+          txfifohead <= #1 txfifohead + 1;          
         end else begin 
-          TXHR     <= Din;
-          txhrfull <= 1'b1;
+          TXHR <= #1 Din;
+          txhrfull <= #1 1;
         end
         $write("%c",Din); // for testbench
       end
       if (txstate == UART_IDLE) begin // move data into tx shift register if available
         if (fifoenabled) begin 
           if (~txfifoempty & ~txsrfull) begin
-            txsr       <= txdata;
-            txfifotail <= txfifotail+1;
-            txsrfull   <= 1'b1;
+            txsr <= #1 txdata;
+            txfifotail <= #1 txfifotail+1;
+            txsrfull <= #1 1;
           end
         end else if (txhrfull) begin
-          txsr     <= txdata;
-          txhrfull <= 1'b0;
-          txsrfull <= 1'b1;
+          txsr <= #1 txdata;
+          txhrfull <= #1 0;
+          txsrfull <= #1 1;
         end
-      end else if (txstate == UART_DONE) txsrfull <= 1'b0; // done transmitting shift register
-      else if (txstate == UART_ACTIVE & txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr
+      end else if (txstate == UART_DONE) txsrfull <= #1 0; // done transmitting shift register
+      else if (txstate == UART_ACTIVE & txnextbit) txsr <= #1 {txsr[10:0], 1'b1}; // shift txhr
       if (!MEMWb & A == 3'b010) // writes to FIFO control register
         if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents
-          txfifohead <= '0; txfifotail <= '0;
+          txfifohead <= #1 0; txfifotail <= #1 0;
         end
     end
 
-  always_ff @(posedge PCLK) begin
-  // special condition to check if the fifo is empty or full.  Because the head
-  // pointer indicates where the next write goes and not the location of the
-  // current head, the head and tail pointer being equal imply two different
-  // things.  First it could mean the fifo is empty and second it could mean
-  // the fifo is full.  To differenciate we need to know which pointer moved
-  // to cause them to be equal.  If the head pointer moved then it is full.
-  // If the tail pointer moved then it is empty.  it resets to empty so
-  // if reset with the tail pointer indicating the last update.
-  if(~PRESETn) 
-    HeadPointerLastMove <= 1'b0;
-  else if(fifoenabled & ~MEMWb & A == 3'b000 & ~DLAB)
-    HeadPointerLastMove <= 1'b1;
-  else if(fifoenabled & ~txfifoempty & ~txsrfull & txstate == UART_IDLE)
-    HeadPointerLastMove <= 1'b0;
+  always_ff @(posedge PCLK, negedge PRESETn) begin
+	// special condition to check if the fifo is empty or full.  Because the head
+	// pointer indicates where the next write goes and not the location of the
+	// current head, the head and tail pointer being equal imply two different
+	// things.  First it could mean the fifo is empty and second it could mean
+	// the fifo is full.  To differenciate we need to know which pointer moved
+	// to cause them to be equal.  If the head pointer moved then it is full.
+	// If the tail pointer moved then it is empty.  it resets to empty so
+	// if reset with the tail pointer indicating the last update.
+	if(~PRESETn) 
+	  HeadPointerLastMove <= 1'b0;
+	else if(fifoenabled & ~MEMWb & A == 3'b000 & ~DLAB)
+	  HeadPointerLastMove <= 1'b1;
+	else if(fifoenabled & ~txfifoempty & ~txsrfull & txstate == UART_IDLE)
+	  HeadPointerLastMove <= 1'b0;
   end
 
   assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove;
-  assign txfifofull  = (txfifohead == txfifotail) & HeadPointerLastMove;
+  // verilator lint_off WIDTH
+  assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : 
+                         (txfifohead + 16 - txfifotail);
+  // verilator lint_on WIDTH
+  //assign txfifofull = (txfifoentries == 4'b1111);
+	assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove;
 
   // transmit buffer ready bit
-  always_ff @(posedge PCLK) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (~PRESETn)         txfifodmaready <= 1'b0;
-    else if (txfifoempty) txfifodmaready <= 1'b1;
-    else if (txfifofull)  txfifodmaready <= 1'b0;
+  always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
+    if (~PRESETn) txfifodmaready <= #1 0;
+    else if (txfifoempty) txfifodmaready <= #1 1;
+    else if (txfifofull)  txfifodmaready <= #1 0;
 
   always_comb
     if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready;
@@ -499,12 +491,11 @@ module uartPC16550D #(parameter UART_PRESCALE) (
 
   // Transmitter pin 
   assign SOUTbit = txsr[11]; // transmit most significant bit
-  assign SOUT    = loop ? 1 : (LCR[6] ? '0 : SOUTbit); // tied to 1 during loopback or 0 during break 
+  assign SOUT = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break 
 
   ///////////////////////////////////////////
   // interrupts
   ///////////////////////////////////////////
-  
   assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
   assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
   assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready; 
@@ -515,7 +506,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // IIR: interrupt priority (Table 5)
   // set intrID based on highest priority pending interrupt source; otherwise, no interrupt is pending
   always_comb begin
-    intrpending = 1'b1;
+    intrpending = 1;
     if      (RXerrIP & IER[2])                     intrID = 3'b011;
     else if (rxdataavailintr & IER[0])             intrID = 3'b010;
     else if (rxfifotimeout & fifoenabled & IER[0]) intrID = 3'b110;
@@ -523,10 +514,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     else if (modemstatusintr & IER[3])             intrID = 3'b000;
     else begin
       intrID = 3'b000;
-      intrpending = 1'b0;
+      intrpending = 0;
     end
   end
-  always_ff @(posedge PCLK) INTR <= intrpending; // prevent glitches on interrupt pin
+  always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
 
   // Side effect of reading LSR is lowering overrun, parity, framing, break intr's
   assign setSquashRXerrIP = ~MEMRb & (A==3'b101);
@@ -543,22 +534,22 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // modem control logic
   ///////////////////////////////////////////
 
-  assign loop  = MCR[4]; 
+  assign loop = MCR[4]; 
   assign DTRb  = ~MCR[0] | loop; // disable modem signals in loopback mode
   assign RTSb  = ~MCR[1] | loop;
   assign OUT1b = ~MCR[2] | loop;
   assign OUT2b = ~MCR[3] | loop;
 
   assign DLAB = LCR[7];
-  assign evenparitysel  = LCR[4];
-  assign fifoenabled    = FCR[0];
+  assign evenparitysel = LCR[4];
+  assign fifoenabled = FCR[0];
   assign fifodmamodesel = FCR[3];
   always_comb
     case (FCR[7:6]) 
-      2'b00: rxfifotriggerlevel = 4'd1;
-      2'b01: rxfifotriggerlevel = 4'd4;
-      2'b10: rxfifotriggerlevel = 4'd8;
-      2'b11: rxfifotriggerlevel = 4'd14;
+      2'b00: rxfifotriggerlevel = 1;
+      2'b01: rxfifotriggerlevel = 4;
+      2'b10: rxfifotriggerlevel = 8;
+      2'b11: rxfifotriggerlevel = 14;
     endcase
 
 endmodule
diff --git a/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv
similarity index 50%
rename from src/uncore/uart_apb.sv
rename to pipelined/src/uncore/uart_apb.sv
index f7dcf2a60..916f61687 100644
--- a/src/uncore/uart_apb.sv
+++ b/pipelined/src/uncore/uart_apb.sv
@@ -8,10 +8,9 @@
 //          Emulates interface of Texas Instruments PC165550D
 //          Compatible with UART in Imperas Virtio model
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 15
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -29,19 +28,21 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module uart_apb import cvw::*; #(parameter cvw_t P) (
-  input  logic                PCLK, PRESETn,
-  input  logic                PSEL,
-  input  logic [2:0]          PADDR, 
-  input  logic [P.XLEN-1:0]   PWDATA,
-  input  logic [P.XLEN/8-1:0] PSTRB,
-  input  logic                PWRITE,
-  input  logic                PENABLE,
-  output logic [P.XLEN-1:0]   PRDATA,
-  output logic                PREADY,
-  input  logic                SIN, DSRb, DCDb, CTSb, RIb,           // from E1A driver from RS232 interface
-  output logic                SOUT, RTSb, DTRb,                     // to E1A driver to RS232 interface
-  output logic                OUT1b, OUT2b, INTR, TXRDYb, RXRDYb);  // to CPU
+`include "wally-config.vh"
+
+module uart_apb (
+  input  logic             PCLK, PRESETn,
+  input  logic             PSEL,
+  input  logic [2:0]       PADDR, 
+  input  logic [`XLEN-1:0] PWDATA,
+  input  logic [`XLEN/8-1:0] PSTRB,
+  input  logic             PWRITE,
+  input  logic             PENABLE,
+  output logic [`XLEN-1:0] PRDATA,
+  output logic             PREADY,
+  (* mark_debug = "true" *) input  logic             SIN, DSRb, DCDb, CTSb, RIb,    // from E1A driver from RS232 interface
+  (* mark_debug = "true" *) output logic             SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
+  (* mark_debug = "true" *) output logic             OUT1b, OUT2b, INTR, TXRDYb, RXRDYb);         // to CPU
 
   // UART interface signals
   logic [2:0]      entry;
@@ -50,17 +51,40 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
 
   assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
   assign memread  = ~PWRITE & PENABLE & PSEL;  
-  assign PREADY   = 1'b1; // CLINT never takes >1 cycle to respond
-  assign entry    = PADDR[2:0];
-  assign MEMRb    = ~memread;
-  assign MEMWb    = ~memwrite;
+  assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond
+  assign entry = PADDR[2:0];
+  assign MEMRb = ~memread;
+  assign MEMWb = ~memwrite;
 
-  assign Din = PWDATA[7:0]; 
-  if (P.XLEN == 64) assign PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
-  else              assign PRDATA = {Dout, Dout, Dout, Dout};   
+  if (`XLEN == 64) begin:uart
+    always_comb begin
+      PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
+      case (entry)
+        3'b000: Din = PWDATA[7:0];
+        3'b001: Din = PWDATA[15:8];
+        3'b010: Din = PWDATA[23:16];
+        3'b011: Din = PWDATA[31:24];
+        3'b100: Din = PWDATA[39:32];
+        3'b101: Din = PWDATA[47:40];
+        3'b110: Din = PWDATA[55:48];
+        3'b111: Din = PWDATA[63:56];
+      endcase 
+    end 
+  end else begin:uart // 32-bit
+    always_comb begin
+      PRDATA = {Dout, Dout, Dout, Dout};
+      case (entry[1:0])
+        2'b00: Din = PWDATA[7:0];
+        2'b01: Din = PWDATA[15:8];
+        2'b10: Din = PWDATA[23:16];
+        2'b11: Din = PWDATA[31:24];
+      endcase
+    end
+  end
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
-  uartPC16550D #(P.UART_PRESCALE) uartPC(  
+  // *** make sure reads don't occur on UART unless fully selected because they could change state.  This applies to all peripherals
+  uartPC16550D u(  
     // Processor Interface
     .PCLK, .PRESETn,
     .A(entry), .Din, 
@@ -75,3 +99,4 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
 );
 
 endmodule
+
diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv
new file mode 100644
index 000000000..50b4a6534
--- /dev/null
+++ b/pipelined/src/uncore/uncore.sv
@@ -0,0 +1,194 @@
+///////////////////////////////////////////
+// uncore.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec
+//
+// Purpose: System-on-Chip components outside the core
+//          Memories, peripherals, external bus control
+// 
+// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module uncore (
+  // AHB Bus Interface
+  input  logic             HCLK, HRESETn,
+  input  logic             TIMECLK,
+  input  logic [`PA_BITS-1:0] HADDR,
+  input  logic [`AHBW-1:0] HWDATA,
+  input  logic [`XLEN/8-1:0] HWSTRB,
+  input  logic             HWRITE,
+  input  logic [2:0]       HSIZE,
+  input  logic [2:0]       HBURST,
+  input  logic [3:0]       HPROT,
+  input  logic [1:0]       HTRANS,
+  input  logic             HMASTLOCK,
+  input  logic [`AHBW-1:0] HRDATAEXT,
+  input  logic             HREADYEXT, HRESPEXT,
+  output logic [`AHBW-1:0] HRDATA,
+  output logic             HREADY, HRESP,
+  output logic             HSELEXT,
+  // peripheral pins
+  output logic             MTimerInt, MSwInt,         // Timer and software interrupts from CLINT
+  output logic             MExtInt, SExtInt,          // External interrupts from PLIC
+  output logic [63:0]      MTIME_CLINT,               // MTIME, from CLINT
+  input  logic [31:0]      GPIOPinsIn,                // GPIO pin input value
+  output logic [31:0]      GPIOPinsOut, GPIOPinsEn,   // GPIO pin output value and enable
+  input  logic             UARTSin,                   // UART serial input
+  output logic             UARTSout,                  // UART serial output
+  output logic             SDCCmdOut,                 // SD Card command output
+  output logic             SDCCmdOE,                  // SD Card command output enable
+  input  logic             SDCCmdIn,                  // SD Card command input
+  input  logic [3:0]       SDCDatIn,                  // SD Card data input
+  output logic             SDCCLK                     // SD Card clock
+);
+  
+  logic [`XLEN-1:0] HREADRam, HREADSDC;
+
+  logic [10:0]      HSELRegions;
+  logic             HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
+  logic             HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
+  logic             HRESPRam,  HRESPSDC;
+  logic             HREADYRam, HRESPSDCD;
+  logic [`XLEN-1:0] HREADBootRom; 
+  logic             HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
+  logic             HSELNoneD;
+  logic             UARTIntr,GPIOIntr;
+  logic 	          SDCIntM;
+  
+  logic             PCLK, PRESETn, PWRITE, PENABLE;
+  logic [3:0]       PSEL, PREADY;
+  logic [31:0]      PADDR;
+  logic [`XLEN-1:0] PWDATA;
+  logic [`XLEN/8-1:0] PSTRB;
+  logic [3:0][`XLEN-1:0] PRDATA;
+  logic [`XLEN-1:0] HREADBRIDGE;
+  logic             HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
+
+  // Determine which region of physical memory (if any) is being accessed
+  // Use a trimmed down portion of the PMA checker - only the address decoders
+  // Set access types to all 1 as don't cares because the MMU has already done access checking
+  adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
+
+  // unswizzle HSEL signals
+  assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1];
+
+  // AHB -> APB bridge
+  ahbapbbridge #(4) ahbapbbridge (
+    .HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
+    .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
+    .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
+  assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected
+                
+  // on-chip RAM
+  if (`UNCORE_RAM_SUPPORTED) begin : ram
+    ram_ahb #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
+      .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
+      .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
+  end
+
+ if (`BOOTROM_SUPPORTED) begin : bootrom
+    rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
+    bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
+      .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
+  end
+
+  // memory-mapped I/O peripherals
+  if (`CLINT_SUPPORTED == 1) begin : clint
+    clint_apb clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+      .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
+  end else begin : clint
+    assign MTIME_CLINT = 0;
+    assign MTimerInt = 0; assign MSwInt = 0;
+  end
+
+  if (`PLIC_SUPPORTED == 1) begin : plic
+    plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+      .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .MExtInt, .SExtInt);
+  end else begin : plic
+    assign MExtInt = 0;
+    assign SExtInt = 0;
+  end
+
+  if (`GPIO_SUPPORTED == 1) begin : gpio
+    gpio_apb gpio(
+      .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+      .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), 
+      .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
+  end else begin : gpio
+    assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
+  end
+  if (`UART_SUPPORTED == 1) begin : uart
+    uart_apb uart(
+      .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
+      .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), 
+      .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
+      .SOUT(UARTSout), .RTSb(), .DTRb(),                                // to E1A driver to RS232 interface
+      .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb());       // to CPU
+  end else begin : uart
+    assign UARTSout = 0; assign UARTIntr = 0; 
+  end
+  if (`SDC_SUPPORTED == 1) begin : sdc
+    SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
+      .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
+      // sdc interface
+      .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,
+      // interrupt to PLIC
+      .SDCIntM	      
+      );
+  end else begin : sdc
+    assign SDCCLK = 0; 
+    assign SDCCmdOut = 0;
+    assign SDCCmdOE = 0;
+  end
+
+  // AHB Read Multiplexer
+  assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
+		              ({`XLEN{HSELEXTD}} & HRDATAEXT) |   
+                  ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
+                  ({`XLEN{HSELBootRomD}} & HREADBootRom) |
+                  ({`XLEN{HSELSDCD}} & HREADSDC);
+
+  assign HRESP = HSELRamD & HRESPRam |
+		             HSELEXTD & HRESPEXT |
+                 HSELBRIDGE & HRESPBRIDGE |
+                 HSELBootRomD & HRESPBootRom |
+                 HSELSDC & HRESPSDC;		 
+
+  assign HREADY = HSELRamD & HREADYRam |
+		              HSELEXTD & HREADYEXT |		  
+                  HSELBRIDGED & HREADYBRIDGE |
+                  HSELBootRomD & HREADYBootRom |
+                  HSELSDCD & HREADYSDC |		  
+                  HSELNoneD; // don't lock up the bus if no region is being accessed
+
+  // Address Decoder Delay (figure 4-2 in spec)
+  // The select for HREADY needs to be based on the address phase address.  If the device 
+  // takes more than 1 cycle to repsond it needs to hold on to the old select until the
+  // device is ready.  Hense this register must be selectively enabled by HREADY.
+  // However on reset None must be seleted.
+  flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, 
+    {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, 
+    HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
+  flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
+endmodule
+
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
new file mode 100644
index 000000000..2e6b63035
--- /dev/null
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -0,0 +1,375 @@
+///////////////////////////////////////////
+// wallypipelinedcore.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Pipelined RISC-V Processor
+// 
+// Documentation: RISC-V System on Chip Design (Figure 4.1)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+/* verilator lint_on UNUSED */
+
+module wallypipelinedcore (
+   input  logic                  clk, reset,
+   // Privileged
+   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
+   input  logic [63:0]           MTIME_CLINT, 
+   // Bus Interface
+   input  logic [`AHBW-1:0]      HRDATA,
+   input  logic                  HREADY, HRESP,
+   output logic                  HCLK, HRESETn,
+   output logic [`PA_BITS-1:0]   HADDR,
+   output logic [`AHBW-1:0]      HWDATA,
+   output logic [`XLEN/8-1:0]    HWSTRB,
+   output logic                  HWRITE,
+   output logic [2:0]            HSIZE,
+   output logic [2:0]            HBURST,
+   output logic [3:0]            HPROT,
+   output logic [1:0]            HTRANS,
+   output logic                  HMASTLOCK
+   );
+
+  logic                          StallF, StallD, StallE, StallM, StallW;
+  logic                          FlushD, FlushE, FlushM, FlushW;
+  logic                          RetM;
+  (* mark_debug = "true" *) logic TrapM;
+
+  //  signals that must connect through DP
+  logic                          IntDivE, W64E;
+  logic                          CSRReadM, CSRWriteM, PrivilegedM;
+  logic [1:0]                    AtomicM;
+  logic [`XLEN-1:0]              ForwardedSrcAE, ForwardedSrcBE;
+(* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
+  logic [2:0]                    Funct3E;
+  logic [31:0]                   InstrD;
+  (* mark_debug = "true" *) logic [31:0]             InstrM;
+  logic [`XLEN-1:0]              PCF, PCE, PCLinkE;
+  (* mark_debug = "true" *) logic [`XLEN-1:0]         PCM;
+ logic [`XLEN-1:0]               CSRReadValW, MDUResultW;
+   logic [`XLEN-1:0]             UnalignedPCNextF, PCNext2F;
+  (* mark_debug = "true" *) logic [1:0]       MemRWM;
+  (* mark_debug = "true" *) logic             InstrValidM;
+  logic                          InstrMisalignedFaultM;
+  logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
+  logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
+  logic                          LoadMisalignedFaultM, LoadAccessFaultM;
+  logic                          StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
+  logic                          InvalidateICacheM, FlushDCacheM;
+  logic                          PCSrcE;
+  logic                          CSRWriteFenceM;
+  logic                          DivBusyE;
+  logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
+  logic                          SquashSCW;
+
+  // floating point unit signals
+  logic [2:0]                    FRM_REGW;
+  logic [4:0]                    RdE, RdM, RdW;
+  logic                          FPUStallD;
+  logic                          FWriteIntE;
+  logic [`FLEN-1:0]              FWriteDataM;
+  logic [`XLEN-1:0]              FIntResM;  
+  logic [`XLEN-1:0]              FCvtIntResW; 
+  logic                          FCvtIntW; 
+  logic                          FDivBusyE;
+  logic                          IllegalFPUInstrM;
+  logic                          FRegWriteM;
+  logic                          FCvtIntStallD;
+  logic                          FpLoadStoreM;
+  logic [4:0]                    SetFflagsM;
+  logic [`XLEN-1:0]              FIntDivResultW;
+
+  // memory management unit signals
+  logic                          ITLBWriteF;
+  logic                          ITLBMissF;
+  logic [`XLEN-1:0]              SATP_REGW;
+  logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
+  logic  [1:0]                   STATUS_MPP, STATUS_FS;
+  logic [1:0]                    PrivilegeModeW;
+  logic [`XLEN-1:0]              PTE;
+  logic [1:0]                    PageType;
+  logic                          sfencevmaM, WFIStallM;
+  logic                          SelHPTW;
+
+
+  // PMA checker signals
+  var logic [`XLEN-1:0]          PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
+  var logic [7:0]                PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
+
+  // IMem stalls
+  logic                          IFUStallF;
+  logic                          LSUStallM;
+
+  // cpu lsu interface
+  logic [2:0]                    Funct3M;
+  logic [`XLEN-1:0]              IEUAdrE;
+  (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
+  (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;  
+  logic [`LLEN-1:0]              ReadDataW;  
+  logic                          CommittedM;
+
+  // AHB ifu interface
+  logic [`PA_BITS-1:0]           IFUHADDR;
+  logic [2:0]                    IFUHBURST;
+  logic [1:0]                    IFUHTRANS;
+  logic [2:0]                    IFUHSIZE;
+  logic                          IFUHWRITE;
+  logic                          IFUHREADY;
+  
+  // AHB LSU interface
+  logic [`PA_BITS-1:0]           LSUHADDR;
+  logic [`XLEN-1:0]              LSUHWDATA;
+  logic [`XLEN/8-1:0]            LSUHWSTRB;
+  logic                          LSUHWRITE;
+  logic                          LSUHREADY;
+  
+  logic                          BPPredWrongE;
+  logic                          DirPredictionWrongM;
+  logic                          BTBPredPCWrongM;
+  logic                          RASPredPCWrongM;
+  logic                          PredictionInstrClassWrongM;
+  logic [3:0]                    InstrClassM;
+  logic                          InstrAccessFaultF, HPTWInstrAccessFaultM;
+  logic [2:0]                    LSUHSIZE;
+  logic [2:0]                    LSUHBURST;
+  logic [1:0]                    LSUHTRANS;
+  
+  logic                          DCacheMiss;
+  logic                          DCacheAccess;
+  logic                          ICacheMiss;
+  logic                          ICacheAccess;
+  logic                          BreakpointFaultM, EcallFaultM;
+  logic                          InstrDAPageFaultF;
+  logic                          BigEndianM;
+  logic                          FCvtIntE;
+  logic                          CommittedF;
+  
+  // Bit manipulation unit
+  logic [`XLEN-1:0]              BMUResultE;    // Bit manipuation result BMU -> IEU
+  logic                          BMUE;          // is this a BMU instruction
+ 
+  // instruction fetch unit: PC, branch prediction, instruction cache
+  ifu ifu(.clk, .reset,
+    .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    // Fetch
+    .HRDATA, .PCF, .IFUHADDR, .PCNext2F,
+    .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
+    .ICacheAccess, .ICacheMiss,
+    // Execute
+    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, 
+    // Mem
+    .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
+    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
+    .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
+    // Faults out
+    .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
+    // mmu management
+    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
+    .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
+    // pmp/pma (inside mmu) signals. 
+    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); 
+    
+  // integer execution unit: integer register file, datapath and controller
+  ieu ieu(.clk, .reset,
+     // Decode Stage interface
+     .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
+     // Execute Stage interface
+     .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
+     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
+     // Memory stage interface
+     .SquashSCW, // from LSU
+     .MemRWM, // read/write control goes to LSU
+     .AtomicM, // atomic control goes to LSU
+     .WriteDataM, // Write data to LSU
+     .Funct3M, // size and signedness to LSU
+     .SrcAM, // to privilege and fpu
+     .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
+     // Writeback stage
+     .CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
+     .InstrValidM, .FCvtIntResW, .FCvtIntW,
+     // hazards
+     .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+     .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
+     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); 
+
+  lsu lsu(
+    .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
+    // CPU interface
+    .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
+    .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
+    .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
+    .ReadDataW, .FlushDCacheM,
+    // connected to ahb (all stay the same)
+    .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
+    .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
+    // connect to csr or privilege and stay the same.
+    .PrivilegeModeW, .BigEndianM,          // connects to csr
+    .PMPCFG_ARRAY_REGW,     // connects to csr
+    .PMPADDR_ARRAY_REGW,    // connects to csr
+    // hptw keep i/o
+    .SATP_REGW, // from csr
+    .STATUS_MXR, // from csr
+    .STATUS_SUM,  // from csr
+    .STATUS_MPRV,  // from csr            
+    .STATUS_MPP,  // from csr      
+    .sfencevmaM,                   // connects to privilege
+    .LoadPageFaultM,   // connects to privilege
+    .StoreAmoPageFaultM, // connects to privilege
+    .LoadMisalignedFaultM, // connects to privilege
+    .LoadAccessFaultM,         // connects to privilege
+    .HPTWInstrAccessFaultM,         // connects to privilege
+    .StoreAmoMisalignedFaultM, // connects to privilege
+    .StoreAmoAccessFaultM,     // connects to privilege
+    .InstrDAPageFaultF,
+    .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
+    .LSUStallM);                    
+
+  if(`BUS) begin : ebu
+    ebu ebu(// IFU connections
+      .clk, .reset,
+      // IFU interface
+      .IFUHADDR,
+      .IFUHBURST, 
+      .IFUHTRANS, 
+      .IFUHREADY,
+      .IFUHSIZE,
+      // LSU interface
+      .LSUHADDR,
+      .LSUHWDATA,
+      .LSUHWSTRB,
+      .LSUHSIZE,
+      .LSUHBURST,
+      .LSUHTRANS,
+      .LSUHWRITE,
+      .LSUHREADY,
+      // BUS interface
+      .HREADY, .HRESP, .HCLK, .HRESETn,
+      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
+      .HPROT, .HTRANS, .HMASTLOCK);
+  end
+
+  // global stall and flush control  
+  hazard  hzu(
+    .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
+    .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
+    .LSUStallM, .IFUStallF,
+    .FCvtIntStallD, .FPUStallD,
+    .DivBusyE, .FDivBusyE,
+    .EcallFaultM, .BreakpointFaultM,
+    .WFIStallM,
+    // Stall & flush outputs
+    .StallF, .StallD, .StallE, .StallM, .StallW,
+    .FlushD, .FlushE, .FlushM, .FlushW);    
+
+  // privileged unit
+  if (`ZICSR_SUPPORTED) begin:priv
+    privileged priv(
+      .clk, .reset,
+      .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
+      .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
+      .InstrM, .CSRReadValW, .UnalignedPCNextF,
+      .RetM, .TrapM, .sfencevmaM,
+      .InstrValidM, .CommittedM, .CommittedF,
+      .FRegWriteM, .LoadStallD,
+      .DirPredictionWrongM, .BTBPredPCWrongM,
+      .RASPredPCWrongM, .PredictionInstrClassWrongM,
+      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
+      .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
+      .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
+      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
+      .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
+      .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
+      .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
+      .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
+      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
+      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
+  end else begin
+    assign CSRReadValW = 0;
+    assign UnalignedPCNextF = PCNext2F;
+    assign RetM = 0;
+    assign TrapM = 0;
+    assign WFIStallM = 0;
+    assign sfencevmaM = 0;
+    assign BigEndianM = 0;
+  end
+
+  // multiply/divide unit
+  if (`M_SUPPORTED) begin:mdu
+    mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
+      .ForwardedSrcAE, .ForwardedSrcBE, 
+      .Funct3E, .Funct3M, .IntDivE, .W64E,
+      .MDUResultW, .DivBusyE); 
+  end else begin // no M instructions supported
+    assign MDUResultW = 0; 
+    assign DivBusyE = 0;
+  end
+
+  // floating point unit
+  if (`F_SUPPORTED) begin:fpu
+    fpu fpu(
+      .clk, .reset,
+      .FRM_REGW, // Rounding mode from CSR
+      .InstrD, // instruction from IFU
+      .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
+      .ForwardedSrcAE, // Integer input being processed (from IEU)
+      .StallE, .StallM, .StallW, // stall signals from HZU
+      .FlushE, .FlushM, .FlushW, // flush signals from HZU
+      .RdE, .RdM, .RdW, // which FP register to write to (from IEU)
+      .STATUS_FS, // is floating-point enabled?
+      .FRegWriteM, // FP register write enable
+      .FpLoadStoreM,
+      .ForwardedSrcBE, // Integer input for intdiv
+      .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
+      .FPUStallD, // Stall the decode stage
+      .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
+      .FWriteDataM, // Data to be written to memory
+      .FIntResM, // data to be written to integer register
+      .FCvtIntResW, // fp -> int conversion result to be stored in int register
+      .FCvtIntW,   // fpu result selection
+      .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
+      .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
+      .SetFflagsM,        // FPU flags (to privileged unit)
+      .FIntDivResultW); 
+  end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
+    assign FPUStallD = 0;
+    assign FWriteIntE = 0; 
+    assign FCvtIntE = 0;
+    assign FIntResM = 0;
+    assign FCvtIntW = 0;
+    assign FDivBusyE = 0;
+    assign IllegalFPUInstrM = 1;
+    assign SetFflagsM = 0;
+    assign FpLoadStoreM = 0;
+  end
+
+  // bit manipulation unit
+  if (`B_SUPPORTED) begin:bmu
+    bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE); 
+  end else begin // no B instructions supported
+    assign BMUResultE = 0; 
+    assign BMUE = 0;
+  end
+
+
+  
+endmodule
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv
new file mode 100644
index 000000000..59f213ad0
--- /dev/null
+++ b/pipelined/src/wally/wallypipelinedsoc.sv
@@ -0,0 +1,92 @@
+///////////////////////////////////////////
+// wally-pipelinedsoc.sv
+//
+// Written: David_Harris@hmc.edu 6 November 2020
+// Modified: 
+//
+// Purpose: System on chip including pipelined processor and uncore memories/peripherals
+//
+// Documentation: RISC-V System on Chip Design (Figure 6.20)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module wallypipelinedsoc (
+  input  logic 		            clk, 
+  input  logic                reset_ext,        // external asynchronous reset pin
+  output logic                reset,            // reset synchronized to clk to prevent races on release
+  // AHB Interface
+  input  logic [`AHBW-1:0]    HRDATAEXT,
+  input  logic 		            HREADYEXT, HRESPEXT,
+  output logic 		            HSELEXT,
+  // outputs to external memory, shared with uncore memory
+  output logic 		            HCLK, HRESETn,
+  output logic [`PA_BITS-1:0] HADDR,
+  output logic [`AHBW-1:0]    HWDATA,
+  output logic [`XLEN/8-1:0]  HWSTRB,
+  output logic 		            HWRITE,
+  output logic [2:0] 	        HSIZE,
+  output logic [2:0] 	        HBURST,
+  output logic [3:0] 	        HPROT,
+  output logic [1:0] 	        HTRANS,
+  output logic 		            HMASTLOCK,
+  output logic 		            HREADY,
+  // I/O Interface
+  input  logic                TIMECLK,          // optional for CLINT MTIME counter
+  input  logic [31:0] 	      GPIOPinsIn,       // inputs from GPIO
+  output logic [31:0] 	      GPIOPinsOut,      // output values for GPIO
+  output logic [31:0]         GPIOPinsEn,       // output enables for GPIO
+  input  logic 		            UARTSin,          // UART serial data input
+  output logic 		            UARTSout,         // UART serial data output
+  input  logic 		            SDCCmdIn,         // SDC Command input
+  output logic 		            SDCCmdOut,        // SDC Command output
+  output logic 		            SDCCmdOE,			    // SDC Command output enable
+  input  logic [3:0] 	        SDCDatIn,         // SDC data input
+  output logic 		            SDCCLK			      // SDC clock
+);
+
+  // Uncore signals
+  logic [`AHBW-1:0]           HRDATA;           // from AHB mux in uncore
+  logic                       HRESP;            // response from AHB
+  logic                       MTimerInt, MSwInt; // timer and software interrupts from CLINT
+  logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
+  logic                       MExtInt,SExtInt;  // from PLIC
+
+  // synchronize reset to SOC clock domain
+  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
+   
+  // instantiate processor and internal memories
+  wallypipelinedcore core(.clk, .reset,
+    .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
+    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
+    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
+   );
+
+  // instantiate uncore if a bus interface exists
+  if (`BUS) begin : uncore
+    uncore uncore(.HCLK, .HRESETn, .TIMECLK,
+      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
+      .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
+      .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, 
+	    .UARTSout, .MTIME_CLINT, 
+	    .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
+  end
+
+endmodule
diff --git a/pipelined/testbench/common/functionName.sv b/pipelined/testbench/common/functionName.sv
new file mode 100644
index 000000000..45a11e8c5
--- /dev/null
+++ b/pipelined/testbench/common/functionName.sv
@@ -0,0 +1,175 @@
+///////////////////////////////////////////
+// datapath.sv
+//
+// Written: Ross Thompson
+// email: ross1728@gmail.com
+// Created: November 9, 2019
+// Modified: March 04, 2021
+//
+// Purpose: Finds the current function or global assembly label based on PCE.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
+  
+  input logic reset;
+  input logic clk;
+  input string ProgramAddrMapFile;
+  input string ProgramLabelMapFile;
+
+  logic [`XLEN-1:0] ProgramAddrMapMemory [];
+  string 	    ProgramLabelMapMemory [integer];
+  string 	    FunctionName;
+  
+
+  logic [`XLEN-1:0] PCF, PCD, PCE, FunctionAddr;
+  logic 	    StallD, StallE, FlushD, FlushE;
+  integer 	    ProgramAddrIndex, ProgramAddrIndexQ;
+
+  assign PCF = testbench.dut.core.PCF;
+  assign StallD = testbench.dut.core.StallD;
+  assign StallE = testbench.dut.core.StallE;  
+  assign FlushD = testbench.dut.core.FlushD;
+  assign FlushE = testbench.dut.core.FlushE;
+
+  // copy from ifu
+  // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not
+  // erroneously change.
+  flopenrc #(`XLEN) PCDReg(clk, reset, 1'b0, ~StallD, FlushE & FlushD ? PCE : PCF, PCD);
+  flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushE ? PCE : PCD, PCE);
+  
+  
+
+  task automatic bin_search_min;
+    input logic [`XLEN-1:0] pc;
+    input logic [`XLEN-1:0] length;
+    ref logic [`XLEN-1:0]   array [];
+    output logic [`XLEN-1:0] minval;
+    output     logic [`XLEN-1:0] mid;
+
+    logic [`XLEN-1:0] 	     left, right;
+
+    begin
+      if ( pc == 0 ) begin
+	// *** want to  keep the old value for mid and minval
+	mid = 0;
+	return;
+      end
+      left = 0;
+      right = length;
+      while (left <= right) begin
+	mid = left + ((right - left) / 2);
+	if (array[mid] == pc) begin
+	  minval = array[mid];
+	  return;
+        end
+	if (array[mid] < pc) begin
+	  left = mid + 1;
+	end else if( array[mid] > pc) begin
+	  right = mid -1;
+	end else begin
+	  //$display("Critical Error in FunctionName. PC, %x not found.", pc);
+	  return;
+	  //$stop();
+	end	  
+      end // while (left <= right)
+      // if the element pc is now found, right and left will be equal at this point.
+      // we need to check if pc is less than the array at left or greather.
+      // if it is less than pc, then we select left as the index.
+      // if it is greather we want 1 less than left.
+      if (array[left] < pc) begin
+	minval = array[left];
+	mid = left;      
+	return;	    
+      end else begin
+	minval = array[left-1];
+	mid = left - 1;	
+	return;
+      end
+    end
+  endtask // bin_search_min
+
+  integer ProgramAddrMapFP, ProgramLabelMapFP;
+  integer ProgramAddrMapLineCount, ProgramLabelMapLineCount;
+  longint ProgramAddrMapLine;
+  string  ProgramLabelMapLine;
+  integer status;
+  
+
+  // preload
+//  initial begin
+  always @ (posedge reset) begin
+    $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
+    // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
+
+    ProgramAddrMapLineCount = 0;
+    ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
+
+    // read line by line to count lines
+    if (ProgramAddrMapFP) begin
+      while (! $feof(ProgramAddrMapFP)) begin
+	status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
+	
+	ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1;
+      end
+    end else begin
+      $display("Cannot open file %s for reading.", ProgramAddrMapFile);
+    end
+    $fclose(ProgramAddrMapFP);
+
+    // ProgramIndexFile maps the program name to the compile index.
+    // The compile index is then used to inditify the application
+    // in the custom radix.
+    // Build an associative array to convert the name to an index.
+    ProgramLabelMapLineCount = 0;
+    ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
+    
+    if (ProgramLabelMapFP) begin
+      while (! $feof(ProgramLabelMapFP)) begin
+	status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine);
+	ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine;
+	ProgramLabelMapLineCount = ProgramLabelMapLineCount + 1;
+      end
+    end else begin
+      $display("Cannot open file %s for reading.", ProgramLabelMapFile);
+    end
+    $fclose(ProgramLabelMapFP);
+    
+  end
+
+  always @(PCE) begin
+    bin_search_min(PCE, ProgramAddrMapLineCount, ProgramAddrMapMemory, FunctionAddr, ProgramAddrIndex);
+  end
+
+  logic OrReducedAdr, AnyUnknown;
+  assign OrReducedAdr = |ProgramAddrIndex;
+  assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0;
+  initial ProgramAddrIndex = '0;
+
+  assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
+  
+
+endmodule // function_radix
+
diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/pipelined/testbench/common/instrNameDecTB.sv
new file mode 100644
index 000000000..4c1a68502
--- /dev/null
+++ b/pipelined/testbench/common/instrNameDecTB.sv
@@ -0,0 +1,260 @@
+// decode the instruction name, to help the test bench
+module instrNameDecTB(
+  input  logic [31:0] instr,
+  output string       name);
+
+  logic [6:0] op;
+  logic [2:0] funct3;
+  logic [6:0] funct7;
+  logic [11:0] imm;
+  logic [4:0] rs2;
+
+  assign op = instr[6:0];
+  assign funct3 = instr[14:12];
+  assign funct7 = instr[31:25];
+  assign imm = instr[31:20];
+  assign rs2 = instr[24:20];
+
+  // it would be nice to add the operands to the name 
+  // create another variable called decoded
+
+  always_comb 
+    casez({op, funct3})
+      10'b0000000_000: name = "BAD";
+      10'b0000011_000: name = "LB";
+      10'b0000011_001: name = "LH";
+      10'b0000011_010: name = "LW";
+      10'b0000011_011: name = "LD";
+      10'b0000011_100: name = "LBU";
+      10'b0000011_101: name = "LHU";
+      10'b0000011_110: name = "LWU";
+      10'b0010011_000: if (instr[31:15] == 0 & instr[11:7] ==0) name = "NOP/FLUSH";
+                       else                                      name = "ADDI";
+      10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
+                       else                      name = "ILLEGAL";
+      10'b0010011_010: name = "SLTI";
+      10'b0010011_011: name = "SLTIU";
+      10'b0010011_100: name = "XORI";
+      10'b0010011_101: if (funct7[6:1] == 6'b000000)      name = "SRLI";
+                       else if (funct7[6:1] == 6'b010000) name = "SRAI"; 
+                       else                           name = "ILLEGAL"; 
+      10'b0010011_110: name = "ORI";
+      10'b0010011_111: name = "ANDI";
+      10'b0010111_???: name = "AUIPC";
+      10'b0100011_000: name = "SB";
+      10'b0100011_001: name = "SH";
+      10'b0100011_010: name = "SW";
+      10'b0100011_011: name = "SD";
+      10'b0011011_000: name = "ADDIW";
+      10'b0011011_001: name = "SLLIW";
+      10'b0011011_101: if      (funct7 == 7'b0000000) name = "SRLIW";
+                       else if (funct7 == 7'b0100000) name = "SRAIW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_000: if      (funct7 == 7'b0000000) name = "ADDW";
+                       else if (funct7 == 7'b0100000) name = "SUBW";
+                       else if (funct7 == 7'b0000001) name = "MULW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_001: if      (funct7 == 7'b0000000) name = "SLLW";
+                       else if (funct7 == 7'b0000001) name = "DIVW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_101: if      (funct7 == 7'b0000000) name = "SRLW";
+                       else if (funct7 == 7'b0100000) name = "SRAW";
+                       else if (funct7 == 7'b0000001) name = "DIVUW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_110: if      (funct7 == 7'b0000001) name = "REMW";
+                       else                           name = "ILLEGAL";
+      10'b0111011_111: if      (funct7 == 7'b0000001) name = "REMUW";
+                       else                           name = "ILLEGAL";
+      10'b0110011_000: if      (funct7 == 7'b0000000) name = "ADD";
+                       else if (funct7 == 7'b0000001) name = "MUL";
+                       else if (funct7 == 7'b0100000) name = "SUB"; 
+                       else                           name = "ILLEGAL"; 
+      10'b0110011_001: if      (funct7 == 7'b0000000) name = "SLL";
+                       else if (funct7 == 7'b0000001) name = "MULH";
+                       else                           name = "ILLEGAL";
+      10'b0110011_010: if      (funct7 == 7'b0000000) name = "SLT";
+                       else if (funct7 == 7'b0000001) name = "MULHSU";
+                       else                           name = "ILLEGAL";
+      10'b0110011_011: if      (funct7 == 7'b0000000) name = "SLTU";
+                       else if (funct7 == 7'b0000001) name = "MULHU";
+                       else                           name = "ILLEGAL";
+      10'b0110011_100: if      (funct7 == 7'b0000000) name = "XOR";
+                       else if (funct7 == 7'b0000001) name = "DIV";
+                       else                           name = "ILLEGAL";
+      10'b0110011_101: if      (funct7 == 7'b0000000) name = "SRL";
+                       else if (funct7 == 7'b0000001) name = "DIVU";
+                       else if (funct7 == 7'b0100000) name = "SRA";
+                       else                           name = "ILLEGAL";
+      10'b0110011_110: if      (funct7 == 7'b0000000) name = "OR";
+                       else if (funct7 == 7'b0000001) name = "REM";
+                       else                           name = "ILLEGAL";
+      10'b0110011_111: if      (funct7 == 7'b0000000) name = "AND";
+                       else if (funct7 == 7'b0000001) name = "REMU";
+                       else                           name = "ILLEGAL";
+      10'b0110111_???: name = "LUI";
+      10'b1100011_000: name = "BEQ";
+      10'b1100011_001: name = "BNE";
+      10'b1100011_100: name = "BLT";
+      10'b1100011_101: name = "BGE";
+      10'b1100011_110: name = "BLTU";
+      10'b1100011_111: name = "BGEU";
+      10'b1100111_000: name = "JALR";
+      10'b1101111_???: name = "JAL";
+      10'b1110011_000: if      (imm == 0) name = "ECALL";
+                       else if (imm == 1) name = "EBREAK";
+                       else if (imm == 258) name = "SRET";
+                       else if (imm == 770) name = "MRET";
+                       else if (funct7 == 9) name = "SFENCE.VMA";
+                       else if (imm == 261) name = "WFI";
+                       else              name = "ILLEGAL";
+      10'b1110011_001: name = "CSRRW";
+      10'b1110011_010: name = "CSRRS";
+      10'b1110011_011: name = "CSRRC";
+      10'b1110011_101: name = "CSRRWI";
+      10'b1110011_110: name = "CSRRSI";
+      10'b1110011_111: name = "CSRRCI";
+      10'b0101111_010: if      (funct7[6:2] == 5'b00010) name = "LR.W";
+                       else if (funct7[6:2] == 5'b00011) name = "SC.W";
+                       else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
+                       else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
+                       else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
+                       else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
+                       else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
+                       else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
+                       else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
+                       else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
+                       else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
+                       else                              name = "ILLEGAL";
+      10'b0101111_011: if      (funct7[6:2] == 5'b00010) name = "LR.D";
+                       else if (funct7[6:2] == 5'b00011) name = "SC.D";
+                       else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
+                       else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
+                       else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
+                       else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
+                       else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
+                       else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
+                       else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
+                       else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
+                       else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
+                       else                              name = "ILLEGAL";
+      10'b0001111_???: name = "FENCE";
+      10'b1000011_???: name = "FMADD";
+      10'b1000111_???: name = "FMSUB";
+      10'b1001011_???: name = "FNMSUB";
+      10'b1001111_???: name = "FNMADD";
+      10'b1010011_000: if      (funct7[6:2] == 5'b00000) name = "FADD";
+                       else if (funct7[6:2] == 5'b00001) name = "FSUB";
+                       else if (funct7[6:2] == 5'b00010) name = "FMUL";
+                       else if (funct7[6:2] == 5'b00011) name = "FDIV";
+                       else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
+                       else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
+                       else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
+                       else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W";
+                       else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X";
+                       else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
+                       else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
+                       else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
+                       else if (funct7[6:2] == 5'b00101) name = "FMIN";
+                       else if (funct7[6:2] == 5'b10100) name = "FLE";
+                       else                              name = "ILLEGAL";
+      10'b1010011_001: if      (funct7[6:2] == 5'b00000) name = "FADD";
+                       else if (funct7[6:2] == 5'b00001) name = "FSUB";
+                       else if (funct7[6:2] == 5'b00010) name = "FMUL";
+                       else if (funct7[6:2] == 5'b00011) name = "FDIV";
+                       else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
+                       else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
+                       else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
+                       else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
+                       else if (funct7[6:2] == 5'b00101) name = "FMAX";
+                       else if (funct7[6:2] == 5'b10100) name = "FLT";
+                       else if (funct7[6:2] == 5'b11100) name = "FCLASS";
+                       else                              name = "ILLEGAL";
+      10'b1010011_010: if      (funct7[6:2] == 5'b00000) name = "FADD";
+                       else if (funct7[6:2] == 5'b00001) name = "FSUB";
+                       else if (funct7[6:2] == 5'b00010) name = "FMUL";
+                       else if (funct7[6:2] == 5'b00011) name = "FDIV";
+                       else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
+                       else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
+                       else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
+                       else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
+                       else if (funct7[6:2] == 5'b10100) name = "FEQ";
+                       else                              name = "ILLEGAL";
+      10'b1010011_???: if      (funct7[6:2] == 5'b00000) name = "FADD";
+                       else if (funct7[6:2] == 5'b00001) name = "FSUB";
+                       else if (funct7[6:2] == 5'b00010) name = "FMUL";
+                       else if (funct7[6:2] == 5'b00011) name = "FDIV";
+                       else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
+                       else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
+                       else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
+                       else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
+                       else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
+                       else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
+                       else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
+                       else                              name = "ILLEGAL";
+      10'b0000111_010: name = "FLW";
+      10'b0100111_010: name = "FSW";
+      10'b0000111_011: name = "FLD";
+      10'b0100111_011: name = "FSD";
+      default:         name = "ILLEGAL";
+    endcase
+endmodule
diff --git a/pipelined/testbench/common/instrTrackerTB.sv b/pipelined/testbench/common/instrTrackerTB.sv
new file mode 100644
index 000000000..2b0ca7c50
--- /dev/null
+++ b/pipelined/testbench/common/instrTrackerTB.sv
@@ -0,0 +1,17 @@
+module instrTrackerTB(
+  input  logic            clk, reset, FlushE,
+  input  logic [31:0]     InstrF, InstrD,
+  input  logic [31:0]     InstrE, InstrM,
+  input  logic [31:0]     InstrW,
+//  output logic [31:0]     InstrW,
+  output string           InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+        
+  // stage Instr to Writeback for visualization
+  // flopr  #(32) InstrWReg(clk, reset, InstrM, InstrW);
+
+  instrNameDecTB fdec(InstrF, InstrFName);
+  instrNameDecTB ddec(InstrD, InstrDName);
+  instrNameDecTB edec(InstrE, InstrEName);
+  instrNameDecTB mdec(InstrM, InstrMName);
+  instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU
+endmodule
diff --git a/tests/fp/vectors/case.sh b/pipelined/testbench/fp/case.sh
similarity index 100%
rename from tests/fp/vectors/case.sh
rename to pipelined/testbench/fp/case.sh
diff --git a/pipelined/testbench/sdc/ram2sdLoad.py b/pipelined/testbench/sdc/ram2sdLoad.py
new file mode 100755
index 000000000..d283ad3ac
--- /dev/null
+++ b/pipelined/testbench/sdc/ram2sdLoad.py
@@ -0,0 +1,12 @@
+#!/usr/bin/python3
+
+import sys, fileinput
+
+address = 0
+
+
+for line in fileinput.input('-'):
+    # the 14- is to reverse the byte order to little endian
+    formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
+    sys.stdout.write('@{:08x} {:s}\n'.format(address, formatedLine))
+    address+=8
diff --git a/testbench/sdc/ramdisk2.hex b/pipelined/testbench/sdc/ramdisk2.hex
similarity index 100%
rename from testbench/sdc/ramdisk2.hex
rename to pipelined/testbench/sdc/ramdisk2.hex
diff --git a/testbench/sdc/run_tb.do b/pipelined/testbench/sdc/run_tb.do
similarity index 100%
rename from testbench/sdc/run_tb.do
rename to pipelined/testbench/sdc/run_tb.do
diff --git a/testbench/sdc/sdModel.sv b/pipelined/testbench/sdc/sdModel.sv
similarity index 99%
rename from testbench/sdc/sdModel.sv
rename to pipelined/testbench/sdc/sdModel.sv
index 34b88a18d..f2a5127d8 100644
--- a/testbench/sdc/sdModel.sv
+++ b/pipelined/testbench/sdc/sdModel.sv
@@ -498,7 +498,7 @@ module    sdModel
 	   crcRst<=0;
 	   crcIn <= #`tIH qCmd; // tIH 0
 	   inCmd[47-cmdRead]  <= #`tIH qCmd;    // tIH 0
-	   cmdRead <= cmdRead+1;
+	   cmdRead <= #1 cmdRead+1;
 	   if (cmdRead >= 40) 
              crcEn<=0;
            
@@ -917,7 +917,7 @@ module    sdModel
 	WRITE_DATA: begin
 	   oeDat<=1;
 	   outdly_cnt<=outdly_cnt+1;
-	   datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
+	   datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross)
 	   
 	   
 	   if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed
diff --git a/testbench/sdc/sd_crc_16.sv b/pipelined/testbench/sdc/sd_crc_16.sv
similarity index 100%
rename from testbench/sdc/sd_crc_16.sv
rename to pipelined/testbench/sdc/sd_crc_16.sv
diff --git a/testbench/sdc/sd_crc_7.sv b/pipelined/testbench/sdc/sd_crc_7.sv
similarity index 100%
rename from testbench/sdc/sd_crc_7.sv
rename to pipelined/testbench/sdc/sd_crc_7.sv
diff --git a/testbench/sdc/sd_defines.h b/pipelined/testbench/sdc/sd_defines.h
similarity index 100%
rename from testbench/sdc/sd_defines.h
rename to pipelined/testbench/sdc/sd_defines.h
diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/pipelined/testbench/sdc/sd_top_tb.sv
new file mode 100644
index 000000000..3282c0e2a
--- /dev/null
+++ b/pipelined/testbench/sdc/sd_top_tb.sv
@@ -0,0 +1,132 @@
+///////////////////////////////////////////
+// sd_top_tb.sv
+//
+// Written: Ross Thompson September 20, 2021
+// Modified: 
+//
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+
+module sd_top_tb();
+
+
+  localparam integer g_COUNT_WIDTH = 8;
+
+  logic a_RST;
+  logic i_SD_CMD;
+  logic o_SD_CMD;
+  logic o_SD_CMD_OE;
+  wire [3:0] i_SD_DAT;
+  logic o_SD_CLK;
+  logic [32:9] i_BLOCK_ADDR;
+  logic [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
+
+  logic o_READY_FOR_READ;
+  logic i_READ_REQUEST;
+  logic [3:0] o_DATA_TO_CORE;
+  logic o_DATA_VALID;
+  logic o_LAST_NIBBLE;
+  logic [4095:0] ReadData;
+  logic o_SD_RESTARTING;
+  logic [2:0] o_ERROR_CODE_Q;
+  logic o_FATAL_ERROR;
+  
+  
+  
+  // Driver
+  wire PAD;
+
+  logic r_CLK;
+  
+
+  // clock
+  
+  sd_top #(g_COUNT_WIDTH) DUT
+    (.CLK(r_CLK),
+    .a_RST(a_RST),
+    .i_SD_CMD(i_SD_CMD),
+    .o_SD_CMD(o_SD_CMD),
+    .o_SD_CMD_OE(o_SD_CMD_OE),
+    .i_SD_DAT(i_SD_DAT),
+    .o_SD_CLK(o_SD_CLK),
+    .i_BLOCK_ADDR(i_BLOCK_ADDR),
+    .o_READY_FOR_READ(o_READY_FOR_READ),
+     .o_SD_RESTARTING(o_SD_RESTARTING),
+     .o_ERROR_CODE_Q(o_ERROR_CODE_Q),
+     .o_FATAL_ERROR(o_FATAL_ERROR),
+    .i_READ_REQUEST(i_READ_REQUEST),
+    .o_DATA_TO_CORE(o_DATA_TO_CORE),
+    .ReadData(ReadData),     
+    .o_DATA_VALID(o_DATA_VALID),
+    .o_LAST_NIBBLE(o_LAST_NIBBLE),
+    .i_COUNT_IN_MAX(i_COUNT_IN_MAX),
+     .LIMIT_SD_TIMERS(1'b1));
+
+  sdModel sdcard
+    (.sdClk(o_SD_CLK),
+    .cmd(PAD), 
+    .dat(i_SD_DAT));
+  
+  // tri state pad
+  // replace with I/O standard cell or FPGA gate.
+  assign PAD = o_SD_CMD_OE ? o_SD_CMD : 1'bz;
+  assign i_SD_CMD = PAD;
+  
+
+  always
+    begin
+      r_CLK = 1; # 5; r_CLK = 0; # 5;
+    end
+  
+
+  initial $readmemh("ramdisk2.hex", sdcard.FLASHmem);
+  
+  initial begin
+
+    a_RST          = 1'b0;
+    i_BLOCK_ADDR   = 24'h100000;
+    i_COUNT_IN_MAX = '0;
+    i_READ_REQUEST = 1'b0;
+
+    # 5;
+    i_COUNT_IN_MAX = -62;
+
+    # 10;
+    a_RST = 1'b1;
+
+    # 4800;
+    
+    a_RST = 1'b0;
+
+    # 2000000;
+    i_READ_REQUEST = 1'b0;
+    # 10000;
+    i_READ_REQUEST = 1'b1;
+    # 10000;
+    i_READ_REQUEST = 1'b0;
+    
+  end
+
+endmodule
diff --git a/testbench/sdc/wave.do b/pipelined/testbench/sdc/wave.do
similarity index 100%
rename from testbench/sdc/wave.do
rename to pipelined/testbench/sdc/wave.do
diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv
new file mode 100644
index 000000000..62a739c40
--- /dev/null
+++ b/pipelined/testbench/testbench-fp.sv
@@ -0,0 +1,1338 @@
+///////////////////////////////////////////
+//
+// Written: me@KatherineParry.com
+// Modified: 7/5/2022
+//
+// Purpose: Testbench for Testfloat
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+`include "wally-config.vh"
+`include "tests-fp.vh"
+
+// steps to run FMA Tests
+//    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
+//    2) go to riscv-wally/pipelined/testbench/fp/Tests
+//    3) run ./sim-fma-batch
+module testbenchfp;
+  parameter TEST="none";
+
+  string      Tests[];        // list of tests to be run
+  logic [2:0] OpCtrl[];       // list of op controls
+  logic [2:0] Unit[];         // list of units being tested
+  logic WriteInt[];           // Is being written to integer resgiter
+  logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
+  logic [1:0] Fmt[];          // list of formats for the other units
+  
+
+  logic               clk=0;
+  logic [31:0]        TestNum=0;    // index for the test
+  logic [31:0]        OpCtrlNum=0;  // index for OpCtrl
+  logic [31:0]        errors=0;     // how many errors
+  logic [31:0]        VectorNum=0;  // index for test vector
+  logic [31:0]        FrmNum=0;     // index for rounding mode
+  logic [`FLEN*4+7:0] TestVectors[8388609:0];     // list of test vectors
+
+  logic [1:0]           FmtVal;          // value of the current Fmt
+  logic [2:0]           UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
+  logic                 WriteIntVal;                // value of the current WriteInt
+  logic [`FLEN-1:0]     X, Y, Z;                    // inputs read from TestFloat
+  logic [`XLEN-1:0]     SrcA;                       // integer input
+  logic [`FLEN-1:0]	    Ans;                        // correct answer from TestFloat
+  logic [`FLEN-1:0]	    Res;                        // result from other units
+  logic [4:0]	 	        AnsFlg;                     // correct flags read from testfloat
+  logic [4:0]	 	        ResFlg, Flg;                // Result flags
+  logic	[`FMTBITS-1:0]  ModFmt;                     // format - 10 = half, 00 = single, 01 = double, 11 = quad
+  logic [`FLEN-1:0]     FpRes, FpCmpRes;            // Results from each unit
+  logic [`XLEN-1:0]     IntRes, CmpRes;             // Results from each unit
+  logic [4:0]           FmaFlg, CvtFlg, DivFlg, CmpFlg;  // Outputed flags
+  logic                 AnsNaN, ResNaN, NaNGood;
+  logic                 Xs, Ys, Zs;                 // sign of the inputs
+  logic [`NE-1:0]       Xe, Ye, Ze;                 // exponent of the inputs
+  logic [`NF:0]         Xm, Ym, Zm;                 // mantissas of the inputs
+  logic                 XNaN, YNaN, ZNaN;           // is the input NaN
+  logic                 XSNaN, YSNaN, ZSNaN;        // is the input a signaling NaN
+  logic                 XSubnorm, ZSubnorm;           // is the input denormalized
+  logic                 XInf, YInf, ZInf;           // is the input infinity
+  logic                 XZero, YZero, ZZero;        // is the input zero
+  logic                 XExpMax, YExpMax, ZExpMax;  // is the input's exponent all ones  
+  logic  [`CVTLEN-1:0]  CvtLzcInE;                  // input to the Leading Zero Counter (priority encoder)
+  logic                 IntZero;
+  logic                 CvtResSgnE;
+  logic [`NE:0]         CvtCalcExpE;    // the calculated expoent
+	logic [`LOGCVTLEN-1:0] CvtShiftAmtE;  // how much to shift by
+	logic [`DIVb:0]       Quot;
+  logic                 CvtResSubnormUfE;
+  logic                 DivStart, FDivBusyE, OldFDivBusyE;
+  logic                 reset = 1'b0;
+  logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
+  logic [`DURLEN-1:0]   Dur;
+
+  // in-between FMA signals
+  logic                 Mult;
+  logic                 Ss;
+  logic [`NE+1:0]	      Pe;
+  logic [`NE+1:0]	      Se;
+  logic 				        ASticky;
+  logic 					      KillProd; 
+  logic [$clog2(3*`NF+5)-1:0]	SCnt;
+  logic [3*`NF+3:0]	    Sm;       
+  logic 			          InvA;
+  logic 			          NegSum;
+  logic 			          As;
+  logic 			          Ps;
+  logic                 DivSticky;
+  logic                 DivDone;
+  logic                 DivNegSticky;
+  logic [`NE+1:0]       DivCalcExp;
+  logic                 divsqrtop;
+
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  //     ||||||||| |||||||| ||||||| |||||||||   ||||||| |||||||| |||
+  //        |||    |||      |||        |||      |||     |||      |||
+  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||
+  //        |||    |||          |||    |||          ||| |||      |||
+  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||||||||
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  // select tests relevent to the specified configuration
+  //    cvtint - test integer conversion unit (fcvtint)
+  //    cvtfp  - test floating-point conversion unit (fcvtfp)
+  //    cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
+  //    add    - test addition
+  //    sub    - test subtraction
+  //    div    - test division
+  //    sqrt   - test square root
+  //    all    - test all of the above
+  initial begin
+    $display("TEST is %s", TEST);
+    if (`Q_SUPPORTED) begin // if Quad percision is supported
+      if (TEST === "cvtint"| TEST === "all") begin  // if testing integer conversion
+                                              // add the 128-bit cvtint tests to the to-be-tested list
+                                              Tests = {Tests, f128rv32cvtint};
+                                              // add the op-codes for these tests to the op-code list
+                                              OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
+                                              WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                              // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b11};
+                                              end
+                                              if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
+                                                Tests = {Tests, f128rv64cvtint};
+                                              // add the op-codes for these tests to the op-code list
+                                                OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+                                                WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                              // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b11};
+                                              end
+                                              end
+                                            end
+      if (TEST === "cvtfp" | TEST === "all") begin  // if the floating-point conversions are being tested
+        if(`D_SUPPORTED) begin // if double precision is supported
+          // add the 128 <-> 64 bit conversions to the to-be-tested list
+          Tests = {Tests, f128f64cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b01, 3'b11};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b01};
+          end
+        end
+        if(`F_SUPPORTED) begin // if single precision is supported
+          // add the 128 <-> 32 bit conversions to the to-be-tested list
+          Tests = {Tests, f128f32cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b00, 3'b11};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b00};
+          end
+        end
+        if(`ZFH_SUPPORTED) begin // if half precision is supported
+          // add the 128 <-> 16 bit conversions to the to-be-tested list
+          Tests = {Tests, f128f16cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b10, 3'b11};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b10};
+          end
+        end
+      end
+      if (TEST === "cmp"   | TEST === "all") begin// if comparisons are being tested
+        // add the compare tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128cmp};
+        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+          for(int i = 0; i<15; i++) begin
+            Unit = {Unit, `CMPUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
+        // add the addition tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128add};
+        OpCtrl = {OpCtrl, `ADD_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `FMAUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "sub"   | TEST === "all") begin // if subtraction is being tested
+        // add the subtraction tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128sub};
+        OpCtrl = {OpCtrl, `SUB_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `FMAUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
+        // add the multiply tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128mul};
+        OpCtrl = {OpCtrl, `MUL_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `FMAUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "div"   | TEST === "all") begin // if division is being tested
+        // add the divide tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128div};
+        OpCtrl = {OpCtrl, `DIV_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `DIVUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tested
+        // add the square-root tests/op-ctrls/unit/fmt
+        Tests = {Tests, f128sqrt};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `DIVUNIT};
+            Fmt = {Fmt, 2'b11};
+          end
+      end
+      if (TEST === "fma"   | TEST === "all") begin  // if fused-mutliply-add is being tested
+        Tests = {Tests, f128fma};
+        OpCtrl = {OpCtrl, `FMA_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b11};
+        end
+      end
+    end
+    if (`D_SUPPORTED) begin // if double precision is supported
+      if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
+                                              Tests = {Tests, f64rv32cvtint};
+                                              // add the op-codes for these tests to the op-code list
+                                              OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
+                                              WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                              // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b01};
+                                              end
+                                              if (`XLEN == 64) begin // if 64-bit integers are being supported
+                                                Tests = {Tests, f64rv64cvtint};
+                                                // add the op-codes for these tests to the op-code list
+                                                OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+                                                WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                                // add what unit is used and the fmt to their lists (one for each test)
+                                                for(int i = 0; i<20; i++) begin
+                                                  Unit = {Unit, `CVTINTUNIT};
+                                                  Fmt = {Fmt, 2'b01};
+                                                end
+                                              end
+                                            end
+      if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
+        if(`F_SUPPORTED) begin // if single precision is supported
+          // add the 64 <-> 32 bit conversions to the to-be-tested list
+          Tests = {Tests, f64f32cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b00, 3'b01};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b01};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b00};
+          end
+        end
+        if(`ZFH_SUPPORTED) begin // if half precision is supported
+          // add the 64 <-> 16 bit conversions to the to-be-tested list
+          Tests = {Tests, f64f16cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b10, 3'b01};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b01};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b10};
+          end
+        end
+      end
+      if (TEST === "cmp"   | TEST === "all") begin // if comparisions are being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64cmp};
+        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+        for(int i = 0; i<15; i++) begin
+          Unit = {Unit, `CMPUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64add};
+        OpCtrl = {OpCtrl, `ADD_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "sub"   | TEST === "all") begin // if subtration is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64sub};
+        OpCtrl = {OpCtrl, `SUB_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64mul};
+        OpCtrl = {OpCtrl, `MUL_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "div"   | TEST === "all") begin // if division is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64div};
+        OpCtrl = {OpCtrl, `DIV_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tessted
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f64sqrt};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+      if (TEST === "fma"   | TEST === "all") begin // if the fused multiply add is being tested
+        Tests = {Tests, f64fma};
+        OpCtrl = {OpCtrl, `FMA_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b01};
+        end
+      end
+    end
+    if (`F_SUPPORTED) begin // if single precision being supported
+      if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
+                                              Tests = {Tests, f32rv32cvtint};
+                                              // add the op-codes for these tests to the op-code list
+                                              OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
+                                              WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                              // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b00};
+                                              end
+                                              if (`XLEN == 64) begin // if 64-bit integers are supported
+                                                Tests = {Tests, f32rv64cvtint};
+                                                // add the op-codes for these tests to the op-code list
+                                                OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+                                                WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                                // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b00};
+                                              end
+                                              end
+                                            end
+      if (TEST === "cvtfp" | TEST === "all") begin  // if floating point conversion is being tested
+        if(`ZFH_SUPPORTED) begin 
+          // add the 32 <-> 16 bit conversions to the to-be-tested list
+          Tests = {Tests, f32f16cvt};
+          // add the op-ctrls (i.e. the format of the result)
+          OpCtrl = {OpCtrl, 3'b10, 3'b00};
+          WriteInt = {WriteInt, 1'b0, 1'b0};
+          // add the unit being tested and fmt (input format)
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b00};
+          end
+          for(int i = 0; i<5; i++) begin
+            Unit = {Unit, `CVTFPUNIT};
+            Fmt = {Fmt, 2'b10};
+          end
+        end
+      end
+      if (TEST === "cmp"   | TEST === "all") begin // if comparision is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32cmp};
+        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+        for(int i = 0; i<15; i++) begin
+          Unit = {Unit, `CMPUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "add"   | TEST === "all") begin // if addition is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32add};
+        OpCtrl = {OpCtrl, `ADD_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "sub"   | TEST === "all") begin // if subtration is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32sub};
+        OpCtrl = {OpCtrl, `SUB_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "mul"   | TEST === "all") begin // if multiply is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32mul};
+        OpCtrl = {OpCtrl, `MUL_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "div"   | TEST === "all") begin // if division is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32div};
+        OpCtrl = {OpCtrl, `DIV_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f32sqrt};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+      if (TEST === "fma"   | TEST === "all")  begin // if fma is being tested
+        Tests = {Tests, f32fma};
+        OpCtrl = {OpCtrl, `FMA_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b00};
+        end
+      end
+    end
+    if (`ZFH_SUPPORTED) begin // if half precision supported
+      if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
+                                              Tests = {Tests, f16rv32cvtint};
+                                              // add the op-codes for these tests to the op-code list
+                                              OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
+                                              WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                              // add what unit is used and the fmt to their lists (one for each test)
+                                              for(int i = 0; i<20; i++) begin
+                                                Unit = {Unit, `CVTINTUNIT};
+                                                Fmt = {Fmt, 2'b10};
+                                              end
+                                              if (`XLEN == 64) begin // if 64-bit integers are supported
+                                                Tests = {Tests, f16rv64cvtint};
+                                                // add the op-codes for these tests to the op-code list
+                                                OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
+                                                WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
+                                                // add what unit is used and the fmt to their lists (one for each test)
+                                                for(int i = 0; i<20; i++) begin
+                                                  Unit = {Unit, `CVTINTUNIT};
+                                                  Fmt = {Fmt, 2'b10};
+                                                end
+                                              end
+                                            end
+      if (TEST === "cmp"   | TEST === "all") begin // if comparisions are being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f16cmp};
+        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
+        for(int i = 0; i<15; i++) begin
+          Unit = {Unit, `CMPUNIT};
+          Fmt = {Fmt, 2'b10};
+        end
+      end
+      if (TEST === "add"   | TEST === "all") begin //  if addition is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f16add};
+        OpCtrl = {OpCtrl, `ADD_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b10};
+        end
+      end
+      if (TEST === "sub"   | TEST === "all") begin // if subtraction is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f16sub};
+        OpCtrl = {OpCtrl, `SUB_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b10};
+        end
+      end
+      if (TEST === "mul"   | TEST === "all") begin // if multiplication is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {Tests, f16mul};
+        OpCtrl = {OpCtrl, `MUL_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b10};
+        end
+      end
+      if (TEST === "div"   | TEST === "all") begin // if division is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        Tests = {f16div, Tests};
+        OpCtrl = {`DIV_OPCTRL, OpCtrl};
+        WriteInt = {1'b0, WriteInt};
+        for(int i = 0; i<5; i++) begin
+          Unit = {`DIVUNIT, Unit};
+          Fmt = {2'b10, Fmt};
+        end
+        /* Tests = {Tests, f16div};
+        OpCtrl = {OpCtrl, `DIV_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b10};
+        end */
+      end
+      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
+        // add the correct tests/op-ctrls/unit/fmt to their lists
+        // reverse order
+        Tests = {f16sqrt, Tests};
+        OpCtrl = {`SQRT_OPCTRL, OpCtrl};
+        WriteInt = {1'b0, WriteInt};
+        for(int i = 0; i<5; i++) begin
+          Unit = {`DIVUNIT, Unit};
+          Fmt = {2'b10, Fmt};
+        end
+/*        Tests = {Tests, f16sqrt};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `DIVUNIT};
+          Fmt = {Fmt, 2'b10};
+        end */
+      end
+      if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
+        Tests = {Tests, f16fma};
+        OpCtrl = {OpCtrl, `FMA_OPCTRL};
+        WriteInt = {WriteInt, 1'b0};
+        for(int i = 0; i<5; i++) begin
+          Unit = {Unit, `FMAUNIT};
+          Fmt = {Fmt, 2'b10};
+        end
+      end
+    end
+
+    // check if nothing is being tested
+    if (Tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  //     ||||||||| |||||||| ||||||||| |||||||     ||||||||| |||||||| ||||||| |||||||||   
+  //     |||   ||| |||      |||   ||| ||   ||        |||    |||      |||        |||      
+  //     ||||||||  |||||||| ||||||||| ||   ||        |||    |||||||| |||||||    |||      
+  //     |||  ||   |||      |||   ||| ||   ||        |||    |||          |||    |||      
+  //     |||   ||| |||||||| |||   ||| |||||||        |||    |||||||| |||||||    |||      
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  // Read the first test
+  initial begin
+    $display("\n\nRunning %s vectors", Tests[TestNum]);
+    $readmemh({`PATH, Tests[TestNum]}, TestVectors);
+    // set the test index to 0
+    TestNum = 0;
+  end
+
+  // set a the signals for all tests
+  always_comb UnitVal = Unit[TestNum];
+  always_comb FmtVal = Fmt[TestNum];
+  always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
+  always_comb WriteIntVal = WriteInt[OpCtrlNum];
+  always_comb FrmVal = Frm[FrmNum];
+
+  // modify the format signal if only 2 percisions supported
+  //    - 1 for the larger precision
+  //    - 0 for the smaller precision
+  always_comb begin
+    if(`FMTBITS == 1) ModFmt = FmtVal == `FMT;
+    else ModFmt = FmtVal;
+  end
+
+  // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
+  readvectors readvectors          (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, 
+                                    .Xs, .Ys, .Zs, .Unit(UnitVal),
+                                    .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
+                                    .Xm, .Ym, .Zm, .DivStart,
+                                    .XNaN, .YNaN, .ZNaN,
+                                    .XSNaN, .YSNaN, .ZSNaN, 
+                                    .XSubnorm, .ZSubnorm, 
+                                    .XZero, .YZero, .ZZero,
+                                    .XInf, .YInf, .ZInf, .XExpMax,
+                                    .X, .Y, .Z);
+
+
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  //     |||||||   |||   ||| ||||||||| 
+  //     |||   ||| |||   |||    |||    
+  //     |||   ||| |||   |||    |||    
+  //     |||   ||| |||   |||    |||         
+  //     |||||||   |||||||||    |||    
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  // instantiate devices under test
+  if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma
+    fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), 
+            .Xe(Xe), .Ye(Ye), .Ze(Ze), 
+            .Xm(Xm), .Ym(Ym), .Zm(Zm),
+            .XZero, .YZero, .ZZero, .Ss, .Se,
+            .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
+            .ASticky); 
+  end
+              
+  postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
+              .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
+              .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
+              .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
+              .XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
+              .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
+              .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
+              .FmaASticky(ASticky), .FmaSe(Se),
+              .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), 
+              .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
+  
+  if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
+    fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), 
+              .XZero(XZero), .XSubnorm(XSubnorm), .OpCtrl(OpCtrlVal), .IntZero,
+              .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
+  end
+
+  if (TEST === "cmp" | TEST === "all") begin: fcmp
+    fcmp fcmp   (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
+                .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
+                .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
+  end
+  if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
+    fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
+                    .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), 
+                    .FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0),
+                    .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+                    .QmM(Quot));
+  end
+
+  assign CmpFlg[3:0] = 0;
+
+  // produce clock
+  always begin
+    clk = 1; #5; clk = 0; #5;
+  end
+  
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//          |||||      |||  ||||||||||  |||||      |||
+//          |||||||    |||  |||    |||  |||||||    |||
+//          |||| |||   |||  ||||||||||  |||| |||   |||
+//          ||||  |||  |||  |||    |||  ||||  |||  |||
+//          ||||   ||| |||  |||    |||  ||||   ||| |||
+//          ||||    ||||||  |||    |||  ||||    ||||||
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+  //Check if the correct answer and result is a NaN
+  always_comb begin
+    if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
+      // an integer output can't be a NaN
+      AnsNaN = 1'b0;
+      ResNaN = 1'b0;
+    end
+    else if (UnitVal === `CVTFPUNIT) begin
+      case (OpCtrlVal[1:0])
+          4'b11: begin // quad             
+            AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]);
+            ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]);
+          end
+          4'b01: begin // double                 
+            AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]);
+            ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]);
+          end
+          4'b00: begin // single
+            AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]);
+            ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]);
+          end
+          4'b10: begin // half
+            AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]);
+            ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]);
+          end
+      endcase
+    end
+    else begin
+      case (FmtVal)
+          4'b11: begin // quad             
+            AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]);
+            ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]);
+          end
+          4'b01: begin // double                 
+            AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]);
+            ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]);
+          end
+          4'b00: begin // single
+            AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]);
+            ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]);
+          end
+          4'b10: begin // half
+            AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]);
+            ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]);
+          end
+      endcase
+    end
+  end
+always_comb begin
+    // select the result to check
+    case (UnitVal)
+      `FMAUNIT: Res = FpRes;
+      `DIVUNIT: Res = FpRes;
+      `CMPUNIT: Res = CmpRes;
+      `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes;
+      `CVTFPUNIT: Res = FpRes;
+    endcase
+
+    // select the flag to check
+    case (UnitVal)
+      `FMAUNIT: ResFlg = Flg;
+      `DIVUNIT: ResFlg = Flg;
+      `CMPUNIT: ResFlg = CmpFlg;
+      `CVTINTUNIT: ResFlg = Flg;
+      `CVTFPUNIT: ResFlg = Flg;
+    endcase
+end
+
+  logic ResMatch, FlagMatch, CheckNow;
+
+always @(posedge clk) 
+  OldFDivBusyE = FDivBusyE;
+
+// check results on falling edge of clk
+always @(negedge clk) begin
+
+
+    // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
+    //    - the sign of the NaN does not matter for the opperations being tested
+    //    - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
+    if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
+      case (FmtVal)
+        4'b11: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
+                          (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | 
+                          (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) |
+                          (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]})));
+        4'b01: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
+                          (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | 
+                          (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) |
+                          (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]})));
+        4'b00: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
+                          (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | 
+                          (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) |
+                          (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]})));
+        4'b10: NaNGood =  (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
+                          (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | 
+                          (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) |
+                          (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]})));
+      endcase
+    else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
+      case (OpCtrlVal[1:0]) 
+        2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) |
+                          (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | 
+                          (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | 
+                          (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})));
+        2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) |
+                          (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | 
+                          (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | 
+                          (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})));
+        2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) |
+                          (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | 
+                          (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | 
+                          (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})));
+        2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
+                          (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) |
+                          (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | 
+                          (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | 
+                          (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})));
+      endcase
+    else NaNGood = 1'b0; // integers can't be NaNs
+
+    
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+  //     ||||||| |||    ||| ||||||| ||||||| |||   |||
+  //     |||     |||    ||| |||     |||     |||  |||
+  //     |||     |||||||||| ||||||| |||     ||||||
+  //     |||     |||    ||| |||     |||     |||  |||
+  //     ||||||| |||    ||| ||||||| ||||||| |||    |||
+
+  ///////////////////////////////////////////////////////////////////////////////////////////////
+
+    // check if result is correct
+    //  - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
+   // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
+    ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
+    FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
+    divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
+    assign DivDone = OldFDivBusyE & ~FDivBusyE;
+
+    //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL;
+    CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT);
+    if(~(ResMatch & FlagMatch) & CheckNow) begin
+//    if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
+      errors += 1;
+      $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
+      $display("Error in %s", Tests[TestNum]);
+      $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+      $stop;
+    end
+    
+    // TestFloat sets the result to all 1's when there is an invalid result, however in 
+    // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says
+    // for an unsigned integer result 0 is also okay
+
+    // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but 
+    // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff...
+    else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | 
+            (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | 
+            (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | 
+            (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin
+      errors += 1;
+      $display("There is an error in %s", Tests[TestNum]);
+      $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+      $stop;
+    end
+
+    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
+
+    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
+
+      // increment the test
+      TestNum += 1;
+
+      // clear the vectors
+      for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}};
+      // read next files
+      $readmemh({`PATH, Tests[TestNum]}, TestVectors);
+
+      // set the vector index back to 0
+      VectorNum = 0;
+      // incemet the operation if all the rounding modes have been tested
+      if(FrmNum === 4) OpCtrlNum += 1;
+      // increment the rounding mode or loop back to rne 
+      if(FrmNum < 4) FrmNum += 1;
+      else FrmNum = 0; 
+
+      // if no more Tests - finish
+      if(Tests[TestNum] === "") begin
+        $display("\nAll Tests completed with %d errors\n", errors);
+        $stop;
+      end 
+
+      $display("Running %s vectors", Tests[TestNum]);
+    end
+  end
+endmodule
+
+
+
+
+module readvectors (
+  input logic clk,
+  input logic [`FLEN*4+7:0] TestVector,
+  input logic [`FMTBITS-1:0] ModFmt,
+  input logic [1:0] Fmt,
+  input logic [2:0] Unit,
+  input logic [31:0] VectorNum,
+  input logic [31:0] TestNum,
+  input logic [2:0] OpCtrl,
+  output logic [`FLEN-1:0] Ans,
+  output logic [`XLEN-1:0] SrcA,
+  output logic [4:0] AnsFlg,
+  output logic                    Xs, Ys, Zs,    // sign bits of XYZ
+  output logic [`NE-1:0]          Xe, Ye, Ze,    // exponents of XYZ (converted to largest supported precision)
+  output logic [`NF:0]            Xm, Ym, Zm,    // mantissas of XYZ (converted to largest supported precision)
+  output logic                    XNaN, YNaN, ZNaN,    // is XYZ a NaN
+  output logic                    XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
+  output logic                    XSubnorm, ZSubnorm,   // is XYZ denormalized
+  output logic                    XZero, YZero, ZZero,         // is XYZ zero
+  output logic                    XInf, YInf, ZInf,            // is XYZ infinity
+  output logic                    XExpMax,
+  output logic                    DivStart,
+  output logic [`FLEN-1:0] X, Y, Z
+);
+  logic XEn, YEn, ZEn;
+
+  // apply test vectors on rising edge of clk
+  // Format of vectors Inputs(1/2/3)_AnsFlg
+  always @(VectorNum) begin
+    #1; 
+    AnsFlg = TestVector[4:0];
+    DivStart = 1'b0;
+    case (Unit)
+      `FMAUNIT:
+        case (Fmt)
+          2'b11: begin       // quad
+            if(OpCtrl === `FMA_OPCTRL) begin
+              X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)];
+              Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
+              Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN];
+            end
+            else begin
+              X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
+              if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)};
+              if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
+            end
+            Ans = TestVector[8+(`Q_LEN-1):8];
+          end
+          2'b01:	if (`D_SUPPORTED)begin	  // double
+            if(OpCtrl === `FMA_OPCTRL) begin
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]};
+              Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
+              Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]};
+            end
+            else begin
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
+              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; 
+              else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)};
+              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; 
+              else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
+            end
+            Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+          end
+          2'b00:	if (`S_SUPPORTED)begin	  // single
+            if(OpCtrl === `FMA_OPCTRL) begin
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]};
+              Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
+              Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]};
+            end
+            else begin
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
+              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; 
+              else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)};
+              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; 
+              else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]};
+            end
+            Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+          end
+          2'b10:	begin	  // half
+            if(OpCtrl === `FMA_OPCTRL) begin
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]};
+              Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
+              Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]};
+            end
+            else begin
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
+              if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; 
+              else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)};
+              if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; 
+              else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
+            end
+            Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+          end
+        endcase
+      `DIVUNIT:
+        if(OpCtrl[0])
+          case (Fmt)
+            2'b11: begin       // quad
+              X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
+              Ans = TestVector[8+(`Q_LEN-1):8];
+              if (~clk) #5;
+              DivStart = 1'b1; #10 // one clk cycle
+              DivStart = 1'b0;
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b00:	if (`S_SUPPORTED)begin	  // single
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+          endcase
+        else
+          case (Fmt)
+            2'b11: begin       // quad
+              X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
+              Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
+              Ans = TestVector[8+(`Q_LEN-1):8];
+              if (~clk) #5;
+              DivStart = 1'b1; #10 // one clk cycle
+              DivStart = 1'b0;
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
+              Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b00:	if (`S_SUPPORTED)begin	  // single
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
+              Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
+              Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+          endcase
+      `CMPUNIT:
+        case (Fmt)        
+          2'b11: begin       // quad
+            X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)];
+            Y = TestVector[12+(`Q_LEN)-1:12];
+            Ans = TestVector[8];
+          end
+          2'b01:	if (`D_SUPPORTED)begin	  // double
+            X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]};
+            Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]};
+            Ans = TestVector[8];
+          end
+          2'b00:	if (`S_SUPPORTED)begin	  // single
+            X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]};
+            Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]};
+            Ans = TestVector[8];
+          end
+          2'b10:	begin	  // half
+            X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]};
+            Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]};
+            Ans = TestVector[8];
+          end
+        endcase
+      `CVTFPUNIT:
+        case (Fmt)
+          2'b11: begin       // quad
+          case (OpCtrl[1:0])
+            2'b11: begin       // quad
+              X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]};
+              Ans = TestVector[8+(`Q_LEN-1):8];
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+            end
+            2'b00:	begin	  // single
+              X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+            end
+            2'b10:	begin	  // half
+              X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+            end
+          endcase
+          end
+          2'b01:	if (`D_SUPPORTED)begin	  // double
+          case (OpCtrl[1:0])
+            2'b11: begin       // quad
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]};
+              Ans = TestVector[8+(`Q_LEN-1):8];
+            end
+            2'b01:	begin	  // double
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+            end
+            2'b00:	begin	  // single
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+            end
+          endcase
+          end
+          2'b00:	if (`S_SUPPORTED)begin	  // single
+          case (OpCtrl[1:0])
+            2'b11: begin       // quad
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]};
+              Ans = TestVector[8+(`Q_LEN-1):8];
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+            end
+            2'b00:	begin	  // single
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+            end
+          endcase
+          end
+          2'b10:	begin	  // half
+          case (OpCtrl[1:0])
+            2'b11: begin       // quad
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]};
+              Ans = TestVector[8+(`Q_LEN-1):8];
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+            end
+            2'b00:	if (`S_SUPPORTED)begin	  // single
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+            end
+          endcase
+          end
+        endcase
+        
+      `CVTINTUNIT:
+        case (Fmt)
+          2'b11: begin       // quad
+            //     {is the integer a long,     is the opperation to an integer}
+            casex ({OpCtrl[2:1]})
+              2'b11: begin       // long -> quad
+                X = {`FLEN{1'bx}};
+                SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)];
+                Ans = TestVector[8+(`Q_LEN-1):8];
+              end
+              2'b10:	begin	  // int -> quad
+                // correctly sign extend the integer depending on if it's a signed/unsigned test
+                X = {`FLEN{1'bx}};
+                SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]};
+                Ans = TestVector[8+(`Q_LEN-1):8];
+              end
+              2'b01:	begin	  // quad -> long
+                X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {TestVector[8+(`XLEN-1):8]};
+              end
+              2'b00:	begin	  // quad -> int
+                X = {TestVector[8+32+`Q_LEN-1:8+(32)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+              end
+            endcase
+          end
+          2'b01:	if (`D_SUPPORTED)begin	  // double
+            //     {Int->Fp?, is the integer a long}
+            casex ({OpCtrl[2:1]})
+              2'b11: begin       // long -> double
+                X = {`FLEN{1'bx}};
+                SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)];
+                Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              end
+              2'b10:	begin	  // int -> double
+                // correctly sign extend the integer depending on if it's a signed/unsigned test
+                X = {`FLEN{1'bx}};
+                SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]};
+                Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              end
+              2'b01:	begin	  // double -> long
+                X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {TestVector[8+(`XLEN-1):8]};
+              end
+              2'b00:	begin	  // double -> int
+                X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+              end
+            endcase
+          end
+          2'b00:	if (`S_SUPPORTED)begin	  // single
+            //     {is the integer a long,     is the opperation to an integer}
+            casex ({OpCtrl[2:1]})
+              2'b11: begin       // long -> single
+                X = {`FLEN{1'bx}};
+                SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)];
+                Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              end
+              2'b10:	begin	  // int -> single
+                // correctly sign extend the integer depending on if it's a signed/unsigned test
+                X = {`FLEN{1'bx}};
+                SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]};
+                Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              end
+              2'b01:	begin	  // single -> long
+                X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {TestVector[8+(`XLEN-1):8]};
+              end
+              2'b00:	begin	  // single -> int
+                X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
+              end
+            endcase
+          end
+          2'b10:	begin	  // half
+            //     {is the integer a long,     is the opperation to an integer}
+            casex ({OpCtrl[2:1]})
+              2'b11: begin       // long -> half
+                X = {`FLEN{1'bx}};
+                SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)];
+                Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              end
+              2'b10:	begin	  // int -> half
+                // correctly sign extend the integer depending on if it's a signed/unsigned test
+                X = {`FLEN{1'bx}};
+                SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]};
+                Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              end
+              2'b01:	begin	  // half -> long
+                X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {TestVector[8+(`XLEN-1):8]};
+              end
+              2'b00:	begin	  // half -> int
+                X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]};
+                SrcA = {`XLEN{1'bx}};
+                Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
+              end
+            endcase
+          end
+        endcase
+    endcase  
+  end
+  
+  assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
+  assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
+  assign ZEn = (Unit == `FMAUNIT);
+  
+  unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
+                .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
+                .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
+                .XEn, .YEn, .ZEn, .XExpMax);
+endmodule
\ No newline at end of file
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
new file mode 100644
index 000000000..da369250e
--- /dev/null
+++ b/pipelined/testbench/testbench-linux.sv
@@ -0,0 +1,872 @@
+///////////////////////////////////////////
+// testbench-linux.sv
+//
+// Written: nboorstin@g.hmc.edu 2021
+// Modified: 
+//
+// Purpose: Testbench for Buildroot Linux
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+// When letting Wally go for it, let wally make own interrupts
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+`define DEBUG_TRACE 0
+// Debug Levels
+// 0: don't check against QEMU
+// 1: print disagreements with QEMU, but only halt on PCW disagreements
+// 2: halt on any disagreement with QEMU except CSRs
+// 3: halt on all disagreements with QEMU
+// 4: print memory accesses whenever they happen
+// 5: print everything
+
+module testbench;
+  ///////////////////////////////////////////////////////////////////////////////
+  /////////////////////////////////// CONFIG ////////////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  // Recommend setting all of these in 'do' script using -G option
+  parameter INSTR_LIMIT  = 0; // # of instructions at which to stop
+  parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
+  parameter CHECKPOINT   = 0;
+  parameter RISCV_DIR = "/opt/riscv";
+  parameter NO_SPOOFING = 0;
+
+
+
+
+
+
+
+
+
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS /////////////////////////
+  ////////////////////////////////////////////////////////////////////////////////////
+  // ========== Testbench Core ==========
+  integer warningCount = 0;
+  integer errorCount = 0;
+  integer fault;
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
+  // ========== Initialization ==========
+  string  testvectorDir;
+  string  linuxImageDir;
+  integer memFile;
+  integer readResult;
+  // ========== Checkpointing ==========
+  string checkpointDir;
+  logic [1:0] initPriv;
+  // ========== Trace parsing & checking ==========
+  integer garbageInt;
+  string  garbageString;
+  `define DECLARE_TRACE_SCANNER_SIGNALS(STAGE) \
+      integer traceFile``STAGE; \
+      integer matchCount``STAGE; \
+      string  line``STAGE; \
+      string  token``STAGE; \
+      string  ExpectedTokens``STAGE [31:0]; \
+      integer index``STAGE; \
+      integer StartIndex``STAGE, EndIndex``STAGE; \
+      integer TokenIndex``STAGE; \
+      integer MarkerIndex``STAGE; \
+      integer NumCSR``STAGE; \
+      logic [`XLEN-1:0] ExpectedPC``STAGE; \
+      logic [31:0]      ExpectedInstr``STAGE; \
+      string            text``STAGE; \
+      string            MemOp``STAGE; \
+      string            RegWrite``STAGE; \
+      integer           ExpectedRegAdr``STAGE; \
+      logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
+      logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
+      string            ExpectedCSRArray``STAGE[10:0]; \
+      logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
+  `DECLARE_TRACE_SCANNER_SIGNALS(E)
+  `DECLARE_TRACE_SCANNER_SIGNALS(M)
+  //  M-stage expected values
+  logic             checkInstrM;
+  integer           MIPexpected, SIPexpected;
+  string            name;
+  logic [`AHBW-1:0] readDataExpected;
+  // W-stage expected values
+  logic             checkInstrW;
+  logic [`XLEN-1:0] ExpectedPCW;
+  logic [31:0]      ExpectedInstrW;
+  string            textW;
+  string            RegWriteW;
+  integer           ExpectedRegAdrW;
+  logic [`XLEN-1:0] ExpectedRegValueW;
+  string            MemOpW;
+  logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
+  integer           NumCSRW;
+  string            ExpectedCSRArrayW[10:0];
+  logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
+  logic [`XLEN-1:0] ExpectedIntType;
+  integer           NumCSRWIndex;
+  integer           NumCSRPostWIndex;
+  logic [`XLEN-1:0] InstrCountW;
+  // ========== Interrupt parsing & spoofing ==========
+  string  interrupt;
+  string  interruptLine;
+  integer interruptFile;
+  integer interruptInstrCount;
+  integer interruptHartVal;
+  integer interruptAsyncVal;
+  longint interruptCauseVal;
+  longint interruptEpcVal;
+  longint interruptTVal;
+  string  interruptDesc;
+  integer           NextMIPexpected, NextSIPexpected;
+  integer           NextMepcExpected;
+  logic [`XLEN-1:0] AttemptedInstructionCount;
+  // ========== Misc Aliases ==========
+  `define RF dut.core.ieu.dp.regf.rf
+  `define PC dut.core.ifu.pcreg.q
+  `define PRIV_BASE   dut.core.priv.priv
+  `define PRIV        `PRIV_BASE.privmode.privmode.privmodereg.q
+  `define CSR_BASE    `PRIV_BASE.csr
+  `define MEIP        `PRIV_BASE.MExtInt
+  `define SEIP        `PRIV_BASE.SExtInt
+  `define MTIP        `PRIV_BASE.MTimerInt
+  `define HPMCOUNTER  `CSR_BASE.counters.counters.HPMCOUNTER_REGW
+  `define MEDELEG     `CSR_BASE.csrm.deleg.MEDELEGreg.q
+  `define MIDELEG     `CSR_BASE.csrm.deleg.MIDELEGreg.q
+  `define MIE         `CSR_BASE.csri.MIE_REGW
+  `define MIP         `CSR_BASE.csri.MIP_REGW_writeable
+  `define MCAUSE      `CSR_BASE.csrm.MCAUSEreg.q
+  `define SCAUSE      `CSR_BASE.csrs.csrs.SCAUSEreg.q
+  `define MEPC        `CSR_BASE.csrm.MEPCreg.q
+  `define SEPC        `CSR_BASE.csrs.csrs.SEPCreg.q
+  `define MCOUNTEREN  `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q
+  `define SCOUNTEREN  `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
+  `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
+  `define SSCRATCH    `CSR_BASE.csrs.csrs.SSCRATCHreg.q
+  `define MTVEC       `CSR_BASE.csrm.MTVECreg.q
+  `define STVEC       `CSR_BASE.csrs.csrs.STVECreg.q
+  `define SATP        `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
+  `define INSTRET     `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2]
+  `define MSTATUS     `CSR_BASE.csrsr.MSTATUS_REGW
+  `define SSTATUS     `CSR_BASE.csrsr.SSTATUS_REGW  
+  `define STATUS_TSR  `CSR_BASE.csrsr.STATUS_TSR_INT
+  `define STATUS_TW   `CSR_BASE.csrsr.STATUS_TW_INT
+  `define STATUS_TVM  `CSR_BASE.csrsr.STATUS_TVM_INT
+  `define STATUS_MXR  `CSR_BASE.csrsr.STATUS_MXR_INT
+  `define STATUS_SUM  `CSR_BASE.csrsr.STATUS_SUM_INT
+  `define STATUS_MPRV `CSR_BASE.csrsr.STATUS_MPRV_INT
+  `define STATUS_FS   `CSR_BASE.csrsr.STATUS_FS_INT
+  `define STATUS_MPP  `CSR_BASE.csrsr.STATUS_MPP
+  `define STATUS_SPP  `CSR_BASE.csrsr.STATUS_SPP
+  `define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
+  `define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
+  `define STATUS_MIE  `CSR_BASE.csrsr.STATUS_MIE
+  `define STATUS_SIE  `CSR_BASE.csrsr.STATUS_SIE
+  `define UART dut.uncore.uncore.uart.uart.u
+  `define UART_IER `UART.IER
+  `define UART_LCR `UART.LCR
+  `define UART_MCR `UART.MCR
+  `define UART_SCR `UART.SCR
+  `define UART_IP `UART.INTR
+  `define PLIC dut.uncore.uncore.plic.plic
+  `define PLIC_INT_PRIORITY `PLIC.intPriority
+  `define PLIC_INT_ENABLE   `PLIC.intEn
+  `define PLIC_THRESHOLD    `PLIC.intThreshold
+  `define PCM dut.core.ifu.PCM
+  // ========== COMMON MACROS ==========
+  // Needed for initialization and core
+  `define SCAN_NEW_INTERRUPT \
+    begin \
+      $fgets(interruptLine, interruptFile); \
+      //$display("Time %t, interruptLine %x", $time, interruptLine); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%d", interruptInstrCount); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%d", interruptHartVal); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%d", interruptAsyncVal); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%x", interruptCauseVal); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%x", interruptEpcVal); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%x", interruptTVal); \
+      $fgets(interruptLine, interruptFile); \
+      $sscanf(interruptLine, "%s", interruptDesc); \
+    end 
+
+
+
+
+
+
+
+  ///////////////////////////////////////////////////////////////////////////////
+  /////////////////////////////// Cache Issue ///////////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  logic       probe;
+  if (NO_SPOOFING)
+    assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
+                   & testbench.dut.core.InstrM != 32'h14021273
+                   & testbench.dut.core.InstrValidM;
+
+
+
+
+
+
+
+
+  ///////////////////////////////////////////////////////////////////////////////
+  ////////////////////////////////// HARDWARE ///////////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  // Clock and Reset
+  logic clk, reset_ext; 
+  logic reset;
+  initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
+  always begin clk <= 1; # 5; clk <= 0; # 5; end
+  // Wally Interface
+  logic [`AHBW-1:0] HRDATAEXT;
+  logic             HREADYEXT, HRESPEXT;
+  logic             HCLK, HRESETn;
+  logic             HREADY;
+  logic 	    HSELEXT;
+  logic [`PA_BITS-1:0] HADDR;
+  logic [`AHBW-1:0] HWDATA;
+  logic [`XLEN/8-1:0] HWSTRB;
+  logic             HWRITE;
+  logic [2:0]       HSIZE;
+  logic [2:0]       HBURST;
+  logic [3:0]       HPROT;
+  logic [1:0]       HTRANS;
+  logic             HMASTLOCK;
+  logic [31:0]      GPIOPinsIn;
+  logic [31:0]      GPIOPinsOut, GPIOPinsEn;
+  logic             UARTSin, UARTSout;
+
+  // FPGA-specific Stuff
+  logic SDCCLK;
+  logic SDCCmdIn;
+  logic SDCCmdOut;
+  logic SDCCmdOE;
+  logic [3:0] SDCDatIn;
+
+  // Hardwire UART, GPIO pins
+  assign GPIOPinsIn = 0;
+  assign UARTSin = 1;
+
+  // Wally
+  wallypipelinedsoc dut(.clk, .reset, .reset_ext,
+                        .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
+			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
+			.HTRANS, .HMASTLOCK, 
+			.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout,
+			.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn);
+
+  // W-stage hardware not needed by Wally itself 
+  parameter nop = 'h13;
+  logic [`XLEN-1:0] PCW;
+  logic [31:0]      InstrW;
+  logic             InstrValidW;
+  logic [`XLEN-1:0] IEUAdrW, WriteDataW;
+  logic             TrapW;
+  `define FLUSHW dut.core.FlushW
+  `define STALLW dut.core.StallW
+  flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
+  flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
+  flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
+  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
+  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
+  flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
+
+
+
+
+
+
+
+
+
+
+  ///////////////////////////////////////////////////////////////////////////////
+  /////////////////////////////// INITIALIZATION ////////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  // ========== CHECKPOINTING ==========
+  `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
+    logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
+    initial begin \
+      #1; \
+      if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \
+    end
+
+  `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
+    `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
+    initial begin \
+      if (CHECKPOINT!=0) begin \
+        force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
+        while (reset!==1) #1; \
+        while (reset!==0) #1; \
+        #1; \
+        release `SIGNAL; \
+      end \
+    end
+
+  `define INIT_CHECKPOINT_PACKED_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
+    `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \
+    for (i=ARRAY_MIN; i<ARRAY_MAX+1; i=i+1) begin \
+      initial begin \
+        if (CHECKPOINT!=0) begin \
+          force `SIGNAL[i] = init``SIGNAL[i]; \
+          while (reset!==1) #1; \
+          while (reset!==0) #1; \
+          #1; \
+          release `SIGNAL[i]; \
+        end \
+      end \
+    end
+
+  // Note that dimension usage is very intentional here.
+  // We are dancing around (un)packed type requirements.
+  `define INIT_CHECKPOINT_VAL(SIGNAL,DIM) \
+    `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,0,0) \
+    initial begin \
+      if (CHECKPOINT!=0) begin \
+        force `SIGNAL = init``SIGNAL[0]; \
+        while (reset!==1) #1; \
+        while (reset!==0) #1; \
+        #1; \
+        release `SIGNAL; \
+      end \
+    end
+
+  // Initializing all zeroes into the branch predictor memory.
+  genvar adrindex;      
+    for(adrindex = 0; adrindex < 1024; adrindex++) begin
+      initial begin 
+      force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+      #1;
+      release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+      release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+      end
+    end
+
+  genvar i;
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(RF,         [`XLEN-1:0],31,1);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0);
+  `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
+  if(!NO_SPOOFING) begin
+    `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
+    `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
+    end
+  `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SCAUSE,     [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MEPC,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SEPC,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
+  `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
+  `INIT_CHECKPOINT_VAL(MSCRATCH,   [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SSCRATCH,   [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MTVEC,      [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(STVEC,      [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
+  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0);
+  `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
+  // UART checkpointing does not cover entire UART state
+  //     Many UART registers are difficult to initialize because under the hood
+  //     they are not simple registers. Instead some are generated by interesting
+  //     combinational blocks such that they depend upon a variety of different
+  //     underlying flops. See for example how RBR might be the actual RXBR
+  //     register, but it could also just as well be 0 or the tail of the fifo
+  //     array.
+  `INIT_CHECKPOINT_VAL(UART_IER,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_LCR,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_MCR,   [4:0]);
+  `INIT_CHECKPOINT_VAL(UART_SCR,   [7:0]);
+  // xSTATUS need to be handled manually because the most upstream signals
+  // are made of individual bits, not registers
+  `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);  
+
+  // ========== INITIALIZATION ==========
+  initial begin
+    if(!NO_SPOOFING) begin
+      force `MEIP = 0;
+      force `SEIP = 0;
+      force `UART_IP = 0;
+      force `MTIP = 0;
+    end
+    $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
+    $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
+    if (CHECKPOINT!=0)
+      $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
+    ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
+    ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
+    // initialize bootrom
+    memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb");
+    readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM,memFile);
+    $fclose(memFile);
+    // initialize RAM and ROM
+    if (CHECKPOINT==0) 
+      memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
+    else
+      memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
+    readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM,memFile);
+    $fclose(memFile);
+    // ---------- Ground-Zero -----------
+    if (CHECKPOINT==0) begin
+      traceFileM = $fopen({testvectorDir,"all.txt"}, "r");
+      traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
+      interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r");
+      `SCAN_NEW_INTERRUPT
+      InstrCountW = '0;
+      AttemptedInstructionCount = 1; // offset needed here when running from ground zero
+    // ---------- Checkpoint ----------
+    end else begin
+      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.uncore.ram.ram.memory.RAM);
+      traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
+      traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
+      interruptFile = $fopen({testvectorDir,"interrupts.txt"}, "r");
+      `SCAN_NEW_INTERRUPT
+      while(interruptInstrCount < CHECKPOINT) begin
+        `SCAN_NEW_INTERRUPT
+      end
+      InstrCountW = CHECKPOINT;
+      AttemptedInstructionCount = CHECKPOINT;
+      // manual checkpoint initializations
+      force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
+      force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
+      force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
+//      force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3]; // dh removed UPIE and UIE 4/25/22 from depricated n-mode
+      force {`STATUS_SPIE} = initMSTATUS[0][5];
+      force {`STATUS_MIE} = initMSTATUS[0][3];
+      force {`STATUS_SIE} = initMSTATUS[0][1];
+      force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
+      force `INSTRET = CHECKPOINT;
+      while (reset!==1) #1;
+      while (reset!==0) #1;
+      #1;
+      release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
+      release {`STATUS_FS,`STATUS_MPP};
+      release {`STATUS_SPP,`STATUS_MPIE};
+      release {`STATUS_SPIE,`STATUS_MIE};
+      release {`STATUS_SIE};
+      release `PLIC_INT_ENABLE;
+      release `INSTRET;
+    end
+    // Get the E-stage trace reader ahead of the M-stage trace reader
+    matchCountE = $fgets(lineE,traceFileE); // *** look at removing?
+  end
+
+  ///////////////////////////////////////////////////////////////////////////////
+  //////////////////////////////////// CORE /////////////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  // =========== TRACE PARSING MACRO ==========
+  // Because qemu does not match exactly to wally it is necessary to read the the
+  // trace in the memory stage and detect if anything in wally must be overwritten.
+  // This includes mtimer, interrupts, and various bits in mstatus and xtval.
+
+  // then on the next posedge the expected state is registered.
+  // on the next falling edge the expected state is compared to the wally state.
+
+  // step 0: read the expected state
+  `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
+    // always check PC, instruction bits \
+    if (checkInstrM) begin \
+      // read 1 line of the trace file \
+      matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \
+      if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \
+      // extract PC, Instr \
+      matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \
+      if (`"STAGE`"=="M") begin \
+        AttemptedInstructionCount += 1; \
+      end \
+ \
+      // for the life of me I cannot get any build in C or C++ string parsing functions/methods to work. \
+      // strtok was the best idea but it cannot be used correctly as system verilog does not have null \
+      // terminated strings. \
+ \
+      // Just going to do this char by char. \
+      StartIndex``STAGE = 0; \
+      TokenIndex``STAGE = 0; \
+      //$display("len = %d", line``STAGE.len()); \
+      for(index``STAGE = 0; index``STAGE < line``STAGE.len(); index``STAGE++) begin \
+        //$display("char = %s", line``STAGE[index]); \
+        if (line``STAGE[index``STAGE] == " " | line``STAGE[index``STAGE] == "\n") begin \
+          EndIndex``STAGE = index``STAGE; \
+          ExpectedTokens``STAGE[TokenIndex``STAGE] = line``STAGE.substr(StartIndex``STAGE, EndIndex``STAGE-1); \
+          //$display("In Tokenizer %s", line``STAGE.substr(StartIndex, EndIndex-1)); \
+          StartIndex``STAGE = EndIndex``STAGE + 1; \
+          TokenIndex``STAGE++; \
+        end \
+      end \
+ \
+      MarkerIndex``STAGE = 3; \
+      NumCSR``STAGE = 0; \
+      MemOp``STAGE = ""; \
+      RegWrite``STAGE = ""; \
+ \
+      #2; \
+ \
+      while(TokenIndex``STAGE > MarkerIndex``STAGE) begin \
+        // parse the GPR \
+        if (ExpectedTokens``STAGE[MarkerIndex``STAGE] == "GPR") begin \
+          RegWrite``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%d", ExpectedRegAdr``STAGE); \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedRegValue``STAGE); \
+          MarkerIndex``STAGE += 3; \
+        // parse memory address, read data, and/or write data \
+        end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
+          MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedIEUAdr``STAGE); \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
+          MarkerIndex``STAGE += 4; \
+        // parse CSRs, because there are 1 or more CSRs after the CSR token \
+        // we check if the CSR token or the number of CSRs is greater than 0. \
+        // if so then we want to parse for a CSR. \
+        end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR" | NumCSR``STAGE > 0) begin \
+          if(ExpectedTokens``STAGE[MarkerIndex``STAGE] == "CSR") begin \
+            // all additional CSR's won't have this token. \
+            MarkerIndex``STAGE++; \
+          end \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE], "%s", ExpectedCSRArray``STAGE[NumCSR``STAGE]); \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedCSRArrayValue``STAGE[NumCSR``STAGE]); \
+          MarkerIndex``STAGE += 2; \
+           \
+          NumCSR``STAGE++; \
+        end \
+      end \
+      if(`"STAGE`"=="M") begin \
+        // override on special conditions \
+        if ((dut.core.lsu.PAdrM == 'h10000002) | (dut.core.lsu.PAdrM == 'h10000005) | (dut.core.lsu.PAdrM == 'h10000006)) begin \
+          if(!NO_SPOOFING) begin \
+            $display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \
+            force dut.core.lsu.ReadDataM = ExpectedMemReadDataM; \
+          end \
+        end else \
+          if(!NO_SPOOFING) \
+            release dut.core.lsu.ReadDataM; \
+        if(textM.substr(0,5) == "rdtime") begin \
+          //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
+          if(!NO_SPOOFING) \
+            force dut.uncore.uncore.clint.clint.MTIME = ExpectedRegValueM; \
+        end \
+      end \
+    end \
+    
+  // ========== VALUE-CHECKING MACROS ==========
+  `define checkEQ(NAME, VAL, EXPECTED) \
+    if(VAL != EXPECTED) begin \
+      $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \
+      if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \
+    end
+
+  `define checkCSR(CSR) \
+    begin \
+      if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \
+        $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \
+        if(`DEBUG_TRACE >= 3) fault = 1; \
+      end \
+    end
+
+  // =========== CORE ===========
+  assign checkInstrM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM & ~dut.core.StallM;
+  always @(negedge clk) begin
+    `SCAN_NEW_INSTR_FROM_TRACE(E)
+    `SCAN_NEW_INSTR_FROM_TRACE(M)
+  end
+
+  // step 1: register expected state into the write back stage.
+  always @(posedge clk) begin
+    if (reset) begin
+      ExpectedPCW <= '0;
+      ExpectedInstrW <= '0;
+      textW <= "";
+      RegWriteW <= "";
+      ExpectedRegAdrW <= '0;
+      ExpectedRegValueW <= '0;
+      ExpectedIEUAdrW <= '0;
+      MemOpW <= "";
+      ExpectedMemWriteDataW <= '0;
+      ExpectedMemReadDataW <= '0;
+      NumCSRW <= '0;
+    end else if(~dut.core.StallW) begin
+      if(dut.core.FlushW) begin
+        ExpectedPCW <= '0;
+        ExpectedInstrW <= '0;
+        textW <= "";
+        RegWriteW <= "";
+        ExpectedRegAdrW <= '0;
+        ExpectedRegValueW <= '0;
+        ExpectedIEUAdrW <= '0;
+        MemOpW <= "";
+        ExpectedMemWriteDataW <= '0;
+        ExpectedMemReadDataW <= '0;
+        NumCSRW <= '0;
+      end else if (dut.core.ieu.c.InstrValidM) begin 
+        ExpectedPCW <= ExpectedPCM;
+        ExpectedInstrW <= ExpectedInstrM;
+        textW <= textM;
+        RegWriteW <= RegWriteM;
+        ExpectedRegAdrW <= ExpectedRegAdrM;
+        ExpectedRegValueW <= ExpectedRegValueM;
+        ExpectedIEUAdrW <= ExpectedIEUAdrM;
+        MemOpW <= MemOpM;
+        ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
+        ExpectedMemReadDataW <= ExpectedMemReadDataM;
+        NumCSRW <= NumCSRM;
+        for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin
+          ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
+          ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
+        end
+      end
+      #1;
+      // override on special conditions
+      if(~dut.core.StallW) begin
+        if(textW.substr(0,5) == "rdtime") begin
+          //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
+          if(!NO_SPOOFING)
+            release dut.uncore.uncore.clint.clint.MTIME;
+        end 
+        //if (ExpectedIEUAdrM == 'h10000005) begin
+          //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, AttemptedInstructionCount);
+          //release dut.core.ieu.dp.ReadDataM;
+        //end
+      end
+    end
+  end
+  
+  // step2: make all checks in the write back stage.
+  assign checkInstrW = InstrValidW & ~dut.core.StallW; // trapW will already be invalid in there was an InstrPageFault in the previous instruction.
+  always @(negedge clk) begin
+    #1; // small delay allows interrupt spoofing to happen first
+    // always check PC, instruction bits
+    if (checkInstrW) begin
+      InstrCountW += 1;
+      // print progress message
+      if (AttemptedInstructionCount % 'd100000 == 0) $display("Reached %d instructions", AttemptedInstructionCount);
+      // turn on waves
+      if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
+      // end sim
+      if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
+      fault = 0;
+      if (`DEBUG_TRACE >= 1) begin
+        `checkEQ("PCW",PCW,ExpectedPCW)
+        //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
+        // compressed to uncompressed conversion
+        `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
+        #2; // delay 2 ns.
+        if(`DEBUG_TRACE >= 5) begin
+          $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
+          $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
+        end
+        if (RegWriteW == "GPR") begin
+          `checkEQ("Reg Write Address",dut.core.ieu.dp.regf.a3,ExpectedRegAdrW)
+          $sformat(name,"RF[%02d]",ExpectedRegAdrW);
+          `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
+        end
+        if (MemOpW.substr(0,2) == "Mem") begin
+          if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
+          `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
+          if(MemOpW == "MemR" | MemOpW == "MemRW") begin
+            if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW);
+            `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW)
+          end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin
+            if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
+            `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW)
+          end
+        end
+        // check csr
+        for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
+          case(ExpectedCSRArrayW[NumCSRPostWIndex])
+            "mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW)
+            "mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW)
+            "sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW)
+            "mtvec":   `checkCSR(`CSR_BASE.csrm.MTVEC_REGW)
+            "mie":     `checkCSR(`CSR_BASE.csrm.MIE_REGW)
+            "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW)
+            "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
+            "mepc":    `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
+            "mtval":   `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
+            "sepc":    `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
+            "scause":  `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
+            "stvec":   `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
+            "stval":   `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
+            "mip": begin
+                       `checkCSR(`CSR_BASE.csrm.MIP_REGW)
+                       if(!NO_SPOOFING) begin
+                         if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0)
+                           force `MEIP = 0;
+                         if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0)
+                           force `SEIP = 0;
+                         if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & ((1<<11) | (1<<09))) == 0)
+                           force `UART_IP = 0;
+                         if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<07) == 0)
+                           force `MTIP = 0;
+                       end
+                   end
+          endcase
+        end
+        if (fault == 1) begin
+          errorCount +=1;
+          $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
+          $stop; $stop;
+        end
+      end // if (`DEBUG_TRACE >= 1)
+    end // if (checkInstrW)
+  end // always @ (negedge clk)
+
+
+  // New IP spoofing
+  logic globalIntsBecomeEnabled;
+  assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22));
+  logic checkInterruptM;
+  assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM;
+  
+  always @(negedge clk) begin
+    if(checkInterruptM) begin
+      if((interruptInstrCount+1) == AttemptedInstructionCount) begin
+        if(!NO_SPOOFING) begin
+          case (interruptCauseVal)
+            11: begin
+                  force `MEIP = 1;
+                  force `UART_IP = 1;
+                end
+            09: begin 
+                  force `SEIP = 1;
+                  force `UART_IP = 1;
+                end
+            07: force `MTIP = 1;
+            default: $display("Unsupported interrupt in interrupts.txt. cause = %0d",interruptCauseVal);
+          endcase
+          $display("Forcing interrupt.");
+        end
+        `SCAN_NEW_INTERRUPT
+        if (globalIntsBecomeEnabled) begin
+            $display("Enabled global interrupts");
+            // The idea here is if a CSR instruction causes an interrupt by
+            // enabling interrupts, that CSR instruction will commit.
+        end else begin
+            // Other instructions, however, will get interrupted and not
+            // commit, so we don't want our W-stage checker to look for them
+            // and get confused when it doesn't find them.
+            garbageInt = $fgets(garbageString,traceFileE);
+            garbageInt = $fgets(garbageString,traceFileM);
+            AttemptedInstructionCount += 1;
+        end
+      end
+    end
+  end
+
+
+
+
+
+
+
+
+
+
+  ///////////////////////////////////////////////////////////////////////////////
+  //////////////////////////////// Extra Features ///////////////////////////////
+  ///////////////////////////////////////////////////////////////////////////////
+  // Function Tracking
+  FunctionName FunctionName(.reset(reset),
+                            .clk(clk),
+                            .ProgramAddrMapFile(ProgramAddrMapFile),
+                            .ProgramLabelMapFile(ProgramLabelMapFile));
+  
+  // Instr Opcode Tracking
+  //   For waveview convenience
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.InstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // ------------------
+  // Address Translator
+  // ------------------
+   /**
+   * Walk the page table stored in ram according to sv39 logic and translate a
+   * virtual address to a physical address.
+   *
+   * See section 4.3.2 of the RISC-V Privileged specification for a full
+   * explanation of the below algorithm.
+   */
+  logic             SvMode, PTE_R, PTE_X;
+  logic [`XLEN-1:0] SATP, PTE;
+  logic [55:0]      BaseAdr, PAdr;
+  logic [8:0]       VPN [2:0];
+  logic [11:0]      Offset;
+  function logic [`XLEN-1:0] adrTranslator( 
+    input logic [`XLEN-1:0] adrIn);
+    begin
+      int i;
+      // Grab the SATP register from privileged unit
+      SATP = dut.core.priv.priv.csr.SATP_REGW;
+      // Split the virtual address into page number segments and offset
+      VPN[2] = adrIn[38:30];
+      VPN[1] = adrIn[29:21];
+      VPN[0] = adrIn[20:12];
+      Offset = adrIn[11:0];
+      // We do not support sv48; only sv39
+      SvMode = SATP[63];
+      // Only perform translation if translation is on and the processor is not
+      // in machine mode
+      if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin
+        BaseAdr = SATP[43:0] << 12;
+        for (i = 2; i >= 0; i--) begin
+          PAdr = BaseAdr + (VPN[i] << 3);
+          // ram.memory.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
+          // by 3 (the PTE size) to get the requested 64-bit PTE.
+          PTE = dut.uncore.uncore.ram.ram.memory.RAM[PAdr >> 3];
+          PTE_R = PTE[1];
+          PTE_X = PTE[3];
+          if (PTE_R | PTE_X) begin
+            // Leaf page found
+            break;
+          end else begin
+            // Go to next level of table
+            BaseAdr = PTE[53:10] << 12;
+          end
+        end
+        // Determine which parts of the PTE page number to use based on the
+        // level of the page table we reached.
+        if (i == 2) begin
+          // Gigapage
+          assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset};
+        end else if (i == 1) begin
+          // Megapage
+          assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset};
+        end else begin
+          // Kilopage
+          assign adrTranslator = {8'b0, PTE[53:10], Offset};
+        end
+      end else begin
+        // Direct translation if address translation is not on
+        assign adrTranslator = adrIn;
+      end
+    end
+  endfunction
+endmodule
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
new file mode 100644
index 000000000..5456ce8b9
--- /dev/null
+++ b/pipelined/testbench/testbench.sv
@@ -0,0 +1,697 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+`include "tests.vh"
+
+`define PrintHPMCounters 0
+`define BPRED_LOGGER 0
+
+module testbench;
+  parameter DEBUG=0;
+  parameter TEST="none";
+ 
+  logic        clk;
+  logic        reset_ext, reset;
+
+  parameter SIGNATURESIZE = 5000000;
+
+  int test, i, errors, totalerrors;
+  logic [31:0] sig32[0:SIGNATURESIZE];
+  logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
+  logic [`XLEN-1:0] testadr, testadrNoBase;
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+
+string tests[];
+logic [3:0] dummy;
+
+  logic [`AHBW-1:0] HRDATAEXT;
+  logic             HREADYEXT, HRESPEXT;
+  logic [`PA_BITS-1:0] HADDR;
+  logic [`AHBW-1:0] HWDATA;
+  logic [`XLEN/8-1:0] HWSTRB;
+  logic             HWRITE;
+  logic [2:0]       HSIZE;
+  logic [2:0]       HBURST;
+  logic [3:0]       HPROT;
+  logic [1:0]       HTRANS;
+  logic             HMASTLOCK;
+  logic             HCLK, HRESETn;
+  logic [`XLEN-1:0] PCW;
+
+  string ProgramAddrMapFile, ProgramLabelMapFile;
+  integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
+
+  logic 	    DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
+    
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+
+  // check assertions for a legal configuration
+  riscvassertions riscvassertions();
+
+  // pick tests based on modes supported
+  initial begin
+    $display("TEST is %s", TEST);
+    //tests = '{};
+    if (`XLEN == 64) begin // RV64
+      case (TEST)
+        "arch64i":                        tests = arch64i;
+        "arch64priv":                     tests = arch64priv;
+        "arch64c":      if (`C_SUPPORTED) 
+                          if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
+                          else                  tests = {arch64c};
+        "arch64m":      if (`M_SUPPORTED) tests = arch64m;
+        "arch64f":      if (`F_SUPPORTED) tests = arch64f;
+        "arch64d":      if (`D_SUPPORTED) tests = arch64d;  
+        "arch64zi":     if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "imperas64i":                     tests = imperas64i;
+        "imperas64f":   if (`F_SUPPORTED) tests = imperas64f;
+        "imperas64d":   if (`D_SUPPORTED) tests = imperas64d;
+        "imperas64m":   if (`M_SUPPORTED) tests = imperas64m;
+        "wally64a":     if (`A_SUPPORTED) tests = wally64a;
+        "imperas64c":   if (`C_SUPPORTED) tests = imperas64c;
+                        else              tests = imperas64iNOc;
+        "custom":                         tests = custom;
+        "wally64i":                       tests = wally64i; 
+        "wally64priv":                    tests = wally64priv;
+        "wally64periph":                  tests = wally64periph;
+        "coremark":                       tests = coremark;
+        "fpga":                           tests = fpga;
+        "ahb" :                           tests = ahb;
+      endcase 
+    end else begin // RV32
+      case (TEST)
+        "arch32i":                        tests = arch32i;
+        "arch32priv":                     tests = arch32priv;
+        "arch32c":      if (`C_SUPPORTED) 
+                          if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
+                          else                  tests = {arch32c};
+        "arch32m":      if (`M_SUPPORTED) tests = arch32m;
+        "arch32f":      if (`F_SUPPORTED) tests = arch32f;
+        "arch32d":      if (`D_SUPPORTED) tests = arch32d;
+        "arch32zi":     if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "imperas32i":                     tests = imperas32i;
+        "imperas32f":   if (`F_SUPPORTED) tests = imperas32f;
+        "imperas32m":   if (`M_SUPPORTED) tests = imperas32m;
+        "wally32a":     if (`A_SUPPORTED) tests = wally32a;
+        "imperas32c":   if (`C_SUPPORTED) tests = imperas32c;
+                        else              tests = imperas32iNOc;
+        "wally32i":                       tests = wally32i; 
+        "wally32e":                       tests = wally32e; 
+        "wally32priv":                    tests = wally32priv;
+        "wally32periph":                   tests = wally32periph;
+        "embench":                        tests = embench;
+        "coremark":                       tests = coremark;
+        "arch32ba":     if (`ZBA_SUPPORTED) tests = arch32ba;
+      endcase
+    end
+    if (tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end
+
+  string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
+  integer outputFilePointer;
+
+  logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1 [3:0]   SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+  
+  logic             InitializingMemories;
+  integer           ResetCount, ResetThreshold;
+  logic             InReset;
+
+  // instantiate device to be tested
+  assign GPIOPinsIn = 0;
+  assign UARTSin = 1;
+
+  if(`EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
+         .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
+         .HWSTRB);
+  end else begin 
+    assign HREADYEXT = 1;
+    assign HRESPEXT = 0;
+    assign HRDATAEXT = 0;
+  end
+
+  if(`FPGA) begin : sdcard
+    sdModel sdcard
+      (.sdClk(SDCCLK),
+       .cmd(SDCCmd), 
+       .dat(SDCDat));
+
+    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
+    assign SDCCmdIn = SDCCmd;
+    assign SDCDatIn = SDCDat;
+  end else begin
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+  end
+
+  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // Track names of instructions
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.InstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // initialize tests
+  localparam integer 	   MemStartAddr = 0;
+  localparam integer 	   MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
+
+  initial
+    begin
+      ResetCount = 0;
+      ResetThreshold = 2;
+      InReset = 1;
+      test = 1;
+      totalerrors = 0;
+      testadr = 0;
+      testadrNoBase = 0;
+      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and  tests[0] == "2" refers to WallyRiscvArchTests 
+      riscofTest = tests[0] == "1" | tests[0] == "2"; 
+      // fill memory with defined values to reduce Xs in simulation
+      // Quick note the memory will need to be initialized.  The C library does not
+      //  guarantee the  initialized reads.  For example a strcmp can read 6 byte
+      //  strings, but uses a load double to read them in.  If the last 2 bytes are
+      //  not initialized the compare results in an 'x' which propagates through 
+      // the design.
+      if (TEST == "coremark") 
+        for (i=MemStartAddr; i<MemEndAddr; i = i+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0; 
+
+      // read test vectors into memory
+      pathname = tvpaths[tests[0].atoi()];
+      /* if (tests[0] == `IMPERASTEST)
+        pathname = tvpaths[0];
+       else pathname = tvpaths[1]; */
+      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else memfilename = {pathname, tests[test], ".elf.memfile"};
+      if (`FPGA) begin
+        string romfilename, sdcfilename;
+        romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        // force sdc timers
+        force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      end else begin
+        if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+        else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+        if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      end
+
+      if (riscofTest) begin
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else begin
+        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+      end
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
+      // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
+      if(!`FPGA) begin
+        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+        $display("Read memfile %s", memfilename);
+      end
+    end
+
+  // generate clock to sequence tests
+  always
+    begin
+      clk = 1; # 5; clk = 0; # 5;
+      // if ($time % 100000 == 0) $display("Time is %0t", $time);
+    end
+   
+  logic [`XLEN-1:0] debugmemoryadr;
+//  assign debugmemoryadr = dut.uncore.uncore.ram.ram.memory.RAM[5140];
+
+  // check results
+  assign reset_ext = InReset;
+  
+  always @(negedge clk)
+    begin    
+      InitializingMemories = 0;
+      if(InReset == 1) begin
+        // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
+        if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
+        else begin // hit reset threshold so we remove reset.
+          InReset = 0;
+          ResetCount = 0;
+        end
+      end else begin
+      if (TEST == "coremark")
+        if (dut.core.priv.priv.EcallFaultM) begin
+          $display("Benchmark: coremark is done.");
+          $stop;
+        end
+      // Termination condition (i.e. we finished running current test) 
+      if (DCacheFlushDone) begin
+        integer begin_signature_addr;
+        InReset = 1;
+        begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+        if (!begin_signature_addr)
+          $display("begin_signature addr not found in %s", ProgramLabelMapFile);
+        testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
+        testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
+        #600; // give time for instructions in pipeline to finish
+        if (TEST == "embench") begin
+          // Writes contents of begin_signature to .sim.output file
+          // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
+          // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
+          $display("Embench Benchmark: %s is done.", tests[test]);
+          if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+          else outputfile = {pathname, tests[test], ".sim.output"};
+          outputFilePointer = $fopen(outputfile);
+          i = 0;
+          while ($unsigned(i) < $unsigned(5'd5)) begin
+            $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+            i = i + 1;
+          end
+          $fclose(outputFilePointer);
+          $display("Embench Benchmark: created output file: %s", outputfile);
+        end else begin 
+          // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+          // clear signature to prevent contamination from previous tests
+          for(i=0; i<SIGNATURESIZE; i=i+1) begin
+            sig32[i] = 'bx;
+          end
+          if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
+          else signame = {pathname, tests[test], ".signature.output"};
+          // read signature, reformat in 64 bits if necessary
+          $readmemh(signame, sig32);
+          i = 0;
+          while (i < SIGNATURESIZE) begin
+            if (`XLEN == 32) begin
+              signature[i] = sig32[i];
+              i = i+1;
+            end else begin
+              signature[i/2] = {sig32[i+1], sig32[i]};
+              i = i + 2;
+            end
+            if (i >= 4 & sig32[i-4] === 'bx) begin
+              if (i == 4) begin
+                i = SIGNATURESIZE+1; // flag empty file
+                $display("  Error: empty test file");
+              end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
+            end
+          end
+
+          // Check errors
+          errors = (i == SIGNATURESIZE+1); // error if file is empty
+          i = 0;
+          /* verilator lint_off INFINITELOOP */
+          while (signature[i] !== 'bx) begin
+            logic [`XLEN-1:0] sig;
+            if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+            else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+            //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+            if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
+              errors = errors+1;
+              $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+              $stop;//***debug
+             end
+            i = i + 1;
+          end
+          /* verilator lint_on INFINITELOOP */
+          if (errors == 0) begin
+            $display("%s succeeded.  Brilliant!!!", tests[test]);
+          end
+          else begin
+            $display("%s failed with %d errors. :(", tests[test], errors);
+            totalerrors = totalerrors+1;
+          end
+        end
+        // move onto the next test, check to see if we're done
+        test = test + 1;
+        if (test == tests.size()) begin
+          if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+          else $display("FAIL: %d test programs had errors", totalerrors);
+          $stop;
+        end
+        else begin
+            InitializingMemories = 1;
+            // If there are still additional tests to run, read in information for the next test
+            //pathname = tvpaths[tests[0]];
+            if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+            else memfilename = {pathname, tests[test], ".elf.memfile"};
+            //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+            if (`IROM_SUPPORTED)               $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+            else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+            if (`DTIM_SUPPORTED)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+
+            if (riscofTest) begin
+              ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+              ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+            end else begin
+              ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+              ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+            end
+            ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
+          if(!`FPGA) begin
+            updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+            $display("Read memfile %s", memfilename);
+          end
+        end
+      end // if (DCacheFlushDone)
+      end
+    end // always @ (negedge clk)
+
+
+  if(`PrintHPMCounters) begin
+    integer HPMCindex;
+    string  HPMCnames[] = '{"Mcycle",
+                            "------",
+                            "InstRet",
+                            "Load Stall",
+                            "Br Dir Wrong",
+                            "Br Count",
+                            "Br Target Wrong",
+                            "Jump, JR, Jal",
+                            "RAS Wrong",
+                            "ret",
+                            "Instr Class Wrong",
+                            "D Cache Access",
+                            "D Cache Miss",
+                            "I Cache Access",
+                            "I Cache Miss"};
+    always @(negedge clk) begin
+      if(DCacheFlushStart & ~DCacheFlushDone) begin
+        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
+          // unlikely to have more than 10M in any counter.
+          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex], HPMCnames[HPMCindex]);
+        end
+      end
+    end
+  end
+
+  // track the current function or global label
+  if (DEBUG == 1) begin : FunctionName
+    FunctionName FunctionName(.reset(reset),
+			      .clk(clk),
+			      .ProgramAddrMapFile(ProgramAddrMapFile),
+			      .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
+
+  // Termination condition
+  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
+  // or sw	gp,-56(t0) for new Imperas tests
+  // or sd gp, -56(t0) 
+  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
+  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
+  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  else                  assign ecf = 0;
+  assign DCacheFlushStart = ecf & 
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+           ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
+           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
+
+  DCacheFlushFSM DCacheFlushFSM(.clk(clk),
+    			.reset(reset),
+	    		.start(DCacheFlushStart),
+		    	.done(DCacheFlushDone));
+
+  // initialize the branch predictor
+  if (`BPRED_ENABLED == 1)
+    begin
+      genvar adrindex;
+      
+      // Initializing all zeroes into the branch predictor memory.
+      for(adrindex = 0; adrindex < 1024; adrindex++) begin
+        initial begin 
+        force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+        force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        #1;
+        release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+        release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+        end
+      end
+
+      if (`BPRED_LOGGER) begin
+        string direction;
+        int    file;
+        initial
+          file = $fopen("branch.log", "w");
+        always @(posedge clk) begin
+           if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+             direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n";
+             $fwrite(file, "%h %s\n", dut.core.PCM, direction);
+           end
+        end
+      end
+    end
+
+  // check for hange up.
+  logic [`XLEN-1:0] OldPCW;
+  integer 			WatchDogTimerCount;
+  localparam WatchDogTimerThreshold = 1000000;
+  logic 			WatchDogTimeOut;
+  always_ff @(posedge clk) begin
+	OldPCW <= PCW;
+	if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
+	else WatchDogTimerCount = '0;
+  end
+
+  always_comb begin
+	WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
+	if(WatchDogTimeOut) begin
+	  $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
+	  $stop;
+	end
+  end
+  
+endmodule
+
+module riscvassertions;
+  initial begin
+    assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
+    assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
+    assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
+    assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
+    assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
+    assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
+    assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
+    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
+    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
+    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
+	  assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
+    assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+    assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
+    assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
+    assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
+    assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
+  end
+
+  // *** DH 8/23/
+endmodule
+
+
+/* verilator lint_on STMTDLY */
+/* verilator lint_on WIDTH */
+
+module DCacheFlushFSM
+  (input logic clk,
+   input logic reset,
+   input logic start,
+   output logic done);
+
+  genvar adr;
+
+  logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
+  
+	if(`DCACHE) begin
+	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+	  localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+	  localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+      
+//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
+	  localparam integer numwords = sramlen/`XLEN;
+      localparam integer lognumlines = $clog2(numlines);
+	  localparam integer loglinebytelen = $clog2(linebytelen);
+	  localparam integer lognumways = $clog2(numways);
+	  localparam integer tagstart = lognumlines + loglinebytelen;
+
+
+
+	  genvar 			 index, way, cacheWord;
+	  logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+      logic [sramlen-1:0] cacheline;
+	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    for(index = 0; index < numlines; index++) begin
+		  for(way = 0; way < numways; way++) begin
+		    for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
+			    copyShadow #(.tagstart(tagstart),
+					.loglinebytelen(loglinebytelen), .sramlen(sramlen))
+			    copyShadow(.clk,
+          .start,
+          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
+          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
+          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
+                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
+          .index(index),
+          .cacheWord(cacheWord),
+          .CacheData(CacheData[way][index][cacheWord]),
+          .CacheAdr(CacheAdr[way][index][cacheWord]),
+          .CacheTag(CacheTag[way][index][cacheWord]),
+          .CacheValid(CacheValid[way][index][cacheWord]),
+          .CacheDirty(CacheDirty[way][index][cacheWord]));
+        end
+      end
+    end
+
+    integer i, j, k, l;
+
+    always @(posedge clk) begin
+      if (start) begin #1
+        #1
+        for(i = 0; i < numlines; i++) begin
+          for(j = 0; j < numways; j++) begin
+            for(l = 0; l < cachesramwords; l++) begin
+              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
+                for(k = 0; k < numwords; k++) begin
+                  //cacheline = CacheData[j][i][0];
+                  // does not work with modelsim
+                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
+                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
+                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
+                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
+                end
+              end
+            end
+          end
+        end
+      end
+    end  
+  end
+  flop #(1) doneReg(.clk, .d(start), .q(done));
+endmodule
+
+module copyShadow
+  #(parameter tagstart, loglinebytelen, sramlen)
+  (input logic clk,
+   input logic 			     start,
+   input logic [`PA_BITS-1:tagstart] tag,
+   input logic 			     valid, dirty,
+   input logic [sramlen-1:0] 	     data,
+   input logic [32-1:0] 	     index,
+   input logic [32-1:0] 	     cacheWord,
+   output logic [sramlen-1:0] 	     CacheData,
+   output logic [`PA_BITS-1:0] 	     CacheAdr,
+   output logic [`XLEN-1:0] 	     CacheTag,
+   output logic 		     CacheValid,
+   output logic 		     CacheDirty);
+  
+
+  always_ff @(posedge clk) begin
+    if(start) begin
+      CacheTag = tag;
+      CacheValid = valid;
+      CacheDirty = dirty;
+      CacheData = data;
+      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
+    end
+  end
+  
+endmodule
+
+task automatic updateProgramAddrLabelArray;
+  input string ProgramAddrMapFile, ProgramLabelMapFile;
+  inout  integer ProgramAddrLabelArray [string];
+  // Gets the memory location of begin_signature
+  integer ProgramLabelMapFP, ProgramAddrMapFP;
+  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
+  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
+  
+  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    while (!$feof(ProgramLabelMapFP)) begin
+      string label, adrstr;
+      integer returncode;
+      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
+      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
+      if (ProgramAddrLabelArray.exists(label)) 
+        ProgramAddrLabelArray[label] = adrstr.atohex();
+    end
+  end
+  $fclose(ProgramLabelMapFP);
+  $fclose(ProgramAddrMapFP);
+endtask
+
diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv
new file mode 100644
index 000000000..6e84e879b
--- /dev/null
+++ b/pipelined/testbench/testbench_imperas.sv
@@ -0,0 +1,439 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+
+module testbench;
+  parameter DEBUG=0;
+ 
+  logic        clk;
+  logic        reset_ext, reset;
+
+
+  logic [`XLEN-1:0] testadr, testadrNoBase;
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+
+  logic [3:0]  dummy;
+
+  logic [`AHBW-1:0] HRDATAEXT;
+  logic             HREADYEXT, HRESPEXT;
+  logic [`PA_BITS-1:0] HADDR;
+  logic [`AHBW-1:0] HWDATA;
+  logic [`XLEN/8-1:0] HWSTRB;
+  logic             HWRITE;
+  logic [2:0]       HSIZE;
+  logic [2:0]       HBURST;
+  logic [3:0]       HPROT;
+  logic [1:0]       HTRANS;
+  logic             HMASTLOCK;
+  logic             HCLK, HRESETn;
+  logic [`XLEN-1:0] PCW;
+
+  string ProgramAddrMapFile, ProgramLabelMapFile;
+  integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
+  logic 	    DCacheFlushDone, DCacheFlushStart;
+  string 		testName;
+  string memfilename, pathname, adrstr;
+
+  logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1 [3:0]   SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+  
+  logic             InitializingMemories;
+  integer           ResetCount, ResetThreshold;
+  logic             InReset;
+
+  // Imperas look here.
+  initial
+    begin
+      ResetCount = 0;
+      ResetThreshold = 2;
+      InReset = 1;
+      testadr = 0;
+      testadrNoBase = 0;
+
+	  //testName =     "rv64i_m/I/src/add-01.S";
+	  testName =     "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S";
+	  
+
+	  //pathname =     "../../tests/riscof/work/riscv-arch-test/";
+	  pathname = "../../tests/riscof/work/wally-riscv-arch-test/";
+	  
+	  memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
+      if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+	  else $error("Imperas test bench requires BUS.");
+
+      ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
+      ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
+
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
+      // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
+      updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+      $display("Read memfile %s", memfilename);
+    end
+
+  rvviTrace rvviTrace();
+
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+
+  // check assertions for a legal configuration
+  riscvassertions riscvassertions();
+
+
+  // instantiate device to be tested
+  assign GPIOPinsIn = 0;
+  assign UARTSin = 1;
+
+  if(`EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
+         .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
+         .HWSTRB);
+  end else begin 
+    assign HREADYEXT = 1;
+    assign HRESPEXT = 0;
+    assign HRDATAEXT = 0;
+  end
+
+  if(`FPGA) begin : sdcard
+    sdModel sdcard
+      (.sdClk(SDCCLK),
+       .cmd(SDCCmd), 
+       .dat(SDCDat));
+
+    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
+    assign SDCCmdIn = SDCCmd;
+    assign SDCDatIn = SDCDat;
+  end else begin
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+  end
+
+  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // Track names of instructions
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // initialize tests
+
+  // generate clock to sequence tests
+  always
+    begin
+      clk = 1; # 5; clk = 0; # 5;
+      // if ($time % 100000 == 0) $display("Time is %0t", $time);
+    end
+   
+  // check results
+  assign reset_ext = InReset;
+  
+  always @(negedge clk)
+    begin    
+      InitializingMemories = 0;
+      if(InReset == 1) begin
+        // once the test inidicates it's done we need to immediately hold reset for a number of cycles.
+        if(ResetCount < ResetThreshold) ResetCount = ResetCount + 1;
+        else begin // hit reset threshold so we remove reset.
+          InReset = 0;
+          ResetCount = 0;
+        end
+      end
+    end // always @ (negedge clk)
+
+
+  // track the current function or global label
+  if (DEBUG == 1) begin : FunctionName
+    FunctionName FunctionName(.reset(reset),
+			      .clk(clk),
+			      .ProgramAddrMapFile(ProgramAddrMapFile),
+			      .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
+
+  // Termination condition
+  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
+  // or sw	gp,-56(t0) for new Imperas tests
+  // or sd gp, -56(t0) 
+  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
+  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
+  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  else                  assign ecf = 0;
+  assign DCacheFlushStart = ecf & 
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+           ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
+           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
+
+  DCacheFlushFSM DCacheFlushFSM(.clk(clk),
+    			.reset(reset),
+	    		.start(DCacheFlushStart),
+		    	.done(DCacheFlushDone));
+
+  // initialize the branch predictor
+  if (`BPRED_ENABLED == 1)
+    begin
+      genvar adrindex;
+      
+      // Initializing all zeroes into the branch predictor memory.
+      for(adrindex = 0; adrindex < 1024; adrindex++) begin
+        initial begin 
+        force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+        force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        #1;
+        release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+        release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+        end
+      end
+    end
+
+  // check for hange up.
+  logic [`XLEN-1:0] OldPCW;
+  integer 			WatchDogTimerCount;
+  localparam WatchDogTimerThreshold = 1000000;
+  logic 			WatchDogTimeOut;
+  always_ff @(posedge clk) begin
+	OldPCW <= PCW;
+	if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
+	else WatchDogTimerCount = '0;
+  end
+
+  always_comb begin
+	WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
+	if(WatchDogTimeOut) begin
+	  $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
+	  $stop;
+	end
+  end
+
+  
+endmodule
+
+module riscvassertions;
+  initial begin
+    assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
+    assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
+    assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
+    assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
+    assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
+    assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
+    assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
+    assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
+    assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
+    assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
+    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
+	  assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
+    assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+    assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
+    assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
+    assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
+    assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
+    assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
+  end
+
+  // *** DH 8/23/
+endmodule
+
+
+/* verilator lint_on STMTDLY */
+/* verilator lint_on WIDTH */
+
+module DCacheFlushFSM
+  (input logic clk,
+   input logic reset,
+   input logic start,
+   output logic done);
+
+  genvar adr;
+
+  logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
+  
+	if(`DCACHE) begin
+	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+	  localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+	  localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+      
+//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
+	  localparam integer numwords = sramlen/`XLEN;
+      localparam integer lognumlines = $clog2(numlines);
+	  localparam integer loglinebytelen = $clog2(linebytelen);
+	  localparam integer lognumways = $clog2(numways);
+	  localparam integer tagstart = lognumlines + loglinebytelen;
+
+
+
+	  genvar 			 index, way, cacheWord;
+	  logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+      logic [sramlen-1:0] cacheline;
+	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    for(index = 0; index < numlines; index++) begin
+		  for(way = 0; way < numways; way++) begin
+		    for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
+			    copyShadow #(.tagstart(tagstart),
+					.loglinebytelen(loglinebytelen), .sramlen(sramlen))
+			    copyShadow(.clk,
+          .start,
+          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
+          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
+          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
+                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
+          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
+          .index(index),
+          .cacheWord(cacheWord),
+          .CacheData(CacheData[way][index][cacheWord]),
+          .CacheAdr(CacheAdr[way][index][cacheWord]),
+          .CacheTag(CacheTag[way][index][cacheWord]),
+          .CacheValid(CacheValid[way][index][cacheWord]),
+          .CacheDirty(CacheDirty[way][index][cacheWord]));
+        end
+      end
+    end
+
+    integer i, j, k, l;
+
+    always @(posedge clk) begin
+      if (start) begin #1
+        #1
+        for(i = 0; i < numlines; i++) begin
+          for(j = 0; j < numways; j++) begin
+            for(l = 0; l < cachesramwords; l++) begin
+              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
+                for(k = 0; k < numwords; k++) begin
+                  //cacheline = CacheData[j][i][0];
+                  // does not work with modelsim
+                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
+                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
+                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
+                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
+                end
+              end
+            end
+          end
+        end
+      end
+    end  
+  end
+  flop #(1) doneReg(.clk, .d(start), .q(done));
+endmodule
+
+module copyShadow
+  #(parameter tagstart, loglinebytelen, sramlen)
+  (input logic clk,
+   input logic 			     start,
+   input logic [`PA_BITS-1:tagstart] tag,
+   input logic 			     valid, dirty,
+   input logic [sramlen-1:0] 	     data,
+   input logic [32-1:0] 	     index,
+   input logic [32-1:0] 	     cacheWord,
+   output logic [sramlen-1:0] 	     CacheData,
+   output logic [`PA_BITS-1:0] 	     CacheAdr,
+   output logic [`XLEN-1:0] 	     CacheTag,
+   output logic 		     CacheValid,
+   output logic 		     CacheDirty);
+  
+
+  always_ff @(posedge clk) begin
+    if(start) begin
+      CacheTag = tag;
+      CacheValid = valid;
+      CacheDirty = dirty;
+      CacheData = data;
+      CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
+    end
+  end
+  
+endmodule
+
+task automatic updateProgramAddrLabelArray;
+  input string ProgramAddrMapFile, ProgramLabelMapFile;
+  inout  integer ProgramAddrLabelArray [string];
+  // Gets the memory location of begin_signature
+  integer ProgramLabelMapFP, ProgramAddrMapFP;
+  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
+  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
+  
+  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    while (!$feof(ProgramLabelMapFP)) begin
+      string label, adrstr;
+      integer returncode;
+      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
+      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
+      if (ProgramAddrLabelArray.exists(label)) 
+        ProgramAddrLabelArray[label] = adrstr.atohex();
+    end
+  end
+  $fclose(ProgramLabelMapFP);
+  $fclose(ProgramAddrMapFP);
+endtask
+
diff --git a/testbench/tests_fp.vh b/pipelined/testbench/tests-fp.vh
similarity index 85%
rename from testbench/tests_fp.vh
rename to pipelined/testbench/tests-fp.vh
index 4c0e9cda5..ff5cf2fb8 100644
--- a/testbench/tests_fp.vh
+++ b/pipelined/testbench/tests-fp.vh
@@ -1,39 +1,13 @@
-///////////////////////////////////////////
-// tests_fp.vh
-//
-// Written: Katherine Parry 2022
-// Modified: 
-//
-// Purpose: List of floating-point tests to apply
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-3 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
 `define PATH "../../tests/fp/vectors/"
-`define ADD_OPCTRL     3'b110
-`define MUL_OPCTRL     3'b100
-`define SUB_OPCTRL     3'b111
-`define FMA_OPCTRL     3'b000
-`define DIV_OPCTRL     3'b000
-`define SQRT_OPCTRL    3'b001
-`define LE_OPCTRL      3'b011
-`define LT_OPCTRL      3'b001
-`define EQ_OPCTRL      3'b010
+`define ADD_OPCTRL 3'b110
+`define MUL_OPCTRL 3'b100
+`define SUB_OPCTRL 3'b111
+`define FMA_OPCTRL 3'b000
+`define DIV_OPCTRL 3'b000
+`define SQRT_OPCTRL 3'b001
+`define LE_OPCTRL 3'b011
+`define LT_OPCTRL 3'b001
+`define EQ_OPCTRL 3'b010
 `define TO_UI_OPCTRL   3'b000
 `define TO_I_OPCTRL    3'b001
 `define TO_UL_OPCTRL   3'b010
@@ -42,16 +16,16 @@
 `define FROM_I_OPCTRL  3'b101
 `define FROM_UL_OPCTRL 3'b110
 `define FROM_L_OPCTRL  3'b111
-`define RNE            3'b000
-`define RZ             3'b001
-`define RU             3'b011
-`define RD             3'b010
-`define RNM            3'b100
-`define FMAUNIT        2
-`define DIVUNIT        1
-`define CVTINTUNIT     0
-`define CVTFPUNIT      4
-`define CMPUNIT        3
+`define RNE 3'b000
+`define RZ  3'b001
+`define RU  3'b011
+`define RD  3'b010
+`define RNM 3'b100
+`define FMAUNIT 2
+`define DIVUNIT 1
+`define CVTINTUNIT 0
+`define CVTFPUNIT 4
+`define CMPUNIT 3
 
 string f16rv32cvtint[] = '{
 	"ui32_to_f16_rne.tv",
@@ -238,6 +212,7 @@ string f128rv32cvtint[] = '{
 	"f128_to_i32_rnm.tv"
 };
 
+
 string f32f16cvt[] = '{
 	"f32_to_f16_rne.tv",
 	"f32_to_f16_rz.tv",
@@ -290,6 +265,7 @@ string f64f32cvt[] = '{
 	"f32_to_f64_rnm.tv"
 };
 
+
 string f128f32cvt[] = '{
 	"f128_to_f32_rne.tv",
 	"f128_to_f32_rz.tv",
@@ -303,6 +279,7 @@ string f128f32cvt[] = '{
 	"f32_to_f128_rnm.tv"
 };
 
+
 string f128f64cvt[] = '{
 	"f128_to_f64_rne.tv",
 	"f128_to_f64_rz.tv",
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
new file mode 100644
index 000000000..bbc82d9ad
--- /dev/null
+++ b/pipelined/testbench/tests.vh
@@ -0,0 +1,1965 @@
+///////////////////////////////////////////
+// tests.vh
+//
+// Written: David_Harris@hmc.edu 7 October 2021
+// Modified: 
+//
+// Purpose: List of tests to apply
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`define IMPERASTEST   "0"
+`define RISCVARCHTEST "1"
+`define WALLYTEST "2"
+`define MYIMPERASTEST   "3"
+`define COREMARK "4"
+`define EMBENCH "5"
+`define CUSTOM "6"
+// *** remove MYIMPERASTEST cases when ported 
+
+string tvpaths[] = '{
+    "../../addins/imperas-riscv-tests/work/",
+    "../../tests/riscof/work/riscv-arch-test/",
+    "../../tests/riscof/work/wally-riscv-arch-test/",
+    "../../tests/imperas-riscv-tests/work/",
+    "../../benchmarks/coremark/work/",
+    "../../addins/embench-iot/",
+    "../../tests/custom/work/"
+    };
+
+  string coremark[] = '{
+    `COREMARK,
+    "coremark.bare.riscv"
+  };
+
+  string embench[] = '{
+    `EMBENCH,
+    "bd_speedopt_speed/src/aha-mont64/aha-mont64",
+    "bd_speedopt_speed/src/crc32/crc32",
+    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
+    "bd_speedopt_speed/src/edn/edn",
+    "bd_speedopt_speed/src/huffbench/huffbench",
+    "bd_speedopt_speed/src/matmult-int/matmult-int",
+    // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
+    "bd_speedopt_speed/src/minver/minver",
+    "bd_speedopt_speed/src/nettle-aes/nettle-aes",
+    "bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
+    "bd_speedopt_speed/src/nbody/nbody",
+    "bd_speedopt_speed/src/nsichneu/nsichneu",
+    "bd_speedopt_speed/src/picojpeg/picojpeg",
+    // "bd_speedopt_speed/src/primecount/primecount",
+    "bd_speedopt_speed/src/qrduino/qrduino",
+    "bd_speedopt_speed/src/sglib-combined/sglib-combined",
+    "bd_speedopt_speed/src/slre/slre",
+    "bd_speedopt_speed/src/st/st",
+    "bd_speedopt_speed/src/statemate/statemate",
+    // "bd_speedopt_speed/src/tarfind/tarfind",
+    "bd_speedopt_speed/src/ud/ud",
+    "bd_speedopt_speed/src/wikisort/wikisort",
+    "bd_sizeopt_speed/src/aha-mont64/aha-mont64",
+    "bd_sizeopt_speed/src/crc32/crc32",
+    "bd_sizeopt_speed/src/cubic/cubic",
+    "bd_sizeopt_speed/src/edn/edn",
+    "bd_sizeopt_speed/src/huffbench/huffbench",
+    "bd_sizeopt_speed/src/matmult-int/matmult-int",
+    // "bd_sizeopt_speed/src/md5sum/md5sum",
+    "bd_sizeopt_speed/src/minver/minver",
+    "bd_sizeopt_speed/src/nbody/nbody",
+    "bd_sizeopt_speed/src/nettle-aes/nettle-aes",
+    "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256",
+    "bd_sizeopt_speed/src/nsichneu/nsichneu",
+    "bd_sizeopt_speed/src/picojpeg/picojpeg",
+    // "bd_sizeopt_speed/src/primecount/primecount",
+    "bd_sizeopt_speed/src/qrduino/qrduino",
+    "bd_sizeopt_speed/src/sglib-combined/sglib-combined",
+    "bd_sizeopt_speed/src/slre/slre",
+    "bd_sizeopt_speed/src/st/st",
+    "bd_sizeopt_speed/src/statemate/statemate",
+    // "bd_sizeopt_speed/src/tarfind/tarfind",
+    "bd_sizeopt_speed/src/ud/ud",
+    "bd_sizeopt_speed/src/wikisort/wikisort"
+  };
+
+  // *** restore CSR tests from Imperas old
+  string extra64i[] = '{
+    `MYIMPERASTEST,
+    "rv64i_m/I/WALLY-ADD",
+    "rv64i_m/I/WALLY-SUB",
+    "rv64i_m/I/WALLY-ADDI",
+    "rv64i_m/I/WALLY-ANDI",
+    "rv64i_m/I/WALLY-ORI",
+    "rv64i_m/I/WALLY-XORI",
+    "rv64i_m/I/WALLY-SLTI",
+    "rv64i_m/I/WALLY-SLTIU",
+    "rv64i_m/I/WALLY-SLLI",
+    "rv64i_m/I/WALLY-SRLI",
+    "rv64i_m/I/WALLY-SRAI",
+    "rv64i_m/I/WALLY-JAL",
+    "rv64i_m/I/WALLY-JALR",
+    "rv64i_m/I/WALLY-STORE",
+    "rv64i_m/I/WALLY-ADDIW",
+    "rv64i_m/I/WALLY-SLLIW",
+    "rv64i_m/I/WALLY-SRLIW",
+    "rv64i_m/I/WALLY-SRAIW",
+    "rv64i_m/I/WALLY-ADDW",
+    "rv64i_m/I/WALLY-SUBW",
+    "rv64i_m/I/WALLY-SLLW",
+    "rv64i_m/I/WALLY-SRLW",
+    "rv64i_m/I/WALLY-SRAW",
+    "rv64i_m/I/WALLY-BEQ",
+    "rv64i_m/I/WALLY-BNE",
+    "rv64i_m/I/WALLY-BLTU",
+    "rv64i_m/I/WALLY-BLT",
+    "rv64i_m/I/WALLY-BGE",
+    "rv64i_m/I/WALLY-BGEU",
+    "rv64i_m/I/WALLY-CSRRW",
+    "rv64i_m/I/WALLY-CSRRS",
+    "rv64i_m/I/WALLY-CSRRC",
+    "rv64i_m/I/WALLY-CSRRWI",
+    "rv64i_m/I/WALLY-CSRRSI",
+    "rv64i_m/I/WALLY-CSRRCI" 
+  };
+
+  
+string imperas32f[] = '{
+    `IMPERASTEST,
+    "rv32i_m/F/FSQRT-S-DYN-RDN-01",
+    "rv32i_m/F/FADD-S-DYN-RDN-01",
+    "rv32i_m/F/FADD-S-DYN-RMM-01",
+    "rv32i_m/F/FADD-S-DYN-RNE-01",
+    "rv32i_m/F/FADD-S-DYN-RTZ-01",
+    "rv32i_m/F/FADD-S-DYN-RUP-01",
+    "rv32i_m/F/FADD-S-RDN-01",
+    "rv32i_m/F/FADD-S-RMM-01",
+    "rv32i_m/F/FADD-S-RNE-01",
+    "rv32i_m/F/FADD-S-RTZ-01",
+    "rv32i_m/F/FADD-S-RUP-01",
+    "rv32i_m/F/FCLASS-S-01",
+    "rv32i_m/F/FCVT-S-W-DYN-RDN-01",
+    "rv32i_m/F/FCVT-S-W-DYN-RMM-01",
+    "rv32i_m/F/FCVT-S-W-DYN-RNE-01",
+    "rv32i_m/F/FCVT-S-W-DYN-RTZ-01",
+    "rv32i_m/F/FCVT-S-W-DYN-RUP-01",
+    "rv32i_m/F/FCVT-S-W-RDN-01",
+    "rv32i_m/F/FCVT-S-W-RMM-01",
+    "rv32i_m/F/FCVT-S-W-RNE-01",
+    "rv32i_m/F/FCVT-S-W-RTZ-01",
+    "rv32i_m/F/FCVT-S-W-RUP-01",
+    "rv32i_m/F/FCVT-S-WU-DYN-RDN-01",
+    "rv32i_m/F/FCVT-S-WU-DYN-RMM-01",
+    "rv32i_m/F/FCVT-S-WU-DYN-RNE-01",
+    "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01",
+    "rv32i_m/F/FCVT-S-WU-DYN-RUP-01",
+    "rv32i_m/F/FCVT-S-WU-RDN-01",
+    "rv32i_m/F/FCVT-S-WU-RMM-01",
+    "rv32i_m/F/FCVT-S-WU-RNE-01",
+    "rv32i_m/F/FCVT-S-WU-RTZ-01",
+    "rv32i_m/F/FCVT-S-WU-RUP-01",
+    "rv32i_m/F/FCVT-W-S-DYN-RDN-01",
+    "rv32i_m/F/FCVT-W-S-DYN-RMM-01",
+    "rv32i_m/F/FCVT-W-S-DYN-RNE-01",
+    "rv32i_m/F/FCVT-W-S-DYN-RTZ-01",
+    "rv32i_m/F/FCVT-W-S-DYN-RUP-01",
+    "rv32i_m/F/FCVT-W-S-RDN-01",
+    "rv32i_m/F/FCVT-W-S-RMM-01",
+    "rv32i_m/F/FCVT-W-S-RNE-01",
+    "rv32i_m/F/FCVT-W-S-RTZ-01",
+    "rv32i_m/F/FCVT-W-S-RUP-01",
+    "rv32i_m/F/FCVT-WU-S-DYN-RDN-01",
+    "rv32i_m/F/FCVT-WU-S-DYN-RMM-01",
+    "rv32i_m/F/FCVT-WU-S-DYN-RNE-01",
+    "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01",
+    "rv32i_m/F/FCVT-WU-S-DYN-RUP-01",
+    "rv32i_m/F/FCVT-WU-S-RDN-01",
+    "rv32i_m/F/FCVT-WU-S-RMM-01",
+    "rv32i_m/F/FCVT-WU-S-RNE-01",
+    "rv32i_m/F/FCVT-WU-S-RTZ-01",
+    "rv32i_m/F/FCVT-WU-S-RUP-01",
+    "rv32i_m/F/FDIV-S-DYN-RDN-01",
+    "rv32i_m/F/FDIV-S-DYN-RMM-01",
+    "rv32i_m/F/FDIV-S-DYN-RNE-01",
+    "rv32i_m/F/FDIV-S-DYN-RTZ-01",
+    "rv32i_m/F/FDIV-S-DYN-RUP-01",
+    "rv32i_m/F/FDIV-S-RDN-01",
+    "rv32i_m/F/FDIV-S-RMM-01",
+    "rv32i_m/F/FDIV-S-RNE-01",
+    "rv32i_m/F/FDIV-S-RTZ-01",
+    "rv32i_m/F/FDIV-S-RUP-01",
+    "rv32i_m/F/FEQ-S-01",
+    "rv32i_m/F/FLE-S-01",
+    "rv32i_m/F/FLT-S-01",
+    "rv32i_m/F/FLW-01",
+    "rv32i_m/F/FMADD-S-DYN-RDN-01",
+    "rv32i_m/F/FMADD-S-DYN-RMM-01",
+    "rv32i_m/F/FMADD-S-DYN-RNE-01",
+    "rv32i_m/F/FMADD-S-DYN-RTZ-01",
+    "rv32i_m/F/FMADD-S-DYN-RUP-01",
+    "rv32i_m/F/FMADD-S-RDN-01",
+    "rv32i_m/F/FMADD-S-RMM-01",
+    "rv32i_m/F/FMADD-S-RNE-01",
+    "rv32i_m/F/FMADD-S-RTZ-01",
+    "rv32i_m/F/FMADD-S-RUP-01",
+    "rv32i_m/F/FMAX-S-01",
+    "rv32i_m/F/FMIN-S-01",
+    "rv32i_m/F/FMSUB-S-DYN-RDN-01",
+    "rv32i_m/F/FMSUB-S-DYN-RMM-01",
+    "rv32i_m/F/FMSUB-S-DYN-RNE-01",
+    "rv32i_m/F/FMSUB-S-DYN-RTZ-01",
+    "rv32i_m/F/FMSUB-S-DYN-RUP-01",
+    "rv32i_m/F/FMSUB-S-RDN-01",
+    "rv32i_m/F/FMSUB-S-RMM-01",
+    "rv32i_m/F/FMSUB-S-RNE-01",
+    "rv32i_m/F/FMSUB-S-RTZ-01",
+    "rv32i_m/F/FMSUB-S-RUP-01",
+    "rv32i_m/F/FMUL-S-DYN-RDN-01",
+    "rv32i_m/F/FMUL-S-DYN-RMM-01",
+    "rv32i_m/F/FMUL-S-DYN-RNE-01",
+    "rv32i_m/F/FMUL-S-DYN-RTZ-01",
+    "rv32i_m/F/FMUL-S-DYN-RUP-01",
+    "rv32i_m/F/FMUL-S-RDN-01",
+    "rv32i_m/F/FMUL-S-RMM-01",
+    "rv32i_m/F/FMUL-S-RNE-01",
+    "rv32i_m/F/FMUL-S-RTZ-01",
+    "rv32i_m/F/FMUL-S-RUP-01",
+    "rv32i_m/F/FMV-W-X-01",
+    "rv32i_m/F/FMV-X-W-01",
+    "rv32i_m/F/FNMADD-S-DYN-RDN-01",
+    "rv32i_m/F/FNMADD-S-DYN-RMM-01",
+    "rv32i_m/F/FNMADD-S-DYN-RNE-01",
+    "rv32i_m/F/FNMADD-S-DYN-RTZ-01",
+    "rv32i_m/F/FNMADD-S-DYN-RUP-01",
+    "rv32i_m/F/FNMADD-S-RDN-01",
+    "rv32i_m/F/FNMADD-S-RMM-01",
+    "rv32i_m/F/FNMADD-S-RNE-01",
+    "rv32i_m/F/FNMADD-S-RTZ-01",
+    "rv32i_m/F/FNMADD-S-RUP-01",
+    "rv32i_m/F/FNMSUB-S-DYN-RDN-01",
+    "rv32i_m/F/FNMSUB-S-DYN-RMM-01",
+    "rv32i_m/F/FNMSUB-S-DYN-RNE-01",
+    "rv32i_m/F/FNMSUB-S-DYN-RTZ-01",
+    "rv32i_m/F/FNMSUB-S-DYN-RUP-01",
+    "rv32i_m/F/FNMSUB-S-RDN-01",
+    "rv32i_m/F/FNMSUB-S-RMM-01",
+    "rv32i_m/F/FNMSUB-S-RNE-01",
+    "rv32i_m/F/FNMSUB-S-RTZ-01",
+    "rv32i_m/F/FNMSUB-S-RUP-01",
+    "rv32i_m/F/FSGNJN-S-01",
+    "rv32i_m/F/FSGNJ-S-01",
+    "rv32i_m/F/FSGNJX-S-01",
+    "rv32i_m/F/FSQRT-S-DYN-RDN-01",
+    "rv32i_m/F/FSQRT-S-DYN-RMM-01",
+    "rv32i_m/F/FSQRT-S-DYN-RNE-01",
+    "rv32i_m/F/FSQRT-S-DYN-RTZ-01",
+    "rv32i_m/F/FSQRT-S-DYN-RUP-01",
+    "rv32i_m/F/FSQRT-S-RDN-01",
+    "rv32i_m/F/FSQRT-S-RMM-01",
+    "rv32i_m/F/FSQRT-S-RNE-01",
+    "rv32i_m/F/FSQRT-S-RTZ-01",
+    "rv32i_m/F/FSQRT-S-RUP-01",
+    "rv32i_m/F/FSUB-S-DYN-RDN-01",
+    "rv32i_m/F/FSUB-S-DYN-RMM-01",
+    "rv32i_m/F/FSUB-S-DYN-RNE-01",
+    "rv32i_m/F/FSUB-S-DYN-RTZ-01",
+    "rv32i_m/F/FSUB-S-DYN-RUP-01",
+    "rv32i_m/F/FSUB-S-RDN-01",
+    "rv32i_m/F/FSUB-S-RMM-01",
+    "rv32i_m/F/FSUB-S-RNE-01",
+    "rv32i_m/F/FSUB-S-RTZ-01",
+    "rv32i_m/F/FSUB-S-RUP-01",
+    "rv32i_m/F/FSW-01"
+  };
+
+  string imperas64f[] = '{
+    `IMPERASTEST,
+    "rv64i_m/F/FADD-S-DYN-RDN-01",
+    "rv64i_m/F/FADD-S-DYN-RMM-01",
+    "rv64i_m/F/FADD-S-DYN-RNE-01",
+    "rv64i_m/F/FADD-S-DYN-RTZ-01",
+    "rv64i_m/F/FADD-S-DYN-RUP-01",
+    "rv64i_m/F/FADD-S-RDN-01",
+    "rv64i_m/F/FADD-S-RMM-01",
+    "rv64i_m/F/FADD-S-RNE-01",
+    "rv64i_m/F/FADD-S-RTZ-01",
+    "rv64i_m/F/FADD-S-RUP-01",
+    "rv64i_m/F/FCLASS-S-01",
+    "rv64i_m/F/FCVT-L-S-DYN-RDN-01",
+    "rv64i_m/F/FCVT-L-S-DYN-RMM-01",
+    "rv64i_m/F/FCVT-L-S-DYN-RNE-01",
+    "rv64i_m/F/FCVT-L-S-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-L-S-DYN-RUP-01",
+    "rv64i_m/F/FCVT-L-S-RDN-01",
+    "rv64i_m/F/FCVT-L-S-RMM-01",
+    "rv64i_m/F/FCVT-L-S-RNE-01",
+    "rv64i_m/F/FCVT-L-S-RTZ-01",
+    "rv64i_m/F/FCVT-L-S-RUP-01",
+    "rv64i_m/F/FCVT-LU-S-DYN-RDN-01",
+    "rv64i_m/F/FCVT-LU-S-DYN-RMM-01",
+    "rv64i_m/F/FCVT-LU-S-DYN-RNE-01",
+    "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-LU-S-DYN-RUP-01",
+    "rv64i_m/F/FCVT-LU-S-RDN-01",
+    "rv64i_m/F/FCVT-LU-S-RMM-01",
+    "rv64i_m/F/FCVT-LU-S-RNE-01",
+    "rv64i_m/F/FCVT-LU-S-RTZ-01",
+    "rv64i_m/F/FCVT-LU-S-RUP-01",
+    "rv64i_m/F/FCVT-S-L-DYN-RDN-01",
+    "rv64i_m/F/FCVT-S-L-DYN-RMM-01",
+    "rv64i_m/F/FCVT-S-L-DYN-RNE-01",
+    "rv64i_m/F/FCVT-S-L-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-S-L-DYN-RUP-01",
+    "rv64i_m/F/FCVT-S-L-RDN-01",
+    "rv64i_m/F/FCVT-S-L-RMM-01",
+    "rv64i_m/F/FCVT-S-L-RNE-01",
+    "rv64i_m/F/FCVT-S-L-RTZ-01",
+    "rv64i_m/F/FCVT-S-L-RUP-01",
+    "rv64i_m/F/FCVT-S-LU-DYN-RDN-01",
+    "rv64i_m/F/FCVT-S-LU-DYN-RMM-01",
+    "rv64i_m/F/FCVT-S-LU-DYN-RNE-01",
+    "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-S-LU-DYN-RUP-01",
+    "rv64i_m/F/FCVT-S-LU-RDN-01",
+    "rv64i_m/F/FCVT-S-LU-RMM-01",
+    "rv64i_m/F/FCVT-S-LU-RNE-01",
+    "rv64i_m/F/FCVT-S-LU-RTZ-01",
+    "rv64i_m/F/FCVT-S-LU-RUP-01",
+    "rv64i_m/F/FCVT-S-W-DYN-RDN-01",
+    "rv64i_m/F/FCVT-S-W-DYN-RMM-01",
+    "rv64i_m/F/FCVT-S-W-DYN-RNE-01",
+    "rv64i_m/F/FCVT-S-W-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-S-W-DYN-RUP-01",
+    "rv64i_m/F/FCVT-S-W-RDN-01",
+    "rv64i_m/F/FCVT-S-W-RMM-01",
+    "rv64i_m/F/FCVT-S-W-RNE-01",
+    "rv64i_m/F/FCVT-S-W-RTZ-01",
+    "rv64i_m/F/FCVT-S-W-RUP-01",
+    "rv64i_m/F/FCVT-S-WU-DYN-RDN-01",
+    "rv64i_m/F/FCVT-S-WU-DYN-RMM-01",
+    "rv64i_m/F/FCVT-S-WU-DYN-RNE-01",
+    "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-S-WU-DYN-RUP-01",
+    "rv64i_m/F/FCVT-S-WU-RDN-01",
+    "rv64i_m/F/FCVT-S-WU-RMM-01",
+    "rv64i_m/F/FCVT-S-WU-RNE-01",
+    "rv64i_m/F/FCVT-S-WU-RTZ-01",
+    "rv64i_m/F/FCVT-S-WU-RUP-01",
+    "rv64i_m/F/FCVT-W-S-DYN-RDN-01",
+    "rv64i_m/F/FCVT-W-S-DYN-RMM-01",
+    "rv64i_m/F/FCVT-W-S-DYN-RNE-01",
+    "rv64i_m/F/FCVT-W-S-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-W-S-DYN-RUP-01",
+    "rv64i_m/F/FCVT-W-S-RDN-01",
+    "rv64i_m/F/FCVT-W-S-RMM-01",
+    "rv64i_m/F/FCVT-W-S-RNE-01",
+    "rv64i_m/F/FCVT-W-S-RTZ-01",
+    "rv64i_m/F/FCVT-W-S-RUP-01",
+    "rv64i_m/F/FCVT-WU-S-DYN-RDN-01",
+    "rv64i_m/F/FCVT-WU-S-DYN-RMM-01",
+    "rv64i_m/F/FCVT-WU-S-DYN-RNE-01",
+    "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01",
+    "rv64i_m/F/FCVT-WU-S-DYN-RUP-01",
+    "rv64i_m/F/FCVT-WU-S-RDN-01",
+    "rv64i_m/F/FCVT-WU-S-RMM-01",
+    "rv64i_m/F/FCVT-WU-S-RNE-01",
+    "rv64i_m/F/FCVT-WU-S-RTZ-01",
+    "rv64i_m/F/FCVT-WU-S-RUP-01",
+    "rv64i_m/F/FDIV-S-DYN-RDN-01",
+    "rv64i_m/F/FDIV-S-DYN-RMM-01",
+    "rv64i_m/F/FDIV-S-DYN-RNE-01",
+    "rv64i_m/F/FDIV-S-DYN-RTZ-01",
+    "rv64i_m/F/FDIV-S-DYN-RUP-01",
+    "rv64i_m/F/FDIV-S-RDN-01",
+    "rv64i_m/F/FDIV-S-RMM-01",
+    "rv64i_m/F/FDIV-S-RNE-01",
+    "rv64i_m/F/FDIV-S-RTZ-01",
+    "rv64i_m/F/FDIV-S-RUP-01",
+    "rv64i_m/F/FEQ-S-01",
+    "rv64i_m/F/FLE-S-01",
+    "rv64i_m/F/FLT-S-01",
+    "rv64i_m/F/FLW-01",
+    "rv64i_m/F/FMADD-S-DYN-RDN-01",
+    "rv64i_m/F/FMADD-S-DYN-RMM-01",
+    "rv64i_m/F/FMADD-S-DYN-RNE-01",
+    "rv64i_m/F/FMADD-S-DYN-RTZ-01",
+    "rv64i_m/F/FMADD-S-DYN-RUP-01",
+    "rv64i_m/F/FMADD-S-RDN-01",
+    "rv64i_m/F/FMADD-S-RMM-01",
+    "rv64i_m/F/FMADD-S-RNE-01",
+    "rv64i_m/F/FMADD-S-RTZ-01",
+    "rv64i_m/F/FMADD-S-RUP-01",
+    "rv64i_m/F/FMAX-S-01",
+    "rv64i_m/F/FMIN-S-01",
+    "rv64i_m/F/FMSUB-S-DYN-RDN-01",
+    "rv64i_m/F/FMSUB-S-DYN-RMM-01",
+    "rv64i_m/F/FMSUB-S-DYN-RNE-01",
+    "rv64i_m/F/FMSUB-S-DYN-RTZ-01",
+    "rv64i_m/F/FMSUB-S-DYN-RUP-01",
+    "rv64i_m/F/FMSUB-S-RDN-01",
+    "rv64i_m/F/FMSUB-S-RMM-01",
+    "rv64i_m/F/FMSUB-S-RNE-01",
+    "rv64i_m/F/FMSUB-S-RTZ-01",
+    "rv64i_m/F/FMSUB-S-RUP-01",
+    "rv64i_m/F/FMUL-S-DYN-RDN-01",
+    "rv64i_m/F/FMUL-S-DYN-RMM-01",
+    "rv64i_m/F/FMUL-S-DYN-RNE-01",
+    "rv64i_m/F/FMUL-S-DYN-RTZ-01",
+    "rv64i_m/F/FMUL-S-DYN-RUP-01",
+    "rv64i_m/F/FMUL-S-RDN-01",
+    "rv64i_m/F/FMUL-S-RMM-01",
+    "rv64i_m/F/FMUL-S-RNE-01",
+    "rv64i_m/F/FMUL-S-RTZ-01",
+    "rv64i_m/F/FMUL-S-RUP-01",
+    "rv64i_m/F/FMV-W-X-01",
+    "rv64i_m/F/FMV-X-W-01",
+    "rv64i_m/F/FNMADD-S-DYN-RDN-01",
+    "rv64i_m/F/FNMADD-S-DYN-RMM-01",
+    "rv64i_m/F/FNMADD-S-DYN-RNE-01",
+    "rv64i_m/F/FNMADD-S-DYN-RTZ-01",
+    "rv64i_m/F/FNMADD-S-DYN-RUP-01",
+    "rv64i_m/F/FNMADD-S-RDN-01",
+    "rv64i_m/F/FNMADD-S-RMM-01",
+    "rv64i_m/F/FNMADD-S-RNE-01",
+    "rv64i_m/F/FNMADD-S-RTZ-01",
+    "rv64i_m/F/FNMADD-S-RUP-01",
+    "rv64i_m/F/FNMSUB-S-DYN-RDN-01",
+    "rv64i_m/F/FNMSUB-S-DYN-RMM-01",
+    "rv64i_m/F/FNMSUB-S-DYN-RNE-01",
+    "rv64i_m/F/FNMSUB-S-DYN-RTZ-01",
+    "rv64i_m/F/FNMSUB-S-DYN-RUP-01",
+    "rv64i_m/F/FNMSUB-S-RDN-01",
+    "rv64i_m/F/FNMSUB-S-RMM-01",
+    "rv64i_m/F/FNMSUB-S-RNE-01",
+    "rv64i_m/F/FNMSUB-S-RTZ-01",
+    "rv64i_m/F/FNMSUB-S-RUP-01",
+    "rv64i_m/F/FSGNJN-S-01",
+    "rv64i_m/F/FSGNJ-S-01",
+    "rv64i_m/F/FSGNJX-S-01",
+    "rv64i_m/F/FSQRT-S-DYN-RDN-01",
+    "rv64i_m/F/FSQRT-S-DYN-RMM-01",
+    "rv64i_m/F/FSQRT-S-DYN-RNE-01",
+    "rv64i_m/F/FSQRT-S-DYN-RTZ-01",
+    "rv64i_m/F/FSQRT-S-DYN-RUP-01",
+    "rv64i_m/F/FSQRT-S-RDN-01",
+    "rv64i_m/F/FSQRT-S-RMM-01",
+    "rv64i_m/F/FSQRT-S-RNE-01",
+    "rv64i_m/F/FSQRT-S-RTZ-01",
+    "rv64i_m/F/FSQRT-S-RUP-01",
+    "rv64i_m/F/FSUB-S-DYN-RDN-01",
+    "rv64i_m/F/FSUB-S-DYN-RMM-01",
+    "rv64i_m/F/FSUB-S-DYN-RNE-01",
+    "rv64i_m/F/FSUB-S-DYN-RTZ-01",
+    "rv64i_m/F/FSUB-S-DYN-RUP-01",
+    "rv64i_m/F/FSUB-S-RDN-01",
+    "rv64i_m/F/FSUB-S-RMM-01",
+    "rv64i_m/F/FSUB-S-RNE-01",
+    "rv64i_m/F/FSUB-S-RTZ-01",
+    "rv64i_m/F/FSUB-S-RUP-01",
+    "rv64i_m/F/FSW-01"
+  };
+
+  string imperas64d[] = '{
+    `IMPERASTEST,
+    "rv64i_m/D/FADD-D-DYN-RDN-01",
+    "rv64i_m/D/FADD-D-DYN-RMM-01",
+    "rv64i_m/D/FADD-D-DYN-RNE-01",
+    "rv64i_m/D/FADD-D-DYN-RTZ-01",
+    "rv64i_m/D/FADD-D-DYN-RUP-01",
+    "rv64i_m/D/FADD-D-RDN-01",
+    "rv64i_m/D/FADD-D-RMM-01",
+    "rv64i_m/D/FADD-D-RNE-01",
+    "rv64i_m/D/FADD-D-RTZ-01",
+    "rv64i_m/D/FADD-D-RUP-01",
+    "rv64i_m/D/FCLASS-D-01",
+    "rv64i_m/D/FCVT-D-L-DYN-RDN-01",
+    "rv64i_m/D/FCVT-D-L-DYN-RMM-01",
+    "rv64i_m/D/FCVT-D-L-DYN-RNE-01",
+    "rv64i_m/D/FCVT-D-L-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-D-L-DYN-RUP-01",
+    "rv64i_m/D/FCVT-D-L-RDN-01",
+    "rv64i_m/D/FCVT-D-L-RMM-01",
+    "rv64i_m/D/FCVT-D-L-RNE-01",
+    "rv64i_m/D/FCVT-D-L-RTZ-01",
+    "rv64i_m/D/FCVT-D-L-RUP-01",
+    "rv64i_m/D/FCVT-D-LU-DYN-RDN-01",
+    "rv64i_m/D/FCVT-D-LU-DYN-RMM-01",
+    "rv64i_m/D/FCVT-D-LU-DYN-RNE-01",
+    "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-D-LU-DYN-RUP-01",
+    "rv64i_m/D/FCVT-D-LU-RDN-01",
+    "rv64i_m/D/FCVT-D-LU-RMM-01",
+    "rv64i_m/D/FCVT-D-LU-RNE-01",
+    "rv64i_m/D/FCVT-D-LU-RTZ-01",
+    "rv64i_m/D/FCVT-D-LU-RUP-01",
+    "rv64i_m/D/FCVT-D-S-01",
+    "rv64i_m/D/FCVT-D-W-01",
+    "rv64i_m/D/FCVT-D-WU-01",
+    "rv64i_m/D/FCVT-L-D-DYN-RDN-01",
+    "rv64i_m/D/FCVT-L-D-DYN-RMM-01",
+    "rv64i_m/D/FCVT-L-D-DYN-RNE-01",
+    "rv64i_m/D/FCVT-L-D-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-L-D-DYN-RUP-01",
+    "rv64i_m/D/FCVT-L-D-RDN-01",
+    "rv64i_m/D/FCVT-L-D-RMM-01",
+    "rv64i_m/D/FCVT-L-D-RNE-01",
+    "rv64i_m/D/FCVT-L-D-RTZ-01",
+    "rv64i_m/D/FCVT-L-D-RUP-01",
+    "rv64i_m/D/FCVT-LU-D-DYN-RDN-01",
+    "rv64i_m/D/FCVT-LU-D-DYN-RMM-01",
+    "rv64i_m/D/FCVT-LU-D-DYN-RNE-01",
+    "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-LU-D-DYN-RUP-01",
+    "rv64i_m/D/FCVT-LU-D-RDN-01",
+    "rv64i_m/D/FCVT-LU-D-RMM-01",
+    "rv64i_m/D/FCVT-LU-D-RNE-01",
+    "rv64i_m/D/FCVT-LU-D-RTZ-01",
+    "rv64i_m/D/FCVT-LU-D-RUP-01",
+    "rv64i_m/D/FCVT-S-D-DYN-RDN-01",
+    "rv64i_m/D/FCVT-S-D-DYN-RMM-01",
+    "rv64i_m/D/FCVT-S-D-DYN-RNE-01",
+    "rv64i_m/D/FCVT-S-D-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-S-D-DYN-RUP-01",
+    "rv64i_m/D/FCVT-S-D-RDN-01",
+    "rv64i_m/D/FCVT-S-D-RMM-01",
+    "rv64i_m/D/FCVT-S-D-RNE-01",
+    "rv64i_m/D/FCVT-S-D-RTZ-01",
+    "rv64i_m/D/FCVT-S-D-RUP-01",
+    "rv64i_m/D/FCVT-W-D-DYN-RDN-01",
+    "rv64i_m/D/FCVT-W-D-DYN-RMM-01",
+    "rv64i_m/D/FCVT-W-D-DYN-RNE-01",
+    "rv64i_m/D/FCVT-W-D-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-W-D-DYN-RUP-01",
+    "rv64i_m/D/FCVT-W-D-RDN-01",
+    "rv64i_m/D/FCVT-W-D-RMM-01",
+    "rv64i_m/D/FCVT-W-D-RNE-01",
+    "rv64i_m/D/FCVT-W-D-RTZ-01",
+    "rv64i_m/D/FCVT-W-D-RUP-01",
+    "rv64i_m/D/FCVT-WU-D-DYN-RDN-01",
+    "rv64i_m/D/FCVT-WU-D-DYN-RMM-01",
+    "rv64i_m/D/FCVT-WU-D-DYN-RNE-01",
+    "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01",
+    "rv64i_m/D/FCVT-WU-D-DYN-RUP-01",
+    "rv64i_m/D/FCVT-WU-D-RDN-01",
+    "rv64i_m/D/FCVT-WU-D-RMM-01",
+    "rv64i_m/D/FCVT-WU-D-RNE-01",
+    "rv64i_m/D/FCVT-WU-D-RTZ-01",
+    "rv64i_m/D/FCVT-WU-D-RUP-01",
+    "rv64i_m/D/FDIV-D-DYN-RDN-01",
+    "rv64i_m/D/FDIV-D-DYN-RMM-01",
+    "rv64i_m/D/FDIV-D-DYN-RNE-01",
+    "rv64i_m/D/FDIV-D-DYN-RTZ-01",
+    "rv64i_m/D/FDIV-D-DYN-RUP-01",
+    "rv64i_m/D/FDIV-D-RDN-01",
+    "rv64i_m/D/FDIV-D-RMM-01",
+    "rv64i_m/D/FDIV-D-RNE-01",
+    "rv64i_m/D/FDIV-D-RTZ-01",
+    "rv64i_m/D/FDIV-D-RUP-01",
+    "rv64i_m/D/FEQ-D-01",
+    "rv64i_m/D/FLD-01",
+    "rv64i_m/D/FLE-D-01",
+    "rv64i_m/D/FLT-D-01",
+    "rv64i_m/D/FMADD-D-DYN-RDN-01",
+    "rv64i_m/D/FMADD-D-DYN-RMM-01",
+    "rv64i_m/D/FMADD-D-DYN-RNE-01",
+    "rv64i_m/D/FMADD-D-DYN-RTZ-01",
+    "rv64i_m/D/FMADD-D-DYN-RUP-01",
+    "rv64i_m/D/FMADD-D-RDN-01",
+    "rv64i_m/D/FMADD-D-RMM-01",
+    "rv64i_m/D/FMADD-D-RNE-01",
+    "rv64i_m/D/FMADD-D-RTZ-01",
+    "rv64i_m/D/FMADD-D-RUP-01",
+    "rv64i_m/D/FMAX-D-01",
+    "rv64i_m/D/FMIN-D-01",
+    "rv64i_m/D/FMSUB-D-DYN-RDN-01",
+    "rv64i_m/D/FMSUB-D-DYN-RMM-01",
+    "rv64i_m/D/FMSUB-D-DYN-RNE-01",
+    "rv64i_m/D/FMSUB-D-DYN-RTZ-01",
+    "rv64i_m/D/FMSUB-D-DYN-RUP-01",
+    "rv64i_m/D/FMSUB-D-RDN-01",
+    "rv64i_m/D/FMSUB-D-RMM-01",
+    "rv64i_m/D/FMSUB-D-RNE-01",
+    "rv64i_m/D/FMSUB-D-RTZ-01",
+    "rv64i_m/D/FMSUB-D-RUP-01",
+    "rv64i_m/D/FMUL-D-DYN-RDN-01",
+    "rv64i_m/D/FMUL-D-DYN-RMM-01",
+    "rv64i_m/D/FMUL-D-DYN-RNE-01",
+    "rv64i_m/D/FMUL-D-DYN-RTZ-01",
+    "rv64i_m/D/FMUL-D-DYN-RUP-01",
+    "rv64i_m/D/FMUL-D-RDN-01",
+    "rv64i_m/D/FMUL-D-RMM-01",
+    "rv64i_m/D/FMUL-D-RNE-01",
+    "rv64i_m/D/FMUL-D-RTZ-01",
+    "rv64i_m/D/FMUL-D-RUP-01",
+    "rv64i_m/D/FMV-D-X-01",
+    "rv64i_m/D/FMV-X-D-01",
+    "rv64i_m/D/FNMADD-D-DYN-RDN-01",
+    "rv64i_m/D/FNMADD-D-DYN-RMM-01",
+    "rv64i_m/D/FNMADD-D-DYN-RNE-01",
+    "rv64i_m/D/FNMADD-D-DYN-RTZ-01",
+    "rv64i_m/D/FNMADD-D-DYN-RUP-01",
+    "rv64i_m/D/FNMADD-D-RDN-01",
+    "rv64i_m/D/FNMADD-D-RMM-01",
+    "rv64i_m/D/FNMADD-D-RNE-01",
+    "rv64i_m/D/FNMADD-D-RTZ-01",
+    "rv64i_m/D/FNMADD-D-RUP-01",
+    "rv64i_m/D/FNMSUB-D-DYN-RDN-01",
+    "rv64i_m/D/FNMSUB-D-DYN-RMM-01",
+    "rv64i_m/D/FNMSUB-D-DYN-RNE-01",
+    "rv64i_m/D/FNMSUB-D-DYN-RTZ-01",
+    "rv64i_m/D/FNMSUB-D-DYN-RUP-01",
+    "rv64i_m/D/FNMSUB-D-RDN-01",
+    "rv64i_m/D/FNMSUB-D-RMM-01",
+    "rv64i_m/D/FNMSUB-D-RNE-01",
+    "rv64i_m/D/FNMSUB-D-RTZ-01",
+    "rv64i_m/D/FNMSUB-D-RUP-01",
+    "rv64i_m/D/FSD-01",
+    "rv64i_m/D/FSGNJ-D-01",
+    "rv64i_m/D/FSGNJN-D-01",
+    "rv64i_m/D/FSGNJX-D-01",
+    "rv64i_m/D/FSQRT-D-DYN-RDN-01",
+    "rv64i_m/D/FSQRT-D-DYN-RMM-01",
+    "rv64i_m/D/FSQRT-D-DYN-RNE-01",
+    "rv64i_m/D/FSQRT-D-DYN-RTZ-01",
+    "rv64i_m/D/FSQRT-D-DYN-RUP-01",
+    "rv64i_m/D/FSQRT-D-RDN-01",
+    "rv64i_m/D/FSQRT-D-RMM-01",
+    "rv64i_m/D/FSQRT-D-RNE-01",
+    "rv64i_m/D/FSQRT-D-RTZ-01",
+    "rv64i_m/D/FSQRT-D-RUP-01",
+    "rv64i_m/D/FSUB-D-DYN-RDN-01",
+    "rv64i_m/D/FSUB-D-DYN-RMM-01",
+    "rv64i_m/D/FSUB-D-DYN-RNE-01",
+    "rv64i_m/D/FSUB-D-DYN-RTZ-01",
+    "rv64i_m/D/FSUB-D-DYN-RUP-01",
+    "rv64i_m/D/FSUB-D-RDN-01",
+    "rv64i_m/D/FSUB-D-RMM-01",
+    "rv64i_m/D/FSUB-D-RNE-01",
+    "rv64i_m/D/FSUB-D-RTZ-01",
+    "rv64i_m/D/FSUB-D-RUP-01"
+};
+
+  string imperas64m[] = '{
+    `IMPERASTEST,
+    "rv64i_m/M/DIV-01",
+    "rv64i_m/M/DIVU-01",
+    "rv64i_m/M/DIVUW-01",
+    "rv64i_m/M/DIVW-01",
+    "rv64i_m/M/MUL-01",
+    "rv64i_m/M/MULH-01",
+    "rv64i_m/M/MULHSU-01",
+    "rv64i_m/M/MULHU-01",
+    "rv64i_m/M/MULW-01",
+    "rv64i_m/M/REM-01",
+    "rv64i_m/M/REMU-01",
+    "rv64i_m/M/REMUW-01",
+    "rv64i_m/M/REMW-01"
+  };
+
+  string imperas64c[] = '{
+    `IMPERASTEST,
+    "rv64i_m/C/C-ADD-01",
+    "rv64i_m/C/C-ADDI-01",
+    "rv64i_m/C/C-ADDI16SP-01",
+    "rv64i_m/C/C-ADDI4SPN-01",
+    "rv64i_m/C/C-ADDIW-01",
+    "rv64i_m/C/C-ADDW-01",
+    "rv64i_m/C/C-AND-01",
+    "rv64i_m/C/C-ANDI-01",
+    "rv64i_m/C/C-BEQZ-01",
+    "rv64i_m/C/C-BNEZ-01",
+    "rv64i_m/C/C-J-01",
+    "rv64i_m/C/C-JALR-01",
+    "rv64i_m/C/C-JR-01",
+    "rv64i_m/C/C-LD-01",
+    "rv64i_m/C/C-LDSP-01",
+    "rv64i_m/C/C-LI-01",
+    "rv64i_m/C/C-LUI-01",
+    "rv64i_m/C/C-LW-01",
+    "rv64i_m/C/C-LWSP-01",
+    "rv64i_m/C/C-MV-01",
+    "rv64i_m/C/C-OR-01",
+    "rv64i_m/C/C-SD-01",
+    "rv64i_m/C/C-SDSP-01",
+    "rv64i_m/C/C-SLLI-01",
+    "rv64i_m/C/C-SRAI-01",
+    "rv64i_m/C/C-SRLI-01",
+    "rv64i_m/C/C-SUB-01",
+    "rv64i_m/C/C-SUBW-01",
+    "rv64i_m/C/C-SW-01",
+    "rv64i_m/C/C-SWSP-01",
+    "rv64i_m/C/C-XOR-01",
+    "rv64i_m/C/I-C-EBREAK-01",
+    "rv64i_m/C/I-C-NOP-01"
+  };
+
+  string imperas64iNOc[] = {
+    `IMPERASTEST,
+    "rv64i_m/I/I-MISALIGN_JMP-01"
+  };
+
+  string imperas64i[] = '{
+    `IMPERASTEST,
+    "rv64i_m/I/I-DELAY_SLOTS-01",
+    "rv64i_m/I/ADD-01",
+    "rv64i_m/I/ADDI-01",
+    "rv64i_m/I/ADDIW-01",
+    "rv64i_m/I/ADDW-01",
+    "rv64i_m/I/AND-01",
+    "rv64i_m/I/ANDI-01",
+    "rv64i_m/I/AUIPC-01",
+    "rv64i_m/I/BEQ-01",
+    "rv64i_m/I/BGE-01",
+    "rv64i_m/I/BGEU-01",
+    "rv64i_m/I/BLT-01",
+    "rv64i_m/I/BLTU-01",
+    "rv64i_m/I/BNE-01",
+    "rv64i_m/I/I-DELAY_SLOTS-01",
+    "rv64i_m/I/I-EBREAK-01",
+    "rv64i_m/I/I-ECALL-01",
+    "rv64i_m/I/I-ENDIANESS-01",
+    "rv64i_m/I/I-IO-01",
+//    "rv64i_m/I/I-MISALIGN_JMP-01",
+    "rv64i_m/I/I-MISALIGN_LDST-01",
+    "rv64i_m/I/I-NOP-01",
+    "rv64i_m/I/I-RF_size-01",
+    "rv64i_m/I/I-RF_width-01",
+    "rv64i_m/I/I-RF_x0-01",
+    "rv64i_m/I/JAL-01",
+    "rv64i_m/I/JALR-01",
+    "rv64i_m/I/LB-01",
+    "rv64i_m/I/LBU-01",
+    "rv64i_m/I/LD-01",
+    "rv64i_m/I/LH-01",
+    "rv64i_m/I/LHU-01",
+    "rv64i_m/I/LUI-01",
+    "rv64i_m/I/LW-01",
+    "rv64i_m/I/LWU-01",
+    "rv64i_m/I/OR-01",
+    "rv64i_m/I/ORI-01",
+    "rv64i_m/I/SB-01",
+    "rv64i_m/I/SD-01",
+    "rv64i_m/I/SH-01",
+    "rv64i_m/I/SLL-01",
+    "rv64i_m/I/SLLI-01",
+    "rv64i_m/I/SLLIW-01",
+    "rv64i_m/I/SLLW-01",
+    "rv64i_m/I/SLT-01",
+    "rv64i_m/I/SLTI-01",
+    "rv64i_m/I/SLTIU-01",
+    "rv64i_m/I/SLTU-01",
+    "rv64i_m/I/SRA-01",
+    "rv64i_m/I/SRAI-01",
+    "rv64i_m/I/SRAIW-01",
+    "rv64i_m/I/SRAW-01",
+    "rv64i_m/I/SRL-01",
+    "rv64i_m/I/SRLI-01",
+    "rv64i_m/I/SRLIW-01",
+    "rv64i_m/I/SRLW-01",
+    "rv64i_m/I/SUB-01",
+    "rv64i_m/I/SUBW-01",
+    "rv64i_m/I/SW-01",
+    "rv64i_m/I/XOR-01",
+    "rv64i_m/I/XORI-01"
+  };
+
+  string imperas32m[] = '{
+    `IMPERASTEST,
+    "rv32i_m/M/DIV-01",
+    "rv32i_m/M/DIVU-01",
+    "rv32i_m/M/MUL-01",
+    "rv32i_m/M/MULH-01",
+    "rv32i_m/M/MULHSU-01",
+    "rv32i_m/M/MULHU-01",
+    "rv32i_m/M/REM-01",
+    "rv32i_m/M/REMU-01"
+  };
+
+  string imperas32c[] = '{
+    `IMPERASTEST,
+    "rv32i_m/C/C-ADD-01",
+    "rv32i_m/C/C-ADDI-01",
+    "rv32i_m/C/C-ADDI16SP-01",
+    "rv32i_m/C/C-ADDI4SPN-01",
+    "rv32i_m/C/C-AND-01",
+    "rv32i_m/C/C-ANDI-01",
+    "rv32i_m/C/C-BEQZ-01",
+    "rv32i_m/C/C-BNEZ-01",
+    "rv32i_m/C/C-J-01",
+    "rv32i_m/C/C-JAL-01",
+    "rv32i_m/C/C-JALR-01",
+    "rv32i_m/C/C-JR-01",
+    "rv32i_m/C/C-LI-01",
+    "rv32i_m/C/C-LUI-01",
+    "rv32i_m/C/C-LW-01",
+    "rv32i_m/C/C-LWSP-01",
+    "rv32i_m/C/C-MV-01",
+    "rv32i_m/C/C-OR-01",
+    "rv32i_m/C/C-SLLI-01",
+    "rv32i_m/C/C-SRAI-01",
+    "rv32i_m/C/C-SRLI-01",
+    "rv32i_m/C/C-SUB-01",
+    "rv32i_m/C/C-SW-01",
+    "rv32i_m/C/C-SWSP-01",
+    "rv32i_m/C/C-XOR-01",
+    "rv32i_m/C/I-C-EBREAK-01",
+    "rv32i_m/C/I-C-NOP-01"
+  };
+
+  string imperas32iNOc[] = {
+    `IMPERASTEST,
+    "rv32i_m/I/I-MISALIGN_JMP-01"
+  };
+
+  string imperas32i[] = {
+    `IMPERASTEST,
+    "rv32i_m/I/ADD-01",
+    "rv32i_m/I/ADDI-01",
+    "rv32i_m/I/AND-01",
+    "rv32i_m/I/ANDI-01",
+    "rv32i_m/I/AUIPC-01",
+    "rv32i_m/I/BEQ-01",
+    "rv32i_m/I/BGE-01",
+    "rv32i_m/I/BGEU-01",
+    "rv32i_m/I/BLT-01",
+    "rv32i_m/I/BLTU-01",
+    "rv32i_m/I/BNE-01",
+    "rv32i_m/I/I-DELAY_SLOTS-01",
+    "rv32i_m/I/I-EBREAK-01",
+    "rv32i_m/I/I-ECALL-01",
+    "rv32i_m/I/I-ENDIANESS-01",
+    "rv32i_m/I/I-IO-01",
+//    "rv32i_m/I/I-MISALIGN_JMP-01",
+    "rv32i_m/I/I-MISALIGN_LDST-01",
+    "rv32i_m/I/I-NOP-01",
+    "rv32i_m/I/I-RF_size-01",
+    "rv32i_m/I/I-RF_width-01",
+    "rv32i_m/I/I-RF_x0-01",
+    "rv32i_m/I/JAL-01",
+    "rv32i_m/I/JALR-01",
+    "rv32i_m/I/LB-01",
+    "rv32i_m/I/LBU-01",
+    "rv32i_m/I/LH-01",
+    "rv32i_m/I/LHU-01",
+    "rv32i_m/I/LUI-01",
+    "rv32i_m/I/LW-01",
+    "rv32i_m/I/OR-01",
+    "rv32i_m/I/ORI-01",
+    "rv32i_m/I/SB-01",
+    "rv32i_m/I/SH-01",
+    "rv32i_m/I/SLL-01",
+    "rv32i_m/I/SLLI-01",
+    "rv32i_m/I/SLT-01",
+    "rv32i_m/I/SLTI-01",
+    "rv32i_m/I/SLTIU-01",
+    "rv32i_m/I/SLTU-01",
+    "rv32i_m/I/SRA-01",
+    "rv32i_m/I/SRAI-01",
+    "rv32i_m/I/SRL-01",
+    "rv32i_m/I/SRLI-01",
+    "rv32i_m/I/SUB-01",
+    "rv32i_m/I/SW-01",
+    "rv32i_m/I/XOR-01",
+    "rv32i_m/I/XORI-01"   
+  };
+
+  string imperas32p[] = '{
+    `MYIMPERASTEST,
+    "rv32p/WALLY-MSTATUS",
+    "rv32p/WALLY-MCAUSE",
+    "rv32p/WALLY-SCAUSE",
+    "rv32p/WALLY-MEPC",
+    "rv32p/WALLY-SEPC",
+    "rv32p/WALLY-MTVAL",
+    "rv32p/WALLY-STVAL",
+    "rv32p/WALLY-MARCHID",
+    "rv32p/WALLY-MIMPID",
+    "rv32p/WALLY-MHARTID",
+    "rv32p/WALLY-MVENDORID",
+    "rv32p/WALLY-MTVEC",
+    "rv32p/WALLY-STVEC",
+    "rv32p/WALLY-MIE",
+    "rv32p/WALLY-MEDELEG",
+    "rv32p/WALLY-IP",
+    "rv32p/WALLY-CSR-PERMISSIONS-M",
+    "rv32p/WALLY-CSR-PERMISSIONS-S"
+  };
+
+ string wally64a[] = '{
+    `WALLYTEST,
+    "rv64i_m/privilege/src/WALLY-amo-01.S",
+    "rv64i_m/privilege/src/WALLY-lrsc-01.S",
+    "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
+  };
+
+ string wally32a[] = '{
+    `WALLYTEST,
+    "rv32i_m/privilege/src/WALLY-amo-01.S",
+    "rv32i_m/privilege/src/WALLY-lrsc-01.S",
+    "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
+ };
+
+  string arch64priv[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/privilege/src/ebreak.S",
+    "rv64i_m/privilege/src/ecall.S",
+//    "rv64i_m/privilege/src/misalign1-jalr-01.S",
+    "rv64i_m/privilege/src/misalign2-jalr-01.S",
+    "rv64i_m/privilege/src/misalign-beq-01.S",
+    "rv64i_m/privilege/src/misalign-bge-01.S",
+    "rv64i_m/privilege/src/misalign-bgeu-01.S",
+    "rv64i_m/privilege/src/misalign-blt-01.S",
+    "rv64i_m/privilege/src/misalign-bltu-01.S",
+    "rv64i_m/privilege/src/misalign-bne-01.S",
+    "rv64i_m/privilege/src/misalign-jal-01.S",
+    "rv64i_m/privilege/src/misalign-ld-01.S",
+    "rv64i_m/privilege/src/misalign-lh-01.S",
+    "rv64i_m/privilege/src/misalign-lhu-01.S",
+    "rv64i_m/privilege/src/misalign-lw-01.S",
+    "rv64i_m/privilege/src/misalign-lwu-01.S",
+    "rv64i_m/privilege/src/misalign-sd-01.S",
+    "rv64i_m/privilege/src/misalign-sh-01.S",
+    "rv64i_m/privilege/src/misalign-sw-01.S"
+    };
+
+  string arch64zi[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/Zifencei/src/Fencei.S"
+    };
+
+  string arch32zi[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/Zifencei/src/Fencei.S"
+    };
+
+  string arch32ba[] = '{
+    `RISCVARCHTEST,
+    // *** unclear why add.uw isn't in the list
+    "rv64i_m/B/src/sh1add-01.S",
+    "rv64i_m/B/src/sh1add-02.S",
+    "rv64i_m/B/src/sh1add-013.S"
+  };
+
+  string arch64m[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/M/src/div-01.S",
+    "rv64i_m/M/src/divu-01.S",
+    "rv64i_m/M/src/divuw-01.S",
+    "rv64i_m/M/src/divw-01.S",
+    "rv64i_m/M/src/mul-01.S",
+    "rv64i_m/M/src/mulh-01.S",
+    "rv64i_m/M/src/mulhsu-01.S",
+    "rv64i_m/M/src/mulhu-01.S",
+    "rv64i_m/M/src/mulw-01.S",
+    "rv64i_m/M/src/rem-01.S",
+    "rv64i_m/M/src/remu-01.S",
+    "rv64i_m/M/src/remuw-01.S",
+    "rv64i_m/M/src/remw-01.S"
+   };
+
+  string arch64c[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/C/src/cadd-01.S",
+    "rv64i_m/C/src/caddi-01.S",
+    "rv64i_m/C/src/caddi16sp-01.S",
+    "rv64i_m/C/src/caddi4spn-01.S",
+    "rv64i_m/C/src/caddiw-01.S",
+    "rv64i_m/C/src/caddw-01.S",
+    "rv64i_m/C/src/cand-01.S",
+    "rv64i_m/C/src/candi-01.S",
+    "rv64i_m/C/src/cbeqz-01.S",
+    "rv64i_m/C/src/cbnez-01.S",
+    "rv64i_m/C/src/cj-01.S",
+    "rv64i_m/C/src/cjalr-01.S",
+    "rv64i_m/C/src/cjr-01.S",
+    "rv64i_m/C/src/cld-01.S",
+    "rv64i_m/C/src/cldsp-01.S",
+    "rv64i_m/C/src/cli-01.S",
+    "rv64i_m/C/src/clui-01.S",
+    "rv64i_m/C/src/clw-01.S",
+    "rv64i_m/C/src/clwsp-01.S",
+    "rv64i_m/C/src/cmv-01.S",
+    "rv64i_m/C/src/cnop-01.S",
+    "rv64i_m/C/src/cor-01.S",
+    "rv64i_m/C/src/csd-01.S",
+    "rv64i_m/C/src/csdsp-01.S",
+    "rv64i_m/C/src/cslli-01.S",
+    "rv64i_m/C/src/csrai-01.S",
+    "rv64i_m/C/src/csrli-01.S",
+    "rv64i_m/C/src/csub-01.S",
+    "rv64i_m/C/src/csubw-01.S",
+    "rv64i_m/C/src/csw-01.S",
+    "rv64i_m/C/src/cswsp-01.S",
+    "rv64i_m/C/src/cxor-01.S"
+  };
+
+  string arch64cpriv[] = '{
+//    `RISCVARCHTEST,
+    "rv64i_m/C/src/cebreak-01.S"
+  };
+
+  string arch64i[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/I/src/add-01.S",
+    "rv64i_m/I/src/addi-01.S",
+    "rv64i_m/I/src/addiw-01.S",
+    "rv64i_m/I/src/addw-01.S",
+    "rv64i_m/I/src/and-01.S",
+    "rv64i_m/I/src/andi-01.S",
+    "rv64i_m/I/src/auipc-01.S",
+    "rv64i_m/I/src/beq-01.S",
+    "rv64i_m/I/src/bge-01.S",
+    "rv64i_m/I/src/bgeu-01.S",
+    "rv64i_m/I/src/blt-01.S",
+    "rv64i_m/I/src/bltu-01.S",
+    "rv64i_m/I/src/bne-01.S",
+    "rv64i_m/I/src/fence-01.S",
+    "rv64i_m/I/src/jal-01.S",
+    "rv64i_m/I/src/jalr-01.S",
+    "rv64i_m/I/src/lb-align-01.S",
+    "rv64i_m/I/src/lbu-align-01.S",
+    "rv64i_m/I/src/ld-align-01.S",
+    "rv64i_m/I/src/lh-align-01.S",
+    "rv64i_m/I/src/lhu-align-01.S",
+    "rv64i_m/I/src/lui-01.S",
+    "rv64i_m/I/src/lw-align-01.S",
+    "rv64i_m/I/src/lwu-align-01.S",
+    "rv64i_m/I/src/or-01.S",
+    "rv64i_m/I/src/ori-01.S",
+    "rv64i_m/I/src/sb-align-01.S",
+    "rv64i_m/I/src/sd-align-01.S",
+    "rv64i_m/I/src/sh-align-01.S",
+    "rv64i_m/I/src/sll-01.S",
+    "rv64i_m/I/src/slli-01.S",
+    "rv64i_m/I/src/slliw-01.S",
+    "rv64i_m/I/src/sllw-01.S",
+    "rv64i_m/I/src/slt-01.S",
+    "rv64i_m/I/src/slti-01.S",
+    "rv64i_m/I/src/sltiu-01.S",
+    "rv64i_m/I/src/sltu-01.S",
+    "rv64i_m/I/src/sra-01.S",
+    "rv64i_m/I/src/srai-01.S",
+    "rv64i_m/I/src/sraiw-01.S",
+    "rv64i_m/I/src/sraw-01.S",
+    "rv64i_m/I/src/srl-01.S",
+    "rv64i_m/I/src/srli-01.S",
+    "rv64i_m/I/src/srliw-01.S",
+    "rv64i_m/I/src/srlw-01.S",
+    "rv64i_m/I/src/sub-01.S",
+    "rv64i_m/I/src/subw-01.S",
+    "rv64i_m/I/src/sw-align-01.S",
+    "rv64i_m/I/src/xor-01.S",
+    "rv64i_m/I/src/xori-01.S"
+  };
+
+  string arch64f[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/F/src/fadd_b10-01.S",
+    "rv64i_m/F/src/fadd_b1-01.S",
+    "rv64i_m/F/src/fadd_b11-01.S",
+    "rv64i_m/F/src/fadd_b12-01.S",
+    "rv64i_m/F/src/fadd_b13-01.S",
+    "rv64i_m/F/src/fadd_b2-01.S",
+    "rv64i_m/F/src/fadd_b3-01.S",
+    "rv64i_m/F/src/fadd_b4-01.S",
+    "rv64i_m/F/src/fadd_b5-01.S",
+    "rv64i_m/F/src/fadd_b7-01.S",
+    "rv64i_m/F/src/fadd_b8-01.S",
+    "rv64i_m/F/src/fclass_b1-01.S",
+    "rv64i_m/F/src/fcvt.s.w_b25-01.S",
+    "rv64i_m/F/src/fcvt.s.w_b26-01.S",
+    "rv64i_m/F/src/fcvt.s.wu_b25-01.S",
+    "rv64i_m/F/src/fcvt.s.wu_b26-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b29-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b29-01.S",
+    "rv64i_m/F/src/fdiv_b1-01.S",
+    "rv64i_m/F/src/fdiv_b20-01.S",
+    "rv64i_m/F/src/fdiv_b2-01.S",
+    "rv64i_m/F/src/fdiv_b21-01.S",
+    "rv64i_m/F/src/fdiv_b3-01.S",
+    "rv64i_m/F/src/fdiv_b4-01.S",
+    "rv64i_m/F/src/fdiv_b5-01.S",
+    "rv64i_m/F/src/fdiv_b6-01.S",
+    "rv64i_m/F/src/fdiv_b7-01.S",
+    "rv64i_m/F/src/fdiv_b8-01.S",
+    "rv64i_m/F/src/fdiv_b9-01.S",
+    "rv64i_m/F/src/feq_b1-01.S",
+    "rv64i_m/F/src/feq_b19-01.S",
+    "rv64i_m/F/src/fle_b1-01.S",
+    "rv64i_m/F/src/fle_b19-01.S",
+    "rv64i_m/F/src/flt_b1-01.S",
+    "rv64i_m/F/src/flt_b19-01.S",
+    "rv64i_m/F/src/flw-align-01.S",
+    "rv64i_m/F/src/fmadd_b1-01.S",
+    "rv64i_m/F/src/fmadd_b14-01.S",
+    //"rv64i_m/F/src/fmadd_b15-01.S",
+    "rv64i_m/F/src/fmadd_b16-01.S",
+    "rv64i_m/F/src/fmadd_b17-01.S",
+    "rv64i_m/F/src/fmadd_b18-01.S",
+    "rv64i_m/F/src/fmadd_b2-01.S",
+    "rv64i_m/F/src/fmadd_b3-01.S",
+    "rv64i_m/F/src/fmadd_b4-01.S",
+    "rv64i_m/F/src/fmadd_b5-01.S",
+    "rv64i_m/F/src/fmadd_b6-01.S",
+    "rv64i_m/F/src/fmadd_b7-01.S",
+    "rv64i_m/F/src/fmadd_b8-01.S",
+    "rv64i_m/F/src/fmax_b1-01.S",
+    "rv64i_m/F/src/fmax_b19-01.S",
+    "rv64i_m/F/src/fmin_b1-01.S",
+    "rv64i_m/F/src/fmin_b19-01.S",
+    "rv64i_m/F/src/fmsub_b1-01.S",
+    "rv64i_m/F/src/fmsub_b14-01.S",
+    "rv64i_m/F/src/fmsub_b15-01.S",
+    "rv64i_m/F/src/fmsub_b16-01.S",
+    "rv64i_m/F/src/fmsub_b17-01.S",
+    "rv64i_m/F/src/fmsub_b18-01.S",
+    "rv64i_m/F/src/fmsub_b2-01.S",
+    "rv64i_m/F/src/fmsub_b3-01.S",
+    "rv64i_m/F/src/fmsub_b4-01.S",
+    "rv64i_m/F/src/fmsub_b5-01.S",
+    "rv64i_m/F/src/fmsub_b6-01.S",
+    "rv64i_m/F/src/fmsub_b7-01.S",
+    "rv64i_m/F/src/fmsub_b8-01.S",
+    "rv64i_m/F/src/fmul_b1-01.S",
+    "rv64i_m/F/src/fmul_b2-01.S",
+    "rv64i_m/F/src/fmul_b3-01.S",
+    "rv64i_m/F/src/fmul_b4-01.S",
+    "rv64i_m/F/src/fmul_b5-01.S",
+    "rv64i_m/F/src/fmul_b6-01.S",
+    "rv64i_m/F/src/fmul_b7-01.S",
+    "rv64i_m/F/src/fmul_b8-01.S",
+    "rv64i_m/F/src/fmul_b9-01.S",
+    "rv64i_m/F/src/fmv.w.x_b25-01.S",
+    "rv64i_m/F/src/fmv.w.x_b26-01.S",
+    "rv64i_m/F/src/fmv.x.w_b1-01.S",
+    "rv64i_m/F/src/fmv.x.w_b22-01.S",
+    "rv64i_m/F/src/fmv.x.w_b23-01.S",
+    "rv64i_m/F/src/fmv.x.w_b24-01.S",
+    "rv64i_m/F/src/fmv.x.w_b27-01.S",
+    "rv64i_m/F/src/fmv.x.w_b28-01.S",
+    "rv64i_m/F/src/fmv.x.w_b29-01.S",
+    "rv64i_m/F/src/fnmadd_b1-01.S",
+    "rv64i_m/F/src/fnmadd_b14-01.S",
+    // "rv64i_m/F/src/fnmadd_b15-01.S",
+    "rv64i_m/F/src/fnmadd_b16-01.S",
+    "rv64i_m/F/src/fnmadd_b17-01.S",
+    "rv64i_m/F/src/fnmadd_b18-01.S",
+    "rv64i_m/F/src/fnmadd_b2-01.S",
+    "rv64i_m/F/src/fnmadd_b3-01.S",
+    "rv64i_m/F/src/fnmadd_b4-01.S",
+    "rv64i_m/F/src/fnmadd_b5-01.S",
+    "rv64i_m/F/src/fnmadd_b6-01.S",
+    "rv64i_m/F/src/fnmadd_b7-01.S",
+    "rv64i_m/F/src/fnmadd_b8-01.S",
+    "rv64i_m/F/src/fnmsub_b1-01.S",
+    "rv64i_m/F/src/fnmsub_b14-01.S",
+    // "rv64i_m/F/src/fnmsub_b15-01.S",
+    "rv64i_m/F/src/fnmsub_b16-01.S",
+    "rv64i_m/F/src/fnmsub_b17-01.S",
+    "rv64i_m/F/src/fnmsub_b18-01.S",
+    "rv64i_m/F/src/fnmsub_b2-01.S",
+    "rv64i_m/F/src/fnmsub_b3-01.S",
+    "rv64i_m/F/src/fnmsub_b4-01.S",
+    "rv64i_m/F/src/fnmsub_b5-01.S",
+    "rv64i_m/F/src/fnmsub_b6-01.S",
+    "rv64i_m/F/src/fnmsub_b7-01.S",
+    "rv64i_m/F/src/fnmsub_b8-01.S",
+    "rv64i_m/F/src/fsgnj_b1-01.S",
+    "rv64i_m/F/src/fsgnjn_b1-01.S",
+    "rv64i_m/F/src/fsgnjx_b1-01.S",
+    "rv64i_m/F/src/fsqrt_b1-01.S",
+    "rv64i_m/F/src/fsqrt_b20-01.S",
+    "rv64i_m/F/src/fsqrt_b2-01.S",
+    "rv64i_m/F/src/fsqrt_b3-01.S",
+    "rv64i_m/F/src/fsqrt_b4-01.S",
+    "rv64i_m/F/src/fsqrt_b5-01.S",
+    "rv64i_m/F/src/fsqrt_b7-01.S",
+    "rv64i_m/F/src/fsqrt_b8-01.S",
+    "rv64i_m/F/src/fsqrt_b9-01.S",
+    "rv64i_m/F/src/fsub_b10-01.S",
+    "rv64i_m/F/src/fsub_b1-01.S",
+    "rv64i_m/F/src/fsub_b11-01.S",
+    "rv64i_m/F/src/fsub_b12-01.S",
+    "rv64i_m/F/src/fsub_b13-01.S",
+    "rv64i_m/F/src/fsub_b2-01.S",
+    "rv64i_m/F/src/fsub_b3-01.S",
+    "rv64i_m/F/src/fsub_b4-01.S",
+    "rv64i_m/F/src/fsub_b5-01.S",
+    "rv64i_m/F/src/fsub_b7-01.S",
+    "rv64i_m/F/src/fsub_b8-01.S",
+    "rv64i_m/F/src/fsw-align-01.S"
+    };
+
+
+  string arch64d[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/D/src/fadd.d_b10-01.S",
+    "rv64i_m/D/src/fadd.d_b1-01.S",
+    "rv64i_m/D/src/fadd.d_b11-01.S",
+    "rv64i_m/D/src/fadd.d_b12-01.S",
+    "rv64i_m/D/src/fadd.d_b13-01.S",
+    "rv64i_m/D/src/fadd.d_b2-01.S",
+    "rv64i_m/D/src/fadd.d_b3-01.S",
+    "rv64i_m/D/src/fadd.d_b4-01.S",
+    "rv64i_m/D/src/fadd.d_b5-01.S",
+    "rv64i_m/D/src/fadd.d_b7-01.S",
+    "rv64i_m/D/src/fadd.d_b8-01.S",
+    "rv64i_m/D/src/fclass.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.d.l_b25-01.S",
+    "rv64i_m/D/src/fcvt.d.l_b26-01.S",
+    "rv64i_m/D/src/fcvt.d.lu_b25-01.S",
+    "rv64i_m/D/src/fcvt.d.lu_b26-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b1-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b22-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b23-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b24-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b27-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b28-01.S",
+    "rv64i_m/D/src/fcvt.d.s_b29-01.S",
+    "rv64i_m/D/src/fcvt.d.w_b25-01.S",
+    "rv64i_m/D/src/fcvt.d.w_b26-01.S",
+    "rv64i_m/D/src/fcvt.d.wu_b25-01.S",
+    "rv64i_m/D/src/fcvt.d.wu_b26-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b22-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b23-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b24-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b27-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b28-01.S",
+    "rv64i_m/D/src/fcvt.l.d_b29-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b22-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b23-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b24-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b27-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b28-01.S",
+    "rv64i_m/D/src/fcvt.lu.d_b29-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b22-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b23-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b24-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b27-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b28-01.S",
+    "rv64i_m/D/src/fcvt.s.d_b29-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b22-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b23-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b24-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b27-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b28-01.S",
+    "rv64i_m/D/src/fcvt.w.d_b29-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b1-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b22-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b23-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b24-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b27-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b28-01.S",
+    "rv64i_m/D/src/fcvt.wu.d_b29-01.S",
+    "rv64i_m/D/src/fdiv.d_b1-01.S",
+    "rv64i_m/D/src/fdiv.d_b20-01.S",
+    "rv64i_m/D/src/fdiv.d_b2-01.S",
+    "rv64i_m/D/src/fdiv.d_b21-01.S",
+    "rv64i_m/D/src/fdiv.d_b3-01.S",
+    "rv64i_m/D/src/fdiv.d_b4-01.S",
+    "rv64i_m/D/src/fdiv.d_b5-01.S",
+    "rv64i_m/D/src/fdiv.d_b6-01.S",
+    "rv64i_m/D/src/fdiv.d_b7-01.S",
+    "rv64i_m/D/src/fdiv.d_b8-01.S",
+    "rv64i_m/D/src/fdiv.d_b9-01.S",
+    "rv64i_m/D/src/feq.d_b1-01.S",
+    "rv64i_m/D/src/feq.d_b19-01.S",
+    "rv64i_m/D/src/fle.d_b1-01.S",
+    "rv64i_m/D/src/fle.d_b19-01.S",
+    "rv64i_m/D/src/flt.d_b1-01.S",
+    "rv64i_m/D/src/flt.d_b19-01.S",
+    "rv64i_m/D/src/fld-align-01.S", 
+    "rv64i_m/D/src/fsd-align-01.S", 
+    "rv64i_m/D/src/fmadd.d_b14-01.S",
+    "rv64i_m/D/src/fmadd.d_b16-01.S",
+    "rv64i_m/D/src/fmadd.d_b17-01.S",
+    "rv64i_m/D/src/fmadd.d_b18-01.S",
+    "rv64i_m/D/src/fmadd.d_b2-01.S",
+    "rv64i_m/D/src/fmadd.d_b3-01.S",
+    "rv64i_m/D/src/fmadd.d_b4-01.S",
+    "rv64i_m/D/src/fmadd.d_b5-01.S",
+    "rv64i_m/D/src/fmadd.d_b6-01.S",
+    "rv64i_m/D/src/fmadd.d_b7-01.S",
+    "rv64i_m/D/src/fmadd.d_b8-01.S",
+    "rv64i_m/D/src/fmax.d_b1-01.S",
+    "rv64i_m/D/src/fmax.d_b19-01.S",
+    "rv64i_m/D/src/fmin.d_b1-01.S",
+    "rv64i_m/D/src/fmin.d_b19-01.S",
+    "rv64i_m/D/src/fmsub.d_b14-01.S",
+    "rv64i_m/D/src/fmsub.d_b16-01.S",
+    "rv64i_m/D/src/fmsub.d_b17-01.S",
+    "rv64i_m/D/src/fmsub.d_b18-01.S",
+    "rv64i_m/D/src/fmsub.d_b2-01.S",
+    "rv64i_m/D/src/fmsub.d_b3-01.S",
+    "rv64i_m/D/src/fmsub.d_b4-01.S",
+    "rv64i_m/D/src/fmsub.d_b5-01.S",
+    "rv64i_m/D/src/fmsub.d_b6-01.S",
+    "rv64i_m/D/src/fmsub.d_b7-01.S",
+    "rv64i_m/D/src/fmsub.d_b8-01.S",
+    "rv64i_m/D/src/fmul.d_b1-01.S",
+    "rv64i_m/D/src/fmul.d_b2-01.S",
+    "rv64i_m/D/src/fmul.d_b3-01.S",
+    "rv64i_m/D/src/fmul.d_b4-01.S",
+    "rv64i_m/D/src/fmul.d_b5-01.S",
+    "rv64i_m/D/src/fmul.d_b6-01.S",
+    "rv64i_m/D/src/fmul.d_b7-01.S",
+    "rv64i_m/D/src/fmul.d_b8-01.S",
+    "rv64i_m/D/src/fmul.d_b9-01.S",
+    "rv64i_m/D/src/fmv.d.x_b25-01.S",
+    "rv64i_m/D/src/fmv.d.x_b26-01.S",
+    "rv64i_m/D/src/fmv.x.d_b1-01.S",
+    "rv64i_m/D/src/fmv.x.d_b22-01.S",
+    "rv64i_m/D/src/fmv.x.d_b23-01.S",
+    "rv64i_m/D/src/fmv.x.d_b24-01.S",
+    "rv64i_m/D/src/fmv.x.d_b27-01.S",
+    "rv64i_m/D/src/fmv.x.d_b28-01.S",
+    "rv64i_m/D/src/fmv.x.d_b29-01.S",
+    "rv64i_m/D/src/fnmadd.d_b14-01.S",
+    "rv64i_m/D/src/fnmadd.d_b16-01.S",
+    "rv64i_m/D/src/fnmadd.d_b17-01.S",
+    "rv64i_m/D/src/fnmadd.d_b18-01.S",
+    "rv64i_m/D/src/fnmadd.d_b2-01.S",
+    "rv64i_m/D/src/fnmadd.d_b3-01.S",
+    "rv64i_m/D/src/fnmadd.d_b4-01.S",
+    "rv64i_m/D/src/fnmadd.d_b5-01.S",
+    "rv64i_m/D/src/fnmadd.d_b6-01.S",
+    "rv64i_m/D/src/fnmadd.d_b7-01.S",
+    "rv64i_m/D/src/fnmadd.d_b8-01.S",
+    "rv64i_m/D/src/fnmsub.d_b14-01.S",
+    "rv64i_m/D/src/fnmsub.d_b16-01.S",
+    "rv64i_m/D/src/fnmsub.d_b17-01.S",
+    "rv64i_m/D/src/fnmsub.d_b18-01.S",
+    "rv64i_m/D/src/fnmsub.d_b2-01.S",
+    "rv64i_m/D/src/fnmsub.d_b3-01.S",
+    "rv64i_m/D/src/fnmsub.d_b4-01.S",
+    "rv64i_m/D/src/fnmsub.d_b5-01.S",
+    "rv64i_m/D/src/fnmsub.d_b6-01.S",
+    "rv64i_m/D/src/fnmsub.d_b7-01.S",
+    "rv64i_m/D/src/fnmsub.d_b8-01.S",
+    "rv64i_m/D/src/fsgnj.d_b1-01.S",
+    "rv64i_m/D/src/fsgnjn.d_b1-01.S",
+    "rv64i_m/D/src/fsgnjx.d_b1-01.S",
+    "rv64i_m/D/src/fsqrt.d_b1-01.S",
+    "rv64i_m/D/src/fsqrt.d_b20-01.S",
+    "rv64i_m/D/src/fsqrt.d_b2-01.S",
+    "rv64i_m/D/src/fsqrt.d_b3-01.S",
+    "rv64i_m/D/src/fsqrt.d_b4-01.S",
+    "rv64i_m/D/src/fsqrt.d_b5-01.S",
+    "rv64i_m/D/src/fsqrt.d_b7-01.S",
+    "rv64i_m/D/src/fsqrt.d_b8-01.S",
+    "rv64i_m/D/src/fsqrt.d_b9-01.S",
+    "rv64i_m/D/src/fssub.d_b10-01.S",
+    "rv64i_m/D/src/fssub.d_b1-01.S",
+    "rv64i_m/D/src/fssub.d_b11-01.S",
+    "rv64i_m/D/src/fssub.d_b12-01.S",
+    "rv64i_m/D/src/fssub.d_b13-01.S",
+    "rv64i_m/D/src/fssub.d_b2-01.S",
+    "rv64i_m/D/src/fssub.d_b3-01.S",
+    "rv64i_m/D/src/fssub.d_b4-01.S",
+    "rv64i_m/D/src/fssub.d_b5-01.S",
+    "rv64i_m/D/src/fssub.d_b7-01.S",
+    "rv64i_m/D/src/fssub.d_b8-01.S"
+};
+
+    string arch32priv[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/privilege/src/ebreak.S",
+    "rv32i_m/privilege/src/ecall.S",
+//    "rv32i_m/privilege/src/misalign1-jalr-01.S",
+    "rv32i_m/privilege/src/misalign2-jalr-01.S",
+    "rv32i_m/privilege/src/misalign-beq-01.S",
+    "rv32i_m/privilege/src/misalign-bge-01.S",
+    "rv32i_m/privilege/src/misalign-bgeu-01.S",
+    "rv32i_m/privilege/src/misalign-blt-01.S",
+    "rv32i_m/privilege/src/misalign-bltu-01.S",
+    "rv32i_m/privilege/src/misalign-bne-01.S",
+    "rv32i_m/privilege/src/misalign-jal-01.S",
+    "rv32i_m/privilege/src/misalign-lh-01.S",
+    "rv32i_m/privilege/src/misalign-lhu-01.S",
+    "rv32i_m/privilege/src/misalign-lw-01.S",
+    "rv32i_m/privilege/src/misalign-sh-01.S",
+    "rv32i_m/privilege/src/misalign-sw-01.S"
+    };
+
+  string arch32m[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/M/src/div-01.S",
+    "rv32i_m/M/src/divu-01.S",
+    "rv32i_m/M/src/rem-01.S",
+    "rv32i_m/M/src/remu-01.S",
+    "rv32i_m/M/src/mul-01.S",
+    "rv32i_m/M/src/mulh-01.S",
+    "rv32i_m/M/src/mulhsu-01.S",
+    "rv32i_m/M/src/mulhu-01.S"
+   };
+
+  string arch32f[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/F/src/fdiv_b20-01.S",
+    "rv32i_m/F/src/fadd_b10-01.S",
+    "rv32i_m/F/src/fadd_b1-01.S",
+    "rv32i_m/F/src/fadd_b11-01.S",
+    "rv32i_m/F/src/fadd_b12-01.S",
+    "rv32i_m/F/src/fadd_b13-01.S",
+    "rv32i_m/F/src/fadd_b2-01.S",
+    "rv32i_m/F/src/fadd_b3-01.S",
+    "rv32i_m/F/src/fadd_b4-01.S",
+    "rv32i_m/F/src/fadd_b5-01.S",
+    "rv32i_m/F/src/fadd_b7-01.S",
+    "rv32i_m/F/src/fadd_b8-01.S",
+    "rv32i_m/F/src/fclass_b1-01.S",
+    "rv32i_m/F/src/fcvt.s.w_b25-01.S",
+    "rv32i_m/F/src/fcvt.s.w_b26-01.S",
+    "rv32i_m/F/src/fcvt.s.wu_b25-01.S",
+    "rv32i_m/F/src/fcvt.s.wu_b26-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b1-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b22-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b23-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b24-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b27-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b28-01.S",
+    "rv32i_m/F/src/fcvt.w.s_b29-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b1-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b22-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b23-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b24-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b27-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b28-01.S",
+    "rv32i_m/F/src/fcvt.wu.s_b29-01.S",
+    "rv32i_m/F/src/fdiv_b20-01.S",
+    "rv32i_m/F/src/fdiv_b1-01.S",
+    "rv32i_m/F/src/fdiv_b2-01.S",
+    "rv32i_m/F/src/fdiv_b21-01.S",
+    "rv32i_m/F/src/fdiv_b3-01.S",
+    "rv32i_m/F/src/fdiv_b4-01.S",
+    "rv32i_m/F/src/fdiv_b5-01.S",
+    "rv32i_m/F/src/fdiv_b6-01.S",
+    "rv32i_m/F/src/fdiv_b7-01.S",
+    "rv32i_m/F/src/fdiv_b8-01.S",
+    "rv32i_m/F/src/fdiv_b9-01.S",
+    "rv32i_m/F/src/feq_b1-01.S",
+    "rv32i_m/F/src/feq_b19-01.S",
+    "rv32i_m/F/src/fle_b1-01.S",
+    "rv32i_m/F/src/fle_b19-01.S",
+    "rv32i_m/F/src/flt_b1-01.S",
+    "rv32i_m/F/src/flt_b19-01.S",
+    "rv32i_m/F/src/flw-align-01.S",
+    "rv32i_m/F/src/fmadd_b1-01.S",
+    "rv32i_m/F/src/fmadd_b14-01.S",
+    "rv32i_m/F/src/fmadd_b15-01.S",
+    "rv32i_m/F/src/fmadd_b16-01.S",
+    "rv32i_m/F/src/fmadd_b17-01.S",
+    "rv32i_m/F/src/fmadd_b18-01.S",
+    "rv32i_m/F/src/fmadd_b2-01.S",
+    "rv32i_m/F/src/fmadd_b3-01.S",
+    "rv32i_m/F/src/fmadd_b4-01.S",
+    "rv32i_m/F/src/fmadd_b5-01.S",
+    "rv32i_m/F/src/fmadd_b6-01.S",
+    "rv32i_m/F/src/fmadd_b7-01.S",
+    "rv32i_m/F/src/fmadd_b8-01.S",
+    "rv32i_m/F/src/fmax_b1-01.S",
+    "rv32i_m/F/src/fmax_b19-01.S",
+    "rv32i_m/F/src/fmin_b1-01.S",
+    "rv32i_m/F/src/fmin_b19-01.S",
+    "rv32i_m/F/src/fmsub_b1-01.S",
+    "rv32i_m/F/src/fmsub_b14-01.S",
+    //"rv32i_m/F/src/fmsub_b15-01.S",
+    "rv32i_m/F/src/fmsub_b16-01.S",
+    "rv32i_m/F/src/fmsub_b17-01.S",
+    "rv32i_m/F/src/fmsub_b18-01.S",
+    "rv32i_m/F/src/fmsub_b2-01.S",
+    "rv32i_m/F/src/fmsub_b3-01.S",
+    "rv32i_m/F/src/fmsub_b4-01.S",
+    "rv32i_m/F/src/fmsub_b5-01.S",
+    "rv32i_m/F/src/fmsub_b6-01.S",
+    "rv32i_m/F/src/fmsub_b7-01.S",
+    "rv32i_m/F/src/fmsub_b8-01.S",
+    "rv32i_m/F/src/fmul_b1-01.S",
+    "rv32i_m/F/src/fmul_b2-01.S",
+    "rv32i_m/F/src/fmul_b3-01.S",
+    "rv32i_m/F/src/fmul_b4-01.S",
+    "rv32i_m/F/src/fmul_b5-01.S",
+    "rv32i_m/F/src/fmul_b6-01.S",
+    "rv32i_m/F/src/fmul_b7-01.S",
+    "rv32i_m/F/src/fmul_b8-01.S",
+    "rv32i_m/F/src/fmul_b9-01.S",
+    "rv32i_m/F/src/fmv.w.x_b25-01.S",
+    "rv32i_m/F/src/fmv.w.x_b26-01.S",
+    "rv32i_m/F/src/fmv.x.w_b1-01.S",
+    "rv32i_m/F/src/fmv.x.w_b22-01.S",
+    "rv32i_m/F/src/fmv.x.w_b23-01.S",
+    "rv32i_m/F/src/fmv.x.w_b24-01.S",
+    "rv32i_m/F/src/fmv.x.w_b27-01.S",
+    "rv32i_m/F/src/fmv.x.w_b28-01.S",
+    "rv32i_m/F/src/fmv.x.w_b29-01.S",
+    "rv32i_m/F/src/fnmadd_b1-01.S",
+    "rv32i_m/F/src/fnmadd_b14-01.S",
+    // "rv32i_m/F/src/fnmadd_b15-01.S",
+    "rv32i_m/F/src/fnmadd_b16-01.S",
+    "rv32i_m/F/src/fnmadd_b17-01.S",
+    "rv32i_m/F/src/fnmadd_b18-01.S",
+    "rv32i_m/F/src/fnmadd_b2-01.S",
+    "rv32i_m/F/src/fnmadd_b3-01.S",
+    "rv32i_m/F/src/fnmadd_b4-01.S",
+    "rv32i_m/F/src/fnmadd_b5-01.S",
+    "rv32i_m/F/src/fnmadd_b6-01.S",
+    "rv32i_m/F/src/fnmadd_b7-01.S",
+    "rv32i_m/F/src/fnmadd_b8-01.S",
+    "rv32i_m/F/src/fnmsub_b1-01.S",
+    "rv32i_m/F/src/fnmsub_b14-01.S",
+    // "rv32i_m/F/src/fnmsub_b15-01.S",
+    "rv32i_m/F/src/fnmsub_b16-01.S",
+    "rv32i_m/F/src/fnmsub_b17-01.S",
+    "rv32i_m/F/src/fnmsub_b18-01.S",
+    "rv32i_m/F/src/fnmsub_b2-01.S",
+    "rv32i_m/F/src/fnmsub_b3-01.S",
+    "rv32i_m/F/src/fnmsub_b4-01.S",
+    "rv32i_m/F/src/fnmsub_b5-01.S",
+    "rv32i_m/F/src/fnmsub_b6-01.S",
+    "rv32i_m/F/src/fnmsub_b7-01.S",
+    "rv32i_m/F/src/fnmsub_b8-01.S",
+    "rv32i_m/F/src/fsgnj_b1-01.S",
+    "rv32i_m/F/src/fsgnjn_b1-01.S",
+    "rv32i_m/F/src/fsgnjx_b1-01.S",
+    "rv32i_m/F/src/fsqrt_b1-01.S",
+    "rv32i_m/F/src/fsqrt_b20-01.S",
+    "rv32i_m/F/src/fsqrt_b2-01.S",
+    "rv32i_m/F/src/fsqrt_b3-01.S",
+    "rv32i_m/F/src/fsqrt_b4-01.S",
+    "rv32i_m/F/src/fsqrt_b5-01.S",
+    "rv32i_m/F/src/fsqrt_b7-01.S",
+    "rv32i_m/F/src/fsqrt_b8-01.S",
+    "rv32i_m/F/src/fsqrt_b9-01.S",
+    "rv32i_m/F/src/fsub_b10-01.S",
+    "rv32i_m/F/src/fsub_b1-01.S",
+    "rv32i_m/F/src/fsub_b11-01.S",
+    "rv32i_m/F/src/fsub_b12-01.S",
+    "rv32i_m/F/src/fsub_b13-01.S",
+    "rv32i_m/F/src/fsub_b2-01.S",
+    "rv32i_m/F/src/fsub_b3-01.S",
+    "rv32i_m/F/src/fsub_b4-01.S",
+    "rv32i_m/F/src/fsub_b5-01.S",
+    "rv32i_m/F/src/fsub_b7-01.S",
+    "rv32i_m/F/src/fsub_b8-01.S",
+    "rv32i_m/F/src/fsw-align-01.S"
+    };
+
+  string arch32d[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/D/src/fadd.d_b10-01.S",
+    "rv32i_m/D/src/fadd.d_b1-01.S",
+    "rv32i_m/D/src/fadd.d_b11-01.S",
+    "rv32i_m/D/src/fadd.d_b12-01.S",
+    "rv32i_m/D/src/fadd.d_b13-01.S",
+    "rv32i_m/D/src/fadd.d_b2-01.S",
+    "rv32i_m/D/src/fadd.d_b3-01.S",
+    "rv32i_m/D/src/fadd.d_b4-01.S",
+    "rv32i_m/D/src/fadd.d_b5-01.S",
+    "rv32i_m/D/src/fadd.d_b7-01.S",
+    "rv32i_m/D/src/fadd.d_b8-01.S",
+    "rv32i_m/D/src/fclass.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b1-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b22-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b23-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b24-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b27-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b28-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b29-01.S",
+    "rv32i_m/D/src/fcvt.d.w_b25-01.S",
+    "rv32i_m/D/src/fcvt.d.w_b26-01.S",
+    "rv32i_m/D/src/fcvt.d.wu_b25-01.S",
+    "rv32i_m/D/src/fcvt.d.wu_b26-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b29-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b29-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b29-01.S",
+    "rv32i_m/D/src/fdiv.d_b1-01.S",
+    "rv32i_m/D/src/fdiv.d_b20-01.S",
+    "rv32i_m/D/src/fdiv.d_b2-01.S",
+    "rv32i_m/D/src/fdiv.d_b21-01.S",
+    "rv32i_m/D/src/fdiv.d_b3-01.S",
+    "rv32i_m/D/src/fdiv.d_b4-01.S",
+    "rv32i_m/D/src/fdiv.d_b5-01.S",
+    "rv32i_m/D/src/fdiv.d_b6-01.S",
+    "rv32i_m/D/src/fdiv.d_b7-01.S",
+    "rv32i_m/D/src/fdiv.d_b8-01.S",
+    "rv32i_m/D/src/fdiv.d_b9-01.S",
+    "rv32i_m/D/src/feq.d_b1-01.S",
+    "rv32i_m/D/src/feq.d_b19-01.S",
+    "rv32i_m/D/src/fle.d_b1-01.S",
+    "rv32i_m/D/src/fle.d_b19-01.S",
+    "rv32i_m/D/src/flt.d_b1-01.S",
+    "rv32i_m/D/src/flt.d_b19-01.S",
+    "rv32i_m/D/src/fld-align-01.S", 
+    "rv32i_m/D/src/fsd-align-01.S", 
+    "rv32i_m/D/src/fmadd.d_b14-01.S",
+    "rv32i_m/D/src/fmadd.d_b16-01.S",
+    "rv32i_m/D/src/fmadd.d_b17-01.S",
+    "rv32i_m/D/src/fmadd.d_b18-01.S",
+    "rv32i_m/D/src/fmadd.d_b2-01.S",
+    "rv32i_m/D/src/fmadd.d_b3-01.S",
+    "rv32i_m/D/src/fmadd.d_b4-01.S",
+    "rv32i_m/D/src/fmadd.d_b5-01.S",
+    "rv32i_m/D/src/fmadd.d_b6-01.S",
+    "rv32i_m/D/src/fmadd.d_b7-01.S",
+    "rv32i_m/D/src/fmadd.d_b8-01.S",
+    "rv32i_m/D/src/fmax.d_b1-01.S",
+    "rv32i_m/D/src/fmax.d_b19-01.S",
+    "rv32i_m/D/src/fmin.d_b1-01.S",
+    "rv32i_m/D/src/fmin.d_b19-01.S",
+    "rv32i_m/D/src/fmsub.d_b14-01.S",
+    "rv32i_m/D/src/fmsub.d_b16-01.S",
+    "rv32i_m/D/src/fmsub.d_b17-01.S",
+    "rv32i_m/D/src/fmsub.d_b18-01.S",
+    "rv32i_m/D/src/fmsub.d_b2-01.S",
+    "rv32i_m/D/src/fmsub.d_b3-01.S",
+    "rv32i_m/D/src/fmsub.d_b4-01.S",
+    "rv32i_m/D/src/fmsub.d_b5-01.S",
+    "rv32i_m/D/src/fmsub.d_b6-01.S",
+    "rv32i_m/D/src/fmsub.d_b7-01.S",
+    "rv32i_m/D/src/fmsub.d_b8-01.S",
+    "rv32i_m/D/src/fmul.d_b1-01.S",
+    "rv32i_m/D/src/fmul.d_b2-01.S",
+    "rv32i_m/D/src/fmul.d_b3-01.S",
+    "rv32i_m/D/src/fmul.d_b4-01.S",
+    "rv32i_m/D/src/fmul.d_b5-01.S",
+    "rv32i_m/D/src/fmul.d_b6-01.S",
+    "rv32i_m/D/src/fmul.d_b7-01.S",
+    "rv32i_m/D/src/fmul.d_b8-01.S",
+    "rv32i_m/D/src/fmul.d_b9-01.S",
+    "rv32i_m/D/src/fnmadd.d_b14-01.S",
+    "rv32i_m/D/src/fnmadd.d_b16-01.S",
+    "rv32i_m/D/src/fnmadd.d_b17-01.S",
+    "rv32i_m/D/src/fnmadd.d_b18-01.S",
+    "rv32i_m/D/src/fnmadd.d_b2-01.S",
+    "rv32i_m/D/src/fnmadd.d_b3-01.S",
+    "rv32i_m/D/src/fnmadd.d_b4-01.S",
+    "rv32i_m/D/src/fnmadd.d_b5-01.S",
+    "rv32i_m/D/src/fnmadd.d_b6-01.S",
+    "rv32i_m/D/src/fnmadd.d_b7-01.S",
+    "rv32i_m/D/src/fnmadd.d_b8-01.S",
+    "rv32i_m/D/src/fnmsub.d_b14-01.S",
+    "rv32i_m/D/src/fnmsub.d_b16-01.S",
+    "rv32i_m/D/src/fnmsub.d_b17-01.S",
+    "rv32i_m/D/src/fnmsub.d_b18-01.S",
+    "rv32i_m/D/src/fnmsub.d_b2-01.S",
+    "rv32i_m/D/src/fnmsub.d_b3-01.S",
+    "rv32i_m/D/src/fnmsub.d_b4-01.S",
+    "rv32i_m/D/src/fnmsub.d_b5-01.S",
+    "rv32i_m/D/src/fnmsub.d_b6-01.S",
+    "rv32i_m/D/src/fnmsub.d_b7-01.S",
+    "rv32i_m/D/src/fnmsub.d_b8-01.S",
+    "rv32i_m/D/src/fsgnj.d_b1-01.S",
+    "rv32i_m/D/src/fsgnjn.d_b1-01.S",
+    "rv32i_m/D/src/fsgnjx.d_b1-01.S",
+    "rv32i_m/D/src/fsqrt.d_b1-01.S",
+    "rv32i_m/D/src/fsqrt.d_b20-01.S",
+    "rv32i_m/D/src/fsqrt.d_b2-01.S",
+    "rv32i_m/D/src/fsqrt.d_b3-01.S",
+    "rv32i_m/D/src/fsqrt.d_b4-01.S",
+    "rv32i_m/D/src/fsqrt.d_b5-01.S",
+    "rv32i_m/D/src/fsqrt.d_b7-01.S",
+    "rv32i_m/D/src/fsqrt.d_b8-01.S",
+    "rv32i_m/D/src/fsqrt.d_b9-01.S",
+    "rv32i_m/D/src/fssub.d_b10-01.S",
+    "rv32i_m/D/src/fssub.d_b1-01.S",
+    "rv32i_m/D/src/fssub.d_b11-01.S",
+    "rv32i_m/D/src/fssub.d_b12-01.S",
+    "rv32i_m/D/src/fssub.d_b13-01.S",
+    "rv32i_m/D/src/fssub.d_b2-01.S",
+    "rv32i_m/D/src/fssub.d_b3-01.S",
+    "rv32i_m/D/src/fssub.d_b4-01.S",
+    "rv32i_m/D/src/fssub.d_b5-01.S",
+    "rv32i_m/D/src/fssub.d_b7-01.S",
+    "rv32i_m/D/src/fssub.d_b8-01.S"
+};
+
+
+  string arch32c[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/C/src/cadd-01.S",
+  "rv32i_m/C/src/caddi-01.S",
+  "rv32i_m/C/src/caddi16sp-01.S",
+  "rv32i_m/C/src/caddi4spn-01.S",
+  "rv32i_m/C/src/cand-01.S",
+  "rv32i_m/C/src/candi-01.S",
+  "rv32i_m/C/src/cbeqz-01.S",
+  "rv32i_m/C/src/cbnez-01.S",
+  "rv32i_m/C/src/cj-01.S",
+  "rv32i_m/C/src/cjal-01.S",
+  "rv32i_m/C/src/cjalr-01.S",
+  "rv32i_m/C/src/cjr-01.S",
+  "rv32i_m/C/src/cli-01.S",
+  "rv32i_m/C/src/clui-01.S",
+  "rv32i_m/C/src/clw-01.S",
+  "rv32i_m/C/src/clwsp-01.S",
+  "rv32i_m/C/src/cmv-01.S",
+  "rv32i_m/C/src/cnop-01.S",
+  "rv32i_m/C/src/cor-01.S",
+  "rv32i_m/C/src/cslli-01.S",
+  "rv32i_m/C/src/csrai-01.S",
+  "rv32i_m/C/src/csrli-01.S",
+  "rv32i_m/C/src/csub-01.S",
+  "rv32i_m/C/src/csw-01.S",
+  "rv32i_m/C/src/cswsp-01.S",
+  "rv32i_m/C/src/cxor-01.S"
+  };
+
+  string arch32cpriv[] = '{
+  //  `RISCVARCHTEST,
+  "rv32i_m/C/src/cebreak-01.S"
+  };      
+
+
+  string arch32i[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/I/src/add-01.S",
+    "rv32i_m/I/src/addi-01.S",
+    "rv32i_m/I/src/and-01.S",
+    "rv32i_m/I/src/andi-01.S",
+    "rv32i_m/I/src/auipc-01.S",
+    "rv32i_m/I/src/beq-01.S",
+    "rv32i_m/I/src/bge-01.S",
+    "rv32i_m/I/src/bgeu-01.S",
+    "rv32i_m/I/src/blt-01.S",
+    "rv32i_m/I/src/bltu-01.S",
+    "rv32i_m/I/src/bne-01.S",
+    "rv32i_m/I/src/fence-01.S",
+    "rv32i_m/I/src/jal-01.S",
+    "rv32i_m/I/src/jalr-01.S",
+    "rv32i_m/I/src/lb-align-01.S",
+    "rv32i_m/I/src/lbu-align-01.S",
+    "rv32i_m/I/src/lh-align-01.S",
+    "rv32i_m/I/src/lhu-align-01.S",
+    "rv32i_m/I/src/lui-01.S",
+    "rv32i_m/I/src/lw-align-01.S",
+    "rv32i_m/I/src/or-01.S",
+    "rv32i_m/I/src/ori-01.S",
+    "rv32i_m/I/src/sb-align-01.S",
+    "rv32i_m/I/src/sh-align-01.S",
+    "rv32i_m/I/src/sll-01.S",
+    "rv32i_m/I/src/slli-01.S",
+    "rv32i_m/I/src/slt-01.S",
+    "rv32i_m/I/src/slti-01.S",
+    "rv32i_m/I/src/sltiu-01.S",
+    "rv32i_m/I/src/sltu-01.S",
+    "rv32i_m/I/src/sra-01.S",
+    "rv32i_m/I/src/srai-01.S",
+    "rv32i_m/I/src/srl-01.S",
+    "rv32i_m/I/src/srli-01.S",
+    "rv32i_m/I/src/sub-01.S",
+    "rv32i_m/I/src/sw-align-01.S",
+    "rv32i_m/I/src/xor-01.S",
+    "rv32i_m/I/src/xori-01.S"
+  };
+
+ string wally64i[] = '{
+    `WALLYTEST,
+    "rv64i_m/I/src/WALLY-ADD.S",
+    "rv64i_m/I/src/WALLY-SLT.S",
+    "rv64i_m/I/src/WALLY-SLTU.S",
+    "rv64i_m/I/src/WALLY-SUB.S",
+    "rv64i_m/I/src/WALLY-XOR.S"
+ };
+
+ 
+ string wally64priv[] = '{
+    `WALLYTEST,
+    "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
+    "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
+    "rv64i_m/privilege/src/WALLY-mie-01.S",
+    "rv64i_m/privilege/src/WALLY-minfo-01.S",
+    "rv64i_m/privilege/src/WALLY-misa-01.S",
+    "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S",
+    "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S",
+    "rv64i_m/privilege/src/WALLY-mtvec-01.S",
+    "rv64i_m/privilege/src/WALLY-pma-01.S",
+    "rv64i_m/privilege/src/WALLY-pmp-01.S",
+    "rv64i_m/privilege/src/WALLY-sie-01.S",
+    "rv64i_m/privilege/src/WALLY-status-mie-01.S",
+    "rv64i_m/privilege/src/WALLY-status-sie-01.S",
+    "rv64i_m/privilege/src/WALLY-status-tw-01.S",
+    "rv64i_m/privilege/src/WALLY-status-tvm-01.S",
+    "rv64i_m/privilege/src/WALLY-stvec-01.S",
+    "rv64i_m/privilege/src/WALLY-trap-01.S",
+    "rv64i_m/privilege/src/WALLY-trap-s-01.S",
+    "rv64i_m/privilege/src/WALLY-trap-sret-01.S",
+    "rv64i_m/privilege/src/WALLY-trap-u-01.S",
+    "rv64i_m/privilege/src/WALLY-wfi-01.S",
+    "rv64i_m/privilege/src/WALLY-endianness-01.S",
+    "rv64i_m/privilege/src/WALLY-status-xlen-01.S",
+    "rv64i_m/privilege/src/WALLY-satp-invalid-01.S"
+ };
+
+ string wally64periph[] = '{
+    `WALLYTEST,
+    "rv64i_m/privilege/src/WALLY-periph-01.S",
+    "rv64i_m/privilege/src/WALLY-clint-01.S",
+    "rv64i_m/privilege/src/WALLY-gpio-01.S",
+    "rv64i_m/privilege/src/WALLY-plic-01.S",
+    "rv64i_m/privilege/src/WALLY-plic-s-01.S",
+    "rv64i_m/privilege/src/WALLY-uart-01.S"
+ };
+
+ string wally32e[] = '{
+    `WALLYTEST,
+    "rv32i_m/I/src/E-add-01.S",
+    "rv32i_m/I/src/E-addi-01.S",
+    "rv32i_m/I/src/E-and-01.S",
+    "rv32i_m/I/src/E-andi-01.S",
+    "rv32i_m/I/src/E-auipc-01.S",
+    "rv32i_m/I/src/E-bge-01.S",
+    "rv32i_m/I/src/E-bgeu-01.S",
+    "rv32i_m/I/src/E-blt-01.S",
+    "rv32i_m/I/src/E-bltu-01.S",
+    "rv32i_m/I/src/E-bne-01.S",
+    "rv32i_m/I/src/E-jal-01.S",
+    "rv32i_m/I/src/E-jalr-01.S",
+    "rv32i_m/I/src/E-lb-align-01.S",
+    "rv32i_m/I/src/E-lbu-align-01.S",
+    "rv32i_m/I/src/E-lh-align-01.S",
+    "rv32i_m/I/src/E-lhu-align-01.S",
+    "rv32i_m/I/src/E-lui-01.S",
+    "rv32i_m/I/src/E-lw-align-01.S",
+    "rv32i_m/I/src/E-or-01.S",
+    "rv32i_m/I/src/E-ori-01.S",
+    "rv32i_m/I/src/E-sb-align-01.S",
+    "rv32i_m/I/src/E-sh-align-01.S",
+    "rv32i_m/I/src/E-sll-01.S",
+    "rv32i_m/I/src/E-slli-01.S",
+    "rv32i_m/I/src/E-slt-01.S",
+    "rv32i_m/I/src/E-slti-01.S",
+    "rv32i_m/I/src/E-sltiu-01.S",
+    "rv32i_m/I/src/E-sltu-01.S",
+    "rv32i_m/I/src/E-sra-01.S",
+    "rv32i_m/I/src/E-srai-01.S",
+    "rv32i_m/I/src/E-srl-01.S",
+    "rv32i_m/I/src/E-srli-01.S",
+    "rv32i_m/I/src/E-sub-01.S",
+    "rv32i_m/I/src/E-sw-align-01.S",
+    "rv32i_m/I/src/E-xor-01.S",
+    "rv32i_m/I/src/E-xori-01.S"
+ };
+
+ string wally32i[] = '{
+    `WALLYTEST,
+    "rv32i_m/I/src/WALLY-ADD.S",
+    "rv32i_m/I/src/WALLY-SLT.S",
+    "rv32i_m/I/src/WALLY-SLTU.S",
+    "rv32i_m/I/src/WALLY-SUB.S",
+    "rv32i_m/I/src/WALLY-XOR.S" 
+ };
+
+
+ string wally32priv[] = '{
+    `WALLYTEST,
+    "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
+    "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
+    "rv32i_m/privilege/src/WALLY-mie-01.S",
+    "rv32i_m/privilege/src/WALLY-minfo-01.S",
+    "rv32i_m/privilege/src/WALLY-misa-01.S",
+    "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
+    "rv32i_m/privilege/src/WALLY-mtvec-01.S",
+    "rv32i_m/privilege/src/WALLY-pma-01.S",
+    "rv32i_m/privilege/src/WALLY-pmp-01.S",
+    "rv32i_m/privilege/src/WALLY-sie-01.S",
+    "rv32i_m/privilege/src/WALLY-status-mie-01.S",
+    "rv32i_m/privilege/src/WALLY-status-sie-01.S",
+    "rv32i_m/privilege/src/WALLY-status-tw-01.S",
+    "rv32i_m/privilege/src/WALLY-status-tvm-01.S",
+    "rv32i_m/privilege/src/WALLY-stvec-01.S",
+    "rv32i_m/privilege/src/WALLY-trap-01.S",
+    "rv32i_m/privilege/src/WALLY-trap-s-01.S",
+    "rv32i_m/privilege/src/WALLY-trap-sret-01.S",
+    "rv32i_m/privilege/src/WALLY-trap-u-01.S",
+    "rv32i_m/privilege/src/WALLY-wfi-01.S",
+    "rv32i_m/privilege/src/WALLY-endianness-01.S",
+    "rv32i_m/privilege/src/WALLY-satp-invalid-01.S"
+ };
+
+ string wally32periph[] = '{
+    `WALLYTEST,
+    "rv32i_m/privilege/src/WALLY-periph-01.S",
+    "rv32i_m/privilege/src/WALLY-gpio-01.S",
+    "rv32i_m/privilege/src/WALLY-clint-01.S",
+    "rv32i_m/privilege/src/WALLY-uart-01.S",
+    "rv32i_m/privilege/src/WALLY-plic-01.S",
+    "rv32i_m/privilege/src/WALLY-plic-s-01.S"
+ };
+
+
+ string wally32d[] = '{
+    `WALLYTEST,
+    "rv32i_m/D/src/WALLY-fld-01.S"
+ };
+
+ string fpga[] = '{
+    `CUSTOM,
+    "NULL"
+ };
+
+ string custom[] = '{
+    `CUSTOM,
+    "simple",
+    "cacheTest"
+ };
+  string testsBP64[] = '{
+    `IMPERASTEST,
+    "rv64BP/simple"
+//    "rv64BP/mmm",
+//    "rv64BP/linpack_bench",
+//    "rv64BP/sieve",
+//    "rv64BP/qsort",
+//    "rv64BP/dhrystone"
+  };
+
+
+ string ahb[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/F/src/fadd_b11-01.S"
+ };
diff --git a/setup.csh b/setup.csh
deleted file mode 100755
index 6b9fa6020..000000000
--- a/setup.csh
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/csh
-
-# setup.csh
-# james.stine@okstate.edu 18 February 2023
-
-echo "Executing Wally setup.csh"
-
-
-# Extend alias which makes extending PATH much easier.
-alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;echo Added \!:2 to \!:1'
-alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1'
-
-# Path to RISC-V Tools
-if ( -d /opt/riscv ) then
-    setenv RISCV /opt/riscv
-else if ( -d ~/riscv ) then
-    setenv RISCV ~/riscv
-else
-    # set the $RISCV directory here and remove the subsequent two lines
-    # setenv RISCV
-    echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.csh to point to your custom \$RISCV directory."
-    exit 1;
-endif
-echo \$RISCV set to "${RISCV}"
-
-# Path to Wally repository
-setenv WALLY $PWD
-echo '$WALLY set to ' ${WALLY}
-# utility functions in Wally repository
-extend PATH $WALLY/bin
-
-# Verilator needs a larger stack to simulate CORE-V Wally
-limit stacksize unlimited
-
-# load site licenses and tool locations
-if ( -e "${RISCV}"/site-setup.csh ) then
-    source $RISCV/site-setup.csh
-else
-    echo "site-setup.csh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it."
-fi
-
-echo "setup done"
diff --git a/setup.sh b/setup.sh
old mode 100644
new mode 100755
index 873d436eb..dc1f418d5
--- a/setup.sh
+++ b/setup.sh
@@ -2,60 +2,42 @@
 
 # setup.sh
 # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
-# Set up tools for cvw
-
-# optionally have .bashrc or .bash_profile source this file with
-#if [ -f ~/cvw/setup.sh ]; then
-#	source ~/cvw/setup.sh
-#fi
-
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# Set up tools for riscv-wally
 
 echo "Executing Wally setup.sh"
 
-# Path to RISC-V Tools
-if [ -d /opt/riscv ]; then
-    export RISCV=/opt/riscv
-elif [ -d ~/riscv ]; then
-    export RISCV=~/riscv
-else
-    # set the $RISCV directory here and remove the subsequent two lines
-    # export RISCV=
-    echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory."
-    exit 1
-fi
-echo \$RISCV set to "${RISCV}"
-
 # Path to Wally repository
-WALLY=$(dirname "${BASH_SOURCE[0]:-$0}")
+WALLY=$(dirname ${BASH_SOURCE[0]:-$0})
 export WALLY=$(cd "$WALLY" && pwd)
-echo \$WALLY set to "${WALLY}"
+echo \$WALLY set to ${WALLY}
+
+# License servers and commercial CAD tool paths
+# Must edit these based on your local environment.  Ask your sysadmin.
+export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu                # Change this to your Siemens license server
+export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
+export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH     # Change this for your path to Questa
+export PATH=/cad/synopsys/SYN/bin:$PATH                             # Change this for your path to Design Compiler
+
+
+# Path to RISC-V Tools
+export RISCV=/opt/riscv   # change this if you installed the tools in a different location
+
+# Tools
+# GCC
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
+export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin      # GCC tools
+# Spike
+export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
+export PATH=$PATH:$RISCV/bin
 # utility functions in Wally repository
-export PATH=$WALLY/bin:$PATH
+export PATH=$WALLY/bin:$PATH    
+# Verilator
+export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
+# ModelSim/Questa (vsim)
+# Note: 2022.1 complains on cache/sram1p1r1w about StoredData cannot be driven by multiple always_ff blocks.  Ues 2021.2 for now
 
-# Setup cvw-arch-verif paths
-if [ -e "${WALLY}"/addins/cvw-arch-verif/setup.sh ]; then
-    source "${WALLY}"/addins/cvw-arch-verif/setup.sh
-else
-    echo "setup.sh not found in \$WALLY/addins/cvw-arch-verif directory. Make sure you cloned the submodules."
-fi
+# Imperas; put this in if you are using it
+#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH  
+#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
 
-# Verilator needs a larger core file size to simulate CORE-V Wally
-ulimit -c 300000
-
-# load site licenses and tool locations
-if [ -e "${RISCV}"/site-setup.sh ]; then
-    source "${RISCV}"/site-setup.sh
-else
-    echo "site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it."
-    exit 1
-fi
-
-if [ ! -e "${WALLY}/.git/hooks/pre-commit" ]; then
-    pushd "${WALLY}" || exit 1
-    echo "Installing pre-commit hooks"
-    pre-commit install
-    popd || exit
-fi
-
-echo "setup done"
+echo "setup done"
\ No newline at end of file
diff --git a/sim/Makefile b/sim/Makefile
deleted file mode 100644
index 0ebea4497..000000000
--- a/sim/Makefile
+++ /dev/null
@@ -1,124 +0,0 @@
-# David_Harris@hmc.edu 15 July 2024
-# Simulation  Makefile for CORE-V-Wally
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-SIM = ${WALLY}/sim
-TESTS = ${WALLY}/tests
-
-.PHONY: all riscoftests wallyriscoftests coveragetests deriv clean wally-riscv-arch-test benchmarks
-
-all: riscoftests coveragetests deriv
-
-wally-riscv-arch-test: wallyriscoftests
-
-riscoftests:
-# 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	$(MAKE) -C ${TESTS}/riscof
-
-wallyriscoftests:
-# 	Builds wally-riscv-arch-test 64 and 32-bit versions
-	$(MAKE) -C ${TESTS}/riscof wally-riscv-arch-test
-
-coveragetests:
-	$(MAKE) -C ${TESTS}/coverage
-
-deriv:
-	derivgen.pl
-
-
-
-.PHONY: QuestaCodeCoverage collect_functcov combine_functcov remove_functcov_artifacts riscvdv riscvdv_functcov
-
-QuestaCodeCoverage:
-	vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log
-#	vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb questa/ucdb/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log
-	vcover report -details questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/priv. > questa/cov/rv64gc_coverage_priv.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/ifu. > questa/cov/rv64gc_coverage_ifu.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/lsu. > questa/cov/rv64gc_coverage_lsu.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/fpu. > questa/cov/rv64gc_coverage_fpu.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/ieu. > questa/cov/rv64gc_coverage_ieu.rpt
-	vcover report questa/ucdb/cov.ucdb -details -instance=/core/hzu. > questa/cov/rv64gc_coverage_hzu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ebu. > questa/cov/rv64gc_uncovered_ebu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/priv. > questa/cov/rv64gc_uncovered_priv.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ifu. > questa/cov/rv64gc_uncovered_ifu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/lsu. > questa/cov/rv64gc_uncovered_lsu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/fpu. > questa/cov/rv64gc_uncovered_fpu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ieu. > questa/cov/rv64gc_uncovered_ieu.rpt
-	vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/hzu. > questa/cov/rv64gc_uncovered_hzu.rpt
-	vcover report -hierarchical questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_hierarchical.rpt
-	vcover report -below 100 -hierarchical questa/ucdb/cov.ucdb > questa/cov/rv64gc_uncovered_hierarchical.rpt
-#	vcover report -below 100 questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage.rpt
-#	vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
-	vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
-
-collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
-
-riscvdv_functcov:
-	mkdir -p ${SIM}/questa/fcov_logs
-	mkdir -p ${SIM}/questa/fcov_ucdb
-	rm -rf ${SIM}/questa/fcov_logs/*
-	rm -rf ${SIM}/questa/fcov_ucdb/*
-	$(MAKE) riscvdv test_name=riscv_arithmetic_basic_test				    >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_amo_test						          	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_ebreak_debug_mode_test			    >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_ebreak_test						          >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_floating_point_arithmetic_test	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_floating_point_mmu_stress_test	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_floating_point_rand_test			  >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_full_interrupt_test			      	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_hint_instr_test					        >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_illegal_instr_test			      	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_invalid_csr_test				       	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_jump_stress_test				      	>> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_loop_test							          >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_machine_mode_rand_test			    >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_mmu_stress_test					        >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_no_fence_test						        >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_non_compressed_instr_test			  >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_pmp_test							          >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_privileged_mode_rand_test			  >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_rand_instr_test					        >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_rand_jump_test					        >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_sfence_exception_test				    >> ${SIM}/questa/fcov.log 2>&1
-	$(MAKE) riscvdv test_name=riscv_unaligned_load_store_test			  >> ${SIM}/questa/fcov.log 2>&1
-
-riscvdv:
-	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile			>> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1
-#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1
-#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1
-#	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1
-
-combine_functcov:
-	mkdir -p ${SIM}/questa/fcov
-	mkdir -p ${SIM}/questa/fcov_logs
-	cd ${SIM}/questa/fcov && rm -rf *
-	cd ${SIM}/questa/fcov_ucdb && rm -rf *
-	wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf --fcov > ${SIM}/questa/fcov_logs/add.log 2>&1
-	wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf --fcov > ${SIM}/questa/fcov_logs/and.log 2>&1
-
-	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf								>> ${SIM}/questa/fcov_logs/add.log 2>&1
-	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf								>> ${SIM}/questa/fcov_logs/add.log 2>&1
-	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf								>> ${SIM}/questa/fcov_logs/add.log 2>&1
-
-	vcover merge ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/*.ucdb -suppress 6854 -64
-	vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb
-	vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log
-	vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log
-#	vcover report ${SIM}/questa/fcov/fcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/fcov/fcov.ucdb.summary.log
-	vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE"  > ${SIM}/questa/fcov/fcov.summary.log
-	grep "Total Coverage By Instance" ${SIM}/questa/fcov/fcov.log
-
-remove_functcov_artifacts:
-	rm -rf ${SIM}/questa/riscv.ucdb ${SIM}/questa/fcov.log ${SIM}/questa/covhtmlreport/ ${SIM}/questa/fcov_logs/ ${SIM}/questa/fcov_ucdb/ ${SIM}/questa/fcov/
-
-benchmarks:
-	$(MAKE) -C ${WALLY}benchmarks/embench build
-	$(MAKE) -C ${WALLY}/benchmarks/embench size
-	$(MAKE) -C ${WALLY}/benchmarks/embench modelsim_build_memfile
-	$(MAKE) -C ${WALLY}/benchmarks/coremark
-
-clean:
-	$(MAKE) clean -C ${TESTS}/riscof
-#   $(MAKE) clean -C ${TESTS}/wally-riscv-arch-test
diff --git a/sim/bp-results/branch-list-global-local.txt b/sim/bp-results/branch-list-global-local.txt
deleted file mode 100644
index 47f1e5171..000000000
--- a/sim/bp-results/branch-list-global-local.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-TODO: These names likely need to be updated
-rv32gc_global6.log global 6
-rv32gc_global8.log global 8
-rv32gc_global10.log global 10
-rv32gc_global12.log global 12
-rv32gc_global14.log global 14
-rv32gc_global16.log global 16
-rv32gc_10local_basic6.log local 10 6
-rv32gc_10local_basic8.log local 10 8
-rv32gc_10local_basic10.log local 10 10
-rv32gc_10local_basic12.log local 10 12
-rv32gc_10local_basic14.log local 10 14
-rv32gc_10local_basic16.log local 10 16
-rv32gc_4local_basic6.log local 4 6
-rv32gc_4local_basic8.log local 4 8
-rv32gc_4local_basic10.log local 4 10
-rv32gc_4local_basic12.log local 4 12
-rv32gc_4local_basic14.log local 4 14
-rv32gc_4local_basic16.log local 4 16
-rv32gc_8local_basic6.log local 8 6
-rv32gc_8local_basic8.log local 8 8
-rv32gc_8local_basic10.log local 8 10
-rv32gc_8local_basic12.log local 8 12
-rv32gc_8local_basic14.log local 8 14
-rv32gc_8local_basic16.log local 8 16
diff --git a/sim/bp-results/branch-list-gshare-local8.txt b/sim/bp-results/branch-list-gshare-local8.txt
deleted file mode 100644
index f6005f351..000000000
--- a/sim/bp-results/branch-list-gshare-local8.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-TODO: These names likely need to be updated
-rv32gc_gshare6.log gshare 6
-rv32gc_gshare8.log gshare 8
-rv32gc_gshare10.log gshare 10
-rv32gc_gshare12.log gshare 12
-rv32gc_gshare14.log gshare 14
-rv32gc_gshare16.log gshare 16
-rv32gc_8local_basic6.log local 8 6
-rv32gc_8local_basic8.log local 8 8
-rv32gc_8local_basic10.log local 8 10
-rv32gc_8local_basic12.log local 8 12
-rv32gc_8local_basic14.log local 8 14
-rv32gc_8local_basic16.log local 8 16
diff --git a/sim/bp-results/branch-list.txt b/sim/bp-results/branch-list.txt
deleted file mode 100644
index c2b8c10eb..000000000
--- a/sim/bp-results/branch-list.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-bpred_GSHARE_6_16_10_1_rv32gc_embench.log gshare 6
-bpred_GSHARE_8_16_10_1_rv32gc_embench.log gshare 8
-bpred_GSHARE_10_16_10_1_rv32gc_embench.log gshare 10
-bpred_GSHARE_12_16_10_1_rv32gc_embench.log gshare 12
-bpred_GSHARE_14_16_10_1_rv32gc_embench.log gshare 14
-bpred_GSHARE_16_16_10_1_rv32gc_embench.log gshare 16
-bpred_TWOBIT_6_16_10_1_rv32gc_embench.log twobit 6
-bpred_TWOBIT_8_16_10_1_rv32gc_embench.log twobit 8
-bpred_TWOBIT_10_16_10_1_rv32gc_embench.log twobit 10
-bpred_TWOBIT_12_16_10_1_rv32gc_embench.log twobit 12
-bpred_TWOBIT_14_16_10_1_rv32gc_embench.log twobit 14
-bpred_TWOBIT_16_16_10_1_rv32gc_embench.log twobit 16
diff --git a/sim/bp-results/btb-list.txt b/sim/bp-results/btb-list.txt
deleted file mode 100644
index 3eda946a1..000000000
--- a/sim/bp-results/btb-list.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-bpred_GSHARE_10_16_6_0_rv32gc_embench.log btb 6
-bpred_GSHARE_10_16_8_0_rv32gc_embench.log btb 8
-bpred_GSHARE_10_16_10_0_rv32gc_embench.log btb 10
-bpred_GSHARE_10_16_12_0_rv32gc_embench.log btb 12
-bpred_GSHARE_10_16_14_0_rv32gc_embench.log btb 14
-bpred_GSHARE_10_16_16_0_rv32gc_embench.log btb 16
diff --git a/sim/bp-results/class-list.txt b/sim/bp-results/class-list.txt
deleted file mode 100644
index b4ae6c3d9..000000000
--- a/sim/bp-results/class-list.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-bpred_GSHARE_10_16_6_1_rv32gc_embench.log btb 6
-bpred_GSHARE_10_16_8_1_rv32gc_embench.log btb 8
-bpred_GSHARE_10_16_10_1_rv32gc_embench.log btb 10
-bpred_GSHARE_10_16_12_1_rv32gc_embench.log btb 12
-bpred_GSHARE_10_16_14_1_rv32gc_embench.log btb 14
-bpred_GSHARE_10_16_16_1_rv32gc_embench.log btb 16
diff --git a/sim/bp-results/ras-list.txt b/sim/bp-results/ras-list.txt
deleted file mode 100644
index 9a3e39d7d..000000000
--- a/sim/bp-results/ras-list.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-bpred_GSHARE_10_3_10_0_rv32gc_embench.log ras 3
-bpred_GSHARE_10_4_10_0_rv32gc_embench.log ras 4
-bpred_GSHARE_10_6_10_0_rv32gc_embench.log ras 6
-bpred_GSHARE_10_10_10_0_rv32gc_embench.log ras 10
-bpred_GSHARE_10_16_10_0_rv32gc_embench.log ras 16
diff --git a/sim/imperas-verbose.ic b/sim/imperas-verbose.ic
deleted file mode 100644
index 7cd53e38e..000000000
--- a/sim/imperas-verbose.ic
+++ /dev/null
@@ -1,3 +0,0 @@
-# Add Imperas simulator application instruction tracing
---verbose --trace --tracechange --traceshowicount --tracemode --tracemem XSL --monitornetschange # --traceafter 300000000
---override cpu/debugflags=6 --override cpu/verbose=1
diff --git a/sim/questa/GetLineNum.do b/sim/questa/GetLineNum.do
deleted file mode 100644
index 4d38d9121..000000000
--- a/sim/questa/GetLineNum.do
+++ /dev/null
@@ -1,18 +0,0 @@
-# Alec Vercruysse
-# 2023-04-12
-# Note that the target string is regex, and needs to be double-escaped.
-# e.g. to match a (, you need \\(.
-proc GetLineNum {fname target} {
-    set f [open $fname]
-    set linectr 1
-    while {[gets $f line] != -1} {
-         if {[regexp $target $line]} {
-             close $f
-             return $linectr
-         }
-         incr linectr
-     }
-    close $f
-    return -code error \
-         "target string not found"
-}
diff --git a/sim/questa/coverage-exclusions-rv64gc.do b/sim/questa/coverage-exclusions-rv64gc.do
deleted file mode 100644
index 159353660..000000000
--- a/sim/questa/coverage-exclusions-rv64gc.do
+++ /dev/null
@@ -1,470 +0,0 @@
-#///////////////////////////////////////////
-#// coverage-exclusions-rv64gc.do
-#//
-#// Written: David_Harris@hmc.edu 19 March 2023
-#//
-#// Purpose: Set of exclusions from coverage for rv64gc configuration
-#//          For example, signals hardwired to 0 should not be checked for toggle coverage
-#//
-#// A component of the CORE-V-WALLY configurable RISC-V project.
-#// https://github.com/openhwgroup/cvw
-#// 
-#// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-#//
-#// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#//
-#// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-#// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-#// may obtain a copy of the License at
-#//
-#// https://solderpad.org/licenses/SHL-2.1/
-#//
-#// Unless required by applicable law or agreed to in writing, any work distributed under the 
-#// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-#// either express or implied. See the License for the specific language governing permissions 
-#// and limitations under the License.
-#////////////////////////////////////////////////////////////////////////////////////////////////
-
-# This file should be a last resort.  It's preferable to put 
-# // coverage off 
-# statements inline with the code whenever possible.
-
-set WALLY $::env(WALLY)
-set SRC ${WALLY}/src
-
-# a hack to describe coverage exclusions without hardcoding linenumbers:
-do GetLineNum.do
-
-# LZA (i<64) statement confuses coverage tool 
-# DH 4/22/23: Exclude all LZAs
-coverage exclude -srcfile lzc.sv 
-
-#################
-# FPU Exclusions
-#################
-# DH 4/22/23: FDIVSQRT can't go directly from done to busy again
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
-# DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy.  The flush is caused by a trap or return,
-# which won't happen while the divider is busy. 
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
-# All Memory-stage stalls have resolved by time fdivsqrt finishes regular operation in this configuration, so can't test StallM
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1
-# Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia
-coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15 
-coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
-# Convert int to fp will never underflow
-coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
-# without Q support, the FMT field is guaranteed to be 00, 01, or 10 
-coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv int to fp"] -item 1 3 5
-coverage exclude -scope /dut/core/fpu/fpu/fctrl -linerange [GetLineNum ${SRC}/fpu/fctrl.sv "fmv fp to int"] -item 1 3 5
-# j0 can only be 1 in iteration 0, j1 can only be 1 in iteration 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[0]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign sqrtspecial"] -item e 1 -fecexprrow 4 6
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[1]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign sqrtspecial"] -item e 1 -fecexprrow 6
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign sqrtspecial"] -item e 1 -fecexprrow 1 2 4 6
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign sqrtspecial"] -item e 1 -fecexprrow 1 2 4 6
-# outside of iterations 1 and 0, (j0 | j1) is always 0 so sqrtspecial is always 0
-# need to exclude scenarios where sqrtspecial is 1 for the ternary operators that assign mk2, mk1, mk0, and mkm1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk2"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk1"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk0"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mkm1"] -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk2"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk1"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mk0"]  -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mkm1"] -item b 1
-# outside of iteration 0, j0 is always 0 so the ternary operator that assigns mkj1 cannot be fully covered
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[3]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mkj1"] -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[2]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mkj1"] -item b 1
-coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtiter/iterations[1]/stage/fdivsqrtstage/uslc4 -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv "assign mkj1"] -item b 1
-
-##################
-# Cache Exclusions
-##################
-
-### Exclude D$ states and logic for the I$ instance
-# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
-# Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_ACCESS STATE_FETCH->STATE_ACCESS
-# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
-# I$ does not flush
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxLRU -item b 1
-# exclude branch/condition coverage: LineDirty if statement
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
-# exclude the unreachable logic
-set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache case"]
-set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache case"]
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
-# exclude Atomic Operation logic
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
-# cache write logic
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
-# output signal logic
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
-set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
-set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8 
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
-
-# cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
-# CacheWay Dirty logic. -scope does not accept wildcards.
-set numcacheways 4
-for {set i 0} {$i < $numcacheways} {incr i} {
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
-    # below: flushD can't go high during an icache write b/c of pipeline stall
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
-    # No CMO to clear valid bits of I$
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"] 
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
-    # No dirty ways in read-only I$
-    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
-}
-# I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"] 
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
-coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
-
-## D$ Exclusions.
-# InvalidateCache is I$ only:
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
-set numcacheways 4
-for {set i 0} {$i < $numcacheways} {incr i} {
-    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
-    # InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated
-    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
-
-    # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
-    # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
-    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
-    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
-# Not right; other ways can get flushed and dirtied simultaneously    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
-}
-# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_ACCESS STATE_FLUSH->STATE_ACCESS STATE_WRITE_LINE->STATE_ACCESS STATE_FLUSH_WRITEBACK->STATE_ACCESS 
-
-####################
-# Unused / illegal peripheral accesses
-####################
-
-# Excluding peripherals as sources of instructions for the ifu
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/dtimdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec
-
-# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
-
-# Excluding so far un-used instruction sources for the ifu
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec
-
-# The following peripherals are always supported
-set line [GetLineNum ${SRC}/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3
-
-#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
-set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
-set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
-
-# set line [GetLineNum ${SRC}/mmu/adrdec.sv "& Supported"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec
-
-# No DTIM or IROM
-coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
-coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
-
-####################
-# Unused access types due to sharing IFU and LSU logic
-####################
-
-## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC ="]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
-set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
-set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "PMAInstrAccessFaultF    \\|"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
-set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
-set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3 
-
-
-## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM & ~WriteAccessM & PMAAccessFault"]
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line
-set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
-set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AtomicMisalignedCausesAccessFaultM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
-set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
-set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoPageFaultM \="] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
-set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
-set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
-set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
-set line [GetLineNum ${SRC}/mmu/mmu.sv "LoadAccessFaultM     \="] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
-set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoAccessFaultM \="] 
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
-set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
-set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
-set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
-
-# IMMU only makes word-sized accesses
-set line [GetLineNum ${SRC}/mmu/mmu.sv "exclusion-tag: immu-wordaccess"] 
-set line2 [expr $line + 6 ]
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
-coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
-
-# IMMU never disables translations
-coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
-coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
-# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
-coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18 
-
-
-
-
-###############
-# HPTW exclusions
-###############
-
-# RV64GC HPTW never starts at L1_ADR
-set line [GetLineNum ${SRC}/mmu/hptw.sv "InitialWalkerState == L1_ADR"] 
-coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2
-
-# Never possible to get a page fault when neither reading nor writing
-set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWLoadPageFault"] 
-coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7
- 
-# Never possible to get a store page fault from an ITLB walk
-set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWStoreAmoPageFault"] 
-coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
- 
-# Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf)
-set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWUpdateDA"] 
-coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
- 
-###############
-# Other exclusions
-###############
-
-# IMMU PMP does not support CBO instructions
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"] 
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"] 
-
-# IMMU PMP only makes 4-byte accesses
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd0"]  -item bs 1
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd1"]  -item bs 1
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "SizeBytesMinus1 = 3'd7"]  -item bs 1
-
-# No irom
-set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"] 
-coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
-set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"] 
-coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
-
-# no DTIM 
-set line [GetLineNum ${SRC}/lsu/lsu.sv "assign BusRW"] 
-coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
-set line [GetLineNum ${SRC}/lsu/lsu.sv "assign CacheRWM"] 
-coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
-
-# Excluding reset and clear for impossible case in the wficountreg in privdec
-#set line [GetLineNum ${SRC}/generic/flop/floprc.sv "reset \\| clear"]
-#coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
-
-# Exclude system reset case in ebu
-set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "BeatCounter\\("]
-coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
-set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "FinalBeatReg\\("]
-coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line  -item bc 1
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
-
-# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then
-# writebacks.  The cache never issues these type of requests.
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
-
-# FetchWait never occurs because HREADY is never 0.
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
-
-# all of these HREADY exclusions occur because HREADY is always 1.  The ram_ahb module never stalls.
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-
-#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
-#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-
-#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
-#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-
-set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
-
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
-
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
-
-# these transitions will not happen
-coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE
-
-# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
-# This is a blunt instrument; perhaps there is a more graceful exclusion
-coverage exclude -srcfile priorityonehot.sv 
-
-# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
-coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
-coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
-
-# StallD always equals StallF so LatestUnstalledD is always 0
-coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazard.sv "StallD always equals StallF"] -item 1 4
-coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazard.sv "coverage tag: LatestUnstalledD always 0"] -item e 1 -fecexprrow 2
-
-####################
-# Privileged
-####################
-
-# Instruction Misaligned never asserted because compresssed instructions are accepted
-coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
-
-# Attempting to access fflags, frm, fcsr with mstatus.FS = 0 traps, so checking for (STATUS_FS != 2'b00)
-# before enabling writes to these CSRs is redundant and uncoverable
-coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum ${SRC}/privileged/csru.sv "assign WriteFRMM"] -item e 1 -fecexprrow 3
-coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum ${SRC}/privileged/csru.sv "assign WriteFFLAGSM"] -item e 1 -fecexprrow 3
-
-# Attempted writes to the nonextistant MTIME register trap, so WriteHPMCOUNTERM cannot be set for that address (0xb01)
-coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "MTIME traps"] -item e 1 -fecexprrow 2 4
-coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "assign NextHPMCOUNTERM"] -item b 1
-
-# attempting to write stimecmp with STCE=0 traps, causing CSRSWriteM to go low 
-coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSTIMECMPM"] -item e 1 -fecexprrow 5
-
-# mode != m_mode and TVM = 1 causes a trap, causing CSRSWriteM to go low
-coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSATPM"] -item e 1 -fecexprrow 5 8
-
-####################
-# EBU
-####################
-
-# Exclude EBU Beat Counter flop because it is only idle when bus has multicycle latency, but rv64gc has single cycle latency
-coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb/BeatCounter/cntrflop
-
-
-
-
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
deleted file mode 100644
index 22f78b91b..000000000
--- a/sim/questa/wally.do
+++ /dev/null
@@ -1,239 +0,0 @@
-# wally.do
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench
-# James Stine, 2008; David Harris 2021; Jordan Carlin 2024
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# Usage: do wally.do <config> <testcases> <testbench> [--ccov] [--fcov] [--gui] [--args "any number of +value"] [--params "any number of VAR=VAL parameter overrides"] [--define "any number of +define+VAR=VAL"]
-# Example: do wally.do rv64gc arch64i testbench
-
-# Use this wally.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-# lcheck - return 1 if value is in list and remove it from list
-proc lcheck {listVariable value} {
-    upvar 1 $listVariable list
-    set index [lsearch -exact $list $value]
-    if {$index >= 0} {
-        set list [lreplace $list $index $index]
-        return 1
-    } else {
-        return 0
-    }
-}
-
-set DEBUG 1
-onbreak {resume}
-onerror {quit -f}
-
-# Initialize variables
-set CFG ${1}
-set TESTSUITE ${2}
-set TESTBENCH ${3}
-set WKDIR wkdir/${CFG}_${TESTSUITE}
-set WALLY $::env(WALLY)
-set CONFIG ${WALLY}/config
-set SRC ${WALLY}/src
-set TB ${WALLY}/testbench
-set FCRVVI ${WALLY}/addins/cvw-arch-verif/fcov
-
-# create library
-if [file exists ${WKDIR}] {
-    vdel -lib ${WKDIR} -all
-}
-vlib ${WKDIR}
-
-set PlusArgs ""
-set ParamArgs ""
-set ExpandedParamArgs {}
-set DefineArgs ""
-
-set ccov 0
-set CoverageVoptArg ""
-set CoverageVsimArg ""
-
-set FunctCoverage 0
-set FCvlog ""
-
-set breker 0
-set brekervlog ""
-set brekervopt ""
-
-set lockstep 0
-set lockstepvlog ""
-
-set SVLib ""
-
-set GUI 0
-set accFlag ""
-
-# Need to be able to pass arguments to vopt.  Unforunately argv does not work because
-# it takes on different values if vsim and the do file are called from the command line or
-# if the do file is called from questa sim directly.  This chunk of code uses the $n variables
-# and compacts them into a single list for passing to vopt. Shift is used to move the arguments
-# through the list.
-set lst {}
-echo "number of args = $argc"
-
-# Shift off the first three arguments (config, testcases, testbench)
-shift
-shift
-shift
-
-# Copy the remaining arguments into a list
-while {$argc > 0} {
-    lappend lst [expr "\$1"]
-    shift
-}
-
-echo "lst = $lst"
-
-# if --gui found set flag and remove from list
-if {[lcheck lst "--gui"]} {
-    set GUI 1
-    set accFlag "+acc"
-}
-
-# if --vcd found set flag and remove from list
-if {[lcheck lst "--vcd"]} {
-    set VCD 1
-    set accFlag "+acc"
-}
-
-# if --ccov found set flag and remove from list
-if {[lcheck lst "--ccov"]} {
-    set ccov 1
-    set CoverageVoptArg "+cover=sbecf"
-    set CoverageVsimArg "-coverage"
-}
-
-# if --fcov found set flag and remove from list
-if {[lcheck lst "--fcov"]} {
-    set FunctCoverage 1
-    set FCvlog "-f ${FCRVVI}/cvw-arch-verif.f"
-}
-
-# if --lockstep found set flag and remove from list
-if {[lcheck lst "--lockstep"]} {
-    set IMPERAS_HOME $::env(IMPERAS_HOME)
-    set lockstep 1
-    set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model "
-    set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \
-                      +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \
-                      ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
-                      ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv"
-    # only add standard rvviTrace interface if not using the custom one from cvw-arch-verif
-    if {!$FunctCoverage} {append lockstepvlog " ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvviTrace.sv"}
-}
-
-# if --breker found set flag and remove from list
-# Requires a license for the breker tool. See tests/breker/README.md for details
-if {[lcheck lst "--breker"]} {
-    set breker 1
-    set BREKER_HOME $::env(BREKER_HOME)
-    set brekervlog "+incdir+${WALLY}/testbench/trek_files \
-                    ${WALLY}/testbench/trek_files/uvm_output/trek_uvm_pkg.sv"
-    set brekervopt "${WKDIR}.trek_uvm"
-    append SVLib " -sv_lib ${BREKER_HOME}/linux64/lib/libtrek "
-}
-
-# Set PlusArgs passed using the --args flag
-set PlusArgsIndex [lsearch -exact $lst "--args"]
-if {$PlusArgsIndex >= 0} {
-    set PlusArgs [lindex $lst [expr {$PlusArgsIndex + 1}]]
-    set lst [lreplace $lst $PlusArgsIndex [expr {$PlusArgsIndex + 1}]]
-}
-
-# Set ParamArgs passed using the --params flag and expand into a list of -G<param> arguments
-set ParamArgsIndex [lsearch -exact $lst "--params"]
-if {$ParamArgsIndex >= 0} {
-    set ParamArgs [lindex $lst [expr {$ParamArgsIndex + 1}]]
-    set ParamArgs [regexp -all -inline {\S+} $ParamArgs]
-    foreach param $ParamArgs {
-        lappend ExpandedParamArgs -G$param
-    }
-    set lst [lreplace $lst $ParamArgsIndex [expr {$ParamArgsIndex + 1}]]
-}
-
-# Set +define macros passed using the --define flag
-set DefineArgsIndex [lsearch -exact $lst "--define"]
-if {$DefineArgsIndex >= 0} {
-    set DefineArgs [lindex $lst [expr {$DefineArgsIndex + 1}]]
-    set lst [lreplace $lst $DefineArgsIndex [expr {$DefineArgsIndex + 1}]]
-}
-
-# Debug print statements
-if {$DEBUG > 0} {
-    echo "GUI = $GUI"
-    echo "ccov = $ccov"
-    echo "lockstep = $lockstep"
-    echo "FunctCoverage = $FunctCoverage"
-    echo "Breker = $breker"
-    echo "remaining list = $lst"
-    echo "Extra +args = $PlusArgs"
-    echo "Extra params = $ExpandedParamArgs"
-    echo "Extra defines = $DefineArgs"
-}
-
-# compile source files
-# suppress spurious warnngs about
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared"
-set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
-vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${lockstepvlog} {*}${FCvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
-
-vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg}
-
-# power add generates the logging necessary for saif generation.
-# power add -r /dut/core/*
-
-# add waveforms if GUI is enabled
-if { ${GUI} } {
-    add log -recursive /*
-    if { ${TESTBENCH} eq "testbench_fp" } {
-        do wave-fpu.do
-    } else {
-        do wave.do
-    }
-}
-
-if {$FunctCoverage} {
-    set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb
-    coverage save -onexit ${UCDB}
-}
-
-run -all
-
-if {$ccov} {
-    set UCDB ${WALLY}/sim/questa/ucdb/${CFG}_${TESTSUITE}.ucdb
-    echo "Saving coverage to ${UCDB}"
-    do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
-    coverage save -instance /testbench/dut/core ${UCDB}
-}
-
-
-# power off -r /dut/core/*
-
-
-
-# These aren't doing anything helpful
-#profile report -calltree -file wally-calltree.rpt -cutoff 2
-#power report -all -bsaif power.saif
-
-# terminate simulation unless we need to keep the GUI running
-if { ${GUI} == 0} {
-    quit
-}
diff --git a/sim/questa/wave-fpu.do b/sim/questa/wave-fpu.do
deleted file mode 100644
index f4da1e8a2..000000000
--- a/sim/questa/wave-fpu.do
+++ /dev/null
@@ -1,30 +0,0 @@
-
-add wave -noupdate /testbench_fp/clk
-add wave -noupdate -radix decimal /testbench_fp/VectorNum
-add wave -noupdate /testbench_fp/FrmNum
-add wave -noupdate /testbench_fp/X
-add wave -noupdate /testbench_fp/Y
-add wave -noupdate /testbench_fp/Z
-add wave -noupdate /testbench_fp/Res
-add wave -noupdate /testbench_fp/Ans
-add wave -noupdate /testbench_fp/reset
-add wave -noupdate /testbench_fp/DivStart
-add wave -noupdate /testbench_fp/FDivBusyE
-add wave -noupdate /testbench_fp/CheckNow
-add wave -noupdate /testbench_fp/DivDone
-add wave -noupdate /testbench_fp/ResMatch
-add wave -noupdate /testbench_fp/FlagMatch
-add wave -noupdate /testbench_fp/CheckNow
-add wave -noupdate /testbench_fp/NaNGood
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/specialcase/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/flags/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/normshift/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/shiftcorrection/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/resultsign/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/round/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/fmashiftcalc/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/divshiftcalc/*
-add wave -group {PostProc} -noupdate /testbench_fp/postprocess/cvtshiftcalc/*
-add wave -group {Testbench} -noupdate /testbench_fp/*
-add wave -group {Testbench} -noupdate /testbench_fp/readvectors/*
diff --git a/sim/questa/wave.do b/sim/questa/wave.do
deleted file mode 100644
index 3ef36eef6..000000000
--- a/sim/questa/wave.do
+++ /dev/null
@@ -1,697 +0,0 @@
-onerror {resume}
-quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /testbench/clk
-add wave -noupdate /testbench/reset
-add wave -noupdate /testbench/memfilename
-add wave -noupdate /testbench/dut/core/SATP_REGW
-add wave -noupdate /testbench/dut/core/InstrValidM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
-add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
-add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF
-add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/core/PCE
-add wave -noupdate -group PCS /testbench/dut/core/PCM
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/IEUAdrE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSrcE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PC1NextF
-add wave -noupdate -group {PCNext Generation} -label {NextValidPCE (from bpred)} /testbench/dut/core/ifu/NextValidPCE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/CSRWriteFenceM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/mretM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/EPCM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapVectorM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/RetM
-add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/ifu/UnalignedPCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[2]}
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[1]}
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[0]}
-add wave -noupdate -group ifu -group Bpred -group RAS -expand /testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory
-add wave -noupdate -group ifu -group Bpred -group RAS /testbench/dut/core/ifu/bpred/bpred/RASPredictor/Ptr
-add wave -noupdate -group ifu -group Bpred -divider {class check}
-add wave -noupdate -group ifu -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group ifu -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
-add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
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-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {requesting address} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheSetTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLineCache
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/Tag
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/ValidWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs -color {Blue Violet} /testbench/dut/core/lsu/bus/dcache/dcache/Hit
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/DirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group SRAM-outputs /testbench/dut/core/lsu/bus/dcache/dcache/HitLineDirty
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelWriteback
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/LineByteMask
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheSetData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheSetTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/TagWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
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-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
-add wave -noupdate -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MENVCFG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/privmode/PrivilegeModeW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrs/csrs/STIMECMP_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
-add wave -noupdate -group CSRs -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/BALUControl
-add wave -noupdate -group alu -divider internals
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1D
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2D
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2E
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdE
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/MemReadE
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteM
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteW
-add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardAE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardBE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/LoadStallD
-add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/ForwardAE
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
-add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
-add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
-add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
-add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf
-add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
-add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
-add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
-add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
-add wave -noupdate -group testbench /testbench/DCacheFlushStart
-add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
-add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
-add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/PCLK
-add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPICLK
-add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPICS
-add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIOut
-add wave -noupdate -group spi -expand -group interface /testbench/dut/uncoregen/uncore/spi/spi/SPIIn
-add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/ChipSelectMode
-add wave -noupdate -group spi /testbench/dut/uncoregen/uncore/spi/spi/SckMode
-add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/ShiftEdge
-add wave -noupdate /testbench/dut/uncoregen/uncore/spi/spi/TransmitData
-add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheEn
-add wave -noupdate /testbench/dut/core/ifu/bus/icache/icache/cachefsm/FlushStage
-add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/FlushStage
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {89834 ns} 1} {{Cursor 4} {79055 ns} 1} {{Cursor 3} {89604 ns} 0}
-quietly wave cursor active 3
-configure wave -namecolwidth 250
-configure wave -valuecolwidth 194
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {89564 ns} {89776 ns}
diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py
deleted file mode 100755
index 57ede0309..000000000
--- a/sim/rv64gc_CacheSim.py
+++ /dev/null
@@ -1,97 +0,0 @@
-#!/usr/bin/env python3
-
-###########################################
-## rv64gc_CacheSim.py
-##
-## Written: lserafini@hmc.edu
-## Created: 11 April 2023
-## Modified: 12 April 2023
-## Modified: 10 August 2023, jcarlin@hmc.edu
-##
-## Purpose: Run the cache simulator on each rv64gc test suite in turn.
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-## either express or implied. See the License for the specific language governing permissions
-## and limitations under the License.
-################################################################################################
-import argparse
-import os
-import subprocess
-
-# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
-# This does not check the test output for correctness, run regression for that.
-# Add -p or --perf to report the hit/miss ratio.
-# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
-# These distributions may not add up to 100; this is because of flushes or invalidations.
-
-class bcolors:
-    HEADER = '\033[95m'
-    OKBLUE = '\033[94m'
-    OKCYAN = '\033[96m'
-    OKGREEN = '\033[92m'
-    WARNING = '\033[93m'
-    FAIL = '\033[91m'
-    ENDC = '\033[0m'
-    BOLD = '\033[1m'
-    UNDERLINE = '\033[4m'
-
-tests64gc = ["coverage64gc", "wally64priv", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zcb",
-             "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", 
-             "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
-             "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]
-# arch64i is the most interesting case.  Uncomment line below to run just that case
-#tests64gc = ["arch64i"]
-#tests64gc = ["coverage64gc"]
-#tests64gc = ["wally64priv"]
-
-cachetypes = ["ICache", "DCache"]
-simdir = os.path.expandvars("$WALLY/sim")
-
-def main():
-    parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
-    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
-    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
-    parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
-    args = parser.parse_args()
-    simargs = "I_CACHE_ADDR_LOGGER=1\\'b1 D_CACHE_ADDR_LOGGER=1\\'b1"
-    testcmd = "wsim --sim " + args.sim + ' rv64gc {} --params "' + simargs + '" > /dev/null'
-    #cachecmd = "CacheSim.py 64 4 56 44 -f {} --verbose"
-    cachecmd = "CacheSim.py 64 4 56 44 -f {}"
-    mismatches = 0
-
-    if args.perf:
-        cachecmd += " -p"
-    if args.dist:
-        cachecmd += " -d"
-
-    for test in tests64gc:
-        print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
-        # remove wkdir to force recompile with logging enabled
-        os.system("rm -rf " + simdir + "/" + args.sim + "/wkdir/rv64gc_" + test)
-        os.system("rm -rf " + simdir + "/" + args.sim + "/*Cache.log")
-        print(testcmd.format(test))
-        os.system(testcmd.format(test))
-        for cache in cachetypes:
-            print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
-            result = subprocess.run(cachecmd.format(args.sim+"/"+cache+".log"), shell=True)
-            mismatches += result.returncode
-        print()
-    return mismatches
-
-if __name__ == '__main__':
-    exit(main())
-
diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs
deleted file mode 100755
index bc266c8ae..000000000
--- a/sim/vcs/run_vcs
+++ /dev/null
@@ -1,119 +0,0 @@
-#!/usr/bin/env python3
-
-# run_vcs
-# David_Harris@hmc.edu 2 July 2024
-# Modified Jordan Carlin jcarlin@hmc.edu Dec 9 2024
-# Run VCS on a given file, passing appropriate flags
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-import argparse
-import os
-import subprocess
-import sys
-
-# Global variables
-WALLY  = os.environ.get("WALLY")
-simdir = f"{WALLY}/sim/vcs"
-cfgdir = f"{WALLY}/config"
-srcdir = f"{WALLY}/src"
-tbdir  = f"{WALLY}/testbench"
-logdir = f"{simdir}/logs"
-
-# run a Linux command and return the result as a string in a form that VCS can use
-def runFindCommand(cmd):
-    res = subprocess.check_output(cmd, shell=True)
-    res = str(res)
-    res = res.replace("\\n", " ")  # replace newline with space
-    res = res.replace("'", "")  # strip off quotation marks
-    res = res[1:] # strip off leading b from byte string
-    return res
-
-def parseArgs():
-    parser = argparse.ArgumentParser()
-    parser.add_argument("config", help="Configuration file")
-    parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
-    parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
-    # parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") # Not yet implemented
-    # parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") # Not yet implemented
-    parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
-    parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
-    parser.add_argument("--define", "-d", help="Optional define macros passed to simulator", default="")
-    parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
-    #parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") # GUI not yet implemented
-    return parser.parse_args()
-
-def createDirs(config, testsuite):
-    wkdir  = f"{simdir}/wkdir/{config}_{testsuite}"
-    covdir = f"{simdir}/cov/{config}_{testsuite}"
-    os.makedirs(wkdir, exist_ok=True)
-    os.makedirs(covdir, exist_ok=True)
-    os.makedirs(logdir, exist_ok=True)
-    return wkdir
-
-def generateFileList(testbench):
-    rtlsrc_cmd = f'find {srcdir} -name "*.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x64.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "{srcdir}/generic/mem/rom1p1r_128x32.sv" ! -path "{srcdir}/generic/mem/ram2p1r1wbe_2048x64.sv"'
-    rtlsrc_files = runFindCommand(rtlsrc_cmd)
-    tbcommon_cmd = f'find {tbdir}/common -name "*.sv"'
-    tbcommon_files = runFindCommand(tbcommon_cmd)
-    tb_file = f"{tbdir}/{testbench}.sv"
-    return f"{tb_file} {rtlsrc_files} {tbcommon_files}"
-
-def processArgs(wkdir, args):
-    compileOptions = []
-    simvOptions = []
-    if args.lockstep:
-        compileOptions.extend(["+incdir+$IMPERAS_HOME/ImpPublic/include/host",
-                                "+incdir+$IMPERAS_HOME/ImpProprietary/include/host",
-                                "$IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv",
-                                "$IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv"])
-        simvOptions.append("-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model")
-    # if args.ccov:
-    #     compileOptions.extend(["-cm line+cond+branch+fsm+tgl", f"-cm_log {wkdir}/coverage.log", f"-cm_dir {wkdir}/coverage"])
-    if args.params:
-        compileOptions.append(setupParamOverrides(wkdir, args))
-    if args.define:
-        compileOptions.append(args.define)
-    # if args.gui:
-    #     compileOptions.append("-debug_access+all+reverse -kdb +vcs+vcdpluson")
-    compileOptions = " ".join(compileOptions)
-    simvOptions = " ".join(simvOptions)
-    return compileOptions, simvOptions
-
-def setupParamOverrides(wkdir, args):
-    paramOverrideFile = os.path.join(wkdir, "param_overrides.txt")
-    with open(paramOverrideFile, "w") as f:
-        for param in args.params.split():
-            [param, value] = param.split("=")
-            value = value.replace("\\'", "'") if "\\'" in value else f'"{value}"' # transform quotes/bit indicators
-            f.write(f"assign {value} {args.tb}/{param}\n")
-    return f" -parameters {wkdir}/param_overrides.txt "
-
-def setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args):
-    includePath = f"+incdir+{cfgdir}/{args.config} +incdir+{cfgdir}/deriv/{args.config} +incdir+{cfgdir}/shared +incdir+$WALLY/tests +incdir+{tbdir} +incdir+{srcdir}"
-    vcsStandardFlags = "+lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn"
-    vcsCMD = f"vcs {vcsStandardFlags} -top {args.tb} {compileOptions} -Mdir={wkdir} {includePath} {srcdir}/cvw.sv {rtlFiles} -o {wkdir}/sim_out -work {wkdir} -Mlib={wkdir} -l {logdir}/{args.config}_{args.testsuite}.log"
-    simvCMD = f"{wkdir}/sim_out +TEST={args.testsuite} {args.args} -no_save {simvOptions}"
-    return vcsCMD, simvCMD
-
-def runVCS(vcsCMD, simvCMD):
-    print(f"Executing: {vcsCMD}")
-    subprocess.run(vcsCMD, shell=True, check=True)
-    subprocess.run(simvCMD, shell=True, check=True)
-
-def runCoverage(wkdir, config, testsuite):
-    COV_RUN = f"urg -dir {wkdir}/coverage.vdb -format text -report IndividualCovReport/{config}_{testsuite}"
-    subprocess.run(COV_RUN, shell=True, check=True)
-
-def main(args):
-    print(f"run_vcs Config={args.config} tests={args.testsuite} lockstep={args.lockstep} args='{args.args}' params='{args.params}' define='{args.define}'")
-    wkdir = createDirs(args.config, args.testsuite)
-    rtlFiles = generateFileList(args.tb)
-    compileOptions, simvOptions = processArgs(wkdir, args)
-    vcsCMD, simvCMD = setupCommands(wkdir, rtlFiles, compileOptions, simvOptions, args)
-    runVCS(vcsCMD, simvCMD)
-    # if args.ccov:
-    #     runCoverage(wkdir, args.config, args.testsuite)
-
-if __name__ == "__main__":
-    args = parseArgs()
-    sys.exit(main(args))
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
deleted file mode 100644
index ecb6b5f42..000000000
--- a/sim/verilator/Makefile
+++ /dev/null
@@ -1,85 +0,0 @@
-# Verilator Makefile for WALLY
-# Kunlin Han, Rose Thompson, David Harris 2024
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-SHELL := /bin/bash
-.PHONY: profile run questa clean
-
-# verilator configurations
-OPT=--assert
-PARAMS?=--no-trace-top
-NONPROF?=--stats
-VERILATOR_DIR=${WALLY}/sim/verilator
-SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
-PLUS_ARGS=
-PARAM_ARGS=
-DEFINE_ARGS=
-EXPANDED_PARAM_ARGS:=$(patsubst %,-G%,$(PARAM_ARGS))
-
-WALLYCONF?=rv64gc
-TEST?=arch64i
-TESTBENCH?=testbench
-
-# constants
-# assume WALLY variable is correctly configured in the shell environment
-# INCLUDE_PATH are pathes that Verilator should search for files it needs
-INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
-# SOURCES are source files
-SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv
-# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
-DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
-
-WORKDIR = $(VERILATOR_DIR)/wkdir/$(WALLYCONF)_$(TEST)
-
-# regular testbench requires a wrapper defining getenvval
-ifeq ($(TESTBENCH), testbench)
-	WRAPPER=${WALLY}/sim/verilator/wrapper.c
-	ARGTEST=+TEST=$(TEST)
-else
-	WRAPPER=
-	ARGTEST=
-endif
-
-default: run
-
-run: $(WORKDIR)/V${TESTBENCH}
-	mkdir -p $(VERILATOR_DIR)/logs
-	$(WORKDIR)/V${TESTBENCH} ${ARGTEST} $(PLUS_ARGS)
-
-profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
-	$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
-	mv gmon.out gmon_$(WALLYCONF).out
-	gprof $(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
-	verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2
-	mkdir -p $(VERILATOR_DIR)/logs_profiling
-	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
-	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
-
-$(WORKDIR)/V${TESTBENCH}: $(DEPENDENCIES)
-	mkdir -p $(WORKDIR)
-	verilator \
-	--Mdir $(WORKDIR) -o V${TESTBENCH} \
-	--binary --trace \
-	$(OPT) $(PARAMS) $(NONPROF) \
-	--top-module ${TESTBENCH}  --relative-includes \
-	$(INCLUDE_PATH) \
-	${WRAPPER} \
-	${DEFINE_ARGS} \
-	${EXPANDED_PARAM_ARGS} \
-	$(SOURCES)
-
-obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
-	mkdir -p obj_dir_profiling
-	verilator \
-	--Mdir obj_dir_profiling -o V${TESTBENCH}_$(WALLYCONF) \
-	--binary \
-	--prof-cfuncs $(OPT) $(PARAMS) \
-	--top-module ${TESTBENCH}  --relative-includes \
-	$(INCLUDE_PATH) \
-	${WRAPPER} \
-	${DEFINE_ARGS} \
-	${EXPANDED_PARAM_ARGS} \
-	$(SOURCES)
-
-clean:
-	rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
diff --git a/sim/verilator/README.md b/sim/verilator/README.md
deleted file mode 100644
index 5fd1b57b3..000000000
--- a/sim/verilator/README.md
+++ /dev/null
@@ -1,32 +0,0 @@
-# Simulation with Verilator
-
-Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=<testsuite>`.
-
-Demand:
-
-- Avoid unnecessary compilation by sharing the same executable for a specific configuration
-    - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly
-- Wsim should support `-s verilator` option and run simulation with Verilator.
-
-## Folder Structure
-
-This folder contains the following files that help the simulation of Wally with Verilator:
-
-- Makefile: simplify the usage with Verialtor
-- executables
-    - `obj_dir_non_profiling`: non-profiling executables for different configurations
-    - `obj_dir_profiling`: profiling executables for different configurations
-- logs in `logs` and `logs_profiling` correspondingly
-- [NOT WORKING] `logs`: contains all the logs
-
-## Examples
-
-```shell
-# non-profiling mode
-make WALLYCONF=rv64gc TEST=arch64i run
-# profiling mode
-make WALLYCONF=rv64gc TEST=arch64i profile
-
-# remove all the temporary files, including executables and logs
-make clean
-```
\ No newline at end of file
diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c
deleted file mode 100644
index 572acaa55..000000000
--- a/sim/verilator/wrapper.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <stdlib.h>
-
-#include "Vtestbench__Dpi.h"
-
-const char *getenvval(const char *pszName) {
-    const char *pszValue = getenv(pszName);
-    if (pszValue == NULL) {
-        return "";
-    }
-    return ((const char *) getenv(pszName));
-}
\ No newline at end of file
diff --git a/sim/xcelium/README.md b/sim/xcelium/README.md
deleted file mode 100644
index 094a939e3..000000000
--- a/sim/xcelium/README.md
+++ /dev/null
@@ -1,3 +0,0 @@
-## Xcelium Simulation with CVW
-
-NOTE: Xcelium is not regularly tested and may not work correctly. It is also not integrated with the `wsim` command used for CVW, so the config and testsuite must be manually modified in `wally.xrun` and it does not support all of the other options provided by `wsim `.
diff --git a/sim/xcelium/wally.xrun b/sim/xcelium/wally.xrun
deleted file mode 100644
index 67b3cdd5f..000000000
--- a/sim/xcelium/wally.xrun
+++ /dev/null
@@ -1,6 +0,0 @@
-xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
-xrun -elaborate -top testbench ../testbench/testbench-xcelium.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench
-
-
-xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench ../src/cvw.sv ../testbench/testbench-xcelium.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -top testbench -defparam testbench.TEST=arch64i
-
diff --git a/site-setup.csh b/site-setup.csh
deleted file mode 100644
index 63f1260be..000000000
--- a/site-setup.csh
+++ /dev/null
@@ -1,63 +0,0 @@
-#!/bin/csh
-
-# site-setup.csh
-
-# License servers and commercial CAD tool paths
-# Must edit these based on your local environment.  Ask your sysadmin.
-setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu                 # Change this to your Siemens license server
-setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu              # Change this to your Synopsys license server
-setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin   # Change this for your path to Questa
-setenv SNPSPATH /cad/synopsys/SYN/bin                             # Change this for your path to Design Compiler
-setenv VCSPATH /cad/synopsys/vcs/U-2023.03-SP2-4/bin              # Change this for your path to Synopsys VCS
-
-# Tools
-# Questa and Synopsys
-extend PATH $QUESTAPATH
-extend PATH $SNPSPATH
-extend PATH $VCSPATH
-
-# GCC
-if ( ! $?LD_LIBRARY_PATH ) then
-    setenv LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib
-else
-    extend LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib
-endif
-
-# RISC-V Tools
-extend LD_LIBRARY_PATH $RISCV/lib
-extend LD_LIBRARY_PATH $RISCV/lib64
-extend LD_LIBRARY_PATH $RISCV/lib/x86_64-linux-gnu/
-extend PATH $RISCV/bin
-
-# Activate riscv-python Virtual Environment
-if ( -e "$RISCV"/riscv-python/bin/activate ) then
-    source "$RISCV"/riscv-python/bin/activate.csh
-else
-    echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it."
-    exit 1
-endif
-
-# environment variables needed for RISCV-DV
-setenv RISCV_GCC `which riscv64-unknown-elf-gcc`		            # Copy this as it is
-setenv RISCV_OBJCOPY `which riscv64-unknown-elf-objcopy`	        # Copy this as it is
-setenv SPIKE_PATH $RISCV/bin										# Change this for your path to riscv-isa-sim (spike)
-
-# Imperas; put this in if you are using it
-#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
-#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
-
-setenv IDV $RISCV/ImperasDV-OpenHW
-if ($?IDV) then
-    # echo "Imperas exists"
-    setenv IMPERAS_HOME $IDV
-    setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC
-    setenv ROOTDIR ~/
-    source ${IMPERAS_HOME}/bin/setup.sh
-    setupImperas ${IMPERAS_HOME}
-    extend PATH $IDV/scripts/cvw
-endif
-
-# Use newer gcc version for older distros
-if ( -e $RISCV/gcc-10 ) then
-    prepend PATH \$RISCV/gcc-10/bin # Ubuntu 20.04 LTS
-endif
diff --git a/site-setup.sh b/site-setup.sh
deleted file mode 100755
index 8bcd3d96e..000000000
--- a/site-setup.sh
+++ /dev/null
@@ -1,85 +0,0 @@
-#!/bin/bash
-
-# site-setup.sh
-# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
-# System Admin should install this into $RISCV/site-setup.sh
-# $RISCV is typically /opt/riscv
-# System Admin must update the licenses and paths for localization.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# license servers and commercial CAD tool paths
-# Must edit these based on your local environment.
-export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change this to your Siemens license server for Questa
-export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
-export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu               # Change this to your Imperas license server
-export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim          # Change this for your path to Questa, excluding bin
-export DC_HOME=/cad/synopsys/SYN                                    # Change this for your path to Synopsys DC, excluding bin
-export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4                   # Change this for your path to Synopsys VCS, excluding bin
-export BREKER_HOME=/cad/breker/trek5-2.1.11-GCC6_el7                # Change this for your path to Breker Trek
-
-# Tools
-# Questa and Synopsys
-export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
-
-# Environmental variables for SoC
-export SYN_pdk=/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
-#export osupdk=/import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
-export SYN_TLU=/home/jstine/TLU+
-#export OSUTLU=/import/yukari1/pdk/TSMC/TLU+
-export SYN_MW=/home/jstine/MW
-#export OSUMW=/import/yukari1/pdk/TSMC/MW
-export SYN_memory=/home/jstine/WallyMem/rv64gc/
-#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
-
-# Environmental variables for CTG (https://github.com/riscv-software-src/riscv-ctg)
-export RISCVCTG=/home/harris/repos/riscv-ctg
-
-
-# GCC
-if [ -z "$LD_LIBRARY_PATH" ]; then
-    export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib
-else
-    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib
-fi
-
-# RISC-V Tools
-export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/lib/x86_64-linux-gnu/
-export PATH=$PATH:$RISCV/bin
-
-# Activate riscv-python Virtual Environment
-if [ -e "$RISCV"/riscv-python/bin/activate ]; then
-    source "$RISCV"/riscv-python/bin/activate
-else
-    echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it."
-    exit 1
-fi
-
-# Environment variables needed for RISCV-DV
-export RISCV_GCC=$(which riscv64-unknown-elf-gcc)		            # Copy this as it is
-export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy)	        # Copy this as it is
-export SPIKE_PATH=$RISCV/bin										# Copy this as it is
-
-# Imperas OVPsim; put this in if you are using it
-#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
-#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
-
-# Imperas DV setup
-export IDV=$RISCV/ImperasDV-OpenHW
-if [ -e "$IDV" ]; then
-    # echo "Imperas exists"
-    export IMPERAS_HOME=$IDV
-    export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
-    export ROOTDIR=~/
-    source "${IMPERAS_HOME}"/bin/setup.sh
-    setupImperas "${IMPERAS_HOME}"
-    export PATH=$IDV/scripts/cvw:$PATH
-fi
-
-# Use newer gcc version for older distros
-if [ -e /opt/rh/gcc-toolset-13/enable ]; then
-    source /opt/rh/gcc-toolset-13/enable # Red Hat Family
-elif [ -e $RISCV/gcc-13 ]; then
-    export PATH=$RISCV/gcc-13/bin:$PATH  # SUSE Family
-elif [ -e $RISCV/gcc-10 ]; then
-    export PATH=$RISCV/gcc-10/bin:$PATH  # Ubuntu 20.04 LTS
-fi
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
deleted file mode 100644
index 91aa5c97b..000000000
--- a/src/cache/cachefsm.sv
+++ /dev/null
@@ -1,211 +0,0 @@
-///////////////////////////////////////////
-// cachefsm.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 25 August 2021
-// Modified: 20 January 2023
-//
-// Purpose: Controller for the cache fsm
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module cachefsm #(parameter READ_ONLY_CACHE = 0) (
-  input  logic       clk,
-  input  logic       reset,
-  // hazard and privilege unit
-  input  logic       Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
-  input  logic       FlushStage,        // Pipeline flush of second stage (prevent writes and bus operations)
-  output logic       CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
-  output logic       CacheStall,        // Cache stalls pipeline during multicycle operation
-  // inputs from IEU
-  input  logic [1:0] CacheRW,           // [1] Read, [0] Write 
-  input  logic       FlushCache,        // Flush all dirty lines back to memory
-  input  logic       InvalidateCache,   // Clear all valid bits
-  input  logic [3:0] CMOpM,             // 0001: cbo.inval; 0010: cbo.flush; 0100: cbo.clean; 1000: cbo.zero
-  // Bus controls
-  input  logic       CacheBusAck,       // Bus operation completed
-  output logic [1:0] CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
-  // performance counter outputs
-  output logic       CacheMiss,         // Cache miss  
-  output logic       CacheAccess,       // Cache access
-
-  // cache internals
-  input  logic       Hit,          // Exactly 1 way hits
-  input  logic       LineDirty,         // The selected line and way is dirty
-  input  logic       HitLineDirty,   // The cache hit way is dirty
-  input  logic       FlushAdrFlag,      // On last set of a cache flush
-  input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
-  output logic       SelAdrData,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
-  output logic       SelAdrTag,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
-  output logic       SetValid,          // Set the valid bit in the selected way and set
-  output logic       ClearValid,        // Clear the valid bit in the selected way and set
-  output logic       SetDirty,          // Set the dirty bit in the selected way and set
-  output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
-  output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback
-  output logic       LRUWriteEn,        // Update the LRU state
-  output logic       SelVictim,         // Overides HitWay Tag matching.  Selects selects the victim tag/data regardless of hit
-  output logic       FlushAdrCntEn,     // Enable the counter for Flush Adr
-  output logic       FlushWayCntEn,     // Enable the way counter during a flush
-  output logic       FlushCntRst,       // Reset both flush counters
-  output logic       SelFetchBuffer,    // Bypass the SRAM for a load hit by directly using the read data from the ahbcacheinterface's FetchBuffer
-  output logic       CacheEn            // Enable the cache memory arrays.  Disable hold read data constant
-);
-  
-  logic              resetDelay;
-  logic              AnyUpdateHit, AnyHit;
-  logic              AnyMiss;
-  logic              FlushFlag;
-  logic              CMOWriteback;
-  logic              CMOZeroNoEviction;
-  logic              StallConditions;
-
-  typedef enum logic [3:0]{STATE_ACCESS, // hit states
-                           // miss states
-                           STATE_FETCH,
-                           STATE_WRITEBACK,
-                           STATE_WRITE_LINE,
-                           STATE_ADDRESS_SETUP,  // required for back to back reads. structural hazard on writting SRAM
-                           // flush cache 
-                           STATE_FLUSH,
-                           STATE_FLUSH_WRITEBACK
-                           } statetype;
-
-  statetype CurrState, NextState;
-
-  assign AnyMiss = (CacheRW[0] | CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
-  assign AnyUpdateHit = (CacheRW[0]) & Hit;                            // exclusion-tag: icache storeAMO1
-  assign AnyHit = AnyUpdateHit | (CacheRW[1] & Hit);                  // exclusion-tag: icache AnyUpdateHit
-  assign CMOZeroNoEviction = CMOpM[3] & ~LineDirty;   // (hit or miss) with no writeback store zeros now
-  assign CMOWriteback = ((CMOpM[1] | CMOpM[2]) & Hit & HitLineDirty) | CMOpM[3] & LineDirty;
-  
-  assign FlushFlag = FlushAdrFlag & FlushWayFlag;
-
-  // outputs for the performance counters.
-  assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
-  assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
-
-  // special case on reset. When the fsm first exists reset twayhe
-  // PCNextF will no longer be pointing to the correct address.
-  // But PCF will be the reset vector.
-  flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
-
-  always_ff @(posedge clk)
-    if (reset | FlushStage)    CurrState <= STATE_ACCESS;
-    else CurrState <= NextState;  
-  
-  always_comb begin
-    NextState = STATE_ACCESS;
-    case (CurrState)                                                                                        // exclusion-tag: icache state-case
-      STATE_ACCESS:           if(InvalidateCache)                               NextState = STATE_ACCESS;     // exclusion-tag: dcache InvalidateCheck
-                             else if(FlushCache & ~READ_ONLY_CACHE)            NextState = STATE_FLUSH;     // exclusion-tag: icache FLUSHStatement
-                             else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;     // exclusion-tag: icache FETCHStatement
-                             else if((AnyMiss | CMOWriteback) & ~READ_ONLY_CACHE) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
-                             else                                              NextState = STATE_ACCESS;
-      STATE_FETCH:           if(CacheBusAck)                                   NextState = STATE_WRITE_LINE;
-                             else                                              NextState = STATE_FETCH;
-      STATE_WRITE_LINE:                                                        NextState = STATE_ADDRESS_SETUP;
-      STATE_ADDRESS_SETUP:       if(Stall)                                         NextState = STATE_ADDRESS_SETUP;
-                             else                                              NextState = STATE_ACCESS;
-      // exclusion-tag-start: icache case
-      STATE_WRITEBACK:       if(CacheBusAck & ~(|CMOpM[3:1]))                  NextState = STATE_FETCH;
-                             else if(CacheBusAck)                              NextState = STATE_ADDRESS_SETUP; // Read_hold lowers CacheStall
-                             else                                              NextState = STATE_WRITEBACK;
-      // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
-      STATE_FLUSH:           if(LineDirty)                                     NextState = STATE_FLUSH_WRITEBACK;
-                             else if (FlushFlag)                               NextState = STATE_ADDRESS_SETUP;
-                             else                                              NextState = STATE_FLUSH;
-      STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)                      NextState = STATE_FLUSH;
-                             else if(CacheBusAck)                              NextState = STATE_ADDRESS_SETUP;
-                             else                                              NextState = STATE_FLUSH_WRITEBACK;
-      // exclusion-tag-end: icache case
-      default:                                                                 NextState = STATE_ACCESS;
-    endcase
-  end
-
-  // com back to CPU
-  assign CacheCommitted = (CurrState != STATE_ACCESS) & ~(READ_ONLY_CACHE & (CurrState == STATE_ADDRESS_SETUP));
-  assign StallConditions =  FlushCache | AnyMiss | CMOWriteback;     // exclusion-tag: icache FlushCache
-  assign CacheStall = (CurrState == STATE_ACCESS & StallConditions) | // exclusion-tag: icache StallStates
-                      (CurrState == STATE_FETCH) |
-                      (CurrState == STATE_WRITEBACK) |
-                      (CurrState == STATE_WRITE_LINE) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
-                      (CurrState == STATE_FLUSH) |
-                      (CurrState == STATE_FLUSH_WRITEBACK);
-  // write enables internal to cache
-  assign SetValid = CurrState == STATE_WRITE_LINE | 
-                    (CurrState == STATE_ACCESS & CMOZeroNoEviction) |
-                    (CurrState == STATE_WRITEBACK & CacheBusAck & CMOpM[3]); 
-  assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0] | (CMOpM[2] & ~HitLineDirty))) |
-  //assign ClearValid = (CurrState == STATE_ACCESS & (CMOpM[0])) |
-                      (CurrState == STATE_WRITEBACK & CMOpM[2] & CacheBusAck);
-  assign LRUWriteEn = (((CurrState == STATE_ACCESS & (AnyHit | CMOZeroNoEviction)) |
-                       (CurrState == STATE_WRITE_LINE)) & ~FlushStage) |
-                      (CurrState == STATE_WRITEBACK & CMOpM[3] & CacheBusAck);
-  // exclusion-tag-start: icache flushdirtycontrols
-  assign SetDirty = (CurrState == STATE_ACCESS & (AnyUpdateHit | CMOZeroNoEviction)) |         // exclusion-tag: icache SetDirty  
-                    (CurrState == STATE_WRITE_LINE & (CacheRW[0])) |
-                    (CurrState == STATE_WRITEBACK & (CMOpM[3] & CacheBusAck));                    
-  assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) |   // exclusion-tag: icache ClearDirty
-                      (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
-  // Flush and eviction controls
-                      CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & CacheBusAck;
-  assign SelVictim = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOpM[1] | CMOpM[2])) | (CacheBusAck & CMOpM[3]))) |
-                  (CurrState == STATE_ACCESS & ((AnyMiss & LineDirty) | (CMOZeroNoEviction & ~Hit))) | 
-                  (CurrState == STATE_WRITE_LINE);
-  assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2] | ~CacheBusAck)) |
-                        (CurrState == STATE_ACCESS & AnyMiss & LineDirty);
-  // coverage off -item e 1 -fecexprrow 1
-  // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck)
-  assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
-             (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
-  assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
-             (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
-  assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
-              (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
-  // exclusion-tag-end: icache flushdirtycontrols
-  // Bus interface controls
-  assign CacheBusRW[1] = (CurrState == STATE_ACCESS & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
-                         (CurrState == STATE_FETCH & ~CacheBusAck) | 
-                         (CurrState == STATE_WRITEBACK & CacheBusAck & ~(|CMOpM));
-
-  logic LoadMiss;
-  assign LoadMiss = (CacheRW[1]) & ~Hit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
-
-  assign CacheBusRW[0] = (CurrState == STATE_ACCESS & LoadMiss & LineDirty) | // exclusion-tag: icache CacheBusW
-                         (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
-                         (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck) |
-                         (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2]) & ~CacheBusAck);
-
-  assign SelAdrData = (CurrState == STATE_ACCESS & (CacheRW[0] | AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
-                  (CurrState == STATE_FETCH) |
-                  (CurrState == STATE_WRITEBACK) |
-                  (CurrState == STATE_WRITE_LINE) |
-                  resetDelay;
-  assign SelAdrTag = (CurrState == STATE_ACCESS & (AnyMiss | (|CMOpM))) | // exclusion-tag: icache SelAdrTag // changes if store delay hazard removed
-                  (CurrState == STATE_FETCH) |
-                  (CurrState == STATE_WRITEBACK) |
-                  (CurrState == STATE_WRITE_LINE) |
-                  resetDelay;
-  assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_ADDRESS_SETUP;
-  assign CacheEn = (~Stall | StallConditions) | (CurrState != STATE_ACCESS) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn
-                       
-endmodule // cachefsm
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
deleted file mode 100644
index e2db5a46c..000000000
--- a/src/cache/cacheway.sv
+++ /dev/null
@@ -1,179 +0,0 @@
-///////////////////////////////////////////
-// cacheway
-//
-// Written: Rose Thompson rose@rosethompson.net 
-// Created: 7 July 2021
-// Modified: 20 January 2023
-//
-// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module cacheway import cvw::*; #(parameter cvw_t P, 
-                  parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
-                  OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
-  input  logic                        clk,
-  input  logic                        reset,
-  input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
-  input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
-  input  logic [$clog2(NUMSETS)-1:0]  CacheSetData,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
-  input  logic [$clog2(NUMSETS)-1:0]  CacheSetTag,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
-  input  logic [PA_BITS-1:0]          PAdr,           // Physical address 
-  input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
-  input  logic                        SetValid,       // Set the valid bit in the selected way and set
-  input  logic                        ClearValid,     // Clear the valid bit in the selected way and set
-  input  logic                        SetDirty,       // Set the dirty bit in the selected way and set
-  input  logic                        SelVictim,      // Overides HitWay Tag matching.  Selects selects the victim tag/data regardless of hit
-  input  logic                        ClearDirty,     // Clear the dirty bit in the selected way and set
-  input  logic                        FlushCache,       // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
-  input  logic                        VictimWay,      // LRU selected this way as victim to evict
-  input  logic                        FlushWay,       // This way is selected for flush and possible writeback if dirty
-  input  logic                        InvalidateCache,// Clear all valid bits
-  input  logic [LINELEN/8-1:0]        LineByteMask,   // Final byte enables to cache (D$ only)
-
-  output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
-  output logic                        HitWay,         // This way hits
-  output logic                        ValidWay,       // This way is valid
-  output logic                        HitDirtyWay,    // The hit way is dirty
-  output logic                        DirtyWay   ,    // The selected way is dirty
-  output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
-
-  logic [NUMSETS-1:0]                ValidBits;
-  logic [NUMSETS-1:0]                DirtyBits;
-  logic [LINELEN-1:0]                 ReadDataLine;
-  logic [TAGLEN-1:0]                  ReadTag;
-  logic                               Dirty;
-  logic                               SelecteDirty;
-  logic                               SelectedWriteWordEn;
-  logic [LINELEN/8-1:0]               FinalByteMask;
-  logic                               SetValidEN, ClearValidEN;
-  logic                               SetValidWay;
-  logic                               ClearValidWay;
-  logic                               SetDirtyWay;
-  logic                               ClearDirtyWay;
-  logic                               SelectedWay;
-  logic                               InvalidateCacheDelay;
-  
-  if (!READ_ONLY_CACHE) begin:flushlogic
-    mux2 #(1) seltagmux(VictimWay, FlushWay, FlushCache, SelecteDirty);
-    mux3 #(1) selectedmux(HitWay, FlushWay, VictimWay, {SelVictim, FlushCache}, SelectedWay);
-    // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
-    // coverage off -item e 1 -fecexprrow 3
-    // nonzero ways will never see FlushCache=0 while FlushWay=1 since FlushWay only advances on a subset of FlushCache assertion cases.
-  end else begin:flushlogic // no flush operation for read-only caches.
-    assign SelecteDirty = VictimWay;
-  mux2 #(1) selectedwaymux(HitWay, SelecteDirty, SelVictim , SelectedWay);
-  end
-
-
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Write Enable demux
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  assign SetValidWay = SetValid & SelectedWay;
-  assign ClearValidWay = ClearValid & SelectedWay;                             // exclusion-tag: icache ClearValidWay
-  assign SetDirtyWay = SetDirty & SelectedWay;                                 // exclusion-tag: icache SetDirtyWay
-  assign ClearDirtyWay = ClearDirty & SelectedWay;
-  assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;  // exclusion-tag: icache SelectedWiteWordEn
-  assign SetValidEN = SetValidWay & ~FlushStage;                           // exclusion-tag: cache SetValidEN
-  assign ClearValidEN = ClearValidWay & ~FlushStage;                       // exclusion-tag: cache ClearValidEN
-
-  // If writing the whole line set all write enables to 1, else only set the correct word.
-  assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Tag Array
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
-    .addr(CacheSetTag), .dout(ReadTag),
-    .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
-
-  // AND portion of distributed tag multiplexer
-  assign TagWay = SelectedWay ? ReadTag : 0; // AND part of AOMux
-  assign HitDirtyWay = Dirty & ValidWay;
-  assign DirtyWay = SelecteDirty & HitDirtyWay;                               // exclusion-tag: icache DirtyWay
-  assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay; // exclusion-tag: dcache HitWay
-
-  flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Data Array
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  genvar               words;
-
-  localparam           NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
-  localparam           SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
-  
-  for(words = 0; words < NUMSRAM; words++) begin: word
-    if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .we(SelectedWriteWordEn));
-    end else begin:wordram // D$ needs byte enables
-     ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
-     end
-  end
-
-  // AND portion of distributed read multiplexers
-  assign ReadDataLineWay = SelectedWay ? ReadDataLine : '0;  // AND part of AO mux.
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Valid Bits
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  
-  always_ff @(posedge clk) begin // Valid bit array, 
-    if (reset) ValidBits        <= '0;
-    if(CacheEn) begin 
-      ValidWay <= ValidBits[CacheSetTag];
-      if(InvalidateCache)                    ValidBits <= '0; // exclusion-tag: dcache invalidateway
-      else if (SetValidEN) ValidBits[CacheSetData] <= SetValidWay;
-      else if (ClearValidEN) ValidBits[CacheSetData] <= '0; // exclusion-tag: icache ClearValidBits
-    end
-  end
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Dirty Bits
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  // Dirty bits
-  if (!READ_ONLY_CACHE) begin:dirty
-    always_ff @(posedge clk) begin
-      // reset is optional.  Consider merging with TAG array in the future.
-      //if (reset) DirtyBits <= {NUMSETS{1'b0}}; 
-      if(CacheEn) begin
-        Dirty <= DirtyBits[CacheSetTag];
-        if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) begin
-          DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
-          if (CacheSetData == CacheSetTag) Dirty <= SetDirtyWay;
-          else Dirty <= DirtyBits[CacheSetTag];
-        end
-      end
-    end
-  end else assign Dirty = 1'b0;
-endmodule
diff --git a/src/cvw.sv b/src/cvw.sv
deleted file mode 100644
index ed0493484..000000000
--- a/src/cvw.sv
+++ /dev/null
@@ -1,303 +0,0 @@
-//////////////////////////////////////////
-// cvw.sv
-//
-// Written: David_Harris@hmc.edu 27 January 2022
-//
-// Purpose: package with shared CORE-V-Wally global parameters
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// Usiing global `define statements isn't ideal in a large SystemVerilog system because
-// of the risk of `define name conflicts across different subsystems.
-// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
-// that is referenced by all Wally modules but not by other subsystems.
-
-`ifndef CVW_T
-
-`define CVW_T 1
-
-package cvw;
-
-  `include "BranchPredictorType.vh"
-
-typedef struct packed {
-  int           XLEN;     // Machine width (32 or 64)
-  logic         IEEE754;  // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
-  int           MISA;     // Machine Instruction Set Architecture
-  int           AHBW;     // AHB bus width (usually = XLEN)
-  int           RAM_LATENCY; // Latency to stress AHB 
-  logic         BURST_EN; // Support AHB Burst Mode
-
-  // RISC-V Features
-  logic         ZICSR_SUPPORTED;
-  logic         ZIFENCEI_SUPPORTED;
-  logic [11:0]  COUNTERS;
-  logic         ZICNTR_SUPPORTED;
-  logic         ZIHPM_SUPPORTED;
-  logic         ZFH_SUPPORTED;
-  logic         ZFA_SUPPORTED;
-  logic         SSTC_SUPPORTED;
-  logic         VIRTMEM_SUPPORTED;
-  logic         VECTORED_INTERRUPTS_SUPPORTED;
-  logic         BIGENDIAN_SUPPORTED;
-  logic         SVADU_SUPPORTED;
-  logic         ZMMUL_SUPPORTED;
-  logic         ZICBOM_SUPPORTED;
-  logic         ZICBOZ_SUPPORTED;
-  logic         ZICBOP_SUPPORTED;
-  logic         ZICCLSM_SUPPORTED;
-  logic         ZICOND_SUPPORTED;
-  logic         SVPBMT_SUPPORTED;
-  logic         SVNAPOT_SUPPORTED;
-  logic         SVINVAL_SUPPORTED;
-  logic         ZAAMO_SUPPORTED;
-  logic         ZALRSC_SUPPORTED;
-
-  // Microarchitectural Features
-  logic         BUS_SUPPORTED;
-  logic         DCACHE_SUPPORTED;
-  logic         ICACHE_SUPPORTED;
-
-// TLB configuration.  Entries should be a power of 2
-  int           ITLB_ENTRIES;
-  int           DTLB_ENTRIES;
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
-  int           DCACHE_NUMWAYS;
-  int           DCACHE_WAYSIZEINBYTES;
-  int           DCACHE_LINELENINBITS;
-  int           ICACHE_NUMWAYS;
-  int           ICACHE_WAYSIZEINBYTES;
-  int           ICACHE_LINELENINBITS;
-  int           CACHE_SRAMLEN;
-
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
-  int           IDIV_BITSPERCYCLE;
-  logic         IDIV_ON_FPU;
-
-// Legal number of PMP entries are 0, 16, or 64
-  int           PMP_ENTRIES;
-
-// Address space
-  logic [63:0]  RESET_VECTOR;
-
-// WFI Timeout Wait
-  int           WFI_TIMEOUT_BIT;
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-  logic         DTIM_SUPPORTED;
-  logic [63:0]  DTIM_BASE;
-  logic [63:0]  DTIM_RANGE;
-  logic         IROM_SUPPORTED;
-  logic [63:0]  IROM_BASE;
-  logic [63:0]  IROM_RANGE;
-  logic         BOOTROM_SUPPORTED;
-  logic [63:0]  BOOTROM_BASE;
-  logic [63:0]  BOOTROM_RANGE;
-  logic         BOOTROM_PRELOAD;
-  logic         UNCORE_RAM_SUPPORTED;
-  logic [63:0]  UNCORE_RAM_BASE;
-  logic [63:0]  UNCORE_RAM_RANGE;
-  logic         UNCORE_RAM_PRELOAD;
-  logic         EXT_MEM_SUPPORTED;
-  logic [63:0]  EXT_MEM_BASE;
-  logic [63:0]  EXT_MEM_RANGE;
-  logic         CLINT_SUPPORTED;
-  logic [63:0]  CLINT_BASE;
-  logic [63:0]  CLINT_RANGE;
-  logic         GPIO_SUPPORTED;
-  logic [63:0]  GPIO_BASE;
-  logic [63:0]  GPIO_RANGE;
-  logic         UART_SUPPORTED;
-  logic [63:0]  UART_BASE;
-  logic [63:0]  UART_RANGE;
-  logic         PLIC_SUPPORTED;
-  logic [63:0]  PLIC_BASE;
-  logic [63:0]  PLIC_RANGE;
-  logic         SDC_SUPPORTED;
-  logic [63:0]  SDC_BASE;
-  logic [63:0]  SDC_RANGE;
-  logic         SPI_SUPPORTED;
-  logic [63:0]  SPI_BASE;
-  logic [63:0]  SPI_RANGE;
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-  logic         GPIO_LOOPBACK_TEST;
-  logic         SPI_LOOPBACK_TEST;
-
-// Hardware configuration
-  int           UART_PRESCALE ;
-
-// Interrupt configuration
-  int           PLIC_NUM_SRC;
-  logic         PLIC_NUM_SRC_LT_32;
-  int           PLIC_GPIO_ID;
-  int           PLIC_UART_ID;
-  int           PLIC_SPI_ID;
-  int           PLIC_SDC_ID;
-
-  logic                BPRED_SUPPORTED;
-  logic [31:0]         BPRED_TYPE;
-  int                  BPRED_NUM_LHR;
-  int                  BPRED_SIZE;
-  int                  BTB_SIZE;
-  int                  RAS_SIZE;
-  logic                INSTR_CLASS_PRED; // is class predictor enabled
-
-// FPU division architecture
-  int           RADIX;
-  int           DIVCOPIES;
-
-// bit manipulation
-  logic         ZBA_SUPPORTED;
-  logic         ZBB_SUPPORTED;
-  logic         ZBC_SUPPORTED;
-  logic         ZBS_SUPPORTED;
-
-// compressed
-  logic         ZCA_SUPPORTED;
-  logic         ZCB_SUPPORTED;
-  logic         ZCD_SUPPORTED;
-  logic         ZCF_SUPPORTED;
-
-// Cryptography
-  logic         ZBKB_SUPPORTED;
-  logic         ZBKC_SUPPORTED;
-  logic         ZBKX_SUPPORTED;
-  logic         ZKND_SUPPORTED;
-  logic         ZKNE_SUPPORTED;
-  logic         ZKNH_SUPPORTED;
-  logic         ZKN_SUPPORTED;
-
-// Memory synthesis configuration
-  logic         USE_SRAM;
-
-// constants defining different privilege modes
-// defined in Table 1.1 of the privileged spec
-  logic [1:0] M_MODE ;
-  logic [1:0] S_MODE ;
-  logic [1:0] U_MODE ;
-
-// Virtual Memory Constants
-  int VPN_SEGMENT_BITS;
-  int VPN_BITS;
-  int PPN_BITS;
-  int PA_BITS;
-  int SVMODE_BITS;
-  int ASID_BASE;
-  int ASID_BITS;
-
-// constants to check SATP_MODE against
-// defined in Table 4.3 of the privileged spec
-  logic [3:0] NO_TRANSLATE;
-  logic [3:0] SV32; 
-  logic [3:0] SV39;
-  logic [3:0] SV48;
-
-// macros to define supported modes
-  logic A_SUPPORTED;
-  logic B_SUPPORTED;
-  logic C_SUPPORTED;
-  logic D_SUPPORTED;
-  logic E_SUPPORTED;
-  logic F_SUPPORTED;
-  logic I_SUPPORTED;
-  logic M_SUPPORTED;
-  logic Q_SUPPORTED;
-  logic S_SUPPORTED;
-  logic U_SUPPORTED;
-  
-// logarithm of XLEN, used for number of index bits to select
-  int LOG_XLEN;
-
-// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
-  int PMPCFG_ENTRIES;
-
-// Floating point constants for Quad, Double, Single, and Half precisions
-  int         Q_LEN;
-  int         Q_NE;
-  int         Q_NF;
-  int         Q_BIAS;
-  logic [1:0] Q_FMT;
-  int         D_LEN;
-  int         D_NE;
-  int         D_NF;
-  int         D_BIAS;
-  logic [1:0] D_FMT;
-  int         S_LEN;
-  int         S_NE;
-  int         S_NF;
-  int         S_BIAS;
-  logic [1:0] S_FMT;
-  int         H_LEN;
-  int         H_NE;
-  int         H_NF;
-  int         H_BIAS;
-  logic [1:0] H_FMT;
-
-// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
-  int         FLEN;
-  int         LOGFLEN;
-  int         NE  ;
-  int         NF  ;
-  logic [1:0] FMT ;
-  int         BIAS;
-
-// Floating point constants needed for FPU paramerterization
-  int         FPSIZES;
-  int         FMTBITS;
-  int         LEN1 ;
-  int         NE1  ;
-  int         NF1  ;
-  logic [1:0] FMT1 ;
-  int         BIAS1;
-  int         LEN2 ;
-  int         NE2  ;
-  int         NF2  ;
-  logic [1:0] FMT2 ;
-  int         BIAS2;
-
-// largest length in IEU/FPU
-  int CVTLEN;
-  int LLEN;
-  int LOGCVTLEN;
-  int NORMSHIFTSZ;
-  int LOGNORMSHIFTSZ;
-  int FMALEN;
-
-// division constants
-  int LOGR       ;
-  int RK         ;
-  int FPDUR      ;
-  int DURLEN     ;
-  int DIVb       ;
-  int DIVBLEN    ;
-// integer division/remainder constants
-  int INTDIVb    ;
-} cvw_t;
-
-endpackage
-
-`endif
diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
deleted file mode 100644
index f3fc676b0..000000000
--- a/src/ebu/ahbcacheinterface.sv
+++ /dev/null
@@ -1,129 +0,0 @@
-///////////////////////////////////////////
-// ahbcacheinterface.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: August 29, 2022
-// Modified: 18 January 2023
-//
-// Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ahbcacheinterface import cvw::*; #(
-  parameter cvw_t P,
-  parameter BEATSPERLINE,  // Number of AHBW words (beats) in cacheline
-  parameter AHBWLOGBWPL,   // Log2 of ^
-  parameter LINELEN,       // Number of bits in cacheline
-  parameter LLENPOVERAHBW, // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
-  parameter READ_ONLY_CACHE
-)(
-  input  logic                HCLK, HRESETn,
-  // bus interface controls
-  input  logic                HREADY,                  // AHB peripheral ready
-  output logic [1:0]          HTRANS,                  // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                HWRITE,                  // AHB 0: Read operation 1: Write operation 
-  output logic [2:0]          HSIZE,                   // AHB transaction width
-  output logic [2:0]          HBURST,                  // AHB burst length
-  // bus interface buses
-  input  logic [P.AHBW-1:0]     HRDATA,                  // AHB read data
-  output logic [P.PA_BITS-1:0]  HADDR,                   // AHB address
-  output logic [P.AHBW-1:0]     HWDATA,                  // AHB write data
-  output logic [P.AHBW/8-1:0]   HWSTRB,                  // AHB byte mask
-  
-  // cache interface
-  input  logic [P.PA_BITS-1:0]  CacheBusAdr,            // Address of cache line
-  input  logic [P.LLEN-1:0]     CacheReadDataWordM,     // One word of cache line during a writeback
-  input  logic                CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
-  input  logic                Cacheable,              // Memory operation is cachable
-  input  logic [1:0]          CacheBusRW,             // Cache bus operation, 01: writeback, 10: fetch
-  output logic                CacheBusAck,            // Handshake to $ indicating bus transaction completed
-  output logic [LINELEN-1:0]  FetchBuffer,            // Register to hold beats of cache line as the arrive from bus
-  output logic [AHBWLOGBWPL-1:0] BeatCount,           // Beat position within the cache line in the Address Phase
-  output logic                SelBusBeat,             // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
-
-  // uncached interface 
-  input logic [P.PA_BITS-1:0]   PAdr,                    // Physical address of uncached memory operation
-  input logic [P.LLEN-1:0]      WriteDataM,              // IEU write data for uncached store
-  input logic [1:0]           BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
-  input logic                 BusAtomic,          // Uncache atomic memory operation
-  input logic [2:0]           Funct3,                  // Size of uncached memory operation
-  input logic                 BusCMOZero,               // Uncached cbo.zero must write zero to full sized cacheline without going through the cache
-
-  // lsu/ifu interface
-  input logic                 Stall,                   // Core pipeline is stalled
-  input logic                 Flush,                   // Pipeline stage flush. Prevents bus transaction from starting
-  output logic                BusStall,                // Bus is busy with an in flight memory operation
-  output logic                BusCommitted);           // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-  
-
-  localparam                  BeatCountThreshold = BEATSPERLINE - 1;  // Largest beat index
-  logic [P.PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
-  logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
-  logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
- logic [P.AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
-  logic [P.PA_BITS-1:0]         PAdrZero;
-
-  genvar                      index;
-
-  // fetch buffer is made of BEATSPERLINE flip-flops
-  for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer
-    logic [BEATSPERLINE-1:0] CaptureBeat;
-    assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed);
-    flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA),
-      .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW]));
-  end
-
-  assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr;
-  mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR);
-  assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR;
-
-  mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE));
-
-  // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data.
-  logic [P.AHBW-1:0]          CacheReadDataWordAHB;
-  if(LLENPOVERAHBW > 1) begin
-    logic [P.AHBW-1:0]          AHBWordSets [(LLENPOVERAHBW)-1:0];
-    genvar                     index;
-    for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux
-        assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)];
-    end
-    assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]];
-  end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0];      
-  
-  mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]),
-    .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
-  flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
-
-  if (READ_ONLY_CACHE) begin
-    assign HWSTRB = '0;
-  end else begin // compute byte mask for AHB transaction based on size and address.  AHBW may be different than LLEN
-    logic [P.AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
-     
-    swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
-    flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
-  end
-  
-  buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm(
-    .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
-    .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed,
-    .HREADY, .HTRANS, .HWRITE, .HBURST);
-endmodule
diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
deleted file mode 100644
index 5e5406c1f..000000000
--- a/src/ebu/ahbinterface.sv
+++ /dev/null
@@ -1,73 +0,0 @@
-///////////////////////////////////////////
-// ahbinterface.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: August 29, 2022
-// Modified: 18 January 2023
-//
-// Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ahbinterface #(
-  parameter XLEN,
-  parameter logic LSU = 1'b0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
-)( 
-  input  logic                          HCLK, HRESETn,
-  // bus interface
-  input  logic                          HREADY,       // AHB peripheral ready
-  output logic [1:0]                    HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                          HWRITE,       // AHB 0: Read operation 1: Write operation 
-  input  logic [XLEN-1:0]               HRDATA,       // AHB read data
-  output logic [XLEN-1:0]               HWDATA,       // AHB write data
-  output logic [XLEN/8-1:0]             HWSTRB,       // AHB byte mask
-  
-  // lsu/ifu interface
-  input  logic                          Stall,        // Core pipeline is stalled
-  input  logic                          Flush,        // Pipeline stage flush. Prevents bus transaction from starting
-  input  logic [1:0]                    BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input  logic                          BusAtomic,    // Uncache atomic memory operation
-  input  logic [XLEN/8-1:0]             ByteMask,     // Bytes enables within a word
-  input  logic [XLEN-1:0]               WriteData,    // IEU write data for a store
-  output logic                          BusStall,     // Bus is busy with an in flight memory operation
-  output logic                          BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-  output logic [XLEN-1:0]  FetchBuffer   // Register to hold HRDATA after arriving from the bus
-);
-  
-  logic                                 CaptureEn;
-
-  flopen #(XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(FetchBuffer));
-
-  if(LSU) begin
-    // delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN    
-    flop #(XLEN)   wdreg(HCLK, WriteData, HWDATA); 
-    flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
-  end else begin
-    assign HWDATA = '0;
-    assign HWSTRB = '0;
-  end    
-
-  busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic,
-    .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
-    .HTRANS, .HWRITE);
-
-endmodule
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
deleted file mode 100644
index f81bfa67a..000000000
--- a/src/ebu/buscachefsm.sv
+++ /dev/null
@@ -1,168 +0,0 @@
-///////////////////////////////////////////
-// busfsm.sv
-//
-// Written: Rose Thompson rose@rosethompson.net 
-// Created: December 29, 2021
-// Modified: 18 January 2023 
-//
-// Purpose: Controller for cache to AHB bus interface
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// HCLK and clk must be the same clock!
-module buscachefsm #(
-  parameter BeatCountThreshold,                      // Largest beat index
-  parameter AHBWLOGBWPL,                             // Log2 of BEATSPERLINE
-  parameter READ_ONLY_CACHE,                         // 1 for read-only instruction cache
-  parameter BURST_EN                                 // burst mode supported
-)(
-  input  logic                   HCLK,
-  input  logic                   HRESETn,
-
-  // IEU interface
-  input  logic                   Stall,              // Core pipeline is stalled
-  input  logic                   Flush,              // Pipeline stage flush. Prevents bus transaction from starting
-  input  logic [1:0]             BusRW,              // Uncached memory operation read/write control: 10: read, 01: write
-  input  logic                   BusAtomic,          // Uncache atomic memory operation
-  input  logic                   BusCMOZero,         // Uncached cbo.zero must write zero to full sized cacheline without going through the cache
-  output logic                   BusStall,           // Bus is busy with an in flight memory operation
-  output logic                   BusCommitted,       // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-                            
-  // ahb cache interface locals.            
-  output logic                   CaptureEn,          // Enable updating the Fetch buffer with valid data from HRDATA
-                            
-  // cache interface                  
-  input  logic [1:0]             CacheBusRW,         // Cache bus operation, 01: writeback, 10: fetch
-  output logic                   CacheBusAck,        // Handshack to $ indicating bus transaction completed
-  
-  // lsu interface
-  output logic [AHBWLOGBWPL-1:0] BeatCount,          // Beat position within the cache line in the Address Phase
-  output logic [AHBWLOGBWPL-1:0] BeatCountDelayed,   // Beat within the cache line in the second (Data) cache stage
-  output logic                   SelBusBeat,         // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
-
-  // BUS interface
-  input  logic                   HREADY,             // AHB peripheral ready
-  output logic [1:0]             HTRANS,             // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                   HWRITE,             // AHB 0: Read operation 1: Write operation 
-  output logic [2:0]             HBURST              // AHB burst length
-);
-  
-  typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, ATOMIC_READ_DATA_PHASE, ATOMIC_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
-  typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
-
-  busstatetype CurrState, NextState;
-
-  logic [AHBWLOGBWPL-1:0] NextBeatCount;
-  logic                   FinalBeatCount;
-  logic [2:0]             LocalBurstType;
-  logic                   BeatCntEn;
-  logic                   BeatCntReset;
-  logic                   CacheAccess;
-  logic                   BusWrite;
-
-  assign BusWrite = (CacheBusRW[0] | BusCMOZero) & ~READ_ONLY_CACHE;
-  
-  always_ff @(posedge HCLK)
-    if (~HRESETn | Flush) CurrState <= ADR_PHASE;
-    else                  CurrState <= NextState;  
-  
-  always_comb begin
-      case(CurrState)
-        ADR_PHASE: if (HREADY & |BusRW)                               NextState = DATA_PHASE;             // exclusion-tag: buscachefsm HREADY0
-                   else if (HREADY & BusWrite & ~READ_ONLY_CACHE)     NextState = CACHE_WRITEBACK;        // exclusion-tag: buscachefsm HREADY1
-                   else if (HREADY & CacheBusRW[1])                   NextState = CACHE_FETCH;            // exclusion-tag: buscachefsm HREADYread
-                   else                                               NextState = ADR_PHASE;
-        DATA_PHASE:  if(HREADY & BusAtomic & ~READ_ONLY_CACHE)        NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
-                     else if(HREADY & ~BusAtomic)                     NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
-                     else                                             NextState = DATA_PHASE;
-        ATOMIC_READ_DATA_PHASE: if(HREADY)                            NextState = ATOMIC_PHASE;           // exclusion-tag: buscachefsm AtomicReadData
-                    else                                              NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm AtomicElse
-        ATOMIC_PHASE: if(HREADY)                                      NextState = MEM3;                   // exclusion-tag: buscachefsm AtomicPhase
-                      else                                            NextState = ATOMIC_PHASE;           // exclusion-tag: buscachefsm AtomicWait
-        MEM3:        if(Stall)                                        NextState = MEM3;
-                     else                                             NextState = ADR_PHASE;
-        CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0])      NextState = CACHE_WRITEBACK;  // exclusion-tag: buscachefsm FetchWriteback
-                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;      // exclusion-tag: buscachefsm FetchWait
-                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
-                     else                                             NextState = CACHE_FETCH;
-        CACHE_WRITEBACK:  if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
-                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;     // exclusion-tag: buscachefsm HREADY4
-                     else if(HREADY & FinalBeatCount & BusCMOZero)    NextState = MEM3;            // exclusion-tag: buscachefsm HREADY5
-                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;       // exclusion-tag: buscachefsm HREADY6
-                     else                                             NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback2
-        default:                                                      NextState = ADR_PHASE;
-      endcase
-  end
-
-  // IEU, LSU, and IFU controls
-  // Used to store data from data phase of AHB.
-  flopenr #(AHBWLOGBWPL) BeatCountReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, NextBeatCount, BeatCount);  
-  flopenr #(AHBWLOGBWPL) BeatCountDelayedReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, BeatCount, BeatCountDelayed);
-  assign NextBeatCount = BeatCount + 1'b1;
-
-  assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[AHBWLOGBWPL-1:0];
-  assign BeatCntEn = (((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) |
-                     (NextState == ADR_PHASE & |CacheBusRW & HREADY)) & ~Flush;
-  assign BeatCntReset = NextState == ADR_PHASE;
-
-  assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1] & ~Flush) | (CurrState == CACHE_FETCH & HREADY);
-  assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
-
-  assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) |
-                    (CurrState == DATA_PHASE) | 
-                    (CurrState == ATOMIC_PHASE) |
-                    (CurrState == ATOMIC_READ_DATA_PHASE) |
-                    (CurrState == CACHE_FETCH & ~FinalBeatCount) |
-                    (CurrState == CACHE_WRITEBACK & ~FinalBeatCount);
-  
-  assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY_CACHE & CurrState == MEM3);
-
-  // AHB bus interface
-  assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) |
-                  (CurrState == ATOMIC_READ_DATA_PHASE) | 
-                  (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
-                  (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
-
-  assign HWRITE = (((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | 
-                  (CurrState == CACHE_WRITEBACK & |BeatCount)) & ~READ_ONLY_CACHE;
-  assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;  
-  
-  always_comb begin
-    case(BeatCountThreshold)
-      0:        LocalBurstType = 3'b000;
-      3:        LocalBurstType = 3'b011; // INCR4
-      7:        LocalBurstType = 3'b101; // INCR8
-      15:       LocalBurstType = 3'b111; // INCR16
-      default:  LocalBurstType = 3'b001; // INCR without end.
-    endcase
-  end
-
-  // communication to cache
-  assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount & ~BusCMOZero);
-  assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | BusWrite)) |
-                      (CurrState == DATA_PHASE & BusRW[0]) |
-                      (CurrState == ATOMIC_PHASE & BusRW[0]) |
-                      (CurrState == ATOMIC_READ_DATA_PHASE & BusRW[0]) |
-                      (CurrState == CACHE_WRITEBACK) |
-                      (CurrState == CACHE_FETCH);
-
-endmodule
diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv
deleted file mode 100644
index 642eb6de4..000000000
--- a/src/ebu/ebu.sv
+++ /dev/null
@@ -1,132 +0,0 @@
-///////////////////////////////////////////
-// abhmulticontroller
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: August 29, 2022
-// Modified: 18 January 2023
-//
-// Purpose: AHB multi controller interface to merge LSU and IFU controls.
-//          See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
-//          Arbitrates requests from instruction and data streams
-//          Connects core to peripherals and I/O pins on SOC
-//          Bus width presently matches XLEN
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ebu import cvw::*;  #(parameter cvw_t P) (
-  input  logic                clk, reset,
-  // Signals from IFU
-  input  logic [1:0]          IFUHTRANS, // IFU AHB transaction request
-  input  logic [2:0]          IFUHSIZE,  // IFU AHB transaction size
-  input  logic [2:0]          IFUHBURST, // IFU AHB burst length
-  input  logic [P.PA_BITS-1:0]  IFUHADDR,  // IFU AHB address
-  output logic                IFUHREADY, // AHB peripheral ready gated by possible non-grant
-  // Signals from LSU
-  input  logic [1:0]          LSUHTRANS, // LSU AHB transaction request
-  input  logic                LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
-  input  logic [2:0]          LSUHSIZE,  // LSU AHB size
-  input  logic [2:0]          LSUHBURST, // LSU AHB burst length
-  input  logic [P.PA_BITS-1:0]  LSUHADDR,  // LSU AHB address
-  input  logic [P.XLEN-1:0]     LSUHWDATA, // initially support AHBW = XLEN
-  input  logic [P.XLEN/8-1:0]   LSUHWSTRB, // AHB byte mask
-  output logic                LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
-
-  // AHB-Lite external signals
-  output logic                HCLK, HRESETn, 
-  input  logic                HREADY,    // AHB peripheral ready
-  input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error.  Presently ignored.
-  output logic [P.PA_BITS-1:0]  HADDR,     // AHB address to peripheral after arbitration
-  output logic [P.AHBW-1:0]     HWDATA,    // AHB Write data after arbitration
-  output logic [P.XLEN/8-1:0]   HWSTRB,    // AHB byte write enables after arbitration
-  output logic                HWRITE,    // AHB transaction direction after arbitration
-  output logic [2:0]          HSIZE,     // AHB transaction size after arbitration
-  output logic [2:0]          HBURST,    // AHB burst length after arbitration
-  output logic [3:0]          HPROT,     // AHB protection.  Wally does not use
-  output logic [1:0]          HTRANS,    // AHB transaction request after arbitration
-  output logic                HMASTLOCK  // AHB master lock.  Wally does not use
-);
-
-  logic                       LSUDisable;
-  logic                       LSUSelect;
-  logic                       IFUSave;
-  logic                       IFURestore;
-  logic                       IFUDisable;
-  logic                       IFUSelect;
-
-  logic [P.PA_BITS-1:0]         IFUHADDROut;
-  logic [1:0]                 IFUHTRANSOut;
-  logic [2:0]                 IFUHBURSTOut;
-  logic [2:0]                 IFUHSIZEOut;
-  logic                       IFUHWRITEOut;
-  
-  logic [P.PA_BITS-1:0]         LSUHADDROut;
-  logic [1:0]                 LSUHTRANSOut;
-  logic [2:0]                 LSUHBURSTOut;
-  logic [2:0]                 LSUHSIZEOut;
-  logic                       LSUHWRITEOut;
-
-  logic                       IFUReq;
-  logic                       LSUReq;
-
-  assign HCLK = clk;
-  assign HRESETn = ~reset;
-
-  // if two requests come in at once pick one to select and save the others Address phase
-  // inputs.  Abritration scheme is LSU always goes first.
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // input stages and muxing for IFU and LSU
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
-    .Request(IFUReq),
-    .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
-    .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
-    .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
-
-  // LSU always has priority so there should never be a need to save and restore the address phase inputs.
-  controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
-    .Request(LSUReq),
-    .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
-    .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
-    .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
-
-  // output mux 
-  assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;
-  assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; 
-  assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
-  assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
-  assign HWRITE = LSUSelect ? LSUHWRITEOut : '0;
-  assign HPROT = {3'b001, LSUSelect}; // treat as privileged access of either Opcode fetch or Data access
-  assign HMASTLOCK = 1'b0; // no locking supported
-
-  // data phase muxing.  This would be a mux if IFU wrote data.
-  assign HWDATA = LSUHWDATA;
-  assign HWSTRB = LSUHWSTRB;
-  // HRDATA is sent to all controllers at the core level.
-
-  ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave,
-          .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect);
-  
-endmodule
-
-
diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv
deleted file mode 100644
index 853acd09b..000000000
--- a/src/ebu/ebufsmarb.sv
+++ /dev/null
@@ -1,121 +0,0 @@
-///////////////////////////////////////////
-// ebufsmarb.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 23 January 2023
-// Modified: 23 January 2023
-//
-// Purpose: Arbitrates requests from instruction and data streams
-//          LSU has priority.
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ebufsmarb (
-  input  logic       HCLK,
-  input  logic       HRESETn,
-  input  logic [2:0] HBURST,
- //  AHB burst length
-  
-  input  logic       HREADY,
-
-  input  logic       LSUReq,
-  input  logic       IFUReq,
-  
-  output logic       IFUSave,
-  output logic       IFURestore,
-  output logic       IFUDisable,
-  output logic       IFUSelect,
-  output logic       LSUDisable,
-  output logic       LSUSelect);
-  
-  typedef enum       logic [1:0] {IDLE, ARBITRATE} statetype;
-  statetype          CurrState, NextState;
-
-  logic              both;                       // Both the LSU and IFU request at the same time
-  logic              IFUReqDelay;                    // 1 cycle delayed IFU request. Part of arbitration
-  logic              FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
-  logic              BeatCntEn;
-  logic [3:0]        BeatCount;                  // Position within a burst transfer
-  logic              BeatCntReset;
-  logic [3:0]        Threshold;                  // Number of beats derived from HBURST
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Aribtration scheme
-  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
-  // a burst is completed.
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  assign both = LSUReq & IFUReq;
-  flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
-  always_comb 
-    case (CurrState) 
-      IDLE:      if (both)                                      NextState = ARBITRATE; 
-                 else                                           NextState = IDLE;
-      ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq))  NextState = IDLE;
-                 else                                           NextState = ARBITRATE;
-      default:                                                  NextState = IDLE;
-    endcase
-
-  // basic arb always selects LSU when both
-  // replace this block for more sophisticated arbitration as needed.
-  // Controller 0 (IFU)
-  assign IFUSave = CurrState == IDLE & both;
-  assign IFURestore = CurrState == ARBITRATE;
-  assign IFUDisable = CurrState == ARBITRATE;
-  assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
-  // Controller 1 (LSU)
-  // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
-  // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
-  // priority and re-issuing the same memory operation, the delayed IFUReqDelay squashes the LSU request.
-  // This is necessary because the pipeline is stalled for the entire duration of both transactions,
-  // and the LSU memory request will stil be active.
-  flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay);
-  assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD));
-  assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq;
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Burst mode logic
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  assign BeatCntReset = NextState == IDLE;
-  assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
-  // Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently.  
-  // LSU has priority. HREADY serves double duty during a burst transaction.  It indicates when the
-  // beat completes and when the transaction finishes.  However there is nothing external to
-  // differentiate them.  The EBU counts the HREADY beats so it knows when to switch to the IFU's 
-  // request.
-  assign BeatCntEn = (NextState == ARBITRATE) & HREADY; 
-  counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount);  
- 
-  // Used to store data from data phase of AHB.
-  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD);
-
-  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1.
-  //  HBURST[2:1] Beats  threshold
-  //  00          1      0
-  //  01          4      3
-  //  10          8      7
-  //  11          16     15
-  always_comb 
-    if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
-    else                      Threshold = ('d2 << HBURST[2:1]) - 'd1;
-endmodule
diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
deleted file mode 100755
index 682e492be..000000000
--- a/src/fpu/fcmp.sv
+++ /dev/null
@@ -1,170 +0,0 @@
-///////////////////////////////////////////
-// fcmp.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: Floating-point comparison unit
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// OpCtrl values
-//    110   min
-//    101   max
-//    010   equal
-//    001   less than
-//    011   less than or equal
-
-module fcmp import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0]   Fmt,           // format of fp number
-  input  logic [2:0]             OpCtrl,        // see above table
-  input  logic                   Zfa,           // Zfa variants: fminm, fmaxm, fleq, fltq
-  input  logic                   Xs, Ys,        // input signs
-  input  logic [P.NE-1:0]        Xe, Ye,        // input exponents
-  input  logic [P.NF:0]          Xm, Ym,        // input mantissa
-  input  logic                   XZero, YZero,  // is zero
-  input  logic                   XNaN, YNaN,    // is NaN
-  input  logic                   XSNaN, YSNaN,  // is signaling NaN
-  input  logic [P.FLEN-1:0]      X, Y,          // original inputs (before unpacker)
-  output logic                   CmpNV,         // invalid flag
-  output logic [P.FLEN-1:0]      CmpFpRes,      // compare floating-point result
-  output logic [P.XLEN-1:0]      CmpIntRes      // compare integer result
-);
-
-  logic LTabs, LT, EQ;          // is X < or > or = Y
-  logic [P.FLEN-1:0] NaNRes;    // NaN result
-  logic BothZero;               // are both inputs zero
-  logic EitherNaN, EitherSNaN;  // are either input a (signaling) NaN
-  
-  assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers
-  assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison
-  assign EQ = (X == Y);
-
-  assign BothZero = XZero&YZero;
-  assign EitherNaN = XNaN|YNaN;
-  assign EitherSNaN = XSNaN|YSNaN;
-
-  // flags
-  //    Min/Max - if an input is a signaling NaN set invalid flag
-  //    LT/LE - signaling - sets invalid if NaN input
-  //    EQ - quiet - sets invalid if signaling NaN input
-  always_comb begin
-    casez (OpCtrl[2:0])
-        3'b110: CmpNV = EitherSNaN; //min 
-        3'b101: CmpNV = EitherSNaN; //max
-        3'b010: CmpNV = EitherSNaN; //equal
-        3'b0?1: if (P.ZFA_SUPPORTED) 
-                  CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid
-                else CmpNV = EitherNaN;                 // flt, fle
-        3'b100: CmpNV = 1'b0;
-        default: CmpNV = 1'bx;
-    endcase
-  end 
-
-  // fmin/fmax of two NaNs returns a quiet NaN of the appropriate size
-  // for IEEE, return the payload of X
-  // for RISC-V, return the canonical NaN
-
-  // select the NaN result
-  if (P.FPSIZES == 1)
-    if(P.IEEE754) assign NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-    else          assign NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-
-  else if (P.FPSIZES == 2) 
-    if(P.IEEE754) assign NaNRes = Fmt ? {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
-    else          assign NaNRes = Fmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-  
-  else if (P.FPSIZES == 3)
-    always_comb
-          case (Fmt)
-              P.FMT:  
-                if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-                else         NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-              P.FMT1:
-                if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN1{1'b1}}, Xs, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
-                else         NaNRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-              P.FMT2:
-                if(P.IEEE754) NaNRes = {{P.FLEN-P.LEN2{1'b1}}, Xs, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
-                else         NaNRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
-              default:        NaNRes = {P.FLEN{1'bx}};
-          endcase
-
-  else if (P.FPSIZES == 4)
-    always_comb
-          case (Fmt)
-              2'h3:  
-                if(P.IEEE754) NaNRes = {Xs, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-                else         NaNRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-              2'h1:  
-                if(P.IEEE754) NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, Xs, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
-                else         NaNRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
-              2'h0: 
-                if(P.IEEE754) NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, Xs, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
-                else         NaNRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
-              2'h2:
-                if(P.IEEE754) NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, Xs, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
-                else         NaNRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
-          endcase
-
-  // Min/Max
-  //    - outputs the min/max of X and Y
-  //    - -0 < 0
-  //    - if both are NaN return quiet X
-  //    - if one is a NaN output the non-NaN
-  always_comb
-    if(OpCtrl[0]) // MAX
-        if (Zfa & P.ZFA_SUPPORTED) // fmaxm perform IEEE754 maxNum that produce NaN if either input is NaN
-          if (XNaN | YNaN) CmpFpRes = NaNRes; // either input is NaN
-          else
-            if (LT) CmpFpRes = Y; // X < Y
-            else    CmpFpRes = X; // X > Y
-        else // fmax performs IEEE754 maxNumber that produces NaN if both inputs are NaN
-          if(XNaN)
-            if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
-            else        CmpFpRes = Y;        // X = NaN Y != NaN
-          else
-            if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
-            else // X,Y != NaN
-                if(LT)  CmpFpRes = Y;        // X < Y
-                else    CmpFpRes = X;        // X > Y
-    else  // MIN
-        if (Zfa & P.ZFA_SUPPORTED) // fminm perform IEEE754 minNum that produce NaN if either input is NaN
-          if (XNaN | YNaN) CmpFpRes = NaNRes; // either input is NaN
-          else
-            if (LT) CmpFpRes = X; // X < Y
-            else    CmpFpRes = Y; // X > Y
-        else // fmin performs IEEE754 minNumber that produces NaN if both inputs are NaN
-          if(XNaN)
-            if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
-            else        CmpFpRes = Y;        // X = NaN Y != NaN
-          else
-            if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
-            else // X,Y != NaN
-                if(LT)  CmpFpRes = X;        // X < Y
-                else    CmpFpRes = Y;        // X > Y
-                                  
-  // LT/LE/EQ
-  //    - -0 = 0
-  //    - inf = inf and -inf = -inf
-  //    - return 0 if comparison with NaN (unordered)
-  assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
-endmodule
diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
deleted file mode 100755
index 805d56857..000000000
--- a/src/fpu/fctrl.sv
+++ /dev/null
@@ -1,388 +0,0 @@
-///////////////////////////////////////////
-// fctrl.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: floating-point control unit
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fctrl import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk,
-  input  logic                 reset,
-  // input control signals
-  input  logic                 StallE, StallM, StallW,             // stall signals
-  input  logic                 FlushE, FlushM, FlushW,             // flush signals
-  input  logic                 IntDivE,                            // is inteteger division
-  input  logic [2:0]           FRM_REGW,                           // rounding mode from CSR
-  input  logic [1:0]           STATUS_FS,                          // is FPU enabled?
-  input  logic                 FDivBusyE,                          // is the divider busy
-  // instruction                                                   
-  input  logic [31:0]          InstrD,                             // the full instruction
-  input  logic [6:0]           Funct7D,                            // bits 31:25 of instruction - may contain precision
-  input  logic [6:0]           OpD,                                // bits 6:0 of instruction
-  input  logic [4:0]           Rs2D,                               // bits 24:20 of instruction
-  input  logic [2:0]           Funct3D,                            // bits 14:12 of instruction - may contain rounding mode
-  // input mux selections                                         
-  output logic                 XEnD, YEnD, ZEnD,                   // enable inputs
-  output logic                 XEnE, YEnE, ZEnE,                   // enable inputs
-  // operation mux selections                                    
-  output logic                 FCvtIntE, FCvtIntW,                 // convert to integer operation
-  output logic [2:0]           FrmE, FrmM,                          // FP rounding mode
-  output logic [P.FMTBITS-1:0] FmtE, FmtM,                         // FP format
-  output logic [2:0]           OpCtrlE, OpCtrlM,                   // Select which operation to do in each component
-  output logic                 FpLoadStoreM,                       // FP load or store instruction
-  output logic [1:0]           PostProcSelE, PostProcSelM,         // select result in the post processing unit
-  output logic [1:0]           FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
-  output logic                 FPUActiveE,                         // FP instruction being executed
-  output logic                 ZfaE, ZfaM,                         // Zfa variants of instructions (fli, fminm, fmaxm, fround, froundnx, fleq, fltq, fmvh, fmvp, fcvtmod)
-  output logic                 ZfaFRoundNXE,                       // Zfa froundnx instruction
-  // register control signals
-  output logic                 FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
-  output logic                 FWriteIntE, FWriteIntM,             // Write to integer register
-  output logic [4:0]           Adr1D, Adr2D, Adr3D,                // adresses of each input
-  output logic [4:0]           Adr1E, Adr2E, Adr3E,                // adresses of each input
-  // other control signals
-  output logic                 IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
-  output logic                 FDivStartE, IDivStartE              // Start division or squareroot
-  );
-
-  `define FCTRLW 14
-
-  logic [`FCTRLW-1:0]          ControlsD;                          // control signals
-  logic                        FRegWriteD;                         // FP register write enable
-  logic                        FDivStartD;                         // start division/sqrt
-  logic                        FWriteIntD;                         // integer register write enable
-  logic [2:0]                  OpCtrlD;                            // Select which operation to do in each component
-  logic [1:0]                  PostProcSelD;                       // select result in the post processing unit
-  logic [1:0]                  FResSelD;                           // Select one of the results that finish in the memory stage
-  logic [2:0]                  FrmD;                               // FP rounding mode
-  logic [P.FMTBITS-1:0]        FmtD;                               // FP format
-  logic [1:0]                  Fmt, Fmt2;                          // format - before possible reduction
-  logic                        SupportedFmt;                       // is the format supported
-  logic                        SupportedFmt2;                      // is the source format supported for fp -> fp
-  logic                        SupportedRM;                        // is the rounding mode supported
-  logic                        FCvtIntD, FCvtIntM;                 // convert to integer operation
-  logic                        ZfaD;                               // Zfa variants of instructions
-  logic                        ZfaFRoundNXD;                       // Zfa froundnx instruction
-
-  // FPU Instruction Decoder
-  assign Fmt = Funct7D[1:0];
-  assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp
-
-  assign SupportedFmt =  (Fmt == 2'b00  | (Fmt == 2'b01 & P.D_SUPPORTED) |
-                         (Fmt == 2'b10 & P.ZFH_SUPPORTED)  | (Fmt == 2'b11 & P.Q_SUPPORTED));
-  assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) |
-                         (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED));
-  // rounding modes 5 and 6 are reserved.  Rounding mode 7 is dynamic, and is reserved if FRM is 5, 6, or 7
-  assign SupportedRM =  ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) |
-                         (OpD == 7'b1010011 & Funct3D == 3'b101 & Funct7D[6:2] == 5'b10100 & P.ZFA_SUPPORTED); // Zfa fltq has a funny rounding mode
-  /*assign SupportedRM =  ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) |
-                          (OpD == 7'b1010011 & P.ZFA_SUPPORTED);
-*/
-  // decode the instruction                       
-  // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX
-  always_comb
-    if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0;
-    else if (OpD != 7'b0000111 & OpD != 7'b0100111 & (~SupportedFmt | ~SupportedRM)) 
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format and rounding mode
-    else begin 
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // default: non-implemented instruction
-      /* verilator lint_off CASEINCOMPLETE */   // default value above has priority so no other default needed
-      case(OpD)
-        7'b0000111: case(Funct3D)
-                      3'b010:                       ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flw
-                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // fld
-                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flq
-                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flh
-                    endcase
-        7'b0100111: case(Funct3D)
-                      3'b010:                       ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsw
-                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsd
-                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsq
-                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsh
-                    endcase
-        7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0_0_0; // fmadd
-        7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0_0_0; // fmsub
-        7'b1001011:   ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0_0_0; // fnmsub
-        7'b1001111:   ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0_0_0; // fnmadd
-        7'b1010011: casez(Funct7D)
-                      7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0_0_0; // fadd
-                      7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0_0_0; // fsub
-                      7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0_0_0; // fmul
-                      7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0_0_0; // fdiv
-                      7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0_0_0; // fsqrt
-                      7'b00100??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0_0_0; // fsgnj
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0_0_0; // fsgnjn
-                                    3'b010:  ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0_0_0; // fsgnjx
-                                  endcase
-                      7'b00101??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_0_0; // fmin
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_0_0; // fmax
-                                    3'b010:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_1_0; // fminm  (Zfa)
-                                    3'b011:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_1_0; // fmaxm  (Zfa)
-                                  endcase
-                      7'b10100??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_0_0; // fle
-                                    3'b001:  ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_0_0; // flt
-                                    3'b010:  ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0_0_0; // feq
-                                    3'b100:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_1_0; // fleq  (Zfa)
-                                    3'b101:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_1_0; // fltq  (Zfa)
-                                  endcase
-                      7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
-                                                ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
-                                  else if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
-                                    if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01)) // coverage-tag: fmv fp to int
-                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h  fp to int register (double only in RV64)
-                                  end else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d  (Zfa) 
-                                  //  Q not supported in RV64GC
-                                  // coverage off   
-                                  else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q  (Zfa)
-                                  // coverage on
-                      7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) begin
-                                    if (Fmt[1:0] == 2'b00 | Fmt[1:0] == 2'b10 | (P.XLEN == 64 & Fmt[1:0] == 2'b01))  // coverage-tag: fmv int to fp
-                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h.x  int to fp reg (double only in RV64)
-                                  end else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli  (Zfa)
-                      7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0_0; // fcvt.s.(d/q/h)
-                                  else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.s  (Zfa) 
-                                  else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.s  (Zfa) 
-                      7'b0100001: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b01)
-                                                ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0_0_0; // fcvt.d.(s/h/q)
-                                  else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.d  (Zfa)
-                                  else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.d  (Zfa)
-                      7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
-                                                ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0_0_0; // fcvt.h.(s/d/q)
-                                  else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.h  (Zfa)
-                                  else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.h  (Zfa)
-                      // coverage off
-                      // Not covered in testing because rv64gc does not support quad precision
-                      7'b0100011: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b11)
-                                                ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0_0_0; // fcvt.q.(s/h/d)
-                                  else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.q  (Zfa)
-                                  else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.q  (Zfa)
-                      // coverage on
-                      7'b1101000: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w   w->s
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.s.wu wu->s
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l   l->s
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s
-                                  endcase
-                      7'b1100000: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.s   s->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.s  s->wu
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s   s->l
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s  s->lu
-                                  endcase
-                      7'b1101001: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.d.w   w->d
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.d.wu wu->d
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l   l->d
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d
-                                  endcase
-                      7'b1100001: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.d   d->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.d  d->wu
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d   d->l
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d  d->lu
-                                    5'b01000: if (P.ZFA_SUPPORTED & P.D_SUPPORTED & Funct3D == 3'b001) 
-                                                 ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1_0; // fcvtmod.w.d (Zfa)
-                                  endcase
-                      7'b1101010: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.h.w   w->h
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.h.wu wu->h
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l   l->h
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h
-                                  endcase
-                      7'b1100010: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.h   h->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.h  h->wu
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h   h->l
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h  h->lu
-                                  endcase
-                      // Not covered in testing because rv64gc does not support quad precision
-                      // coverage off
-                      7'b1101011: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.q.w   w->q
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.q.wu wu->q
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l   l->q
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q
-                                  endcase
-                      7'b1100011: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.q   q->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.q  q->wu
-                                    5'b00010:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q   q->l
-                                    5'b00011:    if (P.XLEN == 64) ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q  q->lu
-                                  endcase
-                      // coverage off
-                      // Not covered in testing because rv64gc is not RV64Q or RV32D
-                      7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) 
-                                                  ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_1_0; // fmvp.d.x  (Zfa) 
-                      7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) 
-                                                  ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_1_0; // fmvp.q.x  (Zfa)
-                      // coverage on
-                   endcase
-      endcase
-    end
-    /* verilator lint_on CASEINCOMPLETE */
-
-  // unswizzle control bits
-  assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD, ZfaFRoundNXD} = ControlsD;
-  
-  // rounding modes:
-  //    000 - round to nearest, ties to even
-  //    001 - round twords 0 - round to min magnitude
-  //    010 - round down - round twords negative infinity
-  //    011 - round up - round twords positive infinity
-  //    100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
-  //    111 - dynamic - choose FRM_REGW as rounding mode
-  assign FrmD = (Funct3D == 3'b111) ? FRM_REGW : Funct3D;
-
-  // Precision
-  //    00 - single
-  //    01 - double
-  //    10 - half
-  //    11 - quad
-  
-    if (P.FPSIZES == 1)
-      assign FmtD = 1'b0;
-    else if (P.FPSIZES == 2) begin
-      logic [1:0] FmtTmp;
-      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
-      assign FmtD = (P.FMT == FmtTmp);
-    end else if (P.FPSIZES == 3|P.FPSIZES == 4)
-      assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : Funct7D[1:0];
-
-  // Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
-  // When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic.
-  
-  //    X - all except int->fp, store, load, mv int->fp
-  assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)|                                                 // load/store
-                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float
-                  ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2]));                           // cvt int to float
-
-  //    Y - all except cvt, mv, load, class, sqrt
-  assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|                                     // load or class 
-                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float as above
-                  ((FResSelD==2'b11)&(PostProcSelD==2'b00))|                                       // mv float to int 
-                  ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
-
-  //    Z - fma ops only
-  assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]);                                    // fma, add, sub   
-
-  //  Final Res Sel:
-  //        fp      int
-  //  00  other     cmp
-  //  01  postproc  cvt
-  //  10  store     class
-  //  11            mv
-
-  //  post processing Sel:
-  //  00  cvt
-  //  01  div
-  //  10  fma
-
-  //  Other Sel:
-  //    Ctrl signal = {OpCtrl[2], &FOpctrl[1:0]}
-  //        000 - sign            00
-  //        001 - negate sign     00
-  //        010 - xor sign        00
-  //        011 - mv to fp        01
-  //        110 - min             10
-  //        101 - max             10
-  //        100 - fround          11
-  //        111 - fli             11
-
-  //  OpCtrl:
-  //    Fma: {not multiply-add?, negate prod?, negate Z?}
-  //        000 - fmadd
-  //        001 - fmsub
-  //        010 - fnmsub
-  //        011 - fnmadd
-  //        100 - mul
-  //        110 - add
-  //        111 - sub
-  //    Div: 
-  //        0 - div
-  //        1 - sqrt
-  //    Cvt Int: {Int to Fp?, 64 bit int?, signed int?}
-  //    Cvt Fp: output format
-  //        10 - to half
-  //        00 - to single
-  //        01 - to double
-  //        11 - to quad
-  //    Cmp: {equal?, less than?}
-  //        010 - eq
-  //        001 - lt
-  //        011 - le
-  //        110 - min
-  //        101 - max
-  //    Sgn:
-  //        00 - sign
-  //        01 - negate sign
-  //        10 - xor sign
-
-  // rename input adresses for readability
-  assign Adr1D = InstrD[19:15];
-  assign Adr2D = InstrD[24:20];
-  assign Adr3D = InstrD[31:27];
- 
-  // D/E pipleine register
-  flopenrc #(`FCTRLW+2+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
-              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ZfaD, ZfaFRoundNXD, ~IllegalFPUInstrD},
-              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE, ZfaFRoundNXE, FPUActiveE});
-  flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
-  flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
-  flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
-
-  // Integer division on FPU divider
-  if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE;
-  else                               assign IDivStartE = 1'b0; 
-
-  // E/M pipleine register
-  flopenrc #(14+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
-              {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE},
-              {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM, ZfaM});
-
-  // renameing for readability
-  assign FpLoadStoreM = FResSelM[1];
-
-  // M/W pipleine register
-  flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
-          {FRegWriteM, FResSelM, FCvtIntM},
-          {FRegWriteW, FResSelW, FCvtIntW});
-
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
deleted file mode 100644
index 2a43b2d91..000000000
--- a/src/fpu/fdivsqrt/fdivsqrt.sv
+++ /dev/null
@@ -1,100 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrt.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk, 
-  input  logic                 reset, 
-  input  logic [P.FMTBITS-1:0] FmtE,
-  input  logic                 XsE,
-  input  logic [P.NF:0]        XmE, YmE,
-  input  logic [P.NE-1:0]      XeE, YeE,
-  input  logic                 XInfE, YInfE, 
-  input  logic                 XZeroE, YZeroE, 
-  input  logic                 XNaNE, YNaNE, 
-  input  logic [P.NE-2:0]      BiasE,                               // Bias of exponent
-  input  logic [P.LOGFLEN-1:0] NfE,                          // Number of fractional bits in selected format
-  input  logic                 FDivStartE, IDivStartE,
-  input  logic                 StallM,
-  input  logic                 FlushE,
-  input  logic                 SqrtE, SqrtM,
-  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // these are the src A/B outputs before the mux choosing between them and PCE to put in srcA/B
-  input  logic [2:0]           Funct3E, Funct3M,
-  input  logic                 IntDivE, W64E,
-  output logic                 DivStickyM,
-  output logic                 FDivBusyE, IFDivStartE, FDivDoneE,
-  output logic [P.NE+1:0]      UeM,                         // Exponent result 
-  output logic [P.DIVb:0]      UmM,                         // Significand result
-  output logic [P.XLEN-1:0]    FIntDivResultM               // Integer division result (IntDivResult in figure)
-);
-
-  // Floating-point division and square root module, with optional integer division and remainder
-  // Computes X/Y, sqrt(X), A/B, or A%B
-
-  logic [P.DIVb+3:0]           WS, WC;                       // Partial remainder components
-  logic [P.DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [P.DIVb+3:0]           D;                            // Iterator Divisor
-  logic [P.DIVb:0]             FirstU, FirstUM;              // Intermediate result values
-  logic [P.DIVb+1:0]           FirstC;                       // Step tracker
-  logic                        WZeroE;                       // Early termination flag
-  logic [P.DURLEN-1:0]         CyclesE;                      // FSM cycles
-  logic                        SpecialCaseM;                 // Divide by zero, square root of negative, etc.
-                                                            
-  // Integer div/rem signals                                
-  logic                        BZeroM;                       // Denominator is zero
-  logic [P.DIVBLEN-1:0]        IntNormShiftM;                // Integer normalizatoin shift amount
-  logic                        ALTBM, AsM, BsM, W64M;        // Special handling for postprocessor
-  logic [P.XLEN-1:0]           AM;                           // Original Numerator for postprocessor
-  logic                        ISpecialCaseE;                // Integer div/remainder special cases
-
-  fdivsqrtpreproc #(P) fdivsqrtpreproc(                          // Preprocessor
-    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
-    .FmtE, .Bias(BiasE), .Nf(NfE), .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
-    // Int-specific 
-    .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
-    .BZeroM, .IntNormShiftM, .AM, .W64M, .ALTBM, .AsM, .BsM);
-
-  fdivsqrtfsm #(P) fdivsqrtfsm(                                  // FSM
-    .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
-    .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
-    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .CyclesE,
-    // Int-specific 
-    .IDivStartE, .ISpecialCaseE, .IntDivE);
-
-  fdivsqrtiter #(P) fdivsqrtiter(                                // CSA Iterator
-    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
-    .FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC));
-
-  fdivsqrtpostproc #(P) fdivsqrtpostproc(                        // Postprocessor
-    .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
-    .SqrtE, .SqrtM, .SpecialCaseM, 
-    .UmM, .WZeroE, .DivStickyM, 
-    // Int-specific 
-    .IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, 
-    .FIntDivResultM);
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
deleted file mode 100644
index 2347c9d21..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ /dev/null
@@ -1,57 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtcycles.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
-// Modified: 18 April 2022
-//
-// Purpose: Determine number of cycles for divsqrt
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.LOGFLEN-1:0] Nf,          // Number of fractional bits in selected format
-  input  logic                 IntDivE,
-  input  logic [P.DIVBLEN-1:0] IntResultBitsE,    
-  output logic [P.DURLEN-1:0]  CyclesE
-);
-
-  logic [P.DIVBLEN-1:0] FPResultBitsE, ResultBitsE; // number of fractional (result) bits
-
-  // Cycle logic
-  // P.DIVCOPIES = k. P.LOGR = log(R) = r.  P.RK = rk.  
-  // Integer division needs p fractional + r integer result bits
-  // FP Division needs at least Nf fractional bits + 2 guard/round bits and one integer digit (LOG R integer bits) = Nf + 2 + r bits
-  // FP Sqrt needs at least Nf fractional bits and 2 guard/round bits.  The integer bit is always initialized to 1 and does not need a cycle.
-  // The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
-
-  /* verilator lint_off WIDTH */
-  always_comb begin 
-    FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
-
-    if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
-    else               ResultBitsE = FPResultBitsE;
-
-    CyclesE = (ResultBitsE-1)/(P.RK) + 1; // ceil (ResultBitsE/rk)
-  end 
-  /* verilator lint_on WIDTH */
-
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
deleted file mode 100644
index 058a3d17b..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtexpcalc.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: Exponent caclulation for divide and square root
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtexpcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.NE-2:0]      Bias,      // Bias of exponent
-  input  logic [P.NE-1:0]      Xe, Ye,    // input exponents
-  input  logic                 Sqrt,
-  input  logic [P.DIVBLEN-1:0] ell, m,    // number of leading 0s in Xe and Ye
-  output logic [P.NE+1:0]      Ue         // result exponent
-  );
-
-  logic [P.NE+1:0] SXExp;
-  logic [P.NE+1:0] SExp;
-  logic [P.NE+1:0] DExp;
-
-  // Square root exponent = (Xe - l - bias) / 2 + bias; l accounts for subnorms
-  assign SXExp = {2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - (P.NE+2)'(P.BIAS);
-  assign SExp  = {SXExp[P.NE+1], SXExp[P.NE+1:1]} + {2'b0, Bias};
-
-  // division exponent = (Xe-l) - (Ye-m) + bias; l and m account for subnorms
-  assign DExp  = ({2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(P.NE+1-P.DIVBLEN){1'b0}}, m} + {3'b0, Bias}); 
-
-  // Select square root or division exponent
-  assign Ue = Sqrt ? SExp : DExp;
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
deleted file mode 100644
index 4e05b5e58..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ /dev/null
@@ -1,80 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtfsm.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: divsqrt state machine for multi-cycle operations
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtfsm import cvw::*;  #(parameter cvw_t P) (
-  input  logic                clk, reset, 
-  input  logic                XInfE, YInfE, 
-  input  logic                XZeroE, YZeroE, 
-  input  logic                XNaNE, YNaNE, 
-  input  logic                FDivStartE, IDivStartE,
-  input  logic                XsE, WZeroE,
-  input  logic                SqrtE,
-  input  logic                StallM, FlushE,
-  input  logic                IntDivE,
-  input  logic                ISpecialCaseE,
-  input  logic [P.DURLEN-1:0] CyclesE,
-  output logic                IFDivStartE,
-  output logic                FDivBusyE, FDivDoneE,
-  output logic                SpecialCaseM
-);
-  
-  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
-  statetype state;
-
-  logic SpecialCaseE, FSpecialCaseE;
-  logic [P.DURLEN-1:0] step;
-
-  // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
-  assign IFDivStartE = (FDivStartE | (IDivStartE & P.IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
-  assign FDivDoneE = (state == DONE);
-  assign FDivBusyE = (state == BUSY) | IFDivStartE; 
- 
-  // terminate immediately on special cases
-  assign FSpecialCaseE = XZeroE | XInfE  | XNaNE |  (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
-  if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
-  else               assign SpecialCaseE = FSpecialCaseE;
-  flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
-
-  always_ff @(posedge clk) begin
-      if (reset | FlushE) begin
-          state <= IDLE; 
-      end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
-          step <= CyclesE; 
-          if (SpecialCaseE) state <= DONE;
-          else              state <= BUSY;
-      end else if (state == BUSY) begin 
-          if (step == 1 | WZeroE) state <= DONE; // finished steps or terminate early on zero residual
-          step <= step - 1;
-      end else if (state == DONE) begin // Can't still be stalled in configs tested, but keep this check for paranoia
-        if (StallM) state <= DONE; // exclusion-tag: fdivsqrtfsm stallm
-        else        state <= IDLE;
-      end 
-  end
-
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
deleted file mode 100644
index ff03d29ec..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ /dev/null
@@ -1,120 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtiter.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
-// Modified:13 January 2022
-//
-// Purpose: k stages of divsqrt logic, plus registers
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk,
-  input  logic              IFDivStartE, 
-  input  logic              FDivBusyE, 
-  input  logic              SqrtE,
-  input  logic [P.DIVb+3:0] X, D,                  // Q4.DIVb
-  output logic [P.DIVb:0]   FirstU, FirstUM,       // U1.DIVb
-  output logic [P.DIVb+1:0] FirstC,                // Q2.DIVb
-  output logic [P.DIVb+3:0] FirstWS, FirstWC       // Q4.DIVb
-);
-
-  logic [P.DIVb+3:0]      WSNext[P.DIVCOPIES-1:0]; // Q4.DIVb
-  logic [P.DIVb+3:0]      WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
-  logic [P.DIVb+3:0]      WS[P.DIVCOPIES:0];       // Q4.DIVb
-  logic [P.DIVb+3:0]      WC[P.DIVCOPIES:0];       // Q4.DIVb
-  logic [P.DIVb:0]        U[P.DIVCOPIES:0];        // U1.DIVb
-  logic [P.DIVb:0]        UM[P.DIVCOPIES:0];       // U1.DIVb
-  logic [P.DIVb:0]        UNext[P.DIVCOPIES-1:0];  // U1.DIVb
-  logic [P.DIVb:0]        UMNext[P.DIVCOPIES-1:0]; // U1.DIVb
-  logic [P.DIVb+1:0]      C[P.DIVCOPIES:0];        // Q2.DIVb
-  logic [P.DIVb+1:0]      initC;                   // Q2.DIVb
-  logic [P.DIVCOPIES-1:0] un; 
-
-  logic [P.DIVb+3:0]      WSN, WCN;                // Q4.DIVb
-  logic [P.DIVb+3:0]      DBar, D2, DBar2;         // Q4.DIVb
-  logic [P.DIVb+1:0]      NextC;                   // Q2.DIVb
-  logic [P.DIVb:0]        UMux, UMMux;             // U1.DIVb
-  logic [P.DIVb:0]        initU, initUM;           // U1.DIVb
-
-  // Top Muxes and Registers
-  // When start is asserted, the inputs are loaded into the divider.
-  // Otherwise, the divisor is retained and the residual and result
-  // are fed back for the next iteration.
- 
-  // Residual WS/SC registers/initialization mux
-  mux2   #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
-  mux2   #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
-  flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
-  flopen #(P.DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
-
-  // UOTFC Result U and UM registers/initialization mux
-  // Initialize U to 0 = 0.0000... and UM to -1 = 1.00000... (in Q1.Divb)
-  assign initU  ={(P.DIVb+1){1'b0}};
-  assign initUM = {{1'b1}, {(P.DIVb){1'b0}}};
-  mux2   #(P.DIVb+1)  Umux(UNext[P.DIVCOPIES-1],  initU,  IFDivStartE, UMux);
-  mux2   #(P.DIVb+1) UMmux(UMNext[P.DIVCOPIES-1], initUM, IFDivStartE, UMMux);
-  flopen #(P.DIVb+1)  UReg(clk, FDivBusyE, UMux,  U[0]);
-  flopen #(P.DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
-
-  // C register/initialization mux: C = -R:
-  // C = -4 = 00.000000... (in Q2.DIVb) for radix 4, C = -2 = 10.000000... for radix2
-  if(P.RADIX == 4) assign initC = '0;
-  else             assign initC = {2'b10, {{P.DIVb{1'b0}}}};
-  mux2   #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC); 
-  flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
-
-  // Divisor Selections
-  assign DBar    = ~D;        // for -D
-  if(P.RADIX == 4) begin : d2
-    assign D2    = D << 1;    // for 2D,  only used in R4
-    assign DBar2 = ~D2;       // for -2D, only used in R4
-  end
-
-  // k=DIVCOPIES of the recurrence logic
-  genvar i;
-  generate
-    for(i=0; $unsigned(i)<P.DIVCOPIES; i++) begin : iterations
-      if (P.RADIX == 2) begin: stage
-        fdivsqrtstage2 #(P) fdivsqrtstage(.D, .DBar, .SqrtE,
-          .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]),
-          .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
-      end else begin: stage
-        fdivsqrtstage4 #(P) fdivsqrtstage(.D, .DBar, .D2, .DBar2, .SqrtE, 
-          .WS(WS[i]), .WC(WC[i]), .WSNext(WSNext[i]), .WCNext(WCNext[i]), 
-          .C(C[i]), .U(U[i]), .UM(UM[i]), .CNext(C[i+1]), .UNext(UNext[i]), .UMNext(UMNext[i]), .un(un[i]));
-      end
-      assign WS[i+1] = WSNext[i];
-      assign WC[i+1] = WCNext[i];
-      assign U[i+1]  = UNext[i];
-      assign UM[i+1] = UMNext[i];
-    end
-  endgenerate
-
-  // Send values from start of cycle for postprocessing
-  assign FirstWS = WS[0];
-  assign FirstWC = WC[0];
-  assign FirstU  = U[0];
-  assign FirstUM = UM[0];
-  assign FirstC  = C[0];
-endmodule
-
diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
deleted file mode 100644
index 869b06f74..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ /dev/null
@@ -1,143 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtpostproc.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: Divide/Square root postprocessing
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk, reset,
-  input  logic                 StallM,
-  input  logic [P.DIVb+3:0]    WS, WC,            // Q4.DIVb
-  input  logic [P.DIVb+3:0]    D,                 // Q4.DIVb
-  input  logic [P.DIVb:0]      FirstU, FirstUM,   // U1.DIVb
-  input  logic [P.DIVb+1:0]    FirstC,            // Q2.DIVb
-  input  logic                 SqrtE,
-  input  logic                 SqrtM, SpecialCaseM, 
-  input  logic [P.XLEN-1:0]    AM,                // U/Q(XLEN.0)
-  input  logic                 RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
-  input  logic [P.DIVBLEN-1:0] IntNormShiftM,     
-  output logic [P.DIVb:0]      UmM,               // U1.DIVb result significand
-  output logic                 WZeroE,
-  output logic                 DivStickyM,
-  output logic [P.XLEN-1:0]    FIntDivResultM     // U/Q(XLEN.0)
-);
-  
-  logic [P.DIVb+3:0]         Sum;
-  logic [P.INTDIVb+3:0]      W;
-  logic [P.DIVb:0]           PreUmM;
-  logic                      NegStickyM;
-  logic                      weq0E, WZeroM;
-  logic [P.XLEN-1:0]         IntDivResultM;
-  logic                      NegQuotM; // Integer quotient is negative
-
-  //////////////////////////
-  // Execute Stage: Detect early termination for an exact result
-  //////////////////////////
-
-  // check for early termination on an exact result. 
-  aplusbeq0 #(P.DIVb+4) wspluswceq0(WS, WC, weq0E);
-
-  if (P.RADIX == 2) begin: R2EarlyTerm
-    logic [P.DIVb+3:0] FZeroE, FZeroSqrtE, FZeroDivE;
-    logic [P.DIVb+2:0] FirstK;
-    logic wfeq0E;
-    logic [P.DIVb+3:0] WCF, WSF;
-
-    assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
-    assign FZeroSqrtE = {FirstUM[P.DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
-    assign FZeroDivE =  D << 1;                                    // F for divide
-    mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
-    csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
-    aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
-    assign WZeroE = weq0E | wfeq0E;
-  end else begin
-    assign WZeroE = weq0E;
-  end 
-
-  //////////////////////////
-  // E/M Pipeline register
-  //////////////////////////
- 
-  flopenr #(1) WZeroMReg(clk, reset, ~StallM, WZeroE, WZeroM);
-
-  //////////////////////////
-  // Memory Stage: Postprocessing
-  //////////////////////////
-
-  //  If the result is not exact, the sticky should be set
-  assign DivStickyM = ~WZeroM & ~SpecialCaseM; 
-
-  // Determine if sticky bit is negative 
-  assign Sum = WC + WS;
-  assign NegStickyM = Sum[P.DIVb+3];
-  mux2 #(P.DIVb+1) preummux(FirstU, FirstUM, NegStickyM, PreUmM); // Select U or U-1 depending on negative sticky bit
-  mux2 #(P.DIVb+1)    ummux(PreUmM, (PreUmM << 1), SqrtM, UmM);
-
-  // Integer quotient or remainder correction, normalization, and special cases
-  if (P.IDIV_ON_FPU) begin:intpostproc // Int supported
-    logic [P.INTDIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
-    logic signed [P.INTDIVb+3:0] PreResultM, PreResultShiftedM, PreIntResultM;
-    logic [P.INTDIVb+3:0] DTrunc, SumTrunc;
-
-
-    assign SumTrunc = Sum[P.DIVb+3:P.DIVb-P.INTDIVb];
-    assign DTrunc = D[P.DIVb+3:P.DIVb-P.INTDIVb];
-
-    assign W = $signed(SumTrunc) >>> P.LOGR;
-    assign UnsignedQuotM = {3'b000, PreUmM[P.DIVb:P.DIVb-P.INTDIVb]};
-
-
-    // Integer remainder: sticky and sign correction muxes
-    assign NegQuotM = AsM ^ BsM; // Integer Quotient is negative
-    mux2 #(P.INTDIVb+4) normremdmux(W, W+DTrunc, NegStickyM, NormRemDM);
-
-
-    // Select quotient or remainder and do normalization shift
-    mux2 #(P.INTDIVb+4)    presresultmux(UnsignedQuotM, NormRemDM, RemOpM, PreResultM);
-    assign PreResultShiftedM = PreResultM >> IntNormShiftM;
-    mux2 #(P.INTDIVb+4)    preintresultmux(PreResultShiftedM, -PreResultShiftedM,AsM ^ (BsM&~RemOpM), PreIntResultM);
-
-    // special case logic
-    // terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B|
-    always_comb
-      if (BZeroM) begin         // Divide by zero
-        if (RemOpM) IntDivResultM = AM;  
-        else        IntDivResultM = {(P.XLEN){1'b1}};
-     end else if (ALTBM) begin // Numerator is small
-        if (RemOpM) IntDivResultM = AM;
-        else        IntDivResultM = '0;
-     end else       IntDivResultM = PreIntResultM[P.XLEN-1:0];
-
-    // sign extend result for W64
-    if (P.XLEN==64) begin
-      mux2 #(64) resmux(IntDivResultM[P.XLEN-1:0], 
-        {{(P.XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
-        W64M, FIntDivResultM);
-    end else 
-      assign FIntDivResultM = IntDivResultM[P.XLEN-1:0];
-  end else
-    assign FIntDivResultM = '0;
-endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
deleted file mode 100644
index a399e4a4f..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ /dev/null
@@ -1,241 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtpreproc.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk,
-  input  logic                 IFDivStartE, 
-  input  logic [P.NF:0]        Xm, Ym,      // Floating-point significands
-  input  logic [P.NE-1:0]      Xe, Ye,      // Floating-point exponents
-  input  logic [P.FMTBITS-1:0] FmtE,
-  input  logic [P.NE-2:0]      Bias,                               // Bias of exponent
-  input  logic [P.LOGFLEN-1:0] Nf,          // Number of fractional bits in selected format
-  input  logic                 SqrtE,
-  input  logic                 XZeroE,
-  input  logic [2:0]           Funct3E,
-  output logic [P.NE+1:0]      UeM,         // biased exponent of result
-  output logic [P.DIVb+3:0]    X, D,        // Q4.DIVb
-  // Int-specific
-  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // U(XLEN.0) inputs from IEU 
-  input  logic                 IntDivE, W64E,
-  // Outputs
-  output logic                 ISpecialCaseE,
-  output logic [P.DURLEN-1:0]  CyclesE,
-  output logic [P.DIVBLEN-1:0] IntNormShiftM,
-  output logic                 ALTBM, W64M,
-  output logic                 AsM, BsM, BZeroM,
-  output logic [P.XLEN-1:0]    AM
-);
-
-  logic [P.DIVb:0]             Xnorm, Dnorm;
-  logic [P.DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
-  logic [P.NE+1:0]             UeE;                                 // Result Exponent (FP only)
-  logic [P.DIVb:0]             IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
-  logic [P.DIVBLEN-1:0]        mE, ell;                             // Leading zeros of inputs
-  logic [P.DIVBLEN-1:0]        IntResultBitsE;                      // bits in integer result
-  logic                        AZeroE, BZeroE;                      // A or B is Zero for integer division
-  logic                        SignedDivE;                          // signed division
-  logic                        AsE, BsE;                            // Signs of integer inputs
-  logic [P.XLEN-1:0]           AE;                                  // input A after W64 adjustment
-  logic                        ALTBE;
-  logic                        EvenExp;
-
-  //////////////////////////////////////////////////////
-  // Integer Preprocessing
-  //////////////////////////////////////////////////////
-
-  if (P.IDIV_ON_FPU) begin:intpreproc // Int Supported
-    logic [P.XLEN-1:0] BE, PosA, PosB;
-
-    // Extract inputs, signs, zero, depending on W64 mode if applicable
-    assign SignedDivE = ~Funct3E[0];
-  
-    // Source handling
-    if (P.XLEN==64) begin // 64-bit, supports W64
-      mux2 #(64)    amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & SignedDivE}}, ForwardedSrcAE[31:0]}, W64E, AE);
-      mux2 #(64)    bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & SignedDivE}}, ForwardedSrcBE[31:0]}, W64E, BE);
-    end else begin // 32 bits only
-      assign AE = ForwardedSrcAE;
-      assign BE = ForwardedSrcBE;
-     end
-    assign AZeroE = ~(|AE);
-    assign BZeroE = ~(|BE);
-    assign AsE = AE[P.XLEN-1] & SignedDivE;
-    assign BsE = BE[P.XLEN-1] & SignedDivE; 
-
-    // Force integer inputs to be postiive
-    mux2 #(P.XLEN) posamux(AE, -AE, AsE, PosA);
-    mux2 #(P.XLEN) posbmux(BE, -BE, BsE, PosB);
-
-    // Select integer or floating point inputs
-    mux2 #(P.DIVb+1) ifxmux({Xm, {(P.DIVb-P.NF){1'b0}}}, {PosA, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFX);
-    mux2 #(P.DIVb+1) ifdmux({Ym, {(P.DIVb-P.NF){1'b0}}}, {PosB, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFD);
-  end else begin // Int not supported
-    assign IFX = {Xm, {(P.DIVb-P.NF){1'b0}}};
-    assign IFD = {Ym, {(P.DIVb-P.NF){1'b0}}};
-  end
-
-  //////////////////////////////////////////////////////
-  // Integer & FP leading zero and normalization shift
-  //////////////////////////////////////////////////////
-
-  // count leading zeros for Subnorm FP and to normalize integer inputs
-  lzc #(P.DIVb+1) lzcX (IFX, ell);
-  lzc #(P.DIVb+1) lzcY (IFD, mE);
-
-  // Normalization shift: shift leading one into most significant bit
-  assign Xnorm = (IFX << ell);
-  assign Dnorm = (IFD << mE); 
-
-  //////////////////////////////////////////////////////
-  // Integer Right Shift to digit boundary
-  //  Determine DivXShifted (X shifted to digit boundary)
-  //  and nE (number of fractional digits)
-  //////////////////////////////////////////////////////
-
-  if (P.IDIV_ON_FPU) begin:intrightshift // Int Supported
-    logic [P.DIVBLEN-1:0] ZeroDiff,p;
-
-    // calculate number of fractional bits p
-    assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
-    assign ALTBE = ZeroDiff[P.DIVBLEN-1];  // A less than B (A has more leading zeros)
-    mux2 #(P.DIVBLEN) pmux(ZeroDiff, '0, ALTBE, p);          
-
-    /* verilator lint_off WIDTH */
-    assign IntResultBitsE = P.LOGR + p;  // Total number of result bits (r integer bits plus p fractional bits)
-    /* verilator lint_on WIDTH */
-
-    // Integer special cases (terminate immediately)
-    assign ISpecialCaseE = BZeroE | ALTBE;
-
-    // calculate right shift amount RightShiftX to complete in discrete number of steps
-    if (P.RK > 1) begin // more than 1 bit per cycle
-      logic [$clog2(P.RK)-1:0] RightShiftX;
-      /* verilator lint_off WIDTH */
-      assign RightShiftX = P.RK - 1 - ((IntResultBitsE - 1) % P.RK); // Right shift amount
-      assign DivXShifted = DivX >> RightShiftX;                     // shift X by up to R*K-1 to complete in n steps
-      /* verilator lint_on WIDTH */
-    end else begin // radix 2 1 copy doesn't require shifting
-      assign DivXShifted = DivX;
-    end
-  end else begin
-    assign {ISpecialCaseE, IntResultBitsE} = '0;
-  end
-
-  //////////////////////////////////////////////////////
-  // Floating-Point Preprocessing
-  // Extend to Q4.b format
-  // shift square root to be in range [1/4, 1)
-  // Normalized numbers are shifted right by 1 if the exponent is odd
-  // Subnormal numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
-   //////////////////////////////////////////////////////
-
-  assign DivX = {3'b000, Xnorm}; // Zero-extend numerator for division
-
-  // Sqrt is initialized on step one as R(X-1), so depends on Radix
-  // If X = 0, then special case logic sets sqrt = 0 so this portion doesn't matter
-  // Otherwise, X has a leading 1 after possible normalization shift and is now in range [1, 2)
-  // Next X is shifted right by 1 or 2 bits to range [1/4, 1) and exponent will be adjusted accordingly to be even
-  // Now (X-1) is negative.  Formed by placing all 1s in all four integer bits (in Q4.b) form, keeping X in fraciton bits
-  // Then multiply by R is left shift by r (1 or 2 for radix 2 or 4)
-  // This is optimized in hardware by first right shifting by 0 or 1 bit (instead of 1 or 2), then left shifting by (r-1), then subtracting 2 or 4
-  // Subtracting 2 is equivalent to adding 1110.  Subtracting 4 is equivalent to adding 1100.  Prepend leading 1s to do a free subtraction.
-  // This also means only one extra fractional bit is needed becaue we never shift right by more than 1.
-  // Radix      Exponent odd          Exponent Even
-  // 2          x-2 = 2(x/2 - 1)      x/2 - 2 = 2(x/4 - 1)
-  // 4          2(x)-4 = 4(x/2 - 1))  2(x/2)-4 = 4(x/4 - 1)
-  // Summary: PreSqrtX = r(x/2or4 - 1)
-
-  assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even
-  mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even
-
-/*  
-  // Attempt to optimize radix 4 to use a left shift by 1 or zero initially, followed by no more left shift
-  // This saves one bit in DIVb because there is no initial right shift.
-  // However, C needs to be extended further, lest it create a k with a 1 in the lsb when C is all 1s.
-  // That is an optimization for another day.
-  if (P.RADIX == 2) begin
-    logic [P.DIVb:0] PreSqrtX;    // U1.DIVb
-    mux2 #(P.DIVb+1) sqrtxmux(Xnorm, {1'b0, Xnorm[P.DIVb:1]}, EvenExp, PreSqrtX); // X if exponent odd, X/2 if exponent even
-    assign SqrtX = {3'b111, PreSqrtX};                          // PreSqrtX - 2 = 2(PreSqrtX/2 - 1)
-  end else begin
-    logic [P.DIVb+1:0] PreSqrtX;  // U2.DIVb
-    mux2 #(P.DIVb+2) sqrtxmux({Xnorm, 1'b0}, {1'b0, Xnorm}, EvenExp, PreSqrtX); // 2X if exponent odd, X if exponent even
-    assign SqrtX = {2'b11, PreSqrtX};                     // PreSqrtX - 4 = 4(PreSqrtX/4 - 1)
-  end
-*/
-
-  // Initialize X for division or square root
-  mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);                    
-
-  //////////////////////////////////////////////////////
-  // Selet integer or floating-point operands
-  //////////////////////////////////////////////////////
-
-  if (P.IDIV_ON_FPU) begin
-    mux2 #(P.DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
-  end else begin
-    assign X = PreShiftX;
-  end
-
-  // Divisior register
-  flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
- 
-  // Floating-point exponent
-  fdivsqrtexpcalc #(P) expcalc(.Bias, .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
-  flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
-
-  // Number of FSM cycles (to FSM)
-  fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE);
-
-  if (P.IDIV_ON_FPU) begin:intpipelineregs
-    logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
-    logic               RemOpE;
-
-    /* verilator lint_off WIDTH */
-    assign IntDivNormShiftE = P.INTDIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift.  n = (Cycles * k - 1)
-    assign IntRemNormShiftE = mE + (P.INTDIVb-(P.XLEN-1));           // m + b - (N-1) for remainder normalization shift
-    /* verilator lint_on WIDTH */
-    assign RemOpE = Funct3E[1];
-    mux2 #(P.DIVBLEN) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE);
-
-    // pipeline registers
-    flopen #(1)         altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
-    flopen #(1)        bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
-    flopen #(1)        asignreg(clk, IFDivStartE, AsE,      AsM);
-    flopen #(1)        bsignreg(clk, IFDivStartE, BsE,      BsM);
-    flopen #(P.DIVBLEN)   nsreg(clk, IFDivStartE, IntNormShiftE, IntNormShiftM); 
-    flopen #(P.XLEN)    srcareg(clk, IFDivStartE, AE,       AM);
-    if (P.XLEN==64) 
-      flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
-    else assign W64M = 0;
-  end else
-    assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = '0;
-
-endmodule
-
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
deleted file mode 100644
index 551a358c4..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ /dev/null
@@ -1,92 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtstage4.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
-// Modified:13 January 2022
-//
-// Purpose: radix-4 divsqrt recurrence stage
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtstage4 import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.DIVb+3:0] D, DBar, D2, DBar2, // Q4.DIVb
-  input  logic [P.DIVb:0]   U,UM,               // U1.DIVb
-  input  logic [P.DIVb+3:0] WS, WC,             // Q4.DIVb
-  input  logic [P.DIVb+1:0] C,                  // Q2.DIVb
-  input  logic              SqrtE, 
-  output logic [P.DIVb+1:0] CNext,              // Q2.DIVb
-  output logic              un,
-  output logic [P.DIVb:0]   UNext, UMNext,      // U1.DIVb
-  output logic [P.DIVb+3:0] WSNext, WCNext      // Q4.DIVb
-);
-
-  logic [P.DIVb+3:0]        Dsel;               // Q4.DIVb
-  logic [3:0]               udigit;             // {+2, +1, -1, -2} or 0000 for 0
-  logic [P.DIVb+3:0]        F;                  // Q4.DIVb
-  logic [P.DIVb+3:0]        AddIn;              // Q4.DIVb
-  logic [4:0]               Smsbs;              // U1.4
-  logic [2:0]               Dmsbs;              // U0.3   drop leading 1 from D
-  logic [7:0]               WCmsbs, WSmsbs;     // U4.4
-  logic                     CarryIn;
-  logic [P.DIVb+3:0]        WSA, WCA;           // Q4.DIVb
-  logic j0, j1;                                 // step j = 0 or step j = 1
-
-  // Digit Selection logic
-  assign j0     = ~C[P.DIVb+1];             // first step of R digit selection: C = 00...0
-  assign j1     = ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; simplified from  C[P.DIVb] & ~C[P.DIVb-1] because j=0 case takes priority
-  assign Smsbs  = U[P.DIVb:P.DIVb-4];       // U1.4 most significant bits of square root
-  assign Dmsbs  = D[P.DIVb-1:P.DIVb-3];     // U0.3 most significant fractional bits of divisor after leading 1
-  assign WCmsbs = WC[P.DIVb+3:P.DIVb-4];    // Q4.4 most significant bits of residual
-  assign WSmsbs = WS[P.DIVb+3:P.DIVb-4];    // Q4.4 most significant bits of residual
-  fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j0, .j1, .udigit);
-  assign un = 1'b0; // unused for radix 4
-
-  // F generation logic
-  fdivsqrtfgen4 #(P) fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
-
-  // Divisor multiple logic
-  always_comb
-    case (udigit)
-      4'b1000: Dsel = DBar2;
-      4'b0100: Dsel = DBar;
-      4'b0000: Dsel = '0;
-      4'b0010: Dsel = D;
-      4'b0001: Dsel = D2;
-      default: Dsel = 'x;
-    endcase
-
-  // Residual Update
-  //  {WS, WC}}Next = (WS + WC - qD or F) << 2
-  assign AddIn = SqrtE ? F : Dsel;
-  assign CarryIn = ~SqrtE & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D 
-  csa #(P.DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
-  assign WSNext = WSA << 2;
-  assign WCNext = WCA << 2;
-
-  // Shift thermometer code C
-  assign CNext = {2'b11, C[P.DIVb+1:2]};
- 
-  // On-the-fly converter to accumulate result
-  fdivsqrtuotfc4 #(P) fdivsqrtuotfc4(.udigit, .C(CNext[P.DIVb:0]), .U, .UM, .UNext, .UMNext);
-endmodule
-
-
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
deleted file mode 100644
index e6eb45f75..000000000
--- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
+++ /dev/null
@@ -1,121 +0,0 @@
-///////////////////////////////////////////
-// fdivsqrtuslc4cmp.sv
-//
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
-// Modified:13 January 2022
-//
-// Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection 
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fdivsqrtuslc4cmp (
-  input  logic [2:0] Dmsbs,             // U0.3 fractional bits after implicit leading 1
-  input  logic [4:0] Smsbs,             // U1.4 leading bits of square root approximation
-  input  logic [7:0] WSmsbs, WCmsbs,    // Q4.4 residual most significant bits
-  input  logic       SqrtE, 
-  input  logic       j0, j1,            // are we on first (j0) or second step (j1) of digit selection
-  output logic [3:0] udigit             // {2, 1, -1, -2} digit is 0 if none are hot
-);
-  logic [6:0] Wmsbs;
-  logic [7:0] PreWmsbs;
-  logic [2:0] A;
-
-  assign PreWmsbs = WCmsbs + WSmsbs;
-  assign Wmsbs = PreWmsbs[7:1];
-  // D = 0001.xxx...
-  // Dmsbs = |   |
-  // W =      xxxx.xxx...
-  // Wmsbs = |        |
-
-  logic [6:0] mk2, mk1, mk0, mkm1;
-  logic [6:0] mkj2, mkj1;
-  logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0];
-  logic sqrtspecial;
-
-  // Prepopulate table of mks for comparison
-  assign mks2[0] = 12;
-  assign mks2[1] = 14;
-  assign mks2[2] = 16;
-  assign mks2[3] = 17;
-  assign mks2[4] = 18;
-  assign mks2[5] = 20;
-  assign mks2[6] = 22;
-  assign mks2[7] = 23;
-  assign mks1[0] = 4;
-  assign mks1[1] = 4;
-  assign mks1[2] = 6;
-  assign mks1[3] = 6;
-  assign mks1[4] = 6;
-  assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
-  assign mks1[6] = 8;
-  assign mks1[7] = 8;
-
-  assign mks0[0] = -4;
-  assign mks0[1] = -4;
-  assign mks0[2] = -6;
-  assign mks0[3] = -6;
-  assign mks0[4] = -6;
-  assign mks0[5] = -8;
-  assign mks0[6] = -8;
-  assign mks0[7] = -8;
-  assign mksm1[0] = -13;
-  assign mksm1[1] = -14;
-  assign mksm1[2] = -16;
-  assign mksm1[3] = -17;
-  assign mksm1[4] = -18;
-  assign mksm1[5] = -20; 
-  assign mksm1[6] = -22;
-  assign mksm1[7] = -23;
-
-  
-  // handles special case when j = 0 or j = 1 for sqrt
-  assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7.
-  assign mkj1 = j0 ? 0 : 8; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1
-  assign sqrtspecial = SqrtE & (j1 | j0);
-
-  // Choose A for current operation 
- always_comb
-    if (SqrtE) begin 
-      if (Smsbs[4]) A = 3'b111; // for S = 1.0000
-      else A = Smsbs[2:0];
-    end else A = Dmsbs;
-    
-  // Choose selection constants based on a
-  
-  assign mk2 = sqrtspecial ? mkj2 : mks2[A];
-  assign mk1 = sqrtspecial ? mkj1 : mks1[A];
-  assign mk0 = sqrtspecial ? -mkj1 : mks0[A];
-  assign mkm1 = sqrtspecial ? -mkj2 : mksm1[A];
-
-/* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000
-  assign mk0 = -mk1;
-  assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table
-  */
- 
-  // Compare residual W to selection constants to choose digit
-  always_comb 
-    if      ($signed(Wmsbs) >= $signed(mk2))  udigit = 4'b1000; // choose 2
-    else if ($signed(Wmsbs) >= $signed(mk1))  udigit = 4'b0100; // choose 1
-    else if ($signed(Wmsbs) >= $signed(mk0))  udigit = 4'b0000; // choose 0
-    else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1
-    else                                      udigit = 4'b0001; // choose -2
-endmodule
diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv
deleted file mode 100644
index 349189f33..000000000
--- a/src/fpu/fli.sv
+++ /dev/null
@@ -1,220 +0,0 @@
-///////////////////////////////////////////
-// fli.sv
-//
-// Written: David_Harris@hmc.edu
-// Modified: 1/16/2024
-//
-// Purpose: Floating-point float immediate
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fli import cvw::*;  #(parameter cvw_t P) (
-  input  logic [4:0]        Rs1,           // Index of immediate to select
-  input  logic [1:0]        Fmt,           // 00 = single, 01 = double, 10 = half, 11 = quad
-  output logic [P.FLEN-1:0] Imm            // Immediate output
-);
-
-  logic [P.FLEN-1:0] HImmBox, SImmBox, DImmBox, QImmBox;
-
-  // select constant for each immediate size supported
-
-  ////////////////////////////
-  // half
-  ////////////////////////////
-  
-  if (P.ZFH_SUPPORTED) begin
-    logic [15:0] HImm;
-    always_comb begin
-        case(Rs1) 
-            0:  HImm = 16'hBC00;
-            1:  HImm = 16'h0400;
-            2:  HImm = 16'h0100;
-            3:  HImm = 16'h0200;
-            4:  HImm = 16'h1C00;
-            5:  HImm = 16'h2000;
-            6:  HImm = 16'h2C00;
-            7:  HImm = 16'h3000;
-            8:  HImm = 16'h3400;
-            9:  HImm = 16'h3500;
-            10: HImm = 16'h3600;
-            11: HImm = 16'h3700;
-            12: HImm = 16'h3800;
-            13: HImm = 16'h3900;
-            14: HImm = 16'h3A00;
-            15: HImm = 16'h3B00;
-            16: HImm = 16'h3C00;
-            17: HImm = 16'h3D00;
-            18: HImm = 16'h3E00;
-            19: HImm = 16'h3F00;
-            20: HImm = 16'h4000;
-            21: HImm = 16'h4100;
-            22: HImm = 16'h4200;
-            23: HImm = 16'h4400;
-            24: HImm = 16'h4800;
-            25: HImm = 16'h4C00;
-            26: HImm = 16'h5800;
-            27: HImm = 16'h5C00;
-            28: HImm = 16'h7800;
-            29: HImm = 16'h7C00;
-            30: HImm = 16'h7C00;
-            31: HImm = 16'h7E00;
-        endcase
-    end
-    assign HImmBox = {{(P.FLEN-16){1'b1}}, HImm}; // NaN-box HImm
-  end else assign HImmBox = '0;
-
-  ////////////////////////////
-  // single
-  ////////////////////////////
-
-    logic [31:0] SImm;
-     always_comb begin
-       case(Rs1) 
-            0:  SImm = 32'hBF800000;
-            1:  SImm = 32'h00800000;
-            2:  SImm = 32'h37800000;
-            3:  SImm = 32'h38000000;
-            4:  SImm = 32'h3B800000;
-            5:  SImm = 32'h3C000000;
-            6:  SImm = 32'h3D800000;
-            7:  SImm = 32'h3E000000;
-            8:  SImm = 32'h3E800000;
-            9:  SImm = 32'h3EA00000;
-            10: SImm = 32'h3EC00000;
-            11: SImm = 32'h3EE00000;
-            12: SImm = 32'h3F000000;
-            13: SImm = 32'h3F200000;
-            14: SImm = 32'h3F400000;
-            15: SImm = 32'h3F600000;
-            16: SImm = 32'h3F800000;
-            17: SImm = 32'h3FA00000;
-            18: SImm = 32'h3FC00000;
-            19: SImm = 32'h3FE00000;
-            20: SImm = 32'h40000000;
-            21: SImm = 32'h40200000;
-            22: SImm = 32'h40400000;
-            23: SImm = 32'h40800000;
-            24: SImm = 32'h41000000;
-            25: SImm = 32'h41800000;
-            26: SImm = 32'h43000000;
-            27: SImm = 32'h43800000;
-            28: SImm = 32'h47000000;
-            29: SImm = 32'h47800000;
-            30: SImm = 32'h7F800000;
-            31: SImm = 32'h7FC00000;
-        endcase
-    end
-    assign SImmBox = {{(P.FLEN-32){1'b1}}, SImm}; // NaN-box SImm
-
-  ////////////////////////////
-  // double
-  ////////////////////////////
-  
-  if (P.D_SUPPORTED) begin
-    logic [63:0] DImm;
-    always_comb begin
-        case(Rs1) 
-            0:  DImm = 64'hBFF0000000000000;
-            1:  DImm = 64'h0010000000000000;
-            2:  DImm = 64'h3EF0000000000000;
-            3:  DImm = 64'h3F00000000000000;
-            4:  DImm = 64'h3F70000000000000;
-            5:  DImm = 64'h3F80000000000000;
-            6:  DImm = 64'h3FB0000000000000;
-            7:  DImm = 64'h3FC0000000000000;
-            8:  DImm = 64'h3FD0000000000000;
-            9:  DImm = 64'h3FD4000000000000;
-            10: DImm = 64'h3FD8000000000000;
-            11: DImm = 64'h3FDC000000000000;
-            12: DImm = 64'h3FE0000000000000;
-            13: DImm = 64'h3FE4000000000000;
-            14: DImm = 64'h3FE8000000000000;
-            15: DImm = 64'h3FEC000000000000;
-            16: DImm = 64'h3FF0000000000000;
-            17: DImm = 64'h3FF4000000000000;
-            18: DImm = 64'h3FF8000000000000;
-            19: DImm = 64'h3FFC000000000000;
-            20: DImm = 64'h4000000000000000;
-            21: DImm = 64'h4004000000000000;
-            22: DImm = 64'h4008000000000000;
-            23: DImm = 64'h4010000000000000;
-            24: DImm = 64'h4020000000000000;
-            25: DImm = 64'h4030000000000000;
-            26: DImm = 64'h4060000000000000;
-            27: DImm = 64'h4070000000000000;
-            28: DImm = 64'h40E0000000000000;
-            29: DImm = 64'h40F0000000000000;
-            30: DImm = 64'h7FF0000000000000;
-            31: DImm = 64'h7FF8000000000000;
-        endcase
-    end
-    assign DImmBox = {{(P.FLEN-64){1'b1}}, DImm}; // NaN-box DImm
-  end else assign DImmBox = '0;
-  
-    ////////////////////////////
-  // double
-  ////////////////////////////
-  
-  if (P.Q_SUPPORTED) begin
-    logic [127:0] QImm;
-    always_comb begin
-        case(Rs1) 
-            0:  QImm = 128'hBFFF0000000000000000000000000000;
-            1:  QImm = 128'h00010000000000000000000000000000;
-            2:  QImm = 128'h3FEF0000000000000000000000000000;
-            3:  QImm = 128'h3FF00000000000000000000000000000;
-            4:  QImm = 128'h3FF70000000000000000000000000000;
-            5:  QImm = 128'h3FF80000000000000000000000000000;
-            6:  QImm = 128'h3FFB0000000000000000000000000000;
-            7:  QImm = 128'h3FFC0000000000000000000000000000;
-            8:  QImm = 128'h3FFD0000000000000000000000000000;
-            9:  QImm = 128'h3FFD4000000000000000000000000000;
-            10: QImm = 128'h3FFD8000000000000000000000000000;
-            11: QImm = 128'h3FFDC000000000000000000000000000;
-            12: QImm = 128'h3FFE0000000000000000000000000000;
-            13: QImm = 128'h3FFE4000000000000000000000000000;
-            14: QImm = 128'h3FFE8000000000000000000000000000;
-            15: QImm = 128'h3FFEC000000000000000000000000000;
-            16: QImm = 128'h3FFF0000000000000000000000000000;
-            17: QImm = 128'h3FFF4000000000000000000000000000;
-            18: QImm = 128'h3FFF8000000000000000000000000000;
-            19: QImm = 128'h3FFFC000000000000000000000000000;
-            20: QImm = 128'h40000000000000000000000000000000;
-            21: QImm = 128'h40004000000000000000000000000000;
-            22: QImm = 128'h40008000000000000000000000000000;
-            23: QImm = 128'h40010000000000000000000000000000;
-            24: QImm = 128'h40020000000000000000000000000000;
-            25: QImm = 128'h40030000000000000000000000000000;
-            26: QImm = 128'h40060000000000000000000000000000;
-            27: QImm = 128'h40070000000000000000000000000000;
-            28: QImm = 128'h400E0000000000000000000000000000;
-            29: QImm = 128'h400F0000000000000000000000000000;
-            30: QImm = 128'h7FFF0000000000000000000000000000;
-            31: QImm = 128'h7FFF8000000000000000000000000000;
-        endcase
-    end
-    assign QImmBox = QImm; // NaN-box QImm trivial because Q is longest format
-  end else assign QImmBox = '0;
-
-  mux4 #(P.FLEN) flimux(SImmBox, DImmBox, HImmBox, QImmBox, Fmt, Imm); // select immediate based on format
-
-endmodule
diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
deleted file mode 100644
index 36d4a0ad5..000000000
--- a/src/fpu/fma/fma.sv
+++ /dev/null
@@ -1,94 +0,0 @@
-///////////////////////////////////////////
-// fma.sv
-//
-// Written:  6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
-// Modified: 
-//
-// Purpose: Floating point multiply-accumulate of configurable size
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fma import cvw::*;  #(parameter cvw_t P) (
-  input  logic                         Xs, Ys, Zs,             // input's signs
-  input  logic [P.NE-1:0]              Xe, Ye, Ze,             // input's biased exponents in B(NE.0) format
-  input  logic [P.NF:0]                Xm, Ym, Zm,             // input's significands in U(0.NF) format
-  input  logic                         XZero, YZero, ZZero,    // is the input zero
-  input  logic [2:0]                   OpCtrl,                 // operation control
-  output logic                         ASticky,                // sticky bit that is calculated during alignment
-  output logic [P.FMALEN-1:0]          Sm,                     // the positive sum's significand
-  output logic                         InvA,                   // Was A inverted for effective subtraction (P-A or -P+A)
-  output logic                         As,                     // the aligned addend's sign (modified Z sign for other operations)
-  output logic                         Ps,                     // the product's sign
-  output logic                         Ss,                     // the sum's sign
-  output logic [P.NE+1:0]              Se,                     // the sum's exponent
-  output logic [$clog2(P.FMALEN+1)-1:0] SCnt                    // normalization shift count
-);
-
-  //  OpCtrl:
-  //    Fma: {not multiply-add?, negate prod?, negate Z?}
-  //        000 - fmadd
-  //        001 - fmsub
-  //        010 - fnmsub
-  //        011 - fnmadd
-  //        100 - mul
-  //        110 - add
-  //        111 - sub
-
-  logic [2*P.NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
-  logic [P.FMALEN-1:0] Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
-  logic [P.FMALEN-1:0] AmInv;      // aligned addend's mantissa possibly inverted
-  logic [2*P.NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
-  logic                KillProd;   // set the product to zero before addition if the product is too small to matter
-  logic [P.NE+1:0]     Pe;         // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Calculate the product
-  //      - When multipliying two fp numbers, add the exponents
-  //      - Subtract the bias (XExp + YExp has two biases, one from each exponent)
-  //      - If the product is zero then kill the exponent
-  //      - Multiply the mantissas
-  ///////////////////////////////////////////////////////////////////////////////
-  
-  // calculate the product's exponent 
-  fmaexpadd #(P) expadd(.Xe, .Ye, .XZero, .YZero, .Pe);
-
-  // multiplication of the mantissa's
-  fmamult #(P) mult(.Xm, .Ym, .Pm);
-  
-  // calculate the signs and take the operation into account
-  fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Alignment shifter
-  ///////////////////////////////////////////////////////////////////////////////
-  
-  fmaalign #(P) align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ASticky, .KillProd);
-                      
-  // ///////////////////////////////////////////////////////////////////////////////
-  // // Addition/LZA
-  // ///////////////////////////////////////////////////////////////////////////////
-      
-  fmaadd #(P) add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
-
-  fmalza #(P.FMALEN, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
-  
-endmodule
diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
deleted file mode 100644
index 292472f7f..000000000
--- a/src/fpu/fma/fmaalign.sv
+++ /dev/null
@@ -1,92 +0,0 @@
-///////////////////////////////////////////
-// fmaalign.sv
-//
-// Written:  6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
-// Modified: 
-//
-// Purpose: FMA alginment shift
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fmaalign import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.NE-1:0]      Xe, Ye, Ze,          // biased exponents in B(NE.0) format
-  input  logic [P.NF:0]        Zm,                  // significand in U(0.NF) format]
-  input  logic                 XZero, YZero, ZZero, // is the input zero
-  output logic [P.FMALEN-1:0]  Am,                  // addend aligned for addition in U(NF+5.2NF+1)
-  output logic                 ASticky,             // Sticky bit calculated from the aliged addend
-  output logic                 KillProd             // should the product be set to zero
-);
-
-  logic [P.NE+1:0]             ACnt;                // how far to shift the addend to align with the product in Q(NE+2.0) format
-  logic [P.FMALEN+P.NF-1:0]    ZmShifted;           // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
-  logic [P.FMALEN+P.NF-1:0]    ZmPreshifted;        // input to the alignment shifter U(NF+5.3NF+1)
-  logic                        KillZ;               // should the addend be killed
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Alignment shifter
-  ///////////////////////////////////////////////////////////////////////////////
-
-  // determine the shift count for alignment
-  //      - negative means Z is larger, so shift Z left
-  //      - positive means the product is larger, so shift Z right
-  // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
-  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+3) - {2'b0, Ze};
-
-  // Default Addition with only inital left shift
-  // extra bit at end and beginning so the correct guard bit is calculated when subtracting
-  //  |   54'b0    |  106'b(product)  | 2'b0 |
-  //  | addnend    |
-
-  assign ZmPreshifted = {Zm,(P.FMALEN-1)'(0)};
-  assign KillProd     = (ACnt[P.NE+1]&~ZZero)|XZero|YZero;
-  assign KillZ        = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(5));
-
-  always_comb begin
-    // If the product is too small to effect the sum, kill the product
-    //  |   54'b0    |  106'b(product)  | 2'b0 |
-    //  | addnend    |
-    if (KillProd) begin
-        ZmShifted = {(P.NF+3)'(0), Zm, (2*P.NF+2)'(0)};
-        ASticky   = ~(XZero|YZero);
-
-    // If the addend is too small to effect the addition        
-    //      - The addend has to shift two past the end of the product to be considered too small
-    //      - The 2 extra bits are needed for rounding
-      
-    //  |   54'b0    |  106'b(product)  | 2'b0 |
-    //  | addnend    |
-    end else if (KillZ)  begin
-        ZmShifted = '0;
-        ASticky   = ~ZZero;
-
-    // If the Addend is shifted right
-    //  |   54'b0    |  106'b(product)  | 2'b0 |
-    //  | addnend    |
-    end else begin
-        ZmShifted = ZmPreshifted >> ACnt;
-        ASticky   = |(ZmShifted[P.NF-1:0]); 
-    end
-  end
-
-  assign Am = ZmShifted[P.FMALEN+P.NF-1:P.NF];
-
-endmodule
diff --git a/src/fpu/fmtparams.sv b/src/fpu/fmtparams.sv
deleted file mode 100644
index ad2dcfa4d..000000000
--- a/src/fpu/fmtparams.sv
+++ /dev/null
@@ -1,86 +0,0 @@
-
-///////////////////////////////////////////
-// fmtparams.sv
-//
-// Written: David_Harris@hmc.edu
-// Modified: 5/11/24
-//
-// Purpose: Look up bias of exponent and number of fractional bits for the selected format
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fmtparams import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0] Fmt,
-  output logic [P.NE-2:0]      Bias,
-  output logic [P.LOGFLEN-1:0] Nf
-);
-
-  if (P.FPSIZES == 1) begin
-    assign Bias = (P.NE-1)'(P.BIAS); 
-  end else if (P.FPSIZES == 2) begin
-    assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
-  end else if (P.FPSIZES == 3) begin
-    always_comb
-      case (Fmt)
-        P.FMT:  Bias =  (P.NE-1)'(P.BIAS);
-        P.FMT1: Bias = (P.NE-1)'(P.BIAS1);
-        P.FMT2: Bias = (P.NE-1)'(P.BIAS2);
-        default: Bias = 'x;
-      endcase
-  end else if (P.FPSIZES == 4) begin        
-    always_comb
-      case (Fmt)
-        2'h3: Bias =  (P.NE-1)'(P.Q_BIAS);
-        2'h1: Bias =  (P.NE-1)'(P.D_BIAS);
-        2'h0: Bias =  (P.NE-1)'(P.S_BIAS);
-        2'h2: Bias =  (P.NE-1)'(P.H_BIAS);
-      endcase
-  end
-
-  /* verilator lint_off WIDTH */
-  if (P.FPSIZES == 1)
-    assign Nf = P.NF;
-  else if (P.FPSIZES == 2)
-    always_comb
-      case (Fmt)
-        1'b0: Nf = P.NF1;
-        1'b1: Nf = P.NF;
-      endcase
-  else if (P.FPSIZES == 3)
-    always_comb
-      case (Fmt)
-        P.FMT:   Nf = P.NF;
-        P.FMT1:  Nf = P.NF1;
-        P.FMT2:  Nf = P.NF2; 
-        default: Nf = 'x; // shouldn't happen
-      endcase
-  else if (P.FPSIZES == 4)  
-    always_comb
-      case(Fmt)
-        P.S_FMT: Nf = P.S_NF;
-        P.D_FMT: Nf = P.D_NF;
-        P.H_FMT: Nf = P.H_NF;
-        P.Q_FMT: Nf = P.Q_NF;
-      endcase 
-  /* verilator lint_on WIDTH */
-
-endmodule
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
deleted file mode 100755
index 7619b92af..000000000
--- a/src/fpu/fpu.sv
+++ /dev/null
@@ -1,397 +0,0 @@
-///////////////////////////////////////////
-// fpu.sv
-//
-// Written: me@KatherineParry.com, James Stine, Brett Mathis, David Harris
-// Modified: 6/23/2021
-//
-// Purpose: Floating Point Unit Top-Level Interface
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fpu import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk,
-  input  logic                 reset,
-  // Hazards
-  input  logic                 StallE, StallM, StallW,             // stall signals (from HZU)
-  input  logic                 FlushE, FlushM, FlushW,             // flush signals (from HZU)
-  output logic                 FPUStallD,                          // Stall the decode stage (To HZU)
-  output logic                 FDivBusyE,                          // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
-  // CSRs                                                  
-  input  logic [1:0]           STATUS_FS,                          // Is floating-point enabled? (From privileged unit)
-  input  logic [2:0]           FRM_REGW,                           // Rounding mode (from CSR)
-  // Decode stage                                          
-  input  logic [31:0]          InstrD,                             // instruction (from IFU)
-  // Execute stage                                         
-  input  logic [2:0]           Funct3E,                            // Funct fields of instruction specify type of operations
-  input  logic                 IntDivE, W64E,                      // Integer division on FPU
-  input  logic [P.XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE,     // Integer input for convert, move, and int div (from IEU)
-  input  logic [4:0]           RdE,                                // which FP register to write to (from IEU)
-  output logic                 FWriteIntE,                         // integer register write enable (to IEU)
-  output logic                 FCvtIntE,                           // Convert to int (to IEU)
-  // Memory stage                                          
-  input  logic [2:0]           Funct3M,                            // Funct fields of instruction specify type of operations
-  input  logic [4:0]           RdM,                                // which FP register to write to (from IEU)
-  output logic                 FRegWriteM,                         // FP register write enable (to privileged unit)
-  output logic                 FpLoadStoreM,                       // Fp load instruction? (to LSU)
-  output logic [P.FLEN-1:0]    FWriteDataM,                        // Data to be written to memory (to LSU) 
-  output logic [P.XLEN-1:0]    FIntResM,                           // data to be written to integer register (to IEU)
-  output logic                 IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction (to IFU)
-  output logic [4:0]           SetFflagsM,                         // FPU flags (to privileged unit)
-  // Writeback stage                                       
-  input  logic [4:0]           RdW,                                // which FP register to write to (from IEU)
-  input  logic [P.FLEN-1:0]    ReadDataW,                          // Read data (from LSU)
-  output logic [P.XLEN-1:0]    FCvtIntResW,                        // convert result to to be written to integer register (to IEU)
-  output logic                 FCvtIntW,                           // select FCvtIntRes (to IEU)
-  output logic [P.XLEN-1:0]    FIntDivResultW                      // Result from integer division (to IEU)
-);
-
-  // RISC-V FPU specifics:
-  //    - multiprecision support uses NAN-boxing, putting 1's in unused msbs
-  //    - RISC-V detects underflow after rounding
-
-  // control signals
-  logic                        FRegWriteW;                         // FP register write enable
-  logic [2:0]                  FrmE, FrmM;                         // FP rounding mode
-  logic [P.FMTBITS-1:0]        FmtE, FmtM;                         // FP precision 0-single 1-double
-  logic                        FDivStartE, IDivStartE;             // Start division or squareroot
-  logic                        FWriteIntM;                         // Write to integer register
-  logic [1:0]                  ForwardXE, ForwardYE, ForwardZE;    // forwarding mux control signals
-  logic [2:0]                  OpCtrlE, OpCtrlM;                   // Select which operation to do in each component
-  logic [1:0]                  FResSelE, FResSelM, FResSelW;       // Select one of the results that finish in the memory stage
-  logic [1:0]                  PostProcSelE, PostProcSelM;         // select result in the post processing unit
-  logic [4:0]                  Adr1D, Adr2D, Adr3D;                // register adresses of each input
-  logic [4:0]                  Adr1E, Adr2E, Adr3E;                // register adresses of each input
-  logic                        XEnD, YEnD, ZEnD;                   // X, Y, Z inputs used for current operation
-  logic                        XEnE, YEnE, ZEnE;                   // X, Y, Z inputs used for current operation
-  logic                        FRegWriteE;                         // Write floating-point register
-  logic                        FPUActiveE;                         // FP instruction being executed
-  logic                        ZfaE, ZfaM;                         // Zfa variants of instructions (fli, fminm, fmaxm, fround, froundnx, fleq, fltq, fmvh, fmvp, fcvtmod.w.d)
-  logic                        ZfaFRoundNXE;                       // Zfa froundnx variant
-
-  // regfile signals
-  logic [P.FLEN-1:0]           FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
-  logic [P.FLEN-1:0]           FRD1E, FRD2E, FRD3E;                // Read Data from FP register - execute stage
-  logic [P.FLEN-1:0]           XE;                                 // Input 1 to the various units (after forwarding)
-  logic [P.XLEN-1:0]           IntSrcXE;                           // Input 1 to the various units (after forwarding)
-  logic [P.FLEN-1:0]           PreYE, YE;                          // Input 2 to the various units (after forwarding)
-  logic [P.FLEN-1:0]           PreZE, ZE;                          // Input 3 to the various units (after forwarding)
-
-  // unpacking signals
-  logic                        XsE, YsE, ZsE;                      // input's sign - execute stage
-  logic                        XsM, YsM;                           // input's sign - memory stage
-  logic [P.NE-1:0]             XeE, YeE, ZeE;                      // input's exponent - execute stage
-  logic [P.NE-1:0]             ZeM;                                // input's exponent - memory stage
-  logic [P.NF:0]               XmE, YmE, ZmE;                      // input's significand - execute stage
-  logic [P.NF:0]               XmM, YmM, ZmM;                      // input's significand - memory stage
-  logic                        XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
-  logic                        XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
-  logic                        XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
-  logic                        XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
-  logic                        XSubnormE;                          // is the input subnormal
-  logic                        XZeroE, YZeroE, ZZeroE;             // is the input zero - execute stage
-  logic                        XZeroM, YZeroM;                     // is the input zero - memory stage
-  logic                        XInfE, YInfE, ZInfE;                // is the input infinity - execute stage
-  logic                        XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
-  logic                        XExpMaxE;                           // is the exponent all ones (max value)
-  logic [P.FLEN-1:0]           XPostBoxE;                          // X after fixing bad NaN box.  Needed for 1-input operations
-  logic [P.NE-2:0]             BiasE;                              // Bias of exponent
-  logic [P.LOGFLEN-1:0]        NfE;                                // Number of fractional bits
-
-  // Fma Signals
-  logic                        FmaAddSubE;                         // Multiply by 1.0 when adding or subtracting
-  logic [1:0]                  FmaZSelE;                           // Select Z = Y when adding or subtracting, 0 when multiplying
-  logic [P.FMALEN-1:0]         SmE, SmM;                           // Sum significand
-  logic                        FmaAStickyE, FmaAStickyM;           // FMA addend sticky bit output
-  logic [P.NE+1:0]             SeE,SeM;                            // Sum exponent
-  logic                        InvAE, InvAM;                       // Invert addend
-  logic                        AsE, AsM;                           // Addend sign
-  logic                        PsE, PsM;                           // Product sign
-  logic                        SsE, SsM;                           // Sum sign
-  logic [$clog2(P.FMALEN+1)-1:0] SCntE, SCntM;                       // LZA sum leading zero count
-  
-  // Cvt Signals
-  logic [P.NE:0]               CeE, CeM;                           // convert intermediate expoent
-  logic [P.LOGCVTLEN-1:0]      CvtShiftAmtE, CvtShiftAmtM;         // how much to shift by
-  logic                        CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
-  logic                        CsE, CsM;                           // convert result sign
-  logic                        IntZeroE, IntZeroM;                 // is the integer zero?
-  logic [P.CVTLEN-1:0]         CvtLzcInE, CvtLzcInM;               // input to the Leading Zero Counter (priority encoder)
-  logic [P.XLEN-1:0]           FCvtIntResM;                        // fcvt integer result (for IEU)
-  
-  // divide signals
-  logic [P.DIVb:0]             UmM;                                // fdivsqrt signifcand
-  logic [P.NE+1:0]             UeM;                                // fdivsqrt exponent
-  logic                        DivStickyM;                         // fdivsqrt sticky bit
-  logic                        FDivDoneE, IFDivStartE;             // fdivsqrt control signals
-  logic [P.XLEN-1:0]           FIntDivResultM;                     // fdivsqrt integer division result (for IEU)
-
-  // result and flag signals
-  logic [P.XLEN-1:0]           ClassResE;                          // classify result
-  logic [P.FLEN-1:0]           CmpFpResE;                          // compare result to FPU (min/max)
-  logic [P.XLEN-1:0]           CmpIntResE;                         // compare result to IEU (eq/lt/le)
-  logic                        CmpNVE;                             // compare invalid flag (Not Valid)     
-  logic [P.FLEN-1:0]           SgnResE;                            // sign injection result
-  logic [P.XLEN-1:0]           FIntResE;                           // FPU to IEU E-stage result (classify, compare, move)
-  logic [P.FLEN-1:0]           PostProcResM;                       // Postprocessor output
-  logic [4:0]                  PostProcFlgM;                       // Postprocessor flags
-  logic                        PreNVE, PreNVM;                     // selected invalid flag that is ready in the memory stage     
-  logic                        PreNXE, PreNXM;                     // selected inexact flag that is ready in the memory stage     
-  logic [P.FLEN-1:0]           FpResM, FpResW;                     // FPU preliminary result
-  logic [P.FLEN-1:0]           PreFpResE, PreFpResM;               // selected result that is ready in the memory stage
-  logic [P.FLEN-1:0]           FResultW;                           // final FP result being written to the FP register   
-
-  // other signals
-  logic [P.FLEN-1:0]           PreIntSrcE, IntSrcE;                // align SrcA from IEU to the floating point format for fmv / fmvp
-  logic [P.FLEN-1:0]           BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
-  logic [P.FLEN-1:0]           BoxedOneE;                          // One value for Z for multiplication, with NaN boxing if needed
-  logic                        StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
-  logic [P.FLEN-1:0]           SgnExtXE;                           // Sign-extended X input for move to integer
-  logic                        mvsgn;                              // sign bit for extending move
-  logic [P.FLEN-1:0]           ZfaResE;                            // Result of Zfa fli or fround instruction
-  logic                        FRoundNVE, FRoundNXE;               // Zfa fround invalid and inexact flags
-
-  //////////////////////////////////////////////////////////////////////////////////////////
-  // Decode Stage: fctrl decoder, read register file
-  //////////////////////////////////////////////////////////////////////////////////////////
-
-  // calculate FP control signals
-  fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
-              .IntDivE, .InstrD,
-              .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
-              .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .ZfaE, .ZfaM, .ZfaFRoundNXE, .FrmE, .FrmM, .FmtE, .FmtM,
-              .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
-              .IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
-              .FResSelE, .FResSelM, .FResSelW, .FPUActiveE, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
-              .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
-
-  // FP register file
-  fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
-    .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
-    .a4(RdW), .wd4(FResultW),
-    .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));  
-
-  // D/E pipeline registers  
-  flopenrc #(P.FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
-  flopenrc #(P.FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
-  flopenrc #(P.FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
-
-  //////////////////////////////////////////////////////////////////////////////////////////
-  // Execute Stage: hazards, forwarding, unpacking, execution units
-  //////////////////////////////////////////////////////////////////////////////////////////
-
-  // Hazard unit for FPU: determines if any forwarding or stalls are needed
-  fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, 
-    .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, 
-    .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
-
-  // forwarding muxs
-  mux3  #(P.FLEN)  fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
-  mux3  #(P.FLEN)  fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
-  mux3  #(P.FLEN)  fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
-
-  // Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z
-  if(P.FPSIZES == 1) assign BoxedOneE = {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)};
-  else if(P.FPSIZES == 2) 
-      mux2 #(P.FLEN) fonemux ({{P.FLEN-P.LEN1{1'b1}}, 2'b0, {P.NE1-1{1'b1}}, (P.NF1)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
-  else if(P.FPSIZES == 3 | P.FPSIZES == 4) 
-      mux4 #(P.FLEN) fonemux ({{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)}, 
-                              {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}, 
-                              {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, 
-                              {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
-  assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10);
-  mux2  #(P.FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
-  
-  // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
-  // For add and subtract, Z comes from second source operand
-  if(P.FPSIZES == 1) assign BoxedZeroE = '0;
-  else if(P.FPSIZES == 2) 
-    mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
-  else if(P.FPSIZES == 3 | P.FPSIZES == 4)
-    mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}, 
-                                {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}, 
-                                {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}, 
-                                (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
-  assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]};
-  mux3  #(P.FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
-
-  // unpack unit: splits FP inputs into their parts and classifies SNaN, NaN, Subnorm, Norm, Zero, Infifnity
-  unpack #(P) unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), 
-    .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE), .FPUActive(FPUActiveE),
-    .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
-    .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
-    .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
-    .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE), .Bias(BiasE), .Nf(NfE));
-  
-  // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
-  fma #(P) fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
-    .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), 
-    .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), .ASticky(FmaAStickyE)); 
-
-  // divide and square root: fdiv, fsqrt, optionally integer division
-  fdivsqrt #(P) fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
-    .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .BiasE, .NfE, .FDivStartE, .IDivStartE, .XsE,
-    .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
-    .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .UeM, 
-    .UmM, .FIntDivResultM);
-
-  // compare: fmin/fmax, flt/fle/feq
-  fcmp #(P) fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Zfa(ZfaE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), 
-    .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), 
-    .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), 
-    .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
-
-  // sign injection: fsgnj/fsgnjx/fsgnjn
-  fsgninj #(P) fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XPostBoxE), .Fmt(FmtE), .SgnRes(SgnResE));
-
-  // classify: fclass
-  fclassify #(P) fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), 
-    .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
-
-  // convert: fcvt.*.*
-  fcvt #(P) fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
-    .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
-    .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
-
-  // ZFA: fround and floating-point load immediate fli
-  if (P.ZFA_SUPPORTED) begin:Zfa
-    logic [4:0] Rs1E;
-    logic [1:0] Fmt2E; // Two-bit format field from instruction
-    logic [P.FLEN-1:0]           FRoundE;                            // Zfa fround output
-    logic [P.FLEN-1:0]           FliResE;                            // Zfa Floating-point load immediate value
-
-    // fround
-    fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE), 
-                       .XNaN(XNaNE), .XSNaN(XSNaNE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE), 
-                       .ZfaFRoundNX(ZfaFRoundNXE),
-                       .FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE));
-
-    // fli
-    flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
-    flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
-    fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); 
-    mux2  #(P.FLEN) ZfaResMux(FRoundE, FliResE, OpCtrlE[0], ZfaResE);
-  end else begin
-    assign {FRoundNXE, FRoundNVE} = '0;
-    assign ZfaResE = 'x;
-  end
-
-  // fmv.*.x: NaN Box SrcA to extend integer to requested FP size 
-  if(P.FPSIZES == 1) 
-    if (P.FLEN >= P.XLEN) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
-    else                  assign PreIntSrcE = ForwardedSrcAE[P.FLEN-1:0];
-  else if(P.FPSIZES == 2) 
-    if (P.FLEN >= P.XLEN)
-      mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE);
-    else
-      mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, ForwardedSrcAE[P.FLEN-1:0], FmtE, PreIntSrcE);
-  else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
-    localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
-    mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, 
-                            {{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]}, 
-                            {{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]}, 
-                            FmtE, PreIntSrcE); // NaN boxing zeroes
-  end
-  // fmvp.*.x: Select pair of registers
-  if (P.ZFA_SUPPORTED & (P.FLEN == 2*P.XLEN))
-       assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x
-  else assign IntSrcE = PreIntSrcE;
-
-  // select a result that may be written to the FP register
-  mux4  #(P.FLEN) FResMux(SgnResE, IntSrcE, CmpFpResE, ZfaResE, {OpCtrlE[2], &OpCtrlE[1:0] | (OpCtrlE == 3'b100) & ZfaE}, PreFpResE);
-  assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE) | FRoundNVE & (OpCtrlE == 3'b100) & ZfaE;
-  assign PreNXE = FRoundNXE & (OpCtrlE == 3'b100);
-
-  // fmv.x.*: select the result that may be written to the integer register
-  if(P.FPSIZES == 1) begin
-    assign mvsgn = XE[P.FLEN-1];
-    assign SgnExtXE = XE;
-  end else if(P.FPSIZES == 2) begin
-    mux2 #(1)      sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
-    mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE);
-  end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
-    mux4 #(1)      sgnmux (XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.H_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
-    mux3 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]}, 
-                              {{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]}, 
-                              {{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]}, 
-                                FmtE, SgnExtXE); // Q not needed because there is no fmv.x.q
-  end
-
-  // sign extend to XLEN if necessary
-  if (P.FLEN >= 2*P.XLEN)
-    if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[2*P.XLEN-1:P.XLEN] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
-    else                                      assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
-  else 
-    assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE};
-  mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
-
-  // E/M pipe registers
-
-  // Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
-  assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE); 
-
-  flopenrc #(P.NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
-  flopenrc #(P.NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
-  flopenrc #(P.FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM});
-  flopenrc #(P.XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
-  flopenrc #(P.FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
-  flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM, 
-    {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
-    {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
-  flopenrc #(2)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, {PreNVE, PreNXE}, {PreNVM, PreNXM});      
-  flopenrc #(P.FMALEN) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
-  flopenrc #($clog2(P.FMALEN+1)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
-    {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
-    {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
-  flopenrc #(P.NE+P.LOGCVTLEN+P.CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
-    {CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
-    {CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
-  flopenrc #(P.FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
-
-  //////////////////////////////////////////////////////////////////////////////////////////
-  // Memory Stage: postprocessor and result muxes
-  //////////////////////////////////////////////////////////////////////////////////////////
-
-  postprocess #(P) postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
-    .FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivUm(UmM), .FmaSs(SsM),
-    .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), 
-    .FmaSm(SmM), .DivUe(UeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
-    .CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), 
-    .ToInt(FWriteIntM), .Zfa(ZfaM), .DivSticky(DivStickyM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), 
-    .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
-
-  // FPU flag selection - to privileged
-  mux2  #(5)       FPUFlgMux({PreNVM, 3'b0, PreNXM}, PostProcFlgM, (FResSelM == 2'b01), SetFflagsM);
-  mux2  #(P.FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
-
-  // M/W pipe registers
-  flopenrc #(P.FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); 
-  flopenrc #(P.XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); 
-  flopenrc #(P.XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); 
-
-  //////////////////////////////////////////////////////////////////////////////////////////
-  // Writeback Stage: result mux
-  //////////////////////////////////////////////////////////////////////////////////////////
-
-  // select the result to be written to the FP register
-  mux2  #(P.FLEN)  FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
-
-endmodule // fpu
diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv
deleted file mode 100644
index 519d55096..000000000
--- a/src/fpu/fround.sv
+++ /dev/null
@@ -1,153 +0,0 @@
-///////////////////////////////////////////
-// fround.sv
-//
-// Written: David_Harris@hmc.edu
-// Modified: 4/21/2024
-//
-// Purpose: Floating-point round to integer for Zfa
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fround import cvw::*;  #(parameter cvw_t P) (
-  input  logic                    Xs,           // input's sign
-  input  logic [P.NE-1:0]         Xe,           // input's exponent
-  input  logic [P.NF:0]           Xm,           // input's fraction with leading integer bit (U1.NF)
-  input  logic                    XNaN,         // X is NaN
-  input  logic                    XSNaN,        // X is Signalling NaN
-  input  logic [P.FMTBITS-1:0]    Fmt,          // the input's precision (11=quad 01=double 00=single 10=half)
-  input  logic [2:0]              Frm,          // rounding mode
-  input  logic [P.LOGFLEN-1:0]    Nf,           // Number of fractional bits in selected format
-  input  logic                    ZfaFRoundNX,  // froundnx instruction can set inexact flag
-  output logic [P.FLEN-1:0]       FRound,       // Rounded result
-  output logic                    FRoundNV,     // fround invalid
-  output logic                    FRoundNX      // fround inexact
-);
-
-  logic [P.NE-1:0] E, Xep1;
-  logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
-  logic [P.FLEN-1:0] W;
-  logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf;
-
-  // Unbiased exponent
-  assign E = Xe - P.BIAS[P.NE-1:0];
-  assign Xep1 = Xe + 1'b1;
-
-  //////////////////////////////////////////
-  // Compute LSB L', rounding bit R' and Sticky bit T'
-  //      if (E < 0)					// negative exponents round to 0 or 1.
-  //              L' = 0      // LSB = 0
-  //              if (E = -1) R' = 1, TMask = 0.1111...111	// if (E = -1) 0.5  X < 1.  Round bit is 1
-  //              else R' = 0; TMask = 1.1111...111  	// if (E < -1), X < 0.5.  Round bit is 0
-  //      else					// positive exponents truncate fraction and may add 1
-  //              IMask = 1.0000…000 >>> E  		// (in U1.Nf form); implies thermometer code generator
-  //              TMask = ~(IMask >>> 1) 			// 0.01111…111 >> E
-  //              HotE = IMask & ~(IMask << 1) 		// a 1 in column E, where 0 is the integer bit, 
- 	//				// 1 is the most significant fractional bit, etc.
-  //              HotEP1 = HotE >> 1			// a 1 in column E+1
-  //              L' = OR(Xm & HotE) 			// Xm[E], where Xm[0] is the integer bit, 
- 	//				// Xm[1] is the most significant fractional bit, etc.
-  //              R' = OR(Xm & HotEP1)			// Xm[E+1] 
-  //              TRUNC = Xm & IMask			// Truncated fraction, corresponds to truncated integer value
-  //              RND =  TRUNC + HotE 			// TRUNC + (1 >> E), corresponds to next integer
-  //      T' = OR(Xm & TMask)				// T’ = OR(Xm[E+2:Nf]) if E >= 0, OR(Xf) if E = -1, 1 if E < -1
-  //////////////////////////////////////////
-
-  // Check if exponent is negative and -1
-  assign Elt0 = E[P.NE-1]; // (E < 0);
-  assign Eeqm1 = ($signed(E) == -1);
-
-  // Logic for nonnegative mask and rounding bits
-  assign IMask = $signed({1'b1, {P.NF{1'b0}}}) >>> E; /// if E > Nf, this produces all 0s instead of all 1s.  Hence exact handling is needed below.
-  assign Tmasknonneg = ~IMask >>> 1'b1;
-  assign HotE = IMask & ~(IMask << 1'b1);
-  assign HotEP1 = HotE >> 1'b1;
-  assign Lnonneg = |(Xm & HotE);
-  assign Rnonneg = |(Xm & HotEP1);
-  assign Trunc = Xm & IMask;
-  assign {Two, Rnd} = Trunc + HotE; // Two means result overflowed to 10.000000 = 2.0
-
-  // mux and AND-OR logic to select final rounding bits
-  mux2 #(1) Lmux(Lnonneg, 1'b0, Elt0, Lp);
-  mux2 #(1) Rmux(Rnonneg, Eeqm1, Elt0, Rp);
-  assign Tmaskneg = {~Eeqm1, {P.NF{1'b1}}}; // 1.11111 or 0.11111
-  mux2 #(P.NF+1) Tmaskmux(Tmasknonneg, Tmaskneg, Elt0, Tmask);
-  assign Tp = |(Xm & Tmask);
-
-  ///////////////////////////
-  // Rounding, flags, special Cases 
-  //      Flags = 0						// unless overridden later
-  //      if (X is NaN)
-  //              W = Canonical NaN
-  //              Invalid = (X is signaling NaN)
-  //      else if (E >= Nf) 
-  //              W = X						// is exact; this also handles infinity
-  //      else 
-  //              RoundUp = RoundingLogic(Xs, L', R', T', rm)	// Table 16.4
-  //              if (E < 0) 					// 0 <= X < 1 rounds to 0 or 1
-  //                      if (RoundUp)     {Ws, We, Wf} = {Xs, bias, 0}	// +/- 1.0
-  //                     else                    {Ws, We, Wf} = {Xs, 0, 0}	// +/- 0
-  //              else //						// X >= 1 rounds to an integer or overflows to infinity
-  //                     if (RoundUp) Rm = RND else Rm = TRUNC	// Round up to RND or down to TRUNC
-  //                     if (Rm = 2.0)					// rounding requires incrementing exponent
-  //                             if (Xe = emax) {Ws, We, Wf} = {Xs, 111..11, 0} 	// overflow to W = Infinity with sign of Xs
-  //                             else	        {Ws, We, Wf} = {Xs, Xe+1, 0}	// 1.0 x 2E+1
-  //                     else                      {Ws, We, Wf} = {Xs, Xe, Rf}	// Rounded fraction, retain sign and exponent
-  //              If (FroundNX instruction) Inexact = R' | T'
-  ///////////////////////////
-
-  // Exact logic
-  /* verilator lint_off WIDTHEXPAND */
-  assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf.  Also check that Xe is positive to avoid wraparound problems
-  /* verilator lint_on WIDTHEXPAND */
-
-  // Rounding logic: determine whether to round up in magnitude
-  always_comb begin
-    case (Frm) // Frm is either specified in the instruction or is the dynamic rounding mode
-      3'b000:  RoundUp = Rp & (Lp | Tp);  // RNE
-      3'b001:  RoundUp = 0;               // RZ
-      3'b010:  RoundUp = Xs & (Rp | Tp);  // RN
-      3'b011:  RoundUp = ~Xs & (Rp | Tp); // RP
-      3'b100:  RoundUp = Rp;              // RNTA
-      default: RoundUp = 0;               // should never happen
-    endcase
-
-    // If result is not exact, select output in unpacked FLEN format initially
-    if (XNaN)            W = {1'b0, {P.NE{1'b1}}, 1'b1, {(P.NF-1){1'b0}}};  // Canonical NaN
-    else if (EgeNf)      W = {Xs, Xe, Xm[P.NF-1:0]};                        // Exact, no rounding needed
-    else if (Elt0)                                                          // 0 <= |X| < 1 rounds to 0 or 1
-      if (RoundUp)       W = {Xs, P.BIAS[P.NE-1:0], {P.NF{1'b0}}};          //   round to +/- 1
-      else               W = {Xs, {(P.FLEN-1){1'b0}}};                      //   round to +/- 0
-    else begin                                                              // |X| >= 1 rounds to an integer
-      if (RoundUp & Two) W = {Xs, Xep1, {(P.NF){1'b0}}};                    //   Round up to 2.0
-      else if (RoundUp)  W = {Xs, Xe, Rnd[P.NF-1:0]};                       //   Round up to Rnd
-      else               W = {Xs, Xe, Trunc[P.NF-1:0]};                     //   Round down to Trunc
-    end
-  end
-
-  packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
-
-  // Flags
-  assign FRoundNV = XSNaN;                                       // invalid if input is signaling NaN
-  assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN;    // Inexact if Round or Sticky bit set for FRoundNX instruction
-                                                                 // Note: NX must not be raised if input is invalid
-
-endmodule
diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
deleted file mode 100755
index 68e2eb493..000000000
--- a/src/fpu/fsgninj.sv
+++ /dev/null
@@ -1,77 +0,0 @@
-///////////////////////////////////////////
-// fsgninj.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 6/23/2021
-//
-// Purpose: FPU Sign Injection instructions
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fsgninj import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 Xs, Ys, // X and Y sign bits
-  input  logic [P.FLEN-1:0]    X,      // X
-  input  logic [P.FMTBITS-1:0] Fmt,    // format
-  input  logic [1:0]           OpCtrl, // operation control
-  output logic [P.FLEN-1:0]    SgnRes  // result
-);
-
-  logic ResSgn;  // result sign
-
-  // OpCtrl:
-  //     00 - fsgnj  - directly copy over sign value of Y
-  //     01 - fsgnjn - negate sign value of Y
-  //     10 - fsgnjx - XOR sign values of X and Y
-  
-  // calculate the result's sign
-  assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys;
-  
-  // format final result based on precision
-  //    - uses NaN-blocking format
-  //        - if there are any unused bits the most significant bits are filled with 1s
-  
-  if (P.FPSIZES == 1)
-    assign SgnRes = {ResSgn, X[P.FLEN-2:0]};
-  else if (P.FPSIZES == 2)
-    assign SgnRes = {~Fmt|ResSgn, X[P.FLEN-2:P.LEN1], Fmt ? X[P.LEN1-1] : ResSgn, X[P.LEN1-2:0]};
-  else if (P.FPSIZES ==  3) begin
-    logic [2:0] SgnBits;
-    always_comb
-      case (Fmt)
-        P.FMT:    SgnBits = {ResSgn, X[P.LEN1-1], X[P.LEN2-1]};
-        P.FMT1:   SgnBits = {1'b1, ResSgn, X[P.LEN2-1]};
-        P.FMT2:   SgnBits = {2'b11, ResSgn};
-        default: SgnBits = {3{1'bx}};
-      endcase
-    assign SgnRes = {SgnBits[2], X[P.FLEN-2:P.LEN1], SgnBits[1], X[P.LEN1-2:P.LEN2], SgnBits[0], X[P.LEN2-2:0]};
-  end else if (P.FPSIZES == 4) begin
-    logic [3:0] SgnBits;
-    always_comb
-      case (Fmt)
-        P.Q_FMT: SgnBits = {ResSgn, X[P.D_LEN-1], X[P.S_LEN-1], X[P.H_LEN-1]};
-        P.D_FMT: SgnBits = {1'b1, ResSgn, X[P.S_LEN-1], X[P.H_LEN-1]};
-        P.S_FMT: SgnBits = {2'b11, ResSgn, X[P.H_LEN-1]};
-        P.H_FMT: SgnBits = {3'b111, ResSgn};
-      endcase
-    assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
-  end
-endmodule
diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv
deleted file mode 100644
index e83f403c5..000000000
--- a/src/fpu/packoutput.sv
+++ /dev/null
@@ -1,103 +0,0 @@
-
-///////////////////////////////////////////
-// packoutput.sv
-//
-// Written: David_Harris@hmc.edu
-// Modified: 5/11/24
-//
-// Purpose: Pack the output of the FPU
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module packoutput import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FLEN-1:0]       Unpacked,
-  input  logic [P.FMTBITS-1:0]    Fmt,
-  output logic [P.FLEN-1:0]       Packed
-);
-
-  logic             Sign; 
-  logic [P.NE1-1:0] Exp1;
-  logic [P.NF1-1:0] Fract1;
-  logic [P.NE2-1:0] Exp2;
-  logic [P.NF2-1:0] Fract2;
-  logic [P.H_NE-1:0] Exp3;
-  logic [P.H_NF-1:0] Fract3;
-
-  // Pack exponent and fraction, with NaN-boxing to full FLEN
-
-  assign Sign = Unpacked[P.FLEN-1];
-  if (P.FPSIZES == 1) begin
-    assign Packed = Unpacked;
-  end else if (P.FPSIZES == 2) begin
-    always_comb begin
-      {Exp1, Fract1} = '0; // default if not used, to prevent latch
-      case (Fmt)
-        1'b1: Packed = Unpacked;
-        1'b0: begin
-                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
-                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
-                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
-              end
-      endcase
-    end
-  end else if (P.FPSIZES == 3) begin
-    always_comb begin
-      {Exp1, Fract1, Exp2, Fract2} = '0; // default if not used, to prevent latch
-      case (Fmt)
-        P.FMT: Packed = Unpacked;
-        P.FMT1: begin
-                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
-                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
-                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
-              end
-        P.FMT2: begin
-                Exp2 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE2-2:P.NF]};
-                Fract2 = Unpacked[P.NF-1:P.NF-P.NF2];
-                Packed = {{(P.FLEN-P.LEN2){1'b1}}, Sign, Exp2, Fract2}; 
-              end
-        default: Packed = 'x;
-      endcase
-    end
-  end else if (P.FPSIZES == 4) begin        
-    always_comb begin
-      {Exp1, Fract1, Exp2, Fract2, Exp3, Fract3} = '0; // default if not used, to prevent latch
-      case (Fmt)
-        2'h3: Packed = Unpacked;  // Quad
-        2'h1: begin // double
-                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
-                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
-                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
-              end
-        2'h0: begin // float
-                Exp2 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE2-2:P.NF]};
-                Fract2 = Unpacked[P.NF-1:P.NF-P.NF2];
-                Packed = {{(P.FLEN-P.LEN2){1'b1}}, Sign, Exp2, Fract2}; 
-              end
-        2'h2: begin // half
-                Exp3 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.H_NE-2:P.NF]};
-                Fract3 = Unpacked[P.NF-1:P.NF-P.H_NF];
-                Packed = {{(P.FLEN-P.H_LEN){1'b1}}, Sign, Exp3, Fract3}; 
-              end
-      endcase
-    end
-  end
-endmodule
diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
deleted file mode 100644
index d46b58f35..000000000
--- a/src/fpu/postproc/divshiftcalc.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-///////////////////////////////////////////
-// divshiftcalc.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: Division shift calculation
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module divshiftcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.NE+1:0]              DivUe,              // divsqrt exponent
-  output logic [P.LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
-  output logic                         DivResSubnorm,      // is the divsqrt result subnormal
-  output logic                         DivSubnormShiftPos  // is the subnormal shift amount positive
-);
-
-  logic [P.LOGNORMSHIFTSZ-1:0]         NormShift;          // normalized result shift amount
-  logic [P.LOGNORMSHIFTSZ-1:0]         DivSubnormShiftAmt; // subnormal result shift amount (killed if negative)
-  logic [P.NE+1:0]                     DivSubnormShift;    // subnormal result shift amount
-
-  // is the result subnormal
-  // if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
-  assign DivResSubnorm = DivUe[P.NE+1]|(~|DivUe[P.NE+1:0]);
-
-  // if the result is subnormal
-  //  00000000x.xxxxxx...                     Exp = DivUe
-  //  .00000000xxxxxxx... >> NF+1             Exp = DivUe+NF+1
-  //  .00xxxxxxxxxxxxx... << DivUe+NF+1       Exp = +1
-  //  .0000xxxxxxxxxxx... >> 1                Exp = 1
-  // Left shift amount      = DivUe+NF+1-1
-  assign DivSubnormShift    = (P.NE+2)'(P.NF)+DivUe;
-  assign DivSubnormShiftPos = ~DivSubnormShift[P.NE+1];
-
-  // if the result is normalized
-  //  00000000x.xxxxxx...                     Exp = DivUe
-  //  .00000000xxxxxxx... >> NF+1             Exp = DivUe+NF+1
-  //  00000000.xxxxxxx... << NF               Exp = DivUe+1
-  //  00000000x.xxxxxx... << NF               Exp = DivUe (extra shift done afterwards)
-  //  00000000xx.xxxxx... << 1?               Exp = DivUe-1 (determined after)
-  // inital Left shift amount  = NF
-  // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
-  assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
-
-  // if the shift amount is negative then don't shift (keep sticky bit)
-  // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
-  assign DivShiftAmt        = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
-
-endmodule
diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
deleted file mode 100644
index 22c354e30..000000000
--- a/src/fpu/postproc/fmashiftcalc.sv
+++ /dev/null
@@ -1,134 +0,0 @@
-///////////////////////////////////////////
-// fmashiftcalc.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: FMA shift calculation
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0]          Fmt,                 // precision 1 = double 0 = single
-  input  logic [P.NE+1:0]               FmaSe,               // sum's exponent
-  input  logic [P.FMALEN-1:0]           FmaSm,               // the positive sum
-  input  logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt,             // normalization shift count
-  output logic [P.NE+1:0]               NormSumExp,          // exponent of the normalized sum not taking into account Subnormal or zero results
-  output logic                          FmaSZero,            // is the sum zero
-  output logic                          FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
-  output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt          // normalization shift count
-);
-  logic [P.NE+1:0]                      PreNormSumExp;       // the exponent of the normalized sum with the P.FLEN bias
-  logic [P.NE+1:0]                      BiasCorr;            // correction for bias
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Normalization
-  ///////////////////////////////////////////////////////////////////////////////
-
-  // Determine if the sum is zero
-  assign FmaSZero = ~(|FmaSm);
-
-  // calculate the sum's exponent FmaSe-FmaSCnt+NF+2
-  assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(P.FMALEN+1)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+4);
-
-  //convert the sum's exponent into the proper precision
-  if (P.FPSIZES == 1) begin
-    assign NormSumExp = PreNormSumExp;
-    assign BiasCorr = '0;
-  end else if (P.FPSIZES == 2) begin
-    assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS);
-    assign NormSumExp = PreNormSumExp+BiasCorr;
-  end else if (P.FPSIZES == 3) begin
-    always_comb begin
-        case (Fmt)
-            P.FMT:   BiasCorr =  '0;
-            P.FMT1:  BiasCorr = (P.NE+2)'(P.BIAS1-P.BIAS);
-            P.FMT2:  BiasCorr = (P.NE+2)'(P.BIAS2-P.BIAS);
-            default: BiasCorr = 'x;
-        endcase
-    end
-    assign NormSumExp = PreNormSumExp+BiasCorr;
-  end else if (P.FPSIZES == 4) begin
-    always_comb begin
-        case (Fmt)
-            2'h3: BiasCorr = '0;
-            2'h1: BiasCorr = (P.NE+2)'(P.D_BIAS-P.Q_BIAS);
-            2'h0: BiasCorr = (P.NE+2)'(P.S_BIAS-P.Q_BIAS);
-            2'h2: BiasCorr = (P.NE+2)'(P.H_BIAS-P.Q_BIAS);
-        endcase
-    end
-    assign NormSumExp = PreNormSumExp+BiasCorr;
-  end
-  
-  // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen)
-  if (P.FPSIZES == 1) begin
-    logic Sum0LEZ, Sum0GEFL;
-    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
-    assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
-  end else if (P.FPSIZES == 2) begin
-    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
-    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
-    assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL);
-  end else if (P.FPSIZES == 3) begin
-    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
-    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
-    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
-    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
-    always_comb begin
-      case (Fmt)
-        P.FMT: FmaPreResultSubnorm   = Sum0LEZ & Sum0GEFL;
-        P.FMT1: FmaPreResultSubnorm  = Sum1LEZ & Sum1GEFL;
-        P.FMT2: FmaPreResultSubnorm  = Sum2LEZ & Sum2GEFL;
-        default: FmaPreResultSubnorm = 1'bx;
-      endcase
-    end
-  end else if (P.FPSIZES == 4) begin
-    logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
-    assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
-    assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
-    assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
-    assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-1+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
-    assign Sum2LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
-    assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-1+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
-    assign Sum3LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
-    assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
-    always_comb begin
-      case (Fmt)
-        2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
-        2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
-        2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
-        2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL;
-      endcase
-    end
-  end
-
-  // set and calculate the shift input and amount
-  //  - shift once if killing a product and the result is subnormal
-  assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
-endmodule
diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
deleted file mode 100644
index 3674303eb..000000000
--- a/src/fpu/postproc/postprocess.sv
+++ /dev/null
@@ -1,225 +0,0 @@
-///////////////////////////////////////////
-// postprocess.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module postprocess import cvw::*;  #(parameter cvw_t P) (
-  // general signals
-  input logic                              Xs, Ys,              // input signs
-  input logic  [P.NF:0]                    Xm, Ym, Zm,          // input mantissas
-  input logic  [2:0]                       Frm,                 // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
-  input logic  [P.FMTBITS-1:0]             Fmt,                 // precision 1 = double 0 = single
-  input logic  [2:0]                       OpCtrl,              // choose which operation (look below for values)
-  input logic                              XZero, YZero,        // inputs are zero
-  input logic                              XInf, YInf, ZInf,    // inputs are infinity
-  input logic                              XNaN, YNaN, ZNaN,    // inputs are NaN
-  input logic                              XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
-  input logic  [1:0]                       PostProcSel,         // select result to be written to fp register
-  //fma signals
-  input logic                              FmaAs,               // the modified Z sign - depends on instruction
-  input logic                              FmaPs,               // the product's sign
-  input logic                              FmaSs,               // Sum sign
-  input logic  [P.NE+1:0]                  FmaSe,               // the sum's exponent
-  input logic  [P.FMALEN-1:0]              FmaSm,               // the positive sum
-  input logic                              FmaASticky,          // sticky bit that is calculated during alignment
-  input logic  [$clog2(P.FMALEN+1)-1:0]    FmaSCnt,             // the normalization shift count
-  //divide signals
-  input logic                              DivSticky,           // divider sticky bit
-  input logic  [P.NE+1:0]                  DivUe,               // divsqrt exponent
-  input logic  [P.DIVb:0]                  DivUm,               // divsqrt significand
-  // conversion signals
-  input logic                              CvtCs,               // the result's sign
-  input logic  [P.NE:0]                    CvtCe,               // the calculated exponent
-  input logic                              CvtResSubnormUf,     // the convert result is subnormal or underflows
-  input logic  [P.LOGCVTLEN-1:0]           CvtShiftAmt,         // how much to shift by
-  input logic                              ToInt,               // is fp->int (since it's writting to the integer register)
-  input logic                              Zfa,                 // Zfa operation (fcvtmod.w.d)
-  input logic  [P.CVTLEN-1:0]              CvtLzcIn,            // input to the Leading Zero Counter (without msb)
-  input logic                              IntZero,             // is the integer input zero
-  // final results
-  output logic [P.FLEN-1:0]                PostProcRes,         // postprocessor final result
-  output logic [4:0]                       PostProcFlg,         // postprocesser flags
-  output logic [P.XLEN-1:0]                FCvtIntRes           // the integer conversion result
-  );
-  
-  // general signals
-  logic                        Rs;                   // result sign
-  logic [P.NF-1:0]             Rf;                   // Result fraction
-  logic [P.NE-1:0]             Re;                   // Result exponent
-  logic                        Ms;                   // normalized sign
-  logic [P.NORMSHIFTSZ-1:0]    Mf;                   // normalized fraction
-  logic [P.NE+1:0]             Me;                   // normalized exponent
-  logic [P.NE+1:0]             FullRe;               // Re with bits to determine sign and overflow
-  logic                        UfPlus1;              // do you add one (for determining underflow flag)
-  logic [P.LOGNORMSHIFTSZ-1:0] ShiftAmt;             // normalization shift amount
-  logic [P.NORMSHIFTSZ-1:0]    ShiftIn;              // input to normalization shift
-  logic [P.NORMSHIFTSZ-1:0]    Shifted;              // the ouput of the normalized shifter (before shift correction)
-  logic                        Plus1;                // add one to the final result?
-  logic                        Overflow;             // overflow flag used to select results
-  logic                        Invalid;              // invalid flag used to select results
-  logic                        Guard, Round, Sticky; // bits needed to determine rounding
-  logic [P.FMTBITS-1:0]        OutFmt;               // output format
-  // fma signals
-  logic [P.NE+1:0]             FmaMe;                // exponent of the normalized sum
-  logic                        FmaSZero;             // is the sum zero
-  logic [P.NE+1:0]             NormSumExp;           // exponent of the normalized sum not taking into account Subnormal or zero results
-  logic                        FmaPreResultSubnorm;  // is the result subnormal - calculated before LZA corection
-  logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt;          // normalization shift amount for fma
-  // division signals
-  logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt;          // divsqrt shif amount
-  logic [P.NE+1:0]             Ue;                   // divsqrt corrected exponent after corretion shift
-  logic                        DivByZero;            // divide by zero flag
-  logic                        DivResSubnorm;        // is the divsqrt result subnormal
-  logic                        DivSubnormShiftPos;   // is the divsqrt subnorm shift amout positive (not underflowed)
-  // conversion signals
-  logic [P.CVTLEN+P.NF:0]      CvtShiftIn;           // number to be shifted for converter
-  logic [1:0]                  CvtNegResMsbs;        // most significant bits of possibly negated int result
-  logic [P.XLEN+1:0]           CvtNegRes;            // possibly negated integer result
-  logic                        CvtResUf;             // did the convert result underflow
-  logic                        IntInvalid;           // invalid integer flag
-  // readability signals
-  logic                        Mult;                 // multiply operation
-  logic                        Sqrt;                 // is the divsqrt operation sqrt
-  logic                        Int64;                // is the integer 64 bits?
-  logic                        Signed;               // is the operation with a signed integer?
-  logic                        IntToFp;              // is the operation an int->fp conversion?
-  logic                        CvtOp;                // convertion operation
-  logic                        FmaOp;                // fma operation
-  logic                        DivOp;                // divider operation
-  logic                        InfIn;                // are any of the inputs infinity
-  logic                        NaNIn;                // are any of the inputs NaN
-
-  // signals to help readability
-  assign Signed  = OpCtrl[0];
-  assign Int64   = OpCtrl[1];
-  assign IntToFp = OpCtrl[2];
-  assign Mult    = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
-  assign CvtOp   = (PostProcSel == 2'b00);
-  assign FmaOp   = (PostProcSel == 2'b10);
-  assign DivOp   = (PostProcSel == 2'b01);
-  assign Sqrt    =  OpCtrl[0];
-
-  // is there an input of infinity or NaN being used
-  assign InfIn = XInf|YInf|ZInf;
-  assign NaNIn = XNaN|YNaN|ZNaN;
-
-  // choose the output format depending on the operation
-  //      - fp -> fp: OpCtrl contains the precision of the output
-  //      - otherwise: Fmt contains the precision of the output
-  if (P.FPSIZES == 2) 
-      assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT); 
-  else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
-      assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; 
-  else assign OutFmt = 0; // FPSIZES = 1
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Normalization
-  ///////////////////////////////////////////////////////////////////////////////
-
-  // final claulations before shifting
-  cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
-      .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
-
-  fmashiftcalc #(P) fmashiftcalc(.FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSm,
-      .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt);
-
-  divshiftcalc #(P) divshiftcalc(.DivUe, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt);
-
-  // select which unit's output to shift
-  always_comb
-    case(PostProcSel)
-      2'b10: begin // fma
-        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt};
-        ShiftIn  =  {{2'b00, FmaSm}, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}};
-      end
-      2'b00: begin // cvt
-        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
-        ShiftIn  =  {CvtShiftIn, {P.NORMSHIFTSZ-(P.CVTLEN+P.NF+1){1'b0}}};
-      end
-      2'b01: begin //divsqrt
-        ShiftAmt = DivShiftAmt;
-        ShiftIn  = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-(P.DIVb+1+P.NF){1'b0}}};
-      end
-      default: begin 
-        ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; 
-        ShiftIn  = {P.NORMSHIFTSZ{1'bx}}; 
-      end
-    endcase
-  
-  // main normalization shift
-  normshift #(P) normshift (.ShiftIn, .ShiftAmt, .Shifted);
-
-  // correct for LZA/divsqrt error
-  shiftcorrection #(P) shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
-      .DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivUe, .Ue, .FmaSZero, .Shifted, .FmaMe, .Mf);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Rounding
-  ///////////////////////////////////////////////////////////////////////////////
-
-  // round to nearest even
-  // round to zero
-  // round to -infinity
-  // round to infinity
-  // round to nearest max magnitude
-
-  // calulate result sign used in rounding unit
-  roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
-
-  round #(P) round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Ue,
-      .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt,  .CvtResUf,
-      .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Sign calculation
-  ///////////////////////////////////////////////////////////////////////////////
-
-  resultsign resultsign(.Frm, .FmaPs, .FmaAs, .Round, .Sticky, .Guard,
-      .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Rs);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Flags
-  ///////////////////////////////////////////////////////////////////////////////
-
-  flags #(P) flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero, 
-              .Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
-              .NaNIn, .FmaAs, .FmaPs, .Round, .IntInvalid, .DivByZero,
-              .Guard, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
-              .Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // Select the result
-  ///////////////////////////////////////////////////////////////////////////////
-
-  negateintres #(P) negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
-
-  specialcase #(P) specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid, 
-      .IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf, 
-      .NaNIn, .IntToFp, .Int64, .Signed, .Zfa, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes,
-      .XInf, .YInf, .DivOp, .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
-
-endmodule
diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
deleted file mode 100644
index 4c6d251fb..000000000
--- a/src/fpu/postproc/round.sv
+++ /dev/null
@@ -1,318 +0,0 @@
-///////////////////////////////////////////
-// round.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: Rounder
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module round import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0]     OutFmt,             // output format
-  input  logic [2:0]               Frm,                // rounding mode
-  input  logic [1:0]               PostProcSel,        // select the postprocessor output
-  input  logic                     Ms,                 // normalized sign
-  input  logic [P.NORMSHIFTSZ-1:0] Mf,                 // normalized fraction
-  // fma
-  input  logic                     FmaOp,              // is an fma operation being done?
-  input  logic [P.NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
-  input  logic                     FmaASticky,         // addend's sticky bit
-  // divsqrt
-  input  logic                     DivOp,              // is a division operation being done
-  input  logic                     DivSticky,          // divsqrt sticky bit
-  input  logic [P.NE+1:0]          Ue,                 // the divsqrt calculated expoent
-  // cvt
-  input  logic                     CvtOp,              // is a convert operation being done
-  input  logic                     ToInt,              // is the cvt op a cvt to integer
-  input  logic                     CvtResSubnormUf,    // is the cvt result subnormal or underflow
-  input  logic                     CvtResUf,           // does the cvt result underflow
-  input  logic [P.NE:0]            CvtCe,              // the cvt calculated expoent
-  // outputs
-  output logic [P.NE+1:0]          Me,                 // normalied fraction
-  output logic                     UfPlus1,            // do you add one to the result if given an unbounded exponent
-  output logic [P.NE+1:0]          FullRe,             // Re with bits to determine sign and overflow
-  output logic [P.NE-1:0]          Re,                 // Result exponent
-  output logic [P.NF-1:0]          Rf,                 // Result fractionNormS
-  output logic                     Sticky,             // sticky bit
-  output logic                     Plus1,              // do you add one to the final result
-  output logic                     Round, Guard        // bits needed to calculate rounding
-);
-
-  logic                            UfCalcPlus1;        // calculated plus one for unbounded exponent
-  logic                            NormSticky;         // normalized sum's sticky bit
-  logic [P.NF-1:0]                 RoundFrac;          // rounded fraction
-  logic                            FpRes;              // is the result a floating point
-  logic                            IntRes;             // is the result an integer
-  logic                            FpGuard, FpRound;   // floating point round/guard bits
-  logic                            FpLsbRes;           // least significant bit of floating point result
-  logic                            LsbRes;             // lsb of result
-  logic                            CalcPlus1;          // calculated plus1
-  logic                            FpPlus1;            // do you add one to the fp result 
-  logic [P.FLEN:0]                 RoundAdd;           // how much to add to the result
-  logic                            CvtToInt;           // Convert to integer operation
-
-// what position is XLEN in?
-//  options: 
-//     1: XLEN > NF   > NF1
-//     2: NF   > XLEN > NF1
-//     3: NF   > NF1  > XLEN
-//  single and double will always be smaller than XLEN
-//`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
-  localparam XLENPOS = P.XLEN > P.NF ? 1 : P.XLEN > P.NF1 ? 2 : 3;
-  
-  ///////////////////////////////////////////////////////////////////////////////
-  // Rounding
-  ///////////////////////////////////////////////////////////////////////////////
-
-  // round to nearest even
-  //      {Round, Sticky}
-  //      0x - do nothing
-  //      10 - tie - Plus1 if result is odd  (LSBNormSum = 1)
-  //         - don't add 1 if a small number was supposed to be subtracted
-  //      11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
-  //         - plus 1 otherwise
-
-  //  round to zero - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0
-
-  //  round to -infinity
-  //          - Plus1 if negative unless a small number was supposed to be subtracted from a result with guard and round bits of 0
-  //          - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0
-
-  //  round to infinity
-  //          - Plus1 if positive unless a small number was supposed to be subtracted from a result with guard and round bits of 0
-  //          - subtract 1 if a small number was supposed to be subtracted from a negative result with guard and round bits of 0
-
-  //  round to nearest max magnitude
-  //      {Guard, Round, Sticky}
-  //      0x - do nothing
-  //      10 - tie - Plus1
-  //         - don't add 1 if a small number was supposed to be subtracted
-  //      11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
-  //         - Plus 1 otherwise
-
-  // determine what format the final result is in: int or fp
-  assign IntRes = ToInt;
-  assign FpRes  = ~IntRes;
-  assign CvtToInt = ToInt; // under current encodings, CvtOp always is 1 when ToInt is selected, so leave it out
-
-  // sticky bit calculation
-  if (P.FPSIZES == 1) begin
-
-      //     1: XLEN > NF
-      //      |         XLEN          |
-      //      |    NF     |1|1|
-      //                     ^    ^ if floating point result
-      //                     ^ if not an FMA result
-      if (XLENPOS == 1)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes)  |
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
-      //     2: NF > XLEN
-      if (XLENPOS == 2)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&IntRes) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
-
-  end else if (P.FPSIZES == 2) begin
-      // XLEN is either 64 or 32
-      // so half and single are always smaller then XLEN
-
-      // 1: XLEN > NF   > NF1
-      if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
-      // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) | 
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
-      // 3: NF   > NF1  > XLEN
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&IntRes) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
-
-  end else if (P.FPSIZES == 3) begin
-      // 1: XLEN > NF   > NF1
-      if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
-      // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | 
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
-      // 3: NF   > NF1  > XLEN
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
-
-  end else if (P.FPSIZES == 4) begin
-      // Quad precision will always be greater than XLEN
-      // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) | 
-                                                (|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) | 
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
-      // 3: NF   > NF1  > XLEN
-      // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
-                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
-                                                (|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
-
-  end
-
-  // only add the Addend sticky if doing an FMA operation
-  //      - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
-  assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[P.NE+1]&FmaOp | DivSticky&DivOp;
-  
-  // determine round and LSB of the rounded value
-  //      - underflow round bit is used to determint the underflow flag
-  if (P.FPSIZES == 1) begin
-      assign FpGuard  = Mf[P.NORMSHIFTSZ-P.NF-1];
-      assign FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
-      assign FpRound  = Mf[P.NORMSHIFTSZ-P.NF-2];
-
-  end else if (P.FPSIZES == 2) begin
-      assign FpGuard  = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-1] : Mf[P.NORMSHIFTSZ-P.NF1-1];
-      assign FpLsbRes = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF] : Mf[P.NORMSHIFTSZ-P.NF1];
-      assign FpRound  = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-2] : Mf[P.NORMSHIFTSZ-P.NF1-2];
-
-  end else if (P.FPSIZES == 3) begin
-      always_comb
-          case (OutFmt)
-              P.FMT: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF-2];
-              end
-              P.FMT1: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF1-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF1];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF1-2];
-              end
-              P.FMT2: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF2-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF2];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF2-2];
-              end
-              default: begin
-                  FpGuard  = 1'bx;
-                  FpLsbRes = 1'bx;
-                  FpRound  = 1'bx;
-              end
-          endcase
-  end else if (P.FPSIZES == 4) begin
-      always_comb
-          case (OutFmt)
-              2'h3: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.Q_NF-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.Q_NF];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.Q_NF-2];
-              end
-              2'h1: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.D_NF-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.D_NF];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.D_NF-2];
-              end
-              2'h0: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.S_NF-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.S_NF];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.S_NF-2];
-              end
-              2'h2: begin
-                  FpGuard  = Mf[P.NORMSHIFTSZ-P.H_NF-1];
-                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.H_NF];
-                  FpRound  = Mf[P.NORMSHIFTSZ-P.H_NF-2];
-              end
-          endcase
-  end
-
-  assign Guard  = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-1] : FpGuard;
-  assign LsbRes = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN] : FpLsbRes;
-  assign Round  = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-2] : FpRound;
-
-  always_comb begin
-      // Determine if you add 1
-      case (Frm)
-          3'b000: CalcPlus1  = Guard & (Round|Sticky|LsbRes);//round to nearest even
-          3'b001: CalcPlus1  = 1'b0;//round to zero
-          3'b010: CalcPlus1  = Ms;//round down
-          3'b011: CalcPlus1  = ~Ms;//round up
-          3'b100: CalcPlus1  = Guard;//round to nearest max magnitude
-          default: CalcPlus1 = 1'bx;
-      endcase
-      // Determine if you add 1 (for underflow flag)
-      case (Frm)
-          3'b000: UfCalcPlus1  = Round & (Sticky|Guard);//round to nearest even
-          3'b001: UfCalcPlus1  = 1'b0;//round to zero
-          3'b010: UfCalcPlus1  = Ms;//round down
-          3'b011: UfCalcPlus1  = ~Ms;//round up
-          3'b100: UfCalcPlus1  = Round;//round to nearest max magnitude
-          default: UfCalcPlus1 = 1'bx;
-      endcase
-  
-  end
-
-  // If an answer is exact don't round
-  assign Plus1   = CalcPlus1 & (Sticky|Round|Guard);
-  assign FpPlus1 = Plus1&~(CvtToInt);
-  assign UfPlus1 = UfCalcPlus1 & (Sticky|Round);
-
-  // place Plus1 into the proper position for the format
-  if (P.FPSIZES == 1) begin
-      assign RoundAdd = {{P.FLEN{1'b0}}, FpPlus1};
-
-  end else if (P.FPSIZES == 2) begin
-      // \/FLEN+1
-      //  | NE+2 |        NF      |
-      //  '-NE+2-^----NF1----^
-      // P.FLEN+1-P.NE-2-P.NF1 = FLEN-1-NE-NF1
-      assign RoundAdd = {(P.NE+1+P.NF1)'(0), FpPlus1&~OutFmt, (P.NF-P.NF1-1)'(0), FpPlus1&OutFmt};
-
-  end else if (P.FPSIZES == 3) begin
-      assign RoundAdd = {(P.NE+1+P.NF2)'(0), FpPlus1&(OutFmt==P.FMT2), (P.NF1-P.NF2-1)'(0), FpPlus1&(OutFmt==P.FMT1), (P.NF-P.NF1-1)'(0), FpPlus1&(OutFmt==P.FMT)};
-
-  end else if (P.FPSIZES == 4)      
-      assign RoundAdd = {(P.Q_NE+1+P.H_NF)'(0), FpPlus1&(OutFmt==P.H_FMT), (P.S_NF-P.H_NF-1)'(0), FpPlus1&(OutFmt==P.S_FMT), (P.D_NF-P.S_NF-1)'(0), FpPlus1&(OutFmt==P.D_FMT), (P.Q_NF-P.D_NF-1)'(0), FpPlus1&(OutFmt==P.Q_FMT)};
-
-  // trim unneeded bits from fraction
-  assign RoundFrac = Mf[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.NF];
-  
-  // select the exponent
-  always_comb
-      case(PostProcSel)
-          2'b10:    Me = FmaMe; // fma
-          2'b00:    Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
-          // 2'b01: Me = DivDone ? Ue : 0; // divide
-          2'b01:    Me = Ue; // divide
-          default:  Me = '0; 
-      endcase
-
-
-
-  // round the result
-  //      - if the fraction overflows one should be added to the exponent
-  assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd;
-  assign Re           = FullRe[P.NE-1:0];
-
-endmodule
diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
deleted file mode 100644
index 0524ca364..000000000
--- a/src/fpu/postproc/shiftcorrection.sv
+++ /dev/null
@@ -1,95 +0,0 @@
-///////////////////////////////////////////
-// shiftcorrection.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: shift correction
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
-  input logic  [P.NORMSHIFTSZ-1:0] Shifted,                // normalization shifter output
-  // divsqrt
-  input logic                      DivOp,                  // is it a divsqrt operation
-  input logic                      DivResSubnorm,          // is the divsqrt result subnormal
-  input logic  [P.NE+1:0]          DivUe,                  // the divsqrt result's exponent
-  input logic                      DivSubnormShiftPos,     // is the subnorm divider shift amount positive (ie not underflowed)
-  //fma
-  input logic                      FmaOp,                  // is it an fma operation
-  input logic  [P.NE+1:0]          NormSumExp,             // exponent of the normalized sum not taking into account Subnormal or zero results
-  input logic                      FmaPreResultSubnorm,    // is the result subnormal - calculated before LZA corection
-  input logic                      FmaSZero,
-  // output
-  output logic [P.NE+1:0]          FmaMe,                  // exponent of the normalized sum
-  output logic [P.NORMSHIFTSZ-1:0] Mf,                     // the shifted sum after correction
-  output logic [P.NE+1:0]          Ue                      // corrected exponent for divider
-);
-
-  logic                            ResSubnorm;             // is the result Subnormal
-  logic                            LZAPlus1;               // add one or two to the sum's exponent due to LZA correction
-  logic                            LeftShiftQm;            // should the divsqrt result be shifted one to the left
-  logic                            RightShift;             // shift right by 1
-
-  // dh 4/16/24 this code is a mess and needs cleaning and explaining
-  // define bit widths
-  // seems to shift by 0, 1, or 2.  right and left shift is confusing
-  
-  // FMA LZA correction
-  // correct the shifting error caused by the LZA
-  //  - the only possible mantissa for a plus two is all zeroes 
-  //  - a one has to propagate all the way through a sum. so we can leave the bottom statement alone
-  assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1];
-
-  // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range
-  // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
-  assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); 
-
-  // Determine the shif for either FMA or divsqrt
-  assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm;
- 
-  // possible one bit right shift for FMA or division
-  // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
-  always_comb
-    if (FmaOp | (DivOp & ~DivResSubnorm))  // one bit shift for FMA or divsqrt
-      if (RightShift)                      Mf = {Shifted[P.NORMSHIFTSZ-2:1], 2'b00};
-      else                                 Mf = {Shifted[P.NORMSHIFTSZ-3:0], 2'b00};
-    else                                   Mf =  Shifted[P.NORMSHIFTSZ-1:0];  // convert and subnormal division result
-    
-  // Determine sum's exponent
-  //  main exponent issues: 
-  //      - LZA was one too large
-  //      - LZA was two too large
-  //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 1
-  //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 2
-  //                          if plus1                    If plus2                               kill if the result Zero or actually subnormal
-  //                          |                           |                                      |
-  assign FmaMe = (NormSumExp+{{P.NE+1{1'b0}}, LZAPlus1} +{{P.NE+1{1'b0}}, FmaPreResultSubnorm}) & {P.NE+2{~(FmaSZero|ResSubnorm)}};
-  
-  // recalculate if the result is subnormal after LZA correction
-  assign ResSubnorm = FmaPreResultSubnorm&~Shifted[P.NORMSHIFTSZ-2]&~Shifted[P.NORMSHIFTSZ-1];
-
-  // the quotent is in the range (.5,2) if there is no early termination
-  // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
-  assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1};
-endmodule
-
diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
deleted file mode 100644
index bb655942d..000000000
--- a/src/fpu/postproc/specialcase.sv
+++ /dev/null
@@ -1,369 +0,0 @@
-///////////////////////////////////////////
-// specialcase.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: special case selection
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module specialcase import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 Xs,                // X sign
-  input  logic [P.NF:0]        Xm, Ym, Zm,        // input significand's
-  input  logic                 XNaN, YNaN, ZNaN,  // are the inputs NaN
-  input  logic [2:0]           Frm,               // rounding mode
-  input  logic [P.FMTBITS-1:0] OutFmt,            // output format
-  input  logic                 InfIn,             // are any inputs infinity
-  input  logic                 NaNIn,             // are any input NaNs
-  input  logic                 XInf, YInf,        // are X or Y inifnity
-  input  logic                 XZero,             // is X zero
-  input  logic                 Plus1,             // do you add one for rounding
-  input  logic                 Rs,                // the result's sign
-  input  logic                 Invalid, Overflow, // flags to choose the result
-  input  logic [P.NE-1:0]      Re,                // Result exponent
-  input  logic [P.NE+1:0]      FullRe,            // Result full exponent
-  input  logic [P.NF-1:0]      Rf,                // Result fraction
-  // fma
-  input  logic                 FmaOp,             // is it a fma operation
-  // divsqrt
-  input  logic                 DivOp,             // is it a divsqrt operation
-  input  logic                 DivByZero,         // divide by zero flag
-  // cvt
-  input  logic                 CvtOp,             // is it a conversion operation
-  input  logic                 IntZero,           // is the integer input zero
-  input  logic                 IntToFp,           // is cvt int -> fp operation
-  input  logic                 Int64,             // is the integer 64 bits
-  input  logic                 Signed,            // is the integer signed
-  input  logic                 Zfa,               // Zfa conversion operation: fcvtmod.w.d
-  input  logic [P.NE:0]        CvtCe,             // the calculated expoent for cvt
-  input  logic                 IntInvalid,        // integer invalid flag to choose the result
-  input  logic                 CvtResUf,          // does the convert result underflow
-  input  logic [P.XLEN+1:0]    CvtNegRes,         // the possibly negated of the integer result
-  // outputs
-  output logic [P.FLEN-1:0]    PostProcRes,       // final result
-  output logic [P.XLEN-1:0]    FCvtIntRes         // final integer result
-);
-
-  logic [P.FLEN-1:0]   XNaNRes;    // X is NaN result
-  logic [P.FLEN-1:0]   YNaNRes;    // Y is NaN result
-  logic [P.FLEN-1:0]   ZNaNRes;    // Z is NaN result
-  logic [P.FLEN-1:0]   InvalidRes; // Invalid result result
-  logic [P.FLEN-1:0]   UfRes;      // underflowed result result
-  logic [P.FLEN-1:0]   OfRes;      // overflowed result result
-  logic [P.FLEN-1:0]   NormRes;    // normal result
-  logic [P.XLEN-1:0]   OfIntRes;   // the overflow result for integer output
-  logic [P.XLEN-1:0]   OfIntRes2;  // the overflow result for integer output after accounting for fcvtmod.w.d
-  logic [P.XLEN-1:0]   Int64Res;   // Result for conversion to 64-bit int after accounting for fcvtmod.w.d
-  logic                OfResMax;   // does the of result output maximum norm fp number
-  logic                KillRes;    // kill the result for underflow
-  logic                SelOfRes;   // should the overflow result be selected (excluding convert)
-  logic                SelCvtOfRes; // select overflow result for convert instruction
-
-  // does the overflow result output the maximum normalized floating point number
-  //                output infinity if the input is infinity
-  assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Rs) | (Frm[1:0]==2'b11&Rs));
-
-  // select correct outputs for special cases
-  if (P.FPSIZES == 1) begin
-      //NaN res selection depending on standard
-      if(P.IEEE754) begin
-          assign XNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-          assign YNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
-          assign ZNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
-          assign InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-      end else begin
-          assign InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-      end
-
-      assign OfRes   =  OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
-      assign UfRes   = {Rs, {P.FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)};
-      assign NormRes = {Rs, Re, Rf};
-
-  end else if (P.FPSIZES == 2) begin
-      if(P.IEEE754) begin
-          assign XNaNRes    = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
-          assign YNaNRes    = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF1]};
-          assign ZNaNRes    = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF1]};
-          assign InvalidRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-      end else begin 
-          assign InvalidRes = OutFmt ? {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}} : {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-      end
-
-      always_comb
-          if(OutFmt)
-              if(OfResMax)    OfRes = {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}};
-              else            OfRes = {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
-          else
-              if(OfResMax)    OfRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1-1{1'b1}}, 1'b0, {P.NF1{1'b1}}};
-              else            OfRes = {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1{1'b1}}, (P.NF1)'(0)};
-      assign UfRes = OutFmt ? {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)} : {{P.FLEN-P.LEN1{1'b1}}, Rs, (P.LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-      assign NormRes = OutFmt ? {Rs, Re, Rf} : {{P.FLEN-P.LEN1{1'b1}}, Rs, Re[P.NE1-1:0], Rf[P.NF-1:P.NF-P.NF1]};
-
-  end else if (P.FPSIZES == 3) begin
-      always_comb
-          case (OutFmt)
-              P.FMT: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-                      YNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
-                      ZNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
-                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-                  end else begin 
-                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-                  end
-                  
-                  OfRes   = OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
-                  UfRes   = {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {Rs, Re, Rf};
-              end
-              P.FMT1: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF1]};
-                      YNaNRes    = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF1]};
-                      ZNaNRes    = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF1]};
-                      InvalidRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-                  end else begin 
-                      InvalidRes = {{P.FLEN-P.LEN1{1'b1}}, 1'b0, {P.NE1{1'b1}}, 1'b1, (P.NF1-1)'(0)};
-                  end
-                  OfRes          = OfResMax ? {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1-1{1'b1}}, 1'b0, {P.NF1{1'b1}}} : {{P.FLEN-P.LEN1{1'b1}}, Rs, {P.NE1{1'b1}}, (P.NF1)'(0)};
-                  UfRes          = {{P.FLEN-P.LEN1{1'b1}}, Rs, (P.LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes        = {{P.FLEN-P.LEN1{1'b1}}, Rs, Re[P.NE1-1:0], Rf[P.NF-1:P.NF-P.NF1]};
-              end
-              P.FMT2: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.NF2]};
-                      YNaNRes    = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.NF2]};
-                      ZNaNRes    = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.NF2]};
-                      InvalidRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
-                  end else begin 
-                      InvalidRes = {{P.FLEN-P.LEN2{1'b1}}, 1'b0, {P.NE2{1'b1}}, 1'b1, (P.NF2-1)'(0)};
-                  end
-                  
-                  OfRes   = OfResMax ? {{P.FLEN-P.LEN2{1'b1}}, Rs, {P.NE2-1{1'b1}}, 1'b0, {P.NF2{1'b1}}} : {{P.FLEN-P.LEN2{1'b1}}, Rs, {P.NE2{1'b1}}, (P.NF2)'(0)};
-                  UfRes   = {{P.FLEN-P.LEN2{1'b1}}, Rs, (P.LEN2-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{P.FLEN-P.LEN2{1'b1}}, Rs, Re[P.NE2-1:0], Rf[P.NF-1:P.NF-P.NF2]};
-              end
-              default: begin
-                  if(P.IEEE754) begin
-                      XNaNRes    = (P.FLEN)'(0);
-                      YNaNRes    = (P.FLEN)'(0);
-                      ZNaNRes    = (P.FLEN)'(0);
-                      InvalidRes = (P.FLEN)'(0);
-                  end else begin 
-                      InvalidRes = (P.FLEN)'(0);
-                  end
-                  OfRes          = (P.FLEN)'(0);
-                  UfRes          = (P.FLEN)'(0);
-                  NormRes        = (P.FLEN)'(0);
-              end
-          endcase
-
-  end else if (P.FPSIZES == 4) begin 
-      always_comb
-          case (OutFmt)
-              2'h3: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Xm[P.NF-2:0]};
-                      YNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Ym[P.NF-2:0]};
-                      ZNaNRes    = {1'b0, {P.NE{1'b1}}, 1'b1, Zm[P.NF-2:0]};
-                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-                  end else begin 
-                      InvalidRes = {1'b0, {P.NE{1'b1}}, 1'b1, {P.NF-1{1'b0}}};
-                  end
-                  
-                  OfRes   = OfResMax ? {Rs, {P.NE-1{1'b1}}, 1'b0, {P.NF{1'b1}}} : {Rs, {P.NE{1'b1}}, {P.NF{1'b0}}};
-                  UfRes   = {Rs, (P.FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {Rs, Re, Rf};
-              end
-              2'h1: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.D_NF]};
-                      YNaNRes    = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.D_NF]};
-                      ZNaNRes    = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.D_NF]};
-                      InvalidRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
-                  end else begin 
-                      InvalidRes = {{P.FLEN-P.D_LEN{1'b1}}, 1'b0, {P.D_NE{1'b1}}, 1'b1, (P.D_NF-1)'(0)};
-                  end
-                  OfRes   = OfResMax ? {{P.FLEN-P.D_LEN{1'b1}}, Rs, {P.D_NE-1{1'b1}}, 1'b0, {P.D_NF{1'b1}}} : {{P.FLEN-P.D_LEN{1'b1}}, Rs, {P.D_NE{1'b1}}, (P.D_NF)'(0)};
-                  UfRes   = {{P.FLEN-P.D_LEN{1'b1}}, Rs, (P.D_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{P.FLEN-P.D_LEN{1'b1}}, Rs, Re[P.D_NE-1:0], Rf[P.NF-1:P.NF-P.D_NF]};
-              end
-              2'h0: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.S_NF]};
-                      YNaNRes    = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.S_NF]};
-                      ZNaNRes    = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.S_NF]};
-                      InvalidRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
-                  end else begin 
-                      InvalidRes = {{P.FLEN-P.S_LEN{1'b1}}, 1'b0, {P.S_NE{1'b1}}, 1'b1, (P.S_NF-1)'(0)};
-                  end
-                  
-                  OfRes   = OfResMax ? {{P.FLEN-P.S_LEN{1'b1}}, Rs, {P.S_NE-1{1'b1}}, 1'b0, {P.S_NF{1'b1}}} : {{P.FLEN-P.S_LEN{1'b1}}, Rs, {P.S_NE{1'b1}}, (P.S_NF)'(0)};
-                  UfRes   = {{P.FLEN-P.S_LEN{1'b1}}, Rs, (P.S_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{P.FLEN-P.S_LEN{1'b1}}, Rs, Re[P.S_NE-1:0], Rf[P.NF-1:P.NF-P.S_NF]};
-              end
-              2'h2: begin  
-                  if(P.IEEE754) begin
-                      XNaNRes    = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Xm[P.NF-2:P.NF-P.H_NF]};
-                      YNaNRes    = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Ym[P.NF-2:P.NF-P.H_NF]};
-                      ZNaNRes    = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, Zm[P.NF-2:P.NF-P.H_NF]};
-                      InvalidRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
-                  end else begin 
-                      InvalidRes = {{P.FLEN-P.H_LEN{1'b1}}, 1'b0, {P.H_NE{1'b1}}, 1'b1, (P.H_NF-1)'(0)};
-                  end
-                  
-                  OfRes   = OfResMax ? {{P.FLEN-P.H_LEN{1'b1}}, Rs, {P.H_NE-1{1'b1}}, 1'b0, {P.H_NF{1'b1}}} : {{P.FLEN-P.H_LEN{1'b1}}, Rs, {P.H_NE{1'b1}}, (P.H_NF)'(0)};      
-                // zero is exact if dividing by infinity so don't add 1
-                  UfRes   = {{P.FLEN-P.H_LEN{1'b1}}, Rs, (P.H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
-                  NormRes = {{P.FLEN-P.H_LEN{1'b1}}, Rs, Re[P.H_NE-1:0], Rf[P.NF-1:P.NF-P.H_NF]};
-              end
-          endcase
-  end
-
-  // determine if you shoould kill the res - Cvt
-  //      - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0
-  //      - dont set to zero if fp input is zero but not using the fp input
-  //      - dont set to zero if int input is zero but not using the int input
-  assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[P.NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResSubnorm & (Re!=1);
-  
-  // calculate if the overflow result should be selected
-  assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp));
-  
-  // output infinity with result sign if divide by zero
-  if(P.IEEE754)
-    always_comb
-      if(XNaN&~(IntToFp&CvtOp))   PostProcRes = XNaNRes;
-      else if(YNaN&~CvtOp)        PostProcRes = YNaNRes;
-      else if(ZNaN&FmaOp)         PostProcRes = ZNaNRes;
-      else if(Invalid)            PostProcRes = InvalidRes;
-      else if(SelOfRes)           PostProcRes = OfRes;
-      else if(KillRes)            PostProcRes = UfRes;
-      else                        PostProcRes = NormRes;
-  else
-    always_comb
-      if(NaNIn|Invalid)           PostProcRes = InvalidRes;
-      else if(SelOfRes)           PostProcRes = OfRes;
-      else if(KillRes)            PostProcRes = UfRes;
-      else                        PostProcRes = NormRes;
-
-  ///////////////////////////////////////////////////////////////////////////////////////
-  // integer result selection        
-  ///////////////////////////////////////////////////////////////////////////////////////        
-
-  // Causes undefined behavior for invalid:
-
-  // Invalid cases are different for IEEE 754 vs. RISC-V.  For RISC-V, typical results are used
-  // unsigned: if invalid (e.g., negative fp to unsigned int, result should overflow and
-  //           overflows to the maximum value 
-  // signed: if invalid, result should overflow to maximum negative value 
-  //         but is undefined and used for information only
-  // Note: The IEEE 754 result comes from values in TestFloat for x86_64
-   
-  // IEEE 754
-  // select the overflow integer res
-  //      - negative infinity and out of range negative input
-  //                 |  int   |  long  |
-  //          signed | -2^31  | -2^63  |
-  //        unsigned | 2^32-1 | 2^64-1 |
-  //
-  //      - positive infinity and out of range positive input and NaNs
-  //                 |   int  |  long  |
-  //          signed | -2^31  |-2^63   |
-  //        unsigned | 2^32-1 | 2^64-1 |
-  //
-  //      other: 32 bit unsigned res should be sign extended as if it were a signed number
-
-  // RISC-V
-  // select the overflow integer res
-  //      - negative infinity and out of range negative input
-  //                 |  int  |  long  |
-  //          signed | -2^31 | -2^63  |
-  //        unsigned |   0   |    0   |
-  //
-  //      - positive infinity and out of range positive input and NaNs
-  //                 |   int  |  long  |
-  //          signed | 2^31-1 | 2^63-1 |
-  //        unsigned | 2^32-1 | 2^64-1 |
-  //
-  //      other: 32 bit unsigned res should be sign extended as if it were a signed number
-
-    if(P.IEEE754) begin   
-      always_comb
-        if(Signed)
-            if(Xs&~NaNIn) // signed negative
-                    if(Int64)   OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
-                    else        OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
-            else          // signed positive
-                    if(Int64)   OfIntRes = {1'b1, {P.XLEN-1{1'b0}}}; 
-                    else        OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; 
-        else
-            if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b1}}; // unsigned negative 
-            else          OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
-    end else begin
-      always_comb
-        if(Signed)
-            if(Xs&~NaNIn) // signed negative
-                    if(Int64)   OfIntRes = {1'b1, {P.XLEN-1{1'b0}}};
-                    else        OfIntRes = {{P.XLEN-32{1'b1}}, 1'b1, {31{1'b0}}};
-            else          // signed positive
-                    if(Int64)   OfIntRes = {1'b0, {P.XLEN-1{1'b1}}};
-                    else        OfIntRes = {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}};
-        else
-            if(Xs&~NaNIn) OfIntRes = {P.XLEN{1'b0}}; // unsigned negative
-            else          OfIntRes = {P.XLEN{1'b1}}; // unsigned positive
-    end  
-   
-  // fcvtmod.w.d logic
-  // fcvtmod.w.d is like fcvt.w.d excep thtat it takes bits [31:0] and sign extends the rest,
-  // and converts +/-inf and NaN to zero.
-
-  if (P.ZFA_SUPPORTED & P.D_SUPPORTED) // fcvtmod.w.d support
-    always_comb begin
-        if (Zfa) OfIntRes2 = '0;                // fcvtmod.w.d produces 0 on overflow
-        else     OfIntRes2 = OfIntRes;
-        if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]};
-        else     Int64Res = CvtNegRes[P.XLEN-1:0];
-        if (Zfa) SelCvtOfRes = InfIn | NaNIn | (CvtCe > 32 + 52); // fcvtmod.w.d only overflows to 0 on NaN or Infinity, or if the shift is so large that only zeros are left
-        else     SelCvtOfRes = IntInvalid;    // regular fcvt gives an overflow if out of range
-    end
-  else 
-    always_comb begin // no fcvtmod.w.d support
-        OfIntRes2 = OfIntRes;
-        Int64Res = CvtNegRes[P.XLEN-1:0];
-        SelCvtOfRes = IntInvalid;
-    end
-
-  // select the integer output
-  //      - if the input is invalid (out of bounds NaN or Inf) then output overflow res
-  //      - if the input underflows
-  //          - if rounding and signed operation and negative input, output -1
-  //          - otherwise output a rounded 0
-  //      - otherwise output the normal res (trmined and sign extended if nessisary)
-  always_comb
-    if(SelCvtOfRes)         FCvtIntRes = OfIntRes2; 
-    else if(CvtCe[P.NE]) 
-      if(Xs&Signed&Plus1)   FCvtIntRes = {{P.XLEN{1'b1}}};
-      else                  FCvtIntRes = {{P.XLEN-1{1'b0}}, Plus1};
-    else if(Int64)          FCvtIntRes = Int64Res;
-    else                    FCvtIntRes = {{P.XLEN-32{CvtNegRes[31]}}, CvtNegRes[31:0]};
-endmodule
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
deleted file mode 100644
index c90ede41d..000000000
--- a/src/fpu/unpackinput.sv
+++ /dev/null
@@ -1,302 +0,0 @@
-///////////////////////////////////////////
-// unpackinput.sv
-//
-// Written: me@KatherineParry.com
-// Modified: 7/5/2022
-//
-// Purpose: unpack input: extract sign, exponent, significand, characteristics
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module unpackinput import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FLEN-1:0]        A,          // inputs from register file
-  input  logic                     En,         // enable the input
-  input  logic [P.FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-  input  logic                     FPUActive,  // Kill inputs when FPU is not active
-  output logic                     Sgn,        // sign bits of the number 
-  output logic [P.NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
-  output logic [P.NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
-  output logic                     NaN,        // is the number a NaN
-  output logic                     SNaN,       // is the number a signaling NaN
-  output logic                     Zero,       // is the number zero
-  output logic                     Inf,        // is the number infinity
-  output logic                     ExpMax,     // does In have the maximum exponent (NaN or Inf)
-  output logic                     Subnorm,    // is the number subnormal
-  output logic [P.FLEN-1:0]        PostBox     // Number reboxed correctly as a NaN
-);
-
-  logic [P.NF-1:0] Frac;        // Fraction of XYZ
-  logic            BadNaNBox;   // incorrectly NaN Boxed
-  logic            FracZero;    // is the fraction zero
-  logic            ExpNonZero;  // is the exponent non-zero
-  logic [P.FLEN-1:0] In;
-
-  // Gate input when FPU is not active to save power and simulation
-  assign In = A & {P.FLEN{FPUActive}};
-
-  if (P.FPSIZES == 1) begin        // if there is only one floating point format supported
-      assign BadNaNBox = 1'b0;
-      assign Sgn = In[P.FLEN-1];  // sign bit
-      assign Frac = In[P.NF-1:0];  // fraction (no assumed 1)
-      assign ExpNonZero = |In[P.FLEN-2:P.NF];  // is the exponent non-zero
-      assign Exp = {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero};  // exponent.  subnormal numbers have effective biased exponent of 1
-      assign ExpMax = &In[P.FLEN-2:P.NF];  // is the exponent all 1's
-      assign PostBox = In;
-  
-  end else if (P.FPSIZES == 2) begin   // if there are 2 floating point formats supported
-      // largest format | smaller format
-      //----------------------------------
-      //      P.FLEN     |     P.LEN1       length of floating point number
-      //      P.NE       |     P.NE1        length of exponent
-      //      P.NF       |     P.NF1        length of fraction
-      //      P.BIAS     |     P.BIAS1      exponent's bias value
-      //      P.FMT      |     P.FMT1       precision's format value - Q=11 D=01 Sticky=00 H=10
-
-      // Possible combinantions specified by spec:
-      //      double and single
-      //      single and half
-
-      // Not needed but can also handle:
-      //      quad   and double
-      //      quad   and single
-      //      quad   and half
-      //      double and half
-
-      assign BadNaNBox = ~(Fmt|(&In[P.FLEN-1:P.LEN1])); // Check NaN boxing
-      always_comb
-        if (BadNaNBox) begin
-          PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
-        end else 
-          PostBox = In;
-
-      // choose sign bit depending on format - 1=larger precsion 0=smaller precision
-      assign Sgn = Fmt ? In[P.FLEN-1] : (BadNaNBox ? 0 : In[P.LEN1-1]); // improperly boxed NaNs are treated as positive
-
-      // extract the fraction, add trailing zeroes to the mantissa if nessisary
-      assign Frac = Fmt ? In[P.NF-1:0] : {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
-
-      // is the exponent non-zero
-      assign ExpNonZero = Fmt ? |In[P.FLEN-2:P.NF] : |In[P.LEN1-2:P.NF1]; 
-
-      // example double to single conversion:
-      // 1023 = 0011 1111 1111
-      // 127  = 0000 0111 1111 (subtract this)
-      // 896  = 0011 1000 0000
-      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
-      // dexp = 0bdd dbbb bbbb 
-      // also need to take into account possible zero/Subnorm/inf/NaN values
-
-      // extract the exponent, converting the smaller exponent into the larger precision if nessisary
-      //      - if the original precision had a Subnormal number convert the exponent value 1
-      assign Exp = Fmt ? {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero} : {In[P.LEN1-2], {P.NE-P.NE1{~In[P.LEN1-2]}}, In[P.LEN1-3:P.NF1+1], In[P.NF1]|~ExpNonZero}; 
-
-      // is the exponent all 1's
-      assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
-  
-  end else if (P.FPSIZES == 3) begin       // three floating point precsions supported
-
-      // largest format | larger format  | smallest format
-      //---------------------------------------------------
-      //      P.FLEN     |     P.LEN1      |    P.LEN2       length of floating point number
-      //      P.NE       |     P.NE1       |    P.NE2        length of exponent
-      //      P.NF       |     P.NF1       |    P.NF2        length of fraction
-      //      P.BIAS     |     P.BIAS1     |    P.BIAS2      exponent's bias value
-      //      P.FMT      |     P.FMT1      |    P.FMT2       precision's format value - Q=11 D=01 Sticky=00 H=10
-
-      // Possible combinantions specified by spec:
-      //      quad   and double and single
-      //      double and single and half
-
-      // Not needed but can also handle:
-      //      quad   and double and half
-      //      quad   and single and half
-
-      // Check NaN boxing
-      always_comb
-          case (Fmt)
-              P.FMT:  BadNaNBox = 1'b0;
-              P.FMT1: BadNaNBox = ~&In[P.FLEN-1:P.LEN1];
-              P.FMT2: BadNaNBox = ~&In[P.FLEN-1:P.LEN2];
-              default: BadNaNBox = 1'bx;
-          endcase
-
-      always_comb
-        if (BadNaNBox & Fmt == P.FMT1)
-            PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
-        else if (BadNaNBox) // Fmt == P.FMT2
-            PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
-        else
-            PostBox = In;
-
-      // extract the sign bit
-      always_comb
-        if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive
-        else
-          case (Fmt)
-              P.FMT:   Sgn = In[P.FLEN-1];
-              P.FMT1:  Sgn = In[P.LEN1-1];
-              P.FMT2:  Sgn = In[P.LEN2-1];
-              default: Sgn = 1'bx;
-          endcase
-
-       // extract the fraction
-      always_comb
-          case (Fmt)
-              P.FMT:   Frac = In[P.NF-1:0];
-              P.FMT1:  Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
-              P.FMT2:  Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)};
-              default: Frac = {P.NF{1'bx}};
-          endcase
-
-      // is the exponent non-zero
-      always_comb
-          case (Fmt)
-              P.FMT:   ExpNonZero = |In[P.FLEN-2:P.NF];   // if input is largest precision (P.FLEN - ie quad or double)
-              P.FMT1:  ExpNonZero = |In[P.LEN1-2:P.NF1];  // if input is larger precsion (P.LEN1 - double or single)
-              P.FMT2:  ExpNonZero = |In[P.LEN2-2:P.NF2];  // if input is smallest precsion (P.LEN2 - single or half)
-              default: ExpNonZero = 1'bx; 
-          endcase
-          
-      // example double to single conversion:
-      // 1023 = 0011 1111 1111
-      // 127  = 0000 0111 1111 (subtract this)
-      // 896  = 0011 1000 0000
-      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
-      // dexp = 0bdd dbbb bbbb 
-      // also need to take into account possible zero/Subnorm/inf/NaN values
-
-      // convert the larger precision's exponent to use the largest precision's bias
-      always_comb 
-          case (Fmt)
-              P.FMT:  Exp = {In[P.FLEN-2:P.NF+1], In[P.NF]|~ExpNonZero};
-              P.FMT1: Exp = {In[P.LEN1-2], {P.NE-P.NE1{~In[P.LEN1-2]}}, In[P.LEN1-3:P.NF1+1], In[P.NF1]|~ExpNonZero}; 
-              P.FMT2: Exp = {In[P.LEN2-2], {P.NE-P.NE2{~In[P.LEN2-2]}}, In[P.LEN2-3:P.NF2+1], In[P.NF2]|~ExpNonZero}; 
-              default: Exp = {P.NE{1'bx}};
-          endcase
-
-      // is the exponent all 1's
-      always_comb
-          case (Fmt)
-              P.FMT:  ExpMax = &In[P.FLEN-2:P.NF];
-              P.FMT1: ExpMax = &In[P.LEN1-2:P.NF1];
-              P.FMT2: ExpMax = &In[P.LEN2-2:P.NF2];
-              default: ExpMax = 1'bx;
-          endcase
-
-  end else if (P.FPSIZES == 4) begin      // if all precsisons are supported - quad, double, single, and half
-  
-      //    quad   |  double  |  single  |  half    
-      //-------------------------------------------------------------------
-      //   P.Q_LEN  |  P.D_LEN  |  P.S_LEN  |  P.H_LEN     length of floating point number
-      //   P.Q_NE   |  P.D_NE   |  P.S_NE   |  P.H_NE      length of exponent
-      //   P.Q_NF   |  P.D_NF   |  P.S_NF   |  P.H_NF      length of fraction
-      //   P.Q_BIAS |  P.D_= 1'b1; |  P.S_BIAS |  P.H_BIAS    exponent's bias value
-      //   P.Q_FMT  |  P.D_FMT  |  P.S_FMT  |  P.H_FMT     precision's format value - Q=11 D=01 Sticky=00 H=10
-
-      // Check NaN boxing
-      always_comb
-          case (Fmt)
-              2'b11: BadNaNBox = 1'b0;
-              2'b01: BadNaNBox = ~&In[P.Q_LEN-1:P.D_LEN];
-              2'b00: BadNaNBox = ~&In[P.Q_LEN-1:P.S_LEN];
-              2'b10: BadNaNBox = ~&In[P.Q_LEN-1:P.H_LEN];
-          endcase
-
-      always_comb
-        if (BadNaNBox) begin
-          case (Fmt)
-            2'b11: PostBox = In;
-            2'b01: PostBox = {{(P.Q_LEN-P.D_LEN){1'b1}}, 1'b1, {(P.D_NE+1){1'b1}}, {(P.D_LEN-P.D_NE-2){1'b0}}};
-            2'b00: PostBox = {{(P.Q_LEN-P.S_LEN){1'b1}}, 1'b1, {(P.S_NE+1){1'b1}}, {(P.S_LEN-P.S_NE-2){1'b0}}};
-            2'b10: PostBox = {{(P.Q_LEN-P.H_LEN){1'b1}}, 1'b1, {(P.H_NE+1){1'b1}}, {(P.H_LEN-P.H_NE-2){1'b0}}};
-          endcase
-        end else 
-          PostBox = In;
-
-      // extract sign bit
-      always_comb
-        if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive
-        else
-          case (Fmt)
-              2'b11: Sgn = In[P.Q_LEN-1];
-              2'b01: Sgn = In[P.D_LEN-1];
-              2'b00: Sgn = In[P.S_LEN-1];
-              2'b10: Sgn = In[P.H_LEN-1];
-          endcase
-
-      // extract the fraction
-      always_comb
-          case (Fmt)
-              2'b11: Frac = In[P.Q_NF-1:0];
-              2'b01: Frac = {In[P.D_NF-1:0], (P.Q_NF-P.D_NF)'(0)};
-              2'b00: Frac = {In[P.S_NF-1:0], (P.Q_NF-P.S_NF)'(0)};
-              2'b10: Frac = {In[P.H_NF-1:0], (P.Q_NF-P.H_NF)'(0)};
-          endcase
-
-      // is the exponent non-zero
-      always_comb
-          case (Fmt)
-              2'b11: ExpNonZero = |In[P.Q_LEN-2:P.Q_NF];
-              2'b01: ExpNonZero = |In[P.D_LEN-2:P.D_NF];
-              2'b00: ExpNonZero = |In[P.S_LEN-2:P.S_NF]; 
-              2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF]; 
-          endcase
-
-      // example double to single conversion:
-      // 1023 = 0011 1111 1111
-      // 127  = 0000 0111 1111 (subtract this)
-      // 896  = 0011 1000 0000
-      // sexp = 0000 bbbb bbbb (add this) b = bit d = ~b 
-      // dexp = 0bdd dbbb bbbb 
-      // also need to take into account possible zero/Subnorm/inf/NaN values
-      
-      // convert the double precsion exponent into quad precsion
-      // 1 is added to the exponent if the input is zero or subnormal
-      always_comb
-          case (Fmt)
-              2'b11: Exp = {In[P.Q_LEN-2:P.Q_NF+1], In[P.Q_NF]|~ExpNonZero};
-              2'b01: Exp = {In[P.D_LEN-2], {P.Q_NE-P.D_NE{~In[P.D_LEN-2]}}, In[P.D_LEN-3:P.D_NF+1], In[P.D_NF]|~ExpNonZero};
-              2'b00: Exp = {In[P.S_LEN-2], {P.Q_NE-P.S_NE{~In[P.S_LEN-2]}}, In[P.S_LEN-3:P.S_NF+1], In[P.S_NF]|~ExpNonZero};
-              2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero}; 
-          endcase
-  
-      // is the exponent all 1's
-      always_comb 
-          case (Fmt)
-              2'b11: ExpMax = &In[P.Q_LEN-2:P.Q_NF];
-              2'b01: ExpMax = &In[P.D_LEN-2:P.D_NF];
-              2'b00: ExpMax = &In[P.S_LEN-2:P.S_NF];
-              2'b10: ExpMax = &In[P.H_LEN-2:P.H_NF];
-          endcase
-
-  end
-
-  // Output logic
-  assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero?
-  assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
-  assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
-  assign SNaN = NaN&~Frac[P.NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero & En; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
-  assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
-
-endmodule
diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
deleted file mode 100644
index 9151a35d2..000000000
--- a/src/generic/mem/ram1p1rwbe.sv
+++ /dev/null
@@ -1,137 +0,0 @@
-///////////////////////////////////////////
-// ram1p1r2be.sv
-// 1 port sram with byte enables
-//
-// Written: rose@rosethompson.net
-// Created: 3 May 2021
-// Modified: 20 January 2023
-//
-// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
-//          Basic sram with 1 read write port.
-//          When clk rises Addr and LineWriteData are sampled.
-//          Following the clk edge read data is output from the sampled Addr.
-// 
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
-
-module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRELOAD_ENABLED=0) (
-  input logic                     clk,
-  input logic                     ce,
-  input logic [$clog2(DEPTH)-1:0] addr,
-  input logic [WIDTH-1:0]         din,
-  input logic                     we,
-  input logic [(WIDTH-1)/8:0]     bwe,
-  output logic [WIDTH-1:0]        dout
-);
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // TRUE SRAM macro
-  ///////////////////////////////////////////////////////////////////////////////
-  if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
-    genvar index;
-    // 64 x 128-bit SRAM
-    logic [WIDTH-1:0] BitWriteMask;
-    for (index=0; index < WIDTH; index++) 
-      assign BitWriteMask[index] = bwe[index/8];
-    ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB(~BitWriteMask), .Q(dout));
-    
-  end else if ((USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
-    genvar index;
-    // 64 x 44-bit SRAM
-    logic [WIDTH-1:0] BitWriteMask;
-    for (index=0; index < WIDTH; index++) 
-      assign BitWriteMask[index] = bwe[index/8];
-    ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB(~BitWriteMask), .Q(dout));
-
-  end else if ((USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
-    genvar index;
-    // 64 x 22-bit SRAM
-    logic [WIDTH-1:0] BitWriteMask;
-    for (index=0; index < WIDTH; index++) 
-      assign BitWriteMask[index] = bwe[index/8];
-    ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB(~BitWriteMask), .Q(dout));     
-    
-    ///////////////////////////////////////////////////////////////////////////////
-    // READ first SRAM model
-    ///////////////////////////////////////////////////////////////////////////////
-  end else begin: ram
-    bit [WIDTH-1:0] RAM[DEPTH-1:0];
-
-    // if (PRELOAD_ENABLED) begin
-    //   initial begin
-    //     RAM[0] = 64'h00600100d2e3ca40;
-    //   end
-    // end
-
-    `ifdef VERILATOR
-      import "DPI-C" function string getenvval(input string env_name);
-    `endif
-
-    initial 
-      if (PRELOAD_ENABLED) begin
-        if (WIDTH == 64) begin
-          `ifdef VERILATOR
-            // because Verilator doesn't automatically accept $WALLY from shell
-            string       WALLY_DIR = getenvval("WALLY"); 
-            $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0);  // load boot RAM for FPGA
-          `else
-            $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0);  // load boot RAM for FPGA
-          `endif
-        end else begin // put something in the RAM so it is not optimized away
-        RAM[0] = 'h00002197;
-        end
-      end
-    
-    // Combinational read: register address and read after clock edge
-    logic [$clog2(DEPTH)-1:0] addrd;
-    flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
-    assign dout = RAM[addrd];
-
-    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
-     always_ff @(posedge clk) 
-     if(ce) dout <= mem[addr]; */
-
-    // Write divided into part for bytes and part for extra msbs
-    // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
-    // Therefore these always blocks use the older always @(posedge clk) 
-    if(WIDTH >= 8) begin
-      integer i;
-      always @(posedge clk) 
-        if (ce & we) 
-          for(i = 0; i < WIDTH/8; i++) 
-            if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8];
-    end
-  
-    if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-      always @(posedge clk) 
-        if (ce & we & bwe[WIDTH/8])
-          RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= din[WIDTH-1:WIDTH-WIDTH%8];
-  end
-
-endmodule
diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv
deleted file mode 100755
index 1b5e1bdb7..000000000
--- a/src/generic/mem/ram1p1rwbe_64x22.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-///////////////////////////////////////////
-// ram1p1rwbe_64x22.sv
-//
-// Written: james.stine@okstate.edu 2 Feburary 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram1p1rwbe_64x22( 
-  input  logic          CLK, 
-  input  logic          CEB, 
-  input  logic          WEB,
-  input  logic [5:0]    A, 
-  input  logic [21:0]   D,
-  input  logic [21:0]   BWEB, 
-  output logic [21:0]   Q
-);
-
-   // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
-   // use part of a larger RAM to avoid generating more flavors of RAM
-  logic [43:0] Qfull;
-  TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D({22'b0, D[21:0]}), .BWEB({22'b0, BWEB[21:0]}), .Q(Qfull));
-  assign Q = Qfull[21:0];
-   // genericRAM #(64, 22) sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
-
-endmodule
diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv
deleted file mode 100644
index 1744ba59f..000000000
--- a/src/generic/mem/ram1p1rwbe_64x44.sv
+++ /dev/null
@@ -1,42 +0,0 @@
-///////////////////////////////////////////
-// ram1p1rwbe_64x44.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram1p1rwbe_64x44( 
-  input  logic          CLK, 
-  input  logic          CEB, 
-  input  logic          WEB,
-  input  logic [5:0]    A, 
-  input  logic [43:0]   D,
-  input  logic [43:0]   BWEB, 
-  output logic [43:0]   Q
-);
-
-   // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
-   // generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
-   TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
-
-endmodule
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
deleted file mode 100644
index 84effae19..000000000
--- a/src/generic/mem/ram1p1rwe.sv
+++ /dev/null
@@ -1,95 +0,0 @@
-///////////////////////////////////////////
-// ram1p1rwe.sv
-// 1 port sram.
-//
-// Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by rose@rosethompson.net)
-// Created: 04 April 2023
-//
-// Purpose: ram1p1wre, but without byte-enable. Used for icache data.
-//          Be careful using this module, since coverage is turned off for (ce & we).
-//          In read-only caches, we never get (we=1, ce=0), so this waiver is needed.
-// 
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
-
-module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
-  input logic                     clk,
-  input logic                     ce,
-  input logic [$clog2(DEPTH)-1:0] addr,
-  input logic [WIDTH-1:0]         din,
-  input logic                     we,
-  output logic [WIDTH-1:0]        dout
-);
-
-  //////////////////////////////////////////////////////////////////////////////
-  // TRUE SRAM macro
-  //////////////////////////////////////////////////////////////////////////////
-  if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
-    // 64 x 128-bit SRAM
-    ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB('0), .Q(dout));
-    
-  end else if ((USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
-    // 64 x 44-bit SRAM
-    ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB('0), .Q(dout));
-
-  end else if ((USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
-    // 64 x 22-bit SRAM
-    ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we),
-      .A(addr), .D(din), 
-      .BWEB('0), .Q(dout));     
-    
-    //////////////////////////////////////////////////////////////////////////////
-    // READ first SRAM model
-    //////////////////////////////////////////////////////////////////////////////
-  end else begin: ram
-    // Vivado is not implementing this as block ram for some reason.
-    // The version with byte write enables it correctly infers block ram.
-
-    bit [WIDTH-1:0]               RAM[DEPTH-1:0];
-
-    // Combinational read: register address and read after clock edge
-    logic [$clog2(DEPTH)-1:0] addrd;
-    flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
-    assign dout = RAM[addrd];
-
-    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
-     always_ff @(posedge clk) 
-     if(ce) dout <= mem[addr]; */
-
-    // Write divided into part for bytes and part for extra msbs
-    // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
-    // Therefore these always blocks use the older always @(posedge clk) 
-    always @(posedge clk)
-      // coverage off
-      // ce only goes low when cachefsm is in READY state and Flush is asserted.
-      // for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state.
-      // so we can never get we=1, ce=0 for I$.
-      if (ce & we)
-        // coverage on
-        RAM[addr] <= din;
-  end
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
deleted file mode 100644
index 95840c2cc..000000000
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-///////////////////////////////////////////
-// ram2p1r1wbe.sv
-// 2 port sram.
-//
-// Written: rose@rosethompson.net May 3, 2021
-//          Two port SRAM 1 read port and 1 write port.
-//          When clk rises Addr and LineWriteData are sampled.
-//          Following the clk edge read data is output from the sampled Addr.
-//          Write
-// Modified: james.stine@okstate.edu Feb 1, 2023
-//           Integration of memories 
-//
-// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
-
-module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) (
-  input  logic                     clk,
-  input  logic                     ce1, ce2,
-  input  logic [$clog2(DEPTH)-1:0] ra1,
-  input  logic [WIDTH-1:0]         wd2,
-  input  logic [$clog2(DEPTH)-1:0] wa2,
-  input  logic                     we2,
-  input  logic [(WIDTH-1)/8:0]     bwe2,
-  output logic [WIDTH-1:0]         rd1
-);
-
-  localparam                      SRAMWIDTH = 32;
-  localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
-
-  ///////////////////////////////////////////////////////////////////////////////
-  // TRUE SRAM macro
-  ///////////////////////////////////////////////////////////////////////////////
-
-  if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
-    
-    ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
-      .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(1'b0), .WEBB(~we2),            
-      .AA(ra1), .AB(wa2),
-      .DA('0),
-      .DB(wd2),
-      .BWEBA('0), .BWEBB('1),
-      .QA(rd1),
-      .QB());
-
-  end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin
-    
-    ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
-      .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(1'b0), .WEBB(~we2),            
-      .AA(ra1), .AB(wa2),
-      .DA('0),
-      .DB(wd2),
-      .BWEBA('0), .BWEBB('1),
-      .QA(rd1),
-      .QB());      
-
-  end else if ((USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin
-
-    logic [SRAMWIDTH-1:0]     SRAMReadData;      
-    logic [SRAMWIDTH-1:0]     SRAMWriteData;      
-    logic [SRAMWIDTH-1:0]     RD1Sets[SRAMNUMSETS-1:0];
-    logic [SRAMNUMSETS-1:0]   SRAMBitMaskPre;      
-    logic [SRAMWIDTH-1:0]     SRAMBitMask;      
-    logic [$clog2(DEPTH)-1:0] RA1Q;
-    
-    onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
-    genvar                    index;
-    for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
-      assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)];   
-      assign SRAMWriteData[index*2+1:index*2] = wd2;
-      assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}};      
-    end
-    flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q);      
-    assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
-    ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), 
-      .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(1'b0), .WEBB(~we2),            
-      .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
-      .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
-      .DA('0),
-      .DB(SRAMWriteData),
-      .BWEBA('0), .BWEBB(SRAMBitMask),
-      .QA(SRAMReadData),
-      .QB());
-
-  end else begin:ram
-    
-    ///////////////////////////////////////////////////////////////////////////////
-    // READ first SRAM model
-    ///////////////////////////////////////////////////////////////////////////////
-
-    bit [WIDTH-1:0] RAM[DEPTH-1:0];
-
-    // Read
-    logic [$clog2(DEPTH)-1:0] ra1d;
-    flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
-    assign rd1 = RAM[ra1d];
-    
-    // Write divided into part for bytes and part for extra msbs
-    // coverage off     
-    //   when byte write enables are tied high, the last IF is always taken
-    if(WIDTH >= 8) begin
-      integer i;
-      always @(posedge clk) 
-        if (ce2 & we2) 
-          for(i = 0; i < WIDTH/8; i++) 
-            if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
-    end
-    // coverage on
-  
-    if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
-      always @(posedge clk) 
-        if (ce2 & we2 & bwe2[WIDTH/8])
-          RAM[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
-  end
-  
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv
deleted file mode 100755
index d499442b4..000000000
--- a/src/generic/mem/ram2p1r1wbe_1024x36.sv
+++ /dev/null
@@ -1,56 +0,0 @@
-///////////////////////////////////////////
-// ram2p1rwbe_1024x36.sv
-//
-// Written: james.stine@okstate.edu 2 February 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram2p1r1wbe_1024x36( 
-  input  logic          CLKA, 
-  input  logic          CLKB, 
-  input  logic          CEBA, 
-  input  logic          CEBB, 
-  input  logic          WEBA,
-  input  logic          WEBB,
-  input  logic [9:0]    AA, 
-  input  logic [9:0]    AB, 
-  input  logic [35:0]   DA,
-  input  logic [35:0]   DB,
-  input  logic [35:0]   BWEBA, 
-  input  logic [35:0]   BWEBB, 
-  output logic [35:0]   QA,
-  output logic [35:0]   QB
-);
-
-   // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor
-   //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-   //           .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-   // use part of a larger RAM to avoid generating more flavors of RAM
-  logic [67:0] QAfull, QBfull;
-  TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-    .AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}), 
-    .BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull));
-  assign QA = QAfull[35:0];
-  assign QB = QBfull[35:0];
-
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv
deleted file mode 100755
index a1633f8e9..000000000
--- a/src/generic/mem/ram2p1r1wbe_1024x68.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// ram2p1rwbe_1024x68.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram2p1r1wbe_1024x68( 
-  input  logic          CLKA, 
-  input  logic          CLKB, 
-  input  logic          CEBA, 
-  input  logic          CEBB, 
-  input  logic          WEBA,
-  input  logic          WEBB,
-  input  logic [9:0]    AA, 
-  input  logic [9:0]    AB, 
-  input  logic [67:0]   DA,
-  input  logic [67:0]   DB,
-  input  logic [67:0]   BWEBA, 
-  input  logic [67:0]   BWEBB, 
-  output logic [67:0]   QA,
-  output logic [67:0]   QB
-);
-
-   // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor
-   //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-   //         .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-  TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-    .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv
deleted file mode 100644
index 54d0ee8dc..000000000
--- a/src/generic/mem/ram2p1r1wbe_128x64.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// ram2p1rwbe_128x64.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram2p1r1wbe_128x64( 
-  input  logic          CLKA, 
-  input  logic          CLKB, 
-  input  logic          CEBA, 
-  input  logic          CEBB, 
-  input  logic          WEBA,
-  input  logic          WEBB,
-  input  logic [6:0]    AA, 
-  input  logic [6:0]    AB, 
-  input  logic [63:0]   DA,
-  input  logic [63:0]   DB,
-  input  logic [63:0]   BWEBA, 
-  input  logic [63:0]   BWEBB, 
-  output logic [63:0]   QA,
-  output logic [63:0]   QB
-);
-
-   // replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor
-  TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-    .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-  // generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-//         .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_2048x64.sv b/src/generic/mem/ram2p1r1wbe_2048x64.sv
deleted file mode 100644
index 95185346a..000000000
--- a/src/generic/mem/ram2p1r1wbe_2048x64.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// ram2p1rwbe_2048x64.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram2p1r1wbe_2048x64( 
-  input  logic          CLKA, 
-  input  logic          CLKB, 
-  input  logic          CEBA, 
-  input  logic          CEBB, 
-  input  logic          WEBA,
-  input  logic          WEBB,
-  input  logic [8:0]    AA, 
-  input  logic [8:0]    AB, 
-  input  logic [63:0]   DA,
-  input  logic [63:0]   DB,
-  input  logic [63:0]   BWEBA, 
-  input  logic [63:0]   BWEBB, 
-  output logic [63:0]   QA,
-  output logic [63:0]   QB
-);
-
-   // replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor
-  TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-    .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-  // generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-//         .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-
-endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv
deleted file mode 100755
index db3cbc846..000000000
--- a/src/generic/mem/ram2p1r1wbe_64x32.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-///////////////////////////////////////////
-// ram2p1rwbe_64x32.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: RAM wrapper for instantiating RAM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ram2p1r1wbe_64x32( 
-  input  logic          CLKA, 
-  input  logic          CLKB, 
-  input  logic          CEBA, 
-  input  logic          CEBB, 
-  input  logic          WEBA,
-  input  logic          WEBB,
-  input  logic [5:0]    AA, 
-  input  logic [5:0]    AB, 
-  input  logic [31:0]   DA,
-  input  logic [31:0]   DB,
-  input  logic [31:0]   BWEBA, 
-  input  logic [31:0]   BWEBB, 
-  output logic [31:0]   QA,
-  output logic [31:0]   QB
-);
-
-   // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor
-   //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-   //       .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-  TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, 
-    .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
-endmodule
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
deleted file mode 100644
index e17b8af60..000000000
--- a/src/generic/mem/rom1p1r.sv
+++ /dev/null
@@ -1,221 +0,0 @@
-///////////////////////////////////////////
-// rom1p1r
-//
-// Written: David_Harris@hmc.edu 8/24/22
-//
-// Purpose: Single-ported ROM
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// This model actually works correctly with vivado.
-
-module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
-  (input  logic                  clk,
-   input  logic                  ce,
-   input  logic [ADDR_WIDTH-1:0] addr,
-   output logic [DATA_WIDTH-1:0] dout
-);
-
-
-   // Core Memory
-   bit [DATA_WIDTH-1:0]    ROM [(2**ADDR_WIDTH)-1:0];
-   
-   // dh 10/30/23 ROM macros are presently commented out
-   // because they don't point to a generated ROM
-/*   if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin
-      rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
-
-   end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin
- rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
-
-  end else begin */
-
-  `ifdef VERILATOR
-    import "DPI-C" function string getenvval(input string env_name);
-  `endif
-  
-  initial 
-    if (PRELOAD_ENABLED) begin
-      if (DATA_WIDTH == 64) begin
-        `ifdef VERILATOR
-            // because Verilator doesn't automatically accept $WALLY from shell
-            string       WALLY_DIR = getenvval("WALLY"); 
-            $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0);  // load boot ROM for FPGA
-        `else
-            $readmemh({"$WALLY/fpga/src/boot.mem"}, ROM, 0);  // load boot ROM for FPGA
-        `endif
-      end else begin // put something in the ROM so it is not optimized away
-        ROM[0] = 'h00002197;
-      end
-    end
-
-  always_ff @ (posedge clk) 
-    if(ce) dout <= ROM[addr];
-   
-   // for FPGA, initialize with zero-stage bootloader
-   /*if(PRELOAD_ENABLED) begin
-      initial begin
-        ROM[0]=64'h8001819300002197;
-        ROM[1]=64'h4281420141014081;
-        ROM[2]=64'h4481440143814301;
-        ROM[3]=64'h4681460145814501;
-        ROM[4]=64'h4881480147814701;
-        ROM[5]=64'h4a814a0149814901;
-        ROM[6]=64'h4c814c014b814b01;
-        ROM[7]=64'h4e814e014d814d01;
-        ROM[8]=64'h0110011b4f814f01;
-        ROM[9]=64'h059b45011161016e;
-        ROM[10]=64'h0004063705fe0010;
-        ROM[11]=64'h1f6000ef8006061b;
-        ROM[12]=64'h0ff003930000100f;
-        ROM[13]=64'h4e952e3110060e37;
-        ROM[14]=64'hc602829b0053f2b7;
-        ROM[15]=64'h2023fe02dfe312fd;
-        ROM[16]=64'h829b0053f2b7007e;
-        ROM[17]=64'hfe02dfe312fdc602;
-        ROM[18]=64'h4de31efd000e2023;
-        ROM[19]=64'h059bf1402573fdd0;
-        ROM[20]=64'h0000061705e20870;
-        ROM[21]=64'h0010029b01260613;
-        ROM[22]=64'h68110002806702fe;
-        ROM[23]=64'h0085179bf0080813;
-        ROM[24]=64'h038008130107f7b3;
-        ROM[25]=64'h480508a86c632781;
-        ROM[26]=64'h1533357902a87963;
-        ROM[27]=64'h38030000181700a8;
-        ROM[28]=64'h1c6301057833f268;
-        ROM[29]=64'h081a403018370808;
-        ROM[30]=64'h0105783342280813;
-        ROM[31]=64'h1815751308081063;
-        ROM[32]=64'h00367513c295e14d;
-        ROM[33]=64'h654ded510207e793;
-        ROM[34]=64'hc1701ff00613f130;
-        ROM[35]=64'h0637c530fff6861b;
-        ROM[36]=64'h664dcd10167d0200;
-        ROM[37]=64'h17fd001007b7c25c;
-        ROM[38]=64'h859b5a5cc20cd21c;
-        ROM[39]=64'h02062a23dfed0007;
-        ROM[40]=64'h4785fffd561c664d;
-        ROM[41]=64'h4501461c06f59063;
-        ROM[42]=64'h4a1cc35c465cc31c;
-        ROM[43]=64'he29dc75c4a5cc71c;
-        ROM[44]=64'h0c63086008138082;
-        ROM[45]=64'h1ae30a9008130105;
-        ROM[46]=64'hb7710017e793f905;
-        ROM[47]=64'he793b75901d7e793;
-        ROM[48]=64'h5f5c674db7410197;
-        ROM[49]=64'h66cd02072e23dffd;
-        ROM[50]=64'hfff78513ff7d5698;
-        ROM[51]=64'h40a0053300a03533;
-        ROM[52]=64'hbfb100a7e7938082;
-        ROM[53]=64'he0a2715d8082557d;
-        ROM[54]=64'he486f052f44ef84a;
-        ROM[55]=64'hfa13e85aec56fc26;
-        ROM[56]=64'h843289ae892a0086;
-        ROM[57]=64'h00959993000a1463;
-        ROM[58]=64'h864ac4396b054a85;
-        ROM[59]=64'h0009859b4549870a;
-        ROM[60]=64'h0004049b05540363;
-        ROM[61]=64'h86a66485008b7363;
-        ROM[62]=64'h870a87aaec7ff0ef;
-        ROM[63]=64'h4531458146014681;
-        ROM[64]=64'hf0ef0207c9639c05;
-        ROM[65]=64'h17820094979beb1f;
-        ROM[66]=64'h873e020541639381;
-        ROM[67]=64'h993e99ba020a1963;
-        ROM[68]=64'h870aa8094501f85d;
-        ROM[69]=64'he8bff0ef45454685;
-        ROM[70]=64'h60a64505fe0559e3;
-        ROM[71]=64'h79a2794274e26406;
-        ROM[72]=64'h61616b426ae27a02;
-        ROM[73]=64'h9301020497138082;
-        ROM[74]=64'hf40647057179b7f1;
-        ROM[75]=64'hd79867cdec26f022;
-        ROM[76]=64'hdff58b85571c674d;
-        ROM[77]=64'h2423d35c03600793;
-        ROM[78]=64'hfffd571c674d0207;
-        ROM[79]=64'h0007a737b00026f3;
-        ROM[80]=64'hb00027f311f70713;
-        ROM[81]=64'h674dfef77de38f95;
-        ROM[82]=64'h4f5ccf9d8b895b1c;
-        ROM[83]=64'h26f3cf5c0027e793;
-        ROM[84]=64'h071305f5e737b000;
-        ROM[85]=64'h8f95b00027f30ff7;
-        ROM[86]=64'h4f5c674dfef77de3;
-        ROM[87]=64'hb00026f3cf5c9bf5;
-        ROM[88]=64'h67f7071300989737;
-        ROM[89]=64'h7de38f95b00027f3;
-        ROM[90]=64'h458146014681fef7;
-        ROM[91]=64'hddbff0ef4501870a;
-        ROM[92]=64'h059346014681870a;
-        ROM[93]=64'hdcbff0ef45211aa0;
-        ROM[94]=64'h1aa007134782e939;
-        ROM[95]=64'h816393d117d24411;
-        ROM[96]=64'h85220ff0041302e7;
-        ROM[97]=64'h614564e270a27402;
-        ROM[98]=64'h46e3da5ff0efa0cd;
-        ROM[99]=64'h0207c7634782fe05;
-        ROM[100]=64'h458146014681870a;
-        ROM[101]=64'hd8bff0ef03700513;
-        ROM[102]=64'h46014681870a87aa;
-        ROM[103]=64'h0a900513403005b7;
-        ROM[104]=64'h4409bf7dfc07d9e3;
-        ROM[105]=64'hc3998b8583f9bfe1;
-        ROM[106]=64'h4681870a00846413;
-        ROM[107]=64'hf0ef450945814601;
-        ROM[108]=64'h870afa0540e3d59f;
-        ROM[109]=64'h123405b746014681;
-        ROM[110]=64'h46e3d45ff0ef450d;
-        ROM[111]=64'h870a77c14482f805;
-        ROM[112]=64'h85a6460146818cfd;
-        ROM[113]=64'h4ae3d2dff0ef451d;
-        ROM[114]=64'hd3d8470567cdf605;
-        ROM[115]=64'h000f4737b00026f3;
-        ROM[116]=64'hb00027f323f70713;
-        ROM[117]=64'h67cdfef77de38f95;
-        ROM[118]=64'h4681870a0007ae23;
-        ROM[119]=64'h0370051385a64601;
-        ROM[120]=64'hf2054fe3cf7ff0ef;
-        ROM[121]=64'h458146014681870a;
-        ROM[122]=64'hce3ff0ef08600513;
-        ROM[123]=64'h4681870af20545e3;
-        ROM[124]=64'h4541200005934601;
-        ROM[125]=64'hf0055de3ccfff0ef;
-        ROM[126]=64'h3023bf010113bf09;
-        ROM[127]=64'h4605842a86aa4081;
-        ROM[128]=64'h40113423850a4585;
-        ROM[129]=64'h86a265a6da5ff0ef;
-        ROM[130]=64'hd99ff0ef04084605;
-        ROM[131]=64'h2201358322813603;
-        ROM[132]=64'h86a2260508700513;
-        ROM[133]=64'hd81ff0ef05629e0d;
-        ROM[134]=64'h2a0135832a813603;
-        ROM[135]=64'h9e0d86a226054505;
-        ROM[136]=64'h3603d6bff0ef057e;
-        ROM[137]=64'h0513320135833281;
-        ROM[138]=64'h9e0d86a226054010;
-        ROM[139]=64'h3083d53ff0ef0556;
-        ROM[140]=64'h4501400134034081;
-        ROM[141]=64'h0000808241010113;
-        
-      end // if (PRELOAD_ENABLED)  
-   end*/
-
-endmodule 
diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv
deleted file mode 100755
index 7a86bc50e..000000000
--- a/src/generic/mem/rom1p1r_128x64.sv
+++ /dev/null
@@ -1,39 +0,0 @@
-///////////////////////////////////////////
-// rom1p1r_128x64.sv
-//
-// Written: james.stine@okstate.edu 28 January 2023
-// Modified: 
-//
-// Purpose: ROM wrapper for instantiating ROM IP
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module rom1p1r_128x64( 
-  input  logic        CLK, 
-  input  logic        CEB, 
-  input  logic [6:0]  A, 
-  output logic [63:0] Q
-);
-
-   // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
-  ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q);
-//   generic64x128ROM romIP (.CLK, .CEB, .A, .Q); 
-
-endmodule
diff --git a/src/ieu/aes/aes32d.sv b/src/ieu/aes/aes32d.sv
deleted file mode 100644
index f761b5060..000000000
--- a/src/ieu/aes/aes32d.sv
+++ /dev/null
@@ -1,41 +0,0 @@
-///////////////////////////////////////////
-// aes32d.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes32dsmi and aes32dsi instruction: RV32 middle and final round AES decryption
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes32d(
-   input  logic [7:0]  SboxIn,
-   input  logic        finalround,
-   output logic [31:0] result
-);
-
-   logic [7:0] 			  SboxOut;
-   logic [31:0] 		     so, mixed;
-   
-   aesinvsbox8 inv_sbox(SboxIn, SboxOut);          // Apply inverse sbox to si
-   aesinvmixcolumns8 mix(SboxOut, mixed);          // Run so through the InvMixColumns AES function
-   assign so = {24'h0, SboxOut};                   // Pad output of inverse substitution box
-   mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
-endmodule
diff --git a/src/ieu/aes/aes32e.sv b/src/ieu/aes/aes32e.sv
deleted file mode 100644
index ab28db196..000000000
--- a/src/ieu/aes/aes32e.sv
+++ /dev/null
@@ -1,41 +0,0 @@
-///////////////////////////////////////////
-// aes32e.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes32esmi and aes32esi instruction: RV32 middle and final round AES encryption
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes32e(
-   input  logic [7:0]  SboxIn,
-   input  logic        finalround,
-   output logic [31:0] result
-);                
-                
-   logic [7:0] 			  SboxOut;
-   logic [31:0] 		     so, mixed;
-   
-   aessbox8 sbox(SboxIn, SboxOut);                 // Substitute
-   assign so = {24'h0, SboxOut};                   // Pad sbox output
-   aesmixcolumns32 mb(so, mixed);                  // Mix using MixColumns component
-   mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip MixColumns
-endmodule
diff --git a/src/ieu/aes/aes64d.sv b/src/ieu/aes/aes64d.sv
deleted file mode 100644
index 517dd4bf0..000000000
--- a/src/ieu/aes/aes64d.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// aes64d.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes64dsm and aes64ds instruction: RV64 middle and final round AES decryption 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes64d(
-   input  logic [63:0] rs1,
-   input  logic [63:0] rs2,
-   input  logic        finalround, aes64im,
-   output logic [63:0] result
-);
-   
-   logic [63:0] 		    ShiftRowsOut, SboxOut, MixcolsIn, MixcolsOut;
-   
-   // Apply inverse shiftrows to rs2 and rs1
-   aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
-   
-   // Apply full word inverse substitution to lower doubleord of shiftrow out
-   aesinvsbox64 invsbox(ShiftRowsOut,  SboxOut);
-   
-   mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolsIn);
-   
-   // Apply inverse MixColumns to sbox outputs
-   aesinvmixcolumns32 invmw0(MixcolsIn[31:0], MixcolsOut[31:0]);
-   aesinvmixcolumns32 invmw1(MixcolsIn[63:32], MixcolsOut[63:32]);
-   
-   // Final round skips mixcolumns.
-   mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
-endmodule
diff --git a/src/ieu/aes/aes64e.sv b/src/ieu/aes/aes64e.sv
deleted file mode 100644
index f4b59178a..000000000
--- a/src/ieu/aes/aes64e.sv
+++ /dev/null
@@ -1,55 +0,0 @@
-///////////////////////////////////////////
-// aes64e.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes64esm and aes64es instruction: RV64 middle and final round AES encryption 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes64e(
-    input  logic [63:0] rs1,
-    input  logic [63:0] rs2,
-    input  logic        finalround, 
-    input  logic [31:0] Sbox0Out,
-    output logic [31:0] SboxEIn,
-    output logic [63:0] result
-);
-  
-    logic [63:0]  ShiftRowsOut, SboxOut, MixcolsOut;
-                
-    // AES shiftrow unit
-    aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
-   
-    // Apply substitution box to 2 lower words
-    // Use the shared sbox in zknde64.sv for the first sbox
-    assign SboxEIn = ShiftRowsOut[31:0];
-    assign SboxOut[31:0] = Sbox0Out;
-
-    aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
-
-    // Apply MixColumns operations
-    aesmixcolumns32 mw0(SboxOut[31:0],  MixcolsOut[31:0]);
-    aesmixcolumns32 mw1(SboxOut[63:32], MixcolsOut[63:32]);
-
-    // Skip mixcolumns on last round
-    mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
-endmodule
diff --git a/src/ieu/aes/aes64ks1i.sv b/src/ieu/aes/aes64ks1i.sv
deleted file mode 100644
index cb2d71018..000000000
--- a/src/ieu/aes/aes64ks1i.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-///////////////////////////////////////////
-// aes64ks1i.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes64ks1i instruction: part of AES keyschedule with involving sbox
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes64ks1i(
-   input  logic [3:0]   round,
-   input  logic [63:32] rs1,
-   input  logic [31:0]  Sbox0Out,
-   output logic [31:0]  SboxKIn,
-   output logic [63:0]  result
-);                 
-                 
-   logic 			        finalround;
-   logic [31:0] 		     rcon, rs1Rotate;
-   
-   rconlut32 rc(round, rcon);                             // Get rcon value from lookup table
-   assign rs1Rotate = {rs1[39:32], rs1[63:40]};           // Get rotated value fo ruse in tmp2
-   assign finalround = (round == 4'b1010);                // round 10 is the last one 
-   assign SboxKIn = finalround ? rs1[63:32] : rs1Rotate;  // Don't rotate on the last round
-
-   // Share sbox with encryption in zknde64.  This module just sends value to shared sbox and gets result back
-   // send out value as SboxKIn, get back subsittuted result as Sbox0Out
-
-   assign result[31:0]  = Sbox0Out ^ rcon;
-   assign result[63:32] = Sbox0Out ^ rcon;	
-endmodule
-
diff --git a/src/ieu/aes/aes64ks2.sv b/src/ieu/aes/aes64ks2.sv
deleted file mode 100644
index b5209d799..000000000
--- a/src/ieu/aes/aes64ks2.sv
+++ /dev/null
@@ -1,39 +0,0 @@
-///////////////////////////////////////////
-// aes64ks2.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aes64ks2 instruction: part of AES keyschedule
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aes64ks2(
-   input  logic [63:0]  rs2,
-   input  logic [63:32] rs1,
-   output logic [63:0]  result
-);
-   
-   logic [31:0] 		    w0, w1;
-   
-   assign w0 = rs1[63:32] ^ rs2[31:0];
-   assign w1 = w0 ^ rs2[63:32];   
-   assign result = {w1, w0};   
-endmodule
diff --git a/src/ieu/aes/aesinvmixcolumns32.sv b/src/ieu/aes/aesinvmixcolumns32.sv
deleted file mode 100644
index d340a6bc3..000000000
--- a/src/ieu/aes/aesinvmixcolumns32.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-///////////////////////////////////////////
-// aesinvmixcolumns32.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 05 March 2024
-//
-// Purpose: AES Inverted Mix Column Function for use with AES
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesinvmixcolumns32(
-   input  logic [31:0] a, 
-   output logic [31:0] y
-);
-
-   logic [7:0] a0, a1, a2, a3, temp;
-   logic [10:0] xor0, xor1, xor2, xor3;
-   
-   assign {a0, a1, a2, a3} = a;
-   assign temp = a0 ^ a1 ^ a2 ^ a3;
-
-   assign xor0 = {temp, 3'b0} ^ {1'b0, a3^a1, 2'b0} ^ {2'b0, a3^a2, 1'b0} ^ {3'b0, temp} ^ {3'b0, a3};
-   assign xor1 = {temp, 3'b0} ^ {1'b0, a2^a0, 2'b0} ^ {2'b0, a2^a1, 1'b0} ^ {3'b0, temp} ^ {3'b0, a2};
-   assign xor2 = {temp, 3'b0} ^ {1'b0, a1^a3, 2'b0} ^ {2'b0, a1^a0, 1'b0} ^ {3'b0, temp} ^ {3'b0, a1};
-   assign xor3 = {temp, 3'b0} ^ {1'b0, a0^a2, 2'b0} ^ {2'b0, a0^a3, 1'b0} ^ {3'b0, temp} ^ {3'b0, a0};
-
-   galoismultinverse8 gm0 (xor0, y[7:0]);
-   galoismultinverse8 gm1 (xor1, y[15:8]);
-   galoismultinverse8 gm2 (xor2, y[23:16]);
-   galoismultinverse8 gm3 (xor3, y[31:24]);
-endmodule 
diff --git a/src/ieu/aes/aesinvmixcolumns8.sv b/src/ieu/aes/aesinvmixcolumns8.sv
deleted file mode 100644
index 134ceeb11..000000000
--- a/src/ieu/aes/aesinvmixcolumns8.sv
+++ /dev/null
@@ -1,47 +0,0 @@
-///////////////////////////////////////////
-// aesinvmixcolumns8.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 05 March 2024
-//
-// Purpose: AES Inverted Mix Column Function for use with AES
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesinvmixcolumns8(
-   input  logic [7:0] a, 
-   output logic [31:0] y
-);
-
-   logic [10:0] t, x0, x1, x2, x3;
-
-   // aes32d operates on shifted versions of the input
-   assign t  = {a, 3'b0} ^ {3'b0, a};
-   assign x0 = {a, 3'b0} ^ {1'b0, a, 2'b0} ^ {2'b0, a, 1'b0};
-   assign x1 = t;
-   assign x2 = t ^ {1'b0, a, 2'b0};
-   assign x3 = t ^ {2'b0, a, 1'b0};
-
-   galoismultinverse8 gm0 (x0, y[7:0]);
-   galoismultinverse8 gm1 (x1, y[15:8]);
-   galoismultinverse8 gm2 (x2, y[23:16]);
-   galoismultinverse8 gm3 (x3, y[31:24]);
-
- endmodule 
diff --git a/src/ieu/aes/aesinvsbox64.sv b/src/ieu/aes/aesinvsbox64.sv
deleted file mode 100644
index ce838cb29..000000000
--- a/src/ieu/aes/aesinvsbox64.sv
+++ /dev/null
@@ -1,42 +0,0 @@
-///////////////////////////////////////////
-// aesinvsbox64.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: 4 sets of Rinjdael Inverse S-BOX for whole word look up
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesinvsbox64(
-   input  logic [63:0] a, 
-   output logic [63:0] y
-);
-   
-   // inverse substitutions boxes for each byte of the 32-bit word
-   aesinvsbox8 sbox0(a[7:0],   y[7:0]);
-   aesinvsbox8 sbox1(a[15:8],  y[15:8]);
-   aesinvsbox8 sbox2(a[23:16], y[23:16]);	
-   aesinvsbox8 sbox3(a[31:24], y[31:24]);   
-   aesinvsbox8 sbox4(a[39:32], y[39:32]);   
-   aesinvsbox8 sbox5(a[47:40], y[47:40]);   
-   aesinvsbox8 sbox6(a[55:48], y[55:48]);   
-   aesinvsbox8 sbox7(a[63:56], y[63:56]);   
-endmodule
diff --git a/src/ieu/aes/aesinvsbox8.sv b/src/ieu/aes/aesinvsbox8.sv
deleted file mode 100644
index 344f444eb..000000000
--- a/src/ieu/aes/aesinvsbox8.sv
+++ /dev/null
@@ -1,292 +0,0 @@
-///////////////////////////////////////////
-// aesinvsbox8.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: Rinjdael Inverted S-BOX in form of a LUT
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesinvsbox8(
-	input  logic [7:0] a, 
-	output logic [7:0] y
-);
-
-   always_comb
-	case(a)
-	  8'h00 : y = 8'h52;
-	  8'h01 : y = 8'h09;
-	  8'h02 : y = 8'h6A;
-	  8'h03 : y = 8'hD5;
-	  8'h04 : y = 8'h30;
-	  8'h05 : y = 8'h36;
-	  8'h06 : y = 8'hA5;
-	  8'h07 : y = 8'h38;
-	  8'h08 : y = 8'hBF;
-	  8'h09 : y = 8'h40;
-	  8'h0A : y = 8'hA3;
-	  8'h0B : y = 8'h9E;
-	  8'h0C : y = 8'h81;
-	  8'h0D : y = 8'hF3;
-	  8'h0E : y = 8'hD7;
-	  8'h0F : y = 8'hFB;
-	  8'h10 : y = 8'h7C;
-	  8'h11 : y = 8'hE3;
-	  8'h12 : y = 8'h39;
-	  8'h13 : y = 8'h82;
-	  8'h14 : y = 8'h9B;
-	  8'h15 : y = 8'h2F;
-	  8'h16 : y = 8'hFF;
-	  8'h17 : y = 8'h87;
-	  8'h18 : y = 8'h34;
-	  8'h19 : y = 8'h8E;
-	  8'h1A : y = 8'h43;
-	  8'h1B : y = 8'h44;
-	  8'h1C : y = 8'hC4;
-	  8'h1D : y = 8'hDE;
-	  8'h1E : y = 8'hE9;
-	  8'h1F : y = 8'hCB;
-	  8'h20 : y = 8'h54;
-	  8'h21 : y = 8'h7B;
-	  8'h22 : y = 8'h94;
-	  8'h23 : y = 8'h32;
-	  8'h24 : y = 8'hA6;
-	  8'h25 : y = 8'hC2;
-	  8'h26 : y = 8'h23;
-	  8'h27 : y = 8'h3D;
-	  8'h28 : y = 8'hEE;
-	  8'h29 : y = 8'h4C;
-	  8'h2A : y = 8'h95;
-	  8'h2B : y = 8'h0B;
-	  8'h2C : y = 8'h42;
-	  8'h2D : y = 8'hFA;
-	  8'h2E : y = 8'hC3;
-	  8'h2F : y = 8'h4E;
-	  8'h30 : y = 8'h08;
-	  8'h31 : y = 8'h2E;
-	  8'h32 : y = 8'hA1;
-	  8'h33 : y = 8'h66;
-	  8'h34 : y = 8'h28;
-	  8'h35 : y = 8'hD9;
-	  8'h36 : y = 8'h24;
-	  8'h37 : y = 8'hB2;
-	  8'h38 : y = 8'h76;
-	  8'h39 : y = 8'h5B;
-	  8'h3A : y = 8'hA2;
-	  8'h3B : y = 8'h49;
-	  8'h3C : y = 8'h6D;
-	  8'h3D : y = 8'h8B;
-	  8'h3E : y = 8'hD1;
-	  8'h3F : y = 8'h25;
-	  8'h40 : y = 8'h72;
-	  8'h41 : y = 8'hF8;
-	  8'h42 : y = 8'hF6;
-	  8'h43 : y = 8'h64;
-	  8'h44 : y = 8'h86;
-	  8'h45 : y = 8'h68;
-	  8'h46 : y = 8'h98;
-	  8'h47 : y = 8'h16;
-	  8'h48 : y = 8'hD4;
-	  8'h49 : y = 8'hA4;
-	  8'h4A : y = 8'h5C;
-	  8'h4B : y = 8'hCC;
-	  8'h4C : y = 8'h5D;
-	  8'h4D : y = 8'h65;
-	  8'h4E : y = 8'hB6;
-	  8'h4F : y = 8'h92;
-	  8'h50 : y = 8'h6C;
-	  8'h51 : y = 8'h70;
-	  8'h52 : y = 8'h48;
-	  8'h53 : y = 8'h50;
-	  8'h54 : y = 8'hFD;
-	  8'h55 : y = 8'hED;
-	  8'h56 : y = 8'hB9;
-	  8'h57 : y = 8'hDA;
-	  8'h58 : y = 8'h5E;
-	  8'h59 : y = 8'h15;
-	  8'h5A : y = 8'h46;
-	  8'h5B : y = 8'h57;
-	  8'h5C : y = 8'hA7;
-	  8'h5D : y = 8'h8D;
-	  8'h5E : y = 8'h9D;
-	  8'h5F : y = 8'h84;
-	  8'h60 : y = 8'h90;
-	  8'h61 : y = 8'hD8;
-	  8'h62 : y = 8'hAB;
-	  8'h63 : y = 8'h00;
-	  8'h64 : y = 8'h8C;
-	  8'h65 : y = 8'hBC;
-	  8'h66 : y = 8'hD3;
-	  8'h67 : y = 8'h0A;
-	  8'h68 : y = 8'hF7;
-	  8'h69 : y = 8'hE4;
-	  8'h6A : y = 8'h58;
-	  8'h6B : y = 8'h05;
-	  8'h6C : y = 8'hB8;
-	  8'h6D : y = 8'hB3;
-	  8'h6E : y = 8'h45;
-	  8'h6F : y = 8'h06;
-	  8'h70 : y = 8'hD0;
-	  8'h71 : y = 8'h2C;
-	  8'h72 : y = 8'h1E;
-	  8'h73 : y = 8'h8F;
-	  8'h74 : y = 8'hCA;
-	  8'h75 : y = 8'h3F;
-	  8'h76 : y = 8'h0F;
-	  8'h77 : y = 8'h02;
-	  8'h78 : y = 8'hC1;
-	  8'h79 : y = 8'hAF;
-	  8'h7A : y = 8'hBD;
-	  8'h7B : y = 8'h03;
-	  8'h7C : y = 8'h01;
-	  8'h7D : y = 8'h13;
-	  8'h7E : y = 8'h8A;
-	  8'h7F : y = 8'h6B;
-	  8'h80 : y = 8'h3A;
-	  8'h81 : y = 8'h91;
-	  8'h82 : y = 8'h11;
-	  8'h83 : y = 8'h41;
-	  8'h84 : y = 8'h4F;
-	  8'h85 : y = 8'h67;
-	  8'h86 : y = 8'hDC;
-	  8'h87 : y = 8'hEA;
-	  8'h88 : y = 8'h97;
-	  8'h89 : y = 8'hF2;
-	  8'h8A : y = 8'hCF;
-	  8'h8B : y = 8'hCE;
-	  8'h8C : y = 8'hF0;
-	  8'h8D : y = 8'hB4;
-	  8'h8E : y = 8'hE6;
-	  8'h8F : y = 8'h73;
-	  8'h90 : y = 8'h96;
-	  8'h91 : y = 8'hAC;
-	  8'h92 : y = 8'h74;
-	  8'h93 : y = 8'h22;
-	  8'h94 : y = 8'hE7;
-	  8'h95 : y = 8'hAD;
-	  8'h96 : y = 8'h35;
-	  8'h97 : y = 8'h85;
-	  8'h98 : y = 8'hE2;
-	  8'h99 : y = 8'hF9;
-	  8'h9A : y = 8'h37;
-	  8'h9B : y = 8'hE8;
-	  8'h9C : y = 8'h1C;
-	  8'h9D : y = 8'h75;
-	  8'h9E : y = 8'hDF;
-	  8'h9F : y = 8'h6E;
-	  8'hA0 : y = 8'h47;
-	  8'hA1 : y = 8'hF1;
-	  8'hA2 : y = 8'h1A;
-	  8'hA3 : y = 8'h71;
-	  8'hA4 : y = 8'h1D;
-	  8'hA5 : y = 8'h29;
-	  8'hA6 : y = 8'hC5;
-	  8'hA7 : y = 8'h89;
-	  8'hA8 : y = 8'h6F;
-	  8'hA9 : y = 8'hB7;
-	  8'hAA : y = 8'h62;
-	  8'hAB : y = 8'h0E;
-	  8'hAC : y = 8'hAA;
-	  8'hAD : y = 8'h18;
-	  8'hAE : y = 8'hBE;
-	  8'hAF : y = 8'h1B;
-	  8'hB0 : y = 8'hFC;
-	  8'hB1 : y = 8'h56;
-	  8'hB2 : y = 8'h3E;
-	  8'hB3 : y = 8'h4B;
-	  8'hB4 : y = 8'hC6;
-	  8'hB5 : y = 8'hD2;
-	  8'hB6 : y = 8'h79;
-	  8'hB7 : y = 8'h20;
-	  8'hB8 : y = 8'h9A;
-	  8'hB9 : y = 8'hDB;
-	  8'hBA : y = 8'hC0;
-	  8'hBB : y = 8'hFE;
-	  8'hBC : y = 8'h78;
-	  8'hBD : y = 8'hCD;
-	  8'hBE : y = 8'h5A;
-	  8'hBF : y = 8'hF4;
-	  8'hC0 : y = 8'h1F;
-	  8'hC1 : y = 8'hDD;
-	  8'hC2 : y = 8'hA8;
-	  8'hC3 : y = 8'h33;
-	  8'hC4 : y = 8'h88;
-	  8'hC5 : y = 8'h07;
-	  8'hC6 : y = 8'hC7;
-	  8'hC7 : y = 8'h31;
-	  8'hC8 : y = 8'hB1;
-	  8'hC9 : y = 8'h12;
-	  8'hCA : y = 8'h10;
-	  8'hCB : y = 8'h59;
-	  8'hCC : y = 8'h27;
-	  8'hCD : y = 8'h80;
-	  8'hCE : y = 8'hEC;
-	  8'hCF : y = 8'h5F;
-	  8'hD0 : y = 8'h60;
-	  8'hD1 : y = 8'h51;
-	  8'hD2 : y = 8'h7F;
-	  8'hD3 : y = 8'hA9;
-	  8'hD4 : y = 8'h19;
-	  8'hD5 : y = 8'hB5;
-	  8'hD6 : y = 8'h4A;
-	  8'hD7 : y = 8'h0D;
-	  8'hD8 : y = 8'h2D;
-	  8'hD9 : y = 8'hE5;
-	  8'hDA : y = 8'h7A;
-	  8'hDB : y = 8'h9F;
-	  8'hDC : y = 8'h93;
-	  8'hDD : y = 8'hC9;
-	  8'hDE : y = 8'h9C;
-	  8'hDF : y = 8'hEF;
-	  8'hE0 : y = 8'hA0;
-	  8'hE1 : y = 8'hE0;
-	  8'hE2 : y = 8'h3B;
-	  8'hE3 : y = 8'h4D;
-	  8'hE4 : y = 8'hAE;
-	  8'hE5 : y = 8'h2A;
-	  8'hE6 : y = 8'hF5;
-	  8'hE7 : y = 8'hB0;
-	  8'hE8 : y = 8'hC8;
-	  8'hE9 : y = 8'hEB;
-	  8'hEA : y = 8'hBB;
-	  8'hEB : y = 8'h3C;
-	  8'hEC : y = 8'h83;
-	  8'hED : y = 8'h53;
-	  8'hEE : y = 8'h99;
-	  8'hEF : y = 8'h61;
-	  8'hF0 : y = 8'h17;
-	  8'hF1 : y = 8'h2B;
-	  8'hF2 : y = 8'h04;
-	  8'hF3 : y = 8'h7E;
-	  8'hF4 : y = 8'hBA;
-	  8'hF5 : y = 8'h77;
-	  8'hF6 : y = 8'hD6;
-	  8'hF7 : y = 8'h26;
-	  8'hF8 : y = 8'hE1;
-	  8'hF9 : y = 8'h69;
-	  8'hFA : y = 8'h14;
-	  8'hFB : y = 8'h63;
-	  8'hFC : y = 8'h55;
-	  8'hFD : y = 8'h21;
-	  8'hFE : y = 8'h0C;
-	  8'hFF : y = 8'h7D;
-	endcase
-endmodule
diff --git a/src/ieu/aes/aesinvshiftrows64.sv b/src/ieu/aes/aesinvshiftrows64.sv
deleted file mode 100644
index 7e24f67c8..000000000
--- a/src/ieu/aes/aesinvshiftrows64.sv
+++ /dev/null
@@ -1,37 +0,0 @@
-///////////////////////////////////////////
-// aesinvshiftrows64.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: AES Shiftrow
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesinvshiftrows64(
-   /* verilator lint_off UNUSEDSIGNAL */
-   input  logic [127:0] a,
-   /* verilator lint_on UNUSEDSIGNAL */
-   output logic [63:0]  y
-);
-
-   assign y = {a[95:88],   a[119:112], a[15:8],    a[39:32],
-               a[63:56],   a[87:80],   a[111:104], a[7:0]};
-endmodule
diff --git a/src/ieu/aes/aesmixcolumns32.sv b/src/ieu/aes/aesmixcolumns32.sv
deleted file mode 100644
index ee5ad53b5..000000000
--- a/src/ieu/aes/aesmixcolumns32.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-///////////////////////////////////////////
-// aesmixcolumns32.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
-// Created: 20 February 2024
-//
-// Purpose: Galois field operation to an individual 32-bit word
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-module aesmixcolumns32(
-   input  logic [31:0] a, 
-   output logic [31:0] y
-);
-
-   logic [7:0] a0, a1, a2, a3, y0, y1, y2, y3, t0, t1, t2, t3, temp;
-
-   assign {a0, a1, a2, a3} = a;
-   assign temp = a0 ^ a1 ^ a2 ^ a3;
-
-   galoismultforward8 gm0 (a0^a1, t0);
-   galoismultforward8 gm1 (a1^a2, t1);
-   galoismultforward8 gm2 (a2^a3, t2);
-   galoismultforward8 gm3 (a3^a0, t3);
-
-   assign y0 = a0 ^ temp ^ t3;
-   assign y1 = a1 ^ temp ^ t0;
-   assign y2 = a2 ^ temp ^ t1;
-   assign y3 = a3 ^ temp ^ t2;
-   
-   assign y = {y0, y1, y2, y3};
-endmodule
diff --git a/src/ieu/aes/aesmixcolumns8.sv b/src/ieu/aes/aesmixcolumns8.sv
deleted file mode 100644
index 256f728d0..000000000
--- a/src/ieu/aes/aesmixcolumns8.sv
+++ /dev/null
@@ -1,39 +0,0 @@
-///////////////////////////////////////////
-// aesmixcolumns8.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
-// Created: 20 February 2024
-//
-// Purpose: Galois field operation to byte in an individual 32-bit word
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-module aesmixcolumns8(
-   input  logic [7:0]  a, 
-   output logic [31:0] y
-);
-
-   logic [7:0] xa, xapa;
-
-   galoismultforward8 gm(a, xa); // xa
-   assign xapa = a ^ xa;         // a ^ xa
-   assign y = {xapa, a, a, xa};
-endmodule
diff --git a/src/ieu/aes/aessbox32.sv b/src/ieu/aes/aessbox32.sv
deleted file mode 100644
index fe00e7028..000000000
--- a/src/ieu/aes/aessbox32.sv
+++ /dev/null
@@ -1,38 +0,0 @@
-///////////////////////////////////////////
-// aessbox32.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aessbox32(
-   input  logic [31:0] a, 
-   output logic [31:0] y
-);   
-   
-   // substitutions boxes for each byte of the 32-bit word
-   aessbox8 sbox0(a[7:0],   y[7:0]);
-   aessbox8 sbox1(a[15:8],  y[15:8]);
-   aessbox8 sbox2(a[23:16], y[23:16]);	
-   aessbox8 sbox3(a[31:24], y[31:24]);   
-endmodule
diff --git a/src/ieu/aes/aessbox8.sv b/src/ieu/aes/aessbox8.sv
deleted file mode 100644
index 5cf41289d..000000000
--- a/src/ieu/aes/aessbox8.sv
+++ /dev/null
@@ -1,293 +0,0 @@
-///////////////////////////////////////////
-// aessbox8.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: Rinjdael forward S-BOX in the form of a LUT
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aessbox8(
-	input  logic [7:0] a, 
-    output logic [7:0] y
-);
-
-   // case statement to lookup the value in the rijndael table
-   always_comb 
-	case(a)
-	  8'h00 : y = 8'h63;
-	  8'h01 : y = 8'h7C;
-	  8'h02 : y = 8'h77;
-	  8'h03 : y = 8'h7B;
-	  8'h04 : y = 8'hF2;
-	  8'h05 : y = 8'h6B;
-	  8'h06 : y = 8'h6F;
-	  8'h07 : y = 8'hC5;
-	  8'h08 : y = 8'h30;
-	  8'h09 : y = 8'h01;
-	  8'h0A : y = 8'h67;
-	  8'h0B : y = 8'h2B;
-	  8'h0C : y = 8'hFE;
-	  8'h0D : y = 8'hD7;
-	  8'h0E : y = 8'hAB;
-	  8'h0F : y = 8'h76;
-	  8'h10 : y = 8'hCA;
-	  8'h11 : y = 8'h82;
-	  8'h12 : y = 8'hC9;
-	  8'h13 : y = 8'h7D;
-	  8'h14 : y = 8'hFA;
-	  8'h15 : y = 8'h59;
-	  8'h16 : y = 8'h47;
-	  8'h17 : y = 8'hF0;
-	  8'h18 : y = 8'hAD;
-	  8'h19 : y = 8'hD4;
-	  8'h1A : y = 8'hA2;
-	  8'h1B : y = 8'hAF;
-	  8'h1C : y = 8'h9C;
-	  8'h1D : y = 8'hA4;
-	  8'h1E : y = 8'h72;
-	  8'h1F : y = 8'hC0;
-	  8'h20 : y = 8'hB7;
-	  8'h21 : y = 8'hFD;
-	  8'h22 : y = 8'h93;
-	  8'h23 : y = 8'h26;
-	  8'h24 : y = 8'h36;
-	  8'h25 : y = 8'h3F;
-	  8'h26 : y = 8'hF7;
-	  8'h27 : y = 8'hCC;
-	  8'h28 : y = 8'h34;
-	  8'h29 : y = 8'hA5;
-	  8'h2A : y = 8'hE5;
-	  8'h2B : y = 8'hF1;
-	  8'h2C : y = 8'h71;
-	  8'h2D : y = 8'hD8;
-	  8'h2E : y = 8'h31;
-	  8'h2F : y = 8'h15;
-	  8'h30 : y = 8'h04;
-	  8'h31 : y = 8'hC7;
-	  8'h32 : y = 8'h23;
-	  8'h33 : y = 8'hC3;
-	  8'h34 : y = 8'h18;
-	  8'h35 : y = 8'h96;
-	  8'h36 : y = 8'h05;
-	  8'h37 : y = 8'h9A;
-	  8'h38 : y = 8'h07;
-	  8'h39 : y = 8'h12;
-	  8'h3A : y = 8'h80;
-	  8'h3B : y = 8'hE2;
-	  8'h3C : y = 8'hEB;
-	  8'h3D : y = 8'h27;
-	  8'h3E : y = 8'hB2;
-	  8'h3F : y = 8'h75;
-	  8'h40 : y = 8'h09;
-	  8'h41 : y = 8'h83;
-	  8'h42 : y = 8'h2C;
-	  8'h43 : y = 8'h1A;
-	  8'h44 : y = 8'h1B;
-	  8'h45 : y = 8'h6E;
-	  8'h46 : y = 8'h5A;
-	  8'h47 : y = 8'hA0;
-	  8'h48 : y = 8'h52;
-	  8'h49 : y = 8'h3B;
-	  8'h4A : y = 8'hD6;
-	  8'h4B : y = 8'hB3;
-	  8'h4C : y = 8'h29;
-	  8'h4D : y = 8'hE3;
-	  8'h4E : y = 8'h2F;
-	  8'h4F : y = 8'h84;
-	  8'h50 : y = 8'h53;
-	  8'h51 : y = 8'hD1;
-	  8'h52 : y = 8'h00;
-	  8'h53 : y = 8'hED;
-	  8'h54 : y = 8'h20;
-	  8'h55 : y = 8'hFC;
-	  8'h56 : y = 8'hB1;
-	  8'h57 : y = 8'h5B;
-	  8'h58 : y = 8'h6A;
-	  8'h59 : y = 8'hCB;
-	  8'h5A : y = 8'hBE;
-	  8'h5B : y = 8'h39;
-	  8'h5C : y = 8'h4A;
-	  8'h5D : y = 8'h4C;
-	  8'h5E : y = 8'h58;
-	  8'h5F : y = 8'hCF;
-	  8'h60 : y = 8'hD0;
-	  8'h61 : y = 8'hEF;
-	  8'h62 : y = 8'hAA;
-	  8'h63 : y = 8'hFB;
-	  8'h64 : y = 8'h43;
-	  8'h65 : y = 8'h4D;
-	  8'h66 : y = 8'h33;
-	  8'h67 : y = 8'h85;
-	  8'h68 : y = 8'h45;
-	  8'h69 : y = 8'hF9;
-	  8'h6A : y = 8'h02;
-	  8'h6B : y = 8'h7F;
-	  8'h6C : y = 8'h50;
-	  8'h6D : y = 8'h3C;
-	  8'h6E : y = 8'h9F;
-	  8'h6F : y = 8'hA8;
-	  8'h70 : y = 8'h51;
-	  8'h71 : y = 8'hA3;
-	  8'h72 : y = 8'h40;
-	  8'h73 : y = 8'h8F;
-	  8'h74 : y = 8'h92;
-	  8'h75 : y = 8'h9D;
-	  8'h76 : y = 8'h38;
-	  8'h77 : y = 8'hF5;
-	  8'h78 : y = 8'hBC;
-	  8'h79 : y = 8'hB6;
-	  8'h7A : y = 8'hDA;
-	  8'h7B : y = 8'h21;
-	  8'h7C : y = 8'h10;
-	  8'h7D : y = 8'hFF;
-	  8'h7E : y = 8'hF3;
-	  8'h7F : y = 8'hD2;
-	  8'h80 : y = 8'hCD;
-	  8'h81 : y = 8'h0C;
-	  8'h82 : y = 8'h13;
-	  8'h83 : y = 8'hEC;
-	  8'h84 : y = 8'h5F;
-	  8'h85 : y = 8'h97;
-	  8'h86 : y = 8'h44;
-	  8'h87 : y = 8'h17;
-	  8'h88 : y = 8'hC4;
-	  8'h89 : y = 8'hA7;
-	  8'h8A : y = 8'h7E;
-	  8'h8B : y = 8'h3D;
-	  8'h8C : y = 8'h64;
-	  8'h8D : y = 8'h5D;
-	  8'h8E : y = 8'h19;
-	  8'h8F : y = 8'h73;
-	  8'h90 : y = 8'h60;
-	  8'h91 : y = 8'h81;
-	  8'h92 : y = 8'h4F;
-	  8'h93 : y = 8'hDC;
-	  8'h94 : y = 8'h22;
-	  8'h95 : y = 8'h2A;
-	  8'h96 : y = 8'h90;
-	  8'h97 : y = 8'h88;
-	  8'h98 : y = 8'h46;
-	  8'h99 : y = 8'hEE;
-	  8'h9A : y = 8'hB8;
-	  8'h9B : y = 8'h14;
-	  8'h9C : y = 8'hDE;
-	  8'h9D : y = 8'h5E;
-	  8'h9E : y = 8'h0B;
-	  8'h9F : y = 8'hDB;
-	  8'hA0 : y = 8'hE0;
-	  8'hA1 : y = 8'h32;
-	  8'hA2 : y = 8'h3A;
-	  8'hA3 : y = 8'h0A;
-	  8'hA4 : y = 8'h49;
-	  8'hA5 : y = 8'h06;
-	  8'hA6 : y = 8'h24;
-	  8'hA7 : y = 8'h5C;
-	  8'hA8 : y = 8'hC2;
-	  8'hA9 : y = 8'hD3;
-	  8'hAA : y = 8'hAC;
-	  8'hAB : y = 8'h62;
-	  8'hAC : y = 8'h91;
-	  8'hAD : y = 8'h95;
-	  8'hAE : y = 8'hE4;
-	  8'hAF : y = 8'h79;
-	  8'hB0 : y = 8'hE7;
-	  8'hB1 : y = 8'hC8;
-	  8'hB2 : y = 8'h37;
-	  8'hB3 : y = 8'h6D;
-	  8'hB4 : y = 8'h8D;
-	  8'hB5 : y = 8'hD5;
-	  8'hB6 : y = 8'h4E;
-	  8'hB7 : y = 8'hA9;
-	  8'hB8 : y = 8'h6C;
-	  8'hB9 : y = 8'h56;
-	  8'hBA : y = 8'hF4;
-	  8'hBB : y = 8'hEA;
-	  8'hBC : y = 8'h65;
-	  8'hBD : y = 8'h7A;
-	  8'hBE : y = 8'hAE;
-	  8'hBF : y = 8'h08;
-	  8'hC0 : y = 8'hBA;
-	  8'hC1 : y = 8'h78;
-	  8'hC2 : y = 8'h25;
-	  8'hC3 : y = 8'h2E;
-	  8'hC4 : y = 8'h1C;
-	  8'hC5 : y = 8'hA6;
-	  8'hC6 : y = 8'hB4;
-	  8'hC7 : y = 8'hC6;
-	  8'hC8 : y = 8'hE8;
-	  8'hC9 : y = 8'hDD;
-	  8'hCA : y = 8'h74;
-	  8'hCB : y = 8'h1F;
-	  8'hCC : y = 8'h4B;
-	  8'hCD : y = 8'hBD;
-	  8'hCE : y = 8'h8B;
-	  8'hCF : y = 8'h8A;
-	  8'hD0 : y = 8'h70;
-	  8'hD1 : y = 8'h3E;
-	  8'hD2 : y = 8'hB5;
-	  8'hD3 : y = 8'h66;
-	  8'hD4 : y = 8'h48;
-	  8'hD5 : y = 8'h03;
-	  8'hD6 : y = 8'hF6;
-	  8'hD7 : y = 8'h0E;
-	  8'hD8 : y = 8'h61;
-	  8'hD9 : y = 8'h35;
-	  8'hDA : y = 8'h57;
-	  8'hDB : y = 8'hB9;
-	  8'hDC : y = 8'h86;
-	  8'hDD : y = 8'hC1;
-	  8'hDE : y = 8'h1D;
-	  8'hDF : y = 8'h9E;
-	  8'hE0 : y = 8'hE1;
-	  8'hE1 : y = 8'hF8;
-	  8'hE2 : y = 8'h98;
-	  8'hE3 : y = 8'h11;
-	  8'hE4 : y = 8'h69;
-	  8'hE5 : y = 8'hD9;
-	  8'hE6 : y = 8'h8E;
-	  8'hE7 : y = 8'h94;
-	  8'hE8 : y = 8'h9B;
-	  8'hE9 : y = 8'h1E;
-	  8'hEA : y = 8'h87;
-	  8'hEB : y = 8'hE9;
-	  8'hEC : y = 8'hCE;
-	  8'hED : y = 8'h55;
-	  8'hEE : y = 8'h28;
-	  8'hEF : y = 8'hDF;
-	  8'hF0 : y = 8'h8C;
-	  8'hF1 : y = 8'hA1;
-	  8'hF2 : y = 8'h89;
-	  8'hF3 : y = 8'h0D;
-	  8'hF4 : y = 8'hBF;
-	  8'hF5 : y = 8'hE6;
-	  8'hF6 : y = 8'h42;
-	  8'hF7 : y = 8'h68;
-	  8'hF8 : y = 8'h41;
-	  8'hF9 : y = 8'h99;
-	  8'hFA : y = 8'h2D;
-	  8'hFB : y = 8'h0F;
-	  8'hFC : y = 8'hB0;
-	  8'hFD : y = 8'h54;
-	  8'hFE : y = 8'hBB;
-	  8'hFF : y = 8'h16;
-	endcase
-endmodule
diff --git a/src/ieu/aes/aesshiftrows64.sv b/src/ieu/aes/aesshiftrows64.sv
deleted file mode 100644
index 11577bf3a..000000000
--- a/src/ieu/aes/aesshiftrows64.sv
+++ /dev/null
@@ -1,37 +0,0 @@
-///////////////////////////////////////////
-// aesshiftrows64.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aesshiftrow for taking in first Data line
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesshiftrows64(
-   /* verilator lint_off UNUSEDSIGNAL */
-   input  logic [127:0] a, 
-   /* verilator lint_on UNUSEDSIGNAL */
-   output logic [63:0] y
-);
-		    
-   assign y = {a[31:24],   a[119:112], a[79:72],   a[39:32],
-               a[127:120], a[87:80],   a[47:40],   a[7:0]};   
-endmodule
diff --git a/src/ieu/aes/galoismultforward8.sv b/src/ieu/aes/galoismultforward8.sv
deleted file mode 100644
index ecb2d1122..000000000
--- a/src/ieu/aes/galoismultforward8.sv
+++ /dev/null
@@ -1,37 +0,0 @@
-///////////////////////////////////////////
-// galoismultforward.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
-// Created: 20 February 2024
-//
-// Purpose: Galois field operations for mix columns operation
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module galoismultforward8(
-   input  logic [7:0] a, 
-   output logic [7:0] y
-);
-
-   logic [7:0] leftshift;
-
-   assign leftshift = {a[6:0], 1'b0};
-   assign y = a[7] ? (leftshift ^ 8'b00011011) : leftshift;
-endmodule
diff --git a/src/ieu/aes/galoismultinverse8.sv b/src/ieu/aes/galoismultinverse8.sv
deleted file mode 100644
index 06a12911f..000000000
--- a/src/ieu/aes/galoismultinverse8.sv
+++ /dev/null
@@ -1,38 +0,0 @@
-///////////////////////////////////////////
-// galoismultinverse.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: Galois field operations for mix columns operation
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module galoismultinverse8(
-   input  logic [10:0] a, 
-   output logic [7:0]  y
-);
-
-   logic [7:0] temp0, temp1;
-
-   assign temp0 = a[8]  ? (a[7:0] ^ 8'b00011011) : a[7:0];
-   assign temp1 = a[9]  ? (temp0  ^ 8'b00110110) : temp0;
-   assign y     = a[10] ? (temp1  ^ 8'b01101100) : temp1;
-endmodule
diff --git a/src/ieu/aes/rconlut32.sv b/src/ieu/aes/rconlut32.sv
deleted file mode 100644
index e1f80964b..000000000
--- a/src/ieu/aes/rconlut32.sv
+++ /dev/null
@@ -1,52 +0,0 @@
-///////////////////////////////////////////
-// rconlut32.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: rcon lookup for aes64ks1i instruction
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module rconlut32(
-	input  logic [3:0]  rd,
-	output logic [31:0] rcon
-);
-
-	logic [7:0] rcon8;
-	
-   	always_comb
-		case(rd)
-			4'h0 : rcon8 = 8'h01;
-			4'h1 : rcon8 = 8'h02;
-			4'h2 : rcon8 = 8'h04;
-			4'h3 : rcon8 = 8'h08;
-			4'h4 : rcon8 = 8'h10;
-			4'h5 : rcon8 = 8'h20;
-			4'h6 : rcon8 = 8'h40;
-			4'h7 : rcon8 = 8'h80;
-			4'h8 : rcon8 = 8'h1b;
-			4'h9 : rcon8 = 8'h36;
-			4'hA : rcon8 = 8'h00;
-			default : rcon8 = 8'h00;
-		endcase	
-
-	assign rcon = {24'b0, rcon8};
-endmodule
diff --git a/src/ieu/aes/rotate.sv b/src/ieu/aes/rotate.sv
deleted file mode 100644
index 7f44f95f4..000000000
--- a/src/ieu/aes/rotate.sv
+++ /dev/null
@@ -1,35 +0,0 @@
-///////////////////////////////////////////
-// rotate.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: rotate a by shamt
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module rotate #(parameter WIDTH=32) (
-   input  logic [WIDTH-1:0]        a,
-   input  logic [$clog2(WIDTH)-1:0] shamt,
-   output logic [WIDTH-1:0]        y
-);                
-
-   assign y = (a << shamt) | (a >> (WIDTH-shamt)); 
-endmodule
diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
deleted file mode 100644
index b63123126..000000000
--- a/src/ieu/alu.sv
+++ /dev/null
@@ -1,124 +0,0 @@
-///////////////////////////////////////////
-// alu.sv
-//
-// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu
-// Created: 9 January 2021
-// Modified: 3 March 2023
-//
-// Purpose: RISC-V Arithmetic/Logic Unit
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module alu import cvw::*; #(parameter cvw_t P) (
-  input  logic [P.XLEN-1:0] A, B,        // Operands
-  input  logic              W64, UW64,   // W64/.uw-type instruction
-  input  logic              SubArith,    // Subtraction or arithmetic shift
-  input  logic [2:0]        ALUSelect,   // ALU mux select signal
-  input  logic [3:0]        BSelect,     // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
-  input  logic [3:0]        ZBBSelect,   // ZBB mux select signal
-  input  logic [2:0]        Funct3,      // For BMU decoding
-  input  logic [6:0]        Funct7,      // For ZKNE and ZKND computation
-  input  logic [4:0]        Rs2E,        // For ZKNE and ZKND computation
-  input  logic [2:0]        BALUControl, // ALU Control signals for B instructions in Execute Stage
-  input  logic              BMUActive,   // Bit manipulation instruction being executed
-  input  logic [1:0]        CZero,       // {czero.nez, czero.eqz} instructions active
-  output logic [P.XLEN-1:0] ALUResult,   // ALU result
-  output logic [P.XLEN-1:0] Sum);        // Sum of operands
-
-  // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
-  // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
-  logic [P.XLEN-1:0] CondMaskInvB, Shift, FullResult, PreALUResult;               // Intermediate Signals 
-  logic [P.XLEN-1:0] CondMaskB;                                                   // Result of B mask select mux
-  logic [P.XLEN-1:0] CondShiftA;                                                  // Result of A shifted select mux
-  logic [P.XLEN-1:0] ZeroCondMaskInvB;                                            // B input to AND gate, accounting for czero.* instructions
-  logic [P.XLEN-1:0] AndResult;                                                   // AND result
-  logic              Carry, Neg;                                                  // Flags: carry out, negative
-  logic              LT, LTU;                                                     // Less than, Less than unsigned
-  logic              Asign, Bsign;                                                // Sign bits of A, B
-
-  // Addition
-  // CondMaskB is B for add/sub, or a masked version of B for certain bit manipulation instructions
-  // CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
-  assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
-  assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(P.XLEN-1){1'b0}}, SubArith};
-
-  // Zicond block conditionally zeros B
-  if (P.ZICOND_SUPPORTED) begin: zicond
-    logic  BZero;
-    
-    assign BZero = (B == 0); // check if rs2 = 0
-    // Create a signal that is 0 when czero.* instruction should clear result
-    // If B = 0 for czero.eqz or if B != 0 for czero.nez
-    always_comb 
-     case (CZero)
-        2'b01:   ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
-        2'b10:   ZeroCondMaskInvB = {P.XLEN{BZero}};  // czero.nez: kill if B != 0
-        default: ZeroCondMaskInvB = CondMaskInvB;     // otherwise normal behavior
-      endcase
-  end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
-
-  // Shifts (configurable for rotation)
-  shifter #(P) sh(.A(CondShiftA), .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
-
-  // Condition code flags are based on subtraction output Sum = A-B.
-  // Overflow occurs when the numbers being subtracted have the opposite sign 
-  // and the result has the opposite sign of A.
-  // LT is simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
-  assign Neg  = Sum[P.XLEN-1];
-  assign Asign = A[P.XLEN-1];
-  assign Bsign = B[P.XLEN-1];
-  assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; 
-  assign LTU = ~Carry;
-  assign AndResult = A & ZeroCondMaskInvB;
- 
-  // Select appropriate ALU Result
-  always_comb 
-    case (ALUSelect)                                
-      3'b000: FullResult = Sum;                            // add or sub (including address generation)
-      3'b001: FullResult = Shift;                          // sll, sra, or srl
-      3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT};       // slt
-      3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU};      // sltu
-      3'b100: FullResult = A ^ CondMaskInvB;               // xor, xnor, binv
-      3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
-      3'b110: FullResult = A | CondMaskInvB;               // or, orn, bset
-      3'b111: FullResult = AndResult;                      // and, bclr, czero.*
-    endcase
-
-  // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
-  if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
-  else              assign PreALUResult = FullResult;
-
-  // Bit manipulation muxing
-  if (P.ZBC_SUPPORTED  | P.ZBS_SUPPORTED  | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED |
-      P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | 
-      P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
-    bitmanipalu #(P) balu(
-      .A, .B, .W64, .UW64, .BSelect, .ZBBSelect, .BMUActive,
-      .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
-      .CondMaskB, .CondShiftA, .ALUResult);
-  end else begin
-    assign ALUResult = PreALUResult;
-    assign CondMaskB = B;
-    assign CondShiftA = A;
-  end
-
-endmodule
diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv
deleted file mode 100644
index 9bb0905ad..000000000
--- a/src/ieu/bmu/bitmanipalu.sv
+++ /dev/null
@@ -1,145 +0,0 @@
-///////////////////////////////////////////
-// bitmanipalu.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
-// Created: 23 March 2023
-// Modified: 9 March 2024
-//
-// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module bitmanipalu import cvw::*; #(parameter cvw_t P) (
-  input logic [P.XLEN-1:0]  A, B,                    // Operands
-  input logic 		        W64, UW64,                     // W64/.uw-type instruction
-  input logic [3:0] 	    BSelect,                 // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
-  input logic [3:0] 	    ZBBSelect,               // ZBB mux select signal
-  input logic [2:0] 	    Funct3,                  // Funct3 field of opcode indicates operation to perform
-  input logic [6:0] 	    Funct7,                  // Funct7 field for ZKND and ZKNE operations
-  input logic [4:0] 	    Rs2E,                    // Register source2 for RNUM of ZKNE/ZKND
-  input logic 		        LT,                      // less than flag
-  input logic 		        LTU,                     // less than unsigned flag
-  input logic [2:0] 	    BALUControl,             // ALU Control signals for B instructions in Execute Stage
-  input logic 		        BMUActive,               // Bit manipulation instruction being executed
-  input logic [P.XLEN-1:0]  PreALUResult,            // PreALUResult signals
-  input  logic [P.XLEN-1:0] FullResult,              // FullResult signals
-  output logic [P.XLEN-1:0] CondMaskB,               // B is conditionally masked for ZBS instructions
-  output logic [P.XLEN-1:0] CondShiftA,              // A is conditionally shifted for ShAdd instructions
-  output logic [P.XLEN-1:0] ALUResult);              // Result
-
-  logic [P.XLEN-1:0]        ZBBResult;               // ZBB Result
-  logic [P.XLEN-1:0]        ZBCResult;               // ZBC Result   
-  logic [P.XLEN-1:0] 	      ZBKBResult;              // ZBKB Result
-  logic [P.XLEN-1:0]        ZBKXResult;              // ZBKX Result      
-  logic [P.XLEN-1:0]        ZKNHResult;              // ZKNH Result
-  logic [P.XLEN-1:0]        ZKNDEResult;             // ZKNE or ZKND Result   
-  logic [P.XLEN-1:0]        MaskB;                   // BitMask of B
-  logic [P.XLEN-1:0]        RevA;                    // Bit-reversed A
-  logic                     Mask;                    // Indicates if it is ZBS instruction
-  logic                     PreShift;                // Inidicates if it is sh1add, sh2add, sh3add instruction
-  logic [1:0]               PreShiftAmt;             // Amount to Pre-Shift A 
-  logic [P.XLEN-1:0]        CondZextA;               // A Conditional Extend Intermediary Signal
-  logic [P.XLEN-1:0]        ABMU, BBMU;              // Gated data inputs to reduce BMU activity
-
-  // gate data inputs to BMU to only operate when BMU is active
-  assign ABMU = A & {P.XLEN{BMUActive}};
-  assign BBMU = B & {P.XLEN{BMUActive}};
-
-  // Extract control signals from bitmanip ALUControl.
-  assign {Mask, PreShift} = BALUControl[1:0];
-
-  // Mask Generation Mux
-  if (P.ZBS_SUPPORTED) begin: zbsdec
-    decoder #($clog2(P.XLEN)) maskgen(BBMU[$clog2(P.XLEN)-1:0], MaskB);
-    mux2 #(P.XLEN) maskmux(B, MaskB, Mask, CondMaskB);
-  end else assign CondMaskB = B;
- 
-  // 0-3 bit Pre-Shift Mux
-  if (P.ZBA_SUPPORTED) begin: zbapreshift
-    if (P.XLEN == 64) begin
-      mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, UW64, CondZextA); 
-    end else assign CondZextA = A;
-    assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
-    assign CondShiftA = CondZextA << (PreShiftAmt);
-  end else begin
-    assign PreShiftAmt = 2'b0;
-    assign CondShiftA = A;
-  end
-
-  // Bit reverse needed for some ZBB, ZBC instructions
-  if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
-    bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
-  end
-
-  // ZBC and ZBKCUnit
-  if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
-    zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3(Funct3[1:0]), .ZBCResult);
-  end else assign ZBCResult = '0;
-
-  // ZBB Unit
-  if (P.ZBB_SUPPORTED) begin: zbb
-    zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult);
-  end else if (P.ZBKB_SUPPORTED) begin: zbkbonly // only needs rev8 portion
-    genvar i;
-    for (i=0;i<P.XLEN;i+=8) begin:byteloop
-      assign ZBBResult[P.XLEN-i-1:P.XLEN-i-8] = ABMU[i+7:i]; // Rev8
-    end
-  end else assign ZBBResult = '0;
-
-  // ZBKB Unit
-  if (P.ZBKB_SUPPORTED) begin: zbkb
-    zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU[P.XLEN/2-1:0]), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
-  end else assign ZBKBResult = '0;
-
-  // ZBKX Unit
-  if (P.ZBKX_SUPPORTED) begin: zbkx
-    zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[0]), .ZBKXResult);
-  end else assign ZBKXResult = '0;
-
-  // ZKND and ZKNE AES decryption and encryption
-  if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin: zknde
-    if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .bs(Funct7[6:5]), .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
-    else              zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU),                   .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
-  end else assign ZKNDEResult = '0;
- 
-  // ZKNH Unit
-  if (P.ZKNH_SUPPORTED) begin: zknh
-    if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
-    else              zknh64 ZKNH64(.A(ABMU),           .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
-  end else assign ZKNHResult = '0;
-
-  // Result Select Mux
-  always_comb
-    case (BSelect)
-      // 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX
-      // 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH...
-      4'b0000: ALUResult = PreALUResult; 
-      4'b0001: ALUResult = FullResult;  // NOTE: don't use ALUResult since ZBA/ZBS doesnt sext the MSB of RH word
-      4'b0010: ALUResult = ZBBResult; 
-      4'b0011: ALUResult = ZBCResult;
-      4'b0100: ALUResult = ZBKBResult;
-      4'b0110: ALUResult = ZBKXResult;
-      4'b0111: ALUResult = ZKNDEResult; 
-      4'b1000: ALUResult = ZKNHResult;
-      default: ALUResult = PreALUResult;
-    endcase
-endmodule
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
deleted file mode 100644
index fe781e78b..000000000
--- a/src/ieu/bmu/bmuctrl.sv
+++ /dev/null
@@ -1,293 +0,0 @@
-///////////////////////////////////////////
-// bmuctrl.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
-// Created: 16 February 2023
-// Modified: 6 March 2023, 9 March 2024
-//
-// Purpose: Top level bit manipulation instruction decoder
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module bmuctrl import cvw::*;  #(parameter cvw_t P) (
-  input  logic        clk, reset,
-  // Decode stage control signals
-  input  logic [31:0] InstrD,                  // Instruction in Decode stage
-  input  logic        ALUOpD,                  // Regular ALU Operation
-  output logic        BRegWriteD,              // Indicates if it is a R type B instruction in Decode Stage
-  output logic        BALUSrcBD,               // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
-  output logic        BW64D,                   // Indiciates if it is a W type B instruction in Decode Stage
-  output logic        BUW64D,                  // Indiciates if it is a .uw type B instruction in Decode Stage
-  output logic        BSubArithD,              // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage
-  output logic        IllegalBitmanipInstrD,   // Indicates if it is unrecognized B instruction in Decode Stage
-  // Execute stage control signals             
-  input  logic        StallE, FlushE,          // Stall, flush Execute stage
-  output logic [2:0]  ALUSelectD,              // ALU select
-  output logic [3:0]  BSelectE,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
-  output logic [3:0]  ZBBSelectE,              // ZBB mux select signal
-  output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
-  output logic        BMUActiveE               // Bit manipulation instruction being executed
-);
-
-  logic [6:0] OpD;                             // Opcode in Decode stage
-  logic [2:0] Funct3D;                         // Funct3 field in Decode stage
-  logic [6:0] Funct7D;                         // Funct7 field in Decode stage
-  logic [4:0] Rs2D;                            // Rs2 source register in Decode stage
-  logic       RotateD;                         // Indicates if rotate instruction in Decode Stage
-  logic       MaskD;                           // Indicates if zbs instruction in Decode Stage
-  logic       PreShiftD;                       // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
-  logic [2:0] BALUControlD;                    // ALU Control signals for B instructions
-  logic [2:0] BALUSelectD;                     // ALU Mux select signal in Decode Stage for BMU operations
-  logic       BALUOpD;                         // Indicates if it is an ALU B instruction in Decode Stage
-  logic [3:0] BSelectD;                        // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
-  logic [3:0] ZBBSelectD;                      // ZBB mux select signal in Decode stage
-
-  `define BMUCTRLW 21
-
-  logic [`BMUCTRLW-1:0] BMUControlsD;          // Main B Instructions Decoder control signals
-
-  // Extract fields
-  assign OpD = InstrD[6:0];
-  assign Funct3D = InstrD[14:12];
-  assign Funct7D = InstrD[31:25];
-  assign Rs2D = InstrD[24:20];
-
-  // Main Instruction Decoder
-  always_comb begin
-    // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BUW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
-    BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1;  // default: Illegal bmu instruction;
-    if (P.ZBA_SUPPORTED) begin
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0;  // sh1add
-        17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0;  // sh2add
-        17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0;  // sh3add
-      endcase
-      if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0;  // sh1add.uw
-          17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0;  // sh2add.uw
-          17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0;  // sh3add.uw
-          17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_0_0;  // add.uw
-          17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_0_1_1_0_0_0_0_0;  // slli.uw
-        endcase
-    end
-
-    if (P.ZBB_SUPPORTED) begin
-      casez({OpD, Funct7D, Funct3D})
-        17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
-                                  BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_0_1_0_0_0_0_0;  // sign extend instruction
-                                else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
-                                  BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_0_1_0_0_0_0_0;  // count instruction
-        17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
-                                 BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_0_1_0_0_0_0_0;  // orc.b
-        17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_0_1_1_0_0_0_0;  // max
-        17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_0_1_1_0_0_0_0;  // maxu
-        17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_0_1_1_0_0_0_0;  // min
-        17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_0_1_1_0_0_0_0;  // minu
-      endcase
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_0_1_0_0_0_0_0;  // zexth (rv32)                       
-        endcase
-      else if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_0_1_0_0_0_0_0;  // zexth (rv64)
-          17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
-                                   BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0_0;  // count word instruction (clzw/ctzw/cpopw)
-        endcase
-    end
-
-    if (P.ZBC_SUPPORTED)
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0;  // clmulr
-        17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0;  // clmul/clmulh
-      endcase
-    if (P.ZBKC_SUPPORTED) begin   
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0000101_0?1: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0;  // clmul/clmulh
-      endcase
-    end
-
-    if (P.ZBS_SUPPORTED) begin // ZBS
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_0_1_1_0_1_0_0;  // bclr
-        17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_0_1_0_0_1_0_0;  // bext
-        17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_0_1_0_0_1_0_0;  // binv
-        17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_0_1_0_0_1_0_0;  // bset
-      endcase
-      if (P.XLEN==32) // ZBS 64-bit
-        casez({OpD, Funct7D, Funct3D})
-          17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_0_1_1_0_1_0_0;  // bclri
-          17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_0_1_0_0_1_0_0;  // bexti
-          17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_0_1_0_0_1_0_0;  // binvi
-          17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_0_1_0_0_1_0_0;  // bseti
-        endcase
-      else if (P.XLEN==64) // ZBS 64-bit
-        casez({OpD, Funct7D, Funct3D})
-          17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_0_1_1_0_1_0_0;  // bclri (rv64)
-          17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_0_1_0_0_1_0_0;  // bexti (rv64)
-          17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_0_1_0_0_1_0_0;  // binvi (rv64)
-          17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_0_1_0_0_1_0_0;  // bseti (rv64)
-        endcase
-    end
-    if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
-      casez({OpD, Funct7D, Funct3D})
-        // variable shifts don't encode shift amount in funct7
-        17'b0110011_0000000_001: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0;  // sll
-        17'b0110011_0?00000_101: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0;  // sra, srl
-        // Immediate Shifts by more than 32 (Funct7[0]) are only supported in RV64
-        17'b0010011_000000?_001: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0;  // slli
-        17'b0010011_0?0000?_101: if (P.XLEN == 64 | !Funct7D[0]) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0;  // srai, srli
-        // w-type shifts only supported in RV64 and must have Funct7[0] = 0 because the shift amount is < 32
-        17'b0111011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0;  // sllw
-        17'b0111011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0;  // sraw, srlw
-        17'b0011011_0000000_001: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0;  // slliw
-        17'b0011011_0?00000_101: if (P.XLEN == 64) BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0;  // sraiw, srliw
-      endcase
-    
-    if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip
-      casez({OpD,Funct7D, Funct3D})
-        17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_0_1_0_0_0_0_0;  // pack
-        17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_0_1_0_0_0_0_0;  // packh
-        17'b0010011_0110100_101: if (Rs2D == 5'b00111)
-                                 BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_0_1_0_0_0_0_0;  // brev8
-      endcase
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0010011_0000100_001: if (Rs2D == 5'b01111) 
-                                   BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_0_1_0_0_0_0_0;  //zip
-          17'b0010011_0000100_101: if (Rs2D == 5'b01111) 
-                                   BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_0_1_0_0_0_0_0;  //unzip
-        endcase
-      else if (P.XLEN==64)
-        casez({OpD,Funct7D, Funct3D})
-          17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_0_1_0_0_0_0_0; //packw
-        endcase
-    end
-    if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin  // ZBB and ZBKB shared instructions
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_0_1_0_1_0_0_0;  // rol
-        17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_0_1_0_1_0_0_0;  // ror
-        17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_0_1_1_0_0_0_0;  // andn
-        17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_0_1_1_0_0_0_0;  // orn
-        17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_0_1_1_0_0_0_0;  // xnor
-        17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
-                                 BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_0_1_0_0_0_0_0;  // rev8
-      endcase
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_0_1_0_1_0_0_0;  // rori (rv32)   
-        endcase
-      else if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_0_1_0_1_0_0_0;  // rolw
-          17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_0_1_0_1_0_0_0;  // rorw
-          17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_0_1_0_1_0_0_0;  // rori (rv64)
-          17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_0_1_0_1_0_0_0;  // roriw 
-        endcase
-    end
-
-    if (P.ZBKX_SUPPORTED) begin  //ZBKX
-      casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_0_1_0_0_0_0_0;  // xperm8
-        17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_0_1_0_0_0_0_0;  // xperm4
-      endcase
-    end
-
-    if (P.ZKND_SUPPORTED) begin //ZKND
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_0_1_0_0_0_0_0;  // aes32dsi - final round decrypt
-          17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_0_1_0_0_0_0_0;  // aes32dsmi - mid round decrypt
-        endcase
-      else if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_0_1_0_0_0_0_0;  // aes64ds - decrypt final round
-          17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_0_1_0_0_0_0_0;  // aes64dsm - decrypt mid round
-          17'b0010011_0011000_001: if (Rs2D == 5'b00000)
-                                   BMUControlsD = `BMUCTRLW'b000_0111_1000_1_1_0_0_1_0_0_0_0_0;  // aes64im - decrypt keyschdule mixcolumns
-        endcase
-    end
-
-    if (P.ZKNE_SUPPORTED) begin //ZKNE
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_0_1_0_0_0_0_0;  // aes32esi - final round encrypt
-          17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_0_1_0_0_0_0_0;  // aes32esmi - mid round encrypt
-        endcase
-      else if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_0_1_0_0_0_0_0;  // aes64es - encrypt final round
-          17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_0_1_0_0_0_0_0;  // aes64esm - encrypt mid round
-        endcase
-    end  
-    
-    if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions
-      casez({OpD, Funct7D, Funct3D})
-        17'b0010011_0011000_001: if (Rs2D[4] == 1'b1 & $unsigned(Rs2D[3:0]) <= 10)
-                                   BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_0_1_0_0_0_0_0;  // aes64ks1i - key schedule istr1
-          17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_0_1_0_0_0_0_0;  // aes64ks2 - key schedule istr2
-      endcase
-    end
-
-    if (P.ZKNH_SUPPORTED) begin // ZKNH
-      casez({OpD, Funct7D, Funct3D})
-        17'b0010011_0001000_001: 
-          if      (Rs2D == 5'b00010)   BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_0_1_0_0_0_0_0;  // sha256sig0
-          else if (Rs2D == 5'b00011)   BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_0_1_0_0_0_0_0;  // sha256sig1
-          else if (Rs2D == 5'b00000)   BMUControlsD = `BMUCTRLW'b000_1000_0010_1_0_0_0_1_0_0_0_0_0;  // sha256sum0
-          else if (Rs2D == 5'b00001)   BMUControlsD = `BMUCTRLW'b000_1000_0011_1_0_0_0_1_0_0_0_0_0;  // sha256sum1
-      endcase
-
-      if (P.XLEN==32)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0110011_0101110_000:     BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_0_1_0_0_0_0_0;  // sha512sig0h
-          17'b0110011_0101010_000:     BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_0_1_0_0_0_0_0;  // sha512sig0l
-          17'b0110011_0101111_000:     BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_0_1_0_0_0_0_0;  // sha512sig1h
-          17'b0110011_0101011_000:     BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_0_1_0_0_0_0_0;  // sha512sig1l
-          17'b0110011_0101000_000:     BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_0_1_0_0_0_0_0;  // sha512sum0r
-          17'b0110011_0101001_000:     BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_0_1_0_0_0_0_0;  // sha512sum1r
-        endcase
-
-      else if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
-          17'b0010011_0001000_001: 
-            if      (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_0_1_0_0_0_0_0;  // sha512sig0
-            else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_0_1_0_0_0_0_0;  // sha512sig1
-            else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_0_1_0_0_0_0_0;  // sha512sum0
-            else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_0_1_0_0_0_0_0;  // sha512sum1
-        endcase
-    end
-  end
-
-  // Unpack Control Signals
-  assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BUW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD;
-  
-  // Pack BALUControl Signals
-  assign BALUControlD = {RotateD, MaskD, PreShiftD};
-
-  // Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition
-  assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
-
-  // BMU Execute stage pipieline control register
-  flopenrc #(12) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BALUControlE, BMUActiveE});
-endmodule
diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv
deleted file mode 100644
index 33a0dc332..000000000
--- a/src/ieu/bmu/byteop.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-///////////////////////////////////////////
-// byteop.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
-// Created: 1 February 2023
-// Modified: 29 February 2024
-//
-// Purpose: RISCV bitmanip byte-wise operation unit
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module byteop #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] A,             // Operands
-  input  logic             ByteSelect,    // LSB of Immediate
-  output logic [WIDTH-1:0] ByteResult);   // rev8, orcb result
-
-  logic [WIDTH-1:0] OrcBResult, Rev8Result;
-  genvar i;
-
-  for (i=0;i<WIDTH;i+=8) begin:byteloop
-    assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
-    assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
-  end
-
-  mux2 #(WIDTH) byteresultmux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
-endmodule
diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv
deleted file mode 100644
index 2ea45606f..000000000
--- a/src/ieu/bmu/clmul.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-///////////////////////////////////////////
-// clmul.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
-// Created: 1 February 2023
-// Modified: 
-//
-// Purpose: Carry-Less multiplication unit
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module clmul #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] X, Y,             // Operands
-  output logic [WIDTH-1:0] ClmulResult);     // ZBS result
-
-  logic [(WIDTH*WIDTH)-1:0] S;               // intermediary signals for carry-less multiply
-  
-  integer i,j;
-
-  always_comb begin
-    for (i=0;i<WIDTH;i++) begin: outer
-      S[WIDTH*i] = X[0] & Y[i];
-      for (j=1;j<=i;j++) begin: inner
-        S[WIDTH*i+j] = (X[j] & Y[i-j]) ^ S[WIDTH*i+j-1];
-      end
-      ClmulResult[i] = S[WIDTH*i+j-1];
-    end
-  end
-endmodule
-
-
diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv
deleted file mode 100644
index f0bc5f72d..000000000
--- a/src/ieu/bmu/cnt.sv
+++ /dev/null
@@ -1,63 +0,0 @@
-///////////////////////////////////////////
-// cnt.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu>
-// Created: 4 February 2023
-// Modified: 
-//
-// Purpose: Count Instruction Submodule
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module cnt #(parameter WIDTH = 32) (
-  input  logic [WIDTH-1:0] A, RevA,    // Operands
-  input  logic [1:0]       B,          // Last 2 bits of immediate
-  input  logic             W64,        // Indicates word operation
-  output logic [WIDTH-1:0] CntResult   // count result
-);
-
-  //count instructions
-  logic [WIDTH-1:0] czResult;        // count zeros result
-  logic [WIDTH-1:0] cpopResult;      // population count result
-  logic [WIDTH-1:0] lzcA, popcntA;
-
-  //only in rv64
-  if (WIDTH==64) begin
-    //clz input select mux
-    mux4 #(WIDTH) lzcmux64(A, {A[31:0],{32{1'b1}}}, RevA, {RevA[63:32],{32{1'b1}}}, {B[0],W64}, lzcA);
-    //cpop select mux
-    mux2 #(WIDTH) popcntmux64(A, {{32{1'b0}}, A[31:0]}, W64, popcntA);
-  end
-  //rv32
-  else begin
-    assign popcntA = A;
-    mux2 #(WIDTH) lzcmux32(A, RevA, B[0], lzcA);
-  end
-
-  lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0]));
-  popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0]));
-  // zero extend these results to fit into width
-  assign czResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
-  assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
-
-  mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult);
-endmodule
diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv
deleted file mode 100644
index 435c8dff1..000000000
--- a/src/ieu/bmu/popcnt.sv
+++ /dev/null
@@ -1,44 +0,0 @@
-///////////////////////////////////////////
-// popccnt.sv
-// Written: Kevin Kim <kekim@hmc.edu>
-// Modified: 2/4/2023
-//
-// Purpose: Population Count
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module popcnt #(parameter WIDTH = 32) (
-  input  logic [WIDTH-1:0]        num,    // number to count total ones
-  output logic [$clog2(WIDTH):0]  PopCnt  // the total number of ones
-);
-
-  logic [$clog2(WIDTH):0] sum; 
-  
-  always_comb begin
-    sum = '0;
-    for (int i=0;i<WIDTH;i++) begin:loop
-      sum = (num[i]) ? sum + 1 : sum;
-    end
-  end
-
-  assign PopCnt = sum;
-endmodule
diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
deleted file mode 100644
index d5ca3bd4b..000000000
--- a/src/ieu/bmu/zbb.sv
+++ /dev/null
@@ -1,56 +0,0 @@
-///////////////////////////////////////////
-// zbb.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
-// Created: 2 February 2023
-// Modified: March 6 2023
-//
-// Purpose: RISC-V ZBB top level unit
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zbb #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] A, RevA, B,   // Operands
-  input  logic             W64,          // Indicates word operation
-  input  logic             LT,           // lt flag
-  input  logic             LTU,          // ltu flag
-  input  logic             BUnsigned,      // max/min (signed) flag
-  input  logic [2:0]       ZBBSelect,    // ZBB Result select signal
-  output logic [WIDTH-1:0] ZBBResult);   // ZBB result
-
-  logic lt;                              // lt given signed/unsigned
-  logic [WIDTH-1:0] CntResult;           // count result
-  logic [WIDTH-1:0] MinMaxResult;        // min, max result
-  logic [WIDTH-1:0] ByteResult;          // byte results
-  logic [WIDTH-1:0] ExtResult;           // sign/zero extend results
-
-  mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
-  cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
-  byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
-  ext #(WIDTH) ext(.A(A[15:0]), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
-
-  // ZBBSelect[2] differentiates between min(u) vs max(u) instruction
-  mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);
-
-  // ZBB Result select mux
-  mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
-endmodule
diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv
deleted file mode 100644
index a9a027ab6..000000000
--- a/src/ieu/bmu/zbc.sv
+++ /dev/null
@@ -1,58 +0,0 @@
-///////////////////////////////////////////
-// zbc.sv
-//
-// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
-// Created: 2 February 2023
-// Modified: 3 March 2023
-//
-// Purpose: RISC-V ZBC top-level unit
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zbc import cvw::*; #(parameter cvw_t P) (
-  input  logic [P.XLEN-1:0] A, RevA, B,       // Operands
-  input  logic [1:0]        Funct3,           // Indicates operation to perform
-  output logic [P.XLEN-1:0] ZBCResult);       // ZBC result
-
-  logic [P.XLEN-1:0] ClmulResult, RevClmulResult;
-  logic [P.XLEN-1:0] RevB;
-  logic [P.XLEN-1:0] X, Y;
-
-  bitreverse #(P.XLEN) brB(B, RevB);
-
-  // choose X = A for clmul, Rev(A) << 1 for clmulh, Rev(A) for clmulr
-  // unshifted Rev(A) source is only needed for clmulr in ZBC, not in ZBKC
-  if (P.ZBC_SUPPORTED)
-    mux3 #(P.XLEN) xmux({RevA[P.XLEN-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
-  else
-    mux2 #(P.XLEN) xmux(A, {RevA[P.XLEN-2:0], {1'b0}}, Funct3[1], X);
-
-  // choose X = B for clmul, Rev(B) for clmulH
-  mux2 #(P.XLEN) ymux(B, RevB, Funct3[1], Y);
-
-  // carry free multiplier
-  clmul #(P.XLEN) clm(.X, .Y, .ClmulResult);
-
-  // choose result = rev(X @ Y) for clmulh/clmulr
-  bitreverse #(P.XLEN) brClmulResult(ClmulResult, RevClmulResult);
-  mux2 #(P.XLEN) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
-endmodule
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
deleted file mode 100644
index eafbe4530..000000000
--- a/src/ieu/controller.sv
+++ /dev/null
@@ -1,481 +0,0 @@
-///////////////////////////////////////////
-// controller.sv
-//
-// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu
-// Created: 9 January 2021
-// Modified: 3 March 2023
-//
-// Purpose: Top level controller module
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module controller import cvw::*;  #(parameter cvw_t P) (
-  input  logic        clk, reset,
-  // Decode stage control signals
-  input  logic        StallD, FlushD,          // Stall, flush Decode stage
-  input  logic [31:0] InstrD,                  // Instruction in Decode stage
-  input  logic [1:0]  STATUS_FS,               // is FPU enabled?
-  input  logic [3:0]  ENVCFG_CBE,              // Cache block operation enables
-  output logic [2:0]  ImmSrcD,                 // Type of immediate extension
-  input  logic        IllegalIEUFPUInstrD,     // Illegal IEU and FPU instruction
-  output logic        IllegalBaseInstrD,       // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
-  output logic        JumpD,                   // Jump instruction
-  output logic        BranchD,                 // Branch instruction
-  output logic        StructuralStallD,        // Structural stalls detected by controller
-  output logic        LoadStallD,              // Structural stalls for load, sent to performance counters
-  output logic        StoreStallD,             // load after store hazard
-  output logic [4:0]  Rs1D, Rs2D, Rs2E,        // Register sources to read in Decode or Execute stage
-  // Execute stage control signals             
-  input  logic        StallE, FlushE,          // Stall, flush Execute stage
-  input  logic [1:0]  FlagsE,                  // Comparison flags ({eq, lt})
-  input  logic        FWriteIntE,              // Write integer register, coming from FPU controller
-  input  logic        FCvtIntE,                              // FPU convert float to int
-  output logic        PCSrcE,                  // Select signal to choose next PC (for datapath and Hazard unit)
-  output logic        ALUSrcAE, ALUSrcBE,      // ALU operands
-  output logic        ALUResultSrcE,           // Selects result to pass on to Memory stage
-  output logic [2:0]  ALUSelectE,              // ALU mux select signal
-  output logic [2:0]  Funct3E,                 // Instruction's funct3 field
-  output logic [6:0]  Funct7E,                 // Instruction's funct7 field
-  output logic        IntDivE,                 // Integer divide
-  output logic        W64E, UW64E,             // RV64 W/.uw-type operation
-  output logic        SubArithE,               // Subtraction or arithmetic shift
-  output logic        JumpE,                   // jump instruction
-  output logic        BranchE,                 // Branch instruction
-  output logic        BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
-  output logic [3:0]  BSelectE,                // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
-  output logic [3:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
-  output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
-  output logic        BMUActiveE,              // Bit manipulation instruction being executed
-  output logic [1:0]  CZeroE,                  // {czero.nez, czero.eqz} instructions active
-  output logic        MDUActiveE,              // Mul/Div instruction being executed
-  output logic [3:0]  CMOpM,                   // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  output logic        IFUPrefetchE,            // instruction prefetch
-  output logic        LSUPrefetchM,            // data prefetch
-  output logic [1:0]  ForwardAE, ForwardBE,    // Select signals for forwarding multiplexers
-  // Memory stage control signals
-  input  logic        StallM, FlushM,          // Stall, flush Memory stage
-  output logic [1:0]  MemRWE,                  // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write 
-  output logic [1:0]  MemRWM,                  // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write 
-  output logic        CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction
-  output logic [1:0]  AtomicM,                 // Atomic (AMO) instruction
-  output logic [2:0]  Funct3M,                 // Instruction's funct3 field
-  output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
-  output logic        FWriteIntM,              // FPU controller writes integer register file
-  // Writeback stage control signals
-  input  logic        StallW, FlushW,          // Stall, flush Writeback stage
-  output logic        RegWriteW, IntDivW,      // Instruction writes a register, is an integer divide
-  output logic [2:0]  ResultSrcW,              // Select source of result to write back to register file
-  // Stall during CSRs
-  output logic        CSRWriteFenceM,          // CSR write or fence instruction; needs to flush the following instructions
-  output logic [4:0]  RdE, RdM,                // Pipelined destination registers
-  // Forwarding controls
-  output logic [4:0]  RdW                      // Register destinations in Execute, Memory, or Writeback stage
-);
-
-  logic [4:0] Rs1E;                      // pipelined register sources
-  logic [6:0] OpD;                             // Opcode in Decode stage
-  logic [2:0] Funct3D;                         // Funct3 field in Decode stage
-  logic [6:0] Funct7D;                         // Funct7 field in Decode stage
-  logic [4:0] RdD;                             // Rs1/2 source register / dest reg in Decode stage
-
-  `define CTRLW 24
-
-  // pipelined control signals
-  logic        RegWriteD, RegWriteE;           // RegWrite (register will be written)
-  logic [2:0]  ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
-  logic [2:0]  PreImmSrcD;                     // Immediate source format (before amending for prefetches)
-  logic [1:0]  MemRWD;                         // Store (write to memory)
-  logic        ALUOpD;                         // 0 for address generation, 1 for all other operations (must use Funct3)
-  logic        BaseW64D;                       // W64 for Base instructions specifically
-  logic        BaseRegWriteD;                  // Indicates if Base instruction register write instruction
-  logic        BaseSubArithD;                  // Indicates if Base instruction subtracts, sra, slt, sltu
-  logic        BaseALUSrcBD;                   // Base instruction ALU B source select signal
-  logic        ALUSrcAD, ALUSrcBD;             // ALU inputs
-  logic        ALUResultSrcD, W64D, MDUD;      // ALU result, is RV64 W-type, is multiply/divide instruction
-  logic        CSRZeroSrcD;                    // Ignore setting and clearing zeros to CSR
-  logic        CSRReadD;                       // CSR read instruction
-  logic [1:0]  AtomicD;                        // Atomic (AMO) instruction
-  logic        FenceXD;                        // Fence instruction
-  logic        CMOD;                           // Cache management instruction
-  logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
-  logic        MemReadE, CSRReadE;             // Instruction reads memory, reads a CSR (needed for Hazard unit)
-  logic        MDUE;                           // MDU (multiply/divide) operation
-  logic        SCE;                            // Store Conditional instruction
-  logic        CSRWriteD, CSRWriteE;           // CSR write
-  logic        PrivilegedD, PrivilegedE;       // Privileged instruction
-  logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
-  logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
-  logic        SubArithD;                      // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
-  logic        subD, sraD, sltD, sltuD;        // Indicates if is one of these instructions
-  logic        BranchTakenE;                   // Branch is taken
-  logic        eqE, ltE;                       // Comparator outputs
-  logic        unused; 
-  logic        BranchFlagE;                    // Branch flag to use (chosen between eq or lt)
-  logic        IEURegWriteE;                   // Register write 
-  logic        IllegalERegAdrD;                // RV32E attempts to write upper 16 registers
-  logic [1:0]  AtomicE;                        // Atomic instruction 
-  logic        FenceD, FenceE;                 // Fence instruction
-  logic        SFenceVmaD;                     // sfence.vma instruction
-  logic        IntDivM;                        // Integer divide instruction
-  logic        RegWriteM;                      // Instruction writes a register (needed for Hazard unit)
-  logic [1:0]  CZeroD;
-  logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
-  logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
-  logic        FLSFunctD;                      // Detect floating-point loads and stores
-  logic        JRFunctD;                       // detect jalr instruction
-  logic        FenceFunctD;                    // Detect fence instruction
-  logic        CMOFunctD;                      // Detect CMO instruction
-  logic        AFunctD, AMOFunctD;             // Detect atomic instructions
-  logic        RWFunctD, MWFunctD;             // detect RW/MW instructions
-  logic        PFunctD, CSRFunctD;             // detect privileged / CSR instruction
-  logic        FenceM;                         // Fence.I or sfence.VMA instruction in memory stage
-  logic [2:0]  PreALUSelectD;                  // ALU Output selection mux control (before possible Zicond logic)
-  logic [2:0]  ALUSelectD;                     // ALU Output selection mux control
-  logic        IWValidFunct3D;                 // Detects if Funct3 is valid for IW instructions
-  logic [3:0]  CMOpD, CMOpE;                   // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  logic        IFUPrefetchD;                   // instruction prefetch
-  logic        LSUPrefetchD, LSUPrefetchE;     // data prefetch
-  logic        MatchDE;                        // Match between a source register in Decode stage and destination register in Execute stage
-  logic        FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read 
-  logic        FunctCZeroD;                    // Funct7 and Funct3 indicate czero.* (not including Op check)
-  logic        BUW64D;                         // Indiciates if it is a .uw type B instruction in Decode Stage
-  
-  // Extract fields
-  assign OpD     = InstrD[6:0];
-  assign Funct3D = InstrD[14:12];
-  assign Funct7D = InstrD[31:25];
-  assign Rs1D    = InstrD[19:15];
-  assign Rs2D    = InstrD[24:20];
-  assign RdD     = InstrD[11:7];
-
-  // Funct 7 checking
-  // Be rigorous about detecting illegal instructions if CSRs or bit manipulation or conditional ops are supported
-  // otherwise be cheap
-
-  if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED  | P.ZBC_SUPPORTED  | P.ZBS_SUPPORTED | 
-      P.ZBKB_SUPPORTED  | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED | 
-      P.ZKND_SUPPORTED  | P.ZKNH_SUPPORTED | P.ZICOND_SUPPORTED) begin:legalcheck // Exact integer decoding
-    logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
-    logic Funct7ShiftZeroD, Funct7Shiftb5D;
-
-    assign Funct7ZeroD      = (Funct7D == 7'b0000000); // most R-type instructions
-    assign Funct7b5D        = (Funct7D == 7'b0100000); // srai, sub
-    assign FunctCZeroD      = (Funct3D == 3'b101 | Funct3D == 3'b111) & (Funct7D == 7'b0000111) & P.ZICOND_SUPPORTED; // czero.eqz or czero.nez
-    assign Funct7ShiftZeroD = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; // 64-bit logical shifts allowed on XLEN=64, non-W
-    assign Funct7Shiftb5D   = (P.XLEN==64 & ~OpD[3]) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D;   // 64-bit arithmetic shifts allowed on XLEN=64, non-W
-    assign IShiftD          = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms
-    assign INoShiftD        = ((Funct3D != 3'b001) & (Funct3D != 3'b101));
-    assign IFunctD          = IShiftD | INoShiftD;
-    assign RFunctD          = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | FunctCZeroD | Funct7ZeroD;
-    assign MFunctD          = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
-    assign LFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | 
-                              ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
-    assign FLSFunctD        = (STATUS_FS != 2'b00) & ((Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) |
-                              (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED));
-    assign FenceFunctD      = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001);
-    assign CMOFunctD        = (Funct3D == 3'b010 & RdD == 5'b0) & 
-                              ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) |
-                               (P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) | 
-                                                      (InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2]));
-    assign AFunctD          = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011);
-    assign AMOFunctD        = (InstrD[31:27] == 5'b00001) |
-                              (InstrD[31:27] == 5'b00000) |
-                              (InstrD[31:27] == 5'b00100) |
-                              (InstrD[31:27] == 5'b01100) |
-                              (InstrD[31:27] == 5'b01000) |
-                              (InstrD[31:27] == 5'b10000) |
-                              (InstrD[31:27] == 5'b10100) |
-                              (InstrD[31:27] == 5'b11000) |
-                              (InstrD[31:27] == 5'b11100);
-    assign RWFunctD         = ((Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101) & Funct7ZeroD |
-                              (Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) & (P.XLEN == 64);
-    assign MWFunctD         = MFunctD & (P.XLEN == 64) & ~(Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b011);
-    assign SFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | 
-                              ((P.XLEN == 64) & (Funct3D == 3'b011));
-    assign BFunctD          = Funct3D[2:1] != 2'b01; // legal branches
-    assign JRFunctD         = Funct3D == 3'b000;
-    assign PFunctD          = Funct3D == 3'b000 & RdD == 5'b0;
-    assign CSRFunctD        = Funct3D[1:0] != 2'b00; 
-    assign IWValidFunct3D   = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101;
-  end else begin:legalcheck2
-    assign IFunctD = 1'b1; // Don't bother to separate out shift decoding
-    assign RFunctD = ~Funct7D[0]; // Not a multiply
-    assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
-    assign LFunctD = 1'b1; // don't bother to check Funct3 for loads
-    assign FLSFunctD = 1'b1; // don't bother to check Func3 for floating-point loads/stores
-    assign FenceFunctD = 1'b1; // don't bother to check fields for fences
-    assign CMOFunctD = 1'b1; // don't bother to check fields for CMO instructions
-    assign AFunctD = 1'b1; // don't bother to check fields for atomics
-    assign AMOFunctD = 1'b1; // don't bother to check Funct7 for AMO operations
-    assign RWFunctD = 1'b1; // don't bother to check fields for RW instructions
-    assign MWFunctD = 1'b1; // don't bother to check fields for MW instructions
-    assign SFunctD = 1'b1; // don't bother to check Funct3 for stores
-    assign BFunctD = 1'b1; // don't bother to check Funct3 for branches
-    assign JRFunctD = 1'b1; // don't bother to check Funct3 for jalrs
-    assign PFunctD = 1'b1; // don't bother to check fields for privileged instructions
-    assign CSRFunctD = 1'b1; // don't bother to check Funct3 for CSR operations
-    assign IWValidFunct3D = 1'b1;
-  end
-
-  // Main Instruction Decoder
-  /* verilator lint_off CASEINCOMPLETE */
-  always_comb begin
-    ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_1; // default: Illegal instruction
-    case(OpD)
-    // RegWrite_ImmSrc_ALUSrc(A_B)_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_BaseW64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal
-      7'b0000011: if (LFunctD) 
-                      ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_0; // loads
-      7'b0000111: if (FLSFunctD)  
-                      ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_1; // flw - only legal if FP supported
-      7'b0001111: if (FenceFunctD) begin
-                    if (P.ZIFENCEI_SUPPORTED)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0_0; // fence
-                    else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // fence treated as nop
-                  end else if (CMOFunctD) begin
-                      ControlsD = `CTRLW'b0_101_01_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction
-                  end
-      7'b0010011: if (IFunctD)    
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // I-type ALU
-      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // auipc
-      7'b0011011: if (IFunctD & IWValidFunct3D & P.XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // IW-type ALU for RV64i
-      7'b0100011: if (SFunctD) 
-                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
-      7'b0100111: if (FLSFunctD)
-                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
-      7'b0101111: if (AFunctD) begin
-                    if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
-                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
-                    else if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00011)
-                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
-                    else if (P.ZAAMO_SUPPORTED & AMOFunctD) 
-                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
-                 end
-      7'b0110011: if (RFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type 
-                  else if (MFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/Divide
-      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui
-      7'b0111011: if (RWFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i
-                  else if (MWFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0_0; // W-type Multiply/Divide
-      7'b1100011: if (BFunctD)   
-                      ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0_0; // branches
-      7'b1100111: if (JRFunctD)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jalr
-      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jal
-      7'b1110011: if (P.ZICSR_SUPPORTED) begin
-                   if (PFunctD)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0_0; // privileged; decoded further in privdec modules
-                   else if (CSRFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0_0; // csrs
-                  end
-    endcase
-  end
-  /* verilator lint_on CASEINCOMPLETE */
-
-  // Unswizzle control bits
-  // Squash control signals if coming from an illegal compressed instruction
-  // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
-  assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
-  assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
-          ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, 
-          PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
-  
-  assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
-  assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]);            // Don't write if setting or clearing zeros
-  assign SFenceVmaD = PrivilegedD & (InstrD[31:25] ==  7'b0001001);
-  assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
-  
-  // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
-  assign sltuD = (Funct3D == 3'b011); 
-  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed to distinguish sub from addi
-  assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
-  assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
-
-  // bit manipulation Configuration Block
-  if (P.ZBS_SUPPORTED  | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED  | P.ZBC_SUPPORTED |
-      P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED | 
-      P.ZKND_SUPPORTED | P.ZKNH_SUPPORTED) begin: bitmanipi 
-    logic IllegalBitmanipInstrD;          // Unrecognized B instruction
-    logic BRegWriteD;                     // Indicates if it is a R type BMU instruction in decode stage
-    logic BW64D;                          // Indicates if it is a W type BMU instruction in decode stage
-    logic BSubArithD;                     // TRUE for BMU ext, clr, andn, orn, xnor
-    logic BALUSrcBD;                      // BMU alu src select signal
-
-    bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD,
-      .BRegWriteD, .BALUSrcBD, .BW64D, .BUW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
-      .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE);
-    if (P.ZBA_SUPPORTED) begin
-      // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
-      assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
-    end else assign sltD = (Funct3D == 3'b010);
-
-    // Combine base and bit manipulation signals
-    // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
-    assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
-    // coverage on
-    assign RegWriteD = BaseRegWriteD | BRegWriteD; 
-    assign W64D = BaseW64D | BW64D;
-    assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
-    assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If BMU or R-type instruction involves inverted operand
-
-  end else begin: bitmanipi
-    assign PreALUSelectD = ALUOpD ? Funct3D : 3'b000; // add for address generation when not doing ALU operation
-    assign sltD = (Funct3D == 3'b010);
-    assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD ;
-    assign RegWriteD = BaseRegWriteD; 
-    assign W64D = BaseW64D;
-    assign ALUSrcBD = BaseALUSrcBD;
-    assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
-    assign BUW64D = 1'b0; // no .uw instructions
-
-    // tie off unused bit manipulation signals
-    assign BSelectE = 4'b0000;
-    assign ZBBSelectE = 4'b0000;
-    assign BALUControlE = 3'b0;
-    assign BMUActiveE = 1'b0;
-  end
-
-  if (P.ZICOND_SUPPORTED) begin: Zicond
-    logic  SomeCZeroD; // instruction is czero.*
-    assign SomeCZeroD = FunctCZeroD & (OpD == 7'b0110011);
-    assign CZeroD = {SomeCZeroD & (Funct3D == 3'b111), SomeCZeroD & (Funct3D == 3'b101)}; // {czero.nez, czero.eqz}
-    assign ALUSelectD = SomeCZeroD ? 3'b111 : PreALUSelectD; // perform AND operation for czero.* instructions
-  end else begin
-    assign CZeroD = 2'b00; // Zicond not supported
-    assign ALUSelectD = PreALUSelectD;
-  end
-
-  // Fences
-  // Ordinary fence is presently a nop
-  // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
-  if (P.ZIFENCEI_SUPPORTED & (P.ICACHE_SUPPORTED | P.DCACHE_SUPPORTED)) begin:fencei
-    logic FenceID;
-    assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
-    assign InvalidateICacheD = FenceID;
-    assign FlushDCacheD = FenceID;
-  end else begin:fencei
-    assign InvalidateICacheD = 1'b0;
-    assign FlushDCacheD = 1'b0;
-  end
-
-  // Cache Management instructions
-  always_comb begin
-    CMOpD = 4'b0000; // default: not a cbo instruction
-    if ((P.ZICBOZ_SUPPORTED) & CMOD) begin
-      CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero
-    end
-    if ((P.ZICBOM_SUPPORTED) & CMOD) begin
-      CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean
-      CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush 
-      CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval
-    end 
-  end
-
-  // Prefetch Hints
-  always_comb begin
-    // default: not a prefetch hint
-    IFUPrefetchD = 1'b0;
-    LSUPrefetchD = 1'b0;
-    ImmSrcD = PreImmSrcD;
-    if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch
-      /* verilator lint_off CASEINCOMPLETE */
-      case (Rs2D) // which type of prefectch?  Note: prefetch.r and .w are handled the same in Wally 
-        5'b00000: IFUPrefetchD = 1'b1; // prefetch.i
-        5'b00001: LSUPrefetchD = 1'b1; // prefetch.r
-        5'b00011: LSUPrefetchD = 1'b1; // prefetch.w
-        // default: not a prefetch hint
-      endcase
-      /* verilator lint_on CASEINCOMPLETE */
-      if (IFUPrefetchD | LSUPrefetchD) ImmSrcD = 3'b001; // use S-type immediate format for prefetches
-    end
-  end
-
-  // Decode stage pipeline control register
-  flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
-
-  // Execute stage pipeline control register and logic
-  flopenrc #(45) controlregE(clk, reset, FlushE, ~StallE,
-                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, BUW64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD},
-                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, UW64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE});
-  flopenrc #(5)  Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)  Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
-  flopenrc #(5)  RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
-
-  // Branch Logic
-  //  The comparator handles both signed and unsigned branches using BranchSignedE
-  //  Hence, only eq and lt flags are needed
-  assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE);
-  assign {eqE, ltE} = FlagsE;
-  mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
-  assign BranchTakenE = BranchFlagE ^ Funct3E[0];
-  assign PCSrcE = JumpE | BranchE & BranchTakenE;
-
-  // Other execute stage controller signals
-  assign MemReadE = MemRWE[1];
-  assign SCE = (ResultSrcE == 3'b100);
-  assign MDUActiveE = (ResultSrcE == 3'b011);
-  assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
-  assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
-  
-  // Memory stage pipeline control register
-  flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
-  flopenrc #(5)  RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);  
-
-  // Writeback stage pipeline control register
-  flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
-                         {RegWriteM, ResultSrcM, IntDivM},
-                         {RegWriteW, ResultSrcW, IntDivW});  
-  flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
-
-  // Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
-  assign CSRWriteFenceM = CSRWriteM | FenceM;
-
-  // Forwarding logic
-  always_comb begin
-    ForwardAE = 2'b00;
-    ForwardBE = 2'b00;
-    if (Rs1E != 5'b0)
-      if      ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
-      else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
- 
-    if (Rs2E != 5'b0)
-      if      ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
-      else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
-  end
-
-  // Stall on dependent operations that finish in Mem Stage and can't bypass in time
-  // Structural hazard causes stall if any of these events occur
-  assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
-  assign LoadStallD = (MemReadE|SCE) & MatchDE;  
-  assign StoreStallD = MemRWD[1] & MemRWE[0];   // Store or AMO followed by load or AMO
-  assign CSRRdStallD = CSRReadE & MatchDE;
-  assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
-  assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
-  assign StructuralStallD = LoadStallD | StoreStallD | CSRRdStallD | MDUStallD | FCvtIntStallD;
-endmodule
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
deleted file mode 100644
index 65eafe7f7..000000000
--- a/src/ieu/datapath.sv
+++ /dev/null
@@ -1,143 +0,0 @@
-///////////////////////////////////////////
-// datapath.sv
-//
-// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
-// Created: 9 January 2021
-// Modified: 
-//
-// Purpose: Wally Integer Datapath
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module datapath import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  // Decode stage signals
-  input  logic [2:0]        ImmSrcD,                 // Selects type of immediate extension
-  input  logic [31:0]       InstrD,                  // Instruction in Decode stage
-  input  logic [4:0]        Rs1D, Rs2D, Rs2E,             // Source registers
-  // Execute stage signals
-  input  logic [P.XLEN-1:0] PCE,                     // PC in Execute stage  
-  input  logic [P.XLEN-1:0] PCLinkE,                 // PC + 4 (of instruction in Execute stage)
-  input  logic [2:0]        Funct3E,                 // Funct3 field of instruction in Execute stage
-  input  logic [6:0]        Funct7E,                 // Funct7 field of instruction in Execute stage
-  input  logic              StallE, FlushE,          // Stall, flush Execute stage
-  input  logic [1:0]        ForwardAE, ForwardBE,    // Forward ALU operands from later stages
-  input  logic              W64E,UW64E,              // W64/.uw-type instruction
-  input  logic              SubArithE,               // Subtraction or arithmetic shift
-  input  logic              ALUSrcAE, ALUSrcBE,      // ALU operands
-  input  logic              ALUResultSrcE,           // Selects result to pass on to Memory stage
-  input  logic [2:0]        ALUSelectE,              // ALU mux select signal
-  input  logic              JumpE,                   // Is a jump (j) instruction
-  input  logic              BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
-  input  logic [3:0]        BSelectE,                // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
-  input  logic [3:0]        ZBBSelectE,              // ZBB mux select signal
-  input  logic [2:0]        BALUControlE,            // ALU Control signals for B instructions in Execute Stage
-  input  logic              BMUActiveE,              // Bit manipulation instruction being executed
-  input  logic [1:0]        CZeroE,                  // {czero.nez, czero.eqz} instructions active
-  output logic [1:0]        FlagsE,                  // Comparison flags ({eq, lt})
-  output logic [P.XLEN-1:0] IEUAdrE,                 // Address computed by ALU
-  output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
-  // Memory stage signals
-  input  logic              StallM, FlushM,          // Stall, flush Memory stage
-  input  logic              FWriteIntM, FCvtIntW,    // FPU writes integer register file, FPU converts float to int
-  input  logic [P.XLEN-1:0] FIntResM,                // FPU integer result
-  output logic [P.XLEN-1:0] SrcAM,                   // ALU's Source A in Memory stage to privilege unit for CSR writes
-  output logic [P.XLEN-1:0] WriteDataM,              // Write data in Memory stage
-  // Writeback stage signals
-  input  logic              StallW, FlushW,          // Stall, flush Writeback stage
-  input  logic              RegWriteW, IntDivW,      // Write register file, integer divide instruction
-  input  logic              SquashSCW,               // Squash a store conditional when a conflict arose
-  input  logic [2:0]        ResultSrcW,              // Select source of result to write back to register file
-  input  logic [P.XLEN-1:0] FCvtIntResW,             // FPU convert fp to integer result
-  input  logic [P.XLEN-1:0] ReadDataW,               // Read data from LSU
-  input  logic [P.XLEN-1:0] CSRReadValW,             // CSR read result
-  input  logic [P.XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
-  input  logic [P.XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
-  input  logic [4:0]        RdW                      // Destination register
-   // Hazard Unit signals 
-);
-
-  // Fetch stage signals
-  // Decode stage signals
-  logic [P.XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
-  logic [P.XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
-  // Execute stage signals
-  logic [P.XLEN-1:0] R1E, R2E;                       // Source operands read from register file
-  logic [P.XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
-  logic [P.XLEN-1:0] SrcAE, SrcBE;                   // ALU operands
-  logic [P.XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
-  // Memory stage signals
-  logic [P.XLEN-1:0] IEUResultM;                     // Result from execution stage
-  logic [P.XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
-  // Writeback stage signals
-  logic [P.XLEN-1:0] SCResultW;                      // Store Conditional result
-  logic [P.XLEN-1:0] ResultW;                        // Result to write to register file
-  logic [P.XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
-  logic [P.XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
-  logic [P.XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
-
-  // Decode stage
-  regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
-  extend #(P)        ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
- 
-  // Execute stage pipeline register and logic
-  flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
-  flopenrc #(P.XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
-  flopenrc #(P.XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
-  
-  mux3  #(P.XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
-  mux3  #(P.XLEN)  fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
-  comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
-  mux2  #(P.XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
-  mux2  #(P.XLEN)  srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
-  alu   #(P)       alu(SrcAE, SrcBE, W64E, UW64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE);
-  mux2  #(P.XLEN)  altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
-  mux2  #(P.XLEN)  ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
-
-  // Memory stage pipeline register
-  flopenrc #(P.XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
-  flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
-  flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
-  
-  // Writeback stage pipeline register and logic
-  flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
-
-  // floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt
-  if (P.F_SUPPORTED) begin:fpmux
-    mux2  #(P.XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
-    mux2  #(P.XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
-    if (P.IDIV_ON_FPU & P.F_SUPPORTED) begin
-      mux2  #(P.XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
-    end else begin 
-      assign MulDivResultW = MDUResultW;
-    end
-  end else begin:fpmux
-    assign IFResultM = IEUResultM; 
-    assign IFCvtResultW = IFResultW;
-    assign MulDivResultW = MDUResultW;
-  end
-  mux5  #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
- 
-  // handle Store Conditional result if atomic extension supported
-  if (P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
-  else                    assign SCResultW = '0;
-endmodule
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
deleted file mode 100644
index e820a3e41..000000000
--- a/src/ieu/ieu.sv
+++ /dev/null
@@ -1,130 +0,0 @@
-///////////////////////////////////////////
-// ieu.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Integer Execution Unit: datapath and controller
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ieu import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  // Decode stage signals
-  input  logic [31:0]       InstrD,                          // Instruction
-  input  logic [1:0]        STATUS_FS,                       // is FPU enabled?
-  input  logic [3:0]        ENVCFG_CBE,                      // Cache block operation enables
-  input  logic              IllegalIEUFPUInstrD,             // Illegal instruction
-  output logic              IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
-  // Execute stage signals
-  input  logic [P.XLEN-1:0] PCE,                             // PC
-  input  logic [P.XLEN-1:0] PCLinkE,                         // PC + 4
-  output logic              PCSrcE,                          // Select next PC (between PC+4 and IEUAdrE)
-  input  logic              FWriteIntE, FCvtIntE,            // FPU writes to integer register file, FPU converts float to int
-  output logic [P.XLEN-1:0] IEUAdrE,                         // Memory address
-  output logic              IntDivE, W64E,                   // Integer divide, RV64 W-type instruction 
-  output logic [2:0]        Funct3E,                         // Funct3 instruction field
-  output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
-  output logic [4:0]        RdE,                             // Destination register
-  output logic              MDUActiveE,                      // Mul/Div instruction being executed
-  output logic [3:0]        CMOpM,                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  output logic              IFUPrefetchE,                    // instruction prefetch
-  output logic              LSUPrefetchM,                    // datata prefetch
-  // Memory stage signals
-  input  logic              SquashSCW,                       // Squash store conditional, from LSU
-  output logic [1:0]        MemRWE,                          // Read/write control goes to LSU
-  output logic [1:0]        MemRWM,                          // Read/write control goes to LSU
-  output logic [1:0]        AtomicM,                         // Atomic control goes to LSU
-  output logic [P.XLEN-1:0] WriteDataM,                      // Write data to LSU
-  output logic [2:0]        Funct3M,                         // Funct3 (size and signedness) to LSU
-  output logic [P.XLEN-1:0] SrcAM,                           // ALU SrcA to Privileged unit and FPU
-  output logic [4:0]        RdM,                             // Destination register
-  input  logic [P.XLEN-1:0] FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
-  output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic              InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
-  output logic              BranchD, BranchE,
-  output logic              JumpD, JumpE,
-  // Writeback stage signals
-  input  logic [P.XLEN-1:0] FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
-  input  logic [P.XLEN-1:0] CSRReadValW,                     // CSR read value, 
-  input  logic [P.XLEN-1:0] MDUResultW,                      // multiply/divide unit result
-  input  logic [P.XLEN-1:0] FCvtIntResW,                     // FPU's float to int conversion result
-  input  logic              FCvtIntW,                        // FPU converts float to int
-  output logic [4:0]        RdW,                             // Destination register
-  input  logic [P.XLEN-1:0] ReadDataW,                       // LSU's read data
-  // Hazard unit signals
-  input  logic              StallD, StallE, StallM, StallW,  // Stall signals from hazard unit
-  input  logic              FlushD, FlushE, FlushM, FlushW,  // Flush signals
-  output logic              StructuralStallD,                // IEU detects structural hazard in Decode stage
-  output logic              LoadStallD,                      // Structural stalls for load, sent to performance counters
-  output logic              StoreStallD,                     // load after store hazard
-  output logic              CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
-  output logic              CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
-);
-
-  logic [2:0] ImmSrcD;                                       // Select type of immediate extension 
-  logic [1:0] FlagsE;                                        // Comparison flags ({eq, lt})
-  logic       ALUSrcAE, ALUSrcBE;                            // ALU source operands
-  logic [2:0] ResultSrcW;                                    // Selects result in Writeback stage
-  logic       ALUResultSrcE;                                 // Selects ALU result to pass on to Memory stage
-  logic [2:0] ALUSelectE;                                    // ALU select mux signal
-  logic       FWriteIntM;                                    // FPU writing to integer register file
-  logic       IntDivW;                                       // Integer divide instruction
-  logic [3:0] BSelectE;                                      // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
-  logic [3:0] ZBBSelectE;                                    // ZBB Result Select Signal in Execute Stage
-  logic [2:0] BALUControlE;                                  // ALU Control signals for B instructions in Execute Stage
-  logic       SubArithE;                                     // Subtraction or arithmetic shift
-  logic       UW64E;                                         // .uw-type instruction
-
-  logic [6:0] Funct7E;
-
-  // Forwarding signals
-  logic [4:0] Rs1D, Rs2D;
-  logic [4:0] Rs2E;                                          // Source registers
-  logic [1:0] ForwardAE, ForwardBE;                          // Select signals for forwarding multiplexers
-  logic       RegWriteW;                                     // Register will be written in Writeback stage
-  logic       BranchSignedE;                                 // Branch does signed comparison on operands
-  logic       BMUActiveE;                                    // Bit manipulation instruction being executed
-  logic [1:0] CZeroE;                                        // {czero.nez, czero.eqz} instructions active
-           
-  controller #(P) c(
-    .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
-    .IllegalIEUFPUInstrD, .IllegalBaseInstrD, 
-    .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,  .Rs2E,
-    .StallE, .FlushE, .FlagsE, .FWriteIntE,
-    .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE,
-    .Funct3E, .Funct7E, .IntDivE, .W64E, .UW64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE,
-    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, 
-    .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
-    .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
-    .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
-    .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
-    .RdW, .RdE, .RdM);
-
-  datapath #(P) dp(
-    .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .UW64E, .SubArithE,
-    .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, 
-    .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE,
-    .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
-    .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
-    .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW);             
-endmodule
diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv
deleted file mode 100644
index ac44916d7..000000000
--- a/src/ieu/kmu/packer.sv
+++ /dev/null
@@ -1,54 +0,0 @@
-///////////////////////////////////////////
-// packer.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 5 October 2023
-//
-// Purpose: RISCV kbitmanip pack operation unit
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module packer #(parameter WIDTH=32) (
-  input  logic [WIDTH/2-1:0] A, B,
-  input  logic [2:0] 	  PackSelect, 
-  output logic [WIDTH-1:0] PackResult
-);
-   
-   logic [WIDTH/2-1:0] 	 lowhalf, highhalf;
-   logic [7:0] 		       lowhalfh, highhalfh;
-   logic [15:0] 	       lowhalfw, highhalfw;
-   logic [WIDTH-1:0] 	   Pack, PackH, PackW;
-   
-   assign lowhalf   = A[WIDTH/2-1:0];
-   assign highhalf  = B[WIDTH/2-1:0];
-   assign lowhalfh  = A[7:0];
-   assign highhalfh = B[7:0];
-   assign lowhalfw  = A[15:0];
-   assign highhalfw = B[15:0];   
-   
-   assign Pack = {highhalf, lowhalf}; 
-   assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh}; 
-   assign PackW = (WIDTH == 64) ? {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw} : Pack;  // not implemented for RV32; treat as Pack to simplify logic in result mux
-   
-  always_comb 
-    if      (PackSelect[1:0] == 2'b11) PackResult = PackH;
-    else if (PackSelect[2]   == 1'b0)  PackResult = Pack;
-    else                               PackResult = PackW;
-endmodule
diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv
deleted file mode 100644
index 942a3d9a9..000000000
--- a/src/ieu/kmu/zbkb.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-///////////////////////////////////////////
-// zbkb.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 4 October 2023
-//
-// Purpose: RISC-V ZBKB top level unit: bit manipulation instructions for crypto
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zbkb #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0]   A, 
-  input  logic [WIDTH/2-1:0] B,
-  input  logic [2:0] 	     Funct3,
-  input  logic [2:0] 	     ZBKBSelect,
-  output logic [WIDTH-1:0]   ZBKBResult
-);
-   
-   logic [WIDTH-1:0] 	     Brev8Result;  // rev8, brev8
-   logic [WIDTH-1:0] 	     PackResult;   // pack, packh, packw (RB64 only)
-   logic [WIDTH-1:0] 	     ZipResult;    // zip, unzip
-
-   // brev8 just uses wires
-   genvar i, j;
-   for (i=0;i<WIDTH/8;i=i+1) 
-      for (j=0; j<8; j=j+1) 
-         assign Brev8Result[i*8+j] = A[i*8+7-j];
-   
-   packer #(WIDTH) pack(.A(A[WIDTH/2-1:0]), .B(B[WIDTH/2-1:0]), .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
-   zipper #(WIDTH) zipper(.A, .ZipSelect(Funct3[2]), .ZipResult);
-   
-   // ZBKB Result Select Mux
-   mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);   
-endmodule
diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv
deleted file mode 100644
index f7937f267..000000000
--- a/src/ieu/kmu/zbkx.sv
+++ /dev/null
@@ -1,52 +0,0 @@
-///////////////////////////////////////////
-// zbkx.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 1 February 2024
-//
-// Purpose: RISC-V ZBKX top level unit: crossbar permutation instructions for crypto
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zbkx #(parameter WIDTH=32) (
-   input  logic [WIDTH-1:0] A, B,
-   input  logic  	          ZBKXSelect,
-   output logic [WIDTH-1:0] ZBKXResult
-);
-   
-   logic [WIDTH-1:0] 	     xperm4, xperm8;
-   /* verilator lint_off UNUSEDSIGNAL */
-   logic [WIDTH-1:0]         xperm4lookup, xperm8lookup; // not all bits are used
-   /* verilator lint_on UNUSEDSIGNAL */
-   int 		     i;
-   
-   always_comb begin
-      for(i=0; i<WIDTH; i=i+4) begin: xperm4calc
-         xperm4lookup = A >> {B[i+:4], 2'b0};
-         xperm4[i+:4] = xperm4lookup[3:0];
-      end
-      for(i=0; i<WIDTH; i=i+8) begin: xperm8calc
-         xperm8lookup = A >> {B[i+:8], 3'b0};
-         xperm8[i+:8] = xperm8lookup[7:0];
-      end   
-   end
-
-   assign ZBKXResult = ZBKXSelect ? xperm4 : xperm8;
-endmodule
diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv
deleted file mode 100644
index 2cc0a3a18..000000000
--- a/src/ieu/kmu/zipper.sv
+++ /dev/null
@@ -1,45 +0,0 @@
-///////////////////////////////////////////
-// zipper.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 9 October 2023
-//
-// Purpose: RISCV kbitmanip zip operation unit
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zipper #(parameter WIDTH=64) (
-   input  logic [WIDTH-1:0] A,
-   input  logic 	          ZipSelect,
-   output logic [WIDTH-1:0] ZipResult
-);
-   
-   logic [WIDTH-1:0] 	     zip, unzip;
-   genvar 		     i;
-   
-   for (i=0; i<WIDTH/2; i+=1) begin: loop
-      assign zip[2*i]           = A[i];
-      assign zip[2*i + 1]       = A[i + WIDTH/2];      
-      assign unzip[i]           = A[2*i];
-      assign unzip[i + WIDTH/2] = A[2*i + 1];
-   end
-   
-   mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);   
-endmodule
diff --git a/src/ieu/kmu/zknde32.sv b/src/ieu/kmu/zknde32.sv
deleted file mode 100644
index 7e482d757..000000000
--- a/src/ieu/kmu/zknde32.sv
+++ /dev/null
@@ -1,61 +0,0 @@
-///////////////////////////////////////////
-// zknde32.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 27 November 2023
-// Modified: 31 January 2024
-//
-// Purpose: NIST AES64 decryption and encryption 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zknde32 import cvw::*; #(parameter cvw_t P) (
-   input  logic [31:0] A, B,
-   input  logic [1:0]  bs,
-   input  logic [3:0]  round,
-   input  logic [3:0]  ZKNSelect,
-   output logic [31:0] ZKNDEResult
-);
-
-    logic [4:0] 	shamt;
-    logic [7:0]     SboxIn;
-    logic [31:0]    ZKNEResult, ZKNDResult, rotin, rotout;             
-
-    // Initial shamt and Sbox input selection steps shared between encrypt and decrypt
-    assign shamt = {bs, 3'b0};          // shamt = bs * 8 (convert bytes to bits)
-    assign SboxIn = B[shamt +: 8];               // select byte bs of rs2
-
-    // Handle logic specific to encrypt or decrypt
-    if (P.ZKND_SUPPORTED) aes32d aes32d(.SboxIn, .finalround(ZKNSelect[2]), .result(ZKNDResult));
-    if (P.ZKNE_SUPPORTED) aes32e aes32e(.SboxIn, .finalround(ZKNSelect[2]), .result(ZKNEResult));
-
-    // Mux result if both decrypt and encrypt are supported; otherwise, choose the only result
-    if (P.ZKND_SUPPORTED & P.ZKNE_SUPPORTED) 
-        mux2 #(32) zknmux(ZKNDResult, ZKNEResult, ZKNSelect[0], rotin); 
-    else if (P.ZKND_SUPPORTED)
-        assign rotin = ZKNDResult;
-    else 
-        assign rotin = ZKNEResult;
-
-    // final rotate and XOR steps shared between encrypt and decrypt
-    mux4 #(32) mrotmux(rotin, {rotin[23:0], rotin[31:24]}, 
-                       {rotin[15:0], rotin[31:16]}, {rotin[7:0], rotin[31:8]},  bs, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
-    assign ZKNDEResult = A ^ rotout;               // xor with running value (A = rs1)
-endmodule
diff --git a/src/ieu/kmu/zknde64.sv b/src/ieu/kmu/zknde64.sv
deleted file mode 100644
index dee518074..000000000
--- a/src/ieu/kmu/zknde64.sv
+++ /dev/null
@@ -1,59 +0,0 @@
-///////////////////////////////////////////
-// zknde64.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 27 November 2023
-// Modified: 31 January 2024
-//
-// Purpose: NIST AES64 decryption and encryption 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zknde64 import cvw::*; #(parameter cvw_t P) (
-   input  logic [63:0] A, B,
-   input  logic [3:0]  round,
-   input  logic [3:0]  ZKNSelect,
-   output logic [63:0] ZKNDEResult
-);
-   
-    logic [63:0] 	     aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res;
-    logic [31:0]         SboxEIn, SboxKIn, Sbox0In, Sbox0Out;
-   
-    if (P.ZKND_SUPPORTED) // ZKND supports aes64ds, aes64dsm, aes64im
-        aes64d    aes64d(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .aes64im(ZKNSelect[3]), .result(aes64dRes)); // decode AES
-    else assign aes64dRes = '0;
-    if (P.ZKNE_SUPPORTED) begin // ZKNE supports aes64es, aes64esm
-        aes64e    aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
-        mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
-    end else begin  
-        assign aes64eRes = '0;
-        assign Sbox0In = SboxKIn;
-    end
-    
-    // One S Box is always needed for aes64ks1i and is also needed for aes64e if that is supported.  Put it at the top level to allow sharing
-    aessbox32 sbox(Sbox0In, Sbox0Out);                       // Substitute bytes of value obtained for tmp2 using Rijndael sbox
-
-    // Both ZKND and ZKNE support aes64ks1i and aes64ks2 instructions
-    aes64ks1i aes64ks1i(.round, .rs1(A[63:32]), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes));
-    aes64ks2  aes64ks2(.rs2(B), .rs1(A[63:32]), .result(aes64ks2Res));
-   
-    // Choose among decrypt, encrypt, key schedule 1, key schedule 2 results
-    mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNDEResult);
-endmodule
diff --git a/src/ieu/kmu/zknh32.sv b/src/ieu/kmu/zknh32.sv
deleted file mode 100644
index b20ce8d3a..000000000
--- a/src/ieu/kmu/zknh32.sv
+++ /dev/null
@@ -1,40 +0,0 @@
-///////////////////////////////////////////
-// zknh32.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 13 February 2024
-// Modified: 12 March 2024
-//
-// Purpose: RISC-V ZKNH 32-Bit top level unit: RV32 NIST Hash
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zknh32 (
-  input  logic [31:0] A, B,  
-  input  logic [3:0]  ZKNHSelect,
-  output logic [31:0] ZKNHResult
-);
-   
-   logic [31:0]	      sha256res, sha512res;
-
-  sha256 sha256(A, ZKNHSelect[1:0], sha256res);                          // 256-bit SHA support: sha256{sig0/sig1/sum0/sum1}
-  sha512_32 sha512(A, B, ZKNHSelect[2:0], sha512res);                    // 512-bit SHA support: sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r}
-  mux2 #(32) resultmux(sha256res, sha512res, ZKNHSelect[3], ZKNHResult); // SHA256 vs. SHA512 result mux
-endmodule
diff --git a/src/ieu/kmu/zknh64.sv b/src/ieu/kmu/zknh64.sv
deleted file mode 100644
index 218837ee8..000000000
--- a/src/ieu/kmu/zknh64.sv
+++ /dev/null
@@ -1,41 +0,0 @@
-///////////////////////////////////////////
-// zknh64.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 13 February 2024
-//
-// Purpose: RISC-V ZKNH 64-Bit top level unit: RV64 NIST Hash
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module zknh64 (
-   input  logic [63:0] A,
-   input  logic [3:0]  ZKNHSelect,
-   output logic [63:0] ZKNHResult
-);
-
-   logic [31:0]         sha256_32;
-   logic [63:0] 	sha256res, sha512res;   
-   
-   sha256 sha256(A[31:0], ZKNHSelect[1:0], sha256_32);                    // 256-bit SHA support: sha256{sig0/sig1/sum0/sum1}
-   assign sha256res = {{32{sha256_32[31]}}, sha256_32};                   // sign-extend 256-bit result from 32 to 64 bits
-   sha512_64 sha512(A, ZKNHSelect[1:0], sha512res);                       // 512-bit SHA support: sha512{sig0/sig1/sum0/sum1}
-   mux2 #(64) resultmux(sha256res, sha512res, ZKNHSelect[3], ZKNHResult); // SHA256 vs. SHA512 result mux
-endmodule
diff --git a/src/ieu/sha/sha256.sv b/src/ieu/sha/sha256.sv
deleted file mode 100644
index 12d08f2ce..000000000
--- a/src/ieu/sha/sha256.sv
+++ /dev/null
@@ -1,66 +0,0 @@
-///////////////////////////////////////////
-// sha256.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 13 February 2024
-//
-// Purpose: RISC-V ZKNH 256-bit SHA: select shifted inputs and XOR3
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module sha256 (
-   input  logic [31:0] A,
-   input  logic [1:0]  ZKNHSelect,
-   output logic [31:0] result
-);
-
-   logic [31:0] x[4][3];
-   logic [31:0] y[3];
-   
-   // sha256{sig0/sig1/sum0/sum1} select shifted operands for 32-bit xor3 and then sign-extend
-
-   // sha256sig0
-   assign x[0][0] = {A[6:0], A[31:7]};    // ror 7
-   assign x[0][1] = {A[17:0], A[31:18]};  // ror 18
-   assign x[0][2] = {3'b0, A[31:3]};      // >> 3
-
-   // sha256sig1
-   assign x[1][0] = {A[16:0], A[31:17]};  // ror 17
-   assign x[1][1] = {A[18:0], A[31:19]};  // ror 19
-   assign x[1][2] = {10'b0, A[31:10]};    // >> 10
-
-   // sha256sum0
-   assign x[2][0] = {A[1:0],  A[31:2]};   // ror 2
-   assign x[2][1] = {A[12:0], A[31:13]};  // ror 13
-   assign x[2][2] = {A[21:0], A[31:22]};  // ror 22
-
-   // sha256sum1
-   assign x[3][0] = {A[5:0], A[31:6]};    // ror 6
-   assign x[3][1] ={ A[10:0], A[31:11]};  // ror 11
-   assign x[3][2] = {A[24:0], A[31:25]};  // ror 25
-
-   // 32-bit muxes to select inputs to xor3 for sha256 
-   assign y[0] = x[ZKNHSelect[1:0]][0];
-   assign y[1] = x[ZKNHSelect[1:0]][1];
-   assign y[2] = x[ZKNHSelect[1:0]][2];
-
-   // sha256 32-bit xor3
-   assign result = y[0] ^ y[1] ^ y[2];
-endmodule
diff --git a/src/ieu/sha/sha512_32.sv b/src/ieu/sha/sha512_32.sv
deleted file mode 100644
index ce205172c..000000000
--- a/src/ieu/sha/sha512_32.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-///////////////////////////////////////////
-// sha512_32.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 13 February 2024
-//
-// Purpose: RISC-V (RV32) ZKNH 512-bit SHA: select shifted inputs and XOR6
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module sha512_32 (
-   input  logic [31:0] A, B,
-   input  logic [2:0]  ZKNHSelect,
-   output logic [31:0] result
-);
-
-   logic [31:0] x[4][3];
-   logic [31:0] y[3];
-
-   // rotate/shift a 64-bit value contained in {B, A} and select 32 bits
-   // sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor
-
-   // The l flavors differ from h by using low bits of B instead of zeros in x[0/1][2]
-
-   // sha512sig0h/l
-   assign x[0][0] = {B[0], A[31:1]};                           // ror 1
-   assign x[0][1] = {B[7:0], A[31:8]};                         // ror 8
-   assign x[0][2] = {B[6:0] & {7{ZKNHSelect[0]}}, A[31:7]};    // ror/srl 7
-
-   // sha512sig1h/l
-   assign x[1][0] = {A[28:0], B[31:29]};                       // ror 61
-   assign x[1][1] = {B[18:0], A[31:19]};                       // ror 19
-   assign x[1][2] = {B[5:0] & {6{ZKNHSelect[0]}}, A[31:6]};    // ror/srl 6
-
-   // sha512sum0r
-   assign x[2][0] = {A[6:0], B[31:7]};                         // ror 39
-   assign x[2][1] = {A[1:0], B[31:2]};                         // ror 34
-   assign x[2][2] = {B[27:0], A[31:28]};                       // ror 28
-
-   // sha512sum1r
-   assign x[3][0] = {A[8:0], B[31:9]};                         // ror 41
-   assign x[3][1] = {B[13:0], A[31:14]};                       // ror 14
-   assign x[3][2] = {B[17:0], A[31:18]};                       // ror 18
-
-   // 32-bit muxes to select inputs to xor6 for sha512
-   assign y[0] = x[ZKNHSelect[2:1]][0];
-   assign y[1] = x[ZKNHSelect[2:1]][1];
-   assign y[2] = x[ZKNHSelect[2:1]][2];
- 
-   // sha512 32-bit xor6
-   assign result = y[0] ^ y[1] ^ y[2];
-endmodule
diff --git a/src/ieu/sha/sha512_64.sv b/src/ieu/sha/sha512_64.sv
deleted file mode 100644
index 47fefce04..000000000
--- a/src/ieu/sha/sha512_64.sv
+++ /dev/null
@@ -1,66 +0,0 @@
-///////////////////////////////////////////
-// sha512_64.sv
-//
-// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
-// Created: 13 February 2024
-//
-// Purpose: RISC-V (RV64) ZKNH 512-bit SHA: select shifted inputs and XOR3
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module sha512_64 (
-   input  logic [63:0] A,
-   input  logic [1:0]  ZKNHSelect,
-   output logic [63:0] result
-);
-
-   logic [63:0] x[4][3];
-   logic [63:0] y[3];
-
-   // sha512{sig0/sig1/sum0/sum1} select rotated/shifted operands for 64-bit xor3
-
-   // sha512sig0
-   assign x[0][0] = {A[0],   A[63:1]};    // ror 1
-   assign x[0][1] = {A[7:0], A[63:8]};    // ror 8
-   assign x[0][2] = {7'b0,   A[63:7]};    // >> 7
-
-   // sha512sig1
-   assign x[1][0] = {A[18:0], A[63:19]};  // ror 19
-   assign x[1][1] = {A[60:0], A[63:61]};  // ror 61
-   assign x[1][2] = {6'b0,    A[63:6]};   // >> 6
-
-   // sha512sum0
-   assign x[2][0] = {A[27:0], A[63:28]};  // ror 28
-   assign x[2][1] = {A[33:0], A[63:34]};  // ror 34
-   assign x[2][2] = {A[38:0], A[63:39]};  // ror 39
-
-   // sha512sum1
-   assign x[3][0] = {A[13:0], A[63:14]};  // ror 14
-   assign x[3][1] = {A[17:0], A[63:18]};  // ror 18
-   assign x[3][2] = {A[40:0], A[63:41]};  // ror 41
-
-   // 64-bit muxes to select inputs to xor3 for sha512
-   assign y[0] = x[ZKNHSelect[1:0]][0];
-   assign y[1] = x[ZKNHSelect[1:0]][1];
-   assign y[2] = x[ZKNHSelect[1:0]][2];
-
-   // sha512 64-bit xor3
-   assign result = y[0] ^ y[1] ^ y[2];
-endmodule
diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv
deleted file mode 100644
index 8d4da28d9..000000000
--- a/src/ieu/shifter.sv
+++ /dev/null
@@ -1,85 +0,0 @@
-///////////////////////////////////////////
-// shifter.sv
-//
-// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, Kevin Kim <kekim@hmc.edu>
-// Created: 9 January 2021
-// Modified: 6 February 2023
-//
-// Purpose: RISC-V 32/64 bit shifter
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module shifter import cvw::*; #(parameter cvw_t P) (
-  input  logic [P.XLEN-1:0]     A,                             // shift Source
-  input  logic [P.LOG_XLEN-1:0] Amt,                           // Shift amount
-  input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
-  output logic [P.XLEN-1:0]     Y);                            // Shifted result
-
-  logic [2*P.XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
-  logic [P.LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
-  logic                        Sign;                          // Sign bit for sign extension
-
-  assign Sign = A[P.XLEN-1] & SubArith;  // sign bit for sign extension
-  if (P.XLEN==32) begin // rv32
-    if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
-      always_comb  // funnel mux
-        case({Right, Rotate})
-          2'b00: Z = {A[31:0], 31'b0};
-          2'b01: Z = {A[31:0], A[31:1]};
-          2'b10: Z = {{31{Sign}}, A[31:0]};
-          2'b11: Z = {A[30:0], A[31:0]};
-        endcase
-    end else begin: norotfunnel32 //rv32 shifter without rotates
-      always_comb  // funnel mux
-        if (Right)  Z = {{31{Sign}}, A[31:0]};
-        else        Z = {A[31:0], 31'b0};
-    end
-    assign TruncAmt = Amt; // shift amount
-  end else begin // rv64
-    logic [P.XLEN-1:0]         A64;                            
-    mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
-    if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
-      // shifter rotate source select mux
-      logic [P.XLEN-1:0]   RotA;                          // rotate source
-      mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
-      always_comb  // funnel mux
-        case ({Right, Rotate})
-          2'b00: Z = {A64[63:0],{63'b0}};
-          2'b01: Z = {RotA[63:0], RotA[63:1]};
-          2'b10: Z = {{63{Sign}}, A64[63:0]};
-          2'b11: Z = {RotA[62:0], RotA[63:0]};
-        endcase
-    end else begin: norotfunnel64 // rv64 shifter without rotates
-      always_comb  // funnel mux
-        if (Right)  Z = {{63{Sign}}, A64[63:0]};
-        else        Z = {A64[63:0], {63'b0}};
-    end
-    assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
-  end
-  
-  // Opposite offset for right shifts
-  assign Offset = Right ? TruncAmt : ~TruncAmt;
-  
-  // Funnel operation
-  assign ZShift = Z >> Offset;
-  assign Y = ZShift[P.XLEN-1:0];    
-endmodule
diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
deleted file mode 100644
index 3bef28881..000000000
--- a/src/ifu/bpred/RASPredictor.sv
+++ /dev/null
@@ -1,102 +0,0 @@
-///////////////////////////////////////////
-// RASPredictor.sv
-//
-// Written: Rose Thomposn rose@rosethompson.net
-// Created: 15 February 2021
-// Modified: 25 January 2023
-//
-// Purpose: 2 bit saturating counter predictor with parameterized table depth.
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module RASPredictor import cvw::*;  #(parameter cvw_t P)(
-  input  logic             clk,
-  input  logic             reset, 
-  input  logic             StallD, StallE, StallM, FlushD, FlushE, FlushM,
-  input  logic             BPReturnWrongD,                      // Prediction class is wrong
-  input  logic             ReturnD,
-  input  logic             ReturnE, CallE,                  // Instr class
-  input  logic             BPReturnF,
-  input  logic [P.XLEN-1:0] PCLinkE,                                   // PC of instruction after a call
-  output logic [P.XLEN-1:0] RASPCF                                     // Top of the stack
-   );
-
-  logic                     CounterEn;
-  localparam Depth = $clog2(P.RAS_SIZE);
-
-  logic [Depth-1:0]         NextPtr, Ptr, P1, M1, IncDecPtr;
-  logic [P.RAS_SIZE-1:0]     [P.XLEN-1:0] memory;
-  integer        index;
-
-  logic      PopF;
-  logic      PushE;
-  logic      RepairD;
-  logic      IncrRepairD, DecRepairD;
-  
-  logic      DecPtr;
-  logic      FlushedReturnDE;
-  logic      WrongPredReturnD;
-  
-  
-  assign PopF = BPReturnF & ~StallD & ~FlushD;
-  assign PushE = CallE & ~StallM & ~FlushM;
-
-  assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE;
-  assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (FlushM & ReturnE); // flushed return
-
-  assign RepairD = WrongPredReturnD | FlushedReturnDE ;
-
-  assign IncrRepairD = FlushedReturnDE | (WrongPredReturnD & ~ReturnD); // Guessed it was a return, but its not
-
-  assign DecRepairD =  WrongPredReturnD & ReturnD; // Guessed non return but is a return.
-    
-  assign CounterEn = PopF | PushE | RepairD;
-
-  assign DecPtr = (PopF | DecRepairD) & ~IncrRepairD;
-
-  assign P1 = 1;
-  assign M1 = '1; // -1
-  mux2 #(Depth) PtrMux(P1, M1, DecPtr, IncDecPtr);
-  logic [Depth-1:0] Sum;
-  assign Sum = Ptr + IncDecPtr;
-  if(|P.RAS_SIZE[Depth-1:0])
-    assign NextPtr = Sum >= P.RAS_SIZE[Depth-1:0] ? 0 : Sum; // wrap back around if our stack is not a power of 2
-  else
-    assign NextPtr = Sum;
-  //assign NextPtr = Ptr + IncDecPtr;
-
-  flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
-
-  // RAS must be reset. 
-  always_ff @ (posedge clk) begin
-    if(reset) begin
-      for(index=0; index<P.RAS_SIZE; index++)
-    memory[index] <= {P.XLEN{1'b0}};
-    end else if(PushE) begin
-      memory[NextPtr] <= PCLinkE;
-    end
-  end
-
-  assign RASPCF = memory[Ptr];
-  
-  
-endmodule
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
deleted file mode 100644
index 8b8793f27..000000000
--- a/src/ifu/bpred/bpred.sv
+++ /dev/null
@@ -1,224 +0,0 @@
-///////////////////////////////////////////
-// bpred.sv
-//
-// Written: Rose Thomposn rose@rosethompson.net
-// Created: 12 February 2021
-// Modified: 19 January 2023
-//
-// Purpose: Branch direction prediction and jump/branch target prediction.
-//          Prediction made during the fetch stage and corrected in the execution stage.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`define INSTR_CLASS_PRED 1
-`include "BranchPredictorType.vh"
-
-
-module bpred import cvw::*;  #(parameter cvw_t P) (
-  input  logic             clk, reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-  // Fetch stage
-  // the prediction
-  input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-  input  logic [P.XLEN-1:0] PCNextF,                   // Next Fetch Address
-  input  logic [P.XLEN-1:0] PCPlus2or4F,               // PCF+2/4
-  output logic [P.XLEN-1:0] PC1NextF,                  // Branch Predictor predicted or corrected fetch address on miss prediction
-  output logic [P.XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
-
-  // Update Predictor
-  input  logic [P.XLEN-1:0] PCF,                       // Fetch stage instruction address
-  input  logic [P.XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-  input  logic [P.XLEN-1:0] PCE,                       // Execution stage instruction address
-  input  logic [P.XLEN-1:0] PCM,                       // Memory stage instruction address
-
-  input  logic [31:0]      PostSpillInstrRawF,        // Instruction
-
-  // Branch and jump outcome
-  input  logic             InstrValidD, InstrValidE,
-  input  logic             BranchD, BranchE,
-  input  logic             JumpD, JumpE,
-  input  logic             PCSrcE,                    // Executation stage branch is taken
-  input  logic [P.XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input  logic [P.XLEN-1:0] IEUAdrM,                   // The branch/jump target address
-  input  logic [P.XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
-  output logic [3:0]       IClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
-
-  // Report branch prediction status
-  output logic             BPWrongE,                  // Prediction is wrong
-  output logic             BPWrongM,                  // Prediction is wrong
-  output logic             BPDirWrongM,           // Prediction direction is wrong
-  output logic             BTAWrongM,                 // Prediction target wrong
-  output logic             RASPredPCWrongM,           // RAS prediction is wrong
-  output logic             IClassWrongM               // Class prediction is wrong
-  );
-
-  logic [1:0]              BPDirF;
-
-  logic                    BPDirWrongE;
-  logic [P.XLEN-1:0]       BPBTAF, RASPCF;
-  
-  logic                    BPPCSrcF;
-  logic [P.XLEN-1:0]       BPPCF;
-  logic [P.XLEN-1:0]       PC0NextF;
-  logic [P.XLEN-1:0]       PCCorrectE;
-
-  logic                    RASTargetWrongE;
-
-  logic                    BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
-  logic                    BPBranchF, BPJumpF, BPReturnF, BPCallF;
-  logic                    BPBranchD, BPJumpD, BPReturnD, BPCallD;
-  logic                    ReturnD, CallD;
-  logic                    ReturnE, CallE;
-  logic                    BranchM, JumpM, ReturnM, CallM;
-  logic                    BranchW, JumpW, ReturnW, CallW;
-  logic                    BPReturnWrongD;
-  logic                    BPBTAWrongM;
-  logic                    PCSrcM;
-  
-  // Part 1 branch direction prediction
-  if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor
-    twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
-      .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
-      .BranchE, .BranchM, .PCSrcE);
-
-  end else if (P.BPRED_TYPE == `BP_GSHARE) begin:Predictor
-    gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE,
-      .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, 
-      .PCSrcE);
-
-  end else if (P.BPRED_TYPE == `BP_GLOBAL) begin:Predictor
-    gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE,
-      .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
-      .PCSrcE);
-
-  end else if (P.BPRED_TYPE == `BP_GSHARE_BASIC) begin:Predictor
-    gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
-      .BranchE, .BranchM, .PCSrcE);
-
-  end else if (P.BPRED_TYPE == `BP_GLOBAL_BASIC) begin:Predictor
-    gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
-      .BranchE, .BranchM, .PCSrcE);
-  
-  end else if (P.BPRED_TYPE == `BP_LOCAL_BASIC) begin:Predictor
-    localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
-      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
-      .BranchE, .BranchM, .PCSrcE);
-  end else if (P.BPRED_TYPE == `BP_LOCAL_AHEAD) begin:Predictor
-    localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
-      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirD(BPDirF), .BPDirWrongE,
-      .BranchE, .BranchM, .PCSrcE);
-  end else if (P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin:Predictor
-    localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
-      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCE, .PCM, .BPDirD(BPDirF), .BPDirWrongE,
-      .BranchD, .BranchE, .BranchM, .PCSrcE);
-  end 
-
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  
-  // Part 2 Branch target address prediction
-  // BTB contains target address for all CFI
-
-  btb #(P, P.BTB_SIZE) 
-    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM,
-      .BPBTAF, 
-      .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
-      .BPBTAWrongM,
-      .IClassWrongM,
-      .IEUAdrE, .IEUAdrM,
-      .IClassD({CallD, ReturnD, JumpD, BranchD}), 
-      .IClassE({CallE, ReturnE, JumpE, BranchE}), 
-      .IClassM({CallM, ReturnM, JumpM, BranchM}),
-      .IClassW({CallW, ReturnW, JumpW, BranchW}));
-
-  icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, 
-    .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
-    .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
-    .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .BPReturnWrongD);
-
-  // Part 3 RAS
-  RASPredictor #(P) RASPredictor(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-    .BPReturnF, .ReturnD, .ReturnE, .CallE,
-    .BPReturnWrongD, .RASPCF, .PCLinkE);
-
-  // Check the prediction
-  // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
-  // if the class prediction is wrong a regular instruction may have been predicted as a taken branch
-  // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
-  // The next instruction is always valid as no other flush would occur at the same time as the branch and not
-  // also flush the branch.  This will change in a superscaler cpu. 
-  // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
-  assign BPWrongE = (PCCorrectE != PCD) & InstrValidE & InstrValidD;
-  flopenrc #(1) BPWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPWrongM);
-  
-  // Output the predicted PC or corrected PC on miss-predict.
-  assign BPPCSrcF = (BPBranchF & BPDirF[1]) | BPJumpF;
-  mux2 #(P.XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF);
-  // Selects the BP or PC+2/4.
-  mux2 #(P.XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF);
-  // If the prediction is wrong select the correct address.
-  mux2 #(P.XLEN) pcmux1(PC0NextF, PCCorrectE, BPWrongE, PC1NextF);  
-  // Correct branch/jump target.
-  mux2 #(P.XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
-  
-  // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
-  // Effectively this is PCM+4 or the non-existant PCLinkM
-  if(`INSTR_CLASS_PRED) mux2 #(P.XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
-  else  assign NextValidPCE = PCE;
-
-  if(P.ZIHPM_SUPPORTED) begin
-    logic [P.XLEN-1:0]       RASPCD, RASPCE;
-    logic                    RASPredPCWrongE;  
-    // performance counters
-    // 1. class         (class wrong / minstret) (IClassWrongM / csr)                    // Correct now
-    // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
-    // 3. target ras    (ras target wrong / class[2])
-    // 4. direction     (br dir wrong / class[0])
-
-    // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
-    // could be wrong or the fall through address selected for branch predict not taken.
-    // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
-    // both without the above inaccuracies.
-    assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
-
-    flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
-    flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
-    flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
-      {BPDirWrongE, RASPredPCWrongE},
-      {BPDirWrongM, RASPredPCWrongM});
-
-    assign BTAWrongM = BPBTAWrongM & PCSrcM;
-    
-  end else begin
-    assign {BTAWrongM, RASPredPCWrongM} = 0;
-  end
-
-  assign IClassM = {CallM, ReturnM, JumpM, BranchM};
-  
-endmodule
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
deleted file mode 100644
index 6c6ace763..000000000
--- a/src/ifu/bpred/btb.sv
+++ /dev/null
@@ -1,107 +0,0 @@
-///////////////////////////////////////////
-// btb.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: February 15, 2021
-// Modified: 24 January 2023 
-//
-// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
-//          It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module btb import cvw::*;  #(parameter cvw_t P, 
-                             parameter Depth = 10 ) (
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
-  input  logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
-  output logic [P.XLEN-1:0] BPBTAF,                      // BTB's guess at PC
-  output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
-  output logic BPBTAWrongM,
-  // update
-  input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
-  input  logic [P.XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
-  input  logic [P.XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
-  input  logic [3:0]       IClassD,                 // Instruction class to insert into btb
-  input  logic [3:0]       IClassE,                 // Instruction class to insert into btb
-  input  logic [3:0]       IClassM,                 // Instruction class to insert into btb
-  input  logic [3:0]       IClassW
-);
-
-  logic [Depth-1:0]        PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex;
-  logic                    MatchD, MatchE, MatchM, MatchW, MatchX;
-  logic [P.XLEN+3:0]       ForwardBTBPredF;
-  logic [P.XLEN+3:0]       TableBTBPredF;
-  logic [P.XLEN-1:0]       IEUAdrW;
-  logic [P.XLEN-1:0]       PCW;
-  logic [P.XLEN-1:0]       BPBTAD, BPBTAE;
-  logic                    BPBTAWrongE;
-  logic                    BTBWrongM;
-  
-  
-  // hashing function for indexing the PC
-  // We have Depth bits to index, but XLEN bits as the input.
-  // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
-  // using compressed instructions.  XOR bit 1 with the MSB of index.
-  assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
-  assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
-  assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
-  assign PCMIndex = {PCM[Depth+1] ^ PCM[1], PCM[Depth:2]};
-  assign PCWIndex = {PCW[Depth+1] ^ PCW[1], PCW[Depth:2]};
-
-  assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 
-
-  assign MatchD = PCFIndex == PCDIndex;
-  assign MatchE = PCFIndex == PCEIndex;
-  assign MatchM = PCFIndex == PCMIndex;
-  assign MatchW = PCFIndex == PCWIndex;
-  assign MatchX = MatchD | MatchE | MatchM | MatchW;
-
-  assign ForwardBTBPredF = MatchD ? {IClassD, BPBTAD} :
-                                 MatchE ? {IClassE, IEUAdrE} :
-                                 MatchM ? {IClassM, IEUAdrM} :
-                                 {IClassW, IEUAdrW} ;
-
-  assign {BTBIClassF, BPBTAF} = MatchX ? ForwardBTBPredF : {TableBTBPredF};
-
-
-  // An optimization may be using a PC relative address.
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**Depth), .WIDTH(P.XLEN+4)) memory(
-    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
-     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({IClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
-
-  flopenrc #(P.XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD);
-
-  // BPBTAE is not strickly necessary.  However it is used by two parts of wally.
-  // 1. It gates updates to the BTB when the prediction does not change.  This save power.
-  // 2. BPBTAWrongE is used by the performance counters to track when the BTB's BPBTA or instruction class is wrong.
-  flopenrc #(P.XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE);
-  assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (IClassE[0] | IClassE[1] & ~IClassE[2]);
-
-  flopenrc #(1) BPBTAWrongMReg(clk, reset, FlushM, ~StallM, BPBTAWrongE, BPBTAWrongM);  
-  assign BTBWrongM = BPBTAWrongM | IClassWrongM;
-  
-  flopenr #(P.XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-  flopenr #(P.XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
-
-endmodule
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
deleted file mode 100644
index 46702e6b1..000000000
--- a/src/ifu/bpred/gshare.sv
+++ /dev/null
@@ -1,116 +0,0 @@
-///////////////////////////////////////////
-// gshare.sv
-//
-// Written: Rose Thompson
-// Email: rose@rosethompson.net
-// Created: 16 March 2021
-// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
-// Modified: 20 February 2023
-//
-// Purpose: gshare and Global History Branch predictors
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-module gshare import cvw::*; #(parameter cvw_t P,
-                               parameter XLEN, 
-                parameter k = 10,
-                parameter integer TYPE = 1) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirF, 
-  output logic            BPDirWrongE,
-  // update
-  input logic [XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input logic             BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE
-);
-
-  logic                   MatchD, MatchE, MatchM, MatchW;
-  logic                   MatchX;
-
-  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF;
-  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
-
-  logic [k-1:0]           IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
-
-  logic [k-1:0]           GHRF, GHRD, GHRE, GHRM;
-  logic [k-1:0]           GHRNextM, GHRNextF;
-  logic                   PCSrcM;
-
-  if(TYPE == 1) begin
-  assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
-  assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
-  assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  end else if(TYPE == 0) begin
-  assign IndexNextF = GHRNextF;
-  assign IndexF = GHRF;
-  assign IndexD = GHRD;
-  assign IndexE = GHRE;
-  assign IndexM = GHRM;
-  end
-
-  flopenrc #(k) IndexWReg(clk, reset, FlushW, ~StallW, IndexM, IndexW);
-
-  assign MatchD = BranchD & ~FlushE & (IndexF == IndexD);
-  assign MatchE = BranchE & ~FlushM & (IndexF == IndexE);
-  assign MatchM = BranchM & ~FlushW & (IndexF == IndexM);
-  assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
-  assign MatchX = MatchD | MatchE | MatchM | MatchW;
-
-  assign FwdNewBPDirF = MatchD ? {2{BPDirD[1]}} :
-                                   MatchE ? {NewBPDirE} :
-                                   MatchM ? {NewBPDirM} :
-                   NewBPDirW ;
-  
-  assign BPDirF = MatchX ? FwdNewBPDirF : PHTBPDirF;
-
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(IndexNextF),
-    .rd1(PHTBPDirF),
-    .wa2(IndexM),
-    .wd2(NewBPDirM),
-    .we2(BranchM),
-    .bwe2(1'b1));
-
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
-
-  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
-
-  assign GHRNextF = BPBranchF ? {BPDirF[1], GHRF[k-1:1]} : GHRF;
-  assign GHRF = BranchD  ? {BPDirD[1], GHRD[k-1:1]} : GHRD;
-  assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
-  assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
-
-  assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
-
-  flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchM, GHRNextM, GHRM);
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-endmodule
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
deleted file mode 100644
index 3f88494fe..000000000
--- a/src/ifu/bpred/gsharebasic.sv
+++ /dev/null
@@ -1,89 +0,0 @@
-///////////////////////////////////////////
-// gsharebasic.sv
-//
-// Written: Rose Thompson
-// Email: rose@rosethompson.net
-// Created: 16 March 2021
-// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
-// Modified: 20 February 2023 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module gsharebasic import cvw::*; #(parameter cvw_t P,
-                     parameter XLEN,
-                     parameter k = 10,
-                     parameter TYPE = 1) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirF, 
-  output logic            BPDirWrongE,
-  // update
-  input logic [XLEN-1:0] PCNextF, PCM,
-  input logic             BranchE, BranchM, PCSrcE
-);
-
-  logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirD, BPDirE;
-  logic [1:0]             NewBPDirE, NewBPDirM;
-
-  logic [k-1:0]           GHRF, GHRD, GHRE, GHRM, GHR;
-  logic [k-1:0]           GHRNext;
-  logic                   PCSrcM;
-
-  if(TYPE == 1) begin
-  assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
-  end else if(TYPE == 0) begin
-  assign IndexNextF = GHRNext;
-  assign IndexM = GHRM;
-  end
-  
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(IndexNextF),
-    .rd1(BPDirF),
-    .wa2(IndexM),
-    .wd2(NewBPDirM),
-    .we2(BranchM),
-    .bwe2(1'b1));
-
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
-
-  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
-
-  assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
-  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
-  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
-  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
-
-
-endmodule
diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv
deleted file mode 100644
index 0b1992210..000000000
--- a/src/ifu/bpred/icpred.sv
+++ /dev/null
@@ -1,106 +0,0 @@
-///////////////////////////////////////////
-// icpred.sv
-//
-// Written: Rose Thomposn rose@rosethompson.net
-// Created: February 26, 2023
-// Modified: February 26, 2023
-//
-// Purpose: Partial decode of instructions into control flow instructions (cfi)P
-//          Call, Return, Jump, and Branch
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module icpred import cvw::*;  #(parameter cvw_t P, 
-                                parameter INSTR_CLASS_PRED = 1)(
-  input  logic             clk, reset,
-  input  logic             StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, 
-  input  logic [31:0]      PostSpillInstrRawF, InstrD,        // Instruction
-  input  logic             BranchD, BranchE,
-  input  logic             JumpD, JumpE,
-  output logic             BranchM, BranchW,
-  output logic             JumpM, JumpW,
-  output logic             CallD, CallE, CallM, CallW,
-  output logic             ReturnD, ReturnE, ReturnM, ReturnW,
-  input  logic             BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF,
-  output logic             BPCallF, BPReturnF, BPJumpF, BPBranchF,
-  output logic             IClassWrongM, BPReturnWrongD
-);
-
-  logic                    IClassWrongD;
-  logic                    BPBranchD, BPJumpD, BPReturnD, BPCallD;
-  logic                    IClassWrongE;
-  
-  if (!INSTR_CLASS_PRED) begin : DirectClassDecode
-    // This section is mainly for testing, verification, and PPA comparison.
-    // An alternative to using the BTB to store the instruction class is to partially decode
-    // the instructions in the Fetch stage into, Call, Return, Jump, and Branch instructions.
-    // This logic is not described in the text book as of 23 February 2023.
-    logic     cjal, cj, cjr, cjalr, CJumpF, CBranchF;
-    logic     NCJumpF, NCBranchF;
-
-    if(P.ZCA_SUPPORTED) begin
-      logic [4:0] CompressedOpcF;
-      assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
-      assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
-      assign cj = CompressedOpcF == 5'h0d;
-      assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-      assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-      assign CJumpF = cjal | cj | cjr | cjalr;
-      assign CBranchF = CompressedOpcF[4:1] == 4'h7;
-    end else begin
-      assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0;
-    end
-
-    assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
-    assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
-    
-    assign BPBranchF = NCBranchF | (P.ZCA_SUPPORTED & CBranchF);
-    assign BPJumpF = NCJumpF | (P.ZCA_SUPPORTED & (CJumpF));
-    assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
-        (P.ZCA_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
-    
-    assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
-        (P.ZCA_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
-
-  end else begin
-    // This section connects the BTB's instruction class prediction.
-    assign {BPCallF, BPReturnF, BPJumpF, BPBranchF} = {BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF};
-  end
-  
-  assign ReturnD = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // returnurn must returnurn to ra or x5
-  assign CallD = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // call(r) must link to ra or x5
-
-  flopenrc #(2) InstrClassRegE(clk, reset,  FlushE, ~StallE, {CallD, ReturnD}, {CallE, ReturnE});
-  flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, {CallE, ReturnE, JumpE, BranchE}, {CallM, ReturnM, JumpM, BranchM});
-  flopenrc #(4) InstrClassRegW(clk, reset,  FlushM, ~StallW, {CallM, ReturnM, JumpM, BranchM}, {CallW, ReturnW, JumpW, BranchW});
-
-  // branch predictor
-  flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, IClassWrongE, IClassWrongM);
-  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, IClassWrongD, IClassWrongE);
-
-  // pipeline the predicted class
-  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, {BPCallF, BPReturnF, BPJumpF, BPBranchF}, {BPCallD, BPReturnD, BPJumpD, BPBranchD});
-
-  // branch class prediction wrong.
-  assign IClassWrongD = |({BPCallD, BPReturnD, BPJumpD, BPBranchD} ^ {CallD, ReturnD, JumpD, BranchD});
-  assign BPReturnWrongD = BPReturnD ^ ReturnD;
-
-endmodule
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
deleted file mode 100644
index e3d6ef8ed..000000000
--- a/src/ifu/bpred/localaheadbp.sv
+++ /dev/null
@@ -1,116 +0,0 @@
-///////////////////////////////////////////
-// localaheadbp
-//
-// Written: Rose Thompson
-// Email: rose@rosethompson.net
-// Created: 16 March 2021
-//
-// Purpose: local history branch predictor with ahead pipelining and SRAM memories.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module localaheadbp import cvw::*; #(parameter cvw_t P, 
-                                     parameter XLEN,
-                      parameter m = 6, // 2^m = number of local history branches 
-                      parameter k = 10) ( // number of past branches stored
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirD, 
-  output logic            BPDirWrongE,
-  // update
-  input logic [XLEN-1:0] PCNextF, PCM,
-  input logic             BranchE, BranchM, PCSrcE
-);
-
-  logic [k-1:0]           IndexNextF, IndexM;
-  //logic [1:0]             BPDirD, BPDirE;
-  logic [1:0]             BPDirE;
-  logic [1:0]             BPDirM;
-  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
-
-  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
-  logic [k-1:0]           LHRNextW;
-  logic                   PCSrcM;
-  logic [2**m-1:0][k-1:0] LHRArray;
-  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
-  logic [XLEN-1:0]       PCW;
-  
-  
-  logic                    UpdateM;
-
-  //assign IndexNextF = LHR;
-  assign IndexM = LHRW;
-  
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
-    .ce1(~StallD), .ce2(~StallW & ~FlushW),
-    .ra1(LHRF),
-    .rd1(BPDirD),
-    .wa2(IndexM),
-    .wd2(NewBPDirW),
-    .we2(BranchM),
-    .bwe2(1'b1));
-
-  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
-  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirE, BPDirM);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM));
-  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
-
-  assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE;
-
-  // This is the main difference between global and local history basic implementations. In global, 
-  // the ghr wraps back into itself directly without
-  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
-  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
-  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
-  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
-  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
-
-  // this is local history
-  //genvar      index;
-  //assign UpdateM = BranchM & ~StallW & ~FlushW;
-  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
-  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
-
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) BHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(IndexLHRNextF),
-    .rd1(LHRF),
-    .wa2(IndexLHRM),
-    .wd2(LHRNextW),
-    .we2(BranchM),
-    .bwe2('1));  
-
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
-  //assign LHRF = LHRNextF;
-  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
-  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
-  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
-  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
-
-  flopenr #(XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
-endmodule
diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv
deleted file mode 100644
index 5b2334a3d..000000000
--- a/src/ifu/bpred/localbpbasic.sv
+++ /dev/null
@@ -1,107 +0,0 @@
-///////////////////////////////////////////
-// localbpbasic
-//
-// Written: Rose Thompson
-// Email: rose@rosethompson.net
-// Created: 16 March 2021
-//
-// Purpose: Local history branch predictor. Basic implementation without any repair and flop memories.
-
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module localbpbasic import cvw::*; #(parameter cvw_t P,
-                                     parameter XLEN,
-                      parameter m = 6, // 2^m = number of local history branches 
-                      parameter k = 10) ( // number of past branches stored
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirF, 
-  output logic            BPDirWrongE,
-  // update
-  input logic [XLEN-1:0] PCNextF, PCM,
-  input logic             BranchE, BranchM, PCSrcE
-);
-
-  logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirD, BPDirE;
-  logic [1:0]             NewBPDirE, NewBPDirM;
-
-  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHR;
-  logic [k-1:0]           LHRNextW;
-  logic                   PCSrcM;
-  logic [2**m-1:0][k-1:0]  LHRArray;
-  logic [m-1:0]            IndexLHRNextF, IndexLHRM;
-  
-  logic                    UpdateM;
-
-  assign IndexNextF = LHR;
-  assign IndexM = LHRM;
-  
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(IndexNextF),
-    .rd1(BPDirF),
-    .wa2(IndexM),
-    .wd2(NewBPDirM),
-    .we2(BranchM),
-    .bwe2(1'b1));
-
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
-
-  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
-
-  // This is the main difference between global and local history basic implementations. In global, 
-  // the ghr wraps back into itself directly without
-  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
-  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
-  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
-  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
-  assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
-
-  // this is local history
-  genvar      index;
-  assign UpdateM = BranchM & ~StallW & ~FlushW;
-  assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
-  for (index = 0; index < 2**m; index = index +1) begin:localhist
-    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
-                                      .d(LHRNextW), .q(LHRArray[index]));
-  end
-  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
-  assign LHR = LHRArray[IndexLHRNextF];
-
-  // this is global history
-  //flopenr #(k) LHRReg(clk, reset, ~StallM & ~FlushM & BranchM, LHRNextW, LHR);
-
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHR, LHRF);
-  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
-  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
-  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
-
-
-endmodule
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
deleted file mode 100644
index e15c77f3c..000000000
--- a/src/ifu/bpred/localrepairbp.sv
+++ /dev/null
@@ -1,137 +0,0 @@
-///////////////////////////////////////////
-// localrepairbp
-//
-// Written: Rose Thompson
-// Email: rose@rosethompson.net
-// Created: 15 April 2023
-//
-// Purpose: Local history branch predictor with speculation and repair using CBH.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module localrepairbp import cvw::*; #(parameter cvw_t P,
-                                      parameter XLEN,
-                       parameter m = 6, // 2^m = number of local history branches 
-                       parameter k = 10) ( // number of past branches stored
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW,
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirD, 
-  output logic            BPDirWrongE,
-  // update
-  input logic [XLEN-1:0] PCNextF, PCE, PCM,
-  input logic             BranchD, BranchE, BranchM, PCSrcE
-);
-
-  //logic [1:0]             BPDirD, BPDirE;
-  logic [1:0]             BPDirE;
-  logic [1:0]             BPDirM;
-  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
-
-  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
-  logic [k-1:0]           LHRNextW;
-  logic                   PCSrcM;
-  logic [2**m-1:0][k-1:0] LHRArray;
-  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
-  logic [XLEN-1:0]       PCW;
-
-  logic [k-1:0]           LHRCommittedF, LHRSpeculativeF;
-  logic [m-1:0]           IndexLHRD;
-  logic [k-1:0]           LHRNextE;
-  logic                   SpeculativeFlushedF;
-  
-  
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
-    .ce1(~StallD), .ce2(~StallW & ~FlushW),
-    .ra1(LHRF),
-    .rd1(BPDirD),
-    .wa2(LHRW),
-    .wd2(NewBPDirW),
-    .we2(BranchM),
-    .bwe2(1'b1));
-
-  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
-  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirE, BPDirM);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM));
-  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
-
-  assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE;
-
-  // This is the main difference between global and local history basic implementations. In global, 
-  // the ghr wraps back into itself directly without
-  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
-  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
-  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
-  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
-  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
-
-  // this is local history
-  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
-  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
-
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) BHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(IndexLHRNextF),
-    .rd1(LHRCommittedF),
-    .wa2(IndexLHRM),
-    .wd2(LHRNextW),
-    .we2(BranchM),
-    .bwe2('1));
-
-  assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
-  assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE;
-  // RT: TODO active research: replace with a small CAM, quantify benefit
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk),
-    .ce1(~StallF), .ce2(~StallE & ~FlushE),
-    .ra1(IndexLHRNextF),
-    .rd1(LHRSpeculativeF),
-    .wa2(IndexLHRD),
-    .wd2(LHRNextE),
-    .we2(BranchD),
-    .bwe2('1));
-  // RT: TODO active research: replace with small CAM, quantify benefit
-  logic [2**m-1:0]        FlushedBits;
-  always_ff @(posedge clk) begin // Valid bit array,
-    SpeculativeFlushedF <= FlushedBits[IndexLHRNextF];
-    if (reset | FlushD) FlushedBits        <= '1;
-    if(BranchD & ~StallE & ~FlushE) begin
-      FlushedBits[IndexLHRD] <= 1'b0;
-    end
-  end
-
-  //assign SpeculativeFlushedF = '1;
-  mux2 #(k) LHRMux(LHRSpeculativeF, LHRCommittedF, SpeculativeFlushedF, LHRF);
-
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
-  //assign LHRF = LHRNextF;
-  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
-  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
-  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
-  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
-
-  flopenr #(XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
-endmodule
diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
deleted file mode 100644
index d0055b1ae..000000000
--- a/src/ifu/decompress.sv
+++ /dev/null
@@ -1,188 +0,0 @@
-///////////////////////////////////////////
-// decompress.sv
-//
-// Written: David_Harris@hmc.edu
-// Created: 9 January 2021
-// Modified: 18 January 2023
-//
-// Purpose: Expand 16-bit compressed instructions to 32 bits
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-module decompress import cvw::*;  #(parameter cvw_t P) (
-  input  logic [31:0] InstrRawD,         // 32-bit instruction or raw compressed 16-bit instruction in bottom half
-  output logic [31:0] InstrD,            // Decompressed instruction
-  output logic        IllegalCompInstrD  // Invalid decompressed instruction
-);
-
-  logic [32:0]        LInstrD; // decompressed instruction with illegal flag in [32]                      
-  logic [15:0]        instr16;
-  logic [4:0]         rds1, rs2, rs1p, rs2p, rds1p, rdp;
-  logic [11:0]        immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
-  logic [19:0]        immCJ, immCILUI;
-  logic [5:0]         immSH;
-  logic [1:0]         op;
-  logic               LegalCompInstrD;   
-    
-  // Extract op and register source/destination fields
-  assign instr16 = InstrRawD[15:0]; // instruction is already aligned
-  assign op = instr16[1:0];
-  assign rds1 = instr16[11:7];
-  assign rs2 = instr16[6:2];
-  assign rs1p = {2'b01, instr16[9:7]};
-  assign rds1p = {2'b01, instr16[9:7]};
-  assign rs2p = {2'b01, instr16[4:2]};
-  assign rdp = {2'b01, instr16[4:2]};
-  
-  // extract compressed immediate formats
-  assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
-  assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
-  assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00}; 
-  assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000}; 
-  assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
-  assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
-  assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
-  assign immCSD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
-  assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
-  assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
-  assign immCI = {{7{instr16[12]}}, instr16[6:2]};
-  assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};                                                    // c.lui
-  assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};        // c.addi16sp
-  assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
-  assign immSH = {instr16[12], instr16[6:2]};                                                             // c. shift instructions: c.srli, c.srai, c.slli
-
-// only for RV128  
-//      assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
-//      assign immCSSQ = {2{instr16[10]}, instr16[10:7], instr16[12:11], 4'b0000};
-//      assign immCLQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
-//      assign immCSQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
-
-  always_comb
-    if (op == 2'b11) begin // noncompressed instruction
-      LInstrD = {1'b1, InstrRawD}; 
-    end else begin  // convert compressed instruction into uncompressed
-      LInstrD = {1'b0, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval
-      case ({op, instr16[15:13]})
-        5'b00000: if (immCIW != 0)                      LInstrD = {1'b1, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011};                      // c.addi4spn
-        5'b00001: if (P.ZCD_SUPPORTED)                  LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000111};                          // c.fld
-        5'b00010:                                       LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000011};                           // c.lw
-        5'b00011: if (P.XLEN==32) begin
-                    if (P.ZCF_SUPPORTED)                LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000111};                           // c.flw
-                  end else                              LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000011};                          // c.ld
-        5'b00100: if (P.ZCB_SUPPORTED) 
-                    if (instr16[12:10] == 3'b000)       LInstrD = {1'b1, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011};   // c.lbu
-                    else if (instr16[12:10] == 3'b001) begin
-                      if (instr16[6])                   LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011};         // c.lh
-                      else                              LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011};         // c.lhu
-                    end else if (instr16[12:10] == 3'b010)
-                                                        LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb 
-                    else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
-                                                        LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh
-        5'b00101: if (P.ZCD_SUPPORTED)                  LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111};      // c.fsd
-        5'b00110:                                       LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011};        // c.sw
-        5'b00111: if (P.XLEN==32) begin
-                    if (P.ZCF_SUPPORTED)                LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111};        // c.fsw
-                  end else                              LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011};      // c.sd
-        5'b01000: if (rds1 != 5'b0) 
-                    if (immCI[5:0] != 0)                LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0010011};                          // c.addi 
-                    else                                LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.addi with imm = 0 is a HINT, treated as nop
-                  else if (immCI[5:0] == 6'b0)          LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.nop = addi x0, x0, 0
-                  else                                  LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.nop with imm != 0 is a HINT, treated as nop
-        5'b01001: if (P.XLEN==32)                       LInstrD = {1'b1, immCJ, 5'b00001, 7'b1101111};                                    // c.jal
-                  else if (rds1 != 5'b0)                LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0011011};                          // c.addiw
-        5'b01010: if (rds1 != 5'b0)                     LInstrD = {1'b1, immCI, 5'b00000, 3'b000, rds1, 7'b0010011};                      // c.li
-                  else                                  LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.li with rd = 0 is a HINT, treated as nop
-        5'b01011: if (rds1 == 5'b00010) begin                
-                     if (immCIASP[9:4] != 6'b0)         LInstrD = {1'b1, immCIASP, rds1, 3'b000, rds1, 7'b0010011};                       // c.addi16sp
-                  end else if (immCILUI[5:0] != 0) 
-                    if (rds1 != 5'b0)                   LInstrD = {1'b1, immCILUI, rds1, 7'b0110111};                                     // c.lui
-                    else                                LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.lui with rd = 0, imm!=0 is a HINT, treated as nop
-        5'b01100: if (instr16[11:10] == 2'b00) begin
-                    if (P.XLEN > 32 | ~immSH[5])        LInstrD = {1'b1, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011};             // c.srli; shamt[5] must be 0 in RV32C
-                  end else if (instr16[11:10] == 2'b01) begin 
-                    if (P.XLEN > 32 | ~immSH[5])        LInstrD = {1'b1, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011};             // c.srai; shamt[5] must be 0 in RV32C
-                  end else if (instr16[11:10] == 2'b10) LInstrD = {1'b1, immCI, rds1p, 3'b111, rds1p, 7'b0010011};                        // c.andi
-                  else if (instr16[12:10] == 3'b011) begin
-                    if (instr16[6:5] == 2'b00)          LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011};             // c.sub
-                    else if (instr16[6:5] == 2'b01)     LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011};             // c.xor
-                    else if (instr16[6:5] == 2'b10)     LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011};             // c.or
-                    else                                LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011};             // c.and
-                  end else begin // (instr16[12:10] == 3'b111)
-                    if (instr16[6:5] == 2'b00 & P.XLEN > 32)
-                                                        LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011};             // c.subw
-                    else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
-                                                        LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011};             // c.addw
-                    else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) 
-                                                        LInstrD = {1'b1, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011};             // c.zext.b = andi rd, rs1, 255
-                    else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
-                                                        LInstrD = {1'b1, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011};             // c.sext.b
-                    else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
-                                                        LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011};  // c.zext.h
-                    else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
-                                                        LInstrD = {1'b1, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011};             // c.sext.h
-                    else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) 
-                                                        LInstrD = {1'b1, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011};             // c.not = xori
-                    else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32) 
-                                                        LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011};         // c.zext.w = add.uw rd, rs1, 0
-                    else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED) 
-                                                        LInstrD = {1'b1, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011};             // c.mul
-                  end
-        5'b01101:                                       LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j
-        5'b01110:                                       LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011};    // c.beqz
-        5'b01111:                                       LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011};    // c.bnez
-        5'b10000: if (immSH != 0) begin
-                    if (P.XLEN > 32 | ~immSH[5]) begin                                                                                    // shamt[5] = 1 is reserved in RV32C
-                      if (rds1 != 5'b0)                 LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011};               // c.slli
-                      else                              LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.slli with rd = 0 is a HINT, treated as nop
-                    end
-                  end else                              LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.slli with immm = 0 is a HINT, treated as nop
-        5'b10001: if (P.ZCD_SUPPORTED)                  LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111};                  // c.fldsp
-        5'b10010: if (rds1 != 5'b0)                     LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011};                   // c.lwsp
-        5'b10011: if (P.XLEN == 32) begin 
-                    if (P.ZCF_SUPPORTED)                LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111};                   // c.flwsp
-                  end else if (rds1 != 5'b0)            LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011};                  // c.ldsp
-        5'b10100: if (instr16[12] == 0)
-                    if (rs2 == 5'b00000) begin 
-                      if (rds1 != 5'b0)                 LInstrD = {1'b1, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111};       // c.jr
-                    end else
-                      if (rds1 != 5'b0)                 LInstrD = {1'b1, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011};            // c.mv
-                      else                              LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.mv with rd = 0 is a HINT, treated as nop
-                  else
-                    if (rs2 == 5'b00000) begin
-                      if (rds1 == 5'b00000)             LInstrD = {1'b1, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011};                  // c.ebreak
-                      else                              LInstrD = {1'b1, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111};                      // c.jalr
-                    end else
-                      if (rds1 != 0)                    LInstrD = {1'b1, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011};                // c.add
-                      else                              LInstrD = {1'b1, 25'b0, 7'b0010011};                                              // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL
-        5'b10101: if (P.ZCD_SUPPORTED)                  LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
-        5'b10110:                                       LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011};   // c.swsp
-        5'b10111: if (P.XLEN==32) begin 
-                    if (P.ZCF_SUPPORTED)                LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111};   // c.fswsp
-                  end else                              LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
-        default: ; // illegal instruction
-      endcase
-    end
-
-  // extract instruction and illegal from LInstrD
-  assign {LegalCompInstrD, InstrD} = LInstrD;
-  assign IllegalCompInstrD = ~LegalCompInstrD;
-
-endmodule
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
deleted file mode 100644
index cc4576fd2..000000000
--- a/src/ifu/ifu.sv
+++ /dev/null
@@ -1,433 +0,0 @@
-///////////////////////////////////////////
-// ifu.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified:
-//
-// Purpose: Instruction Fetch Unit
-//           PC, branch prediction, instruction cache
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ifu import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk, reset,
-  input  logic                 StallF, StallD, StallE, StallM, StallW,
-  input  logic                 FlushD, FlushE, FlushM, FlushW, 
-  output logic                 IFUStallF,                                // IFU stalsl pipeline during a multicycle operation
-  // Command from CPU
-  input  logic                 InvalidateICacheM,                        // Clears all instruction cache valid bits
-  input  logic                 CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
-  input  logic                 InstrValidD, InstrValidE, 
-  input  logic                 BranchD, BranchE,
-  input  logic                 JumpD, JumpE,
-  // Bus interface
-  output logic [P.PA_BITS-1:0] IFUHADDR,                                 // Bus address from IFU to EBU
-  input  logic [P.XLEN-1:0]    HRDATA,                                   // Bus read data from IFU to EBU
-  input  logic                 IFUHREADY,                                // Bus ready from IFU to EBU
-  output logic                 IFUHWRITE,                                // Bus write operation from IFU to EBU
-  output logic [2:0]           IFUHSIZE,                                 // Bus operation size from IFU to EBU
-  output logic [2:0]           IFUHBURST,                                // Bus burst from IFU to EBU
-  output logic [1:0]           IFUHTRANS,                                // Bus transaction type from IFU to EBU
-
-  output logic [P.XLEN-1:0]    PCSpillF,                                 // PCF with possible + 2 to handle spill to HPTW
-  // Execute
-  output logic [P.XLEN-1:0]    PCLinkE,                                  // The address following the branch instruction. (AKA Fall through address)
-  input  logic                 PCSrcE,                                   // Executation stage branch is taken
-  input  logic [P.XLEN-1:0]    IEUAdrE,                                  // The branch/jump target address
-  input  logic [P.XLEN-1:0]    IEUAdrM,                                  // The branch/jump target address
-  output logic [P.XLEN-1:0]    PCE,                                      // Execution stage instruction address
-  output logic                 BPWrongE,                                 // Prediction is wrong
-  output logic                 BPWrongM,                                 // Prediction is wrong
-  // Mem
-  output logic                 CommittedF,                               // I$ or bus memory operation started, delay interrupts
-  input  logic [P.XLEN-1:0]    EPCM,                                     // Exception Program counter from privileged unit
-  input  logic [P.XLEN-1:0]    TrapVectorM,                              // Trap vector, from privileged unit
-  input  logic                 RetM, TrapM,                              // return instruction, or trap
-  output logic [31:0]          InstrD,                                   // The decoded instruction in Decode stage
-  output logic [31:0]          InstrM,                                   // The decoded instruction in Memory stage
-  output logic [31:0]          InstrOrigM,                               // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  output logic [P.XLEN-1:0]    PCM,                                      // Memory stage instruction address
-  // branch predictor
-  output logic [3:0]           IClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-  output logic                 BPDirWrongM,                          // Prediction direction is wrong
-  output logic                 BTAWrongM,                                // Prediction target wrong
-  output logic                 RASPredPCWrongM,                          // RAS prediction is wrong
-  output logic                 IClassWrongM,                             // Class prediction is wrong
-  output logic                 ICacheStallF,                             // I$ busy with multicycle operation
-  // Faults
-  input  logic                 IllegalBaseInstrD,                        // Illegal non-compressed instruction
-  input  logic                 IllegalFPUInstrD,                         // Illegal FP instruction
-  output logic                 InstrPageFaultF,                          // Instruction page fault 
-  output logic                 IllegalIEUFPUInstrD,                      // Illegal instruction including compressed & FP
-  output logic                 InstrMisalignedFaultM,                    // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
-  // mmu management
-  input  logic [1:0]           PrivilegeModeW,                           // Priviledge mode in Writeback stage
-  input  logic [P.XLEN-1:0]    PTE,                                      // Hardware page table walker (HPTW) writes Page table entry (PTE) to ITLB
-  input  logic [1:0]           PageType,                                 // Hardware page table walker (HPTW) writes PageType to ITLB
-  input  logic                 ITLBWriteF,                               // Writes PTE and PageType to ITLB
-  input  logic [P.XLEN-1:0]    SATP_REGW,                                // Location of the root page table and page table configuration
-  input  logic                 STATUS_MXR,                               // Status CSR: make executable page readable 
-  input  logic                 STATUS_SUM,                               // Status CSR: Supervisor access to user memory
-  input  logic                 STATUS_MPRV,                              // Status CSR: modify machine privilege
-  input  logic [1:0]           STATUS_MPP,                               // Status CSR: previous machine privilege level
-  input  logic                 ENVCFG_PBMTE,                             // Page-based memory types enabled
-  input  logic                 ENVCFG_ADUE,                              // HPTW A/D Update enable
-  input  logic                 sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
-  output logic                 ITLBMissOrUpdateAF,                       // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
-  input  var logic [7:0]       PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
-  input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
-  output logic                 InstrAccessFaultF,                        // Instruction access fault 
-  output logic                 ICacheAccess,                             // Report I$ read to performance counters
-  output logic                 ICacheMiss                                // Report I$ miss to performance counters
-);
-
-  localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
-  localparam            LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
-
-  logic [P.XLEN-1:0]           PCNextF;                                  // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
-  logic [P.XLEN-1:0]           PC1NextF;                                 // Branch predictor next PCF
-  logic [P.XLEN-1:0]           PC2NextF;                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
-  logic [P.XLEN-1:0]           UnalignedPCNextF;                         // The next PCF, but not aligned to 2 bytes. 
-  logic                        BranchMisalignedFaultE;                   // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
-  logic [P.XLEN-1:0]           PCPlus2or4F;                              // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
-  logic [P.XLEN-1:0]           PCSpillNextF;                             // Next PCF after possible + 2 to handle spill
-  logic [P.XLEN-1:2]           PCPlus4F;                                 // PCPlus4F is always PCF + 4.  Fancy way to compute PCPlus2or4F
-  logic [P.XLEN-1:0]           PCD;                                      // Decode stage instruction address
-  logic [P.XLEN-1:0]           NextValidPCE;                             // The PC of the next valid instruction in the pipeline after  csr write or fence
-  logic [P.XLEN-1:0]           PCF;                                      // Fetch stage instruction address
-  logic [P.PA_BITS-1:0]        PCPF;                                     // Physical address after address translation
-  logic [P.XLEN+1:0]           PCFExt;                                
-
-  logic [31:0]                 IROMInstrF;                               // Instruction from the IROM
-  logic [31:0]                 ICacheInstrF;                             // Instruction from the I$
-  logic [31:0]                 InstrRawF;                                // Instruction from the IROM, I$, or bus
-  logic                        CompressedF, CompressedE;                 // The fetched instruction is compressed
-  logic [31:0]                 PostSpillInstrRawF;                       // Fetch instruction after merge two halves of spill
-  logic [31:0]                 InstrRawD;                                // Non-decompressed instruction in the Decode stage
-  logic                        IllegalIEUInstrD;                         // IEU Instruction (regular or compressed) is not good
-  
-  logic [1:0]                  IFURWF;                                   // IFU alreays read IFURWF = 10
-  logic [31:0]                 InstrE;                                   // Instruction in the Execution stage
-  logic [31:0]                 NextInstrD, NextInstrE;                   // Instruction into the next stage after possible stage flush
-
-  logic                        CacheableF;                               // PMA indicates instruction address is cacheable
-  logic                        SelSpillNextF;                            // In a spill, stall pipeline and gate local stallF
-  logic                        BusStall;                                 // Bus interface busy with multicycle operation
-  logic                        IFUCacheBusStallF;                        // EIther I$ or bus busy with multicycle operation
-  logic                        GatedStallD;                              // StallD gated by selected next spill
-  // branch predictor signal
-  logic                        BusCommittedF;                            // Bus memory operation in flight, delay interrupts
-  logic                        CacheCommittedF;                          // I$ memory operation started, delay interrupts
-  logic                        SelIROM;                                  // PMA indicates instruction address is in the IROM
-  logic [15:0]                 InstrRawE, InstrRawM;
-  logic [LINELEN-1:0]          FetchBuffer;
-  logic [31:0]                 ShiftUncachedInstr;
-  logic 		       ITLBMissF;
-  logic 		       InstrUpdateAF;                            // ITLB hit needs to update dirty or access bits
-    
-  assign PCFExt = {2'b00, PCSpillF};
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Spill Support
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  if(P.ZCA_SUPPORTED) begin : Spill
-    spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,  .CacheableF, 
-      .IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
-  end else begin : NoSpill
-    assign PCSpillNextF = PCNextF;
-    assign PCSpillF = PCF;
-    assign PostSpillInstrRawF = InstrRawF;
-    assign {SelSpillNextF, CompressedF} = '0;
-  end
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  // Memory management
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-
-  if(P.ZICSR_SUPPORTED == 1) begin : immu
-    ///////////////////////////////////////////
-    // sfence.vma causes TLB flushes
-    ///////////////////////////////////////////
-    // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
-    // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
-    // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and 
-    // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush 
-    // after a cycle AND pulse it for another cycle on any further back-to-back sfences. 
-    logic StallMQ, TLBFlush;
-    flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
-    assign TLBFlush = sfencevmaM & ~StallMQ;
-
-    mmu #(.P(P), .TLB_ENTRIES(P.ITLB_ENTRIES), .IMMU(1))
-    immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-         .PrivilegeModeW, .DisableTranslation(1'b0),
-         .VAdr(PCFExt),
-         .Size(2'b10),
-         .PTE(PTE),
-         .PageTypeWriteVal(PageType),
-         .TLBWrite(ITLBWriteF),
-         .TLBFlush,
-         .PhysicalAddress(PCPF),
-         .TLBMiss(ITLBMissF),
-         .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
-         .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
-         .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
-         .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
-         .UpdateDA(InstrUpdateAF), .CMOpM(4'b0),
-         .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
-         .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
-
-     assign ITLBMissOrUpdateAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateAF);  
-  end else begin
-    assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateAF} = '0;
-    assign PCPF = PCFExt[P.PA_BITS-1:0];
-    assign CacheableF = 1'b1;
-    assign SelIROM = '0;
-    assign ITLBMissOrUpdateAF = '0;
-  end
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  // Memory 
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  
-  // CommittedM tells the CPU's privileged unit the current instruction
-  // in the memory stage is a memory operaton and that memory operation is either completed
-  // or is partially executed. Partially completed memory operations need to prevent an interrupts.
-  // There is not a clean way to restore back to a partial executed instruction.  CommiteedM will
-  // delay the interrupt until the LSU is in a clean state.
-  assign CommittedF = CacheCommittedF | BusCommittedF;
-
-  // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
-  if (P.IROM_SUPPORTED) begin : irom
-    logic IROMce;
-    assign IROMce = ~GatedStallD | reset;
-    assign IFURWF = 2'b10;
-    irom #(P) irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF);
-  end else begin
-    assign IFURWF = 2'b10;
-    assign IROMInstrF = '0;
-  end
-  if (P.BUS_SUPPORTED) begin : bus
-    localparam   BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1;
-    localparam   AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1;
-    
-    if(P.ICACHE_SUPPORTED) begin : icache
-      localparam            LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
-      logic [P.PA_BITS-1:0] ICacheBusAdr;
-      logic                 ICacheBusAck;
-      logic [1:0]           CacheBusRW, BusRW, CacheRWF;
-      
-      assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
-      assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS),
-              .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
-              .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
-      icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
-             .FetchBuffer, .CacheBusAck(ICacheBusAck),
-             .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
-             .CacheBusRW,
-             .ReadDataWord(ICacheInstrF),
-             .SelHPTW('0),
-             .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
-             .ByteMask('0), .BeatCount('0), .SelBusBeat('0),
-             .WriteData('0),
-             .CacheRW(CacheRWF),
-             .FlushCache('0),
-             .NextSet(PCSpillNextF[11:0]),
-             .PAdr(PCPF),
-             .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); 
-
-      ahbcacheinterface #(P, BEATSPERLINE, AHBWLOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
-      ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
-            .HRDATA,
-            .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
-            .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr),
-            .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .BusAtomic('0),
-            .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0),
-            .FetchBuffer, .PAdr(PCPF),
-            .BusRW, .Stall(GatedStallD),
-            .BusStall, .BusCommitted(BusCommittedF));
-
-      mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(ShiftUncachedInstr), .d2(IROMInstrF),
-                                 .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
-    end else begin : passthrough
-      assign IFUHADDR = PCPF;
-      logic [1:0] BusRW;
-      assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : 0;
-      assign IFUHSIZE = 3'b010;
-
-      ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
-        .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
-        .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
-        .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
-
-      assign CacheCommittedF = '0;
-      if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawF);
-      else assign InstrRawF = ShiftUncachedInstr;
-      assign IFUHBURST = 3'b0;
-      assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
-    end
-
-    // mux between the alignments of uncached reads.
-    if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], 
-                                                      FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
-                                                      PCSpillF[2:1], ShiftUncachedInstr);
-    else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
-  end else begin : nobus // block: bus
-    assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS, 
-            BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;   
-    assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
-    assign InstrRawF = IROMInstrF;
-  end
-  
-  assign IFUCacheBusStallF = ICacheStallF | BusStall;
-  assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
-  assign GatedStallD = StallD & ~SelSpillNextF;
-  
-  flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  // PCNextF logic
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-
-  if(P.ZICSR_SUPPORTED | P.ZIFENCEI_SUPPORTED)
-    mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
-  else assign PC2NextF = PC1NextF;
-
-  mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
-  mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
-  flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
-
-  // pcadder
-  // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
-  assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
-
-  if (P.ZCA_SUPPORTED) begin: pcadd
-    // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
-    // Speeds up critical path as compared to selecting adder input based on CompressedF
-    always_comb
-      if (CompressedF) // add 2
-        if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
-        else        PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
-      else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
-  end else begin: pcadd
-    assign PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // always add 4 if compressed instructions are not supported
-  end
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  // Branch and Jump Predictor
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  if (P.BPRED_SUPPORTED) begin : bpred
-    bpred #(P) bpred(.clk, .reset,
-                .StallF, .StallD, .StallE, .StallM, .StallW,
-                .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
-                .BranchD, .BranchE, .JumpD, .JumpE,
-                .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
-                .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
-
-  end else begin : bpred
-    mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
-    logic BranchM, JumpM, BranchW, JumpW;
-    logic CallD, CallE, CallM, CallW;
-    logic ReturnD, ReturnE, ReturnM, ReturnW;
-    assign BPWrongE = PCSrcE;
-    icpred #(P, 0) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, 
-      .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
-      .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, 
-      .BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0),
-      .BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM,
-      .BPReturnWrongD());
-    flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM);
-    assign RASPredPCWrongM = 1'b0;
-    assign BPDirWrongM = BPWrongM;
-    assign BTAWrongM = BPWrongM;
-    assign IClassM = {CallM, ReturnM, JumpM, BranchM};
-    assign NextValidPCE = PCE;
-  end      
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  // Decode stage pipeline register and compressed instruction decoding.
-  ////////////////////////////////////////////////////////////////////////////////////////////////
-  
-  // Decode stage pipeline register and logic
-  flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
-   
-  // expand 16-bit compressed instructions to 32 bits
-  if (P.ZCA_SUPPORTED) begin: decomp
-    logic IllegalCompInstrD;
-    decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
-    assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
-  end else begin: decomp
-    assign InstrD = InstrRawD;
-    assign IllegalIEUInstrD = IllegalBaseInstrD;
-  end
-  assign IllegalIEUFPUInstrD = IllegalIEUInstrD & (IllegalFPUInstrD | !P.F_SUPPORTED);
-
-  // Misaligned PC logic
-  // Instruction address misalignment only from br/jal(r) instructions.
-  // instruction address misalignment is generated by the target of control flow instructions, not
-  // the fetch itself.
-  // xret and Traps both cannot produce instruction misaligned.
-  // xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21. 
-  // The low bit of mepc (mepc[0]) is always zero. On implementations that support
-  // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
-  // Spec 3.1.14
-  // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
-  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.ZCA_SUPPORTED) & PCSrcE;
-  flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
-
-  // Instruction and PC pipeline registers flush to NOP, not zero
-  mux2    #(32)     FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
-  flopenr #(32)     InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
-  flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
-
-  // InstrM is only needed with CSRs or atomic operations
-  if (P.ZICSR_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin
-    mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
-    flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
-  end else assign InstrM = '0;
-  // PCM is only needed with CSRs or branch prediction
-  if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) 
-    flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  else assign PCM = '0; 
-  
-  // If compressed instructions are supported, increment PCLink by 2 or 4 for a jal.  Otherwise, just by 4
-  if (P.ZCA_SUPPORTED) begin
-    logic CompressedD;  // instruction is compressed
-    flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
-    flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
-    assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
-  end else begin
-    assign CompressedE = 1'b0;
-    assign PCLinkE = PCE + 'd4;
-  end
- 
-  // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
-    logic CompressedM; // instruction is compressed
-    flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
-    flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-    flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
-    mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
-  end else
-    assign InstrOrigM = InstrM;
-
-endmodule
diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv
deleted file mode 100644
index f85b60a5d..000000000
--- a/src/ifu/irom.sv
+++ /dev/null
@@ -1,60 +0,0 @@
-///////////////////////////////////////////
-// irom.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 30 January 2022
-// Modified: 18 January 2023
-//
-// Purpose: simple instruction ROM
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module irom import cvw::*;  #(parameter cvw_t P) (
-  input logic              clk, 
-  input logic              ce,        // Chip Enable.  0: Holds IROMInstrF constant
-  input logic [P.XLEN-1:0] Adr,       // PCNextFSpill
-  output logic [31:0]      IROMInstrF // Instruction read data
-);
-
-  localparam XLENBYTES = {{P.PA_BITS-32{1'b0}}, P.XLEN/8}; // XLEN/8, adjusted for width
-  localparam ADDR_WDITH = $clog2(P.IROM_RANGE[P.PA_BITS-1:0]/XLENBYTES); 
-  localparam OFFSET = $clog2(XLENBYTES);
-
-  logic [P.XLEN-1:0] IROMInstrFFull;
-  logic [31:0]       RawIROMInstrF;
-  logic [2:1]        AdrD;
-
-  // preload IROM with the FPGA bootloader by default so that it syntehsizes to something, avoiding having the IEU optimized away because instructions are all 0
-  // the testbench replaces these dummy contents with the actual program of interest during simulation
-  rom1p1r #(ADDR_WDITH, P.XLEN, 1) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
-  if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
-  else              begin
-  // IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two
-  // haves.  Adr is the Next PCF not PCF so we delay 1 cycle.
-    flopen #(1) AdrReg2(clk, ce, Adr[2], AdrD[2]);
-    assign RawIROMInstrF = AdrD[2] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
-  end
-  // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
-  // The spill logic will handle merging the two together.
-  if (P.ZCA_SUPPORTED) begin
-    flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
-    assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
-  end else
-    assign IROMInstrF = RawIROMInstrF;
-endmodule  
diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
deleted file mode 100644
index f073398f3..000000000
--- a/src/ifu/spill.sv
+++ /dev/null
@@ -1,124 +0,0 @@
-///////////////////////////////////////////
-// spill.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 28 January 2022
-// Modified: 19 January 2023
-//
-// Purpose: allows the IFU to make extra memory request if instruction address crosses
-//          cache line boundaries or if instruction address without a cache crosses
-//          XLEN/8 boundary.
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module spill import cvw::*;  #(parameter cvw_t P) (
-  input logic               clk,               
-  input logic               reset,
-  input logic               StallF, FlushD,
-  input logic [P.XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
-  input logic [P.XLEN-1:2]  PCPlus4F,          // PCF + 4
-  input logic [P.XLEN-1:0]  PCNextF,           // The next PCF
-  input logic [31:0]        InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
-  input logic               IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic               ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
-  input logic               CacheableF,        // Is the instruction from the cache?
-  output logic [P.XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
-  output logic [P.XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
-  output logic              SelSpillNextF,     // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic [31:0]       PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
-  output logic              CompressedF);      // The fetched instruction is compressed
-
-  // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
-  typedef enum logic [1:0]  {STATE_READY, STATE_SPILL} statetype;
-
-  statetype          CurrState, NextState;
-  logic [P.XLEN-1:0] PCPlus2NextF, PCPlus2F;         
-  logic              TakeSpillF;
-  logic              SpillF;
-  logic              SelSpillF;
-  logic              SpillSaveF;
-  logic [15:0]       InstrFirstHalfF;
-  logic              EarlyCompressedF;
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // PC logic 
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  
-  // compute PCF+2 from the raw PC+4
-  mux2 #(P.XLEN) pcplus2mux(.d0({PCF[P.XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2NextF));
-  // select between PCNextF and PCF+2
-  mux2 #(P.XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2NextF), .s(SelSpillNextF & ~FlushD), .y(PCSpillNextF));
-  // select between PCF and PCF+2
-  // not required for functional correctness, but improves critical path.  pcspillf ends up on the hptw's ihadr 
-  // and into the dmmu.  Cutting the path here removes the PC+4 adder.
-  flopr #(P.XLEN) pcplus2reg(clk, reset, PCPlus2NextF, PCPlus2F);
-  mux2 #(P.XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCSpillF));
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Detect spill
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  if (P.ICACHE_SUPPORTED) begin
-    logic SpillCachedF, SpillUncachedF;
-    assign SpillCachedF = &PCF[$clog2(P.ICACHE_LINELENINBITS/32)+1:1];
-    assign SpillUncachedF = PCF[1]; 
-    assign SpillF = (CacheableF ? SpillCachedF : SpillUncachedF);
-  end else
-    assign SpillF = PCF[1];
-  // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
-  assign TakeSpillF = SpillF & ~EarlyCompressedF & ~IFUCacheBusStallF & ~ITLBMissOrUpdateAF;
-  
-  always_ff @(posedge clk)
-    if (reset | FlushD)    CurrState <= STATE_READY;
-    else CurrState <= NextState;
-
-  always_comb begin
-    case (CurrState)
-      STATE_READY: if (TakeSpillF)                NextState = STATE_SPILL;
-                   else                           NextState = STATE_READY;
-      STATE_SPILL: if(StallF)                     NextState = STATE_SPILL;
-                   else                           NextState = STATE_READY;
-      default:                                    NextState = STATE_READY;
-    endcase
-  end
-
-  assign SelSpillF = (CurrState == STATE_SPILL);
-  assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallF);
-  assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Merge spilled instruction
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  // save the first 2 bytes
-  flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalfF);
-
-  // merge together
-  mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalfF}, SelSpillF, PostSpillInstrRawF);
-
-  // Need to use always comb to avoid pessimistic x propagation if PostSpillInstrRawF is x
-  always_comb
-  if (PostSpillInstrRawF[1:0] != 2'b11) CompressedF = 1'b1;
-  else CompressedF = 1'b0;
-  assign EarlyCompressedF = ~(&InstrRawF[1:0]);
-
-endmodule
diff --git a/src/lsu/align.sv b/src/lsu/align.sv
deleted file mode 100644
index b6bae2918..000000000
--- a/src/lsu/align.sv
+++ /dev/null
@@ -1,171 +0,0 @@
-///////////////////////////////////////////
-// spill.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 26 October 2023
-// Modified: 26 October 2023
-//
-// Purpose: This module implements native alignment support for the Zicclsm extension
-//          It is simlar to the IFU's spill module and probably could be merged together with 
-//          some effort.
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module align import cvw::*;  #(parameter cvw_t P) (
-  input logic                     clk, 
-  input logic                     reset,
-  input logic                     StallM, FlushM,
-  input logic [P.XLEN-1:0]        IEUAdrM, // 2 byte aligned PC in Fetch stage
-  input logic [P.XLEN-1:0]        IEUAdrE, // The next IEUAdrM
-  input logic [2:0]               Funct3M, // Size of memory operation
-  input logic                     FpLoadStoreM, // Floating point Load or Store 
-  input logic [1:0]               MemRWM, 
-  input logic [P.LLEN*2-1:0]      DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
-  input logic                     CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic                     SelHPTW,
-
-  input logic [(P.LLEN-1)/8:0]    ByteMaskM,
-  input logic [(P.LLEN-1)/8:0]    ByteMaskExtendedM,
-  input logic [P.LLEN-1:0]        LSUWriteDataM, 
-
-  output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM,
-  output logic [P.LLEN*2-1:0]     LSUWriteDataSpillM, 
-
-  output logic [P.XLEN-1:0]       IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
-  output logic [P.XLEN-1:0]       IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
-  output logic                    SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
-  output logic [P.LLEN-1:0]       DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction
-  output logic                    SpillStallM);
-
-  localparam LLENINBYTES = P.LLEN/8;
-  localparam OFFSET_BIT_POS =  $clog2(P.DCACHE_LINELENINBITS/8);
-  // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
-  typedef enum logic [1:0]  {STATE_READY, STATE_SPILL, STATE_STORE_DELAY} statetype;
-
-  statetype          CurrState, NextState;
-  logic              ValidSpillM;
-  logic              SelSpillM;
-  logic              SpillSaveM;
-  logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
-  logic              MisalignedM;
-  logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
-  logic [P.LLEN*2-1:0] ReadDataWordSpillShiftedM;
-
-  logic [P.XLEN-1:0]   IEUAdrIncrementM;
-
-  localparam OFFSET_LEN = $clog2(LLENINBYTES);
-  logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
-  logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
-  logic                                        PotentialSpillM;
-  logic [P.LLEN*3-1:0]                         LSUWriteDataShiftedExtM; 
-
-
-  /* verilator lint_off WIDTHEXPAND */
-  assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
-  /* verilator lint_on WIDTHEXPAND */
-  mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE));
-  mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM));
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Detect spill
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  // spill detection in lsu is more complex than ifu, depends on 3 factors
-  // 1) operation size
-  // 2) offset
-  // 3) access location within the cacheline
-  
-  // compute misalignement
-  always_comb begin
-    case (Funct3M & {FpLoadStoreM, 2'b11}) 
-      3'b000: AccessByteOffsetM = '0; // byte access
-      3'b001: AccessByteOffsetM = {{OFFSET_LEN-1{1'b0}}, IEUAdrM[0]}; // half access
-      3'b010: AccessByteOffsetM = {{OFFSET_LEN-2{1'b0}}, IEUAdrM[1:0]}; // word access
-      3'b011: if(P.LLEN >= 64) AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access
-              else             AccessByteOffsetM = '0;                                    // shouldn't happen
-      // coverage off
-      // RV64GC doesn't support Q
-      3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access
-              else              AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0];
-      // coverage on
-      default: AccessByteOffsetM = '0;                                        // shouldn't happen
-    endcase
-    case (Funct3M[1:0]) 
-      2'b00: PotentialSpillM = 1'b0; // byte access
-      2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access
-      2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access
-      2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access
-      default: PotentialSpillM = 1'b0;
-    endcase
-  end
-  assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != 0);
-      
-  assign ValidSpillM = MisalignedM & PotentialSpillM & ~CacheBusHPWTStall;   // Don't take the spill if there is a stall
-  
-  always_ff @(posedge clk)
-    if (reset | FlushM)    CurrState <= STATE_READY;
-    else CurrState <= NextState;
-
-  always_comb begin
-    case (CurrState)
-      STATE_READY: if (ValidSpillM)  NextState = STATE_SPILL;       // load spill
-                   else                           NextState = STATE_READY;       // no spill
-      STATE_SPILL: if(StallM)                     NextState = STATE_SPILL;
-                   else                           NextState = STATE_READY;
-      default:                                    NextState = STATE_READY;
-    endcase
-  end
-
-  assign SelSpillM = CurrState == STATE_SPILL;
-  assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall);
-  assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
-  assign SpillStallM = SelSpillE;
-
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-  // Merge spilled data
-  ////////////////////////////////////////////////////////////////////////////////////////////////////
-
-  // save the first native word
-  flopenr #(P.LLEN) SpillDataReg(clk, reset, SpillSaveM, DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM);
-
-  // merge together
-  mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM, ReadDataWordSpillAllM);
-
-
-  // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
-  // 8 * is for shifting by bytes not bits
-  assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate
-  assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
-  assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
-
-  // write path. 
-  // 3*LLEN to 2*LLEN funnel shifter to perform left rotation.
-  // Vivado correctly optimizes as 2*LLEN log2(LLEN):1 muxes
-  assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
-  assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
-
-  mux3 #(2*P.LLEN/8) bytemaskspillmux({ByteMaskExtendedM, ByteMaskM}, // no spill
-                                      {{{P.LLEN/8}{1'b0}}, ByteMaskM}, // spill, first half
-                                      {{{P.LLEN/8}{1'b0}}, ByteMaskExtendedM}, // spill, second half
-                                      {SelSpillM, SelSpillE}, ByteMaskSpillM);
-
-endmodule
diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv
deleted file mode 100644
index bc8a29471..000000000
--- a/src/lsu/amoalu.sv
+++ /dev/null
@@ -1,90 +0,0 @@
-///////////////////////////////////////////
-// amoalu.sv
-//
-// Written: David_Harris@hmc.edu
-// Created: 10 March 2021
-// Modified: 18 January 2023 
-//
-// Purpose: Performs AMO operations
-// 
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module amoalu import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.XLEN-1:0] ReadDataM,    // LSU's ReadData
-  input  logic [P.XLEN-1:0] IHWriteDataM, // LSU's WriteData
-  input  logic [6:0]        LSUFunct7M,   // ALU Operation
-  input  logic [2:0]        LSUFunct3M,   // Memoy access width
-  output logic [P.XLEN-1:0] AMOResultM    // ALU output
-);
-
-  logic [P.XLEN-1:0] a, b, y;
-  logic               lt, cmp, sngd, sngd32, eq32, lt32, w64;
-
-  // Rename inputs
-  assign a = ReadDataM;
-  assign b = IHWriteDataM;
-
-  // Share hardware among the four amomin/amomax comparators
-  assign sngd = ~LSUFunct7M[5]; // Funct7[5] = 0 for signed amomin/max
-  assign w64 = (LSUFunct3M[1:0] == 2'b10); // operate on bottom 32 bits
-  assign sngd32 = sngd & (P.XLEN == 32 | w64); // flip sign in lower 32 bits on 32-bit comparisons only
-
-  comparator #(32) cmp32(a[31:0], b[31:0], sngd32, {eq32, lt32});
-  if (P.XLEN == 32) begin
-    assign lt = lt32;
-  end else begin
-    logic equpper, ltupper, lt64;
-
-    comparator #(32) cmpupper(a[63:32], b[63:32], sngd, {equpper, ltupper});
-    assign lt64 = ltupper | equpper & lt32;
-    assign lt = w64 ? lt32 : lt64;
-  end
-
-  assign cmp = lt ^ LSUFunct7M[4]; // flip sense of comparison for maximums
-
-  // AMO ALU
-  always_comb 
-    case (LSUFunct7M[6:2])
-      5'b00001: y = b;           // amoswap
-      5'b00000: y = a + b;       // amoadd
-      5'b00100: y = a ^ b;       // amoxor
-      5'b01100: y = a & b;       // amoand
-      5'b01000: y = a | b;       // amoor
-      5'b10000: y = cmp ? a : b; // amomin
-      5'b10100: y = cmp ? a : b; // amomax
-      5'b11000: y = cmp ? a : b; // amominu
-      5'b11100: y = cmp ? a : b; // amomaxu
-      default:  y = 'x;          // undefined
-    endcase
-
-  // sign extend output if necessary for w64
-  if (P.XLEN == 32) begin:sext
-    assign AMOResultM = y;
-  end else begin:sext // P.XLEN = 64
-    always_comb 
-      if (w64) begin // sign-extend word-length operations
-        AMOResultM = {{32{y[31]}}, y[31:0]};
-      end else begin
-        AMOResultM = y;
-      end
-  end
-endmodule
diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
deleted file mode 100644
index cd87d70ac..000000000
--- a/src/lsu/atomic.sv
+++ /dev/null
@@ -1,67 +0,0 @@
-///////////////////////////////////////////
-// atomic.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 31 January 2022
-// Modified: 18 January 2023
-//
-// Purpose: Wrapper for amoalu and lrsc
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module atomic import cvw::*;  #(parameter cvw_t P) (
-  input logic                 clk,
-  input logic                 reset, 
-  input logic                 StallW,
-  input logic [P.XLEN-1:0]    ReadDataM,      // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [P.XLEN-1:0]    IHWriteDataM,   // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
-  input logic [P.PA_BITS-1:0] PAdrM,          // Physical memory address
-  input logic [6:0]           LSUFunct7M,     // AMO alu operation gated by HPTW
-  input logic [2:0]           LSUFunct3M,     // IEU or HPTW memory operation size
-  input logic [1:0]           LSUAtomicM,     // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
-  input logic [1:0]           PreLSURWM,      // IEU or HPTW Read/Write signal
-  input logic                 LSUFlushW,  // On FlushM or TLB miss ignore memory operation
-  output logic [P.XLEN-1:0]   IMAWriteDataM,  // IEU, HPTW, or AMO write data
-  output logic                SquashSCW,      // Store conditional failed disable write to GPR
-  output logic [1:0]          LSURWM          // IEU or HPTW Read/Write signal gated by LR/SC
-);
-
-  logic [P.XLEN-1:0]          AMOResultM;
-  logic                       MemReadM;
-
-  // AMO ALU
-  if (P.ZAAMO_SUPPORTED) begin
-    amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
-    mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
-  end else 
-    assign IMAWriteDataM = IHWriteDataM;
-  
-  // LRSC unit
-  if (P.ZALRSC_SUPPORTED) begin
-    assign MemReadM = PreLSURWM[1] & ~LSUFlushW;
-    lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
-  end else begin
-    assign SquashSCW = 0;
-    assign LSURWM = PreLSURWM;
-  end
-
-endmodule  
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
deleted file mode 100644
index 20d3cb8f6..000000000
--- a/src/lsu/lrsc.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-///////////////////////////////////////////
-// lrsc.sv
-//
-// Written: David_Harris@hmc.edu
-// Created: 17 July 2021
-// Modified: 18 January 2023
-//
-// Purpose: Load Reserved / Store Conditional unit
-//          Track the reservation and squash the store if it fails
-//
-// Documentation: RISC-V System on Chip Design
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module lrsc import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 clk, 
-  input  logic                 reset,
-  input  logic                 StallW,
-  input  logic                 MemReadM,   // Memory read
-  input  logic [1:0]           PreLSURWM,  // Memory operation from the HPTW or IEU [1]: read, [0]: write
-  output logic [1:0]           LSURWM,     // Memory operation after potential squash of SC
-  input  logic [1:0]           LSUAtomicM, // Atomic memory operaiton
-  input  logic [P.PA_BITS-1:0] PAdrM,      // Physical memory address 
-  output logic                 SquashSCW   // Squash the store conditional by not allowing rf write
-);
-
-  // reservation set size is XLEN for Wally
-  localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
-  localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
-
-  // Handle atomic load reserved / store conditional
-  logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS]        ReservationPAdrW;
-  logic                        ReservationValidM, ReservationValidW; 
-  logic                        lrM, scM, WriteAdrMatchM;
-  logic                        SquashSCM;
-
-  assign lrM = MemReadM & LSUAtomicM[0];
-  assign scM = PreLSURWM[0] & LSUAtomicM[0]; 
-  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] == ReservationPAdrW) & ReservationValidW;
-  assign SquashSCM = scM & ~WriteAdrMatchM;
-  assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
-  always_comb begin // ReservationValidM (next value of valid reservation)
-    if (lrM) ReservationValidM = 1'b1;  // set valid on load reserve
-  // if we implement multiple harts invalidate reservation if another hart stores to this reservation.
-    else if (scM) ReservationValidM = 1'b0; // clear valid on store to same address or any sc
-    else ReservationValidM = ReservationValidW; // otherwise don't change valid
-  end
-  
-  flopenr #(P.PA_BITS-RESERVATION_SET_ADDRESS_BITS) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS], ReservationPAdrW); // could drop clear on this one but not valid
-  flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
-  flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
-endmodule
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
deleted file mode 100644
index f6a215a27..000000000
--- a/src/lsu/lsu.sv
+++ /dev/null
@@ -1,433 +0,0 @@
-/////////////////////////////////////////////////////////////////////////////////////////////////////////
-// lsu.sv
-//
-// Written: David_Harris@hmc.edu, rose@rosethompson.net
-// Created: 9 January 2021
-// Modified: 11 January 2023 
-//
-// Purpose: Load/Store Unit 
-//          HPTW, DMMU, data cache, interface to external bus
-//          Atomic, Endian swap, and subword read/write logic
-//  
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-/////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module lsu import cvw::*;  #(parameter cvw_t P) (
-  input  logic                    clk, reset,
-  input  logic                    StallM, FlushM, StallW, FlushW,
-  output logic                    LSUStallM,                            // LSU stalls pipeline during a multicycle operation
-  // connected to cpu (controls)
-  input  logic [1:0]              MemRWE,                               // Read/Write control
-  input  logic [1:0]              MemRWM,                               // Read/Write control
-  input  logic [2:0]              Funct3M,                              // Size of memory operation
-  input  logic [6:0]              Funct7M,                              // Atomic memory operation function
-  input  logic [1:0]              AtomicM,                              // Atomic memory operation
-  input  logic                    FlushDCacheM,                         // Flush D cache to next level of memory
-  input  logic [3:0]              CMOpM,                                // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  input  logic                    LSUPrefetchM,                         // Prefetch; presently unused
-  output logic                    CommittedM,                           // Delay interrupts while memory operation in flight
-  output logic                    SquashSCW,                            // Store conditional failed disable write to GPR
-  output logic                    DCacheMiss,                           // D cache miss for performance counters
-  output logic                    DCacheAccess,                         // D cache memory access for performance counters
-  // address and write data
-  input  logic [P.XLEN-1:0]       IEUAdrE,                              // Execution stage memory address
-  output logic [P.XLEN-1:0]       IEUAdrM,                              // Memory stage memory address
-  input  logic [P.XLEN-1:0]       WriteDataM,                           // Write data from IEU
-  output logic [P.LLEN-1:0]       ReadDataW,                            // Read data to IEU or FPU
-  // cpu privilege
-  input  logic [1:0]              PrivilegeModeW,                       // Current privilege mode
-  input  logic                    BigEndianM,                           // Swap byte order to big endian
-  input  logic                    sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
-  output logic                    DCacheStallM,                         // D$ busy with multicycle operation
-  // fpu
-  input  logic [P.FLEN-1:0]       FWriteDataM,                          // Write data from FPU
-  input  logic                    FpLoadStoreM,                         // Selects FPU as store for write data
-  // faults
-  output logic                    LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
-  output logic                    LoadMisalignedFaultM,                 // Load address misaligned fault
-  output logic                    LoadAccessFaultM,                     // Load access fault (PMA)
-  output logic                    HPTWInstrAccessFaultF,                // HPTW generated access fault during instruction fetch
-  output logic                    HPTWInstrPageFaultF,                  // HPTW generated access fault during instruction fetch
-  // cpu hazard unit (trap)
-  output logic                    StoreAmoMisalignedFaultM,             // Store or AMO address misaligned fault
-  output logic                    StoreAmoAccessFaultM,                 // Store or AMO access fault
-  // connect to ahb
-  output logic [P.PA_BITS-1:0]    LSUHADDR,                             // Bus address from LSU to EBU
-  input  logic [P.XLEN-1:0]       HRDATA,                               // Bus read data from LSU to EBU
-  output logic [P.XLEN-1:0]       LSUHWDATA,                            // Bus write data from LSU to EBU
-  input  logic                    LSUHREADY,                            // Bus ready from LSU to EBU
-  output logic                    LSUHWRITE,                            // Bus write operation from LSU to EBU
-  output logic [2:0]              LSUHSIZE,                             // Bus operation size from LSU to EBU
-  output logic [2:0]              LSUHBURST,                            // Bus burst from LSU to EBU
-  output logic [1:0]              LSUHTRANS,                            // Bus transaction type from LSU to EBU
-  output logic [P.XLEN/8-1:0]     LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
-  // page table walker
-  input  logic [P.XLEN-1:0]       SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
-  input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,  // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
-  input  logic [1:0]              STATUS_MPP,                           // Machine previous privilege mode
-  input  logic                    ENVCFG_PBMTE,                         // Page-based memory types enabled
-  input  logic                    ENVCFG_ADUE,                          // HPTW A/D Update enable
-  input  logic [P.XLEN-1:0]       PCSpillF,                             // Fetch PC 
-  input  logic                    ITLBMissOrUpdateAF,                   // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
-  output logic [P.XLEN-1:0]       PTE,                                  // Page table entry write to ITLB
-  output logic [1:0]              PageType,                             // Type of page table entry to write to ITLB
-  output logic                    ITLBWriteF,                           // Write PTE to ITLB
-  output logic                    SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
-  input var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
-  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
-);
-  localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
-  localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
-
-  logic [P.XLEN+1:0]     IEUAdrExtM;                             // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [P.XLEN+1:0]     IEUAdrExtE;                             // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
-  logic [P.PA_BITS-1:0]  PAdrM;                                  // Physical memory address
-  logic [P.XLEN+1:0]     IHAdrM;                                 // Either IEU or HPTW memory address
-
-  logic [1:0]            PreLSURWM;                              // IEU or HPTW Read/Write signal
-  logic [1:0]            LSURWM;                                 // IEU or HPTW Read/Write signal gated by LR/SC
-  logic [2:0]            LSUFunct3M;                             // IEU or HPTW memory operation size
-  logic [6:0]            LSUFunct7M;                             // AMO function gated by HPTW
-  logic [1:0]            LSUAtomicM;                             // AMO signal gated by HPTW
-
-  logic                  GatedStallW;                            // Hazard unit StallW gated when SelHPTW = 1
-  
-  logic                  LSUBusStallM;                           // Bus interface busy with multicycle operation masked by HPTWFlushW
-  logic                  HPTWStall;                              // HPTW busy with multicycle operation
-  logic                  DCacheBusStallM;                        // Cache or bus stall
-  logic                  CacheBusHPWTStall;                      // Cache, bus, or hptw is requesting a stall
-  logic                  SelSpillE;                              // Align logic detected a spill and needs to stall
-
-  logic                  CacheableM;                             // PMA indicates memory address is cacheable
-  logic                  BusCommittedM;                          // Bus memory operation in flight, delay interrupts
-  logic                  DCacheCommittedM;                       // D$ memory operation started, delay interrupts
-
-  logic [P.LLEN-1:0]     DTIMReadDataWordM;                      // DTIM read data
-  logic [MLEN-1:0]       DCacheReadDataWordM;                    // D$ read data
-  logic [MLEN-1:0]       LSUWriteDataSpillM;                     // Final write data
-  logic [MLEN/8-1:0]     ByteMaskSpillM;                         // Selects which bytes within a word to write
-  logic [P.LLEN-1:0]     DCacheReadDataWordSpillM;               // D$ read data
-  logic [P.LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
-  logic [P.LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
-  logic [P.LLEN-1:0]     ReadDataM;                              // Final read data
-
-  logic [P.XLEN-1:0]     IHWriteDataM;                           // IEU or HPTW write data
-  logic [P.XLEN-1:0]     IMAWriteDataM;                          // IEU, HPTW, or AMO write data
-  logic [P.LLEN-1:0]     IMAFWriteDataM;                         // IEU, HPTW, AMO, or FPU write data
-  logic [P.LLEN-1:0]     LittleEndianWriteDataM;                 // Ending-swapped write data 
-  logic [P.LLEN-1:0]     LSUWriteDataM;                          // Final write data
-  logic [(P.LLEN-1)/8:0] ByteMaskM;                              // Selects which bytes within a word to write
-  logic [(P.LLEN-1)/8:0] ByteMaskExtendedM;                      // Selects which bytes within a word to write
-  logic [1:0]            MemRWSpillM;
-  logic                  SpillStallM;
-  
-  logic                  DTLBMissM;                              // DTLB miss causes HPTW walk
-  logic                  DTLBWriteM;                             // Writes PTE and PageType to DTLB
-  logic                  LSULoadAccessFaultM;                    // Load acces fault
-  logic                  LSUStoreAmoAccessFaultM;                // Store access fault
-  logic                  HPTWFlushW;                             // HPTW needs to flush operation
-  logic                  LSUFlushW;                              // HPTW or hazard unit flushes operation
-  logic                  SelDTIM;                                // Select DTIM rather than bus or D$
-  logic [P.XLEN-1:0]     WriteDataZM;
-  logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
-  logic 		 DTLBMissOrUpdateDAM;
-   
-  
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Pipeline for IEUAdr E to M
-  // Zero-extend address to 34 bits for XLEN=32
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
-  if(MISALIGN_SUPPORT) begin : ziccslm_align
-    logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
-    align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, 
-                     .MemRWM,
-                     .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
-                     .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
-                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM);
-    assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; 
-    assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
-  end else begin : no_ziccslm_align
-    assign IEUAdrExtM = {2'b00, IEUAdrM}; 
-    assign IEUAdrExtE = {2'b00, IEUAdrE};
-    assign SelSpillE = 1'b0;
-    assign DCacheReadDataWordSpillM = DCacheReadDataWordM;
-    assign ByteMaskSpillM = ByteMaskM;
-    assign LSUWriteDataSpillM = LSUWriteDataM;
-    assign MemRWSpillM = MemRWM;
-    assign {SpillStallM} = 1'b0;
-  end
-
-    if(P.ZICBOZ_SUPPORTED) begin : cboz
-      assign WriteDataZM = CMOpM[3] ? 0 : WriteDataM;
-   end else begin : cboz
-      assign WriteDataZM = WriteDataM;
-    end
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // HPTW (only needed if VM supported)
-  // MMU include PMP and is needed if any privileged supported
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  if(P.VIRTMEM_SUPPORTED) begin : hptw
-    hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
-      .DTLBMissOrUpdateDAM, .DTLBWriteM,
-      .FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
-      .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
-      .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
-      .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
-      .IHAdrM, .HPTWStall, .SelHPTW, 
-      .HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, 
-      .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
-      .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
-);
-  end else begin // No HPTW, so signals are not multiplexed
-    assign PreLSURWM = MemRWM; 
-    assign IHAdrM = IEUAdrExtM;
-    assign LSUFunct3M = Funct3M;
-    assign LSUFunct7M = Funct7M; 
-    assign LSUAtomicM = AtomicM;
-    assign IHWriteDataM = WriteDataZM;
-    assign LoadAccessFaultM = LSULoadAccessFaultM;
-    assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
-    assign LoadPageFaultM = LSULoadPageFaultM;
-    assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM;
-    assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0;
-    assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0;
-   end
-
-  // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
-  // CommittedM is 1 after the first cycle and until the last cycle.  Partially completed memory 
-  // operations delay interrupts until the next instruction by suppressing pending interrupts in 
-  // the trap module.
-  assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
-  assign GatedStallW = StallW & ~SelHPTW;
-  assign DCacheBusStallM = DCacheStallM | LSUBusStallM;
-  assign CacheBusHPWTStall = DCacheBusStallM | HPTWStall;
-  assign LSUStallM = CacheBusHPWTStall | SpillStallM;
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // MMU and misalignment fault logic required if privileged unit exists
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  if(P.ZICSR_SUPPORTED == 1) begin : dmmu
-    logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
-    logic WriteAccessM;
-    logic DataUpdateDAM;                                  // DTLB hit needs to update dirty or access bits
-
-    assign DisableTranslation = SelHPTW | FlushDCacheM;
-    assign WriteAccessM = PreLSURWM[0];
-    mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
-    dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-      .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
-      .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
-      .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), 
-      .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), 
-      .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM), 
-      .StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
-      .UpdateDA(DataUpdateDAM), .CMOpM(CMOpM),
-      .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), 
-      .WriteAccessM, .ReadAccessM(PreLSURWM[1]),
-      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
-
-    assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);  
-  end else begin  // No MMU, so no PMA/page faults and no address translation
-    assign DTLBMissOrUpdateDAM = '0;
-    assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
-    assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0;
-    assign PAdrM = IHAdrM[P.PA_BITS-1:0];
-    assign CacheableM = 1'b1;
-    assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM.  If there is 
-    // a bus then this is always 0. Cannot have both without PMA.
-  end
-  
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Memory System (options)
-  // 1. DTIM
-  // 2. DTIM and bus
-  // 3. Bus
-  // 4. Cache and bus
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  // Pause IEU memory request if TLB miss.  After TLB fill, replay request.
-  // Discard memory request on pipeline flush
-  assign LSUFlushW = HPTWFlushW | FlushW;
-  
-  if (P.DTIM_SUPPORTED) begin : dtim
-    logic [P.PA_BITS-1:0] DTIMAdr;
-    logic [1:0]           DTIMMemRWM;
-    
-    // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
-    mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
-    assign DTIMMemRWM = SelDTIM ? LSURWM : 0;
-    dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW),
-              .MemRWM(DTIMMemRWM),
-              .DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM), 
-              .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
-  end else
-    assign DTIMReadDataWordM = '0;
-  if (P.BUS_SUPPORTED) begin : bus              
-    if(P.DCACHE_SUPPORTED) begin : dcache
-      localparam   LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN;             // Number of LLEN words in cacheline
-      localparam   LLENLOGBWPL = $clog2(LLENWORDSPERLINE);                       // Log2 of ^
-      localparam   BEATSPERLINE = P.DCACHE_LINELENINBITS/P.AHBW;                 // Number of AHBW words (beats) in cacheline
-      localparam   AHBWLOGBWPL = $clog2(BEATSPERLINE);                           // Log2 of ^
-      localparam   LINELEN = P.DCACHE_LINELENINBITS;                             // Number of bits in cacheline
-      localparam   LLENPOVERAHBW = P.LLEN / P.AHBW;                              // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
-      localparam   CACHEWORDLEN = P.ZICCLSM_SUPPORTED ? 2*P.LLEN : P.LLEN;       // Width of the cache's input and output data buses.  Misaligned doubles width for fast access
-
-      logic [LINELEN-1:0]      FetchBuffer;                                      // Temporary buffer to hold partially fetched cacheline
-      logic [P.PA_BITS-1:0]    DCacheBusAdr;                                     // Cacheline address to fetch or writeback.
-      logic [AHBWLOGBWPL-1:0]  BeatCount;                                        // Position within a cacheline.  ahbcacheinterface to cache
-      logic                    DCacheBusAck;                                     // ahbcacheinterface completed fetch or writeback
-      logic                    SelBusBeat;                                       // ahbcacheinterface selects postion in cacheline with BeatCount
-      logic [1:0]              CacheBusRW;                                       // Cache sends request to ahbcacheinterface
-      logic [1:0]              BusRW;                                            // Uncached bus memory access
-      logic                    CacheableOrFlushCacheM;                           // Memory address is cacheable or operation is a cache flush
-      logic [1:0]              CacheRWM;                                         // Cache read (10), write (01), AMO (11)
-      logic                    FlushDCache;                                      // Suppress d cache flush if there is an ITLB miss.
-      logic                    BusCMOZero;
-      logic [3:0]              CacheCMOpM;
-      logic                    BusAtomic;
-
-      if(P.ZICBOZ_SUPPORTED) begin 
-        assign BusCMOZero = CMOpM[3] & ~CacheableM;
-        assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0;
-        assign BusAtomic = AtomicM[1] & ~CacheableM;
-      end else begin
-        assign BusCMOZero = 1'b0;
-        assign CacheCMOpM = '0;
-        assign BusAtomic = 1'b0;
-      end
-      assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : '0;
-      assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
-      assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
-      assign FlushDCache = FlushDCacheM & ~(SelHPTW);
-      
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
-              .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
-        .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
-        .CacheRW(CacheRWM), 
-        .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), 
-        .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
-        .WriteData(LSUWriteDataSpillM), .SelHPTW,
-        .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
-        .CacheCommitted(DCacheCommittedM), 
-        .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), 
-        .FetchBuffer, .CacheBusRW(CacheBusRW), 
-        .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM));
-
-      ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN),  .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
-        .HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW),
-        .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
-        .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY),
-        .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM),
-        .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .BusAtomic, .BusCMOZero, .CacheableOrFlushCacheM,
-        .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM),
-        .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
-        .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM));
-
-      mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
-                                    .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
-                                    .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
-    end else begin : passthrough // No Cache, use simple ahbinterface instad of ahbcacheinterface
-      logic [1:0] BusRW;                    // Non-DTIM memory access, ignore cacheableM
-      logic [P.XLEN-1:0] FetchBuffer;
-      assign BusRW = ~SelDTIM ? LSURWM : 0;
-      
-      assign LSUHADDR = PAdrM;
-      assign LSUHSIZE = LSUFunct3M;
-
-      ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY), 
-        .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
-        .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
-        .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
-
-    // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
-      if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
-      else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0];
-      assign LSUHBURST = 3'b0;
-      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
-    end
-  end else begin: nobus // block: bus, only DTIM
-    assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; 
-    assign DCacheReadDataWordM = '0;
-    assign ReadDataWordMuxM = DTIMReadDataWordM;
-    assign {LSUBusStallM, BusCommittedM} = '0;   
-    assign {DCacheMiss, DCacheAccess} = '0;
-    assign {DCacheStallM, DCacheCommittedM} = '0;
-  end
-  
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Atomic operations
-  /////////////////////////////////////////////////////////////////////////////////////////////
- 
-  if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
-    atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
-      .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW, 
-      .IMAWriteDataM, .SquashSCW, .LSURWM);
-  end else begin:lrsc
-    assign SquashSCW = 1'b0; 
-    assign LSURWM = PreLSURWM; 
-    assign IMAWriteDataM = IHWriteDataM;
-  end
-
-  if (P.F_SUPPORTED) 
-    if (P.FLEN >= P.XLEN)
-      mux2 #(P.LLEN) datamux({{{P.LLEN-P.XLEN}{1'b0}}, IMAWriteDataM}, FWriteDataM, FpLoadStoreM, IMAFWriteDataM);
-    else
-      mux2 #(P.LLEN) datamux(IMAWriteDataM, {{{P.XLEN-P.FLEN}{1'b0}}, FWriteDataM}, FpLoadStoreM, IMAFWriteDataM);
-
-  else assign IMAFWriteDataM = IMAWriteDataM;
-  
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Subword Accesses
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  
-  subwordread #(P) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[3:0]), .BigEndianM,
-    .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
-  subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
-
-  // Compute byte masks
-  swbytemask #(P.LLEN, P.ZICCLSM_SUPPORTED) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM), .ByteMaskExtended(ByteMaskExtendedM));
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // MW Pipeline Register
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  flopen #(P.LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW);
-
-  /////////////////////////////////////////////////////////////////////////////////////////////
-  // Big Endian Byte Swapper
-  //  hart works little-endian internally
-  //  swap the bytes when read from big-endian memory
-  /////////////////////////////////////////////////////////////////////////////////////////////
-
-  if (P.BIGENDIAN_SUPPORTED) begin:endian
-    endianswap #(P.LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
-    endianswap #(P.LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM));
-  end else begin
-    assign LSUWriteDataM = LittleEndianWriteDataM;
-    assign LittleEndianReadDataWordM = ReadDataWordMuxM;
-  end
-endmodule
diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
deleted file mode 100644
index 40e3c11c6..000000000
--- a/src/lsu/subwordread.sv
+++ /dev/null
@@ -1,75 +0,0 @@
-///////////////////////////////////////////
-// subwordread.sv
-//
-// Written: David_Harris@hmc.edu 
-// Created: 9 January 2021
-// Modified: 18 January 2023 
-//
-// Purpose: Extract subwords and sign extend for reads
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module subwordread import cvw::*;  #(parameter cvw_t P) (
-   input logic [P.LLEN-1:0]  ReadDataWordMuxM,
-   input logic [3:0]         PAdrM,
-   input logic [2:0]         Funct3M,
-   input logic               FpLoadStoreM, 
-   input logic               BigEndianM, 
-   output logic [P.LLEN-1:0] ReadDataM
-);
-
-  localparam ADRBITS = $clog2(P.LLEN)-3;
-
-  logic [ADRBITS-1:0]       PAdrSwapM;
-  logic [7:0]               ByteM; 
-  logic [15:0]              HalfwordM;
-  logic [31:0]              WordM;
-  logic [63:0]              DblWordM;
-
-  // invert lsbs of address to select appropriate subword for big endian
-  if (P.BIGENDIAN_SUPPORTED) assign PAdrSwapM = PAdrM[ADRBITS-1:0] ^ {ADRBITS{BigEndianM}};
-  else                       assign PAdrSwapM = PAdrM[ADRBITS-1:0];
-
-  // Use indexed part select to imply muxes to select each size of subword
-  if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
-  else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
-  else assign DblWordM = '0; // unused for RV32F
-  if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
-  else assign WordM = ReadDataWordMuxM;
-  mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);
-  mux2 #(8)  bytemux(HalfwordM[7:0], HalfwordM[15:8], PAdrSwapM[0], ByteM);
-
-  // sign extension/ NaN boxing
-  always_comb
-    case(Funct3M)
-      3'b000:  ReadDataM = {{(P.LLEN-8){ByteM[7]}}, ByteM};                                                     // lb
-      3'b001:  ReadDataM = {{P.LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};                          // lh/flh
-      3'b010:  ReadDataM = {{P.LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};                                  // lw/flw
-      3'b011:  if (P.LLEN >= 64) ReadDataM = {{P.LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};          // ld/fld
-               else ReadDataM = ReadDataWordMuxM;                                                               // shouldn't happen
-      3'b100:  if (P.LLEN == 128) ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{P.LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq   
-               else ReadDataM = {{P.LLEN-8{1'b0}}, ByteM[7:0]};                                                 // lbu
-      3'b101:  ReadDataM = {{P.LLEN-16{1'b0}}, HalfwordM[15:0]};                                                // lhu
-      3'b110:  ReadDataM = {{P.LLEN-32{1'b0}}, WordM[31:0]};                                                    // lwu
-      default: ReadDataM = ReadDataWordMuxM;                                                                    // Shouldn't happen
-    endcase
-endmodule
diff --git a/src/mdu/div.sv b/src/mdu/div.sv
deleted file mode 100644
index 66fe5d9d4..000000000
--- a/src/mdu/div.sv
+++ /dev/null
@@ -1,144 +0,0 @@
-///////////////////////////////////////////
-// intdivrestoring.sv
-//
-// Written: David_Harris@hmc.edu 12 September 2021
-// Modified: 
-//
-// Purpose: Restoring integer division using a shift register and subtractor
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module div import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk,
-  input  logic              reset,
-  input  logic              StallM,
-  input  logic              FlushE,
-  input  logic              IntDivE,                        // integer division/remainder instruction of any type
-  input  logic              DivSignedE,                     // signed division 
-  input  logic              W64E,                           // W-type instructions (divw, divuw, remw, remuw)
-  input  logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
-  output logic              DivBusyE,                       // Divide is busy - stall pipeline
-  output logic [P.XLEN-1:0] QuotM, RemM                     // Quotient and remainder outputs
- );
-
-  localparam STEPBITS = $clog2(P.XLEN/P.IDIV_BITSPERCYCLE); // Number of steps
-
-  typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;    // division FSM state
-  statetype state;
-
-  logic [P.XLEN-1:0]   W[P.IDIV_BITSPERCYCLE:0];            // Residual for each of k steps
-  logic [P.XLEN-1:0]   XQ[P.IDIV_BITSPERCYCLE:0];           // dividend/quotient for each of k steps
-  logic [P.XLEN-1:0]   WNext, XQNext;                       // initialized W and XQ going into registers
-  logic [P.XLEN-1:0]   DinE, XinE;                          // divisor & dividend, possibly truncated to 32 bits
-  logic [P.XLEN-1:0]   DnE;                                 // DnE = ~DinE
-  logic [P.XLEN-1:0]   DAbsBE;                              // absolute value of D
-  logic [P.XLEN-1:0]   DAbsB;                               // registered absolute value of D, constant during division
-  logic [P.XLEN-1:0]   XnE;                                 // DXnE = ~XinE
-  logic [P.XLEN-1:0]   XInitE;                              // |X|, or original X for divide by 0
-  logic [P.XLEN-1:0]   WnM, XQnM;                           // negated residual W and quotient XQ for postprocessing sign correction
-  logic [STEPBITS:0]   step;                                // division step
-  logic                Div0E, Div0M;                        // divide by 0
-  logic                DivStartE;                           // start integer division
-  logic                SignXE, SignDE;                      // sign of dividend and divisor
-  logic                NegQE, NegWM, NegQM;                 // negate quotient or residual during postprocessing
- 
-  //////////////////////////////
-  // Execute Stage: prepare for division calculation with control logic, W logic and absolute values, initialize W and XQ
-  //////////////////////////////
-
-  // Divider control signals
-  assign DivStartE = IntDivE & (state == IDLE) & ~StallM; 
-  assign DivBusyE = (state == BUSY) | DivStartE;
-
-  // Handle sign extension for W-type instructions
-  if (P.XLEN == 64) begin:rv64 // RV64 has W-type instructions
-    mux2 #(P.XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
-    mux2 #(P.XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
-  end else begin // RV32 has no W-type instructions
-    assign XinE = ForwardedSrcAE;
-    assign DinE = ForwardedSrcBE;      
-    end   
-
-  // Extract sign bits and check fo division by zero
-  assign SignDE = DivSignedE & DinE[P.XLEN-1]; 
-  assign SignXE = DivSignedE & XinE[P.XLEN-1];
-  assign NegQE = SignDE ^ SignXE;
-  assign Div0E = (DinE == 0);
-
-  // Take absolute value for signed operations, and negate D to handle subtraction in divider stages
-  neg #(P.XLEN) negd(DinE, DnE);
-  mux2 #(P.XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE);  // take absolute value for signed operations, and negate for subtraction setp
-  neg #(P.XLEN) negx(XinE, XnE);
-  mux3 #(P.XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE);  // take absolute value for signed operations, or keep original value for divide by 0
-
-  //////////////////////////////
-  // Division Iterations (effectively stalled execute stage, no suffix)
-  //////////////////////////////
-
-  // initialization multiplexers on first cycle of operation
-  mux2 #(P.XLEN) wmux(W[P.IDIV_BITSPERCYCLE], {P.XLEN{1'b0}}, DivStartE, WNext);
-  mux2 #(P.XLEN) xmux(XQ[P.IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext);
-
-  // registers before division steps
-  flopen #(P.XLEN) wreg(clk, DivBusyE, WNext, W[0]); 
-  flopen #(P.XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
-  flopen #(P.XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
-
-  // one copy of divstep for each bit produced per cycle
-  genvar i;
-  for (i=0; i<P.IDIV_BITSPERCYCLE; i = i+1)
-    divstep #(P.XLEN) divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
-
-  //////////////////////////////
-  // Memory Stage: output sign correction and special cases
-  //////////////////////////////
-
-  flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
-  
-  // On final setp of signed operations, negate outputs as needed to get correct sign
-  neg #(P.XLEN) qneg(XQ[0], XQnM);
-  neg #(P.XLEN) wneg(W[0], WnM);
-  // Select appropriate output: normal, negated, or for divide by zero
-  mux3 #(P.XLEN) qmux(XQ[0], XQnM, {P.XLEN{1'b1}}, {Div0M, NegQM}, QuotM); // Q taken from XQ register, negated if necessary, or all 1s when dividing by zero
-  mux3 #(P.XLEN) remmux(W[0], WnM, XQ[0], {Div0M, NegWM}, RemM); // REM taken from W register, negated if necessary, or from X when dividing by zero
-
-  //////////////////////////////
-  // Divider FSM to sequence Busy and Done
-  //////////////////////////////
-
- always_ff @(posedge clk) 
-    if (reset | FlushE) begin
-        state <= IDLE; 
-    end else if (DivStartE) begin 
-        step <= 1;
-        if (Div0E) state <= DONE;
-        else       state <= BUSY;
-    end else if (state == BUSY) begin // pause one cycle at beginning of signed operations for absolute value
-        if (step[STEPBITS] | (P.XLEN==64) & W64E & step[STEPBITS-1]) begin // complete in half the time for W-type instructions
-            state <= DONE;
-        end
-        step <= step + 1;
-    end else if (state == DONE) begin
-      if (StallM) state <= DONE;
-      else        state <= IDLE;
-    end 
-endmodule 
diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv
deleted file mode 100644
index aa93d6767..000000000
--- a/src/mdu/divstep.sv
+++ /dev/null
@@ -1,46 +0,0 @@
-///////////////////////////////////////////
-// intdivrestoringstep.sv
-//
-// Written: David_Harris@hmc.edu 2 October 2021
-// Modified: 
-//
-// Purpose: Radix-2 restoring integer division step.  k steps are used in div
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module divstep #(parameter XLEN) (
-  input  logic [XLEN-1:0] W,     // Residual in
-  input  logic [XLEN-1:0] XQ,    // bits of dividend X and quotient Q in
-  input  logic [XLEN-1:0] DAbsB, // complement of absolute value of divisor D (for subtraction)
-  output logic [XLEN-1:0] WOut,  // Residual out
-  output logic [XLEN-1:0] XQOut  // bits of dividend and quotient out: discard one bit of X, append one bit of Q
-);
-
-  logic [XLEN-1:0] WShift;       // Shift W left by one bit, bringing in most significant bit of X
-  logic [XLEN-1:0] WPrime;       // WShift - D, for comparison and possible result
-  logic qi, qib;                  // Quotient digit and its complement
-  
-  assign {WShift, XQOut} = {W[XLEN-2:0], XQ, qi};  // shift W and X/Q left, insert quotient bit at bottom
-  adder #(XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime}); // effective subtractor, carry out determines quotient bit
-  assign qi = ~qib;
-  mux2 #(XLEN) wrestoremux(WShift, WPrime, qi, WOut); // if quotient is zero, restore W
-endmodule
diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv
deleted file mode 100644
index b2f0f7514..000000000
--- a/src/mdu/mdu.sv
+++ /dev/null
@@ -1,88 +0,0 @@
-///////////////////////////////////////////
-// mdu.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: M extension multiply and divide
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module mdu import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  input  logic              StallM, StallW, 
-  input  logic              FlushE, FlushM, FlushW,
-  input  logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
-  input  logic [2:0]        Funct3E, Funct3M,               // type of MDU operation
-  input  logic              IntDivE, W64E,                  // Integer division/remainder, and W-type instrutions
-  input  logic              MDUActiveE,                     // Mul/Div instruction being executed
-  output logic [P.XLEN-1:0] MDUResultW,                     // multiply/divide result
-  output logic              DivBusyE                        // busy signal to stall pipeline in Execute stage
-);
-
-  logic [P.XLEN*2-1:0]      ProdM;                          // double-width product from mul
-  logic [P.XLEN-1:0]        QuotM, RemM;                    // quotient and remainder from intdivrestoring
-  logic [P.XLEN-1:0]        PrelimResultM;                  // selected result before W truncation
-  logic [P.XLEN-1:0]        MDUResultM;                     // result after W truncation
-  logic                     W64M;                           // W-type instruction
-
-  // Multiplier
-  mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
-
-  // Divider
-  // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
-  // When IDIV_ON_FPU is set, use the FPU divider instead
-  // In ZMMUL, with M_SUPPORTED = 0, omit the divider
-  if ((P.IDIV_ON_FPU & P.F_SUPPORTED) | (!P.M_SUPPORTED)) begin:nodiv  
-    assign QuotM = '0;
-    assign RemM = '0;
-    assign DivBusyE = 1'b0;
-  end else begin:div
-    div #(P) div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, 
-        .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
-  end
-    
-  // Result multiplexer
-  // For ZMMUL, QuotM and RemM are tied to 0, so the mux automatically simplifies
-  always_comb
-    case (Funct3M)     
-      3'b000: PrelimResultM = ProdM[P.XLEN-1:0];          // mul
-      3'b001: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulh
-      3'b010: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulhsu
-      3'b011: PrelimResultM = ProdM[P.XLEN*2-1:P.XLEN];   // mulhu
-      3'b100: PrelimResultM = QuotM;                      // div
-      3'b101: PrelimResultM = QuotM;                      // divu
-      3'b110: PrelimResultM = RemM;                       // rem
-      3'b111: PrelimResultM = RemM;                       // remu
-    endcase 
-
-  // Handle sign extension for W-type instructions
-  flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
-  if (P.XLEN == 64) begin:resmux // RV64 has W-type instructions
-    assign MDUResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
-  end else begin:resmux // RV32 has no W-type instructions
-    assign MDUResultM = PrelimResultM;
-  end
-
-  // Writeback stage pipeline register
-  flopenrc #(P.XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);   
-endmodule // mdu
diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
deleted file mode 100644
index 2ef7c25f1..000000000
--- a/src/mmu/adrdecs.sv
+++ /dev/null
@@ -1,56 +0,0 @@
-///////////////////////////////////////////
-// adrdecs.sv
-//
-// Written: David_Harris@hmc.edu 22 June 2021
-// Modified: 
-//
-// Purpose: All the address decoders for peripherals
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-  // verilator lint_off UNOPTFLAT 
-
-module adrdecs import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.PA_BITS-1:0] PhysicalAddress,
-  input  logic                 AccessRW, AccessRX, AccessRWXC,
-  input  logic [1:0]           Size,
-  output logic [11:0]          SelRegions
-);
-
-  localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
- // Determine which region of physical memory (if any) is being accessed
-  adrdec #(P.PA_BITS) dtimdec(PhysicalAddress, P.DTIM_BASE[P.PA_BITS-1:0], P.DTIM_RANGE[P.PA_BITS-1:0], P.DTIM_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[1]);  
-  adrdec #(P.PA_BITS) iromdec(PhysicalAddress, P.IROM_BASE[P.PA_BITS-1:0], P.IROM_RANGE[P.PA_BITS-1:0], P.IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[2]);  
-  adrdec #(P.PA_BITS) ddr4dec(PhysicalAddress, P.EXT_MEM_BASE[P.PA_BITS-1:0], P.EXT_MEM_RANGE[P.PA_BITS-1:0], P.EXT_MEM_SUPPORTED, AccessRWXC, Size, SUPPORTED_SIZE, SelRegions[3]);  
-  adrdec #(P.PA_BITS) bootromdec(PhysicalAddress, P.BOOTROM_BASE[P.PA_BITS-1:0], P.BOOTROM_RANGE[P.PA_BITS-1:0], P.BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[4]);
-  adrdec #(P.PA_BITS) uncoreramdec(PhysicalAddress, P.UNCORE_RAM_BASE[P.PA_BITS-1:0], P.UNCORE_RAM_RANGE[P.PA_BITS-1:0], P.UNCORE_RAM_SUPPORTED, AccessRWXC, Size, SUPPORTED_SIZE, SelRegions[5]);
-  adrdec #(P.PA_BITS) clintdec(PhysicalAddress, P.CLINT_BASE[P.PA_BITS-1:0], P.CLINT_RANGE[P.PA_BITS-1:0], P.CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[6]);
-  adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[7]);
-  adrdec #(P.PA_BITS) uartdec(PhysicalAddress, P.UART_BASE[P.PA_BITS-1:0], P.UART_RANGE[P.PA_BITS-1:0], P.UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[8]);
-  adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[9]);
-  adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]); 
-  adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]);
-
-  assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected
-endmodule
-
-  // verilator lint_on UNOPTFLAT 
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
deleted file mode 100644
index 6b7df68fb..000000000
--- a/src/mmu/hptw.sv
+++ /dev/null
@@ -1,334 +0,0 @@
-///////////////////////////////////////////
-// hptw.sv
-//
-// Written: tfleming@hmc.edu 2 March 2021
-// Modified:  david_harris@hmc.edu 18 July 2021 cleanup and simplification
-//            kmacsaigoren@hmc.edu 1 June 2021
-//            implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
-//            adding support for terapage encoding, and for setting the HPTWAdr using the new level,
-//            adding the internal SvMode signal
-//
-// Purpose: Hardware Page Table Walker
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-module hptw import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  input  logic [P.XLEN-1:0] SATP_REGW,              // includes SATP.MODE to determine number of levels in page table
-  input  logic [P.XLEN-1:0] PCSpillF,               // addresses to translate
-  input  logic [P.XLEN+1:0] IEUAdrExtM,             // addresses to translate
-  input  logic [1:0]        MemRWM, AtomicM,
-  // system status
-  input  logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]        STATUS_MPP,
-  input  logic              ENVCFG_ADUE,            // HPTW A/D Update enable
-  input  logic [1:0]        PrivilegeModeW,
-  input  logic [P.XLEN-1:0] ReadDataM,              // page table entry from LSU 
-  input  logic [P.XLEN-1:0] WriteDataM,
-  input  logic              DCacheBusStallM,           // stall from LSU
-  input  logic [2:0]        Funct3M,
-  input  logic [6:0]        Funct7M,
-  input  logic              ITLBMissOrUpdateAF,
-  input  logic              DTLBMissOrUpdateDAM,
-  input  logic              FlushW,
-  output logic [P.XLEN-1:0] PTE,                    // page table entry to TLBs
-  output logic [1:0]        PageType,               // page type to TLBs
-  output logic              ITLBWriteF, DTLBWriteM, // write TLB with new entry
-  output logic [1:0]        PreLSURWM,
-  output logic [P.XLEN+1:0] IHAdrM,
-  output logic [P.XLEN-1:0] IHWriteDataM,
-  output logic [1:0]        LSUAtomicM,
-  output logic [2:0]        LSUFunct3M,
-  output logic [6:0]        LSUFunct7M,
-  output logic              HPTWFlushW,
-  output logic              SelHPTW,
-  output logic              HPTWStall,
-  input  logic              LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, 
-  input  logic              LSULoadPageFaultM, LSUStoreAmoPageFaultM, 
-  output logic              LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultF,
-  output logic              LoadPageFaultM, StoreAmoPageFaultM, HPTWInstrPageFaultF
-);
-
-  typedef enum logic [3:0] {L0_ADR, L0_RD, 
-          L1_ADR, L1_RD, 
-          L2_ADR, L2_RD, 
-          L3_ADR, L3_RD, 
-          LEAF, IDLE, UPDATE_PTE,
-          FAULT} statetype;
-
-  logic                     DTLBWalk; // register TLBs translation miss requests
-  logic [P.PPN_BITS-1:0]    BasePageTablePPN;
-  logic [P.PPN_BITS-1:0]    CurrentPPN;
-  logic                     Executable, Writable, Readable, Valid, PTE_U;
-  logic                     Misaligned, MegapageMisaligned;
-  logic                     ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
-  logic                     StartWalk;
-  logic                     TLBMissOrUpdateDA;
-  logic                     PRegEn;
-  logic [1:0]               NextPageType;
-  logic [P.SVMODE_BITS-1:0] SvMode;
-  logic [P.XLEN-1:0]        TranslationVAdr;
-  logic [P.XLEN-1:0]        NextPTE, NextPTE2;
-  logic                     UpdatePTE;
-  logic                     HPTWUpdateDA;
-  logic [P.PA_BITS-1:0]     HPTWReadAdr;
-  logic                     SelHPTWAdr;
-  logic [P.XLEN+1:0]        HPTWAdrExt;
-  logic                     LSUAccessFaultM;
-  logic [P.PA_BITS-1:0]     HPTWAdr;
-  logic [1:0]               HPTWRW;
-  logic [2:0]               HPTWSize; // 32 or 64 bit access
-  statetype                 WalkerState, NextWalkerState, InitialWalkerState;
-  logic                     HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault;
-  logic                     HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay;
-  logic                     HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault;
-  logic                     HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay;
-  logic                     HPTWAccessFaultDelay;
-  logic                     TakeHPTWFault;
-  logic                     PBMTFaultM;
-  logic                     DAUFaultM;
-  logic                     PBMTOrDAUFaultM;
-  logic                     HPTWFaultM;
- 
-  // map hptw access faults onto either the original LSU load/store fault or instruction access fault
-  assign LSUAccessFaultM         = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
-  assign PBMTOrDAUFaultM         = PBMTFaultM | DAUFaultM;
-  assign HPTWFaultM              = LSUAccessFaultM | PBMTOrDAUFaultM;
-  assign HPTWLoadAccessFault     = LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];  
-  assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0];
-  assign HPTWInstrAccessFault    = LSUAccessFaultM & ~DTLBWalk;
-  assign HPTWLoadPageFault       = PBMTOrDAUFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
-  assign HPTWStoreAmoPageFault   = PBMTOrDAUFaultM & DTLBWalk & MemRWM[0];
-  assign HPTWInstrPageFault      = PBMTOrDAUFaultM & ~DTLBWalk;
-
-  flopr #(6) HPTWAccesFaultReg(clk, reset, {HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, 
-                                            HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault},
-                               {HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay,
-                                HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay});
-
-  assign TakeHPTWFault = WalkerState != IDLE;
-  
-  // Improve timing by taking HPTW faults off critical path because these are multicycle operations anyway
-  assign LoadAccessFaultM      = TakeHPTWFault ? HPTWLoadAccessFaultDelay : LSULoadAccessFaultM;                     
-  assign StoreAmoAccessFaultM  = TakeHPTWFault ? HPTWStoreAmoAccessFaultDelay : LSUStoreAmoAccessFaultM;
-  assign HPTWInstrAccessFaultF = TakeHPTWFault ? HPTWInstrAccessFaultDelay : 1'b0;
-  assign LoadPageFaultM        = TakeHPTWFault ? HPTWLoadPageFaultDelay : LSULoadPageFaultM;
-  assign StoreAmoPageFaultM    = TakeHPTWFault ? HPTWStoreAmoPageFaultDelay : LSUStoreAmoPageFaultM;
-  assign HPTWInstrPageFaultF   = TakeHPTWFault ? HPTWInstrPageFaultDelay : 1'b0;
-  
-  // Extract bits from CSRs and inputs
-  assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS];
-  assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0];
-  assign TLBMissOrUpdateDA = DTLBMissOrUpdateDAM | ITLBMissOrUpdateAF;
-
-  // Determine which address to translate
-  mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr);
-  assign CurrentPPN = PTE[P.PPN_BITS+9:10];
-
-  // State flops
-  flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
-  assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE | (NextWalkerState == IDLE);
-  assign NextPTE2 = (NextWalkerState == IDLE) ? '0 : NextPTE;
-  flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE2, PTE); // Capture page table entry from data cache
-
-  // Assign PTE descriptors common across all XLEN values
-  // For non-leaf PTEs, D, A, U bits are reserved and ignored.  They do not cause faults while walking the page table
-  assign {PTE_U, Executable, Writable, Readable, Valid} = PTE[4:0];
-  assign LeafPTE = Executable | Writable | Readable; 
-  assign ValidPTE = Valid & ~(Writable & ~Readable);
-  assign ValidLeafPTE = ValidPTE & LeafPTE;
-  assign ValidNonLeafPTE = Valid & ~LeafPTE;
-  if(P.XLEN == 64) assign PBMTFaultM = ValidNonLeafPTE & (|PTE[62:61]);
-  else assign PBMTFaultM = 1'b0;
-  assign DAUFaultM = ValidNonLeafPTE & (|PTE[7:6] | PTE[4]);
-
-  if(P.SVADU_SUPPORTED) begin : hptwwrites
-    logic                 ReadAccess, WriteAccess;
-    logic                 InvalidRead, InvalidWrite, InvalidOp;
-    logic                 UpperBitsUnequal, UpperBitsUnequalD; 
-    logic                 OtherPageFault;
-    logic [1:0]           EffectivePrivilegeMode;
-    logic                 ImproperPrivilege;
-    logic                 SaveHPTWAdr, SelHPTWWriteAdr;
-    logic [P.PA_BITS-1:0] HPTWWriteAdr;  
-    logic                 SetDirty;
-    logic                 Dirty, Accessed;
-    logic [P.XLEN-1:0]    AccessedPTE;
-
-    assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
-    flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
-    
-    assign SaveHPTWAdr = (NextWalkerState == L0_RD | NextWalkerState == L1_RD | NextWalkerState == L2_RD | NextWalkerState == L3_RD); // save the HPTWAdr when the walker is about to read the PTE at any level; the last level read is the one to write during UpdatePTE
-    assign SelHPTWWriteAdr = UpdatePTE | HPTWRW[0];
-    mux2 #(P.PA_BITS) HPTWWriteAdrMux(HPTWReadAdr, HPTWWriteAdr, SelHPTWWriteAdr, HPTWAdr); 
-
-    assign {Dirty, Accessed} = PTE[7:6];
-    assign WriteAccess = MemRWM[0]; // implies | (|AtomicM);
-    assign SetDirty = ~Dirty & DTLBWalk & WriteAccess;
-    assign ReadAccess = MemRWM[1];
-
-    assign EffectivePrivilegeMode = DTLBWalk ? (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW) : PrivilegeModeW; // DTLB uses MPP mode when MPRV is 1
-    assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
-                               ((EffectivePrivilegeMode == P.S_MODE) & PTE_U & (~STATUS_SUM & DTLBWalk));
-
-    // Check for page faults
-    vm64check #(P) vm64check(.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]), .VAdr(TranslationVAdr), 
-      .SV39Mode(), .UpperBitsUnequal);
-    // This register is not functionally necessary, but improves the critical path.
-    flopr #(1) upperbitsunequalreg(clk, reset, UpperBitsUnequal, UpperBitsUnequalD);
-    assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable);
-    assign InvalidWrite = WriteAccess & ~Writable;
-    assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable;
-    assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequalD | Misaligned | ~Valid;
-
-    // hptw needs to know if there is a Dirty or Access fault occuring on this
-    // memory access.  If there is the PTE needs to be updated seting Access
-    // and possibly also Dirty.  Dirty is set if the operation is a store/amo.
-    // However any other fault should not cause the update, and updates are in software when ENVCFG_ADUE = 0
-    assign HPTWUpdateDA = ValidLeafPTE & (~Accessed | SetDirty) & ENVCFG_ADUE & ~OtherPageFault;   
-
-    assign HPTWRW[0] = (WalkerState == UPDATE_PTE);           // HPTWRW[0] will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0 so WalkerState never is UPDATE_PTE
-    assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;  // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
-
-  end else begin // block: hptwwrites
-    assign NextPTE = ReadDataM;
-    assign HPTWAdr = HPTWReadAdr;
-    assign HPTWUpdateDA = 1'b0;
-    assign UpdatePTE = 1'b0;
-    assign HPTWRW[0] = 1'b0;
-  end
-
-  // Enable and select signals based on states
-  assign StartWalk  = (WalkerState == IDLE) & TLBMissOrUpdateDA; 
-  assign HPTWRW[1]  = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
-  assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk;
-  assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk;
-  
-  // FSM to track PageType based on the levels of the page table traversed
-  flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
-  always_comb 
-    case (WalkerState)
-      L3_RD:  NextPageType = 2'b11; // terapage
-      L2_RD:  NextPageType = 2'b10; // gigapage
-      L1_RD:  NextPageType = 2'b01; // megapage
-      L0_RD:  NextPageType = 2'b00; // kilopage
-      default: NextPageType = PageType;
-    endcase
-
-  // HPTWAdr muxing
-  if (P.XLEN==32) begin // RV32
-    logic [9:0] VPN;
-    logic [P.PPN_BITS-1:0] PPN;
-    assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
-    assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
-    assign HPTWReadAdr = {PPN, VPN, 2'b00};
-    assign HPTWSize = 3'b010;
-  end else begin // RV64
-    logic [8:0] VPN;
-    logic [P.PPN_BITS-1:0] PPN;
-    always_comb
-      case (WalkerState) // select VPN field based on HPTW state
-        L3_ADR, L3_RD:  VPN = TranslationVAdr[47:39];
-        L2_ADR, L2_RD:  VPN = TranslationVAdr[38:30];
-        L1_ADR, L1_RD:   VPN = TranslationVAdr[29:21];
-        default:    VPN = TranslationVAdr[20:12];
-      endcase
-    assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
-            (SvMode != P.SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
-    assign HPTWReadAdr = {PPN, VPN, 3'b000};
-    assign HPTWSize = 3'b011;
-  end
-
-  // Initial state and misalignment for RV32/64
-  if (P.XLEN == 32) begin
-    assign InitialWalkerState = L1_ADR;
-    assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
-    assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
-  end else begin
-    logic  GigapageMisaligned, TerapageMisaligned;
-    assign InitialWalkerState = (SvMode == P.SV48) ? L3_ADR : L2_ADR;
-    assign TerapageMisaligned = |(CurrentPPN[26:0]); // Must have zero PPN2, PPN1, PPN0
-    assign GigapageMisaligned = |(CurrentPPN[17:0]); // Must have zero PPN1 and PPN0
-    assign MegapageMisaligned = |(CurrentPPN[8:0]);  // Must have zero PPN0      
-    assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
-  end
-
-  // Page Table Walker FSM
-  flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
-  always_comb 
-    case (WalkerState)
-      IDLE:       if (TLBMissOrUpdateDA)                              NextWalkerState = InitialWalkerState;                      
-                  else                                                NextWalkerState = IDLE;
-      L3_ADR:                                                         NextWalkerState = L3_RD; // First access in SV48
-      L3_RD:      if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (DCacheBusStallM)                           NextWalkerState = L3_RD;
-                  else                                                NextWalkerState = L2_ADR;
-      L2_ADR:     if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39
-                  else                                                NextWalkerState = LEAF;
-      L2_RD:      if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (DCacheBusStallM)                           NextWalkerState = L2_RD;
-                  else                                                NextWalkerState = L1_ADR;
-      L1_ADR:     if  (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32                 
-                  else                                                NextWalkerState = LEAF;  
-      L1_RD:      if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (DCacheBusStallM)                           NextWalkerState = L1_RD;
-                  else                                                NextWalkerState = L0_ADR;
-      L0_ADR:     if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (ValidNonLeafPTE)                           NextWalkerState = L0_RD;
-                  else                                                NextWalkerState = LEAF;
-      L0_RD:      if (HPTWFaultM)                                     NextWalkerState = FAULT;
-                  else if (DCacheBusStallM)                           NextWalkerState = L0_RD;
-                  else                                                NextWalkerState = LEAF;
-      LEAF:       if (P.SVADU_SUPPORTED & HPTWUpdateDA)               NextWalkerState = UPDATE_PTE;
-                  else                                                NextWalkerState = IDLE;
-      UPDATE_PTE: if (DCacheBusStallM)                                NextWalkerState = UPDATE_PTE;
-                  else                                                NextWalkerState = LEAF;
-      FAULT:                                                          NextWalkerState = IDLE;
-      default:                                                        NextWalkerState = IDLE; // Should never be reached
-    endcase // case (WalkerState)
-
-  assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM);
-  
-  assign SelHPTW = WalkerState != IDLE;
-  assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); 
-
-  // HTPW address/data/control muxing
-
-  // Once the walk is done and it is time to update the TLB we need to switch back 
-  // to the orignal data virtual address.
-  assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
-
-  // multiplex the outputs to LSU
-  if (P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // Extend to 66 bits
-  else              assign HPTWAdrExt = HPTWAdr;
-  mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
-  mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
-  mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);    
-  mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
-  mux2 #(P.XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
-  if (P.SVADU_SUPPORTED) 
-    mux2 #(P.XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
-  else assign IHWriteDataM = WriteDataM;
-
-endmodule
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
deleted file mode 100644
index a1022de51..000000000
--- a/src/mmu/mmu.sv
+++ /dev/null
@@ -1,162 +0,0 @@
-///////////////////////////////////////////
-// mmu.sv
-//
-// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
-// Modified: 
-//
-// Purpose: Memory management unit, including TLB, PMA, PMP
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module mmu import cvw::*;  #(parameter cvw_t P,
-                             parameter TLB_ENTRIES = 8, IMMU = 0) (
-  input  logic                 clk, reset,
-  input  logic [P.XLEN-1:0]    SATP_REGW,          // Current value of satp CSR (from privileged unit)
-  input  logic                 STATUS_MXR,         // Status CSR: make executable page readable
-  input  logic                 STATUS_SUM,         // Status CSR: Supervisor access to user memory
-  input  logic                 STATUS_MPRV,        // Status CSR: modify machine privilege
-  input  logic [1:0]           STATUS_MPP,         // Status CSR: previous machine privilege level
-  input  logic                 ENVCFG_PBMTE,       // Page-based memory types enabled
-  input  logic                 ENVCFG_ADUE,        // HPTW A/D Update enable
-  input  logic [1:0]           PrivilegeModeW,     // Current privilege level of the processeor
-  input  logic                 DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
-  input  logic [P.XLEN+1:0]    VAdr,               // virtual/physical address from IEU or physical address from HPTW
-  input  logic [1:0]           Size,               // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
-  input  logic [P.XLEN-1:0]    PTE,                // page table entry
-  input  logic [1:0]           PageTypeWriteVal,   // page type
-  input  logic                 TLBWrite,           // write TLB entry
-  input  logic                 TLBFlush,           // Invalidate all TLB entries
-  output logic [P.PA_BITS-1:0] PhysicalAddress,    // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
-  output logic                 TLBMiss,            // Miss TLB
-  output logic                 Cacheable,          // PMA indicates memory address is cachable
-  output logic                 Idempotent,         // PMA indicates memory address is idempotent
-  output logic                 SelTIM,             // Select a tightly integrated memory
-  // Faults
-  output logic                 InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
-  output logic                 InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
-  output logic                 UpdateDA,                                                  // page fault due to setting dirty or access bit
-  output logic                 LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
-  // PMA checker signals
-  input  logic [3:0]           CMOpM,                                                     // Cache management instructions
-  input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
-  input var logic [7:0]        PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],                      // PMP configuration
-  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0]                   // PMP addresses
-);
-
-  logic [P.PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
-  logic                        PMAInstrAccessFaultF;     // Instruction access fault from PMA
-  logic                        PMPInstrAccessFaultF;     // Instruction access fault from PMP
-  logic                        PMALoadAccessFaultM;      // Load access fault from PMA
-  logic                        PMPLoadAccessFaultM;      // Load access fault from PMP
-  logic                        PMAStoreAmoAccessFaultM;  // Store or AMO access fault from PMA
-  logic                        PMPStoreAmoAccessFaultM;  // Store or AMO access fault from PMP
-  logic                        DataMisalignedM;          // load or store misaligned
-  logic                        Translate;                // Translation occurs when virtual memory is active and DisableTranslation is off
-  logic                        TLBPageFault;             // Page fault from TLB
-  logic                        ReadNoAmoAccessM;         // Read that is not part of atomic operation causes Load faults.  Otherwise StoreAmo faults
-  logic [1:0]                  PBMemoryType;             // PBMT field of PTE during TLB hit, or 00 otherwise
-  logic                        AtomicMisalignedCausesAccessFaultM; // Misaligned atomics are not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM
-  logic [1:0]                  EffectivePrivilegeModeW;  // Effective privilege mode accounting for MPRV
-  
-
-  // Get Effective Privilege Mode
-  // for DLB, when mstatus.MPRV=1, use mstatus.MPP rather than the current privilege mode
-  assign EffectivePrivilegeModeW = IMMU ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW);
-
-  // only instantiate TLB if Virtual Memory is supported
-  if (P.VIRTMEM_SUPPORTED) begin:tlb
-    logic ReadAccess, WriteAccess;
-    assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read.  Execute and Read are never active for the same MMU, so safe to mix pipestages
-    assign WriteAccess = WriteAccessM;
-    tlb #(.P(P), .TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
-          .clk, .reset,
-          .SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
-          .SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
-          .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-          .EffectivePrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
-          .DisableTranslation, .PTE, .PageTypeWriteVal,
-          .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss,
-          .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
-  end else begin:tlb // just pass address through as physical
-    assign Translate    = 1'b0;
-    assign TLBMiss      = 1'b0;
-    assign TLBPageFault = 1'b0;
-    assign PBMemoryType = 2'b00;
-    assign UpdateDA     = 1'b0;
-    assign TLBPAdr      = '0;
-  end
-
-  // If translation is occuring, select translated physical address from TLB
-  // the lower 12 bits are the page offset. These are never changed from the orginal
-  // non translated address.
-  mux2 #(P.PA_BITS-12) addressmux(VAdr[P.PA_BITS-1:12], TLBPAdr[P.PA_BITS-1:12], Translate, PhysicalAddress[P.PA_BITS-1:12]);
-  assign PhysicalAddress[11:0] = VAdr[11:0];
-  
-  ///////////////////////////////////////////
-  // Check physical memory accesses
-  ///////////////////////////////////////////
-
-  pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM, 
-    .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
-    .Cacheable, .Idempotent, .SelTIM, 
-    .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
- 
-  if (P.PMP_ENTRIES > 0) begin : pmp
-    pmpchecker #(P) pmpchecker(.PhysicalAddress, .EffectivePrivilegeModeW,
-      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-      .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .Size, .CMOpM, 
-      .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
-  end else begin
-    assign PMPInstrAccessFaultF     = 1'b0;
-    assign PMPStoreAmoAccessFaultM  = 1'b0;
-    assign PMPLoadAccessFaultM      = 1'b0;
-  end
-
-  assign ReadNoAmoAccessM  = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault
-
-  // Misaligned faults
-  always_comb // exclusion-tag: immu-wordaccess
-    case(Size) 
-      2'b00:  DataMisalignedM = 1'b0;              // lb, sb, lbu
-      2'b01:  DataMisalignedM = VAdr[0];           // lh, sh, lhu
-      2'b10:  DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
-      2'b11:  DataMisalignedM = |VAdr[2:0];        // ld, sd, fld, fsd
-    endcase 
-  // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault
-  assign LoadMisalignedFaultM     = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; 
-  assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess
-
-  // a misaligned Atomic causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware
-  // this is subtle - see privileged spec 3.6.3.3
-  assign AtomicMisalignedCausesAccessFaultM = DataMisalignedM & AtomicAccessM & (P.ZICCLSM_SUPPORTED & Cacheable);
-
-  // Access faults
-  // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
-  assign InstrAccessFaultF    = (PMAInstrAccessFaultF    | PMPInstrAccessFaultF)    & ~TLBMiss;
-  assign LoadAccessFaultM     = (PMALoadAccessFaultM     | PMPLoadAccessFaultM     | AtomicMisalignedCausesAccessFaultM & ReadNoAmoAccessM)     & ~TLBMiss;
-  assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AtomicMisalignedCausesAccessFaultM & WriteAccessM) & ~TLBMiss;
-
-  // Specify which type of page fault is occurring
-  assign InstrPageFaultF    = TLBPageFault & ExecuteAccessF;
-  assign LoadPageFaultM     = TLBPageFault & ReadNoAmoAccessM; 
-  assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | (|CMOpM));
-endmodule
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
deleted file mode 100644
index 021f448b2..000000000
--- a/src/mmu/pmachecker.sv
+++ /dev/null
@@ -1,80 +0,0 @@
-///////////////////////////////////////////
-// pmachecker.sv
-//
-// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
-// Modified: 
-//
-// Purpose: Examines all physical memory accesses and identifies attributes of
-//          the memory region accessed.
-//          Can report illegal accesses to the trap unit and cause a fault.
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module pmachecker import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.PA_BITS-1:0] PhysicalAddress,
-  input  logic [1:0]           Size,
-  input  logic [3:0]           CMOpM,
-  input  logic                 AtomicAccessM,  // Atomic access
-  input  logic                 ExecuteAccessF, // Execute access 
-  input  logic                 WriteAccessM,   // Write access 
-  input  logic                 ReadAccessM,    // Read access
-  input  logic [1:0]           PBMemoryType,     // PBMT field of PTE during TLB hit, or 00 otherwise
-  output logic                 Cacheable, Idempotent, SelTIM,
-  output logic                 PMAInstrAccessFaultF,
-  output logic                 PMALoadAccessFaultM,
-  output logic                 PMAStoreAmoAccessFaultM
-);
-
-  logic                        PMAAccessFault;
-  logic                        AccessRW, AccessRWXC, AccessRX;
-  logic [11:0]                 SelRegions;
-  logic                        AtomicAllowed;
-  logic                        CacheableRegion, IdempotentRegion;
-
-  // Determine what type of access is being made
-  assign AccessRW  = ReadAccessM | WriteAccessM;
-  assign AccessRWXC = ReadAccessM | WriteAccessM | ExecuteAccessF | (|CMOpM);
-  assign AccessRX  = ReadAccessM | ExecuteAccessF;
-
-  // Determine which region of physical memory (if any) is being accessed
-  adrdecs #(P) adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWXC, Size, SelRegions);
-
-  // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
-  assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5];  // exclusion-tag: unused-cachable
-  assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 1'b0;  
-
-  // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
-  // I/O is nonidempotent.  PBMT can override PMA; NC is idempotent and IO is non-idempotent
-  assign IdempotentRegion = SelRegions[1] | SelRegions[2] | SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-idempotent
-  assign Idempotent = (PBMemoryType == 2'b00) ? IdempotentRegion : (PBMemoryType == 2'b01);  
- 
-  // Atomic operations are only allowed on RAM
-  assign AtomicAllowed = SelRegions[1] | SelRegions[3] | SelRegions[5]; // exclusion-tag: unused-atomic
-  // Check if tightly integrated memories are selected
-  assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-tim
-
-  // Detect access faults
-  assign PMAAccessFault          = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
-  assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
-  assign PMALoadAccessFaultM     = ReadAccessM & ~WriteAccessM & PMAAccessFault;
-  assign PMAStoreAmoAccessFaultM = (WriteAccessM | (|CMOpM))   & PMAAccessFault;
-endmodule
diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
deleted file mode 100644
index 3877089b6..000000000
--- a/src/mmu/pmpchecker.sv
+++ /dev/null
@@ -1,111 +0,0 @@
-///////////////////////////////////////////
-// pmpchecker.sv
-//
-// Written: tfleming@hmc.edu & jtorrey@hmc.edu 28 April 2021
-// Modified: 
-//
-// Purpose: Examines all physical memory accesses and checks them against the
-//          current values of the physical memory protection (PMP) registers.
-//          Can raise an access fault on illegal reads, writes, and instruction
-//          fetches.
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module pmpchecker import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.PA_BITS-1:0]     PhysicalAddress,  
-  input  logic [1:0]               EffectivePrivilegeModeW,
-  // ModelSim has a switch -svinputport which controls whether input ports
-  // are nets (wires) or vars by default. The default setting of this switch is
-  // `relaxed`, which means that signals are nets if and only if they are
-  // scalars or one-dimensional vectors. Since this is a two-dimensional vector,
-  // this will be understood as a var. However, if we don't supply the `var`
-  // keyword, the compiler warns us that it's interpreting the signal as a var,
-  // which we might not intend.
-  input  var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
-  input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
-  input  logic                     ExecuteAccessF, WriteAccessM, ReadAccessM,
-  input  logic [1:0]               Size,
-  input  logic [3:0]               CMOpM,
-  output logic                     PMPInstrAccessFaultF,
-  output logic                     PMPLoadAccessFaultM,
-  output logic                     PMPStoreAmoAccessFaultM
-);
-
-  // Bit i is high when the address falls in PMP region i
-  logic                            EnforcePMP; // should PMP be checked in this privilege level
-  logic [P.PMP_ENTRIES-1:0]        Match;      // physical address matches one of the pmp ranges
-  logic [P.PMP_ENTRIES-1:0]        FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-  logic [P.PMP_ENTRIES-1:0]        L, X, W, R; // PMP matches and has flag set
-  logic [P.PMP_ENTRIES-1:0]        PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
-  logic [P.PA_BITS-1:0]            PMPTop[P.PMP_ENTRIES-1:0];     // Upper end of each region, for checking that the access is fully within the region
-  logic                            PMPCMOAccessFault, PMPCBOMAccessFault, PMPCBOZAccessFault;
-  logic [2:0]                      SizeBytesMinus1;
-  logic                            MatchingR, MatchingW, MatchingX, MatchingL;
-  logic [P.PA_BITS-1:0]            MatchingPMPTop, PhysicalAddressTop;
-  logic                            TooBig;
-
-  if (P.PMP_ENTRIES > 0) begin: pmp // prevent complaints about array of no elements when PMP_ENTRIES = 0
-    pmpadrdec #(P) pmpadrdecs[P.PMP_ENTRIES-1:0](
-      .PhysicalAddress, 
-      .Size,
-      .PMPCfg(PMPCFG_ARRAY_REGW),
-      .PMPAdr(PMPADDR_ARRAY_REGW),
-      .FirstMatch,
-      .PAgePMPAdrIn({PAgePMPAdr[P.PMP_ENTRIES-2:0], 1'b1}),
-      .PAgePMPAdrOut(PAgePMPAdr),
-      .Match, .PMPTop, .L, .X, .W, .R);
-  end
-
-  priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
-
-  // Distributed AND-OR mux to select the first matching results
-  // If the access does not match all bytes of the PMP region, it is too big and the matches are disabled
-  assign MatchingR = |(R & FirstMatch) & ~TooBig;
-  assign MatchingW = |(W & FirstMatch) & ~TooBig;
-  assign MatchingX = |(X & FirstMatch) & ~TooBig;
-  assign MatchingL = |(L & FirstMatch);
-  or_rows #(P.PMP_ENTRIES, P.PA_BITS) PTEOr(PMPTop, MatchingPMPTop);
-
-  // Matching PMP entry must match all bytes of an access, or the access fails (Priv Spec 3.7.1.3)
-  // First find the size of the access in terms of the offset to the most significant byte
-  always_comb
-    case (Size)
-      2'b00: SizeBytesMinus1 = 3'd0;
-      2'b01: SizeBytesMinus1 = 3'd1;
-      2'b10: SizeBytesMinus1 = 3'd3;
-      2'b11: SizeBytesMinus1 = 3'd7;
-    endcase
-  // Then find the top of the access and see if it is beyond the top of the region
-  assign PhysicalAddressTop = PhysicalAddress + {{P.PA_BITS-3{1'b0}}, SizeBytesMinus1}; // top of the access range
-  assign TooBig = PhysicalAddressTop > MatchingPMPTop; // check if the access goes beyond the top of the PMP region
-
-  // Only enforce PMP checking for effective S and U modes (accounting for mstatus.MPRV) or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (EffectivePrivilegeModeW != P.M_MODE) | MatchingL;
-
-  assign PMPCBOMAccessFault     = EnforcePMP & (|CMOpM[2:0]) & ~MatchingR ; // checking R is sufficient because W implies R in PMP  // exclusion-tag: immu-pmpcbom
-  assign PMPCBOZAccessFault     = EnforcePMP & CMOpM[3] & ~MatchingW ;          // exclusion-tag: immu-pmpcboz
-  assign PMPCMOAccessFault      = PMPCBOZAccessFault | PMPCBOMAccessFault;              // exclusion-tag: immu-pmpcboaccess
-
-  assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~MatchingX ;
-  assign PMPStoreAmoAccessFaultM  = (EnforcePMP & WriteAccessM & ~MatchingW)  | PMPCMOAccessFault; // exclusion-tag: immu-pmpstoreamoaccessfault
-  assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM & ~WriteAccessM & ~MatchingR;
- endmodule
diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv
deleted file mode 100644
index f1f0b0622..000000000
--- a/src/mmu/tlb/tlb.sv
+++ /dev/null
@@ -1,129 +0,0 @@
-///////////////////////////////////////////
-// tlb.sv
-//
-// Written: jtorrey@hmc.edu 16 February 2021
-// Modified: kmacsaigoren@hmc.edu 1 June 2021
-//            Implemented SV48 on top of SV39. This included adding the SvMode signal,
-//            and using it to decide the translate signal and get the virtual page number
-//
-// Purpose: Translation lookaside buffer
-//          Cache of virtural-to-physical address translations
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-/**
- * SV32 specs
- * ----------
- * Virtual address [31:0] (32 bits)
- *    [________________________________]
- *     |--VPN1--||--VPN0--||----OFF---|
- *         10        10         12
- * 
- * Physical address [33:0] (34 bits)
- *  [__________________________________]
- *   |---PPN1---||--PPN0--||----OFF---|
- *        12         10         12
- * 
- * Page Table Entry [31:0] (32 bits)
- *    [________________________________]
- *     |---PPN1---||--PPN0--|||DAGUXWRV
- *          12         10    ^^
- *                         RSW(2) -- for OS
- */
-
-// The TLB will have 2**ENTRY_BITS total entries
-module tlb import cvw::*;  #(parameter cvw_t P,
-                             parameter TLB_ENTRIES = 8, ITLB = 0) (
-  input logic                      clk, reset,
-  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,        // Current address translation mode
-  input  logic [P.ASID_BITS-1:0]   SATP_ASID,
-  input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]               STATUS_MPP,
-  input  logic                     ENVCFG_PBMTE,     // Page-based memory types enabled
-  input  logic                     ENVCFG_ADUE,      // HPTW A/D Update enable
-  input  logic [1:0]               EffectivePrivilegeModeW,   // Current privilege level of the processeor, accounting for mstatus.MPRV
-  input  logic                     ReadAccess, 
-  input  logic                     WriteAccess,
-  input  logic [3:0]               CMOpM,
-  input  logic                     DisableTranslation,
-  input  logic [P.XLEN-1:0]        VAdr,             // address input before translation (could be physical or virtual)
-  input  logic [P.XLEN-1:0]        PTE,              // page table entry to write
-  input  logic [1:0]               PageTypeWriteVal,
-  input  logic                     TLBWrite,
-  input  logic                     TLBFlush,
-  output logic [P.PA_BITS-1:0]     TLBPAdr,
-  output logic                     TLBMiss,
-  output logic                     Translate,
-  output logic                     TLBPageFault,
-  output logic                     UpdateDA,
-  output logic [1:0]               PBMemoryType     // PBMT field of PTE during TLB hit, or 00 otherwise
-);
-
-  logic [TLB_ENTRIES-1:0]         Matches, WriteEnables, PTE_Gs, PTE_NAPOTs; // used as the one-hot encoding of WriteIndex
-  // Sections of the virtual and physical addresses
-  logic [P.VPN_BITS-1:0]          VPN;
-  logic [P.PPN_BITS-1:0]          PPN;
-  // Sections of the page table entry
-  logic [11:0]                    PTEAccessBits;
-  logic [1:0]                     HitPageType;
-  logic                           CAMHit;
-  logic                           TLBHit;
-  logic                           SV39Mode;
-  logic                           Misaligned;
-  logic                           MegapageMisaligned;
-  logic                           PTE_N;         // NAPOT page table entry
-  logic                           NAPOT4;        // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
-
-  if(P.XLEN == 32) begin
-    assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
-    assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned;
-  end else begin // 64-bit
-    logic  GigapageMisaligned, TerapageMisaligned;
-    assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0
-    assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0
-    assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0      
-    assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) | 
-              ((HitPageType == 2'b10) & GigapageMisaligned) | 
-              ((HitPageType == 2'b01) & MegapageMisaligned);
-  end
-
-  assign VPN = VAdr[P.VPN_BITS+11:12];
-  assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
-
-  tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .EffectivePrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation,
-    .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, 
-    .TLBMiss, .TLBHit, .TLBPageFault, 
-    .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);
-
-  tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .Matches, .TLBHit, .WriteEnables);
-  tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS) 
-    tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs,
-           .SATP_ASID, .Matches, .HitPageType, .CAMHit);
-  tlbram #(P, TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs, .PTE_NAPOTs);
-
-  // Replace segments of the virtual page number with segments of the physical
-  // page number. For 4 KB pages, the entire virtual page number is replaced.
-  // For superpages, some segments are considered offsets into a larger page.
-  tlbmixer #(P) Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .PTE_N, .TLBPAdr);
-
-endmodule
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
deleted file mode 100644
index 96184b011..000000000
--- a/src/mmu/tlb/tlbcontrol.sv
+++ /dev/null
@@ -1,127 +0,0 @@
-///////////////////////////////////////////
-// tlbcontrol.sv
-//
-// Written: David_Harris@hmc.edu 5 July 2021
-// Modified: 
-//
-// Purpose: Control signals for TLB
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
-  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
-  input  logic [P.XLEN-1:0]        VAdr,
-  input  logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-  input  logic [1:0]               STATUS_MPP,
-  input  logic                     ENVCFG_PBMTE,       // Page-based memory types enabled
-  input  logic                     ENVCFG_ADUE,        // HPTW A/D Update enable
-  input  logic [1:0]               EffectivePrivilegeModeW,   // Current privilege level of the processeor, accounting for mstatus.MPRV
-  input  logic                     ReadAccess, WriteAccess,
-  input  logic [3:0]               CMOpM,
-  input  logic                     DisableTranslation,
-  input  logic [11:0]              PTEAccessBits,
-  input  logic                     CAMHit,
-  input  logic                     Misaligned,
-  input  logic                     NAPOT4,             // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
-  output logic                     TLBMiss,
-  output logic                     TLBHit,
-  output logic                     TLBPageFault,
-  output logic                     UpdateDA,
-  output logic                     SV39Mode,
-  output logic                     Translate,
-  output logic                     PTE_N,         // NAPOT page table entry
-  output logic [1:0]               PBMemoryType   // PBMT field of PTE during TLB hit, or 00 otherwise
-);
-
-  // Sections of the page table entry
-  logic [1:0]                     PTE_PBMT;
-  logic                           PTE_RESERVED, PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits
-  logic                           UpperBitsUnequal;
-  logic                           TLBAccess;
-  logic                           ImproperPrivilege;
-  logic                           BadPBMT, BadNAPOT, BadReserved;
-  logic                           ReservedRW;
-  logic                           InvalidAccess;
-  logic                           PreUpdateDA, PrePageFault;
-
-  // Grab the sv mode from SATP and determine whether translation should occur
-  assign Translate = (SATP_MODE != P.NO_TRANSLATE[P.SVMODE_BITS-1:0]) & (EffectivePrivilegeModeW != P.M_MODE) & ~DisableTranslation; 
-
-  // Determine whether TLB is being used
-  assign TLBAccess = ReadAccess | WriteAccess | (|CMOpM);
-
-  // Check that upper bits are legal (all 0s or all 1s)
-  vm64check #(P) vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal);
-
-  // unswizzle useful PTE bits
-  assign PTE_N = PTEAccessBits[11];
-  assign PTE_PBMT = PTEAccessBits[10:9];
-  assign PTE_RESERVED = PTEAccessBits[8];
-  assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
-  assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0];
-
-  // Send PMA a 2-bit MemoryType that is PBMT during leaf page table accesses and 0 otherwise
-  assign PBMemoryType = PTE_PBMT & {2{Translate & TLBHit & P.SVPBMT_SUPPORTED}};
- 
-  // check if reserved, N, or PBMT bits are malformed w in RV64
-  assign BadPBMT = ((PTE_PBMT != 0) & ~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE)) | PTE_PBMT == 3; // PBMT must be zero if not supported; value of 3 is reserved
-  assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4);              // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region
-  assign BadReserved = PTE_RESERVED;                                       // Reserved bits must be zero
-  assign ReservedRW = PTE_W & ~PTE_R;                                      // page fault on reserved encoding with R=0, W=1 per Privileged Spec 10.3.1
- 
-  // Check whether the access is allowed, page faulting if not.
-  if (ITLB == 1) begin:itlb // Instruction TLB fault checking
-    // User mode may only execute user mode pages, and supervisor mode may
-    // only execute non-user mode pages.
-    assign ImproperPrivilege = ((EffectivePrivilegeModeW == P.U_MODE) & ~PTE_U) | ((EffectivePrivilegeModeW == P.S_MODE) & PTE_U);
-    assign PreUpdateDA = ~PTE_A;
-    assign InvalidAccess = ~PTE_X | ReservedRW;
- end else begin:dtlb // Data TLB fault checking
-    logic InvalidRead, InvalidWrite;
-    logic InvalidCBOM, InvalidCBOZ;
-
-    // User mode may only load/store from user mode pages, and supervisor mode
-    // may only access user mode pages when STATUS_SUM is low.
-    assign ImproperPrivilege = ((EffectivePrivilegeModeW == P.U_MODE) & ~PTE_U) |
-      ((EffectivePrivilegeModeW == P.S_MODE) & PTE_U & ~STATUS_SUM);
-    // Check for read error. Reads are invalid when the page is not readable
-    // (and executable pages are not readable) or when the page is neither
-    // readable nor executable (and executable pages are readable).
-    assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X);
-    // Check for write error. Writes are invalid when the page's write bit is 0.
-    assign InvalidWrite = WriteAccess & ~PTE_W;
-    assign InvalidCBOM = (|CMOpM[2:0]) & (~PTE_R & (~STATUS_MXR | ~PTE_X));
-    assign InvalidCBOZ = CMOpM[3] & ~PTE_W;
-    assign InvalidAccess = InvalidRead | InvalidWrite | InvalidCBOM | InvalidCBOZ | ReservedRW;
-    assign PreUpdateDA = ~PTE_A | WriteAccess & ~PTE_D;
-  end
-
-  // Determine wheter to update DA bits.  With SVADU, it is done in hardware
-  assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_ADUE;
-
-  // Determine whether page fault occurs
-  assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_ADUE));
-  assign TLBPageFault = Translate & TLBHit & (PrePageFault | InvalidAccess);
-
-  assign TLBHit = CAMHit & TLBAccess;
-  assign TLBMiss = ~CAMHit & TLBAccess & Translate ;
-endmodule
diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv
deleted file mode 100644
index 0b3e3994a..000000000
--- a/src/mmu/tlb/tlbramline.sv
+++ /dev/null
@@ -1,54 +0,0 @@
-///////////////////////////////////////////
-// tlbramline.sv
-//
-// Written: David_Harris@hmc.edu 4 July 2021
-// Modified:
-//
-// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module tlbramline import cvw::*;  #(parameter cvw_t P)
-  (input  logic              clk, reset,
-   input  logic              re, we,
-   input  logic [P.XLEN-1:0] d,
-   output logic [P.XLEN-1:0] q,
-   output logic              PTE_G,
-   output logic              PTE_NAPOT // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
-);
-
-   logic [P.XLEN-1:0] line;
-
-  if (P.XLEN == 64) begin // save 7 reserved bits
-    // could optimize out N and PBMT from d[63:61] if they aren't supported
-    logic [57:0] ptereg;
-    logic reserved;
-    assign reserved = |d[60:54]; // are any of the reserved bits nonzero?
-    flopenr #(58) pteflop(clk, reset, we, {d[63:61], reserved, d[53:0]}, ptereg);
-    assign line = {ptereg[57:54], 6'b0, ptereg[53:0]};
-  end else // rv32
-    flopenr #(P.XLEN) pteflop(clk, reset, we, d, line);
-
-   assign q = re ? line : 0;
-   assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching
-   assign PTE_NAPOT = P.SVNAPOT_SUPPORTED & line[P.XLEN-1] & (line[13:10] == 4'b1000); // send NAPOT bit to CAM as part of matching lsbs of VPN
-endmodule
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
deleted file mode 100644
index ad3dab32d..000000000
--- a/src/privileged/csr.sv
+++ /dev/null
@@ -1,316 +0,0 @@
-///////////////////////////////////////////
-// csr.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//          dottolia@hmc.edu 7 April 2021
-//
-// Purpose: Counter Control and Status Registers
-//          See RISC-V Privileged Mode Specification 20190608 
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csr import cvw::*;  #(parameter cvw_t P) (
-  input  logic                     clk, reset,
-  input  logic                     FlushM, FlushW,
-  input  logic                     StallE, StallM, StallW,
-  input  logic [31:0]              InstrM,                    // current instruction
-  input  logic [31:0]              InstrOrigM,                // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [P.XLEN-1:0]        PCM,                       // program counter, next PC going to trap/return logic
-  input  logic [P.XLEN-1:0]        SrcAM, IEUAdrM,            // SrcA and memory address from IEU
-  input  logic                     CSRReadM, CSRWriteM,       // read or write CSR
-  input  logic                     TrapM,                     // trap is occurring
-  input  logic                     mretM, sretM,              // return instruction
-  input  logic                     InterruptM,                // interrupt is occurring
-  input  logic                     ExceptionM,                // interrupt is occurring
-  input  logic                     MTimerInt,                 // timer interrupt
-  input  logic                     MExtInt, SExtInt,          // external interrupt (from PLIC) 
-  input  logic                     MSwInt,                    // software interrupt
-  input  logic [63:0]              MTIME_CLINT,               // TIME value from CLINT
-  input  logic                     InstrValidM,               // current instruction is valid
-  input  logic                     FRegWriteM,                // writes to floating point registers change STATUS.FS
-  input  logic [4:0]               SetFflagsM,                // Set floating point flag bits in FCSR
-  input  logic [1:0]               NextPrivilegeModeM,        // STATUS bits updated based on next privilege mode
-  input  logic [1:0]               PrivilegeModeW,            // current privilege mode
-  input  logic [3:0]               CauseM,                    // Trap cause
-  input  logic                     SelHPTW,                   // hardware page table walker active, so base endianness on supervisor mode
-  // inputs for performance counters
-  input  logic                     LoadStallD, StoreStallD, 
-  input  logic                     ICacheStallF,
-  input  logic                     DCacheStallM,
-  input  logic                     BPDirWrongM,
-  input  logic                     BTAWrongM,
-  input  logic                     RASPredPCWrongM,
-  input  logic                     IClassWrongM,
-  input  logic                     BPWrongM,                  // branch predictor is wrong
-  input  logic [3:0]               IClassM,
-  input  logic                     DCacheMiss,
-  input  logic                     DCacheAccess,
-  input  logic                     ICacheMiss,
-  input  logic                     ICacheAccess,
-  input  logic                     sfencevmaM,
-  input  logic                     InvalidateICacheM,
-  input  logic                     DivBusyE,                  // integer divide busy
-  input  logic                     FDivBusyE,                 // floating point divide busy
-  // outputs from CSRs
-  output logic [1:0]               STATUS_MPP,
-  output logic                     STATUS_SPP, STATUS_TSR, STATUS_TVM,
-  output logic [15:0]              MEDELEG_REGW, 
-  output logic [P.XLEN-1:0]        SATP_REGW,
-  output logic [11:0]              MIP_REGW, MIE_REGW, MIDELEG_REGW,
-  output logic                     STATUS_MIE, STATUS_SIE,
-  output logic                     STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW,
-  output logic [1:0]               STATUS_FS,
-  output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
-  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],
-  output logic [2:0]               FRM_REGW, 
-  output logic [3:0]               ENVCFG_CBE,
-  output logic                     ENVCFG_PBMTE,              // Page-based memory type enable
-  output logic                     ENVCFG_ADUE,               // HPTW A/D Update enable
-  // PC logic output from privileged unit to IFU                                  
-  output logic [P.XLEN-1:0]        EPCM,                      // Exception Program counter to IFU PC logic
-  output logic [P.XLEN-1:0]        TrapVectorM,               // Trap vector, to IFU PC logic
-  //
-  output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
-  output logic                     IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
-  output logic                     BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
-);
-
-  localparam MIP = 12'h344;
-  localparam SIP = 12'h144;
-  
-  logic [P.XLEN-1:0]       CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
-  logic [P.XLEN-1:0]       CSRReadValM;  
-  logic [P.XLEN-1:0]       CSRSrcM;
-  logic [P.XLEN-1:0]       CSRRWM, CSRRSM, CSRRCM;  
-  logic [P.XLEN-1:0]       CSRWriteValM;
-  logic [P.XLEN-1:0]       MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
-  logic [P.XLEN-1:0]       STVEC_REGW, MTVEC_REGW;
-  logic [P.XLEN-1:0]       MEPC_REGW, SEPC_REGW;
-  logic [31:0]             MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
-  logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
-  logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
-  logic                    UngatedCSRMWriteM;
-  logic                    WriteFRMM, SetOrWriteFFLAGSM;
-  logic [P.XLEN-1:0]       UnalignedNextEPCM, NextEPCM, NextMtvalM;
-  logic [4:0]              NextCauseM;
-  logic [11:0]             CSRAdrM;
-  logic                    IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
-  logic                    InsufficientCSRPrivilegeM;
-  logic                    IllegalCSRMWriteReadonlyM;
-  logic [P.XLEN-1:0]       CSRReadVal2M;
-  logic [11:0]             MIP_REGW_writeable;
-  logic [P.XLEN-1:0]       TVecM,NextFaultMtvalM;
-  logic                    MTrapM, STrapM;
-  logic                    SelMtvecM;
-  logic [P.XLEN-1:0]       TVecAlignedM;
-  logic                    InstrValidNotFlushedM;
-  logic                    STimerInt;
-  logic [63:0]             MENVCFG_REGW;
-  logic [P.XLEN-1:0]       SENVCFG_REGW;
-  logic                    ENVCFG_STCE; // supervisor timer counter enable
-  logic                    ENVCFG_FIOM; // fence implies io (presently not used)
-
-  // only valid unflushed instructions can access CSRs
-  assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
-
-  ///////////////////////////////////////////
-  // MTVAL: gets value from PC, Instruction, or load/store address
-  ///////////////////////////////////////////
-
-  always_comb
-    if (InterruptM)           NextFaultMtvalM = '0;
-    else case (CauseM)
-      12, 1, 3:               NextFaultMtvalM = PCM;  // Instruction page/access faults, breakpoint
-      2:                      NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 
-      0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
-      default:                NextFaultMtvalM = '0; // Ecall, interrupts
-    endcase
-
-  ///////////////////////////////////////////
-  // Trap Vectoring & Returns; vectored traps must be aligned to 64-byte address boundaries
-  ///////////////////////////////////////////
-
-  // Select trap vector from STVEC or MTVEC and word-align
-  assign SelMtvecM = (NextPrivilegeModeM == P.M_MODE);
-  mux2 #(P.XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM);
-  assign TVecAlignedM = {TVecM[P.XLEN-1:2], 2'b00};
-
-  // Support vectored interrupts
-  if(P.VECTORED_INTERRUPTS_SUPPORTED) begin:vec
-    logic VectoredM;
-    logic [P.XLEN-1:0] TVecPlusCauseM;
-    assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01);
-    assign TVecPlusCauseM = {TVecAlignedM[P.XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition
-    mux2 #(P.XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM);
-  end else 
-    assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd
-
-  // Trap Returns
-  // A trap sets the PC to TrapVector
-  // A return sets the PC to MEPC or SEPC
-  mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
-
-  ///////////////////////////////////////////
-  // CSRWriteValM
-  ///////////////////////////////////////////
-
-  always_comb begin
-    // Choose either rs1 or uimm[4:0] as source
-    CSRSrcM = InstrM[14] ? {{(P.XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
-
-    // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
-    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(P.XLEN-12){1'b0}}, MIP_REGW_writeable};
-    else                                 CSRReadVal2M = CSRReadValM;
-
-    // Compute AND/OR modification
-    CSRRWM =   CSRSrcM;
-    CSRRSM =   CSRReadVal2M | CSRSrcM;
-    CSRRCM =   CSRReadVal2M & ~CSRSrcM;
-    case (InstrM[13:12])
-      2'b01:   CSRWriteValM = CSRRWM;
-      2'b10:   CSRWriteValM = CSRRSM;
-      2'b11:   CSRWriteValM = CSRRCM;
-      default: CSRWriteValM = CSRReadValM;
-    endcase
-  end
-
-  ///////////////////////////////////////////
-  // CSR Write values
-  ///////////////////////////////////////////
-
-  assign CSRAdrM = InstrM[31:20];
-  assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
-  assign NextEPCM = P.ZCA_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
-  assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
-  assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
-  assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);
-  assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
-  assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
-  assign MTrapM = TrapM & (NextPrivilegeModeM == P.M_MODE);
-  assign STrapM = TrapM & (NextPrivilegeModeM == P.S_MODE) & P.S_SUPPORTED;
-
-  ///////////////////////////////////////////
-  // CSRs
-  ///////////////////////////////////////////
-
-  csri #(P) csri(.clk, .reset,  
-    .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
-    .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
-    .MIDELEG_REGW, .ENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
-
-  csrsr #(P) csrsr(.clk, .reset, .StallW, 
-    .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
-    .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
-    .mretM, .sretM, .WriteFRMM, .SetOrWriteFFLAGSM, .CSRWriteValM, .SelHPTW,
-    .MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
-    .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
-    .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
-    .STATUS_FS, .BigEndianM);
-
-  csrm #(P) csrm(.clk, .reset, 
-    .UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM,
-    .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
-    .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
-    .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, 
-    .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
-    .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
-    .MENVCFG_REGW);
-
-
-  if (P.S_SUPPORTED) begin:csrs
-    logic STCE; 
-    assign STCE = P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_REGW[1] & ENVCFG_STCE));
-    csrs #(P) csrs(.clk, .reset,
-      .CSRSWriteM, .STrapM, .CSRAdrM,
-      .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
-      .STATUS_TVM, 
-      .CSRWriteValM, .PrivilegeModeW,
-      .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
-      .SCOUNTEREN_REGW,
-      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE,
-      .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW);
-  end else begin
-    assign WriteSSTATUSM = 1'b0;
-    assign CSRSReadValM = '0;
-    assign SEPC_REGW = '0;
-    assign STVEC_REGW = '0;
-    assign SCOUNTEREN_REGW = '0;
-    assign SATP_REGW = '0;
-    assign IllegalCSRSAccessM = 1'b1;
-    assign STimerInt = '0;
-    assign SENVCFG_REGW = '0;
-  end
-
-  // Floating Point CSRs in User Mode only needed if Floating Point is supported
-  if (P.F_SUPPORTED) begin:csru
-    csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, 
-      .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
-      .SetFflagsM, .FRM_REGW, .WriteFRMM, .SetOrWriteFFLAGSM,
-      .IllegalCSRUAccessM);
-  end else begin
-    assign FRM_REGW = '0;
-    assign CSRUReadValM = '0;
-    assign IllegalCSRUAccessM = 1'b1;
-    assign WriteFRMM = 1'b0;
-    assign SetOrWriteFFLAGSM = 1'b0;
-  end
-  
-  if (P.ZICNTR_SUPPORTED) begin:counters
-    csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
-      .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
-      .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
-      .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
-      .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
-      .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
-      .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
-      .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
-  end else begin
-    assign CSRCReadValM = '0;
-    assign IllegalCSRCAccessM = 1'b1; // counters aren't enabled
-  end
-
-   // Broadcast appropriate environment configuration based on privilege mode
-  assign ENVCFG_STCE =  MENVCFG_REGW[63]; // supervisor timer counter enable
-  assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
-  assign ENVCFG_ADUE  = MENVCFG_REGW[61]; // Hardware A/D Update enable
-  assign ENVCFG_CBE =   (PrivilegeModeW == P.M_MODE) ? 4'b1111 : 
-                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : 
-                                                                       (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);
-  // FIOM presently doesn't do anything because Wally fences don't do anything
-  assign ENVCFG_FIOM =  (PrivilegeModeW == P.M_MODE) ? 1'b1 : 
-                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : 
-                                                                       (MENVCFG_REGW[0] & SENVCFG_REGW[0]);
-
-  // merge CSR Reads
-  assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; 
-  flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
-
-  // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
-  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
-                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);
-  assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & 
-    IllegalCSRSAccessM & IllegalCSRUAccessM |
-    InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
-endmodule
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
deleted file mode 100644
index ccbb6b793..000000000
--- a/src/privileged/csrc.sv
+++ /dev/null
@@ -1,201 +0,0 @@
-///////////////////////////////////////////
-// csrc.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Counter CSRs
-//          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csrc  import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  input  logic              StallE, StallM, 
-  input  logic              FlushM, 
-  input  logic              InstrValidNotFlushedM, LoadStallD, StoreStallD,
-  input  logic              CSRMWriteM, CSRWriteM,
-  input  logic              BPDirWrongM,
-  input  logic              BTAWrongM,
-  input  logic              RASPredPCWrongM,
-  input  logic              IClassWrongM,
-  input  logic              BPWrongM,                                  // branch predictor is wrong
-  input  logic [3:0]        IClassM,
-  input  logic              DCacheMiss,
-  input  logic              DCacheAccess,
-  input  logic              ICacheMiss,
-  input  logic              ICacheAccess,
-  input  logic              ICacheStallF,
-  input  logic              DCacheStallM,
-  input  logic              sfencevmaM,
-  input  logic              InterruptM,
-  input  logic              ExceptionM,
-  input  logic              InvalidateICacheM,
-  input  logic              DivBusyE,                                  // integer divide busy
-  input  logic              FDivBusyE,                                 // floating point divide busy
-  input  logic [11:0]       CSRAdrM,
-  input  logic [1:0]        PrivilegeModeW,
-  input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic [31:0]       MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
-  input  logic [63:0]       MTIME_CLINT, 
-  output logic [P.XLEN-1:0] CSRCReadValM,
-  output logic              IllegalCSRCAccessM
-);
-
-  localparam MHPMCOUNTERBASE  = 12'hB00;
-  localparam MTIME            = 12'hB01;               // this is a memory-mapped register; no such CSR exists, and access should faul;
-  localparam MHPMCOUNTERHBASE = 12'hB80;
-  localparam MTIMEH           = 12'hB81;               // this is a memory-mapped register; no such CSR exists, and access should fault
-  localparam MHPMEVENTBASE    = 12'h323;
-  localparam MHPMEVENTLAST    = 12'h33F;
-  localparam HPMCOUNTERBASE   = 12'hC00;
-  localparam HPMCOUNTERHBASE  = 12'hC80;
-  localparam TIME             = 12'hC01;
-  localparam TIMEH            = 12'hC81;
-
-  logic [4:0]              CounterNumM;
-  logic [P.XLEN-1:0]       HPMCOUNTER_REGW[P.COUNTERS-1:0];
-  logic [P.XLEN-1:0]       HPMCOUNTERH_REGW[P.COUNTERS-1:0];
-  logic                    LoadStallE, LoadStallM;
-  logic                    StoreStallE, StoreStallM;
-  logic [P.COUNTERS-1:0]   WriteHPMCOUNTERM;
-  logic [P.COUNTERS-1:0]   CounterEvent;
-  logic [63:0]             HPMCOUNTERPlusM[P.COUNTERS-1:0];
-  logic [P.XLEN-1:0]       NextHPMCOUNTERM[P.COUNTERS-1:0];
-  genvar                   i;
-
-  // Interface signals
-  flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE));  // don't flush the load stall during a load stall.
-  flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));  
-
-  flopenrc #(1) StoreStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(StoreStallD), .q(StoreStallE));  // don't flush the load stall during a load stall.
-  flopenrc #(1) StoreStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(StoreStallE), .q(StoreStallM));  
-  
-  // Determine when to increment each counter
-  assign CounterEvent[0]    = 1'b1;                                                      // MCYCLE always increments
-  assign CounterEvent[1]    = 1'b0;                                                      // Counter 1 doesn't exist
-  assign CounterEvent[2]    = InstrValidNotFlushedM;                                     // MINSTRET instructions retired
-  if (P.ZIHPM_SUPPORTED) begin: cevent                                                   // User-defined counters
-    // Ideally all events would be counted in the M stage, but the pipelining is costly. The counters may
-    // count an event in a previous pipeline stage.
-    assign CounterEvent[3]  = IClassM[0] & InstrValidNotFlushedM;                        // branch instruction
-    assign CounterEvent[4]  = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM;          // jump and not return instructions
-    assign CounterEvent[5]  = IClassM[2] & InstrValidNotFlushedM;                        // return instructions
-    assign CounterEvent[6]  = BPWrongM & InstrValidNotFlushedM;                          // branch predictor wrong
-    assign CounterEvent[7]  = BPDirWrongM & InstrValidNotFlushedM;                       // Branch predictor wrong direction
-    assign CounterEvent[8]  = BTAWrongM & InstrValidNotFlushedM;                         // branch predictor wrong target
-    assign CounterEvent[9]  = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
-    assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
-    assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[12] = StoreStallM;                                               // Store Stall
-    assign CounterEvent[13] = DCacheAccess;                                              // data cache access
-    assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[15] = DCacheStallM;                                              // D$ miss cycles
-    assign CounterEvent[16] = ICacheAccess;                                              // instruction cache access
-    assign CounterEvent[17] = ICacheMiss;                                                // instruction cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[18] = ICacheStallF;                                              // I$ miss cycles
-    assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                         // CSR writes
-    assign CounterEvent[20] = InvalidateICacheM & InstrValidNotFlushedM;                 // fence.i
-    assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                        // sfence.vma
-    assign CounterEvent[22] = InterruptM;                                                // interrupt, InstrValidNotFlushedM will be low
-    assign CounterEvent[23] = ExceptionM;                                                // exceptions, InstrValidNotFlushedM will be low
-    // coverage off
-    // DivBusyE will never be asserted high because the RV64GC configuration uses the FPU to do integer division
-    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles
-    // coverage on
-    assign CounterEvent[P.COUNTERS-1:25] = '0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
-  end else begin: cevent
-    assign CounterEvent[P.COUNTERS-1:3] = '0;
-  end
-  
-  // Counter update and write logic
-  for (i = 0; $unsigned(i) < P.COUNTERS; i = i+1) begin:cntr
-      assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i); // coverage tag: MTIME traps
-      assign NextHPMCOUNTERM[i][P.XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][P.XLEN-1:0];
-      always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-        if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= '0;
-        else       HPMCOUNTER_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERM[i];
-
-      if (P.XLEN==32) begin // write high and low separately
-        logic [P.COUNTERS-1:0] WriteHPMCOUNTERHM;
-        logic [P.XLEN-1:0] NextHPMCOUNTERHM[P.COUNTERS-1:0];
-        assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
-        assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
-        assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
-        always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-            if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= '0;
-            else       HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERHM[i];
-      end else begin // XLEN=64; write entire register
-          assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
-          assign HPMCOUNTERH_REGW[i] = '0; // disregard for RV64
-      end
-  end
-
-  // Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
-  assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
-  always_comb 
-    if (PrivilegeModeW == P.M_MODE | 
-        MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
-      IllegalCSRCAccessM = 1'b0;
-      if (CSRAdrM >= MHPMEVENTBASE & CSRAdrM <= MHPMEVENTLAST) begin
-        CSRCReadValM = '0; // mphmevent[3:31] tied to read-only zero
-      end else begin
-        if (P.XLEN==64) begin // 64-bit counter reads
-          // Veri lator doesn't realize this only occurs for XLEN=64
-          /* verilator lint_off WIDTH */  
-          if      (CSRAdrM == TIME & ~CSRWriteM)  CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
-          /* verilator lint_on WIDTH */  
-          else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) 
-                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-          else if (CSRAdrM >= HPMCOUNTERBASE  & CSRAdrM  < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM)  // read-only
-                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-          else begin
-              CSRCReadValM = '0;
-              IllegalCSRCAccessM = 1'b1;  // requested CSR doesn't exist
-          end
-        end else begin // 32-bit counter reads
-          // Veril ator doesn't realize this only occurs for XLEN=32
-          /* verilator lint_off WIDTH */  
-          if      (CSRAdrM == TIME & ~CSRWriteM)  CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
-          else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32];
-          /* verilator lint_on WIDTH */  
-          else if (CSRAdrM >= MHPMCOUNTERBASE  & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME)   
-                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-          else if (CSRAdrM >= HPMCOUNTERBASE   & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS  & ~CSRWriteM)    // read-only
-                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
-          else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH)  
-                  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
-          else if (CSRAdrM >= HPMCOUNTERHBASE  & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS  & ~CSRWriteM)   // read-only
-                  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
-          else begin
-            CSRCReadValM = '0;
-            IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist
-          end            
-        end
-      end
-    end else begin 
-      CSRCReadValM = '0;
-      IllegalCSRCAccessM = 1'b1; // no privileges for this csr
-    end
-endmodule
-
-//  mounteren should only exist if u-mode exists
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
deleted file mode 100644
index aac5be917..000000000
--- a/src/privileged/csrm.sv
+++ /dev/null
@@ -1,266 +0,0 @@
-///////////////////////////////////////////
-// csrm.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//          dottolia@hmc.edu 7 April 2021
-//
-// Purpose: Machine-Mode Control and Status Registers
-//          See RISC-V Privileged Mode Specification 20190608 
-// Note: the CSRs do not support the following optional features
-//   - Disabling portions of the instruction set with bits of the MISA register
-//   - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csrm  import cvw::*;  #(parameter cvw_t P) (
-  input  logic                     clk, reset, 
-  input  logic                     UngatedCSRMWriteM, CSRMWriteM, MTrapM,
-  input  logic [11:0]              CSRAdrM,
-  input  logic [P.XLEN-1:0]        NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
-  input  logic [4:0]               NextCauseM,
-  input  logic [P.XLEN-1:0]        CSRWriteValM,
-  input  logic [11:0]              MIP_REGW, MIE_REGW,
-  output logic [P.XLEN-1:0]        CSRMReadValM, MTVEC_REGW,
-  output logic [P.XLEN-1:0]        MEPC_REGW,    
-  output logic [31:0]              MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-  output logic [15:0]              MEDELEG_REGW,
-  output logic [11:0]              MIDELEG_REGW,
-  /* verilator lint_off UNDRIVEN */ // PMP registers are only used when PMP_ENTRIES > 0
-  output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
-  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
-  /* verilator lint_on UNDRIVEN */
-  output logic                     WriteMSTATUSM, WriteMSTATUSHM,
-  output logic                     IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
-  output logic [63:0]              MENVCFG_REGW
-);
-
-  logic [P.XLEN-1:0]               MISA_REGW, MHARTID_REGW;
-  logic [P.XLEN-1:0]               MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
-  logic [P.XLEN-1:0]               MENVCFGH_REGW;
-  logic [P.XLEN-1:0]               TVECWriteValM;
-  logic                            WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
-  logic                            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
-  logic                            WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
-
-  // Machine CSRs
-  localparam MVENDORID     = 12'hF11;
-  localparam MARCHID       = 12'hF12; // github.com/riscv/riscv-isa-manual/blob/main/marchid.md
-  localparam MIMPID        = 12'hF13;
-  localparam MHARTID       = 12'hF14;
-  localparam MCONFIGPTR    = 12'hF15;
-  localparam MSTATUS       = 12'h300;
-  localparam MISA_ADR      = 12'h301;
-  localparam MEDELEG       = 12'h302;
-  localparam MIDELEG       = 12'h303;
-  localparam MIE           = 12'h304;
-  localparam MTVEC         = 12'h305;
-  localparam MCOUNTEREN    = 12'h306;
-  localparam MENVCFG       = 12'h30A;
-  localparam MSTATUSH      = 12'h310;
-  localparam MENVCFGH      = 12'h31A;
-  localparam MCOUNTINHIBIT = 12'h320;
-  localparam MSCRATCH      = 12'h340;
-  localparam MEPC          = 12'h341;
-  localparam MCAUSE        = 12'h342;
-  localparam MTVAL         = 12'h343;
-  localparam MIP           = 12'h344;
-  localparam PMPCFG0       = 12'h3A0;
-  // .. up to 15 more at consecutive addresses
-  localparam PMPADDR0      = 12'h3B0;
-  // ... up to 63 more at consecutive addresses
-  /* verilator lint_off UNUSEDPARAM */
-  localparam TSELECT       = 12'h7A0;
-  localparam TDATA1        = 12'h7A1;
-  localparam TDATA2        = 12'h7A2;
-  localparam TDATA3        = 12'h7A3;
-  localparam DCSR          = 12'h7B0;
-  localparam DPC           = 12'h7B1;
-  localparam DSCRATCH0     = 12'h7B2;
-  localparam DSCRATCH1     = 12'h7B3;
-  /* verilator lint_off UNUSEDPARAM */
-  // Constants
-  localparam ZERO = {(P.XLEN){1'b0}};
-  // when compressed instructions are supported, there can't be misaligned instructions
-  localparam MEDELEG_MASK  = P.ZCA_SUPPORTED ? 16'hB3FE : 16'hB3FF;
-  localparam MIDELEG_MASK  = 12'h222; // we choose to not make machine interrupts delegable
-
- // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
-  genvar i;
-  if (P.PMP_ENTRIES > 0) begin:pmp
-    logic [P.PMP_ENTRIES-1:0] WritePMPCFGM;
-    logic [P.PMP_ENTRIES-1:0] WritePMPADDRM; 
-    logic [7:0]               CSRPMPWriteValM[P.PMP_ENTRIES-1:0];
-    logic [7:0]               CSRPMPLegalizedWriteValM[P.PMP_ENTRIES-1:0];
-    logic [1:0]               CSRPMPWRLegalizedWriteValM[P.PMP_ENTRIES-1:0]; 
-    logic [P.PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
-    for(i=0; i<P.PMP_ENTRIES; i++) begin
-      // when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
-      // also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
-      assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
-      if (i == P.PMP_ENTRIES-1) 
-        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
-      else
-        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
-
-      assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~ADDRLocked[i];
-      flopenr #(P.PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[P.PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]);
-      if (P.XLEN==64) begin
-        assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~CFGLocked[i];
-        assign CSRPMPWriteValM[i] = CSRWriteValM[(i%8)*8+7:(i%8)*8];
-      end else begin
-        assign WritePMPCFGM[i]  = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~CFGLocked[i];
-        assign CSRPMPWriteValM[i] = CSRWriteValM[(i%4)*8+7:(i%4)*8];
-      end
-
-      assign CSRPMPWRLegalizedWriteValM[i] = {(CSRPMPWriteValM[i][1] & CSRPMPWriteValM[i][0]), CSRPMPWriteValM[i][0]}; // legalize WR fields (reserved 10 written as 00)
-      assign CSRPMPLegalizedWriteValM[i] = {CSRPMPWriteValM[i][7], 2'b00, CSRPMPWriteValM[i][4:2], CSRPMPWRLegalizedWriteValM[i]};
-      flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRPMPLegalizedWriteValM[i], PMPCFG_ARRAY_REGW[i]);
-    end
-  end
-
-  localparam MISA_26 = $unsigned(P.MISA) & 32'h03ffffff;
-
-  // MISA is hardwired.  Spec says it could be written to disable features, but this is not supported by Wally
-  assign MISA_REGW = {(P.XLEN == 32 ? 2'b01 : 2'b10), {(P.XLEN-28){1'b0}}, MISA_26[25:0]};
-
-  // MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
-  assign MHARTID_REGW = '0;
-
-  // Write machine Mode CSRs 
-  assign WriteMSTATUSM       = CSRMWriteM & (CSRAdrM == MSTATUS);
-  assign WriteMSTATUSHM      = CSRMWriteM & (CSRAdrM == MSTATUSH) & (P.XLEN==32);
-  assign WriteMTVECM         = CSRMWriteM & (CSRAdrM == MTVEC);
-  assign WriteMEDELEGM       = CSRMWriteM & (CSRAdrM == MEDELEG);
-  assign WriteMIDELEGM       = CSRMWriteM & (CSRAdrM == MIDELEG);
-  assign WriteMSCRATCHM      = CSRMWriteM & (CSRAdrM == MSCRATCH);
-  assign WriteMEPCM          = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC));
-  assign WriteMCAUSEM        = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
-  assign WriteMTVALM         = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
-  assign WriteMCOUNTERENM    = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
-  assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
-
-  assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID | CSRAdrM == MCONFIGPTR);
-
-  // CSRs
-  assign TVECWriteValM = CSRWriteValM[0] ? {CSRWriteValM[P.XLEN-1:6], 6'b000001} : {CSRWriteValM[P.XLEN-1:2], 2'b00};
-  flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, TVECWriteValM, MTVEC_REGW); 
-  if (P.S_SUPPORTED) begin:deleg // DELEG registers should exist
-    flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW);
-    flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW);
-  end else assign {MEDELEG_REGW, MIDELEG_REGW} = '0;
-
-  flopenr #(P.XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
-  flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
-  flopenr #(P.XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
-  flopenr #(P.XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, {CSRWriteValM[31:2], 1'b0, CSRWriteValM[0]}, MCOUNTINHIBIT_REGW);
-  if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
-    flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
-  end else assign MCOUNTEREN_REGW = '0;
-
-  // MENVCFG register
-  if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
-    logic WriteMENVCFGM;
-    logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
-    logic [1:0] LegalizedCBIE;
-    assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
-    assign LegalizedCBIE = MENVCFG_PreWriteValM[5:4] == 2'b10 ? MENVCFG_REGW[5:4] : MENVCFG_PreWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value
-    // MENVCFG is always 64 bits even for RV32
-    assign MENVCFG_WriteValM = {
-      MENVCFG_PreWriteValM[63]  & P.SSTC_SUPPORTED,
-      MENVCFG_PreWriteValM[62]  & P.SVPBMT_SUPPORTED,
-      MENVCFG_PreWriteValM[61]  & P.SVADU_SUPPORTED,
-      53'b0,
-      MENVCFG_PreWriteValM[7]   & P.ZICBOZ_SUPPORTED,
-      MENVCFG_PreWriteValM[6]   & P.ZICBOM_SUPPORTED,
-      LegalizedCBIE             & {2{P.ZICBOM_SUPPORTED}},
-      3'b0,
-      MENVCFG_PreWriteValM[0]   & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
-    };
-    if (P.XLEN == 64) begin
-      assign MENVCFG_PreWriteValM = CSRWriteValM;
-      flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
-      assign MENVCFGH_REGW = '0;
-    end else begin // RV32 has high and low halves
-      logic WriteMENVCFGHM;
-      assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
-      assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
-      flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]);
-      flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
-      assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
-    end
-  end else begin
-    assign MENVCFG_REGW = '0;
-    assign MENVCFGH_REGW = '0;
-  end
-
-  // Read machine mode CSRs
-  // verilator lint_off WIDTH
-  logic [5:0] entry;
-  always_comb begin
-    entry = '0;
-    CSRMReadValM = '0;
-    IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
-    if ($unsigned(CSRAdrM) >= PMPADDR0 & $unsigned(CSRAdrM) < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry
-      CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
-    else if ($unsigned(CSRAdrM) >= PMPCFG0 & $unsigned(CSRAdrM) < PMPCFG0 + P.PMP_ENTRIES/4 & (P.XLEN==32 | CSRAdrM[0] == 0)) begin
-      // only odd-numbered PMPCFG entries exist in RV64
-      if (P.XLEN==64) begin
-        entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
-        CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],
-                        PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
-      end else begin
-        entry = (CSRAdrM - PMPCFG0)*4;
-        CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
-      end
-    end
-    else case (CSRAdrM) 
-      MISA_ADR:      CSRMReadValM = MISA_REGW;
-      MVENDORID:     CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h0000_0602}; // OpenHW JEDEC
-      MARCHID:       CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally 
-      MIMPID:        CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
-      MHARTID:       CSRMReadValM = MHARTID_REGW; // hardwired to 0 
-      MCONFIGPTR:    CSRMReadValM = '0; // hardwired to 0
-      MSTATUS:       CSRMReadValM = MSTATUS_REGW;
-      MSTATUSH:      if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; 
-                     else IllegalCSRMAccessM = 1'b1;
-      MTVEC:         CSRMReadValM = MTVEC_REGW;
-      MEDELEG:       CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW};
-      MIDELEG:       CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW};
-      MIP:           CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIP_REGW};
-      MIE:           CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIE_REGW};
-      MSCRATCH:      CSRMReadValM = MSCRATCH_REGW;
-      MEPC:          CSRMReadValM = MEPC_REGW;
-      MCAUSE:        CSRMReadValM = MCAUSE_REGW;
-      MTVAL:         CSRMReadValM = MTVAL_REGW;
-      MCOUNTEREN:    CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
-      MENVCFG:       if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
-                     else IllegalCSRMAccessM = 1'b1;
-      MENVCFGH:      if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
-                     else IllegalCSRMAccessM = 1'b1;
-      MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
-      default:       IllegalCSRMAccessM = 1'b1;
-    endcase
-  end
-  // verilator lint_on WIDTH
-endmodule
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
deleted file mode 100644
index c30f78e14..000000000
--- a/src/privileged/csrs.sv
+++ /dev/null
@@ -1,179 +0,0 @@
-///////////////////////////////////////////
-// csrs.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//          dottolia@hmc.edu 3 May 2021 - fix bug with stvec getting wrong value
-//
-// Purpose: Supervisor-Mode Control and Status Registers
-//          See RISC-V Privileged Mode Specification 20190608 
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csrs import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset, 
-  input  logic              CSRSWriteM, STrapM,
-  input  logic [11:0]       CSRAdrM,
-  input  logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, 
-  input  logic [4:0]        NextCauseM,
-  input  logic              STATUS_TVM,
-  input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic [1:0]        PrivilegeModeW,
-  output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
-  output logic [P.XLEN-1:0] SEPC_REGW,      
-  output logic [31:0]       SCOUNTEREN_REGW, 
-  output logic [P.XLEN-1:0] SATP_REGW,
-  input  logic [11:0]       MIP_REGW, MIE_REGW, MIDELEG_REGW,
-  input  logic [63:0]       MTIME_CLINT,
-  input  logic              STCE,
-  output logic              WriteSSTATUSM,
-  output logic              IllegalCSRSAccessM,
-  output logic              STimerInt,
-  output logic [P.XLEN-1:0] SENVCFG_REGW
-
-);
-
-  // Supervisor CSRs
-  localparam SSTATUS    = 12'h100;
-  localparam SIE        = 12'h104;
-  localparam STVEC      = 12'h105;
-  localparam SCOUNTEREN = 12'h106;
-  localparam SENVCFG    = 12'h10A;
-  localparam SSCRATCH   = 12'h140;
-  localparam SEPC       = 12'h141;
-  localparam SCAUSE     = 12'h142;
-  localparam STVAL      = 12'h143;
-  localparam SIP        = 12'h144;
-  localparam STIMECMP   = 12'h14D;
-  localparam STIMECMPH  = 12'h15D;
-  localparam SATP       = 12'h180;
-  // Constants
-
-  logic                    WriteSTVECM;
-  logic                    WriteSSCRATCHM, WriteSEPCM;
-  logic                    WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
-  logic                    WriteSTIMECMPM, WriteSTIMECMPHM;
-  logic                    WriteSENVCFGM;
-
-  logic [P.XLEN-1:0]       SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
-  logic [P.XLEN-1:0]       SENVCFG_WriteValM;
-  logic [P.XLEN-1:0]               TVECWriteValM;
-
-  logic [63:0]             STIMECMP_REGW;
-  
-  // write enables
-  assign WriteSSTATUSM    = CSRSWriteM & (CSRAdrM == SSTATUS);
-  assign WriteSTVECM      = CSRSWriteM & (CSRAdrM == STVEC);
-  assign WriteSSCRATCHM   = CSRSWriteM & (CSRAdrM == SSCRATCH);
-  assign WriteSEPCM       = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
-  assign WriteSCAUSEM     = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
-  assign WriteSTVALM      = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
-  if(P.XLEN == 64) begin
-    logic LegalSatpModeM;
-    assign LegalSatpModeM = P.VIRTMEM_SUPPORTED & (CSRWriteValM[63:60] == 0 | CSRWriteValM[63:60] == P.SV39 | CSRWriteValM[63:60] == P.SV48); // supports SV39 and 48
-    assign WriteSATPM     = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & LegalSatpModeM;
-  end else  // RV32
-    assign WriteSATPM     = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM) & P.VIRTMEM_SUPPORTED;
-  assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
-  assign WriteSENVCFGM    = CSRSWriteM & (CSRAdrM == SENVCFG);
-  assign WriteSTIMECMPM   = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE;
-  assign WriteSTIMECMPHM  = CSRSWriteM & (CSRAdrM == STIMECMPH) & STCE & (P.XLEN == 32);
-
-  // CSRs
-  assign TVECWriteValM = CSRWriteValM[0] ? {CSRWriteValM[P.XLEN-1:6], 6'b000001} : {CSRWriteValM[P.XLEN-1:2], 2'b00}; // could share this with MTVEC, but reduces to 4-bit AND to mask bits [5:2]
-  flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, TVECWriteValM, STVEC_REGW); 
-  flopenr #(P.XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
-  flopenr #(P.XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); 
-  flopenr #(P.XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW);
-  flopenr #(P.XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
-  if (P.VIRTMEM_SUPPORTED)
-    flopenr #(P.XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
-  else
-    assign SATP_REGW = '0; // hardwire to zero if virtual memory not supported
-  flopenr #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
-  if (P.SSTC_SUPPORTED) begin : sstc
-    if (P.XLEN == 64) begin : sstc64
-      flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW);
-    end else begin : sstc32
-      flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]);
-      flopenr #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]);
-    end
-  end else assign STIMECMP_REGW = '0;
-
-  // Supervisor timer interrupt logic
-  // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs
-  if (P.SSTC_SUPPORTED)
-   assign STimerInt  = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
-  else 
-    assign STimerInt = 1'b0;
-
-  logic [1:0] LegalizedCBIE;
-  assign LegalizedCBIE = CSRWriteValM[5:4] == 2'b10 ? SENVCFG_REGW[5:4] : CSRWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value
-  assign SENVCFG_WriteValM = {
-    {(P.XLEN-8){1'b0}},
-    CSRWriteValM[7]   & P.ZICBOZ_SUPPORTED,
-    CSRWriteValM[6]   & P.ZICBOM_SUPPORTED,
-    LegalizedCBIE     & {2{P.ZICBOM_SUPPORTED}},
-    3'b0,
-    CSRWriteValM[0]   & P.VIRTMEM_SUPPORTED
-  }; 
-
-  flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW);
-    
-  // CSR Reads
-  always_comb begin:csrr
-    IllegalCSRSAccessM = 1'b0;
-    case (CSRAdrM) 
-      SSTATUS:   CSRSReadValM = SSTATUS_REGW;
-      STVEC:     CSRSReadValM = STVEC_REGW;
-      SIP:       CSRSReadValM = {{(P.XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  
-      SIE:       CSRSReadValM = {{(P.XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
-      SSCRATCH:  CSRSReadValM = SSCRATCH_REGW;
-      SEPC:      CSRSReadValM = SEPC_REGW;
-      SCAUSE:    CSRSReadValM = SCAUSE_REGW;
-      STVAL:     CSRSReadValM = STVAL_REGW;
-      SATP:      if (P.VIRTMEM_SUPPORTED & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
-                 else begin
-                   CSRSReadValM = '0;
-                   IllegalCSRSAccessM = 1'b1;
-                 end
-      SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
-      SENVCFG:   CSRSReadValM = SENVCFG_REGW;
-      STIMECMP:  if (STCE) 
-                   CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; 
-                 else begin 
-                   CSRSReadValM = '0;
-                   IllegalCSRSAccessM = 1'b1;
-                 end
-      STIMECMPH: if (STCE & P.XLEN == 32) // not supported for RV64
-                   CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]};
-                 else begin 
-                   CSRSReadValM = '0;
-                   IllegalCSRSAccessM = 1'b1;
-                 end
-      default: begin
-                  CSRSReadValM = '0; 
-                  IllegalCSRSAccessM = 1'b1;  
-               end       
-    endcase
-  end
-endmodule
diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
deleted file mode 100644
index 08c6e4c19..000000000
--- a/src/privileged/csrsr.sv
+++ /dev/null
@@ -1,215 +0,0 @@
-///////////////////////////////////////////
-// crsr.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Status register (and environment configuration register and others shared across modes)
-//          See RISC-V Privileged Mode Specification 20190608 
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csrsr import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset, StallW,
-  input  logic              WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM, 
-  input  logic              TrapM, FRegWriteM,
-  input  logic [1:0]        NextPrivilegeModeM, PrivilegeModeW,
-  input  logic              mretM, sretM, 
-  input  logic              WriteFRMM, SetOrWriteFFLAGSM,
-  input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic              SelHPTW,
-  output logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
-  output logic [1:0]        STATUS_MPP,
-  output logic              STATUS_SPP, STATUS_TSR, STATUS_TW,
-  output logic              STATUS_MIE, STATUS_SIE,
-  output logic              STATUS_MXR, STATUS_SUM,
-  output logic              STATUS_MPRV, STATUS_TVM,
-  output logic [1:0]        STATUS_FS,
-  output logic              BigEndianM
-);
-  
-  logic STATUS_SD, STATUS_TW_INT, STATUS_TSR_INT, STATUS_TVM_INT, STATUS_MXR_INT, STATUS_SUM_INT, STATUS_MPRV_INT;
-  logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS_INT, STATUS_MPP_NEXT;
-  logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE;
-  logic nextMBE, nextSBE;
-  
-  // STATUS REGISTER FIELD
-  // See Privileged Spec Section 3.1.6
-  // Lower privilege status registers are a subset of the full status register
-  if (P.XLEN==64) begin: csrsr64 // RV64
-    assign MSTATUS_REGW  = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
-                           STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-                           STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
-                           STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0,
-                           STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
-    assign SSTATUS_REGW  = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {STATUS_UXL}, /*9'b0, */ 12'b0,
-                          /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
-                           STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
-                           STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
-                          /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
-    assign MSTATUSH_REGW = '0; // does not exist when XLEN=64, and accessing will throw an illegal instruction
-  end else begin: csrsr32 // RV32
-    assign MSTATUS_REGW  = {STATUS_SD, 8'b0,
-                           STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-                           STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
-                           STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0, STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
-    assign MSTATUSH_REGW = {26'b0, STATUS_MBE, STATUS_SBE, 4'b0}; 
-    assign SSTATUS_REGW  = {STATUS_SD, 11'b0,
-                          /*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
-                           STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
-                           STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
-                          /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
-  end
-
-  // extract values to write to upper status register on 64/32-bit access
-  if (P.XLEN==64) begin:upperstatus
-    assign nextMBE = P.BIGENDIAN_SUPPORTED & CSRWriteValM[37];
-    assign nextSBE = P.S_SUPPORTED & P.BIGENDIAN_SUPPORTED & CSRWriteValM[36];
-  end else begin:upperstatus
-    assign nextMBE = P.BIGENDIAN_SUPPORTED & STATUS_MBE;
-    assign nextSBE = P.S_SUPPORTED & P.BIGENDIAN_SUPPORTED & STATUS_SBE;
-  end
-
-  // hardwired STATUS bits
-  assign STATUS_TSR  = P.S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_TW   = P.U_SUPPORTED & STATUS_TW_INT; // override register with 0 if only machine mode supported
-  assign STATUS_TVM  = P.S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_MXR  = P.S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
-  // SXL and UXL bits only matter for RV64.  Set to 10 for RV64 if mode is supported, or 0 if not
-  assign STATUS_SXL  = P.S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
-  assign STATUS_UXL  = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
-  assign STATUS_SUM  = P.S_SUPPORTED & P.VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_MPRV = P.U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
-  assign STATUS_FS   = P.F_SUPPORTED ? STATUS_FS_INT : 2'b00; // off if no FP
-  assign STATUS_SD   = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
-  assign STATUS_XS   = 2'b00; // No additional user-mode state to be dirty
-
-  always_comb
-    if      (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
-    else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
-    else if (CSRWriteValM[12:11] == P.M_MODE)                 STATUS_MPP_NEXT = P.M_MODE;
-    else                                                      STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10 or unsupported mode
-
-  ///////////////////////////////////////////
-  // Endianness logic Privileged Spec 3.1.6.4
-  ///////////////////////////////////////////
-
-  if (P.BIGENDIAN_SUPPORTED) begin: endianmux
-    // determine whether big endian accesses should be made
-    logic [1:0] EndiannessPrivMode;
-    always_comb begin
-      if      (SelHPTW)                                  EndiannessPrivMode = P.S_MODE;
-      //coverage off -item c 1 -feccondrow 1
-      // status.MPRV always gets reset upon leaving machine mode, so MPRV will never be high when out of machine mode
-      else if (PrivilegeModeW == P.M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP;
-      //coverage on
-      else                                               EndiannessPrivMode = PrivilegeModeW;
-
-      case (EndiannessPrivMode) 
-        P.M_MODE: BigEndianM = STATUS_MBE;
-        P.S_MODE: BigEndianM = STATUS_SBE;
-        default: BigEndianM  = STATUS_UBE;
-      endcase
-    end
-  end else begin: endianmux
-    assign BigEndianM = 1'b0;
-  end
-
-  // registers for STATUS bits
-  // complex register with reset, write enable, and the ability to update other bits in certain cases
-  always_ff @(posedge clk) //, posedge reset)
-    if (reset) begin
-      STATUS_TSR_INT  <= 1'b0;
-      STATUS_TW_INT   <= 1'b0;
-      STATUS_TVM_INT  <= 1'b0;
-      STATUS_MXR_INT  <= 1'b0;
-      STATUS_SUM_INT  <= 1'b0;
-      STATUS_MPRV_INT <= 1'b0; // Per Priv 3.3
-      STATUS_FS_INT   <= 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
-      STATUS_MPP      <= 2'b00; 
-      STATUS_SPP      <= 1'b0; 
-      STATUS_MPIE     <= 1'b0; 
-      STATUS_SPIE     <= 1'b0; 
-      STATUS_MIE      <= 1'b0; 
-      STATUS_SIE      <= 1'b0; 
-      STATUS_MBE      <= 1'b0;
-      STATUS_SBE      <= 1'b0;
-      STATUS_UBE      <= 1'b0;
-    end else if (~StallW) begin
-      if (TrapM) begin
-        // Update interrupt enables per Privileged Spec p. 21
-        // y = PrivilegeModeW
-        // x = NextPrivilegeModeM
-        // Modes: 11 = Machine, 01 = Supervisor, 00 = User
-        if (NextPrivilegeModeM == P.M_MODE) begin
-          STATUS_MPIE <= STATUS_MIE;
-          STATUS_MIE  <= 1'b0;
-          STATUS_MPP  <= PrivilegeModeW;
-        end else if (P.S_SUPPORTED) begin // supervisor mode
-          STATUS_SPIE <= STATUS_SIE;
-          STATUS_SIE  <= 1'b0;
-          STATUS_SPP  <= PrivilegeModeW[0];
-       end
-      end else if (mretM) begin // Privileged 3.1.6.1
-        STATUS_MIE      <= STATUS_MPIE; // restore global interrupt enable
-        STATUS_MPIE     <= 1'b1; // 
-        STATUS_MPP      <= P.U_SUPPORTED ? P.U_MODE : P.M_MODE; // set MPP to lowest supported privilege level
-        STATUS_MPRV_INT <= STATUS_MPRV_INT & (STATUS_MPP == P.M_MODE); // page 21 of privileged spec.
-      end else if (sretM & P.S_SUPPORTED) begin
-        STATUS_SIE      <= STATUS_SPIE; // restore global interrupt enable
-        STATUS_SPIE     <= P.S_SUPPORTED; 
-        STATUS_SPP      <= 1'b0; // set SPP to lowest supported privilege level to catch bugs
-        STATUS_MPRV_INT <= 1'b0; // always clear MPRV
-      end else if (WriteMSTATUSM) begin
-        STATUS_TSR_INT  <= P.S_SUPPORTED & CSRWriteValM[22];
-        STATUS_TW_INT   <= P.U_SUPPORTED & CSRWriteValM[21];
-        STATUS_TVM_INT  <= P.S_SUPPORTED & CSRWriteValM[20];
-        STATUS_MXR_INT  <= P.S_SUPPORTED & CSRWriteValM[19];
-        STATUS_SUM_INT  <= P.VIRTMEM_SUPPORTED & CSRWriteValM[18];
-        STATUS_MPRV_INT <= P.U_SUPPORTED & CSRWriteValM[17];
-        STATUS_FS_INT   <= CSRWriteValM[14:13];
-        STATUS_MPP      <= STATUS_MPP_NEXT;
-        STATUS_SPP      <= P.S_SUPPORTED & CSRWriteValM[8];
-        STATUS_MPIE     <= CSRWriteValM[7];
-        STATUS_SPIE     <= P.S_SUPPORTED & CSRWriteValM[5];
-        STATUS_MIE      <= CSRWriteValM[3];
-        STATUS_SIE      <= P.S_SUPPORTED & CSRWriteValM[1];
-        STATUS_UBE      <= P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED & CSRWriteValM[6];
-        STATUS_MBE      <= nextMBE;
-        STATUS_SBE      <= nextSBE;
-      // coverage off
-      // MSTATUSH only exists in 32-bit configurations, will not be hit on rv64gc
-      end else if ((P.XLEN == 32) & WriteMSTATUSHM) begin
-        STATUS_MBE      <= P.BIGENDIAN_SUPPORTED & CSRWriteValM[5];
-        STATUS_SBE      <= P.S_SUPPORTED & P.BIGENDIAN_SUPPORTED & CSRWriteValM[4];
-      // coverage on
-      end else if (P.S_SUPPORTED & WriteSSTATUSM) begin // write a subset of the STATUS bits
-        STATUS_MXR_INT  <= P.S_SUPPORTED & CSRWriteValM[19];
-        STATUS_SUM_INT  <= P.VIRTMEM_SUPPORTED & CSRWriteValM[18];
-        STATUS_FS_INT   <= CSRWriteValM[14:13];
-        STATUS_SPP      <= P.S_SUPPORTED & CSRWriteValM[8];
-        STATUS_SPIE     <= P.S_SUPPORTED & CSRWriteValM[5];
-        STATUS_SIE      <= P.S_SUPPORTED & CSRWriteValM[1];
-        STATUS_UBE      <= P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED & CSRWriteValM[6];
-      end else if (FRegWriteM | WriteFRMM | SetOrWriteFFLAGSM) STATUS_FS_INT <= 2'b11; 
-    end
-endmodule
diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv
deleted file mode 100644
index 97467afce..000000000
--- a/src/privileged/csru.sv
+++ /dev/null
@@ -1,86 +0,0 @@
-///////////////////////////////////////////
-// csru.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: User-Mode Control and Status Registers for Floating Point
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csru import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset, 
-  input  logic              InstrValidNotFlushedM,
-  input  logic              CSRUWriteM,
-  input  logic [11:0]       CSRAdrM,
-  input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic [1:0]        STATUS_FS,
-  output logic [P.XLEN-1:0] CSRUReadValM,  
-  input  logic [4:0]        SetFflagsM,
-  output logic [2:0]        FRM_REGW,
-  output logic              WriteFRMM, SetOrWriteFFLAGSM,
-  output logic              IllegalCSRUAccessM
-);
-
-  localparam FFLAGS = 12'h001;
-  localparam FRM    = 12'h002;
-  localparam FCSR   = 12'h003;
-
-  logic [4:0]               FFLAGS_REGW;
-  logic [2:0]               NextFRMM;
-  logic [4:0]               NextFFLAGSM;
-  logic                     WriteFFLAGSM;
-  
-  // Write enables
-  // Explicitly checking STATUS_FS != 0 is redundant since the instruction traps otherwise, 
-  // causing CSRWriteM to go low, but it is left here for safety
-  assign WriteFRMM    = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
-  assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);
-
-  // Write Values
-  assign NextFRMM          = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
-  assign NextFFLAGSM       = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
-  assign SetOrWriteFFLAGSM = WriteFFLAGSM | (|SetFflagsM & InstrValidNotFlushedM);
-
-  // CSRs
-  flopenr #(3) FRMreg(clk, reset, WriteFRMM, NextFRMM, FRM_REGW);
-  flopenr #(5) FFLAGSreg(clk, reset, SetOrWriteFFLAGSM, NextFFLAGSM, FFLAGS_REGW); 
-
-  // CSR Reads
-  always_comb begin
-    if (STATUS_FS == 2'b00) begin // fpu disabled, trap
-      IllegalCSRUAccessM = 1'b1;
-      CSRUReadValM = '0;
-    end else begin
-      IllegalCSRUAccessM = 1'b0;
-      case (CSRAdrM) 
-        FFLAGS:    CSRUReadValM = {{(P.XLEN-5){1'b0}}, FFLAGS_REGW};
-        FRM:       CSRUReadValM = {{(P.XLEN-3){1'b0}}, FRM_REGW};
-        FCSR:      CSRUReadValM = {{(P.XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
-        default: begin
-                   CSRUReadValM = '0; 
-                   IllegalCSRUAccessM = 1'b1;
-        end         
-      endcase
-    end
-  end
-endmodule
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
deleted file mode 100644
index 197ab23be..000000000
--- a/src/privileged/privileged.sv
+++ /dev/null
@@ -1,166 +0,0 @@
-///////////////////////////////////////////
-// privileged.sv
-//
-// Written: David_Harris@hmc.edu 5 January 2021
-// Modified: 
-//
-// Purpose: Implements the CSRs, Exceptions, and Privileged operations
-//          See RISC-V Privileged Mode Specification 20190608 
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-// SOFTWARE.
-///////////////////////////////////////////
-
-module privileged import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
-  input  logic              StallD, StallE, StallM, StallW,
-  input  logic              FlushD, FlushE, FlushM, FlushW, 
-  // CSR Reads and Writes, and values needed for traps
-  input  logic              CSRReadM, CSRWriteM,                            // Read or write CSRs
-  input  logic [P.XLEN-1:0] SrcAM,                                          // GPR register to write
-  input  logic [31:0]       InstrM,                                         // Instruction
-  input  logic [31:0]       InstrOrigM,                                     // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [P.XLEN-1:0] IEUAdrM,                                        // address from IEU
-  input  logic [P.XLEN-1:0] PCM,                                            // program counter
-  // control signals                                                       
-  input  logic              InstrValidM,                                    // Current instruction is valid (not flushed)
-  input  logic              CommittedM, CommittedF,                         // current instruction is using bus; don't interrupt
-  input  logic              PrivilegedM,                                    // privileged instruction
-  // processor events for performance counter logging                      
-  input  logic              FRegWriteM,                                     // instruction will write floating-point registers
-  input  logic              LoadStallD,                                     // load instruction is stalling
-  input  logic              StoreStallD,                                    // store instruction is stalling
-  input  logic              ICacheStallF,                                   // I cache stalled
-  input  logic              DCacheStallM,                                   // D cache stalled
-  input  logic              BPDirWrongM,                                // branch predictor guessed wrong direction
-  input  logic              BTAWrongM,                                      // branch predictor guessed wrong target
-  input  logic              RASPredPCWrongM,                                // return adddress stack guessed wrong target
-  input  logic              IClassWrongM,                                   // branch predictor guessed wrong instruction class
-  input  logic              BPWrongM,                                       // branch predictor is wrong
-  input  logic [3:0]        IClassM,                                    // actual instruction class
-  input  logic              DCacheMiss,                                     // data cache miss
-  input  logic              DCacheAccess,                                   // data cache accessed (hit or miss)
-  input  logic              ICacheMiss,                                     // instruction cache miss
-  input  logic              ICacheAccess,                                   // instruction cache access
-  input  logic              DivBusyE,                                       // integer divide busy
-  input  logic              FDivBusyE,                                      // floating point divide busy
-  // fault sources                                                         
-  input  logic              InstrAccessFaultF,                              // instruction access fault
-  input  logic              LoadAccessFaultM, StoreAmoAccessFaultM,         // load or store access fault
-  input  logic              HPTWInstrAccessFaultF,                          // hardware page table access fault while fetching instruction PTE
-  input  logic              HPTWInstrPageFaultF,                            // hardware page table page fault while fetching instruction PTE
-  input  logic              InstrPageFaultF,                                // page faults
-  input  logic              LoadPageFaultM, StoreAmoPageFaultM,             // page faults
-  input  logic              InstrMisalignedFaultM,                          // misaligned instruction fault
-  input  logic              LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
-  input  logic              IllegalIEUFPUInstrD,                            // illegal instruction from IEU or FPU
-  input  logic              MTimerInt, MExtInt, SExtInt, MSwInt,            // interrupt sources
-  input  logic [63:0]       MTIME_CLINT,                                    // timer value from CLINT
-  input  logic [4:0]        SetFflagsM,                                     // set FCSR flags from FPU
-  input  logic              SelHPTW,                                        // HPTW in use.  Causes system to use S-mode endianness for accesses
-  // CSR outputs                                                           
-  output logic [P.XLEN-1:0] CSRReadValW,                                    // Value read from CSR
-  output logic [1:0]        PrivilegeModeW,                                 // current privilege mode
-  output logic [P.XLEN-1:0] SATP_REGW,                                      // supervisor address translation register
-  output logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,            // status register bits
-  output logic [1:0]        STATUS_MPP, STATUS_FS,                          // status register bits
-  output var logic [7:0]    PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],           // PMP configuration entries to MMU
-  output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],  // PMP address entries to MMU
-  output logic [2:0]        FRM_REGW,                                       // FPU rounding mode
-  output logic [3:0]        ENVCFG_CBE,                                     // Cache block operation enables
-  output logic              ENVCFG_PBMTE,                                   // Page-based memory type enable
-  output logic              ENVCFG_ADUE,                                    // HPTW A/D Update enable
-  // PC logic output from privileged unit to IFU                                  
-  output logic [P.XLEN-1:0] EPCM,                                           // Exception Program counter to IFU PC logic
-  output logic [P.XLEN-1:0] TrapVectorM,                                    // Trap vector, to IFU PC logic
-  // control outputs                                                       
-  output logic              RetM, TrapM,                                    // return instruction, or trap
-  output logic              sfencevmaM,                                     // sfence.vma instruction
-  input  logic              InvalidateICacheM,                              // fence instruction
-  output logic              BigEndianM,                                     // Use big endian in current privilege mode
-  // Fault outputs                                                         
-  output logic              wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
-);                                                                         
-                                                                           
-  logic [3:0]               CauseM;                                         // trap cause
-  logic [15:0]              MEDELEG_REGW;                                   // exception delegation CSR
-  logic [11:0]              MIDELEG_REGW;                                   // interrupt delegation CSR
-  logic                     sretM, mretM;                                   // supervisor / machine return instruction
-  logic                     IllegalCSRAccessM;                              // Illegal access to CSR
-  logic                     IllegalIEUFPUInstrM;                            // Illegal IEU or FPU instruction, delayed to Mem stage
-  logic                     InstrPageFaultM;                                // Instruction page fault, delayed to Mem stage
-  logic                     InstrAccessFaultM;                              // Instruction access fault, delayed to Mem stages
-  logic                     IllegalInstrFaultM;                             // Illegal instruction fault
-  logic                     STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;  // Status bits needed within privileged unit
-  logic                     STATUS_MIE, STATUS_SIE;                         // status bits: interrupt enables
-  logic [11:0]              MIP_REGW, MIE_REGW;                             // interrupt pending and enable bits
-  logic [1:0]               NextPrivilegeModeM;                             // next privilege mode based on trap or return
-  logic                     DelegateM;                                      // trap should be delegated
-  logic                     InterruptM;                                     // interrupt occuring
-  logic                     ExceptionM;                                     // Memory stage instruction caused a fault
-  logic                     HPTWInstrAccessFaultM;                          // Hardware page table access fault while fetching instruction PTE
-  logic                     HPTWInstrPageFaultM;                            // Hardware page table page fault while fetching instruction PTE
-  logic                     BreakpointFaultM, EcallFaultM;                  // breakpoint and Ecall traps should retire
-  
-  logic                     wfiW;
-  
-  // track the current privilege level
-  privmode #(P) privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
-    .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
-
-  // decode privileged instructions
-  privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]), 
-    .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
-    .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
-    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
-
-  // Control and Status Registers
-  csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
-    .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, 
-    .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
-    .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-    .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
-    .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
-    .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
-    .IClassWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
-    .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
-    .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
-    .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
-    .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
-    .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .EPCM, .TrapVectorM,
-    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
-
-  // pipeline early-arriving trap sources
-  privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-    .InstrPageFaultF, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .IllegalIEUFPUInstrD, 
-    .InstrPageFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .HPTWInstrPageFaultM, .IllegalIEUFPUInstrM);
-
-  // trap logic
-  trap #(P) trap(.reset,
-    .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .HPTWInstrPageFaultM, .IllegalInstrFaultM,
-    .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
-    .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
-    .LoadPageFaultM, .StoreAmoPageFaultM, .PrivilegeModeW, 
-    .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
-    .InstrValidM, .CommittedM, .CommittedF,
-    .TrapM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
-endmodule
diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
deleted file mode 100644
index 4cab65c34..000000000
--- a/src/privileged/privpiperegs.sv
+++ /dev/null
@@ -1,59 +0,0 @@
-///////////////////////////////////////////
-// privpiperegs.sv
-//
-// Written: David_Harris@hmc.edu 12 May 2022
-// Modified: 
-//
-// Purpose: Pipeline registers for early exceptions
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module privpiperegs (
-  input  logic         clk, reset,  
-  input  logic         StallD, StallE, StallM,
-  input  logic         FlushD, FlushE, FlushM,
-  input  logic         InstrPageFaultF, InstrAccessFaultF,  // instruction faults
-  input  logic         HPTWInstrAccessFaultF,               // hptw fault during instruction page fetch
-  input  logic         HPTWInstrPageFaultF,                 // hptw fault during instruction page fetch
-  input  logic         IllegalIEUFPUInstrD,                 // illegal IEU instruction decoded
-  output logic         InstrPageFaultM, InstrAccessFaultM,  // delayed instruction faults
-  output logic         IllegalIEUFPUInstrM,                 // delayed illegal IEU instruction
-  output logic         HPTWInstrAccessFaultM,               // hptw fault during instruction page fetch
-  output logic         HPTWInstrPageFaultM                  // hptw fault during instruction page fetch
-);
-
-  // Delayed fault signals
-  logic                InstrPageFaultD, InstrAccessFaultD, HPTWInstrAccessFaultD, HPTWInstrPageFaultD;
-  logic                InstrPageFaultE, InstrAccessFaultE, HPTWInstrAccessFaultE, HPTWInstrPageFaultE;
-  logic                IllegalIEUFPUInstrE; 
-
-  // pipeline fault signals
-  flopenrc #(4) faultregD(clk, reset, FlushD, ~StallD,
-                  {InstrPageFaultF, InstrAccessFaultF, HPTWInstrAccessFaultF, HPTWInstrPageFaultF},
-                  {InstrPageFaultD, InstrAccessFaultD, HPTWInstrAccessFaultD, HPTWInstrPageFaultD});
-  flopenrc #(5) faultregE(clk, reset, FlushE, ~StallE,
-                  {IllegalIEUFPUInstrD, InstrPageFaultD, InstrAccessFaultD, HPTWInstrAccessFaultD, HPTWInstrPageFaultD}, 
-                  {IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE, HPTWInstrAccessFaultE, HPTWInstrPageFaultE});
-  flopenrc #(5) faultregM(clk, reset, FlushM, ~StallM,
-                  {IllegalIEUFPUInstrE, InstrPageFaultE, InstrAccessFaultE, HPTWInstrAccessFaultE, HPTWInstrPageFaultE},
-                  {IllegalIEUFPUInstrM, InstrPageFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, HPTWInstrPageFaultM});
-endmodule
diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv
deleted file mode 100644
index 95ae26e1a..000000000
--- a/src/privileged/trap.sv
+++ /dev/null
@@ -1,123 +0,0 @@
-///////////////////////////////////////////
-// trap.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts
-//
-// Purpose: Handle Traps: Exceptions and Interrupts
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module trap import cvw::*;  #(parameter cvw_t P) (
-  input  logic                 reset, 
-  input  logic                 InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, HPTWInstrPageFaultM, IllegalInstrFaultM,
-  input  logic                 BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
-  input  logic                 LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
-  input  logic                 LoadPageFaultM, StoreAmoPageFaultM,              // various trap sources
-  input  logic                 wfiM, wfiW,                                      // wait for interrupt instruction
-  input  logic [1:0]           PrivilegeModeW,                                  // current privilege mode
-  input  logic [11:0]          MIP_REGW, MIE_REGW, MIDELEG_REGW,                // interrupt pending, enabled, and delegate CSRs
-  input  logic [15:0]          MEDELEG_REGW,                                    // exception delegation SR
-  input  logic                 STATUS_MIE, STATUS_SIE,                          // machine/supervisor interrupt enables
-  input  logic                 InstrValidM,                                     // current instruction is valid, not flushed
-  input  logic                 CommittedM, CommittedF,                          // LSU/IFU has committed to a bus operation that can't be interrupted
-  output logic                 TrapM,                                           // Trap is occurring
-  output logic                 InterruptM,                                      // Interrupt is occurring
-  output logic                 ExceptionM,                                      // exception is occurring
-  output logic                 IntPendingM,                                     // Interrupt is pending, might occur if enabled
-  output logic                 DelegateM,                                       // Delegate trap to supervisor handler
-  output logic [3:0]           CauseM                                           // trap cause
-);
-
-  logic                        MIntGlobalEnM, SIntGlobalEnM;                    // Global interupt enables
-  logic                        Committed;                                       // LSU or IFU has committed to a bus operation that can't be interrupted
-  logic                        BothInstrAccessFaultM, BothInstrPageFaultM;      // instruction or HPTW ITLB fill caused an Instruction Access Fault
-  logic [11:0]                 PendingIntsM, ValidIntsM, EnabledIntsM;          // interrupts are pending, valid, or enabled
-
-  ///////////////////////////////////////////
-  // Determine pending enabled interrupts
-  // interrupt if any sources are pending
-  // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
-  // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
-  ///////////////////////////////////////////
-
-  assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
-  assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
-  assign PendingIntsM  = MIP_REGW & MIE_REGW;
-  assign IntPendingM   = |PendingIntsM;
-  assign Committed     = CommittedM | CommittedF;
-  assign EnabledIntsM  = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0);
-  assign ValidIntsM    = Committed ? '0 : EnabledIntsM;
-  assign InterruptM    = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. 
-  // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage.
-  assign DelegateM     = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
-                     (PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
-
-  ///////////////////////////////////////////
-  // Trigger Traps 
-  // According to RISC-V Spec Section 1.6, exceptions are caused by instructions.  Interrupts are external asynchronous.
-  // Traps are the union of exceptions and interrupts.
-  ///////////////////////////////////////////
-  
-  assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM;
-  assign BothInstrPageFaultM = InstrPageFaultM | HPTWInstrPageFaultM;
-  // coverage off -item e 1 -fecexprrow 2
-  // excludes InstrMisalignedFaultM from coverage of this line, since misaligned instructions cannot occur in rv64gc.
-  assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM |
-                      LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
-                      BothInstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
-                      BreakpointFaultM | EcallFaultM |
-                      LoadAccessFaultM | StoreAmoAccessFaultM;
-  // coverage on
-  assign TrapM = (ExceptionM & ~CommittedF) | InterruptM;
-
-  ///////////////////////////////////////////
-  // Cause priority defined in privileged spec
-  ///////////////////////////////////////////
-
-  always_comb
-    if      (reset)                    CauseM = 4'd0; // hard reset 3.3
-    else if (ValidIntsM[11])           CauseM = 4'd11; // Machine External Int
-    else if (ValidIntsM[3])            CauseM = 4'd3;  // Machine Sw Int
-    else if (ValidIntsM[7])            CauseM = 4'd7;  // Machine Timer Int
-    else if (ValidIntsM[9])            CauseM = 4'd9;  // Supervisor External Int 
-    else if (ValidIntsM[1])            CauseM = 4'd1;  // Supervisor Sw Int       
-    else if (ValidIntsM[5])            CauseM = 4'd5;  // Supervisor Timer Int    
-    else if (BothInstrPageFaultM)      CauseM = 4'd12;
-    else if (BothInstrAccessFaultM)    CauseM = 4'd1;
-    else if (IllegalInstrFaultM)       CauseM = 4'd2;
-    // coverage off
-    // Misaligned instructions cannot occur in rv64gc
-    else if (InstrMisalignedFaultM)    CauseM = 4'd0;
-    // coverage on
-    else if (BreakpointFaultM)         CauseM = 4'd3;
-    else if (EcallFaultM)              CauseM = {2'b10, PrivilegeModeW};
-    else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd6;  // misaligned faults are higher priority if they always are taken
-    else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED)     CauseM = 4'd4;
-    else if (StoreAmoPageFaultM)       CauseM = 4'd15;
-    else if (LoadPageFaultM)           CauseM = 4'd13;
-    else if (StoreAmoAccessFaultM)     CauseM = 4'd7;
-    else if (LoadAccessFaultM)         CauseM = 4'd5;
-    else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // See priority in Privileged Spec 3.1.15
-    else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED)     CauseM = 4'd4;
-    else                               CauseM = 4'd0;
-endmodule
diff --git a/src/rvvi/csrindextoaddr.sv b/src/rvvi/csrindextoaddr.sv
deleted file mode 100644
index 4612dd4ee..000000000
--- a/src/rvvi/csrindextoaddr.sv
+++ /dev/null
@@ -1,77 +0,0 @@
-///////////////////////////////////////////
-// csrindextoaddr.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 24 January 2024
-// Modified: 24 January 2024
-//
-// Purpose: Converts the rvvi CSR index into the CSR address
-//
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module csrindextoaddr #(parameter TOTAL_CSRS = 36) (
-  input logic [TOTAL_CSRS-1:0]  CSRWen,
-  output logic [11:0] CSRAddr);
-
-  always_comb begin
-    case(CSRWen) 
-      36'h0_0000_0000: CSRAddr = 12'h000;
-      36'h0_0000_0001: CSRAddr = 12'h300;
-      36'h0_0000_0002: CSRAddr = 12'h310;
-      36'h0_0000_0004: CSRAddr = 12'h305;      
-      36'h0_0000_0008: CSRAddr = 12'h341;      
-      36'h0_0000_0010: CSRAddr = 12'h306;      
-      36'h0_0000_0020: CSRAddr = 12'h320;      
-      36'h0_0000_0040: CSRAddr = 12'h302;      
-      36'h0_0000_0080: CSRAddr = 12'h303;      
-      36'h0_0000_0100: CSRAddr = 12'h344;      
-      36'h0_0000_0200: CSRAddr = 12'h304;      
-      36'h0_0000_0400: CSRAddr = 12'h301;      
-      36'h0_0000_0800: CSRAddr = 12'h30A;      
-      36'h0_0000_1000: CSRAddr = 12'hF14;      
-      36'h0_0000_2000: CSRAddr = 12'h340;
-      36'h0_0000_4000: CSRAddr = 12'h342;
-      36'h0_0000_8000: CSRAddr = 12'h343;
-      36'h0_0001_0000: CSRAddr = 12'hF11;
-      36'h0_0002_0000: CSRAddr = 12'hF12;
-      36'h0_0004_0000: CSRAddr = 12'hF13;
-      36'h0_0008_0000: CSRAddr = 12'hF15;
-      36'h0_0010_0000: CSRAddr = 12'h34A;
-      36'h0_0020_0000: CSRAddr = 12'h100;
-      36'h0_0040_0000: CSRAddr = 12'h104;
-      36'h0_0080_0000: CSRAddr = 12'h105;
-      36'h0_0100_0000: CSRAddr = 12'h141;
-      36'h0_0200_0000: CSRAddr = 12'h106;
-      36'h0_0400_0000: CSRAddr = 12'h10A;
-      36'h0_0800_0000: CSRAddr = 12'h180;
-      36'h0_1000_0000: CSRAddr = 12'h140;
-      36'h0_2000_0000: CSRAddr = 12'h143;
-      36'h0_4000_0000: CSRAddr = 12'h142;
-      36'h0_8000_0000: CSRAddr = 12'h144;
-      36'h1_0000_0000: CSRAddr = 12'h14D;
-      36'h2_0000_0000: CSRAddr = 12'h001;
-      36'h4_0000_0000: CSRAddr = 12'h002;
-      36'h8_0000_0000: CSRAddr = 12'h003;
-      default        : CSRAddr = 12'h000;
-    endcase
-  end
-endmodule
-  
diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv
deleted file mode 100644
index 6b99710cd..000000000
--- a/src/rvvi/packetizer.sv
+++ /dev/null
@@ -1,143 +0,0 @@
-///////////////////////////////////////////
-// packetizer.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 21 May 2024
-// Modified: 21 May 2024
-//
-// Purpose: Converts the compressed RVVI format into AXI 4 burst write transactions.
-//
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module packetizer import cvw::*; #(parameter cvw_t P,
-                                   parameter integer MAX_CSRS, 
-                                   parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4,
-                                   parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2
-)(
-  input  logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi,
-  input  logic valid,
-  input  logic m_axi_aclk, m_axi_aresetn,
-  output logic RVVIStall,
-  // axi 4 write address channel
-  // axi 4 write data channel
-  output logic [31:0]      RvviAxiWdata,
-  output logic [3:0] 	   RvviAxiWstrb,
-  output logic  		   RvviAxiWlast,
-  output logic  		   RvviAxiWvalid,
-  input  logic  		   RvviAxiWready
-  );
-
-  localparam NearTotalFrameLengthBits = 2*48+16+72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16);
-  localparam WordPadLen = 32 - (NearTotalFrameLengthBits % 32);
-  localparam TotalFrameLengthBits = NearTotalFrameLengthBits + WordPadLen;
-  localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8;
-
-  logic [9:0]              WordCount;
-  logic [11:0]             BytesInFrame;
-  logic                    TransReady;
-  logic                    BurstDone;
-  logic                    WordCountReset;
-  logic                    WordCountEnable;
-  logic [47:0]             SrcMac, DstMac;
-  logic [15:0]             EthType, Length;
-  logic [TotalFrameLengthBits-1:0] TotalFrame;
-  logic [31:0] TotalFrameWords [TotalFrameLengthBytes/4-1:0];
-  logic [WordPadLen-1:0]     WordPad;
-
-  logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvviDelay;
-  
-  typedef enum logic [2:0] {STATE_RST, STATE_COUNT, STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_INSERT_DELAY} statetype;
-(* mark_debug = "true" *)  statetype CurrState, NextState;
-
-   logic [31:0] 	    RstCount;
-(* mark_debug = "true" *)   logic [31:0] 	    FrameCount;
-  logic 		    RstCountRst, RstCountEn, CountFlag, DelayFlag;
-   
-
-  always_ff @(posedge m_axi_aclk) begin
-    if(~m_axi_aresetn) CurrState <= STATE_RST;
-    else               CurrState <= NextState;
-  end
-
-  always_comb begin
-    case(CurrState)
-      STATE_RST: NextState = STATE_COUNT;
-      STATE_COUNT: if (CountFlag) NextState = STATE_RDY;
-                   else           NextState = STATE_COUNT;
-      STATE_RDY: if (TransReady & valid) NextState = STATE_TRANS;
-      else if(~TransReady & valid) NextState = STATE_WAIT;
-      else                        NextState = STATE_RDY;
-      STATE_WAIT: if(TransReady)  NextState = STATE_TRANS;
-                  else            NextState = STATE_WAIT;
-      STATE_TRANS: if(BurstDone & TransReady) NextState = STATE_TRANS_INSERT_DELAY;
-                   else          NextState = STATE_TRANS;
-      STATE_TRANS_INSERT_DELAY: if(DelayFlag) NextState = STATE_RDY;
-                                else          NextState = STATE_TRANS_INSERT_DELAY;
-      default: NextState = STATE_RDY;
-    endcase
-  end
-
-  assign RVVIStall = CurrState != STATE_RDY;
-  assign TransReady = RvviAxiWready;
-  assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady);
-  assign WordCountReset = CurrState == STATE_RDY;
-  assign RstCountEn = CurrState == STATE_COUNT | CurrState == STATE_TRANS_INSERT_DELAY;
-  assign RstCountRst = CurrState == STATE_RST | CurrState == STATE_TRANS;
-
-  // have to count at least 250 ms after reset pulled to wait for the phy to actually be ready
-  // at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000.
-  counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount);
-  assign CountFlag = RstCount == RVVI_INIT_TIME_OUT;
-  assign DelayFlag = RstCount == RVVI_PACKET_DELAY;
-
-  counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount);
-   
-
-  flopenr #(72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay);
-
-
-  counter #(10) WordCounter(m_axi_aclk, WordCountReset, WordCountEnable, WordCount);
-  // *** BUG BytesInFrame will eventually depend on the length of the data stored into the ethernet frame
-  // for now this will be exactly 608 bits (76 bytes, 19 words) + the ethernet frame overhead and 2-byte padding = 92-bytes
-  assign BytesInFrame = 12'd2 + 12'd76 + 12'd6 + 12'd6 + 12'd2;
-  assign BurstDone = WordCount == (BytesInFrame[11:2] - 1'b1);
-
-  genvar index;
-  for (index = 0; index < TotalFrameLengthBytes/4; index++) begin 
-    assign TotalFrameWords[index] = TotalFrame[(index*32)+32-1 : (index*32)];
-  end
-
-  assign Length = {4'b0, BytesInFrame};
-  assign WordPad = '0;
-  assign TotalFrame = {WordPad, rvviDelay, EthType, DstMac, SrcMac};
-
-  // *** fix me later
-  assign DstMac = 48'h8F54_0000_1654; // made something up
-  assign SrcMac = 48'h4502_1111_6843;
-  assign EthType = 16'h005c;
-  
-  assign RvviAxiWdata = TotalFrameWords[WordCount[4:0]];
-  assign RvviAxiWstrb = '1;
-  assign RvviAxiWlast = BurstDone & (CurrState == STATE_TRANS);
-  assign RvviAxiWvalid = (CurrState == STATE_TRANS);
-  
-endmodule
- 
diff --git a/src/rvvi/priorityaomux.sv b/src/rvvi/priorityaomux.sv
deleted file mode 100644
index 7b119a81f..000000000
--- a/src/rvvi/priorityaomux.sv
+++ /dev/null
@@ -1,46 +0,0 @@
-///////////////////////////////////////////
-// priorityaomux.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 24 January 2024
-// Modified: 24 January 2024
-//
-// Purpose: priority AND-OR MUX.
-//
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module priorityaomux #(parameter ROWS = 8, COLS = 64) (
-  input logic [ROWS-1:0]  Sel,
-  input                   var logic [COLS-1:0] A [ROWS-1:0],
-  output logic [COLS-1:0] Y,
-  output logic [ROWS-1:0] SelPriority);
-
-  logic [COLS-1:0]           AMasked [ROWS-1:0];
-  genvar                     index;
-  
-  priorityonehot #(ROWS) priorityonehot(Sel, SelPriority);
-  for(index = 0; index < ROWS; index = index + 1) begin
-    assign AMasked[index] = SelPriority[index] ? A[index] : '0;
-  end
-  or_rows #(ROWS, COLS) or_rows(AMasked, Y);
-
-endmodule
-  
diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv
deleted file mode 100644
index 3e8170c93..000000000
--- a/src/rvvi/rvvisynth.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-///////////////////////////////////////////
-// rvvisynth.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: 23 January 2024
-// Modified: 23 January 2024
-//
-// Purpose: Synthesizable rvvi bridge from Wally to generic compressed format.
-//
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module rvvisynth import cvw::*; #(parameter cvw_t P,
-                                  parameter integer MAX_CSRS = 5, 
-                                  parameter integer TOTAL_CSRS = 36)(
-  input logic clk, reset,
-  input logic                                     StallE, StallM, StallW, FlushE, FlushM, FlushW,
-  // required
-  input logic [P.XLEN-1:0]                        PCM,
-  input logic                                     InstrValidM,
-  input logic [31:0]                              InstrRawD,
-  input logic [63:0]                              Mcycle, Minstret,
-  input logic                                     TrapM,
-  input logic [1:0]                               PrivilegeModeW,
-  // registers gpr and fpr
-  input logic                                     GPRWen, FPRWen,
-  input logic [4:0]                               GPRAddr, FPRAddr,
-  input logic [P.XLEN-1:0]                        GPRValue, FPRValue,
-  input var logic [P.XLEN-1:0]                    CSRArray [TOTAL_CSRS-1:0],
-  output logic valid,
-  output logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi
-  );
-
-  // pipeline controlls
-
-  // required
-  logic [P.XLEN-1:0]                        PCW;
-  logic                                     InstrValidW;
-  logic [31:0]                              InstrRawE, InstrRawM, InstrRawW;
-  logic                                     TrapW;
-
-  // registers gpr and fpr
-  logic [P.XLEN-1:0]                        XLENZeros;
-  logic [TOTAL_CSRS-1:0]                    CSRArrayWen;
-  logic [P.XLEN-1:0]                        CSRValue [MAX_CSRS-1:0];
-  logic [TOTAL_CSRS-1:0]                    CSRWen [MAX_CSRS-1:0];
-  logic [11:0]                              CSRAddr [MAX_CSRS-1:0];
-  logic [MAX_CSRS-1:0]                      EnabledCSRs;
-  logic [MAX_CSRS-1:0]                      CSRCountShort;
-  logic [11:0]                              CSRCount;
-  logic [56+3*P.XLEN-1:0]                   Required;
-  logic [16+2*P.XLEN-1:0]                   Registers;
-  logic [MAX_CSRS*(P.XLEN+16)-1:0]          CSRs;
-     
-  assign XLENZeros = '0;
-
-  // start out easy and just populate Required
-  // PC, inst, mcycle, minstret, trap, mode
-  
-  flopenrc #(1)      InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
-  flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
-  flopenrc #(32)     InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
-  flopenrc #(32)     InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(32)     InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(1)      TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
-
-  assign valid  = InstrValidW & ~StallW;
-  assign Required = {4'b0, CSRCount, 3'b0, FPRWen, GPRWen, PrivilegeModeW, TrapW, Minstret, Mcycle, InstrRawW, PCW};
-  assign Registers = {FPRWen, GPRWen} == 2'b11 ? {FPRValue, 3'b0, FPRAddr, GPRValue, 3'b0, GPRAddr} :
-                     {FPRWen, GPRWen} == 2'b01 ? {XLENZeros, 8'b0, GPRValue, 3'b0, GPRAddr} :
-                     {FPRWen, GPRWen} == 2'b10 ? {FPRValue, 3'b0, FPRAddr, XLENZeros, 8'b0} :
-                     '0;
-
-  /* verilator lint_off UNOPTFLAT */
-  // For some reason verilator complains about CSRWenFilterMatrix being in a circular loop when it is not.
-
-  // the CSRs are complex
-  // 1. we need to get the CSR values
-  // 2. we check if the CSR value changes by registering the value then XORing with the old value.
-  // 3. Then use priorityaomux to collect CSR values and addresses for compating into the compressed rvvi format
-
-  // step 2
-  genvar                                   index;
-  for (index = 0; index < TOTAL_CSRS; index = index + 1) begin
-    regchangedetect #(P.XLEN) changedetect(clk, reset, CSRArray[index], CSRArrayWen[index]);
-  end
-
-  // step 3a
-  logic [TOTAL_CSRS-1:0] CSRWenPriorityMatrix [MAX_CSRS-1:0];
-  logic [TOTAL_CSRS-1:0] CSRWenFilterMatrix [MAX_CSRS-1:0];
-  
-  priorityaomux #(TOTAL_CSRS, P.XLEN) firstpriorityaomux(CSRArrayWen, CSRArray, CSRValue[0], CSRWenPriorityMatrix[0]);
-  assign CSRWenFilterMatrix[0] = CSRArrayWen;
-
-  for(index = 1; index < MAX_CSRS; index = index + 1) begin
-    priorityaomux #(TOTAL_CSRS, P.XLEN) priorityaomux(CSRWenFilterMatrix[index], CSRArray, CSRValue[index], CSRWenPriorityMatrix[index]);
-    assign CSRWenFilterMatrix[index] = CSRWenFilterMatrix[index-1] & ~CSRWenPriorityMatrix[index-1];
-  end
-  for(index = 0; index < MAX_CSRS; index = index + 1) begin
-    // step 3b
-    csrindextoaddr #(TOTAL_CSRS) csrindextoaddr(CSRWenPriorityMatrix[index], CSRAddr[index]);
-    assign CSRs[(index+1) * (P.XLEN + 16)- 1: index * (P.XLEN + 16)] = {CSRValue[index], 4'b0, CSRAddr[index]};
-    assign EnabledCSRs[index] = |CSRWenPriorityMatrix[index];
-  end
-
-  integer index2;
-  always_comb begin
-    CSRCountShort = '0;
-    for(index2 = 0; index2 < MAX_CSRS; index2++) begin
-      /* verilator lint_off WIDTHEXPAND */
-      CSRCountShort += EnabledCSRs[index2];
-      /* verilator lint_on WIDTHEXPAND */
-    end
-  end
-  /* verilator lint_on UNOPTFLAT */
-
-  assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort};
-  assign rvvi = {CSRs, Registers, Required};
-  
-endmodule
-                                                                 
diff --git a/src/rvvi/triggergen.sv b/src/rvvi/triggergen.sv
deleted file mode 100644
index 58de7fe8c..000000000
--- a/src/rvvi/triggergen.sv
+++ /dev/null
@@ -1,110 +0,0 @@
-///////////////////////////////////////////
-// triggergen.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Created: June 26, 2024
-// Modified: June 26, 2024
-//
-// Purpose: Scans for specific ethernet frame to generate an ila trigger.
-//
-// Documentation: 
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module triggergen import cvw::*; (
-  input logic clk, reset,
-  input logic [31:0] RvviAxiRdata,
-  input logic [3:0] RvviAxiRstrb,
-  input logic RvviAxiRlast,
-  input logic RvviAxiRvalid,
-  output logic IlaTrigger);
-
-  typedef enum logic[2:0] {STATE_RST, STATE_COMPARE, STATE_MISMATCH, STATE_TRIGGER, STATE_TRIGGER_DONE} statetype;
-(* mark_debug = "true" *)  statetype CurrState, NextState;
-
-  logic [31:0] 	    mem [4:0];
-  logic [2:0] 		    Counter;	
-  logic 		    CounterEn, CounterRst;
-  logic [31:0] 	    RvviAxiRdataDelay;
-  logic [3:0] 	    RvviAxiRstrbDelay;
-  logic 	    RvviAxiRvalidDelay;
-  logic 	    Match, Overflow, Mismatch, Threshold;
-  logic 	    IlaTriggerOneCycle;
-   
-  assign mem[0] = 32'h1111_6843; // dst mac [31:0]
-  assign mem[1] = 32'h1654_4502; // src mac [15:0], dst mac [47:32]
-  assign mem[2] = 32'h8f54_0000; // src mac [47:16]
-  assign mem[3] = 32'h7274_005c; // "rt", ether type 005c
-  assign mem[4] = 32'h6e69_6769; // "igin" (trigin)
-   
-  flopenr #(32) rvviaxirdatareg(clk, reset, RvviAxiRvalid, RvviAxiRdata, RvviAxiRdataDelay);
-  flopenr #(4) rvviaxirstrbreg(clk, reset, RvviAxiRvalid, RvviAxiRstrb, RvviAxiRstrbDelay);
-  flopr #(1) rvviaxirvalidreg(clk, reset, RvviAxiRvalid, RvviAxiRvalidDelay); 
-
-  counter #(3) counter(clk, CounterRst, CounterEn, Counter);
-  
-  always_ff @(posedge clk) begin
-    if(reset) CurrState <= STATE_RST;
-    else      CurrState <= NextState;
-  end
-
-  always_comb begin
-    case(CurrState)
-      STATE_RST: if(RvviAxiRvalid) NextState = STATE_COMPARE;
-                 else NextState = STATE_RST;
-      STATE_COMPARE: if(RvviAxiRlast) NextState = STATE_RST;
-                     else if(Mismatch | Overflow) NextState = STATE_MISMATCH;
-                     else if(Threshold & Match) NextState = STATE_TRIGGER;
-                     else NextState = STATE_COMPARE;
-      STATE_MISMATCH: if(RvviAxiRlast) NextState = STATE_RST;
-                      else NextState = STATE_MISMATCH;
-      STATE_TRIGGER: if(RvviAxiRlast) NextState = STATE_RST;
-                     else NextState = STATE_TRIGGER_DONE;
-      STATE_TRIGGER_DONE: if(RvviAxiRlast) NextState = STATE_RST;
-                          else NextState = STATE_TRIGGER_DONE;
-      default: NextState = STATE_RST;
-    endcase
-  end
-
-  assign Match = (mem[Counter] == RvviAxiRdataDelay) & (CurrState == STATE_COMPARE) & RvviAxiRvalidDelay;
-  assign Overflow = Counter > 4'd4;
-  assign Threshold = Counter >= 4'd4;
-  assign Mismatch =  (mem[Counter] != RvviAxiRdataDelay) & (CurrState == STATE_COMPARE) & RvviAxiRvalidDelay;
-  assign IlaTriggerOneCycle = CurrState == STATE_TRIGGER;
-  assign CounterRst = CurrState == STATE_RST;
-  assign CounterEn = RvviAxiRvalid;
-
-/* -----\/----- EXCLUDED -----\/-----
-  always_ff @(posedge clk) begin
-    if(reset) IlaTrigger <= '0;
-    else if (IlaTriggerOneCycle) IlaTrigger <= '1;
-    else if (IlaTriggerAck) IlaTrigger <= '0;
-    else IlaTrigger <= IlaTrigger;
-  end
- -----/\----- EXCLUDED -----/\----- */
-
-  // this is a bit hacky, but it works!
-  logic [3:0] TriggerCount;
-  logic       TriggerReset, TriggerEn;
-  counter #(4) triggercounter(clk, reset | TriggerReset, TriggerEn, TriggerCount);
-  assign TriggerReset = TriggerCount == 4'd10;
-  assign TriggerEn = IlaTriggerOneCycle | (TriggerCount != 4'd0 & TriggerCount < 4'd10);
-  assign IlaTrigger = TriggerEn;
-
-endmodule
diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
deleted file mode 100644
index 7721d9986..000000000
--- a/src/uncore/gpio_apb.sv
+++ /dev/null
@@ -1,165 +0,0 @@
-///////////////////////////////////////////
-// gpio_apb.sv
-//
-// Written: David_Harris@hmc.edu 14 January 2021
-// Modified: bbracker@hmc.edu 15 Apr. 2021
-//
-// Purpose: General Purpose I/O peripheral
-//   See FE310-G002-Manual-v19p05 for specifications
-//   No interrupts, drive strength, or pull-ups supported
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module gpio_apb import cvw::*;  #(parameter cvw_t P) (
-  input  logic                PCLK, PRESETn,
-  input  logic                PSEL,
-  input  logic [7:0]          PADDR, 
-  input  logic [P.XLEN-1:0]   PWDATA,
-  input  logic [P.XLEN/8-1:0] PSTRB,
-  input  logic                PWRITE,
-  input  logic                PENABLE,
-  output logic [P.XLEN-1:0]   PRDATA,
-  output logic                PREADY,
-  input  logic [31:0]         iof0, iof1,
-  input  logic [31:0]         GPIOIN,
-  output logic [31:0]         GPIOOUT, GPIOEN,
-  output logic                GPIOIntr
-);
-
-  // register map
-  localparam GPIO_INPUT_VAL  = 8'h00;
-  localparam GPIO_INPUT_EN   = 8'h04;
-  localparam GPIO_OUTPUT_EN  = 8'h08;
-  localparam GPIO_OUTPUT_VAL = 8'h0C;
-  localparam GPIO_RISE_IE    = 8'h18;
-  localparam GPIO_RISE_IP    = 8'h1C;
-  localparam GPIO_FALL_IE    = 8'h20;
-  localparam GPIO_FALL_IP    = 8'h24;
-  localparam GPIO_HIGH_IE    = 8'h28;
-  localparam GPIO_HIGH_IP    = 8'h2C;
-  localparam GPIO_LOW_IE     = 8'h30;
-  localparam GPIO_LOW_IP     = 8'h34;
-  localparam GPIO_IOF_EN     = 8'h38;
-  localparam GPIO_IOF_SEL    = 8'h3C;
-  localparam GPIO_OUT_XOR    = 8'h40;
-
-  logic [31:0]                input0d, input1d, input2d, input3d;
-  logic [31:0]                input_val, input_en, output_en, output_val;
-  logic [31:0]                rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; 
-  logic [31:0]                out_xor, iof_en, iof_sel, iof_out, gpio_out;
-  logic [7:0]                 entry;
-  logic [31:0]                Din, Dout;
-  logic                       memwrite;
-  
-  // APB I/O
-  assign entry    = {PADDR[7:2],2'b00};       // 32-bit word-aligned accesses
-  assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign PREADY   = 1'b1;                     // GPIO never takes >1 cycle to respond
-
-  // account for subword read/write circuitry
-  // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
-  assign Din = PWDATA[31:0]; 
-  if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; 
-  else              assign PRDATA = Dout;    
-
-  // register access
-  always_ff @(posedge PCLK)
-    if (~PRESETn) begin
-      input_en  <= '0;
-      output_en <= '0;
-      output_val <= '0;
-      rise_ie    <= '0;
-      rise_ip    <= '0;
-      fall_ie    <= '0;
-      fall_ip    <= '0;
-      high_ie    <= '0;
-      high_ip    <= '0;
-      low_ie     <= '0;
-      low_ip     <= '0;
-      iof_en     <= '0;
-      iof_sel    <= '0;
-      out_xor    <= '0;
-    end else begin     // writes
-        // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
-        /* verilator lint_off CASEINCOMPLETE */
-      if (memwrite) 
-        case(entry)
-          GPIO_INPUT_EN:   input_en   <= Din;
-          GPIO_OUTPUT_EN:  output_en  <= Din;
-          GPIO_OUTPUT_VAL: output_val <= Din;
-          GPIO_RISE_IE:    rise_ie    <= Din;
-          GPIO_FALL_IE:    fall_ie    <= Din;
-          GPIO_HIGH_IE:    high_ie    <= Din;
-          GPIO_LOW_IE:     low_ie     <= Din;
-          GPIO_IOF_EN:     iof_en     <= Din;
-          GPIO_IOF_SEL:    iof_sel    <= Din;
-          GPIO_OUT_XOR:    out_xor    <= Din;
-        endcase
-        /* verilator lint_on CASEINCOMPLETE */
-
-      // interrupts can be cleared by writing corresponding bits to a register
-      if (memwrite & entry == GPIO_RISE_IP)   rise_ip <= rise_ip & ~Din;
-      else                                    rise_ip <= rise_ip | (input2d & ~input3d);
-      if (memwrite & (entry == GPIO_FALL_IP)) fall_ip <= fall_ip & ~Din;
-      else                                    fall_ip <= fall_ip | (~input2d & input3d);
-      if (memwrite & (entry == GPIO_HIGH_IP)) high_ip <= high_ip & ~Din;
-      else                                    high_ip <= high_ip | input3d;
-      if (memwrite & (entry == GPIO_LOW_IP))  low_ip  <= low_ip  & ~Din;
-      else                                    low_ip  <= low_ip  | ~input3d;
-
-      case(entry) // flop to sample inputs
-        GPIO_INPUT_VAL:   Dout <= input_val;
-        GPIO_INPUT_EN:    Dout <= input_en;
-        GPIO_OUTPUT_EN:   Dout <= output_en;
-        GPIO_OUTPUT_VAL:  Dout <= output_val;
-        GPIO_RISE_IE:     Dout <= rise_ie;
-        GPIO_RISE_IP:     Dout <= rise_ip;
-        GPIO_FALL_IE:     Dout <= fall_ie;
-        GPIO_FALL_IP:     Dout <= fall_ip;
-        GPIO_HIGH_IE:     Dout <= high_ie;
-        GPIO_HIGH_IP:     Dout <= high_ip;
-        GPIO_LOW_IE:      Dout <= low_ie;
-        GPIO_LOW_IP:      Dout <= low_ip;
-        GPIO_IOF_EN:      Dout <= iof_en;
-        GPIO_IOF_SEL:     Dout <= iof_sel;
-        GPIO_OUT_XOR:     Dout <= out_xor; 
-        default:          Dout <= '0;
-      endcase
-    end
-
-  // chip i/o
-  // connect OUT to IN for loopback testing
-  if (P.GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOOUT) | (~output_en & GPIOIN)) & input_en;
-  else                      assign input0d = GPIOIN & input_en;
-
-  // synchroninzer for inputs
-  flop #(32) sync1(PCLK,input0d,input1d);
-  flop #(32) sync2(PCLK,input1d,input2d);
-  flop #(32) sync3(PCLK,input2d,input3d);
-  assign input_val = input3d;
-  assign iof_out   = iof_sel & iof1 | ~iof_sel & iof0;        // per-bit mux between iof1 and iof0
-  assign gpio_out  = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val
-  assign GPIOOUT   = gpio_out ^ out_xor;                      // per-bit flip output polarity
-  assign GPIOEN    = output_en;
-
-  assign GPIOIntr  = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
-endmodule
diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
deleted file mode 100644
index 607994906..000000000
--- a/src/uncore/plic_apb.sv
+++ /dev/null
@@ -1,257 +0,0 @@
-///////////////////////////////////////////
-// plic_apb.sv
-//
-// Written: bbracker@hmc.edu 18 January 2021
-// Modified: 
-//
-// Purpose: Platform-Level Interrupt Controller
-//   Based on RISC-V spec (https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
-//   With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
-//   Supports only 1 target core and only a global threshold.
-//   This PLIC implementation serves as both the PLIC Gateways and PLIC Core.
-//   It assumes interrupt sources are level-triggered wires.
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// number of interrupt sources
-// does not include source 0, which does not connect to anything according to spec
-// up to 63 sources supported; in the future, allow up to 1023 sources
-
-`define C 2
-// number of conexts
-// hardcoded to 2 contexts for now; later upgrade to arbitrary (up to 15872) contexts
-
-module plic_apb import cvw::*;  #(parameter cvw_t P) (
-  input  logic                PCLK, PRESETn,
-  input  logic                PSEL,
-  input  logic [27:0]         PADDR, 
-  input  logic [P.XLEN-1:0]   PWDATA,
-  input  logic [P.XLEN/8-1:0] PSTRB,
-  input  logic                PWRITE,
-  input  logic                PENABLE,
-  output logic [P.XLEN-1:0]   PRDATA,
-  output logic                PREADY,
-  input  logic                UARTIntr,GPIOIntr, SPIIntr, SDCIntr,
-  output logic                MExtInt, SExtInt
-);
-
-  // register map
-  localparam PLIC_INTPRIORITY0   = 24'h000000;
-  localparam PLIC_INTPENDING0    = 24'h001000;
-  localparam PLIC_INTPENDING1    = 24'h001004;
-  localparam PLIC_INTEN00        = 24'h002000;
-  localparam PLIC_INTEN01        = 24'h002004;
-  localparam PLIC_INTEN10        = 24'h002080;
-  localparam PLIC_INTEN11        = 24'h002084;
-  localparam PLIC_THRESHOLD0     = 24'h200000;
-  localparam PLIC_CLAIMCOMPLETE0 = 24'h200004;
-  localparam PLIC_THRESHOLD1     = 24'h201000;
-  localparam PLIC_CLAIMCOMPLETE1 = 24'h201004;
-
-  logic                       memwrite, memread;
-  logic [23:0]                entry;
-  logic [31:0]                Din, Dout;
-
-  // context-independent signals
-  logic [P.PLIC_NUM_SRC:1]               requests;
-  logic [P.PLIC_NUM_SRC:1][2:0]          intPriority;
-  logic [P.PLIC_NUM_SRC:1]               intInProgress, intPending, nextIntPending;
-  
-  // context-dependent signals
-  logic [`C-1:0][2:0]        intThreshold;
-  logic [`C-1:0][P.PLIC_NUM_SRC:1]       intEn;
-  logic [`C-1:0][5:0]        intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][P.PLIC_NUM_SRC:1]  irqMatrix;
-  logic [`C-1:0][7:1]        priorities_with_irqs;
-  logic [`C-1:0][7:1]        max_priority_with_irqs;
-  logic [`C-1:0][P.PLIC_NUM_SRC:1]       irqs_at_max_priority;
-  logic [`C-1:0][7:1]        threshMask;
-  logic [P.PLIC_NUM_SRC-1:0] One;
-
-  // hacks to handle gracefully PLIC_NUM_SRC being smaller than 32
-  // Otherwise Questa and other simulators produce part-select out of bounds even 
-  // though sources >=32 are never used
-
-  localparam PLIC_SRC_TOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC : 1;
-  localparam PLIC_SRC_BOT = (P.PLIC_NUM_SRC >= 32) ? 32 : 1;
-  localparam PLIC_SRC_DINTOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC -32 : 0;
-  localparam PLIC_SRC_EXT = (P.PLIC_NUM_SRC >= 32) ? 63-P.PLIC_NUM_SRC : 31;
- 
-  // =======
-  // AHB I/O
-  // =======
-
-  assign memwrite = PWRITE & PENABLE & PSEL;  // only write in access phase
-  assign memread  = ~PWRITE & PSEL;           // read at start of access phase.  PENABLE hasn't set up before this
-  assign PREADY   = 1'b1;                     // PLIC never takes >1 cycle to respond
-  assign entry    = {PADDR[23:2],2'b0};
-  assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment.
-
-  // account for subword read/write circuitry
-  // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
-  assign Din = PWDATA[31:0]; 
-  if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; 
-  else              assign PRDATA = Dout;    
-
-  // ==================
-  // Register Interface
-  // ==================
-  localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31;
-    
-  always_ff @(posedge PCLK) begin
-    // resetting
-    if (~PRESETn) begin
-      intPriority   <= '0;
-      intEn         <= '0;
-      intThreshold  <= '0;
-      intInProgress <= '0;
-    // writing
-    end else begin
-      if (memwrite)        
-        casez(entry)
-          24'h0000??:          intPriority[entry[7:2]] <= Din[2:0];
-          PLIC_INTEN00:        intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
-          PLIC_INTEN10:        intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
-          PLIC_INTEN01:        if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
-          PLIC_INTEN11:        if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
-          PLIC_THRESHOLD0:     intThreshold[0]         <= Din[2:0];
-          PLIC_CLAIMCOMPLETE0: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
-          PLIC_THRESHOLD1:     intThreshold[1]         <= Din[2:0];
-          PLIC_CLAIMCOMPLETE1: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
-        endcase
-
-      // Read synchronously because a read can have side effect of changing intInProgress
-      if (memread) begin
-        casez(entry)
-          PLIC_INTPRIORITY0: Dout <= 32'b0;  // there is no intPriority[0]
-          24'h0000??:        Dout <= {29'b0,intPriority[entry[7:2]]};      
-          PLIC_INTPENDING0:  Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0};
-          PLIC_INTEN00:      Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          PLIC_INTPENDING1:  if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          PLIC_INTEN01:      if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          PLIC_INTEN10:      Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          PLIC_INTEN11:      if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          PLIC_THRESHOLD0:   Dout <= {29'b0,intThreshold[0]};
-          PLIC_CLAIMCOMPLETE0: begin
-            Dout <= {26'b0,intClaim[0]};
-            intInProgress <= intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
-          end
-          PLIC_THRESHOLD1:   Dout <= {29'b0,intThreshold[1]};
-          PLIC_CLAIMCOMPLETE1: begin
-            Dout <= {26'b0,intClaim[1]};
-            intInProgress <= intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
-          end
-          default:           Dout <= 32'h0; // invalid access
-        endcase
-      end else               Dout <= 32'h0;
-   end
-  end
-
-  // connect sources to requests
-  always_comb begin
-    requests = {P.PLIC_NUM_SRC{1'b0}};
-    if(P.PLIC_GPIO_ID != 0) requests[P.PLIC_GPIO_ID] = GPIOIntr;
-    if(P.PLIC_UART_ID != 0) requests[P.PLIC_UART_ID] = UARTIntr;
-    if(P.PLIC_SPI_ID != 0) requests[P.PLIC_SPI_ID] = SPIIntr;
-    if(P.PLIC_SDC_ID !=0)   requests[P.PLIC_SDC_ID]  = SDCIntr;
-  end
-
-  // pending interrupt request
-  assign nextIntPending = (intPending | requests) & ~intInProgress; 
-  flopr #(P.PLIC_NUM_SRC) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
-
-  // context-dependent signals
-  genvar ctx;
-  for (ctx=0; ctx<`C; ctx++) begin
-    // request matrix 
-    //   priority level (rows) X source ID (columns)
-    //
-    //   irqMatrix[ctx][pri][src] is high if source <src>
-    //   has priority level <pri> and has an "active" interrupt request
-    //   ("active" meaning it is enabled in context <ctx> and is pending)
-    genvar src, pri;
-    for (pri=1; pri<=7; pri++) begin
-      for (src=1; src<=P.PLIC_NUM_SRC; src++) begin
-        assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src];
-      end
-    end
-
-    // which prority levels have one or more active requests?
-    assign priorities_with_irqs[ctx][7:1] = {
-      |irqMatrix[ctx][7],
-      |irqMatrix[ctx][6],
-      |irqMatrix[ctx][5],
-      |irqMatrix[ctx][4],
-      |irqMatrix[ctx][3],
-      |irqMatrix[ctx][2],
-      |irqMatrix[ctx][1]
-    }; 
-
-    // get the highest priority level that has active requests
-    assign max_priority_with_irqs[ctx][7:1] = {
-      priorities_with_irqs[ctx][7],
-      priorities_with_irqs[ctx][6] & ~|priorities_with_irqs[ctx][7],
-      priorities_with_irqs[ctx][5] & ~|priorities_with_irqs[ctx][7:6],
-      priorities_with_irqs[ctx][4] & ~|priorities_with_irqs[ctx][7:5],
-      priorities_with_irqs[ctx][3] & ~|priorities_with_irqs[ctx][7:4],
-      priorities_with_irqs[ctx][2] & ~|priorities_with_irqs[ctx][7:3],
-      priorities_with_irqs[ctx][1] & ~|priorities_with_irqs[ctx][7:2]
-    };
-
-    // of the sources at the highest priority level that has active requests,
-    // which sources have active requests?
-    assign irqs_at_max_priority[ctx][P.PLIC_NUM_SRC:1] =
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
-      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
-
-    // of the sources at the highest priority level that has active requests,
-    // choose the source with the lowest source ID to be the most urgent
-    // and set intClaim to the source ID of the most urgent active request
-    integer k;
-    always_comb begin
-      intClaim[ctx] = 6'b0;
-      for (k=P.PLIC_NUM_SRC; k>0; k--) begin
-        if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0];
-      end
-    end
-    
-    // create threshold mask
-    always_comb begin
-      threshMask[ctx][7] = (intThreshold[ctx] != 7);
-      threshMask[ctx][6] = (intThreshold[ctx] != 6) & threshMask[ctx][7];
-      threshMask[ctx][5] = (intThreshold[ctx] != 5) & threshMask[ctx][6];
-      threshMask[ctx][4] = (intThreshold[ctx] != 4) & threshMask[ctx][5];
-      threshMask[ctx][3] = (intThreshold[ctx] != 3) & threshMask[ctx][4];
-      threshMask[ctx][2] = (intThreshold[ctx] != 2) & threshMask[ctx][3];
-      threshMask[ctx][1] = (intThreshold[ctx] != 1) & threshMask[ctx][2];
-    end
-  end
-  // is the max priority > threshold?
-  // would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
-  assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
-  assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
-endmodule
diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
deleted file mode 100644
index 4f4fcbc40..000000000
--- a/src/uncore/spi_apb.sv
+++ /dev/null
@@ -1,351 +0,0 @@
-///////////////////////////////////////////
-// spi_apb.sv
-//
-// Written: Naiche Whyte-Aguayo nwhyteaguayo@g.hmc.edu
-//          Jacob Pease jacobpease@protonmail.com (October 29th, 2024)
-// Created: November 16th, 2022
-//
-// Purpose: SPI peripheral
-//
-// SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers. 
-// The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
-// to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output, 
-// along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
-// Current limitations: Flash read sequencer mode not implemented, dual and quad mode not supported
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module spi_apb import cvw::*; #(parameter cvw_t P) (
-  input  logic                PCLK, PRESETn,
-  input  logic                PSEL,
-  input  logic [7:0]          PADDR,
-  input  logic [P.XLEN-1:0]   PWDATA,
-  input  logic [P.XLEN/8-1:0] PSTRB,
-  input  logic                PWRITE,
-  input  logic                PENABLE,
-  output logic                PREADY,
-  output logic [P.XLEN-1:0]   PRDATA,
-  output logic                SPIOut,
-  input  logic                SPIIn,
-  output logic [3:0]          SPICS,
-  output logic                SPIIntr,
-  output logic                SPICLK
-);
-
-  // register map
-  localparam SPI_SCKDIV =  8'h00;
-  localparam SPI_SCKMODE = 8'h04;
-  localparam SPI_CSID =    8'h10;
-  localparam SPI_CSDEF =   8'h14;
-  localparam SPI_CSMODE =  8'h18;
-  localparam SPI_DELAY0 =  8'h28;
-  localparam SPI_DELAY1 =  8'h2C;
-  localparam SPI_FMT =     8'h40;
-  localparam SPI_TXDATA =  8'h48;
-  localparam SPI_RXDATA =  8'h4C;
-  localparam SPI_TXMARK =  8'h50;
-  localparam SPI_RXMARK =  8'h54;
-  localparam SPI_IE =      8'h70;
-  localparam SPI_IP =      8'h74;
-  
-  // SPI control registers. Refer to SiFive FU540-C000 manual 
-  logic [11:0] SckDiv;
-  logic [1:0]  SckMode;
-  logic [1:0]  ChipSelectID;
-  logic [3:0]  ChipSelectDef; 
-  logic [1:0]  ChipSelectMode;
-  logic [15:0] Delay0, Delay1;
-  logic [4:0]  Format;
-  logic [7:0]  ReceiveData;
-  logic [8:0]  TransmitData;
-  logic [2:0]  TransmitWatermark, ReceiveWatermark;
-  logic [1:0]  InterruptEnable, InterruptPending;
-
-  // Bus interface signals
-  logic [7:0]  Entry;
-  logic        Memwrite;
-  logic [31:0] Din,  Dout;
-
-  // SPI Controller signals
-  logic        SCLKenable;
-  logic        EndOfFrame;
-  logic        Transmitting;
-  logic        InactiveState;
-  logic [3:0]  FrameLength;  
-
-  // Starting Transmission and restarting SCLKenable
-  logic        ResetSCLKenable;
-  logic        TransmitStart;
-  logic        TransmitStartD;
-
-  // Transmit Start State Machine Variables
-  typedef enum logic [1:0] {READY, START, WAIT} txState;
-  txState CurrState, NextState;
-  
-  // FIFO Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
-  logic        TransmitWriteMark, TransmitReadMark, ReceiveWriteMark, ReceiveReadMark;
-
-  // Transmit FIFO Signals
-  logic        TransmitFIFOFull, TransmitFIFOEmpty;
-  logic        TransmitFIFOWriteInc;
-  logic        TransmitFIFOReadInc;                // Increments Tx FIFO read ptr 1 cycle after Tx FIFO is read
-  logic [7:0]  TransmitReadData;
-
-  // ReceiveFIFO Signals
-  logic        ReceiveFIFOWriteInc;
-  logic        ReceiveFIFOReadInc;
-  logic        ReceiveFIFOFull, ReceiveFIFOEmpty;
-  
-  /* verilator lint_off UNDRIVEN */
-  logic [2:0]  TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
-  /* verilator lint_on UNDRIVEN */
-  logic [7:0]  ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
-
-  // Shift reg signals
-  logic        ShiftEdge;                          // Determines which edge of sck to shift from TransmitReg
-  logic        SampleEdge;                         // Determines which edge of sck to sample from ReceiveShiftReg
-  logic [7:0]  TransmitReg;                        // Transmit shift register
-  logic [7:0]  ReceiveShiftReg;                    // Receive shift register
-  logic [7:0]  TransmitDataEndian;                 // Reverses TransmitData from txFIFO if littleendian, since TransmitReg always shifts MSB
-  logic        TransmitLoad;                       // Determines when to load TransmitReg
-  logic        TransmitRegLoaded;
-
-  // Shift stuff due to Format register?
-  logic        ShiftIn;                            // Determines whether to shift from SPIIn or SPIOut (if SPI_LOOPBACK_TEST)  
-  logic [3:0]  LeftShiftAmount;                    // Determines left shift amount to left-align data when little endian              
-  logic [7:0]  ASR;                                // AlignedReceiveShiftReg   
-
-  // CS signals
-  logic [3:0]  ChipSelectAuto;                     // Assigns ChipSelect value to selected CS signal based on CS ID
-  logic [3:0]  ChipSelectInternal;                 // Defines what each ChipSelect signal should be based on transmission status and ChipSelectDef
-
-  // APB access
-  assign Entry = {PADDR[7:2],2'b00};  //  32-bit word-aligned accesses
-  assign Memwrite = PWRITE & PENABLE & PSEL;  // Only write in access phase
-  assign PREADY = 1'b1;
-  
-  // Account for subword read/write circuitry
-  // -- Note SPI registers are 32 bits no matter what; access them with LW SW.
-  
-  assign Din = PWDATA[31:0]; 
-  if (P.XLEN == 64) assign PRDATA = { Dout,  Dout}; 
-  else              assign PRDATA =  Dout;  
-  
-  // Register access  
-  always_ff@(posedge PCLK)
-    if (~PRESETn) begin 
-      SckDiv <= 12'd3;
-      SckMode <= 2'b0;
-      ChipSelectID <= 2'b0;
-      ChipSelectDef <= 4'b1111;
-      ChipSelectMode <= 2'b0;
-      Delay0 <= {8'b1,8'b1};
-      Delay1 <= {8'b0,8'b1};
-      Format <= {5'b10000};
-      TransmitData <= 9'b0;
-      TransmitWatermark <= 3'b0;
-      ReceiveWatermark <= 3'b0;
-      InterruptEnable <= 2'b0;
-      InterruptPending <= 2'b0;
-    end else begin // writes
-      /* verilator lint_off CASEINCOMPLETE */
-      if (Memwrite)
-        case(Entry) // flop to sample inputs
-          SPI_SCKDIV:  SckDiv <= Din[11:0];
-          SPI_SCKMODE: SckMode <= Din[1:0];
-          SPI_CSID:    ChipSelectID <= Din[1:0];
-          SPI_CSDEF:   ChipSelectDef <= Din[3:0];
-          SPI_CSMODE:  ChipSelectMode <= Din[1:0];
-          SPI_DELAY0:  Delay0 <= {Din[23:16], Din[7:0]};
-          SPI_DELAY1:  Delay1 <= {Din[23:16], Din[7:0]};
-          SPI_FMT:     Format <= {Din[19:16], Din[2]};
-          SPI_TXDATA:  if (~TransmitFIFOFull) TransmitData[7:0] <= Din[7:0];
-          SPI_TXMARK:  TransmitWatermark <= Din[2:0];
-          SPI_RXMARK:  ReceiveWatermark <= Din[2:0];
-          SPI_IE:      InterruptEnable <= Din[1:0];
-        endcase
-      /* verilator lint_on CASEINCOMPLETE */
-      
-      // According to FU540 spec: Once interrupt is pending, it will remain set until number 
-      // of entries in tx/rx fifo is strictly more/less than tx/rxmark
-      InterruptPending[0] <= TransmitReadMark;
-      InterruptPending[1] <= ReceiveWriteMark;  
-      
-      case(Entry) // Flop to sample inputs
-        SPI_SCKDIV:  Dout <= {20'b0, SckDiv};
-        SPI_SCKMODE: Dout <= {30'b0, SckMode};
-        SPI_CSID:    Dout <= {30'b0, ChipSelectID};
-        SPI_CSDEF:   Dout <= {28'b0, ChipSelectDef};
-        SPI_CSMODE:  Dout <= {30'b0, ChipSelectMode};
-        SPI_DELAY0:  Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
-        SPI_DELAY1:  Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
-        SPI_FMT:     Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
-        SPI_TXDATA:  Dout <= {TransmitFIFOFull, 23'b0, 8'b0};
-        SPI_RXDATA:  Dout <= {ReceiveFIFOEmpty, 23'b0, ReceiveData[7:0]};
-        SPI_TXMARK:  Dout <= {29'b0, TransmitWatermark};
-        SPI_RXMARK:  Dout <= {29'b0, ReceiveWatermark};
-        SPI_IE:      Dout <= {30'b0, InterruptEnable};
-        SPI_IP:      Dout <= {30'b0, InterruptPending};
-        default:     Dout <= 32'b0;
-      endcase
-    end
-
-  // SPI Controller module -------------------------------------------
-  // This module controls state and timing signals that drive the rest of this module
-  assign ResetSCLKenable = Memwrite & (Entry == SPI_SCKDIV);
-  assign FrameLength = Format[4:1];
-  
-  spi_controller controller(PCLK, PRESETn,
-                            // Transmit Signals
-                            TransmitStart, TransmitRegLoaded, ResetSCLKenable,
-                            // Register Inputs
-                            SckDiv, SckMode, ChipSelectMode, Delay0, Delay1, FrameLength,
-                            // txFIFO stuff
-                            TransmitFIFOEmpty,
-                            // Timing
-                            SCLKenable, ShiftEdge, SampleEdge, EndOfFrame,
-                            // State stuff
-                            Transmitting, InactiveState,
-                            // Outputs
-                            SPICLK);
-  
-  // Transmit FIFO ---------------------------------------------------
-
-  // txFIFO write increment logic
-  flopr #(1) txwincreg(PCLK, ~PRESETn,
-                       (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOFull),
-                       TransmitFIFOWriteInc);
-
-  // txFIFO read increment logic
-  flopenr #(1) txrincreg(PCLK, ~PRESETn, SCLKenable,
-                         TransmitStartD | (EndOfFrame & ~TransmitFIFOEmpty),                  
-                         TransmitFIFOReadInc);
-  
-  // Check whether TransmitReg has been loaded.
-  // We use this signal to prevent returning to the Ready state for TransmitStart
-  always_ff @(posedge PCLK) begin
-    if (~PRESETn) begin
-      TransmitRegLoaded <= 1'b0;
-    end else if (TransmitLoad) begin
-      TransmitRegLoaded <= 1'b1;
-    end else if (ShiftEdge | EndOfFrame) begin
-      TransmitRegLoaded <= 1'b0;  
-    end
-  end
-  
-  // Setup TransmitStart state machine
-  always_ff @(posedge PCLK)
-    if (~PRESETn) CurrState <= READY;
-    else          CurrState <= NextState;
-  
-  // State machine for starting transmissions
-  always_comb begin
-    case (CurrState)
-      READY: if (~TransmitFIFOEmpty & ~Transmitting) NextState = START;
-             else NextState = READY;
-      START: NextState = WAIT;
-      WAIT: if (~Transmitting & ~TransmitRegLoaded) NextState = READY;
-            else NextState = WAIT;
-      default: NextState = READY;
-    endcase
-  end
-
-  // Delayed TransmitStart signal for incrementing tx read point.
-  assign TransmitStart = (CurrState == START);
-  always_ff @(posedge PCLK)
-    if (~PRESETn) TransmitStartD <= 1'b0;
-    else if (TransmitStart) TransmitStartD <= 1'b1;
-    else if (SCLKenable) TransmitStartD <= 1'b0;
-
-  // Transmit FIFO
-  spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn,
-                         TransmitFIFOWriteInc, TransmitFIFOReadInc,
-                         TransmitData[7:0],
-                         TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
-                         TransmitReadData[7:0],
-                         TransmitFIFOFull,
-                         TransmitFIFOEmpty,
-                         TransmitWriteMark, TransmitReadMark);
-
-  // Receive FIFO ----------------------------------------------------
-
-  // Receive FIFO Read Increment register
-  flopr #(1) rxfiforincreg(PCLK, ~PRESETn,
-                           ((Entry == SPI_RXDATA) & ~ReceiveFIFOEmpty & PSEL & ~ReceiveFIFOReadInc),
-                           ReceiveFIFOReadInc);
-
-  // Receive FIFO Write Increment register
-  flopenr #(1) rxfifowincreg(PCLK, ~PRESETn, SCLKenable,
-                             EndOfFrame, ReceiveFIFOWriteInc);
-
-  // Receive FIFO
-  spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn,
-                         ReceiveFIFOWriteInc, ReceiveFIFOReadInc,
-                         ReceiveShiftRegEndian, ReceiveWatermark[2:0],
-                         ReceiveReadWatermarkLevel, 
-                         ReceiveData[7:0],
-                         ReceiveFIFOFull,
-                         ReceiveFIFOEmpty,
-                         ReceiveWriteMark, ReceiveReadMark);
-
-  // Shift Registers --------------------------------------------------
-  // Transmit shift register
-  assign TransmitLoad = TransmitStart | (EndOfFrame & ~TransmitFIFOEmpty);
-  assign TransmitDataEndian = Format[0] ? {<<{TransmitReadData[7:0]}} : TransmitReadData[7:0];
-  always_ff @(posedge PCLK)
-    if(~PRESETn)            TransmitReg <= 8'b0;
-    else if (TransmitLoad)  TransmitReg <= TransmitDataEndian;
-    else if (ShiftEdge)     TransmitReg <= {TransmitReg[6:0], TransmitReg[0]};
-
-  assign SPIOut = TransmitReg[7];
-  
-  // If in loopback mode, receive shift register is connected directly
-  // to module's output pins. Else, connected to SPIIn. There are no
-  // setup/hold time issues because transmit shift register and receive
-  // shift register always shift/sample on opposite edges
-  assign ShiftIn = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
-  
-  // Receive shift register
-  always_ff @(posedge PCLK)
-    if(~PRESETn) begin
-      ReceiveShiftReg <= 8'b0;
-    end else if (SampleEdge) begin
-      ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn};
-    end
-
-  // Aligns received data and reverses if little-endian
-  assign LeftShiftAmount = 4'h8 - FrameLength;
-  assign ASR = ReceiveShiftReg << LeftShiftAmount[2:0];
-  assign ReceiveShiftRegEndian = Format[0] ? {<<{ASR[7:0]}} : ASR[7:0];
-
-  // Interrupt logic: raise interrupt if any enabled interrupts are pending
-  assign SPIIntr = |(InterruptPending & InterruptEnable);
-
-  // Chip select logic
-  assign ChipSelectInternal = InactiveState ? ChipSelectDef : ~ChipSelectDef;
-  always_comb
-    case(ChipSelectID[1:0])
-      2'b00: ChipSelectAuto = {ChipSelectDef[3], ChipSelectDef[2], ChipSelectDef[1], ChipSelectInternal[0]};
-      2'b01: ChipSelectAuto = {ChipSelectDef[3],ChipSelectDef[2], ChipSelectInternal[1], ChipSelectDef[0]};
-      2'b10: ChipSelectAuto = {ChipSelectDef[3],ChipSelectInternal[2], ChipSelectDef[1], ChipSelectDef[0]};
-      2'b11: ChipSelectAuto = {ChipSelectInternal[3],ChipSelectDef[2], ChipSelectDef[1], ChipSelectDef[0]};
-    endcase
-  assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
-  
-endmodule
diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
deleted file mode 100644
index 6438d39c5..000000000
--- a/src/uncore/spi_controller.sv
+++ /dev/null
@@ -1,303 +0,0 @@
-///////////////////////////////////////////
-// spi_controller.sv
-//
-// Written: Jacob Pease jacobpease@protonmail.com
-// Created: October 28th, 2024
-//
-// Purpose: Controller logic for SPI
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module spi_controller (                                            
-  input logic        PCLK,
-  input logic        PRESETn,
-
-  // Start Transmission
-  input logic        TransmitStart,
-  input logic        TransmitRegLoaded,
-  input logic        ResetSCLKenable, 
-
-  // Registers
-  input logic [11:0] SckDiv,
-  input logic [1:0]  SckMode,
-  input logic [1:0]  CSMode,
-  input logic [15:0] Delay0,
-  input logic [15:0] Delay1,
-  input logic [3:0]  FrameLength,
-
-  // Is the Transmit FIFO Empty?
-  input logic        TransmitFIFOEmpty,
-
-  // Control signals
-  output logic       SCLKenable,
-  output logic       ShiftEdge,
-  output logic       SampleEdge,
-  output logic       EndOfFrame, 
-  output logic       Transmitting,
-  output logic       InactiveState,
-  output logic       SPICLK
-);
-  
-  // CSMode Stuff
-  localparam         HOLDMODE = 2'b10;
-  localparam         AUTOMODE = 2'b00;
-  localparam         OFFMODE = 2'b11;         
-
-  // FSM States
-  typedef enum       logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype;
-  statetype CurrState, NextState;
-  
-  // SCLKenable stuff
-  logic [11:0]       DivCounter;
-  logic              SCK;
-
-  // Shift and Sample Edges
-  logic EdgePulse;
-  logic ShiftEdgePulse;
-  logic SampleEdgePulse;
-  logic EndOfFramePulse;
-  logic InvertClock;
-
-  // Frame stuff
-  logic [3:0] BitNum;
-  logic       LastBit;
-
-  // Transmit Stuff
-  logic       ContinueTransmit;       
-  logic       EndTransmission;
-  // logic       TransmitRegLoaded; // TODO: Could be replaced by TransmitRegLoaded?
-  logic       NextEndDelay;
-  logic       CurrentEndDelay;
-
-  // Delay Stuff
-  logic [7:0] cssck;
-  logic [7:0] sckcs;
-  logic [7:0] intercs;
-  logic [7:0] interxfr;
-  logic       Phase;
-  
-  logic       HasCSSCK;
-  logic       HasSCKCS;
-  logic       HasINTERCS;
-  logic       HasINTERXFR;
-  
-  logic       EndOfCSSCK;
-  logic       EndOfSCKCS;
-  logic       EndOfINTERCS;
-  logic       EndOfINTERXFR;
-  logic       EndOfDelay;       
-  
-  logic [7:0] DelayCounter;
-
-  logic       DelayState;
-  
-  // Convenient Delay Reg Names
-  assign cssck = Delay0[7:0];
-  assign sckcs = Delay0[15:8];
-  assign intercs = Delay1[7:0];
-  assign interxfr = Delay1[15:8];
-
-  // Do we have delay for anything?
-  assign HasCSSCK = cssck > 8'b0;
-  assign HasSCKCS = sckcs > 8'b0;
-  assign HasINTERCS = intercs > 8'b0;
-  assign HasINTERXFR = interxfr > 8'b0;
-
-  // Have we hit full delay for any of the delays?
-  assign EndOfCSSCK = (DelayCounter == cssck) & (CurrState == CSSCK);
-  assign EndOfSCKCS = (DelayCounter == sckcs) & (CurrState == SCKCS);
-  assign EndOfINTERCS = (DelayCounter == intercs) & (CurrState == INTERCS);
-  assign EndOfINTERXFR = (DelayCounter == interxfr) & (CurrState == INTERXFR);
-
-  assign EndOfDelay = EndOfCSSCK | EndOfSCKCS | EndOfINTERCS | EndOfINTERXFR;
-  
-  // Clock Signal Stuff -----------------------------------------------
-  // SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
-  // Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
-  // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
-  assign SCLKenable = DivCounter == SckDiv;
-
-  assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame;
-  assign EndTransmission = TransmitFIFOEmpty & EndOfFrame;
-  assign Phase = SckMode[0];
-  
-  always_ff @(posedge PCLK) begin
-    if (~PRESETn) begin
-      DivCounter <= 12'b0;
-      SPICLK <= SckMode[1];
-      SCK <= 0;
-      BitNum <= 4'h0;
-      DelayCounter <= 0;
-    end else begin
-      // SCK logic for delay times  
-      if (TransmitStart & ~DelayState) begin
-        SCK <= 0;
-      end else if (SCLKenable) begin
-        SCK <= ~SCK;
-      end
-
-      // Counter for all four delay types
-      if (DelayState & SCK & SCLKenable) begin
-        DelayCounter <= DelayCounter + 8'd1;
-      end else if ((SCLKenable & EndOfDelay) | Transmitting) begin
-        DelayCounter <= 8'd0;
-      end
-      
-      // SPICLK Logic
-      // We only want to trigger the clock during Transmission.
-      // If Phase == 1, then we want to trigger as soon as NextState == TRANSMIT
-      // Otherwise, only trigger the clock when the CurrState is TRANSMIT.
-      // We never want to trigger the clock if the NextState is NOT TRANSMIT
-      if (TransmitStart & ~DelayState) begin
-        SPICLK <= SckMode[1];
-        end else if (SCLKenable) begin
-        SPICLK <= (NextState == TRANSMIT) & (~Phase & Transmitting | Phase) ? ~SPICLK : SckMode[1];
-      end
-      
-      // Reset divider 
-      if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin
-        DivCounter <= 12'b0;
-      end else begin
-        DivCounter <= DivCounter + 12'd1;
-      end
-      
-      // Increment BitNum
-      if (ShiftEdge & Transmitting) begin
-        BitNum <= BitNum + 4'd1;
-      end else if (EndOfFrame) begin
-        BitNum <= 4'b0;  
-      end
-    end
-  end
-
-  // The very last bit in a frame of any length.
-  assign LastBit = (BitNum == FrameLength - 4'b1);
-  
-  // Any SCLKenable pulse aligns with leading or trailing edge during
-  // Transmission. We can use this signal as the basis for ShiftEdge
-  // and SampleEdge.
-  assign EdgePulse = SCLKenable & Transmitting;
-
-  // Possible pulses for all edge types. Combined with SPICLK to get
-  // edges for different phase and polarity modes.
-  assign ShiftEdgePulse = EdgePulse & ~LastBit;
-  assign SampleEdgePulse = EdgePulse & (NextState == TRANSMIT);
-  assign EndOfFramePulse = EdgePulse & LastBit;
-
-  // Delay ShiftEdge and SampleEdge by a half PCLK period
-  // Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
-  // Sweeeeeeeeeet...
-  assign InvertClock = ^SckMode;
-  always_ff @(negedge PCLK) begin
-    if (~PRESETn | TransmitStart) begin
-      ShiftEdge <= 0;
-      SampleEdge <= 0;
-      EndOfFrame <= 0;
-    end else begin 
-      ShiftEdge <= (InvertClock ^ SPICLK) & ShiftEdgePulse;
-      SampleEdge <= (InvertClock ^ ~SPICLK) & SampleEdgePulse;
-      EndOfFrame <= (InvertClock ^ SPICLK) & EndOfFramePulse;
-    end 
-  end 
-
-  always_ff @(posedge PCLK) begin
-    if (~PRESETn) begin
-      CurrState <= INACTIVE;
-    end else if (SCLKenable) begin
-      CurrState <= NextState;
-    end
-  end
-  
-  always_comb begin
-    case (CurrState)  
-      INACTIVE: if (TransmitRegLoaded) begin
-                  if (~HasCSSCK) NextState = TRANSMIT;
-                  else NextState = CSSCK;
-                end else begin
-                  NextState = INACTIVE;
-                end
-      CSSCK: if (EndOfCSSCK) NextState = TRANSMIT;
-             else NextState = CSSCK;
-      TRANSMIT: begin // TRANSMIT case --------------------------------
-        case(CSMode)
-          AUTOMODE: begin  
-            if (EndTransmission & ~HasSCKCS) NextState = INACTIVE;
-            else if (EndOfFrame & HasSCKCS) NextState = SCKCS;
-            else if (EndOfFrame & ~HasSCKCS) NextState = INTERCS;
-            else NextState = TRANSMIT;
-          end
-          HOLDMODE: begin  
-            if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
-            else if (EndTransmission) NextState = HOLD;
-            else NextState = TRANSMIT;
-          end
-          OFFMODE: begin
-            if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
-            else if (EndTransmission) NextState = HOLD;
-            else NextState = TRANSMIT;
-          end
-          default: NextState = TRANSMIT;
-        endcase
-      end
-      SCKCS: begin // SCKCS case --------------------------------------
-        if (EndOfSCKCS) begin
-          NextState = INTERCS;
-        end else begin
-          NextState = SCKCS;
-        end
-      end
-      HOLD: begin // HOLD mode case -----------------------------------
-        if (CSMode == AUTOMODE) begin
-          NextState = INACTIVE;
-        end else if (TransmitRegLoaded) begin // If FIFO is written to, start again.
-          NextState = TRANSMIT;
-        end else NextState = HOLD;
-      end
-      INTERCS: begin // INTERCS case ----------------------------------
-        if (EndOfINTERCS) begin
-          if (TransmitRegLoaded) begin
-            if (HasCSSCK) NextState = CSSCK;
-            else NextState = TRANSMIT;
-          end else NextState = INACTIVE;
-        end else begin
-          NextState = INTERCS;  
-        end
-      end
-      INTERXFR: begin // INTERXFR case --------------------------------
-        if (EndOfINTERXFR) begin
-          if (TransmitRegLoaded)  NextState = TRANSMIT;
-          else NextState = HOLD;
-        end else begin
-          NextState = INTERXFR;  
-        end
-      end
-      default: begin
-        NextState = INACTIVE;
-      end
-    endcase
-  end
-
-  assign Transmitting = CurrState == TRANSMIT;
-  assign DelayState = (CurrState == CSSCK | CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR);
-  assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;
-  
-endmodule
diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv
deleted file mode 100644
index 514e9df7b..000000000
--- a/src/uncore/spi_fifo.sv
+++ /dev/null
@@ -1,55 +0,0 @@
-module spi_fifo #(parameter M=3, N=8)(                 // 2^M entries of N bits each
-    input  logic         PCLK, wen, ren, PRESETn,
-    input  logic         winc, rinc,
-    input  logic [N-1:0] wdata,
-    input  logic [M-1:0] wwatermarklevel, rwatermarklevel,
-    output logic [N-1:0] rdata,
-    output logic         wfull, rempty,
-    output logic         wwatermark, rwatermark);
-
-    /* Pointer FIFO using design elements from "Simulation and Synthesis Techniques
-       for Asynchronous FIFO Design" by Clifford E. Cummings. Namely, M bit read and write pointers
-       are an extra bit larger than address size to determine full/empty conditions. 
-       Watermark comparisons use 2's complement subtraction between the M-1 bit pointers,
-       which are also used to address memory
-    */
-       
-    logic [N-1:0] mem[2**M];
-    logic [M:0] rptr, wptr;
-    logic [M:0] rptrnext, wptrnext;
-    logic [M-1:0] raddr;
-    logic [M-1:0] waddr;
-
-  logic [M-1:0] numVals;
-  
-  assign numVals = waddr - raddr;
- 
-    assign rdata = mem[raddr];
-    always_ff @(posedge PCLK)
-        if (winc & wen & ~wfull) mem[waddr] <= wdata;
-
-    // write and read are enabled 
-    always_ff @(posedge PCLK)
-        if (~PRESETn) begin 
-            rptr <= '0;
-            wptr <= '0;
-            wfull <= 1'b0;
-            rempty <= 1'b1;
-        end else begin 
-            if (wen) begin
-                wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
-                wptr  <= wptrnext;
-            end
-            if (ren) begin 
-                rptr <= rptrnext;
-                rempty <= (wptr == rptrnext);
-            end
-        end 
-    
-    assign raddr = rptr[M-1:0];
-    assign rptrnext = rptr + {{(M){1'b0}}, (rinc & ~rempty)};      
-    assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull;
-    assign waddr = wptr[M-1:0];
-    assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull;
-    assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)};
-endmodule
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
deleted file mode 100644
index f17fc67fe..000000000
--- a/src/uncore/uncore.sv
+++ /dev/null
@@ -1,205 +0,0 @@
-///////////////////////////////////////////
-// uncore.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: Ben Bracker 6 Mar 2021 to better fit AMBA 3 AHB-Lite spec
-//
-// Purpose: System-on-Chip components outside the core
-//          Memories, peripherals, external bus control
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module uncore import cvw::*;  #(parameter cvw_t P)(
-  // AHB Bus Interface
-  input  logic                 HCLK, HRESETn,
-  input  logic                 TIMECLK,
-  input  logic [P.PA_BITS-1:0] HADDR,
-  input  logic [P.AHBW-1:0]    HWDATA,
-  input  logic [P.XLEN/8-1:0]  HWSTRB,
-  input  logic                 HWRITE,
-  input  logic [2:0]           HSIZE,
-  input  logic [2:0]           HBURST,
-  input  logic [3:0]           HPROT,
-  input  logic [1:0]           HTRANS,
-  input  logic                 HMASTLOCK,
-  input  logic [P.AHBW-1:0]    HRDATAEXT,
-  input  logic                 HREADYEXT, HRESPEXT,
-  output logic [P.AHBW-1:0]    HRDATA,
-  output logic                 HREADY, HRESP,
-  output logic                 HSELEXT,
-  // peripheral pins          
-  output logic                 MTimerInt, MSwInt,         // Timer and software interrupts from CLINT
-  output logic                 MExtInt, SExtInt,          // External interrupts from PLIC
-  output logic [63:0]          MTIME_CLINT,               // MTIME, from CLINT
-  input  logic [31:0]          GPIOIN,                    // GPIO pin input value
-  output logic [31:0]          GPIOOUT, GPIOEN,           // GPIO pin output value and enable
-  input  logic                 UARTSin,                   // UART serial input
-  output logic                 UARTSout,                  // UART serial output
-  input  logic                 SPIIn,
-  output logic                 SPIOut,
-  output logic [3:0]           SPICS,
-  output logic                 SPICLK,
-  input  logic                 SDCIn,                                                 
-  output logic                 SDCCmd,
-  output logic [3:0]           SDCCS,
-  output logic                 SDCCLK
-);
-  
-  logic [P.XLEN-1:0]           HREADRam, HREADSDC;
-
-  logic [11:0]                 HSELRegions;
-  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART,HSELSDC, HSELSPI;
-  logic                        HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
-  logic                        HRESPRam,  HRESPSDC;
-  logic                        HREADYRam, HRESPSDCD;
-  logic [P.XLEN-1:0]           HREADBootRom; 
-  logic                        HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
-  logic                        HSELNoneD;
-  logic                        UARTIntr,GPIOIntr, SPIIntr;
-  logic                        SDCIntM;
-  
-  logic                        PCLK, PRESETn, PWRITE, PENABLE;
-  logic [5:0]                  PSEL;
-  logic [31:0]                 PADDR;
-  logic [P.XLEN-1:0]           PWDATA;
-  logic [P.XLEN/8-1:0]         PSTRB;
-  /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration
-  logic [5:0]                  PREADY;
-  logic [5:0][P.XLEN-1:0]      PRDATA;
-  /* verilator lint_on UNDRIVEN */
-  logic [P.XLEN-1:0]           HREADBRIDGE;
-  logic                        HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
-  /* SDC Interrupt (SPI Controller) */
-  logic                        SDCIntr;
-  
-
-  // Determine which region of physical memory (if any) is being accessed
-  // Use a trimmed down portion of the PMA checker - only the address decoders
-  // Set access types to all 1 as don't cares because the MMU has already done access checking
-  adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
-
-  // unswizzle HSEL signals
-  assign {HSELSPI, HSELSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1];
-
-  // AHB -> APB bridge
-  ahbapbbridge #(P, 6) ahbapbbridge (
-    .HCLK, .HRESETn, .HSEL({HSELSDC, HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
-    .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
-    .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
-  assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI | HSELSDC; // if any of the bridge signals are selected
-                
-  // on-chip RAM
-  if (P.UNCORE_RAM_SUPPORTED) begin : ram
-    ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
-      .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
-      .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
-  end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
-
- if (P.BOOTROM_SUPPORTED) begin : bootrom
-    rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
-    bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
-      .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
-  end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;
-
-  // memory-mapped I/O peripherals
-  if (P.CLINT_SUPPORTED == 1) begin : clint
-    clint_apb #(P) clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
-      .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
-  end else begin : clint
-    assign MTIME_CLINT = '0;
-    assign MTimerInt = 1'b0; assign MSwInt = 1'b0;
-  end
-
-  if (P.PLIC_SUPPORTED == 1) begin : plic
-    plic_apb #(P) plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
-      .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .SDCIntr, .SPIIntr, .MExtInt, .SExtInt);
-  end else begin : plic
-    assign MExtInt = 1'b0;
-    assign SExtInt = 1'b0;
-  end
-
-  if (P.GPIO_SUPPORTED == 1) begin : gpio
-    gpio_apb #(P) gpio(
-      .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
-      .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), 
-      .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr);
-  end else begin : gpio
-    assign GPIOOUT = '0; assign GPIOEN = '0; assign GPIOIntr = 1'b0;
-  end
-  
-  if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
-    uart_apb #(P) uart(
-      .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
-      .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), 
-      .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
-      .SOUT(UARTSout), .RTSb(), .DTRb(),                                // to E1A driver to RS232 interface
-      .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb());       // to CPU
-  end else begin : uart
-    assign UARTSout = 1'b0; assign UARTIntr = 1'b0; 
-  end
-  
-  if (P.SPI_SUPPORTED == 1) begin : spi
-    spi_apb  #(P) spi (
-      .PCLK, .PRESETn, .PSEL(PSEL[4]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
-      .PREADY(PREADY[4]), .PRDATA(PRDATA[4]), 
-      .SPIOut, .SPIIn, .SPICS, .SPICLK, .SPIIntr);
-  end else begin : spi
-    assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0; assign SPICLK = 1'b0;
-  end
-
-  if (P.SDC_SUPPORTED == 1) begin : sdc
-    spi_apb #(P) sdc(
-      .PCLK, .PRESETn, .PSEL(PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
-      .PREADY(PREADY[5]), .PRDATA(PRDATA[5]),
-      .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr));                                      
-  end else begin : sdc
-    assign SDCCmd = '0; assign SDCCS = 4'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
-  end
-  
-
-  // AHB Read Multiplexer
-  assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
-                  ({P.XLEN{HSELEXTD}} & HRDATAEXT) |
-                  ({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) |
-                  ({P.XLEN{HSELBootRomD}} & HREADBootRom);
-
-  assign HRESP = HSELRamD & HRESPRam |
-                 HSELEXTD & HRESPEXT |
-                 HSELBRIDGE & HRESPBRIDGE |
-                 HSELBootRomD & HRESPBootRom;
-  
-  assign HREADY = HSELRamD & HREADYRam |
-		          HSELEXTD & HREADYEXT |		  
-                  HSELBRIDGED & HREADYBRIDGE |
-                  HSELBootRomD & HREADYBootRom |
-                  HSELNoneD; // don't lock up the bus if no region is being accessed
-
-  // Address Decoder Delay (figure 4-2 in spec)
-  // The select for HREADY needs to be based on the address phase address.  If the device 
-  // takes more than 1 cycle to repsond it needs to hold on to the old select until the
-  // device is ready.  Hense this register must be selectively enabled by HREADY.
-  // However on reset None must be seleted.
-  flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, 
-    {HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
-      HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
-  flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
-endmodule
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
deleted file mode 100644
index b5a80a24b..000000000
--- a/src/wally/wallypipelinedcore.sv
+++ /dev/null
@@ -1,360 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedcore.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Pipelined RISC-V Processor
-// 
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [P.AHBW-1:0]     HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [P.PA_BITS-1:0]  HADDR,
-   output logic [P.AHBW-1:0]     HWDATA,
-   output logic [P.XLEN/8-1:0]   HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK,
-   input  logic                  ExternalStall
-);
-
-  logic                          StallF, StallD, StallE, StallM, StallW;
-  logic                          FlushD, FlushE, FlushM, FlushW;
-  logic                          TrapM, RetM;
-
-  //  signals that must connect through DP
-  logic                          IntDivE, W64E;
-  logic                          CSRReadM, CSRWriteM, PrivilegedM;
-  logic [1:0]                    AtomicM;
-  logic [P.XLEN-1:0]             ForwardedSrcAE, ForwardedSrcBE;
-  logic [P.XLEN-1:0]             SrcAM;
-  logic [2:0]                    Funct3E;
-  logic [31:0]                   InstrD;
-  logic [31:0]                   InstrM, InstrOrigM;
-  logic [P.XLEN-1:0]             PCSpillF, PCE, PCLinkE;
-  logic [P.XLEN-1:0]             PCM;
-  logic [P.XLEN-1:0]             CSRReadValW, MDUResultW;
-  logic [P.XLEN-1:0]             EPCM, TrapVectorM;
-  logic [1:0]                    MemRWE;
-  logic [1:0]                    MemRWM;
-  logic                          InstrValidD, InstrValidE, InstrValidM;
-  logic                          InstrMisalignedFaultM;
-  logic                          IllegalBaseInstrD, IllegalFPUInstrD, IllegalIEUFPUInstrD;
-  logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
-  logic                          LoadMisalignedFaultM, LoadAccessFaultM;
-  logic                          StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
-  logic                          InvalidateICacheM, FlushDCacheM;
-  logic                          PCSrcE;
-  logic                          CSRWriteFenceM;
-  logic                          DivBusyE;
-  logic                          StructuralStallD;
-  logic                          LoadStallD;
-  logic                          StoreStallD;
-  logic                          SquashSCW;
-  logic                          MDUActiveE;                      // Mul/Div instruction being executed
-  logic                          ENVCFG_ADUE;                     // HPTW A/D Update enable
-  logic                          ENVCFG_PBMTE;                    // Page-based memory type enable
-  logic [3:0]                    ENVCFG_CBE;                      // Cache Block operation enables
-  logic [3:0]                    CMOpM;                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  logic                          IFUPrefetchE, LSUPrefetchM;      // instruction / data prefetch hints
-
-  // floating point unit signals
-  logic [2:0]                    FRM_REGW;
-  logic [4:0]                    RdE, RdM, RdW;
-  logic                          FPUStallD;
-  logic                          FWriteIntE;
-  logic [P.FLEN-1:0]             FWriteDataM;
-  logic [P.XLEN-1:0]             FIntResM;  
-  logic [P.XLEN-1:0]             FCvtIntResW; 
-  logic                          FCvtIntW; 
-  logic                          FDivBusyE;
-  logic                          FRegWriteM;
-  logic                          FpLoadStoreM;
-  logic [4:0]                    SetFflagsM;
-  logic [P.XLEN-1:0]             FIntDivResultW;
-
-  // memory management unit signals
-  logic                          ITLBWriteF;
-  logic                          ITLBMissOrUpdateAF;
-  logic [P.XLEN-1:0]             SATP_REGW;
-  logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
-  logic [1:0]                    STATUS_MPP, STATUS_FS;
-  logic [1:0]                    PrivilegeModeW;
-  logic [P.XLEN-1:0]             PTE;
-  logic [1:0]                    PageType;
-  logic                          sfencevmaM;
-  logic                          SelHPTW;
-
-  // PMA checker signals
-  /* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit
-  var logic [P.PA_BITS-3:0]      PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
-  var logic [7:0]                PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
-  /* verilator lint_on UNDRIVEN */
-
-  // IMem stalls
-  logic                          IFUStallF;
-  logic                          LSUStallM;
-
-  // cpu lsu interface
-  logic [2:0]                    Funct3M;
-  logic [P.XLEN-1:0]             IEUAdrE;
-  logic [P.XLEN-1:0]             WriteDataM;
-  logic [P.XLEN-1:0]             IEUAdrM;  
-  logic [P.LLEN-1:0]             ReadDataW;  
-  logic                          CommittedM;
-
-  // AHB ifu interface
-  logic [P.PA_BITS-1:0]          IFUHADDR;
-  logic [2:0]                    IFUHBURST;
-  logic [1:0]                    IFUHTRANS;
-  logic [2:0]                    IFUHSIZE;
-  logic                          IFUHWRITE;
-  logic                          IFUHREADY;
-  
-  // AHB LSU interface
-  logic [P.PA_BITS-1:0]          LSUHADDR;
-  logic [P.XLEN-1:0]             LSUHWDATA;
-  logic [P.XLEN/8-1:0]           LSUHWSTRB;
-  logic                          LSUHWRITE;
-  logic                          LSUHREADY;
-  
-  logic                          BPWrongE, BPWrongM;
-  logic                          BPDirWrongM;
-  logic                          BTAWrongM;
-  logic                          RASPredPCWrongM;
-  logic                          IClassWrongM;
-  logic [3:0]                    IClassM;
-  logic                          InstrAccessFaultF, HPTWInstrAccessFaultF, HPTWInstrPageFaultF;
-  logic [2:0]                    LSUHSIZE;
-  logic [2:0]                    LSUHBURST;
-  logic [1:0]                    LSUHTRANS;
-  
-  logic                          DCacheMiss;
-  logic                          DCacheAccess;
-  logic                          ICacheMiss;
-  logic                          ICacheAccess;
-  logic                          BigEndianM;
-  logic                          FCvtIntE;
-  logic                          CommittedF;
-  logic                          BranchD, BranchE, JumpD, JumpE;
-  logic                          DCacheStallM, ICacheStallF;
-  logic                          wfiM, IntPendingM;
-
-  // instruction fetch unit: PC, branch prediction, instruction cache
-  ifu #(P) ifu(.clk, .reset,
-    .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-    .InstrValidE, .InstrValidD,
-    .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
-    // Fetch
-    .HRDATA, .PCSpillF, .IFUHADDR, 
-    .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
-    .ICacheAccess, .ICacheMiss,
-    // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE,  .BPWrongM, 
-    // Mem
-    .CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM,
-    .BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
-    // Faults out
-    .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
-    // mmu management
-    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissOrUpdateAF,
-    // pmp/pma (inside mmu) signals. 
-    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF); 
-    
-  // integer execution unit: integer register file, datapath and controller
-  ieu #(P) ieu(.clk, .reset,
-     // Decode Stage interface
-     .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
-     // Execute Stage interface
-     .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
-     // Memory stage interface
-     .SquashSCW,  // from LSU
-     .MemRWE,     // read/write control goes to LSU
-     .MemRWM,     // read/write control goes to LSU
-     .AtomicM,    // atomic control goes to LSU
-     .WriteDataM, // Write data to LSU
-     .Funct3M,    // size and signedness to LSU
-     .SrcAM,      // to privilege and fpu
-     .RdE, .RdM, .FIntResM, .FlushDCacheM,
-     .BranchD, .BranchE, .JumpD, .JumpE,
-     // Writeback stage
-     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[P.XLEN-1:0]),
-     .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
-     // hazards
-     .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-     .StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
-     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM); 
-
-  lsu #(P) lsu(
-    .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
-    // CPU interface
-    .MemRWE, .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
-    .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
-    .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
-    .ReadDataW, .FlushDCacheM, .CMOpM, .LSUPrefetchM,
-    // connected to ahb (all stay the same)
-    .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
-    .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
-    // connect to csr or privilege and stay the same.
-    .PrivilegeModeW, .BigEndianM, // connects to csr
-    .PMPCFG_ARRAY_REGW,           // connects to csr
-    .PMPADDR_ARRAY_REGW,          // connects to csr
-    // hptw keep i/o
-    .SATP_REGW,                   // from csr
-    .STATUS_MXR,                  // from csr
-    .STATUS_SUM,                  // from csr
-    .STATUS_MPRV,                 // from csr            
-    .STATUS_MPP,                  // from csr     
-    .ENVCFG_PBMTE,                // from csr
-    .ENVCFG_ADUE,                 // from csr
-    .sfencevmaM,                  // connects to privilege
-    .DCacheStallM,                // connects to privilege
-    .LoadPageFaultM,              // connects to privilege
-    .StoreAmoPageFaultM,          // connects to privilege
-    .LoadMisalignedFaultM,        // connects to privilege
-    .LoadAccessFaultM,            // connects to privilege
-    .HPTWInstrAccessFaultF,       // connects to privilege
-    .HPTWInstrPageFaultF,         // connects to privilege
-    .StoreAmoMisalignedFaultM,    // connects to privilege
-    .StoreAmoAccessFaultM,        // connects to privilege
-    .PCSpillF, .ITLBMissOrUpdateAF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
-    .LSUStallM);                    
-
-  if(P.BUS_SUPPORTED) begin : ebu
-    ebu #(P) ebu(// IFU connections
-      .clk, .reset,
-      // IFU interface
-      .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
-      // LSU interface
-      .LSUHADDR, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST,
-      .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
-      // BUS interface
-      .HREADY, .HRESP, .HCLK, .HRESETn,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
-      .HPROT, .HTRANS, .HMASTLOCK);
-  end else begin
-    assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
-            HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
-  end
-
-  // global stall and flush control  
-  hazard hzu(
-    .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
-    .StructuralStallD,
-    .LSUStallM, .IFUStallF,
-    .FPUStallD, .ExternalStall,
-    .DivBusyE, .FDivBusyE,
-    .wfiM, .IntPendingM,
-    // Stall & flush outputs
-    .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushD, .FlushE, .FlushM, .FlushW);    
-
-  // privileged unit
-  if (P.ZICSR_SUPPORTED) begin:priv
-    privileged #(P) priv(
-      .clk, .reset,
-      .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
-      .CSRReadM, .CSRWriteM, .SrcAM, .PCM, 
-      .InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
-      .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
-      .InstrValidM, .CommittedM, .CommittedF,
-      .FRegWriteM, .LoadStallD, .StoreStallD,
-      .BPDirWrongM, .BTAWrongM, .BPWrongM,
-      .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
-      .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
-      .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
-      .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, 
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
-      .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-      .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
-      .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
-      .PrivilegeModeW, .SATP_REGW,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
-      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
-  end else begin
-    assign {CSRReadValW, PrivilegeModeW, 
-            SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
-            // PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW, 
-            ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE, 
-            EPCM, TrapVectorM, RetM, TrapM,
-            sfencevmaM, BigEndianM, wfiM, IntPendingM} = '0;
-  end
-
-  // multiply/divide unit
-  if (P.ZMMUL_SUPPORTED) begin:mdu
-    mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
-      .ForwardedSrcAE, .ForwardedSrcBE, 
-      .Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
-      .MDUResultW, .DivBusyE); 
-  end else begin // no M instructions supported
-    assign MDUResultW = '0; 
-    assign DivBusyE   = 1'b0;
-  end
-
-  // floating point unit
-  if (P.F_SUPPORTED) begin:fpu
-    fpu #(P) fpu(
-      .clk, .reset,
-      .FRM_REGW,                           // Rounding mode from CSR
-      .InstrD,                             // instruction from IFU
-      .ReadDataW(ReadDataW[P.FLEN-1:0]),   // Read data from memory
-      .ForwardedSrcAE,                     // Integer input being processed (from IEU)
-      .StallE, .StallM, .StallW,           // stall signals from HZU
-      .FlushE, .FlushM, .FlushW,           // flush signals from HZU
-      .RdE, .RdM, .RdW,                    // which FP register to write to (from IEU)
-      .STATUS_FS,                          // is floating-point enabled?
-      .FRegWriteM,                         // FP register write enable
-      .FpLoadStoreM,
-      .ForwardedSrcBE,                     // Integer input for intdiv
-      .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
-      .FPUStallD,                          // Stall the decode stage
-      .FWriteIntE, .FCvtIntE,              // integer register write enable, conversion operation
-      .FWriteDataM,                        // Data to be written to memory
-      .FIntResM,                           // data to be written to integer register
-      .FCvtIntResW,                        // fp -> int conversion result to be stored in int register
-      .FCvtIntW,                           // fpu result selection
-      .FDivBusyE,                          // Is the divide/sqrt unit busy (stall execute stage)
-      .IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
-      .SetFflagsM,                         // FPU flags (to privileged unit)
-      .FIntDivResultW); 
-  end else begin                           // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM,
-            IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
-            FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0;
-  end
-  
-endmodule
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
deleted file mode 100644
index 2e534ba59..000000000
--- a/src/wally/wallypipelinedsoc.sv
+++ /dev/null
@@ -1,99 +0,0 @@
-///////////////////////////////////////////
-// wally-pipelinedsoc.sv
-//
-// Written: David_Harris@hmc.edu 6 November 2020
-// Modified: 
-//
-// Purpose: System on chip including pipelined processor and uncore memories/peripherals
-//
-// Documentation: RISC-V System on Chip Design
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
-  input  logic                clk, 
-  input  logic                reset_ext,        // external asynchronous reset pin
-  output logic                reset,            // reset synchronized to clk to prevent races on release
-  // AHB Interface
-  input  logic [P.AHBW-1:0]   HRDATAEXT,
-  input  logic                HREADYEXT, HRESPEXT,
-  output logic                HSELEXT,
-  // fpga debug signals
-  input  logic                ExternalStall,
-  // outputs to external memory, shared with uncore memory
-  output logic                HCLK, HRESETn,
-  output logic [P.PA_BITS-1:0]  HADDR,
-  output logic [P.AHBW-1:0]     HWDATA,
-  output logic [P.XLEN/8-1:0]   HWSTRB,
-  output logic                HWRITE,
-  output logic [2:0]          HSIZE,
-  output logic [2:0]          HBURST,
-  output logic [3:0]          HPROT,
-  output logic [1:0]          HTRANS,
-  output logic                HMASTLOCK,
-  output logic                HREADY,
-  // I/O Interface
-  input  logic                TIMECLK,          // optional for CLINT MTIME counter
-  input  logic [31:0]         GPIOIN,           // inputs from GPIO
-  output logic [31:0]         GPIOOUT,          // output values for GPIO
-  output logic [31:0]         GPIOEN,           // output enables for GPIO
-  input  logic                UARTSin,          // UART serial data input
-  output logic                UARTSout,         // UART serial data output
-  input  logic                SPIIn,            // SPI pins in
-  output logic                SPIOut,           // SPI pins out
-  output logic [3:0]          SPICS,            // SPI chip select pins
-  output logic                SPICLK,           // SPI clock
-  input  logic                SDCIn,            // SDC DATA[0]     to     SPI DI
-  output logic                SDCCmd,           // SDC CMD         from   SPI DO
-  output logic [3:0]          SDCCS,            // SDC Card Detect from   SPI CS
-  output logic                SDCCLK            // SDC Clock       from   SPI Clock
-);
-
-  // Uncore signals
-  logic [P.AHBW-1:0]          HRDATA;           // from AHB mux in uncore
-  logic                       HRESP;            // response from AHB
-  logic                       MTimerInt, MSwInt;// timer and software interrupts from CLINT
-  logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
-  logic                       MExtInt,SExtInt;  // from PLIC
-
-  // synchronize reset to SOC clock domain
-  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
-   
-  // instantiate processor and internal memories
-  wallypipelinedcore #(P) core(.clk, .reset,
-    .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
-    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .ExternalStall
-   );
-
-  // instantiate uncore if a bus interface exists
-  if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
-    uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
-      .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
-      .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, 
-      .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
-  end else begin
-    assign {HRDATA, HREADY, HRESP, HSELEXT, MTimerInt, MSwInt, MExtInt, SExtInt,
-            MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS, SPICLK, SDCCmd, SDCCS, SDCCLK} = '0; 
-  end
-
-  
-endmodule
diff --git a/studies/comparator.sv b/studies/comparator.sv
index 1f9877077..771236f65 100644
--- a/studies/comparator.sv
+++ b/studies/comparator.sv
@@ -7,10 +7,9 @@
 //
 // Purpose: Branch comparison
 // 
-// Documentation: RISC-V System on Chip Design
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
@@ -28,7 +27,7 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "config.vh"
+`include "wally-config.vh"
 
 // This comparator is best
 module comparator_dc_flip #(parameter WIDTH=64) (
diff --git a/studies/ppa/ppa.sv b/studies/ppa/ppa.sv
index 6c9311e98..5363bb9b6 100644
--- a/studies/ppa/ppa.sv
+++ b/studies/ppa/ppa.sv
@@ -693,6 +693,8 @@ module ppa_mux8_128 #(parameter WIDTH = 128) (
   assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
 endmodule
 
+// *** some way to express data-critical inputs
+
 module ppa_flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 0211ce51e..ddb62533e 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -18,20 +18,8 @@ if {$tech == "sky130"} {
     set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
     lappend search_path $s9lib
 } elseif {$tech == "tsmc28"} {
-    set s10lib $SYN_pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
-} elseif {$tech == "tsmc28psyn"} {
-    set s10lib $SYN_pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
-    lappend search_path $s10lib
-    set TLUPLUS true
-    set mw_logic1_net VDD
-    set mw_logic0_net VSS
-    set CAPTABLE $SYN_TLU/1p8m/
-    set MW_REFERENCE_LIBRARY $SYN_MW
-    set MW_TECH_FILE tcbn28hpcplusbwp30p140
-    set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus
-    set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
-    set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
 }
 
 # Synthetic libraries
@@ -47,12 +35,11 @@ if {$tech == "sky130"} {
     lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
 } elseif {$tech == "tsmc28"} {
     lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
-} elseif {$tech == "tsmc28psyn"} {
-    set mw_reference_library [list ]    
-    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140    
 }
 
+# Set Link Library
+set link_library "$target_library $synthetic_library"
+
 # Set up DesignWare cache read and write directories to speed up compile.
 set cache_write  ~
 set cache_read   $cache_write
@@ -61,23 +48,10 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {($tech == "tsmc28psyn")} {
-    lappend target_library $SYN_memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-    lappend target_library $SYN_memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
-    lappend target_library $SYN_memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
-    lappend target_library $SYN_memory/tsdn28hpcpa64x32m4mw_130a/NLDM/tsdn28hpcpa64x32m4mw_tt0p9v25c.db
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x44m4sw
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/ts1n28hpcpsvtb64x128m4sw
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tsdn28hpcpa1024x68m4mw
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tsdn28hpcpa64x32m4mw
-}
-
-# Set Link Library
-set link_library "$target_library $synthetic_library"
 
 # Set up User Information
-set company "Detect-o-rama"
-set user    "Ben Bitdiddle"
+set company "Oklahoma State University"
+set user    "James E. Stine"
 
 # Alias
 alias ra report_area
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 513d54dba..98b719428 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -1,17 +1,17 @@
 #  
 # Makefile for synthesis
 # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
-# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023
+# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 7/8/2022
 NAME := synth
+
 # defaults
 export DESIGN ?= wallypipelinedcore
-export FREQ ?= 10000
-export CONFIG ?= rv64gc
-export MOD ?= orig
+export FREQ ?= 3000
+export CONFIG ?= rv32e
 # title to add a note in the synth's directory name
 TITLE = 
 # tsmc28, sky130, and sky90 presently supported
-export TECH ?= sky130
+export TECH ?= sky90
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
 # Avoid when doing sweeps of many optimization points in parallel
 export MAXCORES ?= 1
@@ -19,16 +19,22 @@ export MAXCORES ?= 1
 # The output netlist is hard to interpret, but significantly better PPA
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
-export USESRAM ?= 0
-export WIDTH ?= 32
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
+export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
-OLDCONFIGDIR ?= ${WALLY}/config
-export CONFIGDIR ?= $(OUTPUTDIR)/config
+CONFIGDIR ?= ${WALLY}/pipelined/config
+CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
+CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
+# FREQS = 25 50 100 150 200 250 300 350 400
+# k = 3 6 
+
+print:
+	@echo $(FREQS)
+	@echo $(CONFIGFILESTRIM)
+
 
 default:
 	@echo "  Basic synthesis procedure for Wally:"
@@ -36,51 +42,82 @@ default:
 	@echo "Use wallySynth.py to run a concurrent sweep "
 
 
-DIRS32 = rv32e rv32gc rv32imc rv32i
-DIRS64 = rv64i rv64gc
+DIRS32 = rv32e rv32gc rv32ic 
+DIRS64 = rv64ic rv64gc
 DIRS = $(DIRS32) $(DIRS64)
 
-configs: $(CONFIG)
-$(CONFIG):
-	@echo $(CONFIG)
-	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
-ifeq ($(MOD), orig)
-	cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true
-else
-	cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)_$(MOD)/config.vh $(CONFIGDIR) | true
-endif
+# bpred:
+# 	@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+# 	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+# 	@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
+# 	@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
+copy: 
+	# remove old config files
+	rm -rf $(CONFIGDIR)/*_*
 
-ifeq ($(SAIFPOWER), 1)
-	cp -f ../sim/power.saif .
-endif
+	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
+	@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
+	@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
+	@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
+	@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
 
-mkdirecs:
+	@$(foreach dir, $(DIRS32), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
+	@$(foreach dir, $(DIRS64), sed -i "s/RAM_RANGE.*/RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
+
+configs: $(DIRS)
+$(DIRS):
+	
+	# turn off FPU 
+	rm -rf $(CONFIGDIR)/$@_FPUoff
+	cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
+	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
+	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
+
+	# PMP 16 
+	rm -rf $(CONFIGDIR)/$@_PMP16
+	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
+	
+	# PMP 0
+	rm -rf $(CONFIGDIR)/$@_PMP0
+	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
+	
+	# no muldiv
+	rm -rf $(CONFIGDIR)/$@_noMulDiv
+	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
+	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
+
+	# no priv
+	rm -rf $(CONFIGDIR)/$@_noPriv
+	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
+
+freqs: 
+	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
+
+synth:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
 	@mkdir -p $(OUTPUTDIR)/hdl
-	@mkdir -p $(OUTPUTDIR)/config
 	@mkdir -p $(OUTPUTDIR)/reports
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
-
-synth: mkdirecs configs rundc # clean
-
-rundc:
-ifeq ($(TECH), tsmc28psyn)
-	dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
-else
-	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out	
+ifeq ($(SAIFPOWER), 1)
+	cp -f ../pipelined/regression/power.saif .
 endif
-
-
-clean:
-	rm -rf $(OUTPUTDIR)/hdl
+	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
+#	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
+
+clean:
 	rm -f default.svf
 	rm -f command.log
 	rm -f filenames*.log
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
-	
+
+fresh: clean copy configs
+	@echo "synth directory cleaned and fresh config files written"
diff --git a/synthDC/README.md b/synthDC/README.md
index f0177d369..91804b29b 100644
--- a/synthDC/README.md
+++ b/synthDC/README.md
@@ -1,61 +1,33 @@
-# Synthesis for RISC-V Microprocessor System-on-Chip Design
+Synthesis for RISC-V Microprocessor System-on-Chip Design
 
 This subdirectory contains synthesis scripts for use with Synopsys
 (snps) Design Compiler (DC).  Synthesis commands are found in
-`scripts/synth.tcl`.
+scripts/synth.tcl.
 
-## Example Usage
-```bash
-make synth DESIGN=wallypipelinedcore FREQ=500 CONFIG=rv32e
-```
+Example Usage
+make synth DESIGN=wallypipelinedcore FREQ=500
 
-## Environment Variables
+environment variables
 
-- `DESIGN`
-  - Design provides the name of the output log.  Default is synth.
-- `FREQ`
-  - Frequency in MHz.  Default is 500
-- `CONFIG`
-  - The Wally configuration file.  The default is rv32e.
-  - Examples: rv32e, rv64gc, rv32gc
-- `TECH`
-  - The target standard cell library.  The default is sky130.
-	- Options:
-    - sky90: skywater 90nm TT 25C
-    - sky130: skywater 130nm TT 25C
-- `SAIFPOWER`
-  - Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif.  The default is 0.
-  - Options:
-    - 0: switching factor power analysis
-    - 1: RTL simulation driven power analysis.
+DESIGN
+        Design provides the name of the output log.  Default is synth.
 
-## Extra Tool (PPA)
+FREQ
+        Frequency in MHz.  Default is 500
 
-To run ppa analysis that hones into target frequency, you can type:
-`python3 ppa/ppaSynth.py` from the synthDC directory.  This runs a sweep
-across all modules listed at the bottom of the `ppaSynth.py` file.
+CONFIG
+        The Wally configuration file.  The default is rv32e.
+        Examples: rv32e, rv64gc, rv32gc
 
-Two options for running the sweep.  The first run runs all modules for
-all techs around a given frequency (i.e., freqs).  The second option
-will run all designs for the specific module based on bestSynths.csv
-values.   Since the second option is 2nd, it has priority.  If the
-second set of values is commented out, it will run all widths.
+TECH
+        The target standard cell library.  The default is sky130.
+        sky90: skywater 90nm TT 25C
+        sky130: skywater 130nm TT 25C
 
-**WARNING:** The first option may runs lots of runs that could expend all the licenses available for a license.  Therefore, care must be taken to be sure that enough licenses are available for this first option.
+SAIFPOWER
+        Controls if power analysis is driven by switching factor or
+	RTL modelsim simulation. When enabled requires a saif file
+	named power.saif.  The default is 0.
+        0: switching factor power analysis
+        1: RTL simulation driven power analysis.
 
-### Run specific syntheses
-```python
-widths = [8, 16, 32, 64, 128]
-modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8']
-techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn']
-freqs = [5000]
-synthsToRun = allCombos(widths, modules, techs, freqs)
-```
-
-### Run a sweep based on best delay found in existing syntheses
-```python
-module = 'adder'
-width = 32
-tech = 'tsmc28psyn'
-synthsToRun = freqSweep(module, width, tech)
-```
diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl
deleted file mode 100755
index cd795d3ff..000000000
--- a/synthDC/extractArea.pl
+++ /dev/null
@@ -1,120 +0,0 @@
-#!/usr/bin/env -S perl -w
-
-###########################################
-## extractArea.pl
-##
-## Written: David_Harris@hmc.edu 
-## Created: 19 Feb 2023
-## Modified: 
-##
-## Purpose: Pull area statistics from run directory
-##
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-##
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https:##solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-use strict;
-use warnings;
-import os;
-
-my %configResults;
-my $dir = "runs";
-my $macro = "Macro/Black Box area:";
-my $seq = "Noncombinational area:";
-my $buf = "Buf/Inv area:";
-my $comb = "Combinational area:";
-my $macroC = "Number of macros/black boxes:";
-my $seqC = "Number of sequential cells:";
-my $bufC = "Number of buf/inv:";
-my $combC = "Number of combinational cells:";
-my @keywords = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", $macro, $seq, $buf, $comb, $macroC, $seqC, $bufC, $combC);
-my @keywordsp = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", 
-                 "RAMs", "Flip-flops", "Inv/Buf", "Logic", "RAMs Cnt", "Flip-flops Cnt", "Inv/Buf Cnt", "Logic Cnt", "Total Cnt");
-my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc");
-
-opendir(DIR, $dir) or die "Could not open $dir";
-
-while (my $filename = readdir(DIR)) {
-    if ($filename =~ /orig_tsmc28psyn/) { 
-#    if ($filename =~ /orig_sky90/) {
-        &processRun("$dir/$filename");
-    }
-}
-closedir(DIR);
-
-# print table of results 
-printf("%20s\t", "");
-foreach my $config (@configs) {
-    printf("%s\t", $config);
-}
-print ("\n");
-foreach my $kw (@keywordsp) {
-    my $kws = substr($kw, 0, 3);
-    printf("%20s\t", $kw);
-    foreach my $config (@configs) {
-        my $r = $configResults{$config};
-        if (exists ${$r}{$kw}) {
-            my $area = ${$r}{$kw};
-            while ($area =~ s/(\d+)(\d\d\d)/$1\,$2/){};
-            #print "${$r}{$kw}\t";
-            print "$area\t";
-        } else {
-            print("\t");
-        }        
-    }
-    print("\n");
-}
-
-sub processRun {
-    my $fname = shift;
-    my $ffname = "$fname/reports/area.rep";
-    open(FILE, "$ffname") or die ("Could not read $ffname");
-
-    # Extract configuration from fname;
-    $fname =~ /_([^_]*)_orig/; 
-    my $config = $1;
-    #print("Reading $config from $ffname\n");
-
-    # Search for results
-    my %results;
-    while (my $line = <FILE>) {
-        foreach my $kw (@keywords) {
-           # print "$kw $line\n";
-            if ($line =~ /^${kw}\s+(\S*)/) {
-                $results{$kw} = int($1);
-            } elsif ($line =~ /^${kw}__\S*\s+(\S*)/) {
-                $results{$kw} = int($1);
-            }
-         }
-    }
-    foreach my $kw (@keywords) {
-        #print "$kw\t$results{$kw}\n";
-    }
-    $results{"Logic"} = $results{$comb} - $results{$buf};
-    $results{"Inv/Buf"} = $results{$buf};
-    $results{"Flip-flops"} = $results{$seq};
-    $results{"RAMs"} = $results{$macro};
-    $results{"Logic Cnt"} = $results{$combC} - $results{$bufC};
-    $results{"Inv/Buf Cnt"} = $results{$bufC};
-    $results{"Flip-flops Cnt"} = $results{$seqC};
-    $results{"RAMs Cnt"} = $results{$macroC};
-    $results{"Total Cnt"} = $results{$macroC} + $results{$seqC} +  $results{$combC};
-    close(FILE);
-    $configResults{$config} = \%results;
-}
\ No newline at end of file
diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index ae75c26e2..978365b16 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -1,19 +1,17 @@
-#!/usr/bin/env python3
+#!/usr/bin/python3
 # Madeleine Masser-Frye (mmmasserfrye@hmc.edu) 06/2022
-import argparse
-import csv
-import os
-import re
-import subprocess
 from collections import namedtuple
-
-import matplotlib.lines as lines
-import matplotlib.pyplot as plt
-import numpy as np
-from adjustText import adjust_text
-from matplotlib import ticker
+import re
+import csv
+import subprocess
 from matplotlib.cbook import flatten
+import matplotlib.pyplot as plt
+import matplotlib.lines as lines
+import numpy as np
 from ppa.ppaAnalyze import noOutliers
+from matplotlib import ticker
+import argparse
+import os
 
 
 def synthsintocsv():
@@ -26,50 +24,45 @@ def synthsintocsv():
     allSynths = output.decode("utf-8").split('\n')[:-1]
 
     specReg = re.compile('[a-zA-Z0-9]+')
-    metricReg = re.compile(r'-?\d+\.\d+[e]?[-+]?\d*')
+    metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
 
-    with open("Summary.csv", "w") as file:
-        writer = csv.writer(file)
-        writer.writerow(['Width', 'Config', 'Mod', 'Tech', 'Target Freq', 'Delay', 'Area'])
-
-        for oneSynth in allSynths:
-            descrip = specReg.findall(oneSynth)
-    #        print("From " + oneSynth + " Find ")
-    #        for d in descrip:
-    #            print(d)
-            base = 4 if descrip[3] == "sram" else 3
-            width = descrip[base][:4]
-            config = descrip[base][4:]
-            if descrip[base+1][-2:] == 'nm':
-                mod = ''
-            else:
-                mod = descrip[base+1]
-                descrip = descrip[1:]
-            tech = descrip[base+1][:-2]
-            freq = descrip[base+2]
-    #        print(width, config, mod, tech, freq)
-            metrics = []
-            for phrase in ['Path Slack', 'Design Area']:
-                bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
-                bashCommand = bashCommand.format(phrase)
-    #            print(bashCommand)
-                try: 
-                    output = subprocess.check_output(['bash','-c', bashCommand])
-                    nums = metricReg.findall(str(output))
-                    nums = [float(m) for m in nums]
-                    metrics += nums
-                except: 
-                    print(width + config + tech + '_' + freq + " doesn't have reports")
-            if metrics == []:
-                pass
-            else:
-                delay = 1000/int(freq) - metrics[0]
-                area = metrics[1]
-                writer.writerow([width, config, mod, tech, freq, delay, area])
+    file = open("Summary.csv", "w")
+    writer = csv.writer(file)
+    writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area'])
 
+    for oneSynth in allSynths:
+        descrip = specReg.findall(oneSynth)
+        width = descrip[2][:4]
+        config = descrip[2][4:]
+        if descrip[3][-2:] == 'nm':
+            special = ''
+        else:
+            special = descrip[3]
+            descrip = descrip[1:]
+        tech = descrip[3][:-2]
+        freq = descrip[4]
+        metrics = []
+        for phrase in ['Path Slack', 'Design Area']:
+            bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
+            bashCommand = bashCommand.format(phrase)
+            try: 
+                output = subprocess.check_output(['bash','-c', bashCommand])
+                nums = metricReg.findall(str(output))
+                nums = [float(m) for m in nums]
+                metrics += nums
+            except: 
+                print(width + config + tech + '_' + freq + " doesn't have reports")
+        if metrics == []:
+            pass
+        else:
+            delay = 1000/int(freq) - metrics[0]
+            area = metrics[1]
+            writer.writerow([width, config, special, tech, freq, delay, area])
+    file.close()
 
+	
 def synthsfromcsv(filename):
-    Synth = namedtuple("Synth", "width config mod tech freq delay area")
+    Synth = namedtuple("Synth", "width config special tech freq delay area")
     with open(filename, newline='') as csvfile:
         csvreader = csv.reader(csvfile)
         global allSynths
@@ -88,17 +81,25 @@ def freqPlot(tech, width, config):
     ''' plots delay, area for syntheses with specified tech, module, width
     '''
 
+    current_directory = os.getcwd()
+    final_directory = os.path.join(current_directory, 'plots/wally')
+    if not os.path.exists(final_directory):
+        os.makedirs(final_directory)
+
     freqsL, delaysL, areasL = ([[], []] for i in range(3))
     for oneSynth in allSynths:
-        if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & (oneSynth.mod == 'orig'):
-            ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period
+        if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special):
+            ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
             freqsL[ind] += [oneSynth.freq]
             delaysL[ind] += [oneSynth.delay]
             areasL[ind] += [oneSynth.area]
     
     fig, (ax1, ax2) = plt.subplots(2, 1, sharex=True)
     allFreqs = list(flatten(freqsL))
-    median = np.median(allFreqs) if allFreqs != [] else 0
+    if allFreqs != []:
+        median = np.median(allFreqs)
+    else:
+        median = 0
 
     for ind in [0,1]:
         areas = areasL[ind]
@@ -106,7 +107,7 @@ def freqPlot(tech, width, config):
         freqs = freqsL[ind]
         freqs, delays, areas = noOutliers(median, freqs, delays, areas)
 
-        c = 'blue' if ind else 'gray'
+        c = 'blue' if ind else 'green'
         targs = [1000/f for f in freqs]
 
         ax1.scatter(targs, delays, color=c)
@@ -116,7 +117,7 @@ def freqPlot(tech, width, config):
     delays = list(flatten(delaysL))
     areas = list(flatten(areasL))
 
-    legend_elements = [lines.Line2D([0], [0], color='gray', ls='', marker='o', label='timing achieved'),
+    legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'),
                        lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')]
 
     ax1.legend(handles=legend_elements)
@@ -129,7 +130,7 @@ def freqPlot(tech, width, config):
     ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
     addFO4axis(fig, ax1, tech)
 
-    plt.savefig(final_directory + '/freqSweep_' + tech + '_' + width + config + '.png')
+    plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png')
 
 
 def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
@@ -144,7 +145,7 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     if norm:
         delays = [d/fo4 for d in delays]
         areas = [a/add32area for a in areas]
-   
+    
     plt.scatter(delays, areas, marker=marker, color=color)
     plt.xlabel('Cycle time (ns)')
     plt.ylabel('Area (sq microns)')
@@ -152,10 +153,10 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     plt.ylim(ymin=0, ymax=1.1*ytop)
     
     ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
-    
-    if (len(labels) > 0):
-        texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
-        adjust_text(texts)
+
+    for i in range(len(labels)):
+        plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center')
+
     return fig
 
 
@@ -163,43 +164,40 @@ def plotFeatures(tech, width, config):
     delays, areas, labels = ([] for i in range(3))
     freq = techdict[tech].targfreq
     for oneSynth in allSynths:
-        if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.config == config) & (width == oneSynth.width):
-            delays += [oneSynth.delay]
-            areas += [oneSynth.area]
-            labels += [oneSynth.mod]
-
-    if (delays == []):
-        print("No delays found for tech ", tech, " freq ", freq, ". Did you set --sky130freq, --sky90freq and --tsmcfreq?\n")
+        if (tech == oneSynth.tech) & (freq == oneSynth.freq):
+            if (oneSynth.config == config) & (width == oneSynth.width):
+                delays += [oneSynth.delay]
+                areas += [oneSynth.area]
+                labels += [oneSynth.special]
 
     fig, (ax) = plt.subplots(1, 1)
 
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
 
-    titlestr = tech+'_'+width+config+'_'+str(freq)+'MHz'
+    titlestr = tech+'_'+width+config
     plt.title(titlestr)
-    plt.savefig(final_directory + '/features_'+titlestr+'.png')
+    plt.savefig('./plots/wally/features_'+titlestr+'.png')
 
-
-def plotConfigs(tech, mod=''):
+	
+def plotConfigs(tech, special=''):
     delays, areas, labels = ([] for i in range(3))
     freq = techdict[tech].targfreq
     for oneSynth in allSynths:
-        if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
-            delays += [oneSynth.delay]
-            areas += [oneSynth.area]
-            labels += [oneSynth.width + oneSynth.config]
+        if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
+                delays += [oneSynth.delay]
+                areas += [oneSynth.area]
+                labels += [oneSynth.width + oneSynth.config]
 
     fig, (ax) = plt.subplots(1, 1)
 
-
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
 
-    titleStr = tech+'_'+mod
+    titleStr = tech+'_'+special
     plt.title(titleStr)
-    plt.savefig(final_directory + '/configs_' + titleStr + '.png')
+    plt.savefig('./plots/wally/configs_' + titleStr + '.png')
 
 
-def normAreaDelay(mod=''):
+def normAreaDelay(special=''):
     fig, (ax) = plt.subplots(1, 1)
     fullLeg = []
     for tech in list(techdict.keys()):
@@ -207,7 +205,7 @@ def normAreaDelay(mod=''):
         spec = techdict[tech]
         freq = spec.targfreq
         for oneSynth in allSynths:
-            if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.mod == mod):
+            if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special):
                     delays += [oneSynth.delay]
                     areas += [oneSynth.area]
                     labels += [oneSynth.width + oneSynth.config]
@@ -218,9 +216,9 @@ def normAreaDelay(mod=''):
     ax.set_xlabel('Cycle Time (FO4)')
     ax.set_ylabel('Area (add32)')        
     ax.legend(handles = fullLeg, loc='upper left')
-    plt.savefig(final_directory + '/normAreaDelay.png')
-
+    plt.savefig('./plots/wally/normAreaDelay.png')
 
+	
 def addFO4axis(fig, ax, tech):
     fo4 = techdict[tech].fo4
 
@@ -247,32 +245,21 @@ def addFO4axis(fig, ax, tech):
 if __name__ == '__main__':
 
     parser = argparse.ArgumentParser()
-    parser.add_argument("-s130", "--sky130freq", type=int, default=500, help = "Target frequency used for sky130 syntheses")
-    parser.add_argument("-s90", "--sky90freq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
-    parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses")
+    parser.add_argument("-s", "--skyfreq", type=int, default=3000, help = "Target frequency used for sky90 syntheses")
+    parser.add_argument("-t", "--tsmcfreq", type=int, default=10000, help = "Target frequency used for tsmc28 syntheses")
     args = parser.parse_args()
 
     TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy")
     techdict = {}
-    techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 2581, 18, 0.685)
-    techdict['sky90'] = TechSpec('gray', 'o', args.sky90freq, 43.2e-3, 1440.600027, 714.057, 0.658023)
-    techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
-
-    current_directory = os.getcwd()
-    final_directory = os.path.join(current_directory, 'wallyplots')
-    if not os.path.exists(final_directory):
-        os.makedirs(final_directory)
+    techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
+    techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
 
     synthsintocsv()
     synthsfromcsv('Summary.csv')
-    freqPlot('tsmc28psyn', 'rv32', 'e')
+    freqPlot('tsmc28', 'rv32', 'e')
     freqPlot('sky90', 'rv32', 'e')
-    freqPlot('sky130', 'rv32', 'e')
     plotFeatures('sky90', 'rv64', 'gc')
-    plotFeatures('sky130', 'rv64', 'gc')
-    plotFeatures('tsmc28psyn', 'rv64', 'gc')
-    plotConfigs('sky90', mod='orig')
-    plotConfigs('sky130', mod='orig')
-    plotConfigs('tsmc28psyn', mod='orig')
-    normAreaDelay(mod='orig')
-    os.system("./extractArea.pl")
+    plotFeatures('tsmc28', 'rv64', 'gc')
+    plotConfigs('sky90', special='orig')
+    plotConfigs('tsmc28', special='orig')
+    normAreaDelay(special='orig')
diff --git a/synthDC/ppa/bestSynths.csv b/synthDC/ppa/bestSynths.csv
index 655f171a1..7e3d35569 100644
--- a/synthDC/ppa/bestSynths.csv
+++ b/synthDC/ppa/bestSynths.csv
@@ -1,74 +1,24 @@
 Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (nJ)
-binencoder,sky130,8,1000,1.0000,50.960001,24.761,0.010685929975270078
-binencoder,sky130,16,1000,1.0000,136.220003,77.243,0.021773774467348
-binencoder,sky130,32,1000,1.0000,372.400007,189.626,0.04371111111111111
-binencoder,sky130,64,1000,1.0000,797.720015,382.205,0.07393850658857981
-binencoder,sky130,128,900,1.1111,1602.300031,610.009,0.1261366969785861
-adder,sky130,8,1700,0.588235,253.820005,154.438,0.10825587752870422
-adder,sky130,16,1300,0.7692307,722.260013,485.109,0.32460910944935417
-adder,sky130,32,1100,0.90909,1440.600027,714.057,0.6580226904376014
-adder,sky130,64,950,1.0526315,2781.240054,1050.0,0.9392239364188874
-adder,sky130,128,900,1.1111,6186.740118,2230.0,2.1480106100795755
-csa,sky130,8,1000,1.0000,266.560005,154.202,0.13650573115665163
-csa,sky130,16,1000,1.0000,533.12001,308.404,0.27263530601922104
-csa,sky130,32,1000,1.0000,1066.240021,616.808,0.5448072247308093
-csa,sky130,64,1000,1.0000,2132.480042,1230.0,1.0905412240768841
-csa,sky130,128,1000,1.0000,4264.960083,2470.0,2.178553363682347
-shifter,sky130,8,1000,1.0000,259.700005,196.451,0.07534088282874972
-shifter,sky130,16,1000,1.0000,666.400006,558.433,0.19552906110283155
-shifter,sky130,32,1000,1.0000,1475.880027,768.262,0.3807431082700759
-shifter,sky130,64,1000,1.0000,3914.120062,2680.0,1.144802541988198
-shifter,sky130,128,900,1.1111,9192.400136,6080.0,2.9008914525432616
-comparator,sky130,8,1700,0.588235,200.900004,136.6,0.05001033271337053
-comparator,sky130,16,1500,0.6666667,358.680007,189.253,0.06321553011448482
-comparator,sky130,32,1300,0.7692307,690.900013,315.709,0.10771793448084398
-comparator,sky130,64,1200,0.8333333,1372.980026,508.393,0.2048577820389901
-comparator,sky130,128,1150,0.869565,2744.980052,796.047,0.34396273737011823
-flop,sky130,8,1000,1.0000,133.279999,64.8145,0.193835
-flop,sky130,16,1000,1.0000,266.5599975,129.629,0.38715000000000005
-flop,sky130,32,1000,1.0000,533.119995,259.258,0.7723000000000001
-flop,sky130,64,1000,1.0000,1066.23999,520.0,1.54955
-flop,sky130,128,1000,1.0000,2132.4799805,1035.0,3.094
-mux2,sky130,8,1000,1.0000,63.700001,21.541,0.01932440083034535
-mux2,sky130,16,1000,1.0000,119.560002,32.354,0.03884536082474227
-mux2,sky130,32,1000,1.0000,375.340008,259.372,0.13671796921846893
-mux2,sky130,64,1000,1.0000,479.220009,115.22,0.15148539160324087
-mux2,sky130,128,1000,1.0000,1302.420025,767.078,0.4665334665334665
-mux4,sky130,8,1000,1.0000,148.960002,66.984,0.04026661024121879
-mux4,sky130,16,1000,1.0000,392.0,398.313,0.1037037037037037
-mux4,sky130,32,1000,1.0000,594.860011,331.197,0.131617289946576
-mux4,sky130,64,1000,1.0000,899.640016,344.331,0.2862533692722372
-mux4,sky130,128,1000,1.0000,2013.900038,818.249,0.6094182825484764
-mux8,sky130,8,1000,1.0000,287.140006,116.648,0.06089260808926081
-mux8,sky130,16,1000,1.0000,582.120003,282.366,0.14455681142177274
-mux8,sky130,32,1000,1.0000,1319.079995,670.683,0.35777218376337316
-mux8,sky130,64,1000,1.0000,2132.48004,808.482,0.44287680660701995
-mux8,sky130,128,1000,1.0000,4575.620089,1830.0,0.9786276715410572
-mul,sky130,8,1000,1.0000,2194.220041,1440.0,1.421374045801527
-mul,sky130,16,1000,1.0000,7519.540137,4940.0,6.376128385155466
-mul,sky130,32,1000,1.0000,25200.700446,14900.0,24.931847968545217
-mul,sky130,64,1000,1.0000,86011.661365,42600.0,88.84651898734177
-mul,sky130,128,800,1.2500,296198.144128,114000.0,273.3148854961832
-binencoder,sky90,8,7683,0.12508649056358195,50.960001,24.761,0.010685929975270078
-binencoder,sky90,16,5773,0.16977016282695304,136.220003,77.243,0.021773774467348
-binencoder,sky90,32,4500,0.2218912222222222,372.400007,189.626,0.04371111111111111
-binencoder,sky90,64,4098,0.2439914738897023,797.720015,382.205,0.07393850658857981
-binencoder,sky90,128,3409,0.2933331557641537,1602.300031,610.009,0.1261366969785861
-adder,sky90,8,3658,0.27337042810278844,253.820005,154.438,0.10825587752870422
-adder,sky90,16,2942,0.3393218266485384,722.260013,485.109,0.32460910944935417
-adder,sky90,32,2468,0.40496338573743923,1440.600027,714.057,0.6580226904376014
-adder,sky90,64,2139,0.4674681813931744,2781.240054,1050.0,0.9392239364188874
-adder,sky90,128,1885,0.5304949787798409,6186.740118,2230.0,2.1480106100795755
+priorityencoder,sky90,8,7683,0.12508649056358195,50.960001,24.761,0.010685929975270078
+priorityencoder,sky90,16,5773,0.16977016282695304,136.220003,77.243,0.021773774467348
+priorityencoder,sky90,32,4500,0.2218912222222222,372.400007,189.626,0.04371111111111111
+priorityencoder,sky90,64,4098,0.2439914738897023,797.720015,382.205,0.07393850658857981
+priorityencoder,sky90,128,3409,0.2933331557641537,1602.300031,610.009,0.1261366969785861
+add,sky90,8,3658,0.27337042810278844,253.820005,154.438,0.10825587752870422
+add,sky90,16,2942,0.3393218266485384,722.260013,485.109,0.32460910944935417
+add,sky90,32,2468,0.40496338573743923,1440.600027,714.057,0.6580226904376014
+add,sky90,64,2139,0.4674681813931744,2781.240054,1050.0,0.9392239364188874
+add,sky90,128,1885,0.5304949787798409,6186.740118,2230.0,2.1480106100795755
 csa,sky90,8,5758,0.16536141368530738,266.560005,154.202,0.13650573115665163
 csa,sky90,16,5931,0.1654056314280897,533.12001,308.404,0.27263530601922104
 csa,sky90,32,5758,0.16536141368530738,1066.240021,616.808,0.5448072247308093
 csa,sky90,64,5931,0.1654056314280897,2132.480042,1230.0,1.0905412240768841
 csa,sky90,128,5931,0.1654056314280897,4264.960083,2470.0,2.178553363682347
-shifter,sky90,8,4327,0.23025600254217704,259.700005,196.451,0.07534088282874972
-shifter,sky90,16,3355,0.29803959314456036,666.400006,558.433,0.19552906110283155
-shifter,sky90,32,2503,0.39951757530962845,1475.880027,768.262,0.3807431082700759
-shifter,sky90,64,2203,0.45385946391284615,3914.120062,2680.0,1.144802541988198
-shifter,sky90,128,1907,0.5242938489774515,9192.400136,6080.0,2.9008914525432616
+shiftleft,sky90,8,4327,0.23025600254217704,259.700005,196.451,0.07534088282874972
+shiftleft,sky90,16,3355,0.29803959314456036,666.400006,558.433,0.19552906110283155
+shiftleft,sky90,32,2503,0.39951757530962845,1475.880027,768.262,0.3807431082700759
+shiftleft,sky90,64,2203,0.45385946391284615,3914.120062,2680.0,1.144802541988198
+shiftleft,sky90,128,1907,0.5242938489774515,9192.400136,6080.0,2.9008914525432616
 comparator,sky90,8,4839,0.20629126741062204,200.900004,136.6,0.05001033271337053
 comparator,sky90,16,4018,0.24806303982080635,358.680007,189.253,0.06321553011448482
 comparator,sky90,32,3602,0.276293542476402,690.900013,315.709,0.10771793448084398
@@ -94,31 +44,31 @@ mux8,sky90,16,3362,0.295237998810232,582.120003,282.366,0.14455681142177274
 mux8,sky90,32,3178,0.3140553102580239,1319.079995,670.683,0.35777218376337316
 mux8,sky90,64,2906,0.3440756228492774,2132.48004,808.482,0.44287680660701995
 mux8,sky90,128,2667,0.3749401308586427,4575.620089,1830.0,0.9786276715410572
-mul,sky90,8,1310,0.7631557786259543,2194.220041,1440.0,1.421374045801527
-mul,sky90,16,997,1.0029260270812437,7519.540137,4940.0,6.376128385155466
-mul,sky90,32,763,1.3106129895150722,25200.700446,14900.0,24.931847968545217
-mul,sky90,64,632,1.5822664810126583,86011.661365,42600.0,88.84651898734177
-mul,sky90,128,524,1.9083759465648855,296198.144128,114000.0,273.3148854961832
-binencoder,tsmc28,8,31335,0.031912196106590074,8.316,34.836,0.001716929950534546
-binencoder,tsmc28,16,21253,0.04703118086858326,21.672,78.026,0.004008845810003294
-binencoder,tsmc28,32,16464,0.06071258114674442,61.614,207.499,0.009323372206025266
-binencoder,tsmc28,64,13804,0.07239877021153289,137.466,425.592,0.01847290640394089
-binencoder,tsmc28,128,11440,0.0874065874125874,317.646,973.649,0.041171328671328666
-adder,tsmc28,8,13838,0.07207477814713109,34.272,187.089,0.013311172134701546
-adder,tsmc28,16,11521,0.08678002100512108,90.972001,475.207,0.03367763214998698
-adder,tsmc28,32,9812,0.1018860211985324,209.286002,1060.0,0.08153281695882594
-adder,tsmc28,64,8206,0.12185605215695831,388.836003,1770.0,0.1409943943456008
-adder,tsmc28,128,7354,0.13597341881968997,907.452008,4360.0,0.3451183029643731
+mult,sky90,8,1310,0.7631557786259543,2194.220041,1440.0,1.421374045801527
+mult,sky90,16,997,1.0029260270812437,7519.540137,4940.0,6.376128385155466
+mult,sky90,32,763,1.3106129895150722,25200.700446,14900.0,24.931847968545217
+mult,sky90,64,632,1.5822664810126583,86011.661365,42600.0,88.84651898734177
+mult,sky90,128,524,1.9083759465648855,296198.144128,114000.0,273.3148854961832
+priorityencoder,tsmc28,8,31335,0.031912196106590074,8.316,34.836,0.001716929950534546
+priorityencoder,tsmc28,16,21253,0.04703118086858326,21.672,78.026,0.004008845810003294
+priorityencoder,tsmc28,32,16464,0.06071258114674442,61.614,207.499,0.009323372206025266
+priorityencoder,tsmc28,64,13804,0.07239877021153289,137.466,425.592,0.01847290640394089
+priorityencoder,tsmc28,128,11440,0.0874065874125874,317.646,973.649,0.041171328671328666
+add,tsmc28,8,13838,0.07207477814713109,34.272,187.089,0.013311172134701546
+add,tsmc28,16,11521,0.08678002100512108,90.972001,475.207,0.03367763214998698
+add,tsmc28,32,9812,0.1018860211985324,209.286002,1060.0,0.08153281695882594
+add,tsmc28,64,8206,0.12185605215695831,388.836003,1770.0,0.1409943943456008
+add,tsmc28,128,7354,0.13597341881968997,907.452008,4360.0,0.3451183029643731
 csa,tsmc28,8,24524,0.040663382319360626,52.416,482.462,0.02173381177621921
 csa,tsmc28,16,24524,0.040663382319360626,104.832,964.99,0.04346762355243842
 csa,tsmc28,32,24524,0.040663382319360626,209.664,1930.0,0.08677214157559941
 csa,tsmc28,64,24524,0.040663382319360626,419.327999,3860.0,0.17342195400424076
 csa,tsmc28,128,24524,0.040663382319360626,838.655998,7720.0,0.3471701190670363
-shifter,tsmc28,8,15202,0.0656078183133798,50.652,367.074,0.016991185370346006
-shifter,tsmc28,16,11804,0.08465604506946797,127.511999,602.29,0.03388681802778719
-shifter,tsmc28,32,9587,0.10430391697089808,384.803997,1940.0,0.10180452696359654
-shifter,tsmc28,64,8272,0.12086674854932303,1041.263998,5460.0,0.2895309477756286
-shifter,tsmc28,128,7023,0.14238329232521713,1836.953994,8670.0,0.566566994162039
+shiftleft,tsmc28,8,15202,0.0656078183133798,50.652,367.074,0.016991185370346006
+shiftleft,tsmc28,16,11804,0.08465604506946797,127.511999,602.29,0.03388681802778719
+shiftleft,tsmc28,32,9587,0.10430391697089808,384.803997,1940.0,0.10180452696359654
+shiftleft,tsmc28,64,8272,0.12086674854932303,1041.263998,5460.0,0.2895309477756286
+shiftleft,tsmc28,128,7023,0.14238329232521713,1836.953994,8670.0,0.566566994162039
 comparator,tsmc28,8,17422,0.05733769130983814,35.784,170.595,0.009488003673516243
 comparator,tsmc28,16,13736,0.07273839778683751,54.558,250.167,0.014349155503785673
 comparator,tsmc28,32,12139,0.08236710865804432,145.782,622.975,0.03567015404893319
@@ -144,58 +94,8 @@ mux8,tsmc28,16,12264,0.08147446510110894,128.771998,548.714,0.02666340508806262
 mux8,tsmc28,32,11713,0.08517122410996329,172.115999,823.633,0.046956373260479814
 mux8,tsmc28,64,11014,0.09067453550027238,304.163999,1460.0,0.08498274922825495
 mux8,tsmc28,128,10474,0.09542350830628223,683.045996,2820.0,0.15705556616383426
-mul,tsmc28,8,5200,0.1922996923076923,577.206,4340.0,0.37769230769230766
-mul,tsmc28,16,3819,0.26184265147944485,1634.472002,11800.0,1.4553548049227547
-mul,tsmc28,32,3033,0.3295775611605671,6343.721998,47200.0,6.303330036267723
-mul,tsmc28,64,2390,0.4184090418410042,16045.092071,109000.0,18.54602510460251
-mul,tsmc28,128,1868,0.5353279057815846,44272.49428,262000.0,50.01177730192719
-binencoder,tsmc28psyn,8,31335,0.031912196106590074,8.316,34.836,0.001716929950534546
-binencoder,tsmc28psyn,16,21253,0.04703118086858326,21.672,78.026,0.004008845810003294
-binencoder,tsmc28psyn,32,16464,0.06071258114674442,61.614,207.499,0.009323372206025266
-binencoder,tsmc28psyn,64,13804,0.07239877021153289,137.466,425.592,0.01847290640394089
-binencoder,tsmc28psyn,128,11440,0.0874065874125874,317.646,973.649,0.041171328671328666
-adder,tsmc28psyn,8,13838,0.07207477814713109,34.272,187.089,0.013311172134701546
-adder,tsmc28psyn,16,11521,0.08678002100512108,90.972001,475.207,0.03367763214998698
-adder,tsmc28psyn,32,9812,0.1018860211985324,209.286002,1060.0,0.08153281695882594
-adder,tsmc28psyn,64,8206,0.12185605215695831,388.836003,1770.0,0.1409943943456008
-adder,tsmc28psyn,128,7000,0.142857142857,907.452008,4360.0,0.3451183029643731
-csa,tsmc28psyn,8,24524,0.040663382319360626,52.416,482.462,0.02173381177621921
-csa,tsmc28psyn,16,24524,0.040663382319360626,104.832,964.99,0.04346762355243842
-csa,tsmc28psyn,32,24524,0.040663382319360626,209.664,1930.0,0.08677214157559941
-csa,tsmc28psyn,64,24524,0.040663382319360626,419.327999,3860.0,0.17342195400424076
-csa,tsmc28psyn,128,24524,0.040663382319360626,838.655998,7720.0,0.3471701190670363
-shifter,tsmc28psyn,8,15202,0.0656078183133798,50.652,367.074,0.016991185370346006
-shifter,tsmc28psyn,16,11804,0.08465604506946797,127.511999,602.29,0.03388681802778719
-shifter,tsmc28psyn,32,9587,0.10430391697089808,384.803997,1940.0,0.10180452696359654
-shifter,tsmc28psyn,64,8272,0.12086674854932303,1041.263998,5460.0,0.2895309477756286
-shifter,tsmc28psyn,128,7023,0.14238329232521713,1836.953994,8670.0,0.566566994162039
-comparator,tsmc28psyn,8,17422,0.05733769130983814,35.784,170.595,0.009488003673516243
-comparator,tsmc28psyn,16,13736,0.07273839778683751,54.558,250.167,0.014349155503785673
-comparator,tsmc28psyn,32,12139,0.08236710865804432,145.782,622.975,0.03567015404893319
-comparator,tsmc28psyn,64,11080,0.09024670758122744,294.21,1250.0,0.0684115523465704
-comparator,tsmc28psyn,128,9371,0.10671119720414043,558.432,2400.0,0.12794792444776437
-flop,tsmc28psyn,8,10,0.048889000000002625,15.12,78.6345,0.027246000000000003
-flop,tsmc28psyn,16,10,0.048889000000002625,30.24,157.29,0.054290000000000005
-flop,tsmc28psyn,32,10,0.048889000000002625,60.4799995,314.5805,0.10908000000000001
-flop,tsmc28psyn,64,10,0.048889000000002625,120.959999,630.0,0.21765500000000004
-flop,tsmc28psyn,128,10,0.048889000000002625,241.919998,1260.0,0.43579999999999997
-mux2,tsmc28psyn,8,29614,0.03374481252110488,16.758,114.564,0.005436617815897886
-mux2,tsmc28psyn,16,18767,0.053046021580433735,15.75,88.025,0.005142004582511856
-mux2,tsmc28psyn,32,17903,0.05585556035301346,32.130001,171.146,0.009897782494553985
-mux2,tsmc28psyn,64,18568,0.05371109651012495,91.35,523.884,0.027574321413183972
-mux2,tsmc28psyn,128,16637,0.05991099044298852,176.525999,941.106,0.05012923002945243
-mux4,tsmc28psyn,8,18151,0.055092383284667513,27.971999,133.963,0.008032615282904523
-mux4,tsmc28psyn,16,16486,0.06057952759917506,39.438,186.231,0.012556108213029236
-mux4,tsmc28psyn,32,15196,0.06580579126085812,69.174,324.969,0.023229797315082915
-mux4,tsmc28psyn,64,13926,0.07180612868016659,137.465999,648.086,0.04574177796926612
-mux4,tsmc28psyn,128,13090,0.07636619404125286,294.335997,1420.0,0.09358288770053477
-mux8,tsmc28psyn,8,12902,0.07750336319950395,44.604,214.286,0.0117501162610448
-mux8,tsmc28psyn,16,12264,0.08147446510110894,128.771998,548.714,0.02666340508806262
-mux8,tsmc28psyn,32,11713,0.08517122410996329,172.115999,823.633,0.046956373260479814
-mux8,tsmc28psyn,64,11014,0.09067453550027238,304.163999,1460.0,0.08498274922825495
-mux8,tsmc28psyn,128,10474,0.09542350830628223,683.045996,2820.0,0.15705556616383426
-mul,tsmc28psyn,8,5200,0.1922996923076923,577.206,4340.0,0.37769230769230766
-mul,tsmc28psyn,16,3819,0.26184265147944485,1634.472002,11800.0,1.4553548049227547
-mul,tsmc28psyn,32,3033,0.3295775611605671,6343.721998,47200.0,6.303330036267723
-mul,tsmc28psyn,64,2390,0.4184090418410042,16045.092071,109000.0,18.54602510460251
-mul,tsmc28psyn,128,1868,0.5353279057815846,44272.49428,262000.0,50.01177730192719
+mult,tsmc28,8,5200,0.1922996923076923,577.206,4340.0,0.37769230769230766
+mult,tsmc28,16,3819,0.26184265147944485,1634.472002,11800.0,1.4553548049227547
+mult,tsmc28,32,3033,0.3295775611605671,6343.721998,47200.0,6.303330036267723
+mult,tsmc28,64,2390,0.4184090418410042,16045.092071,109000.0,18.54602510460251
+mult,tsmc28,128,1868,0.5353279057815846,44272.49428,262000.0,50.01177730192719
diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py
index 296abf20d..2dce62ae5 100755
--- a/synthDC/ppa/ppaAnalyze.py
+++ b/synthDC/ppa/ppaAnalyze.py
@@ -1,258 +1,194 @@
-#!/usr/bin/env python3
-#
-# Python regression test for DC
+#!/usr/bin/python3
 # Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
-# James Stine james.stine@okstate.edu 15 October 2023
-#
 
-import csv
-import os
-import re
-import subprocess
-from collections import namedtuple
-
-import matplotlib as mpl
-import matplotlib.lines as lines
-import matplotlib.pyplot as plt
-import numpy as np
 import scipy.optimize as opt
-import sklearn.metrics as skm  # depricated, will need to replace with scikit-learn
+import subprocess
+import csv
+import re
 from matplotlib.cbook import flatten
-
+import matplotlib.pyplot as plt
+import matplotlib.lines as lines
+import matplotlib as mpl
+import numpy as np
+from collections import namedtuple
+import sklearn.metrics as skm
+import os
 
 def synthsfromcsv(filename):
     Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy")
-    with open(filename, newline="") as csvfile:
+    with open(filename, newline='') as csvfile:
         csvreader = csv.reader(csvfile)
         global allSynths
         allSynths = list(csvreader)[1:]
         for i in range(len(allSynths)):
             for j in range(len(allSynths[0])):
-                try:
-                    allSynths[i][j] = int(allSynths[i][j])
-                except:
-                    try:
-                        allSynths[i][j] = float(allSynths[i][j])
-                    except:
-                        pass
+                try: allSynths[i][j] = int(allSynths[i][j])
+                except: 
+                    try: allSynths[i][j] = float(allSynths[i][j])
+                    except: pass
             allSynths[i] = Synth(*allSynths[i])
     return allSynths
-
-
+    
 def synthsintocsv():
-    """writes a CSV with one line for every available synthesis
-    each line contains the module, tech, width, target freq, and resulting metrics
-    """
+    ''' writes a CSV with one line for every available synthesis
+        each line contains the module, tech, width, target freq, and resulting metrics
+    '''
     print("This takes a moment...")
-    bashCommand = "find . -path '*runs/*' -prune"
-    output = subprocess.check_output(["bash", "-c", bashCommand])
-    allSynths = output.decode("utf-8").split("\n")[:-1]
+    bashCommand = "find . -path '*runs/ppa*rv32e*' -prune"
+    output = subprocess.check_output(['bash','-c', bashCommand])
+    allSynths = output.decode("utf-8").split('\n')[:-1]
 
-    specReg = re.compile("[a-zA-Z0-9]+")
-    metricReg = re.compile(r"-?\d+\.\d+[e]?[-+]?\d*")
+    specReg = re.compile('[a-zA-Z0-9]+')
+    metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*')
 
-    with open("ppaData.csv", "w") as file:
-        writer = csv.writer(file)
-        writer.writerow(
-            [
-                "Module",
-                "Tech",
-                "Width",
-                "Target Freq",
-                "Delay",
-                "Area",
-                "L Power (nW)",
-                "D energy (nJ)",
-            ]
-        )
+    file = open("ppaData.csv", "w")
+    writer = csv.writer(file)
+    writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (nJ)'])
 
-        for oneSynth in allSynths:
-            module, width, risc, tech, freq = specReg.findall(oneSynth)[1:6]
-            tech = tech[:-2]  
-            metrics = []
-            for phrase in [["Path Slack", "qor"], ["Design Area", "qor"], ["100", "power"]]:
-                bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
-                bashCommand = bashCommand.format(*phrase)
-                try:
-                    output = subprocess.check_output(["bash", "-c", bashCommand])
-                except:
-                    print(module + width + tech + freq + " doesn't have reports")
-                    print("Consider running cleanup() first")
-                nums = metricReg.findall(str(output))
-                nums = [float(m) for m in nums]
-                metrics += nums
-            delay = 1000 / int(freq) - metrics[0]
-            area = metrics[1]
-            lpower = metrics[4]
-            tpower = (metrics[2] + metrics[3] + metrics[4]*.000001)
-            denergy = (
-                (tpower) / int(freq) * 1000
-            )  # (switching + internal powers)*delay, more practical units for regression coefs
+    for oneSynth in allSynths:
+        module, width, risc, tech, freq = specReg.findall(oneSynth)[2:7]
+        tech = tech[:-2]
+        metrics = []
+        for phrase in [['Path Slack', 'qor'], ['Design Area', 'qor'], ['100', 'power']]:
+            bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*'
+            bashCommand = bashCommand.format(*phrase)
+            try: output = subprocess.check_output(['bash','-c', bashCommand])
+            except: 
+                print(module + width + tech + freq + " doesn't have reports")
+                print("Consider running cleanup() first")
+            nums = metricReg.findall(str(output))
+            nums = [float(m) for m in nums]
+            metrics += nums
+        delay = 1000/int(freq) - metrics[0]
+        area = metrics[1]
+        lpower = metrics[4]
+        denergy = (metrics[2] + metrics[3])/int(freq)*1000 # (switching + internal powers)*delay, more practical units for regression coefs
 
-            if "flop" in module:  # since two flops in each module
-                [area, lpower, denergy] = [n / 2 for n in [area, lpower, denergy]]
-
-            writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
+        if ('flop' in module): # since two flops in each module 
+            [area, lpower, denergy] = [n/2 for n in [area, lpower, denergy]] 
 
+        writer.writerow([module, tech, width, freq, delay, area, lpower, denergy])
+    file.close()
 
 def cleanup():
-    """removes runs that didn't work"""
+    ''' removes runs that didn't work
+    '''
     bashCommand = 'grep -r "Error" runs/ppa*/reports/*qor*'
-    try:
-        output = subprocess.check_output(["bash", "-c", bashCommand])
-        allSynths = output.decode("utf-8").split("\n")[:-1]
+    try: 
+        output = subprocess.check_output(['bash','-c', bashCommand])
+        allSynths = output.decode("utf-8").split('\n')[:-1]
         for run in allSynths:
-            run = run.split("MHz")[0]
-            bc = "rm -r " + run + "*"
-            output = subprocess.check_output(["bash", "-c", bc])
-    except:
-        pass
+            run = run.split('MHz')[0]
+            bc = 'rm -r '+ run + '*'
+            output = subprocess.check_output(['bash','-c', bc])
+    except: pass
 
-    bashCommand = "find . -path '*runs/*' -prune"
-    output = subprocess.check_output(["bash", "-c", bashCommand])
-    allSynths = output.decode("utf-8").split("\n")[:-1]
+    bashCommand = "find . -path '*runs/ppa*rv32e*' -prune"
+    output = subprocess.check_output(['bash','-c', bashCommand])
+    allSynths = output.decode("utf-8").split('\n')[:-1]
     for oneSynth in allSynths:
-        for phrase in [["Path Length", "qor"]]:
-            bashCommand = 'grep "{}" ' + oneSynth[2:] + "/reports/*{}*"
+        for phrase in [['Path Length', 'qor']]:
+            bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*'
             bashCommand = bashCommand.format(*phrase)
-            try:
-                output = subprocess.check_output(["bash", "-c", bashCommand])
-            except:
-                bc = "rm -r " + oneSynth[2:]
-                output = subprocess.check_output(["bash", "-c", bc])
+            try: output = subprocess.check_output(['bash','-c', bashCommand])
+            except: 
+                bc = 'rm -r '+ oneSynth[2:]
+                output = subprocess.check_output(['bash','-c', bc])
     print("All cleaned up!")
 
-
 def getVals(tech, module, var, freq=None, width=None):
-    """for a specified tech, module, and variable/metric
-    returns a list of values for that metric in ascending width order
-    works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width
-    """
+    ''' for a specified tech, module, and variable/metric
+        returns a list of values for that metric in ascending width order
+        works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width
+    '''
 
-    widthsToGet = width if width is not None else widths
+    if width != None:
+        widthsToGet = width
+    else:
+        widthsToGet = widths
 
     metric = []
     widthL = []
 
-    if freq is not None:
+    if (freq != None):
         for oneSynth in allSynths:
-            if (
-                (oneSynth.freq == freq)
-                & (oneSynth.tech == tech)
-                & (oneSynth.module == module)
-                & (oneSynth.width != 1)
-            ):
+            if (oneSynth.freq == freq) & (oneSynth.tech == tech) & (oneSynth.module == module) & (oneSynth.width != 1):
                 widthL += [oneSynth.width]
                 osdict = oneSynth._asdict()
                 metric += [osdict[var]]
-        metric = [x for _, x in sorted(zip(widthL, metric))]  # ordering
+        metric = [x for _, x in sorted(zip(widthL, metric))] # ordering
     else:
         for w in widthsToGet:
             for oneSynth in bestSynths:
-                if (
-                    (oneSynth.width == w)
-                    & (oneSynth.tech == tech)
-                    & (oneSynth.module == module)
-                ):
+                if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module):
                     osdict = oneSynth._asdict()
                     met = osdict[var]
                     metric += [met]
     return metric
 
-
 def csvOfBest(filename):
     bestSynths = []
     for tech in [x.tech for x in techSpecs]:
         for mod in modules:
             for w in widths:
-                m = np.Inf  # large number to start
+                m = np.Inf # large number to start
                 best = None
-                for oneSynth in allSynths:  # best achievable, rightmost green
+                for oneSynth in allSynths: # best achievable, rightmost green
                     if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod):
-                        if (oneSynth.delay < m) & (1000 / oneSynth.delay > oneSynth.freq):
+                        if (oneSynth.delay < m) & (1000/oneSynth.delay > oneSynth.freq): 
                             m = oneSynth.delay
                             best = oneSynth
 
-                if (best is not None) & (best not in bestSynths):
+                if (best != None) & (best not in bestSynths):
                     bestSynths += [best]
-
-    with open(filename, "w") as file:
-        writer = csv.writer(file)
-        writer.writerow(
-            [
-                "Module",
-                "Tech",
-                "Width",
-                "Target Freq",
-                "Delay",
-                "Area",
-                "L Power (nW)",
-                "D energy (nJ)",
-            ]
-        )
-        for synth in bestSynths:
-            writer.writerow(list(synth))
+    
+    file = open(filename, "w")
+    writer = csv.writer(file)
+    writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (nJ)'])
+    for synth in bestSynths:
+        writer.writerow(list(synth))
+    file.close()
     return bestSynths
-
-
+    
 def genLegend(fits, coefs, r2=None, spec=None, ale=False):
-    """generates a list of two legend elements (or just an equation if no r2 or spec)
-    labels line with fit equation and dots with r squared of the fit
-    """
+    ''' generates a list of two legend elements (or just an equation if no r2 or spec)
+        labels line with fit equation and dots with r squared of the fit
+    '''
 
     coefsr = [str(sigfig(c, 2)) for c in coefs]
     if ale:
-        if normAddWidth == 32:
-            sub = "S"
+        if (normAddWidth == 32):
+            sub = 'S'
         elif normAddWidth != 1:
-            print("Equations are wrong, check normAddWidth")
+            print('Equations are wrong, check normAddWidth')
     else:
-        sub = "N"
+        sub = 'N'
 
-    eqDict = {
-        "c": "",
-        "l": sub,
-        "s": "$" + sub + "^2$",
-        "g": "$log_2$(" + sub + ")",
-        "n": "" + sub + "$log_2$(" + sub + ")",
-    }
-    eq = ""
-    ind = 0
+    eqDict = {'c': '', 'l': sub, 's': '$'+sub+'^2$', 'g': '$log_2$('+sub+')', 'n': ''+sub+'$log_2$('+sub+')'}
+    eq = ''
+    ind = 0    
 
-    for k in eqDict:
+    for k in eqDict.keys():
         if k in fits:
-            if str(coefsr[ind]) != "0":
-                eq += " + " + coefsr[ind] + eqDict[k]
+            if str(coefsr[ind]) != '0': eq += " + " + coefsr[ind] + eqDict[k]
             ind += 1
 
-    eq = eq[3:]  # chop off leading ' + '
+    eq = eq[3:] # chop off leading ' + '
 
-    if (r2 is None) or (spec is None):
+    if (r2==None) or (spec==None):
         return eq
     else:
         legend_elements = [lines.Line2D([0], [0], color=spec.color, label=eq)]
-        legend_elements += [
-            lines.Line2D(
-                [0],
-                [0],
-                color=spec.color,
-                ls="",
-                marker=spec.shape,
-                label="$R^2$=" + str(round(r2, 4)),
-            )
-        ]
+        legend_elements += [lines.Line2D([0], [0], color=spec.color, ls='', marker=spec.shape, label='$R^2$='+ str(round(r2, 4)))]
         return legend_elements
 
-
-def oneMetricPlot(
-    module, widths, var, freq=None, ax=None, fits="clsgn", norm=True, color=None
-):
-    """module: string module name
-    freq: int freq (MHz)
-    var: string delay, area, lpower, or denergy
-    fits: constant, linear, square, log2, Nlog2
-    plots given variable vs width for all matching syntheses with regression
-    """
+def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, color=None):
+    ''' module: string module name
+        freq: int freq (MHz)
+        var: string delay, area, lpower, or denergy
+        fits: constant, linear, square, log2, Nlog2
+        plots given variable vs width for all matching syntheses with regression
+    '''
     singlePlot = True
     if ax or (freq == 10):
         singlePlot = False
@@ -263,24 +199,24 @@ def oneMetricPlot(
     allWidths = []
     allMetrics = []
 
-    ale = var != "delay"  # if not delay, must be area, leakage, or energy
+    ale = (var != 'delay') # if not delay, must be area, leakage, or energy
     modFit = fitDict[module]
     fits = modFit[ale]
 
-    ls = "--" if freq else "-"
+    if freq:
+        ls = '--'
+    else:
+        ls = '-'
 
     for spec in techSpecs:
-        # print(f"Searching for module of spec {spec} and module {module} and var {var}")
         metric = getVals(spec.tech, module, var, freq=freq)
-        # print(f"Found metric : {metric}")
+        
         if norm:
             techdict = spec._asdict()
             norm = techdict[var]
-            metric = [m / norm for m in metric]
+            metric = [m/norm for m in metric]
 
-        if len(widths) == len(metric):
-            # don't include the spec if we don't have points for all widths
-            # print(f"Width \neq Metric")
+        if len(metric) == 5: # don't include the spec if we don't have points for all widths
             xp, pred, coefs, r2 = regress(widths, metric, fits, ale)
             fullLeg += genLegend(fits, coefs, r2, spec, ale=ale)
             c = color if color else spec.color
@@ -289,77 +225,44 @@ def oneMetricPlot(
             allWidths += widths
             allMetrics += metric
 
-        # print(f"Widths passed into regress : {allWidths}")
-        if len(allWidths) > 0:
-            xp, pred, coefs, r2 = regress(allWidths, allMetrics, fits)
-            ax.plot(xp, pred, color="orange", linestyle=ls)
-        else:
-            xp, pred, coefs, r2 = regress(widths, metric, fits)
-            ax.plot(xp, pred, color="orange", linestyle=ls)
+    xp, pred, coefs, r2 = regress(allWidths, allMetrics, fits)
+    ax.plot(xp, pred, color='red', linestyle=ls)
 
     if norm:
-        ylabeldic = {
-            "lpower": "Leakage Power (add32)",
-            "denergy": "Energy/Op (add32)",
-            "area": "Area (add32)",
-            "delay": "Delay (FO4)",
-        }
+        ylabeldic = {"lpower": "Leakage Power (add32)", "denergy": "Energy/Op (add32)", "area": "Area (add32)", "delay": "Delay (FO4)"}
     else:
-        ylabeldic = {
-            "lpower": "Leakage Power (nW)",
-            "denergy": "Dynamic Energy (nJ)",
-            "area": "Area (sq microns)",
-            "delay": "Delay (ns)",
-        }
+        ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (nJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"}
 
     ax.set_ylabel(ylabeldic[var])
     ax.set_xticks(widths)
 
-    if singlePlot or (var == "lpower") or (var == "denergy"):
+    if singlePlot or (var == 'lpower') or (var == 'denergy'):
         ax.set_xlabel("Width (bits)")
-    if not singlePlot and ((var == "delay") or (var == "area")):
-        ax.tick_params(labelbottom=False)
+    if not singlePlot and ((var == 'delay') or (var == 'area')):
+        ax.tick_params(labelbottom=False)    
 
     if singlePlot:
         fullLeg += genLegend(fits, coefs, r2, combined, ale=ale)
-        legLoc = "upper left" if ale else "center right"
+        legLoc = 'upper left' if ale else 'center right'
         ax.add_artist(ax.legend(handles=fullLeg, loc=legLoc))
-        titleStr = (
-            "  (target  " + str(freq) + "MHz)"
-            if freq is not None
-            else " (best achievable delay)"
-        )
+        titleStr = "  (target  " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)"
         ax.set_title(module + titleStr)
-        plt.savefig(".plots/" + module + "_" + var + ".png")
+        plt.savefig('.plots/'+ module + '_' + var + '.png')
         # plt.show()
     return r2
 
+def regress(widths, var, fits='clsgn', ale=False):
+    ''' fits a curve to the given points
+        returns lists of x and y values to plot that curve and coefs for the eq with r2
+    '''
 
-def regress(widths, var, fits="clsgn", ale=False):
-    """fits a curve to the given points
-    returns lists of x and y values to plot that curve and coefs for the eq with r2
-    """
-    if len(var) != len(widths):
-        # print(
-        #    f"There are not enough variables to match widths. Widths : {widths} Variables Found : {var}, padding to match may affect correctness (doing it anyways)\n"
-        # )
-        if len(widths) > len(var):
-            while len(widths) > len(var):
-                var.append(0.0)
-        if len(var) > len(widths):
-            while len(var) > len(widths):
-                widths.append(0)
-
-    # widths = [8, 16, 32, 64, 128]
-    # print(f"Regress var : {var}")
-    # print(f"Regress widths : {widths}")
     funcArr = genFuncs(fits)
-    xp = np.linspace(min(widths) / 2, max(widths) * 1.1, 200)
+    xp = np.linspace(min(widths)/2, max(widths)*1.1, 200)
     xpToCalc = xp
 
     if ale:
-        widths = [w / normAddWidth for w in widths]
-        xpToCalc = [x / normAddWidth for x in xp]
+        widths = [w/normAddWidth for w in widths]
+        xpToCalc = [x/normAddWidth for x in xp]
 
     mat = []
     for w in widths:
@@ -367,9 +270,8 @@ def regress(widths, var, fits="clsgn", ale=False):
         for func in funcArr:
             row += [func(w)]
         mat += [row]
-
-    # var = [0, 1, 2, 3, 4]
-    y = np.array(var, dtype=np.float64)
+    
+    y = np.array(var, dtype=np.float)
     coefs = opt.nnls(mat, y)[0]
 
     yp = []
@@ -385,22 +287,62 @@ def regress(widths, var, fits="clsgn", ale=False):
 
     return xp, pred, coefs, r2
 
-
 def makeCoefTable():
-    """writes CSV with each line containing the coefficients for a regression fit
-    to a particular combination of module, metric (including both techs, normalized)
-    """
-    with open("ppaFitting.csv", "w") as file:
-        writer = csv.writer(file)
-        writer.writerow(
-            ["Module", "Metric", "Target", "1", "N", "N^2", "log2(N)", "Nlog2(N)", "R^2"]
-        )
+    ''' writes CSV with each line containing the coefficients for a regression fit 
+        to a particular combination of module, metric (including both techs, normalized)
+    '''
+    file = open("ppaFitting.csv", "w")
+    writer = csv.writer(file)
+    writer.writerow(['Module', 'Metric', 'Target', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2'])
 
-        for module in modules:
-            for freq in [10, None]:
-                target = "easy" if freq else "hard"
-                for var in ["delay", "area", "lpower", "denergy"]:
-                    ale = var != "delay"
+    for module in modules:
+        for freq in [10, None]:
+            target = 'easy' if freq else 'hard'
+            for var in ['delay', 'area', 'lpower', 'denergy']:
+                ale = (var != 'delay')
+                metL = []
+                modFit = fitDict[module]
+                fits = modFit[ale]
+
+                for spec in techSpecs:
+                    metric = getVals(spec.tech, module, var, freq=freq)
+                    techdict = spec._asdict()
+                    norm = techdict[var]
+                    metL += [m/norm for m in metric]
+
+                xp, pred, coefs, r2 = regress(widths*2, metL, fits, ale)
+                coefs = np.ndarray.tolist(coefs)
+                coefsToWrite  = [None]*5
+                fitTerms = 'clsgn'
+                ind = 0
+                for i in range(len(fitTerms)):
+                    if fitTerms[i] in fits:
+                        coefsToWrite[i] = coefs[ind]
+                        ind += 1
+                row = [module, var, target] + coefsToWrite + [r2]
+                writer.writerow(row)
+
+    file.close()
+
+def sigfig(num, figs):
+    return '{:g}'.format(float('{:.{p}g}'.format(num, p=figs)))
+
+def makeEqTable():
+    ''' writes CSV with each line containing the equations for fits for each metric 
+        to a particular module (including both techs, normalized)
+    '''
+    file = open("ppaEquations.csv", "w")
+    writer = csv.writer(file)
+    writer.writerow(['Element', 'Best delay', 'Fast area', 'Fast leakage', 'Fast energy', 'Small area', 'Small leakage', 'Small energy'])
+
+    for module in modules:
+        eqs = []
+        for freq in [None, 10]:
+            for var in ['delay', 'area', 'lpower', 'denergy']:
+                if (var == 'delay') and (freq == 10):
+                    pass
+                else:
+                    ale = (var != 'delay')
                     metL = []
                     modFit = fitDict[module]
                     fits = modFit[ale]
@@ -409,174 +351,103 @@ def makeCoefTable():
                         metric = getVals(spec.tech, module, var, freq=freq)
                         techdict = spec._asdict()
                         norm = techdict[var]
-                        metL += [m / norm for m in metric]
+                        metL += [m/norm for m in metric]
 
-                    xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
+                    xp, pred, coefs, r2 = regress(widths*2, metL, fits, ale)
                     coefs = np.ndarray.tolist(coefs)
-                    coefsToWrite = [None] * 5
-                    fitTerms = "clsgn"
-                    ind = 0
-                    for i in range(len(fitTerms)):
-                        if fitTerms[i] in fits:
-                            coefsToWrite[i] = coefs[ind]
-                            ind += 1
-                    row = [module, var, target] + coefsToWrite + [r2]
-                    writer.writerow(row)
+                    eqs += [genLegend(fits, coefs, ale=ale)]
+        row = [module] + eqs
+        writer.writerow(row)
 
+    file.close()
 
-def sigfig(num, figs):
-    return "{:g}".format(float("{:.{p}g}".format(num, p=figs)))
-
-
-def makeEqTable():
-    """writes CSV with each line containing the equations for fits for each metric
-    to a particular module (including both techs, normalized)
-    """
-    with open("ppaEquations.csv", "w") as file:
-        writer = csv.writer(file)
-        writer.writerow(
-            [
-                "Element",
-                "Best delay",
-                "Fast area",
-                "Fast leakage",
-                "Fast energy",
-                "Small area",
-                "Small leakage",
-                "Small energy",
-            ]
-        )
-
-        for module in modules:
-            eqs = []
-            for freq in [None, 10]:
-                for var in ["delay", "area", "lpower", "denergy"]:
-                    if (var == "delay") and (freq == 10):
-                        pass
-                    else:
-                        ale = var != "delay"
-                        metL = []
-                        modFit = fitDict[module]
-                        fits = modFit[ale]
-
-                        for spec in techSpecs:
-                            metric = getVals(spec.tech, module, var, freq=freq)
-                            techdict = spec._asdict()
-                            norm = techdict[var]
-                            metL += [m / norm for m in metric]
-
-                        xp, pred, coefs, r2 = regress(widths * 2, metL, fits, ale)
-                        coefs = np.ndarray.tolist(coefs)
-                        eqs += [genLegend(fits, coefs, ale=ale)]
-            row = [module] + eqs
-            writer.writerow(row)
-
-def genFuncs(fits="clsgn"):
-    """helper function for regress()
-    returns array of functions with one for each term desired in the regression fit
-    """
+def genFuncs(fits='clsgn'):
+    ''' helper function for regress()
+        returns array of functions with one for each term desired in the regression fit
+    '''
     funcArr = []
-    if "c" in fits:
+    if 'c' in fits:
         funcArr += [lambda x: 1]
-    if "l" in fits:
+    if 'l' in fits:
         funcArr += [lambda x: x]
-    if "s" in fits:
+    if 's' in fits:
         funcArr += [lambda x: x**2]
-    if "g" in fits:
+    if 'g' in fits:
         funcArr += [lambda x: np.log2(x)]
-    if "n" in fits:
-        funcArr += [lambda x: x * np.log2(x)]
+    if 'n' in fits:
+        funcArr += [lambda x: x*np.log2(x)]
     return funcArr
 
-
 def noOutliers(median, freqs, delays, areas):
-    """returns a pared down list of freqs, delays, and areas
-    cuts out any syntheses in which target freq isn't within 75% of the min delay target to focus on interesting area
-    helper function to freqPlot()
-    """
-    f = []
-    d = []
-    a = []
+    ''' returns a pared down list of freqs, delays, and areas 
+        cuts out any syntheses in which target freq isn't within 75% of the min delay target to focus on interesting area
+        helper function to freqPlot()
+    '''
+    f=[]
+    d=[]
+    a=[]
     for i in range(len(freqs)):
-        norm = freqs[i] / median
-        if (norm > 0.4) & (norm < 1.4):
+        norm = freqs[i]/median
+        if (norm > 0.4) & (norm<1.4):
             f += [freqs[i]]
             d += [delays[i]]
             a += [areas[i]]
-
+    
     return f, d, a
 
-
 def freqPlot(tech, mod, width):
-    """plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width"""
+    ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width
+    '''
 
     freqsL, delaysL, areasL = ([[], []] for i in range(3))
     for oneSynth in allSynths:
-        if (
-            (mod == oneSynth.module)
-            & (width == oneSynth.width)
-            & (tech == oneSynth.tech)
-        ):
-            ind = (
-                1000 / oneSynth.delay < oneSynth.freq
-            )  # when delay is within target clock period
+        if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech):
+            ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
             freqsL[ind] += [oneSynth.freq]
             delaysL[ind] += [oneSynth.delay]
             areasL[ind] += [oneSynth.area]
 
     median = np.median(list(flatten(freqsL)))
-
+    
     f, (ax1, ax2) = plt.subplots(2, 1, sharex=True)
     for ax in (ax1, ax2):
-        ax.ticklabel_format(useOffset=False, style="plain")
+        ax.ticklabel_format(useOffset=False, style='plain')
 
-    for ind in [0, 1]:
+    for ind in [0,1]:
         areas = areasL[ind]
         delays = delaysL[ind]
         freqs = freqsL[ind]
 
-        freqs, delays, areas = noOutliers(
-            median, freqs, delays, areas
-        )  # comment out to see all syntheses
+        freqs, delays, areas = noOutliers(median, freqs, delays, areas) # comment out to see all syntheses
 
-        c = "blue" if ind else "green"
+        c = 'blue' if ind else 'green'
         ax1.scatter(freqs, delays, color=c)
         ax2.scatter(freqs, areas, color=c)
 
-    legend_elements = [
-        lines.Line2D(
-            [0], [0], color="green", ls="", marker="o", label="timing achieved"
-        ),
-        lines.Line2D([0], [0], color="blue", ls="", marker="o", label="slack violated"),
-    ]
+    legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'),
+                       lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')]
 
     ax1.legend(handles=legend_elements)
     width = str(width)
-
+    
     ax2.set_xlabel("Target Freq (MHz)")
-    ax1.set_ylabel("Delay (ns)")
-    ax2.set_ylabel("Area (sq microns)")
-    ax1.set_title(mod + "_" + width)
-    if ("mux" in mod) & ("d" in mod):
+    ax1.set_ylabel('Delay (ns)')
+    ax2.set_ylabel('Area (sq microns)')
+    ax1.set_title(mod + '_' + width)
+    if ('mux' in mod) & ('d' in mod):
         width = mod
-        mod = "muxd"
-    plt.savefig("./plots/freqBuckshot/" + tech + "/" + mod + "/" + width + ".png")
+        mod = 'muxd'
+    plt.savefig('./plots/freqBuckshot/' + tech + '/' + mod + '/' + width + '.png')
     # plt.show()
 
-
 def squareAreaDelay(tech, mod, width):
-    """plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width"""
+    ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width
+    '''
     global allSynths
     freqsL, delaysL, areasL = ([[], []] for i in range(3))
     for oneSynth in allSynths:
-        if (
-            (mod == oneSynth.module)
-            & (width == oneSynth.width)
-            & (tech == oneSynth.tech)
-        ):
-            ind = (
-                1000 / oneSynth.delay < oneSynth.freq
-            )  # when delay is within target clock period
+        if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech):
+            ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period
             freqsL[ind] += [oneSynth.freq]
             delaysL[ind] += [oneSynth.delay]
             areasL[ind] += [oneSynth.area]
@@ -584,212 +455,180 @@ def squareAreaDelay(tech, mod, width):
     f, (ax1) = plt.subplots(1, 1)
     ax2 = ax1.twinx()
 
-    for ind in [0, 1]:
+    for ind in [0,1]:
         areas = areasL[ind]
         delays = delaysL[ind]
         targets = freqsL[ind]
-        targets = [1000 / f for f in targets]
-
-        targets, delays, areas = noOutliers(
-            targets, delays, areas
-        )  # comment out to see all
-
+        targets = [1000/f for f in targets]
+        
+        targets, delays, areas = noOutliers(targets, delays, areas) # comment out to see all 
+        
         if not ind:
             achievedDelays = delays
 
-        c = "blue" if ind else "green"
-        ax1.scatter(targets, delays, marker="^", color=c)
-        ax2.scatter(targets, areas, marker="s", color=c)
-
+        c = 'blue' if ind else 'green'
+        ax1.scatter(targets, delays, marker='^', color=c)
+        ax2.scatter(targets, areas, marker='s', color=c)
+    
     bestAchieved = min(achievedDelays)
+        
+    legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='^', label='delay (timing achieved)'),
+                       lines.Line2D([0], [0], color='green', ls='', marker='s', label='area (timing achieved)'),
+                       lines.Line2D([0], [0], color='blue', ls='', marker='^', label='delay (timing violated)'),
+                       lines.Line2D([0], [0], color='blue', ls='', marker='s', label='area (timing violated)')]
 
-    legend_elements = [
-        lines.Line2D(
-            [0], [0], color="green", ls="", marker="^", label="delay (timing achieved)"
-        ),
-        lines.Line2D(
-            [0], [0], color="green", ls="", marker="s", label="area (timing achieved)"
-        ),
-        lines.Line2D(
-            [0], [0], color="blue", ls="", marker="^", label="delay (timing violated)"
-        ),
-        lines.Line2D(
-            [0], [0], color="blue", ls="", marker="s", label="area (timing violated)"
-        ),
-    ]
-
-    ax2.legend(handles=legend_elements, loc="upper left")
-
+    ax2.legend(handles=legend_elements, loc='upper left')
+    
     ax1.set_xlabel("Delay Targeted (ns)")
     ax1.set_ylabel("Delay Achieved (ns)")
-    ax2.set_ylabel("Area (sq microns)")
-    ax1.set_title(mod + "_" + str(width))
+    ax2.set_ylabel('Area (sq microns)')
+    ax1.set_title(mod + '_' + str(width))
 
     squarify(f)
 
     xvals = np.array(ax1.get_xlim())
-    frac = (min(flatten(delaysL)) - xvals[0]) / (xvals[1] - xvals[0])
-    areaLowerLim = min(flatten(areasL)) - 100
-    areaUpperLim = max(flatten(areasL)) / frac + areaLowerLim
+    frac = (min(flatten(delaysL))-xvals[0])/(xvals[1]-xvals[0])
+    areaLowerLim = min(flatten(areasL))-100
+    areaUpperLim = max(flatten(areasL))/frac + areaLowerLim
     ax2.set_ylim([areaLowerLim, areaUpperLim])
     ax1.plot(xvals, xvals, ls="--", c=".3")
-    ax1.hlines(y=bestAchieved, xmin=xvals[0], xmax=xvals[1], color="black", ls="--")
+    ax1.hlines(y=bestAchieved, xmin=xvals[0], xmax=xvals[1], color="black", ls='--')
 
-    plt.savefig("./plots/squareareadelay_" + mod + "_" + str(width) + ".png")
+    plt.savefig('./plots/squareareadelay_' + mod + '_' + str(width) + '.png')
     # plt.show()
 
-
 def squarify(fig):
-    """helper function for squareAreaDelay()
-    forces matplotlib figure to be a square
-    """
+    ''' helper function for squareAreaDelay()
+        forces matplotlib figure to be a square
+    '''
     w, h = fig.get_size_inches()
     if w > h:
         t = fig.subplotpars.top
         b = fig.subplotpars.bottom
-        axs = h * (t - b)
-        l = (1.0 - axs / w) / 2
-        fig.subplots_adjust(left=l, right=1 - l)
+        axs = h*(t-b)
+        l = (1.-axs/w)/2
+        fig.subplots_adjust(left=l, right=1-l)
     else:
         t = fig.subplotpars.right
         b = fig.subplotpars.left
-        axs = w * (t - b)
-        l = (1.0 - axs / h) / 2
-        fig.subplots_adjust(bottom=l, top=1 - l)
-
+        axs = w*(t-b)
+        l = (1.-axs/h)/2
+        fig.subplots_adjust(bottom=l, top=1-l)
 
 def plotPPA(mod, freq=None, norm=True, aleOpt=False):
-    """for the module specified, plots width vs delay, area, leakage power, and dynamic energy with fits
-    if no freq specified, uses the synthesis with best achievable delay for each width
-    overlays data from both techs
-    """
-    with mpl.rc_context({"figure.figsize": (7, 3.46)}):
+    ''' for the module specified, plots width vs delay, area, leakage power, and dynamic energy with fits
+        if no freq specified, uses the synthesis with best achievable delay for each width
+        overlays data from both techs
+    '''
+    with mpl.rc_context({"figure.figsize": (7,3.46)}):
         fig, axs = plt.subplots(2, 2)
 
-    arr = [["delay", "area"], ["lpower", "denergy"]]
+    arr = [['delay', 'area'], ['lpower', 'denergy']]
 
     freqs = [freq]
-    if aleOpt:
-        freqs += [10]
+    if aleOpt: freqs += [10]
 
     for i in [0, 1]:
         for j in [0, 1]:
             leg = []
             for f in freqs:
-                if (arr[i][j] == "delay") and (f == 10):
+                if (arr[i][j]=='delay') and (f==10):
                     pass
                 else:
-                    # print(f"Pasing in widths {widths}")
-                    r2 = oneMetricPlot(
-                        mod, widths, arr[i][j], ax=axs[i, j], freq=f, norm=norm
-                    )
-                    ls = "--" if f else "-"
-                    leg += [
-                        lines.Line2D(
-                            [0],
-                            [0],
-                            color="orange",
-                            label="$R^2$=" + str(round(r2, 4)),
-                            linestyle=ls,
-                        )
-                    ]
+                    r2 = oneMetricPlot(mod, arr[i][j], ax=axs[i, j], freq=f, norm=norm)
+                    ls = '--' if f else '-'
+                    leg += [lines.Line2D([0], [0], color='red', label='$R^2$='+str(round(r2, 4)), linestyle=ls)]
 
-            if (mod in ["flop", "csa"]) & (arr[i][j] == "delay"):
+            if (mod in ['flop', 'csa']) & (arr[i][j] == 'delay'):
                 axs[i, j].set_ylim(ymin=0)
                 ytop = axs[i, j].get_ylim()[1]
-                axs[i, j].set_ylim(ymax=1.1 * ytop)
+                axs[i, j].set_ylim(ymax=1.1*ytop)
             else:
                 axs[i, j].legend(handles=leg, handlelength=1.5)
-
-    titleStr = f"  (target {freq} MHz)" if freq is not None else ""
+    
+    titleStr = "  (target  " + str(freq)+ "MHz)" if freq != None else ""
     plt.suptitle(mod + titleStr)
-    plt.tight_layout(pad=0.05, w_pad=1, h_pad=0.5, rect=(0, 0, 1, 0.97))
+    plt.tight_layout(pad=0.05, w_pad=1, h_pad=0.5, rect=(0,0,1,0.97))
 
-    if freq != 10:
-        n = "normalized" if norm else "unnormalized"
-        saveStr = "./plots/" + n + "/" + mod + "_" + ".png"
-        print(f"Saving to {saveStr}")
+    if freq != 10: 
+        n = 'normalized' if norm else 'unnormalized'
+        saveStr = './plots/'+ n + '/' + mod + '.png'
         plt.savefig(saveStr)
     # plt.show()
 
-
 def makeLineLegend():
-    """generates legend to accompany normalized plots"""
-    plt.rcParams["figure.figsize"] = (5.5, 0.3)
+    ''' generates legend to accompany normalized plots
+    '''
+    plt.rcParams["figure.figsize"] = (5.5,0.3)
     fig = plt.figure()
-    fullLeg = [lines.Line2D([0], [0], color="black", label="fastest", linestyle="-")]
-    fullLeg += [lines.Line2D([0], [0], color="black", label="smallest", linestyle="--")]
-    fullLeg += [lines.Line2D([0], [0], color="blue", label="tsmc28", marker="^")]
-    fullLeg += [lines.Line2D([0], [0], color="blue", label="tsmc28psyn", marker="x")]
-    fullLeg += [lines.Line2D([0], [0], color="green", label="sky90", marker="o")]
-    fullLeg += [lines.Line2D([0], [0], color="purple", label="sky130", marker="+")]
-    fullLeg += [lines.Line2D([0], [0], color="orange", label="combined", marker="_")]
-    fig.legend(handles=fullLeg, ncol=5, handlelength=1.4, loc="center")
-    saveStr = "./plots/legend.png"
+    fullLeg = [lines.Line2D([0], [0], color='black', label='fastest', linestyle='-')]
+    fullLeg += [lines.Line2D([0], [0], color='black', label='smallest', linestyle='--')]
+    fullLeg += [lines.Line2D([0], [0], color='blue', label='tsmc28', marker='^')]
+    fullLeg += [lines.Line2D([0], [0], color='green', label='sky90', marker='o')]
+    fullLeg += [lines.Line2D([0], [0], color='red', label='combined', marker='_')]
+    fig.legend(handles=fullLeg, ncol=5, handlelength=1.4, loc='center') 
+    saveStr = './plots/legend.png'
     plt.savefig(saveStr)
 
-
-def muxPlot(fits="clsgn", norm=True):
-    """module: string module name
-    freq: int freq (MHz)
-    var: string delay, area, lpower, or denergy
-    fits: constant, linear, square, log2, Nlog2
-    plots given variable vs width for all matching syntheses with regression
-    """
+def muxPlot(fits='clsgn', norm=True):
+    ''' module: string module name
+        freq: int freq (MHz)
+        var: string delay, area, lpower, or denergy
+        fits: constant, linear, square, log2, Nlog2
+        plots given variable vs width for all matching syntheses with regression
+    '''
     ax = plt.gca()
 
     inputs = [2, 4, 8]
-    allInputs = inputs * 2
+    allInputs = inputs*2
     fullLeg = []
 
-    for crit in ["data", "control"]:
+    for crit in ['data', 'control']:
         allMetrics = []
-        muxes = ["mux2", "mux4", "mux8"]
+        muxes = ['mux2', 'mux4', 'mux8']
 
-        if crit == "data":
-            ls = "--"
-            muxes = [m + "d" for m in muxes]
-        elif crit == "control":
-            ls = "-"
+        if crit == 'data':
+            ls = '--'
+            muxes = [m + 'd' for m in muxes]
+        elif crit == 'control':
+            ls = '-'
 
         for spec in techSpecs:
             metric = []
             for module in muxes:
-                metric += getVals(spec.tech, module, "delay", width=[1])
-
+                metric += getVals(spec.tech, module, 'delay', width=[1])
+            
             if norm:
                 techdict = spec._asdict()
-                norm = techdict["delay"]
-                metric = [m / norm for m in metric]
+                norm = techdict['delay']
+                metric = [m/norm for m in metric]
                 # print(spec.tech, ' ', metric)
 
-            if (
-                len(metric) == 3
-            ):  # don't include the spec if we don't have points for all
+            if len(metric) == 3: # don't include the spec if we don't have points for all
                 xp, pred, coefs, r2 = regress(inputs, metric, fits, ale=False)
                 ax.scatter(inputs, metric, color=spec.color, marker=spec.shape)
                 ax.plot(xp, pred, color=spec.color, linestyle=ls)
                 allMetrics += metric
 
         xp, pred, coefs, r2 = regress(allInputs, allMetrics, fits)
-        ax.plot(xp, pred, color="red", linestyle=ls)
-        fullLeg += [lines.Line2D([0], [0], color="red", label=crit, linestyle=ls)]
-
-    ax.set_ylabel("Delay (FO4)")
+        ax.plot(xp, pred, color='red', linestyle=ls)
+        fullLeg += [lines.Line2D([0], [0], color='red', label=crit, linestyle=ls)]
+    
+    ax.set_ylabel('Delay (FO4)')
     ax.set_xticks(inputs)
     ax.set_xlabel("Number of inputs")
-    ax.set_title("mux timing")
-
-    ax.legend(handles=fullLeg)
-    plt.savefig("./plots/mux.png")
-
+    ax.set_title('mux timing')
+    
+    ax.legend(handles = fullLeg)
+    plt.savefig('./plots/mux.png')
 
 def stdDevError():
-    """calculates std deviation and error for paper-writing purposes"""
-    for var in ["delay", "area", "lpower", "denergy"]:
+    ''' calculates std deviation and error for paper-writing purposes
+    '''
+    for var in ['delay', 'area', 'lpower', 'denergy']:
         errlist = []
         for module in modules:
-            ale = var != "delay"
+            ale = (var != 'delay')
             metL = []
             modFit = fitDict[module]
             fits = modFit[ale]
@@ -799,17 +638,20 @@ def stdDevError():
                 metric = getVals(spec.tech, module, var)
                 techdict = spec._asdict()
                 norm = techdict[var]
-                metL += [m / norm for m in metric]
+                metL += [m/norm for m in metric]
 
-            ws = [w / normAddWidth for w in widths] if ale else widths
-            ws = ws * 2
+            if ale:
+                ws = [w/normAddWidth for w in widths]
+            else:
+                ws = widths
+            ws = ws*2
             mat = []
             for w in ws:
                 row = []
                 for func in funcArr:
                     row += [func(w)]
                 mat += [row]
-
+            
             y = np.array(metL, dtype=np.float)
             coefs = opt.nnls(mat, y)[0]
 
@@ -818,83 +660,66 @@ def stdDevError():
                 n = [func(w) for func in funcArr]
                 yp += [sum(np.multiply(coefs, n))]
 
-            if (var == "delay") & (module == "flop"):
+            if (var == 'delay') & (module == 'flop'):
                 pass
-            elif (module == "mult") & ale:
+            elif (module == 'mult') & ale:
                 pass
             else:
                 for i in range(len(y)):
-                    errlist += [abs(y[i] / yp[i] - 1)]
+                    errlist += [abs(y[i]/yp[i]-1)]
                 # print(module, ' ', var, ' ', np.mean(errlist[-10:]))
-
+            
         avgErr = np.mean(errlist)
         stdv = np.std(errlist)
 
-        print(var, " ", avgErr, " ", stdv)
-
+        print(var, ' ', avgErr, ' ', stdv)
 
 def makePlotDirectory():
-    """creates plots directory in same level as this script to store plots in"""
+    ''' creates plots directory in same level as this script to store plots in
+    '''
     current_directory = os.getcwd()
-    final_directory = os.path.join(current_directory, "plots")
+    final_directory = os.path.join(current_directory, 'plots')
     if not os.path.exists(final_directory):
         os.makedirs(final_directory)
     os.chdir(final_directory)
 
-    for folder in ["freqBuckshot", "normalized", "unnormalized"]:
+    for folder in ['freqBuckshot', 'normalized', 'unnormalized']:
         new_directory = os.path.join(final_directory, folder)
         if not os.path.exists(new_directory):
             os.makedirs(new_directory)
         os.chdir(new_directory)
-        if "freq" in folder:
-            for tech in ["sky90", "sky130", "tsmc28", "tsmc28psyn"]:
+        if 'freq' in folder:
+            for tech in ['sky90', 'tsmc28']:
                 for mod in modules:
                     tech_directory = os.path.join(new_directory, tech)
                     mod_directory = os.path.join(tech_directory, mod)
                     if not os.path.exists(mod_directory):
                         os.makedirs(mod_directory)
-                os.chdir("..")
-
+                os.chdir('..')
+    
     os.chdir(current_directory)
-
-
-if __name__ == "__main__":
+    
+if __name__ == '__main__':
     ##############################
     # set up stuff, global variables
     widths = [8, 16, 32, 64, 128]
-    modules = ["adder"]
+    modules = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mux2', 'mux4', 'mux8', 'mult'] #, 'mux2d', 'mux4d', 'mux8d']
+    normAddWidth = 32 # divisor to use with N since normalizing to add_32
 
-    normAddWidth = 32  # divisor to use with N since normalizing to add_32
-
-    fitDict = {
-        "adder": ["cg", "l", "l"],
-        "mul": ["cg", "s", "s"],
-        "comparator": ["cg", "l", "l"],
-        "csa": ["c", "l", "l"],
-        "shifter": ["cg", "l", "ln"],
-        "flop": ["c", "l", "l"],
-        "binencoder": ["cg", "l", "l"],
-    }
-    fitDict.update({key: ["cg", "l", "l"] for key in ["mux2", "mux4", "mux8"]})
+    fitDict = {'add': ['cg', 'l', 'l'], 'mult': ['cg', 's', 's'], 'comparator': ['cg', 'l', 'l'], 'csa': ['c', 'l', 'l'], 'shiftleft': ['cg', 'l', 'ln'], 'flop': ['c', 'l', 'l'], 'priorityencoder': ['cg', 'l', 'l']}
+    fitDict.update(dict.fromkeys(['mux2', 'mux4', 'mux8'], ['cg', 'l', 'l']))
 
     TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy")
-    # FO4 delay information information
-    techSpecs = [
-        #["sky90", "green", "o", 43.2e-3, 1440.600027, 714.057, 0.658022690438],
-        # Area/Lpower/Denergy needs to be corrected here (jes)
-        ["sky130", "orange", "o", 99.5e-3, 1440.600027, 714.057, 0.658022690438],
-        # ["tsmc28", "blue", "^", 12.2e-3, 209.286002, 1060.0, 0.08153281695882594],
-        # ["tsmc28psyn", "blue", "^", 12.2e-3, 209.286002, 1060.0, 0.08153281695882594],
-    ]
+    techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1440.600027, 714.057, 0.658022690438],  ['tsmc28', 'blue', '^', 12.2e-3, 209.286002, 1060.0, .08153281695882594]]
     techSpecs = [TechSpec(*t) for t in techSpecs]
-    combined = TechSpec("combined fit", "red", "_", 0, 0, 0, 0)
+    combined = TechSpec('combined fit', 'red', '_', 0, 0, 0, 0)
     ##############################
 
     # cleanup() # run to remove garbage synth runs
-    synthsintocsv()  # slow, run only when new synth runs to add to csv
-
-    allSynths = synthsfromcsv("ppaData.csv")  # your csv here!
-    bestSynths = csvOfBest("bestSynths.csv")
+    synthsintocsv() # slow, run only when new synth runs to add to csv
+  
+    allSynths = synthsfromcsv('ppaData.csv') # your csv here!
+    bestSynths = csvOfBest('bestSynths.csv')
     makePlotDirectory()
 
     # ### other functions
@@ -905,10 +730,8 @@ if __name__ == "__main__":
 
     for mod in modules:
         for w in widths:
-            #freqPlot('sky90', mod, w)
-            freqPlot("sky130", mod, w)
-            # freqPlot('tsmc28', mod, w)
-            # freqPlot('tsmc28psyn', mod, w)
-            plotPPA(mod, norm=False)
-            plotPPA(mod, aleOpt=True)
-            plt.close("all")
+            freqPlot('sky90', mod, w)
+            freqPlot('tsmc28', mod, w)
+        plotPPA(mod, norm=False)
+        plotPPA(mod, aleOpt=True)
+        plt.close('all')
\ No newline at end of file
diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py
index a730b1736..cbfd52538 100755
--- a/synthDC/ppa/ppaSynth.py
+++ b/synthDC/ppa/ppaSynth.py
@@ -1,32 +1,26 @@
-#!/usr/bin/env python3
-#
-# Python regression test for DC
-# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22
-# James Stine james.stine@okstate.edu 15 October 2023
-#
+#!/usr/bin/python3
+# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22
 
-import re
 import subprocess
+import re
 from multiprocessing import Pool
-
 from ppaAnalyze import synthsfromcsv
 
-
 def runCommand(module, width, tech, freq):
-    command = f"make synth DESIGN={module} WIDTH={width} TECH={tech} DRIVE=INV FREQ={freq} MAXOPT=1 MAXCORES=1"
-    subprocess.call(command, shell=True)
+    command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1".format(module, width, tech, freq)
+    subprocess.Popen(command, shell=True)
 
 def deleteRedundant(synthsToRun):
     '''removes any previous runs for the current synthesis specifications'''
-    synthStr = "rm -rf runs/{}_{}_rv32e_{}_{}_*"
+    synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*"
     for synth in synthsToRun:   
         bashCommand = synthStr.format(*synth)
-        subprocess.check_output(['bash','-c', bashCommand])
+        outputCPL = subprocess.check_output(['bash','-c', bashCommand])
 
 def freqSweep(module, width, tech):
     synthsToRun = []
     arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
-    allSynths = synthsfromcsv('ppa/bestSynths.csv')
+    allSynths = synthsfromcsv('bestSynths.csv')
     for synth in allSynths:
         if (synth.module == module) & (synth.tech == tech) & (synth.width == width):
             f = 1000/synth.delay
@@ -34,21 +28,8 @@ def freqSweep(module, width, tech):
                 synthsToRun += [[synth.module, str(synth.width), synth.tech, str(freq)]]
     return synthsToRun
 
-def freqModuleSweep(widths, modules, tech):
-    synthsToRun = []
-    arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8]
-    allSynths = synthsfromcsv('ppa/bestSynths.csv')
-    for w in widths:
-        for module in modules:
-            for synth in allSynths:
-                if (synth.module == str(module)) & (synth.tech == tech) & (synth.width == w):
-                    f = 1000/synth.delay
-                    for freq in [round(f+f*x/100) for x in arr]:
-                        synthsToRun += [[synth.module, str(synth.width), synth.tech, str(freq)]]
-    return synthsToRun
-
 def filterRedundant(synthsToRun):
-    bashCommand = "find . -path '*runs/*' -prune"
+    bashCommand = "find . -path '*runs/ppa*rv32e*' -prune"
     output = subprocess.check_output(['bash','-c', bashCommand])
     specReg = re.compile('[a-zA-Z0-9]+')
     allSynths = output.decode("utf-8").split('\n')[:-1]
@@ -72,30 +53,21 @@ def allCombos(widths, modules, techs, freqs):
 
 if __name__ == '__main__':
     
-    ##### Run specific syntheses for a specific frequency
+    ##### Run specific syntheses
     widths = [8, 16, 32, 64, 128] 
-    modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8']
-    techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn']
+    modules = ['mult', 'add', 'shiftleft', 'flop', 'comparator', 'priorityencoder', 'add', 'csa', 'mux2', 'mux4', 'mux8']
+    techs = ['sky90', 'tsmc28']
     freqs = [5000]
     synthsToRun = allCombos(widths, modules, techs, freqs)
     
     ##### Run a sweep based on best delay found in existing syntheses
-    module = 'adder'
+    module = 'add'
     width = 32
-    tech = 'tsmc28psyn'
+    tech = 'sky90'
     synthsToRun = freqSweep(module, width, tech)
-
-    ##### Run a sweep for multiple modules/widths based on best delay found in existing syntheses
-    modules = ['adder']
-#	widths = [8, 16, 32, 64, 128]
-    widths = [32]
-    tech = 'sky130'
-    synthsToRun = freqModuleSweep(widths, modules, tech)	
         
     ##### Only do syntheses for which a run doesn't already exist
-    synthsToRun = filterRedundant(synthsToRun)	
-    pool = Pool(processes=25)
+    synthsToRun = filterRedundant(synthsToRun)
 
-pool.starmap(runCommand, synthsToRun)
-pool.close()
-pool.join()
+    pool = Pool(processes=25)
+    pool.starmap(print, synthsToRun)
\ No newline at end of file
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 53f1645f4..ed43a1ab3 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -12,36 +12,28 @@ suppress_message {VER-130}
 # statements in initial blocks are ignored
 suppress_message {VER-281} 
 suppress_message {VER-173} 
- # Unsupported system task '$warn'
-suppress_message {VER-274}
-# Disable Warning:  Little argument or return value checking implemented for system task or function '$readmemh'. (VER-209)
-suppress_message {VER-209}
 
 # Enable Multicore
 set_host_options -max_cores $::env(MAXCORES)
 
-# get outputDir and configDir from environment (Makefile)
+# get outputDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
-set cfg $::env(CONFIGDIR)
-set hdl_src "../src"
+set cfgName $::env(CONFIG)
+# Config
+set hdl_src "../pipelined/src"
+set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
-set width $::env(WIDTH)
 
-eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
-eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
+eval file copy -force ${cfg} {$outputDir/hdl/}
+#eval file copy -force ${cfg} $outputDir
+eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
-eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
+eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
 
-# Check if a wrapper is needed and create it (to pass parameters when cvw_t parameters are used)
-set wrapper 0
-if {[catch {eval exec grep "cvw_t" $outputDir/hdl/$::env(DESIGN).sv}] == 0} {
-    echo "Creating wrapper"
-    set wrapper 1
-    # make the wrapper
-	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN) $outputDir/hdl
-}
+# Only for FMA class project; comment out when done
+# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
 
 # Enables name mapping
 if { $saifpower == 1 } {
@@ -49,15 +41,10 @@ if { $saifpower == 1 } {
 }
 
 # Verilog files
-set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
+set my_verilog_files [glob $outputDir/hdl/*]
 
 # Set toplevel
-if { $wrapper == 1 } {
-    set my_toplevel $::env(DESIGN)wrapper
-} else {
-    set my_toplevel $::env(DESIGN)
-}
-set my_design $::env(DESIGN)
+set my_toplevel $::env(DESIGN)
 
 # Set number of significant digits
 set report_default_significant_digits 6
@@ -66,37 +53,13 @@ set report_default_significant_digits 6
 set verilogout_show_unconnected_pins "true"
 set vhdlout_show_unconnected_pins "true"
 
-#  Set up MW List
-set MY_LIB_NAME $my_toplevel
-# Create MW
-if { [shell_is_in_topographical_mode] } {
-    echo "In Topographical Mode...processing\n"
-    create_mw_lib  -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \
-        -mw_reference_library $mw_reference_library $outputDir/$MY_LIB_NAME
-    # Open MW
-    open_mw_lib $outputDir/$MY_LIB_NAME
-    
-    # TLU+
-    set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \
-	-tech2itf_map $PRS_MAP_FILE
-
-} else {
-    echo "In normal DC mode...processing\n"
-}
-
 # Due to parameterized Verilog must use analyze/elaborate and not 
 # read_verilog/vhdl (change to pull in Verilog and/or VHDL)
 #
 #set alib_library_analysis_path ./$outputDir
 define_design_lib WORK -path ./$outputDir/WORK
 analyze -f sverilog -lib WORK $my_verilog_files
-# If wrapper=0, we want to run against a specific module and pass
-# width to DC
-if { $wrapper == 1 } {
-    elaborate $my_toplevel -lib WORK 
-} else {
-    elaborate $my_toplevel -lib WORK -parameters WIDTH=$width
-}
+elaborate $my_toplevel -lib WORK 
 
 # Set the current_design 
 current_design $my_toplevel
@@ -115,7 +78,6 @@ if { $saifpower == 1 } {
 if {$drive != "INV"} {
     set_false_path -from [get_ports reset]
 }
-# for PPA multiplexer synthesis
 if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} {
     set_false_path -from {s}
 }
@@ -133,15 +95,14 @@ if {  $find_clock != [list] } {
     set my_clk $my_clock_pin
     create_clock -period $my_period $my_clk
     set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
- } else {
+} else {
     echo "Did not find clock! Design is probably combinational!"
     set my_clk vclk
     create_clock -period $my_period -name $my_clk
 }
 
-
 # Optimize paths that are close to critical
-set_critical_range 0.05 $current_design
+set_critical_range [expr $my_period*0.05] $current_design
 
 # Partitioning - flatten or hierarchically synthesize
 if { $maxopt == 1 } {
@@ -158,29 +119,25 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
 
 # Setting constraints on input ports 
 if {$tech == "sky130"} {
-    if {$drive == "INV"} {
-	    set_driving_cell -lib_cell inv -pin Y $all_in_ex_clk
-    } elseif {$drive == "FLOP"} {
-	    set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
-    }
+    set_driving_cell  -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
 } elseif {$tech == "sky90"} {
     if {$drive == "INV"} {
-	    set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
+	set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
     } elseif {$drive == "FLOP"} {
-	    set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
+	set_driving_cell  -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
     }
-} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} {
+} elseif {$tech == "tsmc28"} {
     if {$drive == "INV"} {
-	    set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
+	set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
     } elseif {$drive == "FLOP"} {
-        set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
+    set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
     }
 }
 
 # Set input/output delay
 if {$drive == "FLOP"} {
-    set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
-    set_output_delay 0.0 -max -clock $my_clk [all_outputs]
+    set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk
+    set_output_delay 0.1 -max -clock $my_clk [all_outputs]
 } else {
     set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk
     set_output_delay 0.0 -max -clock $my_clk [all_outputs]
@@ -188,29 +145,23 @@ if {$drive == "FLOP"} {
 
 # Setting load constraint on output ports 
 if {$tech == "sky130"} {
+    set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
+} elseif {$tech == "sky90"} {
     if {$drive == "INV"} {
-	    set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__inv_4/A] * 1] [all_outputs]
-    } elseif {$drive == "FLOP"} {
-        set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
-    }
- } elseif {$tech == "sky90"} {
-    if {$drive == "INV"} {
-	    set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
+	set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
     } elseif {$drive == "FLOP"} {
         set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
     }
-} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
+} elseif {$tech == "tsmc28"} {
     if {$drive == "INV"} {
-	    set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
+	set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
     } elseif {$drive == "FLOP"} {
         set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs]
     }
 }
 
-if {$tech != "tsmc28psyn"} {
-    # Set the wire load model 
-    set_wire_load_mode "top"
-}
+# Set the wire load model 
+set_wire_load_mode "top"
 
 # Set switching activities
 # default activity factors are 1 for clocks, 0.1 for others
@@ -259,71 +210,44 @@ set write_rep  1	;# generates estimated area and timing report
 set write_cst  1        ;# generate report of constraints
 set write_hier 1        ;# generate hierarchy report
 
-# Report on DESIGN, not wrapper.  However, design has a suffix for the parameters.
-if { $wrapper == 1 } {
-    set designname [format "%s%s" $my_design "__*"]
-    current_design $designname
-
-    # recreate clock below wrapper level or reporting doesn't work properly
-    set find_clock [ find port [list $my_clock_pin] ]
-    if {  $find_clock != [list] } {
-        echo "Found clock!"
-        set my_clk $my_clock_pin
-        create_clock -period $my_period $my_clk
-        set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
-    } else {
-        echo "Did not find clock! Design is probably combinational!"
-        set my_clk vclk
-        create_clock -period $my_period -name $my_clk
-    }
-} 
-
 # Report Constraint Violators
-set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"]
 redirect $filename {report_constraint -all_violators}
 
 # Check design
 redirect $outputDir/reports/check_design.rpt { check_design }
 
 # Report Final Netlist (Hierarchical)
-set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sv"]
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
 write_file -f verilog -hierarchy -output $filename
 
-set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdc"]
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
 write_sdc $filename
 
-set filename [format "%s%s%s%s" $outputDir  "/mapped/" $my_design ".ddc"]
+set filename [format "%s%s%s%s" $outputDir  "/mapped/" $my_toplevel ".ddc"]
 write_file -format ddc -hierarchy -o $filename
 
-set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
+set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
 write_sdf $filename
 
-# Write SPEF file in case need more precision power exploration for TSMC28psyn
-if {$tech == "tsmc28psyn"} {
-    set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".spef"]
-    redirect $filename { write_parasitics }
-}
-
 # QoR
-set filename [format "%s%s"  $outputDir "/reports/qor.rep"]
+set filename [format "%s%s%s%s"  $outputDir "/reports/" $my_toplevel "_qor.rep"]
 redirect $filename { report_qor }
 
 # Report Timing
-set filename [format "%s%s" $outputDir "/reports/reportpath.rep"]
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"]
 #redirect $filename { report_path_group }
 
-set filename [format "%s%s" $outputDir "/reports/report_clock.rep"]
+set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"]
 # redirect $filename { report_clock }
 
-set filename [format "%s%s" $outputDir  "/reports/timing.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_timing.rep"]
 redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 }
 
-set filename [format "%s%s" $outputDir  "/reports/mindelay.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mindelay.rep"]
 redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
 
-set filename [format "%s%s" $outputDir  "/reports/per_module_timing.rep"]
-redirect -append $filename { echo "\n\n\n//// Critical paths through Stall ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {Stall*} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_per_module_timing.rep"]
 redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
@@ -333,7 +257,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 redirect -append $filename { echo "\n\n\n//// Critical paths through ebu (ahblite) ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 } 
 redirect -append $filename { echo "\n\n\n//// Critical paths through mdu ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/*} -nworst 1 } 
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } 
 redirect -append $filename { echo "\n\n\n//// Critical paths through hzu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 } 
 redirect -append $filename { echo "\n\n\n//// Critical paths through priv ////\n\n\n" }
@@ -341,31 +265,31 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 redirect -append $filename { echo "\n\n\n//// Critical paths through fpu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 }
 
-set filename [format "%s%s" $outputDir  "/reports/mdu_timing.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mdu_timing.rep"]
 redirect -append $filename { echo "\n\n\n//// Critical paths through entire mdu ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/*} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through multiply unit ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.mul/*} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through redundant multiplier ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.mul/bigmul/*} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through ProdM (mul output) ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.ProdM} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through PP0E (mul partial product) ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.mul/PP0E} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through divide unit ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.div/*} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through QuotM (div output) ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.QuotM} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through RemM (div output) ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.RemM} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through div/WNextE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.div/WNextE} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through div/XQNextE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.div/XQNextE} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical path through div/DAbsBE ////\n\n\n" }
-redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu.mdu/genblk1.div/DAbsBE} -nworst 1 }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/fpu_timing.rep"]
+# set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
 # redirect $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
 # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 }
 # redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
@@ -373,87 +297,90 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets -
 # redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" }
 # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/ifu_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ifu_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical path through PCF ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through PCNextF ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through FinalInstrRawF ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through InstrD ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/stall_flush_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_stall_flush_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical path through StallD ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through StallE ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through StallM ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through StallW ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushD ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushE ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushM ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/ieu_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_ieu_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/fpu_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_fpu_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/mmu_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_mmu_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through dmmu/physicaladdress ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 }
 
-# set filename [format "%s%s%s%s" $outputDir  "/reports/priv_timing.rep"]
-# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
-# redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
-# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_priv_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/TrapM ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValM ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 }
+redirect -append $filename { echo "\n\n\n//// Critical paths through priv/CSRReadValW ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 }
 
-set filename [format "%s%s" $outputDir  "/reports/area.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_min_timing.rep"]
+redirect $filename { report_timing -delay min }
+
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_area.rep"]
 redirect $filename { report_area -hierarchy -nosplit -physical -designware}
 
-set filename [format "%s%s" $outputDir  "/reports/cell.rep"]
-#redirect $filename { report_cell [get_cells -hier *] }  # not too useful
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_cell.rep"]
+# redirect $filename { report_cell [get_cells -hier *] }
 
-set filename [format "%s%s" $outputDir  "/reports/power.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_power.rep"]
 redirect $filename { report_power -hierarchy -levels 1 }
 
-set filename [format "%s%s" $outputDir  "/reports/constraint.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_constraint.rep"]
 redirect $filename { report_constraint }
 
-set filename [format "%s%s" $outputDir  "/reports/hier.rep"]
+set filename [format "%s%s%s%s" $outputDir  "/reports/" $my_toplevel "_hier.rep"]
 # redirect $filename { report_hierarchy }
 
 # end run clock and echo run time in minutes
diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py
deleted file mode 100755
index 7cc406369..000000000
--- a/synthDC/scripts/wrapperGen.py
+++ /dev/null
@@ -1,66 +0,0 @@
-#!/usr/bin/env python3
-"""
-wrapperGen.py
-
-kekim@hmc.edu
-
-script that generates top-level wrappers for verilog modules to synthesize
-"""
-
-import argparse
-import glob
-import os
-
-#create argument parser
-parser = argparse.ArgumentParser()
-
-parser.add_argument("DESIGN")
-parser.add_argument("HDLPATH")
-
-args=parser.parse_args()
-
-fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0]
-
-with open(fin_path) as fin:
-    lines = fin.readlines()
-
-    # keeps track of what line number the module header begins
-    lineModuleStart = 0
-
-    # keeps track of what line number the module header ends
-    lineModuleEnd = 0
-
-    # keeps track of module name
-    moduleName = ""
-
-    # string that will keep track of the running module header
-    buf = 'import cvw::*;\n`include "config.vh"\n`include "parameter-defs.vh"\n'
-
-    # are we writing into the buffer
-    writeBuf=False
-
-    index=0
-
-    # string copy logic
-    for l in lines:
-        if l.lstrip().find("module") == 0:
-            lineModuleStart = index
-            moduleName = l.split()[1]
-            writeBuf = True
-            buf += f"module {moduleName}wrapper (\n"
-            continue
-        if (writeBuf):
-            buf += l
-        if l.lstrip().find (");") == 0:
-            lineModuleEnd = index
-            break
-        index+=1
-
-    # post-processing buffer: add DUT and endmodule lines
-    buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
-
-    # path to wrapper
-    wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
-
-    with open(wrapperPath, "w") as fout:
-        fout.write(buf)
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 1e8e1a66e..0c1579813 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -1,68 +1,64 @@
-#!/usr/bin/env python3
-# Madeleine Masser-Frye mmasserfrye@hmc.edu 1/2023
+#!/usr/bin/python3
+# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22
 
-import argparse
 import subprocess
 from multiprocessing import Pool
+import argparse
 
-
-def runSynth(config, mod, tech, freq, maxopt, usesram):
+def runSynth(config, tech, freq, maxopt):
     global pool
-    prefix = "syn_sram_" if usesram else "syn_"
-    cfg = prefix + config
-    command = f"make synth DESIGN=wallypipelinedcore CONFIG={cfg} MOD={mod} TECH={tech} DRIVE=FLOP FREQ={freq} MAXOPT={maxopt} USESRAM={usesram} MAXCORES=1"
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt)
     pool.map(mask, [command])
 
 def mask(command):
     subprocess.Popen(command, shell=True)
 
+def freshStart():
+    out = subprocess.check_output(['bash','-c', 'make fresh'])
+    for x in out.decode("utf-8").split('\n')[:-1]:
+        print(x)
+    return
+
 
 if __name__ == '__main__':
     
-    techs = ['sky130', 'sky90', 'tsmc28', 'tsmc28psyn']
-    allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
+    techs = ['sky90', 'tsmc28']
+    allConfigs = ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e', 'rv32i', 'rv64i']
     freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
-#    freqVaryPct = [-20, -10, 0, 10, 20]
 
     pool = Pool()
 
     parser = argparse.ArgumentParser()
 
     parser.add_argument("-s", "--freqsweep", type=int, help = "Synthesize wally with target frequencies at given MHz and +/- 2, 4, 6, 8 %%")
-    parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32imc, 64ic, 32gc, and 64gc")
+    parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32ic, 64ic, 32gc, and 64gc")
     parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path")
 
     parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally")
     parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy")
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
-    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules")
 
     args = parser.parse_args()
 
+    freq = args.targetfreq if args.targetfreq else 3000
     tech = args.tech if args.tech else 'sky90'
     maxopt = int(args.maxopt)
-    usesram = int(args.usesram)
-    mod = 'orig'
 
     if args.freqsweep:
         sc = args.freqsweep
         config = args.version if args.version else 'rv32e'
+        freshStart()
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
-            runSynth(config, mod, tech, freq, maxopt, usesram)
-    elif args.configsweep:
-        defaultfreq = 1500 if tech == 'sky90' else 5000
-        freq = args.targetfreq if args.targetfreq else defaultfreq
-        for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
-            runSynth(config, mod, tech, freq, maxopt, usesram)
-    elif args.featuresweep:
-        defaultfreq = 500 if tech == 'sky90' else 1500
-        freq = args.targetfreq if args.targetfreq else defaultfreq
-        config = args.version if args.version else 'rv64gc'
-        for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'pmp0']: 
-            runSynth(config, mod, tech, freq, maxopt, usesram)
-    else:
-        defaultfreq = 500 if tech == 'sky90' else 1500
-        freq = args.targetfreq if args.targetfreq else defaultfreq
-        config = args.version if args.version else 'rv64gc'
-        runSynth(config, mod, tech, freq, maxopt, usesram)
+            runSynth(config, tech, freq, maxopt)
+    if args.configsweep:
+        freshStart()
+        for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs
+            config = config + '_orig' # until memory integrated
+            runSynth(config, tech, freq, maxopt)
+    if args.featuresweep:
+        freshStart()
+        v = args.version if args.version else 'rv64gc'
+        for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations
+            config = v + '_' + mod
+            runSynth(config, tech, freq, maxopt)
diff --git a/synthDC/wallySynthAll.sh b/synthDC/wallySynthAll.sh
deleted file mode 100755
index f235c73e3..000000000
--- a/synthDC/wallySynthAll.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-# Run all Wally synthesis experiments from chapter 8
-# However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail
-# Adding the sleep gives them time to finish.
-./wallySynth.py --freqsweep 330 --tech sky130 
-sleep 300 
-./wallySynth.py --freqsweep 870 --tech sky90 
-sleep 300 
-./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
-sleep 300 
-
-# These jobs can run in parallel and take longer
-./wallySynth.py --configsweep --tech sky130 --targetfreq 330
-./wallySynth.py --configsweep --tech sky90 --targetfreq 870
-./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram
-./wallySynth.py --featuresweep --tech sky130 --targetfreq 330
-./wallySynth.py --featuresweep --tech sky90 --targetfreq 870
-./wallySynth.py --featuresweep --tech tsmc28psyn --targetfreq 2800 --usesram
-
-# Extract summary data (run this by hand after all experiments finish)
-./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800
-
diff --git a/testbench/Makefile b/testbench/Makefile
deleted file mode 100644
index 4af5e9c27..000000000
--- a/testbench/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# Makefile for testbench to create .memfile, .objdump.addr, and .objdump.lab from an ELF
-# David_Harris@hmc.edu 3 July 2024
-# james.stine@okstate.edu 24 Jan 2025
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# the width is set by the elf's type to allow for individual elf compilation
-%.memfile: %
-	@if grep -q 'elf32' $*.objdump; then \
-		BIT_WIDTH=32; \
-	else \
-		BIT_WIDTH=64; \
-	fi; \
-	echo "Processing $< with --bit-width $$BIT_WIDTH"; \
-	riscv64-unknown-elf-elf2hex --bit-width $$BIT_WIDTH --input $< --output $@
-
-%.objdump.addr: %.objdump
-	extractFunctionRadix.sh $<
-
-%.objdump: %
-	riscv64-unknown-elf-objdump -S -D $< > $@
diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv
deleted file mode 100644
index 5764ce26b..000000000
--- a/testbench/common/DCacheFlushFSM.sv
+++ /dev/null
@@ -1,151 +0,0 @@
-///////////////////////////////////////////
-// DCacheFlushFSM.sv
-//
-// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net
-// Modified: 14 June 2023
-//
-// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty
-//          line before the end of test.  Signature based regression tests need to check the L1 data cache
-//          in addition to the main memory.  These modules create a shadow memory with a projection of the
-//          D$ contents.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) 
-  (input logic clk,
-   input logic start,
-   output logic done);
-
-  genvar adr;
-
-  logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
-  logic         startD;
-  
-  if(P.DCACHE_SUPPORTED) begin
-    localparam numlines       = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS;
-    localparam numways        = P.DCACHE_NUMWAYS;
-    localparam linelen        = P.DCACHE_LINELENINBITS;
-    localparam linebytelen    = linelen/8;
-    localparam sramlen        = P.CACHE_SRAMLEN;
-    localparam cachesramwords = linelen/sramlen;
-    localparam numwords       = sramlen/P.XLEN;
-    localparam lognumlines    = $clog2(numlines);
-    localparam loglinebytelen = $clog2(linebytelen);
-    localparam lognumways     = $clog2(numways);
-    localparam tagstart       = lognumlines + loglinebytelen;
-    
-    genvar               index, way, cacheWord;
-    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [sramlen-1:0]  cacheline;
-    logic [P.XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [P.PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    for(index = 0; index < numlines; index++) begin
-      for(way = 0; way < numways; way++) begin
-        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
-          copyShadow #(.P(P), .tagstart(tagstart),
-          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
-          copyShadow(.clk,
-          .start,
-          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.ram.RAM[index][P.PA_BITS-1-tagstart:0]),
-          .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
-          .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
-                           // these dirty bit selections would be needed if dirty is moved inside the tag array.
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
-          //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.ram.RAM[index]),
-          .index(index),
-          .cacheWord(cacheWord),
-          .CacheData(CacheData[way][index][cacheWord]),
-          .CacheAdr(CacheAdr[way][index][cacheWord]),
-          .CacheTag(CacheTag[way][index][cacheWord]),
-          .CacheValid(CacheValid[way][index][cacheWord]),
-          .CacheDirty(CacheDirty[way][index][cacheWord]));
-        end
-      end
-    end
-
-    integer i, j, k, l;
-
-    always @(posedge clk) begin
-      if (startD) begin 
-        for(i = 0; i < numlines; i++) begin
-          for(j = 0; j < numways; j++) begin
-            for(l = 0; l < cachesramwords; l++) begin
-              if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
-                for(k = 0; k < numwords; k++) begin
-                  //cacheline = CacheData[j][i][0];
-                  // does not work with modelsim
-                  // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
-                  // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
-                  //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
-                  /* verilator lint_off WIDTHTRUNC */
-                  // avoid lint error: address trunc warning for shadowram index
-                  ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
-                  /* verilator lint_on WIDTHTRUNC */
-                end
-              end
-            end
-          end
-        end
-      end
-    end  
-  end
-  flop #(1) doneReg1(.clk, .d(start), .q(startD));
-  flop #(1) doneReg2(.clk, .d(startD), .q(done));
-endmodule
-
-module copyShadow import cvw::*; #(parameter cvw_t P,
-  parameter tagstart, loglinebytelen, sramlen)
-  (input  logic                       clk,
-   input  logic                       start,
-   input  logic [P.PA_BITS-1:tagstart] tag,
-   input  logic                       valid, dirty,
-   input  logic [sramlen-1:0]         data,
-   input  logic [32-1:0]              index,
-   input  logic [32-1:0]              cacheWord,
-   output logic [sramlen-1:0]         CacheData,
-   output logic [P.PA_BITS-1:0]        CacheAdr,
-   output logic [P.XLEN-1:0]           CacheTag,
-   output logic                       CacheValid,
-   output logic                       CacheDirty);
-
-  logic [P.XLEN+1:0]               TagExtend;
-  logic [P.XLEN+1:0]               IndexExtend;
-  logic [P.XLEN+1:0]               CacheWordExtend;
-  logic [P.XLEN+1:0]               CacheAdrExtend;
-  
-  assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)+2}{1'b0}}, tag};
-  assign IndexExtend = {{{P.XLEN-32+2}{1'b0}}, index};
-  assign CacheWordExtend = {{{P.XLEN-32+2}{1'b0}}, cacheWord};
-
-  always_ff @(posedge clk) begin
-    if(start) begin
-      CacheTag = TagExtend[P.XLEN-1:0];
-      CacheValid = valid;
-      CacheDirty = dirty;
-      CacheData = data;
-      CacheAdrExtend = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8));
-    end
-  end
-
-  assign CacheAdr = CacheAdrExtend[P.PA_BITS-1:0];
-  
-endmodule
diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv
deleted file mode 100644
index 141dcd88f..000000000
--- a/testbench/common/functionName.sv
+++ /dev/null
@@ -1,182 +0,0 @@
-///////////////////////////////////////////
-// functionName.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// 
-// Purpose: decode name of function
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module functionName import cvw::*; #(parameter cvw_t P) (
-  input logic reset,
-  input logic clk,
-  input string ProgramAddrMapFile,
-  input string ProgramLabelMapFile
-  );
-  
-  logic [P.XLEN-1:0] ProgramAddrMapMemory [logic [P.XLEN-1:0]];
-  string 	    ProgramLabelMapMemory [logic [P.XLEN-1:0]];
-  string 	    FunctionName;
-  
-
-  logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
-  logic 	    StallD, StallE, StallM, FlushD, FlushE, FlushM;
-  logic 		InstrValidM;
-  logic [P.XLEN-1:0] 	    ProgramAddrIndex, ProgramAddrIndexQ;
-
-  assign PCF = testbench.dut.core.ifu.PCF;
-  assign StallD = testbench.dut.core.StallD;
-  assign StallE = testbench.dut.core.StallE;  
-  assign StallM = testbench.dut.core.StallM;  
-  assign FlushD = testbench.dut.core.FlushD;
-  assign FlushE = testbench.dut.core.FlushE;
-  assign FlushM = testbench.dut.core.FlushM;
-  assign InstrValidM = testbench.dut.core.InstrValidM;
-
-  // copy from ifu
-  // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not
-  // erroneously change.
-  // also need to hold the old value not an erroneously fetched PC.
-  flopenr #(P.XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
-  flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
-  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
-  flopenr #(P.XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
-  assign PCM = InstrValidM ? PCM_temp : PCMOld;
-
-  task automatic bin_search_min;
-    input logic [P.XLEN-1:0] pc;
-    input logic [P.XLEN-1:0] length;
-    ref logic [P.XLEN-1:0]   array [logic [P.XLEN-1:0]];
-    output logic [P.XLEN-1:0] minval;
-    output     logic [P.XLEN-1:0] mid;
-
-    logic [P.XLEN-1:0] 	     left, right;
-
-    begin
-      if ( pc == 0 ) begin
-	// want to  keep the old value for mid and minval
-	mid = 0;
-	return;
-      end
-      left = 0;
-      right = length;
-      while (left <= right) begin
-	mid = left + ((right - left) / 2);
-	if (array[mid] == pc) begin
-	  minval = array[mid];
-	  return;
-        end
-	if (array[mid] < pc) begin
-	  left = mid + 1;
-	end else if( array[mid] > pc) begin
-	  right = mid -1;
-	end else begin
-	  //$display("Critical Error in FunctionName. PC, %x not found.", pc);
-	  return;
-	  //$stop();
-	end	  
-      end // while (left <= right)
-      // if the element pc is now found, right and left will be equal at this point.
-      // we need to check if pc is less than the array at left or greather.
-      // if it is less than pc, then we select left as the index.
-      // if it is greather we want 1 less than left.
-      if (array[left] < pc) begin
-	minval = array[left];
-	mid = left;      
-	return;	    
-      end else begin
-	minval = array[left-1];
-	mid = left - 1;	
-	return;
-      end
-    end
-  endtask // bin_search_min
-
-  integer ProgramAddrMapFP, ProgramLabelMapFP;
-  logic [P.XLEN-1:0] ProgramAddrMapLineCount;
-  logic [P.XLEN-1:0] ProgramLabelMapLineCount;
-  logic [P.XLEN-1:0] ProgramAddrMapLine;
-  string  ProgramLabelMapLine;
-  integer status;
-  
-
-  // preload
-//  initial begin
-  always @ (negedge reset) begin
-
-    // cannot readmemh directoy to a dynmaic array. Sad times :(
-    // Let's initialize a static array with FFFF_FFFF for all addresses.
-    // Then we can readmemh and finally copy to the dynamic array.
-    
-	// clear out the old mapping between programs.
-    ProgramAddrMapMemory.delete();
-    ProgramLabelMapMemory.delete();
-
-    // Unfortunately verilator version 5.011 readmemh does not support dynamic arrays
-    //$readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
-    // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
-
-    ProgramAddrMapLineCount = 0;
-    ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
-
-    // read line by line to count lines
-    if (ProgramAddrMapFP != 0) begin
-      while (! $feof(ProgramAddrMapFP)) begin
-	    status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine);
-        ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine;
-	    ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1;
-      end
-    end else begin
-      $display("Cannot open file %s for reading.", ProgramAddrMapFile);
-    end
-    $fclose(ProgramAddrMapFP);
-
-    // ProgramIndexFile maps the program name to the compile index.
-    // The compile index is then used to inditify the application
-    // in the custom radix.
-    // Build an associative array to convert the name to an index.
-    ProgramLabelMapLineCount = 0;
-    ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
-    
-    if (ProgramLabelMapFP != 0) begin
-      while (! $feof(ProgramLabelMapFP)) begin
-	status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine);
-	ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine;
-	ProgramLabelMapLineCount = ProgramLabelMapLineCount + 1;
-      end
-    end else begin
-      $display("Cannot open file %s for reading.", ProgramLabelMapFile);
-    end
-    $fclose(ProgramLabelMapFP);
-
-  end
-
-  always @(PCM) begin
-    bin_search_min(PCM, ProgramAddrMapLineCount, ProgramAddrMapMemory, FunctionAddr, ProgramAddrIndex);
-  end
-
-  logic OrReducedAdr, AnyUnknown;
-  assign OrReducedAdr = |ProgramAddrIndex;
-  assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0;
-  initial ProgramAddrIndex = 0;
-
-  always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
-
-endmodule // function_radix
-
diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
deleted file mode 100644
index cb180df6e..000000000
--- a/testbench/common/instrNameDecTB.sv
+++ /dev/null
@@ -1,439 +0,0 @@
-///////////////////////////////////////////
-// instrNameDecTB.sv
-//
-// Purpose: decode name of function
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// decode the instruction name, to help the test bench
-module instrNameDecTB #(parameter XLEN) (
-  input  logic [31:0] instr,
-  output string       name);
-
-  logic [6:0] op;
-  logic       funct1;
-  logic [1:0] funct2;
-  logic [2:0] funct3;
-  logic [4:0] funct5;
-  logic [6:0] funct7;
-  logic [11:0] imm;
-  logic [4:0] rs2, rd, CRrs2;
-  logic [1:0] compressedOp;
-  logic [5:0] compressed15_10;
-
-
-  assign op = instr[6:0];
-  assign funct1 = instr[6];
-  assign funct2 = instr[6:5];
-  assign funct3 = instr[14:12];
-  assign funct5 = instr[6:2];
-  assign funct7 = instr[31:25];
-  assign imm = instr[31:20];
-  assign rs2 = instr[24:20];
-  assign rd = instr[11:7];
-  assign compressedOp = instr[1:0];
-  assign compressed15_10 = instr[15:10];
-  assign CRrs2 = instr[6:2];
-
-  // it would be nice to add the operands to the name 
-  // create another variable called decoded
-
-  always_comb
-    case (compressedOp)
-      2'b00:
-        casez (compressed15_10)
-          6'b000???: if (instr[12:5] != 8'b0) name = "C.ADDI4SPN";
-                     else if(compressed15_10 == 6'b000000 & op == 7'b0000000 & funct3 == 3'b000) name = "BAD";
-          6'b010???: name = "C.LW";
-          6'b110???: name = "C.SW";
-          6'b011???: if (XLEN == 32'd32) name = "C.FLW";
-                     else name = "C.LD";
-          6'b111???: if (XLEN == 32'd32) name = "C.FSW";
-                     else name = "C.SD";
-          6'b100000: name = "C.LBU";
-          6'b100001: if (funct1 == 1'b1) name = "C.LH";
-                     else if (funct1 == 1'b0) name = "C.LHU";
-          6'b100010: name = "C.SB";
-          6'b100011: if (funct1 == 1'b0) name = "C.SH";
-          6'b001???: name = "C.FLD";
-          6'b101???: name = "C.FSD";
-          default: name = "ILLEGAL";
-        endcase
-      2'b01:
-        casez (compressed15_10)
-          6'b000???: if (instr[12:10] == 3'b0 & rd == 5'b00000 & instr[6:2] == 5'b00000) name = "C.NOP";
-                     else if (rd != 5'b00000 & instr[6:2] != 5'b00000) name = "C.ADDI";
-          6'b010???: if (rd != 5'b00000) name = "C.LI";
-          6'b011???: if (rd != 5'b00000 & rd != 5'b00010 & instr[6:2] != 5'b00000) name = "C.LUI";
-                     else if (rd == 5'b00010 & instr[6:2] != 5'b00000) name = "C.ADDI16SP";
-          6'b100?00: name = "C.SRLI";
-          6'b100?01: name = "C.SRAI";
-          6'b100?10: name = "C.ANDI";
-          6'b100011: if (funct2 == 2'b00) name = "C.SUB";
-                     else if (funct2 == 2'b01) name = "C.XOR";
-                     else if (funct2 == 2'b10) name = "C.OR";
-                     else if (funct2 == 2'b11) name = "C.AND";
-          6'b101???: name = "C.J";
-          6'b110???: name = "C.BEQZ";
-          6'b111???: name = "C.BNEZ";
-          6'b001???: if (XLEN == 32'd32) name = "C.JAL";
-                     else if (XLEN == 32'd64 & rd != 5'b00000) name = "C.ADDIW";
-          6'b100111: if (XLEN == 32'd64 & funct2 == 2'b00) name = "C.SUBW";
-                     else if (XLEN == 32'd64 & funct2 == 2'b01) name = "C.ADDW";
-                     else if (funct5 == 5'b11000) name = "C.ZEXT.B";
-                     else if (funct5 == 5'b11001) name = "C.SEXT.B";
-                     else if (funct5 == 5'b11010) name = "C.ZEXT.H";
-                     else if (funct5 == 5'b11011) name = "C.SEXT.H";
-                     else if (funct5 == 5'b11101) name = "C.NOT";
-                     else if (funct2 == 2'b10) name = "C.MUL";
-                     else if (funct5 == 5'b11100) name = "C.ZEXT.W";
-          default: name = "ILLEGAL";
-        endcase
-      2'b10:
-        casez (compressed15_10)
-          6'b000???: if (rd != 5'b00000) name = "C.SLLI";
-          6'b010???: if (rd != 5'b00000) name = "C.LWSP";
-          6'b1000??: if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JR";
-                     else if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.MV";
-          6'b1001??: if (rd == 5'b00000 & CRrs2 == 5'b00000 ) name = "C.EBREAK";
-                     else if (rd != 5'b00000 & CRrs2 == 5'b00000 ) name = "C.JALR";
-                     else if (rd != 5'b00000 & CRrs2 != 5'b00000 ) name = "C.ADD";
-          6'b110???: name = "C.SWSP";
-          6'b011???: if (XLEN == 32'd32) name = "C.FLWSP";
-                     else if (rd != 5'b00000) name = "C.LDSP";
-          6'b111???: if (XLEN == 32'd32) name = "C.FSWSP";
-                     else name = "C.SDSP";
-          6'b001???: name = "C.FLDSP";
-          6'b101???: name = "C.FSDSP";
-          default: name = "ILLEGAL";
-        endcase
-      2'b11:
-        casez({op, funct3})
-          10'b0000011_000: name = "LB";
-          10'b0000011_001: name = "LH";
-          10'b0000011_010: name = "LW";
-          10'b0000011_011: name = "LD";
-          10'b0000011_100: name = "LBU";
-          10'b0000011_101: name = "LHU";
-          10'b0000011_110: name = "LWU";
-          10'b0010011_000: if (instr[31:15] == 0 & instr[11:7] ==0) name = "NOP/FLUSH";
-                          else                                      name = "ADDI";
-          10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
-                          else if (funct7[6:1] == 6'b010010) name = "BCLRI";
-                          else if (funct7[6:1] == 6'b011010) name = "BINVI";
-                          else if (funct7[6:1] == 6'b001010) name = "BSETI";
-                          else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "ZIP";
-                          else if (funct7 == 7'b0011000 & rs2 == 5'b00000) name = "AES64IM";
-                          else if (funct7 == 7'b0011000 & rs2[4] == 1'b1) name = "AES64KS1I";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00010) name = "SHA256SIG0";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00011) name = "SHA256SIG1";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00000) name = "SHA256SUM0";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00001) name = "SHA256SUM1";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00110) name = "SHA512SIG0";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00111) name = "SHA512SIG1";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00100) name = "SHA512SUM0";
-                          else if (funct7 == 7'b0001000 & rs2 == 5'b00101) name = "SHA512SUM1";
-                          else if (funct7 == 7'b0110000) begin
-                            case (rs2)
-                              5'b00000: name = "CLZ";
-                              5'b00010: name = "CPOP";
-                              5'b00001: name = "CTZ";
-                              5'b00100: name = "SEXT.B";
-                              5'b00101: name = "SEXT.H";
-                              default:  name = "ILLEGAL";
-                            endcase
-                          end else                      name = "ILLEGAL";
-          10'b0010011_010: name = "SLTI";
-          10'b0010011_011: name = "SLTIU";
-          10'b0010011_100: name = "XORI";
-          10'b0010011_101: if (funct7[6:1] == 6'b000000)      name = "SRLI";
-                          else if (funct7[6:1] == 6'b010000) name = "SRAI"; 
-                          else if (funct7[6:1] == 6'b011010 & rs2 == 5'b11000) name = "REV8";
-                          else if (funct7[6:1] == 6'b011000) name = "RORI";
-                          else if (funct7[6:1] == 6'b010010) name = "BEXTI";
-                          else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
-                          else if (imm == 12'b011010000111) name = "BREV8";
-                          else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "UNZIP";
-                          else                           name = "ILLEGAL"; 
-          10'b0010011_110: if      (rd == 0 & rs2 == 0) name = "PREFETCH.I";
-                          else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
-                          else if (rd == 0 & rs2 == 3) name = "PREFETCH.W";
-                          else                         name = "ORI";
-          10'b0010011_111: name = "ANDI";
-          10'b0010111_???: name = "AUIPC";
-          10'b0100011_000: name = "SB";
-          10'b0100011_001: name = "SH";
-          10'b0100011_010: name = "SW";
-          10'b0100011_011: name = "SD";
-          10'b0011011_000: name = "ADDIW";
-          10'b0011011_001: if      (funct7 == 7'b0000000 )name = "SLLIW";
-                          else if (funct7[6:1] == 6'b000010) name = "SLLI.UW";
-                          else if (funct7 == 7'b0110000) begin
-                            case (rs2)
-                              5'b00000:                  name = "CLZW";
-                              5'b00010:                  name = "CPOPW";
-                              5'b00001:                  name = "CTZW";
-                              default:                   name = "ILLEGAL";
-                            endcase
-                          end else                       name = "ILLEGAL";
-          10'b0011011_101: if      (funct7 == 7'b0000000) name = "SRLIW";
-                          else if (funct7 == 7'b0100000) name = "SRAIW";
-                          else if (funct7 == 7'b0110000) name = "RORIW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_000: if      (funct7 == 7'b0000000) name = "ADDW";
-                          else if (funct7 == 7'b0100000) name = "SUBW";
-                          else if (funct7 == 7'b0000001) name = "MULW";
-                          else if (funct7 == 7'b0000100) name = "ADD.UW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_001: if      (funct7 == 7'b0000000) name = "SLLW";
-                          else if (funct7 == 7'b0000001) name = "DIVW";
-                          else if (funct7 == 7'b0110000) name = "ROLW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_010: if      (funct7 == 7'b0010000) name = "SH1ADD.UW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_100: if      (funct7 == 7'b0010000) name = "SH2ADD.UW";
-                          else if (funct7 == 7'b0000100) name = "ZEXT.H";
-                          else                           name = "ILLEGAL";
-          10'b0111011_101: if      (funct7 == 7'b0000000) name = "SRLW";
-                          else if (funct7 == 7'b0100000) name = "SRAW";
-                          else if (funct7 == 7'b0000001) name = "DIVUW";
-                          else if (funct7 == 7'b0110000) name = "RORW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_110: if      (funct7 == 7'b0000001) name = "REMW";
-                          else if (funct7 == 7'b0010000) name = "SH3ADD.UW";
-                          else                           name = "ILLEGAL";
-          10'b0111011_111: if      (funct7 == 7'b0000001) name = "REMUW";
-                          else                           name = "ILLEGAL";
-          10'b0110011_000: if      (funct7 == 7'b0000000) name = "ADD";
-                          else if (funct7 == 7'b0000001) name = "MUL";
-                          else if (funct7 == 7'b0100000) name = "SUB"; 
-                          else if (funct7[4:0] == 5'b10101) name = "AES32DSI";
-                          else if (funct7[4:0] == 5'b10111) name = "AES32DSMI";
-                          else if (funct7 == 7'b0011101)    name = "AES64DS";
-                          else if (funct7 == 7'b0011111)    name = "AES64DSM";
-                          else if (funct7[4:0] == 5'b10001) name = "AES32ESI";
-                          else if (funct7[4:0] == 5'b10011) name = "AES32ESMI";
-                          else if (funct7 == 7'b0011001)    name = "AES64ES";
-                          else if (funct7 == 7'b0011011)    name = "AES64ESM";
-                          else if (funct7 == 7'b0111111)    name = "AES64KS2";
-                          else if (funct7 == 7'b0101110) name = "SHA512SIG0H";
-                          else if (funct7 == 7'b0101010) name = "SHA512SIG0L";
-                          else if (funct7 == 7'b0101111) name = "SHA512SIG1H";
-                          else if (funct7 == 7'b0101011) name = "SHA512SIG1L";
-                          else if (funct7 == 7'b0101000) name = "SHA512SUM0R";
-                          else if (funct7 == 7'b0101001) name = "SHA512SUM1R";
-                          else                           name = "ILLEGAL"; 
-          10'b0110011_001: if      (funct7 == 7'b0000000) name = "SLL";
-                          else if (funct7 == 7'b0000001) name = "MULH";
-                          else if (funct7 == 7'b0110000) name = "ROL";
-                          else if (funct7 == 7'b0000101) name = "CLMUL";
-                          else if (funct7 == 7'b0100100) name = "BCLR";
-                          else if (funct7 == 7'b0110100) name = "BINV";
-                          else if (funct7 == 7'b0010100) name = "BSET";
-                          else                           name = "ILLEGAL";
-          10'b0110011_010: if      (funct7 == 7'b0000000) name = "SLT";
-                          else if (funct7 == 7'b0000001) name = "MULHSU";
-                          else if (funct7 == 7'b0010000) name = "SH1ADD";
-                          else if (funct7 == 7'b0000101) name = "CLMULR";
-                          else                           name = "ILLEGAL";
-          10'b0110011_011: if      (funct7 == 7'b0000000) name = "SLTU";
-                          else if (funct7 == 7'b0000001) name = "MULHU";
-                          else if (funct7 == 7'b0000101) name = "CLMULH";
-                          else                           name = "ILLEGAL";
-          10'b0110011_100: if      (funct7 == 7'b0000000) name = "XOR";
-                          else if (funct7 == 7'b0000001) name = "DIV";
-                          else if (funct7 == 7'b0010000) name = "SH2ADD";
-                          else if (funct7 == 7'b0000101) name = "MIN";
-                          else if (funct7 == 7'b0100000) name = "ORN";
-                          else if (funct7 == 7'b0000100 & rs2 == 5'b00000) name = "ZEXT.H";
-                          else if (funct7 == 7'b0000100 & op == 7'b0110011) name = "PACK";
-                          else if (funct7 == 7'b0000100 & op == 7'b0111011) name = "PACKW";
-                          else                           name = "ILLEGAL";
-          10'b0110011_101: if      (funct7 == 7'b0000000) name = "SRL";
-                          else if (funct7 == 7'b0000001) name = "DIVU";
-                          else if (funct7 == 7'b0100000) name = "SRA";
-                          else if (funct7 == 7'b0000101) name = "MINU";
-                          else if (funct7 == 7'b0110000) name = "ROR";
-                          else if (funct7 == 7'b0100100) name = "BEXT";
-                          else if (funct7 == 7'b0000111) name = "CZERO.EQZ";
-                          else                           name = "ILLEGAL";
-          10'b0110011_110: if      (funct7 == 7'b0000000) name = "OR";
-                          else if (funct7 == 7'b0000001) name = "REM";
-                          else if (funct7 == 7'b0010000) name = "SH3ADD";
-                          else if (funct7 == 7'b0000101) name = "MAX";
-                          else if (funct7 == 7'b0100000) name = "XNOR";
-                          else                           name = "ILLEGAL";
-          10'b0110011_111: if      (funct7 == 7'b0000000) name = "AND";
-                          else if (funct7 == 7'b0000001) name = "REMU";
-                          else if (funct7 == 7'b0000101) name = "MAXU";
-                          else if (funct7 == 7'b0100000) name = "ANDN";
-                          else if (funct7 == 7'b0000111) name = "CZERO.NEZ";
-                          else                           name = "ILLEGAL";
-          10'b0110111_???: name = "LUI";
-          10'b1100011_000: name = "BEQ";
-          10'b1100011_001: name = "BNE";
-          10'b1100011_100: name = "BLT";
-          10'b1100011_101: name = "BGE";
-          10'b1100011_110: name = "BLTU";
-          10'b1100011_111: name = "BGEU";
-          10'b1100111_000: name = "JALR";
-          10'b1101111_???: name = "JAL";
-          10'b1110011_000: if      (imm == 0) name = "ECALL";
-                          else if (imm == 1) name = "EBREAK";
-                          else if (imm == 258) name = "SRET";
-                          else if (imm == 770) name = "MRET";
-                          else if (funct7 == 9) name = "SFENCE.VMA";
-                          else if (funct7 == 11) name = "SINVAL.VMA";
-                          else if (funct7 == 12 & rs2 == 0) name = "SFENCE.W.INVAL";
-                          else if (funct7 == 12 & rs2 == 1) name = "SFENCE.INVAL.IR";
-                          else if (imm == 259) name = "WFI";
-                          else if (imm == 261) name = "WFI";
-                          else              name = "ILLEGAL";
-          10'b1110011_001: name = "CSRRW";
-          10'b1110011_010: name = "CSRRS";
-          10'b1110011_011: name = "CSRRC";
-          10'b1110011_101: name = "CSRRWI";
-          10'b1110011_110: name = "CSRRSI";
-          10'b1110011_111: name = "CSRRCI";
-          10'b0101111_010: if      (funct7[6:2] == 5'b00010) name = "LR.W";
-                          else if (funct7[6:2] == 5'b00011) name = "SC.W";
-                          else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
-                          else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
-                          else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
-                          else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
-                          else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
-                          else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
-                          else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
-                          else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
-                          else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
-                          else                              name = "ILLEGAL";
-          10'b0101111_011: if      (funct7[6:2] == 5'b00010) name = "LR.D";
-                          else if (funct7[6:2] == 5'b00011) name = "SC.D";
-                          else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
-                          else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
-                          else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
-                          else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
-                          else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
-                          else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
-                          else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
-                          else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
-                          else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
-                          else                              name = "ILLEGAL";
-          10'b0001111_000: name = "FENCE";
-          10'b0001111_001: name = "FENCE.I";
-          10'b0001111_010: if      (instr[31:20] == 12'd0) name = "CBO.INVAL";
-                          else if (instr[31:20] == 12'd1) name = "CBO.CLEAN";
-                          else if (instr[31:20] == 12'd2) name = "CBO.FLUSH";
-                          else if (instr[31:20] == 12'd4) name = "CBO.ZERO";    
-                          else                            name = "ILLEGAL";                   
-          10'b1000011_???: name = "FMADD";
-          10'b1000111_???: name = "FMSUB";
-          10'b1001011_???: name = "FNMSUB";
-          10'b1001111_???: name = "FNMADD";
-          10'b1010011_???: if      (funct7[6:2] == 5'b00000) name = "FADD";
-                          else if (funct7[6:2] == 5'b00001) name = "FSUB";
-                          else if (funct7[6:2] == 5'b00010) name = "FMUL";
-                          else if (funct7[6:2] == 5'b00011) name = "FDIV";
-                          else if (funct7[6:2] == 5'b01011) name = "FSQRT";
-                          else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
-                          else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
-                          else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
-                          else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
-                          else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
-                          else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
-                          else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
-                          else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
-                          else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
-                          else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
-                          else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
-                          else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
-                          else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
-                          else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
-                          else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
-                          else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
-                          else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
-                          else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
-                          else if (funct7 == 7'b1100010 & rs2 == 5'b00000) name = "FCVT.W.H";
-                          else if (funct7 == 7'b1100010 & rs2 == 5'b00001) name = "FCVT.WU.H";
-                          else if (funct7 == 7'b1100010 & rs2 == 5'b00010) name = "FCVT.L.H";
-                          else if (funct7 == 7'b1100010 & rs2 == 5'b00011) name = "FCVT.LU.H";
-                          else if (funct7 == 7'b1101010 & rs2 == 5'b00000) name = "FCVT.H.W";
-                          else if (funct7 == 7'b1101010 & rs2 == 5'b00001) name = "FCVT.H.WU";
-                          else if (funct7 == 7'b1101010 & rs2 == 5'b00010) name = "FCVT.H.L";
-                          else if (funct7 == 7'b1101010 & rs2 == 5'b00011) name = "FCVT.H.LU";
-                          else if (funct7 == 7'b1100011 & rs2 == 5'b00000) name = "FCVT.W.Q";
-                          else if (funct7 == 7'b1100011 & rs2 == 5'b00001) name = "FCVT.WU.Q";
-                          else if (funct7 == 7'b1100011 & rs2 == 5'b00010) name = "FCVT.L.Q";
-                          else if (funct7 == 7'b1100011 & rs2 == 5'b00011) name = "FCVT.LU.Q";
-                          else if (funct7 == 7'b1101011 & rs2 == 5'b00000) name = "FCVT.Q.W";
-                          else if (funct7 == 7'b1101011 & rs2 == 5'b00001) name = "FCVT.Q.WU";
-                          else if (funct7 == 7'b1101011 & rs2 == 5'b00010) name = "FCVT.Q.L";
-                          else if (funct7 == 7'b1101011 & rs2 == 5'b00011) name = "FCVT.Q.LU";
-                          else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
-                          else if (funct7 == 7'b0100000 & rs2 == 5'b00010) name = "FCVT.S.H";
-                          else if (funct7 == 7'b0100000 & rs2 == 5'b00011) name = "FCVT.S.Q";
-                          else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
-                          else if (funct7 == 7'b0100001 & rs2 == 5'b00010) name = "FCVT.D.H";
-                          else if (funct7 == 7'b0100001 & rs2 == 5'b00011) name = "FCVT.D.Q";
-                          else if (funct7 == 7'b0100010 & rs2 == 5'b00000) name = "FCVT.H.S";
-                          else if (funct7 == 7'b0100010 & rs2 == 5'b00001) name = "FCVT.H.D";
-                          else if (funct7 == 7'b0100010 & rs2 == 5'b00011) name = "FCVT.H.Q";
-                          else if (funct7 == 7'b0100011 & rs2 == 5'b00000) name = "FCVT.Q.S";
-                          else if (funct7 == 7'b0100011 & rs2 == 5'b00001) name = "FCVT.Q.D";
-                          else if (funct7 == 7'b0100011 & rs2 == 5'b00010) name = "FCVT.Q.H";
-                          else if (funct7 == 7'b1110000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.W";
-                          else if (funct7 == 7'b1111000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.W.X";
-                          else if (funct7 == 7'b1110001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.D";
-                          else if (funct7 == 7'b1111001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.D.X"; 
-                          else if (funct7 == 7'b1110010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.H";
-                          else if (funct7 == 7'b1111010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.H.X";
-                          else if (funct7[6:2] == 5'b00100 & funct3 == 3'b000) name = "FSGNJ";
-                          else if (funct7[6:2] == 5'b00101 & funct3 == 3'b000) name = "FMIN";
-                          else if (funct7[6:2] == 5'b10100 & funct3 == 3'b000) name = "FLE";
-                          else if (funct7[6:2] == 5'b00100 & funct3 == 3'b001) name = "FSGNJN";
-                          else if (funct7[6:2] == 5'b00101 & funct3 == 3'b001) name = "FMAX";
-                          else if (funct7[6:2] == 5'b10100 & funct3 == 3'b001) name = "FLT";
-                          else if (funct7[6:2] == 5'b11100 & funct3 == 3'b001) name = "FCLASS";
-                          else if (funct7[6:2] == 5'b00100 & funct3 == 3'b010) name = "FSGNJX";
-                          else if (funct7[6:2] == 5'b10100 & funct3 == 3'b010) name = "FEQ";
-                          else if (funct7[6:2] == 5'b11110 & funct3 == 3'b000 & rs2 == 5'b00001) name = "FLI";
-                          else if (funct7[6:2] == 5'b00101 & funct3 == 3'b010) name = "FMINM";
-                          else if (funct7[6:2] == 5'b00101 & funct3 == 3'b011) name = "FMAXM";
-                          else if (funct7[6:2] == 5'b01000 & rs2 == 5'b00100) name = "FROUND";
-                          else if (funct7[6:2] == 5'b01000 & rs2 == 5'b00101) name = "FROUNDNX";
-                          else if (funct7[6:2] == 5'b10100 & funct3 == 3'b100) name = "FLEQ";
-                          else if (funct7[6:2] == 5'b10100 & funct3 == 3'b101) name = "FLTQ";
-                          else if (funct7 == 7'b1110001 & funct3 == 3'b000 & rs2 == 5'b00001) name = "FMVH.X.D";
-                          else if (funct7 == 7'b1110011 & funct3 == 3'b000 & rs2 == 5'b00001) name = "FMVH.X.Q";
-                          else if (funct7 == 7'b1011001 & funct3 == 3'b000) name = "FMVP.D.X";
-                          else if (funct7 == 7'b1011011 & funct3 == 3'b000) name = "FMVP.Q.X";
-                          else if (funct7 == 7'b1100001 & funct3 == 3'b001 & rs2 == 5'b01000) name = "FCVTMOD.W.D";
-                          else                              name = "ILLEGAL";
-          10'b0000111_001: name = "FLH";
-          10'b0000111_010: name = "FLW";
-          10'b0000111_011: name = "FLD";
-          10'b0000111_100: name = "FLQ";
-          10'b0100111_001: name = "FSH";
-          10'b0100111_010: name = "FSW";
-          10'b0100111_011: name = "FSD";
-          10'b0100111_100: name = "FSQ";
-          default:         name = "ILLEGAL";
-        endcase
-    endcase
-endmodule
diff --git a/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv
deleted file mode 100644
index dfd2dc4a0..000000000
--- a/testbench/common/instrTrackerTB.sv
+++ /dev/null
@@ -1,38 +0,0 @@
-///////////////////////////////////////////
-// instrTrackerTB.sv
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module instrTrackerTB #(parameter XLEN) (
-  input  logic            clk, reset, FlushE,
-  input  logic [31:0]     InstrF, InstrD,
-  input  logic [31:0]     InstrE, InstrM,
-  input  logic [31:0]     InstrW,
-//  output logic [31:0]     InstrW,
-  output string           InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-        
-  // stage Instr to Writeback for visualization
-  // flopr  #(32) InstrWReg(clk, reset, InstrM, InstrW);
-
-  instrNameDecTB #(XLEN) fdec(InstrF, InstrFName);
-  instrNameDecTB #(XLEN) ddec(InstrD, InstrDName);
-  instrNameDecTB #(XLEN) edec(InstrE, InstrEName);
-  instrNameDecTB #(XLEN) mdec(InstrM, InstrMName);
-  instrNameDecTB #(XLEN) wdec(InstrW, InstrWName);
-endmodule
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
deleted file mode 100644
index 5ed07b6d6..000000000
--- a/testbench/common/loggers.sv
+++ /dev/null
@@ -1,294 +0,0 @@
-///////////////////////////////////////////
-// loggers.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Modified: 14 June 2023
-// 
-// Purpose: Log branch instructions, log instruction fetches,
-//          log I$ misses, log data memory accesses, log D$ misses, and
-//          log other related operations
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module loggers import cvw::*; #(parameter cvw_t P,
-
-                                parameter PrintHPMCounters,
-                                parameter I_CACHE_ADDR_LOGGER,
-                                parameter D_CACHE_ADDR_LOGGER,
-                                parameter BPRED_LOGGER) (
-  input logic  clk,
-  input logic  reset,
-  input logic  DCacheFlushStart,
-  input logic  DCacheFlushDone,                                                         
-//  input logic BeginSample,
-//  input logic StartSample,
-//  input logic EndSample,
-  input string memfilename,
-  input string TEST
-  );
-  
-  // performance counter logging 
-  logic        BeginSample;
-  logic StartSample, EndSample;
-  if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
-    integer           HPMCindex;
-    logic             StartSampleFirst;
-    logic             StartSampleDelayed, BeginDelayed;
-    logic             EndSampleFirst;
-    logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
-    logic              EndSampleDelayed;
-
-    string  HPMCnames[] = '{"Mcycle",
-                            "------",
-                            "InstRet",
-                            "Br Count",
-                            "Jump Not Return",
-                            "Return",
-                            "BP Wrong",
-                            "BP Dir Wrong",
-                            "BP Target Wrong",
-                            "RAS Wrong",
-                            "Instr Class Wrong",
-                            "Load Stall",
-                            "Store Stall",
-                            "D Cache Access",
-                            "D Cache Miss",
-                            "D Cache Cycles",
-                            "I Cache Access",
-                            "I Cache Miss",
-                            "I Cache Cycles",
-                            "CSR Write",
-                            "FenceI",
-                            "SFenceVMA",
-                            "Interrupt",
-                            "Exception",
-                            "Divide Cycles"
-                          };
-
-
-    always_comb
-      if (TEST == "embench") begin  
-        StartSampleFirst = functionName.functionName.FunctionName == "start_trigger";
-        EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger";
-      end else if (TEST == "coremark") begin
-        StartSampleFirst = functionName.functionName.FunctionName == "start_time";
-        EndSampleFirst = functionName.functionName.FunctionName == "stop_time";
-      end else begin
-        StartSampleFirst = reset;
-        EndSampleFirst = '0;
-      end
-
-    flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-    always_comb
-      if (TEST == "embench" | TEST == "coremark") begin
-        EndSample = EndSampleFirst & ~ EndSampleDelayed;
-      end else begin
-        EndSample = DCacheFlushStart & ~DCacheFlushDone;
-      end
-    
-  /*
-    if(TEST == "embench") begin
-      // embench runs warmup then runs start_trigger
-      // embench end with stop_trigger.
-      //assign StartSampleFirst = functionName.functionName.FunctionName == "start_trigger";
-      //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      //assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else if(TEST == "coremark") begin
-      // embench runs warmup then runs start_trigger
-	    // embench end with stop_trigger.
-      //assign StartSampleFirst = functionName.functionName.FunctionName == "start_time";
-      //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      //assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-
-      //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_time";
-      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
-
-    end else begin
-      // default start condiction is reset
-      // default end condiction is end of test (DCacheFlushDone)
-      //assign StartSampleFirst = reset;
-      //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-      //assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-      //assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
-
-      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
-      assign BeginSample = StartSampleFirst & ~BeginDelayed;
-
-    end
-
-  */
-
-    flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-    assign StartSample = StartSampleFirst & ~StartSampleDelayed;
-    flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
-    assign BeginSample = StartSampleFirst & ~BeginDelayed;
-
-
-    always @(negedge clk) begin
-      if(StartSample) begin
-        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
-          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
-        end
-      end
-      if(EndSample) begin
-        for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
-          // unlikely to have more than 10M in any counter.
-          $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
-        end
-      end
-    end
-  end
-
-  if (P.ICACHE_SUPPORTED & I_CACHE_ADDR_LOGGER) begin : ICacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enable;
-    logic  InvalDelayed, InvalEdge;
-    
-    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
-                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
-                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
-                    dut.core.ifu.bus.icache.icache.cachefsm.CacheEn &
-                    ~reset;
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
-
-    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
-    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
-
-    initial begin
-      LogFile = "ICache.log";
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
-    end
-    string AccessTypeString, HitMissString;
-    always @(*) begin
-      HitMissString = dut.core.ifu.bus.icache.icache.Hit ? "H" :
-                      dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
-    end
-    always @(posedge clk) begin
-    if(resetEdge) $fwrite(file, "TRAIN\n");
-    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-    if(Enable) begin  // only log i cache reads
-      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
-    end
-    if(InvalEdge) $fwrite(file, "0 I X\n");
-    if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-
-  if (P.DCACHE_SUPPORTED & D_CACHE_ADDR_LOGGER) begin : DCacheLogger
-    int    file;
-    string LogFile;
-    logic  resetD, resetEdge;
-    logic  Enabled;
-    string AccessTypeString, HitMissString;
-
-    flop #(1) ResetDReg(clk, reset, resetD);
-    assign resetEdge = ~reset & resetD;
-    always @(*) begin
-      HitMissString = dut.core.lsu.bus.dcache.dcache.Hit ? "H" :
-                      (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
-                      dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
-      AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
-                         dut.core.lsu.LSUAtomicM[1] ? "A" :
-                         dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
-                         dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
-                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" :   // cbo.zero
-                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" :   // cbo.inval should just clear the valid and dirty bits
-                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" :   // cbo.clean should act like a read in terms of the lru, but clears the dirty bit
-                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" :   // cbo.flush should just clear and the valid and drity bits
-                         "NULL";
-    end
-
-    assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn |
-                      // don't include cbo.zero as it uses LRUWriteEn to update the LRU and would be double counted.
-                      ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall)) &
-                     ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
-                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
-                     dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &
-                     (AccessTypeString != "NULL");
-
-    initial begin
-      LogFile = "DCache.log";
-      file = $fopen(LogFile, "w");
-      $fwrite(file, "BEGIN %s\n", memfilename);
-    end
-    always @(posedge clk) begin
-      if(resetEdge) $fwrite(file, "TRAIN\n");
-      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-      if(Enabled) begin
-        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
-      end
-      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
-      if(EndSample) $fwrite(file, "END %s\n", memfilename);
-    end
-  end
-
-  if (P.BPRED_SUPPORTED) begin : BranchLogger
-    if (BPRED_LOGGER) begin
-      string direction;
-      int    file, CFIfile;
-      logic  PCSrcM;
-      string LogFile, CFILogFile;
-      logic  resetD, resetEdge;
-      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
-      flop #(1) ResetDReg(clk, reset, resetD);
-      assign resetEdge = ~reset & resetD;
-      initial begin
-        LogFile = "branch.log"; // will break some of Rose's research analysis scripts
-        CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
-        //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
-        file = $fopen(LogFile, "w");
-        CFIfile = $fopen(CFILogFile, "w");
-      end
-      always @(posedge clk) begin
-        if(resetEdge) begin 
-          $fwrite(file, "TRAIN\n");
-          $fwrite(CFIfile, "TRAIN\n");
-        end
-        if(StartSample) begin
-          $fwrite(file, "BEGIN %s\n", memfilename);
-          $fwrite(CFIfile, "BEGIN %s\n", memfilename);
-        end
-        if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-          direction = PCSrcM ? "t" : "n";
-          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
-        end
-        if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-          direction = PCSrcM ? "t" : "n";
-          $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
-        end
-        if(EndSample) begin
-          $fwrite(file, "END %s\n", memfilename);
-          $fwrite(CFIfile, "END %s\n", memfilename);
-        end
-      end
-    end
-  end
-
-endmodule
diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv
deleted file mode 100644
index fac34fb43..000000000
--- a/testbench/common/ramxdetector.sv
+++ /dev/null
@@ -1,47 +0,0 @@
-///////////////////////////////////////////
-// ramxdetector.sv
-//
-// Written: David_Harris@hmc.edu
-// Modified: 2 July 2023
-//
-// Purpose: Detects if the processor is attempting to read unitialized RAM
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module ramxdetector #(parameter XLEN, LLEN) (
-  input  logic            clk,
-  input  logic            MemReadM,
-  input  logic            LSULoadAccessFaultM,
-  input  logic [LLEN-1:0] ReadDataM,
-  input  logic [XLEN-1:0] PCM,
-  input  logic [31:0]     InstrM,
-  input  logic [XLEN-1:0] IEUAdrM,
-  input  string           InstrMName
-);
-
-  always_ff @(posedge clk)
-    /* verilator lint_off WIDTHXZEXPAND */
-    if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
-      /* verilator lint_on WIDTHXZEXPAND */
-      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
-      $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
-      //$stop;
-    end
-  
-endmodule
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
deleted file mode 100644
index 4481d3f96..000000000
--- a/testbench/common/riscvassertions.sv
+++ /dev/null
@@ -1,75 +0,0 @@
-///////////////////////////////////////////
-// riscvassertions.sv
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module riscvassertions import cvw::*; #(parameter cvw_t P);
-  initial begin
-    assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (P.S_SUPPORTED | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
-    assert (P.IDIV_BITSPERCYCLE == 1 | P.IDIV_BITSPERCYCLE==2 | P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
-    assert (P.F_SUPPORTED | ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
-    assert (P.D_SUPPORTED | ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
-    assert (P.F_SUPPORTED | ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (P.DCACHE_SUPPORTED | ~P.F_SUPPORTED | P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
-    assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
-    assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (P.DCACHE_LINELENINBITS >= 128 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
-    assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
-    assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (P.ICACHE_LINELENINBITS >= 32 | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
-    assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
-    assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
-    assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
-	  assert (P.ZICSR_SUPPORTED == 1 | (P.PMP_ENTRIES == 0 & P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
-    assert (P.ZICSR_SUPPORTED == 1 | (P.S_SUPPORTED == 0 & P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
-    assert (P.U_SUPPORTED | (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
-    assert (P.VIRTMEM_SUPPORTED == 0 | (P.DTIM_SUPPORTED == 0 & P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (P.DCACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
-    assert (P.ICACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
-    assert ((P.DCACHE_SUPPORTED == 0 & P.ICACHE_SUPPORTED == 0) | P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
-    assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
-    assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (P.DCACHE_SUPPORTED | (P.ZAAMO_SUPPORTED == 0 & P.ZALRSC_SUPPORTED == 0)) else $fatal(1, "Atomic extension (ZAAMO/ZALRSC) requires cache on Wally.");
-    assert (P.IDIV_ON_FPU == 0 | P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
-    assert (P.SSTC_SUPPORTED == 0 | (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
-    assert ((P.M_SUPPORTED == 0) | (P.ZMMUL_SUPPORTED == 1)) else $fatal(1, "M requires ZMMUL");
-    assert ((P.ZICNTR_SUPPORTED == 0) | (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
-    assert ((P.ZIHPM_SUPPORTED == 0) | (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
-    assert ((P.ZICBOM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
-    assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
-    assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DTIM_SUPPORTED == 0)) else $fatal(1, "ZICBOZ incompatible with DTIM");
-    assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
-    assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
-    assert ((P.SVINVAL_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1)) else $fatal(1, "SVINVAL requires VIRTMEM_SUPPORTED");
-    assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA");
-    assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
-    assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
-    assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
-    assert ((P.ZICCLSM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICCLSM requires DCACHE_SUPPORTED");
-  end
-
-endmodule
-
-
diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv
deleted file mode 100644
index f9c1f316c..000000000
--- a/testbench/common/rvvitbwrapper.sv
+++ /dev/null
@@ -1,170 +0,0 @@
-///////////////////////////////////////////
-// loggers.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Modified: 24 July 2024
-// 
-// Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module rvvitbwrapper import cvw::*; #(parameter cvw_t P,
-                                parameter MAX_CSRS = 5,
-                                parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4,
-                                parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2)(
-  input  logic clk,
-  input  logic reset,
-  output logic RVVIStall,
-  input  logic mii_tx_clk,
-  output logic [3:0] mii_txd,
-  output logic mii_tx_en, mii_tx_er,
-  input  logic mii_rx_clk,
-  input  logic [3:0] mii_rxd,
-  input  logic mii_rx_dv,
-  input  logic mii_rx_er
-);
-
-  logic        valid;
-  logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
-
-  localparam TOTAL_CSRS = 36;
-  
-  // pipeline controlls
-  logic                                             StallE, StallM, StallW, FlushE, FlushM, FlushW;
-  // required
-  logic [P.XLEN-1:0]                                PCM;
-  logic                                             InstrValidM;
-  logic [31:0]                                      InstrRawD;
-  logic [63:0]                                      Mcycle, Minstret;
-  logic                                             TrapM;
-  logic [1:0]                                       PrivilegeModeW;
-  // registers gpr and fpr
-  logic                                             GPRWen, FPRWen;
-  logic [4:0]                                       GPRAddr, FPRAddr;
-  logic [P.XLEN-1:0]                                GPRValue, FPRValue;
-  logic [P.XLEN-1:0]                                CSRArray [TOTAL_CSRS-1:0];
-
-  // axi 4 write data channel
-  logic [31:0]                                      RvviAxiWdata;
-  logic [3:0]                                       RvviAxiWstrb;
-  logic                                             RvviAxiWlast;
-  logic                                             RvviAxiWvalid;
-  logic                                             RvviAxiWready;
-
-  logic                                             tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
-  logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
-
-  logic                                             MiiTxEnDelay;
-  logic                                             EthernetTXCounterEn;
-  logic [31:0]                                      EthernetTXCount;
-
-  assign StallE         = dut.core.StallE;
-  assign StallM         = dut.core.StallM;
-  assign StallW         = dut.core.StallW;
-  assign FlushE         = dut.core.FlushE;
-  assign FlushM         = dut.core.FlushM;
-  assign FlushW         = dut.core.FlushW;
-  assign InstrValidM    = dut.core.ieu.InstrValidM;
-  assign InstrRawD      = dut.core.ifu.InstrRawD;
-  assign PCM            = dut.core.ifu.PCM;
-  assign Mcycle         = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
-  assign Minstret       = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-  assign TrapM          = dut.core.TrapM;
-  assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
-  assign GPRAddr        = dut.core.ieu.dp.regf.a3;
-  assign GPRWen         = dut.core.ieu.dp.regf.we3;
-  assign GPRValue       = dut.core.ieu.dp.regf.wd3;
-  assign FPRAddr        = dut.core.fpu.fpu.fregfile.a4;
-  assign FPRWen         = dut.core.fpu.fpu.fregfile.we4;
-  assign FPRValue       = dut.core.fpu.fpu.fregfile.wd4;
-
-  assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
-  assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
-  assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
-  assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
-  assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
-  assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
-  assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
-  assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
-  assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
-  assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
-  assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
-  assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
-  assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
-  assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
-  assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
-  assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
-  assign CSRArray[16] = 0; // 12'hF11
-  assign CSRArray[17] = 0; // 12'hF12
-  assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
-  assign CSRArray[19] = 0; // 12'hF15
-  assign CSRArray[20] = 0; // 12'h34A
-  // supervisor CSRs
-  assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
-  assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
-  assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
-  assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
-  assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
-  assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
-  assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
-  assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
-  assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
-  assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
-  assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
-  assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
-  // user CSRs
-  assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
-  assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
-  assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
-
-  rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
-                                                 .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, 
-                                                 .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
-                                                 .valid, .rvvi);
-
-  packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
-    .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
-
-  eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset),
-    .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
-    .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
-    .rx_axis_tlast(), .rx_axis_tuser(),
-
-    .mii_rx_clk(clk),
-    .mii_rxd('0),
-    .mii_rx_dv('0),
-    .mii_rx_er('0),
-    .mii_tx_clk(clk),
-    .mii_txd,
-    .mii_tx_en,
-    .mii_tx_er,
-
-    // status
-    .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
-    .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, 
-    .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1));
-
-  flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay);
-  assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay;
-  counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount);
-
-endmodule  
-
-
-
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
deleted file mode 100644
index b0fb67c67..000000000
--- a/testbench/common/wallyTracer.sv
+++ /dev/null
@@ -1,501 +0,0 @@
-///////////////////////////////////////////
-// wallyTracer.sv
-//
-// A component of the Wally configurable RISC-V project.
-// Implements a RISC-V Verification Interface (RVVI)
-// to support functional coverage and lockstep simulation.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`define STD_LOG 0
-`define PRINT_PC_INSTR 0
-`define PRINT_MOST 0
-`define PRINT_ALL 0
-`define PRINT_CSRS 0
-
-// Since we are detecting the CSR change by comparing the old value, we need to
-// ensure the CSR is detected when the pipeline's Writeback stage is not
-// stalled.  If it is stalled we want to hold the old value.
-`define CONNECT_CSR(name, addr, val) \
-  logic [P.XLEN-1:0] prev_csr_``name; \
-  always_ff @(posedge clk) \
-    prev_csr_``name <= rvvi.csr[0][0][addr]; \
-  assign rvvi.csr_wb[0][0][addr] = (rvvi.csr[0][0][addr] != prev_csr_``name); \
-  assign rvvi.csr[0][0][addr] = valid ? val : prev_csr_``name;
-
-module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
-
-  localparam NUM_REGS = P.E_SUPPORTED ? 16 : 32;
-  localparam NUM_CSRS = 4096;
-  
-  // wally specific signals
-  logic                  reset;
-  logic                  clk;
-  logic                  InstrValidD, InstrValidE;
-  logic                  StallF, StallD;
-  logic                  STATUS_SXL, STATUS_UXL;
-  logic [P.XLEN-1:0]     PCNextF, PCF, PCD, PCE, PCM, PCW;
-  logic [31:0]           InstrRawD, InstrRawE, InstrRawM, InstrRawW;
-  logic                  InstrValidM, InstrValidW;
-  logic                  StallE, StallM, StallW;
-  logic                  GatedStallW;
-  logic                  SelHPTW;
-  logic                  FlushD, FlushE, FlushM, FlushW;
-  logic                  TrapM, TrapW;
-  logic                  HaltM, HaltW;
-  logic [1:0]            PrivilegeModeW;
-  logic [P.XLEN-1:0]     rf[NUM_REGS];
-  logic [NUM_REGS-1:0]   rf_wb;
-  logic [4:0]            rf_a3;
-  logic                  rf_we3;
-  logic [P.FLEN-1:0]     frf[32];
-  logic [31:0]           frf_wb;
-  logic [4:0]            frf_a4;
-  logic                  frf_we4;
-  logic                  CSRWriteM, CSRWriteW;
-  logic [11:0]           CSRAdrM, CSRAdrW;
-  logic                  wfiM;
-  logic                  InterruptM, InterruptW;
-  logic                  MExtInt, SExtInt, MTimerInt, MSwInt;
-  logic                  valid;
-
-  //For VM Verification
-  logic [(P.XLEN-1):0]     IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
-  logic [(P.XLEN-1):0]     IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW;
-  logic [(P.PA_BITS-1):0]  IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW;
-  logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW;
-  logic [1:0]              IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
-  logic                    ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
-  logic                    ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
-
-  assign clk = testbench.dut.clk;
-  //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
-  assign InstrValidD    = testbench.dut.core.ieu.c.InstrValidD;
-  assign InstrValidE    = testbench.dut.core.ieu.c.InstrValidE;
-  assign InstrValidM    = testbench.dut.core.ieu.InstrValidM;
-  assign InstrRawD      = testbench.dut.core.ifu.InstrRawD;
-  assign PCNextF        = testbench.dut.core.ifu.PCNextF;
-  assign PCF            = testbench.dut.core.ifu.PCF;
-  assign PCD            = testbench.dut.core.ifu.PCD;
-  assign PCE            = testbench.dut.core.ifu.PCE;
-  assign PCM            = testbench.dut.core.ifu.PCM;
-  assign reset          = testbench.reset;
-  assign StallF         = testbench.dut.core.StallF;
-  assign StallD         = testbench.dut.core.StallD;
-  assign StallE         = testbench.dut.core.StallE;
-  assign StallM         = testbench.dut.core.StallM;
-  assign StallW         = testbench.dut.core.StallW;
-  assign GatedStallW    = testbench.dut.core.lsu.GatedStallW;
-  assign FlushD         = testbench.dut.core.FlushD;
-  assign FlushE         = testbench.dut.core.FlushE;
-  assign FlushM         = testbench.dut.core.FlushM;
-  assign FlushW         = testbench.dut.core.FlushW;
-  assign TrapM          = testbench.dut.core.TrapM;
-  assign HaltM          = testbench.DCacheFlushStart;
-  if (P.ZICSR_SUPPORTED) begin
-    assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
-    assign STATUS_SXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
-    assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
-    assign wfiM           = testbench.dut.core.priv.priv.wfiM;
-    assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
-    assign MExtInt        = testbench.dut.MExtInt;
-    assign SExtInt        = testbench.dut.SExtInt;
-    assign MTimerInt      = testbench.dut.MTimerInt;
-    assign MSwInt         = testbench.dut.MSwInt;
-  end else begin
-    assign PrivilegeModeW = 2'b11;
-    assign STATUS_SXL     = 0;
-    assign STATUS_UXL     = 0;
-    assign wfiM           = 0;
-    assign InterruptM     = 0;
-    assign MExtInt        = 0;
-    assign SExtInt        = 0;
-    assign MTimerInt      = 0;
-    assign MSwInt         = 0;
-  end
-
-  //For VM Verification
-  if (P.VIRTMEM_SUPPORTED) begin
-    assign SelHPTW        = testbench.dut.core.lsu.hptw.hptw.SelHPTW;
-    assign IVAdrF         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
-    assign DVAdrM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
-    assign IPAF           = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
-    assign DPAM           = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
-    assign ReadAccessM    = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
-    assign WriteAccessM   = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
-    assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
-    assign IPTEF          = testbench.dut.core.ifu.immu.immu.PTE;
-    assign DPTEM          = testbench.dut.core.lsu.dmmu.dmmu.PTE;
-    assign IPPNF          = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
-    assign DPPNM          = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
-    assign IPageTypeF     = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
-    assign DPageTypeM     = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
-  end else begin
-    assign SelHPTW        = 1'b0;
-    assign IVAdrF         = 0;
-    assign DVAdrM         = 0;
-    assign IPAF           = 0;
-    assign DPAM           = 0;
-    assign ReadAccessM    = 0;
-    assign WriteAccessM   = 0;
-    assign ExecuteAccessF = 0;
-    assign IPTEF          = 0;
-    assign DPTEM          = 0;
-    assign IPPNF          = 0;
-    assign DPPNM          = 0;
-    assign IPageTypeF     = 0;
-    assign DPageTypeM     = 0;
-  end
-
-
-  // CSR connections
-  if (P.ZICSR_SUPPORTED) begin
-    // M-mode trap CSRs
-    `CONNECT_CSR(MSTATUS, 12'h300, testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW);
-    `CONNECT_CSR(MEDELEG, 12'h302, testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW);
-    `CONNECT_CSR(MIDELEG, 12'h303, testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
-    `CONNECT_CSR(MIE, 12'h304, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW);
-    `CONNECT_CSR(MTVEC, 12'h305, testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW);
-    `CONNECT_CSR(MSCRATCH, 12'h340, testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW);
-    `CONNECT_CSR(MEPC, 12'h341, testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW);
-    `CONNECT_CSR(MCAUSE, 12'h342, testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW);
-    `CONNECT_CSR(MTVAL, 12'h343, testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW);
-    `CONNECT_CSR(MIP, 12'h344, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW);
-
-    // S-mode trap CSRs
-    if (P.S_SUPPORTED) begin
-      `CONNECT_CSR(SSTATUS, 12'h100, testbench.dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW);
-      `CONNECT_CSR(SIE, 12'h104, testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
-      `CONNECT_CSR(STVEC, 12'h105, testbench.dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW);
-      `CONNECT_CSR(SSCRATCH, 12'h140, testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW);
-      `CONNECT_CSR(SEPC, 12'h141, testbench.dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW);
-      `CONNECT_CSR(SCAUSE, 12'h142, testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW);
-      `CONNECT_CSR(STVAL, 12'h143, testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW);
-      `CONNECT_CSR(SIP, 12'h144, testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW);
-    end
-
-    // Virtual Memory CSRs
-    if (P.VIRTMEM_SUPPORTED) begin
-      `CONNECT_CSR(SATP, 12'h180, testbench.dut.core.priv.priv.csr.csrs.csrs.SATP_REGW);
-    end
-
-    // Floating-Point CSRs
-    if (P.F_SUPPORTED) begin
-      `CONNECT_CSR(FFLAGS, 12'h001, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW);
-      `CONNECT_CSR(FRM, 12'h002, testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW);
-      `CONNECT_CSR(FCSR, 12'h003, {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW});
-    end
-
-    // Counters / Performance Monitoring CSRs
-    if (P.U_SUPPORTED) begin
-      `CONNECT_CSR(MCOUNTEREN, 12'h306, testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW);
-    end
-    if (P.S_SUPPORTED) begin
-      `CONNECT_CSR(SCOUNTEREN, 12'h106, testbench.dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW);
-    end
-    `CONNECT_CSR(MCOUNTINHIBIT, 12'h320, testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW);
-    // mhpmevent3-31 not connected (232-33F)
-    if (P.ZICNTR_SUPPORTED) begin
-      `CONNECT_CSR(MCYCLE, 12'hB00, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]); // MCYCLE
-      `CONNECT_CSR(MINSTRET, 12'hB02, testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]); // MINSTRET
-      // mhpmcounter3-31 not connected (B03-B1F)
-      // cycle, time, instret not connected (C00-C02)
-      // hpmcounter3-31 not connected (C03-C1F)
-    end
-
-    // Machine Information Registers and Configuration CSRs
-    `CONNECT_CSR(MISA, 12'h301, testbench.dut.core.priv.priv.csr.csrm.MISA_REGW);
-    `CONNECT_CSR(MENVCFG, 12'h30A, testbench.dut.core.priv.priv.csr.csrm.MENVCFG_REGW);
-    `CONNECT_CSR(MSECCFG, 12'h747, 0); // mseccfg
-    `CONNECT_CSR(MVENDORID, 12'hF11, 0); //mvendorid
-    `CONNECT_CSR(MARCHID, 12'hF12, 0); // marchid
-    `CONNECT_CSR(MIMPID, 12'hF13, {{P.XLEN-12{1'b0}}, 12'h100}); // mimpid
-    `CONNECT_CSR(MHARTID, 12'hF14, testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW);
-    `CONNECT_CSR(MCONFIGPTR, 12'hF15, 0); //mconfigptr
-
-    // Supervisor Information Registers and Configuration CSRs
-    if (P.S_SUPPORTED) begin
-      `CONNECT_CSR(SENVCFG, 12'h10A, testbench.dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW);
-    end
-
-    // Sstc CSRs
-    if (P.SSTC_SUPPORTED) begin
-      `CONNECT_CSR(STIMECMP, 12'h14D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]);
-      if (P.XLEN == 32) begin
-        `CONNECT_CSR(STIMECMPH, 12'h15D, testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]);
-      end
-    end
-    
-    // Zkr CSRs
-    // seed not connected (015)
-
-    // extra M mode CSRs for RV32
-    if (P.XLEN == 32) begin
-      `CONNECT_CSR(MSTATUSH, 12'h310, testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW);
-      `CONNECT_CSR(MENVCFGH, 12'h31A, testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW);
-      `CONNECT_CSR(MSECCFGH, 12'h757, 0); // mseccfgh
-    end
-  end
-
-  if (P.PMP_ENTRIES > 0) begin
-    localparam inc = P.XLEN == 32 ? 4 : 8;
-    // PMPCFG CSRs (space is 0-15 3a0 - 3af)
-    for (genvar pmpCfgID = 0; pmpCfgID < P.PMP_ENTRIES; pmpCfgID += inc) begin
-      logic [P.XLEN-1:0] pmp;
-      localparam int i4 = pmpCfgID / 4;
-      if (P.XLEN == 32) begin
-        // For RV32, only access 4 entries
-        assign pmp = {testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+3],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+2],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+1],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+0]};
-      end else begin
-        // For RV64, access all 8 entries
-        assign pmp = {testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+7],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+6],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+5],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+4],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+3],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+2],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+1],
-                      testbench.dut.core.priv.priv.csr.csrm.PMPCFG_ARRAY_REGW[pmpCfgID+0]};
-      end
-      `CONNECT_CSR(PMPCFG``i4, 12'h3A0 + i4, pmp);
-    end
-
-  // PMPADDR CSRs 3B0 to 3EF
-    for(genvar pmpAddrID = 0; pmpAddrID < P.PMP_ENTRIES; pmpAddrID++) begin
-      `CONNECT_CSR(PMPADDR``pmpAddrID, 12'h3B0 + pmpAddrID, testbench.dut.core.priv.priv.csr.csrm.PMPADDR_ARRAY_REGW[pmpAddrID]);
-    end
-  end
-
-  // Integer register file
-  assign rf[0] = 0;
-  for(genvar index = 1; index < NUM_REGS; index += 1) 
-    assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
-
-  assign rf_a3  = testbench.dut.core.ieu.dp.regf.a3;
-  assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
-
-  always_comb begin
-    rf_wb <= 0;
-    if(rf_we3)
-      rf_wb[rf_a3] <= 1'b1;
-  end
-
-  // Floating-point register file
-  if (P.F_SUPPORTED) begin
-    assign frf_a4  = testbench.dut.core.fpu.fpu.fregfile.a4;
-    assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
-    for(genvar index = 0; index < 32; index += 1) 
-      assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
-  end else begin
-    assign frf_a4  = '0;
-    assign frf_we4 = 0;
-    for(genvar index = 0; index < 32; index += 1) 
-      assign frf[index] = '0;
-  end
-
-  always_comb begin
-    frf_wb <= 0;
-    if(frf_we4)
-      frf_wb[frf_a4] <= 1'b1;
-  end
-
-  // CSR writes
-  assign CSRAdrM  = testbench.dut.core.priv.priv.csr.CSRAdrM;
-  assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
-  
-  // pipeline to writeback stage
-  flopenrc #(32)    InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
-  flopenrc #(32)    InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(32)    InstrRawWReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrRawM, InstrRawW);
-  flopenrc #(P.XLEN)PCWReg       (clk, reset, FlushW & ~TrapM, ~StallW, PCM, PCW);
-  flopenrc #(1)     InstrValidMReg (clk, reset, FlushW & ~TrapM, ~StallW, InstrValidM, InstrValidW);
-  flopenrc #(1)     TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
-  flopenrc #(1)     InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
-  flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
-
-  flopenrc #(12)    CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
-  flopenrc #(1)     CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
-
-  //for VM Verification
-  flopenrc #(P.XLEN)     IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
-  flopenrc #(P.XLEN)     IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU
-  flopenrc #(P.XLEN)     IVAdrMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IVAdrE, IVAdrM); //Virtual Address for IMMU
-  flopenrc #(P.XLEN)     IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-  flopenrc #(P.XLEN)     DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-
-  flopenrc #(P.PA_BITS)  IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
-  flopenrc #(P.PA_BITS)  IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU
-  flopenrc #(P.PA_BITS)  IPAMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPAE, IPAM); //Physical Address for IMMU
-  flopenrc #(P.PA_BITS)  IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-  flopenrc #(P.PA_BITS)  DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-
-  flopenrc #(P.XLEN)     IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
-  flopenrc #(P.XLEN)     IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU
-  flopenrc #(P.XLEN)     IPTEMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPTEE, IPTEM); //PTE for IMMU
-  flopenrc #(P.XLEN)     IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-  flopenrc #(P.XLEN)     DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-
-  flopenrc #(2)     IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
-  flopenrc #(2)     IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU
-  flopenrc #(2)     IPageTypeMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU
-  flopenrc #(2)     IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-  flopenrc #(2)     DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
-
-  flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU
-  flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU
-  flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU
-  flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU
-  flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU
-
-  flopenrc #(1)  ReadAccessWReg    (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW);   //LoadAccess
-  flopenrc #(1)  WriteAccessWReg   (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess
-
-  flopenrc #(1)  ExecuteAccessDReg (clk, reset, 1'b0, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access
-  flopenrc #(1)  ExecuteAccessEReg (clk, reset, 1'b0, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access
-  flopenrc #(1)  ExecuteAccessMReg (clk, reset, 1'b0, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access
-  flopenrc #(1)  ExecuteAccessWReg (clk, reset, 1'b0, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access
-
-  // Initially connecting the writeback stage signals, but may need to use M stage
-  // and gate on ~FlushW.
-
-  assign valid  = ((InstrValidW | TrapW) & ~StallW) & ~reset;
-  assign rvvi.clk = clk;
-  assign rvvi.valid[0][0]    = valid;
-  assign rvvi.order[0][0]    = rvvi.csr[0][0][12'hB02];  // TODO: IMPERAS Should be event order
-  assign rvvi.insn[0][0]     = InstrRawW;
-  assign rvvi.pc_rdata[0][0] = PCW;
-  assign rvvi.trap[0][0]     = TrapW;
-  assign rvvi.halt[0][0]     = HaltW;
-  assign rvvi.intr[0][0]     = InterruptW;
-  assign rvvi.mode[0][0]     = PrivilegeModeW;
-  assign rvvi.ixl[0][0]      = PrivilegeModeW == 2'b11 ? 2'b10 :
-                               PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
-  assign rvvi.pc_wdata[0][0] = ~FlushW ? PCM :
-                               ~FlushM ? PCE :
-                               ~FlushE ? PCD :
-                               ~FlushD ? PCF : PCNextF;
-
-  for(genvar index = 0; index < NUM_REGS; index += 1) begin
-    assign rvvi.x_wdata[0][0][index] = rf[index];
-    assign rvvi.x_wb[0][0][index]    = rf_wb[index];
-  end
-  for(genvar index = 0; index < 32; index += 1) begin
-    assign rvvi.f_wdata[0][0][index] = frf[index];
-    assign rvvi.f_wb[0][0][index]    = frf_wb[index];
-  end
-
-`ifdef FCOV
-  // Interrupts
-  assign rvvi.m_ext_intr[0][0]   = MExtInt;
-  assign rvvi.s_ext_intr[0][0]   = SExtInt;
-  assign rvvi.m_timer_intr[0][0] = MTimerInt;
-  assign rvvi.m_soft_intr[0][0]  = MSwInt;
-`endif
-
-  // *** implementation only cancel? so sc does not clear?
-  assign rvvi.lrsc_cancel[0][0] = 0;
-
-`ifdef FCOV
-  // Virtual Memory signals for verification
-  assign rvvi.virt_adr_i[0][0]     = IVAdrW;
-  assign rvvi.virt_adr_d[0][0]     = DVAdrW;
-  assign rvvi.phys_adr_i[0][0]     = IPAW;
-  assign rvvi.phys_adr_d[0][0]     = DPAW;
-  assign rvvi.read_access[0][0]    = ReadAccessW;
-  assign rvvi.write_access[0][0]   = WriteAccessW;
-  assign rvvi.execute_access[0][0] = ExecuteAccessW;
-  assign rvvi.pte_i[0][0]          = IPTEW;
-  assign rvvi.pte_d[0][0]          = DPTEW;
-  assign rvvi.ppn_i[0][0]          = IPPNW;
-  assign rvvi.ppn_d[0][0]          = DPPNW;
-  assign rvvi.page_type_i[0][0]    = IPageTypeW;
-  assign rvvi.page_type_d[0][0]    = DPageTypeW;
-`endif
-
-  integer index2;
-
-  string  instrWName;
-  int     file;
-  string  LogFile;
-  if(`STD_LOG) begin
-    instrNameDecTB #(P.XLEN) NameDecoder(rvvi.insn[0][0], instrWName);
-    initial begin
-      LogFile = "logs/boottrace.log";
-      file = $fopen(LogFile, "w");
-    end
-  end
-  
-  always_ff @(posedge clk) begin
-    if(valid) begin
-      if(`STD_LOG) begin
-        $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
-        for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
-          if(rvvi.x_wb[0][0][index2]) begin
-            $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
-          end
-        end
-      end
-      for(index2 = 0; index2 < 32; index2 += 1) begin
-        if(rvvi.f_wb[0][0][index2]) begin
-          $fwrite(file, "frf[%02d] = %016x ", index2, rvvi.f_wdata[0][0][index2]);
-        end
-      end
-      for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
-        if(rvvi.csr_wb[0][0][index2]) begin
-          $fwrite(file, "csr[%03x] = %016x ", index2, rvvi.csr[0][0][index2]);
-        end
-      end
-      $fwrite(file, "\n");
-      if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
-        $display("order = %08d, PC = %08x, insn = %08x", rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0]);
-      else if(`PRINT_MOST & !`PRINT_ALL)
-        $display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x", 
-                 rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0], rf_a3, rvvi.x_wdata[0][0][rf_a3], frf_a4, rvvi.f_wdata[0][0][frf_a4], CSRAdrW, rvvi.csr[0][0][CSRAdrW]);
-      else if(`PRINT_ALL) begin
-        $display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x", 
-                 rvvi.order[0][0], rvvi.pc_rdata[0][0], rvvi.insn[0][0], rvvi.trap[0][0], rvvi.halt[0][0], rvvi.intr[0][0], rvvi.mode[0][0], rvvi.ixl[0][0], rvvi.pc_wdata[0][0]);
-        for(index2 = 0; index2 < NUM_REGS; index2 += 1) begin
-          $display("x%02d = %08x", index2, rvvi.x_wdata[0][0][index2]);
-        end
-        for(index2 = 0; index2 < 32; index2 += 1) begin
-          $display("f%02d = %08x", index2, rvvi.f_wdata[0][0][index2]);
-        end
-      end
-      // Need to figure out how to print values on change if they are not in a large array
-      // if (`PRINT_CSRS) begin
-      //   for(index2 = 0; index2 < NUM_CSRS; index2 += 1) begin
-      //     if((rvvi.csr[0][0][index2] != CSRArrayOld[index2])) begin
-      //       $display("%t: CSR %03x = %x", $time(), index2, rvvi.csr[0][0][index2]);
-      //     end
-      //   end
-      // end
-    end
-    if(HaltW) begin
-`ifdef FCOV
-      $display("Functional coverage test complete.");
-`endif
-`ifdef QUESTA
-      $stop;  // if this is changed to $finish for Questa, wally.do does not go to the next step to run coverage and terminates without allowing GUI debug
-`else
-      $finish;
-`endif
-    end
-  end
-endmodule
diff --git a/testbench/common/watchdog.sv b/testbench/common/watchdog.sv
deleted file mode 100644
index f4b02a2e3..000000000
--- a/testbench/common/watchdog.sv
+++ /dev/null
@@ -1,60 +0,0 @@
-///////////////////////////////////////////
-// watchdog.sv
-//
-// Written: Rose Thompson rose@rosethompson.net
-// Modified: 14 June 2023
-//
-// Purpose: Detects if the processor is stuck and halts the simulation
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module watchdog #(parameter XLEN, WatchDogTimerThreshold) 
-  (input clk,
-   input reset,
-   string TEST
-   );
-  
-  // check for hang up.
-  logic [XLEN-1:0]      PCM, PCW, OldPCW;
-  integer               WatchDogTimerCount;
-  logic                 WatchDogTimeOut;
-
-  flopenr #(XLEN) PCMReg(clk, reset, ~dut.core.ifu.StallM, dut.core.ifu.PCE, PCM); // duplicate PCM register because it is not in ifu for all configurations
-  flopenr #(XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, PCM, PCW);
-
-  always_ff @(posedge clk) begin
-    OldPCW <= PCW;
-    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
-    else WatchDogTimerCount = 0;
-  end
-
-  always_comb begin
-    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
-    if(WatchDogTimeOut) begin
-      if (TEST == "buildroot") $display("Watch Dog Time Out triggered.  This is a normal termination for a full buildroot boot.  Check sim/<simulator>/logs/buildroot_uart.log to check if the boot printed the login prompt.");
-      else $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
-      `ifdef QUESTA
-        $stop;  // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
-      `else
-        $finish;
-      `endif
-    end
-  end
-
-endmodule
diff --git a/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py
deleted file mode 100755
index 8beb14adb..000000000
--- a/testbench/sdc/ram2sdLoad.py
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/usr/bin/env python3
-
-import fileinput
-import sys
-
-address = 0
-
-
-with fileinput.input('-') as f:
-    for line in f:
-        # the 14- is to reverse the byte order to little endian
-        formatedLine = ' '.join(line[14-i:14-i+2] for i in range(0, len(line), 2))
-        sys.stdout.write(f'@{address:08x} {formatedLine:s}\n')
-        address+=8
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
deleted file mode 100644
index 3f9f4de7f..000000000
--- a/testbench/testbench.sv
+++ /dev/null
@@ -1,1058 +0,0 @@
-///////////////////////////////////////////
-// testbench.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified:
-//
-// Purpose: Wally Testbench and helper modules
-//          Applies test programs from the riscv-arch-test and other custom tests
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "config.vh"
-`include "tests.vh"
-`include "BranchPredictorType.vh"
-
-`ifdef USE_IMPERAS_DV
-    `include "idv/idv.svh"
-`endif
-
-import cvw::*;
-
-module testbench;
-  /* verilator lint_off WIDTHTRUNC */
-  /* verilator lint_off WIDTHEXPAND */
-  parameter DEBUG=0;
-  parameter PrintHPMCounters=0;
-  parameter BPRED_LOGGER=0;
-  parameter I_CACHE_ADDR_LOGGER=0;
-  parameter D_CACHE_ADDR_LOGGER=0;
-  parameter RVVI_SYNTH_SUPPORTED=0;
-  parameter MAKE_VCD=0;
-
-  // TREK Requires a license for the Breker tool. See tests/breker/README.md for details
-  `ifdef USE_TREK_DV
-    event trek_start;
-    always @(testbench.trek_start) begin
-      trek_uvm_pkg::trek_uvm_events::do_backdoor_init();
-    end
-  `endif
-
-  `ifdef USE_IMPERAS_DV
-    import idvPkg::*;
-    import rvviApiPkg::*;
-    import idvApiPkg::*;
-    `define ENABLE_RVVI_TRACE
-  `endif
-
-  `ifdef FCOV
-    `define ENABLE_RVVI_TRACE
-  `endif
-
-  `ifdef VERILATOR
-      import "DPI-C" function string getenvval(input string env_name);
-      string       RISCV_DIR = getenvval("RISCV");
-      string       WALLY_DIR = getenvval("WALLY"); // ~/cvw typical
-  `elsif VCS
-      import "DPI-C" function string getenv(input string env_name);
-      string       RISCV_DIR = getenv("RISCV");
-      string       WALLY_DIR = getenv("WALLY");
-  `else
-      string       RISCV_DIR = "$RISCV";
-      string       WALLY_DIR = "$WALLY";
-  `endif
-
-  `include "parameter-defs.vh"
-
-  logic        clk;
-  logic        reset_ext, reset;
-  logic        ResetMem;
-
-  // Variables that can be overwritten with $value$plusargs at start of simulation
-  string       TEST, ElfFile;
-  integer      INSTR_LIMIT;
-
-  // DUT signals
-  logic [P.AHBW-1:0]    HRDATAEXT;
-  logic                 HREADYEXT, HRESPEXT;
-  logic [P.PA_BITS-1:0] HADDR;
-  logic [P.AHBW-1:0]    HWDATA;
-  logic [P.XLEN/8-1:0]  HWSTRB;
-  logic                 HWRITE;
-  logic [2:0]           HSIZE;
-  logic [2:0]           HBURST;
-  logic [3:0]           HPROT;
-  logic [1:0]           HTRANS;
-  logic                 HMASTLOCK;
-  logic                 HCLK, HRESETn;
-
-  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
-  logic        UARTSin, UARTSout;
-  logic        SPIIn, SPIOut;
-  logic [3:0]  SPICS;
-  logic        SPICLK;
-  logic        SDCCmd;
-  logic        SDCIn;
-  logic [3:0]  SDCCS;
-  logic        SDCCLK;
-
-  logic        HREADY;
-  logic        HSELEXT;
-
-
-  string  ProgramAddrMapFile, ProgramLabelMapFile;
-  integer ProgramAddrLabelArray [string];
-
-  int test, i, errors, totalerrors;
-
-  string outputfile;
-  integer outputFilePointer;
-
-  string tests[];
-  logic DCacheFlushDone, DCacheFlushStart;
-  logic riscofTest;
-  logic Validate;
-  logic SelectTest;
-  logic TestComplete;
-  logic PrevPCZero;
-  logic RVVIStall;
-
-  initial begin
-    // look for arguments passed to simulation, or use defaults
-    if (!$value$plusargs("TEST=%s", TEST))
-      TEST = "none";
-    if (!$value$plusargs("ElfFile=%s", ElfFile))
-      ElfFile = "none";
-    if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
-      INSTR_LIMIT = 0;
-    //$display("TEST = %s ElfFile = %s", TEST, ElfFile);
-
-    // pick tests based on modes supported
-    //tests = '{};
-    if (P.XLEN == 64) begin // RV64
-      case (TEST)
-        "arch64i":                                tests = arch64i;
-        "arch64priv":                             tests = arch64priv;
-        "arch64c":      if (P.ZCA_SUPPORTED)
-                          if (P.ZICSR_SUPPORTED)  
-                            if (P.ZCD_SUPPORTED)  tests = {arch64c, arch64cpriv, arch64zcd};
-                            else                  tests = {arch64c, arch64cpriv};
-                          else                    tests = {arch64c};
-        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
-        "arch64a_amo":      if (P.ZAAMO_SUPPORTED)        tests = arch64a_amo;
-        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
-        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;
-        "arch64f_fma":  if (P.F_SUPPORTED)        tests = arch64f_fma;
-        "arch64d_fma":  if (P.D_SUPPORTED)        tests = arch64d_fma;
-        "arch64f_divsqrt":  if (P.F_SUPPORTED)        tests = arch64f_divsqrt;
-        "arch64d_divsqrt":  if (P.D_SUPPORTED)        tests = arch64d_divsqrt;
-        "arch64zifencei":  if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
-        "arch64zicond":  if (P.ZICOND_SUPPORTED)  tests = arch64zicond;
-        "wally64q":     if (P.Q_SUPPORTED)        tests = wally64q;
-        "wally64a_lrsc":     if (P.ZALRSC_SUPPORTED)        tests = wally64a_lrsc;
-        "custom":                                 tests = custom;
-        "wally64priv":                            tests = wally64priv;
-        "wally64periph":                          tests = wally64periph;
-        "coremark":                               tests = coremark;
-        "fpga":                                   tests = fpga;
-        "ahb64" :                                 tests = ahb64;
-        "coverage64gc" :                          tests = coverage64gc;
-        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
-        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
-        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
-        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
-        "arch64zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch64zicboz;
-        "arch64zcb":     if (P.ZCB_SUPPORTED)     tests = arch64zcb;
-        "arch64zfh":     if (P.ZFH_SUPPORTED)     
-                           if (P.D_SUPPORTED)     tests = {arch64zfh, arch64zfh_d};
-                           else                   tests = arch64zfh;
-        "arch64zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch64zfh_fma;
-        "arch64zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch64zfh_divsqrt;
-        "arch64zfaf":    if (P.ZFA_SUPPORTED)     tests = arch64zfaf;
-        "arch64zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch64zfad;
-        "buildroot":                              tests = buildroot;
-        "arch64zbkb":    if (P.ZBKB_SUPPORTED)    tests = arch64zbkb;
-        "arch64zbkc":    if (P.ZBKC_SUPPORTED)    tests = arch64zbkc;
-        "arch64zbkx":    if (P.ZBKX_SUPPORTED)    tests = arch64zbkx;
-        "arch64zknd":    if (P.ZKND_SUPPORTED)    tests = arch64zknd;
-        "arch64zkne":    if (P.ZKNE_SUPPORTED)    tests = arch64zkne;
-        "arch64zknh":    if (P.ZKNH_SUPPORTED)    tests = arch64zknh;
-        "arch64pmp":     if (P.PMP_ENTRIES > 0)   tests = arch64pmp;
-      endcase
-    end else begin // RV32
-      case (TEST)
-        "arch32e":                                tests = arch32e;
-        "arch32i":                                tests = arch32i;
-        "arch32priv":                             tests = arch32priv;
-        "arch32c":      if (P.C_SUPPORTED)
-                          if (P.ZICSR_SUPPORTED)  
-                            if (P.ZCF_SUPPORTED)  
-                              if (P.ZCD_SUPPORTED)  tests = {arch32c, arch32cpriv, arch32zcf, arch32zcd};
-                              else                tests = {arch32c, arch32cpriv, arch32zcf};
-                            else                  tests = {arch32c, arch32cpriv};
-                          else                    tests = {arch32c};
-        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
-        "arch32a_amo":      if (P.ZAAMO_SUPPORTED)  tests = arch32a_amo;
-        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
-        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
-        "arch32f_fma":  if (P.F_SUPPORTED)        tests = arch32f_fma;
-        "arch32d_fma":  if (P.D_SUPPORTED)        tests = arch32d_fma;
-        "arch32f_divsqrt":  if (P.F_SUPPORTED)        tests = arch32f_divsqrt;
-        "arch32d_divsqrt":  if (P.D_SUPPORTED)        tests = arch32d_divsqrt;
-        "arch32zifencei":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
-        "arch32zicond":  if (P.ZICOND_SUPPORTED)  tests = arch32zicond;
-        "wally32a_lrsc":     if (P.ZALRSC_SUPPORTED)        tests = wally32a_lrsc;
-        "wally32priv":                            tests = wally32priv;
-        "wally32periph":                          tests = wally32periph;
-        "ahb32" :                                 tests = ahb32;
-        "embench":                                tests = embench;
-        "coremark":                               tests = coremark;
-        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
-        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
-        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
-        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
-        "arch32zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch32zicboz;
-        "arch32zcb":     if (P.ZCB_SUPPORTED)     tests = arch32zcb;
-        "arch32zfh":     if (P.ZFH_SUPPORTED)     
-                           if (P.D_SUPPORTED)     tests = {arch32zfh, arch32zfh_d};
-                           else                   tests = arch32zfh;
-        "arch32zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch32zfh_fma;
-        "arch32zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch32zfh_divsqrt;
-        "arch32zfaf":    if (P.ZFA_SUPPORTED)     tests = arch32zfaf;
-        "arch32zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch32zfad;
-        "arch32zbkb":    if (P.ZBKB_SUPPORTED)    tests = arch32zbkb;
-        "arch32zbkc":    if (P.ZBKC_SUPPORTED)    tests = arch32zbkc;
-        "arch32zbkx":    if (P.ZBKX_SUPPORTED)    tests = arch32zbkx;
-        "arch32zknd":    if (P.ZKND_SUPPORTED)    tests = arch32zknd;
-        "arch32zkne":    if (P.ZKNE_SUPPORTED)    tests = arch32zkne;
-        "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
-        "arch32pmp":     if (P.PMP_ENTRIES > 0)   tests = arch32pmp;
-        "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
-      endcase
-    end
-    if (tests.size() == 0 & ElfFile == "none") begin
-      if (tests.size() == 0) begin
-        $display("TEST %s not supported in this configuration", TEST);
-      end else if(ElfFile == "none") begin
-        $display("ElfFile %s not found", ElfFile);
-      end
-      $finish;
-    end
-    if (MAKE_VCD) begin
-      $dumpfile("testbench.vcd");
-      $dumpvars;
-    end
-  end // initial begin
-
-  // Model the testbench as an fsm.
-  // Do this in parts so it easier to verify
-  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
-  // part 2: drive some of the controls
-  // part 3: drive all logic and remove old inital and always @ negedge clk block
-
-  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
-                           STATE_INIT_TEST,
-                           STATE_RESET_MEMORIES,
-                           STATE_RESET_MEMORIES2,
-                           STATE_LOAD_MEMORIES,
-                           STATE_RESET_TEST,
-                           STATE_RUN_TEST,
-                           STATE_COPY_RAM,
-                           STATE_CHECK_TEST,
-                           STATE_CHECK_TEST_WAIT,
-                           STATE_VALIDATE,
-                           STATE_INCR_TEST} statetype;
-  statetype CurrState, NextState;
-  logic        TestBenchReset;
-  logic [2:0]  ResetCount, ResetThreshold;
-  logic        LoadMem;
-  logic        ResetCntEn;
-  logic        ResetCntRst;
-  logic        CopyRAM;
-
-  string  signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
-  integer begin_signature_addr, end_signature_addr, signature_size;
-  integer uartoutfile;
-
-  assign ResetThreshold = 3'd5;
-
-  initial begin
-    TestBenchReset = 1'b1;
-    # 100;
-    TestBenchReset = 1'b0;
-  end
-
-  always_ff @(posedge clk)
-    if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
-    else CurrState <= NextState;
-
-  // fsm next state logic
-  always_comb begin
-    // riscof tests have a different signature, tests[0] == "0" refers to RiscvArchTests
-    // and tests[0] == "1" refers to WallyRiscvArchTests
-    riscofTest = tests[0] == "0" | tests[0] == "1";
-    pathname = tvpaths[tests[0].atoi()];
-
-    case(CurrState)
-      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
-      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
-      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
-      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
-      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
-      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
-                             else                 NextState = STATE_RUN_TEST;
-      STATE_RUN_TEST:        if(TestComplete)     NextState = STATE_COPY_RAM;
-                             else                 NextState = STATE_RUN_TEST;
-      STATE_COPY_RAM:                             NextState = STATE_CHECK_TEST;
-      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
-                             else                 NextState = STATE_CHECK_TEST_WAIT;
-      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
-                             else                 NextState = STATE_CHECK_TEST_WAIT;
-      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
-      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
-      default:                                    NextState = STATE_TESTBENCH_RESET;
-    endcase
-  end // always_comb
-  // fsm output control logic
-  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
-                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
-                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
-  // this initialization is very expensive, only do it for coremark.
-  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
-  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
-  assign ResetCntRst = CurrState == STATE_INIT_TEST;
-  assign ResetCntEn = CurrState == STATE_RESET_TEST;
-  assign Validate = CurrState == STATE_VALIDATE;
-  assign SelectTest = CurrState == STATE_INIT_TEST;
-  assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST;
-  assign DCacheFlushStart = CurrState == STATE_COPY_RAM;
-
-  // fsm reset counter
-  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Find the test vector files and populate the PC to function label converter
-  ////////////////////////////////////////////////////////////////////////////////
-  logic [P.XLEN-1:0] testadr;
-
-  //VCS ignores the dynamic types while processing the implicit sensitivity lists of always @*, always_comb, and always_latch
-  //procedural blocks. VCS supports the dynamic types in the implicit sensitivity list of always @* block as specified in the Section 9.2 of the IEEE Standard SystemVerilog Specification 1800-2012.
-  //To support memory load and dump task verbosity: flag : -diag sys_task_mem
-  always @(*) begin
-  	begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
- 	end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
-  	signature_size = end_signature_addr - begin_signature_addr;
-  end
-  logic EcallFaultM;
-  if (P.ZICSR_SUPPORTED)
-    assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
-  else
-    assign EcallFaultM = 0;
-
-  always @(posedge clk) begin
-    ////////////////////////////////////////////////////////////////////////////////
-    // Verify the test ran correctly by checking the memory against a known signature.
-    ////////////////////////////////////////////////////////////////////////////////
-    if(TestBenchReset) test = 1;
-    if (P.ZICSR_SUPPORTED & TEST == "coremark")
-      if (EcallFaultM) begin
-        $display("Benchmark: coremark is done.");
-        $stop;
-      end
-    if(SelectTest) begin
-      if (riscofTest) begin
-        memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-        elffilename = {pathname, tests[test], "ref/ref.elf"};
-        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-      end else if(TEST == "buildroot") begin
-        memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
-        elffilename = "buildroot";
-        bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-        uartoutfilename = {"logs/", TEST, "_uart.out"};
-        uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
-        ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
-        ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
-      end else if(TEST == "fpga") begin
-        bootmemfilename = {WALLY_DIR, "/fpga/src/boot.mem"};
-        memfilename = {WALLY_DIR, "/fpga/src/data.mem"};
-        ProgramAddrMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.addr"};
-        ProgramLabelMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.lab"};
-      end else if(ElfFile != "none") begin
-        elffilename = ElfFile;
-        memfilename = {ElfFile, ".memfile"};
-        ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
-        ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
-      end else begin
-        elffilename = {pathname, tests[test], ".elf"};
-        memfilename = {pathname, tests[test], ".elf.memfile"};
-        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-      end
-      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find
-      // the addr of each label and fill the array. To expand, add more elements to this array
-      // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray);
-    end
-    if(Validate) begin
-      if (PrevPCZero) totalerrors = totalerrors + 1; //  error if PC is stuck at zero
-      if (TEST == "buildroot")
-        $fclose(uartoutfile);
-      if (TEST == "embench") begin
-        // Writes contents of begin_signature to .sim.output file
-        // this contains instret and cycles for start and end of test run, used by embench
-        // python speed script to calculate embench speed score.
-        // also, begin_signature contains the results of the self checking mechanism,
-        // which will be read by the python script for error checking
-        $display("Embench Benchmark: %s is done.", tests[test]);
-        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
-        else outputfile = {pathname, tests[test], ".sim.output"};
-        outputFilePointer = $fopen(outputfile, "w");
-        i = 0;
-        testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
-        while ($unsigned(i) < $unsigned(5'd5)) begin
-          $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
-          i = i + 1;
-        end
-        $fclose(outputFilePointer);
-        $display("Embench Benchmark: created output file: %s", outputfile);
-      end else if (TEST == "coverage64gc") begin
-        $display("%s ran. Coverage tests don't get checked", tests[test]);
-      end else if (ElfFile != "none") begin
-        `ifdef USE_TREK_DV
-          $display("Breker test is done.");
-        `elsif FCOV
-          $display("Functional coverage test complete.");
-        `else
-          $display("Single Elf file tests are not signatured verified.");
-        `endif
-`ifdef QUESTA
-        $stop;  // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
-`else
-        $finish;
-`endif
-      end else begin
-        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
-        // clear signature to prevent contamination from previous tests
-        if (!begin_signature_addr)
-          $display("begin_signature addr not found in %s", ProgramLabelMapFile);
-        else if (TEST != "embench") begin
-          CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
-          if(errors > 0) totalerrors = totalerrors + 1;
-        end
-      end
-      test = test + 1;
-      if (test == tests.size()) begin
-        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
-        else $display("FAIL: %d test programs had errors", totalerrors);
-`ifdef QUESTA
-        $stop;  // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
-`else
-        $finish;
-`endif
-      end
-    end
-  end
-
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // load memories with program image
-  ////////////////////////////////////////////////////////////////////////////////
-
-  integer ShadowIndex;
-  integer LogXLEN;
-  integer StartIndex;
-  integer EndIndex;
-  integer BaseIndex;
-  integer memFile, uncoreMemFile;
-  integer readResult;
-  if (P.SDC_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        string romfilename, sdcfilename;
-        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
-        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
-        //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM);
-        //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
-        // shorten sdc timers for simulation
-        //dut.uncoregen.uncore.sdc.SDC.LimitTimers = 1;
-      end
-    end
-  end else if (P.IROM_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-      end
-    end
-  end else if (P.BUS_SUPPORTED) begin : bus_supported
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        if (TEST == "buildroot") begin
-          memFile = $fopen(bootmemfilename, "rb");
-          if (memFile == 0) begin
-            $display("Error: Could not open file %s", memfilename);
-            $finish;
-          end
-          if (P.BOOTROM_SUPPORTED)
-            readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
-          else begin
-            $display("Buildroot test requires BOOTROM_SUPPORTED");
-            $finish;
-          end
-          $fclose(memFile);
-          memFile = $fopen(memfilename, "rb");
-          if (memFile == 0) begin
-            $display("Error: Could not open file %s", memfilename);
-            $finish;
-          end
-          readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
-          $fclose(memFile);
-        end else if (TEST == "fpga") begin
-          memFile = $fopen(bootmemfilename, "rb");
-          if (memFile == 0) begin
-            $display("Error: Could not open file %s", memfilename);
-            $finish;
-          end
-          if (P.BOOTROM_SUPPORTED) begin
-            readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
-          end
-          $fclose(memFile);
-          memFile = $fopen(memfilename, "rb");
-          if (memFile == 0) begin
-            $display("Error: Could not open file %s", memfilename);
-            $finish;
-          end
-          readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
-          $fclose(memFile);
-        end else begin
-          uncoreMemFile = $fopen(memfilename, "r");  // Is there a better way to test if a file exists?
-          if (uncoreMemFile == 0) begin
-            $display("Error: Could not open file %s", memfilename);
-            $finish;
-          end else begin
-            $fclose(uncoreMemFile);
-            $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM);
-            `ifdef USE_TREK_DV
-              -> trek_start;
-              $display("starting Trek....");
-            `endif
-          end
-        end
-        if (TEST == "embench") $display("Read memfile %s", memfilename);
-      end
-      if (CopyRAM) begin
-        LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
-        StartIndex = begin_signature_addr >> LogXLEN;
-        EndIndex = (end_signature_addr >> LogXLEN) + 8;
-        BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
-        for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.ram.RAM[ShadowIndex - BaseIndex];
-        end
-      end
-    end
-  end
-  if (P.DTIM_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM);
-      end
-      if (CopyRAM) begin
-        LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
-        StartIndex = begin_signature_addr >> LogXLEN;
-        EndIndex = (end_signature_addr >> LogXLEN) + 8;
-        BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
-        for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.ram.RAM[ShadowIndex - BaseIndex];
-        end
-      end
-    end
-  end
-
-  integer adrindex;
-  if (P.UNCORE_RAM_SUPPORTED)
-    always @(posedge clk)
-      if (ResetMem)  // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
-        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
-          dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0;
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Actual hardware
-  ////////////////////////////////////////////////////////////////////////////////
-
-  // instantiate device to be tested
-  assign GPIOIN = '0;
-  assign UARTSin = 1'b1;
-  assign SPIIn = 1'b0;
-
-  if(P.EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.P(P), .RANGE(P.EXT_MEM_RANGE))
-    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
-      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
-  end else begin
-    assign HREADYEXT = 1'b1;
-    assign {HRESPEXT, HRDATAEXT} = '0;
-  end
-
-  if(P.SDC_SUPPORTED) begin : sdcard
-    // JP: Add back sd card when sd card AHB implementation done
-    /* -----\/----- EXCLUDED -----\/-----
-    sdModel sdcard
-      (.sdClk(SDCCLK),
-       .cmd(SDCCmd),
-       .dat(SDCDat));
-
-    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
-    assign SDCCmdIn = SDCCmd;
-    assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
-    assign SDCDatIn = SDCDat;
-    -----/\----- EXCLUDED -----/\----- */
-  end else begin
-    assign SDCIn = 1'b1;
-
-  end
-
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall),
-    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
-    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK);
-
-  // generate clock to sequence tests
-  always begin
-    clk = 1'b1; # 5; clk = 1'b0; # 5;
-  end
-
-  if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
-    localparam MAX_CSRS = 5;
-    localparam logic [31:0] RVVI_INIT_TIME_OUT = 32'd4;
-    localparam logic [31:0] RVVI_PACKET_DELAY = 32'd2;
-
-    logic [3:0]                                       mii_txd;
-    logic                                             mii_tx_en, mii_tx_er;
-
-    rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY)
-    rvvitbwrapper(.clk, .reset, .RVVIStall, .mii_tx_clk(clk), .mii_txd, .mii_tx_en, .mii_tx_er,
-                  .mii_rx_clk(clk), .mii_rxd('0), .mii_rx_dv('0), .mii_rx_er('0));
-  end else begin
-    assign RVVIStall = '0;
-  end
-
-
-  /*
-  // Print key info  each cycle for debugging
-  always @(posedge clk) begin
-    #2;
-    $display("PCM: %x  InstrM: %x (%5s) WriteDataM: %x  IEUResultM: %x",
-         dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
-  end
-  */
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Support logic
-  ////////////////////////////////////////////////////////////////////////////////
-
-  // Duplicate copy of pipeline registers that are optimized out of some configurations
-  logic [31:0] NextInstrE, InstrM;
-  mux2    #(32)     FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
-  flopenr #(32)     InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
-
-  // Track names of instructions
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  InstrM, InstrW);
-  instrTrackerTB #(P.XLEN) it(clk, reset, dut.core.ieu.dp.FlushE,
-                dut.core.ifu.InstrRawF[31:0],
-                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
-                InstrM,  InstrW,
-                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
-  // watch for problems such as lockup, reading unitialized memory, bad configs
-  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST);  // check if PCW is stuck
-  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
-                                      dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
-  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
-  loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
-    loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
-
-  // track the current function or global label
-  if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : functionName
-    functionName #(P) functionName(.reset(reset_ext | TestBenchReset),
-            .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
-  end
-
-  // Append UART output to file for tests
-  if (P.UART_SUPPORTED) begin: uart_logger
-    always @(posedge clk) begin
-      if (TEST == "buildroot") begin
-        if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
-          $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); // append characters one at a time so we see a consistent log appearing during the run
-          $fflush(uartoutfile);
-        end
-      end
-    end
-  end
-
-  // Termination condition
-  // Terminate on
-  // 1. jump to self loop (0x0000006f)
-  // 2. a store word writes to the address "tohost"
-  // 3. or PC is stuck at 0
-
-
-  always @(posedge clk) begin
-  //  if (reset) PrevPCZero <= 0;
-  //  else if (dut.core.InstrValidM) PrevPCZero <= (functionName.PCM == 0 & dut.core.ifu.InstrM == 0);
-    TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
-		   ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
-    //   (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
-   // if (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
-    //  $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row.  Usually due to fault with no fault handler.");
-  end
-
-  DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
-
-  if(P.ZICSR_SUPPORTED) begin
-    logic [P.XLEN-1:0] Minstret;
-    assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
-    always @(negedge clk) begin
-      if (INSTR_LIMIT > 0) begin
-        if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
-        if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
-      end
-    end
-end
-
-// RVVI trace for functional coverage and lockstep
-`ifdef ENABLE_RVVI_TRACE
-  rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
-  wallyTracer #(P) wallyTracer(rvvi);
-`endif
-
-// Functional coverage
-`ifdef FCOV
-  cvw_arch_verif cvw_arch_verif(rvvi);
-`endif
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // ImperasDV Co-simulator hooks
-  ////////////////////////////////////////////////////////////////////////////////
-`ifdef USE_IMPERAS_DV
-
-  // enabling of comparison types
-  trace2api #(.CMP_PC      (1),
-              .CMP_INS     (1),
-              .CMP_GPR     (1),
-              .CMP_FPR     (P.F_SUPPORTED),
-              .CMP_VR      (0),
-              .CMP_CSR     (P.ZICSR_SUPPORTED)
-              ) idv_trace2api(rvvi);
-
-  string filename;
-  initial begin
-    // imperasDV requires the elffile be defined at the begining of the simulation.
-    int iter;
-    longint x64;
-    int     x32[2];
-    longint index;
-    string  memfilenameImperasDV, bootmemfilenameImperasDV;
-    #1;
-    IDV_MAX_ERRORS = 3;
-    elffilename = ElfFile;
-
-    // Initialize REF (do this before initializing the DUT)
-    if (!rvviVersionCheck(RVVI_API_VERSION)) begin
-      $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
-      $fatal;
-    end
-
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,            "riscv.ovpworld.org"));
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,              "riscv"));
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,           "RV64GCK"));
-    void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH,     XLEN==64 ? 56 : 34));
-    void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
-
-    if(elffilename == "buildroot") filename = "";
-    else filename = elffilename;
-
-    // use the ImperasDV rvviRefInit to load the reference model with an elf file
-    if(elffilename != "none") begin
-      if (!rvviRefInit(filename)) begin
-        $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
-        $fatal;
-      end
-    end else begin // for buildroot use the binary instead to load the reference model.
-      if (!rvviRefInit("")) begin // still have to call with nothing
-        $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
-        $fatal;
-      end
-
-      memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
-      bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-
-      $display("RVVI Loading bootmem.bin");
-      memFile = $fopen(bootmemfilenameImperasDV, "rb");
-      index = 'h1000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-
-      $display("RVVI Loading ram.bin");
-      memFile = $fopen(memfilenameImperasDV, "rb");
-      index = 'h80000000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("ram  %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-
-      $display("RVVI Loading Complete");
-
-      void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
-    end
-
-    // Volatile CSRs
-    // Counter CSRs
-    if (P.ZICNTR_SUPPORTED) begin
-      void'(rvviRefCsrSetVolatile(0, 32'hC00));   // CYCLE
-      void'(rvviRefCsrSetVolatile(0, 32'hB00));   // MCYCLE
-      void'(rvviRefCsrSetVolatile(0, 32'hC02));   // INSTRET
-      void'(rvviRefCsrSetVolatile(0, 32'hB02));   // MINSTRET
-      void'(rvviRefCsrSetVolatile(0, 32'hC01));   // TIME
-      if (P.XLEN == 32) begin
-        void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
-        void'(rvviRefCsrSetVolatile(0, 32'hB80));   // MCYCLEH
-        void'(rvviRefCsrSetVolatile(0, 32'hC82));   // INSTRETH
-        void'(rvviRefCsrSetVolatile(0, 32'hB82));   // MINSTRETH
-        void'(rvviRefCsrSetVolatile(0, 32'hC81));   // TIMEH
-      end
-      // HPM counters
-      if (P.ZIHPM_SUPPORTED) begin
-        // User HPMCOUNTER3 - HPMCOUNTER31
-        if (P.U_SUPPORTED) begin
-          for (iter='hC03; iter<='hC1F; iter++) begin
-            void'(rvviRefCsrSetVolatile(0, iter));   // HPMCOUNTERx
-            if (P.XLEN == 32)
-              void'(rvviRefCsrSetVolatile(0, iter+128));   // HPMCOUNTERxH
-          end
-        end
-
-        // Machine MHPMCOUNTER3 - MHPMCOUNTER31
-        for (iter='hB03; iter<='hB1F; iter++) begin
-          void'(rvviRefCsrSetVolatile(0, iter));   // MHPMCOUNTERx
-          if (P.XLEN == 32)
-            void'(rvviRefCsrSetVolatile(0, iter+128));   // MHPMCOUNTERxH
-        end
-      end
-    end
-
-    // cannot predict this register due to latency between
-    // pending and taken
-    void'(rvviRefCsrSetVolatile(0, 32'h344));   // MIP
-    if (P.S_SUPPORTED) begin
-      void'(rvviRefCsrSetVolatile(0, 32'h144));   // SIP
-    end
-
-    // Privileges for PMA are set in the imperas.ic
-    // volatile (IO) regions are defined here
-    // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
-    if (P.CLINT_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
-    end
-    if (P.GPIO_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
-    end
-    if (P.UART_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
-    end
-    if (P.PLIC_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
-    end
-    if (P.SDC_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
-    end
-    if (P.SPI_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE)));
-    end
-  end
-
-  if (P.ZICSR_SUPPORTED) begin
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[7]));
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[11])  void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
-    always @(dut.core.priv.priv.csr.csri.MIP_REGW[3])   void'(rvvi.net_push("MSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[3]));
-    if (P.S_SUPPORTED) begin
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[5])   void'(rvvi.net_push("STimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[5]));
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[9])   void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
-      always @(dut.core.priv.priv.csr.csri.MIP_REGW[1])   void'(rvvi.net_push("SSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[1]));
-    end
-  end
-
-  final begin
-    void'(rvviRefShutdown());
-  end
-
-`endif
-  ////////////////////////////////////////////////////////////////////////////////
-  // END of ImperasDV Co-simulator hooks
-  ////////////////////////////////////////////////////////////////////////////////
-
-  task automatic CheckSignature;
-    // This task must be declared inside this module as it needs access to parameter P.  There is
-    // no way to pass P to the task unless we convert it to a module.
-
-    input string  pathname;
-    input string  TestName;
-    input logic   riscofTest;
-    input integer begin_signature_addr;
-    output integer errors;
-    int fd, code;
-    string line;
-    int siglines, sigentries;
-
-    localparam SIGNATURESIZE = 5000000;
-    integer        i;
-    logic [31:0]   sig32[0:SIGNATURESIZE];
-    logic [31:0]   parsed;
-    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
-    string            signame;
-    logic [P.XLEN-1:0] testadr, testadrNoBase;
-
-    //$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time);
-
-    // read .signature.output file and compare to check for errors
-    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
-    else signame = {pathname, TestName, ".signature.output"};
-
-    // read signature file from memory and count lines.  Can't use readmemh because we need the line count
-    // $readmemh(signame, sig32);
-    fd = $fopen(signame, "r");
-    siglines = 0;
-    if (fd == 0) $display("Unable to read %s", signame);
-    else begin
-      while (!$feof(fd)) begin
-        code = $fgets(line, fd);
-        if (code != 0) begin
-          int errno;
-          string errstr;
-          errno = $ferror(fd, errstr);
-          if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
-          if (line.len() > 1) begin // skip blank lines
-            if ($sscanf(line, "%x", parsed) != 0) begin
-              sig32[siglines] = parsed;
-              siglines = siglines + 1; // increment if line is not blank
-            end
-          end
-        end
-      end
-      $fclose(fd);
-    end
-
-    // Check valid number of lines were read
-    if (siglines == 0) begin
-      errors = 1;
-      $display("Error: empty test file %s", signame);
-    end else if (P.XLEN == 64 & (siglines % 2)) begin
-      errors = 1;
-      $display("Error: RV64 signature has odd number of lines %s", signame);
-    end else errors = 0;
-
-    // copy lines into signature, converting to XLEN if necessary
-    sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries
-    for (i=0; i<sigentries; i++) begin
-      signature[i] = (P.XLEN == 32) ? sig32[i] : {sig32[i*2+1], sig32[i*2]};
-      //$display("XLEN = %d signature[%d] = %x", P.XLEN, i, signature[i]);
-    end
-
-    // Check errors
-    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
-    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
-    for (i=0; i<sigentries; i++) begin
-      if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
-        errors = errors+1;
-        $display("  Error on test %s result %d: adr = %h sim (D$) %h signature = %h",
-			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
-        $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
-      end
-    end
-    if (errors) $display("%s failed with %d errors. :(", TestName, errors);
-    else $display("%s succeeded.  Brilliant!!!", TestName);
-  endtask
-
-`ifdef PMP_COVERAGE
-test_pmp_coverage #(P) pmp_inst(clk);
-`endif
-  /* verilator lint_on WIDTHTRUNC */
-  /* verilator lint_on WIDTHEXPAND */
-
-endmodule
-
-/* verilator lint_on STMTDLY */
-/* verilator lint_on WIDTH */
-
-task automatic updateProgramAddrLabelArray;
-  /* verilator lint_off WIDTHTRUNC */
-  /* verilator lint_off WIDTHEXPAND */
-  input string ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR;
-  inout  integer ProgramAddrLabelArray [string];
-  // Gets the memory location of begin_signature
-  integer ProgramLabelMapFP, ProgramAddrMapFP;
-  string cmd;
-
-  // if memfile, label, or addr files are out of date or don't exist, generate them
-  cmd = {"make -s -f ", WALLY_DIR, "/testbench/Makefile ", memfilename, " ", ProgramAddrMapFile};
-  $system(cmd);
-
-  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
-  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
-
-  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
-    ProgramAddrLabelArray["begin_signature"] = 0;
-    ProgramAddrLabelArray["tohost"] = 0;
-    ProgramAddrLabelArray["sig_end_canary"] = 0;
-    while (!$feof(ProgramLabelMapFP)) begin
-      string label, adrstr;
-      integer returncode;
-      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
-      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
-      if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
-    end
-  end
-
-//  if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
-//  if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
-
-  $fclose(ProgramLabelMapFP);
-  $fclose(ProgramAddrMapFP);
-  /* verilator lint_on WIDTHTRUNC */
-  /* verilator lint_on WIDTHEXPAND */
-endtask
-
diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv
deleted file mode 100644
index 48d4a293d..000000000
--- a/testbench/testbench_fp.sv
+++ /dev/null
@@ -1,1394 +0,0 @@
-///////////////////////////////////////////
-//
-// Written: me@KatherineParry.com, james.stine@okstate.edu
-//
-// Purpose: Testbench for UCB Testfloat on Wally
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "config.vh"
-`include "tests_fp.vh"
-
-import cvw::*;
-
-module testbench_fp;
-  // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
-  // to run specific precisions (e.g., quad or all)
-  parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly
-  parameter string TEST_SIZE="all";
-
-  `include "parameter-defs.vh"
-
-  parameter MAXVECTORS = 8388610;
-
-  // FIXME: needs cleaning of unused variables (jes)
-  string       Tests[];                        // list of tests to be run
-  logic [2:0]  OpCtrl[];                       // list of op controls
-  logic [2:0]  Unit[];                         // list of units being tested
-  logic        WriteInt[];                     // Is being written to integer resgiter
-  logic [2:0]  Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
-  logic [1:0]  Fmt[];                          // list of formats for the other units
-
-  logic        clk=0;
-  logic [31:0] TestNum=0;                      // index for the test
-  logic [31:0] OpCtrlNum=0;                    // index for OpCtrl
-  logic [31:0] errors=0;                       // how many errors
-  logic [31:0] VectorNum=0;                    // index for test vector
-  logic [31:0] FrmNum=0;                       // index for rounding mode
-  logic [P.Q_LEN*4+7:0]  TestVectors[MAXVECTORS-1:0]; // list of test vectors
-
-  logic [1:0] FmtVal;                          // value of the current Fmt
-  logic [2:0] UnitVal, OpCtrlVal, FrmVal;      // value of the currnet Unit/OpCtrl/FrmVal
-  logic       WriteIntVal;                     // value of the current WriteInt
-  logic [P.Q_LEN-1:0]  X, Y, Z;                // inputs read from TestFloat
-  logic [P.FLEN-1:0]   XPostBox;               // inputs read from TestFloat
-  logic [P.XLEN-1:0]   SrcA;                   // integer input
-  logic [P.Q_LEN-1:0]  Ans;                    // correct answer from TestFloat
-  logic [P.Q_LEN-1:0]  Res;                    // result from other units
-  logic [4:0] AnsFlg;                          // correct flags read from testfloat
-  logic [4:0] ResFlg, Flg;                     // Result flags
-  logic [P.FMTBITS-1:0] ModFmt;                // format - 10 = half, 00 = single, 01 = double, 11 = quad
-  logic [P.FLEN-1:0]    FpRes, FpCmpRes;       // Results from each unit
-  logic [P.XLEN-1:0]    IntRes, CmpRes;        // Results from each unit
-  logic [P.Q_LEN-1:0]   FpResExtended;         // FpRes extended to same length as Ans/Res
-  logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg;  // Outputed flags
-  logic            AnsNaN, ResNaN, NaNGood;
-  logic            Xs, Ys, Zs;                 // sign of the inputs
-  logic [P.NE-1:0] Xe, Ye, Ze;                 // exponent of the inputs
-  logic [P.NF:0]   Xm, Ym, Zm;                 // mantissas of the inputs
-  logic            XNaN, YNaN, ZNaN;           // is the input NaN
-  logic            XSNaN, YSNaN, ZSNaN;        // is the input a signaling NaN
-  logic            XSubnorm, ZSubnorm;         // is the input denormalized
-  logic            XInf, YInf, ZInf;           // is the input infinity
-  logic            XZero, YZero, ZZero;        // is the input zero
-  logic            XExpMax, YExpMax, ZExpMax;  // is the input's exponent all ones
-  logic [P.CVTLEN-1:0] CvtLzcInE;              // input to the Leading Zero Counter (priority encoder)
-  logic                IntZero;
-  logic                CvtResSgnE;
-  logic [P.NE:0] CvtCalcExpE;                  // the calculated exponent
-  logic [P.LOGCVTLEN-1:0] CvtShiftAmtE;        // how much to shift by
-  logic [P.DIVb:0] Quot;
-  logic CvtResSubnormUfE;
-  logic DivStart;
-  logic FDivBusyE;
-  logic OldFDivBusyE;
-  logic reset = 1'b0;
-  logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt;
-
-  // in-between FMA signals
-  logic Mult;
-  logic Ss;
-  logic [P.NE+1:0] Pe;
-  logic [P.NE+1:0] Se;
-  logic ASticky;
-  logic KillProd;
-  logic [$clog2(P.FMALEN+1)-1:0] SCnt;
-  logic [P.FMALEN-1:0] Sm;
-  logic InvA;
-  logic NegSum;
-  logic As;
-  logic Ps;
-  logic DivSticky;
-  logic DivDone;
-  logic DivNegSticky;
-  logic [P.NE+1:0] DivCalcExp;
-  logic            divsqrtop;
-
-  // Missing logic vectors fdivsqrt
-  logic [2:0] Funct3E;
-  logic [2:0] Funct3M;
-  logic       FlushE;
-  logic       IFDivStartE;
-  logic       FDivDoneE;
-  logic [P.NE+1:0]   UeM;
-  logic [P.DIVb:0]   UmM;
-  logic [P.XLEN-1:0] FIntDivResultM;
-  logic ResMatch;                   // Check if result match
-  logic FlagMatch;                  // Check if IEEE flags match
-  logic CheckNow;                   // Final check
-  logic FMAop;                      // Is this a FMA operation?
-
-  logic [P.NE-2:0]      BiasE;      // Bias of exponent
-  logic [P.LOGFLEN-1:0] NfE;        // Number of fractional bits
-
-  // FSM for testing each item per clock
-  typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
-  statetype state, nextstate;
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  //     ||||||||| |||||||| ||||||| |||||||||   ||||||| |||||||| |||
-  //        |||    |||      |||        |||      |||     |||      |||
-  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||
-  //        |||    |||          |||    |||          ||| |||      |||
-  //        |||    |||||||| |||||||    |||      ||||||| |||||||| |||||||||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // select tests relevent to the specified configuration
-  //    cvtint - test integer conversion unit (fcvtint)
-  //    cvtfp  - test floating-point conversion unit (fcvtfp)
-  //    cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
-  //    add    - test addition
-  //    sub    - test subtraction
-  //    div    - test division
-  //    sqrt   - test square root
-  //    all    - test all of the above < doesn't report errors properly >
-
-  initial begin
-    // Information displayed for user on what is simulating
-    // $display("\nThe start of simulation...");
-    // $display("This simulation for TEST is %s", TEST);
-    // $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
-
-    if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
-      if (TEST === "cvtint" | TEST === "all") begin  // if testing integer conversion
-        // add the 128-bit cvtint tests to the to-be-tested list
-        Tests = {Tests, f128rv32cvtint};
-        // add the op-codes for these tests to the op-code list
-        OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-        // add what unit is used and the fmt to their lists (one for each test)
-        for(int i = 0; i<20; i++) begin
-          Unit = {Unit, `CVTINTUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-        if (P.XLEN == 64) begin // if 64-bit integers are supported add their conversions
-          Tests = {Tests, f128rv64cvtint};
-          // add the op-codes for these tests to the op-code list
-          OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
-          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-          // add what unit is used and the fmt to their lists (one for each test)
-          for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-        end
-      end
-      // if the floating-point conversions are being tested
-      if (TEST === "cvtfp" | TEST === "all") begin
-        if (P.D_SUPPORTED) begin // if double precision is supported
-          // add the 128 <-> 64 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f64cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b01, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-        end
-        if (P.F_SUPPORTED) begin // if single precision is supported
-          // add the 128 <-> 32 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f32cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b00, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-        end
-        if (P.ZFH_SUPPORTED) begin // if half precision is supported
-          // add the 128 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f128f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b11};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b11};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested
-        // add the compare tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "add" | TEST === "all") begin // if addition is being tested
-        // add the addition tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested
-        // add the subtraction tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
-        // add the multiply tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "div" | TEST === "all") begin // if division is being tested
-        // add the divide tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested
-        // add the square-root tests/op-ctrls/unit/fmt
-        Tests = {Tests, f128sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-      if (TEST === "fma" | TEST === "all") begin  // if fused-mutliply-add is being tested
-        Tests = {Tests, f128fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b11};
-        end
-      end
-    end
-    if (P.D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported
-      if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested
-        Tests = {Tests, f64rv32cvtint};
-        // add the op-codes for these tests to the op-code list
-        OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-        // add what unit is used and the fmt to their lists (one for each test)
-        for(int i = 0; i<20; i++) begin
-          Unit = {Unit, `CVTINTUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-        if (P.XLEN == 64) begin // if 64-bit integers are being supported
-          Tests = {Tests, f64rv64cvtint};
-          // add the op-codes for these tests to the op-code list
-          OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
-          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-          // add what unit is used and the fmt to their lists (one for each test)
-          for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-        end
-      end
-      if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
-        if (P.F_SUPPORTED) begin // if single precision is supported
-          // add the 64 <-> 32 bit conversions to the to-be-tested list
-          Tests = {Tests, f64f32cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b00, 3'b01};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-        end
-        if (P.ZFH_SUPPORTED) begin // if half precision is supported
-          // add the 64 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f64f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b01};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b01};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "add" | TEST === "all") begin // if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "sub" | TEST === "all") begin // if subtration is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "div" | TEST === "all") begin // if division is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f64sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-      if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested
-        Tests = {Tests, f64fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b01};
-        end
-      end
-    end
-    if (P.F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported
-      if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
-        Tests = {Tests, f32rv32cvtint};
-        // add the op-codes for these tests to the op-code list
-        OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-        // add what unit is used and the fmt to their lists (one for each test)
-        for(int i = 0; i<20; i++) begin
-          Unit = {Unit, `CVTINTUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-        if (P.XLEN == 64) begin // if 64-bit integers are supported
-          Tests = {Tests, f32rv64cvtint};
-          // add the op-codes for these tests to the op-code list
-          OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
-          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-          // add what unit is used and the fmt to their lists (one for each test)
-          for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-        end
-      end
-      if (TEST === "cvtfp" | TEST === "all") begin  // if floating point conversion is being tested
-        if (P.ZFH_SUPPORTED) begin
-          // add the 32 <-> 16 bit conversions to the to-be-tested list
-          Tests = {Tests, f32f16cvt};
-          // add the op-ctrls (i.e. the format of the result)
-          OpCtrl = {OpCtrl, 3'b10, 3'b00};
-          WriteInt = {WriteInt, 1'b0, 1'b0};
-          // add the unit being tested and fmt (input format)
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `CVTFPUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "add" | TEST === "all") begin // if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "sub" | TEST === "all") begin // if subtration is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "mul" | TEST === "all") begin // if multiply is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-    if (TEST === "div" | TEST === "all") begin // if division is being tested
-      // add the correct tests/op-ctrls/unit/fmt to their lists
-      Tests = {Tests, f32div};
-      OpCtrl = {OpCtrl, `DIV_OPCTRL};
-      WriteInt = {WriteInt, 1'b0};
-      for(int i = 0; i<5; i++) begin
-        Unit = {Unit, `DIVUNIT};
-        Fmt = {Fmt, 2'b00};
-      end
-    end
-      if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f32sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b00};
-        end
-      end
-      if (TEST === "fma" | TEST === "all")  begin // if fma is being tested
-          Tests = {Tests, f32fma};
-          OpCtrl = {OpCtrl, `FMA_OPCTRL};
-          WriteInt = {WriteInt, 1'b0};
-          for(int i = 0; i<5; i++) begin
-            Unit = {Unit, `FMAUNIT};
-            Fmt = {Fmt, 2'b00};
-          end
-      end
-    end
-    if (P.ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported
-      if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested
-        Tests = {Tests, f16rv32cvtint};
-        // add the op-codes for these tests to the op-code list
-        OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-        // add what unit is used and the fmt to their lists (one for each test)
-        for(int i = 0; i<20; i++) begin
-          Unit = {Unit, `CVTINTUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-        if (P.XLEN == 64) begin // if 64-bit integers are supported
-          Tests = {Tests, f16rv64cvtint};
-          // add the op-codes for these tests to the op-code list
-          OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
-          WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
-          // add what unit is used and the fmt to their lists (one for each test)
-          for(int i = 0; i<20; i++) begin
-            Unit = {Unit, `CVTINTUNIT};
-            Fmt = {Fmt, 2'b10};
-          end
-        end
-      end
-      if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16cmp};
-        OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0};
-        for(int i = 0; i<15; i++) begin
-          Unit = {Unit, `CMPUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "add" | TEST === "all") begin //  if addition is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16add};
-        OpCtrl = {OpCtrl, `ADD_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16sub};
-        OpCtrl = {OpCtrl, `SUB_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16mul};
-        OpCtrl = {OpCtrl, `MUL_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "div" | TEST === "all") begin // if division is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16div};
-        OpCtrl = {OpCtrl, `DIV_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested
-        // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16sqrt};
-        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `DIVUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-      if (TEST === "fma" | TEST === "all") begin // if fma is being tested
-        Tests = {Tests, f16fma};
-        OpCtrl = {OpCtrl, `FMA_OPCTRL};
-        WriteInt = {WriteInt, 1'b0};
-        for(int i = 0; i<5; i++) begin
-          Unit = {Unit, `FMAUNIT};
-          Fmt = {Fmt, 2'b10};
-        end
-      end
-    end
-    // check if nothing is being tested
-    if (Tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
-`ifdef QUESTA
-      $stop;  // if this is changed to $finish for Questa, wally.do terminates without allowing GUI debug
-`else
-      $finish;
-`endif
-    end
-  end
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  //     ||||||||| |||||||| ||||||||| |||||||     ||||||||| |||||||| ||||||| |||||||||
-  //     |||   ||| |||      |||   ||| ||   ||        |||    |||      |||        |||
-  //     ||||||||  |||||||| ||||||||| ||   ||        |||    |||||||| |||||||    |||
-  //     |||  ||   |||      |||   ||| ||   ||        |||    |||          |||    |||
-  //     |||   ||| |||||||| |||   ||| |||||||        |||    |||||||| |||||||    |||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // Read the first test
-  initial begin
-    static string pp = `PATH;
-    string testname;
-    string tt0;
-    tt0 = $sformatf("%s", Tests[TestNum]);
-    testname = {pp, tt0};
-    //$display("Here you are %s", testname);
-    // clear the vectors
-    for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = '1;
-    $display("\n\nRunning %s vectors ", Tests[TestNum]);
-    $readmemh(testname, TestVectors);
-    // set the test index to 0
-    TestNum = 0;
-  end
-
-  // set the signals for all tests
-  always_ff @(posedge clk) begin
-    UnitVal = Unit[TestNum];
-    FmtVal = Fmt[TestNum];
-    OpCtrlVal = OpCtrl[OpCtrlNum];
-    WriteIntVal = WriteInt[OpCtrlNum];
-    FrmVal = Frm[FrmNum];
-  end
-
-  // modify the format signal if only 2 precisions supported
-  //    - 1 for the larger precision
-  //    - 0 for the smaller precision
-  always_comb begin
-    if (P.FMTBITS == 1) ModFmt = {1'b0, FmtVal == P.FMT};
-    else ModFmt = FmtVal;
-  end
-
-  // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
-  readvectors #(P) readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
-                                .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
-                                .Xs, .Ys, .Zs, .Unit(UnitVal),
-                                .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
-                                .Xm, .Ym, .Zm,
-                                .XNaN, .YNaN, .ZNaN,
-                                .XSNaN, .YSNaN, .ZSNaN,
-                                .XSubnorm, .ZSubnorm,
-                                .XZero, .YZero, .ZZero,
-                                .XInf, .YInf, .ZInf, .XExpMax,
-                                .X, .Y, .Z, .XPostBox, .NfE, .BiasE);
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  //     |||||||   |||   ||| |||||||||
-  //     |||   ||| |||   |||    |||
-  //     |||   ||| |||   |||    |||
-  //     |||   ||| |||   |||    |||
-  //     |||||||   |||||||||    |||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // instantiate devices under test
-  if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
-    fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
-      .Xe(Xe), .Ye(Ye), .Ze(Ze),
-      .Xm(Xm), .Ym(Ym), .Zm(Zm),
-      .XZero, .YZero, .ZZero, .Ss, .Se,
-      .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps,
-      .ASticky);
-  end
-
-  postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
-    .OpCtrl(OpCtrlVal), .DivUm(Quot), .DivUe(DivCalcExp),
-    .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
-    .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
-    .XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
-    .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
-    .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
-    .FmaASticky(ASticky), .FmaSe(Se),
-    .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
-    .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes), .Zfa(1'b0));
-
-  if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
-    fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal),
-      .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero,
-      .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE),
-      .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE));
-  end
-
-  if (TEST === "cmp" | TEST === "all") begin: fcmp
-    fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Zfa(1'b0), .Xs, .Ys, .Xe, .Ye,
-      .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
-      .XNaN, .YNaN, .XSNaN, .YSNaN, .X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
-  end
-
-  if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
-    fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
-      .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
-      .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
-      .XNaNE(XNaN), .YNaNE(YNaN), .NfE, .BiasE,
-      .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
-      .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .UeM(DivCalcExp),
-      .UmM(Quot),
-      .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
-      .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
-      .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
-  end
-
-  assign CmpFlg[3:0] = 0;
-
-  // produce clock
-  always begin
-    clk = 1; #5; clk = 0; #5;
-  end
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  //          |||||      |||  ||||||||||  |||||      |||
-  //          |||||||    |||  |||    |||  |||||||    |||
-  //          |||| |||   |||  ||||||||||  |||| |||   |||
-  //          ||||  |||  |||  |||    |||  ||||  |||  |||
-  //          ||||   ||| |||  |||    |||  ||||   ||| |||
-  //          ||||    ||||||  |||    |||  ||||    ||||||
-
-  ///////////////////////////////////////////////////////////////////////////////////////////////
-
-  // Check if the correct answer and result is a NaN
-  always_comb begin
-    if (UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
-      // an integer output can't be a NaN
-      AnsNaN = 1'b0;
-      ResNaN = 1'b0;
-    end else if (UnitVal === `CVTFPUNIT) begin
-      case (OpCtrlVal[1:0])
-        2'b11: begin // quad
-          AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]);
-          ResNaN = &Res[P.Q_LEN-2:P.NF]&(|Res[P.Q_NF-1:0]);
-        end
-        2'b01: begin // double
-          AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
-          ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
-        end
-        2'b00: begin // single
-          AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
-          ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
-        end
-        2'b10: begin // half
-          AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
-          ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
-        end
-      endcase
-    end else begin
-      case (FmtVal)
-        2'b11: begin // quad
-          AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]);
-          ResNaN = &Res[P.Q_LEN-2:P.Q_NF]&(|Res[P.Q_NF-1:0]);
-        end
-        2'b01: begin // double
-          AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]);
-          ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]);
-        end
-        2'b00: begin // single
-          AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]);
-          ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]);
-        end
-        2'b10: begin // half
-          AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]);
-          ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
-        end
-      endcase
-    end
-  end
-
-  always_comb begin
-    FpResExtended = {{(P.Q_LEN-P.FLEN){1'b1}}, FpRes};
-    // select the result to check
-    case (UnitVal)
-      `FMAUNIT: Res = FpResExtended;
-      `DIVUNIT: Res = FpResExtended;
-      `CMPUNIT: Res = {{(Q_LEN-XLEN){1'b0}}, CmpRes};
-      `CVTINTUNIT: if (WriteIntVal) Res = {{(Q_LEN-XLEN){1'b0}}, IntRes}; else Res = FpResExtended;
-      `CVTFPUNIT: Res = FpResExtended;
-    endcase
-
-    // select the flag to check
-    case (UnitVal)
-      `FMAUNIT: ResFlg = Flg;
-      `DIVUNIT: ResFlg = Flg;
-      `CMPUNIT: ResFlg = CmpFlg;
-      `CVTINTUNIT: ResFlg = Flg;
-      `CVTFPUNIT: ResFlg = Flg;
-    endcase
-
-    // Use four state test sequence to handle div properly.
-    // Four states should allow other operations to finish
-    // properly and within time.
-    case (state)
-      S0: begin
-        DivStart = 1'b0;
-        nextstate = Start;
-      end
-      Start: begin
-        if (UnitVal == `DIVUNIT)
-          DivStart = 1'b1;
-        else
-          DivStart = 1'b0;
-        nextstate = S2;
-      end
-      S2: begin
-        DivStart = 1'b0;
-        if ((FDivBusyE|~DivDone)&(UnitVal == `DIVUNIT))
-          nextstate = S2;
-        else
-          nextstate = Done;
-      end
-      Done: begin
-        DivStart = 1'b0;
-        nextstate = S0;
-      end
-      default: begin
-        DivStart = 1'b0;
-        nextstate = S0;
-      end
-    endcase // case (state)
-  end
-
-  // Provide reset for divsqrt to reset state
-  initial
-    begin
-      #0  reset = 1'b1;
-      #25 reset = 1'b0;
-    end
-
-  // Left-over from before - will remove soon
-  always @(posedge clk)
-    OldFDivBusyE = FDivDoneE;
-
-  // state machine to handle timing for testing due
-  // various cycle counts for different fp/int operations
-  // Adds vector at start of clock
-  always @(posedge clk) begin
-    // state machine element for testing
-    if (reset)
-      state <= S0;
-    else
-      state <= nextstate;
-    // Increment the vector when Done with each test
-    if (state == Done) begin
-      VectorNum += 1; // increment the vector
-    end
-  end
-
-  // check results on falling edge of clk
-  always @(negedge clk) begin
-    // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
-    //    - the sign of the NaN does not matter for the opperations being tested
-    //    - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
-    if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
-      case (FmtVal)
-        2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
-                          (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
-                          (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) |
-                          (ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]})));
-        2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
-                          (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
-                          (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) |
-                          (ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]})));
-        2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
-                          (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
-                          (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) |
-                          (ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]})));
-        2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
-                          (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
-                          (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
-                          (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
-      endcase
-    else if (UnitVal === `CVTFPUNIT) // if converting from FP to FP OpCtrl contains the final FP format
-      case (OpCtrlVal[1:0])
-        2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
-                          (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
-                          (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})));
-        2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) |
-                          (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) |
-                          (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})));
-        2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) |
-                          (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) |
-                          (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})));
-        2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
-                          (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) |
-                          (AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
-                          (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
-                          (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
-      endcase
-    else NaNGood = 1'b0; // integers can't be NaNs
-
-    ///////////////////////////////////////////////////////////////////////////////////////////////
-
-    //     ||||||| |||    ||| ||||||| ||||||| |||   |||
-    //     |||     |||    ||| |||     |||     |||  |||
-    //     |||     |||||||||| ||||||| |||     ||||||
-    //     |||     |||    ||| |||     |||     |||  |||
-    //     ||||||| |||    ||| ||||||| ||||||| |||    |||
-
-    ///////////////////////////////////////////////////////////////////////////////////////////////
-
-    // check if result is correct
-    assign ResMatch = ((Res[P.FLEN-1:0] === Ans[P.FLEN-1:0]) | NaNGood | (NaNGood === 1'bx));
-    assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
-    assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
-    assign FMAop = (OpCtrlVal == `FMAUNIT);
-    assign DivDone = OldFDivBusyE & ~FDivBusyE;
-    assign CheckNow = ((DivDone | ~divsqrtop) |
-      (TEST == "add" | TEST == "fma" | TEST == "sub") |
-      ((TEST == "all") & (DivDone | ~divsqrtop)));
-
-    if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin
-      errors += 1;
-      $display("\nError in %s", Tests[TestNum]);
-      $display("TestNum %d VectorNum %d OpCtrl %d", TestNum, VectorNum, OpCtrl[TestNum]);
-      $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h",
-        X[P.FLEN-1:0], Y[P.FLEN-1:0], Z[P.FLEN-1:0], SrcA, Res[P.FLEN-1:0], ResFlg, Ans[P.FLEN-1:0], AnsFlg);
-      //$display("  fma.Xs %h Xe %h Xm %h Ys %h Ye %h Ym %h Ss %h Se %h Sm %h", fma.Xs, fma.Xe, fma.Xm, fma.Ys, fma.Ye, fma.Ym, fma.Ss, fma.Se, fma.Sm);
-      //$display("  readvectors.unpack.X %h Xs %h Xe %h Xm %h", readvectors.unpack.X, readvectors.unpack.Xs, readvectors.unpack.Xe, readvectors.unpack.Xm);
-`ifdef QUESTA
-      $stop;  // if this is changed to $finish for Questa, wally.do terminates without allowing GUI debug
-`else
-      $finish;
-`endif
-    end
-
-    if (TestVectors[VectorNum] == '1 & Tests[TestNum] !== "") begin // if reached the eof
-      // increment the test
-      TestNum += 1;
-      // clear the vectors
-      for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = '1;
-      // read next files
-      $readmemh({`PATH, Tests[TestNum]}, TestVectors);
-      // set the vector index back to 0
-      VectorNum = 0;
-      // incemet the operation if all the rounding modes have been tested
-      if (FrmNum === 4) OpCtrlNum += 1;
-      // increment the rounding mode or loop back to rne
-      if (FrmNum < 4) FrmNum += 1;
-      else begin
-        FrmNum = 0;
-        // Add some time as a buffer between tests at the end of each test
-        // (to be removed, but as of 7/14/24 breaks Verilator sqrt sim to remove dh)
-        repeat (10)
-          @(posedge clk);
-      end
-      // if no more Tests - finish
-      if (Tests[TestNum] === "") begin
-        $display("\nAll Tests completed with %d errors\n", errors);
-`ifdef QUESTA
-        $stop;  // if this is changed to $finish for Questa, wally.do terminates without allowing GUI debug
-`else
-        $finish;
-`endif
-      end
-      $display("Running %s vectors", Tests[TestNum]);
-    end
-  end
-endmodule
-
-
-module readvectors import cvw::*; #(parameter cvw_t P) (
-  input  logic clk,
-  input  logic [P.Q_LEN*4+7:0] TestVector,
-  input  logic [P.FMTBITS-1:0] ModFmt,
-  input  logic [1:0]  Fmt,
-  input  logic [2:0]  Unit,
-  input  logic [31:0] VectorNum,
-  input  logic [31:0] TestNum,
-  input  logic [2:0]  OpCtrl,
-  output logic [P.Q_LEN-1:0] Ans,
-  output logic [P.XLEN-1:0]  SrcA,
-  output logic [4:0] AnsFlg,
-  output logic            Xs, Ys, Zs,          // sign bits of XYZ
-  output logic [P.NE-1:0] Xe, Ye, Ze,          // exponents of XYZ (converted to largest supported precision)
-  output logic [P.NF:0]   Xm, Ym, Zm,          // mantissas of XYZ (converted to largest supported precision)
-  output logic            XNaN, YNaN, ZNaN,    // is XYZ a NaN
-  output logic            XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
-  output logic            XSubnorm, ZSubnorm,  // is XYZ denormalized
-  output logic            XZero, YZero, ZZero, // is XYZ zero
-  output logic            XInf, YInf, ZInf,    // is XYZ infinity
-  output logic            XExpMax,
-  output logic [P.Q_LEN-1:0]   X, Y, Z,
-  output logic [P.FLEN-1:0]    XPostBox,
-  output logic [P.NE-2:0]      BiasE,          // Bias of exponent
-  output logic [P.LOGFLEN-1:0] NfE             // Number of fractional bits
-);
-
-  localparam Q_LEN = 32'd128;
-
-  logic XEn;
-  logic YEn;
-  logic ZEn;
-  logic FPUActive;
-
-  // apply test vectors on rising edge of clk
-  // Format of vectors Inputs(1/2/3)_AnsFlg
-  always @(posedge clk) begin
-    AnsFlg = TestVector[4:0];
-    //$display("  Entering readvectors with VectorNum=%d, TestVector=%x, Unit=%d, Fmt=%d, OpCtrl=%d", VectorNum, TestVector, Unit, Fmt, OpCtrl); */
-    case (Unit)
-      `FMAUNIT:
-        case (Fmt)
-          2'b11:  if (P.Q_SUPPORTED) begin // quad
-                    if (OpCtrl === `FMA_OPCTRL) begin
-                      X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
-                      Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
-                      Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN];
-                    end else begin
-                      X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
-                      if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
-                      else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
-                      if (OpCtrl === `MUL_OPCTRL) Z = 0;
-                      else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
-                    end
-                    Ans = TestVector[8+(P.Q_LEN-1):8];
-                  end
-          2'b01:  if (P.D_SUPPORTED) begin // double
-                    if (OpCtrl === `FMA_OPCTRL) begin
-                      X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
-                      Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
-                      Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
-                    end else begin
-                      X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
-                      if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
-                      else Y = {{P.Q_LEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
-                      if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
-                      else Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
-                    end
-                    Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-                  end
-          2'b00:  if (P.F_SUPPORTED) begin // single
-                    if (OpCtrl === `FMA_OPCTRL) begin
-                      X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
-                      Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
-                      Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
-                    end else begin
-                      X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
-                      if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
-                      else Y = {{P.Q_LEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
-                      if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
-                      else Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
-                    end
-                    Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-                  end
-          2'b10:  begin // half
-                    if (OpCtrl === `FMA_OPCTRL) begin
-                      X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
-                      Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
-                      Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
-                    end else begin
-                      X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
-                      if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
-                      else Y = {{P.Q_LEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
-                      if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
-                      else Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
-                    end
-                    Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-                  end
-        endcase
-      `DIVUNIT:
-        if (OpCtrl[0])
-          case (Fmt)
-            2'b11: begin // quad
-              X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
-              Ans = TestVector[8+(P.Q_LEN-1):8];
-            end
-            2'b01: if (P.D_SUPPORTED) begin // double
-              X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
-              Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-            end
-            2'b00: if (P.F_SUPPORTED) begin // single
-              X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
-              Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-            end
-            2'b10: begin // half
-              X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
-              Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-            end
-          endcase
-        else
-          case (Fmt)
-            2'b11: begin // quad
-              X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
-              Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
-              Ans = TestVector[8+(P.Q_LEN-1):8];
-            end
-            2'b01: if (P.D_SUPPORTED) begin // double
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
-                Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-            end
-            2'b00: if (P.F_SUPPORTED) begin // single
-              X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
-              Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
-              Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-            end
-            2'b10: begin // half
-              X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
-              Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
-              Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-            end
-          endcase
-      `CMPUNIT:
-        case (Fmt)
-          2'b11: begin // quad
-            X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
-            Y = TestVector[12+(P.Q_LEN)-1:12];
-            Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
-          end
-          2'b01: if (P.D_SUPPORTED) begin // double
-            X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
-            Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
-            Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
-          end
-          2'b00: if (P.F_SUPPORTED) begin // single
-            X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
-            Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
-            Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
-          end
-          2'b10: begin // half
-            X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
-            Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
-            Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
-          end
-        endcase
-      `CVTFPUNIT:
-        case (Fmt)
-          2'b11: begin // quad
-            case (OpCtrl[1:0])
-              2'b11: begin // quad
-                X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b01: if (P.D_SUPPORTED) begin // double
-                X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b00: begin // single
-                X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b10: begin // half
-                X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-            endcase
-          end
-          2'b01: if (P.D_SUPPORTED) begin // double
-            case (OpCtrl[1:0])
-              2'b11: begin // quad
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b01: begin // double
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b00: begin // single
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b10: begin // half
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-            endcase
-          end
-          2'b00: if (P.F_SUPPORTED) begin // single
-            case (OpCtrl[1:0])
-              2'b11: begin // quad
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b01: if (P.D_SUPPORTED) begin // double
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b00: begin // single
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b10: begin // half
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-            endcase
-          end
-          2'b10: begin // half
-            case (OpCtrl[1:0])
-              2'b11: begin // quad
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b01: if (P.D_SUPPORTED) begin // double
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b00: if (P.F_SUPPORTED) begin // single
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b10: begin // half
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-            endcase
-          end
-        endcase
-      `CVTINTUNIT:
-        case (Fmt)
-          2'b11: begin // quad
-            // {is the integer a long, is the opperation to an integer}
-            casez ({OpCtrl[2:1]})
-              2'b11: begin // long -> quad
-                X = {P.Q_LEN{1'bx}};
-                SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b10: begin // int -> quad
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {P.Q_LEN{1'bx}};
-                SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
-                Ans = TestVector[8+(P.Q_LEN-1):8];
-              end
-              2'b01: begin // quad -> long
-                X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
-              end
-              2'b00: begin // quad -> int
-                X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b01: if (P.D_SUPPORTED) begin // double
-            // {Int->Fp?, is the integer a long}
-            casez ({OpCtrl[2:1]})
-              2'b11: begin // long -> double
-                X = {P.Q_LEN{1'bx}};
-                SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b10: begin // int -> double
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {P.Q_LEN{1'bx}};
-                SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
-                Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
-              end
-              2'b01: begin // double -> long
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
-              end
-              2'b00: begin // double -> int
-                X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b00: if (P.F_SUPPORTED) begin // single
-            // {is the integer a long, is the opperation to an integer}
-            casez ({OpCtrl[2:1]})
-              2'b11: begin // long -> single
-                X = {P.Q_LEN{1'bx}};
-                SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b10: begin // int -> single
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {P.Q_LEN{1'bx}};
-                SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
-                Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
-              end
-              2'b01: begin // single -> long
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
-              end
-              2'b00: begin // single -> int
-                X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-          2'b10: begin // half
-            // {is the integer a long, is the opperation to an integer}
-            casez ({OpCtrl[2:1]})
-              2'b11: begin // long -> half
-                X = {P.Q_LEN{1'bx}};
-                SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-              2'b10: begin // int -> half
-                // correctly sign extend the integer depending on if it's a signed/unsigned test
-                X = {P.Q_LEN{1'bx}};
-                SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
-                Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
-              end
-              2'b01: begin // half -> long
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
-              end
-              2'b00: begin // half -> int
-                X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
-                SrcA = {P.XLEN{1'bx}};
-                Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
-              end
-            endcase
-          end
-        endcase
-    endcase
-  end
-
-  assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
-  assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
-  assign ZEn = (Unit == `FMAUNIT);
-  assign FPUActive = 1'b1;
-
-  unpack #(P) unpack(.X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .Z(Z[P.FLEN-1:0]), .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
-                     .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
-                     .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
-                     .XEn, .YEn, .ZEn, .XExpMax, .XPostBox, .Bias(BiasE), .Nf(NfE));
-endmodule
diff --git a/testbench/tests.vh b/testbench/tests.vh
deleted file mode 100644
index 46911dca5..000000000
--- a/testbench/tests.vh
+++ /dev/null
@@ -1,3619 +0,0 @@
-///////////////////////////////////////////
-// tests.vh
-//
-// Written: David_Harris@hmc.edu 7 October 2021
-// Modified:
-//
-// Purpose: List of tests to apply
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`define RISCVARCHTEST "0"
-`define WALLYTEST "1"
-`define COREMARK "2"
-`define EMBENCH "3"
-`define CUSTOM "4"
-`define COVERAGE "5"
-`define BUILDROOT "6"
-
-string tvpaths[] = '{
-  "../../tests/riscof/work/riscv-arch-test/",
-  "../../tests/riscof/work/wally-riscv-arch-test/",
-  "../../benchmarks/coremark/work/",
-  "../../addins/embench-iot/",
-  "../../tests/custom/work/",
-  "../../tests/coverage/"
-};
-
-string coverage64gc[] = '{
-  `COVERAGE,
-  "ieu",
-  "priv",
-  "ebu",
-  "csrwrites",
-  "ifu",
-  "fpu",
-  "lsu",
-  "vm64check",
-  "tlbmisc",
-  "tlbNAPOT",
-  "tlbASID",
-  "tlbGLB",
-  "tlbMP",
-  "tlbGP",
-  "tlbTP",
-  "tlbMisaligned",
-  "hptwAccessFault",
-  "nonleafpbmtfault",
-  "amoAccessFault",
-  "floatmisc",
-  "ifuCamlineWrite",
-  "dcache1",
-  "dcache2",
-  "pmp",
-  "pmpcfg",
-  "pmpcfg1",
-  "pmpcfg2",
-  "pmppriority",
-  "pmpcbo",
-  "pmpadrdecs",
-  "btbthrash"
-};
-
-string buildroot[] = '{
-  `BUILDROOT,
-  "buildroot"
-};
-
-string coremark[] = '{
-  `COREMARK,
-  "coremark.bare.riscv"
-};
-
-string embench[] = '{
-  `EMBENCH,
-  "bd_speedopt_speed/src/aha-mont64/aha-mont64",
-  "bd_speedopt_speed/src/crc32/crc32",
-  "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
-  "bd_speedopt_speed/src/edn/edn",
-  "bd_speedopt_speed/src/huffbench/huffbench",
-  "bd_speedopt_speed/src/matmult-int/matmult-int",
-  "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
-  "bd_speedopt_speed/src/minver/minver",
-  "bd_speedopt_speed/src/nettle-aes/nettle-aes",
-  "bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
-  "bd_speedopt_speed/src/nsichneu/nsichneu",
-  "bd_speedopt_speed/src/nbody/nbody",
-  "bd_speedopt_speed/src/picojpeg/picojpeg",
-  "bd_speedopt_speed/src/primecount/primecount",
-  "bd_speedopt_speed/src/qrduino/qrduino",
-  "bd_speedopt_speed/src/sglib-combined/sglib-combined",
-  "bd_speedopt_speed/src/slre/slre",
-  "bd_speedopt_speed/src/st/st",
-  "bd_speedopt_speed/src/statemate/statemate",
-  "bd_speedopt_speed/src/tarfind/tarfind",
-  "bd_speedopt_speed/src/ud/ud",
-  "bd_speedopt_speed/src/wikisort/wikisort",
-  "bd_sizeopt_speed/src/aha-mont64/aha-mont64",
-  "bd_sizeopt_speed/src/crc32/crc32",
-  "bd_sizeopt_speed/src/cubic/cubic",
-  "bd_sizeopt_speed/src/edn/edn",
-  "bd_sizeopt_speed/src/huffbench/huffbench",
-  "bd_sizeopt_speed/src/matmult-int/matmult-int",
-  "bd_sizeopt_speed/src/md5sum/md5sum",
-  "bd_sizeopt_speed/src/minver/minver",
-  "bd_sizeopt_speed/src/nbody/nbody",
-  "bd_sizeopt_speed/src/nettle-aes/nettle-aes",
-  "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256",
-  "bd_sizeopt_speed/src/nsichneu/nsichneu",
-  "bd_sizeopt_speed/src/picojpeg/picojpeg",
-  "bd_sizeopt_speed/src/primecount/primecount",
-  "bd_sizeopt_speed/src/qrduino/qrduino",
-  "bd_sizeopt_speed/src/sglib-combined/sglib-combined",
-  "bd_sizeopt_speed/src/slre/slre",
-  "bd_sizeopt_speed/src/st/st",
-  "bd_sizeopt_speed/src/statemate/statemate",
-  "bd_sizeopt_speed/src/tarfind/tarfind",
-  "bd_sizeopt_speed/src/ud/ud",
-  "bd_sizeopt_speed/src/wikisort/wikisort"
-};
-
-string wally64q[] = '{
-  `WALLYTEST,
-  "rv64i_m/Q/src/WALLY-q-01.S"
-};
-
-string wally64a_lrsc[] = '{
-  `WALLYTEST,
-  "rv64i_m/privilege/src/WALLY-lrsc-01.S"
-};
-
-string wally32a_lrsc[] = '{
-  `WALLYTEST,
-  "rv32i_m/privilege/src/WALLY-lrsc-01.S"
-};
-
-string arch32pmp[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/pmp32/src/pmp-CFG-reg.S",
-  "rv32i_m/pmp32/src/pmp-CSR-access.S",
-  "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
-  "rv32i_m/pmp32/src/pmp-NA4-R.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RW.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RWX.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
-  "rv32i_m/pmp32/src/pmp-NA4-RX.S",
-  "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
-  "rv32i_m/pmp32/src/pmp-NA4-X.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-R.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
-  "rv32i_m/pmp32/src/pmp-NAPOT-X.S",
-  "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
-  "rv32i_m/pmp32/src/pmp-TOR-R.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
-  "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RW.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RWX.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
-  "rv32i_m/pmp32/src/pmp-TOR-RX.S",
-  "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
-  "rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
-  "rv32i_m/pmp32/src/pmp-TOR-X.S"
-};
-
-string arch64pmp[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/pmp/src/pmp64-CSR-ALL-MODES.S",
-  "rv64i_m/pmp/src/pmp64-NA4-M.S",
-  "rv64i_m/pmp/src/pmp64-NA4-S.S",
-  "rv64i_m/pmp/src/pmp64-NA4-U.S",
-  "rv64i_m/pmp/src/pmp64-NAPOT-M.S",
-  "rv64i_m/pmp/src/pmp64-NAPOT-S.S",
-  "rv64i_m/pmp/src/pmp64-NAPOT-U.S",
-  "rv64i_m/pmp/src/pmp64-TOR-M.S",
-  "rv64i_m/pmp/src/pmp64-TOR-S.S",
-  "rv64i_m/pmp/src/pmp64-TOR-U.S"
-};
-
-string arch32vm_sv32[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/vm_sv32/src/mstatus_tvm_test.S",
-  "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
-  "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
-  "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
-  "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
-  "rv32i_m/vm_sv32/src/satp_access_tests.S",
-  "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_VA_all_ones_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_global_pte_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_global_pte_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mprv_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mprv_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mprv_bare_mode.S",
-  // "rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_S_mode.S", TODO: Reenable when Sail big endian support is merged
-  // "rv32i_m/vm_sv32/src/vm_mstatus_sbe_set_sum_set_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_sum_set_U_Bit_unset_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S"
-};
-
-string arch64priv[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/privilege/src/ebreak.S",
-  "rv64i_m/privilege/src/ecall.S",
-  "rv64i_m/privilege/src/misalign2-jalr-01.S",
-  "rv64i_m/privilege/src/misalign-beq-01.S",
-  "rv64i_m/privilege/src/misalign-bge-01.S",
-  "rv64i_m/privilege/src/misalign-bgeu-01.S",
-  "rv64i_m/privilege/src/misalign-blt-01.S",
-  "rv64i_m/privilege/src/misalign-bltu-01.S",
-  "rv64i_m/privilege/src/misalign-bne-01.S",
-  "rv64i_m/privilege/src/misalign-jal-01.S"
-  // commented out for now because rv64gc supports Zicclsm, but Sail does not yet.  Restore when Sail supports Zicclsm.
-  /* -----\/----- EXCLUDED -----\/-----
-  "rv64i_m/privilege/src/misalign-ld-01.S",
-  "rv64i_m/privilege/src/misalign-lh-01.S",
-  "rv64i_m/privilege/src/misalign-lhu-01.S",
-  "rv64i_m/privilege/src/misalign-lw-01.S",
-  "rv64i_m/privilege/src/misalign-lwu-01.S",
-  "rv64i_m/privilege/src/misalign-sd-01.S",
-  "rv64i_m/privilege/src/misalign-sh-01.S",
-  "rv64i_m/privilege/src/misalign-sw-01.S"
-  -----/\----- EXCLUDED -----/\----- */
-};
-
-string arch64zifencei[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/Zifencei/src/Fencei.S"
-};
-
-string arch64zicond[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/Zicond/src/czero.eqz-01.S",
-  "rv64i_m/Zicond/src/czero.nez-01.S"
-};
-
-string arch32a_amo[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/A/src/amoadd.w-01.S",
-  "rv32i_m/A/src/amoand.w-01.S",
-  "rv32i_m/A/src/amomax.w-01.S",
-  "rv32i_m/A/src/amomaxu.w-01.S",
-  "rv32i_m/A/src/amomin.w-01.S",
-  "rv32i_m/A/src/amominu.w-01.S",
-  "rv32i_m/A/src/amoor.w-01.S",
-  "rv32i_m/A/src/amoswap.w-01.S",
-  "rv32i_m/A/src/amoxor.w-01.S"
-};
-
-
-string arch32zifencei[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/Zifencei/src/Fencei.S"
-};
-
-string arch32zicond[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/Zicond/src/czero.eqz-01.S",
-  "rv32i_m/Zicond/src/czero.nez-01.S"
-};
-
-string arch32zba[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/sh1add-01.S",
-  "rv32i_m/B/src/sh2add-01.S",
-  "rv32i_m/B/src/sh3add-01.S"
-};
-
-string arch32zbb[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/max-01.S",
-  "rv32i_m/B/src/maxu-01.S",
-  "rv32i_m/B/src/min-01.S",
-  "rv32i_m/B/src/minu-01.S",
-  "rv32i_m/B/src/orcb_32-01.S",
-  "rv32i_m/B/src/rev8_32-01.S",
-  "rv32i_m/B/src/andn-01.S",
-  "rv32i_m/B/src/orn-01.S",
-  "rv32i_m/B/src/xnor-01.S",
-  "rv32i_m/B/src/zext.h_32-01.S",
-  "rv32i_m/B/src/sext.b-01.S",
-  "rv32i_m/B/src/sext.h-01.S",
-  "rv32i_m/B/src/clz-01.S",
-  "rv32i_m/B/src/cpop-01.S",
-  "rv32i_m/B/src/ctz-01.S",
-  "rv32i_m/B/src/ror-01.S",
-  "rv32i_m/B/src/rori-01.S",
-  "rv32i_m/B/src/rol-01.S"
-};
-
-string arch32zbc[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/clmul-01.S",
-  "rv32i_m/B/src/clmulh-01.S",
-  "rv32i_m/B/src/clmulr-01.S"
-};
-
-string arch32zbs[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/bclr-01.S",
-  "rv32i_m/B/src/bclri-01.S",
-  "rv32i_m/B/src/bext-01.S",
-  "rv32i_m/B/src/bexti-01.S",
-  "rv32i_m/B/src/binv-01.S",
-  "rv32i_m/B/src/binvi-01.S",
-  "rv32i_m/B/src/bset-01.S",
-  "rv32i_m/B/src/bseti-01.S"
-};
-
-string arch32zbkc[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/clmul-01.S",
-  "rv32i_m/B/src/clmulh-01.S"
-};
-
-string arch32zbkx[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/K/src/xperm8-01.S",
-  "rv32i_m/K/src/xperm4-01.S"
-};
-
-string arch32zknd[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/K/src/aes32dsi-01.S",
-  "rv32i_m/K/src/aes32dsmi-01.S"
-};
-
-string arch32zkne[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/K/src/aes32esi-01.S",
-  "rv32i_m/K/src/aes32esmi-01.S"
-};
-
-string arch32zknh[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/K/src/sha256sig0-01.S",
-  "rv32i_m/K/src/sha256sig1-01.S",
-  "rv32i_m/K/src/sha256sum0-01.S",
-  "rv32i_m/K/src/sha256sum1-01.S",
-  "rv32i_m/K/src/sha512sig0h-01.S",
-  "rv32i_m/K/src/sha512sig0l-01.S",
-  "rv32i_m/K/src/sha512sig1h-01.S",
-  "rv32i_m/K/src/sha512sig1l-01.S",
-  "rv32i_m/K/src/sha512sum0r-01.S",
-  "rv32i_m/K/src/sha512sum1r-01.S"
-};
-
-string arch32zbkb[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/B/src/ror-01.S",
-  "rv32i_m/B/src/rol-01.S",
-  "rv32i_m/B/src/rori-01.S",
-  "rv32i_m/B/src/andn-01.S",
-  "rv32i_m/B/src/orn-01.S",
-  "rv32i_m/B/src/xnor-01.S",
-  "rv32i_m/B/src/rev8_32-01.S",
-  "rv32i_m/K/src/pack-01.S",
-  "rv32i_m/K/src/packh-01.S",
-  "rv32i_m/K/src/brev8_32-01.S",
-  "rv32i_m/K/src/zip-01.S",
-  "rv32i_m/K/src/unzip-01.S"
-};
-
-string arch64zbkb[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/B/src/ror-01.S",
-  "rv64i_m/B/src/rol-01.S",
-  "rv64i_m/B/src/rori-01.S",
-  "rv64i_m/B/src/rorw-01.S",
-  "rv64i_m/B/src/rolw-01.S",
-  "rv64i_m/B/src/roriw-01.S",
-  "rv64i_m/B/src/andn-01.S",
-  "rv64i_m/B/src/orn-01.S",
-  "rv64i_m/B/src/xnor-01.S",
-  "rv64i_m/B/src/rev8-01.S",
-  "rv64i_m/K/src/pack-01.S",
-  "rv64i_m/K/src/packh-01.S",
-  "rv64i_m/K/src/packw-01.S",
-  "rv64i_m/K/src/brev8-01.S"
-};
-
-string arch64m[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/M/src/div-01.S",
-  "rv64i_m/M/src/divu-01.S",
-  "rv64i_m/M/src/divuw-01.S",
-  "rv64i_m/M/src/divw-01.S",
-  "rv64i_m/M/src/mul-01.S",
-  "rv64i_m/M/src/mulh-01.S",
-  "rv64i_m/M/src/mulhsu-01.S",
-  "rv64i_m/M/src/mulhu-01.S",
-  "rv64i_m/M/src/mulw-01.S",
-  "rv64i_m/M/src/rem-01.S",
-  "rv64i_m/M/src/remu-01.S",
-  "rv64i_m/M/src/remuw-01.S",
-  "rv64i_m/M/src/remw-01.S"
-};
-
-string arch64a_amo[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/A/src/amoadd.w-01.S",
-  "rv64i_m/A/src/amoand.w-01.S",
-  "rv64i_m/A/src/amomax.w-01.S",
-  "rv64i_m/A/src/amomaxu.w-01.S",
-  "rv64i_m/A/src/amomin.w-01.S",
-  "rv64i_m/A/src/amominu.w-01.S",
-  "rv64i_m/A/src/amoor.w-01.S",
-  "rv64i_m/A/src/amoswap.w-01.S",
-  "rv64i_m/A/src/amoxor.w-01.S",
-  "rv64i_m/A/src/amoadd.d-01.S",
-  "rv64i_m/A/src/amoand.d-01.S",
-  "rv64i_m/A/src/amomax.d-01.S",
-  "rv64i_m/A/src/amomaxu.d-01.S",
-  "rv64i_m/A/src/amomin.d-01.S",
-  "rv64i_m/A/src/amominu.d-01.S",
-  "rv64i_m/A/src/amoor.d-01.S",
-  "rv64i_m/A/src/amoswap.d-01.S",
-  "rv64i_m/A/src/amoxor.d-01.S"
-};
-
-string arch64c[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/C/src/cadd-01.S",
-  "rv64i_m/C/src/caddi-01.S",
-  "rv64i_m/C/src/caddi16sp-01.S",
-  "rv64i_m/C/src/caddi4spn-01.S",
-  "rv64i_m/C/src/caddiw-01.S",
-  "rv64i_m/C/src/caddw-01.S",
-  "rv64i_m/C/src/cand-01.S",
-  "rv64i_m/C/src/candi-01.S",
-  "rv64i_m/C/src/cbeqz-01.S",
-  "rv64i_m/C/src/cbnez-01.S",
-  "rv64i_m/C/src/cj-01.S",
-  "rv64i_m/C/src/cjalr-01.S",
-  "rv64i_m/C/src/cjr-01.S",
-  "rv64i_m/C/src/cld-01.S",
-  "rv64i_m/C/src/cldsp-01.S",
-  "rv64i_m/C/src/cli-01.S",
-  "rv64i_m/C/src/clui-01.S",
-  "rv64i_m/C/src/clw-01.S",
-  "rv64i_m/C/src/clwsp-01.S",
-  "rv64i_m/C/src/cmv-01.S",
-  "rv64i_m/C/src/cnop-01.S",
-  "rv64i_m/C/src/cor-01.S",
-  "rv64i_m/C/src/csd-01.S",
-  "rv64i_m/C/src/csdsp-01.S",
-  "rv64i_m/C/src/cslli-01.S",
-  "rv64i_m/C/src/csrai-01.S",
-  "rv64i_m/C/src/csrli-01.S",
-  "rv64i_m/C/src/csub-01.S",
-  "rv64i_m/C/src/csubw-01.S",
-  "rv64i_m/C/src/csw-01.S",
-  "rv64i_m/C/src/cswsp-01.S",
-  "rv64i_m/C/src/cxor-01.S",
-  "rv64i_m/C/src/misalign1-cjalr-01.S",
-  "rv64i_m/C/src/misalign1-cjr-01.S"
-};
-
-string arch64cpriv[] = '{
-  // `RISCVARCHTEST,
-  "rv64i_m/C/src/cebreak-01.S"
-};
-
-string arch64zcd[] = '{
-  // `RISCVARCHTEST,
-  "rv64i_m/D_Zcd/src/c.fld-01.S",
-  "rv64i_m/D_Zcd/src/c.fldsp-01.S",
-  "rv64i_m/D_Zcd/src/c.fsd-01.S",
-  "rv64i_m/D_Zcd/src/c.fsdsp-01.S"
-};
-
-string arch64i[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/I/src/add-01.S",
-  "rv64i_m/I/src/addi-01.S",
-  "rv64i_m/I/src/addiw-01.S",
-  "rv64i_m/I/src/addw-01.S",
-  "rv64i_m/I/src/and-01.S",
-  "rv64i_m/I/src/andi-01.S",
-  "rv64i_m/I/src/auipc-01.S",
-  "rv64i_m/I/src/beq-01.S",
-  "rv64i_m/I/src/bge-01.S",
-  "rv64i_m/I/src/bgeu-01.S",
-  "rv64i_m/I/src/blt-01.S",
-  "rv64i_m/I/src/bltu-01.S",
-  "rv64i_m/I/src/bne-01.S",
-  "rv64i_m/I/src/fence-01.S",
-  "rv64i_m/I/src/jal-01.S",
-  "rv64i_m/I/src/jalr-01.S",
-  "rv64i_m/I/src/lb-align-01.S",
-  "rv64i_m/I/src/lbu-align-01.S",
-  "rv64i_m/I/src/ld-align-01.S",
-  "rv64i_m/I/src/lh-align-01.S",
-  "rv64i_m/I/src/lhu-align-01.S",
-  "rv64i_m/I/src/lui-01.S",
-  "rv64i_m/I/src/lw-align-01.S",
-  "rv64i_m/I/src/lwu-align-01.S",
-  "rv64i_m/I/src/or-01.S",
-  "rv64i_m/I/src/ori-01.S",
-  "rv64i_m/I/src/sb-align-01.S",
-  "rv64i_m/I/src/sd-align-01.S",
-  "rv64i_m/I/src/sh-align-01.S",
-  "rv64i_m/I/src/sll-01.S",
-  "rv64i_m/I/src/slli-01.S",
-  "rv64i_m/I/src/slliw-01.S",
-  "rv64i_m/I/src/sllw-01.S",
-  "rv64i_m/I/src/slt-01.S",
-  "rv64i_m/I/src/slti-01.S",
-  "rv64i_m/I/src/sltiu-01.S",
-  "rv64i_m/I/src/sltu-01.S",
-  "rv64i_m/I/src/sra-01.S",
-  "rv64i_m/I/src/srai-01.S",
-  "rv64i_m/I/src/sraiw-01.S",
-  "rv64i_m/I/src/sraw-01.S",
-  "rv64i_m/I/src/srl-01.S",
-  "rv64i_m/I/src/srli-01.S",
-  "rv64i_m/I/src/srliw-01.S",
-  "rv64i_m/I/src/srlw-01.S",
-  "rv64i_m/I/src/sub-01.S",
-  "rv64i_m/I/src/subw-01.S",
-  "rv64i_m/I/src/sw-align-01.S",
-  "rv64i_m/I/src/xor-01.S",
-  "rv64i_m/I/src/xori-01.S"
-};
-
-string arch64f_fma[] = '{
-  `RISCVARCHTEST,
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-001.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-002.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-003.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-004.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-005.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-006.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-007.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-008.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-009.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-010.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-011.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-012.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-013.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-014.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-015.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-016.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-017.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-018.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-019.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-020.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-021.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-022.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-023.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-024.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-025.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-026.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-027.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-028.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-029.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-030.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-031.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-032.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-033.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-034.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-035.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-036.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-037.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-038.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-039.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-040.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-041.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-042.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-043.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-044.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-045.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-046.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-047.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-048.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-049.S",
-  // "rv64i_m/F/src/fmadd_b15/fmadd_b15-050.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-001.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-002.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-003.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-004.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-005.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-006.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-007.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-008.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-009.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-010.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-011.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-012.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-013.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-014.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-015.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-016.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-017.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-018.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-019.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-020.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-021.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-022.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-023.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-024.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-025.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-026.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-027.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-028.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-029.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-030.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-031.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-032.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-033.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-034.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-035.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-036.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-037.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-038.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-039.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-040.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-041.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-042.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-043.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-044.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-045.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-046.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-047.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-048.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-049.S",
-  "rv64i_m/F/src/fmsub_b15/fmsub_b15-050.S"
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-001.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-002.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-003.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-004.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-005.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-006.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-007.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-008.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-009.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-010.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-011.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-012.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-013.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-014.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-015.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-016.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-017.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-018.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-019.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-020.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-021.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-022.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-023.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-024.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-025.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-026.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-027.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-028.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-029.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-030.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-031.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-032.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-033.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-034.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-035.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-036.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-037.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-038.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-039.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-040.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-041.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-042.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-043.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-044.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-045.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-046.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-047.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-048.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-049.S",
-  // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-050.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-001.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-002.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-003.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-004.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-005.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-006.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-007.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-008.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-009.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-010.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-011.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-012.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-013.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-014.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-015.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-016.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-017.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-018.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-019.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-020.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-021.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-022.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-023.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-024.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-025.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-026.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-027.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-028.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-029.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-030.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-031.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-032.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-033.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-034.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-035.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-036.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-037.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-038.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-039.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-040.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-041.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-042.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-043.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-044.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-045.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-046.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-047.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-048.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-049.S",
-  // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-050.S"
-};
-
-string arch64zfh_fma[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/Zfh/src/fmadd_b15-01.S",
-  "rv64i_m/Zfh/src/fmsub_b15-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b15-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b15-01.S"
-};
-
-string arch64f_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/F/src/fdiv_b20-01.S",
-  "rv64i_m/F/src/fdiv_b1-01.S",
-  "rv64i_m/F/src/fdiv_b2-01.S",
-  "rv64i_m/F/src/fdiv_b21-01.S",
-  "rv64i_m/F/src/fdiv_b3-01.S",
-  "rv64i_m/F/src/fdiv_b4-01.S",
-  "rv64i_m/F/src/fdiv_b5-01.S",
-  "rv64i_m/F/src/fdiv_b6-01.S",
-  "rv64i_m/F/src/fdiv_b7-01.S",
-  "rv64i_m/F/src/fdiv_b8-01.S",
-  "rv64i_m/F/src/fdiv_b9-01.S",
-  "rv64i_m/F/src/fsqrt_b1-01.S",
-  "rv64i_m/F/src/fsqrt_b20-01.S",
-  "rv64i_m/F/src/fsqrt_b2-01.S",
-  "rv64i_m/F/src/fsqrt_b3-01.S",
-  "rv64i_m/F/src/fsqrt_b4-01.S",
-  "rv64i_m/F/src/fsqrt_b5-01.S",
-  "rv64i_m/F/src/fsqrt_b7-01.S",
-  "rv64i_m/F/src/fsqrt_b8-01.S",
-  "rv64i_m/F/src/fsqrt_b9-01.S"
-};
-
-string arch64f[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/F/src/fadd_b10-01.S",
-  "rv64i_m/F/src/fadd_b1-01.S",
-  "rv64i_m/F/src/fadd_b11-01.S",
-  "rv64i_m/F/src/fadd_b12-01.S",
-  "rv64i_m/F/src/fadd_b13-01.S",
-  "rv64i_m/F/src/fadd_b2-01.S",
-  "rv64i_m/F/src/fadd_b3-01.S",
-  "rv64i_m/F/src/fadd_b4-01.S",
-  "rv64i_m/F/src/fadd_b5-01.S",
-  "rv64i_m/F/src/fadd_b7-01.S",
-  "rv64i_m/F/src/fadd_b8-01.S",
-  "rv64i_m/F/src/fclass_b1-01.S",
-  "rv64i_m/F/src/fcvt.s.l_b25-01.S",
-  "rv64i_m/F/src/fcvt.s.l_b26-01.S",
-  "rv64i_m/F/src/fcvt.s.lu_b25-01.S",
-  "rv64i_m/F/src/fcvt.s.lu_b26-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b1-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b22-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b23-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b24-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b27-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b28-01.S",
-  "rv64i_m/F/src/fcvt.l.s_b29-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b1-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b22-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b23-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b24-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b27-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b28-01.S",
-  "rv64i_m/F/src/fcvt.lu.s_b29-01.S",
-  "rv64i_m/F/src/fcvt.s.w_b25-01.S",
-  "rv64i_m/F/src/fcvt.s.w_b26-01.S",
-  "rv64i_m/F/src/fcvt.s.wu_b25-01.S",
-  "rv64i_m/F/src/fcvt.s.wu_b26-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b1-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b22-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b23-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b24-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b27-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b28-01.S",
-  "rv64i_m/F/src/fcvt.w.s_b29-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b1-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b22-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b23-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b24-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b27-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b28-01.S",
-  "rv64i_m/F/src/fcvt.wu.s_b29-01.S",
-  "rv64i_m/F/src/feq_b1-01.S",
-  "rv64i_m/F/src/feq_b19-01.S",
-  "rv64i_m/F/src/fle_b1-01.S",
-  "rv64i_m/F/src/fle_b19-01.S",
-  "rv64i_m/F/src/flt_b1-01.S",
-  "rv64i_m/F/src/flt_b19-01.S",
-  "rv64i_m/F/src/flw-align-01.S",
-  "rv64i_m/F/src/fmadd_b1-01.S",
-  "rv64i_m/F/src/fmadd_b14-01.S",
-  "rv64i_m/F/src/fmadd_b16-01.S",
-  "rv64i_m/F/src/fmadd_b17-01.S",
-  "rv64i_m/F/src/fmadd_b18-01.S",
-  "rv64i_m/F/src/fmadd_b2-01.S",
-  "rv64i_m/F/src/fmadd_b3-01.S",
-  "rv64i_m/F/src/fmadd_b4-01.S",
-  "rv64i_m/F/src/fmadd_b5-01.S",
-  "rv64i_m/F/src/fmadd_b6-01.S",
-  "rv64i_m/F/src/fmadd_b7-01.S",
-  "rv64i_m/F/src/fmadd_b8-01.S",
-  "rv64i_m/F/src/fmax_b1-01.S",
-  "rv64i_m/F/src/fmax_b19-01.S",
-  "rv64i_m/F/src/fmin_b1-01.S",
-  "rv64i_m/F/src/fmin_b19-01.S",
-  "rv64i_m/F/src/fmsub_b1-01.S",
-  "rv64i_m/F/src/fmsub_b14-01.S",
-  "rv64i_m/F/src/fmsub_b16-01.S",
-  "rv64i_m/F/src/fmsub_b17-01.S",
-  "rv64i_m/F/src/fmsub_b18-01.S",
-  "rv64i_m/F/src/fmsub_b2-01.S",
-  "rv64i_m/F/src/fmsub_b3-01.S",
-  "rv64i_m/F/src/fmsub_b4-01.S",
-  "rv64i_m/F/src/fmsub_b5-01.S",
-  "rv64i_m/F/src/fmsub_b6-01.S",
-  "rv64i_m/F/src/fmsub_b7-01.S",
-  "rv64i_m/F/src/fmsub_b8-01.S",
-  "rv64i_m/F/src/fmul_b1-01.S",
-  "rv64i_m/F/src/fmul_b2-01.S",
-  "rv64i_m/F/src/fmul_b3-01.S",
-  "rv64i_m/F/src/fmul_b4-01.S",
-  "rv64i_m/F/src/fmul_b5-01.S",
-  "rv64i_m/F/src/fmul_b6-01.S",
-  "rv64i_m/F/src/fmul_b7-01.S",
-  "rv64i_m/F/src/fmul_b8-01.S",
-  "rv64i_m/F/src/fmul_b9-01.S",
-  "rv64i_m/F/src/fmv.w.x_b25-01.S",
-  "rv64i_m/F/src/fmv.w.x_b26-01.S",
-  "rv64i_m/F/src/fmv.x.w_b1-01.S",
-  "rv64i_m/F/src/fmv.x.w_b22-01.S",
-  "rv64i_m/F/src/fmv.x.w_b23-01.S",
-  "rv64i_m/F/src/fmv.x.w_b24-01.S",
-  "rv64i_m/F/src/fmv.x.w_b27-01.S",
-  "rv64i_m/F/src/fmv.x.w_b28-01.S",
-  "rv64i_m/F/src/fmv.x.w_b29-01.S",
-  "rv64i_m/F/src/fnmadd_b1-01.S",
-  "rv64i_m/F/src/fnmadd_b14-01.S",
-  "rv64i_m/F/src/fnmadd_b16-01.S",
-  "rv64i_m/F/src/fnmadd_b17-01.S",
-  "rv64i_m/F/src/fnmadd_b18-01.S",
-  "rv64i_m/F/src/fnmadd_b2-01.S",
-  "rv64i_m/F/src/fnmadd_b3-01.S",
-  "rv64i_m/F/src/fnmadd_b4-01.S",
-  "rv64i_m/F/src/fnmadd_b5-01.S",
-  "rv64i_m/F/src/fnmadd_b6-01.S",
-  "rv64i_m/F/src/fnmadd_b7-01.S",
-  "rv64i_m/F/src/fnmadd_b8-01.S",
-  "rv64i_m/F/src/fnmsub_b1-01.S",
-  "rv64i_m/F/src/fnmsub_b14-01.S",
-  "rv64i_m/F/src/fnmsub_b16-01.S",
-  "rv64i_m/F/src/fnmsub_b17-01.S",
-  "rv64i_m/F/src/fnmsub_b18-01.S",
-  "rv64i_m/F/src/fnmsub_b2-01.S",
-  "rv64i_m/F/src/fnmsub_b3-01.S",
-  "rv64i_m/F/src/fnmsub_b4-01.S",
-  "rv64i_m/F/src/fnmsub_b5-01.S",
-  "rv64i_m/F/src/fnmsub_b6-01.S",
-  "rv64i_m/F/src/fnmsub_b7-01.S",
-  "rv64i_m/F/src/fnmsub_b8-01.S",
-  "rv64i_m/F/src/fsgnj_b1-01.S",
-  "rv64i_m/F/src/fsgnjn_b1-01.S",
-  "rv64i_m/F/src/fsgnjx_b1-01.S",
-  "rv64i_m/F/src/fsub_b10-01.S",
-  "rv64i_m/F/src/fsub_b1-01.S",
-  "rv64i_m/F/src/fsub_b11-01.S",
-  "rv64i_m/F/src/fsub_b12-01.S",
-  "rv64i_m/F/src/fsub_b13-01.S",
-  "rv64i_m/F/src/fsub_b2-01.S",
-  "rv64i_m/F/src/fsub_b3-01.S",
-  "rv64i_m/F/src/fsub_b4-01.S",
-  "rv64i_m/F/src/fsub_b5-01.S",
-  "rv64i_m/F/src/fsub_b7-01.S",
-  "rv64i_m/F/src/fsub_b8-01.S",
-  "rv64i_m/F/src/fsw-align-01.S"
-};
-
-string arch64zfh_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/Zfh/src/fdiv_b20-01.S",
-  "rv64i_m/Zfh/src/fdiv_b1-01.S",
-  "rv64i_m/Zfh/src/fdiv_b2-01.S",
-  "rv64i_m/Zfh/src/fdiv_b21-01.S",
-  "rv64i_m/Zfh/src/fdiv_b3-01.S",
-  "rv64i_m/Zfh/src/fdiv_b4-01.S",
-  "rv64i_m/Zfh/src/fdiv_b5-01.S",
-  "rv64i_m/Zfh/src/fdiv_b6-01.S",
-  "rv64i_m/Zfh/src/fdiv_b7-01.S",
-  "rv64i_m/Zfh/src/fdiv_b8-01.S",
-  "rv64i_m/Zfh/src/fdiv_b9-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b1-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b20-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b2-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b3-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b4-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b5-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b7-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b8-01.S",
-  "rv64i_m/Zfh/src/fsqrt_b9-01.S"
-};
-
-string arch64zfh[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/Zfh/src/fadd_b10-01.S",
-  "rv64i_m/Zfh/src/fadd_b1-01.S",
-  "rv64i_m/Zfh/src/fadd_b11-01.S",
-  "rv64i_m/Zfh/src/fadd_b12-01.S",
-  "rv64i_m/Zfh/src/fadd_b13-01.S",
-  "rv64i_m/Zfh/src/fadd_b2-01.S",
-  "rv64i_m/Zfh/src/fadd_b3-01.S",
-  "rv64i_m/Zfh/src/fadd_b4-01.S",
-  "rv64i_m/Zfh/src/fadd_b5-01.S",
-  "rv64i_m/Zfh/src/fadd_b7-01.S",
-  "rv64i_m/Zfh/src/fadd_b8-01.S",
-  "rv64i_m/Zfh/src/fclass_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.s_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.w_b25-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.w_b26-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.s.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.w.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.l.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S",
-  "rv64i_m/Zfh/src/feq_b1-01.S",
-  "rv64i_m/Zfh/src/feq_b19-01.S",
-  "rv64i_m/Zfh/src/fle_b1-01.S",
-  "rv64i_m/Zfh/src/fle_b19-01.S",
-  "rv64i_m/Zfh/src/flt_b1-01.S",
-  "rv64i_m/Zfh/src/flt_b19-01.S",
-  "rv64i_m/Zfh/src/flh-align-01.S",
-  "rv64i_m/Zfh/src/fmax_b1-01.S",
-  "rv64i_m/Zfh/src/fmax_b19-01.S",
-  "rv64i_m/Zfh/src/fmin_b1-01.S",
-  "rv64i_m/Zfh/src/fmin_b19-01.S",
-  "rv64i_m/Zfh/src/fmul_b1-01.S",
-  "rv64i_m/Zfh/src/fmul_b2-01.S",
-  "rv64i_m/Zfh/src/fmul_b3-01.S",
-  "rv64i_m/Zfh/src/fmul_b4-01.S",
-  "rv64i_m/Zfh/src/fmul_b5-01.S",
-  "rv64i_m/Zfh/src/fmul_b6-01.S",
-  "rv64i_m/Zfh/src/fmul_b7-01.S",
-  "rv64i_m/Zfh/src/fmul_b8-01.S",
-  "rv64i_m/Zfh/src/fmul_b9-01.S",
-  "rv64i_m/Zfh/src/fmv.h.x_b25-01.S",
-  "rv64i_m/Zfh/src/fmv.h.x_b26-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b1-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b22-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b23-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b24-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b27-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b28-01.S",
-  "rv64i_m/Zfh/src/fmv.x.h_b29-01.S",
-  "rv64i_m/Zfh/src/fsgnj_b1-01.S",
-  "rv64i_m/Zfh/src/fsgnjn_b1-01.S",
-  "rv64i_m/Zfh/src/fsgnjx_b1-01.S",
-  "rv64i_m/Zfh/src/fsub_b10-01.S",
-  "rv64i_m/Zfh/src/fsub_b1-01.S",
-  "rv64i_m/Zfh/src/fsub_b11-01.S",
-  "rv64i_m/Zfh/src/fsub_b12-01.S",
-  "rv64i_m/Zfh/src/fsub_b13-01.S",
-  "rv64i_m/Zfh/src/fsub_b2-01.S",
-  "rv64i_m/Zfh/src/fsub_b3-01.S",
-  "rv64i_m/Zfh/src/fsub_b4-01.S",
-  "rv64i_m/Zfh/src/fsub_b5-01.S",
-  "rv64i_m/Zfh/src/fsub_b7-01.S",
-  "rv64i_m/Zfh/src/fsub_b8-01.S",
-  "rv64i_m/Zfh/src/fsh-align-01.S",
-  "rv64i_m/Zfh/src/fmadd_b1-01.S",
-  "rv64i_m/Zfh/src/fmadd_b14-01.S",
-  "rv64i_m/Zfh/src/fmadd_b16-01.S",
-  "rv64i_m/Zfh/src/fmadd_b17-01.S",
-  "rv64i_m/Zfh/src/fmadd_b18-01.S",
-  "rv64i_m/Zfh/src/fmadd_b2-01.S",
-  "rv64i_m/Zfh/src/fmadd_b3-01.S",
-  "rv64i_m/Zfh/src/fmadd_b4-01.S",
-  "rv64i_m/Zfh/src/fmadd_b5-01.S",
-  "rv64i_m/Zfh/src/fmadd_b6-01.S",
-  "rv64i_m/Zfh/src/fmadd_b7-01.S",
-  "rv64i_m/Zfh/src/fmadd_b8-01.S",
-  "rv64i_m/Zfh/src/fmsub_b1-01.S",
-  "rv64i_m/Zfh/src/fmsub_b14-01.S",
-  "rv64i_m/Zfh/src/fmsub_b16-01.S",
-  "rv64i_m/Zfh/src/fmsub_b17-01.S",
-  "rv64i_m/Zfh/src/fmsub_b18-01.S",
-  "rv64i_m/Zfh/src/fmsub_b2-01.S",
-  "rv64i_m/Zfh/src/fmsub_b3-01.S",
-  "rv64i_m/Zfh/src/fmsub_b4-01.S",
-  "rv64i_m/Zfh/src/fmsub_b5-01.S",
-  "rv64i_m/Zfh/src/fmsub_b6-01.S",
-  "rv64i_m/Zfh/src/fmsub_b7-01.S",
-  "rv64i_m/Zfh/src/fmsub_b8-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b1-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b14-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b16-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b17-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b18-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b2-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b3-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b4-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b5-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b6-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b7-01.S",
-  "rv64i_m/Zfh/src/fnmadd_b8-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b1-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b14-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b16-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b17-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b18-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b2-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b3-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b4-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b5-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b6-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b7-01.S",
-  "rv64i_m/Zfh/src/fnmsub_b8-01.S"
-};
-
-string arch64zfh_d[] = '{
-  // `RISCVARCHTEST,
-  "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S",
-  "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S"
-};
-
-string arch64d_fma[] = '{
-  `RISCVARCHTEST,
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-001.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-002.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-003.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-004.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-005.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-006.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-007.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-008.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-009.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-010.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-011.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-012.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-013.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-014.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-015.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-016.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-017.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-018.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-019.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-020.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-021.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-022.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-023.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-024.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-025.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-026.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-027.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-028.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-029.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-030.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-031.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-032.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-033.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-034.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-035.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-036.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-037.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-038.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-039.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-040.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-041.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-042.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-043.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-044.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-045.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-046.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-047.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-048.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-049.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-050.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-051.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-052.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-053.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-054.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-055.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-056.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-057.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-058.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-059.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-060.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-061.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-062.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-063.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-064.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-065.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-066.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-067.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-068.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-069.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-070.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-071.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-072.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-073.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-074.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-075.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-076.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-077.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-078.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-079.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-080.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-081.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-082.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-083.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-084.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-085.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-086.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-087.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-088.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-089.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-090.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-091.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-092.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-093.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-094.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-095.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-096.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-097.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-098.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-099.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-100.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-101.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-102.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-103.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-104.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-105.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-106.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-107.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-108.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-109.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-110.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-111.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-112.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-113.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-114.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-115.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-116.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-117.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-118.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-119.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-120.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-121.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-122.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-123.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-124.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-125.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-126.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-127.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-128.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-129.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-130.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-131.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-132.S",
-  // "rv64i_m/D/src/fmadd.d_b15/fmadd.d_b15-133.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-001.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-002.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-003.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-004.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-005.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-006.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-007.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-008.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-009.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-010.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-011.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-012.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-013.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-014.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-015.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-016.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-017.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-018.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-019.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-020.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-021.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-022.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-023.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-024.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-025.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-026.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-027.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-028.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-029.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-030.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-031.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-032.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-033.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-034.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-035.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-036.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-037.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-038.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-039.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-040.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-041.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-042.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-043.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-044.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-045.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-046.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-047.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-048.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-049.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-050.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-051.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-052.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-053.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-054.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-055.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-056.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-057.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-058.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-059.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-060.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-061.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-062.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-063.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-064.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-065.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-066.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-067.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-068.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-069.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-070.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-071.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-072.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-073.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-074.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-075.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-076.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-077.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-078.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-079.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-080.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-081.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-082.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-083.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-084.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-085.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-086.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-087.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-088.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-089.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-090.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-091.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-092.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-093.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-094.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-095.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-096.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-097.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-098.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-099.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-100.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-101.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-102.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-103.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-104.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-105.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-106.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-107.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-108.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-109.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-110.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-111.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-112.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-113.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-114.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-115.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-116.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-117.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-118.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-119.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-120.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-121.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-122.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-123.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-124.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-125.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-126.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-127.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-128.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-129.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-130.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-131.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-132.S",
-  // "rv64i_m/D/src/fmsub.d_b15/fmsub.d_b15-133.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-001.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-002.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-003.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-004.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-005.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-006.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-007.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-008.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-009.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-010.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-011.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-012.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-013.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-014.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-015.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-016.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-017.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-018.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-019.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-020.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-021.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-022.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-023.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-024.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-025.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-026.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-027.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-028.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-029.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-030.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-031.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-032.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-033.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-034.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-035.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-036.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-037.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-038.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-039.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-040.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-041.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-042.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-043.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-044.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-045.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-046.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-047.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-048.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-049.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-050.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-051.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-052.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-053.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-054.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-055.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-056.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-057.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-058.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-059.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-060.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-061.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-062.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-063.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-064.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-065.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-066.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-067.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-068.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-069.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-070.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-071.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-072.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-073.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-074.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-075.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-076.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-077.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-078.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-079.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-080.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-081.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-082.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-083.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-084.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-085.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-086.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-087.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-088.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-089.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-090.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-091.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-092.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-093.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-094.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-095.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-096.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-097.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-098.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-099.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-100.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-101.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-102.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-103.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-104.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-105.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-106.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-107.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-108.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-109.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-110.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-111.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-112.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-113.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-114.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-115.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-116.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-117.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-118.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-119.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-120.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-121.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-122.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-123.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-124.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-125.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-126.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-127.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-128.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-129.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-130.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-131.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-132.S",
-  "rv64i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-133.S"
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-001.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-002.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-003.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-004.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-005.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-006.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-007.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-008.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-009.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-010.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-011.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-012.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-013.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-014.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-015.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-016.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-017.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-018.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-019.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-020.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-021.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-022.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-023.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-024.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-025.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-026.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-027.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-028.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-029.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-030.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-031.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-032.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-033.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-034.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-035.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-036.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-037.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-038.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-039.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-040.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-041.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-042.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-043.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-044.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-045.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-046.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-047.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-048.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-049.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-050.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-051.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-052.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-053.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-054.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-055.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-056.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-057.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-058.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-059.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-060.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-061.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-062.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-063.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-064.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-065.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-066.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-067.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-068.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-069.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-070.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-071.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-072.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-073.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-074.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-075.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-076.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-077.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-078.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-079.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-080.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-081.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-082.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-083.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-084.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-085.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-086.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-087.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-088.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-089.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-090.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-091.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-092.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-093.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-094.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-095.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-096.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-097.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-098.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-099.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-100.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-101.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-102.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-103.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-104.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-105.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-106.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-107.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-108.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-109.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-110.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-111.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-112.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-113.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-114.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-115.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-116.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-117.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-118.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-119.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-120.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-121.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-122.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-123.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-124.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-125.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-126.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-127.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-128.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-129.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-130.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-131.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-132.S",
-  // "rv64i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-133.S"
-};
-
-string arch64d_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/D/src/fdiv.d_b1-01.S",
-  "rv64i_m/D/src/fdiv.d_b20-01.S",
-  "rv64i_m/D/src/fdiv.d_b2-01.S",
-  "rv64i_m/D/src/fdiv.d_b21-01.S",
-  "rv64i_m/D/src/fdiv.d_b3-01.S",
-  "rv64i_m/D/src/fdiv.d_b4-01.S",
-  "rv64i_m/D/src/fdiv.d_b5-01.S",
-  "rv64i_m/D/src/fdiv.d_b6-01.S",
-  "rv64i_m/D/src/fdiv.d_b7-01.S",
-  "rv64i_m/D/src/fdiv.d_b8-01.S",
-  "rv64i_m/D/src/fdiv.d_b9-01.S",
-  "rv64i_m/D/src/fsqrt.d_b1-01.S",
-  "rv64i_m/D/src/fsqrt.d_b20-01.S",
-  "rv64i_m/D/src/fsqrt.d_b2-01.S",
-  "rv64i_m/D/src/fsqrt.d_b3-01.S",
-  "rv64i_m/D/src/fsqrt.d_b4-01.S",
-  "rv64i_m/D/src/fsqrt.d_b5-01.S",
-  "rv64i_m/D/src/fsqrt.d_b7-01.S",
-  "rv64i_m/D/src/fsqrt.d_b8-01.S",
-  "rv64i_m/D/src/fsqrt.d_b9-01.S"
-};
-
-string arch64d[] = '{
-  `RISCVARCHTEST,
-  // for speed
-  "rv64i_m/D/src/fadd.d_b10-01.S",
-  "rv64i_m/D/src/fadd.d_b1-01.S",
-  "rv64i_m/D/src/fadd.d_b11-01.S",
-  "rv64i_m/D/src/fadd.d_b12-01.S",
-  "rv64i_m/D/src/fadd.d_b13-01.S",
-  "rv64i_m/D/src/fadd.d_b2-01.S",
-  "rv64i_m/D/src/fadd.d_b3-01.S",
-  "rv64i_m/D/src/fadd.d_b4-01.S",
-  "rv64i_m/D/src/fadd.d_b5-01.S",
-  "rv64i_m/D/src/fadd.d_b7-01.S",
-  "rv64i_m/D/src/fadd.d_b8-01.S",
-  "rv64i_m/D/src/fclass.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.d.l_b25-01.S",
-  "rv64i_m/D/src/fcvt.d.l_b26-01.S",
-  "rv64i_m/D/src/fcvt.d.lu_b25-01.S",
-  "rv64i_m/D/src/fcvt.d.lu_b26-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b1-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b22-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b23-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b24-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b27-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b28-01.S",
-  "rv64i_m/D/src/fcvt.d.s_b29-01.S",
-  "rv64i_m/D/src/fcvt.d.w_b25-01.S",
-  "rv64i_m/D/src/fcvt.d.w_b26-01.S",
-  "rv64i_m/D/src/fcvt.d.wu_b25-01.S",
-  "rv64i_m/D/src/fcvt.d.wu_b26-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b22-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b23-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b24-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b27-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b28-01.S",
-  "rv64i_m/D/src/fcvt.l.d_b29-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b22-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b23-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b24-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b27-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b28-01.S",
-  "rv64i_m/D/src/fcvt.lu.d_b29-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b22-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b23-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b24-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b27-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b28-01.S",
-  "rv64i_m/D/src/fcvt.s.d_b29-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b22-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b23-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b24-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b27-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b28-01.S",
-  "rv64i_m/D/src/fcvt.w.d_b29-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b1-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b22-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b23-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b24-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b27-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b28-01.S",
-  "rv64i_m/D/src/fcvt.wu.d_b29-01.S",
-  "rv64i_m/D/src/feq.d_b1-01.S",
-  "rv64i_m/D/src/feq.d_b19-01.S",
-  "rv64i_m/D/src/fle.d_b1-01.S",
-  "rv64i_m/D/src/fle.d_b19-01.S",
-  "rv64i_m/D/src/flt.d_b1-01.S",
-  "rv64i_m/D/src/flt.d_b19-01.S",
-  "rv64i_m/D/src/fld-align-01.S",
-  "rv64i_m/D/src/fsd-align-01.S",
-  "rv64i_m/D/src/fmadd.d_b14-01.S",
-  "rv64i_m/D/src/fmadd.d_b16-01.S",
-  "rv64i_m/D/src/fmadd.d_b17-01.S",
-  "rv64i_m/D/src/fmadd.d_b18-01.S",
-  "rv64i_m/D/src/fmadd.d_b2-01.S",
-  "rv64i_m/D/src/fmadd.d_b3-01.S",
-  "rv64i_m/D/src/fmadd.d_b4-01.S",
-  "rv64i_m/D/src/fmadd.d_b5-01.S",
-  "rv64i_m/D/src/fmadd.d_b6-01.S",
-  "rv64i_m/D/src/fmadd.d_b7-01.S",
-  "rv64i_m/D/src/fmadd.d_b8-01.S",
-  "rv64i_m/D/src/fmax.d_b1-01.S",
-  "rv64i_m/D/src/fmax.d_b19-01.S",
-  "rv64i_m/D/src/fmin.d_b1-01.S",
-  "rv64i_m/D/src/fmin.d_b19-01.S",
-  "rv64i_m/D/src/fmsub.d_b14-01.S",
-  "rv64i_m/D/src/fmsub.d_b16-01.S",
-  "rv64i_m/D/src/fmsub.d_b17-01.S",
-  "rv64i_m/D/src/fmsub.d_b18-01.S",
-  "rv64i_m/D/src/fmsub.d_b2-01.S",
-  "rv64i_m/D/src/fmsub.d_b3-01.S",
-  "rv64i_m/D/src/fmsub.d_b4-01.S",
-  "rv64i_m/D/src/fmsub.d_b5-01.S",
-  "rv64i_m/D/src/fmsub.d_b6-01.S",
-  "rv64i_m/D/src/fmsub.d_b7-01.S",
-  "rv64i_m/D/src/fmsub.d_b8-01.S",
-  "rv64i_m/D/src/fmul.d_b1-01.S",
-  "rv64i_m/D/src/fmul.d_b2-01.S",
-  "rv64i_m/D/src/fmul.d_b3-01.S",
-  "rv64i_m/D/src/fmul.d_b4-01.S",
-  "rv64i_m/D/src/fmul.d_b5-01.S",
-  "rv64i_m/D/src/fmul.d_b6-01.S",
-  "rv64i_m/D/src/fmul.d_b7-01.S",
-  "rv64i_m/D/src/fmul.d_b8-01.S",
-  "rv64i_m/D/src/fmul.d_b9-01.S",
-  "rv64i_m/D/src/fmv.d.x_b25-01.S",
-  "rv64i_m/D/src/fmv.d.x_b26-01.S",
-  "rv64i_m/D/src/fmv.x.d_b1-01.S",
-  "rv64i_m/D/src/fmv.x.d_b22-01.S",
-  "rv64i_m/D/src/fmv.x.d_b23-01.S",
-  "rv64i_m/D/src/fmv.x.d_b24-01.S",
-  "rv64i_m/D/src/fmv.x.d_b27-01.S",
-  "rv64i_m/D/src/fmv.x.d_b28-01.S",
-  "rv64i_m/D/src/fmv.x.d_b29-01.S",
-  "rv64i_m/D/src/fnmadd.d_b14-01.S",
-  "rv64i_m/D/src/fnmadd.d_b16-01.S",
-  "rv64i_m/D/src/fnmadd.d_b17-01.S",
-  "rv64i_m/D/src/fnmadd.d_b18-01.S",
-  "rv64i_m/D/src/fnmadd.d_b2-01.S",
-  "rv64i_m/D/src/fnmadd.d_b3-01.S",
-  "rv64i_m/D/src/fnmadd.d_b4-01.S",
-  "rv64i_m/D/src/fnmadd.d_b5-01.S",
-  "rv64i_m/D/src/fnmadd.d_b6-01.S",
-  "rv64i_m/D/src/fnmadd.d_b7-01.S",
-  "rv64i_m/D/src/fnmadd.d_b8-01.S",
-  "rv64i_m/D/src/fnmsub.d_b14-01.S",
-  "rv64i_m/D/src/fnmsub.d_b16-01.S",
-  "rv64i_m/D/src/fnmsub.d_b17-01.S",
-  "rv64i_m/D/src/fnmsub.d_b18-01.S",
-  "rv64i_m/D/src/fnmsub.d_b2-01.S",
-  "rv64i_m/D/src/fnmsub.d_b3-01.S",
-  "rv64i_m/D/src/fnmsub.d_b4-01.S",
-  "rv64i_m/D/src/fnmsub.d_b5-01.S",
-  "rv64i_m/D/src/fnmsub.d_b6-01.S",
-  "rv64i_m/D/src/fnmsub.d_b7-01.S",
-  "rv64i_m/D/src/fnmsub.d_b8-01.S",
-  "rv64i_m/D/src/fsgnj.d_b1-01.S",
-  "rv64i_m/D/src/fsgnjn.d_b1-01.S",
-  "rv64i_m/D/src/fsgnjx.d_b1-01.S",
-  "rv64i_m/D/src/fssub.d_b10-01.S",
-  "rv64i_m/D/src/fssub.d_b1-01.S",
-  "rv64i_m/D/src/fssub.d_b11-01.S",
-  "rv64i_m/D/src/fssub.d_b12-01.S",
-  "rv64i_m/D/src/fssub.d_b13-01.S",
-  "rv64i_m/D/src/fssub.d_b2-01.S",
-  "rv64i_m/D/src/fssub.d_b3-01.S",
-  "rv64i_m/D/src/fssub.d_b4-01.S",
-  "rv64i_m/D/src/fssub.d_b5-01.S",
-  "rv64i_m/D/src/fssub.d_b7-01.S",
-  "rv64i_m/D/src/fssub.d_b8-01.S"
-};
-
-string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
-  `RISCVARCHTEST,
-  "rv64i_m/CMO/src/cbo.zero-01.S"
-};
-
-string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
-  `RISCVARCHTEST,
-  "rv32i_m/CMO/src/cbo.zero-01.S"
-};
-
-string arch64zcb[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/C/src/clbu-01.S",
-  "rv64i_m/C/src/clh-01.S",
-  "rv64i_m/C/src/clhu-01.S",
-  "rv64i_m/C/src/csb-01.S",
-  "rv64i_m/C/src/csh-01.S",
-  "rv64i_m/C/src/csext.b-01.S",
-  "rv64i_m/C/src/csext.h-01.S",
-  "rv64i_m/C/src/czext.b-01.S",
-  "rv64i_m/C/src/czext.h-01.S",
-  "rv64i_m/C/src/cmul-01.S",
-  "rv64i_m/C/src/cnot-01.S",
-  "rv64i_m/C/src/czext.w-01.S"
-};
-
-string arch32zcb[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/C/src/clbu-01.S",
-  "rv32i_m/C/src/clh-01.S",
-  "rv32i_m/C/src/clhu-01.S",
-  "rv32i_m/C/src/csb-01.S",
-  "rv32i_m/C/src/csh-01.S",
-  "rv32i_m/C/src/csext.b-01.S",
-  "rv32i_m/C/src/csext.h-01.S",
-  "rv32i_m/C/src/czext.b-01.S",
-  "rv32i_m/C/src/czext.h-01.S",
-  "rv32i_m/C/src/cmul-01.S",
-  "rv32i_m/C/src/cnot-01.S"
-};
-
-string arch64zba[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/B/src/slli.uw-01.S",
-  "rv64i_m/B/src/add.uw-01.S",
-  "rv64i_m/B/src/sh1add-01.S",
-  "rv64i_m/B/src/sh2add-01.S",
-  "rv64i_m/B/src/sh3add-01.S",
-  "rv64i_m/B/src/sh1add.uw-01.S",
-  "rv64i_m/B/src/sh2add.uw-01.S",
-  "rv64i_m/B/src/sh3add.uw-01.S"
-};
-
-string arch64zbb[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/B/src/max-01.S",
-  "rv64i_m/B/src/maxu-01.S",
-  "rv64i_m/B/src/min-01.S",
-  "rv64i_m/B/src/minu-01.S",
-  "rv64i_m/B/src/orcb_64-01.S",
-  "rv64i_m/B/src/rev8-01.S",
-  "rv64i_m/B/src/andn-01.S",
-  "rv64i_m/B/src/orn-01.S",
-  "rv64i_m/B/src/xnor-01.S",
-  "rv64i_m/B/src/zext.h_64-01.S",
-  "rv64i_m/B/src/sext.b-01.S",
-  "rv64i_m/B/src/sext.h-01.S",
-  "rv64i_m/B/src/clz-01.S",
-  "rv64i_m/B/src/clzw-01.S",
-  "rv64i_m/B/src/cpop-01.S",
-  "rv64i_m/B/src/cpopw-01.S",
-  "rv64i_m/B/src/ctz-01.S",
-  "rv64i_m/B/src/ctzw-01.S",
-  "rv64i_m/B/src/rolw-01.S",
-  "rv64i_m/B/src/ror-01.S",
-  "rv64i_m/B/src/rori-01.S",
-  "rv64i_m/B/src/roriw-01.S",
-  "rv64i_m/B/src/rorw-01.S",
-  "rv64i_m/B/src/rol-01.S"
-};
-
-string arch64zbc[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/B/src/clmul-01.S",
-  "rv64i_m/B/src/clmulh-01.S",
-  "rv64i_m/B/src/clmulr-01.S"
-};
-
-string arch64zbs[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/B/src/bclr-01.S",
-  "rv64i_m/B/src/bclri-01.S",
-  "rv64i_m/B/src/bext-01.S",
-  "rv64i_m/B/src/bexti-01.S",
-  "rv64i_m/B/src/binv-01.S",
-  "rv64i_m/B/src/binvi-01.S",
-  "rv64i_m/B/src/bset-01.S",
-  "rv64i_m/B/src/bseti-01.S"
-};
-
-string arch64zbkc[] = '{
-`RISCVARCHTEST,
-"rv64i_m/B/src/clmul-01.S",
-"rv64i_m/B/src/clmulh-01.S"
-};
-
-string arch64zbkx[] = '{
-`RISCVARCHTEST,
-"rv64i_m/K/src/xperm8-01.S",
-"rv64i_m/K/src/xperm4-01.S"
-};
-
-string arch64zknd[] = '{
-`RISCVARCHTEST,
-"rv64i_m/K/src/aes64ds-01.S",
-"rv64i_m/K/src/aes64dsm-01.S",
-"rv64i_m/K/src/aes64im-01.S",
-"rv64i_m/K/src/aes64ks1i-01.S",
-"rv64i_m/K/src/aes64ks2-01.S"
-};
-
-string arch64zkne[] = '{
-`RISCVARCHTEST,
-"rv64i_m/K/src/aes64es-01.S",
-"rv64i_m/K/src/aes64esm-01.S",
-"rv64i_m/K/src/aes64ks1i-01.S",
-"rv64i_m/K/src/aes64ks2-01.S"
-};
-
-string arch64zknh[] = '{
-`RISCVARCHTEST,
-"rv64i_m/K/src/sha256sig0-01.S",
-"rv64i_m/K/src/sha256sig1-01.S",
-"rv64i_m/K/src/sha256sum0-01.S",
-"rv64i_m/K/src/sha256sum1-01.S",
-"rv64i_m/K/src/sha512sig0-01.S",
-"rv64i_m/K/src/sha512sig1-01.S",
-"rv64i_m/K/src/sha512sum0-01.S",
-"rv64i_m/K/src/sha512sum1-01.S"
-};
-
-string arch32priv[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/privilege/src/ebreak.S",
-  "rv32i_m/privilege/src/ecall.S",
-  "rv32i_m/privilege/src/misalign2-jalr-01.S",
-  "rv32i_m/privilege/src/misalign-beq-01.S",
-  "rv32i_m/privilege/src/misalign-bge-01.S",
-  "rv32i_m/privilege/src/misalign-bgeu-01.S",
-  "rv32i_m/privilege/src/misalign-blt-01.S",
-  "rv32i_m/privilege/src/misalign-bltu-01.S",
-  "rv32i_m/privilege/src/misalign-bne-01.S",
-  "rv32i_m/privilege/src/misalign-jal-01.S",
-  "rv32i_m/privilege/src/misalign-lh-01.S",
-  "rv32i_m/privilege/src/misalign-lhu-01.S",
-  "rv32i_m/privilege/src/misalign-lw-01.S",
-  "rv32i_m/privilege/src/misalign-sh-01.S",
-  "rv32i_m/privilege/src/misalign-sw-01.S"
-};
-
-string arch32m[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/M/src/div-01.S",
-  "rv32i_m/M/src/divu-01.S",
-  "rv32i_m/M/src/rem-01.S",
-  "rv32i_m/M/src/remu-01.S",
-  "rv32i_m/M/src/mul-01.S",
-  "rv32i_m/M/src/mulh-01.S",
-  "rv32i_m/M/src/mulhsu-01.S",
-  "rv32i_m/M/src/mulhu-01.S"
-};
-
-string arch32f_fma[] = '{
-  `RISCVARCHTEST,
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-001.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-002.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-003.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-004.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-005.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-006.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-007.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-008.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-009.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-010.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-011.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-012.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-013.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-014.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-015.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-016.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-017.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-018.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-019.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-020.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-021.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-022.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-023.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-024.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-025.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-026.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-027.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-028.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-029.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-030.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-031.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-032.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-033.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-034.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-035.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-036.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-037.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-038.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-039.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-040.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-041.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-042.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-043.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-044.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-045.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-046.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-047.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-048.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-049.S",
-  // "rv32i_m/F/src/fmadd_b15/fmadd_b15-050.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-001.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-002.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-003.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-004.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-005.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-006.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-007.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-008.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-009.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-010.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-011.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-012.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-013.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-014.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-015.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-016.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-017.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-018.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-019.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-020.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-021.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-022.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-023.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-024.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-025.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-026.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-027.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-028.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-029.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-030.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-031.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-032.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-033.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-034.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-035.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-036.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-037.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-038.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-039.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-040.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-041.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-042.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-043.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-044.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-045.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-046.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-047.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-048.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-049.S",
-  "rv32i_m/F/src/fmsub_b15/fmsub_b15-050.S"
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-001.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-002.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-003.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-004.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-005.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-006.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-007.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-008.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-009.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-010.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-011.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-012.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-013.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-014.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-015.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-016.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-017.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-018.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-019.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-020.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-021.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-022.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-023.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-024.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-025.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-026.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-027.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-028.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-029.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-030.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-031.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-032.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-033.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-034.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-035.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-036.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-037.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-038.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-039.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-040.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-041.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-042.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-043.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-044.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-045.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-046.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-047.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-048.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-049.S",
-  // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-050.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-001.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-002.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-003.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-004.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-005.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-006.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-007.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-008.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-009.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-010.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-011.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-012.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-013.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-014.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-015.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-016.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-017.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-018.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-019.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-020.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-021.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-022.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-023.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-024.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-025.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-026.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-027.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-028.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-029.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-030.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-031.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-032.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-033.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-034.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-035.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-036.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-037.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-038.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-039.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-040.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-041.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-042.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-043.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-044.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-045.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-046.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-047.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-048.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-049.S",
-  // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-050.S"
-};
-
-string arch32f_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/F/src/fdiv_b20-01.S",
-  "rv32i_m/F/src/fdiv_b1-01.S",
-  "rv32i_m/F/src/fdiv_b2-01.S",
-  "rv32i_m/F/src/fdiv_b21-01.S",
-  "rv32i_m/F/src/fdiv_b3-01.S",
-  "rv32i_m/F/src/fdiv_b4-01.S",
-  "rv32i_m/F/src/fdiv_b5-01.S",
-  "rv32i_m/F/src/fdiv_b6-01.S",
-  "rv32i_m/F/src/fdiv_b7-01.S",
-  "rv32i_m/F/src/fdiv_b8-01.S",
-  "rv32i_m/F/src/fdiv_b9-01.S",
-  "rv32i_m/F/src/fsqrt_b1-01.S",
-  "rv32i_m/F/src/fsqrt_b20-01.S",
-  "rv32i_m/F/src/fsqrt_b2-01.S",
-  "rv32i_m/F/src/fsqrt_b3-01.S",
-  "rv32i_m/F/src/fsqrt_b4-01.S",
-  "rv32i_m/F/src/fsqrt_b5-01.S",
-  "rv32i_m/F/src/fsqrt_b7-01.S",
-  "rv32i_m/F/src/fsqrt_b8-01.S",
-  "rv32i_m/F/src/fsqrt_b9-01.S"
-};
-
-string arch32f[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/F/src/fadd_b11-01.S",
-  "rv32i_m/F/src/fadd_b10-01.S",
-  "rv32i_m/F/src/fadd_b1-01.S",
-  "rv32i_m/F/src/fadd_b11-01.S",
-  "rv32i_m/F/src/fadd_b12-01.S",
-  "rv32i_m/F/src/fadd_b13-01.S",
-  "rv32i_m/F/src/fadd_b2-01.S",
-  "rv32i_m/F/src/fadd_b3-01.S",
-  "rv32i_m/F/src/fadd_b4-01.S",
-  "rv32i_m/F/src/fadd_b5-01.S",
-  "rv32i_m/F/src/fadd_b7-01.S",
-  "rv32i_m/F/src/fadd_b8-01.S",
-  "rv32i_m/F/src/fclass_b1-01.S",
-  "rv32i_m/F/src/fcvt.s.w_b25-01.S",
-  "rv32i_m/F/src/fcvt.s.w_b26-01.S",
-  "rv32i_m/F/src/fcvt.s.wu_b25-01.S",
-  "rv32i_m/F/src/fcvt.s.wu_b26-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b1-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b22-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b23-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b24-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b27-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b28-01.S",
-  "rv32i_m/F/src/fcvt.w.s_b29-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b1-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b22-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b23-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b24-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b27-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b28-01.S",
-  "rv32i_m/F/src/fcvt.wu.s_b29-01.S",
-  "rv32i_m/F/src/feq_b1-01.S",
-  "rv32i_m/F/src/feq_b19-01.S",
-  "rv32i_m/F/src/fle_b1-01.S",
-  "rv32i_m/F/src/fle_b19-01.S",
-  "rv32i_m/F/src/flt_b1-01.S",
-  "rv32i_m/F/src/flt_b19-01.S",
-  "rv32i_m/F/src/flw-align-01.S",
-  "rv32i_m/F/src/fmadd_b1-01.S",
-  "rv32i_m/F/src/fmadd_b14-01.S",
-  "rv32i_m/F/src/fmadd_b16-01.S",
-  "rv32i_m/F/src/fmadd_b17-01.S",
-  "rv32i_m/F/src/fmadd_b18-01.S",
-  "rv32i_m/F/src/fmadd_b2-01.S",
-  "rv32i_m/F/src/fmadd_b3-01.S",
-  "rv32i_m/F/src/fmadd_b4-01.S",
-  "rv32i_m/F/src/fmadd_b5-01.S",
-  "rv32i_m/F/src/fmadd_b6-01.S",
-  "rv32i_m/F/src/fmadd_b7-01.S",
-  "rv32i_m/F/src/fmadd_b8-01.S",
-  "rv32i_m/F/src/fmax_b1-01.S",
-  "rv32i_m/F/src/fmax_b19-01.S",
-  "rv32i_m/F/src/fmin_b1-01.S",
-  "rv32i_m/F/src/fmin_b19-01.S",
-  "rv32i_m/F/src/fmsub_b1-01.S",
-  "rv32i_m/F/src/fmsub_b14-01.S",
-  "rv32i_m/F/src/fmsub_b16-01.S",
-  "rv32i_m/F/src/fmsub_b17-01.S",
-  "rv32i_m/F/src/fmsub_b18-01.S",
-  "rv32i_m/F/src/fmsub_b2-01.S",
-  "rv32i_m/F/src/fmsub_b3-01.S",
-  "rv32i_m/F/src/fmsub_b4-01.S",
-  "rv32i_m/F/src/fmsub_b5-01.S",
-  "rv32i_m/F/src/fmsub_b6-01.S",
-  "rv32i_m/F/src/fmsub_b7-01.S",
-  "rv32i_m/F/src/fmsub_b8-01.S",
-  "rv32i_m/F/src/fmul_b1-01.S",
-  "rv32i_m/F/src/fmul_b2-01.S",
-  "rv32i_m/F/src/fmul_b3-01.S",
-  "rv32i_m/F/src/fmul_b4-01.S",
-  "rv32i_m/F/src/fmul_b5-01.S",
-  "rv32i_m/F/src/fmul_b6-01.S",
-  "rv32i_m/F/src/fmul_b7-01.S",
-  "rv32i_m/F/src/fmul_b8-01.S",
-  "rv32i_m/F/src/fmul_b9-01.S",
-  "rv32i_m/F/src/fmv.w.x_b25-01.S",
-  "rv32i_m/F/src/fmv.w.x_b26-01.S",
-  "rv32i_m/F/src/fmv.x.w_b1-01.S",
-  "rv32i_m/F/src/fmv.x.w_b22-01.S",
-  "rv32i_m/F/src/fmv.x.w_b23-01.S",
-  "rv32i_m/F/src/fmv.x.w_b24-01.S",
-  "rv32i_m/F/src/fmv.x.w_b27-01.S",
-  "rv32i_m/F/src/fmv.x.w_b28-01.S",
-  "rv32i_m/F/src/fmv.x.w_b29-01.S",
-  "rv32i_m/F/src/fnmadd_b1-01.S",
-  "rv32i_m/F/src/fnmadd_b14-01.S",
-  "rv32i_m/F/src/fnmadd_b16-01.S",
-  "rv32i_m/F/src/fnmadd_b17-01.S",
-  "rv32i_m/F/src/fnmadd_b18-01.S",
-  "rv32i_m/F/src/fnmadd_b2-01.S",
-  "rv32i_m/F/src/fnmadd_b3-01.S",
-  "rv32i_m/F/src/fnmadd_b4-01.S",
-  "rv32i_m/F/src/fnmadd_b5-01.S",
-  "rv32i_m/F/src/fnmadd_b6-01.S",
-  "rv32i_m/F/src/fnmadd_b7-01.S",
-  "rv32i_m/F/src/fnmadd_b8-01.S",
-  "rv32i_m/F/src/fnmsub_b1-01.S",
-  "rv32i_m/F/src/fnmsub_b14-01.S",
-  "rv32i_m/F/src/fnmsub_b16-01.S",
-  "rv32i_m/F/src/fnmsub_b17-01.S",
-  "rv32i_m/F/src/fnmsub_b18-01.S",
-  "rv32i_m/F/src/fnmsub_b2-01.S",
-  "rv32i_m/F/src/fnmsub_b3-01.S",
-  "rv32i_m/F/src/fnmsub_b4-01.S",
-  "rv32i_m/F/src/fnmsub_b5-01.S",
-  "rv32i_m/F/src/fnmsub_b6-01.S",
-  "rv32i_m/F/src/fnmsub_b7-01.S",
-  "rv32i_m/F/src/fnmsub_b8-01.S",
-  "rv32i_m/F/src/fsgnj_b1-01.S",
-  "rv32i_m/F/src/fsgnjn_b1-01.S",
-  "rv32i_m/F/src/fsgnjx_b1-01.S",
-  "rv32i_m/F/src/fsub_b10-01.S",
-  "rv32i_m/F/src/fsub_b1-01.S",
-  "rv32i_m/F/src/fsub_b11-01.S",
-  "rv32i_m/F/src/fsub_b12-01.S",
-  "rv32i_m/F/src/fsub_b13-01.S",
-  "rv32i_m/F/src/fsub_b2-01.S",
-  "rv32i_m/F/src/fsub_b3-01.S",
-  "rv32i_m/F/src/fsub_b4-01.S",
-  "rv32i_m/F/src/fsub_b5-01.S",
-  "rv32i_m/F/src/fsub_b7-01.S",
-  "rv32i_m/F/src/fsub_b8-01.S",
-  "rv32i_m/F/src/fsw-align-01.S"
-};
-
-string arch32zfh_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/Zfh/src/fdiv_b20-01.S",
-  "rv32i_m/Zfh/src/fdiv_b1-01.S",
-  "rv32i_m/Zfh/src/fdiv_b2-01.S",
-  "rv32i_m/Zfh/src/fdiv_b21-01.S",
-  "rv32i_m/Zfh/src/fdiv_b3-01.S",
-  "rv32i_m/Zfh/src/fdiv_b4-01.S",
-  "rv32i_m/Zfh/src/fdiv_b5-01.S",
-  "rv32i_m/Zfh/src/fdiv_b6-01.S",
-  "rv32i_m/Zfh/src/fdiv_b7-01.S",
-  "rv32i_m/Zfh/src/fdiv_b8-01.S",
-  "rv32i_m/Zfh/src/fdiv_b9-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b1-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b20-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b2-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b3-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b4-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b5-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b7-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b8-01.S",
-  "rv32i_m/Zfh/src/fsqrt_b9-01.S"
-};
-
-string arch32zfh[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/Zfh/src/fadd_b10-01.S",
-  "rv32i_m/Zfh/src/fadd_b1-01.S",
-  "rv32i_m/Zfh/src/fadd_b11-01.S",
-  "rv32i_m/Zfh/src/fadd_b12-01.S",
-  "rv32i_m/Zfh/src/fadd_b13-01.S",
-  "rv32i_m/Zfh/src/fadd_b2-01.S",
-  "rv32i_m/Zfh/src/fadd_b3-01.S",
-  "rv32i_m/Zfh/src/fadd_b4-01.S",
-  "rv32i_m/Zfh/src/fadd_b5-01.S",
-  "rv32i_m/Zfh/src/fadd_b7-01.S",
-  "rv32i_m/Zfh/src/fadd_b8-01.S",
-  "rv32i_m/Zfh/src/fclass_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.s_b29-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.w_b25-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.w_b26-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.s.h_b29-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.w.h_b29-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S",
-  "rv32i_m/Zfh/src/feq_b1-01.S",
-  "rv32i_m/Zfh/src/feq_b19-01.S",
-  "rv32i_m/Zfh/src/fle_b1-01.S",
-  "rv32i_m/Zfh/src/fle_b19-01.S",
-  "rv32i_m/Zfh/src/flt_b1-01.S",
-  "rv32i_m/Zfh/src/flt_b19-01.S",
-  "rv32i_m/Zfh/src/flh-align-01.S",
-  "rv32i_m/Zfh/src/fmax_b1-01.S",
-  "rv32i_m/Zfh/src/fmax_b19-01.S",
-  "rv32i_m/Zfh/src/fmin_b1-01.S",
-  "rv32i_m/Zfh/src/fmin_b19-01.S",
-  "rv32i_m/Zfh/src/fmul_b1-01.S",
-  "rv32i_m/Zfh/src/fmul_b2-01.S",
-  "rv32i_m/Zfh/src/fmul_b3-01.S",
-  "rv32i_m/Zfh/src/fmul_b4-01.S",
-  "rv32i_m/Zfh/src/fmul_b5-01.S",
-  "rv32i_m/Zfh/src/fmul_b6-01.S",
-  "rv32i_m/Zfh/src/fmul_b7-01.S",
-  "rv32i_m/Zfh/src/fmul_b8-01.S",
-  "rv32i_m/Zfh/src/fmul_b9-01.S",
-  "rv32i_m/Zfh/src/fmv.h.x_b25-01.S",
-  "rv32i_m/Zfh/src/fmv.h.x_b26-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b1-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b22-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b23-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b24-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b27-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b28-01.S",
-  "rv32i_m/Zfh/src/fmv.x.h_b29-01.S",
-  "rv32i_m/Zfh/src/fsgnj_b1-01.S",
-  "rv32i_m/Zfh/src/fsgnjn_b1-01.S",
-  "rv32i_m/Zfh/src/fsgnjx_b1-01.S",
-  "rv32i_m/Zfh/src/fsub_b10-01.S",
-  "rv32i_m/Zfh/src/fsub_b1-01.S",
-  "rv32i_m/Zfh/src/fsub_b11-01.S",
-  "rv32i_m/Zfh/src/fsub_b12-01.S",
-  "rv32i_m/Zfh/src/fsub_b13-01.S",
-  "rv32i_m/Zfh/src/fsub_b2-01.S",
-  "rv32i_m/Zfh/src/fsub_b3-01.S",
-  "rv32i_m/Zfh/src/fsub_b4-01.S",
-  "rv32i_m/Zfh/src/fsub_b5-01.S",
-  "rv32i_m/Zfh/src/fsub_b7-01.S",
-  "rv32i_m/Zfh/src/fsub_b8-01.S",
-  "rv32i_m/Zfh/src/fsh-align-01.S",
-  "rv32i_m/Zfh/src/fmadd_b1-01.S",
-  "rv32i_m/Zfh/src/fmadd_b14-01.S",
-  "rv32i_m/Zfh/src/fmadd_b16-01.S",
-  "rv32i_m/Zfh/src/fmadd_b17-01.S",
-  "rv32i_m/Zfh/src/fmadd_b18-01.S",
-  "rv32i_m/Zfh/src/fmadd_b2-01.S",
-  "rv32i_m/Zfh/src/fmadd_b3-01.S",
-  "rv32i_m/Zfh/src/fmadd_b4-01.S",
-  "rv32i_m/Zfh/src/fmadd_b5-01.S",
-  "rv32i_m/Zfh/src/fmadd_b6-01.S",
-  "rv32i_m/Zfh/src/fmadd_b7-01.S",
-  "rv32i_m/Zfh/src/fmadd_b8-01.S",
-  "rv32i_m/Zfh/src/fmsub_b1-01.S",
-  "rv32i_m/Zfh/src/fmsub_b14-01.S",
-  "rv32i_m/Zfh/src/fmsub_b16-01.S",
-  "rv32i_m/Zfh/src/fmsub_b17-01.S",
-  "rv32i_m/Zfh/src/fmsub_b18-01.S",
-  "rv32i_m/Zfh/src/fmsub_b2-01.S",
-  "rv32i_m/Zfh/src/fmsub_b3-01.S",
-  "rv32i_m/Zfh/src/fmsub_b4-01.S",
-  "rv32i_m/Zfh/src/fmsub_b5-01.S",
-  "rv32i_m/Zfh/src/fmsub_b6-01.S",
-  "rv32i_m/Zfh/src/fmsub_b7-01.S",
-  "rv32i_m/Zfh/src/fmsub_b8-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b1-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b14-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b16-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b17-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b18-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b2-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b3-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b4-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b5-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b6-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b7-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b8-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b1-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b14-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b16-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b17-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b18-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b2-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b3-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b4-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b5-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b6-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b7-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b8-01.S"
-};
-
-string arch32zfh_d[] = '{
-  // `RISCVARCHTEST,
-  "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S",
-  "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S"
-};
-
-string arch32zfaf[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/F_Zfa/src/fround_b1-01.S",
-  "rv32i_m/F_Zfa/src/froundnx_b1-01.S",
-  "rv32i_m/F_Zfa/src/fleq_b1-01.S",
-  "rv32i_m/F_Zfa/src/fleq_b19-01.S",
-  "rv32i_m/F_Zfa/src/fli.s-01.S",
-  "rv32i_m/F_Zfa/src/fltq_b1-01.S",
-  "rv32i_m/F_Zfa/src/fltq_b19-01.S",
-  "rv32i_m/D_Zfa/src/fltq_b1-01.S", // these D tests are more comprehensive and seem they should replace the F tests.  Applies to all F tests duplicated in D
-  "rv32i_m/D_Zfa/src/fltq_b19-01.S",
-  "rv32i_m/F_Zfa/src/fminm_b1-01.S",
-  "rv32i_m/F_Zfa/src/fminm_b19-01.S",
-  "rv32i_m/F_Zfa/src/fmaxm_b1-01.S",
-  "rv32i_m/F_Zfa/src/fmaxm_b19-01.S"
-};
-
-string arch32zfad[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/D_Zfa/src/fround_b1-01.S",
-  "rv32i_m/D_Zfa/src/froundnx_b1-01.S",
-  "rv32i_m/D_Zfa/src/fround.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/froundnx.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S",
-  "rv32i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S",
-  "rv32i_m/D_Zfa/src/fleq_b1-01.S",
-  "rv32i_m/D_Zfa/src/fleq_b19-01.S",
-  "rv32i_m/D_Zfa/src/fleq.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fleq.d_b19-01.S",
-  "rv32i_m/D_Zfa/src/fli.d-01.S",
-  "rv32i_m/D_Zfa/src/fltq_b1-01.S",
-  "rv32i_m/D_Zfa/src/fltq_b19-01.S",
-  "rv32i_m/D_Zfa/src/fltq.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fltq.d_b19-01.S",
-  "rv32i_m/D_Zfa/src/fminm_b1-01.S",
-  "rv32i_m/D_Zfa/src/fminm_b19-01.S",
-  "rv32i_m/D_Zfa/src/fminm.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fminm.d_b19-01.S",
-  "rv32i_m/D_Zfa/src/fmaxm_b1-01.S",
-  "rv32i_m/D_Zfa/src/fmaxm_b19-01.S",
-  "rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b1-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b22-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b23-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b24-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S",
-  "rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S"
-};
-
-string arch64zfaf[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/F_Zfa/src/fround_b1-01.S",
-  "rv64i_m/F_Zfa/src/froundnx_b1-01.S",
-  "rv64i_m/F_Zfa/src/fleq_b1-01.S",
-  "rv64i_m/F_Zfa/src/fleq_b19-01.S",
-  "rv64i_m/F_Zfa/src/fli.s-01.S",
-  "rv64i_m/F_Zfa/src/fltq_b1-01.S",
-  "rv64i_m/F_Zfa/src/fltq_b19-01.S",
-  "rv64i_m/F_Zfa/src/fminm_b1-01.S",
-  "rv64i_m/F_Zfa/src/fminm_b19-01.S",
-  "rv64i_m/F_Zfa/src/fmaxm_b1-01.S",
-  "rv64i_m/F_Zfa/src/fmaxm_b19-01.S"
-};
-
-string arch64zfad[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/D_Zfa/src/fround_b1-01.S",
-  "rv64i_m/D_Zfa/src/froundnx_b1-01.S",
-  "rv64i_m/D_Zfa/src/fround.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/froundnx.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S",
-  "rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S",
-  "rv64i_m/D_Zfa/src/fleq_b1-01.S",
-  "rv64i_m/D_Zfa/src/fleq_b19-01.S",
-  "rv64i_m/D_Zfa/src/fleq.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fleq.d_b19-01.S",
-  "rv64i_m/D_Zfa/src/fli.d-01.S",
-  "rv64i_m/D_Zfa/src/fltq_b1-01.S",
-  "rv64i_m/D_Zfa/src/fltq_b19-01.S",
-  "rv64i_m/D_Zfa/src/fltq.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fltq.d_b19-01.S",
-  "rv64i_m/D_Zfa/src/fminm_b1-01.S",
-  "rv64i_m/D_Zfa/src/fminm_b19-01.S",
-  "rv64i_m/D_Zfa/src/fminm.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fminm.d_b19-01.S",
-  "rv64i_m/D_Zfa/src/fmaxm_b1-01.S",
-  "rv64i_m/D_Zfa/src/fmaxm_b19-01.S",
-  "rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S",
-  "rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S"
-};
-
-string arch32d_fma[] = '{
-  `RISCVARCHTEST,
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-001.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-002.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-003.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-004.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-005.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-006.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-007.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-008.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-009.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-010.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-011.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-012.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-013.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-014.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-015.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-016.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-017.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-018.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-019.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-020.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-021.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-022.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-023.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-024.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-025.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-026.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-027.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-028.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-029.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-030.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-031.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-032.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-033.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-034.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-035.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-036.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-037.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-038.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-039.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-040.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-041.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-042.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-043.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-044.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-045.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-046.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-047.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-048.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-049.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-050.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-051.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-052.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-053.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-054.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-055.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-056.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-057.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-058.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-059.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-060.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-061.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-062.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-063.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-064.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-065.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-066.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-067.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-068.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-069.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-070.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-071.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-072.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-073.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-074.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-075.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-076.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-077.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-078.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-079.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-080.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-081.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-082.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-083.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-084.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-085.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-086.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-087.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-088.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-089.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-090.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-091.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-092.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-093.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-094.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-095.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-096.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-097.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-098.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-099.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-100.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-101.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-102.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-103.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-104.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-105.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-106.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-107.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-108.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-109.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-110.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-111.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-112.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-113.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-114.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-115.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-116.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-117.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-118.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-119.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-120.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-121.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-122.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-123.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-124.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-125.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-126.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-127.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-128.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-129.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-130.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-131.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-132.S",
-  // "rv32i_m/D/src/fmadd.d_b15/fmadd.d_b15-133.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-001.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-002.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-003.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-004.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-005.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-006.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-007.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-008.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-009.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-010.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-011.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-012.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-013.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-014.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-015.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-016.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-017.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-018.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-019.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-020.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-021.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-022.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-023.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-024.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-025.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-026.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-027.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-028.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-029.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-030.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-031.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-032.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-033.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-034.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-035.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-036.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-037.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-038.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-039.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-040.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-041.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-042.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-043.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-044.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-045.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-046.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-047.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-048.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-049.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-050.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-051.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-052.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-053.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-054.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-055.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-056.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-057.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-058.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-059.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-060.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-061.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-062.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-063.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-064.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-065.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-066.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-067.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-068.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-069.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-070.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-071.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-072.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-073.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-074.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-075.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-076.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-077.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-078.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-079.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-080.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-081.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-082.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-083.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-084.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-085.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-086.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-087.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-088.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-089.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-090.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-091.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-092.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-093.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-094.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-095.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-096.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-097.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-098.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-099.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-100.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-101.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-102.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-103.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-104.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-105.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-106.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-107.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-108.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-109.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-110.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-111.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-112.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-113.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-114.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-115.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-116.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-117.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-118.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-119.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-120.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-121.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-122.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-123.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-124.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-125.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-126.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-127.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-128.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-129.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-130.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-131.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-132.S",
-  // "rv32i_m/D/src/fmsub.d_b15/fmsub.d_b15-133.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-001.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-002.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-003.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-004.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-005.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-006.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-007.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-008.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-009.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-010.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-011.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-012.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-013.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-014.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-015.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-016.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-017.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-018.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-019.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-020.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-021.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-022.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-023.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-024.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-025.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-026.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-027.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-028.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-029.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-030.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-031.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-032.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-033.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-034.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-035.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-036.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-037.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-038.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-039.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-040.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-041.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-042.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-043.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-044.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-045.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-046.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-047.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-048.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-049.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-050.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-051.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-052.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-053.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-054.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-055.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-056.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-057.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-058.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-059.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-060.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-061.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-062.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-063.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-064.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-065.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-066.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-067.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-068.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-069.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-070.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-071.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-072.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-073.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-074.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-075.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-076.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-077.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-078.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-079.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-080.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-081.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-082.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-083.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-084.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-085.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-086.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-087.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-088.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-089.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-090.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-091.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-092.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-093.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-094.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-095.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-096.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-097.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-098.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-099.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-100.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-101.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-102.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-103.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-104.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-105.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-106.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-107.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-108.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-109.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-110.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-111.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-112.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-113.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-114.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-115.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-116.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-117.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-118.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-119.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-120.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-121.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-122.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-123.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-124.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-125.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-126.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-127.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-128.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-129.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-130.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-131.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-132.S",
-  // "rv32i_m/D/src/fnmadd.d_b15/fnmadd.d_b15-133.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-001.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-002.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-003.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-004.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-005.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-006.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-007.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-008.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-009.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-010.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-011.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-012.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-013.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-014.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-015.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-016.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-017.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-018.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-019.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-020.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-021.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-022.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-023.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-024.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-025.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-026.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-027.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-028.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-029.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-030.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-031.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-032.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-033.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-034.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-035.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-036.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-037.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-038.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-039.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-040.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-041.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-042.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-043.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-044.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-045.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-046.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-047.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-048.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-049.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-050.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-051.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-052.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-053.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-054.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-055.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-056.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-057.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-058.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-059.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-060.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-061.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-062.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-063.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-064.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-065.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-066.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-067.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-068.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-069.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-070.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-071.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-072.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-073.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-074.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-075.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-076.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-077.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-078.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-079.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-080.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-081.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-082.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-083.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-084.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-085.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-086.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-087.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-088.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-089.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-090.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-091.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-092.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-093.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-094.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-095.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-096.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-097.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-098.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-099.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-100.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-101.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-102.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-103.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-104.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-105.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-106.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-107.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-108.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-109.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-110.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-111.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-112.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-113.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-114.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-115.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-116.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-117.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-118.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-119.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-120.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-121.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-122.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-123.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-124.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-125.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-126.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-127.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-128.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-129.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-130.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-131.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-132.S",
-  "rv32i_m/D/src/fnmsub.d_b15/fnmsub.d_b15-133.S"
-};
-
-string arch32zfh_fma[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/Zfh/src/fmadd_b15-01.S",
-  "rv32i_m/Zfh/src/fmsub_b15-01.S",
-  "rv32i_m/Zfh/src/fnmadd_b15-01.S",
-  "rv32i_m/Zfh/src/fnmsub_b15-01.S"
-};
-
-string arch32d_divsqrt[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/D/src/fdiv.d_b1-01.S",
-  "rv32i_m/D/src/fdiv.d_b20-01.S",
-  "rv32i_m/D/src/fdiv.d_b2-01.S",
-  "rv32i_m/D/src/fdiv.d_b21-01.S",
-  "rv32i_m/D/src/fdiv.d_b3-01.S",
-  "rv32i_m/D/src/fdiv.d_b4-01.S",
-  "rv32i_m/D/src/fdiv.d_b5-01.S",
-  "rv32i_m/D/src/fdiv.d_b6-01.S",
-  "rv32i_m/D/src/fdiv.d_b7-01.S",
-  "rv32i_m/D/src/fdiv.d_b8-01.S",
-  "rv32i_m/D/src/fdiv.d_b9-01.S",
-  "rv32i_m/D/src/fsqrt.d_b1-01.S",
-  "rv32i_m/D/src/fsqrt.d_b20-01.S",
-  "rv32i_m/D/src/fsqrt.d_b2-01.S",
-  "rv32i_m/D/src/fsqrt.d_b3-01.S",
-  "rv32i_m/D/src/fsqrt.d_b4-01.S",
-  "rv32i_m/D/src/fsqrt.d_b5-01.S",
-  "rv32i_m/D/src/fsqrt.d_b7-01.S",
-  "rv32i_m/D/src/fsqrt.d_b8-01.S",
-  "rv32i_m/D/src/fsqrt.d_b9-01.S"
-};
-
-string arch32d[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/D/src/fadd.d_b10-01.S",
-  "rv32i_m/D/src/fadd.d_b1-01.S",
-  "rv32i_m/D/src/fadd.d_b11-01.S",
-  "rv32i_m/D/src/fadd.d_b12-01.S",
-  "rv32i_m/D/src/fadd.d_b13-01.S",
-  "rv32i_m/D/src/fadd.d_b2-01.S",
-  "rv32i_m/D/src/fadd.d_b3-01.S",
-  "rv32i_m/D/src/fadd.d_b4-01.S",
-  "rv32i_m/D/src/fadd.d_b5-01.S",
-  "rv32i_m/D/src/fadd.d_b7-01.S",
-  "rv32i_m/D/src/fadd.d_b8-01.S",
-  "rv32i_m/D/src/fclass.d_b1-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b1-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b22-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b23-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b24-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b27-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b28-01.S",
-  "rv32i_m/D/src/fcvt.d.s_b29-01.S",
-  "rv32i_m/D/src/fcvt.d.w_b25-01.S",
-  "rv32i_m/D/src/fcvt.d.w_b26-01.S",
-  "rv32i_m/D/src/fcvt.d.wu_b25-01.S",
-  "rv32i_m/D/src/fcvt.d.wu_b26-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b1-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b22-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b23-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b24-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b27-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b28-01.S",
-  "rv32i_m/D/src/fcvt.s.d_b29-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b1-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b22-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b23-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b24-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b27-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b28-01.S",
-  "rv32i_m/D/src/fcvt.w.d_b29-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b1-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b22-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b23-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b24-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b27-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b28-01.S",
-  "rv32i_m/D/src/fcvt.wu.d_b29-01.S",
-  "rv32i_m/D/src/feq.d_b1-01.S",
-  "rv32i_m/D/src/feq.d_b19-01.S",
-  "rv32i_m/D/src/fle.d_b1-01.S",
-  "rv32i_m/D/src/fle.d_b19-01.S",
-  "rv32i_m/D/src/flt.d_b1-01.S",
-  "rv32i_m/D/src/flt.d_b19-01.S",
-  "rv32i_m/D/src/fld-align-01.S",
-  "rv32i_m/D/src/fsd-align-01.S",
-  "rv32i_m/D/src/fmadd.d_b14-01.S",
-  "rv32i_m/D/src/fmadd.d_b16-01.S",
-  "rv32i_m/D/src/fmadd.d_b17-01.S",
-  "rv32i_m/D/src/fmadd.d_b18-01.S",
-  "rv32i_m/D/src/fmadd.d_b2-01.S",
-  "rv32i_m/D/src/fmadd.d_b3-01.S",
-  "rv32i_m/D/src/fmadd.d_b4-01.S",
-  "rv32i_m/D/src/fmadd.d_b5-01.S",
-  "rv32i_m/D/src/fmadd.d_b6-01.S",
-  "rv32i_m/D/src/fmadd.d_b7-01.S",
-  "rv32i_m/D/src/fmadd.d_b8-01.S",
-  "rv32i_m/D/src/fmax.d_b1-01.S",
-  "rv32i_m/D/src/fmax.d_b19-01.S",
-  "rv32i_m/D/src/fmin.d_b1-01.S",
-  "rv32i_m/D/src/fmin.d_b19-01.S",
-  "rv32i_m/D/src/fmsub.d_b14-01.S",
-  "rv32i_m/D/src/fmsub.d_b16-01.S",
-  "rv32i_m/D/src/fmsub.d_b17-01.S",
-  "rv32i_m/D/src/fmsub.d_b18-01.S",
-  "rv32i_m/D/src/fmsub.d_b2-01.S",
-  "rv32i_m/D/src/fmsub.d_b3-01.S",
-  "rv32i_m/D/src/fmsub.d_b4-01.S",
-  "rv32i_m/D/src/fmsub.d_b5-01.S",
-  "rv32i_m/D/src/fmsub.d_b6-01.S",
-  "rv32i_m/D/src/fmsub.d_b7-01.S",
-  "rv32i_m/D/src/fmsub.d_b8-01.S",
-  "rv32i_m/D/src/fmul.d_b1-01.S",
-  "rv32i_m/D/src/fmul.d_b2-01.S",
-  "rv32i_m/D/src/fmul.d_b3-01.S",
-  "rv32i_m/D/src/fmul.d_b4-01.S",
-  "rv32i_m/D/src/fmul.d_b5-01.S",
-  "rv32i_m/D/src/fmul.d_b6-01.S",
-  "rv32i_m/D/src/fmul.d_b7-01.S",
-  "rv32i_m/D/src/fmul.d_b8-01.S",
-  "rv32i_m/D/src/fmul.d_b9-01.S",
-  "rv32i_m/D/src/fnmadd.d_b14-01.S",
-  "rv32i_m/D/src/fnmadd.d_b16-01.S",
-  "rv32i_m/D/src/fnmadd.d_b17-01.S",
-  "rv32i_m/D/src/fnmadd.d_b18-01.S",
-  "rv32i_m/D/src/fnmadd.d_b2-01.S",
-  "rv32i_m/D/src/fnmadd.d_b3-01.S",
-  "rv32i_m/D/src/fnmadd.d_b4-01.S",
-  "rv32i_m/D/src/fnmadd.d_b5-01.S",
-  "rv32i_m/D/src/fnmadd.d_b6-01.S",
-  "rv32i_m/D/src/fnmadd.d_b7-01.S",
-  "rv32i_m/D/src/fnmadd.d_b8-01.S",
-  "rv32i_m/D/src/fnmsub.d_b14-01.S",
-  "rv32i_m/D/src/fnmsub.d_b16-01.S",
-  "rv32i_m/D/src/fnmsub.d_b17-01.S",
-  "rv32i_m/D/src/fnmsub.d_b18-01.S",
-  "rv32i_m/D/src/fnmsub.d_b2-01.S",
-  "rv32i_m/D/src/fnmsub.d_b3-01.S",
-  "rv32i_m/D/src/fnmsub.d_b4-01.S",
-  "rv32i_m/D/src/fnmsub.d_b5-01.S",
-  "rv32i_m/D/src/fnmsub.d_b6-01.S",
-  "rv32i_m/D/src/fnmsub.d_b7-01.S",
-  "rv32i_m/D/src/fnmsub.d_b8-01.S",
-  "rv32i_m/D/src/fsgnj.d_b1-01.S",
-  "rv32i_m/D/src/fsgnjn.d_b1-01.S",
-  "rv32i_m/D/src/fsgnjx.d_b1-01.S",
-  "rv32i_m/D/src/fssub.d_b10-01.S",
-  "rv32i_m/D/src/fssub.d_b1-01.S",
-  "rv32i_m/D/src/fssub.d_b11-01.S",
-  "rv32i_m/D/src/fssub.d_b12-01.S",
-  "rv32i_m/D/src/fssub.d_b13-01.S",
-  "rv32i_m/D/src/fssub.d_b2-01.S",
-  "rv32i_m/D/src/fssub.d_b3-01.S",
-  "rv32i_m/D/src/fssub.d_b4-01.S",
-  "rv32i_m/D/src/fssub.d_b5-01.S",
-  "rv32i_m/D/src/fssub.d_b7-01.S",
-  "rv32i_m/D/src/fssub.d_b8-01.S"
-};
-
-
-string arch32c[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/C/src/cadd-01.S",
-  "rv32i_m/C/src/caddi-01.S",
-  "rv32i_m/C/src/caddi16sp-01.S",
-  "rv32i_m/C/src/caddi4spn-01.S",
-  "rv32i_m/C/src/cand-01.S",
-  "rv32i_m/C/src/candi-01.S",
-  "rv32i_m/C/src/cbeqz-01.S",
-  "rv32i_m/C/src/cbnez-01.S",
-  "rv32i_m/C/src/cj-01.S",
-  "rv32i_m/C/src/cjal-01.S",
-  "rv32i_m/C/src/cjalr-01.S",
-  "rv32i_m/C/src/cjr-01.S",
-  "rv32i_m/C/src/cli-01.S",
-  "rv32i_m/C/src/clui-01.S",
-  "rv32i_m/C/src/clw-01.S",
-  "rv32i_m/C/src/clwsp-01.S",
-  "rv32i_m/C/src/cmv-01.S",
-  "rv32i_m/C/src/cnop-01.S",
-  "rv32i_m/C/src/cor-01.S",
-  "rv32i_m/C/src/cslli-01.S",
-  "rv32i_m/C/src/csrai-01.S",
-  "rv32i_m/C/src/csrli-01.S",
-  "rv32i_m/C/src/csub-01.S",
-  "rv32i_m/C/src/csw-01.S",
-  "rv32i_m/C/src/cswsp-01.S",
-  "rv32i_m/C/src/cxor-01.S",
-  "rv32i_m/C/src/misalign1-cjalr-01.S",
-  "rv32i_m/C/src/misalign1-cjr-01.S"
-};
-
-string arch32cpriv[] = '{
-  // `RISCVARCHTEST,
-  "rv32i_m/C/src/cebreak-01.S"
-};
-
-string arch32zcf[] = '{
-  // `RISCVARCHTEST,
-  "rv32i_m/F_Zcf/src/c.flw-01.S",
-  "rv32i_m/F_Zcf/src/c.flwsp-01.S",
-  "rv32i_m/F_Zcf/src/c.fsw-01.S",
-  "rv32i_m/F_Zcf/src/c.fswsp-01.S"
-};
-
-string arch32zcd[] = '{
-  // `RISCVARCHTEST,
-  "rv32i_m/D_Zcd/src/c.fld-01.S",
-  "rv32i_m/D_Zcd/src/c.fldsp-01.S",
-  "rv32i_m/D_Zcd/src/c.fsd-01.S",
-  "rv32i_m/D_Zcd/src/c.fsdsp-01.S"
-};
-
-string arch32i[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/I/src/add-01.S",
-  "rv32i_m/I/src/addi-01.S",
-  "rv32i_m/I/src/and-01.S",
-  "rv32i_m/I/src/andi-01.S",
-  "rv32i_m/I/src/auipc-01.S",
-  "rv32i_m/I/src/beq-01.S",
-  "rv32i_m/I/src/bge-01.S",
-  "rv32i_m/I/src/bgeu-01.S",
-  "rv32i_m/I/src/blt-01.S",
-  "rv32i_m/I/src/bltu-01.S",
-  "rv32i_m/I/src/bne-01.S",
-  "rv32i_m/I/src/fence-01.S",
-  "rv32i_m/I/src/jal-01.S",
-  "rv32i_m/I/src/jalr-01.S",
-  "rv32i_m/I/src/lb-align-01.S",
-  "rv32i_m/I/src/lbu-align-01.S",
-  "rv32i_m/I/src/lh-align-01.S",
-  "rv32i_m/I/src/lhu-align-01.S",
-  "rv32i_m/I/src/lui-01.S",
-  "rv32i_m/I/src/lw-align-01.S",
-  "rv32i_m/I/src/or-01.S",
-  "rv32i_m/I/src/ori-01.S",
-  "rv32i_m/I/src/sb-align-01.S",
-  "rv32i_m/I/src/sh-align-01.S",
-  "rv32i_m/I/src/sll-01.S",
-  "rv32i_m/I/src/slli-01.S",
-  "rv32i_m/I/src/slt-01.S",
-  "rv32i_m/I/src/slti-01.S",
-  "rv32i_m/I/src/sltiu-01.S",
-  "rv32i_m/I/src/sltu-01.S",
-  "rv32i_m/I/src/sra-01.S",
-  "rv32i_m/I/src/srai-01.S",
-  "rv32i_m/I/src/srl-01.S",
-  "rv32i_m/I/src/srli-01.S",
-  "rv32i_m/I/src/sub-01.S",
-  "rv32i_m/I/src/sw-align-01.S",
-  "rv32i_m/I/src/xor-01.S",
-  "rv32i_m/I/src/xori-01.S"
-};
-
-string arch32e[] = '{
-  `RISCVARCHTEST,
-  "rv32e_m/E/src/add-01.S",
-  "rv32e_m/E/src/addi-01.S",
-  "rv32e_m/E/src/and-01.S",
-  "rv32e_m/E/src/andi-01.S",
-  "rv32e_m/E/src/auipc-01.S",
-  "rv32e_m/E/src/bge-01.S",
-  "rv32e_m/E/src/bgeu-01.S",
-  "rv32e_m/E/src/blt-01.S",
-  "rv32e_m/E/src/bltu-01.S",
-  "rv32e_m/E/src/bne-01.S",
-  "rv32e_m/E/src/jal-01.S",
-  "rv32e_m/E/src/jalr-01.S",
-  "rv32e_m/E/src/lb-align-01.S",
-  "rv32e_m/E/src/lbu-align-01.S",
-  "rv32e_m/E/src/lh-align-01.S",
-  "rv32e_m/E/src/lhu-align-01.S",
-  "rv32e_m/E/src/lui-01.S",
-  "rv32e_m/E/src/lw-align-01.S",
-  "rv32e_m/E/src/or-01.S",
-  "rv32e_m/E/src/ori-01.S",
-  "rv32e_m/E/src/sb-align-01.S",
-  "rv32e_m/E/src/sh-align-01.S",
-  "rv32e_m/E/src/sll-01.S",
-  "rv32e_m/E/src/slli-01.S",
-  "rv32e_m/E/src/slt-01.S",
-  "rv32e_m/E/src/slti-01.S",
-  "rv32e_m/E/src/sltiu-01.S",
-  "rv32e_m/E/src/sltu-01.S",
-  "rv32e_m/E/src/sra-01.S",
-  "rv32e_m/E/src/srai-01.S",
-  "rv32e_m/E/src/srl-01.S",
-  "rv32e_m/E/src/srli-01.S",
-  "rv32e_m/E/src/sub-01.S",
-  "rv32e_m/E/src/sw-align-01.S",
-  "rv32e_m/E/src/xor-01.S",
-  "rv32e_m/E/src/xori-01.S"
-};
-
-string wally64priv[] = '{
-  `WALLYTEST,
-  "rv64i_m/privilege/src/WALLY-minfo-01.S",
-  "rv64i_m/privilege/src/WALLY-misaligned-access-01.S",
-  "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
-  "rv64i_m/privilege/src/WALLY-cboz-01.S",
-  "rv64i_m/privilege/src/WALLY-cbom-01.S",
-  "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
-  "rv64i_m/privilege/src/WALLY-mie-01.S",
-  "rv64i_m/privilege/src/WALLY-minfo-01.S",
-  "rv64i_m/privilege/src/WALLY-misa-01.S",
-  // "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S",  // run this if SVADU_SUPPORTED = 0
-  // "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S",  // run this if SVADU_SUPPORTED = 0
-  "rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S",  // run this if SVADU_SUPPORTED = 1
-  "rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S",  // run this if SVADU_SUPPORTED = 1
-  "rv64i_m/privilege/src/WALLY-mtvec-01.S",
-  "rv64i_m/privilege/src/WALLY-pma-01.S",
-  "rv64i_m/privilege/src/WALLY-pmp-01.S",
-  "rv64i_m/privilege/src/WALLY-sie-01.S",
-  "rv64i_m/privilege/src/WALLY-status-mie-01.S",
-  "rv64i_m/privilege/src/WALLY-status-sie-01.S",
-  "rv64i_m/privilege/src/WALLY-status-tw-01.S",
-  "rv64i_m/privilege/src/WALLY-status-tvm-01.S",
-  "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S",
-  "rv64i_m/privilege/src/WALLY-stvec-01.S",
-  "rv64i_m/privilege/src/WALLY-trap-01.S",
-  "rv64i_m/privilege/src/WALLY-trap-s-01.S",
-  "rv64i_m/privilege/src/WALLY-trap-sret-01.S",
-  "rv64i_m/privilege/src/WALLY-trap-u-01.S",
-  "rv64i_m/privilege/src/WALLY-wfi-01.S",
-  "rv64i_m/privilege/src/WALLY-endianness-01.S",
-  "rv64i_m/privilege/src/WALLY-status-xlen-01.S",
-  "rv64i_m/privilege/src/WALLY-satp-invalid-01.S"
-};
-
-string wally64periph[] = '{
-  `WALLYTEST,
-  "rv64i_m/privilege/src/WALLY-periph-01.S",
-  "rv64i_m/privilege/src/WALLY-clint-01.S",
-  "rv64i_m/privilege/src/WALLY-gpio-01.S",
-  "rv64i_m/privilege/src/WALLY-plic-01.S",
-  "rv64i_m/privilege/src/WALLY-plic-s-01.S",
-  "rv64i_m/privilege/src/WALLY-uart-01.S",
-  "rv64i_m/privilege/src/WALLY-spi-01.S"
-};
-
-string wally32priv[] = '{
-  `WALLYTEST,
-  "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
-  "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
-  // "rv32i_m/privilege/src/WALLY-cbom-01.S",
-  "rv32i_m/privilege/src/WALLY-cboz-01.S",
-  "rv32i_m/privilege/src/WALLY-mie-01.S",
-  "rv32i_m/privilege/src/WALLY-minfo-01.S",
-  "rv32i_m/privilege/src/WALLY-misa-01.S",
-  // "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",    // run this if SVADU_SUPPORTED = 0
-  "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S", // run this if SVADU_SUPPORTED = 1
-  "rv32i_m/privilege/src/WALLY-mtvec-01.S",
-  "rv32i_m/privilege/src/WALLY-pma-01.S",
-  "rv32i_m/privilege/src/WALLY-pmp-01.S",
-  "rv32i_m/privilege/src/WALLY-sie-01.S",
-  "rv32i_m/privilege/src/WALLY-status-mie-01.S",
-  "rv32i_m/privilege/src/WALLY-status-sie-01.S",
-  "rv32i_m/privilege/src/WALLY-status-tw-01.S",
-  "rv32i_m/privilege/src/WALLY-status-tvm-01.S",
-  "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S",
-  "rv32i_m/privilege/src/WALLY-stvec-01.S",
-  "rv32i_m/privilege/src/WALLY-trap-01.S",
-  "rv32i_m/privilege/src/WALLY-trap-s-01.S",
-  "rv32i_m/privilege/src/WALLY-trap-sret-01.S",
-  "rv32i_m/privilege/src/WALLY-trap-u-01.S",
-  "rv32i_m/privilege/src/WALLY-wfi-01.S",
-  "rv32i_m/privilege/src/WALLY-endianness-01.S",
-  "rv32i_m/privilege/src/WALLY-satp-invalid-01.S",
-  // These peripherals are here instead of wally32periph because they don't work on rv32imc, which lacks a PMP register to configure
-  "rv32i_m/privilege/src/WALLY-periph-s-01.S",
-  "rv32i_m/privilege/src/WALLY-gpio-01.S",
-  "rv32i_m/privilege/src/WALLY-clint-01.S",
-  "rv32i_m/privilege/src/WALLY-uart-01.S",
-  "rv32i_m/privilege/src/WALLY-plic-01.S",
-  "rv32i_m/privilege/src/WALLY-plic-s-01.S",
-  "rv32i_m/privilege/src/WALLY-spi-01.S"
-};
-
-string wally32periph[] = '{
-  `WALLYTEST,
-  "rv32i_m/privilege/src/WALLY-periph-01.S"
-};
-
-string fpga[] = '{
-  `CUSTOM,
-  "NULL"
-};
-
-string custom[] = '{
-  `CUSTOM,
-  "NULL"
-};
-
-string ahb64[] = '{
-  `RISCVARCHTEST,
-  "rv64i_m/F/src/fadd_b11-01.S"
-};
-
-string ahb32[] = '{
-  `RISCVARCHTEST,
-  "rv32i_m/F/src/fadd_b11-01.S"
-};
diff --git a/testbench/trek_files/Makefile b/testbench/trek_files/Makefile
deleted file mode 100644
index 62a045af2..000000000
--- a/testbench/trek_files/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-SHELL            := /bin/bash
-TREKFILES        := $(WALLY)/testbench/trek_files
-PLATFORM_YAML    := $(TREKFILES)/platform.yaml
-TREKSVIP_YAML    := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml
-TREKEXE_FLAGS    += --seed 0x # free (0x) or lock (0x1) the seed used for test generation
-TREKSVIP = source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS)
-
-uvm_output: uvm_output/trek_uvm.sv
-
-uvm_output/trek_uvm.sv: $(PLATFORM_YAML) $(TREKSVIP_YAML)
-	$(TREKSVIP) -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) --uvm_output=uvm_output
-
-clean:
-	rm -rf uvm_output
diff --git a/testbench/trek_files/README.md b/testbench/trek_files/README.md
deleted file mode 100644
index 1c7c14b38..000000000
--- a/testbench/trek_files/README.md
+++ /dev/null
@@ -1,9 +0,0 @@
-Jordan Carlin, jcarlin@hmc.edu, December 2024
-
-# Breker Trek Tests Support Files for CVW
-
-[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users).
-
-This directory contains the support files necessary to run Breker's Trek Tests on CVW. For additional details on the tests see [`$WALLY/tests/breker/README.md`](../../tests/breker/README.md)
-
-To generate the Breker support files (with a license), run `make` in the `testbench/trek_files` directory (this one). Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. This Makefile only needs to be run once.
diff --git a/testbench/trek_files/breker-setup.sh b/testbench/trek_files/breker-setup.sh
deleted file mode 100644
index 9b651eeef..000000000
--- a/testbench/trek_files/breker-setup.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/bash
-export BREKER_ARCH=${BREKER_HOME}/linux64
-export PATH=${BREKER_HOME}/bin:${BREKER_HOME}/examples/tutorials/apps/coherency/bin:${PATH}
-export LD_LIBRARY_PATH=".:${BREKER_ARCH}/lib:${BREKER_HOME}/opensrc/gcc/lib:${BREKER_HOME}/opensrc/gcc/lib64":${LD_LIBRARY_PATH}
-export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu/:$LIBRARY_PATH
diff --git a/testbench/trek_files/customer.yaml b/testbench/trek_files/customer.yaml
deleted file mode 100644
index 05ad17c86..000000000
--- a/testbench/trek_files/customer.yaml
+++ /dev/null
@@ -1,23 +0,0 @@
-trek:
-  svip:
-    global:
-      scenarios:
-        scenario_count:
-          # primary control for length of test
-          value: 50
-    riscv:
-      extensions:
-        # disable hypervisor extension by setting value to 0
-        # if your system does not support this feature
-        h_hypervisor:
-          value: 0
-
-  # uncomment the `weights:` line below if any entries under `weights:` need to be enabled
-  weights:
-    # disable testing of Sv57: Page-Based 57-bit Virtual-Memory System
-    # if your system does not support this feature
-    pss_top.rvMmu.rvMmuOp.RvMmuOp::satpModeSv57: 0
-
-    # qemu-riscv64 does not ignore writes to WARL bits in hgatp
-    # Comment out the next line unless your design has this issue
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::writeHgatpWarl : 0
diff --git a/testbench/trek_files/platform.yaml b/testbench/trek_files/platform.yaml
deleted file mode 100644
index c5b201342..000000000
--- a/testbench/trek_files/platform.yaml
+++ /dev/null
@@ -1,267 +0,0 @@
-trek:
-  platform_config:
-    doc: >-
-      Testbench platform specific configuration.
-    processors:
-      doc: >-
-        Information about available processors.
-      processor_count:
-        value: 1
-        doc: >-
-          How many processors can be used by the generated test case
-      sw_threads_per_processor:
-        value: 2
-        doc: >-
-          How many software threads to put on each processor
-    tlm_generic_ports:
-      doc: >-
-        Information about available tlm_generic_payload ports
-      port_count:
-        value: 0
-        doc: >-
-          How many tlm ports to use for memory operations
-      threads_per_port:
-        value: 4
-        doc: >-
-          How many threads to put on each tlm port
-      debug:
-        value: 1
-        doc: >-
-          Turn on for verbose tlm port messages
-    memories:
-      doc: >-
-        Information about memory regions that can be used by the generated test case.
-      defaults:
-        doc: >-
-          Default values for all memories
-        natural_alignment:
-          value: 1
-          doc: >-
-            Should all memory addresses be naturally aligned (up to 8 byte alignment)
-        init_type:
-          value: frontdoor
-          doc: >-
-            Strategy to use for memory initialization.
-            Options are:
-              - static
-              - backdoor
-              - frontdoor
-      memory:
-        doc: >-
-          Define a memory region.
-          Multiple memory regions may be defined in this section.
-        name:
-          value: ddr0
-          doc: >-
-            Name of the memory region
-        base:
-          value: 0x83000000
-          doc: >-
-            Base address of memory region.
-            Ignored for `static` initialized memory
-        size:
-          value: 0x100000
-          doc: >-
-            Size of memory region in bytes.
-        init_type:
-          value: backdoor #frontdoor
-          doc: >-
-            Strategy to use for memory initialization.
-            Options are:
-              - static
-              - backdoor
-              - frontdoor
-    caches:
-      doc: >-
-        parameters related to cache architecture
-      cache_line_size:
-        value: 64
-        doc: >-
-          Size of a cache line in bytes
-      llc_cache_size:
-        value: 0x200000
-        doc: >-
-          size of last level cache in bytes
-      llc_cache_ways:
-        value: 8
-        doc: >-
-          number of ways in the last level cache
-    mailbox:
-      doc: >-
-        Configure memory mailbox usage
-      type:
-        value: single
-        doc: >-
-          Configure mailbox type.
-          Options are:
-            - single: for use by TrekBox with backdoor access
-            - queue: for use in post-silicon post-process flow
-      single:
-        doc: >-
-          Detail settings when mailbox type is `single`
-        init_type:
-          value: backdoor #static
-          doc: >-
-            Strategy to use for mailbox memory initialization.
-            Options are:
-              - static
-              - backdoor
-              - frontdoor
-        c2t_base:
-          value: 0x82000000
-          doc: >-
-            Fixed base address of C to trekbox mailbox region.
-            Allow 64 bytes per processor.
-            Used for init_type of `backdoor` and `frontdoor` only.
-        t2c_base:
-          value: 0x82001000
-          doc: >-
-            Fixed base address of trekbox to C mailbox region.
-            Allow 64 bytes per processor.
-            Used for init_type of `backdoor` and `frontdoor` only.
-        cacheable:
-          value: 1
-          doc: >-
-            Set this parameter to 1 to do a cache flush after every mailbox
-            write.
-      queue:
-        doc: >-
-          Detail settings when mailbox type is `queue`
-        length:
-          value: 1000
-          doc: >-
-            Max number of messages that can be stored in the queue mailbox.
-            Longer tests may need a larger queue.
-        debug:
-          value: 0
-          doc: >-
-            If this flag is set to 1, messages will be printed directly to the
-            console instead of being queued in memory.
-    stdio:
-      doc: >-
-        Is the <stdio> standard library available for use by the generated test.
-      available:
-        value: 0
-        doc: >-
-          Set this value to 0 of the <stdio> library is not available in
-          your system.
-      use_lock:
-        value: 1
-        doc: >-
-          Calls to <stdio> console print messages will be mutex locked unless
-          this flag is set to 0.
-    header:
-      doc: >-
-        Verbatim code that will be put into the header section of the test.
-      value: |-
-        // enable mtimer  interrupts 
-        #define TREK_MTIME_BASE     (0x0200bff8)
-        #define TREK_MTIMECMP_BASE  (0x02004000)
-        #define TREK_MSWI_BASE      (0x02000000)
-        #define TREK_MTIMECMP_DELAY  0x1000
-    declaration:
-      doc: >-
-        Verbatim code that will be put into the declaration section of the test.
-      value: |-
-        extern void tohost_exit(int status);
-
-        #undef trek_exit
-        #define trek_exit(status) tohost_exit(status);
-
-        int main(void)
-        {
-          return trek_main();
-        }
-
-  mmu:  # Trek can generate code to program page/translation tables
-        # that you MAY want to use with your SDV generated C files.
-        # Here, you have some control over that process.
-
-    va_bits: 39  # How many bits are used for virtual addresses
-                 #
-                 # For aarch64, the value here is used to determine the
-                 # "initial lookup level" (as detailed in Table D5-13).
-                 # This must correlate to TCR_EL3.T0SZ!
-                 #
-                 # For riscv64, only 39, 48, and 57 are supported
-                 # corresponding to "Sv39", "Sv48", and "Sv57".
-                 #
-                 # default: 39  [from T0SZ=64-39=25(0x19)]
-
-    memory_map:  # A *MAP* of all memory regions, excluding the
-                 # memory_resources in your platformConfig.h file.
-                 #
-                 # Each map entry should be a unique name.
-                 #
-                 # Mandatory submap pairs:
-                 #     normal: *true*/false  (false = "device"/"io" memory)
-                 #      begin: starting address
-                 #        end: ending address
-                 #
-                 # Optional submap pairs:
-                 #   readable: *true*/false
-                 #  writeable: *true*/false
-                 # executable: true/*false*
-                 #  cacheable: *true*/false  (*false* for device)
-                 #  share_type (aarch64 only): *inner-shareable*,
-                 #                  outer-shareable, non-shareable
-                 #
-                 # Note that memory_resources will use all defaults.
-                 #
-                 # Note that "normal: false" (device-memory) change defaults
-                 #   to "cacheable = false", and on arch64 it implies
-                 #   share_type = non-shareable, and alloc_type = no-allocate
-
-      UART0:
-        type:       device
-        begin:      0x10000000
-        end:        0x10000fff
-
-      code:
-        type:       normal
-        begin:      0x80000000
-        end:        0x807fffff
-        executable: true
-
-      stack:
-        type:       normal
-        begin:      0x87000000
-        end:        0x87ffffff
-
-
-    aarch64:  # Customizations that are only valid for aarch64.
-
-        TCR_EL3: 0x80923519  # Should Trek to program the TCR_TL3 register? If
-                             # so, put the value here. If not, comment out
-                             # this option.
-                             # NOTE: T0SZ should correlate to va_bits above!
-                             # default: -no default-
-
-        allocate_type: read-write-allocate  # Default allocate_type.
-                                            # read-allocate, write-allocate,
-                                            # *read-write-allocate*, no-allocate
-
-        cache_type: write-back-nontransient  # non-cacheable,
-                                             # write-through-transient,
-                                             # write-back-transient,
-                                             # write-through-non-transient,
-                                             # *write-back-non-transient*
-
-        device_type: nGnRnE # *nGnRnE*, nGnRE, nGRE, GRE
-
-        share_type: inner-shareable # non-shareable
-                                    # inner-shareable
-                                    # outer-shareable
-
-    riscv64:  # Customizations that are only valid for riscv64.
-
-        Svnapot: false  # If standard extension "Svnapot" is implemented, and
-                        # when you are using Sv39, you might set this to "true"
-                        # to allow PTE bit[63] "N" to be set when appropriate.
-                        # default: false
-
-        Svpbmt: true   # If standard extension "Svpbmt" is implemented, and
-                       # when you are using Sv39, you might set this to "true"
-                       # to allow cacheable/device information to flow into
-                       # bits[62:61] "PBMT" as appropriate.
-                       # default: false
diff --git a/testbench/trek_files/trek_user_backdoor.sv b/testbench/trek_files/trek_user_backdoor.sv
deleted file mode 100644
index 342ade7b9..000000000
--- a/testbench/trek_files/trek_user_backdoor.sv
+++ /dev/null
@@ -1,91 +0,0 @@
-/// custom routines defined for the platform
-
-// Design parameters, used in the code below and custom to this design!
-//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram
-//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM 
-//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM
-//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory
-`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram
-//`define RAM_BASE_ADDR 32'h80000000
-`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE
-
-// These two routines are specific to a particular design. They are used
-// to read and write to the "mailbox" locations, to synchronize behaviors
-// between C code on the processors with activity performed in UVM (and
-// among activities in UVM).
-//
-// Every design will be different. Here we just have a simple Verilog
-// array that we can read and write.
-//
-function automatic void trek_backdoor_read64(
-    input longint unsigned address,
-   output longint unsigned data,
-    input     int unsigned debug = 1);
-
-  //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
-  bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
-  if (address[1:0] != 2'b00) begin: misaligned
-    $display("%t trek_backdoor_read64: Misaligned address", $time);
-    $finish();
-  end
-  
-  //data[63:32] = `RAM_PATH[offset + 0];
-  //data[31: 0] = `RAM_PATH[offset + 1];
-  data[63:0] = `RAM_PATH.RAM[offset + 0];
-if (data != 0)
-  $display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h",
-           $time, data, address);
-endfunction: trek_backdoor_read64
-
-
-function automatic void trek_backdoor_write64(
-    input longint unsigned address,
-    input longint unsigned data,
-    input     int unsigned debug = 1);
-
-  //bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
-  bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
-
-  if (address[1:0] != 2'b00) begin: misaligned
-    $display("%t trek_backdoor_write64: Misaligned address", $time);
-    $finish();
-  end
-  //`RAM_PATH[offset + 0] = data[63:32];
-  //`RAM_PATH[offset + 1] = data[31: 0];
-  `RAM_PATH.RAM[offset + 0] = data[63:0];
-  //$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h",
-           //$time, data, address);
-endfunction: trek_backdoor_write64
-
-
-// For performance, we want to read mailboxes ONLY when they're written to!
-// (This is very important on emulators!)
-//
-// Here we trigger a signal when a memory write happens to the range of
-// addresses where the mailboxes are.
-//
-// A clock later, we go poll all the mailboxes (using the "backdoor_read"
-// method above.
-//
-// Each design will be different, depending on where you are able to snoop
-// for writes and how long it takes a write to propagate from that point
-// to the place where the backdoor read will find it.
-
-bit  trek_c2t_mbox_event;
-bit  trek_is_event_addr;
-
-//assign trek_is_event_addr =
-//      ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) &&
-//       (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) <  `TREK_C2T_MBOX_LIMIT));
-//
-//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes
-//  trek_c2t_mbox_event <= (trek_is_event_addr &&
-//                          (`RAM_PATH.n_cs == 1'b0) &&
-//                          (`RAM_PATH.n_we == 1'b0));
-//end
-
-// Design specifc: one stage delayed so write has a time to settle
-//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes
-always @(posedge testbench.clk) begin: read_all_mailboxes
-  trek_poll_mbox();
-end
diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv
deleted file mode 100644
index 62c7b67e7..000000000
--- a/testbench/wallywrapper.sv
+++ /dev/null
@@ -1,85 +0,0 @@
-///////////////////////////////////////////
-// wallywrapper.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Wrapper module to define parameters for Wally Verilator linting
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "config.vh"
-
-
-
-module wallywrapper import cvw::*;(
-  input logic clk,
-  input logic reset_ext,
-  input logic SPIIn,
-  input logic SDCIn
-);
- 
-`include "parameter-defs.vh"
-
-  logic        reset;
-
-  logic [P.AHBW-1:0]    HRDATAEXT;
-  logic                HREADYEXT, HRESPEXT;
-  logic [P.PA_BITS-1:0] HADDR;
-  logic [P.AHBW-1:0]    HWDATA;
-  logic [P.XLEN/8-1:0]  HWSTRB;
-  logic                HWRITE;
-  logic [2:0]          HSIZE;
-  logic [2:0]          HBURST;
-  logic [3:0]          HPROT;
-  logic [1:0]          HTRANS;
-  logic                HMASTLOCK;
-  logic                HCLK, HRESETn;
-
-  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
-  logic        UARTSin, UARTSout;
-  logic        SPIOut;
-  logic [3:0]  SPICS;
-  logic        SPICLK;
-
-  logic        SDCCmd;
-  logic [3:0]  SDCCS;
-  logic        SDCCLK;
-
-  logic        HREADY;
-  logic        HSELEXT;
-
-  logic        ExternalStall;
-  
-  // instantiate device to be tested
-  assign GPIOIN = 0;
-  assign UARTSin = 1;
-
-    assign HREADYEXT = 1;
-    assign HRESPEXT = 0;
-    assign HRDATAEXT = 0;
-
-  assign ExternalStall = '0;
-
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .ExternalStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); 
-
-endmodule
diff --git a/tests/breker/Makefile b/tests/breker/Makefile
deleted file mode 100644
index 2df6a3521..000000000
--- a/tests/breker/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-NUM_TESTS ?= 1 # Number of tests to generate for each constraint file
-
-# General Makefile settings
-SHELL := /bin/bash
-
-# Breker/Trek paths and variables
-TESTDIR          := $(WALLY)/tests/breker/work
-TREKFILES        := $(WALLY)/testbench/trek_files
-CONSTRAINTS_DIR  := $(WALLY)/tests/breker/constraints
-PLATFORM_YAML    := $(TREKFILES)/platform.yaml
-CUSTOMER_YAML    := $(TREKFILES)/customer.yaml
-TREKSVIP_YAML    := $(BREKER_HOME)/examples/tutorials/svip/treksvip/yaml/treksvip.yaml
-CONSTRAINT_FILES := $(wildcard $(CONSTRAINTS_DIR)/*.yaml)
-TREKEXE_FLAGS    += --seed 0x # free (0x) or lock (0x1) the seed used for test generation
-TREKSVIP         := source $(TREKFILES)/breker-setup.sh && treksvip -p $(PLATFORM_YAML) -p $(TREKSVIP_YAML) $(TREKEXE_FLAGS)
-
-# Compilation paths and variables
-START_LIB_DIR := $(WALLY)/examples/C/common
-START_LIB     := $(START_LIB_DIR)/crt.S $(START_LIB_DIR)/syscalls.c
-MARCH         :=-march=rv64gc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zicond_zbkb_zbkx_zknd_zkne_zknh_svinval
-MABI          :=-mabi=lp64d
-LINKER        := $(START_LIB_DIR)/test.ld
-LINK_FLAGS    := -nostartfiles
-CFLAGS        := -Wa,-alhs -Wa,-L -mcmodel=medany -Og -DSINGLE_CPU
-WIDTH         := 64
-
-# Find all constraint files and generate NUM_TESTS tests for each one
-TESTS = $(foreach yaml,$(CONSTRAINT_FILES),$(foreach n,$(shell seq 1 $(NUM_TESTS)),$(patsubst $(CONSTRAINTS_DIR)/%.yaml,$(TESTDIR)/%_$(n),$(yaml))))
-
-.PHONY: all clean
-all: $(TESTS)
-
-# Generate c tests
-$(TESTDIR)/%: | $(TESTDIR)
-	$(eval CONSTRAINT_FILE := $(shell echo $* | sed 's/_[0-9]*$$//'))
-	$(TREKSVIP) -p $(CONSTRAINTS_DIR)/$(CONSTRAINT_FILE).yaml -p $(CUSTOMER_YAML) -o $@/$* -e pss_top.entry
-	$(MAKE) $@/$*.elf
-
-# Compile c code
-.PRECIOUS: $(TESTDIR)/%.elf
-$(TESTDIR)/%.elf: $(TESTDIR)/%.c 
-	riscv64-unknown-elf-gcc $(MARCH) $(MABI) $(CFLAGS) $(LINK_FLAGS) -T$(LINKER) -I$(START_LIB_DIR) $(START_LIB) -g -o $@ $< > /dev/null
-	$(MAKE) $@.objdump
-
-# Convert elf to hex
-$(TESTDIR)/%.elf.objdump: $(TESTDIR)/%.elf
-	riscv64-unknown-elf-objdump -D $< > $@
-# riscv64-unknown-elf-elf2hex --bit-width $(WIDTH) --input $< --output $@
-# extractFunctionRadix.sh $<.objdump
-
-# View the model graph TODO: What does this do? Move to another makefile?
-%.view_graph: $(CONSTRAINTS_DIR)/%.yaml
-	$(TREKSVIP) -p $(CONSTRAINTS_DIR)/$^.yaml -p $(CUSTOMER_YAML) -t pss_top.entry
-
-$(TESTDIR):
-	mkdir -p $(TESTDIR)
-
-clean:
-	rm -rf $(TESTDIR)/*
diff --git a/tests/breker/README.md b/tests/breker/README.md
deleted file mode 100644
index 300ebc16e..000000000
--- a/tests/breker/README.md
+++ /dev/null
@@ -1,18 +0,0 @@
-Jordan Carlin, jcarlin@hmc.edu, December 2024
-
-# Breker Tests for CVW
-
-[Breker's Trek Test Suite](https://brekersystems.com/products/trek-suite/) is a proprietary set of tests that require a license to use (this license is not generally available to noncommercial users).
-
-To generate the Breker tests (with a license), run `make` in both the `tests/breker` and `testbench/trek_files` directories. Alternatively, running `make breker` from the top-level `$WALLY` directory will run both of these. Before running, make sure to set `$BREKER_HOME` in your system's `site-setup.sh` file. The `testbench/trek_files` Makefile only needs to be run once, but the tests that are generated can be different each time so rerunning the `tests/breker` Makefile is worthwhile.
-
-This will generate a testsuite for each of the constraint yaml files in the `constraints` directory. These generated tests are produced in the `tests/breker/work` directory. To run a single test use `wsim` to run the elf. The `breker` configuration must be used. For example,
-
-```bash
-$ wsim breker $WALLY/tests/breker/riscv/riscv.elf
-```
-
-To run all of the generated Breker tests use 
-```bash
-$ regression-wally --breker
-```
diff --git a/tests/breker/constraints/archive/hello.yaml b/tests/breker/constraints/archive/hello.yaml
deleted file mode 100644
index e95b17393..000000000
--- a/tests/breker/constraints/archive/hello.yaml
+++ /dev/null
@@ -1,52 +0,0 @@
-# Constraint file to generate simple hello world test that checks the
-# initialized values for a few memory locations.
-
-# This constraint file disable all features other than the
-trek:
-  svip:
-    global:
-      scenarios:
-        scenario_count:
-          # reduce number of scenarios
-          value: 2
-      memory_allocation:
-        memory_sets:
-          block_size:
-            # force 4 byte operation
-            min: 4
-            max: 4
-          block_count:
-            # force a single memory block
-            min: 1
-            max: 1
-    coherency:
-      cacheline_states:
-        scenario_length:
-          # minimize scenario length
-          min: 1
-          max: 1
-  weights:
-
-    # turn of SoC level Dekker and Atomics tests
-    pss_top.soc: 0
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various cache state tests
-    pss_top.readOnly.entry: 0
-    pss_top.writeOnly.entry: 0
-    pss_top.writeRead.entry: 0
-    pss_top.readWrite.entry: 0
-    pss_top.moesiStates.entry: 0
-    pss_top.tilelinkStates.entry: 0
-
-    # turn of micro loop feature
-    pss_top.microLoops.microLoopScn: 0
-
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
diff --git a/tests/breker/constraints/archive/microloops.yaml b/tests/breker/constraints/archive/microloops.yaml
deleted file mode 100644
index 00582ff60..000000000
--- a/tests/breker/constraints/archive/microloops.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    # pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    pss_top.readOnly.entry: 0
-    pss_top.writeOnly.entry: 0
-    pss_top.writeRead.entry: 0
-    pss_top.readWrite.entry: 0
-    pss_top.moesiStates.entry: 0
-    pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/atomics.yaml b/tests/breker/constraints/atomics.yaml
deleted file mode 100644
index 443cff12c..000000000
--- a/tests/breker/constraints/atomics.yaml
+++ /dev/null
@@ -1,51 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    # pss_top.soc: 0
-    pss_top.dekker.dekkerTest: 0
-    # pss_top.atomics.atomicsTest: 0
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/coherency.yaml b/tests/breker/constraints/coherency.yaml
deleted file mode 100644
index 258147abc..000000000
--- a/tests/breker/constraints/coherency.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    # pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    # pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/dekker.yaml b/tests/breker/constraints/dekker.yaml
deleted file mode 100644
index 7b57f0564..000000000
--- a/tests/breker/constraints/dekker.yaml
+++ /dev/null
@@ -1,51 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    # pss_top.soc: 0
-    # pss_top.dekker.dekkerTest: 0
-    pss_top.atomics.atomicsTest: 0
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/mmu.yaml b/tests/breker/constraints/mmu.yaml
deleted file mode 100644
index 8d4878a32..000000000
--- a/tests/breker/constraints/mmu.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    # pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/riscv.yaml b/tests/breker/constraints/riscv.yaml
deleted file mode 100644
index 5d05f1742..000000000
--- a/tests/breker/constraints/riscv.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    # pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    # pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/test.yaml b/tests/breker/constraints/test.yaml
deleted file mode 100644
index 9e2238f92..000000000
--- a/tests/breker/constraints/test.yaml
+++ /dev/null
@@ -1,63 +0,0 @@
-trek:
-  # svip:
-  #   global:
-  #     scenarios:
-  #       scenario_count:
-  #         # primary control for length of test
-  #         value: 10
-  #   riscv:
-  #     extensions:
-  #       # disable hypervisor extension by setting value to 0
-  #       # if your system does not support this feature
-  #       h_hypervisor:
-  #         value: 0
-
-  # weights:
-    # turn off MMU Tests
-    # pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    # pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    # pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    # pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    # pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    # pss_top.readOnly.entry: 0
-    # pss_top.writeOnly.entry: 0
-    # pss_top.writeRead.entry: 0
-    # pss_top.readWrite.entry: 0
-    # pss_top.moesiStates.entry: 0
-    # pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    # pss_top.microLoops.microLoopScn: 0
diff --git a/tests/breker/constraints/workload.yaml b/tests/breker/constraints/workload.yaml
deleted file mode 100644
index 565a71e5b..000000000
--- a/tests/breker/constraints/workload.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-trek:
-  weights:
-    # turn off MMU Tests
-    pss_top.rvMmu.rvMmuOp: 0
-
-    # turn off rvMmu Self-modifying-code (SMC) scenarios
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::doExec: 0
-
-    # turn off rvMmuOp page fault cases
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteAClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteD1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteR1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU0SetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteU1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteVClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteW1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::leafPteX1ClrErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteASetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteDSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteUSetErr: 0
-    # pss_top.rvMmu.rvMmuOp.RvMmuOp::nonLeafPteVClrErr: 0
-
-    # turn of SoC level Dekker and Atomics tests
-    pss_top.soc: 0
-
-
-    # turn off RV64 opcode tests
-    pss_top.rv64.rv64Ops: 0
-
-    # turn off software interrupts
-    pss_top.rvMswi.rvMswiOp: 0
-
-
-    # turn off all coherency tests
-    # pss_top.coherency: 0
-
-    # turn off coherency memory workload tests
-    # pss_top.workload.entry: 0
-
-    # turn of various coherency cache state tests
-    pss_top.readOnly.entry: 0
-    pss_top.writeOnly.entry: 0
-    pss_top.writeRead.entry: 0
-    pss_top.readWrite.entry: 0
-    pss_top.moesiStates.entry: 0
-    pss_top.tilelinkStates.entry: 0
-
-    # turn of coherency micro loop feature
-    # these scenarios take a while to run
-    pss_top.microLoops.microLoopScn: 0
diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile
deleted file mode 100644
index 7e68c28c0..000000000
--- a/tests/coverage/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-# Disable builtin rules because they are a shorter (but incorrect) path that Make will use by default
-MAKEFLAGS += --no-builtin-rules
-SRCDIR    := .
-SRCEXT    := S
-AEXT      := s
-OBJEXT    := o
-EXEEXT    := elf
-SOURCES		?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
-ELFS   		:= $(SOURCES:.$(SRCEXT)=.$(EXEEXT))
-OBJDUMPS  := $(addsuffix .objdump, $(ELFS))
-MEMFILES  := $(addsuffix .memfile, $(ELFS))
-
-all: $(OBJDUMPS) $(MEMFILES)
-
-# Create dissassembly
-%.elf.objdump: %.elf
-	riscv64-unknown-elf-objdump -S -D $< > $@
-	extractFunctionRadix.sh $@
-
-# Create memfile
-%.elf.memfile: %.elf
-	riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
-
-# Link object file to create executable
-.PRECIOUS: %.$(EXEEXT)
-%.$(EXEEXT): %.$(OBJEXT)
-	riscv64-unknown-elf-gcc -g -o $@ -mcmodel=medany -nostartfiles -T../../examples/link/link.ld $*.o
-
-# Assemble into object files
-%.$(OBJEXT): %.$(AEXT)
-	riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -mabi=lp64 $<
-
-# Preprocess assembly files
-%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h
-	riscv64-unknown-elf-gcc -E -g -o $@ $<
-
-sim: %.$(EXEEXT)
-	spike +signature=%.signature.output +signature-granularity=8 %.elf
-	diff --ignore-case %.signature.output %.reference_output || exit
-	echo "Signature matches! Success!"
-
-clean:
-	rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile *.o *.s
diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h
deleted file mode 100644
index 59245bb2c..000000000
--- a/tests/coverage/WALLY-init-lib.h
+++ /dev/null
@@ -1,152 +0,0 @@
-///////////////////////////////////////////
-// WALLY-init-lib.h
-//
-// Written: David_Harris@hmc.edu 21 March 2023
-//
-// Purpose: Initialize stack, handle interrupts, terminate test case
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-// The PMP tests are sensitive to the exact addresses in this code, so unfortunately
-// modifying anything breaks those tests.
-
-.section .text.init
-.global rvtest_entry_point
-
-rvtest_entry_point:
-    la sp, topofstack       # Initialize stack pointer (not used)
-
-    # Set up interrupts
-    la t0, trap_handler
-    csrw mtvec, t0      # Initialize MTVEC to trap_handler
-    csrw mideleg, zero  # Don't delegate interrupts
-    csrw medeleg, zero  # Don't delegate exceptions
-#    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
-#    li t1, 0x02004000   # MTIMECMP in CLINT
-#    sd t0, 0(t1)      
-    li t0, 0x80         
-#    li t0, 0x00         
-    csrw mie, t0        # Enable machine timer interrupt
-    la t0, topoftrapstack 
-    csrw mscratch, t0   # MSCRATCH holds trap stack pointer
-    csrsi mstatus, 0x8  # Turn on mstatus.MIE global interrupt enable
-    # set up PMP so user and supervisor mode can access full address space
-    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
-    li t0, 0xFFFFFFFF   
-    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
-    j main              # Call main function in user test program
-
-done:
-    li a0, 4            # argument to finish program    
-    ecall               # system call to finish program
-    j self_loop         # wait forever (not taken)
-
-.align 4                # trap handlers must be aligned to multiple of 4
-trap_handler:
-    # Load trap handler stack pointer tp
-    csrrw tp, mscratch, tp  # swap MSCRATCH and tp
-    sd t0, 0(tp)        # Save t0 and t1 on the stack
-    sd t1, -8(tp)
-    csrr t0, mcause     # Check the cause
-    csrr t1, mtval      # And the trap value
-    bgez t0, exception  # if msb is clear, it is an exception
-
-interrupt:              # must be a timer interrupt 
-    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
-    li t1, 0x02004000   # MTIMECMP in CLIN
-    sd t0, 0(t1)      
-    csrw stimecmp, t0   # sets stimecmp to big number so it doesnt interrupt 
-    li t0, 32
-    csrc sip, t0        # clears stimer interrupt
-    j trap_return       # clean up and return
-
-exception:
-    csrr t0, mcause
-    li t1, 8            # is it an ecall trap?
-    andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
-    bne t0, t1, trap_return # ignore other exceptions
-
-ecall:
-    li t0, 4
-    beq a0, t0, write_tohost    # call 4: terminate program
-    bltu a0, t0, changeprivilege    # calls 0-3: change privilege level
-    j trap_return       # ignore other ecalls
-
-changeprivilege:
-    li t0, 0x00001800   # mask off mstatus.MPP in bits 11-12
-    csrc mstatus, t0
-    andi a0, a0, 0x003  # only keep bottom two bits of argument
-    slli a0, a0, 11     # move into mstatus.MPP position
-    csrs mstatus, a0    # set mstatus.MPP with desired privilege
-
-trap_return:            # return from trap handler
-    csrr t0, mepc  # get address of instruction that caused exception
-    li t1, 0x20000  
-    csrs mstatus, t1    # set mprv bit to fetch instruction with permission of code that trapped
-    lh t0, 0(t0)   # get instruction that caused exception
-    csrc mstatus, t1    # clear mprv bit to restore normal operation
-    li t1, 3
-    and t0, t0, t1  # mask off upper bits
-    beq t0, t1, instr32  # if lower 2 bits are 11, instruction is uncompresssed
-    li t0, 2        # increment PC by 2 for compressed instruction
-    j updateepc
-instr32:
-    li t0, 4
-updateepc:
-    csrr t1, mepc   # add 2 or 4 (from t0) to MEPC to determine return Address
-    add t1, t1, t0
-    csrw mepc, t1
-
-    ld t1, -8(tp)       # restore t1 and t0
-    ld t0, 0(tp)
-    csrrw tp, mscratch, tp  # restore tp
-    mret                # return from trap
-
-write_tohost:
-    la t1, tohost
-    li t0, 1            # 1 for success, 3 for failure
-    sd t0, 0(t1)        # send success code
-
-self_loop:
-    j self_loop         # wait
-    
-.section .tohost 
-tohost:                 # write to HTIF
-    .dword 0
-fromhost:
-    .dword 0
-
-.EQU XLEN,64
-begin_signature:
-    .fill 6*(XLEN/32),4,0xdeadbeef    # 
-end_signature:
-
-# Initialize stack with room for 512 bytes
-.bss
-    .space 512
-topofstack:
-# And another stack for the trap handler
-.bss   
-    .space 512
-topoftrapstack:
-
-.align 4
-.section .text.main
\ No newline at end of file
diff --git a/tests/coverage/amoAccessFault.S b/tests/coverage/amoAccessFault.S
deleted file mode 100644
index b69c545a4..000000000
--- a/tests/coverage/amoAccessFault.S
+++ /dev/null
@@ -1,53 +0,0 @@
-///////////////////////////////////////////
-// hptwAccessFault.S
-//
-// Written: Rose Thompson rose@rosethompson.net
-//
-// Purpose: Checks that only Store/AMO access faults are generated on AMO operations
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-
-    la t1, data # first a valid AMO
-    li t2, 2
-    li t3, 3
-    amoadd.d t3, t2, (t1)
-
-    li t1, 0x90000000 # invalid AMO address
-    li t2, 2
-    li t3, 3
-    amoadd.d t3, t2, (t1)
-
-    fence.I
-
-finished:
-    j done
-
-        .data
-
-.align 8
-data:
-        .8byte 0x1
diff --git a/tests/coverage/btbthrash.S b/tests/coverage/btbthrash.S
deleted file mode 100644
index 8fedf372a..000000000
--- a/tests/coverage/btbthrash.S
+++ /dev/null
@@ -1,145 +0,0 @@
-///////////////////////////////////////////
-// btbtrash.S
-//
-// Written: Rose Thompson rose@rosethompson.net 23 October 2024
-//
-// Purpose: Test the branch target buffer alias with divide and cache pipeline stalls
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-
-    # Division test (having trouble with buildroot)
-        li x1, 1938759018
-        li x2, 3745029
-        li x3, 458
-        li x4, 29587209347
-        li x5, 28957
-        li x6, 298
-        li x7, 238562
-        li x8, 198674
-        li x9, 134
-        li x10, 906732
-        li x11, 29
-        li x12, 50912
-        li x13, 59
-        li x14, 6902385
-        li x15, 1923857
-        li x16, 3985
-        li x17, 3947
-        li x18, 15984
-        li x19, 5
-        li x20, 9684658489
-        li x21, 6548
-        li x22, 3564
-        li x23, 94
-        li x24, 689464
-        li x25, 42567
-        li x26, 98453
-        li x27, 648
-        li x28, 984
-        li x29, 6984
-        li x30, 864
-
-        # x31 will be our loop counter
-        li x31, 4
-
-.align 12
-jump1:  
-        divuw x0, x1, x2
-        j jump3
-jump4:
-        divuw x0, x5, x6
-        j jump5
-jump6:
-        divuw x0, x10, x9
-        j jump7
-jump8:
-        divuw x0, x14, x3
-        j jump9
-jump10:
-        divuw x0, x18, x17
-        j jump11
-jump12:
-        divuw x0, x21, x22
-        j jump13
-jump14:
-        divuw x0, x24, x25
-        j jump15
-jump16:
-        divuw x0, x29, x28
-        j jump17
-jump18:
-        divuw x0, x1, x30
-        j jump19
-jump20:
-        divuw x0, x3, x19
-        j jump21
-jump22:
-        divuw x0, x12, x13
-        j jump23
-
-.align 12 # size of the 1024 btb apart
-jump2:
-        j jump1
-jump3:  
-        divuw x0, x4, x3
-        j jump4
-jump5:  
-        divuw x0, x7, x8
-        j jump6
-jump7:  
-        divuw x0, x12, x11
-        j jump8
-jump9:  
-        divuw x0, x15, x16
-        j jump10
-jump11:  
-        divuw x0, x20, x19
-        j jump12
-jump13:  
-        divuw x0, x24, x23
-        j jump14
-jump15:  
-        divuw x0, x26, x27
-        j jump16
-jump17:  
-        divuw x0, x29, x30
-        j jump18
-jump19:  
-        divuw x0, x2, x3
-        j jump20
-jump21:  
-        divuw x0, x4, x5
-        j jump22
-jump23:  
-        divuw x0, x20, x21
-        #j jump22
-
-        fence.i
-
-        addi x31, x31, -1
-        bne x31, x0, jump1
-finsihed:       
-    j done
-
diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S
deleted file mode 100644
index ef0c283ec..000000000
--- a/tests/coverage/csrwrites.S
+++ /dev/null
@@ -1,71 +0,0 @@
-///////////////////////////////////////////
-// csrwrites.S
-//
-// Written: David_Harris@hmc.edu 21 March 2023
-//
-// Purpose: Test writes to CSRs
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-    li t0, -5
-    csrw stimecmp, t0   # initialize so ImperasDV agrees
-    csrrw t0, stimecmp, t0
-    csrrw t0, satp, zero
-    csrrw t0, stvec, zero
-    csrrw t0, sscratch, zero
-    li t0, -2
-    csrrw t1, menvcfg, t0
-    csrrw t2, senvcfg, t0
-
-    # Test writing to TIME CSR
-    csrw time, zero
-
-    # testing FIOM with different privilege modes
-    # setting environment config (to both 1 and 0) in each privilege mode
-    csrsi menvcfg, 1
-    li a0, 1
-    ecall               # enter supervisor mode
-
-    li a0, 0
-    ecall               # enter user mode
-
-    li a0, 1
-    ecall               # enter supervisor mode
-
-    csrsi senvcfg, 1
-    li a0, 0
-    ecall               # enter user mode
-
-    li a0, 3
-    ecall               # enter machine mode
-    csrci menvcfg, 1
-
-    li a0, 1
-    ecall               # enter supervisor mode
-
-    li a0, 0
-    ecall               # enter user mode
-
-
-    j done
diff --git a/tests/coverage/dcache1.S b/tests/coverage/dcache1.S
deleted file mode 100644
index d54326d0d..000000000
--- a/tests/coverage/dcache1.S
+++ /dev/null
@@ -1,94 +0,0 @@
-      #include "WALLY-init-lib.h"
-main:
-      // start way test #1
-      li t0, 0x80100000
-.align 6
-      // i$ boundary, way test #1
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      sd zero, 0(t0)
-      sd zero, 0(t0)
-      .word 0x00000013
-      .word 0x00000013
-      // start way test #2
-      li t0, 0x80101000
-.align 6
-      // i$ boundary, way test #2
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      sd zero, 0(t0)
-      sd zero, 0(t0)
-      .word 0x00000013
-      .word 0x00000013
-      // start way test #3
-      li t0, 0x80102000
-.align 6
-      // i$ boundary, way test #3
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      sd zero, 0(t0)
-      sd zero, 0(t0)
-      .word 0x00000013
-      .word 0x00000013
-      // start way test #4
-      li t0, 0x80103000
-.align 6
-      // i$ boundary, way test #4
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      .word 0x00000013
-      sd zero, 0(t0)
-      sd zero, 0(t0)
-      .word 0x00000013
-      .word 0x00000013
-
-# test flushing
-      li t0, 0x80100000
-      cbo.flush (t0)
-      li t0, 0x80101000
-      cbo.flush (t0)
-      li t0, 0x80102000
-      cbo.flush (t0)
-      li t0, 0x80103000
-      cbo.flush (t0)
-
-      j done
diff --git a/tests/coverage/dcache1.py b/tests/coverage/dcache1.py
deleted file mode 100644
index 728d58ae9..000000000
--- a/tests/coverage/dcache1.py
+++ /dev/null
@@ -1,86 +0,0 @@
-####################
-# dcache1.py
-#
-# Written: avercruysse@hmc.edu 18 April 2023
-#
-# Purpose: Test Coverage for D$
-#          (For each way, trigger a CacheDataMem write enable while chip enable is low)
-#
-# A component of the CORE-V-WALLY configurable RISC-V project.
-#
-# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-#
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-# except in compliance with the License, or, at your option, the Apache License version 2.0. You
-# may obtain a copy of the License at
-#
-# https://solderpad.org/licenses/SHL-2.1/
-#
-# Unless required by applicable law or agreed to in writing, any work distributed under the
-# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-# either express or implied. See the License for the specific language governing permissions
-# and limitations under the License.
-################################################
-
-import os
-
-test_name = "dcache1.S"
-dcache_num_ways = 4
-dcache_way_size_in_bytes = 4096
-# warning i$ line size is not currently parameterized.
-
-# arbitrary start location of where I send stores to.
-mem_start_addr = 0x80100000
-
-# pointer to the start of unused memory (strictly increasing)
-mem_addr = mem_start_addr
-
-
-def wl(line="", comment=None, fname=test_name):
-    with open(fname, "a") as f:
-        instr = not (":" in line or 
-                     ".align" in line or 
-                     "# include" in line)
-        indent = 6 if instr else 0
-        comment = "// " + comment if comment is not None else ""
-        to_write = " " * indent + line + comment + "\n"
-        f.write(to_write)
-
-
-def write_repro_instrs():
-    """
-    Assumes that the store location has been fetched to d$, and is in t0.
-    """
-    for i in range(16): # write a whole cache set.
-        if i == 12:
-            wl('sd zero, 0(t0)') # D$ write to set PCM = PCF + 8 for proper alignment (stallD will happen).
-        elif i == 13:
-            # the store in question happens here, at adresses 0x34, 0x74
-            wl('sd zero, 0(t0)') # it should hit this time
-        else:
-            # can't be a NOP or anything else that is encoded as compressed.
-            # this is because the branch predictor will use the wrong address
-            # so the IFU cache miss will come late.
-            wl('.word 0x00000013') # addi x0, x0, 0 (canonical NOP, uncompressed).
-
-if __name__ == "__main__":
-    if os.path.exists(test_name):
-        os.remove(test_name)
-        # os.rename(test_name, test_name + ".old")
-    wl(comment="This file is generated by dcache1.py (run that script manually)")
-    wl('#include "WALLY-init-lib.h"')
-    wl('main:')
-
-    # excercise all 4 D$ ways. If they're not all full, it uses the first empty.
-    # So we are sure all 4 ways are exercised.
-    for i in range(dcache_num_ways):
-        wl(comment=f"start way test #{i+1}")
-        wl(f'li t0, {hex(mem_addr)}')
-        wl('.align 6')                # start at i$ set boundary. 6 lsb bits are zero.
-        wl(comment=f"i$ boundary, way test #{i+1}")
-        write_repro_instrs()
-        mem_addr += dcache_way_size_in_bytes  # so that we excercise a new D$ way.
-
-    wl("j done")
diff --git a/tests/coverage/dcache2.S b/tests/coverage/dcache2.S
deleted file mode 100644
index d5ba57022..000000000
--- a/tests/coverage/dcache2.S
+++ /dev/null
@@ -1,62 +0,0 @@
-///////////////////////////////////////////
-// dcache2.S
-//
-// Written: avercruysse@hmc.edu 18 April 2023
-//
-// Purpose: Test Coverage for D$
-//          (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-#include "WALLY-init-lib.h"
-main:
-        // way 0
-        li t0, 0x80100770
-        sd zero, 0(t0)
-        sd zero, 1(t0)
-        lr.d t1, (t0)
-        addi t0, t0, 1
-        sc.d t2, t1, (t0)
-
-        // way 1
-        li t0, 0x80101770
-        sd zero, 0(t0)
-        sd zero, 1(t0)
-        lr.d t1, (t0)
-        addi t0, t0, 1
-        sc.d t2, t1, (t0)
-
-        // way 2
-        li t0, 0x80102770
-        sd zero, 0(t0)
-        sd zero, 1(t0)
-        lr.d t1, (t0)
-        addi t0, t0, 1
-        sc.d t2, t1, (t0)
-
-        // way 3
-        li t0, 0x80103770
-        sd zero, 0(t0)
-        sd zero, 1(t0)
-        lr.d t1, (t0)
-        addi t0, t0, 1
-        sc.d t2, t1, (t0)
-
-        j done
diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S
deleted file mode 100644
index 4537686a1..000000000
--- a/tests/coverage/ebu.S
+++ /dev/null
@@ -1,313 +0,0 @@
-///////////////////////////////////////////
-// ebu.S
-//
-// Written: David_Harris@hmc.edu 21 January 2024
-//
-// Purpose: Test coverage for EBU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    li t5, 0x1
-    slli t5, t5, 62
-    ori t5, t5, 0xF0
-    csrs menvcfg, t5  # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
-
-    # Page table root address at 0x80010000; SV48
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    #
-
-#   Tricky case to cover.  I$ miss concurrent with DTLB miss.  HPTW has to hit the first
-#   access in the cache and miss a later one.  Trigger this by doing a load that touches
-#   a page not in the DTLB but where the top-level PTE is already there.  Has to happen
-#   near the end of the 16-instruction I$ line.
-#
-#    Condition Coverage for instance /core/ebu/ebu/ebufsmarb --
-#
-#  File ../src/ebu/ebufsmarb.sv
-#----------------Focused Condition View-------------------
-#Line       72 Item    1  ((HREADY & FinalBeatD) & (LSUReq ~& IFUReq))
-#Condition totals: 2 of 4 input terms covered = 50.00%
-#
-#  Input Term   Covered  Reason for no coverage   Hint
-# -----------  --------  -----------------------  --------------
-#      HREADY         Y
-#  FinalBeatD         Y
-#      LSUReq         N  '_1' not hit             Hit '_1'
-#      IFUReq         N  No hits                  Hit '_0' and '_1'
-#
-#     Rows:       Hits  FEC Target            Non-masking condition(s)
-# ---------  ---------  --------------------  -------------------------
-#  Row   1:          2  HREADY_0              ((LSUReq ~& IFUReq) && FinalBeatD)
-#  Row   2:         14  HREADY_1              ((LSUReq ~& IFUReq) && FinalBeatD)
-#  Row   3:          1  FinalBeatD_0          ((LSUReq ~& IFUReq) && HREADY)
-#  Row   4:         14  FinalBeatD_1          ((LSUReq ~& IFUReq) && HREADY)
-#  Row   5:         14  LSUReq_0              ((HREADY & FinalBeatD) && IFUReq)
-#  Row   6:    ***0***  LSUReq_1              ((HREADY & FinalBeatD) && IFUReq)
-#  Row   7:    ***0***  IFUReq_0              ((HREADY & FinalBeatD) && LSUReq)
-# Row   8:    ***0***  IFUReq_1              ((HREADY & FinalBeatD) && LSUReq)
-
-
-    li a0, 0x80000000
-    li a1, 0x80A00000
-    j label1
-
-.align  6   # start on multiple of 64 bytes / 16 instruction cache line
-label1:
-    addi t2, t3, 0x100  # occupy part of cache line
-    sfence.vma          # flush tlb
-    lw t0, 0x234(a0)        # load to get an entry in the DTLB accessing top-level PTE
-    addi t2, t3, 0x103  # occupy part of cache line
-    addi t2, t3, 0x104  # occupy part of cache line
-    addi t2, t3, 0x105  # occupy part of cache line
-    addi t2, t3, 0x106  # occupy part of cache line
-    addi t2, t3, 0x107  # occupy part of cache line
-    addi t2, t3, 0x108  # occupy part of cache line
-    addi t2, t3, 0x109  # occupy part of cache line
-    addi t2, t3, 0x10A  # occupy part of cache line
-    lw t0, 0x234(a1)        # trigger DTLB miss
-    addi t2, t3, 0x10C  # occupy part of cache line
-    addi t2, t3, 0x10D  # occupy part of cache line
-    addi t2, t3, 0x10E  # occupy part of cache line
-    addi t2, t3, 0x10F  # occupy part of cache line
-
-# next multiple of 16
-    addi t2, t3, 0x100  # occupy part of cache line
-    sfence.vma          # flush tlb
-    lw t0, 0x334(a0)        # load to get an entry in the DTLB accessing top-level PTE
-    addi t2, t3, 0x103  # occupy part of cache line
-    addi t2, t3, 0x104  # occupy part of cache line
-    addi t2, t3, 0x105  # occupy part of cache line
-    addi t2, t3, 0x106  # occupy part of cache line
-    addi t2, t3, 0x107  # occupy part of cache line
-    addi t2, t3, 0x108  # occupy part of cache line
-    addi t2, t3, 0x109  # occupy part of cache line
-    addi t2, t3, 0x10A  # occupy part of cache line
-    addi t2, t3, 0x10B  # occupy part of cache line
-    lw t0, 0x334(a1)        # trigger DTLB miss
-    addi t2, t3, 0x10D  # occupy part of cache line
-    addi t2, t3, 0x10E  # occupy part of cache line
-    addi t2, t3, 0x10F  # occupy part of cache line
-
-# next multiple of 16
-    addi t2, t3, 0x100  # occupy part of cache line
-    sfence.vma          # flush tlb
-    lw t0, 0x434(a0)        # load to get an entry in the DTLB accessing top-level PTE
-    addi t2, t3, 0x103  # occupy part of cache line
-    addi t2, t3, 0x104  # occupy part of cache line
-    addi t2, t3, 0x105  # occupy part of cache line
-    addi t2, t3, 0x106  # occupy part of cache line
-    addi t2, t3, 0x107  # occupy part of cache line
-    addi t2, t3, 0x108  # occupy part of cache line
-    addi t2, t3, 0x109  # occupy part of cache line
-    addi t2, t3, 0x10A  # occupy part of cache line
-    addi t2, t3, 0x10B  # occupy part of cache line
-    addi t2, t3, 0x10C  # occupy part of cache line
-    lw t0, 0x434(a1)        # trigger DTLB miss
-    addi t2, t3, 0x10E  # occupy part of cache line
-    addi t2, t3, 0x10F  # occupy part of cache line
-
-# next multiple of 16
-    addi t2, t3, 0x100  # occupy part of cache line
-    sfence.vma          # flush tlb
-    lw t0, 0x534(a0)        # load to get an entry in the DTLB accessing top-level PTE
-    addi t2, t3, 0x103  # occupy part of cache line
-    addi t2, t3, 0x104  # occupy part of cache line
-    addi t2, t3, 0x105  # occupy part of cache line
-    addi t2, t3, 0x106  # occupy part of cache line
-    addi t2, t3, 0x107  # occupy part of cache line
-    addi t2, t3, 0x108  # occupy part of cache line
-    addi t2, t3, 0x109  # occupy part of cache line
-    addi t2, t3, 0x10A  # occupy part of cache line
-    addi t2, t3, 0x10B  # occupy part of cache line
-    addi t2, t3, 0x10C  # occupy part of cache line
-    addi t2, t3, 0x10D  # occupy part of cache line
-    lw t0, 0x534(a1)        # trigger DTLB miss
-    addi t2, t3, 0x10F  # occupy part of cache line
-
-    # wrap up
-    li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
-    ecall
-    j done
-
-
-
-.data
-
-.align 16
-# root Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401  # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid
-    .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000
-
-# next page table at 0x80011000
-.align 12
-    .8byte 0x000000000000100F # misaligned gigapage at 0x00000000
-    .8byte 0x0000000020005801 # PTE for pages at 0x40000000
-    .8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000
-
-
-# Next page table at 0x80012000 for gigapage at 0x80000000
-.align 12
-    .8byte 0x0000000020004C01  # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
-    .8byte 0x0000000020014C0F  # for VA starting at 80200000 (misaligned megapage)
-    .8byte 0x0000000020005001  # for VA starting at 80400000 (bad PBMT pages)
-    .8byte 0x4000000020004C01  # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
-    .8byte 0x0000000020005401  # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
-    .8byte 0x0000000020005801  # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-
-# Leaf page table at 0x80013000 with NAPOT pages
-.align 12
-    #80000000
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-# Leaf page table at 0x80014000 with PBMT pages
-.align 12
-    #80400000
-    .8byte 0x60000000200020CF   # reserved entry
-
-# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
-.align 12
-    #80800000
-    .8byte 0x00000000200000CF   # valid rwx for VA 80800000
-    .8byte 0x00000000200000CB   # valid r x for VA 80801000
-    .8byte 0x00000000200000C3   # valid r   for VA 80802000
-    .8byte 0x00000000200000C9   # valid   x for VA 80803000
-    .8byte 0x00000000200000CD   # valid  wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
-    .8byte 0x000000002000000F   # valid rwx for VA 80805000  for covering ITLB translate and UpdateDA
-    .8byte 0x20000000200000CF   # PBMT=1    for VA 80806000  for covering ITLB BadPBMT
-
-# Leaf page table at 0x80016000 with NAPOT pages
-.align 12
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
diff --git a/tests/coverage/floatmisc.S b/tests/coverage/floatmisc.S
deleted file mode 100644
index 46bbc5418..000000000
--- a/tests/coverage/floatmisc.S
+++ /dev/null
@@ -1,84 +0,0 @@
-// debug.S
-// David_Harris@hmc.edu 4 February 2023
-// Small code snippets for the purpose of debugging issues
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-.global rvtest_entry_point
-rvtest_entry_point:
-    lui t0, 0x02            # turn on Floating point and XS
-    csrs mstatus, t0
-
-    la a6, begin_signature
-    la a7, rvtest_data
-
-    # openhwgroup/cvw Issue #55
-    fld f4, 0(a7)
-    fld f9, 8(a7)
-    fsgnjx.s f12,f9,f4  # expected f 0xffffffff7fc00000, hdl has been giving fff8000000000000
-    fsd f12, 0(a6)
-
-    # openhwgroup/cvw Issue #56
-    fld f4, 16(a7) # cfa695b1047553b1
-    fld f14, 24(a7)
-    fsgnjx.s f10,f4,f14  # expected f 0xffffffff7fc00000, hdl has been giving 0xcfa695b1047553b1
-    fsd f19, 16(a6)
-
-    # openhwgroup/cvw Issue #57
-    fld f0, 32(a7)
-    fld f15, 40(a7)
-    fsgnjx.s f30,f0,f15  # expected f 0xfffffffffb3754ef, hdl has been giving 0xffffffff7b3754ef
-    fsd f30, 24(a6)
-
-    # openhwgroup/cvw Issue #58
-    fld f14, 48(a7)
-    fclass.s x2, f14 # expected 0x0000000000000200, hdl had been giving 0x0000000000000220
-    sd x2, 32(a6)
-
-    # fsgnjx.s, fclass.s, fsgnjn.s, fsgnj.s, fneg.s, fabs.s, fmv.s all treat inputs as dp rather than sp
-
-    #openhwgroup/cvw Issue #65 #expected 0xffffffffffffffff, hdl had been giving 0x00000000ffffffff
-    fld f17, 56(a7)
-    fmv.x.s x30, f17
-    sd x30, 40(a6)
-
-
-#########################
-# HTIF and signature
-#########################
-
-write_tohost:
-    la t1, tohost
-    li t0, 1            # 1 for success, 3 for failure
-    sd t0, 0(t1)        # send success code
-
-self_loop:
-    j self_loop         # wait
-
-.align 6
-.section .tohost
-tohost:                 # write to HTIF
-    .dword 0
-fromhost:
-    .dword 0
-
-.align 6
-.data
-
-rvtest_data:
-.dword 0x7ff0000000000001
-.dword 0x7ff8000000000000
-.dword 0xcfa695b1047553b1
-.dword 0xffffffff7fc00000
-.dword 0xfffffffffb3754ef
-.dword 0x7fefffffffffffff
-.dword 0x00000000ffffffff
-
-.EQU XLEN,64
-begin_signature:
-    .fill 8*(XLEN/32),4,0xdeadbeef    #
-end_signature:
-
-# Initialize stack with room for 512 bytes
-.bss
-    .space 512
-topofstack:
diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S
deleted file mode 100644
index 760898306..000000000
--- a/tests/coverage/fpu.S
+++ /dev/null
@@ -1,219 +0,0 @@
-///////////////////////////////////////////
-// fpu.S
-//
-// Written: David_Harris@hmc.edu 28 March 2023
-//
-// Purpose: Test coverage for FPU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-
-    bseti t0, zero, 14  # turn on FPU
-    csrs mstatus, t0
-
-    #Pull denormalized FP number from memory and pass it to fclass.S for coverage
-    la t0, TestData1
-    flw ft0, 0(t0)
-    fclass.s t1, ft0
-
-    # zfa instructions (because Zfa tests aren't running yet)
-    fli.d fs0, 16
-    fcvtmod.w.d t0, fs0, rtz
-#    fminm.d fs1, fs0, fs0
-#    fmaxm.d fs1, fs0, fs0
-#    fltq.d t0, fs1, ft0
-#    fleq.d t0, fs1, ft0
-    fcvt.d.q fs1, fs0
-    fcvt.h.q fs1, fs0
-    fcvt.s.q fs1, fs0
-    # round for now because these tests are excluded from Zfa until rounding is implemented
-    fround.s fs1, fs0
-    froundnx.s fs1, fs0
-    fround.d fs1, fs0
-    froundnx.d fs1, fs0
-    fround.h fs1, fs0
-    froundnx.h fs1, fs0
-    fround.s fs1, fs0
-    froundnx.s fs1, fs0
-
-    #Result Sign Test Coverage
-    la t0, TestData2
-    flw ft0, 0(t0)
-    flw ft1, 4(t0)
-    fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD
-
-    flw ft2, 4(t0)
-    fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit
-
-    #Adds Coverage for Flag fmaAs, fmaPs, YSNaN, ZSNaN
-    fmadd.s ft3, ft0, ft1, ft2
-
-    flw ft0, 8(t0)
-    fmadd.s ft3, ft0, ft1, ft2
-
-    flw ft1, 12(t0)
-    fmadd.s ft3, ft0, ft1, ft2
-
-    flw ft2, 12(t0)
-    flw ft1, 4(t0)
-    fmadd.s ft3, ft0, ft1, ft2
-
-    #Add Coverage for round lsbRes
-    flw ft0, 16(t0)
-    flw ft1, 4(t0)
-    fmadd.s ft3, ft0, ft1, ft2
-
-    #Fix BadNaNBox test on unpackinput Z
-    la t0, TestData2
-    flw ft3, 0(t0)
-    flw ft4, 0(t0)
-    fadd.s ft5, ft3, ft4
-
-    # Test legal instructions not covered elsewhere
-    flq ft0, 0(a0)
-    flh ft0, 8(a0)
-    fsq ft0, 0(a0)
-    fsh ft0, 8(a0)
-
-    # Tests for fpu/fctrl.sv
-    fcvt.h.s ft1, ft0
-    fcvt.q.s ft2, ft0
-    fcvt.h.w ft3, a0
-    fcvt.h.wu ft3, a0
-    fcvt.h.l ft3, a0
-    fcvt.h.lu ft3, a0
-    fcvt.w.h a0, ft3
-    fcvt.wu.h a0, ft3
-    fcvt.l.h a0, ft3
-    fcvt.lu.h a0, ft3
-    fcvt.q.w ft3, a0
-    fcvt.q.wu ft3, a0
-    fcvt.q.l ft3, a0
-    fcvt.q.lu ft3, a0
-    fcvt.w.q a0, ft3
-    fcvt.wu.q a0, ft3
-    fcvt.l.q a0, ft3
-    fcvt.lu.q a0, ft3
-    fcvt.l.s a0, ft0
-    fcvt.lu.s a0, ft0
-    fcvt.s.l ft0, t0
-    fcvt.s.lu ft0, t0
-
-    // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
-    # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
-                      // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
-    # fcvt.h.w ft3, a0
-    # fcvt.w.h a0, ft0
-    # fcvt.q.w ft3, a0
-    # fcvt.w.q a0, ft0
-    # fcvt.q.d ft3, ft0
-
-    # half-precision NaN boxing
-    la t0, TestData3
-    fld ft2, 0(t0)          // bad NaN-boxed number
-    fmadd.h ft1, ft2, ft2, ft2 // Test NaN boxing
-    fmadd.s ft1, ft2, ft2, ft2 // Test NaN boxing
-
-    // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives)
-    // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes.
-    li t0, 0x3F812345 # random value slightly bigger than 1
-    li t1, 0x3F823456
-    fmv.w.x ft0, t0  # move int to fp register
-    fmv.w.x ft1, t1
-    li t0, -1           # set mtimecmp to biggest number so it doesnt interrupt again
-    li t1, 0x02004000   # MTIMECMP in CLINT
-    sd t0, 0(t1)
-    csrsi mstatus, 0b1000   # enable interrupts with mstatus.MIE
-    li t1, 0x0200bff8   # read MTIME in CLINT
-    ld t0, 0(t1)
-    addi t0, t0, 11
-    li t1, 0x02004000   # MTIMECMP in CLINT
-    sd t0, 0(t1)        # write mtime+10 to cause interrupt soon  This is very touchy timing and is sensitive to cache line fetch latency
-    nop
-    fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush
-    csrci mstatus, 0b1000   # disable interrupts with mstatus.MIE
-
-    # Completing branch coverage in fctrl.sv
-    .word 0x38007553    // Testing the all False case for 119 - funct7 under, op = 101 0011
-    .word 0x40000053    // Line 145 All False Test case - illegal instruction?
-    .word 0xd0400053    // Line 156 All False Test case - illegal instruction?
-    .word 0xc0400053    // Line 162 All False Test case - illegal instruction?
-    .word 0xd2400053    // Line 168 All False Test case - illegal instruction?
-    .word 0xc2400053    // Line 174 All False Test case - illegal instruction?
-
-    # Increasing conditional coverage in fctrl.sv
-    .word 0xc5000007    // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to
-    .word 0xe0101053    // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2)
-    .word 0xe0100053    // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2)
-    .word 0x40D00053    // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl.
-    .word 0x40300053    // toggling SupportFmt2 to 0 on line 145 in fctrl.
-    .word 0x42100053    // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr
-    .word 0xf0100053    // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr
-
-    # Test illegal instructions are detected
-    .word 0x00000007 // illegal floating-point load (bad Funct3)
-    .word 0x00000027 // illegal floating-point store (bad Funct3)
-    .word 0x58F00053 // illegal fsqrt (bad Rs2D)
-    .word 0x20007053 // illegal fsgnj (bad Funct3)
-    .word 0x28007053 // illegal fmin/max (bad Funct3)
-    .word 0xA0007053 // illegal fcmp (bad Funct3)
-    .word 0xE0007053 // illegal fclass/fmv (bad Funct3)
-    .word 0xF0007053 // illegal fmv (bad Funct3)
-    .word 0x43007053 // illegal fcvt.d.* (bad Rs2D)
-    .word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1])
-    .word 0xD5F00053 // illegal fcvt.h.* (bad Rs2D)
-    .word 0xC5F00053 // illegal fcvt.*.h (bad Rs2D)
-    .word 0x04000043 // illegal fmadd.h (h not supported)
-    .word 0xC2800053 // illegal fcvtmod.w.d with rm rne
-    .word 0xF0101053 // illegal fli with Funct3D not 0
-    .word 0xF0400053 // illegal fli with Rs2D not 1
-    .word 0x44200053 // illegal instruction for f.cvt.h.h
-
-    // Test divide by zero with rounding mode toward zero
-    li t0, 1
-    csrw frm, t0    // set rounding mode = 1
-    li t0, 0x3f800000
-    fcvt.s.w ft1, t0
-    fcvt.s.w ft2, zero
-    fdiv.s ft3, ft1, ft2
-
-    # Test floating point convert to integer and using result
-    fcvt.w.s t0, f0
-    add t1, t0, t0
-
-    j done
-
-.section .data
-.align 3
-TestData1:
-.int 0x00100000 #Denormalized FP number
-TestData2:
-.int 0x3f800000 #FP 1.0
-.word 0x7f800000 #INF
-.int 0xbf800000 #FP -1.0
-.int 0x7fa00000 #SNaN
-.int 0x3fffffff #OverFlow Test
-TestData3:
-.dword 0xABCD543212345678 # NaN box test
-DivTestData:
diff --git a/tests/coverage/hptwAccessFault.S b/tests/coverage/hptwAccessFault.S
deleted file mode 100644
index cb918a6e3..000000000
--- a/tests/coverage/hptwAccessFault.S
+++ /dev/null
@@ -1,168 +0,0 @@
-///////////////////////////////////////////
-// hptwAccessFault.S
-//
-// Written: Rose Thompson rose@rosethompson.net
-//
-// Purpose: Force the HPTW to walk a page table with invalid addresses so that the pma checker
-// generate access faults.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-    li t5, 0
-    li t2, 0x1000
-    li t0, 0x8000001000
-
-    lw t1, 0(t0)       # this load is a valid virtual address, but the page table will access an invalid address so it should cause a load access fault
-    li t1, 0x00008067  # this store is a valid virtual address, but the page table will access an invalid address so it should cause a store access fault
-    add t0, t0, t2
-        sw t1, 0(t0)
-
-        j jumppoint
-
-jumppoint:
-.align 6 # aligns to cache line size
-        sw t1, 0(t0)
-        sw t1, 4(t0)
-        sw t1, 8(t0)
-        sw t1, 12(t0)
-        sw t1, 16(t0)
-        sw t1, 20(t0)
-        sw t1, 24(t0)
-        sw t1, 28(t0)
-        sw t1, 32(t0)
-        sw t1, 36(t0)
-        sw t1, 40(t0)
-        sw t1, 44(t0)
-        sw t1, 48(t0)
-        sw t1, 52(t0) # this one causes a concurrent I$ miss with HPTW access exception (store access exception)
-        sw t1, 56(t0)
-        lw t3, 0(t0)
-        lw t3, 4(t0)
-        lw t3, 8(t0)
-        lw t3, 12(t0)
-        lw t3, 16(t0)
-
-    fence.I
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401
-    .8byte 0x30004401  # point to invalid region of physical memory
-
-.align 12
-    .8byte 0x0000004020004801
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-
-
-.align 12
-    .8byte 0x0000000020004C01
-
-.align 12
-    #80000000
-    .8byte 0x200000CF
-    .8byte 0x200004CF
-    .8byte 0x200008CF
-    .8byte 0x20000CCF
-
-    .8byte 0x200010CF
-    .8byte 0x200014CF
-    .8byte 0x200018CF
-    .8byte 0x20001CCF
-
-    .8byte 0x200020CF
-    .8byte 0x200024CF
-    .8byte 0x200028CF
-    .8byte 0x20002CCF
-
-    .8byte 0x200030CF
-    .8byte 0x200034CF
-    .8byte 0x200038CF
-    .8byte 0x20003CCF
-
-    .8byte 0x200040CF
-    .8byte 0x200044CF
-    .8byte 0x200048CF
-    .8byte 0x20004CCF
-
-    .8byte 0x200050CF
-    .8byte 0x200054CF
-    .8byte 0x200058CF
-    .8byte 0x20005CCF
-
-    .8byte 0x200060CF
-    .8byte 0x200064CF
-    .8byte 0x200068CF
-    .8byte 0x20006CCF
-
-    .8byte 0x200070CF
-    .8byte 0x200074CF
-    .8byte 0x200078CF
-    .8byte 0x20007CCF
-
-    .8byte 0x200080CF
-    .8byte 0x200084CF
-    .8byte 0x200088CF
-    .8byte 0x20008CCF
-
-    .8byte 0x200090CF
-    .8byte 0x200094CF
-    .8byte 0x200098CF
-    .8byte 0x20009CCF
-
-    .8byte 0x2000A0CF
-    .8byte 0x2000A4CF
-    .8byte 0x2000A8CF
-    .8byte 0x2000ACCF
-
-    .8byte 0x2000B0CF
-    .8byte 0x2000B4CF
-    .8byte 0x2000B8CF
-    .8byte 0x2000BCCF
-
-    .8byte 0x2000C0CF
-    .8byte 0x2000C4CF
-    .8byte 0x2000C8CF
-    .8byte 0x2000CCCF
-
-    .8byte 0x2000D0CF
-    .8byte 0x2000D4CF
diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S
deleted file mode 100644
index 285a170cb..000000000
--- a/tests/coverage/ieu.S
+++ /dev/null
@@ -1,108 +0,0 @@
-///////////////////////////////////////////
-// ieu.S
-//
-// Written: David_Harris@hmc.edu 21 March 2023
-//
-// Purpose: Test coverage for IEU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-
-    # Division test (having trouble with buildroot)
-    li x11, 0x384000
-    li x12, 0x1c2000
-    divuw x9, x11, x12
-
-    # Test clz with all bits being 0
-    li t0, 0
-    clz t1, t0
-    li t0, -1
-    clz t1, t0
-    li t0, 1
-    clz t1, t0
-
-    # Test forwarding from store conditional
-    mv a0, sp
-    lr.w t0, 0(a0)
-    sc.w t0, a1, 0(a0)
-    addi t0, t0, 1
-
-    # test prefetch Hints (ori with destination x0)
-    ori x0, x0, 0
-    ori x0, x0, 1
-    ori x0, x0, 2
-    ori x0, x0, 3
-
-
-    # Test illegal instructions are detected
-    .word 0x80000033 // illegal R-type instruction
-    .word 0x00007003 // illegal Load instruction
-    .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000
-    .word 0x00000000 // illegal instruction
-    .word 0x0000701B  // Illegal IW instruction
-    .word 0x00004023  // Illegal store instruction
-    .word 0x0400003B  // Illegal RW or MulDivW instruction
-    .word 0x00007067  // Illegal JALR instruction
-    .word 0x00002063  // Illegal branch instruction
-    .word 0x60F01013  // Illegal BMU sign extend / count instruction
-    .word 0x60801013  // Illegal BMU sign extend / count instruction
-    .word 0x60301013  // Illegal BMU sign extend / count instruction
-    .word 0x6BF05013  // Illegal BMU similar to rev8
-    .word 0x69805013  // Illegal BMU similar to rev8
-    .word 0x28F05013  // Illegal BMU similar to or.c
-    .word 0x60F0101B  // Illegal BMU similar to count word
-    .word 0x6080101B  // Illegal BMU similar to count word
-    .word 0x6030101B  // Illegal BMU similar to count word
-    .word 0x0000202F  // Illegal similar to LR
-    .word 0x1010202F  // Illegal similar to LR
-    .word 0x00402003  // illegal similar to CMO
-    .word 0x00202003  // illegal similar to CMO
-    .word 0xFF00302F  // illegal Atomic instruction
-    .word 0xFF00402F  // illegal Atomic instruction
-    .word 0x00000873  // illegal CSR instruction
-    .word 0x31bf1f93  // illegal aes64ksli1 instruction
-
-    # Illegal CMO instructions because envcfg is 0 and system is in user Mode
-    li a0, 0
-    ecall # switch to user mode
-    cbo.inval (x1)
-    cbo.clean (x1)
-    cbo.flush (x1)
-    cbo.zero  (x1)
-
-    li a0, 3
-    ecall # switch back to machine mode
-    li x1, 0x50
-    csrw menvcfg, x1
-    csrw senvcfg, x1
-    li a0, 0
-    ecall # swtich to user mode
-    cbo.inval (x2)
-    cbo.clean (x3)
-    cbo.flush (x1)
-
-
-
-
-    j done
diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S
deleted file mode 100644
index 054f4f336..000000000
--- a/tests/coverage/ifu.S
+++ /dev/null
@@ -1,98 +0,0 @@
-///////////////////////////////////////////
-// ifu.S
-//
-// Written: sriley@g.hmc.edu 28 March 2023
-//
-// Purpose: Test coverage for IFU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-    # turn floating point on
-    li t0, 0x2000
-    csrs mstatus, t0
-
-    # calling compressed floating point load double instruction
-    //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
-                        // binary version 0000 0000 0000 0000 0010 0000 0000 0000
-    mv s0, sp
-    c.fld fs0, 0(s0)    // Previously uncovered instructions
-    c.fsd fs0, 0(s0)
-    .hword 0x2002      // c.fldsp fs0, 0
-    .hword 0xA002      // c.fsdsp fs0, 0
-    .hword 0x9C41      // line 134 Illegal compressed instruction
-
-    # Zcb coverage tests
-    mv s0, sp
-    c.lbu s1, 0(s0)   // exercise c.lbu
-    c.lh s1, 0(s0)    // exercise c.lh
-    c.lhu s1, 0(s0)   // exercise c.lhu
-    c.sb s1, 0(s0)    // exercise c.sb
-    c.sh s1, 0(s0)    // exercise c.sh
-
-    .hword 0x2005      // line 110
-    .hword 0x6101      // line 114
-    .hword 0x6201      // line 115
-    .hword 0x0202      // Illegal compressed instruction with op = 10, Instr[15:13] = 000, c.slli x4, 0. Line 151 illegal instruction
-    .hword 0x4002      // Illegal compressed instruction with op = 10, Instr[15:13] = 010, c.lwsp zero, 0. Line 158 illegal instruction
-    .hword 0x8C44      // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
-    .hword 0x9C00      // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
-
-    li s0, 0xFF
-    c.zext.b s0      // exercise c.zext.b
-    c.sext.b s0      // exercise c.sext.b
-    c.zext.h s0      // exercise c.zext.h
-    c.sext.h s0      // exercise c.sext.h
-    c.zext.w s0      // exercise c.zext.w
-    c.not s0         // exercise c.not
-
-    .hword 0x9C7D      // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
-
-    # exercise all the cache ways
-    j way0code
-
-# stress test cache ways by loading stuff from each one and then doing fence.i to invalidate
-.align 12
-way0code:
-    jal way1code
-    fence.i
-    j done
-
-.align 12
-way1code:
-    j way2code
-
-.align 12
-way2code:
-    j way3code
-
-.align 12
-way3code:
-    j way00code
-
-.align 12
-way00code:
-    ret
-
-
-    j done
diff --git a/tests/coverage/ifuCamlineWrite.S b/tests/coverage/ifuCamlineWrite.S
deleted file mode 100644
index 31dcc5d05..000000000
--- a/tests/coverage/ifuCamlineWrite.S
+++ /dev/null
@@ -1,147 +0,0 @@
-///////////////////////////////////////////
-// ifuCamlineWrite.S
-//
-// Written: Miles Cook <mdcook@g.hmc.edu> and Kevin Box <kbox@g.hmc.edu> 4/17
-//
-// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza
-//                   and Noah Limpert.
-//
-// Purpose: Test coverage for TLBCamlines in IFU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    li t0, 0x80015000 # base addr
-
-    li t2, 0       # i = 0
-    li t3, 33     # Max amount of Loops = 32
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    li t4, 0x1000
-    li t1, 0x00008067 # load in jalr
-    sw t1, 0 (t0)
-    fence.I
-    jalr t0
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401 // old page table was 200040 which just pointed to itself! wrong
-
-.align 12
-    .8byte 0x0000000000000000
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-
-
-.align 12
-    .8byte 0x0000000020004C01
-    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
-
-.align 12
-    #80000000
-    .8byte 0x200000CF
-    .8byte 0x200004CF
-    .8byte 0x200008CF
-    .8byte 0x20000CCF
-
-    .8byte 0x200010CF
-    .8byte 0x200014CF
-    .8byte 0x200018CF
-    .8byte 0x20001CCF
-
-    .8byte 0x200020CF
-    .8byte 0x200024CF
-    .8byte 0x200028CF
-    .8byte 0x20002CCF
-
-    .8byte 0x200030CF
-    .8byte 0x200034CF
-    .8byte 0x200038CF
-    .8byte 0x20003CCF
-
-    .8byte 0x200040CF
-    .8byte 0x200044CF
-    .8byte 0x200048CF
-    .8byte 0x20004CCF
-
-    .8byte 0x200050CF
-    .8byte 0x200054CF
-    .8byte 0x200058CF
-    .8byte 0x20005CCF
-
-    .8byte 0x200060CF
-    .8byte 0x200064CF
-    .8byte 0x200068CF
-    .8byte 0x20006CCF
-
-    .8byte 0x200070CF
-    .8byte 0x200074CF
-    .8byte 0x200078CF
-    .8byte 0x20007CCF
-
-    .8byte 0x200080CF
-    .8byte 0x200084CF
-    .8byte 0x200088CF
-    .8byte 0x20008CCF
-
-    .8byte 0x200090CF
-    .8byte 0x200094CF
-    .8byte 0x200098CF
-    .8byte 0x20009CCF
-
-    .8byte 0x200100CF
-    .8byte 0x200104CF
-    .8byte 0x200108CF
-    .8byte 0x20010CCF
-
-    .8byte 0x200110CF
-    .8byte 0x200114CF
-    .8byte 0x200118CF
-    .8byte 0x20011CCF
-
-    .8byte 0x200120CF
-    .8byte 0x200124CF
-    .8byte 0x200128CF
-    .8byte 0x20012CCF
-
-    .8byte 0x200130CF
-    .8byte 0x200134CF
diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S
deleted file mode 100644
index 1c1d7fea6..000000000
--- a/tests/coverage/lsu.S
+++ /dev/null
@@ -1,37 +0,0 @@
-///////////////////////////////////////////
-// lsu.S
-//
-// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023
-//
-// Purpose: Test coverage for lsu
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-
-    sfence.vma x0, x0 // sfence.vma to assert TLBFlush
-
-    li a0, 0x80000001   # misaligned address
-    amoadd.w t0, a0, (a0) # amo access to misaligned address
-
-    j done
diff --git a/tests/coverage/nonleafpbmtfault.S b/tests/coverage/nonleafpbmtfault.S
deleted file mode 100644
index 29ca490d6..000000000
--- a/tests/coverage/nonleafpbmtfault.S
+++ /dev/null
@@ -1,143 +0,0 @@
-///////////////////////////////////////////
-// hptwAccessFault.S
-//
-// Written: Rose Thompson rose@rosethompson.net
-//
-// Purpose: Force the HPTW to walk a page table with non-leaf non-zero PBMT bits.  This will generate
-// a load or store/amo page fault based on the original access type.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-    li t5, 0
-    li t2, 0x1000
-    li t0, 0x8000001000
-
-    lw t1, 0(t0)       # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
-    li t1, 0x00008067
-    add t0, t0, t2
-    sw t1, 0(t0)      # valid virtual address, valid physical address, but invalid PBMT in middle of page table.
-
-    fence.I
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401
-    .8byte 0x20004401
-
-.align 12
-    .8byte 0x4000004020004801
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-
-
-.align 12
-    .8byte 0x0000000020004C01
-
-.align 12
-    #80000000
-    .8byte 0x200000CF
-    .8byte 0x200004CF
-    .8byte 0x200008CF
-    .8byte 0x20000CCF
-
-    .8byte 0x200010CF
-    .8byte 0x200014CF
-    .8byte 0x200018CF
-    .8byte 0x20001CCF
-
-    .8byte 0x200020CF
-    .8byte 0x200024CF
-    .8byte 0x200028CF
-    .8byte 0x20002CCF
-
-    .8byte 0x200030CF
-    .8byte 0x200034CF
-    .8byte 0x200038CF
-    .8byte 0x20003CCF
-
-    .8byte 0x200040CF
-    .8byte 0x200044CF
-    .8byte 0x200048CF
-    .8byte 0x20004CCF
-
-    .8byte 0x200050CF
-    .8byte 0x200054CF
-    .8byte 0x200058CF
-    .8byte 0x20005CCF
-
-    .8byte 0x200060CF
-    .8byte 0x200064CF
-    .8byte 0x200068CF
-    .8byte 0x20006CCF
-
-    .8byte 0x200070CF
-    .8byte 0x200074CF
-    .8byte 0x200078CF
-    .8byte 0x20007CCF
-
-    .8byte 0x200080CF
-    .8byte 0x200084CF
-    .8byte 0x200088CF
-    .8byte 0x20008CCF
-
-    .8byte 0x200090CF
-    .8byte 0x200094CF
-    .8byte 0x200098CF
-    .8byte 0x20009CCF
-
-    .8byte 0x2000A0CF
-    .8byte 0x2000A4CF
-    .8byte 0x2000A8CF
-    .8byte 0x2000ACCF
-
-    .8byte 0x2000B0CF
-    .8byte 0x2000B4CF
-    .8byte 0x2000B8CF
-    .8byte 0x2000BCCF
-
-    .8byte 0x2000C0CF
-    .8byte 0x2000C4CF
-    .8byte 0x2000C8CF
-    .8byte 0x2000CCCF
-
-    .8byte 0x2000D0CF
-    .8byte 0x2000D4CF
diff --git a/tests/coverage/pmp.S b/tests/coverage/pmp.S
deleted file mode 100644
index 9680bfdeb..000000000
--- a/tests/coverage/pmp.S
+++ /dev/null
@@ -1,1646 +0,0 @@
-///////////////////////////////////////////
-// /content/sample_data/PMPConfigregs.S
-// Kevin Box, kbox@hmc.edu
-// Created 2023-04-09 23:20:54.863039
-///////////////////////////////////////////
-
-
-
-
-#include "WALLY-init-lib.h"
-
-main:
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 0
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |0      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |1      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |2      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |3      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |4      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |5      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |6      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |7      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |8      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |9      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |10     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |11     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |12     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |13     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |14     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |15     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 0 in mode 0
-li t5, 536870975
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 1
-li t5, 536871039
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 2
-li t5, 536871102
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 3
-li t5, 536871198
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 0
-li t5, 536871231
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 1
-li t5, 536871295
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 2
-li t5, 536871358
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 3
-li t5, 536871454
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 0
-li t5, 536871487
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 1
-li t5, 536871551
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 2
-li t5, 536871614
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 3
-li t5, 536871710
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 0
-li t5, 536871743
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 1
-li t5, 536871807
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 2
-li t5, 536871870
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 3
-li t5, 536871966
-csrw pmpaddr15, t5
-
-
-  # write pmpcfg0, output 0x191109019b938b83
-li t4, 1806234828062034819
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x181008001c140c04
-li t4, 1733894653101739012
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 0
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 1
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |1      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |2      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |3      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |4      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |5      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |6      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |7      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |8      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |9      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |10     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |11     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |12     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |13     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |14     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |15     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |0      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 1 in mode 0
-li t5, 536870975
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 1
-li t5, 536871039
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 2
-li t5, 536871102
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 3
-li t5, 536871198
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 0
-li t5, 536871231
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 1
-li t5, 536871295
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 2
-li t5, 536871358
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 3
-li t5, 536871454
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 0
-li t5, 536871487
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 1
-li t5, 536871551
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 2
-li t5, 536871614
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 3
-li t5, 536871710
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 0
-li t5, 536871743
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 1
-li t5, 536871807
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 2
-li t5, 536871870
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 3
-li t5, 536871966
-csrw pmpaddr0, t5
-
-
-  # write pmpcfg0, output 0x1109019b938b8318
-li t4, 1227514141142123288
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x1008001c140c0419
-li t4, 1155173425015948313
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 1
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 2
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |2      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |3      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |4      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |5      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |6      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |7      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |8      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |9      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |10     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |11     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |12     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |13     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |14     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |15     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |0      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |1      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 2 in mode 0
-li t5, 536870975
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 1
-li t5, 536871039
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 2
-li t5, 536871102
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 3
-li t5, 536871198
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 0
-li t5, 536871231
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 1
-li t5, 536871295
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 2
-li t5, 536871358
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 3
-li t5, 536871454
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 0
-li t5, 536871487
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 1
-li t5, 536871551
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 2
-li t5, 536871614
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 3
-li t5, 536871710
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 0
-li t5, 536871743
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 1
-li t5, 536871807
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 2
-li t5, 536871870
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 3
-li t5, 536871966
-csrw pmpaddr1, t5
-
-
-  # write pmpcfg0, output 0x09019b938b831810
-li t4, 648970879321184272
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x08001c140c041911
-li t4, 576491624729942289
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 2
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 3
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |3      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |4      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |5      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |6      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |7      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |8      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |9      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |10     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |11     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |12     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |13     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |14     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |15     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |0      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |1      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |2      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 3 in mode 0
-li t5, 536870975
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 1
-li t5, 536871039
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 2
-li t5, 536871102
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 3
-li t5, 536871198
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 0
-li t5, 536871231
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 1
-li t5, 536871295
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 2
-li t5, 536871358
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 3
-li t5, 536871454
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 0
-li t5, 536871487
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 1
-li t5, 536871551
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 2
-li t5, 536871614
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 3
-li t5, 536871710
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 0
-li t5, 536871743
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 1
-li t5, 536871807
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 2
-li t5, 536871870
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 3
-li t5, 536871966
-csrw pmpaddr2, t5
-
-
-  # write pmpcfg0, output 0x019b938b83181008
-li t4, 115848442837209096
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x001c140c04191109
-li t4, 7903341188813065
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 3
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 4
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |4      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |5      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |6      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |7      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |8      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |9      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |10     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |11     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |12     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |13     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |14     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |15     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |0      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |1      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |2      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |3      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 4 in mode 0
-li t5, 536870975
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 1
-li t5, 536871039
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 2
-li t5, 536871102
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 3
-li t5, 536871198
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 0
-li t5, 536871231
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 1
-li t5, 536871295
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 2
-li t5, 536871358
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 3
-li t5, 536871454
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 0
-li t5, 536871487
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 1
-li t5, 536871551
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 2
-li t5, 536871614
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 3
-li t5, 536871710
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 0
-li t5, 536871743
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 1
-li t5, 536871807
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 2
-li t5, 536871870
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 3
-li t5, 536871966
-csrw pmpaddr3, t5
-
-
-  # write pmpcfg0, output 0x9b938b8318100800
-li t4, 11210457292615976960
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x1c140c0419110901
-li t4, 2023255344336144641
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 4
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 5
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |5      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |6      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |7      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |8      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |9      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |10     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |11     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |12     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |13     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |14     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |15     | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |0      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |1      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |2      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |3      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |4      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 5 in mode 0
-li t5, 536870975
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 1
-li t5, 536871039
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 2
-li t5, 536871102
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 3
-li t5, 536871198
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 0
-li t5, 536871231
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 1
-li t5, 536871295
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 2
-li t5, 536871358
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 3
-li t5, 536871454
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 0
-li t5, 536871487
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 1
-li t5, 536871551
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 2
-li t5, 536871614
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 3
-li t5, 536871710
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 0
-li t5, 536871743
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 1
-li t5, 536871807
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 2
-li t5, 536871870
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 3
-li t5, 536871966
-csrw pmpaddr4, t5
-
-
-  # write pmpcfg0, output 0x938b83181008001c
-li t4, 10631735484709601308
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x140c04191109019b
-li t4, 1444534086185583003
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 5
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 6
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |6      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |7      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |8      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |9      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |10     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |11     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |12     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |13     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |14     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |15     | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |0      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |1      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |2      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |3      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |4      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |5      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 6 in mode 0
-li t5, 536870975
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 1
-li t5, 536871039
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 2
-li t5, 536871102
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 3
-li t5, 536871198
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 0
-li t5, 536871231
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 1
-li t5, 536871295
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 2
-li t5, 536871358
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 3
-li t5, 536871454
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 0
-li t5, 536871487
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 1
-li t5, 536871551
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 2
-li t5, 536871614
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 3
-li t5, 536871710
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 0
-li t5, 536871743
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 1
-li t5, 536871807
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 2
-li t5, 536871870
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 3
-li t5, 536871966
-csrw pmpaddr5, t5
-
-
-  # write pmpcfg0, output 0x8b83181008001c14
-li t4, 10052905250353847316
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x0c04191109019b93
-li t4, 865844589318216595
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 6
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 7
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |7      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |8      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |9      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |10     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |11     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |12     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |13     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |14     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |15     | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |0      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |1      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |2      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |3      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |4      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |5      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |6      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 7 in mode 0
-li t5, 536870975
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 1
-li t5, 536871039
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 2
-li t5, 536871102
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 3
-li t5, 536871198
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 0
-li t5, 536871231
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 1
-li t5, 536871295
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 2
-li t5, 536871358
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 3
-li t5, 536871454
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 0
-li t5, 536871487
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 1
-li t5, 536871551
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 2
-li t5, 536871614
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 3
-li t5, 536871710
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 0
-li t5, 536871743
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 1
-li t5, 536871807
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 2
-li t5, 536871870
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 3
-li t5, 536871966
-csrw pmpaddr6, t5
-
-
-  # write pmpcfg0, output 0x83181008001c140c
-li t4, 9446317844957238284
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x04191109019b938b
-li t4, 295285980948829067
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 7
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 8
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |8      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |9      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |10     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |11     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |12     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |13     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |14     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |15     | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |0      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |1      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |2      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |3      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |4      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |5      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |6      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |7      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 8 in mode 0
-li t5, 536870975
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 1
-li t5, 536871039
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 2
-li t5, 536871102
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 3
-li t5, 536871198
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 0
-li t5, 536871231
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 1
-li t5, 536871295
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 2
-li t5, 536871358
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 3
-li t5, 536871454
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 0
-li t5, 536871487
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 1
-li t5, 536871551
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 2
-li t5, 536871614
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 3
-li t5, 536871710
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 0
-li t5, 536871743
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 1
-li t5, 536871807
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 2
-li t5, 536871870
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 3
-li t5, 536871966
-csrw pmpaddr7, t5
-
-
-  # write pmpcfg0, output 0x181008001c140c04
-li t4, 1733894653101739012
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x191109019b938b83
-li t4, 1806234828062034819
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 8
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 9
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |9      | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |10     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |11     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |12     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |13     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |14     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |15     | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |0      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |1      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |2      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |3      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |4      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |5      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |6      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |7      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |8      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 9 in mode 0
-li t5, 536870975
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 1
-li t5, 536871039
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 2
-li t5, 536871102
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 3
-li t5, 536871198
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 0
-li t5, 536871231
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 1
-li t5, 536871295
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 2
-li t5, 536871358
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 3
-li t5, 536871454
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 0
-li t5, 536871487
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 1
-li t5, 536871551
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 2
-li t5, 536871614
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 3
-li t5, 536871710
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 0
-li t5, 536871743
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 1
-li t5, 536871807
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 2
-li t5, 536871870
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 3
-li t5, 536871966
-csrw pmpaddr8, t5
-
-
-  # write pmpcfg0, output 0x1008001c140c0419
-li t4, 1155173425015948313
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x1109019b938b8318
-li t4, 1227514141142123288
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 9
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 10
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |10     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |11     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |12     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |13     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |14     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |15     | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |0      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |1      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |2      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |3      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |4      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |5      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |6      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |7      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |8      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |9      | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 10 in mode 0
-li t5, 536870975
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 1
-li t5, 536871039
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 2
-li t5, 536871102
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 3
-li t5, 536871198
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 0
-li t5, 536871231
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 1
-li t5, 536871295
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 2
-li t5, 536871358
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 3
-li t5, 536871454
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 0
-li t5, 536871487
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 1
-li t5, 536871551
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 2
-li t5, 536871614
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 3
-li t5, 536871710
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 0
-li t5, 536871743
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 1
-li t5, 536871807
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 2
-li t5, 536871870
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 3
-li t5, 536871966
-csrw pmpaddr9, t5
-
-
-  # write pmpcfg0, output 0x08001c140c041911
-li t4, 576491624729942289
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x09019b938b831810
-li t4, 648970879321184272
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 10
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 11
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |11     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |12     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |13     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |14     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |15     | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |0      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |1      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |2      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |3      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |4      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |5      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |6      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |7      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |8      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |9      | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |10     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 11 in mode 0
-li t5, 536870975
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 1
-li t5, 536871039
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 2
-li t5, 536871102
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 3
-li t5, 536871198
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 0
-li t5, 536871231
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 1
-li t5, 536871295
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 2
-li t5, 536871358
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 3
-li t5, 536871454
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 0
-li t5, 536871487
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 1
-li t5, 536871551
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 2
-li t5, 536871614
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 3
-li t5, 536871710
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 0
-li t5, 536871743
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 1
-li t5, 536871807
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 2
-li t5, 536871870
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 3
-li t5, 536871966
-csrw pmpaddr10, t5
-
-
-  # write pmpcfg0, output 0x001c140c04191109
-li t4, 7903341188813065
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x019b938b83181008
-li t4, 115848442837209096
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 11
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 12
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |12     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |13     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |14     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |15     | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |0      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |1      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |2      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |3      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |4      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |5      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |6      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |7      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |8      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |9      | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |10     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |11     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 12 in mode 0
-li t5, 536870975
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 1
-li t5, 536871039
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 2
-li t5, 536871102
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 3
-li t5, 536871198
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 0
-li t5, 536871231
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 1
-li t5, 536871295
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 2
-li t5, 536871358
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 3
-li t5, 536871454
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 0
-li t5, 536871487
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 1
-li t5, 536871551
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 2
-li t5, 536871614
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 3
-li t5, 536871710
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 0
-li t5, 536871743
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 1
-li t5, 536871807
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 2
-li t5, 536871870
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 3
-li t5, 536871966
-csrw pmpaddr11, t5
-
-
-  # write pmpcfg0, output 0x1c140c0419110901
-li t4, 2023255344336144641
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x9b938b8318100800
-li t4, 11210457292615976960
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 12
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 13
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |13     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |14     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |15     | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |0      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |1      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |2      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |3      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |4      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |5      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |6      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |7      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |8      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |9      | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |10     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |11     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |12     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 13 in mode 0
-li t5, 536870975
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 1
-li t5, 536871039
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 2
-li t5, 536871102
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 3
-li t5, 536871198
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 0
-li t5, 536871231
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 1
-li t5, 536871295
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 2
-li t5, 536871358
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 3
-li t5, 536871454
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 0
-li t5, 536871487
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 1
-li t5, 536871551
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 2
-li t5, 536871614
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 3
-li t5, 536871710
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 0
-li t5, 536871743
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 1
-li t5, 536871807
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 2
-li t5, 536871870
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 3
-li t5, 536871966
-csrw pmpaddr12, t5
-
-
-  # write pmpcfg0, output 0x140c04191109019b
-li t4, 1444534086185583003
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x938b83181008001c
-li t4, 10631735484709601308
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 13
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 14
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |14     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |15     | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |0      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |1      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |2      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |3      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |4      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |5      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |6      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |7      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |8      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |9      | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |10     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |11     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |12     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |13     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 14 in mode 0
-li t5, 536870975
-csrw pmpaddr14, t5
-
- # configure the pmp address of register 15 in mode 1
-li t5, 536871039
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 2
-li t5, 536871102
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 3
-li t5, 536871198
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 0
-li t5, 536871231
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 1
-li t5, 536871295
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 2
-li t5, 536871358
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 3
-li t5, 536871454
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 0
-li t5, 536871487
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 1
-li t5, 536871551
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 2
-li t5, 536871614
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 3
-li t5, 536871710
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 0
-li t5, 536871743
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 1
-li t5, 536871807
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 2
-li t5, 536871870
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 3
-li t5, 536871966
-csrw pmpaddr13, t5
-
-
-  # write pmpcfg0, output 0x0c04191109019b93
-li t4, 865844589318216595
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x8b83181008001c14
-li t4, 10052905250353847316
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 14
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// BEGIN Configuration and Testing Starting at Register: 15
-//
-// Configuration
-
-  # | Reg   | pmpaddr     | pmpcfg    | L | A    | X | W | R | Comments
-  # |15     | 0x2000003f  | 0x83      | 1 | 00   | 0 | 1 | 1 | 0
-  # |0      | 0x2000007f  | 0x8b      | 1 | 01   | 0 | 1 | 1 | 1
-  # |1      | 0x200000be  | 0x93      | 1 | 10   | 0 | 1 | 1 | 2
-  # |2      | 0x2000011e  | 0x9b      | 1 | 11   | 0 | 1 | 1 | 3
-  # |3      | 0x2000013f  | 0x01      | 0 | 00   | 0 | 0 | 1 | 4
-  # |4      | 0x2000017f  | 0x09      | 0 | 01   | 0 | 0 | 1 | 5
-  # |5      | 0x200001be  | 0x11      | 0 | 10   | 0 | 0 | 1 | 6
-  # |6      | 0x2000021e  | 0x19      | 0 | 11   | 0 | 0 | 1 | 7
-  # |7      | 0x2000023f  | 0x04      | 0 | 00   | 1 | 0 | 0 | 8
-  # |8      | 0x2000027f  | 0x0c      | 0 | 01   | 1 | 0 | 0 | 9
-  # |9      | 0x200002be  | 0x14      | 0 | 10   | 1 | 0 | 0 | 10
-  # |10     | 0x2000031e  | 0x1c      | 0 | 11   | 1 | 0 | 0 | 11
-  # |11     | 0x2000033f  | 0x00      | 0 | 00   | 0 | 0 | 0 | 12
-  # |12     | 0x2000037f  | 0x08      | 0 | 01   | 0 | 0 | 0 | 13
-  # |13     | 0x200003be  | 0x10      | 0 | 10   | 0 | 0 | 0 | 14
-  # |14     | 0x2000041e  | 0x18      | 0 | 11   | 0 | 0 | 0 | 15
- # configure the pmp address of register 15 in mode 0
-li t5, 536870975
-csrw pmpaddr15, t5
-
- # configure the pmp address of register 0 in mode 1
-li t5, 536871039
-csrw pmpaddr0, t5
-
- # configure the pmp address of register 1 in mode 2
-li t5, 536871102
-csrw pmpaddr1, t5
-
- # configure the pmp address of register 2 in mode 3
-li t5, 536871198
-csrw pmpaddr2, t5
-
- # configure the pmp address of register 3 in mode 0
-li t5, 536871231
-csrw pmpaddr3, t5
-
- # configure the pmp address of register 4 in mode 1
-li t5, 536871295
-csrw pmpaddr4, t5
-
- # configure the pmp address of register 5 in mode 2
-li t5, 536871358
-csrw pmpaddr5, t5
-
- # configure the pmp address of register 6 in mode 3
-li t5, 536871454
-csrw pmpaddr6, t5
-
- # configure the pmp address of register 7 in mode 0
-li t5, 536871487
-csrw pmpaddr7, t5
-
- # configure the pmp address of register 8 in mode 1
-li t5, 536871551
-csrw pmpaddr8, t5
-
- # configure the pmp address of register 9 in mode 2
-li t5, 536871614
-csrw pmpaddr9, t5
-
- # configure the pmp address of register 10 in mode 3
-li t5, 536871710
-csrw pmpaddr10, t5
-
- # configure the pmp address of register 11 in mode 0
-li t5, 536871743
-csrw pmpaddr11, t5
-
- # configure the pmp address of register 12 in mode 1
-li t5, 536871807
-csrw pmpaddr12, t5
-
- # configure the pmp address of register 13 in mode 2
-li t5, 536871870
-csrw pmpaddr13, t5
-
- # configure the pmp address of register 14 in mode 3
-li t5, 536871966
-csrw pmpaddr14, t5
-
-
-  # write pmpcfg0, output 0x04191109019b938b
-li t4, 295285980948829067
-csrw pmpcfg0, t4
-
-  # write pmpcfg2, output 0x83181008001c140c
-li t4, 9446317844957238284
-csrw pmpcfg2, t4
-
-
-// Testing
-
-// END Configuration and Testing Starting at Register: 15
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-    j done
diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S
deleted file mode 100644
index f338b3a10..000000000
--- a/tests/coverage/pmpadrdecs.S
+++ /dev/null
@@ -1,183 +0,0 @@
-// pmpadrdecs
-// Liam Chalk, lchalk@hmc.edu, 4/27/2023
-// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4]
-
-#include "WALLY-init-lib.h"
-main:
-
-    # Writing values to pmpcfg0 to change AdrMode to 2 or 3
-    # pmpadrdec[0]
-    li t0, 0x0000000010
-    csrw pmpcfg0, t0
-    # pmpadrdec[1]
-    li t0, 0x0000001800
-    csrw pmpcfg0, t0
-    # pmpadrdec[2]
-    li t0, 0x0000180000
-    csrw pmpcfg0, t0
-    # pmpadrdec[4]
-    li t0, 0x1000000000
-    csrw pmpcfg0, t0
-
-    # test hitting each region in NA4 mode for DMMU
-    li t0, 0x20000000 # address 0x80000000
-    csrw pmpaddr15, t0
-    csrw pmpaddr14, t0
-    csrw pmpaddr13, t0
-    csrw pmpaddr12, t0
-    li t0, 0x1717171717171717 # every region is NA4 XWR
-    csrw pmpcfg0, t0
-    csrw pmpcfg2, t0
-
-
-    # test hitting region in NA4 mode for IMMU
-    la t0, pmpjump # address of a jump destination to exercise immu pmpchecker
-    srli t1, t0, 2 # shift right by 2 to convert to PMP format
-    csrw pmpaddr15, t1
-    csrw pmpaddr14, t1
-    csrw pmpaddr13, t1
-    csrw pmpaddr12, t1
-    csrw pmpaddr11, t1
-    csrw pmpaddr10, t1
-    csrw pmpaddr9, t1
-    csrw pmpaddr8, t1
-    csrw pmpaddr7, t1
-    csrw pmpaddr6, t1
-    csrw pmpaddr5, t1
-    csrw pmpaddr4, t1
-    csrw pmpaddr3, t1
-    csrw pmpaddr2, t1
-    csrw pmpaddr1, t1
-    csrw pmpaddr0, t1
-    jalr t0
-
-    # test hitting region in TOR mode for IMMU
-    add t2, t1, 1   # top of range
-
-    # region 0 TOR at pmpjump
-    li t3, 0x0F # TOR XWR
-    csrw pmpcfg0, t3
-    csrw pmpcfg2, 0
-    csrw pmpaddr0, t2
-    jalr t0
-
-    # region 1 TOR at pmpjump
-    li t3, 0x0F00 # TOR XWR
-    csrw pmpcfg0, t3
-    csrw pmpcfg2, 0
-    csrw pmpaddr0, t1
-    csrw pmpaddr1, t2
-    jalr t0
-
-    # region 1 TOR at pmpjump
-    li t3, 0x0F00 # TOR XWR
-    csrw pmpcfg0, t3
-    csrw pmpcfg2, 0
-    csrw pmpaddr0, t1
-    csrw pmpaddr1, t2
-    jalr t0
-
-    # region 8 TOR at pmpjump
-    li t3, 0x0F # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr7, t1
-    csrw pmpaddr8, t2
-    jalr t0
-
-    # region 9 TOR at pmpjump
-    li t3, 0x0F00 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr8, t1
-    csrw pmpaddr9, t2
-    jalr t0
-
-    # region 10 TOR at pmpjump
-    li t3, 0x0F0000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr9, t1
-    csrw pmpaddr10, t2
-    jalr t0
-
-    # region 11 TOR at pmpjump
-    li t3, 0x0F000000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr10, t1
-    csrw pmpaddr11, t2
-    jalr t0
-
-    # region 12 TOR at pmpjump
-    li t3, 0x0F00000000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr11, t1
-    csrw pmpaddr12, t2
-    jalr t0
-
-    # region 13 TOR at pmpjump
-    li t3, 0x0F0000000000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr12, t1
-    csrw pmpaddr13, t2
-    jalr t0
-
-    # region 14 TOR at pmpjump
-    li t3, 0x0F000000000000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr13, t1
-    csrw pmpaddr14, t2
-    jalr t0
-
-    # region 15 TOR at pmpjump
-    li t3, 0x0F00000000000000 # TOR XWR
-    csrw pmpcfg2, t3
-    csrw pmpcfg0, 0
-    csrw pmpaddr14, t1
-    csrw pmpaddr15, t2
-    jalr t0
-
-
-
-    # test AMO not causing Load access fault
-    # assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM & ~WriteAccessM & ~MatchingR;
-    la s0, scratch
-
-    li t0, 0x0F000C00 # region 3 encompassing all addresses has TOR XWR, region 1 has TOR X only
-    csrw pmpcfg0, t0
-
-    # give only execute access to scratch
-    # set up TOR region 0-1 to do this (yes, NA4 would work too)
-    srli t0, s0, 2 # drop bottom two bits
-    csrw pmpaddr0, t0
-    addi t0, t0, 1 # next word
-    csrw pmpaddr1, t0
-
-    # everything else has full access, with a big TOR from 0 t0 FFFFFFFF
-    csrw pmpaddr2, zero
-    li t0, 0xFFFFFFFF  # full range
-    csrw pmpaddr3, t0
-    
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    # test the AMO
-    amoswap.w t1, zero, (s0)  # attempt amo; should get store but not load access fault because this region is X only
-
-    li a0, 3
-    ecall     # return to M mode
-   
-    j done
-
-.align 2
-pmpjump:
-    ret
-
-.align 2
-scratch:
-    .word 0
diff --git a/tests/coverage/pmpcbo.S b/tests/coverage/pmpcbo.S
deleted file mode 100644
index 3a7638404..000000000
--- a/tests/coverage/pmpcbo.S
+++ /dev/null
@@ -1,31 +0,0 @@
-// pmpcbo.S
-// David_Harris@hmc.edu 1/21/24
-// Cover PMP checks of cache management instructions
-
-#include "WALLY-init-lib.h"
-main:
-
-     # set up PMP so user and supervisor mode can access partial address space
-    li t0, 0x080F;
-#    li t0, 0x0808;
-    csrw pmpcfg0, t0  # configure PMP0 to TOR RWX and PMP1 to TOR no access
-    li t0, 0x2003FFFF
-    li t1, 0xFFFFFFFF
-    csrw pmpaddr0, t0   # configure PMP0 top of range to 0x800FFFFF to allow all 32-bit addresses
-    csrw pmpaddr1, t1   # configure PMP1 top of range to 0xFFFFFFFF to prohibit accesses above
-
-    # enable cbo instructions
-    li t0, 0xF0
-    csrw menvcfg, t0
-    csrw senvcfg, t0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    # cbo instructions to PMP-forbidded address
-    li a0, 0x81000000   # forbidden address
-    cbo.zero (a0)
-    cbo.inval (a0)
-
-    j done
diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S
deleted file mode 100644
index 1013439b7..000000000
--- a/tests/coverage/pmpcfg.S
+++ /dev/null
@@ -1,106 +0,0 @@
-// pmpcfg part 1
-// Kevin Wan, kewan@hmc.edu, 4/18/2023
-// Liam Chalk, lchalk@hmc.edu, 4/25/2023
-// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
-// See the next part in pmpcfg1.S
-
-#include "WALLY-init-lib.h"
-main:
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00000017
-    csrw pmpcfg0, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr2, t0
-    li t0, 0x00000017
-    csrw pmpcfg2, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00001700
-    csrw pmpcfg0, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00001700
-    csrw pmpcfg1, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00001700
-    csrw pmpcfg2, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00001700
-    csrw pmpcfg3, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr1, t0
-    li t0, 0x00001700
-    csrw pmpcfg1, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr2, t0
-    li t0, 0x00001700
-    csrw pmpcfg2, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr3, t0
-    li t0, 0x00001700
-    csrw pmpcfg3, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x00170000
-    csrw pmpcfg0, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr2, t0
-    li t0, 0x00170000
-    csrw pmpcfg2, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr0, t0
-    li t0, 0x17000000
-    csrw pmpcfg0, t0
-
-    li t0, 0x90000000
-    csrw pmpaddr2, t0
-    li t0, 0x17000000
-    csrw pmpcfg2, t0
-
-    li t0, 0x8800000000000000
-    csrw pmpcfg2, t0
-    li t0, 0x88000000000000
-    csrw pmpcfg2, t0
-    li t0, 0x880000000000
-    csrw pmpcfg2, t0
-    li t0, 0x8800000000
-    csrw pmpcfg2, t0
-    li t0, 0x88000000
-    csrw pmpcfg2, t0
-    li t0, 0x880000
-    csrw pmpcfg2, t0
-    li t0, 0x8800
-    csrw pmpcfg2, t0
-    li t0, 0x88
-    csrw pmpcfg2, t0
-    li t0, 0x8800000000000000
-    csrw pmpcfg0, t0
-    li t0, 0x88000000000000
-    csrw pmpcfg0, t0
-    li t0, 0x880000000000
-    csrw pmpcfg0, t0
-    li t0, 0x8800000000
-    csrw pmpcfg0, t0
-    li t0, 0x88000000
-    csrw pmpcfg0, t0
-    li t0, 0x880000
-    csrw pmpcfg0, t0
-    li t0, 0x8800
-    csrw pmpcfg0, t0
-
-    j done
diff --git a/tests/coverage/pmpcfg1.S b/tests/coverage/pmpcfg1.S
deleted file mode 100644
index 37dcec14b..000000000
--- a/tests/coverage/pmpcfg1.S
+++ /dev/null
@@ -1,48 +0,0 @@
-// another set of pmpcfg tests. A new file is made because pmpcfg register fields are
-// locked forever after writing 1 to the lock bit for the first time.
-
-// Kevin Wan, kewan@hmc.edu, 4/13/2023
-// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits.
-// for the other part of the tests, see pmpcfg.S
-
-#include "WALLY-init-lib.h"
-main:
-    li t0, 0x800
-    csrw pmpcfg0, t0
-    li t0, 0x8000000
-    csrw pmpcfg0, t0
-
-    li t0, 0x8000000000000000
-    csrw pmpcfg2, t0
-    li t0, 0x80000000000000
-    csrw pmpcfg2, t0
-    li t0, 0x800000000000
-    csrw pmpcfg2, t0
-    li t0, 0x8000000000
-    csrw pmpcfg2, t0
-    li t0, 0x80000000
-    csrw pmpcfg2, t0
-    li t0, 0x800000
-    csrw pmpcfg2, t0
-    li t0, 0x8000
-    csrw pmpcfg2, t0
-    li t0, 0x80
-    csrw pmpcfg2, t0
-    li t0, 0x8000000000000000
-    csrw pmpcfg0, t0
-    li t0, 0x80000000000000
-    csrw pmpcfg0, t0
-    li t0, 0x800000000000
-    csrw pmpcfg0, t0
-    li t0, 0x8000000000
-    csrw pmpcfg0, t0
-    li t0, 0x80000000
-    csrw pmpcfg0, t0
-    li t0, 0x800000
-    csrw pmpcfg0, t0
-    li t0, 0x8000
-    csrw pmpcfg0, t0
-
-
-
-    j done
diff --git a/tests/coverage/pmpcfg2.S b/tests/coverage/pmpcfg2.S
deleted file mode 100644
index 4e0002e6e..000000000
--- a/tests/coverage/pmpcfg2.S
+++ /dev/null
@@ -1,12 +0,0 @@
-// pmpcfg part 3
-// Kevin Wan, kewan@hmc.edu, 4/18/2023
-// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
-// See the next part in pmpcfg1.S
-
-#include "WALLY-init-lib.h"
-main:
-    li t0, 0x80
-    csrw pmpcfg0, t0
-
-
-    j done
diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S
deleted file mode 100644
index 8a30c6019..000000000
--- a/tests/coverage/pmppriority.S
+++ /dev/null
@@ -1,158 +0,0 @@
-// pmppriority test cases
-// Kevin Wan kewan@hmc.edu 4/27/2023
-// want memory ranges to match:
-// 1. only the most significant address and none of the lower ones,
-// 2. the most significant address and ANY of the lower ones.
-
-
-
-#include "WALLY-init-lib.h"
-main:
-
-    li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg.
-    csrw pmpaddr0, t1
-    csrw pmpaddr1, t1
-    csrw pmpaddr2, t1
-    csrw pmpaddr3, t1
-    csrw pmpaddr4, t1
-    csrw pmpaddr5, t1
-    csrw pmpaddr6, t1
-    csrw pmpaddr7, t1
-
-    csrw pmpaddr8, t1
-    csrw pmpaddr9, t1
-    csrw pmpaddr10, t1
-    csrw pmpaddr11, t1
-    csrw pmpaddr12, t1
-    csrw pmpaddr13, t1
-    csrw pmpaddr14, t1
-    csrw pmpaddr15, t1
-
-
-    li t0, 0x1F
-    csrw pmpcfg0, t0 //set to XWR and NAPOT
-    sw zero, 0(sp)
-
-    li t0, 0x1F00
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F0000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F000000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F00000000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F0000000000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F000000000000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F00000000000000
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F1F1F
-    csrw pmpcfg0, t0
-    sw zero, 0(sp)
-
-    li t0, 0x0
-    csrw pmpcfg0, t0
-    li t0, 0x1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F00
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F0000
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F00000000
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F0000000000
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F000000000000
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F00000000000000
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F1F1F
-    csrw pmpcfg0, t0
-    li t0, 0x1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-    li t0, 0x1F1F1F1F1F1F1F1F
-    csrw pmpcfg2, t0
-    sw zero, 0(sp)
-
-
-
-    j done
diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S
deleted file mode 100644
index 211e7d13a..000000000
--- a/tests/coverage/priv.S
+++ /dev/null
@@ -1,329 +0,0 @@
-///////////////////////////////////////////
-// priv.S
-//
-// Written: David_Harris@hmc.edu 23 March 2023
-//
-// Purpose: Test coverage for EBU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-#include "WALLY-init-lib.h"
-
-main:
-    # Tests sret in machine mode
-    la t1, sretdone
-    csrw sepc, t1
-    sret
-sretdone:
-    addi t2, x0, 42
-
-    # switch to user mode
-    li a0, 0
-    ecall
-    sret #should be treated as illegal instruction
-    mret #mret in user mode and should be illegal
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    # Test read to stimecmp fails when MCOUNTEREN_TM is not set
-    li t1, -3
-    csrw stimecmp, t1
-    csrr t0, stimecmp
-
-
-    # satp write with mstatus.TVM = 1
-    bseti t0, zero, 20
-    csrs mstatus, t0
-    csrw satp, zero
-
-    # STIMECMP from S mode
-    # 1st is when MENVCFG_STCE is cleared
-    li a0, 3
-    ecall # starts in M-mode
-    li t1, -3
-    csrw stimecmp, t1 # sets stimecmp to large value to prevent it from interrupting immediately
-    li t0, 2
-    csrs mstatus, t0 # enables sie
-    li t0, 32
-    csrs sie, t0 # enables sie.stie
-    csrw menvcfg, x0
-    li a0, 1
-    ecall   # enter S-mode
-    csrw stimecmp, zero
-    li a0, 3
-    ecall # in M-mode
-    li t0, 32
-    csrs mip, t0
-    li a0, 1
-    ecall # in S-mode and expects stimer interrupt to occur
-    li a0, 3
-    ecall   # return to M-mode
-    csrsi mcounteren, 2 # mcounteren_tm = 1
-    li a0, 1
-    ecall   # supervisor mode again
-    csrw stimecmp, zero
-    li a0, 3
-    ecall  # machine mode again
-
-    # STIMECMP from S mode
-    # 2nd is when MENVCFG_STCE is set
-    csrci mcounteren, 2 # mcounteren_tm = 0
-    li t0, 1
-    slli t0, t0, 63
-    csrw menvcfg, t0
-    li a0, 1
-    ecall   # enter S-mode
-    csrw stimecmp, zero
-    li a0, 3
-    ecall   # return to M-mode
-    csrsi mcounteren, 2 # mcounteren_tm = 1
-    li a0, 1
-    ecall   # supervisor mode again
-    csrw stimecmp, zero
-    li a0, 3
-    ecall  # machine mode again
-
-    # writes to FCSR
-    li t0, 1
-    slli t0, t0, 13
-    csrs mstatus, t0
-    li t0, 1
-    csrw fcsr, t0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
-    li t0, 0
-    csrw stval, t0
-    csrw scause, t0
-    csrw sepc, t0
-    csrw stimecmp, t0
-    csrw scounteren, zero
-    csrw satp, zero
-
-
-    # Switch to machine mode
-    li a0, 3
-    ecall
-
-    # Write to MCOUNTINHIBIT CSR
-    csrw mcountinhibit, t0
-
-    # Testing the HPMCOUNTERM performance counter: writing
-    # Base address is 2816 (MHPMCOUNTERBASE)
-    # There are 32 HPMCOUNTER registers
-    csrw 2816, t0
-    csrw 2817, t0
-    csrw 2818, t0
-    csrw 2819, t0
-    csrw 2820, t0
-    csrw 2821, t0
-    csrw 2822, t0
-    csrw 2823, t0
-    csrw 2824, t0
-    csrw 2825, t0
-    csrw 2826, t0
-    csrw 2827, t0
-    csrw 2828, t0
-    csrw 2829, t0
-    csrw 2830, t0
-    csrw 2831, t0
-    csrw 2832, t0
-    csrw 2833, t0
-    csrw 2834, t0
-    csrw 2835, t0
-    csrw 2836, t0
-    csrw 2837, t0
-    csrw 2838, t0
-    csrw 2839, t0
-    csrw 2840, t0
-    csrw 2841, t0
-    csrw 2842, t0
-    csrw 2843, t0
-    csrw 2844, t0
-    csrw 2845, t0
-    csrw 2846, t0
-    csrw 2847, t0
-
-    # Testing the HPMCOUNTERM performance counter: reading
-    csrr t0, 2817
-
-    # Test writes to pmp address registers
-    csrw 951, t0
-    csrw 952, t0
-    csrw 953, t0
-    csrw 954, t0
-    csrw 955, t0
-    csrw 956, t0
-    csrw 957, t0
-    csrw 958, t0
-
-
-    # Testing writes to MTVAL, MCAUSE
-    li t0, 0
-    csrw mtval, t0
-    csrw mcause, t0
-
-    # set mstatus to enable floating point registers (mstatus.FS = 11)
-    bseti t1, zero, 13
-    csrs mstatus, t1
-    bseti t1, zero, 14
-    csrs mstatus, t1
-
-    # Test writes to floating point CSRs
-    csrw frm, t0
-    csrw fflags, t0
-
-    # CSRC MCOUNTEREN Register
-    # Go to machine mode
-    li a0, 3
-    ecall
-    # Activate HPM3
-    li t0, -1
-    csrw mcounteren, t0
-    csrw scounteren, t0
-
-    # Go to supervisor
-    li a0, 1
-    ecall
-    #try to write to HPMs
-    csrw 333, t0
-    #go to user mode
-    li a0, 0
-    ecall
-    csrr t0, hpmcounter22
-
-    # setting registers bits to 0
-    li a0, 3 # back to machine mode
-    ecall
-    li t0, 0
-    csrw mcounteren, t0
-    csrw scounteren, t0
-
-    #getting the remainder of PMD instructions
-
-    #go to user mode
-    li a0, 0
-    ecall
-    #set status TVM to 0 by writing to bit 20 of mstatus as 0
-    #bseti t0, zero, 20
-    sfence.vma zero, zero
-
-    # Go to supervisor mode
-    li a0, 1
-    ecall
-
-    sfence.vma zero, zero
-
-    li a0, 3
-    ecall
-
-    # Write to satp when status.TVM is 1 from machine mode
-    bseti t0, zero, 20
-    csrs mstatus, t0
-
-    csrw satp, t0
-
-
-
-    # Test checking privilege for reading counters (using counter 22 as an example)
-
-    # Go to machine mode
-    li a0, 3
-    ecall
-
-    # Set SCOUNTEREN to all 0s, MCOUNTEREN to all 1s
-    li t0, 0
-    csrw scounteren, t0
-    li t1, -1
-    csrw mcounteren, t1
-
-
-    # Go to supervisor mode
-    li a0, 1
-    ecall
-
-    # try to read from HPM22
-    csrr t0, hpmcounter22
-
-    # go to user mode
-    li a0, 0
-    ecall
-
-    csrr t0, hpmcounter22
-
-    #getting the mpp and mstatus Mpriv condition met
-    #go to machine mode
-    li a0, 3
-    ecall
-    # set bit 17 of mstatus to enable STATUS_MPRV
-    bseti t1, zero, 17
-    csrs mstatus, t1
-
-    li a0, 3
-    ecall
-
-    # set bit 21 of mstatus to 0 to disable STATUS_TW
-    csrr t1, mstatus
-    bseti t2, zero, 21
-    not t2, t2
-    and t1, t1, t2
-    csrs mstatus, t1
-
-    # go to user mode
-    li a0, 0
-    ecall
-
-    wfi
-
-
-
-    # Test uncovered privdec instructions
-    li a0, 3
-    ecall
-    # exercise sfence.inval.ir instruction
-    sfence.inval.ir
-
-    # exercise sret with rs1 not 0
-    .word 0x102F8073
-
-    # illegal ebreak with nonzero rs1
-    .word 0x00110073
-
-
-    # cover mret when mpp = 3 and mprv = 1
-    li a0, 3
-    ecall               # enter machine mode
-    bseti t0, zero, 17
-    csrs mstatus, t0    # set MPRV
-    li t1, 0x00001800
-    csrs mstatus, t1    # set MPP=3
-    la t1, finished
-    csrr t0, mepc
-    csrw mepc, t1       # set mepc for mret to jump to
-    mret
-
-
-finished: j done
diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S
deleted file mode 100644
index 29078f0da..000000000
--- a/tests/coverage/tlbASID.S
+++ /dev/null
@@ -1,131 +0,0 @@
-///////////////////////////////////////////
-// tlbASID.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-//
-// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd
-// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080080 // try making asid = 0.
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    li t0, 0xC0000000
-
-    li t2, 0            # i = 0
-    li t5, 0            # j = 0 // now use as a counter for new asid loop
-    li t3, 32           # Max amount of Loops = 32
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    sfence.vma
-    li t1, 0x00008067 #load in jalr
-    sw t1, 0(t0)
-    fence.I
-    jalr t0
-    li t5, 0x9001000000080080 // try making asid = 1
-    csrw satp, t5
-    jalr t0
-    li t5, 0x9000000000080080 // try making asid = 0
-    csrw satp, t5
-    li t4, 0x1000
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-finished:
-    j done
-
-.data
-.align 19
-# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
-pagetable:
-    .8byte 0x20020401
-
-.align 12 // level 2 page table, contains direction to a gigapage
-    .8byte 0x0
-    .8byte 0x0
-    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
-    .8byte 0x20020801 // pointer to next page table entry at 8008 2000
-
-.align 12 // level 1 page table, points to level 0 page table
-    .8byte 0x20020C01
-
-.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
-    .8byte 0x200000CF // access xC000 0000
-    .8byte 0x200004CF // access xC000 1000
-    .8byte 0x200008CF // access xC000 2000
-    .8byte 0x20000CCF // access xC000 3000
-
-    .8byte 0x200010CF // access xC000 4000
-    .8byte 0x200014CF
-    .8byte 0x200018CF
-    .8byte 0x20001CCF
-
-    .8byte 0x200020CF // access xC000 8000
-    .8byte 0x200024CF
-    .8byte 0x200028CF
-    .8byte 0x20002CCF
-
-    .8byte 0x200030CF // access xC000 C000
-    .8byte 0x200034CF
-    .8byte 0x200038CF
-    .8byte 0x20003CCF
-
-    .8byte 0x200040CF // access xC001 0000
-    .8byte 0x200044CF
-    .8byte 0x200048CF
-    .8byte 0x20004CCF
-
-    .8byte 0x200050CF // access xC001 4000
-    .8byte 0x200054CF
-    .8byte 0x200058CF
-    .8byte 0x20005CCF
-
-    .8byte 0x200060CF // access xC001 8000
-    .8byte 0x200064CF
-    .8byte 0x200068CF
-    .8byte 0x20006CCF
-
-    .8byte 0x200070CF // access xC001 C000
-    .8byte 0x200074CF
-    .8byte 0x200078CF
-    .8byte 0x20007CCF
-
-    .8byte 0x200080CF // access xC002 0000
-    .8byte 0x200084CF
-    .8byte 0x200088CF
-    .8byte 0x20008CCF
diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S
deleted file mode 100644
index b8fdee742..000000000
--- a/tests/coverage/tlbGLB.S
+++ /dev/null
@@ -1,181 +0,0 @@
-///////////////////////////////////////////
-// tlbGLB.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-// Modified: kevin.j.thomas@okstate.edu May/4/20203
-//
-// Purpose: Coverage for the Page Table Entry Global flag check.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080080 // try making asid = 0.
-    csrw satp, t5
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    li t5, 0            # j = 0, run nASID only once
-    li t3, 32                       //Max amount of Loops = 32
-    li t4, 0x1000                   //offset between addressses.
-    li t1, 0x00008067               //load in jalr x0 x1 0 instruction to be stored
-
-setup:
-    li t0, 0xC0000000               //starting address
-    li t2, 0             # i = 0
-    beq t5, zero, loop              //jump to first loop
-
-loop2:  #jump to each of the addresses in different address space
-    bge t2, t3, done
-    jalr t0                         //jump to instruction at the virtual address
-    add t0, t0, t4                  //change address for next loop
-    addi t2, t2, 1                  //keep track of number of loops ran
-    j loop2
-
-loop:   #store jalr across memory
-    bge t2, t3, nASID   # exit loop if i >= loops
-    sw t1, 0(t0)                    //stores this jalr in the virtual address
-    fence.I                         //invalidate instruction cache
-    jalr t0                         //jump to instruction at the virtual address
-    add t0, t0, t4                  //change address for next loop
-    addi t2, t2, 1                  //keep track of number of loops ran
-    j loop
-
-nASID:   #swap to different address space -> jump to each address
-    li a0, 3                        //swap to machine mode
-    ecall
-    li t5, 0x9000100000080080       //swap to address space 1 from 0
-    csrw satp, t5
-    li a0, 1                        // change back to supervisor mode.
-    ecall
-    li t5, 1                        //flag for finished after loops
-    j setup
-
-
-
-.data
-.align 19
-# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
-pagetable:
-    .8byte 0x20020401
-
-.align 12 // level 2 page table, contains direction to a gigapageg
-    .8byte 0x0
-    .8byte 0x0
-    .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000
-    .8byte 0x20020821 // pointer to next page table entry at 8008 2000
-
-.align 12 // level 1 page table, points to level 0 page table
-    .8byte 0x20020C21
-
-.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
-    .8byte 0x200000EF // access xC000 0000
-    .8byte 0x200004EF // access xC000 1000
-    .8byte 0x200008EF // access xC000 2000
-    .8byte 0x20000CEF // access xC000 3000
-
-    .8byte 0x200010EF // access xC000 4000
-    .8byte 0x200014EF
-    .8byte 0x200018EF
-    .8byte 0x20001CEF
-
-    .8byte 0x200020EF // access xC000 8000
-    .8byte 0x200024EF
-    .8byte 0x200028EF
-    .8byte 0x20002CEF
-
-    .8byte 0x200030EF // access xC000 C000
-    .8byte 0x200034EF
-    .8byte 0x200038EF
-    .8byte 0x20003CEF
-
-    .8byte 0x200040EF // access xC001 0000
-    .8byte 0x200044EF
-    .8byte 0x200048EF
-    .8byte 0x20004CEF
-
-    .8byte 0x200050EF // access xC001 4000
-    .8byte 0x200054EF
-    .8byte 0x200058EF
-    .8byte 0x20005CEF
-
-    .8byte 0x200060EF // access xC001 8000
-    .8byte 0x200064EF
-    .8byte 0x200068EF
-    .8byte 0x20006CEF
-
-    .8byte 0x200070EF // access xC001 C000
-    .8byte 0x200074eF
-    .8byte 0x200078EF
-    .8byte 0x20007CEF
-
-    .8byte 0x200080EF // access xC002 0000
-    .8byte 0x200084EF
-    .8byte 0x200088EF
-    .8byte 0x20008CEF
-
-        .8byte 0x200010EF // access xC000 4000
-    .8byte 0x200014EF
-    .8byte 0x200018EF
-    .8byte 0x20001CEF
-
-    .8byte 0x200020EF // access xC000 8000
-    .8byte 0x200024EF
-    .8byte 0x200028EF
-    .8byte 0x20002CEF
-
-    .8byte 0x200030EF // access xC000 C000
-    .8byte 0x200034EF
-    .8byte 0x200038EF
-    .8byte 0x20003CEF
-
-    .8byte 0x200040EF // access xC001 0000
-    .8byte 0x200044EF
-    .8byte 0x200048EF
-    .8byte 0x20004CEF
-
-    .8byte 0x200050EF // access xC001 4000
-    .8byte 0x200054EF
-    .8byte 0x200058EF
-    .8byte 0x20005CEF
-
-    .8byte 0x200060EF // access xC001 8000
-    .8byte 0x200064EF
-    .8byte 0x200068EF
-    .8byte 0x20006CEF
-
-    .8byte 0x200070EF // access xC001 C000
-    .8byte 0x200074eF
-    .8byte 0x200078EF
-    .8byte 0x20007CEF
-
-    .8byte 0x200080EF // access xC002 0000
-    .8byte 0x200084EF
-    .8byte 0x200088EF
-    .8byte 0x20008CEF
diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S
deleted file mode 100644
index 25fb2af94..000000000
--- a/tests/coverage/tlbGP.S
+++ /dev/null
@@ -1,154 +0,0 @@
-///////////////////////////////////////////
-// tlbGP.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-//
-// Purpose: Create Page tables and access gigapages
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-    li t5, 0
-    li t0, 0xC0200000 // go to first gigapage
-    li t4, 0x40000000 // put this outside the loop.
-    li t2, 0      # i = 0
-    li t3, 64     # Max amount of Loops = 16
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    lw t1, 0(t0)
-    li t1, 0x00008067 #load in jalr
-    sw t1, 0(t0)
-    fence.I
-    jalr t0
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401
-
-.align 12
-    .8byte 0x000000CF  //8000 0000
-    .8byte 0x100000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-
-
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
-    .8byte 0x200000CF
diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S
deleted file mode 100644
index 7c7a76bbd..000000000
--- a/tests/coverage/tlbMP.S
+++ /dev/null
@@ -1,199 +0,0 @@
-///////////////////////////////////////////
-// tlbMP.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-//
-// Purpose: Test coverage for LSU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    li t5, 0
-    li t0, 0x84000000 // go to first megapage
-    li t4, 0x200000 // put this outside the loop.
-    li t2, 0      # i = 0
-    li t3, 32     # Max amount of Loops = 16
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    li t1, 0x00008067 #load in jalr
-    sw t1, 0(t0)
-    fence.I
-    jalr t0
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401
-
-.align 12
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-
-
-.align 12 // megapages starting at 8000 0000 going to 8480 0000  (32*2 MiB beyond that)
-
-    .8byte 0x200000CF // access 8000,0000
-    .8byte 0x200800CF // access 8020,0000
-    .8byte 0x201000CF // acesss 8040,0000
-    .8byte 0x201800CF // acesss 8060,0000
-
-    .8byte 0x202000CF // access 8080,0000
-    .8byte 0x202800CF // access 80A0,0000
-    .8byte 0x203000CF // access 80C0,0000
-    .8byte 0x203800CF // access 80E0,0000
-
-    .8byte 0x204000CF // access 8100,0000
-    .8byte 0x204800CF
-    .8byte 0x205000CF
-    .8byte 0x205800CF
-
-    .8byte 0x206000CF // access 8180,0000
-    .8byte 0x206800CF
-    .8byte 0x207000CF
-    .8byte 0x207800CF
-
-    .8byte 0x208000CF // access 8200,0000
-    .8byte 0x208800CF
-    .8byte 0x209000CF
-    .8byte 0x209800CF
-
-    .8byte 0x20A000CF // access 8280,0000
-    .8byte 0x20A800CF
-    .8byte 0x20B000CF
-    .8byte 0x20B800CF
-
-    .8byte 0x20C000CF // access 8300,0000
-    .8byte 0x20C800CF
-    .8byte 0x20D000CF
-    .8byte 0x20D800CF
-
-    .8byte 0x20E000CF // access 8380,0000
-    .8byte 0x20E800CF
-    .8byte 0x20F000CF
-    .8byte 0x20F800CF
-
-    .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME.
-    .8byte 0x200800CF // access 8020,0000
-    .8byte 0x201000CF // acesss 8040,0000
-    .8byte 0x201800CF // acesss 8060,0000
-
-    .8byte 0x202000CF // access 8080,0000
-    .8byte 0x202800CF // access 80A0,0000
-    .8byte 0x203000CF // access 80C0,0000
-    .8byte 0x203800CF // access 80E0,0000
-
-    .8byte 0x204000CF // access 8100,0000
-    .8byte 0x204800CF
-    .8byte 0x205000CF
-    .8byte 0x205800CF
-
-    .8byte 0x206000CF // access 8180,0000
-    .8byte 0x206800CF
-    .8byte 0x207000CF
-    .8byte 0x207800CF
-
-    .8byte 0x208000CF // access 8200,0000
-    .8byte 0x208800CF
-    .8byte 0x209000CF
-    .8byte 0x209800CF
-
-    .8byte 0x20A000CF // access 8280,0000
-    .8byte 0x20A800CF
-    .8byte 0x20B000CF
-    .8byte 0x20B800CF
-
-    .8byte 0x20C000CF // access 8300,0000
-    .8byte 0x20C800CF
-    .8byte 0x20D000CF
-    .8byte 0x20D800CF
-
-    .8byte 0x20E000CF // access 8380,0000
-    .8byte 0x20E800CF
-    .8byte 0x20F000CF
-    .8byte 0x20F800CF
-
-    .8byte 0x20004C01
-     // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
-                      // point to ...
-
-.align 12 // should start at 84000000
-    .8byte 0x210000CF
-    .8byte 0x210004CF
-    .8byte 0x210008CF
-    .8byte 0x21000CCF
-
-    .8byte 0x210010CF
-    .8byte 0x210014CF
-    .8byte 0x210018CF
-    .8byte 0x21001CCF
-
-    .8byte 0x210020CF
-    .8byte 0x210024CF
-    .8byte 0x210028CF
-    .8byte 0x21002CCF
-
-    .8byte 0x210030CF
-    .8byte 0x210034CF
-    .8byte 0x210038CF
-    .8byte 0x21003CCF
-
-    .8byte 0x210040CF
-    .8byte 0x210044CF
-    .8byte 0x210048CF
-    .8byte 0x21004CCF
-
-    .8byte 0x210050CF
-    .8byte 0x210054CF
-    .8byte 0x210058CF
-    .8byte 0x21005CCF
-
-    .8byte 0x210060CF
-    .8byte 0x210064CF
-    .8byte 0x210068CF
-    .8byte 0x21006CCF
-
-    .8byte 0x210070CF
-    .8byte 0x210074CF
-    .8byte 0x210078CF
-    .8byte 0x21007CCF
diff --git a/tests/coverage/tlbMisaligned.S b/tests/coverage/tlbMisaligned.S
deleted file mode 100644
index d72643c08..000000000
--- a/tests/coverage/tlbMisaligned.S
+++ /dev/null
@@ -1,152 +0,0 @@
-///////////////////////////////////////////
-// tlbMisaligned.S
-//
-// Written: Rose Thompson rose@rosethompson.net
-//
-// Purpose: Create a page table with misaligned load and store access.  Checks TLB misses prevent misaligned load/store fault.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    li t5, 0x1
-    slli t5, t5, 62
-    ori t5, t5, 0xF0
-    csrs menvcfg, t5  # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
-
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-    li t5, 0
-    li t2, 0x1000
-    li t0, 0x1000 // go to first gigapage
-    li t4, 0x40000000 // put this outside the loop.
-
-    lw t1, 1(t0) # load a misaligned aligned cached address
-    li t1, 0x00008067 #load in jalr
-    add t0, t0, t2 # go to the next page
-    sw t1, 1(t0) # store to another misaligned cached address.
-
-    add t0, t0, t2 # go to the next page
-    lw t1, 1(t0) # load a misaligned aligned uncached address should fault
-    add t0, t0, t2 # go to the next page
-    sw t1, 1(t0) # store to another misaligned uncached address should falt.
-
-    fence.I
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401
-
-.align 12
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-    .8byte 0x0000000020004801
-
-
-.align 12
-    .8byte 0x0000000020004C01
-    //.8byte 0x000002008000F// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
-
-.align 12
-    #80000000
-    .8byte 0x200000CF
-    .8byte 0x200004CF  # first page
-    .8byte 0x200008CF  # second page
-    .8byte 0x2000000020000CCF  # 3rd page
-
-    .8byte 0x20000000200010CF  # 4th page
-    .8byte 0x200014CF
-    .8byte 0x200018CF
-    .8byte 0x20001CCF
-
-    .8byte 0x200020CF
-    .8byte 0x200024CF
-    .8byte 0x200028CF
-    .8byte 0x20002CCF
-
-    .8byte 0x200030CF
-    .8byte 0x200034CF
-    .8byte 0x200038CF
-    .8byte 0x20003CCF
-
-    .8byte 0x200040CF
-    .8byte 0x200044CF
-    .8byte 0x200048CF
-    .8byte 0x20004CCF
-
-    .8byte 0x200050CF
-    .8byte 0x200054CF
-    .8byte 0x200058CF
-    .8byte 0x20005CCF
-
-    .8byte 0x200060CF
-    .8byte 0x200064CF
-    .8byte 0x200068CF
-    .8byte 0x20006CCF
-
-    .8byte 0x200070CF
-    .8byte 0x200074CF
-    .8byte 0x200078CF
-    .8byte 0x20007CCF
-
-    .8byte 0x200080CF
-    .8byte 0x200084CF
-    .8byte 0x200088CF
-    .8byte 0x20008CCF
-
-    .8byte 0x200090CF
-    .8byte 0x200094CF
-    .8byte 0x200098CF
-    .8byte 0x20009CCF
-
-    .8byte 0x2000A0CF
-    .8byte 0x2000A4CF
-    .8byte 0x2000A8CF
-    .8byte 0x2000ACCF
-
-    .8byte 0x2000B0CF
-    .8byte 0x2000B4CF
-    .8byte 0x2000B8CF
-    .8byte 0x2000BCCF
-
-    .8byte 0x2000C0CF
-    .8byte 0x2000C4CF
-    .8byte 0x2000C8CF
-    .8byte 0x2000CCCF
-
-    .8byte 0x2000D0CF
-    .8byte 0x2000D4CF
diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S
deleted file mode 100644
index 859476d23..000000000
--- a/tests/coverage/tlbNAPOT.S
+++ /dev/null
@@ -1,439 +0,0 @@
-///////////////////////////////////////////
-// tlbNAPOT.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-// Adapted David_Harris@hmc.edu 8/29/23 to exercise NAPOT huge pages
-//
-// Purpose: Test coverage for LSU NAPOT
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    li t5, 0x1
-    slli t5, t5, 62
-    csrs menvcfg, t5
-    # Page table root address at 0x80010000; SV48
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    li t4, 0x200000   # address step size
-    li a2, 0x80215240 # Test NAPOT pages
-    jal a1, looptest
-    li a2, 0xC0215240  # Test ill-formed NAPOT pages
-    jal a1, looptest
-    li a2, 0x40215240  # Test properly formed pages with 1 in PPN[3] that are not NAPOT
-    jal a1, looptest
-    li t4, 0x1000     # address step size
-    li a2, 0x80216000 # Test NAPOT pages
-    jal a1, looptest
-
-    sfence.vma
-    li t4, 0x200000   # address step size
-    li a2, 0x80215240 # Test NAPOT pages
-    jal a1, looptest
-    li a2, 0xC0215240  # Test ill-formed NAPOT pages
-    jal a1, looptest
-    li a2, 0x40215240  # Test properly formed pages with 1 in PPN[3] that are not NAPOT
-    jal a1, looptest
-
-    li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
-    ecall
-    j done
-
-looptest:
-    mv t0, a2       # base address
-    li t2, 0        # i = 0
-    li t3, 32     # Max amount of Loops = 32
-    li t5, 0x8082 # return instruction opcode
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    sw t5, 0(t0)   # store a return at this address to exercise DTLB
-    lw t1, 0(t0)   # read it back
-    fence.i    # synchronize with I$
-    jal changetoipfhandler  # set up trap handler to return from instruction page fault if necessary
-    jalr ra, t0 # jump to the return statement to exercise the ITLB
-    jal changetodefaulthandler
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-finished:
-    jr a1
-
-changetoipfhandler:
-    li a0, 3
-    ecall       # switch to machine mode
-    la a0, ipf_handler
-    csrw mtvec, a0 # point to new handler
-    li a0, 1
-    ecall       # switch back to supervisor mode
-    ret
-
-changetodefaulthandler:
-    li a0, 3
-    ecall       # switch to machine mode
-    la a0, trap_handler
-    csrw mtvec, a0 # point to new handler
-    li a0, 1
-    ecall       # switch back to supervisor mode
-    ret
-
-instructionpagefaulthandler:
-    csrw mepc, ra # go back to calling function
-    mret
-
-.align 4                # trap handlers must be aligned to multiple of 4
-ipf_handler:
-    # Load trap handler stack pointer tp
-    csrrw tp, mscratch, tp  # swap MSCRATCH and tp
-    sd t0, 0(tp)        # Save t0 and t1 on the stack
-    sd t1, -8(tp)
-    csrr t0, mcause     # Check the cause
-    li t1, 8            # is it an ecall trap?
-    andi t0, t0, 0xFC   # if CAUSE = 8, 9, or 11
-    beq t0, t1, ecall   # yes, take ecall
-    csrr t0, mcause
-    li t1, 12           # is it an instruction page fault
-    beq t0, t1, ipf     # yes, return to calling function
-    j trap_return
-
-ipf:
-    csrw mepc, ra       # return to calling function
-    ld t1, -8(tp)       # restore t1 and t0
-    ld t0, 0(tp)
-    csrrw tp, mscratch, tp  # restore tp
-    mret                # return from trap
-
-.data
-
-.align 16
-# root Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401 // old page table was 200040 which just pointed to itself! wrong
-
-# next page table at 0x80011000
-.align 12
-    .8byte 0x0000000000000000 # gigapage at 0x00000000
-    .8byte 0x0000000020005801 # gigapage at 0x40000000 used for non-NAPOT with PPN bit 3 set
-    .8byte 0x0000000020004801 # gigapage at 0x80000000 used for testing NAPOT huge pages
-    .8byte 0x0000000020005001 # gigapage at 0xC0000000 mapped to ill-formed NAPOT with wrong PPN
-
-
-# Next page table at 0x80012000 for gigapage at 0x80000000
-.align 12
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-    .8byte 0x0000000020004C01
-
-# Leaf page table at 0x80013000 with NAPOT pages
-.align 12
-    #80000000
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-# Next page table at 0x80014000: mega-sized, pointing to malformed NAPOT  for gigapage at 0xC9000000
-.align 12
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-    .8byte 0x0000000020005401
-
-# Leaf page table at 0x80015000 with malformed NAPOT pages (wrong PPN) starting at 0xC0000000
-.align 12
-    #80000000
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-    .8byte 0x80000000200000CF
-
-
-# Next page table at 0x80016000: mega-sized, pointing to properly formed PTE with 1 in PPN bit 3  for gigapage at 0x40000000
-.align 12
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-    .8byte 0x0000000020005C01
-
-# Leaf page table at 0x80017000 with properly formed PTE with bit 4 of PPN set but no NAPOT
-.align 12
-    #80000000
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
-
-    .8byte 0x00000000200020CF
-    .8byte 0x00000000200060CF
-    .8byte 0x000000002000A0CF
-    .8byte 0x000000002000E0CF
diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S
deleted file mode 100644
index 89b5d1ec7..000000000
--- a/tests/coverage/tlbTP.S
+++ /dev/null
@@ -1,145 +0,0 @@
-///////////////////////////////////////////
-// tlbTP.S
-//
-// Written: mmendozamanriquez@hmc.edu 4 April 2023
-//          nlimpert@hmc.edu
-//
-// Purpose: Test coverage for LSU
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    # Page table root address at 0x80010000
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-    li t5, 0
-    li t0, 0x80000000 // go to first gigapage
-    li t4, 0x8000000000 // put this outside the loop.
-    li t2, 0      # i = 0
-    li t3, 64     # run through 64 PTEs
-
-loop: bge t2, t3, finished   # exit loop if i >= loops
-    li t1, 0x00008067
-    sw t1, 0(t0)
-    fence.I
-    jalr t0
-    add t0, t0, t4
-    addi t2, t2, 1
-    j loop
-
-
-finished:
-    j done
-
-.data
-
-.align 16
-# Page table situated at 0x80010000
-pagetable:
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
-    .8byte 0x0CF
diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S
deleted file mode 100644
index b16cca8cd..000000000
--- a/tests/coverage/tlbmisc.S
+++ /dev/null
@@ -1,487 +0,0 @@
-///////////////////////////////////////////
-// tlbmisc.S
-//
-// Written David_Harris@hmc.edu 1/1/24
-//
-// Purpose: Test coverage for other TLB issues
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-    li t5, 0x1
-    slli t5, t5, 62
-    ori t5, t5, 0xF0
-    csrs menvcfg, t5  # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
-
-    # store ret instruction in case we jump to an address mapping to 80000000
-    li t0, 0x80000000
-    li t5, 0x8082 # return instruction opcode
-    sw t5, 0(t0)
-    fence.i
-
-    # Test not being able to write illegal SATP mode
-    li t5, 0xA000000000080010
-    csrw satp, t5
-
-    # Page table root address at 0x80010000; SV48
-    li t5, 0x9000000000080010
-    csrw satp, t5
-
-    # sfence.vma x0, x0
-
-    # switch to supervisor mode
-    li a0, 1
-    ecall
-
-    # Instruction fetch from misaligned pages
-    jal changetoipfhandler  # set up trap handler to return from instruction page fault if necessary
-    li t0, 0x8000000000
-    jalr ra, t0 # jump misaligned terapage
-    li t0, 0x00000000
-    jalr ra, t0 # jump to misaligned gigapage
-    li t0, 0x80200000
-    jalr ra, t0 # jump to misaligned megapage
-    li t0, 0x7FFFFFFF80000000
-
-
-    jalr ra, t0 # jump to page with UpperBitsUnequal
-    li t0, 0x0000000080C00000
-    jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
-
-    # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,
-    li a0, 3
-    ecall       # switch to machine mode
-    li t0, 1
-    slli t0, t0, 61
-    csrs menvcfg, t0 # set menvcfg.ADUE
-    li a0, 1
-    ecall       # switch back to supervisor mode
-    li t0, 0x0000000080E00000
-    jalr ra, t0 # jump to page without accessed bit yet set
-    li a0, 3
-    ecall       # switch to machine mode
-    li t0, 1
-    slli t0, t0, 61
-    csrc menvcfg, t0 # clear menvcfg.ADUE
-    li a0, 1
-    ecall       # switch back to supervisor mode
-
-     # exercise malformed PBMT pages
-
-    # page has PBMT = 3 (reserved)
-    li t0, 0x80400000
-    lw t1, 0(t0)    # read from page
-    sw t1, 0(t0)    # write to page
-    jalr ra, t0     # jump to page
-
-    # AMO at page has PBMT = 2 or 1 (uncached)
-    li t0, 0x80401000
-    li t1, 10
-    amoadd.w t1, t1, (t0)
-
-    la t2, SpecialPage
-    li t0, 0x200000000  # an address to a specific 1 GiB page
-    j ConcurrentICacheMissDTLBMiss
-
-.align 6
-ConcurrentICacheMissDTLBMiss:
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-    lw t1, 0(t0)
-
-    # write a cacheline length (512 bits) to memory in uncached region
-    li t0, 0x80401000
-    cbo.zero (t0)
-
-    # Nonleaf PTE has PBMT != 0     causes a page fault during page walking.  H
-    li t0, 0x80600000
-    lw t1, 0(t0)    # read from page
-    sw t1, 0(t0)    # write to page
-    jalr ra, t0     # jump to page
-
-    # jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
-    li t0, 0x80805000
-    jalr ra, t0
-    li t0, 0x80807000 # again, triggering setting access bit
-    jalr ra, t0
-
-    # atomic access to uncachable memory
-    #li t0, 0x80806000
-    #sd zero, 0(t0)
-    #amoadd.w t1, t0, (t0)
-
-    # Access page with R=0 W = 1
-    li t0, 0x80804000
-    li t1, 0x8067 # ret
-    sw t1, 0(t0) # have something to return from
-    jalr ra, t0
-
-    # Good PBMT with menvcfg.PBMT = 1, 
-    li t0, 0x80806000
-    jalr ra, t0
-
-    # Good PBMT with menvcfg.PBMTE = 0
-    li a0, 3
-    ecall   # switch to machine mode
-    li t5, 0x1
-    slli t5, t5, 62
-    csrc menvcfg, t5  # menvcfg.PBMTE = 0
-    li a0, 1
-    ecall   # switch back to supervisor mode
-    li t0, 0x80806000
-    jalr ra, t0      # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
-
-    # Load and AMO operation on page table entry that causes access fault
-    li t0, 0x81000000
-    lw t1, 0(t0)
-    sfence.vma
-    amoadd.w t0, t0, 0(t0)
-
-    # Access fault on top level PTE
-    li t0, 0x1000000000
-    lw t1, 0(t0)
-
-    # Bad PBMT on top level PTE
-    li t0, 0x1800000000
-    lw t1, 0(t0)
-
-    # Access fault on megapage
-    li t0, 0x81400000
-    lw t1, 0(t0)
-
-    # Access fault walking page tables at megapage level
-    li t0, 0xC0000000
-    lw t1, 0(t0)
-
-    # AMO operation on page table entry that causes page fault due to malformed PBMT
-    li t0, 0x81200000
-    jalr t0          # Attempt to fetch instruction from address causing faulty page walk
-    lw t1, 0(t0)
-    sfence.vma
-    amoadd.w t0, t0, 0(t0)
-
-    # point top-level page table to an illegal address and verify it faults
-    li t0, 0x9000000000070000 # trap handler at non-existing memory location
-    csrw satp, t0 # should cause trap
-    sfence.vma
-    nop
-
-
-    # change back to default trap handler after checking everything that might cause an instruction page fault
-    jal changetodefaulthandler
-
-    # uncachable AMO access
-    li t0, 0x80401000  # PBMT sets as uncachable
-    amoadd.w t0, t0, 0(t0)
-
-    # exercise CBOM instructions with various permissions
-    li t0, 0x80800000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80801000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80802000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80803000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80804000
-    cbo.zero (t0)
-    cbo.clean (t0)
-
-    # set mstatus.MXR
-    li a0, 3
-    ecall
-    li t0, 1
-    slli t0, t0, 19
-    csrs mstatus, t0 # mstatus.mxr = 1
-    li a0, 1
-    ecall
-
-    # exercise CBOM again now that MXR is set
-    li t0, 0x80800000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80801000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80802000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80803000
-    cbo.zero (t0)
-    cbo.clean (t0)
-    li t0, 0x80804000
-    cbo.zero (t0)
-    cbo.clean (t0)
-
-    # clear mstatus.MXR
-    li a0, 3
-    ecall
-    li t0, 1
-    slli t0, t0, 19
-    csrc mstatus, t0 # mstatus.mxr = 1
-    li a0, 1
-    ecall
-
-
-
-
-    # wrap up
-    li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
-    ecall
-    j done
-
-backandforth:
-    ret
-
-changetoipfhandler:
-    li a0, 3
-    ecall       # switch to machine mode
-    la a0, ipf_handler
-    csrw mtvec, a0 # point to new handler
-    li a0, 1
-    ecall       # switch back to supervisor mode
-    ret
-
-changetodefaulthandler:
-    li a0, 3
-    ecall       # switch to machine mode
-    la a0, trap_handler
-    csrw mtvec, a0 # point to new handler
-    li a0, 1
-    ecall       # switch back to supervisor mode
-    ret
-
-instructionpagefaulthandler:
-    csrw mepc, ra # go back to calling function
-    mret
-
-.align 4                # trap handlers must be aligned to multiple of 16
-ipf_handler:
-    # Load trap handler stack pointer tp
-    csrrw tp, mscratch, tp  # swap MSCRATCH and tp
-    sd t0, 0(tp)        # Save t0 and t1 on the stack
-    sd t1, -8(tp)
-    li t5, 0x9000000000080010
-    csrw satp, t5       # make sure we are pointing to the root page table
-    csrr t0, mcause     # Check the cause
-    li t1, 8            # is it an ecall trap?
-    andi t0, t0, 0xFC   # if CAUSE = 8, 9, or 11
-    beq t0, t1, ecall   # yes, take ecall
-    csrr t0, mcause
-    li t1, 12           # is it an instruction page fault
-    beq t0, t1, ipf     # yes, return to calling function
-    j trap_return
-
-ipf:
-    csrw mepc, ra       # return to calling function
-    ld t1, -8(tp)       # restore t1 and t0
-    ld t0, 0(tp)
-    csrrw tp, mscratch, tp  # restore tp
-    mret                # return from trap
-
-.align 4                # trap handlers must be aligned to multiple of 16
-fixsatptraphandler:
-    li t5, 0x9000000000080010   # fix satp entry to normal page table root
-    csrw satp, t5
-    mret
-
-.data
-
-.align 16
-# root Page table situated at 0x80010000
-pagetable:
-    .8byte 0x20004401  # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 01 valid
-    .8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
-    .8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
-    .8byte 0x4000000020004401 # Bad PBMT at VA 0x180_0000000
-
-# next page table at 0x80011000
-.align 12
-    .8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
-    .8byte 0x0000000020005801 # PTE for pages at 0x40000000 pointing to 0x80150000
-    .8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000
-    .8byte 0x0000000000000001 # gigapage at VA 0xC0000000 causes access fault
-    .8byte 0x0
-    .8byte 0x0
-    .8byte 0x0
-    .8byte 0x0
-SpecialPage:
-    .8byte 0x00000000200000CF   # 0x2_0000_0000 1GiB page1
-
-
-# Next page table at 0x80012000 for gigapage at 0x80000000
-.align 12
-    .8byte 0x0000000020004C01  # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages Page table at 80013000)
-    .8byte 0x0000000020014CCF  # for VA starting at 80200000 (misaligned megapage)
-    .8byte 0x0000000020005001  # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000)
-    .8byte 0x4000000020004C01  # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
-    .8byte 0x0000000020005401  # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000)
-    .8byte 0x0000000020004C01  # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000.  page table at 0x80013000)
-    .8byte 0x0F00000020004CCF  # for VA starting at 80C00000 (bad reserved field in bits 60:54)
-    .8byte 0x000000002000000F  # for VA starting at 80E00000 (megapage not dirty or accessed)
-    .8byte 0x0000000000004C01  # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault)
-    .8byte 0x4000000020004C01  # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault)
-    .8byte 0x00000000000000CF  # for VA starting at 81400000 (megapage with access fault)
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-    .8byte 0x0000000020004CC1
-
-# Leaf page table at 0x80013000 with 64 KiB NAPOT pages
-.align 12
-    #80000000
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-    .8byte 0xA0000000200020CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-    .8byte 0x80000000200060CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-    .8byte 0x800000002000A0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-    .8byte 0x800000002000E0CF
-    .8byte 0x800000002000E0CF
-
-# Leaf page table at 0x80014000 with PBMT pages
-.align 12
-    #80400000
-    .8byte 0x60000000200020CF   # reserved entry             VA 80400000
-    .8byte 0x40000000201000CF   # non-cache non-idempotent   VA 80401000
-
-# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
-.align 12
-    #80800000
-    .8byte 0x00000000200000CF   # valid rwx for VA 80800000
-    .8byte 0x00000000200000CB   # valid r x for VA 80801000
-    .8byte 0x00000000200000C3   # valid r   for VA 80802000
-    .8byte 0x00000000200000C9   # valid   x for VA 80803000
-    .8byte 0x00000000200000CD   # valid  wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
-    .8byte 0x00000000200000CF   # valid rwx for VA 80805000  for covering ITLB translate
-    .8byte 0x20000000200000CF   # PBMT=1    for VA 80806000  for covering ITLB BadPBMT
-    .8byte 0x000000002000000F   # valid rwx for VA 80807000  for covering UpdateDA
diff --git a/tests/coverage/vm64check.S b/tests/coverage/vm64check.S
deleted file mode 100644
index 0cc16ef8d..000000000
--- a/tests/coverage/vm64check.S
+++ /dev/null
@@ -1,174 +0,0 @@
-///////////////////////////////////////////
-// vm64check.S
-//
-// Written: David_Harris@hmc.edu 7 April 2023
-//
-// Purpose: vm64check coverage
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// Cover IMMU vm64check block by jumping to illegal virtual addresses
-// Need a nonstandard trap handler to deal with returns from theses jumps
-//    assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
- //   assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
- //   assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
-
-.section .text.init
-.global rvtest_entry_point
-
-rvtest_entry_point:
-    la sp, topofstack       # Initialize stack pointer (not used)
-
-    # Set up interrupts
-    la t0, trap_handler
-    csrw mtvec, t0      # Initialize MTVEC to trap_handler
-    # set up PMP so user and supervisor mode can access full address space
-    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
-    li t0, 0xFFFFFFFF
-    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
-
-    # SATP in non-39 mode
-    csrw satp, zero
-
-    // vm64check coverage
-check1:
-    // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
-    li t0, 0x00000001800F0000   # unimplemented memory with upper and lower all zero
-    la ra, check2
-    jalr t0
-
-check2:
-    li t0, 0xFFFFFFF1800F0000   # unimplemented memory with upper and lower all one
-    la ra, check3
-    jalr t0
-
-check3:
-    li t0, 0xFFF81001800F0000   # unimplemented memory with upper all one, lower mixed
-    la ra, check4
-    jalr t0
-
-check4:
-    li t0, 0x03001001800F0000   # unimplemented memory with upper mixed, lower mixed
-    la ra, check5
-    jalr t0
-
-check5:
-    li t0, 0x00001001800F0000   # unimplemented memory with upper all zero, lower mixed
-    la ra, check11
-    jalr t0
-
-check11:
-    # SATP in SV39 mode
-    li t0, 0x8000000000000000
-    csrw satp, t0
-
-    // check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
-    li t0, 0x00000001800F0000   # unimplemented memory with upper and lower all zero
-    la ra, check12
-    jalr t0
-
-check12:
-    li t0, 0xFFFFFFF1800F0000   # unimplemented memory with upper and lower all one
-    la ra, check13
-    jalr t0
-
-check13:
-    li t0, 0xFFF81001800F0000   # unimplemented memory with upper all one, lower mixed
-    la ra, check14
-    jalr t0
-
-check14:
-    li t0, 0x03001001800F0000   # unimplemented memory with upper mixed, lower mixed
-    la ra, check15
-    jalr t0
-
-check15:
-    li t0, 0x00001001800F0000   # unimplemented memory with upper all zero, lower mixed
-    la ra, check16
-    jalr t0
-
-check16:
-
-write_tohost:
-    la t1, tohost
-    li t0, 1            # 1 for success, 3 for failure
-    sd t0, 0(t1)        # send success code
-
-self_loop:
-    j self_loop         # wait
-
-.align 4                # trap handlers must be aligned to multiple of 4
-trap_handler:
-    csrw mepc, ra       # return to address in ra
-    mret
-
-.section .tohost
-tohost:                 # write to HTIF
-    .dword 0
-fromhost:
-    .dword 0
-
-
-# Initialize stack with room for 512 bytes
-.bss
-    .space 512
-topofstack:
-
-
-
-
-
-    j done
-
-    lw t1, 0(t0)
-    li t0, 0xFFFFFFFF80000000
-    lw t1, 0(t0)
-    li t1, 0xFFF8000080000000
-    lw t1, 0(t0)
-    li t1, 0x1000000080000000
-    lw t1, 0(t0)
-    li t1, 0x0000010080000000
-    lw t1, 0(t0)
-   li t0, 0x8000000000000000
-   csrw satp, t0   # SV39 mode
-    li t0, 0x0000000080000000
-    lw t1, 0(t0)
-    li t0, 0xFFFFFFFF80000000
-    lw t1, 0(t0)
-    li t1, 0xFFF8000080000000
-    lw t1, 0(t0)
-    li t1, 0x1000000080000000
-    lw t1, 0(t0)
-    li t1, 0x0000010080000000
-    lw t1, 0(t0)
-   li t0, 0x9000000000000000
-   csrw satp, t0   # SV48 mode
-    li t0, 0x0000000080000000
-    lw t1, 0(t0)
-    li t0, 0xFFFFFFFF80000000
-    lw t1, 0(t0)
-    li t1, 0xFFF8000080000000
-    lw t1, 0(t0)
-    li t1, 0x1000000080000000
-    lw t1, 0(t0)
-    li t1, 0x0000010080000000
-    lw t1, 0(t0)
-   li t0, 0x0000000000000000
-   csrw satp, t0   # disable virtual memory
diff --git a/tests/custom/lpddrtest/Makefile b/tests/custom/cacheTest/Makefile
similarity index 79%
rename from tests/custom/lpddrtest/Makefile
rename to tests/custom/cacheTest/Makefile
index 50d2aae07..f5ad40232 100644
--- a/tests/custom/lpddrtest/Makefile
+++ b/tests/custom/cacheTest/Makefile
@@ -1,13 +1,13 @@
-TARGETDIR	:= lpddr_test
+TARGETDIR	:= cacheTest
 TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
 ROOT		:= ..
 LIBRARY_DIRS	:= ${ROOT}/crt0
 LIBRARY_FILES	:= crt0
 
-MARCH           :=-march=rv64imfdczicbom
+MARCH           :=-march=rv64imfdc
 MABI            :=-mabi=lp64d
 LINKER          := ${ROOT}/linker8000-0000.x
-LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
 
 CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
 CC=riscv64-unknown-elf-gcc
diff --git a/tests/custom/cacheTest/header.h b/tests/custom/cacheTest/header.h
new file mode 100644
index 000000000..aab8973fd
--- /dev/null
+++ b/tests/custom/cacheTest/header.h
@@ -0,0 +1,12 @@
+#ifndef __header
+#define __header
+
+int fail();
+int simple_csrbr_test();
+int lbu_test();
+int icache_spill_test();
+void global_hist_0_space_test();
+void global_hist_1_space_test();
+void global_hist_2_space_test();
+void global_hist_3_space_test();
+#endif
diff --git a/tests/custom/cacheTest/main.c b/tests/custom/cacheTest/main.c
new file mode 100644
index 000000000..fccdaf0ed
--- /dev/null
+++ b/tests/custom/cacheTest/main.c
@@ -0,0 +1,12 @@
+#include "header.h"
+
+#define LIMIT 8192
+int main(int argc, char *argv[]){
+  long int array [LIMIT];
+  int index;
+  for(index = 0; index < LIMIT; index++) {
+    array[index] = index;
+  }
+  *argv = array;
+  return array[LIMIT-1] + argc;
+}
diff --git a/tests/custom/crt0/Makefile b/tests/custom/crt0/Makefile
index ec6d662cf..0b6a3af23 100644
--- a/tests/custom/crt0/Makefile
+++ b/tests/custom/crt0/Makefile
@@ -6,7 +6,7 @@ LIBRARY_FILES	:=
 
 MARCH           :=-march=rv64imfdc
 MABI            :=-mabi=lp64d
-LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
 LINKER          := ${ROOT}/linker.x
 
 AFLAGS =$(MARCH) $(MABI) -W
diff --git a/tests/custom/crt0/pre_main.c b/tests/custom/crt0/pre_main.c
index 3a5166558..fce61ffdf 100644
--- a/tests/custom/crt0/pre_main.c
+++ b/tests/custom/crt0/pre_main.c
@@ -2,8 +2,6 @@
 
 #include "pcnt_driver.h"
 
-extern int main(int argc, char *argv[]);
-
 int pre_main(int argc, char *argv[]) {
   long int bpmp0, brcnt0, bpmp1, brcnt1;
   long int bpmp_diff, brcnt_diff;
diff --git a/tests/custom/fpga-blink-led/Makefile b/tests/custom/fpga-blink-led/Makefile
new file mode 100644
index 000000000..df7544416
--- /dev/null
+++ b/tests/custom/fpga-blink-led/Makefile
@@ -0,0 +1,112 @@
+CEXT		:= c
+CPPEXT		:= cpp
+AEXT		:= s
+SEXT		:= S
+SRCEXT 		:= \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
+OBJEXT		:= o
+DEPEXT		:= d
+SRCDIR		:= .
+BUILDDIR	:= OBJ
+
+SOURCES		?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
+OBJECTS		:= $(SOURCES:.$(CEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(AEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(SEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
+OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
+
+TARGETDIR	:= bin
+TARGET		:= $(TARGETDIR)/blink-led
+ROOT		:= ..
+LIBRARY_DIRS	:= 
+LIBRARY_FILES	:=
+
+MARCH           :=-march=rv64imfdc
+MABI            :=-mabi=lp64d
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
+LINKER		:=$(ROOT)/linker1000.x
+
+
+AFLAGS =$(MARCH) $(MABI) -W
+CFLAGS =$(MARCH) $(MABI) -mcmodel=medany  -O2
+AS=riscv64-unknown-elf-as
+CC=riscv64-unknown-elf-gcc
+AR=riscv64-unknown-elf-ar
+
+
+#Default Make
+all: directories  $(TARGET).memfile
+
+#Remake
+remake: clean all
+
+#Make the Directories
+directories:
+	@mkdir -p $(TARGETDIR)
+	@mkdir -p $(BUILDDIR)
+
+clean:
+	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump 
+
+
+#Needed for building additional library projects
+ifdef LIBRARY_DIRS
+LIBS+=${LIBRARY_DIRS:%=-L%}  ${LIBRARY_FILES:%=-l%}
+INC+=${LIBRARY_DIRS:%=-I%}
+
+${LIBRARY_DIRS}: 
+	make -C $@ -j 1
+
+.PHONY: $(LIBRARY_DIRS) $(TARGET)
+endif
+
+
+#Pull in dependency info for *existing* .o files
+-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
+
+#Link
+$(TARGET): $(OBJECTS) $(LIBRARY_DIRS)
+	$(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER}
+
+
+#Compile
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT)
+	@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
+	@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
+	@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
+	@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
+
+# gcc won't output dependencies for assembly files for some reason
+# most asm files don't have dependencies so the echo will work for now.
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
+
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
+
+# C++
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT)
+	@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
+	@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
+	@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
+	@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
+
+# convert to hex
+$(TARGET).memfile: $(TARGET)
+	@echo 'Making object dump file.'
+	@riscv64-unknown-elf-objdump -D $< > $<.objdump
+	@echo 'Making memory file'
+	exe2memfile0.pl $<
+	extractFunctionRadix.sh $<.objdump
+	mkdir -p ../../imperas-riscv-tests/work/rv64BP/
+	cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
diff --git a/tests/custom/fpga-blink-led/blink-led.s b/tests/custom/fpga-blink-led/blink-led.s
new file mode 100644
index 000000000..5d4d48ceb
--- /dev/null
+++ b/tests/custom/fpga-blink-led/blink-led.s
@@ -0,0 +1,86 @@
+PERIOD = 22000000
+#PERIOD = 100
+
+.section .init
+.global _start
+.type _start, @function
+
+		
+_start:
+	  # Initialize global pointer
+	.option push
+	.option norelax
+	1:auipc gp, %pcrel_hi(__global_pointer$)
+	addi  gp, gp, %pcrel_lo(1b)
+	.option pop
+	
+	li x1, 0
+	li x2, 0
+	li x4, 0
+	li x5, 0
+	li x6, 0
+	li x7, 0
+	li x8, 0
+	li x9, 0
+	li x10, 0
+	li x11, 0
+	li x12, 0
+	li x13, 0
+	li x14, 0
+	li x15, 0
+	li x16, 0
+	li x17, 0
+	li x18, 0
+	li x19, 0
+	li x20, 0
+	li x21, 0
+	li x22, 0
+	li x23, 0
+	li x24, 0
+	li x25, 0
+	li x26, 0
+	li x27, 0
+	li x28, 0
+	li x29, 0
+	li x30, 0
+	li x31, 0
+
+	# write to gpio
+	li	x2, 0xFF
+	la	x3, 0x10060000
+
+	# +8 is output enable
+	# +C is output value
+
+	addi	x4, x3, 8
+	addi	x5, x3, 0xC
+
+	# write initial value of 0xFF to GPO
+	sw	x2, 0x0(x5)
+	# enable output
+	sw	x2, 0x0(x4)
+
+loop:
+
+	# delay
+	li	x20, PERIOD/2
+delay1:	
+	addi	x20, x20, -1
+	bge	x20, x0, delay1
+
+	# clear GPO
+	sw	x0, 0x0(x5)
+
+	# delay
+	li	x20, PERIOD/2
+delay2:	
+	addi	x20, x20, -1
+	bge	x20, x0, delay2
+
+	# write GPO
+	sw	x2, 0x0(x5)
+
+	j	loop
+
+
+
diff --git a/tests/custom/fpga-test-dram/Makefile b/tests/custom/fpga-test-dram/Makefile
new file mode 100644
index 000000000..df7544416
--- /dev/null
+++ b/tests/custom/fpga-test-dram/Makefile
@@ -0,0 +1,112 @@
+CEXT		:= c
+CPPEXT		:= cpp
+AEXT		:= s
+SEXT		:= S
+SRCEXT 		:= \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
+OBJEXT		:= o
+DEPEXT		:= d
+SRCDIR		:= .
+BUILDDIR	:= OBJ
+
+SOURCES		?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
+OBJECTS		:= $(SOURCES:.$(CEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(AEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(SEXT)=.$(OBJEXT))
+OBJECTS		:= $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
+OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
+
+TARGETDIR	:= bin
+TARGET		:= $(TARGETDIR)/blink-led
+ROOT		:= ..
+LIBRARY_DIRS	:= 
+LIBRARY_FILES	:=
+
+MARCH           :=-march=rv64imfdc
+MABI            :=-mabi=lp64d
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
+LINKER		:=$(ROOT)/linker1000.x
+
+
+AFLAGS =$(MARCH) $(MABI) -W
+CFLAGS =$(MARCH) $(MABI) -mcmodel=medany  -O2
+AS=riscv64-unknown-elf-as
+CC=riscv64-unknown-elf-gcc
+AR=riscv64-unknown-elf-ar
+
+
+#Default Make
+all: directories  $(TARGET).memfile
+
+#Remake
+remake: clean all
+
+#Make the Directories
+directories:
+	@mkdir -p $(TARGETDIR)
+	@mkdir -p $(BUILDDIR)
+
+clean:
+	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump 
+
+
+#Needed for building additional library projects
+ifdef LIBRARY_DIRS
+LIBS+=${LIBRARY_DIRS:%=-L%}  ${LIBRARY_FILES:%=-l%}
+INC+=${LIBRARY_DIRS:%=-I%}
+
+${LIBRARY_DIRS}: 
+	make -C $@ -j 1
+
+.PHONY: $(LIBRARY_DIRS) $(TARGET)
+endif
+
+
+#Pull in dependency info for *existing* .o files
+-include $(OBJECTS:.$(OBJEXT)=.$(DEPEXT))
+
+#Link
+$(TARGET): $(OBJECTS) $(LIBRARY_DIRS)
+	$(CC) $(LINK_FLAGS) -g -o $(TARGET) $(OBJECTS) ${LIBS} -T ${LINKER}
+
+
+#Compile
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CEXT) > $(BUILDDIR)/$*.$(DEPEXT)
+	@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
+	@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
+	@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
+	@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
+
+# gcc won't output dependencies for assembly files for some reason
+# most asm files don't have dependencies so the echo will work for now.
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(AEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
+
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(SEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@echo $@: $< > $(BUILDDIR)/$*.$(DEPEXT)
+
+# C++
+$(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
+	@mkdir -p $(dir $@)
+	$(CC) $(CFLAGS) $(INC) -c -o $@ $< > $(BUILDDIR)/$*.list
+	@$(CC) $(CFLAGS) $(INC) -MM $(SRCDIR)/$*.$(CPPEXT) > $(BUILDDIR)/$*.$(DEPEXT)
+	@cp -f $(BUILDDIR)/$*.$(DEPEXT) $(BUILDDIR)/$*.$(DEPEXT).tmp
+	@sed -e 's|.*:|$(BUILDDIR)/$*.$(OBJEXT):|' < $(BUILDDIR)/$*.$(DEPEXT).tmp > $(BUILDDIR)/$*.$(DEPEXT)
+	@sed -e 's/.*://' -e 's/\\$$//' < $(BUILDDIR)/$*.$(DEPEXT).tmp | fmt -1 | sed -e 's/^ *//' -e 's/$$/:/' >> $(BUILDDIR)/$*.$(DEPEXT)
+	@rm -f $(BUILDDIR)/$*.$(DEPEXT).tmp
+
+# convert to hex
+$(TARGET).memfile: $(TARGET)
+	@echo 'Making object dump file.'
+	@riscv64-unknown-elf-objdump -D $< > $<.objdump
+	@echo 'Making memory file'
+	exe2memfile0.pl $<
+	extractFunctionRadix.sh $<.objdump
+	mkdir -p ../../imperas-riscv-tests/work/rv64BP/
+	cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
diff --git a/tests/custom/fpga-test-dram/blink-led.s b/tests/custom/fpga-test-dram/blink-led.s
new file mode 100644
index 000000000..9e524b2e1
--- /dev/null
+++ b/tests/custom/fpga-test-dram/blink-led.s
@@ -0,0 +1,130 @@
+PERIOD = 22000000
+#PERIOD = 100
+
+.section .init
+.global _start
+.type _start, @function
+
+		
+_start:
+	  # Initialize global pointer
+	.option push
+	.option norelax
+	1:auipc gp, %pcrel_hi(__global_pointer$)
+	addi  gp, gp, %pcrel_lo(1b)
+	.option pop
+	
+	li x1, 0
+	li x2, 0
+	li x4, 0
+	li x5, 0
+	li x6, 0
+	li x7, 0
+	li x8, 0
+	li x9, 0
+	li x10, 0
+	li x11, 0
+	li x12, 0
+	li x13, 0
+	li x14, 0
+	li x15, 0
+	li x16, 0
+	li x17, 0
+	li x18, 0
+	li x19, 0
+	li x20, 0
+	li x21, 0
+	li x22, 0
+	li x23, 0
+	li x24, 0
+	li x25, 0
+	li x26, 0
+	li x27, 0
+	li x28, 0
+	li x29, 0
+	li x30, 0
+	li x31, 0
+
+	# write to gpio
+	li	x2, 0xFF
+	la	x3, 0x10060000
+
+	# +8 is output enable
+	# +C is output value
+
+	addi	x4, x3, 8
+	addi	x5, x3, 0xC
+
+	# write initial value of 0xFF to GPO
+	sw	x2, 0x0(x5)
+	# enable output
+	sw	x2, 0x0(x4)
+
+	# before jumping to led loop
+	# lets try writting to dram.
+
+	li	x21, 0
+	li	x23, 4096*16    # 64KB of data
+
+	li	x22, 0x80000000
+	li	x24, 0
+
+write_loop:
+	add	x25, x22, x24
+	sw	x24, 0(x25)
+	addi	x24, x24, 4
+	blt	x24, x23, write_loop
+
+	li	x24, 0
+read_loop:
+	add	x25, x22, x24
+	lw	x21, 0(x25)
+
+	# check value
+	bne	x21, x24, fail_loop
+
+	addi	x24, x24, 4
+	
+	#
+	blt	x24, x23, read_loop
+
+	
+
+loop:
+
+	# delay
+	li	x20, PERIOD
+delay1:	
+	addi	x20, x20, -1
+	bge	x20, x0, delay1
+
+	# new GPO
+	addi	x2, x2, 1
+	sw	x2, 0x0(x5)
+
+	j	loop
+
+
+fail_loop:
+
+	# delay
+	li	x20, PERIOD/20
+fail_delay1:	
+	addi	x20, x20, -1
+	bge	x20, x0, fail_delay1
+
+	# clear GPO
+	sw	x0, 0x0(x5)
+
+	# delay
+	li	x20, PERIOD/20
+fail_delay2:	
+	addi	x20, x20, -1
+	bge	x20, x0, fail_delay2
+
+	# write GPO
+	sw	x2, 0x0(x5)
+
+	j	fail_loop
+
+
diff --git a/tests/custom/spitest/Makefile b/tests/custom/fpga-test-sdc/Makefile
similarity index 97%
rename from tests/custom/spitest/Makefile
rename to tests/custom/fpga-test-sdc/Makefile
index d8aa42567..32affba87 100644
--- a/tests/custom/spitest/Makefile
+++ b/tests/custom/fpga-test-sdc/Makefile
@@ -16,7 +16,7 @@ OBJECTS		:= $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
 OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
 
 TARGETDIR	:= bin
-TARGET		:= $(TARGETDIR)/spitest.elf
+TARGET		:= $(TARGETDIR)/fpga-test-sdc
 ROOT		:= ..
 LIBRARY_DIRS	:= 
 LIBRARY_FILES	:=
@@ -24,7 +24,7 @@ LIBRARY_FILES	:=
 MARCH           :=-march=rv64imfdc
 MABI            :=-mabi=lp64d
 LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
-LINKER		:=$(ROOT)/linker8000-0000.x
+LINKER		:=$(ROOT)/linker1000.x
 
 
 AFLAGS =$(MARCH) $(MABI) -W
@@ -55,7 +55,7 @@ LIBS+=${LIBRARY_DIRS:%=-L%}  ${LIBRARY_FILES:%=-l%}
 INC+=${LIBRARY_DIRS:%=-I%}
 
 ${LIBRARY_DIRS}: 
-	$(MAKE) -C $@ -j 1
+	make -C $@ -j 1
 
 .PHONY: $(LIBRARY_DIRS) $(TARGET)
 endif
diff --git a/fpga/zsbl/bios.S b/tests/custom/fpga-test-sdc/bios.s
similarity index 84%
rename from fpga/zsbl/bios.S
rename to tests/custom/fpga-test-sdc/bios.s
index a7283b38d..8057a277d 100644
--- a/fpga/zsbl/bios.S
+++ b/tests/custom/fpga-test-sdc/bios.s
@@ -1,6 +1,5 @@
-#include "system.h"
-
-PERIOD = (SYSTEMCLOCK / 2)
+PERIOD = 11000000
+#PERIOD = 20
 
 .section .init
 .global _start
@@ -48,10 +47,10 @@ _start:
 
 
 	# set the stack pointer to the top of memory - 8 bytes (pointer size)
-	li sp, (EXT_MEM_END - 8)
+	li sp, 0x87FFFFF8
 
 	li a0, 0x00000000
-	li a1, EXT_MEM_BASE
+	li a1, 0x80000000
 	#li a2, 128*1024*1024/512 # copy 128MB
 	li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
 	#li a2, 800 # copy 400KB
@@ -88,10 +87,10 @@ delay2:
 	# jump to the copied contents of the sd card.
 
 jumpToLinux:	
-	csrrs	a0, 0xF14, x0   # copy hart ID to a0
-	li	a1, FDT_ADDRESS  # This is the device tree address
+	csrrs	a0, 0xF14, x0   # copy hard ID to a0
+	li	a1, 0x87000000  # end of memory? not 100% sure on this but it's 112MB
 	la	a2, end_of_bios
-	li	t0, EXT_MEM_BASE  # start of code
+	li	t0, 0x80000000  # start of code
 	
 	jalr	x0, t0, 0
 
diff --git a/tests/custom/fpga-test-sdc/copyFlash.c b/tests/custom/fpga-test-sdc/copyFlash.c
new file mode 100644
index 000000000..4165fe21c
--- /dev/null
+++ b/tests/custom/fpga-test-sdc/copyFlash.c
@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// copyFlash.sv
+//
+// Written: Ross Thompson September 25, 2021
+// Modified: 
+//
+// Purpose: copies flash card into memory
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "sdcDriver.h"
+
+void copyFlash(long int blockAddr, long int * Dst, int numBlocks) {
+
+  setSDCCLK(4); // must be even, 1 gives no division.
+  waitInitSDC();
+
+  int index;
+
+  for(index = 0; index < numBlocks; index++) {
+    copySDC512(blockAddr+(index*512), Dst+(index*512/8));
+  }
+  
+    
+}
diff --git a/tests/custom/fpga-test-sdc/old.asm b/tests/custom/fpga-test-sdc/old.asm
new file mode 100644
index 000000000..6137fae7e
--- /dev/null
+++ b/tests/custom/fpga-test-sdc/old.asm
@@ -0,0 +1,154 @@
+	# start by writting the clock divider to 4 setting SDC to 25MHz
+	la	x3, 0x12100
+	li	x4, -4
+	sw	x4, 0x0(x3)
+
+	# start by writting the clock divider to 1 setting SDC to 100MHZ
+	la	x3, 0x12100
+	li	x4, 1
+	sw	x4, 0x0(x3)
+
+
+	# wait until the SDC is done with initialization
+	li	x4, 0x1
+wait_sdc_done_init:	
+	lw	x5, 4(x3)
+	and	x5, x5, x4
+	bne	x5, x4, wait_sdc_done_init
+
+	# now that it is done lets setup for a read
+	li	x6, 0x20000000
+	sd	x6, 0x10(x3)    # write address register
+
+	# send read by writting to command register
+	li	x7, 0x4
+	sw	x7, 0x8(x3)
+
+	li 	x4, 0x2
+wait_sdc_done_read:	
+	lw	x5, 4(x3)
+	and	x5, x5, x4
+	beq	x5, x4, wait_sdc_done_read
+
+	# copy data from mailbox
+	li	x11, 0x80000000
+	li	x9, 0
+copy_sdc:	
+	li 	x8, 512/8
+	ld	x10, 0x18(x3)  # read the mailbox
+	sd	x10, 0x0(x11)  # write to dram
+	addi	x9, x9, 1
+	addi	x11, x11, 8
+	blt	x9, x8, copy_sdc
+
+	# second read of sdc
+	# now that it is done lets setup for a read
+	li	x6, 0x20000200
+	sd	x6, 0x10(x3)    # write address register
+
+	# send read by writting to command register
+	li	x7, 0x4
+	sw	x7, 0x8(x3)
+
+	li 	x4, 0x2
+wait_sdc_done_read2:	
+	lw	x5, 4(x3)
+	and	x5, x5, x4
+	beq	x5, x4, wait_sdc_done_read2
+
+	# copy data from mailbox
+	li	x11, 0x80000200
+	li	x9, 0
+copy_sdc2:	
+	li 	x8, 512/8
+	ld	x10, 0x18(x3)  # read the mailbox
+	sd	x10, 0x0(x11)  # write to dram
+	addi	x9, x9, 1
+	addi	x11, x11, 8
+	blt	x9, x8, copy_sdc2
+	
+
+
+	# write to gpio
+	li	x2, 0xFF
+	la	x3, 0x10060000
+
+	# +8 is output enable
+	# +C is output value
+
+	addi	x4, x3, 8
+	addi	x5, x3, 0xC
+
+	# write initial value of 0xFF to GPO
+	sw	x2, 0x0(x5)
+	# enable output
+	sw	x2, 0x0(x4)
+
+	# before jumping to led loop
+	# lets try writting to dram.
+
+	li	x21, 0
+	li	x23, 4096*16    # 64KB of data
+
+	li	x22, 0x80000000
+	li	x24, 0
+
+write_loop:
+	add	x25, x22, x24
+	sw	x24, 0(x25)
+	addi	x24, x24, 4
+	blt	x24, x23, write_loop
+
+	li	x24, 0
+read_loop:
+	add	x25, x22, x24
+	lw	x21, 0(x25)
+
+	# check value
+	bne	x21, x24, fail_loop
+
+	addi	x24, x24, 4
+	
+	#
+	blt	x24, x23, read_loop
+
+	
+
+loop:
+
+	# delay
+	li	x20, PERIOD
+delay1:	
+	addi	x20, x20, -1
+	bge	x20, x0, delay1
+
+	# new GPO
+	addi	x2, x2, 1
+	sw	x2, 0x0(x5)
+
+	j	loop
+
+
+fail_loop:
+
+	# delay
+	li	x20, PERIOD/20
+fail_delay1:	
+	addi	x20, x20, -1
+	bge	x20, x0, fail_delay1
+
+	# clear GPO
+	sw	x0, 0x0(x5)
+
+	# delay
+	li	x20, PERIOD/20
+fail_delay2:	
+	addi	x20, x20, -1
+	bge	x20, x0, fail_delay2
+
+	# write GPO
+	sw	x2, 0x0(x5)
+
+	j	fail_loop
+
+
diff --git a/tests/custom/fpga-test-sdc/sdcDriver.c b/tests/custom/fpga-test-sdc/sdcDriver.c
new file mode 100644
index 000000000..edbe0677d
--- /dev/null
+++ b/tests/custom/fpga-test-sdc/sdcDriver.c
@@ -0,0 +1,69 @@
+///////////////////////////////////////////
+// SDC.sv
+//
+// Written: Ross Thompson September 25, 2021
+// Modified: 
+//
+// Purpose: driver for sdc reader.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+
+#include "sdcDriver.h"
+
+#define SDC_MAIL_BOX 0x12100
+
+void copySDC512(long int blockAddr, long int * Dst) {
+
+  waitInitSDC();
+
+  volatile long int * mailBoxAddr;
+  volatile int * mailBoxCmd;
+  volatile int * mailBoxStatus;
+  volatile long int * mailBoxReadData;
+  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);  
+  mailBoxCmd = (int *) (SDC_MAIL_BOX + 0x8);
+  mailBoxAddr = (long int *) (SDC_MAIL_BOX + 0x10);
+  mailBoxReadData = (long int *) (SDC_MAIL_BOX + 0x18);  
+  
+  // write the SDC address register with the blockAddr
+  *mailBoxAddr = blockAddr;
+  *mailBoxCmd = 0x4;
+
+  // wait until the mailbox has valid data
+  // this occurs when status[1] = 0
+  while((*mailBoxStatus & 0x2) == 0x2);
+
+  int index;
+  for(index = 0; index < 512/8; index++) {
+    Dst[index] = *mailBoxReadData;
+  }
+}
+
+volatile void waitInitSDC(){
+  volatile int * mailBoxStatus;
+  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);
+  while((*mailBoxStatus & 0x1) != 0x1);
+}
+
+void setSDCCLK(int divider){
+  divider = (1 - (divider >> 1));
+  volatile int * mailBoxCLK;
+  mailBoxCLK = (int *) (SDC_MAIL_BOX + 0x0);
+  *mailBoxCLK = divider;
+}
diff --git a/tests/custom/fpga-test-sdc/sdcDriver.h b/tests/custom/fpga-test-sdc/sdcDriver.h
new file mode 100644
index 000000000..7876aeda1
--- /dev/null
+++ b/tests/custom/fpga-test-sdc/sdcDriver.h
@@ -0,0 +1,9 @@
+#ifndef __SDCDRIVER_H
+#define __SDCDRIVER_H
+
+
+void copySDC512(long int, long int *);
+volatile void waitInitSDC();
+void setSDCCLK(int);
+
+#endif
diff --git a/tests/custom/spitest/start.s b/tests/custom/fpga-test-sdc/test-sdc.asm
similarity index 63%
rename from tests/custom/spitest/start.s
rename to tests/custom/fpga-test-sdc/test-sdc.asm
index 57f66ce79..4bc98a27f 100644
--- a/tests/custom/spitest/start.s
+++ b/tests/custom/fpga-test-sdc/test-sdc.asm
@@ -1,7 +1,11 @@
+#PERIOD = 22000000
+PERIOD = 20
+
 .section .init
 .global _start
 .type _start, @function
 
+		
 _start:
 	  # Initialize global pointer
 	.option push
@@ -42,11 +46,42 @@ _start:
 	li x31, 0
 
 
-
 	# set the stack pointer to the top of memory - 8 bytes (pointer size)
 	li sp, 0x87FFFFF8
 
-	jal ra, main
+	li a0, 0x20000000
+	li a1, 0x80000000
+	li a2, 2
+	jal ra, copyFlash
+	
+
+	# now toggle led so we know the copy completed.
+
+	# write to gpio
+	li	t2, 0xFF
+	la	t3, 0x1001200C
+	li	t4, 5
+
+loop:
+
+	# delay
+	li	t0, PERIOD/2
+delay1:	
+	addi	t0, t0, -1
+	bge	t0, x0, delay1
+	sw	t2, 0x0(t3)
+
+	li	t0, PERIOD/2
+delay2:	
+	addi	t0, t0, -1
+	bge	t0, x0, delay2
+	sw	x0, 0x0(t3)
+
+	addi	t4, t4, -1
+	bgt	t4, x0, loop
+
+	
+
 	jal ra, _halt
 
 .section .text
@@ -57,3 +92,6 @@ _halt:
 	li a0, 0
 	ecall
 	j _halt
+	
+
+
diff --git a/tests/custom/james_mm/Makefile b/tests/custom/james_mm/Makefile
new file mode 100644
index 000000000..d13a3ad8d
--- /dev/null
+++ b/tests/custom/james_mm/Makefile
@@ -0,0 +1,19 @@
+TARGETDIR	:= mmm
+TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
+ROOT		:= ..
+LIBRARY_DIRS	:= ${ROOT}/crt0
+LIBRARY_FILES	:= crt0
+
+MARCH           :=-march=rv64imfdc
+MABI            :=-mabi=lp64d
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
+LINKER          := ${ROOT}/linker8000-0000.x
+
+CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
+
+CC=riscv64-unknown-elf-gcc
+DA=riscv64-unknown-elf-objdump -d
+
+
+include $(ROOT)/makefile.inc
+
diff --git a/tests/custom/james_mm/james_mm.c b/tests/custom/james_mm/james_mm.c
new file mode 100644
index 000000000..fa5366e34
--- /dev/null
+++ b/tests/custom/james_mm/james_mm.c
@@ -0,0 +1,235 @@
+#include <stdio.h>
+
+typedef double Float;
+
+Float C[100][100];
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+{ 1.90092051029205322265625, 1.97075498104095458984375, 1.90136587619781494140625, 1.1271336078643798828125, 1.1307432651519775390625, 1.20074498653411865234375, 1.04964983463287353515625, 1.5069148540496826171875, 1.54414331912994384765625, 1.4015419483184814453125, 1.31514680385589599609375, 1.04354953765869140625, 1.81082141399383544921875, 1.16905486583709716796875, 1.38940799236297607421875, 1.06475818157196044921875, 1.4000384807586669921875, 1.92805016040802001953125, 1.8690140247344970703125, 1.80133783817291259765625, 1.47905385494232177734375, 1.2680895328521728515625, 1.5290119647979736328125, 1.09809887409210205078125, 1.5615622997283935546875, 1.02946674823760986328125, 1.3463535308837890625, 1.8748028278350830078125, 1.90613162517547607421875, 1.1391456127166748046875, 1.273332118988037109375, 1.3371002674102783203125, 1.6646401882171630859375, 1.196697235107421875, 1.7610204219818115234375, 1.9374675750732421875, 1.780714511871337890625, 1.81023800373077392578125, 1.03270804882049560546875, 1.08614480495452880859375, 1.63816630840301513671875, 1.68236637115478515625, 1.10733854770660400390625, 1.61207354068756103515625, 1.459430694580078125, 1.446100711822509765625, 1.57294762134552001953125, 1.97383368015289306640625, 1.45400321483612060546875, 1.25081717967987060546875, 1.11010015010833740234375, 1.22058141231536865234375, 1.716877460479736328125, 1.098186492919921875, 1.76532781124114990234375, 1.7029864788055419921875, 1.87698268890380859375, 1.9281117916107177734375, 1.97456657886505126953125, 1.5341701507568359375, 1.49562084674835205078125, 1.45466649532318115234375, 1.3365943431854248046875, 1.8006420135498046875, 1.21490478515625, 1.7520310878753662109375, 1.13646793365478515625, 1.52323782444000244140625, 1.65619528293609619140625, 1.5904309749603271484375, 1.618961334228515625, 1.36805737018585205078125, 1.068538665771484375, 1.52207434177398681640625, 1.0120027065277099609375, 1.10740125179290771484375, 1.7271044254302978515625, 1.7170889377593994140625, 1.3001120090484619140625, 1.8307087421417236328125, 1.08162224292755126953125, 1.549459934234619140625, 1.74783861637115478515625, 1.90549564361572265625, 1.6548202037811279296875, 1.93296778202056884765625, 1.17319834232330322265625, 1.688291072845458984375, 1.69086182117462158203125, 1.407124996185302734375, 1.97111165523529052734375, 1.98557531833648681640625, 1.5537836551666259765625, 1.97311413288116455078125, 1.88684070110321044921875, 1.26471769809722900390625, 1.87593281269073486328125, 1.67972505092620849609375, 1.53942692279815673828125, 1.61491334438323974609375},
+{ 1.959292888641357421875, 1.6951286792755126953125, 1.4581210613250732421875, 1.9094793796539306640625, 1.71363484859466552734375, 1.29085826873779296875, 1.01000118255615234375, 1.06306111812591552734375, 1.14998805522918701171875, 1.207620143890380859375, 1.49085235595703125, 1.1071140766143798828125, 1.3669474124908447265625, 1.7939479351043701171875, 1.0865495204925537109375, 1.49210059642791748046875, 1.69040238857269287109375, 1.1393420696258544921875, 1.65948116779327392578125, 1.57741868495941162109375, 1.75947487354278564453125, 1.097707271575927734375, 1.20948731899261474609375, 1.029839038848876953125, 1.3624570369720458984375, 1.06079018115997314453125, 1.08479630947113037109375, 1.97194325923919677734375, 1.02274811267852783203125, 1.48161637783050537109375, 1.942962646484375, 1.88056087493896484375, 1.33479225635528564453125, 1.14792859554290771484375, 1.461804866790771484375, 1.23520696163177490234375, 1.0500164031982421875, 1.20562374591827392578125, 1.8003423213958740234375, 1.91651976108551025390625, 1.91276705265045166015625, 1.93219053745269775390625, 1.80973303318023681640625, 1.354697704315185546875, 1.24624812602996826171875, 1.2601470947265625, 1.99421155452728271484375, 1.42793762683868408203125, 1.28845882415771484375, 1.0504779815673828125, 1.22202575206756591796875, 1.110871791839599609375, 1.27813041210174560546875, 1.1160724163055419921875, 1.186374664306640625, 1.87300550937652587890625, 1.290664196014404296875, 1.9951612949371337890625, 1.6163463592529296875, 1.827154636383056640625, 1.8240687847137451171875, 1.474754810333251953125, 1.2378547191619873046875, 1.6278831958770751953125, 1.13489806652069091796875, 1.86408007144927978515625, 1.48457729816436767578125, 1.11994040012359619140625, 1.3241879940032958984375, 1.01801812648773193359375, 1.95889317989349365234375, 1.7366988658905029296875, 1.1733944416046142578125, 1.11054217815399169921875, 1.64281976222991943359375, 1.64859163761138916015625, 1.73033106327056884765625, 1.15815460681915283203125, 1.85895073413848876953125, 1.6615498065948486328125, 1.6451060771942138671875, 1.29332458972930908203125, 1.981393337249755859375, 1.8654401302337646484375, 1.256060123443603515625, 1.78792560100555419921875, 1.8967063426971435546875, 1.03250205516815185546875, 1.42570412158966064453125, 1.826673030853271484375, 1.2148368358612060546875, 1.7657859325408935546875, 1.126656055450439453125, 1.0305612087249755859375, 1.23005807399749755859375, 1.39759004116058349609375, 1.777578830718994140625, 1.7303016185760498046875, 1.63190734386444091796875, 1.6378982067108154296875} 
+};
+
+
+
+
+void main() {
+
+  int k;
+  int i;
+  int j;
+  int NCB;
+  int NRA;
+  int NCA;
+
+  NCA = 100;
+  NRA = 100;
+  NCB = 100; 
+
+  for (k=0; k < NCB; k++)
+    for (i=0; i < NRA; i++) {
+      C[i][k] = 0.0;
+      for (j=0; j < NCA; j++) {
+	C[i][k] = C[i][k] + A[i][j] * B[j][k];
+      }
+    }
+}
+
+
diff --git a/tests/custom/linker.x b/tests/custom/linker.x
index 95618b722..f448109cc 100644
--- a/tests/custom/linker.x
+++ b/tests/custom/linker.x
@@ -2,6 +2,7 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
 	      "elf64-littleriscv")
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
+SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
diff --git a/tests/custom/linker1000.x b/tests/custom/linker1000.x
index b479e73dd..4156c6571 100644
--- a/tests/custom/linker1000.x
+++ b/tests/custom/linker1000.x
@@ -2,6 +2,7 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
 	      "elf64-littleriscv")
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
+SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
@@ -71,7 +72,6 @@ SECTIONS
   PROVIDE (__etext = .);
   PROVIDE (_etext = .);
   PROVIDE (etext = .);
-  . = 0x0000000000002000;
   .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
   .rodata1        : { *(.rodata1) }
   .sdata2         :
diff --git a/tests/custom/linker8000-0000.x b/tests/custom/linker8000-0000.x
index 3635f8d27..548c9d45c 100644
--- a/tests/custom/linker8000-0000.x
+++ b/tests/custom/linker8000-0000.x
@@ -2,6 +2,7 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
 	      "elf64-littleriscv")
 OUTPUT_ARCH(riscv)
 ENTRY(_start)
+SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
diff --git a/tests/custom/lpddrtest/header.h b/tests/custom/lpddrtest/header.h
deleted file mode 100644
index 7e83cb22d..000000000
--- a/tests/custom/lpddrtest/header.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef __header
-#define __header
-
-void lpddr_test();
-#endif
diff --git a/tests/custom/lpddrtest/lpddr_test.s b/tests/custom/lpddrtest/lpddr_test.s
deleted file mode 100644
index a77d9081f..000000000
--- a/tests/custom/lpddrtest/lpddr_test.s
+++ /dev/null
@@ -1,29 +0,0 @@
-.section .text
-.globl lpddr_test
-.type lpddr_test, @function
-lpddr_test:
-	li t1, 0x90000000
-        addi t5, t1, 0
-	li t2, 0xAABBCCDD00112233
-
-        li t3, 10
-        li t4, 0
-loop_write:     
-        beq t4, t3, done_write
-        sd t2, 0(t5)
-        addi t5, t5, 8
-        addi t4, t4, 1
-        j loop_write
-done_write:   
-	
-        li t4, 0
-        addi t5, t1, 0
-loop_read:     
-        beq t4, t3, done_read
-        ld t6, 0(t5)
-        addi t5, t5, 8
-        addi t4, t4, 1
-        j loop_read
-done_read:      
-	ret
-	
diff --git a/tests/custom/lpddrtest/main.c b/tests/custom/lpddrtest/main.c
deleted file mode 100644
index feafa5f75..000000000
--- a/tests/custom/lpddrtest/main.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "header.h"
-
-int main(){
-  lpddr_test();  
-  return 0;
-}
diff --git a/tests/custom/mibench_qsort/LICENSE b/tests/custom/mibench_qsort/LICENSE
new file mode 100644
index 000000000..6016daa7c
--- /dev/null
+++ b/tests/custom/mibench_qsort/LICENSE
@@ -0,0 +1,3 @@
+Matt wrote this using STL. 
+
+It is GPL'ed.
diff --git a/tests/custom/mibench_qsort/Makefile b/tests/custom/mibench_qsort/Makefile
new file mode 100644
index 000000000..a738265da
--- /dev/null
+++ b/tests/custom/mibench_qsort/Makefile
@@ -0,0 +1,20 @@
+TARGETDIR	:= qsort
+TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
+ROOT		:= ..
+LIBRARY_DIRS	:= ${ROOT}/crt0
+LIBRARY_FILES	:= crt0
+
+MARCH           :=-march=rv64ic
+MABI            :=-mabi=lp64
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
+LINKER          := ${ROOT}/linker8000-0000.x
+
+CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
+
+CC=riscv64-unknown-elf-gcc
+DA=riscv64-unknown-elf-objdump -d
+
+
+include $(ROOT)/makefile.inc
+
+
diff --git a/tests/custom/mibench_qsort/qsort_small.c b/tests/custom/mibench_qsort/qsort_small.c
new file mode 100644
index 000000000..1b28eea4c
--- /dev/null
+++ b/tests/custom/mibench_qsort/qsort_small.c
@@ -0,0 +1,10038 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#define UNLIMIT
+#define MAXARRAY 11000 /* this number, if too large, will cause a seg. fault!! */
+
+struct myStringStruct {
+  char qstring[128];
+};
+
+struct myStringStruct array[MAXARRAY];
+
+int compare(const void *elem1, const void *elem2)
+{
+  int result;
+  
+  result = strcmp((*((struct myStringStruct *)elem1)).qstring, (*((struct myStringStruct *)elem2)).qstring);
+
+  return (result < 0) ? 1 : ((result == 0) ? 0 : -1);
+}
+
+
+int
+main(int argc, char *argv[]) {
+  FILE *fp;
+  int i,count=0;
+
+strcpy(array[count++].qstring, "Kurt");
+strcpy(array[count++].qstring, "Vonneguts");
+strcpy(array[count++].qstring, "Commencement");
+strcpy(array[count++].qstring, "Address");
+strcpy(array[count++].qstring, "at");
+strcpy(array[count++].qstring, "MIT");
+strcpy(array[count++].qstring, "Ladies");
+strcpy(array[count++].qstring, "and");
+strcpy(array[count++].qstring, "gentlemen");
+strcpy(array[count++].qstring, "of");
+strcpy(array[count++].qstring, "the");
+strcpy(array[count++].qstring, "class");
+strcpy(array[count++].qstring, "of");
+strcpy(array[count++].qstring, "97");
+strcpy(array[count++].qstring, "Wear");
+strcpy(array[count++].qstring, "sunscreen");
+strcpy(array[count++].qstring, "If");
+strcpy(array[count++].qstring, "I");
+strcpy(array[count++].qstring, "could");
+strcpy(array[count++].qstring, "offer");
+strcpy(array[count++].qstring, "you");
+strcpy(array[count++].qstring, "only");
+strcpy(array[count++].qstring, "one");
+strcpy(array[count++].qstring, "tip");
+strcpy(array[count++].qstring, "for");
+strcpy(array[count++].qstring, "the");
+strcpy(array[count++].qstring, "future");
+strcpy(array[count++].qstring, "sunscreen");
+strcpy(array[count++].qstring, "would");
+strcpy(array[count++].qstring, "be");
+strcpy(array[count++].qstring, "it");
+strcpy(array[count++].qstring, "The");
+strcpy(array[count++].qstring, "longterm");
+strcpy(array[count++].qstring, "benefits");
+strcpy(array[count++].qstring, "of");
+strcpy(array[count++].qstring, "sunscreen");
+strcpy(array[count++].qstring, "have");
+strcpy(array[count++].qstring, "been");
+strcpy(array[count++].qstring, "proved");
+strcpy(array[count++].qstring, "by");
+strcpy(array[count++].qstring, "scientists");
+strcpy(array[count++].qstring, "whereas");
+strcpy(array[count++].qstring, "the");
+strcpy(array[count++].qstring, "rest");
+strcpy(array[count++].qstring, "of");
+strcpy(array[count++].qstring, "my");
+strcpy(array[count++].qstring, "advice");
+strcpy(array[count++].qstring, "has");
+strcpy(array[count++].qstring, "no");
+strcpy(array[count++].qstring, "basis");
+strcpy(array[count++].qstring, "more");
+strcpy(array[count++].qstring, "reliable");
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+strcpy(array[count++].qstring, "magazines");
+strcpy(array[count++].qstring, "They");
+strcpy(array[count++].qstring, "will");
+strcpy(array[count++].qstring, "only");
+strcpy(array[count++].qstring, "make");
+strcpy(array[count++].qstring, "you");
+strcpy(array[count++].qstring, "feel");
+strcpy(array[count++].qstring, "ugly");
+strcpy(array[count++].qstring, "Get");
+strcpy(array[count++].qstring, "to");
+strcpy(array[count++].qstring, "know");
+strcpy(array[count++].qstring, "your");
+strcpy(array[count++].qstring, "parents");
+strcpy(array[count++].qstring, "You");
+strcpy(array[count++].qstring, "never");
+strcpy(array[count++].qstring, "know");
+strcpy(array[count++].qstring, "when");
+strcpy(array[count++].qstring, "theyll");
+strcpy(array[count++].qstring, "be");
+strcpy(array[count++].qstring, "gone");
+strcpy(array[count++].qstring, "for");
+strcpy(array[count++].qstring, "good");
+strcpy(array[count++].qstring, "Be");
+strcpy(array[count++].qstring, "nice");
+strcpy(array[count++].qstring, "to");
+strcpy(array[count++].qstring, "your");
+strcpy(array[count++].qstring, "siblings");
+strcpy(array[count++].qstring, "Theyre");
+strcpy(array[count++].qstring, "your");
+strcpy(array[count++].qstring, "best");
+strcpy(array[count++].qstring, "link");
+strcpy(array[count++].qstring, "to");
+strcpy(array[count++].qstring, "your");
+strcpy(array[count++].qstring, "past");
+strcpy(array[count++].qstring, "and");
+strcpy(array[count++].qstring, "the");
+strcpy(array[count++].qstring, "people");
+strcpy(array[count++].qstring, "most");
+strcpy(array[count++].qstring, "likely");
+strcpy(array[count++].qstring, "to");
+
+  
+  
+//printf("\nSorting %d elements.\n\n",count);
+  qsort(array,count,sizeof(struct myStringStruct),compare);
+  
+  //for(i=0;i<count;i++)
+  //  printf("%s\n", array[i].qstring);
+  return 0;
+}
diff --git a/tests/custom/sieve/Makefile b/tests/custom/sieve/Makefile
new file mode 100644
index 000000000..c000b04eb
--- /dev/null
+++ b/tests/custom/sieve/Makefile
@@ -0,0 +1,20 @@
+TARGETDIR	:= sieve
+TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
+ROOT		:= ..
+LIBRARY_DIRS	:= ${ROOT}/crt0
+LIBRARY_FILES	:= crt0
+
+MARCH           :=-march=rv64ic
+MABI            :=-mabi=lp64
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
+LINKER          := ${ROOT}/linker8000-0000.x
+
+CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
+
+CC=riscv64-unknown-elf-gcc
+DA=riscv64-unknown-elf-objdump -d
+
+
+include $(ROOT)/makefile.inc
+
+
diff --git a/tests/custom/sieve/sieve.c b/tests/custom/sieve/sieve.c
new file mode 100644
index 000000000..f7d36d957
--- /dev/null
+++ b/tests/custom/sieve/sieve.c
@@ -0,0 +1,101 @@
+/*
+ * Filename:
+ *
+ *   sieve.c
+ *
+ * Description:
+ *
+ *   The Sieve of Eratosthenes benchmark, from Byte Magazine
+ *   early 1980s, when a PC would do well to run this in 10 
+ *   seconds. This version really does count prime numbers
+ *   but omits the numbers 1, 3 and all even numbers. The
+ *   expected count is 1899.
+ *
+ */
+
+#include <sys/time.h>
+#include <stdio.h>
+
+#define SIZE 8190
+
+//#define SIZE 8388608
+double time_diff(struct timeval x , struct timeval y);
+
+int sieve () {
+
+  unsigned char flags [SIZE + 1];
+  int iter; 
+  int count;
+
+  for (iter = 1; iter <= 10; iter++) 
+    {
+      int i, prime, k;
+
+      count = 0;
+
+      for (i = 0; i <= SIZE; i++)
+        flags [i] = 1;
+
+      for (i = 0; i <= SIZE; i++) 
+        {
+          if (flags [i]) 
+            {
+              prime = i + i + 3;
+              k = i + prime;
+
+              while (k <= SIZE)
+                {
+                  flags [k] = 0;
+                  k += prime;
+                }
+
+              count++;
+            }
+        }
+    }
+
+  return count;
+}
+
+int main () {
+
+  int ans;
+
+  //struct timeval before , after;
+  //gettimeofday(&before , NULL);
+    
+  ans = sieve ();
+  //gettimeofday(&after , NULL);
+  /* /\* /\\* if (ans != 1899) *\\/ *\/ */
+  /* /\* /\\*   printf ("Sieve result wrong, ans = %d, expected 1899", ans); *\\/ *\/ */
+
+  /* /\* //printf("Total time elapsed : %.0lf us\n" , time_diff(before , after) ); *\/ */
+
+
+  /* /\* printf("Round 2\n"); *\/ */
+  /* //gettimeofday(&before , NULL); */
+    
+  /* ans = sieve (); */
+  /* //gettimeofday(&after , NULL); */
+  /* if (ans != 1899) */
+  /*   printf ("Sieve result wrong, ans = %d, expected 1899", ans); */
+
+  /* //printf("Total time elapsed : %.0lf us\n" , time_diff(before , after) );  */
+  
+  return 0;
+
+}
+
+
+double time_diff(struct timeval x , struct timeval y)
+{
+    double x_ms , y_ms , diff;
+     
+    x_ms = (double)x.tv_sec*1000000 + (double)x.tv_usec;
+    y_ms = (double)y.tv_sec*1000000 + (double)y.tv_usec;
+     
+    diff = (double)y_ms - (double)x_ms;
+     
+    return diff;
+}
+ 
diff --git a/tests/custom/simple/Makefile b/tests/custom/simple/Makefile
new file mode 100644
index 000000000..f85aedd5c
--- /dev/null
+++ b/tests/custom/simple/Makefile
@@ -0,0 +1,19 @@
+TARGETDIR	:= simple
+TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
+ROOT		:= ..
+LIBRARY_DIRS	:= ${ROOT}/crt0
+LIBRARY_FILES	:= crt0
+
+MARCH           :=-march=rv64imfdc
+MABI            :=-mabi=lp64d
+LINKER          := ${ROOT}/linker8000-0000.x
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
+
+CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
+CC=riscv64-unknown-elf-gcc
+DA=riscv64-unknown-elf-objdump -d
+
+
+include $(ROOT)/makefile.inc
+
+
diff --git a/tests/custom/simple/fail.s b/tests/custom/simple/fail.s
new file mode 100644
index 000000000..552604fe2
--- /dev/null
+++ b/tests/custom/simple/fail.s
@@ -0,0 +1,11 @@
+# Ross Thompson
+# March 17, 2021
+# Oklahoma State University
+
+.section .text	
+.global fail
+.type fail, @function
+fail:
+	li gp, 1
+	li a0, -1
+	ecall
diff --git a/tests/coverage/gshare.S b/tests/custom/simple/global_hist_test.s
similarity index 64%
rename from tests/coverage/gshare.S
rename to tests/custom/simple/global_hist_test.s
index ef0fcab77..9cd56fe62 100644
--- a/tests/coverage/gshare.S
+++ b/tests/custom/simple/global_hist_test.s
@@ -1,54 +1,3 @@
-///////////////////////////////////////////
-// gshare.S
-//
-// Written: Rose Thompson rose@rosethompson.net
-//
-// Purpose: basic check that global history and gshare branch npredictors are working as expected.  Requires manual inspection.
-// TODO: *** Automate checking prediction accuracy.
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-//
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
-// either express or implied. See the License for the specific language governing permissions
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-// load code to initalize stack, handle interrupts, terminate
-
-#include "WALLY-init-lib.h"
-
-# run-elf.bash find this in project description
-main:
-
-        addi sp, sp, 8
-        sd ra, 0(sp)
-        jal ra, oneLoopTest
-        jal ra, global_hist_6_space_test
-        jal ra, global_hist_4_space_test
-        jal ra, global_hist_3_space_test
-        jal ra, global_hist_2_space_test
-        jal ra, global_hist_1_space_test
-        jal ra, global_hist_0_space_test
-
-        fence.I
-
-finished:
-    j done
-
-        .data
-
 .section .text
 .globl oneLoopTest
 .type oneLoopTest, @function
@@ -100,7 +49,7 @@ oneLoopTest5:
 	# instruction
 	addi t3, t3, 1
 	bne t3, t4, oneLoopTest5     # this branch toggles between taken and not taken.
-
+        
 	ret
 
 .section .text
@@ -116,10 +65,10 @@ loop_6:
 	# instruction
 	addi t3, t3, 1
 	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
+	addi t3, t3, 1		
+	addi t3, t3, 1		
+	addi t3, t3, 1		
+	addi t3, t3, 1		
 	beqz t4, zero_6     # this branch toggles between taken and not taken.
 	li t4, 0
 	j one_6
@@ -129,12 +78,12 @@ zero_6:
 	addi t3, t3, 1
 	addi t3, t3, 1
 	add t1, t1, t4
-
+	
 one_6:
-	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
+	addi t3, t3, 1		
+	addi t3, t3, 1		
+	addi t3, t3, 1		
+	addi t3, t3, 1		
 	addi t2, t2, -1
 	bnez t2, loop_6
 
@@ -153,8 +102,8 @@ loop_4:
 	# instruction
 	addi t3, t3, 1
 	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
+	addi t3, t3, 1		
+	addi t3, t3, 1		
 	beqz t4, zero_4     # this branch toggles between taken and not taken.
 	li t4, 0
 	j one_4
@@ -162,9 +111,9 @@ zero_4:
 	li t4, 1
 	addi t3, t3, 1
 	add t1, t1, t4
-
+	
 one_4:
-	addi t3, t3, 1
+	addi t3, t3, 1		
 	addi t2, t2, -1
 	bnez t2, loop_4
 
@@ -183,8 +132,8 @@ loop_3:
 	# instruction
 	addi t3, t3, 1
 	addi t3, t3, 1
-	addi t3, t3, 1
-	addi t3, t3, 1
+	addi t3, t3, 1		
+	addi t3, t3, 1		
 	beqz t4, zero_3     # this branch toggles between taken and not taken.
 	li t4, 0
 	j one_3
@@ -192,9 +141,9 @@ zero_3:
 	li t4, 1
 	addi t3, t3, 1
 	add t1, t1, t4
-
+	
 one_3:
-	addi t3, t3, 1
+	addi t3, t3, 1		
 	addi t2, t2, -1
 	bnez t2, loop_3
 
@@ -220,7 +169,7 @@ loop_2:
 zero_2:
 	li t4, 1
 	add t1, t1, t4
-
+	
 one_2:
 	addi t2, t2, -1
 	bnez t2, loop_2
@@ -245,13 +194,13 @@ loop_1:
 zero_1:
 	li t4, 1
 	add t1, t1, t4
-
+	
 one_1:
 	addi t2, t2, -1
 	bnez t2, loop_1
 
 	ret
-
+	
 .section .text
 .globl global_hist_0_space_test
 .type global_hist_0_space_test, @function
@@ -269,9 +218,10 @@ loop_0:
 zero_0:
 	li t4, 1
 	add t1, t1, t4
-
+	
 one_0:
 	addi t2, t2, -1
 	bnez t2, loop_0
 
 	ret
+	
diff --git a/tests/custom/simple/header.h b/tests/custom/simple/header.h
new file mode 100644
index 000000000..973bdd59a
--- /dev/null
+++ b/tests/custom/simple/header.h
@@ -0,0 +1,15 @@
+#ifndef __header
+#define __header
+
+int fail();
+int simple_csrbr_test();
+int lbu_test();
+int icache_spill_test();
+void global_hist_0_space_test();
+void global_hist_1_space_test();
+void global_hist_2_space_test();
+void global_hist_3_space_test();
+void global_hist_4_space_test();
+void global_hist_6_space_test();
+void oneLoopTest();
+#endif
diff --git a/tests/custom/simple/lbu_test.s b/tests/custom/simple/lbu_test.s
new file mode 100644
index 000000000..d620e7cc6
--- /dev/null
+++ b/tests/custom/simple/lbu_test.s
@@ -0,0 +1,19 @@
+.section .text	
+.global lbu_test
+.type lbu_test, @function
+
+lbu_test:
+
+	li t0, 0x80000
+	lbu t1, 0(t0)
+
+
+pass:
+	li a0, 0
+done:
+	ret
+
+fail:
+	li a0, -1
+	j done
+	
diff --git a/tests/custom/simple/main.c b/tests/custom/simple/main.c
new file mode 100644
index 000000000..bebd96f6b
--- /dev/null
+++ b/tests/custom/simple/main.c
@@ -0,0 +1,24 @@
+#include "header.h"
+
+int main(){
+  //int res = icache_spill_test();
+  oneLoopTest();
+  global_hist_6_space_test();  
+  global_hist_4_space_test();  
+  global_hist_3_space_test();  
+  global_hist_2_space_test();
+  global_hist_1_space_test();
+  global_hist_0_space_test();    
+  int res = 1;
+  if (res < 0) {
+    fail();
+    return 0;
+  }else {
+    if((res = lbu_test()) < 0) {
+      fail();
+      return 0;
+    }
+    res = simple_csrbr_test();
+    return 0;
+  }
+}
diff --git a/tests/custom/simple/sample.s b/tests/custom/simple/sample.s
new file mode 100644
index 000000000..a5f5df04c
--- /dev/null
+++ b/tests/custom/simple/sample.s
@@ -0,0 +1,62 @@
+.section .text	
+.global simple_csrbr_test
+.type simple_csrbr_test, @function
+
+simple_csrbr_test:	
+
+	# step 1 enable the performance counters
+	# by default the hardware enables all performance counters
+	# however we will eventually want to manually enable incase
+	# some other code disables them
+
+	# br count is counter 5
+	# br mp count is counter 4
+	li t0, 0x30
+	
+	csrrc x0, 0x320, t0  # clear bits 4 and 5 of inhibit register.
+
+	# step 2 read performance counters into general purpose registers
+
+	csrrw t2, 0xB05, x0 # t2 = BR COUNT (perf count 5)
+	csrrw t3, 0xB04, x0 # t3 = BRMP COUNT (perf count 4)
+
+	# step 3 simple loop to show the counters are updated.
+	li t0, 0   # this is the loop counter
+	li t1, 100 # this is the loop end condition
+
+	# for(t1 = 0; t1 < t0; t1++);
+
+loop:	
+	addi t0, t0, 1
+	blt t0, t1, loop
+
+loop_done:	
+	
+	# step 2 read performance counters into general purpose registers
+
+	csrrw t4, 0xB05, x0 # t4 = BR COUNT (perf count 5)
+	csrrw t5, 0xB04, x0 # t5 = BRMP COUNT (perf count 4)
+
+	sub t2, t4, t2 # this is the number of branch instructions committed.
+	sub t3, t5, t3 # this is the number of branch mispredictions committed.
+
+	# now check if the branch count equals 100 and if the branch
+	bne t4, t2, fail
+	li  t5, 3
+	bne t3, t5, fail
+	
+pass:
+	li a0, 0
+done:
+	li t0, 0x30
+	csrrs x0, 0x320, t0  # set bits 4 and 5
+	ecall
+	ret
+
+fail:
+	li a0, -1
+	j done
+
+.data 
+sample_data:
+.int 0	
diff --git a/tests/custom/spitest/spi.h b/tests/custom/spitest/spi.h
deleted file mode 100644
index 2b1d541da..000000000
--- a/tests/custom/spitest/spi.h
+++ /dev/null
@@ -1,116 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// spi.h
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
-//
-// Purpose: Header file for interfaceing with the SPI peripheral
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#pragma once
-#ifndef SPI_HEADER
-#define SPI_HEADER
-
-#include <stdint.h>
-
-#define SPI_BASE              0x13000 /* Base address of SPI device used for SDC */
-
-/* register offsets */
-#define SPI_SCKDIV            SPI_BASE + 0x00 /* Serial clock divisor */
-#define SPI_SCKMODE           SPI_BASE + 0x04 /* Serial clock mode */
-#define SPI_CSID              SPI_BASE + 0x10 /* Chip select ID */
-#define SPI_CSDEF             SPI_BASE + 0x14 /* Chip select default */
-#define SPI_CSMODE            SPI_BASE + 0x18 /* Chip select mode */
-#define SPI_DELAY0            SPI_BASE + 0x28 /* Delay control 0 */
-#define SPI_DELAY1            SPI_BASE + 0x2c /* Delay control 1 */
-#define SPI_FMT               SPI_BASE + 0x40 /* Frame format */
-#define SPI_TXDATA            SPI_BASE + 0x48 /* Tx FIFO data */
-#define SPI_RXDATA            SPI_BASE + 0x4c /* Rx FIFO data */
-#define SPI_TXMARK            SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */
-#define SPI_RXMARK            SPI_BASE + 0x54 /* Rx FIFO watermark */
-
-/* Non-implemented
-#define SPI_FCTRL             SPI_BASE + 0x60 // SPI flash interface control
-#define SPI_FFMT              SPI_BASE + 0x64 // SPI flash instruction format
-*/
-#define SPI_IE                SPI_BASE + 0x70 /* Interrupt Enable Register */
-#define SPI_IP                SPI_BASE + 0x74 /* Interrupt Pendings Register */
-
-/* delay0 bits */
-#define SIFIVE_SPI_DELAY0_CSSCK(x)       ((uint32_t)(x))
-#define SIFIVE_SPI_DELAY0_CSSCK_MASK     0xffU
-#define SIFIVE_SPI_DELAY0_SCKCS(x)       ((uint32_t)(x) << 16)
-#define SIFIVE_SPI_DELAY0_SCKCS_MASK     (0xffU << 16)
-
-/* delay1 bits */
-#define SIFIVE_SPI_DELAY1_INTERCS(x)     ((uint32_t)(x))
-#define SIFIVE_SPI_DELAY1_INTERCS_MASK   0xffU
-#define SIFIVE_SPI_DELAY1_INTERXFR(x)    ((uint32_t)(x) << 16)
-#define SIFIVE_SPI_DELAY1_INTERXFR_MASK  (0xffU << 16)
-
-/* csmode bits */
-#define SIFIVE_SPI_CSMODE_MODE_AUTO      0U
-#define SIFIVE_SPI_CSMODE_MODE_HOLD      2U
-#define SIFIVE_SPI_CSMODE_MODE_OFF       3U
-
-// inline void write_reg(uintptr_t addr, uint32_t value);
-//inline uint32_t read_reg(uintptr_t addr);
-//inline void spi_sendbyte(uint8_t byte);
-//inline void waittx();
-//inline void waitrx();
-uint8_t spi_txrx(uint8_t byte);
-uint8_t spi_dummy();
-//inline uint8_t spi_readbyte();
-//uint64_t spi_read64();
-void spi_init();
-void spi_set_clock(uint32_t clkin, uint32_t clkout);
-
-static inline void write_reg(uintptr_t addr, uint32_t value) {
-  volatile uint32_t * loc = (volatile uint32_t *) addr;
-  *loc = value;
-}
-
-// Read a register
-static inline uint32_t read_reg(uintptr_t addr) {
-  return *(volatile uint32_t *) addr;
-}
-
-// Queues a single byte in the transfer fifo
-static inline void spi_sendbyte(uint8_t byte) {
-  // Write byte to transfer fifo
-  write_reg(SPI_TXDATA, byte);
-}
-
-static inline void waittx() {
-  while(!(read_reg(SPI_IP) & 1)) {}
-}
-
-static inline void waitrx() {
-  while(read_reg(SPI_IP) & 2) {}
-}
-
-static inline uint8_t spi_readbyte() {
-  return read_reg(SPI_RXDATA);
-}
-
-#endif
diff --git a/tests/custom/spitest/spitest.c b/tests/custom/spitest/spitest.c
deleted file mode 100644
index 23d408c16..000000000
--- a/tests/custom/spitest/spitest.c
+++ /dev/null
@@ -1,107 +0,0 @@
-///////////////////////////////////////////////////////////////////////
-// spi.c
-//
-// Written: Jaocb Pease jacob.pease@okstate.edu 8/27/2024
-//
-// Purpose: C code to test SPI bugs
-//
-// 
-//
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the
-// “License”); you may not use this file except in compliance with the
-// License, or, at your option, the Apache License version 2.0. You
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work
-// distributed under the License is distributed on an “AS IS” BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// permissions and limitations under the License.
-///////////////////////////////////////////////////////////////////////
-
-#include "spi.h"
-
-// Testing SPI peripheral in loopback mode
-// TODO: Need to make sure the configuration I'm using uses loopback
-//       mode. This can be specified in derivlists.txt
-// TODO:
-
-uint8_t spi_txrx(uint8_t byte) {
-  spi_sendbyte(byte);
-  waittx();
-  return spi_readbyte();
-}
-
-uint8_t spi_dummy() {
-  return spi_txrx(0xff);
-}
-
-void spi_set_clock(uint32_t clkin, uint32_t clkout) {
-  uint32_t div = (clkin/(2*clkout)) - 1;
-  write_reg(SPI_SCKDIV, div);
-}
-
-// Initialize Sifive FU540 based SPI Controller
-void spi_init(uint32_t clkin) {
-  // Enable interrupts
-  write_reg(SPI_IE, 0x3);
-
-  // Set TXMARK to 1. If the number of entries is < 1
-  // IP's txwm field will go high.
-  // Set RXMARK to 0. If the number of entries is > 0
-  // IP's rwxm field will go high.
-  write_reg(SPI_TXMARK, 1);
-  write_reg(SPI_RXMARK, 0);
-
-  // Set Delay 0 to default
-  write_reg(SPI_DELAY0,
-            SIFIVE_SPI_DELAY0_CSSCK(1) |
-			SIFIVE_SPI_DELAY0_SCKCS(1));
-
-  // Set Delay 1 to default
-  write_reg(SPI_DELAY1,
-            SIFIVE_SPI_DELAY1_INTERCS(1) |
-            SIFIVE_SPI_DELAY1_INTERXFR(0));
-
-  // Initialize the SPI controller clock to 
-  // div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18 
-  write_reg(SPI_SCKDIV, 0x18); 
-}
-
-void main() {
-  spi_init(100000000);
-
-  spi_set_clock(100000000,50000000);
-  
-  volatile uint8_t *p = (uint8_t *)(0x8F000000);
-  int j;
-  uint64_t n = 0;
-
-  write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD);
-  //n = 512/8;
-
-  n = 4;
-  do {
-    // Send 8 dummy bytes (fifo should be empty)
-    for (j = 0; j < 8; j++) {
-      spi_sendbyte(0xaa + j);
-    }
-    
-    // Reset counter. Process bytes AS THEY COME IN.
-    for (j = 0; j < 8; j++) {
-      while (!(read_reg(SPI_IP) & 2)) {}
-      uint8_t x = spi_readbyte();
-      *p++ = x;      
-    }
-  } while(--n > 0);
-
-  write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO);
-}
diff --git a/fpga/zsbl/Makefile b/tests/custom/zsbl/Makefile
similarity index 76%
rename from fpga/zsbl/Makefile
rename to tests/custom/zsbl/Makefile
index 581a9496b..6dec9c797 100644
--- a/fpga/zsbl/Makefile
+++ b/tests/custom/zsbl/Makefile
@@ -16,35 +16,26 @@ OBJECTS		:= $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
 OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
 
 TARGETDIR	:= bin
-TARGET		:= $(TARGETDIR)/boot
-MEMFILES    := $(TARGETDIR/boot.mem $(TARGETDIR)/data.mem
+TARGET		:= $(TARGETDIR)/fpga-test-sdc
 ROOT		:= ..
 LIBRARY_DIRS	:= 
 LIBRARY_FILES	:=
 
-MARCH           :=-march=rv64imfdc_zifencei
+MARCH           :=-march=rv64imfdc
 MABI            :=-mabi=lp64d
-LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
-LINKER		:=linker1000.x
-
-# FGPA parameters
-SYSTEMCLOCK   ?= 20000000
-MAXSDCCLOCK   ?=  5000000
-EXT_MEM_BASE  ?= 0x80000000
-EXT_MEM_RANGE ?= 0x10000000
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
+LINKER		:=linker.x
 
 
 AFLAGS =$(MARCH) $(MABI) -W
-# Override directive allows us to prepend other options on the command line
-# e.g. $ make CFLAGS=-g
-override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g  -DSYSTEMCLOCK=${SYSTEMCLOCK} -DMAXSDCCLOCK=${MAXSDCCLOCK} -DEXT_MEM_BASE=${EXT_MEM_BASE} -DEXT_MEM_RANGE=${EXT_MEM_RANGE}
+CFLAGS =$(MARCH) $(MABI) -mcmodel=medany  -O2
 AS=riscv64-unknown-elf-as
 CC=riscv64-unknown-elf-gcc
 AR=riscv64-unknown-elf-ar
 
 
 #Default Make
-all: directories $(TARGET).memfile
+all: directories  $(TARGET).memfile
 
 #Remake
 remake: clean all
@@ -55,7 +46,7 @@ directories:
 	@mkdir -p $(BUILDDIR)
 
 clean:
-	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump boot.mem data.mem
+	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump 
 
 
 #Needed for building additional library projects
@@ -64,7 +55,7 @@ LIBS+=${LIBRARY_DIRS:%=-L%}  ${LIBRARY_FILES:%=-l%}
 INC+=${LIBRARY_DIRS:%=-I%}
 
 ${LIBRARY_DIRS}: 
-	$(MAKE) -C $@ -j 1
+	make -C $@ -j 1
 
 .PHONY: $(LIBRARY_DIRS) $(TARGET)
 endif
@@ -113,11 +104,9 @@ $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
 # convert to hex
 $(TARGET).memfile: $(TARGET)
 	@echo 'Making object dump file.'
-	riscv64-unknown-elf-objdump -DS $< > $<.objdump
+	@riscv64-unknown-elf-objdump -D $< > $<.objdump
 	@echo 'Making memory file'
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
 	extractFunctionRadix.sh $<.objdump
-	@echo 'Splitting memfile.'
-	./splitfile.sh $@
-	mv boot.mem ../src/boot.mem
-	mv data.mem ../src/data.mem
+	mkdir -p ../../imperas-riscv-tests/work/rv64BP/
+	cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
diff --git a/tests/custom/zsbl/bios.s b/tests/custom/zsbl/bios.s
new file mode 100644
index 000000000..ebeadcf59
--- /dev/null
+++ b/tests/custom/zsbl/bios.s
@@ -0,0 +1,98 @@
+PERIOD = 11000000
+#PERIOD = 20
+
+.section .init
+.global _start
+.type _start, @function
+
+		
+_start:
+	  # Initialize global pointer
+	.option push
+	.option norelax
+	1:auipc gp, %pcrel_hi(__global_pointer$)
+	addi  gp, gp, %pcrel_lo(1b)
+	.option pop
+	
+	li x1, 0
+	li x2, 0
+	li x4, 0
+	li x5, 0
+	li x6, 0
+	li x7, 0
+	li x8, 0
+	li x9, 0
+	li x10, 0
+	li x11, 0
+	li x12, 0
+	li x13, 0
+	li x14, 0
+	li x15, 0
+	li x16, 0
+	li x17, 0
+	li x18, 0
+	li x19, 0
+	li x20, 0
+	li x21, 0
+	li x22, 0
+	li x23, 0
+	li x24, 0
+	li x25, 0
+	li x26, 0
+	li x27, 0
+	li x28, 0
+	li x29, 0
+	li x30, 0
+	li x31, 0
+
+
+	# set the stack pointer to the top of memory - 8 bytes (pointer size)
+	li sp, 0x87FFFFF8
+
+	jal ra, main
+	
+	fence.i
+	# now toggle led so we know the copy completed.
+
+	# write to gpio
+	li	t2, 0xFF
+	la	t3, 0x1006000C
+	li	t4, 5
+
+loop:
+
+	# delay
+	li	t0, PERIOD/2
+delay1:	
+	addi	t0, t0, -1
+	bge	t0, x0, delay1
+	sw	t2, 0x0(t3)
+
+	li	t0, PERIOD/2
+delay2:	
+	addi	t0, t0, -1
+	bge	t0, x0, delay2
+	sw	x0, 0x0(t3)
+
+	addi	t4, t4, -1
+	bgt	t4, x0, loop
+
+
+	# now that the card is copied and the led toggled we
+	# jump to the copied contents of the sd card.
+
+jumpToLinux:
+	csrr a0, mhartid
+        li s0, 0x80000000
+        la a1, _dtb
+        jr s0
+end_of_bios:	
+
+
+
+.section .rodata
+.globl _dtb
+.align 4, 0
+_dtb:
+.incbin "wally-vcu118.dtb"
+
diff --git a/tests/custom/zsbl/copyFlash.c b/tests/custom/zsbl/copyFlash.c
new file mode 100644
index 000000000..4165fe21c
--- /dev/null
+++ b/tests/custom/zsbl/copyFlash.c
@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// copyFlash.sv
+//
+// Written: Ross Thompson September 25, 2021
+// Modified: 
+//
+// Purpose: copies flash card into memory
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "sdcDriver.h"
+
+void copyFlash(long int blockAddr, long int * Dst, int numBlocks) {
+
+  setSDCCLK(4); // must be even, 1 gives no division.
+  waitInitSDC();
+
+  int index;
+
+  for(index = 0; index < numBlocks; index++) {
+    copySDC512(blockAddr+(index*512), Dst+(index*512/8));
+  }
+  
+    
+}
diff --git a/tests/custom/zsbl/gpt.c b/tests/custom/zsbl/gpt.c
new file mode 100644
index 000000000..0c645d70e
--- /dev/null
+++ b/tests/custom/zsbl/gpt.c
@@ -0,0 +1,119 @@
+#include "gpt.h"
+
+#include "sdcDriver.h"
+
+#include "uart.h"
+#include <stddef.h>
+
+int gpt_find_boot_partition(long int* dest, uint32_t size)
+{
+  //int ret = init_sd();
+  int ret;
+  setSDCCLK(4); // must be even, 1 gives no division.
+  waitInitSDC();
+  ret = 0;
+    if (ret != 0) {
+        print_uart("could not initialize sd... exiting\r\n");
+        return -1;
+    }
+
+    print_uart("sd initialized!\r\n");
+
+    // load LBA1
+    size_t block_size = 512/8;
+    long int lba1_buf[block_size];
+
+    //int res = sd_copy(lba1_buf, 1, 1);
+    int res;
+    copySDC512(1, lba1_buf);
+    res = 0;
+
+    if (res != 0)
+    {
+        print_uart("SD card failed!\r\n");
+        print_uart("sd copy return value: ");
+        print_uart_addr(res);
+        print_uart("\r\n");
+        return -2;
+    }
+
+    gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf;
+
+    print_uart("gpt partition table header:");
+    print_uart("\r\n\tsignature:\t");
+    print_uart_addr(lba1->signature);
+    print_uart("\r\n\trevision:\t");
+    print_uart_int(lba1->revision);
+    print_uart("\r\n\tsize:\t\t");
+    print_uart_int(lba1->header_size);
+    print_uart("\r\n\tcrc_header:\t");
+    print_uart_int(lba1->crc_header);
+    print_uart("\r\n\treserved:\t");
+    print_uart_int(lba1->reserved);
+    print_uart("\r\n\tcurrent lba:\t");
+    print_uart_addr(lba1->current_lba);
+    print_uart("\r\n\tbackup lda:\t");
+    print_uart_addr(lba1->backup_lba);
+    print_uart("\r\n\tpartition entries lba:   \t");
+    print_uart_addr(lba1->partition_entries_lba);
+    print_uart("\r\n\tnumber partition entries:\t");
+    print_uart_int(lba1->nr_partition_entries);
+    print_uart("\r\n\tsize partition entries:  \t");
+    print_uart_int(lba1->size_partition_entry);
+    print_uart("\r\n");
+
+    long int lba2_buf[block_size];
+
+    //res = sd_copy(lba2_buf, lba1->partition_entries_lba, 1);
+    copySDC512(lba1->partition_entries_lba, lba2_buf);
+    res = 0;
+
+    if (res != 0)
+    {
+        print_uart("SD card failed!\r\n");
+        print_uart("sd copy return value: ");
+        print_uart_addr(res);
+        print_uart("\r\n");
+        return -2;
+    }
+
+    for (int i = 0; i < 4; i++)
+    {
+        partition_entries_t *part_entry = (partition_entries_t *)(lba2_buf + (i * 128));
+        print_uart("gpt partition entry ");
+        print_uart_byte(i);
+        print_uart("\r\n\tpartition type guid:\t");
+        for (int j = 0; j < 16; j++)
+            print_uart_byte(part_entry->partition_type_guid[j]);
+        print_uart("\r\n\tpartition guid:     \t");
+        for (int j = 0; j < 16; j++)
+            print_uart_byte(part_entry->partition_guid[j]);
+        print_uart("\r\n\tfirst lba:\t");
+        print_uart_addr(part_entry->first_lba);
+        print_uart("\r\n\tlast lba:\t");
+        print_uart_addr(part_entry->last_lba);
+        print_uart("\r\n\tattributes:\t");
+        print_uart_addr(part_entry->attributes);
+        print_uart("\r\n\tname:\t");
+        for (int j = 0; j < 72; j++)
+            print_uart_byte(part_entry->name[j]);
+        print_uart("\r\n");
+    }
+
+    partition_entries_t *boot = (partition_entries_t *)(lba2_buf);
+    print_uart("copying boot image ");
+    //res = sd_copy(dest, boot->first_lba, boot->last_lba - boot->first_lba + 1);
+    copyFlash(boot->first_lba, dest, boot->last_lba - boot->first_lba + 1);
+
+    if (res != 0)
+    {
+        print_uart("SD card failed!\r\n");
+        print_uart("sd copy return value: ");
+        print_uart_addr(res);
+        print_uart("\r\n");
+        return -2;
+    }
+
+    print_uart(" done!\r\n");
+    return 0;
+}
diff --git a/tests/custom/zsbl/gpt.h b/tests/custom/zsbl/gpt.h
new file mode 100644
index 000000000..dcc27ae8a
--- /dev/null
+++ b/tests/custom/zsbl/gpt.h
@@ -0,0 +1,39 @@
+#pragma once
+
+#include <stdint.h>
+
+// LBA 0: Protective MBR
+// ignored here
+
+// Partition Table Header (LBA 1)
+typedef struct gpt_pth
+{
+    uint64_t signature;
+    uint32_t revision;
+    uint32_t header_size; //! little endian, usually 0x5c = 92
+    uint32_t crc_header;
+    uint32_t reserved; //! must be 0
+    uint64_t current_lba;
+    uint64_t backup_lba;
+    uint64_t first_usable_lba;
+    uint64_t last_usable_lba;
+    uint8_t disk_guid[16];
+    uint64_t partition_entries_lba;
+    uint32_t nr_partition_entries;
+    uint32_t size_partition_entry; //! usually 0x80 = 128
+    uint32_t crc_partition_entry;
+} gpt_pth_t;
+
+// Partition Entries (LBA 2-33)
+typedef struct partition_entries
+{
+    uint8_t partition_type_guid[16];
+    uint8_t partition_guid[16];
+    uint64_t first_lba;
+    uint64_t last_lba; //! inclusive
+    uint64_t attributes;
+    uint8_t name[72]; //! utf16 encoded
+} partition_entries_t;
+
+// Find boot partition and load it to the destination
+int gpt_find_boot_partition(long int* dest, uint32_t size);
diff --git a/tests/custom/zsbl/main.c b/tests/custom/zsbl/main.c
new file mode 100644
index 000000000..898025c30
--- /dev/null
+++ b/tests/custom/zsbl/main.c
@@ -0,0 +1,26 @@
+#include "uart.h"
+#include "sdcDriver.h"
+#include "gpt.h"
+
+int main()
+{
+    init_uart(30000000, 115200);
+    print_uart("Hello World!\r\n");
+
+    int res = gpt_find_boot_partition((long int *)0x80000000UL, 2 * 16384);
+
+    if (res == 0)
+    {
+      return 0;
+    }
+
+    while (1)
+    {
+        // do nothing
+    }
+}
+
+void handle_trap(void)
+{
+    // print_uart("trap\r\n");
+}
diff --git a/tests/custom/zsbl/sdcDriver.c b/tests/custom/zsbl/sdcDriver.c
new file mode 100644
index 000000000..edbe0677d
--- /dev/null
+++ b/tests/custom/zsbl/sdcDriver.c
@@ -0,0 +1,69 @@
+///////////////////////////////////////////
+// SDC.sv
+//
+// Written: Ross Thompson September 25, 2021
+// Modified: 
+//
+// Purpose: driver for sdc reader.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+
+#include "sdcDriver.h"
+
+#define SDC_MAIL_BOX 0x12100
+
+void copySDC512(long int blockAddr, long int * Dst) {
+
+  waitInitSDC();
+
+  volatile long int * mailBoxAddr;
+  volatile int * mailBoxCmd;
+  volatile int * mailBoxStatus;
+  volatile long int * mailBoxReadData;
+  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);  
+  mailBoxCmd = (int *) (SDC_MAIL_BOX + 0x8);
+  mailBoxAddr = (long int *) (SDC_MAIL_BOX + 0x10);
+  mailBoxReadData = (long int *) (SDC_MAIL_BOX + 0x18);  
+  
+  // write the SDC address register with the blockAddr
+  *mailBoxAddr = blockAddr;
+  *mailBoxCmd = 0x4;
+
+  // wait until the mailbox has valid data
+  // this occurs when status[1] = 0
+  while((*mailBoxStatus & 0x2) == 0x2);
+
+  int index;
+  for(index = 0; index < 512/8; index++) {
+    Dst[index] = *mailBoxReadData;
+  }
+}
+
+volatile void waitInitSDC(){
+  volatile int * mailBoxStatus;
+  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);
+  while((*mailBoxStatus & 0x1) != 0x1);
+}
+
+void setSDCCLK(int divider){
+  divider = (1 - (divider >> 1));
+  volatile int * mailBoxCLK;
+  mailBoxCLK = (int *) (SDC_MAIL_BOX + 0x0);
+  *mailBoxCLK = divider;
+}
diff --git a/tests/custom/zsbl/sdcDriver.h b/tests/custom/zsbl/sdcDriver.h
new file mode 100644
index 000000000..3e7381837
--- /dev/null
+++ b/tests/custom/zsbl/sdcDriver.h
@@ -0,0 +1,10 @@
+#ifndef __SDCDRIVER_H
+#define __SDCDRIVER_H
+
+
+void copySDC512(long int, long int *);
+volatile void waitInitSDC();
+void setSDCCLK(int);
+void copyFlash(long int, long int *, int);
+
+#endif
diff --git a/tests/custom/zsbl/smp.h b/tests/custom/zsbl/smp.h
new file mode 100644
index 000000000..bb037755d
--- /dev/null
+++ b/tests/custom/zsbl/smp.h
@@ -0,0 +1,52 @@
+#pragma once
+
+// The hart that non-SMP tests should run on
+#ifndef NONSMP_HART
+#define NONSMP_HART 0
+#endif
+
+// The maximum number of HARTs this code supports
+#define CLINT_CTRL_ADDR 0x2000000
+#ifndef MAX_HARTS
+#define MAX_HARTS 256
+#endif
+#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS * 4)
+
+/* If your test needs to temporarily block multiple-threads, do this:
+ *    smp_pause(reg1, reg2)
+ *    ... single-threaded work ...
+ *    smp_resume(reg1, reg2)
+ *    ... multi-threaded work ...
+ */
+
+#define smp_pause(reg1, reg2) \
+    li reg2, 0x8;             \
+    csrw mie, reg2;           \
+    li reg1, NONSMP_HART;     \
+    csrr reg2, mhartid;       \
+    bne reg1, reg2, 42f
+
+#define smp_resume(reg1, reg2)   \
+    li reg1, CLINT_CTRL_ADDR;    \
+    41:;                         \
+    li reg2, 1;                  \
+    sw reg2, 0(reg1);            \
+    addi reg1, reg1, 4;          \
+    li reg2, CLINT_END_HART_IPI; \
+    blt reg1, reg2, 41b;         \
+    42:;                         \
+    wfi;                         \
+    csrr reg2, mip;              \
+    andi reg2, reg2, 0x8;        \
+    beqz reg2, 42b;              \
+    li reg1, CLINT_CTRL_ADDR;    \
+    csrr reg2, mhartid;          \
+    slli reg2, reg2, 2;          \
+    add reg2, reg2, reg1;        \
+    sw zero, 0(reg2);            \
+    41:;                         \
+    lw reg2, 0(reg1);            \
+    bnez reg2, 41b;              \
+    addi reg1, reg1, 4;          \
+    li reg2, CLINT_END_HART_IPI; \
+    blt reg1, reg2, 41b
diff --git a/tests/custom/zsbl/uart.c b/tests/custom/zsbl/uart.c
new file mode 100644
index 000000000..a8084ee5e
--- /dev/null
+++ b/tests/custom/zsbl/uart.c
@@ -0,0 +1,91 @@
+#include "uart.h"
+
+void write_reg_u8(uintptr_t addr, uint8_t value)
+{
+    volatile uint8_t *loc_addr = (volatile uint8_t *)addr;
+    *loc_addr = value;
+}
+
+uint8_t read_reg_u8(uintptr_t addr)
+{
+    return *(volatile uint8_t *)addr;
+}
+
+int is_transmit_empty()
+{
+    return read_reg_u8(UART_LINE_STATUS) & 0x20;
+}
+
+void write_serial(char a)
+{
+    while (is_transmit_empty() == 0) {};
+
+    write_reg_u8(UART_THR, a);
+}
+
+void init_uart(uint32_t freq, uint32_t baud)
+{
+    uint32_t divisor = freq / (baud << 4);
+
+    write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts
+    write_reg_u8(UART_LINE_CONTROL, 0x80);     // Enable DLAB (set baud rate divisor)
+    write_reg_u8(UART_DLAB_LSB, divisor);         // divisor (lo byte)
+    write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF);  // divisor (hi byte)
+    write_reg_u8(UART_LINE_CONTROL, 0x03);     // 8 bits, no parity, one stop bit
+    write_reg_u8(UART_FIFO_CONTROL, 0xC7);     // Enable FIFO, clear them, with 14-byte threshold
+    write_reg_u8(UART_MODEM_CONTROL, 0x20);    // Autoflow mode
+}
+
+void print_uart(const char *str)
+{
+    const char *cur = &str[0];
+    while (*cur != '\0')
+    {
+        write_serial((uint8_t)*cur);
+        ++cur;
+    }
+}
+
+uint8_t bin_to_hex_table[16] = {
+    '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'};
+
+void bin_to_hex(uint8_t inp, uint8_t res[2])
+{
+    res[1] = bin_to_hex_table[inp & 0xf];
+    res[0] = bin_to_hex_table[(inp >> 4) & 0xf];
+    return;
+}
+
+void print_uart_int(uint32_t addr)
+{
+    int i;
+    for (i = 3; i > -1; i--)
+    {
+        uint8_t cur = (addr >> (i * 8)) & 0xff;
+        uint8_t hex[2];
+        bin_to_hex(cur, hex);
+        write_serial(hex[0]);
+        write_serial(hex[1]);
+    }
+}
+
+void print_uart_addr(uint64_t addr)
+{
+    int i;
+    for (i = 7; i > -1; i--)
+    {
+        uint8_t cur = (addr >> (i * 8)) & 0xff;
+        uint8_t hex[2];
+        bin_to_hex(cur, hex);
+        write_serial(hex[0]);
+        write_serial(hex[1]);
+    }
+}
+
+void print_uart_byte(uint8_t byte)
+{
+    uint8_t hex[2];
+    bin_to_hex(byte, hex);
+    write_serial(hex[0]);
+    write_serial(hex[1]);
+}
diff --git a/tests/custom/zsbl/uart.h b/tests/custom/zsbl/uart.h
new file mode 100644
index 000000000..df3aef9c8
--- /dev/null
+++ b/tests/custom/zsbl/uart.h
@@ -0,0 +1,27 @@
+#pragma once
+
+#include <stdint.h>
+
+#define UART_BASE 0x10000000
+
+#define UART_RBR UART_BASE + 0
+#define UART_THR UART_BASE + 0
+#define UART_INTERRUPT_ENABLE UART_BASE + 4
+#define UART_INTERRUPT_IDENT UART_BASE + 8
+#define UART_FIFO_CONTROL UART_BASE + 8
+#define UART_LINE_CONTROL UART_BASE + 12
+#define UART_MODEM_CONTROL UART_BASE + 16
+#define UART_LINE_STATUS UART_BASE + 20
+#define UART_MODEM_STATUS UART_BASE + 24
+#define UART_DLAB_LSB UART_BASE + 0
+#define UART_DLAB_MSB UART_BASE + 4
+
+void init_uart();
+
+void print_uart(const char* str);
+
+void print_uart_int(uint32_t addr);
+
+void print_uart_addr(uint64_t addr);
+
+void print_uart_byte(uint8_t byte);
diff --git a/tests/fp/Makefile b/tests/fp/Makefile
deleted file mode 100755
index d4abb6ee4..000000000
--- a/tests/fp/Makefile
+++ /dev/null
@@ -1,38 +0,0 @@
-# Jordan Carlin, jcarlin@hmc.edu, August 2024
-# Floating Point Tests Makefile for CORE-V-Wally
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-MAKEFLAGS += --output-sync --no-print-directory
-
-SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC
-TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
-
-.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
-
-all: vectors combined_IF_vectors
-
-softfloat: ${SOFTFLOAT_DIR}/softfloat.a
-
-testfloat: ${TESTFLOAT_DIR}/testfloat_gen
-
-vectors: testfloat
-	$(MAKE) -C ${WALLY}/tests/fp/vectors
-
-combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
-	cd ${WALLY}/tests/fp/combined_IF_vectors \
-	&& ./create_IF_vectors.sh
-
-clean:
-	$(MAKE) -C ${WALLY}/tests/fp/vectors clean
-	$(MAKE) -C ${SOFTFLOAT_DIR} clean
-	$(MAKE) -C ${TESTFLOAT_DIR} clean
-	rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
-
-${SOFTFLOAT_DIR}/softfloat.a:
-	$(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR}
-
-${TESTFLOAT_DIR}/testfloat_gen: ${SOFTFLOAT_DIR}/softfloat.a
-	$(MAKE) -C ${TESTFLOAT_DIR}
-
-${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
-	@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")
diff --git a/tests/fp/README.md b/tests/fp/README.md
index c4cd2b97b..3508bcee4 100644
--- a/tests/fp/README.md
+++ b/tests/fp/README.md
@@ -1,202 +1,187 @@
-james.stine@okstate.edu 14 Jan 2022\
-jcarlin@hmc.edu Sept 2024
+james.stine@okstate.edu 14 Jan 2022
 
-# TestFloat for CVW
+These are the testvectors (TV) to test the floating-point units using
+Berkeley TestFloat written originally by John Hauser.  TestFloat
+requires both TestFloat and SoftFloat.
 
-The CVW floating point unit is tested using testvectors from the Berkeley TestFloat suite, written originally by John Hauser.
+The locations at time of this README is found here:
+TestFloat-3e:  http://www.jhauser.us/arithmetic/TestFloat.html
+SoftFloat-3e:  http://www.jhauser.us/arithmetic/SoftFloat.html
 
-TestFloat and SoftFloat can be found as submodules in the addins directory, and are linked here:
-- TestFloat:  https://github.com/ucb-bar/berkeley-testfloat-3
-- SoftFloat:  https://github.com/ucb-bar/berkeley-softfloat-3
+These files have been compiled on a x86_64 environment by going into
+the build/Linux-x86_64-GCC directory and typing make.  A script
+createX.sh (e.g., create_vectors32.sh) has been included that create
+the TV for each rounding mode  and operation.  These scripts must be
+run in the build directory of TestFloat.
 
-## Compiling SoftFloat/TestFloat and Generating Testvectors
+A set of scripts is also include that runs everything from the
+baseline directory.  Please change the BUILD and OUTPUT variable to
+change your baseline program where its compiled and where you want to
+output the vectors.  By default, the vectors are output into the
+vectors subdirectory.
 
-The entire testvector generation process can be performed by running make in this directory.
+After each TV has been created a script (included) is run called
+undy.sh that puts an underscore between vector to allow SystemVerilog
+readmemh to read correctly.
 
-```bash
-make --jobs
-```
+./undy.sh file.tv
 
-This compiles SoftFloat for an x86_64 environment in its `build/Linux-x86_64-GCC` directory using the `SPECIALIZE_TYPE=RISCV` flag to get RISC-V behavior. TestFloat is then compiled in its `build/Linux-x86_64-GCC` directory using this SoftFloat library.
+To remove all the underscores from all the TV files, one can run the
+command that will add underscores appropriately to all the files.
 
-The Makefile in the vectors subdirectory of this directory is then called to  generate testvectors for each rounding mode and operation. It also puts an underscore between each vector instead of a space to allow SystemVerilog `$readmemh` to read correctly.
+cd vectors
+../undy.sh \*
 
-Testvectors for the combined integer floating-point divider are also generated.
+Note: due to size, the fxx_fma_xx.tv vectors are not included.
+However, they can easily be created with the create scripts.
 
-Although not needed, a `case.sh` script is included to change the case of the hex output.  This is for those that do not like to see hexadecimal capitalized :P.
+Although not needed, a case.sh script is included to change the case
+of the hex output.  This is for those that do not like to see
+hexadecimal capitalized :P. 
 
-## Running TestFloat Vectors on Wally
-
-TestFloat is run using the standard Wally simulation commands.
-
-To run all TestFloat tests on many different derived configurations of Wally, use
-```bash
-regression-wally --testfloat
-```
-
-To run a single test, use
-```bash
-wsim <config> <test> --tb testbench_fp
-```
-The choices for `<test>` are as follows:
-
-    cvtint - test integer conversion unit (fcvtint)
-    cvtfp  - test floating-point conversion unit (fcvtfp)
-    cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
-    add    - test addition
-    fma    - test fma
-    mul    - test mult with fma
-    sub    - test subtraction
-    div    - test division
-    sqrt   - test square root
-
-Any config that includes floating point support can be used. Each test will test all its vectors for all precisions supported by the given config.
-
-### Testvector Count
-
-      46464   185856   836352 f16_add_rd.tv
-      46464   185856   836352 f16_add_rne.tv
-      46464   185856   836352 f16_add_ru.tv
-      46464   185856   836352 f16_add_rz.tv
-      46464   185856   836352 f16_div_rd.tv
-      46464   185856   836352 f16_div_rne.tv
-      46464   185856   836352 f16_div_ru.tv
-      46464   185856   836352 f16_div_rz.tv
-      46464   185856   836352 f16_mul_rd.tv
-      46464   185856   836352 f16_mul_rne.tv
-      46464   185856   836352 f16_mul_ru.tv
-      46464   185856   836352 f16_mul_rz.tv
-        408     1224     5304 f16_sqrt_rd.tv
-        408     1224     5304 f16_sqrt_rne.tv
-        408     1224     5304 f16_sqrt_ru.tv
-        408     1224     5304 f16_sqrt_rz.tv
-      46464   185856   836352 f16_sub_rd.tv
-      46464   185856   836352 f16_sub_rne.tv
-      46464   185856   836352 f16_sub_ru.tv
-      46464   185856   836352 f16_sub_rz.tv
-      46464   185856  1393920 f32_add_rd.tv
-      46464   185856  1393920 f32_add_rne.tv
-      46464   185856  1393920 f32_add_ru.tv
-      46464   185856  1393920 f32_add_rz.tv
-      46464   185856  1068672 f32_cmp_eq_signaling.tv
-      46464   185856  1068672 f32_cmp_eq.tv
-      46464   185856  1068672 f32_cmp_le_quiet.tv
-      46464   185856  1068672 f32_cmp_le.tv
-      46464   185856  1068672 f32_cmp_lt_quiet.tv
-      46464   185856  1068672 f32_cmp_lt.tv
-      46464   185856  1393920 f32_div_rd.tv
-      46464   185856  1393920 f32_div_rne.tv
-      46464   185856  1393920 f32_div_ru.tv
-      46464   185856  1393920 f32_div_rz.tv
-        600     1800    17400 f32_f64_rd.tv
-        600     1800    17400 f32_f64_rne.tv
-        600     1800    17400 f32_f64_ru.tv
-        600     1800    17400 f32_f64_rz.tv
-        600     1800    12600 f32_i32_rd.tv
-        600     1800    12600 f32_i32_rne.tv
-        600     1800    12600 f32_i32_ru.tv
-        600     1800    12600 f32_i32_rz.tv
-        600     1800    17400 f32_i64_rd.tv
-        600     1800    17400 f32_i64_rne.tv
-        600     1800    17400 f32_i64_ru.tv
-        600     1800    17400 f32_i64_rz.tv
-      46464   185856  1393920 f32_mul_rd.tv
-      46464   185856  1393920 f32_mul_rne.tv
-      46464   185856  1393920 f32_mul_ru.tv
-      46464   185856  1393920 f32_mul_rz.tv
-        600     1800    12600 f32_sqrt_rd.tv
-        600     1800    12600 f32_sqrt_rne.tv
-        600     1800    12600 f32_sqrt_ru.tv
-        600     1800    12600 f32_sqrt_rz.tv
-      46464   185856  1393920 f32_sub_rd.tv
-      46464   185856  1393920 f32_sub_rne.tv
-      46464   185856  1393920 f32_sub_ru.tv
-      46464   185856  1393920 f32_sub_rz.tv
-        600     1800    12600 f32_ui32_rd.tv
-        600     1800    12600 f32_ui32_rne.tv
-        600     1800    12600 f32_ui32_ru.tv
-        600     1800    12600 f32_ui32_rz.tv
-        600     1800    17400 f32_ui64_rd.tv
-        600     1800    17400 f32_ui64_rne.tv
-        600     1800    17400 f32_ui64_ru.tv
-        600     1800    17400 f32_ui64_rz.tv
-      46464   185856  2509056 f64_add_rd.tv
-      46464   185856  2509056 f64_add_rne.tv
-      46464   185856  2509056 f64_add_ru.tv
-      46464   185856  2509056 f64_add_rz.tv
-      46464   185856  1812096 f64_cmp_eq_signaling.tv
-      46464   185856  1812096 f64_cmp_eq.tv
-      46464   185856  1812096 f64_cmp_le_quiet.tv
-      46464   185856  1812096 f64_cmp_le.tv
-      46464   185856  1812096 f64_cmp_lt_quiet.tv
-      46464   185856  1812096 f64_cmp_lt.tv
-      46464   185856  2509056 f64_div_rd.tv
-      46464   185856  2509056 f64_div_rne.tv
-      46464   185856  2509056 f64_div_ru.tv
-      46464   185856  2509056 f64_div_rz.tv
-        768     2304    22272 f64_f32_rd.tv
-        768     2304    22272 f64_f32_rne.tv
-        768     2304    22272 f64_f32_ru.tv
-        768     2304    22272 f64_f32_rz.tv
-        768     2304    22272 f64_i32_rd.tv
-        768     2304    22272 f64_i32_rne.tv
-        768     2304    22272 f64_i32_ru.tv
-        768     2304    22272 f64_i32_rz.tv
-        768     2304    28416 f64_i64_rd.tv
-        768     2304    28416 f64_i64_rne.tv
-        768     2304    28416 f64_i64_ru.tv
-        768     2304    28416 f64_i64_rz.tv
-      46464   185856  2509056 f64_mul_rd.tv
-      46464   185856  2509056 f64_mul_rne.tv
-      46464   185856  2509056 f64_mul_ru.tv
-      46464   185856  2509056 f64_mul_rz.tv
-        768     2304    28416 f64_sqrt_rd.tv
-        768     2304    28416 f64_sqrt_rne.tv
-        768     2304    28416 f64_sqrt_ru.tv
-        768     2304    28416 f64_sqrt_rz.tv
-      46464   185856  2509056 f64_sub_rd.tv
-      46464   185856  2509056 f64_sub_rne.tv
-      46464   185856  2509056 f64_sub_ru.tv
-      46464   185856  2509056 f64_sub_rz.tv
-        768     2304    22272 f64_ui32_rd.tv
-        768     2304    22272 f64_ui32_rne.tv
-        768     2304    22272 f64_ui32_ru.tv
-        768     2304    22272 f64_ui32_rz.tv
-        768     2304    28416 f64_ui64_rd.tv
-        768     2304    28416 f64_ui64_rne.tv
-        768     2304    28416 f64_ui64_ru.tv
-        768     2304    28416 f64_ui64_rz.tv
-        372     1116     7812 i32_f32_rd.tv
-        372     1116     7812 i32_f32_rne.tv
-        372     1116     7812 i32_f32_ru.tv
-        372     1116     7812 i32_f32_rz.tv
-        372     1116    10788 i32_f64_rd.tv
-        372     1116    10788 i32_f64_rne.tv
-        372     1116    10788 i32_f64_ru.tv
-        372     1116    10788 i32_f64_rz.tv
-        756     2268    21924 i64_f32_rd.tv
-        756     2268    21924 i64_f32_rne.tv
-        756     2268    21924 i64_f32_ru.tv
-        756     2268    21924 i64_f32_rz.tv
-        756     2268    27972 i64_f64_rd.tv
-        756     2268    27972 i64_f64_rne.tv
-        756     2268    27972 i64_f64_ru.tv
-        756     2268    27972 i64_f64_rz.tv
-        372     1116     7812 ui32_f32_rd.tv
-        372     1116     7812 ui32_f32_rne.tv
-        372     1116     7812 ui32_f32_ru.tv
-        372     1116     7812 ui32_f32_rz.tv
-        372     1116    10788 ui32_f64_rd.tv
-        372     1116    10788 ui32_f64_rne.tv
-        372     1116    10788 ui32_f64_ru.tv
-        372     1116    10788 ui32_f64_rz.tv
-        756     2268    21924 ui64_f32_rd.tv
-        756     2268    21924 ui64_f32_rne.tv
-        756     2268    21924 ui64_f32_ru.tv
-        756     2268    21924 ui64_f32_rz.tv
-        756     2268    27972 ui64_f64_rd.tv
-        756     2268    27972 ui64_f64_rne.tv
-        756     2268    27972 ui64_f64_ru.tv
-        756     2268    27972 ui64_f64_rz.tv
-    2840352 11308896 94651296 total
+   46464   185856   836352 f16_add_rd.tv
+   46464   185856   836352 f16_add_rne.tv
+   46464   185856   836352 f16_add_ru.tv
+   46464   185856   836352 f16_add_rz.tv
+   46464   185856   836352 f16_div_rd.tv
+   46464   185856   836352 f16_div_rne.tv
+   46464   185856   836352 f16_div_ru.tv
+   46464   185856   836352 f16_div_rz.tv
+   46464   185856   836352 f16_mul_rd.tv
+   46464   185856   836352 f16_mul_rne.tv
+   46464   185856   836352 f16_mul_ru.tv
+   46464   185856   836352 f16_mul_rz.tv
+     408     1224     5304 f16_sqrt_rd.tv
+     408     1224     5304 f16_sqrt_rne.tv
+     408     1224     5304 f16_sqrt_ru.tv
+     408     1224     5304 f16_sqrt_rz.tv
+   46464   185856   836352 f16_sub_rd.tv
+   46464   185856   836352 f16_sub_rne.tv
+   46464   185856   836352 f16_sub_ru.tv
+   46464   185856   836352 f16_sub_rz.tv
+   46464   185856  1393920 f32_add_rd.tv
+   46464   185856  1393920 f32_add_rne.tv
+   46464   185856  1393920 f32_add_ru.tv
+   46464   185856  1393920 f32_add_rz.tv
+   46464   185856  1068672 f32_cmp_eq_signaling.tv
+   46464   185856  1068672 f32_cmp_eq.tv
+   46464   185856  1068672 f32_cmp_le_quiet.tv
+   46464   185856  1068672 f32_cmp_le.tv
+   46464   185856  1068672 f32_cmp_lt_quiet.tv
+   46464   185856  1068672 f32_cmp_lt.tv
+   46464   185856  1393920 f32_div_rd.tv
+   46464   185856  1393920 f32_div_rne.tv
+   46464   185856  1393920 f32_div_ru.tv
+   46464   185856  1393920 f32_div_rz.tv
+     600     1800    17400 f32_f64_rd.tv
+     600     1800    17400 f32_f64_rne.tv
+     600     1800    17400 f32_f64_ru.tv
+     600     1800    17400 f32_f64_rz.tv
+     600     1800    12600 f32_i32_rd.tv
+     600     1800    12600 f32_i32_rne.tv
+     600     1800    12600 f32_i32_ru.tv
+     600     1800    12600 f32_i32_rz.tv
+     600     1800    17400 f32_i64_rd.tv
+     600     1800    17400 f32_i64_rne.tv
+     600     1800    17400 f32_i64_ru.tv
+     600     1800    17400 f32_i64_rz.tv
+   46464   185856  1393920 f32_mul_rd.tv
+   46464   185856  1393920 f32_mul_rne.tv
+   46464   185856  1393920 f32_mul_ru.tv
+   46464   185856  1393920 f32_mul_rz.tv
+     600     1800    12600 f32_sqrt_rd.tv
+     600     1800    12600 f32_sqrt_rne.tv
+     600     1800    12600 f32_sqrt_ru.tv
+     600     1800    12600 f32_sqrt_rz.tv
+   46464   185856  1393920 f32_sub_rd.tv
+   46464   185856  1393920 f32_sub_rne.tv
+   46464   185856  1393920 f32_sub_ru.tv
+   46464   185856  1393920 f32_sub_rz.tv
+     600     1800    12600 f32_ui32_rd.tv
+     600     1800    12600 f32_ui32_rne.tv
+     600     1800    12600 f32_ui32_ru.tv
+     600     1800    12600 f32_ui32_rz.tv
+     600     1800    17400 f32_ui64_rd.tv
+     600     1800    17400 f32_ui64_rne.tv
+     600     1800    17400 f32_ui64_ru.tv
+     600     1800    17400 f32_ui64_rz.tv
+   46464   185856  2509056 f64_add_rd.tv
+   46464   185856  2509056 f64_add_rne.tv
+   46464   185856  2509056 f64_add_ru.tv
+   46464   185856  2509056 f64_add_rz.tv
+   46464   185856  1812096 f64_cmp_eq_signaling.tv
+   46464   185856  1812096 f64_cmp_eq.tv
+   46464   185856  1812096 f64_cmp_le_quiet.tv
+   46464   185856  1812096 f64_cmp_le.tv
+   46464   185856  1812096 f64_cmp_lt_quiet.tv
+   46464   185856  1812096 f64_cmp_lt.tv
+   46464   185856  2509056 f64_div_rd.tv
+   46464   185856  2509056 f64_div_rne.tv
+   46464   185856  2509056 f64_div_ru.tv
+   46464   185856  2509056 f64_div_rz.tv
+     768     2304    22272 f64_f32_rd.tv
+     768     2304    22272 f64_f32_rne.tv
+     768     2304    22272 f64_f32_ru.tv
+     768     2304    22272 f64_f32_rz.tv
+     768     2304    22272 f64_i32_rd.tv
+     768     2304    22272 f64_i32_rne.tv
+     768     2304    22272 f64_i32_ru.tv
+     768     2304    22272 f64_i32_rz.tv
+     768     2304    28416 f64_i64_rd.tv
+     768     2304    28416 f64_i64_rne.tv
+     768     2304    28416 f64_i64_ru.tv
+     768     2304    28416 f64_i64_rz.tv
+   46464   185856  2509056 f64_mul_rd.tv
+   46464   185856  2509056 f64_mul_rne.tv
+   46464   185856  2509056 f64_mul_ru.tv
+   46464   185856  2509056 f64_mul_rz.tv
+     768     2304    28416 f64_sqrt_rd.tv
+     768     2304    28416 f64_sqrt_rne.tv
+     768     2304    28416 f64_sqrt_ru.tv
+     768     2304    28416 f64_sqrt_rz.tv
+   46464   185856  2509056 f64_sub_rd.tv
+   46464   185856  2509056 f64_sub_rne.tv
+   46464   185856  2509056 f64_sub_ru.tv
+   46464   185856  2509056 f64_sub_rz.tv
+     768     2304    22272 f64_ui32_rd.tv
+     768     2304    22272 f64_ui32_rne.tv
+     768     2304    22272 f64_ui32_ru.tv
+     768     2304    22272 f64_ui32_rz.tv
+     768     2304    28416 f64_ui64_rd.tv
+     768     2304    28416 f64_ui64_rne.tv
+     768     2304    28416 f64_ui64_ru.tv
+     768     2304    28416 f64_ui64_rz.tv
+     372     1116     7812 i32_f32_rd.tv
+     372     1116     7812 i32_f32_rne.tv
+     372     1116     7812 i32_f32_ru.tv
+     372     1116     7812 i32_f32_rz.tv
+     372     1116    10788 i32_f64_rd.tv
+     372     1116    10788 i32_f64_rne.tv
+     372     1116    10788 i32_f64_ru.tv
+     372     1116    10788 i32_f64_rz.tv
+     756     2268    21924 i64_f32_rd.tv
+     756     2268    21924 i64_f32_rne.tv
+     756     2268    21924 i64_f32_ru.tv
+     756     2268    21924 i64_f32_rz.tv
+     756     2268    27972 i64_f64_rd.tv
+     756     2268    27972 i64_f64_rne.tv
+     756     2268    27972 i64_f64_ru.tv
+     756     2268    27972 i64_f64_rz.tv
+     372     1116     7812 ui32_f32_rd.tv
+     372     1116     7812 ui32_f32_rne.tv
+     372     1116     7812 ui32_f32_ru.tv
+     372     1116     7812 ui32_f32_rz.tv
+     372     1116    10788 ui32_f64_rd.tv
+     372     1116    10788 ui32_f64_rne.tv
+     372     1116    10788 ui32_f64_ru.tv
+     372     1116    10788 ui32_f64_rz.tv
+     756     2268    21924 ui64_f32_rd.tv
+     756     2268    21924 ui64_f32_rne.tv
+     756     2268    21924 ui64_f32_ru.tv
+     756     2268    21924 ui64_f32_rz.tv
+     756     2268    27972 ui64_f64_rd.tv
+     756     2268    27972 ui64_f64_rne.tv
+     756     2268    27972 ui64_f64_ru.tv
+     756     2268    27972 ui64_f64_rz.tv
+ 2840352 11308896 94651296 total
 
diff --git a/tests/fp/combined_IF_vectors/IF_vectors/README b/tests/fp/combined_IF_vectors/IF_vectors/README
deleted file mode 100644
index bfbf368dd..000000000
--- a/tests/fp/combined_IF_vectors/IF_vectors/README
+++ /dev/null
@@ -1,4 +0,0 @@
-This folder holds the archtest and testfloat vectors necessary fo evaluating performance
-of standalone intdiv vs combined IFdivsqrt
-
-to generate vectors, uncomment line 8 in create_all_vectors.sh
\ No newline at end of file
diff --git a/tests/fp/combined_IF_vectors/create_IF_vectors.sh b/tests/fp/combined_IF_vectors/create_IF_vectors.sh
deleted file mode 100755
index 707b2d5f4..000000000
--- a/tests/fp/combined_IF_vectors/create_IF_vectors.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/sh
-# create test vectors for stand alone int
-
-./extract_testfloat_vectors.py
-./extract_arch_vectors.py
diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
deleted file mode 100755
index b1cd7205a..000000000
--- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py
+++ /dev/null
@@ -1,307 +0,0 @@
-#!/usr/bin/env python3
-
-# author: Alessandro Maiuolo, Kevin Kim
-# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
-# date created: 3-29-2023
-
-# extract all arch test vectors
-import os
-
-wally = os.popen('echo $WALLY').read().strip()
-
-def ext_bits(my_string):
-    target_len = 32 # we want 128 bits, div by 4 bc hex notation
-    zeroes_to_add = target_len - len(my_string)
-    return zeroes_to_add*"0" + my_string
-
-def twos_comp(b, x):
-    if b == 32:
-        return hex(0x100000000 - int(x,16))[2:]
-    elif b == 64:
-        return hex(0x10000000000000000 - int(x,16))[2:]
-    else:
-        return "UNEXPECTED_BITSIZE"
-
-def unpack_rf(packed):
-    bin_u = bin(int(packed, 16))[2:].zfill(8) # translate to binary
-    flags = hex(int(bin_u[3:],2))[2:].zfill(2)
-    rounding_mode = hex(int(bin_u[:3],2))[2:]
-    return flags, rounding_mode
-
-# rounding mode dictionary
-round_dict = {
-    "rne":"0",
-    "rnm":"4",
-    "ru":"3",
-    "rz":"1",
-    "rd":"2",
-    "dyn":"7"
-}
-
-# fcsr dictionary
-fcsr_dict = {
-    "0":"rne",
-    "128":"rnm",
-    "96":"ru",
-    "32":"rz",
-    "64":"rd",
-    "224":"dyn"
-}
-
-print("creating arch test vectors")
-
-class Config:
-  def __init__(self, bits, letter, op, filt, op_code):
-    self.bits = bits
-    self.letter = letter
-    self.op = op
-    self.filt = filt
-    self.op_code = op_code
-
-def create_vectors(my_config):
-    suite_folder_num = my_config.bits
-    if my_config.bits == 64 and my_config.letter == "F": suite_folder_num = 32
-    source_dir1 = f"{wally}/addins/riscv-arch-test/riscv-test-suite/rv{suite_folder_num}i_m/{my_config.letter}/src/"
-    source_dir2 = f"{wally}/tests/riscof/work/riscv-arch-test/rv{my_config.bits}i_m/{my_config.letter}/src/"
-    dest_dir = f"{wally}/tests/fp/combined_IF_vectors/IF_vectors/"
-    all_vectors1 = os.listdir(source_dir1)
-
-    filt_vectors1 = [v for v in all_vectors1 if my_config.filt in v]
-    # print(filt_vectors1)
-    filt_vectors2 = [v + "/ref/Reference-sail_c_simulator.signature" for v in all_vectors1 if my_config.filt in v]
-
-    # iterate through all vectors
-    for i in range(len(filt_vectors1)):
-        vector1 = filt_vectors1[i]
-        vector2 = filt_vectors2[i]
-        operation = my_config.op_code
-        rounding_mode = "X"
-        flags = "XX"
-        # use name to create our new tv and open vectors
-        with open(f"{dest_dir}cvw_{my_config.bits}_{vector1[:-2]}.tv", 'w') as dest_file, open(source_dir1 + vector1) as src_file1, open(source_dir2 + vector2) as src_file2:
-            # for each test in the vector
-            reading = True
-            src_file2.readline() #skip first bc junk
-            # print(my_config.bits, my_config.letter)
-            if my_config.letter == "F" and my_config.bits == 64:
-                reading = True
-                # print("trigger 64F")
-                #skip first 2 lines bc junk
-                src_file2.readline()
-                while reading:
-                    # get answer and flags from Ref...signature
-                    # answers are before deadbeef (first line of 4)
-                    # flags are after deadbeef (third line of 4)
-                    answer = src_file2.readline().strip()
-                    deadbeef = src_file2.readline().strip()
-                    # print(answer)
-                    if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
-                        # get flags
-                        packed = src_file2.readline().strip()[6:]
-                        flags, rounding_mode = unpack_rf(packed)
-                        # skip 00000000 buffer
-                        src_file2.readline()
-
-                        # parse through .S file
-                        detected = False
-                        done = False
-                        op1val = "0"
-                        op2val = "0"
-                        while not (detected or done):
-                            # print("det1")
-                            line = src_file1.readline()
-                            # print(line)
-                            if "op1val" in line:
-                                # print("det2")
-                                # parse line
-
-                                # handle special case where destination register is hardwired to zero
-                                if "dest:x0" in line:
-                                    answer = "x" * len(answer)
-
-                                op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
-                                if my_config.op != "fsqrt": # sqrt doesn't have two input vals
-                                    op2val = line.split("op2val")[1].split("x")[1].strip()
-                                    if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
-                                else:
-                                    op2val = 32*"X"
-                                # go to next test in vector
-                                detected = True
-                            elif "RVTEST_CODE_END" in line:
-                                done = True
-                        # put it all together
-                        if not done:
-                            translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
-                            dest_file.write(translation + "\n")
-                    else:
-                        # print("read false")
-                        reading = False
-            elif my_config.letter == "M" and my_config.bits == 64:
-                reading = True
-                #skip first 2 lines bc junk
-                src_file2.readline()
-                while reading:
-                    # print("trigger 64M")
-                    # get answer from Ref...signature
-                    # answers span two lines and are reversed
-                    answer2 = src_file2.readline().strip()
-                    answer1 = src_file2.readline().strip()
-                    answer = answer1 + answer2
-                    #print(answer1,answer2)
-                    if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
-                        # parse through .S file
-                        detected = False
-                        done = False
-                        op1val = "0"
-                        op2val = "0"
-                        while not (detected or done):
-                            # print("det1")
-                            line = src_file1.readline()
-                            # print(line)
-                            if "op1val" in line:
-                                # print("det2")
-                                # parse line
-                                # handle special case where destination register is hardwired to zero
-                                if "dest:x0" in line:
-                                    answer = "x" * len(answer)
-                                op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
-                                if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
-                                    op1val = twos_comp(my_config.bits, op1val)
-                                if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
-                                    op2val = line.split("op2val")[1].split("x")[1].strip()
-                                    if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
-                                    if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
-                                        op2val = twos_comp(my_config.bits, op2val)
-                                # go to next test in vector
-                                detected = True
-                            elif "RVTEST_CODE_END" in line:
-                                done = True
-                        # ints don't have flags
-                        flags = "XX"
-                        # put it all together
-                        if not done:
-                            translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
-                            dest_file.write(translation + "\n")
-                    else:
-                        # print("read false")
-                        reading = False
-            elif my_config.letter == "M" and my_config.bits == 32:
-                reading = True
-                while reading:
-                    # print("trigger 64M")
-                    # get answer from Ref...signature
-                    # answers span two lines and are reversed
-                    answer = src_file2.readline().strip()
-                    # print(f"Answer: {answer}")
-                    #print(answer1,answer2)
-                    if answer != '6f5ca309': # if there is still stuff to read
-                        # parse through .S file
-                        detected = False
-                        done = False
-                        op1val = "0"
-                        op2val = "0"
-                        while not (detected or done):
-                            # print("det1")
-                            line = src_file1.readline()
-                            # print(line)
-                            if "op1val" in line:
-                                # print("det2")
-                                # parse line
-                                # handle special case where destination register is hardwired to zero
-                                if "dest:x0" in line: 
-                                    answer = "x" * len(answer)
-                                op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
-                                if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
-                                    op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
-                                if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
-                                    op1val = twos_comp(my_config.bits, op1val)
-                                if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
-                                    op2val = line.split("op2val")[1].split("x")[1].strip()
-                                    if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
-                                    if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
-                                        op2val = twos_comp(my_config.bits, op2val)
-                                # go to next test in vector
-                                detected = True
-                            elif "RVTEST_CODE_END" in line:
-                                done = True
-                        # ints don't have flags
-                        flags = "XX"
-                        # put it all together
-                        if not done:
-                            translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags.strip()}_{rounding_mode}"
-                            dest_file.write(translation + "\n")
-                    else:
-                        # print("read false")
-                        reading = False 
-            else:
-                while reading:
-                    # get answer and flags from Ref...signature
-                    answer = src_file2.readline()
-                    #print(answer)
-                    packed = src_file2.readline()[6:]
-                    #print("Packed: ", packed)
-                    if len(packed.strip())>0: # if there is still stuff to read
-                        # print("packed")
-                        # parse through .S file
-                        detected = False
-                        done = False
-                        op1val = "0"
-                        op2val = "0"
-                        while not (detected or done):
-                            # print("det1")
-                            line = src_file1.readline()
-                            # print(line)
-                            if "op1val" in line:
-                                # print("det2")
-                                # parse line
-
-                                # handle special case where destination register is hardwired to zero
-                                if "dest:x0" in line: 
-                                    answer = "x" * len(answer)
-
-                                op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
-                                if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
-                                    op1val = twos_comp(my_config.bits, op1val)
-                                if my_config.op != "fsqrt": # sqrt doesn't have two input vals
-                                    op2val = line.split("op2val")[1].split("x")[1].strip()
-                                    if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
-                                    if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
-                                        op2val = twos_comp(my_config.bits, op2val)
-                                # go to next test in vector
-                                detected = True
-                            elif "RVTEST_CODE_END" in line:
-                                done = True
-                        # rounding mode for float
-                        if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
-                            flags, rounding_mode = unpack_rf(packed)
-                        
-                        # put it all together
-                        if not done:
-                            translation = f"{operation}_{ext_bits(op1val)}_{ext_bits(op2val)}_{ext_bits(answer.strip())}_{flags}_{rounding_mode}"
-                            dest_file.write(translation + "\n")
-                    else:
-                        # print("read false")
-                        reading = False
-            # print("out")
-
-config_list = [
-Config(32, "M", "div", "div-", 0),
-Config(32, "F", "fdiv", "fdiv", 1),
-Config(32, "F", "fsqrt", "fsqrt", 2),
-Config(32, "M", "rem", "rem-", 3),
-Config(32, "M", "divu", "divu-", 4),
-Config(32, "M", "remu", "remu-", 5),
-Config(64, "M", "div", "div-", 0),
-Config(64, "F", "fdiv", "fdiv", 1),
-Config(64, "F", "fsqrt", "fsqrt", 2),
-Config(64, "M", "rem", "rem-", 3),
-Config(64, "M", "divu", "divu-", 4),
-Config(64, "M", "remu", "remu-", 5),
-Config(64, "M", "divw", "divw-", 6),
-Config(64, "M", "divuw", "divuw-", 7),
-Config(64, "M", "remw", "remw-", 8),
-Config(64, "M", "remuw", "remuw-", 9)
-]
-
-for c in config_list:
-    create_vectors(c)
diff --git a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py b/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
deleted file mode 100755
index 12d55e71c..000000000
--- a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
+++ /dev/null
@@ -1,72 +0,0 @@
-#!/usr/bin/env python3
-# extract sqrt and float div testfloat vectors
-
-# author: Alessandro Maiuolo
-# contact: amaiuolo@g.hmc.edu
-# date created: 3-29-2023
-
-import os
-
-wally = os.popen('echo $WALLY').read().strip()
-# print(wally)
-
-def ext_bits(my_string):
-    target_len = 32 # we want 128 bits, div by 4 bc hex notation
-    zeroes_to_add = target_len - len(my_string)
-    return zeroes_to_add*"0" + my_string
-
-# rounding mode dictionary
-round_dict = {
-    "rne":"0",
-    "rnm":"4",
-    "ru":"3",
-    "rz":"1",
-    "rd":"2",
-    "dyn":"7"
-}
-
-
-print("creating testfloat div test vectors")
-
-source_dir = f"{wally}/tests/fp/vectors/"
-dest_dir = f"{wally}/tests/fp/combined_IF_vectors/IF_vectors/"
-all_vectors = os.listdir(source_dir)
-
-div_vectors = [v for v in all_vectors if "div" in v]
-
-# iterate through all float div vectors
-for vector in div_vectors:
-    # use name to determine configs
-    config_list = vector.split(".")[0].split("_")
-    operation = "1" #float div
-    rounding_mode = round_dict[str(config_list[2])]
-    # use name to create our new tv and open vector
-    with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
-        # for each test in the vector
-        for i in src_file.readlines():
-            translation = "" # this stores the test that we are currently working on
-            [input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
-            # put it all together, strip nec for removing \n on the end of the flags
-            translation = f"{operation}_{ext_bits(input_1)}_{ext_bits(input_2)}_{ext_bits(answer)}_{flags.strip()}_{rounding_mode}"
-            dest_file.write(translation + "\n")
-
-
-print("creating testfloat sqrt test vectors")
-
-sqrt_vectors = [v for v in all_vectors if "sqrt" in v]
-
-# iterate through all float div vectors
-for vector in sqrt_vectors:
-    # use name to determine configs
-    config_list = vector.split(".")[0].split("_")
-    operation = "2" #sqrt
-    rounding_mode = round_dict[str(config_list[2])]
-    # use name to create our new tv and open vector    
-    with open(dest_dir + "cvw_" + vector, 'a') as dest_file, open(source_dir + vector) as src_file:
-        # for each test in the vector
-        for i in src_file.readlines():
-            translation = "" # this stores the test that we are currently working on
-            [input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
-            # put it all together, strip nec for removing \n on the end of the flags
-            translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
-            dest_file.write(translation + "\n")
diff --git a/tests/fp/create_all_vectors.sh b/tests/fp/create_all_vectors.sh
new file mode 100755
index 000000000..f1ba3625c
--- /dev/null
+++ b/tests/fp/create_all_vectors.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+mkdir -p vectors
+./create_vectors.sh
+./remove_spaces.sh
diff --git a/tests/fp/create_vectors.sh b/tests/fp/create_vectors.sh
new file mode 100755
index 000000000..3ca574fc8
--- /dev/null
+++ b/tests/fp/create_vectors.sh
@@ -0,0 +1,483 @@
+#!/bin/sh
+BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
+OUTPUT="./vectors"
+echo "Creating ui32_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv
+echo "Creating ui32_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv
+echo "Creating ui32_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv
+echo "Creating ui32_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv
+echo "Creating ui64_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv
+echo "Creating ui64_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv
+echo "Creating ui64_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv
+echo "Creating ui64_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv
+echo "Creating i32_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv
+echo "Creating i32_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv
+echo "Creating i32_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv
+echo "Creating i32_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv
+echo "Creating i64_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv
+echo "Creating i64_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv
+echo "Creating i64_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv
+echo "Creating i64_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv
+echo "Creating f16_to_ui32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv
+echo "Creating f32_to_ui32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv
+echo "Creating f64_to_ui32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv
+echo "Creating f128_to_ui32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv
+echo "Creating f16_to_ui64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv
+echo "Creating f32_to_ui64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv
+echo "Creating f64_to_ui64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv
+echo "Creating f128_to_ui64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv
+echo "Creating f16_to_i32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv
+echo "Creating f32_to_i32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv
+echo "Creating f64_to_i32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv
+echo "Creating f128_to_i32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv
+echo "Creating f16_to_i64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv
+echo "Creating f32_to_i64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv
+echo "Creating f64_to_i64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv
+echo "Creating f128_to_i64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv
+echo "Creating f16_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv
+echo "Creating f16_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv
+echo "Creating f16_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv
+echo "Creating f32_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv
+echo "Creating f32_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv
+echo "Creating f32_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv
+echo "Creating f64_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv
+echo "Creating f64_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv
+echo "Creating f64_to_f128 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv
+echo "Creating f128_to_f16 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv
+echo "Creating f128_to_f32 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv
+echo "Creating f128_to_f64 convert vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv
+echo "Creating f16_add vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv
+echo "Creating f32_add vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv
+echo "Creating f64_add vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv
+echo "Creating f128_add vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv
+echo "Creating f16_sub vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv
+echo "Creating f32_sub vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv
+echo "Creating f64_sub vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv
+echo "Creating f128_sub vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv
+echo "Creating f16_mul vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv
+echo "Creating f32_mul vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv
+echo "Creating f64_mul vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv
+echo "Creating f128_mul vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv
+echo "Creating f16_div vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv
+echo "Creating f32_div vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv
+echo "Creating f64_div vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv
+echo "Creating f128_div vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv
+echo "Creating f16_sqrt vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv
+echo "Creating f32_sqrt vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv
+echo "Creating f64_sqrt vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv
+echo "Creating f128_sqrt vectors"
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv
+echo "Creating f16_eq vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv
+echo "Creating f32_eq vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv
+echo "Creating f64_eq vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv
+echo "Creating f128_eq vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv
+echo "Creating f16_le vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv
+echo "Creating f32_le vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv
+echo "Creating f64_le vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv
+echo "Creating f128_le vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv
+echo "Creating f16_lt vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv
+echo "Creating f32_lt vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv
+echo "Creating f64_lt vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv
+echo "Creating f128_lt vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv
+echo "Creating f16_mulAdd vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv
+echo "Creating f32_mulAdd vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv
+echo "Creating f64_mulAdd vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv
+echo "Creating f128_mulAdd vectors"
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv
+$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv
diff --git a/tests/fp/remove_spaces.sh b/tests/fp/remove_spaces.sh
new file mode 100755
index 000000000..ed6106fd6
--- /dev/null
+++ b/tests/fp/remove_spaces.sh
@@ -0,0 +1,483 @@
+#!/bin/sh
+BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC"
+OUTPUT="./vectors"
+echo "Editing ui32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv
+echo "Editing ui32_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv
+echo "Editing ui32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv
+echo "Editing ui32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv
+echo "Editing ui64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv
+echo "Editing ui64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv
+echo "Editing ui64_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv
+echo "Editing ui64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv
+echo "Editing i32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv
+echo "Editing i32_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv
+echo "Editing i32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv
+echo "Editing i32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv
+echo "Editing i64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv
+echo "Editing i64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv
+echo "Editing i64_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv
+echo "Editing i64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv
+echo "Editing f16_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv
+echo "Editing f32_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv
+echo "Editing f64_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv
+echo "Editing f128_to_ui32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv
+echo "Editing f16_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv
+echo "Editing f32_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv
+echo "Editing f64_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv
+echo "Editing f128_to_ui64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv
+echo "Editing f16_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv
+echo "Editing f32_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv
+echo "Editing f64_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv
+echo "Editing f128_to_i32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv
+echo "Editing f16_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv
+echo "Editing f32_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv
+echo "Editing f64_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv
+echo "Editing f128_to_i64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv
+echo "Editing f16_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv
+echo "Editing f16_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv
+echo "Editing f16_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv
+echo "Editing f32_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv
+echo "Editing f32_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv
+echo "Editing f32_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv
+echo "Editing f64_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv
+echo "Editing f64_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv
+echo "Editing f64_to_f128 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv
+echo "Editing f128_to_f16 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv
+echo "Editing f128_to_f32 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv
+echo "Editing f128_to_f64 test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv
+echo "Editing f16_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv
+echo "Editing f32_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv
+echo "Editing f64_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv
+echo "Editing f128_add test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv
+echo "Editing f16_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv
+echo "Editing f32_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv
+echo "Editing f64_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv
+echo "Editing f128_sub test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv
+echo "Editing f16_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv
+echo "Editing f32_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv
+echo "Editing f64_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv
+echo "Editing f128_mul test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv
+echo "Editing f16_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv
+echo "Editing f32_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv
+echo "Editing f64_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv
+echo "Editing f128_div test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv
+echo "Editing f16_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv
+echo "Editing f32_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv
+echo "Editing f64_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv
+echo "Editing f128_sqrt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv
+echo "Editing f16_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv
+echo "Editing f32_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv
+echo "Editing f64_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv
+echo "Editing f128_eq test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv
+echo "Editing f16_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv
+echo "Editing f32_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv
+echo "Editing f64_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv
+echo "Editing f128_le test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv
+echo "Editing f16_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv
+echo "Editing f32_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv
+echo "Editing f64_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv
+echo "Editing f128_lt test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv
+echo "Editing f16_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv
+echo "Editing f32_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv
+echo "Editing f64_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv
+echo "Editing f128_mulAdd test vectors"
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv
+sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv
diff --git a/tests/fp/vectors/Makefile b/tests/fp/vectors/Makefile
deleted file mode 100755
index 5db3aa5ab..000000000
--- a/tests/fp/vectors/Makefile
+++ /dev/null
@@ -1,75 +0,0 @@
-# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
-# Makefile to generate RISCV floating point testvectors for CORE-V-Wally
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-.DELETE_ON_ERROR:
-.ONESHELL:
-SHELL := /bin/bash
-
-TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
-TESTFLOAT_GEN := ${TESTFLOAT_DIR}/testfloat_gen
-
-# List of testvectors to generate. Each rounding mode will be generated for each test.
-cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
-          ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
-          i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
-          i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
-          f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
-          f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
-cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
-         f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
-         f16_to_f32 f16_to_f64 f16_to_f128 \
-         f32_to_f16 f32_to_f64 f32_to_f128 \
-         f64_to_f16 f64_to_f32 f64_to_f128 \
-         f128_to_f16 f128_to_f32 f128_to_f64
-add := f16_add f32_add f64_add f128_add
-sub := f16_sub f32_sub f64_sub f128_sub
-mul := f16_mul f32_mul f64_mul f128_mul
-div := f16_div f32_div f64_div f128_div
-sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
-eq := f16_eq f32_eq f64_eq f128_eq
-le := f16_le f32_le f64_le f128_le
-lt := f16_lt f32_lt f64_lt f128_lt
-mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
-
-tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
-
-# Set rounding modes and extensions
-rne: ROUND_MODE := rnear_even
-rne: ROUND_EXT  := rne
-rz: ROUND_MODE  := rminMag
-rz: ROUND_EXT   := rz
-ru: ROUND_MODE  := rmax
-ru: ROUND_EXT   := ru
-rd: ROUND_MODE  := rmin
-rd: ROUND_EXT   := rd
-rnm: ROUND_MODE := rnear_maxMag
-rnm: ROUND_EXT  := rnm
-
-.PHONY: all rne rz ru rd rnm clean
-
-# Generate all test vectors
-all: rne rz ru rd rnm
-
-# Generate test vectors for each rounding mode
-rne: $(addsuffix _rne.tv, $(tests))
-rz: $(addsuffix _rz.tv, $(tests))
-ru: $(addsuffix _ru.tv, $(tests))
-rd: $(addsuffix _rd.tv, $(tests))
-rnm: $(addsuffix _rnm.tv, $(tests))
-
-# Rule to generate individual test vectors
-%.tv: ${TESTFLOAT_GEN}
-	@echo Creating $@ vectors
-	@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
-	@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
-	${TESTFLOAT_GEN}  -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
-	@sed -i 's/ /_/g' $@
-
-# Generate TestFloat first if necessary
-${TESTFLOAT_GEN}:
-	$(MAKE) -C ${WALLY}/tests/fp testfloat
-
-clean:
-	rm -f *.tv
-	rm -f sed*
diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile
index 131d724c4..2918494dd 100644
--- a/tests/riscof/Makefile
+++ b/tests/riscof/Makefile
@@ -1,49 +1,58 @@
-.SECONDEXPANSION:
+arch_dir = ../../addins/riscv-arch-test
+wally_dir = ../wally-riscv-arch-test
+work_dir = ./riscof_work
+work = ./work
+arch_workdir = $(work)/riscv-arch-test
+wally_workdir = $(work)/wally-riscv-arch-test
 
-MAKEFLAGS += --output-sync --no-print-directory
-nproc := $(shell nproc --ignore=1)
+current_dir = $(shell pwd)
+#XLEN    ?= 64
 
-# Directories
-arch_dir := $(WALLY)/addins/riscv-arch-test
-wally_dir := $(WALLY)/tests/wally-riscv-arch-test
-work_dir := ./riscof_work
-work := ./work
-arch_workdir := $(work)/riscv-arch-test
-wally_workdir := $(work)/wally-riscv-arch-test
-current_dir := $(shell pwd)
+#all: root wally32 wally64
+all: root arch32 wally32  wally32e arch64 wally64
 
-# General make rules
-.PHONY: all riscv-arch-test wally-riscv-arch-test quad64 clean
-all: riscv-arch-test wally-riscv-arch-test
-riscv-arch-test: arch32e arch32 arch64
-wally-riscv-arch-test: wally32 wally64
+root:
+	mkdir -p $(work_dir)
+	mkdir -p $(work)
+	mkdir -p $(arch_workdir)
+	mkdir -p $(wally_workdir)
+	sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
+	sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
+	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
 
-# Generate config.ini files
-config%.ini: config.ini
-	sed 's,{0},$(current_dir),g;s,{1},$(patsubst %64,%64gc,$(patsubst %32,%32gc,$*)),g;s,{2},$(nproc),g' config.ini > $@
+arch32:
+	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
 
-# Generate riscv-arch-test targets
-arch%: config$$*.ini | $(work_dir) $(arch_workdir)
-	riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
-	$(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@ BITWIDTH=$(patsubst %32e,%32,$*)
-	rsync -a $(work_dir)/$@/rv*/* $(arch_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed"
+arch64:
+	riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
+#	 Also copy F and D tests to RV64
+	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"  
 
-# Generate wally-riscv-arch-test targets
-wally%: config$$*.ini | $(work_dir) $(wally_workdir)
-	riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
-	$(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@
-	rsync -a $(work_dir)/$@/rv*/* $(wally_workdir)/rv$(patsubst %64,%64i,$(patsubst %32,%32i,$*))_m || echo "error suppressed"
+wally32:
+	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
 
-quad64: config64.ini $(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests | $(work_dir)
-	riscof run --work-dir=$(work_dir)/$@ --config=$< --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env
-	$(MAKE) -f makefile-memfile WORKDIR=$(work_dir)/$@
+wally64:
+	riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
+
+wally32e:
+	riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
+	rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
+
+
+memfile: 
+	find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done
+	find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
+	find $(work) -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
 
 clean:
-	rm -f config??*.ini
+	rm -f config64.ini
+	rm -f config32.ini
+	rm -f config32e.ini
 	rm -rf $(work_dir)
 	rm -rf $(wally_workdir)
 	rm -rf $(arch_workdir)
-	rm -rf $(submodule_wor_dir)
-
-$(work_dir) $(arch_workdir) $(wally_workdir):
-	mkdir -p $@
diff --git a/tests/riscof/config.ini b/tests/riscof/config.ini
index 761021799..ae5a2f13b 100644
--- a/tests/riscof/config.ini
+++ b/tests/riscof/config.ini
@@ -9,9 +9,6 @@ pluginpath={0}/spike
 ispec={0}/spike/spike_rv{1}_isa.yaml
 pspec={0}/spike/spike_platform.yaml
 target_run=1
-# Optional as mentioned in https://riscof.readthedocs.io/en/latest/inputs.html#config-ini-syntax
-jobs={2}
 
 [sail_cSim]
 pluginpath={0}/sail_cSim
-jobs={2}
diff --git a/tests/riscof/makefile-memfile b/tests/riscof/makefile-memfile
deleted file mode 100644
index 6ccdca37c..000000000
--- a/tests/riscof/makefile-memfile
+++ /dev/null
@@ -1,24 +0,0 @@
-WORKDIR	?= $(WALLY)/tests/riscof/work/
-
-ELFFILES	?= $(shell find $(WORKDIR) -type f -regex ".*\.elf")
-OBJDUMPFILES	?= $(shell find $(WORKDIR) -type f -regex ".*\.elf.objdump")
-MEMFILES ?= $(ELFFILES:.elf=.elf.memfile)
-ADDRFILES ?= $(OBJDUMPFILES:.objdump=.objdump.addr)
-
-.PHONY: wally-sim-files
-wally-sim-files: $(MEMFILES) $(ADDRFILES)
-
-# notes to self on how this works.
-# The find command locates all of the *.elf files in directory DIR1.  A list of .memfiles and
-# .addr files are generated from the .elf.  These are used as targets.
-# % is a wildcard in a make target which is then referenced as % in the depenecies and $*
-# in the recipe.
-# because elf2hex requires a bit width we use findstring to figure out if the compiled directory
-# is XLEN=64 or 32. This is hacky and will likely break in the future.
-# the .addr is a separate target so make can split into more jobs and more parallism.
-%.elf.memfile: BITWIDTH ?= $(if $(findstring rv64,$*),64,32)
-%.elf.memfile: %.elf
-	riscv64-unknown-elf-elf2hex --bit-width $(BITWIDTH) --input $< --output $@
-
-%.elf.objdump.addr: %.elf.objdump
-	extractFunctionRadix.sh $<
diff --git a/tests/riscof/sail_cSim/__init__.py b/tests/riscof/sail_cSim/__init__.py
index b36383a61..0bfb5a62b 100644
--- a/tests/riscof/sail_cSim/__init__.py
+++ b/tests/riscof/sail_cSim/__init__.py
@@ -1,3 +1,2 @@
 from pkgutil import extend_path
-
-__path__ = extend_path(__path__, __name__)
+__path__ = extend_path(__path__, __name__)
\ No newline at end of file
diff --git a/tests/riscof/sail_cSim/env/model_test.h b/tests/riscof/sail_cSim/env/model_test.h
index 29c800887..be07d625d 100644
--- a/tests/riscof/sail_cSim/env/model_test.h
+++ b/tests/riscof/sail_cSim/env/model_test.h
@@ -28,8 +28,7 @@
 
 //RV_COMPLIANCE_DATA_END
 #define RVMODEL_DATA_END                                                      \
-  .align 4;\
-  .global end_signature; end_signature:  
+  .align 4; .global end_signature; end_signature:  
 
 //RVTEST_IO_INIT
 #define RVMODEL_IO_INIT
@@ -44,136 +43,13 @@
 //RVTEST_IO_ASSERT_DFPR_EQ
 #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
 
-#define ACCESS_FAULT_ADDRESS 0
-#define CLINT_BASE_ADDR 0x02000000
-#define PLIC_BASE_ADDR 0x0C000000
-#define GPIO_BASE_ADDR 0x10060000
+#define RVMODEL_SET_MSW_INT
 
-#define MTIME           (CLINT_BASE_ADDR + 0xBFF8)
-#define MSIP            (CLINT_BASE_ADDR)
-#define MTIMECMP        (CLINT_BASE_ADDR + 0x4000)
-#define MTIMECMPH       (CLINT_BASE_ADDR + 0x4004)
+#define RVMODEL_CLEAR_MSW_INT
 
-#define THRESHOLD_0     (PLIC_BASE_ADDR + 0x200000)
-#define THRESHOLD_1     (PLIC_BASE_ADDR + 0x201000)
-#define INT_PRIORITY_3  (PLIC_BASE_ADDR + 0x00000C)
-#define INT_EN_00       (PLIC_BASE_ADDR + 0x002000)
-#define INT_EN_10       (PLIC_BASE_ADDR + 0x002080)
+#define RVMODEL_CLEAR_MTIMER_INT
 
-#define GPIO_OUTPUT_EN  (GPIO_BASE_ADDR + 0x08)
-#define GPIO_OUTPUT_VAL (GPIO_BASE_ADDR + 0x0C)
-
-#define RVMODEL_SET_MSW_INT       \
- li t1, 1;                         \
- li t2, 0x2000000;                 \
- sw t1, 0(t2);
-
-#define RVMODEL_CLEAR_MSW_INT     \
- li t2, 0x2000000;                 \
- sw x0, 0(t2);
-
-#define RVMODEL_CLEAR_MTIMER_INT \
- li t0, -1; \
- la t2, MTIMECMP; \
- SREG t0, 0(t2); \
- #ifdef __riscv_xlen \
-     #if __riscv_xlen == 32 \
-         sw t0, 4(t2); \
-     #endif \
- #else \
-     ERROR: __riscv_xlen not defined; \
- #endif
-
-#define RVMODEL_CLEAR_MEXT_INT \
-la t0, THRESHOLD_0; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, THRESHOLD_1; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, INT_PRIORITY_3; \
-sw zero, 0(t0); \
-la t0, INT_EN_00; \
-sw zero, 0(t0); \
-la t0, GPIO_BASE_ADDR; \
-sw zero, 0x18(t0); \
-sw zero, 0x20(t0); \
-sw zero, 0x28(t0); \
-sw zero, 0x30(t0);
-
-#define RVMODEL_CLR_MSW_INT \
-la t0, MSIP; \
-lw t2, 0(t0); \
-andi t2, t2, -2; \
-sw t2, 0(t0);
-
-#define RVMODEL_CLR_MTIMER_INT \
-li t0, -1; \
-la t2, MTIMECMP; \
-SREG t0, 0(t2); \
-#ifdef __riscv_xlen \
-    #if __riscv_xlen == 32 \
-        sw t0, 4(t2); \
-    #endif \
-#else \
-    ERROR: __riscv_xlen not defined; \
-#endif
-
-#define RVMODEL_CLR_MEXT_INT \
-la t0, THRESHOLD_0; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, THRESHOLD_1; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, INT_PRIORITY_3; \
-sw zero, 0(t0); \
-la t0, INT_EN_00; \
-sw zero, 0(t0); \
-la t0, GPIO_BASE_ADDR; \
-sw zero, 0x18(t0); \
-sw zero, 0x20(t0); \
-sw zero, 0x28(t0); \
-sw zero, 0x30(t0);
-
-#define RVMODEL_SET_SSW_INT
-#define RVMODEL_CLR_SSW_INT
-
-#define RVMODEL_MCLR_SSW_INT \
-csrrci t6, mip, 2; 
-
-#define RVMODEL_SCLR_SSW_INT \
-csrrci t6, sip, 2; 
-
-#define RVMODEL_CLR_STIMER_INT
-
-#define RVMODEL_MCLR_STIMER_INT \
-li t0, 32; \
-csrrc t6, mip, t0;
-
-#define RVMODEL_SCLR_STIMER_INT
-
-#define RVMODEL_CLR_SEXT_INT \
-la t0, THRESHOLD_0; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, THRESHOLD_1; \
-li t2, 7; \
-sw t2, 0(t0); \
-la t0, INT_PRIORITY_3; \
-sw zero, 0(t0); \
-la t0, INT_EN_00; \
-sw zero, 0(t0); \
-la t0, GPIO_BASE_ADDR; \
-sw zero, 0x18(t0); \
-sw zero, 0x20(t0); \
-sw zero, 0x28(t0); \
-sw zero, 0x30(t0);
-
-#define RVMODEL_SET_VSW_INT
-#define RVMODEL_CLR_VSW_INT
-#define RVMODEL_CLR_VTIMER_INT
-#define RVMODEL_CLR_VEXT_INT
+#define RVMODEL_CLEAR_MEXT_INT
 
 
 #endif // _COMPLIANCE_MODEL_H
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index 98ab27b4a..aa32757ca 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -1,10 +1,17 @@
-import logging
 import os
 import re
 import shutil
+import subprocess
+import shlex
+import logging
+import random
+import string
+from string import Template
 
 import riscof.utils as utils
 from riscof.pluginTemplate import pluginTemplate
+import riscof.constants as constants
+from riscv_isac.isac import isac
 
 logger = logging.getLogger()
 
@@ -21,8 +28,8 @@ class sail_cSim(pluginTemplate):
             raise SystemExit(1)
         self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
         self.pluginpath = os.path.abspath(config['pluginpath'])
-        self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_rv32d"),
-                '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_rv64d")}
+        self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV32"),
+                '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV64")}
         self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
         self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
         self.make = config['make'] if 'make' in config else 'make'
@@ -45,31 +52,22 @@ class sail_cSim(pluginTemplate):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
-        self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
         self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
-        if "E" in ispec["ISA"]:
-            self.isa += 'e'
         if "M" in ispec["ISA"]:
             self.isa += 'm'
-        if "A" in ispec["ISA"]:
-            self.isa += 'a'
         if "C" in ispec["ISA"]:
             self.isa += 'c'
         if "F" in ispec["ISA"]:
             self.isa += 'f'
         if "D" in ispec["ISA"]:
             self.isa += 'd'
-        if "Zcb" in ispec["ISA"]:   # for some strange reason, Sail requires a command line argument to enable Zcb
-            self.sailargs += "--enable-zcb"
-        if "Q" in ispec["ISA"]:
-            self.isa += 'q'
-        objdump = "riscv64-unknown-elf-objdump"
+        objdump = "riscv64-unknown-elf-objdump".format(self.xlen)
         if shutil.which(objdump) is None:
             logger.error(objdump+": executable not found. Please check environment setup.")
             raise SystemExit(1)
-        compiler = "riscv64-unknown-elf-gcc"
+        compiler = "riscv64-unknown-elf-gcc".format(self.xlen)
         if shutil.which(compiler) is None:
             logger.error(compiler+": executable not found. Please check environment setup.")
             raise SystemExit(1)
@@ -96,7 +94,7 @@ class sail_cSim(pluginTemplate):
 
             execute = "@cd "+testentry['work_dir']+";"
 
-            cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
+            cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
             compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
             execute+=compile_cmd+";"
 
@@ -107,9 +105,9 @@ class sail_cSim(pluginTemplate):
             if ('NO_SAIL=True' in testentry['macros']):
                 # if the tests can't run on SAIL we copy the reference output to the src directory
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
-                execute += f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
+                execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
             else:
-                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step  ' + self.sailargs + f' --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:
@@ -117,10 +115,10 @@ class sail_cSim(pluginTemplate):
 
             if cgf_file is not None:
                 coverage_cmd = 'riscv_isac --verbose info coverage -d \
-                        -t {}.log --parser-name c_sail -o coverage.rpt  \
+                        -t {0}.log --parser-name c_sail -o coverage.rpt  \
                         --sig-label begin_signature  end_signature \
                         --test-label rvtest_code_begin rvtest_code_end \
-                        -e ref.elf -c {} -x{} {};'.format(\
+                        -e ref.elf -c {1} -x{2} {3};'.format(\
                         test_name, ' -c '.join(cgf_file), self.xlen, cov_str)
             else:
                 coverage_cmd = ''
@@ -131,5 +129,4 @@ class sail_cSim(pluginTemplate):
             make.add_target(execute)
 #        make.execute_all(self.work_dir)
 # DH 7/26/22 increase timeout so sim will finish on slow machines
-# DH 5/17/23 increase timeout to 3600 seconds
-        make.execute_all(self.work_dir, timeout = 3600)
+        make.execute_all(self.work_dir, timeout = 1800)
diff --git a/tests/riscof/spike/env/model_test.h b/tests/riscof/spike/env/model_test.h
deleted file mode 120000
index 627598d32..000000000
--- a/tests/riscof/spike/env/model_test.h
+++ /dev/null
@@ -1 +0,0 @@
-../../sail_cSim/env/model_test.h
\ No newline at end of file
diff --git a/tests/riscof/spike/env/model_test.h b/tests/riscof/spike/env/model_test.h
new file mode 100644
index 000000000..3890c4985
--- /dev/null
+++ b/tests/riscof/spike/env/model_test.h
@@ -0,0 +1,60 @@
+#ifndef _COMPLIANCE_MODEL_H
+#define _COMPLIANCE_MODEL_H
+#define RVMODEL_DATA_SECTION \
+        .pushsection .tohost,"aw",@progbits;                            \
+        .align 8; .global tohost; tohost: .dword 0;                     \
+        .align 8; .global fromhost; fromhost: .dword 0;                 \
+        .popsection;                                                    \
+        .align 8; .global begin_regstate; begin_regstate:               \
+        .word 128;                                                      \
+        .align 8; .global end_regstate; end_regstate:                   \
+        .word 4;
+
+//RV_COMPLIANCE_HALT
+#define RVMODEL_HALT                                              \
+  li x1, 1;                                                                   \
+  write_tohost:                                                               \
+    sw x1, tohost, t0;                                                        \
+    j write_tohost;
+
+#define RVMODEL_BOOT
+
+//RV_COMPLIANCE_DATA_BEGIN
+#define RVMODEL_DATA_BEGIN                                              \
+  RVMODEL_DATA_SECTION                                                        \
+  .align 4;\
+  .global begin_signature; begin_signature:
+
+//RV_COMPLIANCE_DATA_END
+#define RVMODEL_DATA_END                                                      \
+  .align 4;\
+  .global end_signature; end_signature:  
+
+//RVTEST_IO_INIT
+#define RVMODEL_IO_INIT
+//RVTEST_IO_WRITE_STR
+#define RVMODEL_IO_WRITE_STR(_R, _STR)
+//RVTEST_IO_CHECK
+#define RVMODEL_IO_CHECK()
+//RVTEST_IO_ASSERT_GPR_EQ
+#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
+//RVTEST_IO_ASSERT_SFPR_EQ
+#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+//RVTEST_IO_ASSERT_DFPR_EQ
+#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#define RVMODEL_SET_MSW_INT       \
+ li t1, 1;                         \
+ li t2, 0x2000000;                 \
+ sw t1, 0(t2);
+
+#define RVMODEL_CLEAR_MSW_INT     \
+ li t2, 0x2000000;                 \
+ sw x0, 0(t2);
+
+#define RVMODEL_CLEAR_MTIMER_INT
+
+#define RVMODEL_CLEAR_MEXT_INT
+
+
+#endif // _COMPLIANCE_MODEL_H
diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py
index ece688241..d7d65c0b3 100644
--- a/tests/riscof/spike/riscof_spike.py
+++ b/tests/riscof/spike/riscof_spike.py
@@ -1,8 +1,16 @@
-import logging
 import os
 import re
+import shutil
+import subprocess
+import shlex
+import logging
+import random
+import string
+from string import Template
+import sys
 
 import riscof.utils as utils
+import riscof.constants as constants
 from riscof.pluginTemplate import pluginTemplate
 
 logger = logging.getLogger()
@@ -89,54 +97,14 @@ class spike(pluginTemplate):
       self.isa = 'rv' + self.xlen
       if "I" in ispec["ISA"]:
           self.isa += 'i'
-      if "E" in ispec["ISA"]:
-          self.isa += 'e'
       if "M" in ispec["ISA"]:
           self.isa += 'm'
-      if "A" in ispec["ISA"]:
-          self.isa += 'a'
       if "F" in ispec["ISA"]:
           self.isa += 'f'
       if "D" in ispec["ISA"]:
           self.isa += 'd'
-      if "Q" in ispec["ISA"]:
-          self.isa += 'q'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
-      if "Zicsr" in ispec["ISA"]:
-          self.isa += '_Zicsr'
-      if "Zicond" in ispec["ISA"]:
-          self.isa += '_Zicond'
-      if "Zicboz" in ispec["ISA"]:
-          self.isa += '_Zicboz'
-      if "Zfa" in ispec["ISA"]:
-          self.isa += '_Zfa'
-      if "Zfh" in ispec["ISA"]:
-          self.isa += '_Zfh'
-      if "Zca" in ispec["ISA"]:
-          self.isa += '_Zca'
-      if "Zcb" in ispec["ISA"]:
-          self.isa += '_Zcb'
-      if "Zba" in ispec["ISA"]:
-          self.isa += '_Zba'
-      if "Zbb" in ispec["ISA"]:
-          self.isa += '_Zbb'
-      if "Zbc" in ispec["ISA"]:
-          self.isa += '_Zbc'
-      if "Zbs" in ispec["ISA"]:
-          self.isa += '_Zbs'
-      if "Zbkb" in ispec["ISA"]:
-          self.isa += '_Zbkb'
-      if "Zbkc" in ispec["ISA"]:
-          self.isa += '_Zbkc'
-      if "Zknd" in ispec["ISA"]:
-          self.isa += '_Zknd'
-      if "Zkne" in ispec["ISA"]:
-          self.isa += '_Zkne'
-      if "Zbkx" in ispec["ISA"]:
-          self.isa += '_Zbkx'
-      if "Zknh" in ispec["ISA"]:
-          self.isa += '_Zknh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately
@@ -183,25 +151,24 @@ class spike(pluginTemplate):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-#          cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros)
-          cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen, test, elf, compile_macros)
+          cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros)
 
-      # if the user wants to disable running the tests and only compile the tests, then
-      # the "else" clause is executed below assigning the sim command to simple no action
-      # echo statement.
+	  # if the user wants to disable running the tests and only compile the tests, then
+	  # the "else" clause is executed below assigning the sim command to simple no action
+	  # echo statement.
           if self.target_run:
             # set up the simulation command. Template is for spike. Please change.
             if ('NO_SAIL=True' in testentry['macros']):
                 # if the tests can't run on SAIL we copy the reference output to the src directory
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
-                simcmd = f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
+                simcmd = 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
             else:
-                simcmd = self.dut_exe + f' --isa={self.isa} +signature={sig_file} +signature-granularity=4 {elf}'
+                simcmd = self.dut_exe + ' --isa={0} +signature={1} +signature-granularity=4 {2}'.format(self.isa, sig_file, elf)
           else:
             simcmd = 'echo "NO RUN"'
 
           # concatenate all commands that need to be executed within a make-target.
-          execute = '@cd {}; {}; {};'.format(testentry['work_dir'], cmd, simcmd)
+          execute = '@cd {0}; {1}; {2};'.format(testentry['work_dir'], cmd, simcmd)
 
           # create a target. The makeutil will create a target with the name "TARGET<num>" where num
           # starts from 0 and increments automatically for each new target that is added
@@ -215,8 +182,7 @@ class spike(pluginTemplate):
       # parallel using the make command set above.
       #make.execute_all(self.work_dir)
       # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines
-      # DH 5/17/23 increase timeout to 3600 seconds
-      make.execute_all(self.work_dir, timeout = 3600) 
+      make.execute_all(self.work_dir, timeout = 1800) 
 
 
       # if target runs are not required then we simply exit as this point after running all
diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml
index ee0aeec11..7ae54347a 100644
--- a/tests/riscof/spike/spike_rv32e_isa.yaml
+++ b/tests/riscof/spike/spike_rv32e_isa.yaml
@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32EMCZicsr_Zifencei_Zbkc
+  ISA: RV32EMFCZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x40001014
+   reset-val: 0x40001034
    rv32:
      accessible: true
      mxl:
diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml
similarity index 59%
rename from tests/riscof/spike/spike_rv32gc_isa.yaml
rename to tests/riscof/spike/spike_rv32imc_isa.yaml
index 435d6cf46..3438e17a0 100644
--- a/tests/riscof/spike/spike_rv32gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32imc_isa.yaml
@@ -1,12 +1,11 @@
 hart_ids: [0]
 hart0:
-#  ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
-  ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
+  ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x4014112D
+   reset-val: 0x4000112D
    rv32:
      accessible: true
      mxl:
@@ -24,6 +23,6 @@ hart0:
            warl:
               dependency_fields: []
               legal:
-                - extensions[25:0] bitmask [0x014112D, 0x0000000]
+                - extensions[25:0] bitmask [0x000112D, 0x0000000]
               wr_illegal:
-                - Unchanged
+                - Unchanged
\ No newline at end of file
diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml
index 1ab1afb8a..a8837ac76 100644
--- a/tests/riscof/spike/spike_rv64gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv64gc_isa.yaml
@@ -1,14 +1,11 @@
 hart_ids: [0]
 hart0:
-#  ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
-  ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
-#  ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh  
+  ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]
   misa:
    reset-val: 0x800000000014112D
-#    reset-val: 0x800000000015112D
    rv32:
       accessible: false
    rv64:
@@ -28,7 +25,7 @@ hart0:
            warl:
               dependency_fields: []
               legal:
-                - extensions[25:0] bitmask [0x015112D, 0x0000000]
+                - extensions[25:0] bitmask [0x014112D, 0x0000000]
               wr_illegal:
                 - Unchanged
  
diff --git a/tests/testgen/PIPELINE.py b/tests/testgen/PIPELINE.py
new file mode 100755
index 000000000..6432bb023
--- /dev/null
+++ b/tests/testgen/PIPELINE.py
@@ -0,0 +1,166 @@
+#!/usr/bin/python3
+##################################
+# PIPELINE.py
+#
+# David_Harris@hmc.edu 27 October 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def twoscomp(a):
+  amsb = a >> (xlen-1)
+  alsbs = ((1 << (xlen-1)) - 1) & a
+  if (amsb):
+      asigned = a - (1<<xlen)
+  else:
+      asigned = a
+  #print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
+  return asigned
+
+def computeExpected(a, b, test, xlen):
+  asigned = twoscomp(a)
+  bsigned = twoscomp(b)
+
+  if (test == "ADD"):
+    return a + b
+  elif (test == "SUB"):
+    return a - b
+  elif (test == "SLT"):
+    return asigned < bsigned
+  elif (test == "SLTU"):
+    return a < b
+  elif (test == "XOR"):
+    return a ^ b
+  elif (test == "OR"):
+    return a | b
+  elif (test == "AND"):
+    return a & b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd, xlen):
+  global testnum
+  expected = computeExpected(a, b, test, xlen)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+instrs = ["ADD"] # "SUB", "XOR", "OR", "AND", "SLT", "SLTU", ]
+author = "David_Harris@hmc.edu"
+xlens = [32, 64]
+numrand = 1000
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
+  fname = pathname + "src/PIPELINE.S"
+  testnum = 0
+
+  # print custom header part
+  f = open(fname, "w")
+#  r = open(refname, "w")
+  line = "///////////////////////////////////////////\n"
+  f.write(line)
+  lines="// "+fname+ "\n// " + author + "\n"
+  f.write(lines)
+  line ="// Created " + str(datetime.now()) 
+  f.write(line)
+
+  # insert generic header
+  h = open("testgen_header.S", "r")
+  for line in h:  
+    f.write(line)
+
+  maxreg = 5
+  for i in range(numrand):
+    instr = instrs[randint(0,len(instrs)-1)]
+    reg1 = randint(0,maxreg)
+    reg2 = randint(1,maxreg)
+    reg3 = randint(1,maxreg)
+    line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+    f.write(line)
+
+  for i in range(1,maxreg+1):
+    line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n"
+    f.write(line)
+
+  # print directed and random test vectors
+  # for a in corners:
+  #   for b in corners:
+  #     writeVector(a, b, storecmd, xlen)
+  # for i in range(0,numrand):
+  #   a = getrandbits(xlen)
+  #   b = getrandbits(xlen)
+  #   writeVector(a, b, storecmd, xlen)
+
+
+  # print footer
+  h = open("testgen_footer.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # Finish
+#  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+#  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  f.write(lines)
+  f.close()
+#  r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
new file mode 100755
index 000000000..9f795036b
--- /dev/null
+++ b/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
@@ -0,0 +1,158 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def twoscomp(a):
+  amsb = a >> (xlen-1)
+  alsbs = ((1 << (xlen-1)) - 1) & a
+  if (amsb):
+      asigned = a - (1<<xlen)
+  else:
+      asigned = a
+  #print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
+  return asigned
+
+def computeExpected(a, b, test, xlen):
+  asigned = twoscomp(a)
+  bsigned = twoscomp(b)
+
+  if (test == "ADD"):
+    return a + b
+  elif (test == "SUB"):
+    return a - b
+  elif (test == "SLT"):
+    return asigned < bsigned
+  elif (test == "SLTU"):
+    return a < b
+  elif (test == "XOR"):
+    return a ^ b
+  elif (test == "OR"):
+    return a | b
+  elif (test == "AND"):
+    return a & b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd, xlen):
+  global testnum
+  expected = computeExpected(a, b, test, xlen)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"]
+author = "David_Harris@hmc.edu & Katherine Parry"
+xlens = [32, 64]
+numrand = 100;
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners:
+      for b in corners:
+        writeVector(a, b, storecmd, xlen)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, b, storecmd, xlen)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
new file mode 100644
index 000000000..b755519f6
--- /dev/null
+++ b/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
@@ -0,0 +1,161 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADD-SUB.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def computeExpected(a, b, test):
+  if (test == "ADDI"):
+    return a + b
+  elif (test == "XORI"):
+    return a ^ b
+  elif (test == "ORI"):
+    return a | b
+  elif (test == "ANDI"):
+    return a & b
+  elif (test == "SLTI"):
+    return a < b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+
+def evaluateTwoComplement(b, bits):
+  if (b & (1 << (bits -1))!= 0):
+    b = b - (1 << bits)
+  return b
+
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg3 == 6):
+    return randRegs()
+  else:
+      return reg1, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+
+
+
+  expected = computeExpected(evaluateTwoComplement(a,xlen), evaluateTwoComplement(b, 12), test)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+
+
+
+  reg1, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), imm12:" + "(" +formatstrimm12.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstrimm12.format(b) + ")\n"
+  # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["ADDI", "XORI", "ORI", "ANDI", "SLTI"]
+author = "Shriya Nadgauda & Ethan Falicov"
+xlens = [32, 64]
+numrand = 100
+
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+
+  formatstrimm12 = "0x{:03x}" # format as 3-bit hexadecimal number
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for test in tests:
+    corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+
+    immBitSize = 12
+    corners2 = [0, 1, 2, 0xFF, 0x624 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, 
+            2**(immBitSize-1), 2**(immBitSize-1)+1, 0xC36 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1]
+
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners1:
+      for b in corners2:
+        writeVector(a, b, storecmd)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(12)
+      writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
diff --git a/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
new file mode 100755
index 000000000..57a2bad77
--- /dev/null
+++ b/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
@@ -0,0 +1,182 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
+#
+# ehedenberg@hmc.edu 4 February 2021
+# heavily influenced by Prof Harris Code
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+import sys
+
+##################################
+# functions
+##################################
+def logical_rshift(signed_integer, places):
+  unsigned_integer=signed_integer%(1<<32)
+  return unsigned_integer >> places
+
+def toSigned12bit(n):
+  n=n & 0xfff
+  if (n&(1<<11)):
+    n=n|0xfffffffffffff000
+  return n
+
+def toSigned32bit(n):
+  n=n & 0xffffffff
+  if (n&(1<<31)):
+    n=n|0xffffffff00000000
+  return n
+
+
+def computeExpected(a, b, test):
+  if (test == "ADDIW"):
+    b=toSigned12bit(b)
+    return a + b
+  elif (test == "SLLIW"):
+    return (a << b)
+  elif (test == "SRLIW"):
+    return logical_rshift(a, b)
+  elif(test == "SRAIW"):
+    a= toSigned32bit(a)
+    return a >> b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+  expected = computeExpected(a, b, test)
+  expected = expected % 2**64 # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**64 + expected
+    #expected=expected+2^32<<32
+  if (expected >= (2**32)):
+    expected=expected%(2**32)
+  expected=toSigned32bit(expected)
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), imm:"+formatstr.format(b) 
+  lines = lines + ", result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  #lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstr.format(b) + ")\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg3) +", "+formatstr.format(expected)+")\n"
+  #lines = lines + str(b)+"\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["ADDIW", "SLLIW", "SRLIW", "SRAIW"]
+author = "Eizabeth Hedenberg"
+xlens = [64]
+shiftlen=5
+addlen=12
+numrand = 100
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  #formatstrlen6=str(int())
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  #formatstr6 = "0x{:0" + "2" + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    cornersa = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+            #test both confined to top 32 and not
+    cornersshift=[0, 1, 2, 2**(shiftlen)-1, 2**(shiftlen)-2, 0b00101, 0b01110]
+    #6 bits: 0, 1, 2, largest, largest -1, largest -2,  21, 46
+    cornersadd=[0, 1, 2, 2**(addlen-1), 2**(addlen-1)-1, 2**(addlen-1)-2, 2**(addlen-1)+1, 2**(addlen)-2, 2**(addlen)-1, 0b001010010101, 0b101011101111]
+    #12 bit, 0, 1, 2 argest positive, largest -1, largest -2, largest negative number, -2, -1, random
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    if test=="ADDIW":
+      for a in cornersa:
+        for b in cornersadd:
+          writeVector(a, b, storecmd)
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        b = getrandbits(12)
+        writeVector(a, b, storecmd)
+    else:
+      for a in cornersa:
+        for b in cornersshift:
+          writeVector(a, b, storecmd)
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        b = getrandbits(5)
+        writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
new file mode 100755
index 000000000..d95bc3fc4
--- /dev/null
+++ b/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
@@ -0,0 +1,174 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
+#
+# trao@g.hmc.edu 11 February 2021
+# Based on testgen-ADD-SUB.py by Prof. David Harris
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+import sys
+
+##################################
+# functions
+##################################
+def logical_rshift(signed_integer, places):
+  unsigned_integer=signed_integer%(1<<32)
+  return unsigned_integer >> places
+
+def toSigned12bit(n):
+  n=n & 0xfff
+  if (n&(1<<11)):
+    n=n|0xfffffffffffff000
+  return n
+
+def toSigned32bit(n):
+  n=n & 0xffffffff
+  if (n&(1<<31)):
+    n=n|0xffffffff00000000
+  return n
+
+
+def computeExpected(a, b, test):
+  if (test == "ADDW"):
+    return toSigned32bit(a + b)
+  elif (test == "SUBW"):
+    return toSigned32bit(a - b)
+  elif (test == "SLLW"):
+    b = b & 0x1F
+    return toSigned32bit(a << b)
+  elif (test == "SRLW"):
+    b = b & 0x1F
+    return toSigned32bit(logical_rshift(a, b))
+  elif(test == "SRAW"):
+    a= toSigned32bit(a)
+    b = b & 0x1F
+    return toSigned32bit(a >> b)
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+  expected = computeExpected(a, b, test)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["ADDW", "SUBW", "SLLW", "SRLW", "SRAW"]
+author = "Tejus Rao"
+xlens = [64]
+shiftlen=5
+addlen=32
+numrand = 100
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  #formatstrlen6=str(int())
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  #formatstr6 = "0x{:0" + "2" + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  storecmd = "sd"
+  wordsize = 8
+  for test in tests:
+    cornersa = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+            #test both confined to top 32 and not
+    cornersshift=[0, 1, 2, 2**(shiftlen)-1, 2**(shiftlen)-2, 0b00101, 0b01110]
+    #6 bits: 0, 1, 2, largest, largest -1, largest -2,  21, 46
+    cornersadd=[0, 1, 2, 2**(addlen-1), 2**(addlen-1)-1, 2**(addlen-1)-2, 2**(addlen-1)+1, 2**(addlen)-2, 2**(addlen)-1, 0b001010010101, 0b101011101111]
+    #12 bit, 0, 1, 2 argest positive, largest -1, largest -2, largest negative number, -2, -1, random
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    if test=="ADDW" or test == "SUBW":
+      for a in cornersa:
+        for b in cornersadd:
+          writeVector(a, b, storecmd)
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        b = getrandbits(xlen)
+        writeVector(a, b, storecmd)
+    else:
+      for a in cornersa:
+        for b in cornersshift:
+          writeVector(a, b, storecmd)
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        b = getrandbits(5)
+        writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-BRANCH.py b/tests/testgen/imperas/testgen-BRANCH.py
new file mode 100755
index 000000000..04a9caa80
--- /dev/null
+++ b/tests/testgen/imperas/testgen-BRANCH.py
@@ -0,0 +1,155 @@
+#!/usr/bin/python3
+##################################
+# testgen-branch.py
+#
+# ssanghai@hmc.edu 13th Feb 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+def computeExpected(a, b, test):
+  if (test == "BEQ"):
+    return 0xcccc if a==b else 0xeeee
+  elif (test == "BNE"):
+    return 0xeeee if a==b else 0xcccc
+  elif (test == "BGEU"):
+    return 0xcccc if a>=b else 0xeeee
+  elif (test == "BLT"):
+    if (1<<(xlen-1)) & a:
+      a = a -(2**xlen) 
+    if (1<<(xlen-1)) & b:
+      b = b - (2**xlen)
+    return 0xcccc if a<b else 0xeeee
+  elif (test == "BLTU"):
+    return 0xcccc if a<b else 0xeeee
+  elif (test == "BGE"):
+    if (1<<(xlen-1)) & a:
+      a = a - (2**xlen)
+    if (1<<(xlen-1)) & b:
+      b = b - (2**xlen)
+    return 0xcccc if a>=b else 0xeeee
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(2,31)
+  reg2 = randint(2,31)
+  if (reg1 == 6 or reg2 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2
+
+label = 0
+
+def writeVector(a, b, storecmd):
+  global testnum 
+  global label
+  expected = computeExpected(a, b, test)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) + "\n"
+  lines = lines + "li x1, MASK_XLEN(0xcccc)\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg1) + ", x" + str(reg2) + ", " + str(label) + "f\n"
+  lines = lines + "li x1, MASK_XLEN(0xeeee)\n"
+  lines = lines + str(label) + ":\n"
+  lines = lines + storecmd + " x1, " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, x1, "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  label += 1
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["BEQ", "BNE", "BLT", "BGE", "BGEU", "BLTU"] 
+author = "Shreya Sanghai"
+xlens = [32, 64]
+numrand = 100
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners:
+      for b in corners:
+        writeVector(a, b, storecmd)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-CSR.py b/tests/testgen/imperas/testgen-CSR.py
new file mode 100644
index 000000000..f28f9925d
--- /dev/null
+++ b/tests/testgen/imperas/testgen-CSR.py
@@ -0,0 +1,218 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADD-SUB.py
+#
+# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021
+# Modified: ushakya@hmc.edu 21 April 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+  csr = "mscratch"
+
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  " + csr + "\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
+
+  # Page 6 of unpriviledged spec
+  # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
+
+  expected = a
+
+  if test == "csrrw":
+    if testnum == 0:
+      # this is a corner case (reading and writing same register)
+      expected = 4
+      lines += "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(0x8) + ")\n"
+      lines += "la x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(0x4) + ")\n"
+      lines += "csrrw x" + str(reg3) + ", mtvec, x" + str(reg1) + "\n"
+      lines += test +  " x" + str(reg2) + ", mtvec, x" + str(reg2) + "\n"
+      lines += "csrrw x0, mtvec, x" + str(reg3) + "\n"
+    else:
+      lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+      lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+
+  elif test == "csrrs": # at some point, try writing a non-zero value first
+    lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
+
+    lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+    lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+  elif test == "csrrc": # at some point, try writing a non-one value first
+    allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
+
+    lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
+    lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
+
+    lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+
+    lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+    lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+
+    expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
+  elif test == "csrrwi":
+    a = a & 0x1F # imm is only 5 bits
+
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+
+    expected = a
+  elif test == "csrrsi": # at some point, try writing a non-zero value first
+    a = a & 0x1F
+
+    lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
+
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+
+    expected = a
+  elif test == "csrrci": # at some point, try writing a non-one value first
+    a = a & 0x1F
+    allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
+
+    lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
+    lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
+
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+    lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
+
+    expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
+
+
+  lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+def writeSpec(a, storecmd):
+  global testnum
+  csr = "mscratch"
+  reg1 = 3
+  reg2 = 3
+
+  lines = "\n# Testcase " + str(testnum) + ":  " + csr + "\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  expected = a
+
+  lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+  lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
+
+  lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
+tests = ["csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci"]
+author = "ushakya@hmc.edu & dottolia@hmc.edu"
+xlens = [32, 64]
+numrand = 60;
+
+# setup
+seed(0xC365DDEB9173AB42) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    corners = [
+      0, 1, 2, 0x1E, 0x1F, 0xFF,
+      0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+      2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
+    ]
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test.upper() 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    # test that reading and writing from same register work
+    if test == "csrrw":
+      a = getrandbits(xlen)
+      #writeSpec(a, storecmd)
+    for a in corners:
+      for b in corners:
+        writeVector(a, b, storecmd)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -4\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-JAL-JALR.py b/tests/testgen/imperas/testgen-JAL-JALR.py
new file mode 100755
index 000000000..87c0c423d
--- /dev/null
+++ b/tests/testgen/imperas/testgen-JAL-JALR.py
@@ -0,0 +1,286 @@
+#!/usr/bin/python3
+##################################
+# testgen-JAL.py
+#
+# Ben Bracker (bbracker@hmc.edu) 19 January 2021
+# Based on testgen-ADD-SUB.py by David Harris
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint
+from random import choice
+from random import seed
+from random import getrandbits
+from copy import deepcopy
+
+##################################
+# helper functions
+##################################
+def InitTestGroup():
+  global TestGroup,TestGroupSizes,AllRegs,UnusedRegs,StoreAdrReg
+  TestGroup += 1
+  TestGroupSizes.append(0)
+  UnusedRegs = deepcopy(AllRegs)
+  oldStoreAdrReg = StoreAdrReg
+  while ((StoreAdrReg == oldStoreAdrReg) or (StoreAdrReg == 0) or (StoreAdrReg == 31)):
+    StoreAdrReg = choice(UnusedRegs)
+  UnusedRegs.remove(StoreAdrReg)
+  f.write("\n    # ---------------------------------------------------------------------------------------------\n")
+  f.write("    # new register for address of test results\n")
+  addInst("    la x"+str(StoreAdrReg)+", test_1_res\n")
+  f.write("    # ---------------------------------------------------------------------------------------------\n")
+
+def registerSelect():
+  # ensures that rd experiences all possible registers
+  # *** does not yet ensure that rs experiences all possible registers
+  # ensures that at least once rd = rs
+  global UnusedRegs
+  if len(UnusedRegs)==0: 
+    InitTestGroup()
+  rd = choice(UnusedRegs)
+  UnusedRegs.remove(rd)
+  OtherRegs = deepcopy(UnusedRegs)
+  if 0 in OtherRegs: 
+    OtherRegs.remove(0)
+  if len(OtherRegs) == 0:
+    OtherRegs = deepcopy(AllRegs)
+    OtherRegs.remove(0)
+  rs = choice(OtherRegs)
+  OtherRegs = deepcopy(AllRegs)
+  OtherRegs.remove(StoreAdrReg)
+  OtherRegs.remove(rd)
+  if 0 in OtherRegs: 
+    OtherRegs.remove(0)
+  if rs in OtherRegs: 
+    OtherRegs.remove(rs)
+  DataReg = choice(OtherRegs)
+  OtherRegs.remove(DataReg)
+  OtherRd = choice(OtherRegs)
+  return (rd,rs,DataReg,OtherRd)
+
+def addInst(line):
+  global CurrAdr
+  f.write(line)
+  if ("li x" in line) and ("slli x" not in line):
+    CurrAdr += 8 if (xlen == 32) else 20
+  elif ("la x" in line):
+    CurrAdr += 8
+  else:
+    CurrAdr += 4
+
+def expectValue(expectReg, expectVal, sigOffset):
+  global TestGroupSizes
+  TestGroupSizes[TestGroup-1] += 1
+  addInst("    "+storecmd+" x"+str(expectReg)+", "+str(wordsize*sigOffset)+"(x"+str(StoreAdrReg)+")\n")
+  f.write("    RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(expectReg)+", "+formatstr.format(expectVal)+")\n")
+  if (xlen == 32):
+    r.write(formatrefstr.format(expectVal)+"\n")
+  else:
+    r.write(formatrefstr.format(expectVal % 2**32)+"\n" + formatrefstr.format(expectVal >> 32)+"\n")
+
+def addJalr(rs,rd,dist):
+  target = CurrAdr + 20 + dist
+  target31_12 = CurrAdr >> 12 # 20 bits for lui
+  target11_0 = target - (target31_12 << 12) # 12 remaining bits
+  target31_16 = target31_12 >> 4 # lui sign extends, so shift in a leading 0
+  target15_12 = target31_12 - (target31_16 << 4) # the nibble we just lost
+  if target11_0 > 0:
+    offset = randint(-(1<<11)-1,(1<<11)-2-target11_0)
+  else:
+    offset = randint(-(1<<11)-1-target11_0,(1<<11)-2)
+  addInst("    lui x"+str(rs)+", 0x"+imm20formatstr.format(target31_16)+"\n")
+  addInst("    addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x0"+imm12formatstr.format(target15_12 << 8)+")\n")
+  addInst("    slli x"+str(rs)+", x"+str(rs)+", SEXT_IMM(4)\n") 
+  addInst("    addi x"+str(rs)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(offset+target11_0+randint(0,1)))+")\n")
+  addInst("    JALR x"+str(rd)+", x"+str(rs)+", SEXT_IMM(0x"+imm12formatstr.format(0xfff&(-offset))+")\n")
+
+##################################
+# test functions
+##################################
+def writeForwardsJumpVector(spacers,instr):
+  global TestNum
+  TestNum += 1
+  rd, rs, DataReg, OtherRd = registerSelect()
+  # Header
+  f.write("\n")
+  f.write("    # Testcase "+str(TestNum)+"\n")
+  # Test Code
+  addInst("    li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
+  if (instr=="JAL"):
+    addInst("    JAL x"+str(rd)+", 1f\n")
+  elif (instr=="JALR"):
+    dist = spacers*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr
+    addJalr(rs,rd,dist);
+  else:
+    exit("invalid instruction") 
+  LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
+  for i in range(spacers):
+    addInst("    li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
+  f.write("1:\n")
+  # Store values to be verified
+  expectValue(rd, LinkAdr, 2*TestNum+0)
+  expectValue(DataReg, expected, 2*TestNum+1)
+
+def writeBackwardsJumpVector(spacers,instr):
+  global TestNum
+  TestNum += 1
+  rd, rs, DataReg, OtherRd = registerSelect()
+  # Header
+  f.write("\n")
+  f.write("    # Testcase "+str(TestNum)+"\n")
+  # Test Code
+  addInst("    JAL x"+str(OtherRd)+", 2f\n")
+  f.write("1:\n")
+  addInst("    li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
+  addInst("    JAL x"+str(OtherRd)+", 3f\n")
+  f.write("2:\n")
+  for i in range(spacers):
+    addInst("    li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
+  if (instr=="JAL"):
+    addInst("    JAL x"+str(rd)+", 1b\n")
+  elif (instr=="JALR"):
+    dist = -20 - 4 - (1+spacers)*(8 if (xlen == 32) else 20) # Compute distance from linked adr to target adr
+    addJalr(rs,rd,dist);
+  else:
+    exit("invalid instruction") 
+  LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
+  f.write("3:\n")
+  # Store values to be verified
+  expectValue(rd, LinkAdr, 2*TestNum+0)
+  expectValue(DataReg, expected, 2*TestNum+1)
+
+def writeChainVector(repetitions,spacers):
+  global TestNum
+  TestNum += 1
+  rd, rs, DataReg,OtherRd = registerSelect()
+  # Header
+  f.write("\n")
+  f.write("    # Testcase "+str(TestNum)+"\n")
+  # Test Code
+  addInst("    li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
+  for i in range(repetitions):
+    addInst("    JAL x"+str(OtherRd)+", "+str(3*i+2)+"f\n")
+    if spacers:
+      for j in range(i):
+        addInst("    li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
+    f.write(str(3*i+1)+":\n")
+    addInst("    JAL x"+str(OtherRd)+", "+str(3*i+3)+"f\n")
+    if spacers:
+      for j in range(i):
+        addInst("    li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
+    f.write(str(3*i+2)+":\n")
+    addInst("    JAL x"+str(rd)+", "+str(3*i+1)+"b\n")
+    LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
+    if spacers:
+      for j in range(i):
+        addInst("    li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
+    f.write(str(3*i+3)+":\n")
+  # Store values to be verified
+  expectValue(rd, LinkAdr, 2*TestNum+0)
+  expectValue(DataReg, expected, 2*TestNum+1)
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+test = 0
+tests = ["JAL","JALR"]
+author = "Ben Bracker (bbracker@hmc.edu)"
+xlens = [32,64]
+numtests = 100
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for test in tests:
+  for xlen in xlens:
+    print(test+" "+str(xlen))
+    CurrAdr = int("80000108",16)
+    TestNum = -1
+    TestGroup = 1
+    TestGroupSizes = [0]
+    AllRegs = list(range(0,32))
+    UnusedRegs = deepcopy(AllRegs) 
+    StoreAdrReg = 6 # matches what's in header script 
+    UnusedRegs.remove(6)
+    if (xlen==64):
+      expected = int("fedbca9876540000",16)
+      unexpected = int("ffff0000ffff0000",16)
+    else:
+      expected = int("fedbca98",16)
+      unexpected = int("ff00ff00",16)
+
+    formatstrlen = str(int(xlen/4))
+    formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+    formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+    imm20formatstr = "{:05x}"
+    imm12formatstr = "{:03x}"
+
+    if (xlen == 32):
+      storecmd = "sw"
+      wordsize = 4
+    else:
+      storecmd = "sd"
+      wordsize = 8
+
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    f.write("///////////////////////////////////////////\n")
+    f.write("// "+fname+ "\n")
+    f.write("//\n")
+    f.write("// This file can be used to test the RISC-V JAL(R) instruction.\n")
+    f.write("// But be warned that altering the test environment may break this test!\n")
+    f.write("// In order to work, this test expects that the first instruction (la)\n")
+    f.write("// be allocated at 0x80000100.\n")
+    f.write("//\n")
+    f.write("// " + author + "\n")
+    f.write("// Created "+str(datetime.now())+"\n") 
+    
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed test vectors
+    if test == "JAL":
+      for i in range(0,31):
+        writeForwardsJumpVector(randint(0,4),"JAL")
+      for i in range(0,31):
+        writeBackwardsJumpVector(randint(0,4),"JAL")
+      writeForwardsJumpVector(100,"JAL")
+      writeBackwardsJumpVector(100,"JAL")
+      writeChainVector(6,True)
+      writeChainVector(16,False)
+    elif test == "JALR":
+      for i in range(0,31):
+        writeForwardsJumpVector(randint(0,4),"JALR")
+      for i in range(0,31):
+        writeBackwardsJumpVector(randint(0,4),"JALR")
+      # can't make these latter two too long else 12 bit immediate overflows
+      # (would need to lui or slli rs to achieve longer ranges)
+      writeForwardsJumpVector(15,"JALR")
+      writeBackwardsJumpVector(15,"JALR")
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    f.write(".fill "+str(sum(TestGroupSizes))+", "+str(wordsize)+", -1\n")
+    f.write("\nRV_COMPLIANCE_DATA_END\n")
+    f.close()
+    r.close()
diff --git a/tests/testgen/imperas/testgen-LOAD.py b/tests/testgen/imperas/testgen-LOAD.py
new file mode 100755
index 000000000..4a80fbfc7
--- /dev/null
+++ b/tests/testgen/imperas/testgen-LOAD.py
@@ -0,0 +1,227 @@
+#!/usr/bin/python3
+##################################
+# testgen-LOAD.py
+#
+# Jarred Allen <jaallen@g.hmc.edu> 02 February 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint, seed, getrandbits
+
+##################################
+# functions
+##################################
+
+def rand_reg():
+  """Produce a random register (skipping 6 and 31, since they're used for other things)"""
+  r = randint(1,29)
+  if r >= 6:
+    r += 1
+  return r
+
+def rand_value(width):
+    """Generate a random value which fits in the given width"""
+    return randint(0, (1 << width) - 1)
+
+def rand_offset():
+    """Generate a random offset"""
+    ret = rand_value(12)
+    # print("Random offset: %d" % ret)
+    return ret
+
+def rand_source():
+    """Generate a random value for the source register, such that the load address is in the test data"""
+    ret = randint(1 << 12, (1 << 12) + (1 << 10))
+    # print("Random source: %d" % ret)
+    return ret
+
+def add_offset_to_source(source, offset):
+    """Find the address from the given source value and offset"""
+    if offset & 0x800:
+        offset -= 0x1000
+    return source + offset
+
+def insert_into_data(test_data, source, offset, value, width, xlen):
+    """Insert the given value into the given location of the test data"""
+    address = add_offset_to_source(source, offset)
+    # print("Test #%d" % testcase_num)
+    # print(f"Source: {source}, Offset: {offset}, Value: {value}, Width: {width}, xlen: {xlen}, Addr: {address}")
+    if address < 0:
+        return False
+    word_offset = address % (xlen // 8)
+    word_address = address - word_offset
+    if word_address in test_data:
+        return False
+    test_data[word_address] = value * (1 << (word_offset*8)) + ((~(((1 << width)-1) << (word_offset*8))) & rand_value(xlen))
+    # print(f"Word: {hex(test_data[word_address])}")
+    return True
+
+def align(address, width):
+    """Align the address to the given width, in bits"""
+    return address - (address % (width // 8))
+
+testcase_num = 0
+def generate_case(xlen, instruction, load_register, source_register, source_register_value, offset, expected):
+    """Produce the specified test case and return it as a pair of strings, where the first is the test case and the second is the output"""
+    global testcase_num
+    if xlen == 64:
+        store = "sd"
+    elif xlen == 32:
+        if instruction in ["lwu", "ld"]:
+            raise Exception("Instruction %s not supported in RV32I" % instruction)
+        store = "sw"
+    else:
+        raise Exception("Unknown xlen value: %s" % xlen)
+    if offset >= 0x800:
+        offset -= 0x1000
+    if widths[instruction] != xlen:
+        expected = expected % (1 << widths[instruction])
+        if 'u' not in instruction:
+            if expected & (1 << (widths[instruction] - 1)):
+                expected = (expected + ~((1 << widths[instruction]) - 1)) & ((1 << xlen) - 1)
+    data = f"""# Testcase {testcase_num}: source {offset}(x{source_register} == {source_register_value}), result: x{load_register} == {expected}
+    la x31, test_data
+    lui x{source_register}, {source_register_value // (1 << 12)}
+    addi x{source_register}, x{source_register}, {source_register_value % (1 << 12)} 
+    add x{source_register}, x{source_register}, x31
+    {instruction} x{load_register}, {offset}(x{source_register})
+    {store} x{load_register}, {(testcase_num*xlen//8) % 0x800}(x6)
+    RVTEST_IO_ASSERT_GPR_EQ(x8, x{load_register}, {expected})
+
+    """
+    testcase_num += 1
+    if testcase_num*xlen//8 % 0x800 == 0:
+        data += "# Adjust x6 because we're storing too many things\naddi x6, x6, 1024\naddi x6, x6, 1024\n\n"
+    if xlen == 32:
+        reference_output = "{:08x}\n".format(expected) 
+    elif xlen == 64:
+        reference_output = "{:08x}\n{:08x}\n".format(expected % (1 << 32), expected >> 32) 
+    return (data, reference_output)
+
+def write_header(outfile):
+    outfile.write(f"""///////////////////////////////////////////
+//
+// WALLY-LOAD
+//
+// Author: {author}
+//
+// Created {str(datetime.now())}
+// 
+""")
+    outfile.write(open("testgen_header.S", "r").read())
+
+def write_test_data(outfile, test_data, xlen):
+    # print("Begin writing test data:")
+    # print("{} entries, from address {} to {}".format(len(test_data), min(test_data.keys()), max(test_data.keys())))
+    # print(test_data)
+    outfile.write("""
+    .align 16
+test_data:
+    
+    """)
+    if xlen == 32:
+        data_word = ".word"
+    elif xlen == 64:
+        data_word = ".dword"
+    else:
+        raise Exception("Unknown xlen: %d" % xlen)
+    byte_width = xlen // 8
+    for addr in [0] + sorted(test_data.keys()):
+        if addr in test_data:
+            word = f"    {data_word} {hex(test_data[addr] % (1 << xlen))} # test_data+{hex(addr)}\n"
+        else:
+            word = ""
+        try:
+            fill_len = (min(k for k in test_data.keys() if k > addr) - addr) // byte_width - 1
+            if word == "":
+                fill_len += 1
+            fill = f"    .fill {fill_len}, {byte_width}, 0x0\n"
+        except:
+            fill = ""
+        case = word+fill
+        outfile.write(case)
+
+##################################
+# main body
+##################################
+
+widths = {
+    "lb": 8,
+    "lbu": 8,
+    "lh": 16,
+    "lhu": 16,
+    "lw": 32,
+    "lwu": 32,
+    "ld": 64,
+}
+instructions = [i for i in widths]
+author = "Jarred Allen"
+xlens = [32, 64]
+numrand = 100;
+
+# setup
+seed(0) # make tests reproducible
+
+for xlen in xlens:
+    testcase_num = 0
+    fname = "../../imperas-riscv-tests/riscv-test-suite/rv{}i/src/WALLY-LOAD.S".format(xlen)
+    refname = "../../imperas-riscv-tests/riscv-test-suite/rv{}i/references/WALLY-LOAD.reference_output".format(xlen)
+    f = open(fname, "w")
+    r = open(refname, "w")
+    write_header(f)
+    test_data = dict()
+    corner_values = [0x00, 0xFFFFFFFF, 0x7F, 0x7FFF, 0x7FFFFFFF]
+    if xlen == 64:
+        corner_values += [0xFFFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFF]
+    corner_offsets = [0x800, 0x000, 0x7FF]
+    for instruction in instructions:
+        print("Running xlen: %d, instruction: %s" % (xlen, instruction))
+        if xlen == 32:
+            if instruction in ["lwu", "ld"]:
+                continue
+        for value in corner_values + [rand_value(widths[instruction]) for _ in range(3)]:
+            value = value % (1 << widths[instruction])
+            source_reg = rand_source()
+            for offset in corner_offsets + [rand_offset() for _ in range(3)]:
+                offset = align(offset, widths[instruction])
+                source_reg = align(source_reg, widths[instruction])
+                if insert_into_data(test_data, source_reg, offset, value, widths[instruction], xlen):
+                    data, output = generate_case(xlen, instruction, rand_reg(), rand_reg(), source_reg, offset, value)
+                    f.write(data)
+                    r.write(output)
+    while testcase_num % 4:
+        source = rand_source()
+        offset = rand_offset()
+        value = rand_value(widths[instruction])
+        if insert_into_data(test_data, source, offset, value, widths['lb'], xlen):
+            data, output = generate_case(xlen, 'lb', rand_reg(), rand_reg(), source, offset, value)
+            f.write(data)
+            r.write(output)
+    f.write("""# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+	.data
+    # Input data section
+""")
+    write_test_data(f, test_data, xlen)
+    f.write("""# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
+""")
+    f.write(f".fill {testcase_num}, {xlen//8}, -1\n")
+    f.write("\nRV_COMPLIANCE_DATA_END\n")
+    f.close()
+    r.close()
diff --git a/tests/testgen/imperas/testgen-PIPELINE.py b/tests/testgen/imperas/testgen-PIPELINE.py
new file mode 100755
index 000000000..3a425da98
--- /dev/null
+++ b/tests/testgen/imperas/testgen-PIPELINE.py
@@ -0,0 +1,1917 @@
+#!/usr/bin/python
+###################################################################################################
+# testgen-PIPELINE.py
+#
+# Shriya Nadgauda: snadgauda@hmc.edu & Ethan Falicov: efalicov@hmc.edu
+# Created: Feb 2, 2021
+#
+# Generate random assembly code for RISC-V Processor Design Validation.
+###################################################################################################
+
+# Many Functions Based On: https://github.com/wallento/riscv-python-model (MIT License)
+
+
+###################################################################################################
+# Libraries
+###################################################################################################
+from random import seed
+from random import randint
+from enum import Enum
+import numpy as np
+
+import re
+
+from datetime import datetime
+
+MEMSTART = 'testdata'
+###################################################################################################
+# Main Body
+###################################################################################################
+
+class InvalidImmediateValueException(Exception):
+    pass
+
+class InvalidRegisterNumberException(Exception):
+    pass
+
+class InvalidRegisterValueException(Exception):
+    pass
+
+class WriteToImmutableRegisterException(Exception):
+    pass
+
+class ReadFromUninitializedMemoryException(Exception):
+    pass
+
+class InvalidMemoryWriteLocation(Exception):
+    pass
+
+def zeroExtend(inputBits, resultNumBits):
+    numDigitsToAppend = resultNumBits - len(inputBits)
+    newBits = inputBits
+    if numDigitsToAppend > 0:
+        newBits = ('0' * numDigitsToAppend) + inputBits
+    return newBits
+
+def oneExtend(inputBits, resultNumBits):
+    numDigitsToAppend = resultNumBits - len(inputBits)
+    newBits = inputBits
+    if numDigitsToAppend > 0:
+        newBits = ('1' * numDigitsToAppend) + inputBits
+    return newBits
+
+def signExtend(inputBits, resultNumBits):
+    if inputBits[0] == '1':
+        return oneExtend(inputBits = inputBits, resultNumBits = resultNumBits)
+    return zeroExtend(inputBits = inputBits, resultNumBits = resultNumBits)
+
+def binToDec(inputBits):
+    if inputBits[0] == '0':
+        return int(inputBits, 2)
+    
+    numBits = len(inputBits)
+    twoCompMask = (1 << (numBits - 1)) - 1
+    msbMask = (1 << (numBits -1))
+    
+    return int((-1 * (msbMask * int(inputBits[0], 2))) + (twoCompMask & int(inputBits, 2)))
+
+def randBinary(signed, numBits, valueAlignment):
+    # use this for corners: xlen = 32 here
+    # corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+    # 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+    # when not biased don't gen numbers from (|2^(n-2) to 2^(n-2)|)
+    biased = np.random.randint(0, 3) # on 2 generate random edge case
+    returnVal = 0
+    sign = 0
+    if biased < 2:
+        # print("unbiased")
+        if not(signed):
+            returnVal = np.random.randint(0, 2**(numBits - 2))
+
+        else:    
+            returnVal = np.random.randint(-2**(numBits - 2), 2**(numBits - 2))
+    
+    else:
+        # print("corner")
+        if not(signed):
+            returnVal = np.random.randint(2**(numBits - 2)+1, 2**(numBits - 1)-2)
+
+        else:    
+            sign = np.random.randint(0, 2) # 0 is pos, 1 is neg
+            if sign:
+                returnVal = np.random.randint(2**(numBits - 2)+1, 2**(numBits - 1)-2)
+            else:
+                returnVal = np.random.randint(-2**(numBits - 1), -2**(numBits - 2)-1)
+
+    binReturnVal = bin(returnVal) #remove "0b"
+    if returnVal >= 0:
+        binReturnVal = binReturnVal[2:]
+
+        #make binary correct length
+        while(len(binReturnVal) < numBits):
+            binReturnVal = "0" + binReturnVal
+    else:
+        binReturnVal = binReturnVal[3:]
+        #two's compliment
+        flipped = ''.join('1' if x == '0' else '0' for x in binReturnVal)
+        added = bin(int(flipped, 2) + 1)[2:]
+
+        while(len(added) < len(flipped)):
+            added = "0" + added
+        while(len(added) < numBits):
+            added = "1" + added
+        
+        binReturnVal = added
+
+    # ensure correct value assignment
+    if valueAlignment == 1:
+        return binReturnVal
+    
+    indexVal = valueAlignment // 2
+    returnValue = binReturnVal[:-indexVal] + "0"*indexVal 
+    return returnValue
+
+def randHex(sign, numBits, divisibleByValue):
+    val = hex(int(randBinary(sign, numBits*4, divisibleByValue), 2))
+    return val
+
+def randDec(valueRangeMin, valueRangeMax, divisibleByValue):
+    valRange = (valueRangeMax - valueRangeMin)//divisibleByValue   
+    return (np.random.randint(0, valRange + 1) * divisibleByValue + valueRangeMin)
+
+class Label:
+    def __init__(self, name, pcValue):
+        self.name = name
+        self.pcValue = pcValue
+
+class Immediate:
+    def __init__(self, xlen, numBits = None, signed = 1):
+        self.xlen = int(xlen)
+        if numBits == None:
+            numBits = self.xlen
+        self.numBits = int(numBits)
+        self.signed = signed
+        self.bits = '0'*self.numBits
+        self.twoCompMask = (1 << (self.numBits - 1)) - 1
+        self.msbMask = (1 << (self.numBits -1))
+
+        self.value = self.getDecValue()
+    
+        self.maxValue = self.getMaxValue()
+        self.minValue = self.getMinValue()
+
+    def getDecValue(self):
+        if self.signed == 1:
+            return self.getValueSigned()
+        return self.getValueUnsigned()
+
+    def getMaxValue(self):
+        if self.signed == 1:
+            return ((2**(self.numBits - 1)) - 1)
+        return ((2**self.numBits) - 1) 
+
+    def getMinValue(self):
+        if self.signed == 1:
+            return (-1 * 2**(self.numBits - 1))
+        return 0
+
+    def signExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return signExtend(inputBits, self.numBits)
+
+    def oneExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return oneExtend(inputBits, self.numBits)
+
+    def zeroExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return zeroExtend(inputBits, self.numBits)
+
+    def setValue(self, newValue, signed = None):
+        if signed != None:
+            self.signed = signed
+        self.maxValue = self.getMaxValue()
+        self.minValue = self.getMinValue()
+
+        if newValue > self.maxValue:
+            errStr = 'Attempted: {}, Max: {}'.format(newValue, self.maxValue)
+            raise InvalidImmediateValueException(errStr)
+            newValue = self.maxValue
+
+        elif newValue < self.minValue:
+            errStr = 'Attempted: {}, Min: {}'.format(newValue, self.minValue)
+            raise InvalidImmediateValueException(errStr)
+            newValue = self.minValue
+        
+        self.value = newValue
+
+        bitValue = ''
+        if (self.signed == 1) and (newValue < 0):
+            bitValue = bin(self.value)[3:] # Remove the -0b
+            flipped = ''.join('1' if x == '0' else '0' for x in bitValue)
+            bitValue = bin(int(flipped, 2) + 1)[2:]
+
+            if len(bitValue) < len(flipped): # Correction for removing sig figs
+                bitValue = '0'*(len(flipped)-len(bitValue)) + bitValue
+
+            bitValue = self.oneExtend(bitValue)
+        elif self.signed == 1 and newValue >= 0:
+            bitValue = bin(self.value)[2:] # Remove the 0b
+            bitValue = self.zeroExtend(bitValue)
+        else:
+            bitValue = bitValue = bin(self.value)[2:] # Remove the 0b
+            bitValue = self.zeroExtend(bitValue)
+        
+        self.bits = bitValue
+
+    def setBits(self, newBits, signed = None):
+        if signed != None:
+            self.signed = signed
+
+        if len(newBits) != self.numBits:
+            errStr = 'Attempted to write {} bits into {} bit immediate'.format(len(newBits), self.numBits)
+            raise InvalidImmediateValueException(errStr)
+        
+        self.bits = newBits
+        self.value = self.getDecValue()
+        
+    def randomize(self, signed = None, minVal = None, maxVal = None, granularity = None):
+        if signed != None: 
+            self.signed = signed
+        self.maxValue = self.getMaxValue()
+        self.minValue = self.getMinValue()
+
+        if minVal == None:
+            minVal = self.minValue
+        if maxVal == None:
+            maxVal = self.maxValue
+        if granularity == None:
+            granularity = GRANULARITY.BYTE
+        
+        granularityNum = 1
+        if granularity == GRANULARITY.HALFWORD:
+            granularityNum = self.xlen // 16
+        elif granularity == GRANULARITY.WORD:
+            granularityNum = self.xlen // 8 
+
+        minVal = int(np.ceil(minVal / granularityNum) * granularityNum)
+        maxVal = int(np.floor(maxVal / granularityNum) * granularityNum)
+
+        
+        valRange = (maxVal - minVal)//granularityNum
+        randValue = randint(0, valRange) * granularityNum + minVal
+
+        self.setValue(randValue, signed=self.signed)
+
+    def getValueSigned(self):
+        if self.bits[0] == '0':
+            return int(self.bits, 2)
+        else:
+            return int((-1 * (self.msbMask * int(self.bits[0], 2))) + (self.twoCompMask & int(self.bits, 2)))
+
+    def getValueUnsigned(self):
+        return int(self.bits, 2)
+
+    def __str__(self):
+        infoStr = ''
+        if self.signed == 1:
+            infoStr = 'Signed {} bit value: {}'.format(self.numBits, self.value)
+        infoStr = 'Unsigned {} bit value: {}'.format(self.numBits, self.value)
+        return 'Immediate bits {} ({})'.format(self.bits, infoStr)
+
+    @classmethod
+    def randImm12(cls, xlen, signed = 1):
+        imm = cls(xlen = xlen, numBits = 12, signed = signed)
+        imm.randomize()
+        return imm
+
+    @classmethod
+    def setImm12(cls, xlen, value, signed = 1):
+        imm = cls(xlen = xlen, numBits = 12, signed = signed)
+        imm.setValue(newValue = value)
+        return imm
+
+    @classmethod
+    def setImm20(cls, xlen, value, signed = 1):
+        imm = cls(xlen = xlen, numBits = 20, signed = signed)
+        imm.setValue(newValue = value, signed=1)
+        return imm
+
+    @classmethod
+    def randZImm5(cls, xlen, signed = 0):
+        imm = cls(xlen = xlen, numBits = 5, signed = signed)
+        imm.randomize()
+        return imm
+
+    @classmethod
+    def randImm13(cls, xlen, signed = 1):
+        imm = cls(xlen = xlen, numBits = 13, signed = signed)
+        imm.randomize()
+        return imm
+
+    @classmethod
+    def randImm20(cls, xlen, signed = 1):
+        imm = cls(xlen = xlen, numBits = 20, signed = signed)
+        imm.randomize()
+        return imm
+       
+class Register:
+    def __init__(self, xlen, signed = 1):
+        self.xlen = int(xlen)
+        self.numBits = self.xlen
+        self.signed = signed
+        self.bits = '0'*self.numBits
+        self.twoCompMask = (1 << (self.numBits - 1)) - 1
+        self.msbMask = (1 << (self.numBits -1))
+
+        self.value = self.getDecValue()
+        self.immutable = False
+        self.regName = None
+    
+        self.maxValue = self.getMaxValue()
+        self.minValue = self.getMinValue()
+    
+    def getRegName(self):
+        return self.regName
+        
+    def setRegName(self, newName):
+        self.regName = newName
+
+    def setImmutable(self, immutable):
+        self.immutable = immutable    
+
+    def getDecValue(self):
+        if self.signed == 1:
+            return self.getValueSigned()
+        return self.getValueUnsigned()
+
+    def getMaxValue(self):
+        if self.signed == 1:
+            return (2**(self.numBits - 1) - 1)
+        return (2**(self.numBits) - 1) 
+
+    def getMinValue(self):
+        if self.signed == 1:
+            return (-1 * 2**(self.numBits - 1))
+        return 0
+
+    def signExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return signExtend(inputBits, self.numBits)
+
+    def oneExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return oneExtend(inputBits, self.numBits)
+
+    def zeroExtend(self, inputBits = None):
+        if inputBits == None:
+            inputBits = self.bits
+
+        return zeroExtend(inputBits, self.numBits)  
+
+    def setValue(self, newValue, signed = None):
+        if self.immutable:
+            raise(WriteToImmutableRegisterException)
+        else:
+            if signed != None:
+                self.signed = signed
+            self.maxValue = self.getMaxValue()
+            self.minValue = self.getMinValue()
+
+            if newValue > self.maxValue:
+                errStr = 'Attempted: {}, Max: {}'.format(newValue, self.maxValue)
+                raise InvalidRegisterValueException(errStr)
+                newValue = self.maxValue
+
+            elif newValue < self.minValue:
+                errStr = 'Attempted: {}, Min: {}'.format(newValue, self.minValue)
+                raise InvalidRegisterValueException(errStr)
+                newValue = self.minValue
+            
+            self.value = newValue
+
+            bitValue = ''
+            if signed == 1 and newValue < 0:
+                bitValue = bin(self.value)[3:] # Remove the -0b
+                flipped = ''.join('1' if x == '0' else '0' for x in bitValue)
+                bitValue = bin(int(flipped, 2) + 1)[2:]
+
+                if len(bitValue) < len(flipped): # Correction for removing sig figs
+                    bitValue = '0'*(len(flipped)-len(bitValue)) + bitValue
+
+                bitValue = self.oneExtend(bitValue)
+            elif signed == 1 and newValue >= 0:
+                bitValue = bin(self.value)[2:] # Remove the 0b
+                bitValue = self.zeroExtend(bitValue)
+            else:
+                bitValue = bitValue = bin(self.value)[2:] # Remove the 0b
+                bitValue = self.zeroExtend(bitValue)
+            
+            self.bits = bitValue
+
+    def setBits(self, newBits, signed = None):
+        if self.immutable:
+            raise(WriteToImmutableRegisterException)
+        else:
+            if signed != None:
+                self.signed = signed
+
+            if len(newBits) != self.numBits:
+                errStr = 'Attempted to write {} bits into {} bit register'.format(len(newBits), self.numBits)
+                raise InvalidRegisterValueException(errStr)
+            
+            self.bits = newBits
+            self.value = self.getDecValue()
+        
+    def randomize(self, signed = None, minVal = None, maxVal = None, granularity = None):
+        if self.immutable:
+            raise(WriteToImmutableRegisterException)
+        else:
+            if signed != None: 
+                self.signed = signed
+            self.maxValue = self.getMaxValue()
+            self.minValue = self.getMinValue()
+            
+            if minVal == None:
+                minVal = self.minValue
+            if maxVal == None:
+                maxVal = self.maxValue
+            if granularity == None:
+                granularity = GRANULARITY.BYTE
+            
+            granularityNum = 1
+            if granularity == GRANULARITY.HALFWORD:
+                granularityNum = self.xlen // 16
+            elif granularity == GRANULARITY.WORD:
+                granularityNum = self.xlen // 8 
+
+            minVal = int(np.ceil(minVal / granularityNum) * granularityNum)
+            maxVal = int(np.floor(maxVal / granularityNum) * granularityNum)
+
+            
+            valRange = (maxVal - minVal)//granularityNum
+            randValue = randint(0, valRange) * granularityNum + minVal
+        
+            self.setValue(randValue, signed=self.signed)
+    
+    def getValueSigned(self):
+        if self.bits[0] == 0:
+            return int(self.bits, 2)
+        else:
+            return int((-1 * (self.msbMask * int(self.bits[0], 2))) + (self.twoCompMask & int(self.bits, 2)))
+
+    def getValueUnsigned(self):
+        return int(self.bits, 2)
+
+    def __str__(self):
+        infoStr = ''
+        if self.signed == 1:
+            infoStr += 'Signed'
+        else:
+            infoStr += 'Unsigned'
+
+        if self.immutable == True:
+            infoStr += ' Immutable'
+        
+            
+        return('Register {} bits: {} ({} value: {})'.format(self.regName, self.bits, infoStr, self.value))
+
+    def __add__(self, other):
+        self.setValue(self.value + int(other))
+        return self
+
+    @classmethod 
+    def immutableRegister(cls, xlen, value, signed = 1):
+        reg = cls(xlen = xlen)
+        reg.setValue(newValue = value, signed = signed)
+        reg.setImmutable(immutable = True)
+        return reg
+
+class RegFile():
+    def __init__(self, xlen, numRegs = 32, immutableRegsDict = {0 : 0}, prefix = 'x'):
+        self.xlen = xlen
+        self.numRegs = numRegs
+        self.regs = []
+        self.immutableRegsList = []
+        self.prefix = prefix
+
+        for i in range(0, numRegs):
+            self.regs.append(Register(xlen))
+            self.regs[-1].setRegName('{}{}'.format(prefix, i))
+            
+
+        for immutableRegKey, immutableRegVal in immutableRegsDict.items():
+            self.regs[immutableRegKey].setValue(newValue = immutableRegVal, signed = 1)
+            self.immutableRegsList.append(immutableRegKey)
+                
+    def getRandReg(self):
+        reg = randint(1, len(self.regs)-1)
+        while(reg in self.immutableRegsList):
+            reg = randint(1, len(self.regs)-1)
+        return self.regs[reg]
+    
+    # def getRandMemReg(self):
+    #     reg = randint(1, len(self.memoryreg)-1)
+    #     while(reg in self.immutableRegsList):
+    #         reg = randint(1, len(self.memoryreg)-1)
+    #     return str(reg)
+
+    def randomize(self):
+        for regNum in range(0, self.numRegs):
+            if regNum not in self.immutableRegsList:
+                self.regs[regNum].randomize()
+    
+    def setRegValue(self, regNum, newValue, signed = None):
+        if regNum in self.immutableRegsList:
+            errStr = 'Write to x{} not allowed'.format(regNum)
+            raise WriteToImmutableRegisterException(errStr)
+        if regNum > self.numRegs - 1:
+            errStr = 'Write to x{} exceeds number of registers: {}'.format(regNum, self.numRegs)
+            raise InvalidRegisterNumberException(errStr)
+
+
+        self.regs[regNum].setValue(newValue = newValue, signed = signed)
+
+    def setRegBits(self, regNum, newBits, signed = None):
+        if regNum in self.immutableRegsList:
+            errStr = 'Write to x{} not allowed'.format(regNum)
+            raise WriteToImmutableRegisterException(errStr)
+
+        if regNum > self.numRegs - 1:
+            errStr = 'Write to x{} exceeds number of registers: {}'.format(regNum, self.numRegs)
+            raise InvalidRegisterNumberException(errStr)
+
+        self.regs[regNum].setBits(newBits = newBits, signed = signed)
+        
+    def __str__(self):
+        formattedString = ''
+        for x in range(0, len(self.regs)):
+            formattedString += 'x{}:\t{}\n'.format(str(x), str(self.regs[x]))
+        return formattedString
+
+class Memory():
+    def __init__(self, xlen):
+        self.memDict = {} #keys: strings, values: binary strings
+        self.xlen = int(xlen)
+        self.minVal = 0
+        self.maxVal = 2047
+    def populateMemory(self, memDict):
+        # add all values of memDict to self.memDict
+        # overwrites any values that already exist 
+        for key in memDict.keys():
+            self.memDict[key] = memDict[key]
+
+    def updateMemory(self, addr, granularity, value):
+        # sign extend value to 32 bits
+        if addr > self.maxVal:
+            errStr = 'Tried to write to invalid memory location {} max {}'.format(value, self.maxVal)
+            raise InvalidMemoryWriteLocation(errStr)
+        exValue = signExtend(value, self.xlen)
+        self.memDict[addr] = exValue
+
+    def readMemory(self, addr, granularity):
+        # check if memory is unitilaized 
+        if addr not in self.memDict.keys():
+            errStr = 'Tried to read from uninitialized address: {}'.format(addr)
+            raise ReadFromUninitializedMemoryException(errStr)
+
+        val = self.memDict[addr]
+        if granularity == GRANULARITY.WORD:
+            val = val
+        elif granularity == GRANULARITY.HALFWORD:
+            val = val[-(self.xlen//2):]
+        else:
+            val = val[-(self.xlen//4):]
+        if val == "":
+            return '0'
+        return val
+    
+    def genRandMemoryValue(self):
+
+        #generate a random value
+        minVal = self.minVal
+        maxVal = self.maxVal
+        randValue = randint(0, self.maxVal + 1)
+
+        # #convert to binary string
+        # bitValue = ''
+        # bitValue = bitValue = bin(randValue)[2:] # Remove the 0b
+        # bitValue = signExtend(bitValue, self.xlen)
+        
+        return randValue
+
+class Model():
+    def __init__(self, xlen, numRegs, immutableRegsDict, initPc = 0):
+        self.xlen = int(xlen)
+        self.memory = Memory(xlen=self.xlen)
+        self.regFile = RegFile(xlen=self.xlen, immutableRegsDict = immutableRegsDict)
+        self.pc = Register(xlen=self.xlen, signed=0)
+        self.pc.setValue(newValue=initPc)
+        self.pc.setRegName(newName = 'PC')
+        self.memStart = 0x8000400
+        self.memoryImmediateCounter = 0
+        self.resultImmediateCounter = 0
+        self.totalStoreCount = 0
+    
+class TestGen():
+    def __init__(self, numInstr, immutableRegsDict, instrSet, imperasPath):
+        self.numInstr = numInstr
+        self.instrSet = instrSet
+        self.xlen = int((re.search(r'\d+', instrSet)).group())
+        self.model = Model(xlen=self.xlen, numRegs=16, immutableRegsDict = immutableRegsDict)
+
+        self.prevLabel = 0
+        self.test_count = 0
+
+        self.imperasPath = imperasPath + instrSet.lower() + '/'
+        self.exportTestName = 'PIPELINE'
+        if (self.numInstr == 100000):
+            self.exportTestName += "-100K"
+        elif (self.numInstr == 1000000):
+            self.exportTestName += "-1M"
+        self.basename = 'WALLY-'+ self.exportTestName
+        self.fname = self.imperasPath + "src/" + self.basename + ".S"
+        self.refname = self.imperasPath + "references/" + self.basename + ".reference_output"
+        
+    def genTestInstr(self, reg):
+        imm = Immediate.setImm12(xlen = self.xlen, value = self.model.resultImmediateCounter)
+        reg6 = self.model.regFile.regs[6]
+        out = [Instr.issue(model = self.model, instrName = "sw", rs2 = reg, imm = imm, rs1 = reg6)]
+        self.model.resultImmediateCounter += 4
+        if (self.model.resultImmediateCounter == 2040):
+            # Reset
+            imm2 = Immediate.setImm12(xlen = self.xlen, value = 2040)
+            reg6.setImmutable(False)
+            wreset = Instr.issue(model = self.model, instrName = "addi", rd = reg6, imm = imm2, rs1 = reg6) 
+            reg6.setImmutable(True)
+            self.model.resultImmediateCounter = 0
+            out.append(wreset)     
+        out.append('\n')
+        self.model.totalStoreCount += 1       
+        return out
+
+    def branchInstruction(self, instr):
+        # get field and granularity of instruction
+
+        # randomly determine forward or back branch direction
+        fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0
+        taken = np.random.randint(0,2) #not taken on 0, taken on 1
+
+        # pick 2 registers for branch comparison
+        reg1 = self.model.regFile.getRandReg()
+        reg2 = reg1
+        reg0 = self.model.regFile.regs[0]
+        while(reg2 == reg1):
+            reg2 = self.model.regFile.getRandReg()
+
+        instructions = []
+       
+        
+        if (fwd == 1):
+            # set r1 and r2 to what they should be to do the branching we want
+            if  (instr == "beq" and taken==1)   or (instr == "bne" and taken==0) or \
+                (instr == "blt" and taken==0)   or (instr == "bge" and taken==1) or \
+                (instr == "bltu" and taken==0)  or (instr == "bgeu" and taken==1): #r1 = r2
+                newInstr = Instr.issue(model = self.model, instrName="add", rd = reg1, rs1  = reg2, rs2 = reg0)
+                instructions.append(newInstr)
+
+            elif (instr == "beq" and taken==0)   or (instr == "bne" and taken==1) or \
+                (instr == "blt" and taken==1)   or (instr == "bltu" and taken==1): #r2 = r1 + 1
+                imm = Immediate.setImm12(xlen = self.xlen, value = 1)
+                newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                instructions.append(newInstr)
+
+            else: #r2 = r1 - 1
+                imm = Immediate.setImm12(xlen = self.xlen, value = -1)
+                newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                instructions.append(newInstr)
+
+            # add branching instruction
+            label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+            branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'f')
+            instructions.append(branch)
+            numInstr = np.random.randint(0, 6)
+            # add random alu instructions after branching before branch point
+            for i in range(0, numInstr):
+                curr = "RAND ALU INSTRUCTION"
+                rd = self.model.regFile.getRandReg()
+                r1 = self.model.regFile.getRandReg()
+                r2 = self.model.regFile.getRandReg()
+                instr = "add"
+                if (taken == 0):
+                    instructions.append('add {}, {}, {}'.format(rd.getRegName(), r1.getRegName(), r2.getRegName()))
+                else:
+                    instructions.append(Instr.issue(model = self.model, instrName = instr, rd = rd, rs1 = r1, rs2 = r2))
+
+            instructions.append(str(self.prevLabel) + ":")
+            self.prevLabel += 1
+            return instructions
+        else:
+            if (not taken):
+                if instr == "beq":
+                    randImm = np.random.randint(1, 10)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = randImm)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "bne":
+                    imm = Immediate.setImm12(xlen = self.xlen, value = 0)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                
+                elif instr == "bltu":
+                    # deals with overflow
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    randImm = np.random.randint(1, 11)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = randImm)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "blt":
+                    # deals with overflow
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    randImm = np.random.randint(1, 11)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = randImm)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "bgeu":
+                    # deals with overflow
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 15)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    randImm = np.random.randint(-10, 0)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = randImm)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "bge":
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 15)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    randImm = np.random.randint(-10, 0)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = randImm)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+
+                label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                instructions.append(str(self.prevLabel) + ":")
+                numInstr = np.random.randint(0, 6)
+                # add random alu instructions after branching before branch point
+                for i in range(0, numInstr):
+                    curr = "RAND ALU INSTRUCTION"
+                    rd = self.model.regFile.getRandReg()
+                    while(rd == reg2 or rd == reg1):
+                        rd = self.model.regFile.getRandReg()
+                    r1 = self.model.regFile.getRandReg()
+                    r2 = self.model.regFile.getRandReg()
+                    instrJunk = "add"
+                    instructions.append('add {}, {}, {}'.format(rd.getRegName(), r1.getRegName(), r2.getRegName()))
+                branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'b')
+                instructions.append(branch)  
+            else:
+                #setup reg instructions before any branching stuff
+                if instr == "beq": 
+                    numTimesRepeat = 1 #can only be repeated once with the way we are doing this
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = -1)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "bne":
+                    numTimesRepeat = np.random.randint(2, 6) 
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = -1)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr)
+                
+                elif instr == "bltu": 
+                    numTimesRepeat = np.random.randint(2, 6)*(-1)
+                    # deals with overflow
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = 1)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr)
+                
+                elif instr == "blt":
+                    # deals with overflow
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+                    
+                    numTimesRepeat = np.random.randint(2, 6)*(-1)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = 1)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr)
+
+                elif instr == "bgeu":
+                    numTimesRepeat = np.random.randint(2, 6)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    
+                    # deals with overflow
+                    imm1 = Immediate.setImm12(xlen = self.xlen, value = 2)
+                    newInstr1 = Instr.issue(model = self.model, instrName="srli", rd = reg1, rs1  = reg1, imm = imm1)
+                    instructions.append(newInstr1)
+
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 15)
+                    newInstr2 = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr2)
+
+                    newInstr3 = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr3)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = -1)
+                    newInstr4 = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr4)
+
+                elif instr == "bge":
+                    imm2 = Immediate.setImm12(xlen = self.xlen, value = 15)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg1, rs1  = reg1, imm = imm2)
+                    instructions.append(newInstr)
+                    
+                    numTimesRepeat = np.random.randint(2, 6)
+                    imm = Immediate.setImm12(xlen = self.xlen, value = numTimesRepeat)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg1, imm = imm)
+                    instructions.append(newInstr)
+                    
+                    label = Label(name = self.prevLabel, pcValue = self.model.pc.getValueUnsigned())
+                    instructions.append(str(self.prevLabel) + ":")
+
+                    imm = Immediate.setImm12(xlen = self.xlen, value = -1)
+                    newInstr = Instr.issue(model = self.model, instrName="addi", rd = reg2, rs1  = reg2, imm = imm)
+                    instructions.append(newInstr)
+
+                numInstr = np.random.randint(0, 5)
+                for i in range(0, numInstr):
+                    curr = "RAND ALU INSTRUCTION"
+                    rd = self.model.regFile.getRandReg()
+                    while(rd == reg2) or (rd == reg1):
+                        rd = self.model.regFile.getRandReg()
+                    r1 = self.model.regFile.getRandReg()
+                    r2 = self.model.regFile.getRandReg()
+                    instrJunk = "add"
+                    instructions.append(Instr.issue(model = self.model, instrName = instrJunk, rd = rd, rs1 = r1, rs2 = r2))
+
+                branch = Instr.issue(model = self.model, instrName = instr, rs1 = reg2, rs2 = reg1, label = label, dir = 'b')
+                instructions.append(branch) 
+            self.prevLabel += 1
+        return instructions
+
+
+    def getForwardingInstructions(self, instr):
+        ld_instr = instr
+        divBy = 1 
+        
+        granularity = None
+        if (instr == "lw"):
+            granularity = GRANULARITY.WORD
+        elif (instr == "lh") | (instr == 'lhu'):
+            divBy = self.xlen//2
+            granularity = GRANULARITY.HALFWORD
+        else:
+            divBy = self.xlen//4
+            granularity =  GRANULARITY.BYTE
+
+        instructions = []
+        
+        rd = self.model.regFile.getRandReg()
+        reg1 = self.model.regFile.regs[7]
+
+        memVal = self.model.memoryImmediateCounter
+        self.model.memoryImmediateCounter += 4
+        if instr == "ld":
+            if ((memVal + reg1.getValueUnsigned()) % 8) != 0:
+                memVal -= 4
+                self.model.memoryImmediateCounter -= 4 # we haven't read from a new location
+
+        
+        
+        if (self.model.memoryImmediateCounter == 2040):
+            self.model.memoryImmediateCounter = 0
+            immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
+            instructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = reg1, rs1 = reg1, imm = immMem))
+
+
+        imm1 = Immediate.setImm12(xlen = self.model.xlen, value = memVal)
+
+        reg2 = self.model.regFile.getRandReg()
+        instructions.append(Instr.issue(model = self.model, instrName = "sw" , rs2 = reg2, rs1 = reg1, imm = imm1))
+    
+        
+        while (rd == reg1):
+            rd = self.model.regFile.getRandReg()
+        instructions.append(Instr.issue(model = self.model, instrName = ld_instr, rd = rd, rs1 = reg1, imm = imm1))
+        
+        return instructions
+
+    def jumpInstruction(self, instr):
+        # fields, alignment = self.instrDict.instr[instr]
+        granularity = GRANULARITY.BYTE
+        divBy = 1
+
+        # randomly determine forward or back branch direction
+        fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0
+        taken = np.random.randint(0,2) #not taken on 0, taken on 1
+
+        reg_pc = self.model.regFile.getRandReg()
+        instructions = []
+
+        label1 = Label(name = 1, pcValue = self.model.pc.getValueUnsigned())
+        label2 = Label(name = 2, pcValue = self.model.pc.getValueUnsigned())
+        label3 = Label(name = 3, pcValue = self.model.pc.getValueUnsigned())
+
+        if fwd == 1:
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, label = label1, dir = "f")  
+            instructions.append(newInstr)
+            
+            numInstr = np.random.randint(0, 6)
+            # add random alu instructions after jumping before jump point
+            reg_check = self.model.regFile.getRandReg()
+            for i in range(0, numInstr):
+                rd = self.model.regFile.getRandReg()
+                while (rd == reg_pc):
+                    rd = self.model.regFile.getRandReg()
+                reg_check = rd
+                r1 = self.model.regFile.getRandReg()
+                r2 = self.model.regFile.getRandReg()
+                instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2))
+            instructions.append("1:")
+            self.model.pc += 4
+
+            # #make sure jump was taken
+            check_instr = self.genTestInstr(reg_check)
+            for check in check_instr:
+                instructions.append(check)
+
+            # #check value in pc + 4 reg
+            check_instr = self.genTestInstr(reg_pc)
+            for check in check_instr:
+                instructions.append(check)
+        else:
+            reg1 = self.model.regFile.getRandReg()
+            reg2 = self.model.regFile.getRandReg()
+            while reg2 == reg1:
+                reg2 = self.model.regFile.getRandReg()
+            
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg1, label = label1, dir = "f")  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg1 + ", 1f")
+            
+            instructions.append("2:")
+            self.model.pc += 4
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, label = label3, dir = "f")  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg2 + ", 3f")
+            
+            instructions.append("1:")
+            self.model.pc += 4
+
+            numInstr = np.random.randint(0,6)
+            for i in range(0, numInstr):
+                rd = self.model.regFile.getRandReg()
+                r1 = self.model.regFile.getRandReg()
+                r2 = self.model.regFile.getRandReg()
+                instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2))
+            
+            #test case here
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg2, label = label2, dir = "b")  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg2 + ", 2b")
+            instructions.append("3:")
+            self.model.pc += 4
+            
+            check_instr = self.genTestInstr(reg1)
+            for check in check_instr:
+                instructions.append(check)
+            
+                # jump to 1
+                # #2
+                #     jump to 3
+                # #1
+                #     junk here
+                #     test: jump to 2
+                # #3  
+                #     check answer from 1
+        return instructions
+
+
+    def jumpRInstruction(self, instr):
+        # fields, alignment = self.instrDict.instr[instr]
+        granularity = GRANULARITY.BYTE
+        divBy = 1
+
+        # randomly determine forward or back branch direction
+        fwd = np.random.randint(0, 2) #fwd on 1, bwd on 0
+
+        reg_pc = self.model.regFile.getRandReg()
+        instructions = []
+
+        label1 = Label(name = 1, pcValue = self.model.pc.getValueUnsigned())
+        label2 = Label(name = 2, pcValue = self.model.pc.getValueUnsigned())
+        label3 = Label(name = 3, pcValue = self.model.pc.getValueUnsigned())
+
+        if fwd == 1:
+            numInstr = np.random.randint(0, 6)
+            
+            rs1 = self.model.regFile.getRandReg()
+            while (rs1 == reg_pc):
+                rs1 = self.model.regFile.getRandReg() 
+                
+            # TODO fix the value of rs1 - should be pc location of "1f"
+            rs1.setValue(newValue = 0)
+            
+            imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
+            
+            instructions.append('la {}, {}'.format(rs1.regName , "1f"))
+            self.model.pc += 8     
+
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)  
+            instructions.append(newInstr)
+            
+            # add random alu instructions after jumping before jump point
+            reg_check = self.model.regFile.getRandReg()
+            for i in range(0, numInstr):
+                rd = self.model.regFile.getRandReg()
+                while (rd == reg_pc):
+                    rd = self.model.regFile.getRandReg()
+                reg_check = rd
+                r1 = self.model.regFile.getRandReg()
+                r2 = self.model.regFile.getRandReg()
+                instructions.append(Instr.issue(model = self.model, instrName = "and", rd = rd, rs1 = r1, rs2 = r2))
+
+            instructions.append("1:")
+            self.model.pc += 4
+
+            #make sure jump was taken
+            check_instr = self.genTestInstr(reg_check)
+            for check in check_instr:
+                instructions.append(check)
+
+            #check value in pc + 4 reg
+            check_instr = self.genTestInstr(reg_pc)
+            for check in check_instr:
+                instructions.append(check)
+        else:
+            reg1 = self.model.regFile.getRandReg()
+            reg2 = self.model.regFile.getRandReg()
+            while reg2 == reg1:
+                reg2 = self.model.regFile.getRandReg()
+            
+            jumpDestVal = self.model.pc.value + 4
+            newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg1, label = label1, dir = "f")  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg1 + ", 1f")
+            
+            instructions.append("2:")
+            self.model.pc += 4
+
+            newInstr = Instr.issue(model = self.model, instrName='jal', rd = reg2, label = label3, dir = "f")  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg2 + ", 3f")
+            
+            instructions.append("1:")
+            self.model.pc += 4
+
+
+            rs1 = self.model.regFile.getRandReg()
+            while (rs1 == reg_pc):
+                rs1 = self.model.regFile.getRandReg()
+                
+            imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
+            
+            
+            instructions.append('la {}, {}'.format(rs1.regName ,"2b"))
+            self.model.pc += 8
+
+            
+            rs1.setValue(newValue = 0) #TODO: this value is wrong, should be address of label
+            imm = Immediate.setImm12(xlen = self.model.xlen, value = 0)
+
+
+            numInstr = np.random.randint(0,6)
+            for i in range(0, numInstr):
+                rd = self.model.regFile.getRandReg()
+                while(rd == rs1) or (rd == reg_pc):
+                    rd = self.model.regFile.getRandReg()
+                r1 = self.model.regFile.getRandReg()
+                r2 = self.model.regFile.getRandReg()
+                instructions.append(Instr.issue(model = self.model, instrName = 'and', rd = rd, rs1 = r1, rs2 = r2))
+            
+            #test case here
+            newInstr = Instr.issue(model = self.model, instrName=instr, rd = reg_pc, rs1 = rs1, imm = imm)  
+            instructions.append(newInstr)
+            # instructions.append("jal x" + reg2 + ", 2b")
+            instructions.append("3:")
+            self.model.pc += 4
+            
+            check_instr = self.genTestInstr(reg1)
+            for check in check_instr:
+                instructions.append(check)
+            
+            check_instr = self.genTestInstr(reg_pc)
+            for check in check_instr:
+                instructions.append(check)
+            
+                # jump to 1
+                # #2
+                # jump to 3
+                # #1
+                # junk instructions
+                # ...
+                # ...
+                # test instruction to 2
+                # #3  
+                # check answer from 1
+        return instructions
+
+    def generateASM(self, instrSet, instrTypes):
+        generatedInstructions = []
+
+        # for memLocation in self.model.memory.memDict.keys():
+        #     memData = self.model.memory.readMemory(addr = memLocation, granularity = GRANULARITY.WORD)
+        #     memDataVal = hex(int(memData, 2))
+        #     generatedInstructions.append('li x2, MASK_XLEN({})'.format(memDataVal))
+        #     self.model.pc += 8
+        #     generatedInstructions.append('li x3, MASK_XLEN({})'.format(memLocation))
+        #     self.model.pc += 8
+        #     generatedInstructions.append('sw x2, 0(x3)')
+        #     self.model.pc += 4
+
+        generatedInstructions.append('la x7, test_data')
+        self.model.pc += 8
+
+        for reg in self.model.regFile.regs:
+            if (int(reg.regName[-1:]) not in self.model.regFile.immutableRegsList) :
+                immHex = randHex(False, 5, 1)
+                imm = int(immHex, 16)
+                reg.setValue(imm)
+                generatedInstructions.append('li {}, MASK_XLEN({})'.format(reg.getRegName(), immHex))
+                self.model.pc += 8
+            elif (reg == self.model.regFile.regs[0]):
+                immHex = 0
+                imm = 0
+                reg.setValue(imm)
+                generatedInstructions.append('li {}, MASK_XLEN({})'.format(reg.getRegName(), immHex))
+                self.model.pc += 8
+            elif (reg == self.model.regFile.regs[6]):
+                # immHex = 0
+                # imm = 0
+                # reg.setValue(imm)
+                # generatedInstructions.append('la {}, {}'.format(reg.getRegName(), "test_1_res"))
+                # self.model.pc += 8
+                pass
+        for i in range(0, self.numInstr):
+            # decide which instruction to issue
+            randInstr = instrSet[randint(0, len(instrSet)-1)]
+
+            randNum = randint(0, 2)
+            if randInstr in InstrTypes['B']:
+                newInstr = self.branchInstruction(instr = randInstr)
+                for i in newInstr:
+                    generatedInstructions.append(i)
+            elif randInstr in InstrTypes['J']:
+                newInstr = self.jumpInstruction(instr = randInstr)
+                for i in newInstr:
+                    generatedInstructions.append(i)
+            elif randInstr[0] == 'l' and randNum == 0 and randInstr != "lui":
+                newInstr = self.getForwardingInstructions(instr = randInstr)
+                for i in newInstr:
+                    generatedInstructions.append(i)
+            else:
+                if randInstr in InstrTypes['R']:
+                    rd = self.model.regFile.getRandReg()
+                    rs1 = self.model.regFile.getRandReg()
+                    rs2 = self.model.regFile.getRandReg()
+                    instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, rs2 = rs2)
+                    generatedInstructions.append(instr)
+
+                    testInstrs = self.genTestInstr(rd)
+                    for testInstr in testInstrs:
+                        generatedInstructions.append(testInstr)
+
+                elif randInstr in InstrTypes['I']:
+                    if randInstr == "jalr":
+                        newInstr = self.jumpRInstruction(instr = randInstr)
+                        for i in newInstr:
+                            generatedInstructions.append(i)
+                    # memory instruction
+                    elif randInstr[0] == 'l': 
+                        rs1 = self.model.regFile.regs[7]
+
+                        memLocation = list(self.model.memory.memDict.keys())[randint(0, len(self.model.memory.memDict.keys()) -1)]
+                        if randInstr == "ld":
+                            if ((memLocation + rs1.getValueUnsigned()) % 8) != 0:
+                                if (memLocation != 0):
+                                    memLocation -=4
+                                else:
+                                    memLocation = 4
+
+                        rd = self.model.regFile.getRandReg()
+                        
+                        imm12 = Immediate.setImm12(xlen = self.model.xlen, value = memLocation)
+                        instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12)
+                        generatedInstructions.append(instr)
+
+                        testInstrs = self.genTestInstr(rd)
+                        for testInstr in testInstrs:
+                            generatedInstructions.append(testInstr)
+                    else:
+                        rd = self.model.regFile.getRandReg()
+                        rs1 = self.model.regFile.getRandReg()
+                        imm12 = Immediate.randImm12(xlen = self.model.xlen)
+
+                        instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, rs1 = rs1, imm = imm12)
+                        generatedInstructions.append(instr)
+
+                        testInstrs = self.genTestInstr(rd)
+                        for testInstr in testInstrs:
+                            generatedInstructions.append(testInstr)
+
+                elif randInstr in InstrTypes['S']:
+                    rs1 = self.model.regFile.regs[7]
+
+                    immValue = self.model.memoryImmediateCounter
+                    self.model.memoryImmediateCounter += 4
+                    if randInstr == 'Sd':
+                        if ((immValue + rs1.getValueUnsigned()) % 8) != 0:
+                            immValue -= 4
+                            self.model.memoryImmediateCounter -= 4 #haven't put a value in a new mem locatoin
+                    
+                    rs2 = self.model.regFile.getRandReg()
+                    
+
+                    immMem = Immediate.setImm12(xlen = self.model.xlen, value = 2040)
+                    if (self.model.memoryImmediateCounter == 2040):
+                        self.model.memoryImmediateCounter = 0
+                        generatedInstructions.append(Instr.issue(model = self.model, instrName = "addi" , rd = rs1, rs1 = rs1, imm = immMem))
+
+                    imm12 = Immediate.setImm12(xlen = self.model.xlen, value = immValue)
+                    instr = Instr.issue(model = self.model, instrName = randInstr, rs1 = rs1, rs2 = rs2, imm = imm12)
+                    generatedInstructions.append(instr)
+
+                elif randInstr in InstrTypes['U']:
+                    rd = self.model.regFile.getRandReg()
+                    imm20 = Immediate.randImm20(xlen = self.model.xlen, signed = 0)
+                    instr = Instr.issue(model = self.model, instrName = randInstr, rd = rd, imm = imm20)
+                    generatedInstructions.append(instr)
+
+                    testInstrs = self.genTestInstr(rd)
+                    for testInstr in testInstrs:
+                        generatedInstructions.append(testInstr)
+
+                elif randInstr in InstrTypes['R4']:
+                    continue
+                else:
+                    # INVALID INSTR
+                    print(randInstr)
+                    print("You made a typo")
+        return generatedInstructions    
+
+    def exportASM(self, instrSet, instrTypes):
+        asmFile = open(self.fname, 'w')
+        refFile = open(self.refname, 'w')
+        
+        # Custom Header
+        line = "///////////////////////////////////////////\n"
+        asmFile.write(line)
+        line ="// "+self.fname+ "\n// " + "Ethan Falicov & Shriya Nadgauda" + "\n"
+        asmFile.write(line)
+        line ="// Created " + str(datetime.now())  + "\n" + "\n"
+        asmFile.write(line)
+        line = "// Begin Tests" + "\n"
+        asmFile.write(line)
+
+        # Generic Header
+        headerFile = open("testgen_header.S", "r")
+        for line in headerFile:  
+            asmFile.write(line)
+        asmFile.write("\n")
+
+
+        # Write Instructions
+        generatedInstructions = self.generateASM(instrSet = INSTRSETS[instrSet], instrTypes = instrType)
+        for generatedInstr in generatedInstructions:
+            asmFile.write("\t" + generatedInstr + "\n")
+            if ("RVTEST_IO_ASSERT_GPR_EQ" in generatedInstr):
+                asmFile.write("\n")
+
+        # Footer
+        footerFile = open("testgen_footer.S", "r")
+        lineNum = 0
+        for line in footerFile:  
+            asmFile.write(line)
+            if lineNum  == 14:
+                asmFile.write('test_data:\n')
+                memList = list(self.model.memory.memDict.keys())
+                memList.sort()
+                paddingSize = 0
+                for memLoc in memList:
+                    hexVal = int(self.model.memory.memDict[memLoc],2)
+                    hexDigitSize = self.model.xlen / 4
+                    formattedStr = '0x{0:0{1}x}'.format(hexVal, hexDigitSize)
+                    if self.model.xlen == 64:
+                        asmFile.write('\t.dword {}\n'.format(formattedStr))
+                    else:
+                        asmFile.write('\t.word {}\n'.format(formattedStr))
+            lineNum += 1
+        
+        asmFile.write("\n")
+        line = "\t.fill " + str(self.model.totalStoreCount) + ", " + str(self.xlen//8) + ", -1\n"
+        asmFile.write(line)
+        asmFile.write("\n")
+        
+        line = "\nRV_COMPLIANCE_DATA_END\n" 
+        asmFile.write(line)
+        
+        asmFile.close()
+        refFile.close()
+
+class Instr():
+    @classmethod
+    def issue(self, model, instrName, **kwargs):
+        funcName = 'Instr_' + str(instrName)
+        return getattr(Instr, funcName)(model = model, **kwargs)
+ 
+    @classmethod
+    def Instr_label(self, model, label = None):
+        label.pcValue = model.pc.value
+        model.pc += 4
+        return '{}:'.format(label.name)
+
+    ###############################################################################################
+    # RV32I Instructions
+    ###############################################################################################
+    @classmethod
+    def Instr_lb(self, model, rd = None, rs1 = None, imm = None):  
+        addr = imm.getDecValue()
+        rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lb {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+        
+    @classmethod
+    def Instr_lh(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.HALFWORD), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lh {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+    
+    @classmethod
+    def Instr_lw(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lw {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_lbu(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lbu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+        
+    @classmethod
+    def Instr_lhu(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.HALFWORD), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lhu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_addi(self, model, rd = None, rs1 = None, imm = None):
+        newValue = rs1.getDecValue() + imm.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'addi {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+        
+    @classmethod
+    def Instr_slli(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[-(len(bits) - immShift):]
+        shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
+        rd.setValue(newValue = shiftedExt, signed = 1)
+        model.pc += 4
+        return 'slli {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_slti(self, model, rd = None, rs1 = None, imm = None):
+        if (rs1.getValueSigned() < imm.getValueSigned()):
+            rd.setValue(newValue = 1, signed = 1)
+        else:
+            rd.setValue(newValue = 0, signed = 1)
+        model.pc += 4
+        return 'slti {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_sltiu(self, model, rd = None, rs1 = None, imm = None):
+        if (rs1.getValueUnsigned() < imm.getValueUnsigned()):
+            rd.setValue(newValue = 1, signed = 1)
+        else:
+            rd.setValue(newValue = 0, signed = 1)
+        model.pc += 4
+        return 'slti {}, {}, SEXT_IMM({})'.format(rd.getRegName(),rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_xori(self, model, rd = None, rs1 = None, imm = None):
+        newValue = rs1.getDecValue() ^ imm.getDecValue()
+        rd.setValue(newValue = newValue, signed = rs1.signed)
+        model.pc += 4
+        return 'xori {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_srli(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[0:len(bits) - immShift]
+        extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'srli {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_srai(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[0:len(bits) - immShift]
+        extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'srai {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_ori(self, model, rd = None, rs1 = None, imm = None):
+        rd.setValue(newValue = (rs1.getDecValue() | imm.getDecValue()), signed = rs1.signed)
+        return 'ori {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_andi(self, model, rd = None, rs1 = None, imm = None):
+        rd.setValue(newValue = (rs1.getDecValue() & imm.getDecValue()), signed = rs1.signed)
+        return 'andi {}, {}, SEXT_IMM({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_auipc(self, model, rd = None, imm = None):
+        rd.setValue(newValue = binToDec(inputBits = imm.bits[:-12] + '0'*12) + model.pc.getDecValue(), signed = 1)
+        return 'auipc {}, MASK_XLEN({})'.format(rd.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_sb(self, model, rs1 = None, rs2 = None, imm = None):
+        addr = imm.getDecValue()
+        if addr in model.memory.memDict.keys():
+            originalMem = model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD)
+            model.memory.updateMemory(addr = addr, value = originalMem[:-8] + rs2.bits[-8:], granularity = GRANULARITY.WORD)
+        else:
+            model.memory.updateMemory(addr = addr, value = '0'*(model.xlen - 8) + rs2.bits[-8:], granularity = GRANULARITY.WORD)
+        model.pc += 4
+        return 'sb {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_sh(self, model, rs1 = None, rs2 = None, imm = None):
+        addr = imm.getDecValue()
+        if addr in model.memory.memDict.keys():
+            originalMem = model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD)
+            model.memory.updateMemory(addr = addr, value = originalMem[:-16] + rs2.bits[-16:], granularity = GRANULARITY.WORD)
+        else:
+            model.memory.updateMemory(addr = addr, value = '0'*(model.xlen - 16) + rs2.bits[-16:], granularity = GRANULARITY.WORD)
+        model.pc += 4
+        return 'sh {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_sw(self, model, rs1 = None, rs2 = None, imm = None):
+        addr = imm.getDecValue()
+        model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD)
+        model.pc += 4
+        return 'sw {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_add(self, model, rd = None, rs1 = None, rs2 = None):
+        newValue = rs1.getDecValue() + rs2.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'add {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_sub(self, model, rd = None, rs1 = None, rs2 = None):
+        newValue = rs1.getDecValue() - rs2.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'sub {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_sll(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[-(len(bits) - rs2Shift):]
+        shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
+        rd.setValue(newValue = shiftedExt, signed = 1)
+        model.pc += 4
+        return 'sll {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_slt(self, model, rd = None, rs1 = None, rs2 = None):
+        if (rs1.getDecValue() < rs2.getDecValue()):
+            rd.setValue(newValue = 1, signed = 1)
+        else:
+            rd.setValue(newValue = 0, signed = 1)
+        model.pc += 4
+        return 'slt {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+
+    @classmethod
+    def Instr_sltu(self, model, rd = None, rs1 = None, rs2 = None):
+        if (rs1.getValueUnsigned() < rs2.getValueUnsigned()):
+            rd.setValue(newValue = 1, signed = 1)
+        else:
+            rd.setValue(newValue = 0, signed = 1)
+        model.pc += 4
+        return 'sltu {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_xor(self, model, rd = None, rs1 = None, rs2 = None):
+        rd.setValue(newValue = (rs1.getDecValue() ^ rs2.getDecValue()), signed = rs1.signed)
+        model.pc += 4
+        return 'xor {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_srl(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[0:len(bits) - rs2Shift]
+        extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'srl {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_sra(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[0:len(bits) - rs2Shift]
+        extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'sra {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_or(self, model, rd = None, rs1 = None, rs2 = None):
+        rd.setValue(newValue = (rs1.getDecValue() | rs2.getDecValue()), signed = rs1.signed)
+        model.pc += 4
+        return 'or {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_and(self, model, rd = None, rs1 = None, rs2 = None):
+        rd.setValue(newValue = (rs1.getDecValue() & rs2.getDecValue()), signed = rs1.signed)
+        model.pc += 4
+        return 'and {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_lui(self, model, rd = None, imm = None):
+        rd.setValue(newValue = binToDec(inputBits = imm.bits[:20] + '0'*(model.xlen-20)) , signed = 1)
+        model.pc += 4
+        return 'lui {}, {}'.format(rd.getRegName(), imm.getDecValue())
+
+
+    @classmethod
+    def Instr_beq(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueSigned() == rs2.getValueSigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'beq {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_bne(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueSigned() != rs2.getValueSigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'bne {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_blt(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueSigned() < rs2.getValueSigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'blt {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_bge(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueSigned() >= rs2.getValueSigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'bge {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_bltu(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueUnsigned() < rs2.getValueUnsigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'bltu {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_bgeu(self, model, rs1 = None, rs2 = None, label = None, dir = None):
+        if (rs1.getValueUnsigned() >= rs2.getValueUnsigned()):
+            model.pc.setValue(label.pcValue)
+        else:
+            model.pc += 4
+        return 'bgeu {}, {}, {}{}'.format(rs1.getRegName(), rs2.getRegName(), label.name, dir)
+
+    @classmethod
+    def Instr_jalr(self, model, rd = None, rs1 = None, imm = None):
+        rd.setValue(newValue = model.pc.getDecValue() + 4, signed = 1)
+        model.pc.setValue(rs1.getDecValue() + imm.getDecValue())
+        return 'jalr {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+
+    @classmethod
+    def Instr_jal(self, model, rd = None, label = None, dir = None):
+        rd.setValue(newValue = model.pc.getDecValue() + 4, signed = 1)
+        model.pc.setValue(label.pcValue)
+        return 'jal {}, {}{}'.format(rd.getRegName(), label.name, dir)
+
+
+    
+    
+    ###################################################################################################
+    # RV 64I
+    ###################################################################################################
+    #TODO These may not keep the internal model consistent. You have been warned...sorry lol
+    
+    @classmethod
+    def Instr_ld(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = signExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.WORD), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'ld {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_lwu(self, model, rd = None, rs1 = None, imm = None):
+        addr = imm.getDecValue()
+        rd.setBits(newBits = zeroExtend(model.memory.readMemory(addr = addr, granularity = GRANULARITY.BYTE), \
+            resultNumBits = model.xlen))
+        model.pc += 4
+        return 'lwu {}, {}({})'.format(rd.getRegName(), imm.getDecValue(), rs1.getRegName())
+    
+    @classmethod
+    def Instr_addiw(self, model, rd = None, rs1 = None, imm = None):
+        newValue = rs1.getDecValue() + imm.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue())
+    
+    @classmethod
+    def Instr_slliw(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[-(len(bits) - immShift):]
+        shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
+        rd.setValue(newValue = shiftedExt, signed = 1)
+        model.pc += 4
+        return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_srliw(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[0:len(bits) - immShift]
+        extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None):
+        bits = rs1.bits
+        immBits = imm.bits[-5:]
+        immShift = int(immBits, 2)
+        shifted = bits[0:len(bits) - immShift]
+        extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits)
+
+    @classmethod
+    def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None):
+        addr = imm.getDecValue()
+        model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD)
+        model.pc += 4
+        return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName())
+
+    @classmethod
+    def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None):
+        newValue = rs1.getDecValue() + rs2.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+    
+    @classmethod
+    def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None):
+        newValue = rs1.getDecValue() - rs2.getDecValue()
+        newValueBin = 0
+        if newValue > 0:
+            newValueBin = bin(newValue)[2:]
+        elif newValue == 0:
+            newValueBin = "0" * model.xlen
+        else:
+            newValueBin = bin(newValue)[3:]
+        newValueBinTrunk = newValueBin[-model.xlen:]
+        rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1)
+        model.pc += 4
+        return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+        
+    @classmethod
+    def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[-(len(bits) - rs2Shift):]
+        shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted)))
+        rd.setValue(newValue = shiftedExt, signed = 1)
+        model.pc += 4
+        return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+    @classmethod
+    def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[0:len(bits) - rs2Shift]
+        extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+    
+    @classmethod
+    def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None):
+        bits = rs1.bits
+        rs2Bin = rs2.bits[-5:]
+        rs2Shift = int(rs2Bin,2)
+        shifted = bits[0:len(bits) - rs2Shift]
+        extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen)
+        rd.setBits(newBits = extShifted, signed = 1)
+        model.pc += 4
+        return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName())
+
+
+###################################################################################################
+# Global Constants
+###################################################################################################
+GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE'])
+# 'jalr',
+INSTRSETS = {'RV32I':   ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
+                        'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
+                        'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
+                        'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \
+            'RV64I':   ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \
+                        'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \
+                        'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \
+                        'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jalr', 'jal', \
+                        'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw', 'Sd', 'addw', 'subw', \
+                        'sllw', 'srlw', 'sraw'] \
+            }
+
+
+InstrTypes = {  'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \
+                        'addw', 'subw', 'sllw', 'srlw', 'sraw'], \
+                'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \
+                        'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \
+                'S' : ['sw', 'sh', 'sb', 'Sd'], \
+                'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \
+                'U' : ['lui', 'auipc'], \
+                'J' : ['jal'],  \
+                'R4': []}
+###################################################################################################
+# Main Body
+###################################################################################################
+
+XLEN = ['32', '64']
+INSTRUCTION_TYPE = ['I']
+NUMINSTR = [100000, 1000000]
+IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/"
+
+seed(42)
+np.random.seed(42)
+for num_instructions in NUMINSTR:
+    for xlen in XLEN:
+        memInit = {}
+        for i in range(0, 400, 4):
+            val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1)
+            memInit[i] = val
+        for instrType in INSTRUCTION_TYPE:
+            instrSet = 'RV' + xlen + instrType
+
+            print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet))
+            
+            dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH)
+            # regFile = 
+            dut.model.memory.populateMemory(memDict = memInit)
+            dut.exportASM(instrSet = instrSet, instrTypes = instrType)
\ No newline at end of file
diff --git a/tests/testgen/imperas/testgen-SLL-SRL-SRA.py b/tests/testgen/imperas/testgen-SLL-SRL-SRA.py
new file mode 100755
index 000000000..6b4996d90
--- /dev/null
+++ b/tests/testgen/imperas/testgen-SLL-SRL-SRA.py
@@ -0,0 +1,154 @@
+#!/usr/bin/python3
+##################################
+# testgen-SLL-SRL-SRA.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def twoscomp(a):
+  amsb = a >> (xlen-1)
+  alsbs = ((1 << (xlen-1)) - 1) & a
+  if (amsb):
+      asigned = a - (1<<xlen)
+  else:
+      asigned = a
+  #print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
+  return asigned
+
+def computeExpected(a, b, test, xlen):
+  asigned = twoscomp(a)
+  b = b % xlen
+  if (test == "SLL"):
+    return a << b
+  elif (test == "SRL"):
+    return a >> b
+  elif (test == "SRA"):
+    return asigned >> b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd, xlen):
+  global testnum
+  expected = computeExpected(a, b, test, xlen)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["SLL", "SRL", "SRA"]
+author = "David_Harris@hmc.edu"
+xlens = [32, 64]
+numrand = 48
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+    corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+    if (xlen == 32):
+        shamt = [0, 1, 2, 3, 4, 8, 15, 16, 29, 30, 31]
+    else:
+        shamt = [0, 1, 3, 8, 15, 16, 29, 31, 32, 47, 48, 62, 63]
+
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners:
+      for b in shamt:
+        writeVector(a, b, storecmd, xlen)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, b, storecmd, xlen)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py b/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py
new file mode 100644
index 000000000..201763890
--- /dev/null
+++ b/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py
@@ -0,0 +1,189 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADD-SUB.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def computeExpected(a, b, test):
+  if (test == "SLLI"):
+    return a << b
+  elif (test == "SRLI"):
+      return srli(a,b)
+  elif (test == "SRAI"):
+      return a >> b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def signExt(b, bits):
+  a_str = bin(b)[2::]
+  if (a_str[0] == "b"):
+    a_str = a_str[1:]
+
+  if (len(a_str) < 12):
+    zeroPadding = "0" * (bits - len(a_str))
+    a_str = zeroPadding + a_str
+  
+  print( "{:x}, {:s} ".format(b, a_str))
+  padding = a_str[len(a_str)-1] * (bits - len(a_str))
+  return int(padding + a_str, 2)
+
+
+def evaluateTwoComplement(b, bits):
+  if (b & (1 << (bits -1))!= 0):
+    b = b - (1 << bits)
+  return b
+
+
+def srli(a,b):
+    if (a < 0):
+        a = 2**xlen + a
+    if (b==0):
+        return a
+    a_str = bin(a)[2:]
+    if a_str[0]== "b":
+        a_str = a_str[1:]
+    # print(a_str)
+    numZeroPad = (len(a_str)-abs(b))
+    out = a_str[:numZeroPad]
+    if (numZeroPad <= 0):
+        return 0
+    print("a: {:b}, b: {:d}, out:{:b}".format(a, b, int(out,2)))
+    return int(out,2)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg3 == 6):
+    return randRegs()
+  else:
+      return reg1, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+
+
+  
+
+  expected = computeExpected(evaluateTwoComplement(a, xlen), b, test)
+#   print( "original {:x}, sign Extended {:x} ".format(b, signExt(b,xlen)))
+#   print (str(a)  + "<" + str(signExt(b,xlen)) + " : " + str(expected))
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+
+
+
+  reg1, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), imm5:" + "(" +formatstrimm5.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", " + formatstrimm5.format(b) + "\n"
+  # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["SLLI", "SRLI", "SRAI"]
+author = "Shriya Nadgauda & Ethan Falicov"
+xlens = [32, 64]
+numrand = 100
+
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+
+  formatstrimm5 = "0b{:05b}" # format as 5-bit binary number
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for test in tests:
+    corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+
+    immBitSize = 5
+    corners2 = [0, 1, 2, 0x07, 0x14 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, 
+            2**(immBitSize-1), 2**(immBitSize-1)+1, 0x06 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1]
+   
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners1:
+      for b in corners2:
+        writeVector(a, b, storecmd)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(5)
+      writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
diff --git a/tests/testgen/imperas/testgen-SLTIU.py b/tests/testgen/imperas/testgen-SLTIU.py
new file mode 100644
index 000000000..25eb5ddfb
--- /dev/null
+++ b/tests/testgen/imperas/testgen-SLTIU.py
@@ -0,0 +1,173 @@
+#!/usr/bin/python3
+##################################
+# testgen-ADD-SUB.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def computeExpected(a, b, test):
+  if (test == "SLTIU"):
+    return a < b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def signExt(b, bits):
+  a_str = bin(b)[2::]
+  if (a_str[0] == "b"):
+    a_str = a_str[1:]
+
+  if (len(a_str) < 12):
+    zeroPadding = "0" * (12 - len(a_str))
+    a_str = zeroPadding + a_str
+  
+  
+  padding = a_str[0] * (bits - len(a_str))
+  print( "b {:x}, sign extended {:s} ".format(b, padding + a_str))
+  return int(padding + a_str, 2)
+
+
+
+def evaluateTwoComplement(b, bits):
+  if (b & (1 << (bits -1))!= 0):
+    b = b - (1 << bits)
+  return b
+
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg3 == 6):
+    return randRegs()
+  else:
+      return reg1, reg3
+
+def writeVector(a, b, storecmd):
+  global testnum
+
+
+  
+  signExtImm = signExt(b,xlen)
+  if signExtImm < 0:
+    signExtImm = signExtImm + 2 ** xlen
+  expected = computeExpected(a, signExtImm, test)
+  # s
+  
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+
+
+
+  reg1, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), imm12:" + "(" +formatstrimm12.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", SEXT_IMM(" + formatstrimm12.format(b) + ")\n"
+  # lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " +"x" + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["SLTIU"]
+author = "Shriya Nadgauda & Ethan Falicov"
+xlens = [32, 64]
+numrand = 100
+
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+
+  formatstrimm12 = "0x{:03x}" # format as 3-bit hexadecimal number
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for test in tests:
+    corners1 = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+
+    immBitSize = 12
+    corners2 = [0, 1, 2, 0xFF, 0x624 % 2**immBitSize, 2**(immBitSize-1)-2, 2**(immBitSize-1)-1, 
+            2**(immBitSize-1), 2**(immBitSize-1)+1, 0xC36 % 2**immBitSize, 2**(immBitSize)-2, 2**(immBitSize)-1]
+
+    imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
+    basename = "WALLY-" + test 
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners1:
+      for b in corners2:
+        writeVector(a, b, storecmd)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(12)
+      writeVector(a, b, storecmd)
+
+
+    # print footer
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
diff --git a/tests/testgen/imperas/testgen-STORE.py b/tests/testgen/imperas/testgen-STORE.py
new file mode 100755
index 000000000..d4a995d48
--- /dev/null
+++ b/tests/testgen/imperas/testgen-STORE.py
@@ -0,0 +1,282 @@
+#!/usr/bin/python3
+##################################
+# testgen-STORE.py
+#
+# Jessica Torrey <jtorrey@hmc.edu>  03 February 2021
+# Thomas Fleming <tfleming@hmc.edu> 03 February 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint, seed, getrandbits
+from textwrap import dedent
+
+##################################
+# global structures
+##################################
+size_to_store = {8: "sd", 4: "sw", 2: "sh", 1: "sb"}
+size_to_load = {8: "ld", 4: "lw", 2: "lh", 1: "lb"}
+store_to_size = {"sd": 8, "sw": 4, "sh": 2, "sb": 1}
+testcase_num = 0
+signature_len = 2000
+signature = [0xff for _ in range(signature_len)]
+
+##################################
+# functions
+##################################
+
+def rand_reg():
+  """
+  Produce a random register from 1 to 31 (skipping 6, since r6 is used for
+  other things).
+  """
+  r = randint(1,30)
+  if r >= 6:
+    r += 1
+  return r
+
+def rand_regs():
+  """
+  Generate two random, unequal register numbers (skipping x6).
+  """
+  rs1 = rand_reg()
+  rs2 = rand_reg()
+  while rs1 == rs2:
+    rs2 = rand_reg()
+  
+  return rs1, rs2
+
+def generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta):
+  """
+  Create assembly code for a given STORE test case, returned as a string.
+
+  Generates an `xlen`-bit test case for `instruction` (one of sb, sh, sw, or
+  sd) that loads `value` into `value_register`, then attempts to store that
+  value in memory at address (x6 + `base_delta`). The test case
+  assumes the current base address for the signature is in register x6.
+
+  The form of the STORE instruction is as follows:
+
+  `instruction` `value_register` `offset`(`addr_register`)
+  """
+  global testcase_num
+
+  hex_value = f"{value:0{xlen // 4}x}"
+
+  data = f"""# Testcase {testcase_num}: source: x{value_register} (value 0x{hex_value}), destination: {offset}(x{addr_register}) ({base_delta} bytes into signature)
+    addi x{addr_register}, x6, {base_delta}
+    li x{value_register}, MASK_XLEN({-offset})
+    add x{addr_register}, x{addr_register}, x{value_register}
+    li x{value_register}, 0x{hex_value}
+    {instruction} x{value_register}, {offset}(x{addr_register})
+    """
+
+  update_signature(store_to_size[instruction], value, base_delta)
+
+  testcase_num += 1
+  return data
+
+def validate_memory(scratch_register, value_register, value, base_delta, length):
+  """
+  Create assembly code to verify that `length` bytes at mem[x6 + `base_delta`]
+  store `value`.
+
+  Assumes x6 stores the current base address for the signature.
+  """
+  truncated_value = value & (2**(length * 8) - 1)
+  hex_value = f"{truncated_value:0{length * 2}x}"
+
+  load = size_to_load[length]
+  data = f"""addi x{scratch_register}, x6, {base_delta}
+    {load} x{value_register}, 0(x{scratch_register})
+    RVTEST_IO_ASSERT_GPR_EQ(x{scratch_register}, x{value_register}, 0x{hex_value})
+
+    """
+  return data
+
+def update_signature(length, value, base_delta):
+  """
+  Write the lower `length` bytes of `value` to the little-endian signature
+  array, starting at byte `base_delta`.
+  """
+  truncated_value = value & (2**(length * 8) - 1)
+  value_bytes = truncated_value.to_bytes(length, 'little')
+  #print("n: {}, value: {:x}, trunc: {:x}, length: {}, bd: {:x}".format(testcase_num, value, truncated_value, length, base_delta))
+  for i in range(length):
+    signature[base_delta + i] = value_bytes[i]
+
+def write_signature(outfile):
+  """
+  Writes successive 32-bit words from the signature array into a given file.
+  """
+  for i in range(0, signature_len, 4):
+    word = list(reversed(signature[i:i+4]))
+    hexword = bytearray(word).hex()
+    outfile.write(f"{hexword}\n")
+
+def write_header(outfile):
+  """
+  Write the name of the test file, authors, and creation date.
+  """
+  outfile.write(dedent(f"""\
+    ///////////////////////////////////////////
+    //
+    // WALLY-STORE
+    //
+    // Author: {author}
+    //
+    // Created {str(datetime.now())}
+    """))
+  outfile.write(open("testgen_header.S", "r").read())
+
+def write_footer(outfile):
+  """
+  Write necessary closing code, including a data section for the signature.
+  """
+  outfile.write(open("testgen_footer.S", 'r').read())
+  data_section = dedent(f"""\
+    \t.fill {signature_len}, 1, -1
+    RV_COMPLIANCE_DATA_END
+    """)
+  outfile.write(data_section)
+
+##################################
+# test cases
+##################################
+
+def write_basic_tests(outfile, xlen, instr_len, num, base_delta):
+  """
+  Test basic functionality of STORE, using random registers, offsets, and
+  values.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory at consecutive locations, starting `base_delta` bytes from
+  the start of the signature.
+
+  Returns the number of bytes from the start of the signature where testing
+  ended.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    value_register, addr_register = rand_regs()
+    offset = randint(-2**(12 - 1), 2**(12 - 1) - 1)
+    value = randint(0, 2**(instr_len * 8) - 1)
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+    outfile.write(test)
+    outfile.write(validate)
+    base_delta += instr_len
+  return base_delta
+
+def write_random_store_tests(outfile, xlen, instr_len, num, min_base_delta):
+  """
+  Test random access of STORE, using random registers, offsets, values, and
+  memory locations.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory at random locations between `min_base_delta` bytes past
+  the start of the signature to the end of the signature.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    base_delta = randint(min_base_delta, signature_len - 1)
+    base_delta -= (base_delta % instr_len)
+    value_register, addr_register = rand_regs()
+    offset = randint(-2**(12 - 1), 2**(12 - 1) - 1)
+    value = randint(0, 2**(instr_len * 8) - 1)
+
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+    outfile.write(test)
+    outfile.write(validate)
+
+def write_repeated_store_tests(outfile, xlen, instr_len, num, base_delta):
+  """
+  Test repeated access of STORE, using random registers, offsets, values, and a
+  single memory location.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory `base_delta` bytes past the start of the signature.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    value_register, addr_register = rand_regs()
+    offset = 0
+    value = (1 << ((2 * i) % xlen))
+
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+
+    outfile.write(test)
+    outfile.write(validate)
+
+def write_corner_case_tests(outfile, xlen, instr_len, base_delta):
+  instruction = size_to_store[instr_len]
+
+  corner_cases_32 = [0x0, 0x10000001, 0x01111111]
+  corner_cases_64 = [0x1000000000000001, 0x0111111111111111]
+  corner_cases = corner_cases_32
+  if xlen == 64:
+    corner_cases += corner_cases_64
+
+  for offset in corner_cases:
+    for value in corner_cases:
+      value_register, addr_register = rand_regs()
+      test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+      validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+
+      outfile.write(test)
+      outfile.write(validate)
+
+      base_delta += instr_len
+  
+  return base_delta
+
+##################################
+# main body
+##################################
+
+instructions = ["sd", "sw", "sh", "sb"]
+author = "Jessica Torrey <jtorrey@hmc.edu> & Thomas Fleming <tfleming@hmc.edu>"
+xlens = [32, 64]
+numrand = 100
+
+# setup
+seed(0) # make tests reproducible
+
+for xlen in xlens:
+  if (xlen == 32):
+    wordsize = 4
+  else:
+    wordsize = 8
+
+  fname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/src/WALLY-STORE.S"
+  refname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/references/WALLY-STORE.reference_output"
+  f = open(fname, "w")
+  r = open(refname, "w")
+
+  write_header(f)
+
+  base_delta = 0
+
+  for instruction in instructions:
+    if xlen == 32 and instruction == 'sd':
+      continue
+    instr_len = store_to_size[instruction]
+    base_delta = write_basic_tests(f, xlen, instr_len, 5, base_delta)
+    write_repeated_store_tests(f, xlen, instr_len, 32, base_delta)
+    write_random_store_tests(f, xlen, instr_len, 5, base_delta + wordsize)
+
+  write_footer(f)
+
+  write_signature(r)
+  f.close()
+  r.close()
+
+  # Reset testcase_num and signature
+  testcase_num = 0
+  signature = [0xff for _ in range(signature_len)]
diff --git a/tests/testgen/imperas/testgen-VIRTUALMEMORY.py b/tests/testgen/imperas/testgen-VIRTUALMEMORY.py
new file mode 100644
index 000000000..07bb6e374
--- /dev/null
+++ b/tests/testgen/imperas/testgen-VIRTUALMEMORY.py
@@ -0,0 +1,285 @@
+#!/usr/bin/python3
+##################################
+# testgen-VIRTUALMEMORY.py
+#
+# Jessica Torrey <jtorrey@hmc.edu>  01 March 2021
+# Thomas Fleming <tfleming@hmc.edu> 01 March 2021
+#
+# Generate an ad-hoc test program for RISC-V Design Validation. Tests the
+# functionality of the memory management unit (MMU).
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint, seed, getrandbits
+from textwrap import dedent
+from virtual_memory_util import *
+
+##################################
+# global structures
+##################################
+
+testcase_num = 0
+signature_len = 2000
+signature = [0xff for _ in range(signature_len)]
+
+##################################
+# functions
+##################################
+
+def rand_reg():
+  """
+  Produce a random register from 1 to 31 (skipping 6, since r6 is used for
+  other things).
+  """
+  r = randint(1,30)
+  if r >= 6:
+    r += 1
+  return r
+
+def rand_regs():
+  """
+  Generate two random, unequal register numbers (skipping x6).
+  """
+  rs1 = rand_reg()
+  rs2 = rand_reg()
+  while rs1 == rs2:
+    rs2 = rand_reg()
+  
+  return rs1, rs2
+
+def initialize_page_directory()
+
+def generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta):
+  """
+  Create assembly code for a given STORE test case, returned as a string.
+
+  Generates an `xlen`-bit test case for `instruction` (one of sb, sh, sw, or
+  sd) that loads `value` into `value_register`, then attempts to store that
+  value in memory at address (x6 + `base_delta`). The test case
+  assumes the current base address for the signature is in register x6.
+
+  The form of the STORE instruction is as follows:
+
+  `instruction` `value_register` `offset`(`addr_register`)
+  """
+  global testcase_num
+
+  hex_value = f"{value:0{xlen // 4}x}"
+
+  data = f"""# Testcase {testcase_num}: source: x{value_register} (value 0x{hex_value}), destination: {offset}(x{addr_register}) ({base_delta} bytes into signature)
+    addi x{addr_register}, x6, {base_delta}
+    li x{value_register}, MASK_XLEN({-offset})
+    add x{addr_register}, x{addr_register}, x{value_register}
+    li x{value_register}, 0x{hex_value}
+    {instruction} x{value_register}, {offset}(x{addr_register})
+    """
+
+  #update_signature(store_to_size[instruction], value, base_delta)
+
+  testcase_num += 1
+  return data
+
+def validate_memory(scratch_register, value_register, value, base_delta, length):
+  """
+  Create assembly code to verify that `length` bytes at mem[x6 + `base_delta`]
+  store `value`.
+
+  Assumes x6 stores the current base address for the signature.
+  """
+  truncated_value = value & (2**(length * 8) - 1)
+  hex_value = f"{truncated_value:0{length * 2}x}"
+
+  load = size_to_load[length]
+  data = f"""addi x{scratch_register}, x6, {base_delta}
+    {load} x{value_register}, 0(x{scratch_register})
+    RVTEST_IO_ASSERT_GPR_EQ(x{scratch_register}, x{value_register}, 0x{hex_value})
+
+    """
+  return data
+
+def update_signature(length, value, base_delta):
+  """
+  Write the lower `length` bytes of `value` to the little-endian signature
+  array, starting at byte `base_delta`.
+  """
+  truncated_value = value & (2**(length * 8) - 1)
+  value_bytes = truncated_value.to_bytes(length, 'little')
+  #print("n: {}, value: {:x}, trunc: {:x}, length: {}, bd: {:x}".format(testcase_num, value, truncated_value, length, base_delta))
+  for i in range(length):
+    signature[base_delta + i] = value_bytes[i]
+
+def write_signature(outfile):
+  """
+  Writes successive 32-bit words from the signature array into a given file.
+  """
+  for i in range(0, signature_len, 4):
+    word = list(reversed(signature[i:i+4]))
+    hexword = bytearray(word).hex()
+    outfile.write(f"{hexword}\n")
+
+def write_header(outfile):
+  """
+  Write the name of the test file, authors, and creation date.
+  """
+  outfile.write(dedent(f"""\
+    ///////////////////////////////////////////
+    //
+    // WALLY-STORE
+    //
+    // Author: {author}
+    //
+    // Created {str(datetime.now())}
+    """))
+  outfile.write(open("testgen_header.S", "r").read())
+
+def write_footer(outfile):
+  """
+  Write necessary closing code, including a data section for the signature.
+  """
+  outfile.write(open("testgen_footer.S", 'r').read())
+  data_section = dedent(f"""\
+    \t.fill {signature_len}, 1, -1
+    RV_COMPLIANCE_DATA_END
+    """)
+  outfile.write(data_section)
+
+##################################
+# test cases
+##################################
+
+def write_basic_tests(outfile, xlen, instr_len, num, base_delta):
+  """
+  Test basic functionality of STORE, using random registers, offsets, and
+  values.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory at consecutive locations, starting `base_delta` bytes from
+  the start of the signature.
+
+  Returns the number of bytes from the start of the signature where testing
+  ended.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    value_register, addr_register = rand_regs()
+    offset = randint(-2**(12 - 1), 2**(12 - 1) - 1)
+    value = randint(0, 2**(instr_len * 8) - 1)
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+    outfile.write(test)
+    outfile.write(validate)
+    base_delta += instr_len
+  return base_delta
+
+def write_random_store_tests(outfile, xlen, instr_len, num, min_base_delta):
+  """
+  Test random access of STORE, using random registers, offsets, values, and
+  memory locations.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory at random locations between `min_base_delta` bytes past
+  the start of the signature to the end of the signature.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    base_delta = randint(min_base_delta, signature_len - 1)
+    base_delta -= (base_delta % instr_len)
+    value_register, addr_register = rand_regs()
+    offset = randint(-2**(12 - 1), 2**(12 - 1) - 1)
+    value = randint(0, 2**(instr_len * 8) - 1)
+
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+    outfile.write(test)
+    outfile.write(validate)
+
+def write_repeated_store_tests(outfile, xlen, instr_len, num, base_delta):
+  """
+  Test repeated access of STORE, using random registers, offsets, values, and a
+  single memory location.
+
+  Creates `num` tests for a single store instruction of length `instr_len`,
+  writing to memory `base_delta` bytes past the start of the signature.
+  """
+  instruction = size_to_store[instr_len]
+  for i in range(num):
+    value_register, addr_register = rand_regs()
+    offset = 0
+    value = (1 << ((2 * i) % xlen))
+
+    test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+    validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+
+    outfile.write(test)
+    outfile.write(validate)
+
+def write_corner_case_tests(outfile, xlen, instr_len, base_delta):
+  instruction = size_to_store[instr_len]
+
+  corner_cases_32 = [0x0, 0x10000001, 0x01111111]
+  corner_cases_64 = [0x1000000000000001, 0x0111111111111111]
+  corner_cases = corner_cases_32
+  if xlen == 64:
+    corner_cases += corner_cases_64
+
+  for offset in corner_cases:
+    for value in corner_cases:
+      value_register, addr_register = rand_regs()
+      test = generate_case(xlen, instruction, value_register, value, addr_register, offset, base_delta)
+      validate = validate_memory(addr_register, value_register, value, base_delta, instr_len)
+
+      outfile.write(test)
+      outfile.write(validate)
+
+      base_delta += instr_len
+  
+  return base_delta
+
+##################################
+# main body
+##################################
+
+if __name__ == "__main__":
+  instructions = ["sd", "sw", "sh", "sb"]
+  author = "Jessica Torrey <jtorrey@hmc.edu> & Thomas Fleming <tfleming@hmc.edu>"
+  xlens = [32, 64]
+  numrand = 100
+
+  # setup
+  seed(0) # make tests reproducible
+
+  for xlen in xlens:
+    if (xlen == 32):
+      wordsize = 4
+    else:
+      wordsize = 8
+
+    fname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/src/WALLY-VIRTUALMEMORY.S"
+    refname = f"../../imperas-riscv-tests/riscv-test-suite/rv{xlen}i/references/WALLY-VIRTUALMEMORY.reference_output"
+    f = open(fname, "w")
+    r = open(refname, "w")
+
+    write_header(f)
+
+    base_delta = 0
+
+    for instruction in instructions:
+      if xlen == 32 and instruction == 'sd':
+        continue
+      instr_len = store_to_size[instruction]
+      base_delta = write_basic_tests(f, xlen, instr_len, 5, base_delta)
+      write_repeated_store_tests(f, xlen, instr_len, 32, base_delta)
+      write_random_store_tests(f, xlen, instr_len, 5, base_delta + wordsize)
+
+    write_footer(f)
+
+    write_signature(r)
+    f.close()
+    r.close()
+
+    # Reset testcase_num and signature
+    testcase_num = 0
+    signature = [0xff for _ in range(signature_len)]
\ No newline at end of file
diff --git a/tests/testgen/imperas/testgen_footer.S b/tests/testgen/imperas/testgen_footer.S
new file mode 100644
index 000000000..f7cc0b18b
--- /dev/null
+++ b/tests/testgen/imperas/testgen_footer.S
@@ -0,0 +1,18 @@
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
diff --git a/tests/testgen/imperas/testgen_header.S b/tests/testgen/imperas/testgen_header.S
new file mode 100644
index 000000000..118042a5c
--- /dev/null
+++ b/tests/testgen/imperas/testgen_header.S
@@ -0,0 +1,38 @@
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Adapted from Imperas RISCV-TEST_SUITE
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV64M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	#RVTEST_IO_WRITE_STR(x31, "# Test group 1\n")
+
+
+    # address for test results
+    la x6, test_1_res
+		
\ No newline at end of file
diff --git a/tests/testgen/privileged/README.md b/tests/testgen/privileged/README.md
new file mode 100644
index 000000000..9b3faff6f
--- /dev/null
+++ b/tests/testgen/privileged/README.md
@@ -0,0 +1,36 @@
+# Privileged Test Generators
+
+Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use:
+
+```bash
+sh run.sh NAME
+```
+
+For example, for `testgen-CAUSE.py`, we would run `sh run.sh CAUSE`.
+
+This bash file is super basic, so only allows for a single argument after the name.
+Provide -sim as the second argument to simulate the compiled tests using wally.
+
+```bash
+sh run.sh NAME -sim
+```
+
+To compile tests without running them in OVPsim, provide -c as the second argument
+
+```bash
+sh run.sh NAME -c
+```
+
+The test generator also has a really nice feature that grabs the location of begin_signature after compiling the tests. For example, running `sh run.sh EPC` will output something like this at the end:
+
+```verilog
+rv64p = '{
+    'rv64p/WALLY-MEPC', '5000',
+    'rv64p/WALLY-SEPC', '4000'
+};
+
+rv32p = '{
+    'rv32p/WALLY-MEPC', '5000',
+    'rv32p/WALLY-SEPC', '4000'
+};
+```
\ No newline at end of file
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
new file mode 100755
index 000000000..1fa3a9d01
--- /dev/null
+++ b/tests/testgen/privileged/run.sh
@@ -0,0 +1,74 @@
+#!/bin/bash
+
+#
+# Written 1 Mar 2021 by Domenico Ottolia (dottolia@hmc.edu)
+#
+# See README.md in this directory for more info
+#
+
+clear
+printf "\n\n#####\nStarting tests for $1\n#####\n\n"
+
+if [[ "$2" != "-simonly" ]]
+then
+	cd $WALLY/pipelined/testgen/privileged
+	python3 "testgen-$1.py"
+	printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
+
+	if [[ "$2" == "-c" ]]
+	then
+		printf "\n\n###\nWARNING\nThis seems to not be outputting begin_signature at the moment... Probably won't work in modelsim...\n###\n\n\n"
+		cd $WALLY/imperas-riscv-tests/riscv-test-suite/rv64p/src
+		riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf"
+		cd $WALLY/imperas-riscv-tests/work/rv64p
+		riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump
+ 
+	elif [[ "$2" != "-nosim" ]]
+	then
+		cd $WALLY/imperas-riscv-tests
+		make privileged
+
+		exe2memfile.pl work/*/*.elf
+		extractFunctionRadix.sh work/rv64p/*.elf.objdump
+	fi
+fi
+
+if [[ "$2" == "-simonly" ]]
+then
+	printf "\n\n###\nWARNING\nThis seems to not be outputting begin_signature at the moment... Probably won't work in modelsim...\n###\n\n\n"
+	cd $WALLY/imperas-riscv-tests/riscv-test-suite/rv64p/src
+	riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf"
+	cd $WALLY/imperas-riscv-tests/work/rv64p
+	riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump
+
+	# 	riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-CAUSE".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-CAUSE.elf"
+	# riscv64-unknown-elf-objdump -d "WALLY-CAUSE.elf" > "WALLY-CAUSE.elf.objdump"
+fi
+
+if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
+then
+	printf "\n\n\n#####\nSimulating!\n#####\n\n"
+	cd $WALLY/pipelined/regression
+	vsim -do wally-privileged.do -c
+fi
+
+cd $WALLY/pipelined
+printf "\n\n\n#####\nDone!\n#####\n\n"
+
+cd $WALLY/imperas-riscv-tests/work
+for isa in "rv64p" "rv32p"; do
+	printf "$isa = '{"
+	COMMA=""
+	for file in "$isa"/*.elf.objdump; do
+		if [[ "$file" == *"$1"* ]]; then
+		    RES=$(grep "^\s*0*8000.000 <begin_signature>" $file)
+		    RES=$(echo "$RES" | sed -r 's/^0*80+([0-9]+).+?$/\1/g')
+		    file=$(echo "$file" | sed -r 's/^(.+?)\.elf\.objdump/\1/g')
+		    printf "$COMMA\n    '$file', '${RES}'"
+		    COMMA=","
+		fi
+	done
+	printf "\n};\n\n"
+done
+
+cd $WALLY/pipelined
\ No newline at end of file
diff --git a/tests/testgen/privileged/testgen-CAUSE.py b/tests/testgen/privileged/testgen-CAUSE.py
new file mode 100755
index 000000000..0ab0128b4
--- /dev/null
+++ b/tests/testgen/privileged/testgen-CAUSE.py
@@ -0,0 +1,573 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py (new)
+#
+# dottolia@hmc.edu 1 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+#
+#
+##################################
+# DOCUMENTATION:
+#
+# The most up-to-date comments explaining what everything
+# does and the layout of the privileged tests
+# can be found in testgen-TVAL.py. This and
+# other files do not have as many comments
+#
+###################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
+
+def randRegs():
+  reg1 = randint(1,20)
+  reg2 = randint(1,20)
+  reg3 = randint(1,20)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return str(reg1), str(reg2), str(reg3)
+
+def writeVectors(storecmd, returningInstruction):
+  global testnum
+
+  if testMode == "m":
+    if fromMode == "m":
+      expectedCode = 7 if fromMode == "m" else 5
+      clintAddr = "0x2004000"
+
+      writeTest(storecmd, f, r, f"""
+        li x1, 0x8
+        csrrs x0, {fromMode}status, x1
+
+        la x18, {clintAddr}
+        {loadcmd} x11, 0(x18)
+        li x1, 0x3fffffffffffffff
+        {storecmd} x1, 0(x18)
+
+        li x1, 0x80
+        csrrs x0, {fromMode}ie, x1
+
+        {storecmd} x0, 0(x18)
+      """, True, expectedCode, f"""
+        li x1, 0x80
+        csrrc x0, {fromMode}ie, x1
+
+        li x1, 0x8
+        csrrc x0, {fromMode}status, x1
+
+        la x18, {clintAddr}
+        li x1, -1
+        {storecmd} x1, 0(x18)
+      """)
+
+    # Page 6 of unpriviledged spec
+  # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
+
+  # User Software Interrupt: True, 0
+  # Supervisor Software Interrupt: True, 1
+  # Machine Software Interrupt: True, 2
+
+  # When running run.sh CAUSE -c, everything works, but begin_signature doesn't appear
+  # 0x2000000 in wally
+  # writeTest(storecmd, f, r, f"""
+  #   la x10, 0x2000000 #clint
+
+  #   li x1, 42
+  #   sw x1, 0(x10)
+  # """, True, 2, "m", f"""
+  #   lw x0, 0(x10)
+  # """)
+
+  # User Timer Interrupt: True, 4
+  # Supervior timer interrupt: True, 5
+  # Machine timer interrupt: True, 7
+
+  # if fromMode == "m":
+  #   clintAddr = "0x2004000"
+
+  #   writeTest(storecmd, f, r, f"""
+  #     # li x1, 0x8
+  #     # csrrs x0, mstatus, x1
+
+  #     # li x1, 0x80
+  #     # csrrs x0, mie, x1
+
+  #     # la x18, {clintAddr}
+  #     # lw x11, 0(x18)
+  #     # lw x12, 4(x18)
+  #     # li x1, 1
+  #     # {storecmd} x1, 0(x18)
+  #     nop
+  #     sub x1, x2, x3
+  #     sub x2, x3, x4
+  #     sub x3, x4, x5
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #     nop
+  #   """, True, 7, f"""
+  #     # la x18, {clintAddr}
+  #     # {storecmd} x11, 0(x18)
+  #   """)
+
+  #writeTest(storecmd, f, r, f"""
+  #  li x2, 0x0
+#
+  #   li x4, 0x80
+  #   csrrs x0, mie, x4
+
+  #   la x2, 0x2004000
+    
+  #   li x3, 0x0
+  #   lw x5, 0(x2)
+  #   sd x3, 0(x2)
+  #   wfi
+  # """, True, 7, "m", f"""
+  #   t
+  # """)
+
+  # writeTest(storecmd, f, r, f"""
+  #   csrr x18, mstatus
+  #   # csrsi mstatus, 0b11111
+  #   csrr x19, mie
+  #   li x17, 0b1111111111111
+  #   # csrs mie, x17
+
+  #   la x10, 0x2004000 #clint timer
+  #   li x1, 0
+
+  #   lw x11, 0(x10)
+  #   lw x12, 4(x10)
+
+  #   {storecmd} x0, 0(x10)
+  #   {storecmd} x0, 4(x10)
+  # """, True, 7, "m", f"""
+  #   {storecmd} x11, 0(x10)
+  #   {storecmd} x12, 4(x10)
+
+  #   csrw mstatus, x18
+  #   csrw mie, x19
+  # """)
+
+  # User external input: True, 8
+  # Supervisor external input: True, 9
+  # Machine externa input: True, 11
+
+  # Instruction address misaligned: False, 0
+  # looks like this is giving us an infinite loop for wally
+  # BUG: jumping to a misaligned instruction address doesn't cause an exception: we actually jump...
+  # Either that, or somehow at the end we always end up at 0x80004002
+  # This is fine in OVPsim
+  # writeTest(storecmd, f, r, f"""
+  #   li x1, 11
+  #   jr x1 # Something about this instruction is funky on wally, but fine with ovpsim
+  # """, False, 0)
+
+  # Instruction access fault: False, 1
+
+  # Illegal Instruction 
+  writeTest(storecmd, f, r, f"""
+    .fill 1, 4, 0
+  """, False, 2)
+
+  # Breakpoint
+  if returningInstruction != "ebreak":
+    writeTest(storecmd, f, r, f"""
+      ebreak
+    """, False, 3)
+
+  # Load Address Misaligned 
+  writeTest(storecmd, f, r, f"""
+    lw x0, 11(x0)
+  """, False, 4)
+
+  # Load Access fault: False, 5
+
+  # Store/AMO address misaligned
+  writeTest(storecmd, f, r, f"""
+    sw x0, 11(x0)
+  """, False, 6)
+
+  # Environment call from u-mode: only for when only M and U mode enabled?
+  # writeTest(storecmd, f, r, f"""
+  #   ecall
+  # """, False, 8, "u")
+  if returningInstruction != "ecall":
+    if fromMode == "u":
+      writeTest(storecmd, f, r, f"""
+        ecall
+      """, False, 8)
+
+    # Environment call from s-mode
+    if fromMode == "s":
+      writeTest(storecmd, f, r, f"""
+        ecall
+      """, False, 9)
+
+    # Environment call from m-mode
+    if fromMode == "m":
+      writeTest(storecmd, f, r, f"""
+        ecall
+      """, False, 11)  
+
+  # Instruction page fault: 12
+  # Load page fault: 13
+  # Store/AMO page fault: 15
+  
+
+  
+
+def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
+  global testnum, storeAddressOffset
+
+  expected = code
+  if(interrupt):
+    expected+=(1 << (xlen - 1))
+
+  # The code we actually change for our test
+  lines = f"""
+    csrr x25, {testMode}cause
+  """
+
+  # Boilerplate
+  #
+  # x28 is the address that our trap handler will jump to before returning.
+  # This is where we can do our actual tests. After we're done computing and storing
+  # what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
+  # 
+  lines = f"""
+    la x28, _jtest{testnum}
+    j _jdo{testnum}
+
+    _jtest{testnum}:
+    {lines}
+    {resetHander}
+    jr x27
+
+    _jdo{testnum}:
+    li x25, 0xDEADBEA7
+    li gp, 0
+    {test}
+  """
+
+  # We expect x25 to be 0 always. This is because of the code we wrote at the begining
+  # of this function
+  
+  # Store the expected value of x25 to memory and in the .reference_output file
+  lines += f"""
+    {storecmd} x25, {testnum * wordsize}(x6)
+  """
+
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+testCount = 8;
+
+# setup
+# Change this seed to a different constant value for every test
+seed(0xC363DAEB9193AB45) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    loadcmd = "lw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    loadcmd = "ld"
+    wordsize = 8
+
+  # testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
+  for testMode in ["m", "s"]:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + testMode.upper() + "CAUSE"
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+    storeAddressOffset = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+     f.write(line.replace("RV_COMPLIANCE_RV64M", "RV_COMPLIANCE_RV" + str(xlen) + "M"))
+    # f.write(f"""
+    #   #include "riscv_test_macros.h"
+    #   #include "compliance_test.h"
+    #   #include "compliance_io.h"
+
+    #   0000000080000000 <_start>:
+    #   80000000: 0480006f            j 80000048 <reset_vector>
+    # """)
+
+    # We need to leave at least one bit in medeleg unset so that we have a way to get
+    # back to machine mode when the tests are complete (otherwise we'll only ever be able
+    # to get up to supervisor mode). 
+    #
+    # So, we define a returning instruction which will be used to cause the exception that
+    # brings us into machine mode. The bit for this returning instruction is NOT set in
+    # medeleg. However, this also means that we can't test that instruction. So, we have
+    # two different returning instructions.
+    #
+    # Current code is written to only support ebreak and ecall.
+    #
+    # For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
+    # returning instruction. For others, like testgen-CAUSE, we'll need to put
+    # both ebreak and ecall here.
+    for returningInstruction in ["ebreak"]:
+
+      # All registers used:
+      # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
+      # ...
+      # x28: address trap handler should jump to for the test
+      # x27: address the test should return to after the test
+      # ...
+      # x25: value to write to memory
+      # ...
+      # x20: intermediate value in trap handler. Don't overwrite this!
+      # x19: mtvec old value
+      # x18: medeleg old value
+      # x17: sedeleg old value (currently unused — user mode traps deprecated)
+      # x16: mideleg old value
+      # ...
+      # x10 - x14 can be freely written
+      # ...
+      # x7: copy of x6. Increment this instead of using an offset on x6.
+      #     this allows us to create more than 2048/wordlen tests.
+      #     This is the address we write results to
+      # x6: Starting address we should write expected results to
+      # ...
+      # x1 - x5 can be freely written  
+
+
+
+      # Set up x7 and store old value of mtvec
+      lines = f"""
+        add x7, x6, x0
+        csrr x19, mtvec
+
+        slli  a0,a0,0x1f
+        slli  a0,a0,0x1e
+        slli  a0,a0,0x1d
+        slli  a0,a0,0x1c
+        slli  a0,a0,0x1b
+        slli  a0,a0,0x1a
+        slli  a0,a0,0x19
+      """
+
+      # Not used — user mode traps are deprecated
+      if testMode == "u":
+        lines += f"""
+          csrr x17, sedeleg
+          li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
+          csrs sedeleg, x9
+          """
+
+      # Code that will jump to the test (x28 is set in writeTest above)
+      testJumpCode = f"""
+        auipc x27, 0
+        addi x27, x27, 12
+        jr x28
+      """
+
+      # Code for handling traps in different modes
+      # Some comments are inside of the below strings (prefixed with a #, as you might expected)
+      lines += f"""
+        # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
+        li x30, 0
+
+        # Set up 
+        la x1, _j_m_trap_{returningInstruction}
+        csrw mtvec, x1
+        la x1, _j_s_trap_{returningInstruction}
+        csrw stvec, x1
+        la x1, _j_u_trap_{returningInstruction}
+        # csrw utvec, x1 # user mode traps are not supported
+
+        # Start the tests!
+        j _j_t_begin_{returningInstruction}
+
+        # Machine mode traps
+        _j_m_trap_{returningInstruction}:
+        {testJumpCode if testMode == "m" else "li x25, 0xBAD00003"}
+
+        csrrs x20, mepc, x0
+        addi x20, x20, 4
+        csrrw x0, mepc, x20
+        bnez x30, _j_all_end_{returningInstruction}
+        mret
+
+        # Supervisor mode traps
+        _j_s_trap_{returningInstruction}:
+        {testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
+
+        csrrs x20, sepc, x0
+        addi x20, x20, 4
+        csrrw x0, sepc, x20
+        bnez x30, _j_goto_machine_mode_{returningInstruction}
+        sret
+
+        # Unused: user mode traps are no longer supported
+        _j_u_trap_{returningInstruction}:
+        {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
+
+        csrrs x20, uepc, x0
+        addi x20, x20, 4
+        csrrw x0, uepc, x20
+        bnez x30, _j_goto_supervisor_mode_{returningInstruction}
+        uret
+
+        # Currently unused. Just jumps to _j_goto_machine_mode. If you actually
+        # want to implement this, you'll likely need to reset sedeleg here
+        # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
+        _j_goto_supervisor_mode_{returningInstruction}:
+        j _j_goto_machine_mode_{returningInstruction}
+
+        _j_goto_machine_mode_{returningInstruction}:
+        li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
+        {returningInstruction} # ... this instruction!
+
+        # Run the actual tests!
+        _j_t_begin_{returningInstruction}:
+      """
+
+      fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
+
+      # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
+      # back to machine mode at the end! (and we need to be in machine mode to complete the tests)
+      medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
+
+      # Set medeleg and mideleg
+      lines += f"""
+        csrr x18, medeleg
+        li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
+        csrw medeleg, x9
+
+        csrr x16, mideleg
+        li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
+        csrw mideleg, x9
+      """
+
+      f.write(lines)
+
+      for fromMode in fromModeOptions:
+        lines = ""
+        
+        # Code to bring us down to supervisor mode
+        if fromMode == "s" or fromMode == "u":
+          lines += f"""
+            li x1, 0b110000000000
+            csrrc x31, mstatus, x1
+            li x1, 0b0100000000000
+            csrrs x31, mstatus, x1
+
+            auipc x1, 0
+            addi x1, x1, 16 # x1 is now right after the mret instruction
+            csrw mepc, x1
+            mret
+
+            # We're now in supervisor mode...
+          """
+
+        # Code to bring us down to user mode
+        if fromMode == "u":
+          lines += f"""
+
+          li x1, 0b110000000000
+          csrrc x31, sstatus, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the sret instruction
+          csrw sepc, x1
+          sret
+
+          # We're now in user mode...
+          """
+
+        f.write(lines)
+        for i in range(0,testCount):
+          writeVectors(storecmd, returningInstruction)
+
+
+      # Very end of test. Bring us back up to machine mode
+      # We set x30 to 1, which will cause us to branch to _j_all_end in the
+      # machine mode trap handler, before executing the mret instruction. This will
+      # make us stay in machine mode.
+      #
+      # If we're currently in user mode, this will first bump us up to the supervisor mode
+      # trap handler, which will call returningInstruction again before it's sret instruction,
+      # bumping us up to machine mode
+      #
+      # Get into the trap handler by running returningInstruction (either an ecall or ebreak) 
+      f.write(f"""
+        li x30, 1
+        li gp, 0
+        {returningInstruction}
+        _j_all_end_{returningInstruction}:
+
+        # Reset trap handling csrs to old values
+        csrw mtvec, x19
+        csrw medeleg, x18
+        csrw mideleg, x16
+      """)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
diff --git a/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py b/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py
new file mode 100755
index 000000000..1cd262458
--- /dev/null
+++ b/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py
@@ -0,0 +1,248 @@
+#!/usr/bin/python3
+##################################
+# testgen-CSR-PERMISSIONS.py
+#
+# dottolia@hmc.edu 1 May 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+# Verify that an illegal instruction is raised when trying to write to csrs of a higher privilege
+#
+##################################
+# DOCUMENTATION:
+#
+# Most of the comments explaining what everything
+# does and the layout of the privileged tests
+# can be found in this file
+#
+###################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+testCount = 2
+
+def writeVectors(storecmd, testMode):
+  global testnum
+
+  csrs = ["status", "edeleg", "ideleg", "ie", "tvec", "counteren", "scratch", "epc", "cause", "tval", "ip"]
+  if testMode == "s":
+    csrs.append("atp")
+  #csrs = ["status"]
+  for csrStart in csrs:
+    for i in range(0, testCount):
+      a = 1
+
+      csr = testMode + csrStart
+
+      # only check for CSR changes if testing machine-mode registers
+      csrWillChange = testMode == "s" or csrStart == "status" or csrStart == "epc" or csrStart == "cause" or csrStart == "tval"
+      newCSRValue = "" if testMode == "s" else "csrr x24, " + csr
+
+      f.write(f"""
+        li x13, 1
+      """)
+
+      fromModeOptions = ["s", "u"] if testMode == "m" else ["u"]
+      for fromMode in fromModeOptions:
+        label = f"""{fromMode}_{csr}_{testnum}"""
+        endlabel = f"""_j_end_{label}"""
+        # This is all from testgen-TVAL.py, within the for loop on returningInstruction
+        #
+        # x25: mepc value
+        # x24: new csr value
+        # x23: original csr value
+        lines = f"""
+          li x30, 0
+          la x1, _m_trap_from_{label}
+          csrw mtvec, x1
+
+          csrr x23, {csr}
+
+          j _j_test_{label}
+
+          _m_trap_from_{label}:
+          bnez x30, {endlabel}
+
+          csrr x25, mcause
+          {newCSRValue}
+
+          csrrs x20, mepc, x0
+          addi x20, x20, 4
+          csrrw x0, mepc, x20
+        
+          mret
+
+          _j_test_{label}:
+        """
+
+        lines += f"""
+          li x1, 0b110000000000
+          csrrc x0, mstatus, x1
+          li x1, 0b0100000000000
+          csrrs x0, mstatus, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the mret instruction
+          csrw mepc, x1
+          mret
+
+          # We're now in supervisor mode...
+        """
+
+        # Code to bring us down to user mode
+        if fromMode == "u":
+          lines += f"""
+
+          li x1, 0b110000000000
+          csrrc x0, sstatus, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the sret instruction
+          csrw sepc, x1
+          sret
+
+          # We're now in user mode...
+          """
+
+        f.write(lines)
+
+
+        writeTest(storecmd, f, r, f"""csrrw x1, {csr}, x0""", csrWillChange)
+        writeTest(storecmd, f, r, f"""csrrw x0, {csr}, x13""", csrWillChange)
+        writeTest(storecmd, f, r, f"""csrrwi x0, {csr}, {a}""", csrWillChange)
+        if a != 0:
+          writeTest(storecmd, f, r, f"""csrrs x0, {csr}, x13""", csrWillChange)
+          writeTest(storecmd, f, r, f"""csrrc x0, {csr}, x13""", csrWillChange)
+          writeTest(storecmd, f, r, f"""csrrsi x0, {csr}, {a}""", csrWillChange)
+          writeTest(storecmd, f, r, f"""csrrci x0, {csr}, {a}""", csrWillChange)
+
+        f.write(f"""
+          li x30, 1
+          ebreak
+          {endlabel}:
+        """)
+
+
+  
+
+def writeTest(storecmd, f, r, test, csrWillChange):
+  global testnum
+
+  test = f"""
+    _jdo{testnum}:
+    li x25, 0xDEADBEA7
+
+    {test}
+
+    {storecmd} x25, 0(x7)
+    addi x7, x7, {wordsize}
+  """
+
+  # We expect x25 to always be an illegal instruction
+  expected = 2
+
+  f.write(test)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+  if not csrWillChange:
+    # We expect x24 should be equal to x23
+    expected = 0
+
+    f.write(f"""
+      sub x25, x24, x23
+      {storecmd} x25, 0(x7)
+      addi x7, x7, {wordsize}
+    """)
+    if (xlen == 32):
+      line = formatrefstr.format(expected)+"\n"
+    else:
+      line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+    r.write(line)
+    testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+
+# setup
+# Change this seed to a different constant value for every test
+seed(0xC363DAEB9193AB45) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for testMode in ["m", "s"]:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-CSR-PERMISSIONS-" + testMode.upper()
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+    storeAddressOffset = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    f.write(f"""
+      add x7, x6, x0
+      csrr x19, mtvec
+    """)
+
+    writeVectors(storecmd, testMode)
+
+    f.write(f"""
+      csrw mtvec, x19
+    """)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/privileged/testgen-DELEG.py b/tests/testgen/privileged/testgen-DELEG.py
new file mode 100755
index 000000000..ab08d09d5
--- /dev/null
+++ b/tests/testgen/privileged/testgen-DELEG.py
@@ -0,0 +1,371 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py
+#
+# dottolia@hmc.edu 27 Apr 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+#
+#
+##################################
+# DOCUMENTATION:
+# Most of the comments explaining what everything
+# does can be found in testgen-TVAL.py
+###################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
+
+def randRegs():
+  reg1 = randint(1,20)
+  reg2 = randint(1,20)
+  reg3 = randint(1,20)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return str(reg1), str(reg2), str(reg3)
+
+def writeVectors(storecmd):
+  global testnum
+
+  # User Software Interrupt: True, 0
+  # Supervisor Software Interrupt: True, 1
+  # Machine Software Interrupt: True, 2
+
+  writeTest(storecmd, f, r, "timer-interrupt", True, -1) # code determined inside of writeTest
+
+  # User external input: True, 8
+  # Supervisor external input: True, 9
+  # Machine externa input: True, 11
+
+  # Instruction address misaligned: False, 0
+
+  # Instruction access fault: False, 1
+
+  # Illegal Instruction 
+  writeTest(storecmd, f, r, f"""
+    .fill 1, 4, 0
+  """, False, 2)
+
+  # Breakpoint
+  writeTest(storecmd, f, r, "ebreak", False, 3)
+
+  # Load Address Misaligned 
+  writeTest(storecmd, f, r, f"""
+    lw x0, 11(x0)
+  """, False, 4)
+
+  # # Load Access fault: False, 5
+  # TODO: THIS NEEDS TO BE IMPLEMENTED
+
+  # # Store/AMO address misaligned
+  writeTest(storecmd, f, r, f"""
+    sw x0, 11(x0)
+  """, False, 6)
+
+  # Breakpoint: codes 8, 9, 11
+  writeTest(storecmd, f, r, "ecall", False, -1) # code determined inside of writeTest
+
+  # Instruction page fault: 12
+  # TODO: THIS NEEDS TO BE IMPLEMENTED
+
+  # Load page fault: 13
+  # TODO: THIS NEEDS TO BE IMPLEMENTED
+
+  # Store/AMO page fault: 15
+  # TODO: THIS NEEDS TO BE IMPLEMENTED
+  
+
+  #writeTest(storecmd, f, r, "ecall", False, 11, "m")
+  
+def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
+  global testnum
+  global testMode
+  global isInterrupts
+
+  beforeTest = ""
+
+  if interrupt != isInterrupts:
+    return
+  
+  isTimerInterruptTest = test == "timer-interrupt"
+  delegateType = "i" if interrupt else "e"
+  for mode in (["m", "s", "u"] if testMode == "m" else ["s", "u"]):
+    if isTimerInterruptTest:
+      clintAddr = "0x2004000"
+
+      if mode == "m":
+        code = 7
+        test = f"""
+          la x18, {clintAddr}
+          {storecmd} x0, 0(x18)
+        """
+
+      elif mode == "s":
+        code = 5
+        test = ""
+      else:
+        code = 4
+        test = ""
+
+      ieMask = 1 << code
+      statusMask = 0b1010
+
+      beforeTest = f"""
+        li x1, {statusMask}
+        csrrs x0, mstatus, x1
+
+        li x1, 0b0010
+        csrrs x0, sstatus, x1
+
+        la x18, {clintAddr}
+        lw x11, 0(x18)
+        li x1, 0x7fffffffffffffff
+        {storecmd} x1, 0(x18)
+
+        li x1, {ieMask}
+        csrrs x0, mie, x1
+
+        li x1, {ieMask}
+        csrrs x0, sie, x1
+      """
+
+      resetHander = f"""
+        #li x1, 0x80
+        #csrrc x0, sie, x1
+
+        li x1, {ieMask}
+        csrrc x0, mie, x1
+
+        li x1, {ieMask}
+        csrrc x0, sie, x1
+
+        li x1, {statusMask}
+        csrrc x0, mstatus, x1
+
+        li x1, 0b0010
+        csrrc x0, sstatus, x1
+
+        la x18, {clintAddr}
+        {storecmd} x11, 0(x18)
+      """
+
+      if mode == "s":
+        beforeTest += f"""
+          li x1, {ieMask}
+          csrrs x0, sip, x1
+        """
+
+        resetHander += f"""
+          li x1, {ieMask}
+          csrrc x0, sip, x1
+        """
+
+    elif test == "ecall":
+      if mode == "m":
+        code = 11
+      elif mode == "s":
+        code = 9
+      else:
+        code = 8
+
+    mask = 1 << code
+    for delegated in [True, False]:
+      labelSuffix = testnum
+
+      f.write(f"""
+        _start_{labelSuffix}:
+
+        la x1, _j_m_trap_{labelSuffix}
+        csrw mtvec, x1
+        la x1, _j_s_trap_{labelSuffix}
+        csrw stvec, x1
+
+        j _j_test_{labelSuffix}
+
+        _j_m_trap_{labelSuffix}:
+        {resetHander}
+        li x25, 3
+
+        csrr x1, mepc
+        addi x1, x1, 4
+        csrrw x0, mepc, x1
+        bnez x30, _j_finished_{labelSuffix}
+        mret
+
+        _j_s_trap_{labelSuffix}:
+        {resetHander}
+        li x25, 1
+
+        csrr x1, sepc
+        addi x1, x1, 4
+        csrrw x0, sepc, x1
+        bnez x30, _j_goto_machine_mode_{labelSuffix}
+        sret
+
+        _j_goto_machine_mode_{labelSuffix}:
+        li x30, 1
+        {"ebreak" if test is not "ebreak" else "ecall"}
+
+        _j_test_{labelSuffix}:
+      """)
+
+      original = f"""
+        li x1, {mask if delegated else 0}
+        csrw m{delegateType}deleg, x1
+      """
+
+      if mode != "m":
+        lines = f"""
+          {original}
+
+          {beforeTest}
+
+          li x1, 0b110000000000
+          csrrc x31, {testMode}status, x1
+          li x1, 0b{"01" if mode == "s" else "00"}00000000000
+          csrrs x31, {testMode}status, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the ret instruction
+          csrrw x27, {testMode}epc, x1
+          {testMode}ret
+
+          # From {testMode}, we're now in {mode} mode...
+          {test}
+        """
+
+        writeTestInner(storecmd, f, r, lines, 1 if delegated else 3)
+
+        f.write(f"""
+          j _j_goto_machine_mode_{labelSuffix}
+        """)
+
+      else:
+        lines = f"""
+          {original}
+          {beforeTest}
+          {test}
+        """
+        writeTestInner(storecmd, f, r, lines, 3)
+
+      f.write(f"""
+        _j_finished_{labelSuffix}:
+        li x30, 0
+      """)
+      
+
+def writeTestInner(storecmd, f, r, lines, expected):
+  global testnum
+
+  lines = f"""
+    li x25, 0xDEADBEA7
+    {lines}
+  """
+
+  lines += storecmd + " x25, " + str(testnum * wordsize) + "(x6)\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+numrand = 1;
+
+# setup
+seed(0xD0C0_D0C0_D0C0_D0C0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for testMode in ["m"]:
+    for isInterrupts in [True, False]:
+      imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+      basename = "WALLY-" + testMode.upper() + ("I" if isInterrupts else "E") + "DELEG"
+      fname = imperaspath + "src/" + basename + ".S"
+      refname = imperaspath + "references/" + basename + ".reference_output"
+
+      # print custom header part
+      f = open(fname, "w")
+      r = open(refname, "w")
+      line = "///////////////////////////////////////////\n"
+      f.write(line)
+      lines="// "+fname+ "\n// " + author + "\n"
+      f.write(lines)
+      line ="// Created " + str(datetime.now()) 
+      f.write(line)
+
+      # insert generic header
+      h = open("../testgen_header.S", "r")
+      for line in h:  
+        f.write(line)
+
+      # All registers used:
+      # x19: mtvec old value
+      # x18: medeleg old value
+      # x17: mideleg old value
+
+      f.write(f"""
+        add x7, x6, x0
+        csrr x19, mtvec
+        csrr x18, medeleg
+        csrr x17, medeleg
+      """)
+
+      testnum = 0
+      for i in range(0, 2):
+        writeVectors(storecmd)
+
+      f.write(f"""
+        csrw mtvec, x19
+        csrw medeleg, x18
+        csrw mideleg, x17
+      """)
+
+      # if we're in supervisor mode, this leaves the ebreak instruction untested (we need a way to)
+      # get back to machine mode. 
+
+      # print footer
+      h = open("../testgen_footer.S", "r")
+      for line in h:  
+        f.write(line)
+
+      # Finish
+      lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+      lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+      f.write(lines)
+      f.close()
+      r.close()
+
+
+
diff --git a/tests/testgen/privileged/testgen-EPC.py b/tests/testgen/privileged/testgen-EPC.py
new file mode 100755
index 000000000..8093ef403
--- /dev/null
+++ b/tests/testgen/privileged/testgen-EPC.py
@@ -0,0 +1,263 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py
+#
+# dottolia@hmc.edu 1 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
+
+def randRegs():
+  reg1 = randint(1,20)
+  reg2 = randint(1,20)
+  reg3 = randint(1,20)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return str(reg1), str(reg2), str(reg3)
+
+def writeVectors(storecmd):
+  global testnum
+
+  # Load address misaligned
+  writeTest(storecmd, f, r, f"""
+    ecall
+  """, False, 9)
+  
+
+def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
+  global testnum
+  global testMode
+
+  nops = ""
+  for i in range(0, randint(1, 16)):
+    nops+="nop\n"
+
+  lines = f"""
+    {nops}
+    li x25, 0xDEADBEA7
+    auipc x26, 0
+    addi x26, x26, 8
+    {test}
+
+    _jend{testnum}:
+
+    {storecmd} x25, 0(x7)
+    addi x7, x7, {wordsize}
+  """
+
+  f.write(lines)
+
+  expected = 0
+
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+numrand = 64;
+
+# setup
+seed(0x9365DDEB9173AB42) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  corners = [
+    0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+    2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
+  ]
+
+  for testMode in ["m", "s"]:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + testMode.upper() + "EPC"
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # All registers used:
+    # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
+    # ...
+    # x26: expected epc value
+    # x25: value to write to memory
+    # ...
+    # x19: mtvec old value
+    # x18: medeleg old value
+    # x17: sedeleg old value
+
+
+    lines = f"""
+      add x7, x6, x0
+      csrr x19, mtvec
+
+      csrr x18, medeleg
+      li x9, {"0b1100000000" if testMode == "s" or testMode == "u" else "0b0000000000"}
+      csrs medeleg, x9
+
+    """
+
+    if testMode == "u":
+      lines += f"""
+        csrr x17, sedeleg
+        li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
+        csrs sedeleg, x9
+        """
+
+    lines += f"""
+
+      li x30, 0
+
+      la x1, _j_m_trap
+      csrw mtvec, x1
+      la x1, _j_s_trap
+      csrw stvec, x1
+      la x1, _j_u_trap
+      csrw utvec, x1
+      j _j_t_begin
+
+      _j_m_trap:
+      csrrs x1, mepc, x0
+      {"sub x25, x26, x1" if testMode == "m" else "li x25, 0xBAD00003"}
+
+      addi x1, x1, 4
+      csrrw x0, mepc, x1
+      bnez x30, _j_all_end
+      mret
+
+      _j_s_trap:
+      csrrs x1, sepc, x0
+      {"sub x25, x26, x1" if testMode == "s" else "li x25, 0xBAD00001"}
+
+      addi x1, x1, 4
+      csrrw x0, sepc, x1
+      bnez x30, _j_goto_machine_mode
+      sret
+
+      _j_u_trap:
+      csrrs x1, uepc, x0
+      {"sub x25, x26, x1" if testMode == "u" else "li x25, 0xBAD00000"}
+
+      addi x1, x1, 4
+      csrrw x0, uepc, x1
+      bnez x30, _j_goto_supervisor_mode
+      uret
+
+      _j_goto_supervisor_mode:
+      csrw sedeleg, x17
+      j _j_goto_machine_mode
+
+      _j_goto_machine_mode:
+      csrw medeleg, x18
+      li x30, 1
+      ecall
+
+      _j_t_begin:
+    """
+
+    fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
+
+    f.write(lines)
+
+    for fromMode in fromModeOptions:
+      lines = ""
+      
+      if fromMode == "s" or fromMode == "u":
+        lines += f"""
+          li x1, 0b110000000000
+          csrrc x31, mstatus, x1
+          li x1, 0b0100000000000
+          csrrs x31, mstatus, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the mret instruction
+          csrw mepc, x1
+          mret
+
+          # We're now in supervisor mode...
+        """
+
+      if fromMode == "u":
+        lines += f"""
+
+        li x1, 0b110000000000
+        csrrc x31, sstatus, x1
+
+        auipc x1, 0
+        addi x1, x1, 16 # x1 is now right after the sret instruction
+        csrw sepc, x1
+        sret
+
+        # We're now in user mode...
+        """
+
+      # print directed and random test vectors
+      f.write(lines)
+      for i in range(0,numrand):
+        writeVectors(storecmd)
+
+
+    f.write(f"""
+      li x30, 1
+      ecall
+      _j_all_end:
+
+      csrw mtvec, x19
+    """)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
diff --git a/tests/testgen/privileged/testgen-IE.py b/tests/testgen/privileged/testgen-IE.py
new file mode 100755
index 000000000..5a82d019f
--- /dev/null
+++ b/tests/testgen/privileged/testgen-IE.py
@@ -0,0 +1,406 @@
+#!/usr/bin/python3
+##################################
+# testgen-IE.py
+#
+# ushakya@hmc.edu 31 March 2021
+# Modified: 4 April 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def writeTrapHandlers(storecmd, mode):
+  global testnum
+  [reg1, reg2, reg3] = [30, 29, 28]
+  [reg4, reg5] = [27, 26]
+  if mode == "M":
+    lines = "\n# Trap Handler: Machine Timer Interupt\n"
+    lines += "_timerM_trap_handler:\n"
+    lines += "li x" + str(reg1) + ", MASK_XLEN(0xFFFF)\n"
+    lines += "la x" + str(reg2) + ", 0x2004000\n"
+    lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
+    lines += "csrrc x" + str(reg3) + ", mepc, x0\n"
+    lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+    lines += "csrrw x0, mepc, x" + str(reg3) + "\n"
+    # clear machine timer interupt enable bit in mie
+    lines += "li x" + str(reg4) + ", MASK_XLEN(" + str(0x80) + ")\n"
+    lines += "csrrc x0, mie, x" + str(reg4) + "\n"
+    lines += "mret\n"
+  elif mode == "S":
+    lines = "\n# Trap Handler: Supervisor Timer Interupt\n"
+    lines += "_timerS_trap_handler:\n"
+    lines += "li x" + str(reg4) + ", MASK_XLEN(0x20)\n"
+    lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+    lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+    lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+    lines += "mret\n"
+
+  #lines += "\n# Trap Handler: User Timer Interupt\n"
+  #lines += "_timerU_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x10)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: Machine Software Interupt\n"
+  #lines += "_softwareM_trap_handler:\n"
+  #lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
+  #lines += "la x" + str(reg2) + ", 0x2000000\n"
+  #lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
+  ##lines += "csrrs x" + str(reg3) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+  #lines += "csrrw x0, mepc, x" + str(reg3) + "\n"
+  #lines += "mret\n"
+
+  """lines += "\n# Trap Handler: Supervisor Software Interupt\n"
+  lines += "_softwareS_trap_handler:\n"
+  lines += "li x" + str(reg4) + ", MASK_XLEN(0x2)\n"
+  lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  lines += "csrrs x" + str(reg5) + ", mepc, x0\n"
+  lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  lines += "csrrw x0, mepc, x" + str(reg5) + "\n"
+  lines += "mret\n"
+"""
+  #lines += "\n# Trap Handler: User Software Interupt\n"
+  #lines += "_softwareU_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x1)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: Machine External Interupt\n"
+  #lines += "_externalM_trap_handler:\n"
+  #lines += "li x" + str(reg1) + ", MASK_XLEN(0x0)\n" # clear MSIP bit in CLINT
+  #lines += "la x" + str(reg2) + ", 0x2000000\n"
+  #lines += str(storecmd) + " x" + str(reg1) + ",  0(x" + str(reg2) + ")\n"
+  #lines += "csrrw x" + str(reg3) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg3) + ", x" + str(reg3) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: Supervisor External Interupt\n"
+  #lines += "_externalS_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x200)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  #lines += "\n# Trap Handler: User External Interupt\n"
+  #lines += "_externalU_trap_handler:\n"
+  #lines += "li x" + str(reg4) + ", MASK_XLEN(0x100)\n"
+  #lines += "csrrc x0, mip, x" + str(reg4) + "\n"
+  #lines += "csrrw x" + str(reg5) + ", mepc, x0\n"
+  #lines += "addi x"+ str(reg5) + ", x" + str(reg5) + ", MASK_XLEN(0x4)\n"
+  #lines += "mret\n"
+
+  f.write(lines)
+
+def getInteruptEnableValues():
+  if test == "timerM":
+    mstatusE = 0x8
+    mieE = 0x80
+  elif test == "timerS":
+    mstatusE = 0x2
+    mieE = 0x20
+  elif test == "timerU":
+    mstatusE = 0x1
+    mieE = 0x10
+  elif test == "softwareM":
+    mstatusE = 0x8
+    mieE = 0x8
+  elif test == "softwareS":
+    mstatusE = 0x2
+    mieE = 0x2
+  elif test == "softwareU":
+    mstatusE = 0x1
+    mieE = 0x1
+  elif test == "externalM":
+    mstatusE = 0x8
+    mieE = 0x800
+  elif test == "externalS":
+    mstatusE = 0x2
+    mieE = 0x200
+  elif test == "externalU":
+    mstatusE = 0x1
+    mieE = 0x100
+  return [mstatusE, mieE]
+
+def getMcause():
+  b = 1 << (xlen-1)
+  if test == "timerM":
+    b = b + 0x7
+  elif test == "timerS":
+    b = b + 0x5
+  elif test == "timerU":
+    b = b + 0x4
+  elif test == "softwareM":
+    b = b + 0x3
+  elif test == "softwareS":
+    b = b + 0x1
+  elif test == "softwareU":
+    b = b
+  elif test == "externalM":
+    b = b + 0xB
+  elif test == "externalS":
+    b = b + 0x9
+  elif test == "externalU":
+    b = b + 0x8
+  return b
+
+def writeVectors(a, xlen, storecmd):
+  global testnum
+
+  # Registers used:
+  # x13 ---> read mcause value
+  # x12 ---> save old value of mtvec
+  # x8  ---> holds mieE
+  # x5  ---> holds value of trap handler
+  # x3  ---> holds mstatusE
+  # remaining registers (not used by mode management) are free to be used by tests
+
+  [reg2, reg3] = [2, 3]
+  [reg5, reg8] = [5, 8]
+  [reg10, reg11, reg12] = [10, 11, 12]
+  [reg13, reg14, reg15] = [13, 14, 15]
+
+  lines = f"\n# Testcase {testnum}: {test} Interupt\n"
+  
+  # mcause code
+  expected = getMcause()
+
+  [mstatusE, mieE] = getInteruptEnableValues()
+  # ensure interupt enable bit in mie is low
+  lines += "li x" + str(reg8) + ", MASK_XLEN(" + formatstr.format(mieE) + ")\n"
+  lines += "csrrc x0, mie, x" + str(reg8) + "\n"
+
+  # set interupt enable bit in mstatus
+  lines += "li x" + str(reg3) + ", MASK_XLEN(" + formatstr.format(mstatusE) + ")\n"
+  lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
+
+  # Save and set trap handler address for interrupt
+  lines += "la x" + str(reg5) + ", _" + test + "_trap_handler\n"
+  
+  # save orignal mtvec address
+  lines += "csrrw x" + str(reg12) + ", mtvec, x" + str(reg5) + "\n"
+  
+  # cause timer interupt
+  if test == "timerM":
+    
+    # load MTIMECMP register address
+    lines += "la x" + str(reg2) + ", 0x2004000\n"
+
+    # to be stored in MTIMECMP
+    lines += "li x" + str(reg10) + ", MASK_XLEN(0)\n"
+
+    # save old value of mtimecmp and then set mtimecmp to zero
+    if xlens == 64:
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+
+    elif xlen == 32:
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  4(x" + str(reg2) + ")\n"
+
+  elif test == "timerS":
+    lines += "li x" + str(reg3) + ", MASK_XLEN(0x20)\n"
+    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
+  
+  # cause software interupt
+  if test == "softwareM":
+    lines += "la x" + str(reg8) + ", 0x2000000\n" # Write to the MSIP bit in CLINT
+    lines += "li x" + str(reg11) + ", MASK_XLEN(0x1)\n"
+    lines += str(storecmd) + " x" + str(reg11) + ",  0(x" + str(reg8) + ")\n"
+  elif test == "softwareS":
+    lines += "li x" + str(reg3) + ", MASK_XLEN(0x2)\n"
+    lines += "csrrs x0, mip, x" + str(reg3) + "\n"
+  
+
+  # set timer interupt enable bit in mie
+  lines += "csrrs x0, mie, x" + str(reg8) + "\n"
+  
+  # wait for interupt to be taken
+  lines += "nop\nnop\n"
+
+  lines += "csrrs " + " x" + str(reg13) + ", mcause, x0\n"
+
+  # reset mtvec
+  lines += "csrrw x0, mtvec, x" + str(reg12) + "\n"
+
+  lines += storecmd + " x" + str(reg13) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg13) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["timerM"] #, "timerM", "timerS", "softwareM", "softwareS"]
+author = "ushakya@hmc.edu"
+xlens = [64] #, 32]
+modes = ["M"]#, "S"]
+numrand = 100;
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for mode in modes:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + mode + "IE"
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+    
+    line = "\n"
+    # Registers used for dropping down to supervisor mode:
+    # x30 ---> set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
+    # x20 ---> hold address of _j_all_end_{returningInstruction}
+    # x19 ---> save old value of mtvec
+    # x18 ---> save old value of medeleg
+    # x16 ---> save old value of mideleg
+    # x9  ---> bit mask for mideleg and medeleg
+    # x1  ---> used to go down to supervisor mode
+
+    # We need to leave at least one bit in medeleg unset so that we have a way to get
+    # back to machine mode when the tests are complete (otherwise we'll only ever be able
+    # to get up to supervisor mode). 
+    #
+    # So, we define a returning instruction which will be used to cause the exception that
+    # brings us into machine mode. The bit for this returning instruction is NOT set in
+    # medeleg. However, this also means that we can't test that instruction. So, we have
+    # two different returning instructions.
+    #
+    # Current code is written to only support ebreak and ecall.
+    #
+    # For testgen-IE, we don't need to test ebreak, so we can use that as the sole
+    # returning instruction.
+    returningInstruction = "ebreak"
+    if mode == "S":
+      # need to move down to supervisor mode (based on code in testgen-TVAL)
+      lines += f"""
+        # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
+        li x30, 0
+      """
+
+      # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
+      # back to machine mode at the end! (and we need to be in machine mode to complete the tests)
+      medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
+
+      # Set medeleg and mideleg
+      lines += f"""
+        csrr x18, medeleg
+        li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
+        csrw medeleg, x9
+
+        csrr x16, mideleg
+        li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
+        csrw mideleg, x9
+      """
+
+      # bring down to supervisor mode
+      lines += f"""
+            li x1, 0b110000000000
+            csrrc x31, mstatus, x1
+            li x1, 0b0100000000000
+            csrrs x31, mstatus, x1
+
+            auipc x1, 0
+            addi x1, x1, 16 # x1 is now right after the mret instruction
+            csrw mepc, x1
+            mret
+
+            # We're now in supervisor mode...
+          """
+
+    for test in tests:
+      # print directed and random test vectors
+      for i in range(0,numrand):
+        a = getrandbits(xlen)
+        writeVectors(a, xlen, storecmd)
+
+    if mode == "S":
+      # Bring us back up to machine mode!
+      # Creates a new trap handler that just jumps to _j_all_end_{returningInstruction}
+      #
+      # Get into the trap handler by running returningInstruction (in this case its ebreak) 
+      f.write(f"""
+        li x30, 1 #may not need this 
+        csrr x19, mtvec # save old value of mtvec
+        la x20 _j_all_end_{returningInstruction}
+        csrw mtvec, x20
+        {returningInstruction}
+
+        _returnMachineMode_handler:
+        j _j_all_end_{returningInstruction}
+        mret
+
+        _j_all_end_{returningInstruction}:
+
+        # Reset trap handling csrs to old values
+        csrw mtvec, x19
+        csrw medeleg, x18
+        csrw mideleg, x16
+      """)
+    
+    f.write(lines)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+
+    writeTrapHandlers(storecmd, mode)
+
+    f.close()
+    r.close()
diff --git a/tests/testgen/privileged/testgen-IP.py b/tests/testgen/privileged/testgen-IP.py
new file mode 100755
index 000000000..a4910977d
--- /dev/null
+++ b/tests/testgen/privileged/testgen-IP.py
@@ -0,0 +1,196 @@
+#!/usr/bin/python3
+##################################
+# testgen-IE.py
+#
+# ushakya@hmc.edu 31 March 2021
+# Modified: 4 April 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def getInteruptEnableValues():
+  if test == "timerM":
+    mstatusE = 0x8
+    mieE = 0x80
+  elif test == "timerS":
+    mstatusE = 0x2
+    mieE = 0x20
+  elif test == "timerU":
+    mstatusE = 0x1
+    mieE = 0x10
+  elif test == "softwareM":
+    mstatusE = 0x8
+    mieE = 0x8
+  elif test == "softwareS":
+    mstatusE = 0x2
+    mieE = 0x2
+  elif test == "softwareU":
+    mstatusE = 0x1
+    mieE = 0x1
+  elif test == "externalM":
+    mstatusE = 0x8
+    mieE = 0x800
+  elif test == "externalS":
+    mstatusE = 0x2
+    mieE = 0x200
+  elif test == "externalU":
+    mstatusE = 0x1
+    mieE = 0x100
+  return [mstatusE, mieE]
+
+def getMcause():
+  b = 1 << (xlen-1)
+  if test == "timerM":
+    b = b + 0x7
+  elif test == "timerS":
+    b = b + 0x5
+  elif test == "timerU":
+    b = b + 0x4
+  elif test == "softwareM":
+    b = b + 0x3
+  elif test == "softwareS":
+    b = b + 0x1
+  elif test == "softwareU":
+    b = b
+  elif test == "externalM":
+    b = b + 0xB
+  elif test == "externalS":
+    b = b + 0x9
+  elif test == "externalU":
+    b = b + 0x8
+  return b
+
+# MIP is implicitly tested in the MIE tests
+# these tests are to test that when mtimecmp < mtime
+# MTIP bit is high in MIP
+def writeVectors(a, xlen, storecmd):
+  global testnum
+
+  [reg2, reg3] = [2, 3]
+  [reg5, reg8] = [5, 8]
+  [reg10, reg11, reg12] = [10, 11, 12]
+  [reg13, reg14, reg15] = [13, 14, 15]
+
+  lines = f"\n# Testcase {testnum}: {test} Interupt\n"
+  
+  # mcause code
+  expected = 0x80
+
+  [mstatusE, mieE] = getInteruptEnableValues()
+  # ensure interupt enable bit in mie is low
+  lines += "li x" + str(reg8) + ", MASK_XLEN(" + formatstr.format(mieE) + ")\n"
+  lines += "csrrc x0, mie, x" + str(reg8) + "\n"
+
+  # set interupt enable bit in mstatus
+  lines += "li x" + str(reg3) + ", MASK_XLEN(" + formatstr.format(mstatusE) + ")\n"
+  lines += "csrrs x0, mstatus, x" + str(reg3) + "\n"
+  
+  # cause timer interupt
+  if test == "timerM":
+    
+    # load MTIMECMP register address
+    lines += "la x" + str(reg2) + ", 0x2004000\n"
+
+    # to be stored in MTIMECMP
+    lines += "li x" + str(reg10) + ", MASK_XLEN(0)\n"
+
+    # save old value of mtimecmp and then set mtimecmp to zero
+    if xlens == 64:
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+
+    elif xlen == 32:
+      lines += "lw x" + str(reg11) + ", 0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  0(x" + str(reg2) + ")\n"
+      lines += str(storecmd) + " x" + str(reg10) + ",  4(x" + str(reg2) + ")\n"
+
+  lines += "csrrs " + " x" + str(reg13) + ", mip, x0\n"
+
+  lines += storecmd + " x" + str(reg13) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, x" + str(reg13) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["timerM"] #, "softwareM"]
+author = "ushakya@hmc.edu"
+xlens = [64, 32]
+numrand = 100;
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  
+  imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+  basename = "WALLY-IP"
+  fname = imperaspath + "src/" + basename + ".S"
+  refname = imperaspath + "references/" + basename + ".reference_output"
+  testnum = 0
+
+  # print custom header part
+  f = open(fname, "w")
+  r = open(refname, "w")
+  line = "///////////////////////////////////////////\n"
+  f.write(line)
+  lines="// "+fname+ "\n// " + author + "\n"
+  f.write(lines)
+  line ="// Created " + str(datetime.now()) 
+  f.write(line)
+
+  # insert generic header
+  h = open("../testgen_header.S", "r")
+  for line in h:  
+    f.write(line)
+  
+  for test in tests:
+    # print directed and random test vectors
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      writeVectors(a, xlen, storecmd)
+
+  f.write(lines)
+
+  # print footer
+  h = open("../testgen_footer.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # Finish
+  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  f.write(lines)
+
+  f.close()
+  r.close()
diff --git a/tests/testgen/privileged/testgen-READONLY.py b/tests/testgen/privileged/testgen-READONLY.py
new file mode 100755
index 000000000..ad94b60cd
--- /dev/null
+++ b/tests/testgen/privileged/testgen-READONLY.py
@@ -0,0 +1,235 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py
+#
+# dottolia@hmc.edu 1 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
+
+def randRegs():
+  reg1 = randint(1,20)
+  reg2 = randint(1,20)
+  reg3 = randint(1,20)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return str(reg1), str(reg2), str(reg3)
+
+def writeVectors(a, storecmd):
+  writeSingleVector(a, storecmd, f"""csrrw x0, {test}, x13""")
+  writeSingleVector(a, storecmd, f"""csrrwi x0, {test}, {a % 32}""")
+  if a != 0:
+    writeSingleVector(a, storecmd, f"""csrrs x0, {test}, x13""")
+    writeSingleVector(a, storecmd, f"""csrrc x0, {test}, x13""")
+    writeSingleVector(a, storecmd, f"""csrrsi x0, {test}, {(a % 31) + 1}""")
+    writeSingleVector(a, storecmd, f"""csrrci x0, {test}, {(a % 31) + 1}""")
+
+
+def writeSingleVector(a, storecmd, writeInstruction):
+  global testnum
+
+  # Illegal Instruction 
+  writeTest(storecmd, f, r, f"""
+    li x13, MASK_XLEN({a})
+    csrrw x11, {test}, x0
+    {writeInstruction}
+    csrrwi x12, {test}, 0
+    sub x15, x11, x12
+  """, False, 2)
+  
+  expected = 0
+  lines = ""
+  lines += storecmd + " x15, " + str(wordsize*testnum) + "(x6)\n"
+  #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+  
+
+def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = ""):
+  global testnum
+
+  expected = code
+  if(interrupt):
+    expected+=(1 << (wordsize - 1))
+
+
+  trapEnd = ""
+  before = ""
+  if mode != "m":
+    before = f"""
+      li x1, 0b110000000000
+      csrrc x28, mstatus, x1
+      li x1, 0b{"01" if mode == "s" else "00"}0000000000
+      csrrs x28, mstatus, x1
+
+      auipc x1, 0
+      addi x1, x1, 16 # x1 is now right after the mret instruction
+      csrrw x27, mepc, x1
+      mret
+
+      # We're now in {mode} mode...
+    """
+
+    trapEnd = f"""j _jend{testnum}"""
+
+
+  # Setup
+  # TODO: Adding 8 to x30 won't work for 32 bit?
+  # x31: Old mtvec value
+  # x30: trap handler address
+  # x29: Old mtvec value for user/supervisor mode
+  # x28: Old mstatus value
+  # x27: Old mepc value
+  # x26: 0 if we should execute mret normally. 1 otherwise. This allows us to stay in machine
+  # x25: mcause
+  # mode for the next tests
+  lines = f"""
+    # Testcase {testnum}
+    csrrs x31, mtvec, x0
+
+    auipc x30, 0
+    addi x30, x30, 12
+    j _jtest{testnum}
+
+    # Machine trap vector
+    {resetHander}
+    csrrs x25, mcause, x0
+    csrrs x1, mepc, x0
+    addi x1, x1, 4
+    csrrw x0, mepc, x1
+    {trapEnd}
+    mret
+
+    # Actual test
+    _jtest{testnum}:
+    csrrw x0, mtvec, x30
+
+    # Start test code
+    li x25, 0x7BAD
+    {before}
+    {test}
+
+    # Finished test. Reset to old mtvec
+    _jend{testnum}:
+
+    csrrw x0, mtvec, x31
+  """
+
+  #expected = 42
+  
+  lines += storecmd + " x25, " + str(wordsize*testnum) + "(x6)\n"
+  #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+  # lines += storecmd + " x0" + ", " + str(wordsize*testnum) + "(x6)\n"
+  # #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
+  # f.write(lines)
+  # if (xlen == 32):
+  #   line = formatrefstr.format(expected)+"\n"
+  # else:
+  #   line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  # r.write(line)
+  # testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+numrand = 4;
+tests = ["marchid", "mhartid", "mimpid", "mvendorid"]
+
+# setup
+seed(0xD365DDEB9173AB42) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  for test in tests:
+    corners = [
+      0, 1, 2, 31, 32,
+      0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+      2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
+    ]
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + test.upper()
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for i in corners:
+      writeVectors(i, storecmd)
+    for i in range(0,numrand):
+      writeVectors(getrandbits(xlen), storecmd)
+
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/privileged/testgen-RET.py b/tests/testgen/privileged/testgen-RET.py
new file mode 100755
index 000000000..8921cfb8e
--- /dev/null
+++ b/tests/testgen/privileged/testgen-RET.py
@@ -0,0 +1,157 @@
+#!/usr/bin/python3
+##################################
+# testgen-CAUSE.py
+#
+# dottolia@hmc.edu 16 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from enum import Enum
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+# def computeExpected(a, b, test):
+#   if (test == "ADD"):
+#     return a + b
+#   elif (test == "SUB"):
+#     return a - b
+#   else:
+#     die("bad test name ", test)
+#   #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,30)
+  reg2 = randint(1,30)
+  reg3 = randint(1,30)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVectors(storecmd):  
+  global testnum
+  reg1, reg2, reg3 = randRegs()
+
+  # t5 gets written with mtvec?
+
+  # lines = f"""
+
+  # li x{reg1}, 0
+  # csrwi mtvec, 80002000
+  # .data 00000000
+  # j _done{testnum}
+
+  # _trap{testnum}:
+  # csrrs x{reg1}, mcause, x0
+  # ecall
+
+  # _done{testnum}:
+  # add x0, x0, x0
+  # """
+
+  #lines = 
+
+
+  # https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html
+
+  lines = f"""
+  li x1, 100
+  li x2, 200
+  add x3, x1, x2
+  add x6, x3, x3
+
+  """
+  f.write(lines)
+
+  expected = 600
+
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+
+##################################
+# main body
+##################################
+
+author = "Domenico Ottolia (dottolia@hmc.edu)"
+xlens = [32, 64]
+numrand = 60;
+
+# setup
+seed(0xC395D19B9173AD42) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  imperaspath = f"""../../../imperas-riscv-tests/riscv-test-suite/rv{xlen}p/"""
+  basename = "WALLY-RET"
+  fname = imperaspath + "src/" + basename + ".S"
+  refname = imperaspath + "references/" + basename + ".reference_output"
+  testnum = 0
+
+  # print custom header part
+  f = open(fname, "w")
+  r = open(refname, "w")
+  line = "///////////////////////////////////////////\n"
+  f.write(line)
+  lines="// "+fname+ "\n// " + author + "\n"
+  f.write(lines)
+  line ="// Created " + str(datetime.now()) 
+  f.write(line)
+
+  # insert generic header
+  # h = open("../testgen_header.S", "r")
+  # for line in h:  
+  #   f.write(line)
+
+  # print directed and random test vectors
+
+  h = open("../testgen_header.S", "r")
+  for line in h:  
+    f.write(line)
+
+  writeVectors(storecmd)
+
+  h = open("../testgen_footer.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # Finish
+  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  f.write(lines)
+
+
+  # print footer
+  # h = open("../testgen_footer.S", "r")
+  # for line in h:  
+  #   f.write(line)
+
+  # Finish
+  # lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+  # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  # f.write(lines)
+  f.close()
+  r.close()
+
diff --git a/tests/testgen/privileged/testgen-TVAL.py b/tests/testgen/privileged/testgen-TVAL.py
new file mode 100755
index 000000000..572d930c9
--- /dev/null
+++ b/tests/testgen/privileged/testgen-TVAL.py
@@ -0,0 +1,374 @@
+#!/usr/bin/python3
+##################################
+# testgen-TVAL.py
+#
+# dottolia@hmc.edu 1 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+#
+##################################
+# DOCUMENTATION:
+#
+# Most of the comments explaining what everything
+# does and the layout of the privileged tests
+# can be found in this file
+#
+###################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def writeVectors(storecmd):
+  global testnum
+
+  # Illegal Instruction 
+  writeTest(storecmd, f, r, f"""
+    .fill 1, 4, 0
+  """, f"""
+    li x23, 0
+  """)
+
+  val = (randint(0, 200) * 2) + 1
+
+  # Load Address Misaligned 
+  writeTest(storecmd, f, r, f"""
+    lw x0, {val}(x0)
+  """, f"""
+    li x23, {val}
+  """)
+
+  val = (randint(0, 200) * 2) + 1
+
+  # Store Address Misaligned 
+  writeTest(storecmd, f, r, f"""
+    sw x0, {val}(x0)
+  """, f"""
+    li x23, {val}
+  """)
+  
+
+  
+
+def writeTest(storecmd, f, r, test, expected, mode = "m", resetHander = ""):
+  global testnum, storeAddressOffset
+
+  # The code we actually change for our test
+  lines = f"""
+    {expected}
+    csrr x25, {testMode}tval
+    sub x25, x25, x23
+  """
+
+  # Boilerplate
+  #
+  # x28 is the address that our trap handler will jump to before returning.
+  # This is where we can do our actual tests. After we're done computing and storing
+  # what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
+  # 
+  lines = f"""
+    la x28, _jtest{testnum}
+    j _jdo{testnum}
+
+    _jtest{testnum}:
+    {lines}
+    jr x27
+
+    _jdo{testnum}:
+    li x25, 0xDEADBEA7
+    {test}
+  """
+
+  # We expect x25 to be 0 always. This is because of the code we wrote at the begining
+  # of this function
+  expected = 0
+  
+  # Store the expected value of x25 to memory and in the .reference_output file
+  lines += f"""
+    {storecmd} x25, 0(x7)
+    addi x7, x7, {wordsize}
+  """
+
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+testCount = 32;
+
+# setup
+# Change this seed to a different constant value for every test
+seed(0xC363DAEB9193AB45) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  # testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
+  for testMode in ["m", "s"]:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + testMode.upper() + "TVAL"
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+    storeAddressOffset = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # We need to leave at least one bit in medeleg unset so that we have a way to get
+    # back to machine mode when the tests are complete (otherwise we'll only ever be able
+    # to get up to supervisor mode). 
+    #
+    # So, we define a returning instruction which will be used to cause the exception that
+    # brings us into machine mode. The bit for this returning instruction is NOT set in
+    # medeleg. However, this also means that we can't test that instruction. So, we have
+    # two different returning instructions.
+    #
+    # Current code is written to only support ebreak and ecall.
+    #
+    # For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
+    # returning instruction. For others, like testgen-CAUSE, we'll need to put
+    # both ebreak and ecall here.
+    for returningInstruction in ["ebreak"]:
+
+      # All registers used:
+      # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
+      # ...
+      # x28: address trap handler should jump to for the test
+      # x27: address the test should return to after the test
+      # ...
+      # x25: value to write to memory
+      # ...
+      # x20: intermediate value in trap handler. Don't overwrite this!
+      # x19: mtvec old value
+      # x18: medeleg old value
+      # x17: sedeleg old value (currently unused — user mode traps deprecated)
+      # x16: mideleg old value
+      # ...
+      # x10 - x14 can be freely written
+      # ...
+      # x7: copy of x6. Increment this instead of using an offset on x6.
+      #     this allows us to create more than 2048/wordlen tests.
+      #     This is the address we write results to
+      # x6: Starting address we should write expected results to
+      # ...
+      # x4 & x5 can be freely written
+      # x3 — DO NOT WRITE ANY NON-ZERO VALUE TO THIS — test exits on ecall if x3 = 1 (x3 is gp)
+      # x1 & x2 can be freely written 
+
+
+
+      # Set up x7 and store old value of mtvec
+      lines = f"""
+        add x7, x6, x0
+        csrr x19, mtvec
+      """
+
+      # Not used — user mode traps are deprecated
+      if testMode == "u":
+        lines += f"""
+          csrr x17, sedeleg
+          li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
+          csrs sedeleg, x9
+          """
+
+      # Code that will jump to the test (x28 is set in writeTest above)
+      testJumpCode = f"""
+        auipc x27, 0
+        addi x27, x27, 12
+        jr x28
+      """
+
+      # Code for handling traps in different modes
+      # Some comments are inside of the below strings (prefixed with a #, as you might expected)
+      lines += f"""
+        # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
+        li x30, 0
+
+        # Set up 
+        la x1, _j_m_trap_{returningInstruction}
+        csrw mtvec, x1
+        la x1, _j_s_trap_{returningInstruction}
+        csrw stvec, x1
+        la x1, _j_u_trap_{returningInstruction}
+        # csrw utvec, x1 # user mode traps are not supported
+
+        # Start the tests!
+        j _j_t_begin_{returningInstruction}
+
+        # Machine mode traps
+        _j_m_trap_{returningInstruction}:
+        {testJumpCode if testMode == "m" else "li x25, 0xBAD00003"}
+
+        csrrs x20, mepc, x0
+        addi x20, x20, 4
+        csrrw x0, mepc, x20
+        bnez x30, _j_all_end_{returningInstruction}
+        mret
+
+        # Supervisor mode traps
+        _j_s_trap_{returningInstruction}:
+        {testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
+
+        csrrs x20, sepc, x0
+        addi x20, x20, 4
+        csrrw x0, sepc, x20
+        bnez x30, _j_goto_machine_mode_{returningInstruction}
+        sret
+
+        # Unused: user mode traps are no longer supported
+        _j_u_trap_{returningInstruction}:
+        {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
+
+        csrrs x20, uepc, x0
+        addi x20, x20, 4
+        csrrw x0, uepc, x20
+        bnez x30, _j_goto_supervisor_mode_{returningInstruction}
+        uret
+
+        # Currently unused. Just jumps to _j_goto_machine_mode. If you actually
+        # want to implement this, you'll likely need to reset sedeleg here
+        # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
+        _j_goto_supervisor_mode_{returningInstruction}:
+        j _j_goto_machine_mode_{returningInstruction}
+
+        _j_goto_machine_mode_{returningInstruction}:
+        li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
+        {returningInstruction} # ... this instruction!
+
+        # Run the actual tests!
+        _j_t_begin_{returningInstruction}:
+      """
+
+      fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
+
+      # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
+      # back to machine mode at the end! (and we need to be in machine mode to complete the tests)
+      medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
+
+      # Set medeleg and mideleg
+      lines += f"""
+        csrr x18, medeleg
+        li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
+        csrw medeleg, x9
+
+        csrr x16, mideleg
+        li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
+        csrw mideleg, x9
+      """
+
+      f.write(lines)
+
+      for fromMode in fromModeOptions:
+        lines = ""
+        
+        # Code to bring us down to supervisor mode
+        if fromMode == "s" or fromMode == "u":
+          lines += f"""
+            li x1, 0b110000000000
+            csrrc x31, mstatus, x1
+            li x1, 0b0100000000000
+            csrrs x31, mstatus, x1
+
+            auipc x1, 0
+            addi x1, x1, 16 # x1 is now right after the mret instruction
+            csrw mepc, x1
+            mret
+
+            # We're now in supervisor mode...
+          """
+
+        # Code to bring us down to user mode
+        if fromMode == "u":
+          lines += f"""
+
+          li x1, 0b110000000000
+          csrrc x31, sstatus, x1
+
+          auipc x1, 0
+          addi x1, x1, 16 # x1 is now right after the sret instruction
+          csrw sepc, x1
+          sret
+
+          # We're now in user mode...
+          """
+
+        f.write(lines)
+        for i in range(0,testCount):
+          writeVectors(storecmd)
+
+
+      # Very end of test. Bring us back up to machine mode
+      # We set x30 to 1, which will cause us to branch to _j_all_end in the
+      # machine mode trap handler, before executing the mret instruction. This will
+      # make us stay in machine mode.
+      #
+      # If we're currently in user mode, this will first bump us up to the supervisor mode
+      # trap handler, which will call returningInstruction again before it's sret instruction,
+      # bumping us up to machine mode
+      #
+      # Get into the trap handler by running returningInstruction (either an ecall or ebreak) 
+      f.write(f"""
+        li x30, 1
+        {returningInstruction}
+        _j_all_end_{returningInstruction}:
+
+        # Reset trap handling csrs to old values
+        csrw mtvec, x19
+        csrw medeleg, x18
+        csrw mideleg, x16
+      """)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/privileged/testgen-TVEC.py b/tests/testgen/privileged/testgen-TVEC.py
new file mode 100755
index 000000000..fcdc80d7f
--- /dev/null
+++ b/tests/testgen/privileged/testgen-TVEC.py
@@ -0,0 +1,473 @@
+#!/usr/bin/python3
+##################################
+# testgen-TVEC.py (new)
+#
+# dottolia@hmc.edu 1 Mar 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+#
+#
+##################################
+# DOCUMENTATION:
+#
+# The most up-to-date comments explaining what everything
+# does and the layout of the privileged tests
+# can be found in testgen-TVAL.py. This and
+# other files do not have as many comments
+#
+###################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# setup
+##################################
+
+areVectoredTrapsSupported = True
+
+##################################
+# functions
+##################################
+
+#For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
+
+def randRegs():
+  reg1 = randint(1,20)
+  reg2 = randint(1,20)
+  reg3 = randint(1,20)
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return str(reg1), str(reg2), str(reg3)
+
+def writeVectors(storecmd, returningInstruction):
+  global testnum
+
+
+  # Illegal Instruction 
+  # writeTest(storecmd, f, r, f"""
+  #   .fill 1, 4, 0
+  # """, False, 0)
+
+  # # Breakpoint
+  # if returningInstruction != "ebreak":
+  #   writeTest(storecmd, f, r, f"""
+  #     ebreak
+  #   """, False, 0)
+
+  # # Load Address Misaligned 
+  # writeTest(storecmd, f, r, f"""
+  #   lw x0, 11(x0)
+  # """, False, 0)
+
+  # # Load Access fault: False, 5
+
+  # # Store/AMO address misaligned
+  # writeTest(storecmd, f, r, f"""
+  #   sw x0, 11(x0)
+  # """, False, 0)
+
+  # # Environment call from u-mode: only for when only M and U mode enabled?
+  # # writeTest(storecmd, f, r, f"""
+  # #   ecall
+  # # """, False, 8, "u")
+  if returningInstruction != "ecall":
+    writeTest(storecmd, f, r, f"""
+      ecall
+    """, False, 0)
+
+
+  if fromMode == "m" and testMode == "m":
+    expectedCode = 7 if fromMode == "m" else 5
+    clintAddr = "0x2004000"
+
+    writeTest(storecmd, f, r, f"""
+      li x1, 0x8
+      csrrs x0, {fromMode}status, x1
+
+      la x18, {clintAddr}
+      # lw x11, 0(x18)
+      # li x1, 0x3fffffffffffffff
+      # {storecmd} x1, 0(x18)
+
+      li x1, 0x80
+      csrrs x0, {fromMode}ie, x1
+
+      {storecmd} x0, 0(x18)
+    """, True, expectedCode, f"""
+      li x1, 0x80
+      csrrc x0, {fromMode}ie, x1
+
+      li x1, 0x8
+      csrrc x0, {fromMode}status, x1
+
+      la x18, {clintAddr}
+      {storecmd} x0, 0(x18)
+    """)
+
+  # Instruction page fault: 12
+  # Load page fault: 13
+  # Store/AMO page fault: 15
+  
+
+  
+
+def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
+  global testnum, storeAddressOffset, xlen
+
+  expected = code
+
+  # Boilerplate
+  #
+  # x28 is the address that our trap handler will jump to before returning.
+  # This is where we can do our actual tests. After we're done computing and storing
+  # what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
+  # 
+  lines = f"""
+    la x28, _jtest{testnum}
+    j _jdo{testnum}
+
+    _jtest{testnum}:
+    nop
+    {resetHander}
+    jr x27
+
+    _jdo{testnum}:
+    li x25, 0xDEADBEA7
+    {test}
+  """
+
+
+  if not areVectoredTrapsSupported or not vectoredInterrupts:
+    expected = 0
+
+  writeGeneralTest(storecmd, f, r, lines, expected)
+
+def writeGeneralTest(storecmd, f, r, test, expected):
+  global testnum, storeAddressOffset, xlen
+
+  lines = f"""
+    {test}
+    {storecmd} x25, {testnum * wordsize}(x6)
+  """
+
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+author = "dottolia@hmc.edu"
+xlens = [32, 64]
+testCount = 4;
+
+# setup
+# Change this seed to a different constant value for every test
+seed(0xC363DAEB9193AB45) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+
+  # testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
+  for testMode in ["m", "s"]:
+    imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
+    basename = "WALLY-" + testMode.upper() + "TVEC"
+    fname = imperaspath + "src/" + basename + ".S"
+    refname = imperaspath + "references/" + basename + ".reference_output"
+    testnum = 0
+    storeAddressOffset = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("../testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Ensure MODE of *tvec (last 2 bits) is either 00 or 01
+    f.write(f"""
+      csrr x19, {testMode}tvec
+    """)
+
+    for i in range(0, 16):
+      i = i;
+      trySet = i | 0b10;
+      expected = trySet & 0xFFFF_FFFFD;
+      writeGeneralTest(storecmd, f, r, f"""
+        li x1, {trySet}
+        csrw {testMode}tvec, x1
+        csrr x25, {testMode}tvec
+      """, expected)
+
+    f.write(f"""
+      csrw {testMode}tvec, x19
+    """)
+
+    # We need to leave at least one bit in medeleg unset so that we have a way to get
+    # back to machine mode when the tests are complete (otherwise we'll only ever be able
+    # to get up to supervisor mode). 
+    #
+    # So, we define a returning instruction which will be used to cause the exception that
+    # brings us into machine mode. The bit for this returning instruction is NOT set in
+    # medeleg. However, this also means that we can't test that instruction. So, we have
+    # two different returning instructions.
+    #
+    # Current code is written to only support ebreak and ecall.
+    #
+    # For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
+    # returning instruction. For others, like testgen-CAUSE, we'll need to put
+    # both ebreak and ecall here.
+
+
+    for returningInstruction in ["ebreak"]:
+      for vectoredInterrupts in [True, False]:
+
+        # All registers used:
+        # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
+        # ...
+        # x28: address trap handler should jump to for the test
+        # x27: address the test should return to after the test
+        # ...
+        # x25: value to write to memory
+        # ...
+        # x20: intermediate value in trap handler. Don't overwrite this!
+        # x19: mtvec old value
+        # x18: medeleg old value
+        # x17: sedeleg old value (currently unused — user mode traps deprecated)
+        # x16: mideleg old value
+        # ...
+        # x10 - x14 can be freely written
+        # ...
+        # x7: copy of x6. Increment this instead of using an offset on x6.
+        #     this allows us to create more than 2048/wordlen tests.
+        #     This is the address we write results to
+        # x6: Starting address we should write expected results to
+        # ...
+        # x1 - x5 can be freely written  
+
+
+
+        # Set up x7 and store old value of mtvec
+        lines = f"""
+          # add x7, x6, x0
+          csrr x19, mtvec
+        """
+
+        # Not used — user mode traps are deprecated
+        if testMode == "u":
+          lines += f"""
+            csrr x17, sedeleg
+            li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
+            csrs sedeleg, x9
+            """
+
+        # Code that will jump to the test (x28 is set in writeTest above)
+        testJumpCode = f"""
+          auipc x27, 0
+          addi x27, x27, 12
+          jr x28
+        """
+
+        beforeCode = {"m": "", "s": ""}
+        for pm in ["m", "s"]:
+          for i in range(0, 16):
+            beforeCode[pm] = beforeCode[pm] + f"""
+              nop
+              nop
+              li x25, {i}
+              j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts}
+            """
+
+        # Code for handling traps in different modes
+        # Some comments are inside of the below strings (prefixed with a #, as you might expected)
+        enableVectored = "addi x1, x1, 1" if vectoredInterrupts else ""
+
+        lines += f"""
+          # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
+          li x30, 0
+
+          # Set up 
+          la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts}
+          {enableVectored} # enable/don't enable vectored interrupts
+          csrw mtvec, x1
+          la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts}
+          {enableVectored} # enable/don't enable vectored interrupts
+          csrw stvec, x1
+          la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts}
+          {enableVectored} # enable/don't enable vectored interrupts
+          # csrw utvec, x1 # user mode traps are not supported
+
+          # Start the tests!
+          j _j_t_begin_{returningInstruction}_{vectoredInterrupts}
+
+          # Machine mode traps
+          _j_m_trap_{returningInstruction}_{vectoredInterrupts}:
+          {beforeCode['m']}
+
+          _j_m_trap_end_{returningInstruction}_{vectoredInterrupts}:
+          {testJumpCode}
+
+          csrrs x20, mepc, x0
+          addi x20, x20, 4
+          csrrw x0, mepc, x20
+          bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts}
+          mret
+
+          # Supervisor mode traps
+          _j_s_trap_{returningInstruction}_{vectoredInterrupts}:
+          {beforeCode['s']}
+
+          _j_s_trap_end_{returningInstruction}_{vectoredInterrupts}:
+          {testJumpCode}
+
+          csrrs x20, sepc, x0
+          addi x20, x20, 4
+          csrrw x0, sepc, x20
+          bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
+          sret
+
+          # Unused: user mode traps are no longer supported
+          _j_u_trap_{returningInstruction}_{vectoredInterrupts}:
+          {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
+
+          csrrs x20, uepc, x0
+          addi x20, x20, 4
+          csrrw x0, uepc, x20
+          bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}
+          uret
+
+          # Currently unused. Just jumps to _j_goto_machine_mode. If you actually
+          # want to implement this, you'll likely need to reset sedeleg here
+          # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
+          _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}:
+          j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}
+
+          _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}:
+          li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking...
+          {returningInstruction} # ... this instruction!
+
+          # Run the actual tests!
+          _j_t_begin_{returningInstruction}_{vectoredInterrupts}:
+        """
+
+        fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
+
+        # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
+        # back to machine mode at the end! (and we need to be in machine mode to complete the tests)
+        medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
+
+        # Set medeleg and mideleg
+        lines += f"""
+          csrr x18, medeleg
+          li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
+          csrw medeleg, x9
+
+          csrr x16, mideleg
+          li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
+          csrw mideleg, x9
+        """
+
+        f.write(lines)
+
+        for fromMode in fromModeOptions:
+          lines = ""
+          
+          # Code to bring us down to supervisor mode
+          if fromMode == "s" or fromMode == "u":
+            lines += f"""
+              li x1, 0b110000000000
+              csrrc x31, mstatus, x1
+              li x1, 0b0100000000000
+              csrrs x31, mstatus, x1
+
+              auipc x1, 0
+              addi x1, x1, 16 # x1 is now right after the mret instruction
+              csrw mepc, x1
+              mret
+
+              # We're now in supervisor mode...
+            """
+
+          # Code to bring us down to user mode
+          if fromMode == "u":
+            lines += f"""
+
+            li x1, 0b110000000000
+            csrrc x31, sstatus, x1
+
+            auipc x1, 0
+            addi x1, x1, 16 # x1 is now right after the sret instruction
+            csrw sepc, x1
+            sret
+
+            # We're now in user mode...
+            """
+
+          f.write(lines)
+          for i in range(0,testCount):
+            writeVectors(storecmd, returningInstruction)
+
+
+        # Very end of test. Bring us back up to machine mode
+        # We set x30 to 1, which will cause us to branch to _j_all_end in the
+        # machine mode trap handler, before executing the mret instruction. This will
+        # make us stay in machine mode.
+        #
+        # If we're currently in user mode, this will first bump us up to the supervisor mode
+        # trap handler, which will call returningInstruction again before it's sret instruction,
+        # bumping us up to machine mode
+        #
+        # Get into the trap handler by running returningInstruction (either an ecall or ebreak) 
+        f.write(f"""
+          li x30, 1
+          li gp, 0
+          {returningInstruction}
+          _j_all_end_{returningInstruction}_{vectoredInterrupts}:
+
+          # Reset trap handling csrs to old values
+          csrw mtvec, x19
+          csrw medeleg, x18
+          csrw mideleg, x16
+        """)
+
+    # print footer
+    h = open("../testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
diff --git a/tests/testgen/testgen.py b/tests/testgen/testgen.py
new file mode 100755
index 000000000..c1526356b
--- /dev/null
+++ b/tests/testgen/testgen.py
@@ -0,0 +1,161 @@
+#!/usr/bin/python3
+##################################
+# testgen.py
+#
+# David_Harris@hmc.edu 19 January 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def twoscomp(a, xlen):
+  amsb = a >> (xlen-1)
+  alsbs = ((1 << (xlen-1)) - 1) & a
+  if (amsb):
+      asigned = a - (1<<xlen)
+  else:
+      asigned = a
+  #print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
+  return asigned
+
+def computeExpected(a, b, test, xlen):
+  asigned = twoscomp(a, xlen)
+  bsigned = twoscomp(b, xlen)
+
+  if (test == "ADD"):
+    return a + b
+  elif (test == "SUB"):
+    return a - b
+  elif (test == "SLT"):
+    return asigned < bsigned
+  elif (test == "SLTU"):
+    return a < b
+  elif (test == "XOR"):
+    return a ^ b
+  elif (test == "OR"):
+    return a | b
+  elif (test == "AND"):
+    return a & b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd, xlen):
+  global testnum
+  expected = computeExpected(a, b, test, xlen)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+#  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+tests = ["ADD", "SUB", "SLT", "SLTU", "XOR"]
+author = "David_Harris@hmc.edu & Katherine Parry"
+xlens = [32, 64]
+numrand = 3
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  for test in tests:
+#    corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
+#            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
+    corners = [0, 1, 2**(xlen)-1]
+    pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
+    basename = "WALLY-" + test 
+    fname = pathname + "src/" + basename + ".S"
+    refname = pathname + "references/" + basename + ".reference_output"
+    testnum = 0
+
+    # print custom header part
+    f = open(fname, "w")
+    r = open(refname, "w")
+    line = "///////////////////////////////////////////\n"
+    f.write(line)
+    lines="// "+fname+ "\n// " + author + "\n"
+    f.write(lines)
+    line ="// Created " + str(datetime.now()) 
+    f.write(line)
+
+    # insert generic header
+    h = open("testgen_header.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # print directed and random test vectors
+    for a in corners:
+      for b in corners:
+        writeVector(a, b, storecmd, xlen)
+    for i in range(0,numrand):
+      a = getrandbits(xlen)
+      b = getrandbits(xlen)
+      writeVector(a, b, storecmd, xlen)
+
+
+    # print footer
+    line = "\n.EQU NUMTESTS," + str(testnum) + "\n\n"
+    f.write(line)
+    h = open("testgen_footer.S", "r")
+    for line in h:  
+      f.write(line)
+
+    # Finish
+#    lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+#    lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+    f.write(lines)
+    f.close()
+    r.close()
+
+
+
+
diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S
new file mode 100644
index 000000000..108119436
--- /dev/null
+++ b/tests/testgen/testgen_footer.S
@@ -0,0 +1,30 @@
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S
new file mode 100644
index 000000000..4129782f6
--- /dev/null
+++ b/tests/testgen/testgen_header.S
@@ -0,0 +1,26 @@
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
diff --git a/tests/testgen/virtual_memory_util.py b/tests/testgen/virtual_memory_util.py
new file mode 100644
index 000000000..0aafb3a12
--- /dev/null
+++ b/tests/testgen/virtual_memory_util.py
@@ -0,0 +1,292 @@
+#!/usr/bin/python3
+##################################
+# virtual_memory_util.py
+#
+# Jessica Torrey <jtorrey@hmc.edu>  01 March 2021
+# Thomas Fleming <tfleming@hmc.edu> 01 March 2021
+#
+# Modified kmacsaigoren@hmc.edu 2 June 2021
+#             file now reflects actual use to generate assembly code pagetable.
+#             file now also includes small guide on how it can be used.
+#
+# Utility for generating the pagetable for any test assembly code where virtual memory is needed.
+##################################
+
+######################################################
+""" HOW TO USE THIS FILE
+    
+This is all assuming you are writing code very similar to the WALLY-VIRTUALMEMORY tests and would like your own virtual memory map.
+This guide is also stored in the WALLY-VIRTUALMEMORY.S file as well.
+
+Begin by copying an existing page directory over to your test and running make (it'll be wrong, but we'll fix it in a second).
+  Make may hang or give you an error because the reference outputs may be wrong, but all we're trying to do is get an elf file.
+Simulate the test code on your favorite riscv processor simulator with a debugger that will show you internal state/register values.
+  I used OVPsimPlus with the command 'riscvOVPsimPlus.exe --variant <Variant name, ex: RV64I> --program <path to elf file> --gdbconsole'
+Run through the simulation until it has written to satp and read the bottom 60 bits of it. 
+  Assuming you're a test with the same setup code, this should be the value of the base ppn.
+
+Near the top of the python file you're reading right now, edit the value of 'INITIAL_PPN' to be the base PPN you just found in hex.
+
+Now find the mappings at the very bottom of the python file.
+Each of these loops is adding a mapping from each virtual page in the loop to a physical page somewhere in RAM. 
+
+add or remove mappings as you see fit. the first loop maps VPNs of 0x80000 to 0x80014 onto PPNs of 0x80000 to 0x80014
+  you can map single pages or ranges of pages. you can also map multiple VPNs onto the same PPN.
+  Make sure NOT to include the final VPN that causes the page fault in your test or your program will hang on the j loop instruction (unless you change the end condition).
+
+double check that you're using the right architecture/svmode in the 'arch' variable
+
+then run this python file and paste its output at the bottom of your assembly code. Be sure not to delete the signature fills.
+
+email kmacsaigoren@hmc.edu if you have any questions and he might be able to remember the answers.
+
+*** Currently doesn't work: mapping something with nonzeros in the VPN[3] feild onto any physical aderss. 
+    It'll produce a page table, but writing to those virtual adresses will not correspond to the correctly mapped physical adresses.
+
+    additionally, the expected behaviour doesn't really work when we try to map to a ram afress that starts with something larger than 000000008
+    This could be ebcause of the 32 bit adress space for physical memory.
+
+    remember that these things are broken with this program that generates page tables for test code. it does not say whether the test or module
+    itself works or not.
+*/
+
+"""
+######################################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint, seed, getrandbits
+from textwrap import dedent
+
+##################################
+# global structures
+##################################
+PTE_D = 1 << 7
+PTE_A = 1 << 6
+PTE_G = 1 << 5
+PTE_U = 1 << 4
+PTE_X = 1 << 3
+PTE_W = 1 << 2
+PTE_R = 1 << 1
+PTE_V = 1 << 0
+
+PTE_PTR_MASK = ~(PTE_W | PTE_R | PTE_X)
+
+pgdir = []
+
+pages = {}
+
+
+testcase_num = 0
+signature_len = 2000
+signature = [0xff for _ in range(signature_len)]
+
+# Base PPN, comes after 2 pages of test code and 2 pages of filler signature output space.
+# depending on your test however, this value may be different. You can use OVPsimPlus or QEMU with your testcode to find it. 
+INITIAL_PPN = 0x80005
+
+
+##################################
+# classes
+##################################
+class Architecture:
+  def __init__(self, xlen, svMode):
+    if (xlen == 32):
+      self.PTESIZE = 4 # bytes
+      self.PTE_BITS = 32
+
+      self.VPN_BITS = 20
+      self.VPN_SEGMENT_BITS = 10
+
+      self.PPN_BITS = 22
+
+      self.LEVELS = 2
+    elif (xlen == 64):
+      if (svMode == 39): 
+        self.PTESIZE = 8
+        self.PTE_BITS = 54
+
+        self.VPN_BITS = 27
+        self.VPN_SEGMENT_BITS = 9
+
+        self.PPN_BITS = 44
+
+        self.LEVELS = 3
+      elif (svMode == 48):
+        self.PTESIZE = 8
+        self.PTE_BITS = 54
+
+        self.VPN_BITS = 36
+        self.VPN_SEGMENT_BITS = 9
+
+        self.PPN_BITS = 44
+
+        self.LEVELS = 4
+      else:
+        raise ValueError('Only Sv39 and Sv48 are implemented')
+    else:
+      raise ValueError('Only rv32 and rv64 are allowed.')
+
+    self.PGSIZE = 2**12
+    self.NPTENTRIES = self.PGSIZE // self.PTESIZE
+    self.OFFSET_BITS = 12
+    self.FLAG_BITS = 8
+    self.VA_BITS = self.VPN_BITS + self.OFFSET_BITS
+
+class PageTableEntry:
+  def __init__(self, ppn, flags, arch):
+    assert 0 <= ppn and ppn < 2**arch.PPN_BITS, "Invalid physical page number for PTE"
+    assert 0 <= flags and flags < 2**arch.FLAG_BITS, "Invalid flags for PTE"
+    self.ppn = ppn
+    self.flags = flags
+    self.arch = arch
+
+  def entry(self):
+    return (self.ppn << (self.arch.PTE_BITS - self.arch.PPN_BITS)) | self.flags
+
+  def __str__(self):
+    return "0x{0:0{1}x}".format(self.entry(), self.arch.PTESIZE*2)
+
+  def __repr__(self):
+    return f"<ppn: {hex(self.ppn)}, flags: {self.flags:08b}>"
+
+class PageTable:
+  """
+  Represents a single level of the page table, located at some physical page
+  number `ppn` with symbol `name`, using a specified architecture `arch`.
+  """
+  def __init__(self, name, ppn, arch):
+    self.table = {}
+    self.name = name
+    self.ppn = ppn
+    self.arch = arch
+
+    self.children = 0
+
+    pages[ppn] = self
+
+  def add_entry(self, vpn_segment, ppn, flags):
+    if not (0 <= vpn_segment < 2**self.arch.VPN_SEGMENT_BITS):
+      raise ValueError("Invalid virtual page segment number")
+    self.table[vpn_segment] = PageTableEntry(ppn, flags, self.arch)
+
+  def add_mapping(self, va, pa, flags):
+    """
+    Maps a virtual address `va` to a physical address `pa` with given `flags`,
+    creating missing page table levels as needed.
+    """
+    if not (0 <= va < 2**self.arch.VA_BITS):
+      raise ValueError("Invalid virtual page number")
+
+    vpn = virtual_to_vpn(va, self.arch)
+    ppn = pa >> self.arch.OFFSET_BITS
+    current_level = self
+
+    pathname = self.name
+
+    for level in range(self.arch.LEVELS - 1, -1, -1):
+      if level == 0:
+        current_level.add_entry(vpn[level], ppn, flags)
+      elif vpn[level] in current_level.table:
+        current_level = pages[current_level.table[vpn[level]].ppn]
+        pathname += f"_{current_level.name}"
+      else:
+        next_level_ppn = next_ppn()
+        current_level.add_entry(vpn[level], next_level_ppn, flags & PTE_PTR_MASK)
+        pathname += f"_t{current_level.children}"
+        current_level.children += 1
+        pages[next_level_ppn] = PageTable(pathname, next_level_ppn, self.arch)
+        current_level = pages[next_level_ppn]
+
+  def assembly(self):
+    # Sort the page table
+    entries = list(sorted(self.table.items(), key=lambda item: item[0]))
+    current_index = 0
+
+    # Align the table
+    asm = f".balign {self.arch.PGSIZE}\n{self.name}:\n"
+    for entry in entries:
+      vpn_index, pte = entry
+      if current_index < vpn_index:
+        asm += f"  .fill {vpn_index - current_index}, {self.arch.PTESIZE}, 0\n"
+      asm += f"  .{self.arch.PTESIZE}byte {str(pte)}\n"
+      current_index = vpn_index + 1
+    if current_index < self.arch.NPTENTRIES:
+      asm += f"  .fill {self.arch.NPTENTRIES - current_index}, {self.arch.PTESIZE}, 0\n"
+    return asm
+  
+  def __str__(self):
+    return self.assembly()
+
+  def __repr__(self):
+    return f"<table: {self.table}>"
+
+
+##################################
+# functions
+##################################
+
+def virtual_to_vpn(vaddr, arch):
+  if not (0 <= vaddr < 2**arch.VA_BITS):
+    raise ValueError("Invalid physical address")
+
+  page_number = [0 for _ in range(arch.LEVELS)]
+
+  vaddr = vaddr >> arch.OFFSET_BITS
+  mask = 2**arch.VPN_SEGMENT_BITS - 1
+  for level in range(arch.LEVELS):
+    page_number[level] = vaddr & mask
+    vaddr = vaddr >> arch.VPN_SEGMENT_BITS
+
+  return page_number
+
+next_free_ppn = INITIAL_PPN
+def next_ppn():
+  global next_free_ppn
+  ppn = next_free_ppn
+  next_free_ppn += 1
+  return ppn
+
+def print_pages():
+  for page in pages:
+    print(pages[page])
+
+##################################
+# helper variables
+##################################
+sv32 = Architecture(32, 32)
+sv39 = Architecture(64, 39)
+sv48 = Architecture(64, 48)
+
+if __name__ == "__main__":
+  arch = sv39
+  pgdir = PageTable("page_directory", next_ppn(), arch)
+
+  # Directly map the first 20 pages of RAM
+  for page in range(20):
+    vaddr = 0x80000000 + (arch.PGSIZE * page)
+    paddr = 0x80000000 + (arch.PGSIZE * page)
+    pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
+
+  # Map Vpn of of the offset below and the 20 pages after it mapped onto the same 20 pages of ram.
+  # the first two of these are also the location of the output for each test.
+  for page in range(40):
+    vaddr = 0x00000000 + (arch.PGSIZE * page)
+    paddr = 0x80000000 + (arch.PGSIZE * page)
+    if page >= 20:
+      pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | 0) # gives me an invalid mapping where I can try to store/read to force a page fault.
+    else:
+      pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
+
+
+  """
+  supervisor_pgdir = PageTable("sdir", next_ppn(), rv64)
+  supervisor_pgdir.add_mapping(0x80000000, 0x80000000, PTE_R | PTE_W | PTE_X)
+  supervisor_pgdir.add_mapping(0x80000001, 0x80000001, PTE_R | PTE_W | PTE_X)
+  supervisor_pgdir.add_mapping(0x80001000, 0x80000000, PTE_R | PTE_W | PTE_X)
+  supervisor_pgdir.add_mapping(0xffff0000, 0x80000000, PTE_R | PTE_W | PTE_X)
+  """
+
+  print_pages()
diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile
new file mode 100644
index 000000000..168f03c3c
--- /dev/null
+++ b/tests/wally-riscv-arch-test/Makefile
@@ -0,0 +1,123 @@
+#
+# Ensure the compiler and necessary executables are on the search PATH
+#
+
+#
+# Ensure you have set the following Variables
+#
+#
+export ROOTDIR    = $(shell pwd)
+export WORK      ?= $(ROOTDIR)/work
+
+include Makefile.include
+
+pipe:= |
+empty:=
+comma:= ,
+space:= $(empty) $(empty)
+
+RISCV_ISA_ALL = $(shell ls $(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m)
+RISCV_ISA_OPT = $(subst $(space),$(pipe),$(RISCV_ISA_ALL))
+
+RISCV_ISA_ALL := $(filter-out Makefile.include,$(RISCV_ISA_ALL))
+
+ifeq ($(RISCV_DEVICE),)
+    RISCV_DEVICE = I
+    DEFAULT_TARGET=all_variant
+else
+    DEFAULT_TARGET=variant
+endif
+export SUITEDIR   = $(ROOTDIR)/riscv-test-suite/rv$(XLEN)i_m/$(RISCV_DEVICE)
+
+$(info )
+$(info ============================ VARIABLE INFO ==================================)
+$(info ROOTDIR: ${ROOTDIR} [origin: $(origin ROOTDIR)])
+$(info WORK: ${WORK} [origin: $(origin WORK)])
+$(info TARGETDIR: ${TARGETDIR} [origin: $(origin TARGETDIR)])
+$(info RISCV_TARGET: ${RISCV_TARGET} [origin: $(origin RISCV_TARGET)])
+$(info XLEN: ${XLEN} [origin: $(origin XLEN)])
+$(info RISCV_DEVICE: ${RISCV_DEVICE} [origin: $(origin RISCV_DEVICE)])
+$(info =============================================================================)
+$(info )
+
+RVTEST_DEFINES = 
+ifeq ($(RISCV_ASSERT),1)
+	RVTEST_DEFINES += -DRVMODEL_ASSERT
+endif
+export RVTEST_DEFINES
+
+VERBOSE ?= 0
+ifeq ($(VERBOSE),1)
+    export V=
+    export REDIR1 =
+    export REDIR2 =
+else
+    export V=@
+    export REDIR1 = 1>/dev/null
+    export REDIR2 = 2>/dev/null
+endif
+
+default: $(DEFAULT_TARGET)
+
+variant: compile simulate verify
+
+all_variant:
+	@for isa in $(RISCV_ISA_ALL); do \
+		$(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa variant; \
+			rc=$$?; \
+			if [ $$rc -ne 0 ]; then \
+				exit $$rc; \
+			fi \
+	done
+
+build: compile
+run: simulate
+clean_all: clean
+
+compile:
+	$(MAKE) $(JOBS) \
+		RISCV_TARGET=$(RISCV_TARGET) \
+		RISCV_DEVICE=$(RISCV_DEVICE) \
+		compile -C $(SUITEDIR)
+
+simulate:
+	$(MAKE) $(JOBS) \
+		RISCV_TARGET=$(RISCV_TARGET) \
+		RISCV_DEVICE=$(RISCV_DEVICE) \
+		run -C $(SUITEDIR)
+
+verify: simulate
+	riscv-test-env/verify.sh
+
+postverify:
+ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
+	$(info No post verify script found $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh)
+else
+	$(TARGETDIR)/$(RISCV_TARGET)/postverify.sh
+endif
+
+clean:
+	$(MAKE) $(JOBS) \
+		RISCV_TARGET=$(RISCV_TARGET) \
+		RISCV_DEVICE=$(RISCV_DEVICE) \
+		clean -C $(SUITEDIR)
+
+help:
+	@echo "RISC-V Architectural Tests"
+	@echo ""
+	@echo "  Makefile Environment Variables to be set per Target"
+	@echo "     -- TARGETDIR='<directory containing the target folder>'"
+	@echo "     -- XLEN='<make supported xlen>'"
+	@echo "     -- RISCV_TARGET='<name of target>'"
+	@echo "     -- RISCV_TARGET_FLAGS='<any flags to be passed to target>'"
+	@echo "     -- RISCV_DEVICE='$(RISCV_ISA_OPT)' [ leave empty to run all devices ]"
+	@echo "     -- RISCV_TEST='<name of the test. eg. I-ADD-01'"
+	@echo "    "
+	@echo "  Makefile targets available"
+	@echo "     -- build: To compile all the tests within the RISCV_DEVICE suite and generate the elfs. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
+	@echo "     -- run: To run compiled tests on the target model and generate signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
+	@echo "     -- verify: To verify if the generated signatures match the corresponding reference signatures. Note this will default to running on the I extension alone if RISCV_DEVICE is empty"
+	@echo "     -- postverify: To run post verification processing for a target, for example with this, riscvOVPsim runs instructional functional coverage on the tests"
+	@echo "     -- clean : removes the working directory from the root folder and also from the respective device folders of the target"
+	@echo "     -- default: build, run, and verify on all devices enabled"
+
diff --git a/tests/wally-riscv-arch-test/Makefile.include b/tests/wally-riscv-arch-test/Makefile.include
new file mode 100644
index 000000000..001fd1623
--- /dev/null
+++ b/tests/wally-riscv-arch-test/Makefile.include
@@ -0,0 +1,27 @@
+# set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
+export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target
+
+export RISCV_PREFIX = riscv64-unknown-elf-
+
+# set XLEN to max supported XLEN. Allowed values are 32 and 64
+export XLEN 							?= 64
+
+# name of the target. Note a folder of the same name must exist in the TARGETDIR directory
+export RISCV_TARGET       ?= spike
+
+# set the RISCV_DEVICE environment to a single extension you want to compile, simulate and/or verify. 
+# Leave this blank if you want to iterate through all the supported extensions available in the target
+export RISCV_DEVICE       ?= 
+
+# set this to a string which needs to be passed to your target Makefile.include files
+export RISCV_TARGET_FLAGS ?= 
+
+# set this if you want to enable assertions on the test-suites. Currently no tests support
+# assertions.
+export RISCV_ASSERT       ?= 0
+
+# set the number of parallel jobs (along with any other arguments) you would like to execute. Note that the target needs to ensure
+# that no common files across jobs are created/overwritten leading to unknown behavior
+JOBS= -j1
+
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include
new file mode 100644
index 000000000..fe5f14aaa
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include
@@ -0,0 +1,77 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+act_dir := .
+src_dir := $(act_dir)/src
+ref_dir := $(act_dir)/references
+work_dir := $(WORK)
+work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE)
+
+include $(act_dir)/Makefrag
+ifneq ($(RISCV_TEST),)
+	target_tests = $(RISCV_TEST).elf
+	target_tests_nosim = $(empty)
+endif
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+vpath %.S $(act_dir)
+
+INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m/$(RISCV_DEVICE)/Makefile.include
+ifeq ($(wildcard $(INCLUDE)),)
+    $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.)
+endif
+-include $(INCLUDE)
+
+#------------------------------------------------------------
+# Build and run assembly tests
+
+%.log: %.elf
+	$(V) echo "Execute $(@)"
+	$(V) $(RUN_TARGET)
+
+
+define compile_template
+
+$(work_dir_isa)/%.elf: $(src_dir)/%.S
+	$(V) echo "Compile $$(@)"
+	@mkdir -p $$(@D)
+	$(V) $(COMPILE_TARGET)
+
+.PRECIOUS: $(work_dir_isa)/%.elf
+
+endef
+
+target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e))
+target_elf_nosim = $(foreach e,$(addsuffix .elf, $(target_tests_nosim)),$(work_dir_isa)/$(e))
+combined_elf = $(target_elf_nosim) $(target_elf)
+target_log = $(patsubst %.elf,%.log,$(target_elf))
+
+ifdef target_tests_nosim 
+compile: copy 
+# now copy must be performed before compile, 
+# allowing us to copy over outputs if they won't simulate on spike correctly.
+endif
+
+copy:
+	@mkdir -p $(work_dir_isa)
+	$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
+	$(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>)
+	$(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
+	$(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)"
+	$(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done
+
+compile: $(combined_elf)
+run: $(target_log) 
+# note that run doesnt use the combined elf so it doesnt run the nosim tests.
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(work_dir)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h
index fee1e748b..4ae101822 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h
@@ -1,1996 +1,1184 @@
-// -----------
-// Copyright (c) 2020-2023. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-
-
-// This file is divided into the following sections:
-//      RV Arch Test Constants
-//      general test and helper macros, required,  optional, or just useful
-//         _ARGn, SIG[BASE/UPD[_F/ID]],BASEUPD,BIT,LA ,LI,RVTEST_[INIT/SAVE]_GPRS, XCSR_RENAME
-//      RV ARCH Test Interrupt Macros ****FIXME:spec which regs must not be altered
-//      primary macros used by handle: RVTEST_TRAP{_PROLOG/_HANDLER/_EPILOG/SAVEAREA}
-//      required test format spec macros:      RVTEST_{Code/DATA/SIG}{_BEGIN/_END}
-//      macros from Andrew Waterman's risc-v test macros
-//      deprecated macro name aliases, just for migration ease
-
-//  The resulting memory layout of the trap handler is (MACRO_NAME, label [function])
-//****************************************************************
-//  (code section)
-// RVMODEL_BOOT
-//      rvtest_entry_point: [boot code]
-// RVTEST_CODE_BEGIN
-//      rvtest_init:       [TRAP_PROLOG]   (m, ms, or msv)
-//                         [INIT_GPRS]
-//      rvtest_code_begin:
-//*****************************
-//********(body of tests)******
-//*****************************
-// RVTEST_CODE_END
-//      rvtest_code_end:   [*optional* SAVE_GPRS routine]
-//                         [RVTEST_GOTO_MMODE ] **FIXME** this won't work if MMU enabled unless VA=PA
-//      cleanup_epilogs    [TRAP_EPILOG   (m, ms, or msv)] (jump to exit_cleanup)
-//                         [TRAP_HANDLER  (m, ms, or msv)]
-//      exit_cleanup:      [RVMODEL_HALT macro or a branch to it.]
-//
-//--------------------------------this could start a new section--------------------------------
-//  (Data section) - align to 4K boundary
-// RVTEST_DATA_BEGIN
-//**************************************
-//*****(Ld/St test data is here)********
-//**************************************
-//
-//**************************************
-//*****(trap handler data is here)******
-//**************************************
-//
-//    rvtest_trap_sig:   [global trap signature start (shared by all modes) inited to mtrap_sigptr] **FIXME: needs VA=PA
-//    RVTEST_TRAP_SAVEAREA      [handler sv area(m, ms, or msv) temp reg save, CSRs, tramp table, ptrs]
-//      rvtest_data_begin: [input data     (shared by all modes)]
-//    RVTEST_DATA_END
-//      rvtest_data_end:
-//    RVTEST_ROOT_PG_TBL [sets up identity map (VA=PA)
-//      sroot_pg_tbl:   (if smode)
-//      vroot_pg_tbl:   (if hypervisor)
-//--------------------------------this could start a new section--------------------------------
-// RVTEST_SIG_BEGIN
-//    RVMODEL_DATA_BEGIN
-//      rvtest_sig_begin:  [beginning of signature, used by signature dump, can be used by tests]
-//      mtrap_sigptr:      [global trap signature start (shared by all modes)] - defined by tests
-//      gpr_save:          [gpr save area (optional, enabled if rvtest_gpr_save is defined)]
-// RVTEST_SIG_END
-//    rvtest_sig_end:   [global test   end signature (shared by all modes)] (shouldn't matter what RVMODEL_DATA_END does)
-//    RVMODEL_DATA_END
-//--------------------------------end of test--------------------------------
-
-/* The following macros are optional if interrupt tests are enabled (defaulted if not defined):
-        RVMODEL_SET_[M/V/S]_[SW]_INT
-        RVMODEL_CLR_[M/V/S]_[SW/TIMTER/EXT]_INT
-        rvtest_[M/V/S]trap_routine
-        GOTO_[M/S/U]MODE, INSTANTIATE_MODE_MACRO (prolog/handler/epilog/savearea)
-   The following macro is optional, and defaults to fence.i if not defined
-        RVMODEL.FENCEI
-   The following variables are used     if interrupt tests are enabled (defaulted if not defined):
-         NUM_SPECD_INTCAUSES
-   The following variables are optional if exception tests are enabled (defaulted if not defined):
-         DATA_REL_TVAL_MSK     CODE_REL_TVAL_MSK
-   The following variables are optional:
-         rvtest_gpr_save: if defined, stores GPR contents into signature at test end (for debug)
-   The following labels are required and defined by required macros:
-          rvtest_code_begin:   defined by RVTEST_CODE_BEGIN  macro (boot code can precede this)
-          rvtest_code_end:     defined by RVTEST_CODE_END    macro (trap handlers follow this)
-          rvtest_data_begin:   defined by RVTEST_DATA_BEGIN  macro
-          rvtest_data_end:     defined by RVTEST_DATA_END    macro
-          rvtest_sig_begin:    defined by RVTEST_SIG_BEGIN   macro (after  RVMODEL_DATA_BEGIN) defines signature begin
-          rvtest_sig_end:      defined by RVTEST_SIG_END     macro (before RVMODEL_DATA_END)   defines signature end
-          rvtest_Sroot_pg_tbl: defined by RVTEST_PTE_IDENT_MAP macro inside RVTEST_DATA_BEGIN if  Smode implemented
-          rvtest_Vroot_pg_tbl: defined by RVTEST_PTE_IDENT_MAP macro inside RVTEST_DATA_BEGIN if VSmode implemented
-    labels/variables that must be defined by the DUT in model specific macros or #defines
-           mtrap_sigptr:       defined by test if traps are possible, else is defaulted
-*/
-// don't put C-style macros (#define xxx) inside assembly macros; C-style is evaluated before assembly
-
-#include "encoding.h"
-#include "test_macros.h"
-#define RVTEST_ISA(_STR)         //empty macro used by framework
-
-#define T1      x6
-#define T2      x7
-#define T3      x8
-#define T4      x9
-#define T5      x10
-#define T6      x11
-
-#define MIN(a,b) (((a)<(b))?(a):(b))
-#define MAX(a,b) (((a)>(b))?(a):(b))
-#define BIT(addr, bit) (((addr)>>(bit))&1)
-#define MASK (((1<<(XLEN-1))-1) + (1<<(XLEN-1))) // XLEN bits of 1s
-#define MASK_XLEN(val)  val&MASK // shortens 64b values to XLEN when XLEN==32
-
-#define REGWIDTH   (XLEN>>3)     // in units of #bytes
-
-#define WDSZ       32
-#define WDSGN      (       WDSZ  -1)
-#define WDMSK      ( (1 << WDSZ) -1)
-#define SEXT_WRD(x)  ((x & WDMSK) | (-BIT((x), WRDSGN)<< WRDSZ))
-
-#define IMMSZ      12
-#define IMMSGN            (IMMSZ -1)
-#define IMMMSK     ( (1 << IMMSZ)-1)
-#define SEXT_IMM(x)  ((x & IMMMSK) | (-BIT((x), IMMSGN)<< IMMSZ))
-
-#define LIMMSZ     (WDSZ - IMMSZ)
-#define LIMMSGN          (LIMMSZ -1)
-#define LIMMMSK    ( (1 <<LIMMSZ)-1)
-#define SEXT_LIMM(x) ((x &LIMMMSK) | (-BIT((x),LIMMSGN)<<LIMMSZ))
-
-#define WDBYTSZ    (WDSZ >> 3)  // in units of #bytes
-#define WDBYTMSK         (WDBYTSZ-1)
-
-#define ALIGNSZ ((XLEN>>5)+2)   // log2(XLEN): 2,3,4 for XLEN 32,64,128
-#if XLEN>FLEN
-  #define SIGALIGN REGWIDTH
-#else
-  #define SIGALIGN FREGWIDTH
-#endif
-
-#ifndef RVMODEL_MTVEC_ALIGN
-  #define MTVEC_ALIGN 6    // ensure that a trampoline is on a typical cacheline boundary, just in case
-#else
-  #define MTVEC_ALIGN RVMODEL_MTVEC_ALIGN  //Let the model defined value be used for required trap handler alignment based on implemented MTVEC
-#endif
-
-//==============================================================================
-// this section has RV Arch Test Constants, mostly YAML based.
-// It ensures they're defined  & defaulted if necessary)
-//==============================================================================
-
-// set defaults
-#ifndef   NUM_SPECD_INTCAUSES
-  #define NUM_SPECD_INTCAUSES 16
-  #define INT_CAUSE_MSK ((1<<4)-1)
-#endif
-
-        // set defaults
-#ifndef   NUM_SPECD_EXCPTCAUSES
-  #define NUM_SPECD_EXCPTCAUSES 16
-  #define EXCPT_CAUSE_MSK ((1<<4)-1)
-#endif
-
-// set defaults
-#ifndef RVMODEL_CBZ_BLOCKSIZE
-  #define RVMODEL_CBZ_BLOCKSIZE 64
-#endif
-
-// set defaults
-#ifndef RVMODEL_CMO_BLOCKSIZE
-  #define RVMODEL_CMO_BLOCKSIZE 64
-#endif
-
-//==========================================================================================
-// By default, ZIFENCE is defined as nop for the implementation that does not support Zifencei
-// Implementations that support Zifencei may use the fence.i instruction.
-// This only gets executed if xTVEC is not writable to point to the trap trampoline, 
-// and if it isn't writable, the model better have the zifencei extension implemented.
-//==========================================================================================
-
-#ifndef   RVMODEL_FENCEI
-  #ifndef ZIFENCE
-       #define RVMODEL_FENCEI nop                                // make sure ifetches get new code
-  #else                            
-       #define RVMODEL_FENCEI fence.i 
-  #endif
-#endif
-
-#ifndef UNROLLSZ
-  #define UNROLLSZ 5
-#endif
-
-// **Note** that this is different that previous DATA_REL_TVAL_MASK! This is the OR of Code_Rel+Data_Rel
-// if xTVAL is set to zero for some cause, then the corresponding bit in SET_REL_TVAL_MSK should be cleared
-
-#ifndef SET_REL_TVAL_MSK
-#define SET_REL_TVAL_MSK ((1<<CAUSE_MISALIGNED_FETCH | 1<<CAUSE_FETCH_ACCESS                             | 1<<CAUSE_BREAKPOINT   | \
-                           1<<CAUSE_MISALIGNED_LOAD  | 1<<CAUSE_LOAD_ACCESS  | 1<<CAUSE_MISALIGNED_STORE | 1<<CAUSE_STORE_ACCESS | \
-                           1<<CAUSE_FETCH_PAGE_FAULT | 1<<CAUSE_LOAD_PAGE_FAULT                          | 1<<CAUSE_STORE_PAGE_FAULT) \
-                        & 0xFFFFFFFF)
-#endif
-#ifndef SET_ABS_TVAL_MSK
-#define SET_ABS_TVAL_MSK ((1<<CAUSE_ILLEGAL_INSTRUCTION) & 0xFFFFFFFF)
-#endif
-
-#ifndef GOTO_M_OP
-    #define GOTO_M_OP   ecall
-#endif
-
-//this is a valid global pte entry with all permissions. IF at the root entry, it forms an identity map.
-#define RVTEST_PTE_IDENT_MAP  .fill   4096/REGWIDTH, REGWIDTH, (PTE_G | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
-#define RVTEST_PTE_NOACC_MAP  .fill   4096/REGWIDTH, REGWIDTH, (PTE_G | PTE_U )
-
-//_ADDR_SZ_ is a global variable extracted from YAML; set a default if it isn't defined
-// This should be the MAX(phy_addr_size, VADDR_SZ) from YAML, where VADDR_SZ is derived from SATP.mode at reset
-#ifndef _ADDR_SZ_
-  #if XLEN==64
-    #define _ADDR_SZ_ 57
-  #else
-    #define _ADDR_SZ_ 32
-  #endif
-#endif
-
-// define a bunch of XLEN dependent constants
-#if   XLEN==32
-    #define SREG sw
-    #define LREG lw
-    #define XLEN_WIDTH 5
-    #define LREGWU lw
-#elif XLEN==64
-    #define SREG sd
-    #define LREG ld
-    #define XLEN_WIDTH 6
-    #define LREGWU lwu
-#else
-    #define SREG sq
-    #define LREG lq
-    #define XLEN_WIDTH 7
-#endif
-
-#if FLEN==32
-    #define FLREG flw
-    #define FSREG fsw
-    #define FREGWIDTH 4
-#elif FLEN==64
-    #define FLREG fld
-    #define FSREG fsd
-    #define FREGWIDTH 8
-#else
-    #define FLREG flq
-    #define FSREG fsq
-    #define FREGWIDTH 16
-#endif
-
-
-#if SIGALIGN==8
-  #define CANARY \
-      .dword 0x6F5CA309E7D4B281
-#else
-  #define CANARY \
-      .word 0x6F5CA309 
-#endif
-
-//---------------------------mode encoding definitions-----------------------------
-.set MMODE_SIG, 3
-.set SMODE_SIG, 1
-.set VMODE_SIG, 2
-        /* these macros need to be defined because mode is uppercase in mode specific macros */
-        /* note that vs mode uses smode return */
-
-#define GVA_LSB    6    //bit pos of LSB of the hstatus.GVA  field
-#define MPP_LSB   11    //bit pos of LSB of the mstatus.MPP  field
-#define MPRV_LSB  17    //bit pos of LSB of the mstatus.MPRV field
-#define MPV_LSB    7    // bit pos of prev vmod mstatush.MPV in either mstatush or mstatus upper
-#define MPP_SMODE (1<<MPP_LSB)
-//define sizes
-#define actual_tramp_sz ((XLEN + 3* NUM_SPECD_INTCAUSES + 5) * 4)     // 5 is added ops before common entry pt
-#define tramp_sz        ((actual_tramp_sz+4) & -8)                    // round up to keep aligment for sv area alloc
-#define ptr_sv_sz       (16*8)
-#define reg_sv_sz       ( 8*REGWIDTH)
-#define sv_area_sz      (tramp_sz + ptr_sv_sz + reg_sv_sz)           // force dblword alignment
-#define int_hndlr_tblsz (XLEN*2*WDBYTSZ)
-/*
-//#define sv_area_sz      (Msv_area_end-Mtramptbl_sv)           //sv_area start with aligned tramp_tbl
-//#define tramp_sz        (((common_Mentry-Mtrampoline)+4)& -8) // #ops from Mend..Mentry, forced to dblword size
-*/
-//define a fixed offsets into the save area
-#define tramp_sv_off                  ( 0*8)  // (Mtramptbl_sv    -Mtrapreg_sv) algned to dblwd
-
-#define code_bgn_off         (tramp_sz+ 0*8)  // (Mcode_bgn_ptr   -Mtrapreg_sv)
-#define code_seg_siz         (tramp_sz+ 1*8)  // (Mcode_seg_siz   -Mtrapreg_sv)
-#define data_bgn_off         (tramp_sz+ 2*8)  // (Mdata_bgn_ptr   -Mtrapreg_sv) <--update on mapping chg
-#define data_seg_siz         (tramp_sz+ 3*8)  // (Mdata_seg_siz   -Mtrapreg_sv)
-#define sig_bgn_off          (tramp_sz+ 4*8)  // ( Msig_bgn_ptr   -Mtrapreg_sv) <--update on mapping chg
-#define sig_seg_siz          (tramp_sz+ 5*8)  // ( Msig_seg_siz   -Mtrapreg_sv)
-#define vmem_bgn_off         (tramp_sz+ 6*8)  // (Mvmem_bgn_ptr   -Mtrapreg_sv) <--update on mapping chg
-#define vmem_seg_siz         (tramp_sz+ 7*8)  // (Mvmem_seg_siz   -Mtrapreg_sv)
-
-#define mpp_sv_off (sv_area_sz+tramp_sz+8*8)  //  (Strap_sig      -Mtrapreg_sv)
-#define trapsig_ptr_off      (tramp_sz+ 8*8)  //  (Mtrap_sig      -Mtrapreg_sv)
-#define xsatp_sv_off         (tramp_sz+ 9*8)  //  (Msatp_sv       -Mtrapreg_sv)
-#define trampend_off         (tramp_sz+10*8)  //  (Mtrampend_sv   -Mtrapreg_sv) 
-#define tentry_addr          (tramp_sz+11*8)  //  (Mtentry_sv     -Mtrapreg_sv) <--update on mapping chg
-#define xedeleg_sv_off       (tramp_sz+12*8)  //  (Medeleg_sv     -Mtrapreg_sv)
-#define xtvec_new_off        (tramp_sz+13*8)  //  (tvec_new       -Mtrapreg_sv)
-#define xtvec_sav_off        (tramp_sz+14*8)  //  (tvec_save      -Mtrapreg_sv)
-#define xscr_save_off        (tramp_sz+15*8)  //  (scratch_save   -Mtrapreg_sv)
-#define trap_sv_off          (tramp_sz+16*8)  //  (trapreg_sv     -Mtrapreg_sv) 8 registers long
-
-//==============================================================================
-// this section has  general test helper macros, required,  optional, or just useful
-//==============================================================================
-
-#define _ARG5(_1ST,_2ND, _3RD,_4TH,_5TH,...) _5TH
-#define _ARG4(_1ST,_2ND, _3RD,_4TH,...) _4TH
-#define _ARG3(_1ST,_2ND, _3RD, ...) _3RD
-#define _ARG2(_1ST,_2ND, ...) _2ND
-#define _ARG1(_1ST,...) _1ST
-#define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0)
-#define RVTEST_CASE(_PNAME,_DSTR,...)
-
-//-----------------------------------------------------------------------
-//Fixed length la, li macros; # of ops is ADDR_SZ dependent, not data dependent
-//-----------------------------------------------------------------------
-
-// this generates a constants using the standard addi or lui/addi sequences
-// but also handles cases that are contiguous bit masks in any position,
-// and also constants handled with the addi/lui/addi but are shifted left
-
-/**** fixed length LI macro ****/
-#if (XLEN<64)
-  #define LI(reg, imm)                                                            ;\
-  .set immx,    (imm & MASK)    /* trim to XLEN (noeffect on RV64)      */      ;\
-  .set absimm,  ((immx^(-BIT(immx,XLEN-1)))&MASK) /* cvt to posnum to simplify code */  ;\
-  .set cry,     (BIT(imm, IMMSGN))                                              ;\
-  .set imm12,   (SEXT_IMM(immx))                                                ;\
-  .if     ((absimm>>IMMSGN)==0) /* fits 12b signed imm (properly sgnext)? */    ;\
-        li   reg, imm12         /* yes, <= 12bit, will be simple li       */    ;\
-  .else                                                                         ;\
-        lui  reg, (((immx>>IMMSZ)+cry) & LIMMMSK) /* <= 32b, use lui/addi */    ;\
-    .if   ((imm&IMMMSK)!=0)     /* but skip this if lower bits are zero   */    ;\
-        addi reg, reg, imm12                                                    ;\
-    .endif                                                                      ;\
-  .endif
-  #else
-#define LI(reg, imm)                                                            ;\
-  .option push                                                                  ;\
-  .option norvc                                                                 ;\
-  .set immx,    (imm & MASK)    /* trim to XLEN (noeffect on RV64)      */      ;\
-/***************** used in loop that detects bitmasks                   */      ;\
-  .set edge1,   1               /* 1st "1" bit pos scanning r to l      */      ;\
-  .set edge2,   0               /* 1st "0" bit pos scanning r to l      */      ;\
-  .set fnd1,    -1              /* found 1st "1" bit pos scanning r to l */     ;\
-  .set fnd2,    -1              /* found 1st "0" bit pos scanning r to l */     ;\
-  .set imme,    ((immx^(-BIT(immx,0     )))&MASK) /* cvt to even, cvt back at end */    ;\
-  .set pos,      0                                                              ;\
-/***************** used in code that checks for 32b immediates          */      ;\
-  .set absimm,  ((immx^(-BIT(immx,XLEN-1)))&MASK) /* cvt to posnum to simplify code */  ;\
-  .set cry,     (BIT(immx, IMMSGN))                                             ;\
-  .set imm12,   (SEXT_IMM(immx))                                                ;\
-/***************** used in code that gnerates bitmasks                  */      ;\
-  .set even,    (1-BIT(imm, 0)) /* imm has at least 1 trailing zero     */      ;\
-  .set cryh,    (BIT(immx, IMMSGN+32))                                          ;\
-/******** loop finding rising/falling edge fm LSB-MSB given even operand ****/  ;\
-  .rept XLEN                                                                    ;\
-    .if     (fnd1<0)            /* looking for first edge?              */      ;\
-      .if (BIT(imme,pos)==1)    /* look for falling edge[pos]           */      ;\
-        .set  edge1,pos         /* fnd falling edge, don’t chk for more */      ;\
-        .set  fnd1,0                                                            ;\
-      .endif                                                                    ;\
-    .elseif (fnd2<0)            /* looking for second edge?             */      ;\
-      .if (BIT(imme,pos)==0)    /* yes, found rising edge[pos]?         */      ;\
-         .set  edge2, pos       /* fnd rising  edge, don’t chk for more */      ;\
-         .set  fnd2,0                                                           ;\
-      .endif                                                                    ;\
-    .endif                                                                      ;\
-    .set    pos,  pos+1         /* keep looking (even if already found) */      ;\
-  .endr                                                                         ;\
-/***************** used in code that generates shifted 32b values       */      ;\
-  .set immxsh, (immx>>edge1)    /* *sh variables only used if positive  */      ;\
-  .set imm12sh,(SEXT_IMM(immxsh))/* look @1st 12b of shifted imm val    */      ;\
-  .set crysh,     (BIT(immxsh, IMMSGN))                                         ;\
-  .set absimmsh, immxsh         /* pos, no inversion needed, just shift */      ;\
-/*******does it fit into std li or lui+li sequence****************************/ ;\
-  .if     ((absimm>>IMMSGN)==0) /* fits 12b signed imm (properly sgnext)? */    ;\
-        li   reg, imm12         /* yes, <= 12bit, will be simple li       */    ;\
-  .elseif ((absimm+ (cry << IMMSZ) >> WDSGN)==0)/*fits 32b sgnimm?(w/ sgnext)?*/;\
-        lui  reg, (((immx>>IMMSZ)+cry) & LIMMMSK) /* <= 32b, use lui/addi */    ;\
-    .if   ((imm&IMMMSK)!=0)     /* but skip this if lower bits are zero   */    ;\
-        addi reg, reg, imm12                                                    ;\
-    .endif                                                                      ;\
- /*********** look for  0->1->0 masks, or inverse sgl/multbit *************/    ;\
-  .elseif ( even && (fnd2<0))           /* only rising  edge, so 111000   */    ;\
-        li      reg, -1                                                         ;\
-        slli    reg, reg, edge1         /* make 111s --> 000s mask        */    ;\
-  .elseif (!even && (fnd2<0))           /* only falling edge, so 000111   */    ;\
-        li      reg, -1                                                         ;\
-        srli    reg, reg, XLEN-edge1    /* make 000s --> 111s mask        */    ;\
-  .elseif (imme == (1<<edge1))          /* check for single bit case      */    ;\
-        li      reg, 1                                                          ;\
-        slli    reg, reg, edge1         /* make 0001000 sgl bit mask      */    ;\
-    .if   (!even)                                                               ;\
-        xori    reg, reg, -1            /* orig odd, cvt to 1110111 mask  */    ;\
-    .endif                                                                      ;\
-  .elseif (imme == ((1<<edge2) - (1<<edge1))) /* chk for multibit case    */    ;\
-        li      reg, -1                                                         ;\
-        srli    reg, reg, XLEN-(edge2-edge1) /* make multibit 1s mask     */    ;\
-        slli    reg, reg, edge1         /* and put it into position       */    ;\
-    .if   (!even)                                                               ;\
-        xori    reg, reg, -1            /* orig odd, cvt to 1110111 mask  */    ;\
-    .endif                                                                      ;\
-  /************** look for 12b or 32b imms with trailing zeroes ***********/    ;\
-  .elseif ((immx==imme)&&((absimmsh>>IMMSGN)==0))/* fits 12b after shift? */    ;\
-        li      reg, imm12sh            /* <= 12bit, will be simple li    */    ;\
-        slli    reg, reg, edge1         /* add trailing zeros             */    ;\
-  .elseif ((immx==imme)&&(((absimmsh>>WDSGN)+crysh)==0)) /* fits 32 <<shft? */  ;\
-        lui     reg, ((immxsh>>IMMSZ)+crysh)&LIMMMSK /* <=32b, use lui/addi */  ;\
-    .if   ((imm12sh&IMMMSK)!=0)         /* but skip this if low bits ==0  */    ;\
-        addi    reg, reg, imm12sh                                               ;\
-    .endif                                                                      ;\
-        slli    reg, reg, edge1         /* add trailing zeros             */    ;\
-  .else                                 /* give up, use fixed 8op sequence*/    ;\
-  /******* TBD add sp case of zero short imms, rmv add/merge shifts  ******/    ;\
-        lui     reg, ((immx>>(XLEN-LIMMSZ))+cryh)&LIMMMSK /* 1st 20b (63:44) */ ;\
-        addi    reg, reg, SEXT_IMM(immx>>32)            /* nxt 12b (43:32) */   ;\
-        slli    reg, reg, 11    /* following are <12b, don't need SEXT     */   ;\
-        addi    reg, reg, (immx>>21) & (IMMMSK>>1)      /* nxt 11b (31:21) */   ;\
-        slli    reg, reg, 11                            /* mk room for 11b */   ;\
-        addi    reg, reg, (immx>>10) & (IMMMSK>>1)      /* nxt 11b (20:10) */   ;\
-        slli    reg, reg, 10                            /* mk room for 10b */   ;\
-    .if   ((imm&(IMMMSK>>2))!=0) /* but skip this if lower bits are zero   */   ;\
-        addi    reg, reg, (immx)     & (IMMMSK>>2)      /* lst 10b (09:00) */   ;\
-    .endif                                                                      ;\
-    .if (XLEN==32)                                                              ;\
-        .warning "Should never get here for RV32"                               ;\
-    .endif                                                                      ;\
- .endif                                                                         ;\
- .option pop
- #endif
-
-/**** fixed length LA macro; alignment and rvc/norvc unknown before execution ****/
-#define LA(reg,val)     ;\
-        .option push    ;\
-        .option rvc     ;\
-        .align UNROLLSZ ;\
-        .option norvc   ;\
-        la reg,val      ;\
-        .align UNROLLSZ ;\
-        .option pop
-
-#define ADDI(dst, src, imm) /* helper*/ ;\
-.if ((imm<=2048) & (imm>=-2048))        ;\
-        addi    dst, src, imm           ;\
-.else                                   ;\
-        LI(     dst, imm)               ;\
-        addi    dst, src, dst           ;\
-.endif
-
-/*****************************************************************/
-/**** initialize regs, just to make sure you catch any errors ****/
-/*****************************************************************/
-
-/* init regs, to ensure you catch any errors */
-.macro RVTEST_INIT_GPRS
-     LI (x1,  (0xFEEDBEADFEEDBEAD & MASK))
-     LI (x2,  (0xFF76DF56FF76DF56 & MASK))
-     LI (x3,  (0x7FBB6FAB7FBB6FAB & MASK))
-     LI (x4,  (0xBFDDB7D5BFDDB7D5 & MASK))
-     LI (x5,  (0xDFEEDBEADFEEDBEA & MASK))
-     LI (x6,  (0x6FF76DF56FF76DF5 & MASK))
-     LI (x7,  (0xB7FBB6FAB7FBB6FA & MASK))
-     LI (x8,  (0x5BFDDB7D5BFDDB7D & MASK))
-     LI (x9,  (0xADFEEDBEADFEEDBE & MASK))
-     LI (x10, (0x56FF76DF56FF76DF & MASK))
-     LI (x11, (0xAB7FBB6FAB7FBB6F & MASK))
-     LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK))
-     LI (x13, (0xEADFEEDBEADFEEDB & MASK))
-     LI (x14, (0xF56FF76DF56FF76D & MASK))
-     LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK))
-   #ifndef RVTEST_E
-     LI (x16, (0x7D5BFDDB7D5BFDDB & MASK))
-     LI (x17, (0xBEADFEEDBEADFEED & MASK))
-     LI (x18, (0xDF56FF76DF56FF76 & MASK))
-     LI (x19, (0x6FAB7FBB6FAB7FBB & MASK))
-     LI (x20, (0xB7D5BFDDB7D5BFDD & MASK))
-     LI (x21, (0xDBEADFEEDBEADFEE & MASK))
-     LI (x22, (0x6DF56FF76DF56FF7 & MASK))
-     LI (x23, (0xB6FAB7FBB6FAB7FB & MASK))
-     LI (x24, (0xDB7D5BFDDB7D5BFD & MASK))
-     LI (x25, (0xEDBEADFEEDBEADFE & MASK))
-     LI (x26, (0x76DF56FF76DF56FF & MASK))
-     LI (x27, (0xBB6FAB7FBB6FAB7F & MASK))
-     LI (x28, (0xDDB7D5BFDDB7D5BF & MASK))
-     LI (x29, (0xEEDBEADFEEDBEADF & MASK))
-     LI (x30, (0xF76DF56FF76DF56F & MASK))
-     LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK))
-   #endif
-.endm
-/******************************************************************************/
-/**** this is a helper macro that conditionally instantiates the macros    ****/
-/**** PROLOG/HANDLER/EPILOG/SAVEAREA depending on test type & mode support ****/
-/******************************************************************************/
-.macro INSTANTIATE_MODE_MACRO MACRO_NAME
- #ifdef rvtest_mtrap_routine
-  \MACRO_NAME M         // actual m-mode prolog/epilog/handler code
-
-        #ifdef rvtest_strap_routine
-      \MACRO_NAME S     // actual s-mode prolog/epilog/handler code
-
-        #ifdef rvtest_vtrap_routine
-          \MACRO_NAME V // actual v-mode prolog/epilog/handler code
-        #endif
-    #endif
- #endif
-.endm
-
-/**************************************************************************/
-/**** this is a helper macro defaulting the int macro if its undefined ****/
-/**** It builds the macro name from arguments prefix,  mode, and type  ****/
-/**** The macro names are RV_MODEL_SET_[M/S/V][SW/TMR,EXT]             ****/
-/****  and                RV_MODEL_CLR_[M/S/V][SW]                     ****/
-/**************************************************************************/
-
-.macro DFLT_INT_MACRO MACRO_NAME
-.set      MACRO_NAME_, \MACRO_NAME
- .ifndef    MACRO_NAME_
-  .warning  "MACRO_NAME_ is not defined by target. Executing this will end test."
-   #define  MACRO_NAME_     j cleanup_epilogs
- .endif
-.endm
-
-/******************************************************************************/
-/**** These macros enable parameterization of trap handlers for each mode  ****/
-/******************************************************************************/
-
- .macro _XCSR_RENAME_V
-  .set CSR_XSTATUS, CSR_VSSTATUS /****FIXME? is the right substitution? ****/
-  .set CSR_XEDELEG, CSR_HEDELEG  /****FIXME? is the right substitution? ****/
-  .set CSR_XIE,     CSR_HIE
-  .set CSR_XIP,     CSR_HIP
-  .set CSR_XCAUSE,  CSR_VSCAUSE
-  .set CSR_XEPC,    CSR_VSEPC
-  .set CSR_XSATP,   CSR_VSATP
-  .set CSR_XSCRATCH,CSR_VSSCRATCH
-  .set CSR_XTVAL,   CSR_VSTVAL
-  .set CSR_XTVEC,   CSR_VSTVEC
-.endm
-
-.macro _XCSR_RENAME_S
-  .set CSR_XSTATUS, CSR_SSTATUS
-  .set CSR_XEDELEG, CSR_SEDELEG
-  .set CSR_XIE,     CSR_SIE
-  .set CSR_XIP,     CSR_SIP
-  .set CSR_XCAUSE,  CSR_SCAUSE
-  .set CSR_XEPC,    CSR_SEPC
-  .set CSR_XSATP,   CSR_SATP
-  .set CSR_XSCRATCH,CSR_SSCRATCH
-  .set CSR_XTVAL,   CSR_STVAL
-  .set CSR_XTVEC,   CSR_STVEC
-.endm
-
-.macro _XCSR_RENAME_M
-  .set CSR_XSTATUS, CSR_MSTATUS
-  .set CSR_XEDELEG, CSR_MEDELEG
-  .set CSR_XIE,     CSR_MIE
-  .set CSR_XIP,     CSR_MIP
-  .set CSR_XCAUSE,  CSR_MCAUSE
-  .set CSR_XEPC,    CSR_MEPC
-  .set CSR_XSATP,   CSR_SATP
-  .set CSR_XSCRATCH,CSR_MSCRATCH
-  .set CSR_XTVAL,   CSR_MTVAL
-  .set CSR_XTVEC,   CSR_MTVEC
-.endm
-
-/******************************************************************************/
-/**** this is a helper macro that creates CSR aliases so code that         ****/
-/**** accesses CSRs when V=1 in different modes can share the code         ****/
-/******************************************************************************/
-
- .macro XCSR_RENAME __MODE__    // enable CSR names to be parameterized, V,S merged
-  .ifc   \__MODE__ , M
-       _XCSR_RENAME_M
-  .endif
-  .ifc   \__MODE__ , S
-       _XCSR_RENAME_S
-  .endif
-  .ifc  \__MODE__ ,  V
-       _XCSR_RENAME_S
-  .endif
-.endm
-
-/******************************************************************************/
-/**** this is a helper macro that creates CSR aliases so code that         ****/
-/**** accesses CSRs when V=1 in different modes can share the code         ****/
-/**** this verasion treats Vmodes separately as opposed to XCSR_RENAME     ****/
-/**** this is used when the using it is run from Mmode                     ****/
-/******************************************************************************/
-
- .macro XCSR_VRENAME __MODE__   // enable CSR names to be parameterized, V,S separate 
-  .ifc   \__MODE__ , M
-       _XCSR_RENAME_M
-  .endif
-  .ifc   \__MODE__ , S
-       _XCSR_RENAME_S
-  .endif
-  .ifc  \__MODE__ ,  V
-       _XCSR_RENAME_V
-  .endif
- .endm
-
-////////////////////////////////////////////////////////////////////////////////////////
-//**** This is a helper macro that saves GPRs. Normally used only inside CODE_END ****//
-//**** Note: this needs a temp scratch register, & there isn't anything that will ****//
-//**** will work, so we always trash some register, determined by macro param     ****//
-//**** NOTE: Only be use for debug! Xregs containing addresses won't be relocated ****//
-////////////////////////////////////////////////////////////////////////////////////////
-
-#define RVTEST_SAVE_GPRSM(_BR, _LBL, ...)               ;\
-        .option push                                    ;\
-        .option norvc                                   ;\
-        .set __SV_MASK__,  -1 /* default to save all */ ;\
-    .if NARG(__VA_ARGS__) == 1                          ;\
-        .set __SV_MASK__,  _ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\
-    .endif                                              ;\
-    .set offset, 0                                      ;\
-    LA(_BR, _LBL)                                       ;\
-    .if (__SV_MASK__ &        (0x2)) == 0x2             ;\
-    RVTEST_SIGUPD(_BR, x1)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &        (0x4)) == 0x4             ;\
-    RVTEST_SIGUPD(_BR, x2)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &        (0x8)) == 0x8             ;\
-    RVTEST_SIGUPD(_BR, x3)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &       (0x10)) == 0x10            ;\
-    RVTEST_SIGUPD(_BR, x4)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &       (0x20)) == 0x20            ;\
-    RVTEST_SIGUPD(_BR, x5)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &       (0x40)) == 0x40            ;\
-    RVTEST_SIGUPD(_BR, x6)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &       (0x80)) == 0x80            ;\
-    RVTEST_SIGUPD(_BR, x7)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &      (0x100)) == 0x100           ;\
-    RVTEST_SIGUPD(_BR, x8)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &      (0x200)) == 0x200           ;\
-    RVTEST_SIGUPD(_BR, x9)                              ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &      (0x400)) == 0x400           ;\
-    RVTEST_SIGUPD(_BR, x10)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &      (0x800)) == 0x800           ;\
-    RVTEST_SIGUPD(_BR, x11)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &     (0x1000)) == 0x1000          ;\
-    RVTEST_SIGUPD(_BR, x12)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &     (0x2000)) == 0x2000          ;\
-    RVTEST_SIGUPD(_BR, x13)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &     (0x4000)) == 0x4000          ;\
-    RVTEST_SIGUPD(_BR, x14)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &     (0x8000)) == 0x8000          ;\
-    RVTEST_SIGUPD(_BR, x15)                             ;\
-    .endif                                              ;\
-#ifndef RVTEST_E                                        ;\
-    .if (__SV_MASK__ &    (0x10000)) == 0x10000         ;\
-    RVTEST_SIGUPD(_BR, x16)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &    (0x20000)) == 0x20000         ;\
-    RVTEST_SIGUPD(_BR, x17)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &    (0x40000)) == 0x40000         ;\
-    RVTEST_SIGUPD(_BR, x18)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &    (0x80000)) == 0x80000         ;\
-    RVTEST_SIGUPD(_BR, x19)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &   (0x100000)) == 0x100000        ;\
-    RVTEST_SIGUPD(_BR, x20)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &   (0x200000)) == 0x200000        ;\
-    RVTEST_SIGUPD(_BR, x21)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &   (0x400000)) == 0x400000        ;\
-    RVTEST_SIGUPD(_BR, x22)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &   (0x800000)) == 0x800000        ;\
-    RVTEST_SIGUPD(_BR, x23)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &  (0x1000000)) == 0x1000000       ;\
-    RVTEST_SIGUPD(_BR, x24)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &  (0x2000000)) == 0x2000000       ;\
-    RVTEST_SIGUPD(_BR, x25)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &  (0x4000000)) == 0x4000000       ;\
-    RVTEST_SIGUPD(_BR, x26)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ &  (0x8000000)) == 0x8000000       ;\
-    RVTEST_SIGUPD(_BR, x27)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ & (0x10000000)) == 0x10000000      ;\
-    RVTEST_SIGUPD(_BR, x28)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ & (0x20000000)) == 0x20000000      ;\
-    RVTEST_SIGUPD(_BR, x29)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ & (0x40000000)) == 0x40000000      ;\
-    RVTEST_SIGUPD(_BR, x30)                             ;\
-    .endif                                              ;\
-    .if (__SV_MASK__ & (0x80000000)) == 0x80000000      ;\
-    RVTEST_SIGUPD(_BR, x31)                             ;\
-    .endif                                              ;\
-    .option pop                                         ;\
-#endif
-
-/********************* REQUIRED FOR NEW TESTS *************************/
-/**** new macro encapsulating RVMODEL_DATA_BEGIN (signature area)  ****/
-/**** defining rvtest_sig_begin: label to enabling direct stores   ****/
-/**** into the signature area to be properly relocated             ****/
-/**********************************************************************/
-#define RVTEST_SIG_BEGIN                                                  ;\
-.global rvtest_sig_begin        /* defines beginning of signature area */ ;\
-    RVMODEL_DATA_BEGIN          /* model specific stuff                */ ;\
-sig_begin_canary:                                                         ;\
-CANARY                                                                    ;\
-rvtest_sig_begin:
-
-// Tests allocate normal signature space here, then define
-// the mtrap_sigptr: label to separate normal and trap
-// signature space, then allocate trap signature space
-
-/********************* REQUIRED FOR NEW TESTS *************************/
-/**** new macro definong start of trap signature area              ****/
-/**** defining rvtest_sig_end: label to enabling direct stores     ****/
-/**** into the signature area to be properLY relocated             ****/
-/**********************************************************************/
-#define RVTEST_TSIG_BEGIN                                                ;\
-.global rvtest_tsig_begin     /* defines beginning of trap sig area   */ ;\
-                                                                         ;\
-tsig_begin_canary:                                                       ;\
-   CANARY                                                                ;\
-   mtrap_sigptr:        .fill 3*(XLEN/32),4,0xdeadbeef                   ;\
-   tsig_end_canary:                                                      ;\
-   CANARY
-
-/********************* REQUIRED FOR NEW TESTS *************************/
-/**** new macro encapsulating RVMODEL_SIG_END (signature area)     ****/
-/**** defining rvtest_sig_end: label to enabling direct stores     ****/
-/**** into the signature area to be properLY relocated             ****/
-/**********************************************************************/
-#define RVTEST_SIG_END                                                   ;\
-.global rvtest_sig_end  /* defines beginning of trap sig area         */ ;\
-                                                                         ;\
-#ifdef rvtest_gpr_save                                                   ;\
-gpr_save:                                                                ;\
-  .fill 32*(XLEN/32),4,0xdeadbeef                                        ;\
-#endif                                                                   ;\
-                                                                         ;\
-sig_end_canary:                                                          ;\
-  CANARY                                                                 ;\
-  CANARY                /* add one extra word of guardband            */ ;\
-rvtest_sig_end:                                                          ;\
-RVMODEL_DATA_END        /* model specific stuff */
-
-
-/***********************************************************************************/
-/**** At end of test, this code is entered. It sets a register x2 to 0 and by   ****/
-/**** default executes an ecall.  The handler checks if the cause of the trap   ****/   
-/**** was ecall, w/ x2=0, and divert a special rtn_fm_mmode handler. That code  ****/
-/**** determines the caller's mode, uses it to select it's CODE_BEGIN, and uses ****/
-/**** to calculate it offset from Mmode's CODE_BEGIN, adjusts MEPC by that amt  ****/   
-/**** to convert it to an Mmode address, restores saved regs, and branches to   ****/
-/**** the relocated addr+4, immediately following the ECALL, but now in Mmode   ****/
-/**** **NOTE**: this destroys T2 and clears x2 (AKA sp)                                               ****/
-/**** **NOTE**: this works from any mode but MUST not be used if                ****/
-/****       medeleg[<GOTO_M_OP_cause>]==1 to prevent infinite delegation loops.   ****/
-/**** **NOTE: tests that set medeleg[GOTO_M_OP_cause] must replace  GOTO_M_OP   ****/
-/****  with an op that causes a different exception cause that isn't delegated. ****/
-/***********************************************************************************/
-
-.macro  RVTEST_GOTO_MMODE
-.option push
-.option norvc
-#ifdef  rvtest_mtrap_routine    /**** this can be empty if no Umode ****/
-    li   x2, 0                  /* Ecall w/x2=0 is handled specially to rtn here */
-// Note that if illegal op trap is delegated , this may infinite loop
-// The solution is either for test to disable delegation, or to
-// redefine the GOTO_M_OP to be an op that will trap  to mmode
-
-    GOTO_M_OP                   /* ECALL: traps always, but returns immediately to */
-                                /* the next op if x2=0, else handles trap normally */
-
- #endif
-.option pop
-.endm
-
-
-/**** This is a helper macro that causes harts to transition from    ****/
-/**** M-mode to a lower priv mode at the instruction that follows    ****/
-/**** the macro invocation. Legal params are VS,HS,VU,HU,S,U.        ****/
-/**** The H,U variations leave V unchanged. This uses T4 only.       ****/
-/**** NOTE: this MUST be executed in M-mode. Precede with GOTO_MMODE ****/
-/**** FIXME - SATP & VSATP must point to the identity map page table ****/
-
-#define HSmode  0x9
-#define HUmode  0x8
-#define VUmode  0x4
-#define VSmode  0x5
-#define Smode   0x1
-#define Umode   0x0
-
-.macro RVTEST_GOTO_LOWER_MODE LMODE
-.option push
-.option norvc
-
-        // first, clear MSTATUS.PP (and .MPV if it will be changed_
-        // then set them to the values that represent the lower mode
-#if (XLEN==32)
-   .if     ((\LMODE\()==VUmode) | (\LMODE\()==VSmode))
-     csrsi CSR_MSTATUS, MSTATUS_MPV     /* set V                        */
-   .elseif ((\LMODE\()==HUmode) | (\LMODE\()==HSmode))
-     csrci CSR_MSTATUS, MSTATUS_MPV     /* clr V                        */
-   .endif                               /* lv  V unchged for S or U     */
-
-  LI(    T4, MSTATUS_MPP)
-  csrc   CSR_MSTATUS, T4                /* clr PP always                */
-
-  .if    ((\LMODE\()==VSmode) || (\LMODE\()==HSmode) || (\LMODE\()==Smode))
-    LI(  T4, MPP_SMODE)                 /* val for Smode                */
-    csrs CSR_MSTATUS, T4                /* set in PP                    */
-  .endif
-        // do the same if XLEN=64
-#else                           /* XLEN=64, maybe 128? FIXME for 128    */
-  .if ((\LMODE\()==Smode) || (\LMODE\()==Umode)) /* lv V unchanged here  */
-    LI(  T4,  MSTATUS_MPP)      /* but always clear PP                  */
-  .else
-    LI(  T4, (MSTATUS_MPP | MSTATUS_MPV))       /* clr V and P          */
-  .endif
-  csrc   CSR_MSTATUS, T4        /* clr PP to umode & maybe Vmode        */
-
-  .if (!((\LMODE\()==HUmode) || (\LMODE\()==Umode)))  /* lv pp unchged, v=0 or unchged   */
-    .if      (\LMODE\()==VSmode)
-      LI(  T4, (MPP_SMODE | MSTATUS_MPV)) /* val for pp & v             */
-    .elseif ((\LMODE\()==HSmode) || (\LMODE\()==Smode))
-      LI(  T4, (MPP_SMODE))     /* val for pp only                      */
-    .else                       /* only VU left; set MPV only           */
-      li   T4, 1                /* optimize for single bit              */
-      slli T4, T4, 32+MPV_LSB   /* val for v only                       */
-    .endif
-    csrs CSR_MSTATUS, T4        /* set correct mode and Vbit            */
-  .endif
-#endif
-  csrr   sp, CSR_MSCRATCH       /* ensure sp points to Mmode datae area */
-        /**** mstatus MPV and PP now set up to desired mode    ****/
-        /**** set MEPC to mret+4; requires relocating the pc   ****/
-.if     (\LMODE\() == Vmode)     // get trapsig_ptr & init val up 2 save areas (M<-S<-V)
-        LREG    T1, code_bgn_off + 2*sv_area_sz(sp)
-.elseif (\LMODE\() == Smode || \LMODE\() == Umode)     // get trapsig_ptr & init val up 1 save areas (M<-S)
-        LREG    T1, code_bgn_off + 1*sv_area_sz(sp)
-.else                            // get trapsig ptr & init val for this Mmode, (M)
-        LREG    T1, code_bgn_off + 0*sv_area_sz(sp)
-.endif
-        LREG    T4, code_bgn_off(sp)
-  sub   T1, T1,T4               /* calc addr delta between this mode (M) and lower mode code */
-  addi  T1, T1, 4*WDBYTSZ       /* bias by # ops after auipc continue executing at mret+4 */
-  auipc T4, 0
-  add   T4, T4, T1              /* calc addr after mret in LMODE's VM   */
-  csrrw T4, CSR_MEPC, T4        /* set rtn addr to mret+4 in LMODE's VM */
-  mret                          /* transition to desired mode           */
-.option pop
-.endm                           // end of RVTEST_GOTO_LOWER_MODE
-
-//==============================================================================
-// Helper macro to set defaults for undefined interrupt set/clear
-// macros. This is used to populated the interrupt vector table.
-// These are only used during interrupt testing, so it is safe to 
-// define them as empty macros if and only if that particular interrupt
-// isn't being tested
-//==============================================================================
-//****************************************************************
-#define RVTEST_DFLT_INT_HNDLR      j cleanup_epilogs
-        //Mmode interrupts
-#ifndef RVMODEL_SET_MSW_INT    
-        //.warning "RVMODEL_SET_MSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_SET_MSW_INT     RVTEST_DFLT_INT_HNDLR   
-#endif
-#ifndef RVMODEL_CLR_MSW_INT
-        //.warning "RVMODEL_CLR_MSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning" 
-        #define  RVMODEL_CLR_MSW_INT     RVTEST_DFLT_INT_HNDLR   
-#endif
-#ifndef RVMODEL_CLR_MTIMER_INT 
-        //.warning "RVMODEL_CLR_MTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning" 
-        #define  RVMODEL_CLR_MTIMER_INT  RVTEST_DFLT_INT_HNDLR   
-#endif
-#ifndef RVMODEL_CLR_MEXT_INT
-        //.warning "RVMODEL_CLR_MEXT_INT   not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_MEXT_INT     RVTEST_DFLT_INT_HNDLR   
-#endif
-//Smode interrupts
-#ifndef RVMODEL_SET_SSW_INT
-        //.warning "RVMODEL_SET_SSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_SET_SSW_INT     RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_SSW_INT
-        //.warning "RVMODEL_CLR_SSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_SSW_INT     RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_STIMER_INT
-        //.warning "RVMODEL_CLR_STIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_STIMER_INT  RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_SEXT_INT
-        //.warning "RVMODEL_CLR_SEXT_INT   not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_SEXT_INT  RVTEST_DFLT_INT_HNDLR
-#endif
-//Vmode interrupts
-#ifndef RVMODEL_SET_VSW_INT
-        //.warning "RVMODEL_SET_VSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_SET_VSW_INT     RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_VSW_INT
-        //.warning "RVMODEL_CLR_VSW_INT    not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_VSW_INT     RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_VTIMER_INT
-        //.warning "RVMODEL_CLR_VTIMER_INT not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_VTIMER_INT  RVTEST_DFLT_INT_HNDLR
-#endif
-#ifndef RVMODEL_CLR_VEXT_INT
-        //.warning "RVMODEL_CLR_VEXT_INT   not defined. Executing this will end test. Define an empty macro to suppress this warning"
-        #define  RVMODEL_CLR_VEXT_INT   RVTEST_DFLT_INT_HNDLR
-#endif
-
-//==============================================================================
-// This section defines macros used by these required macros:
-// RVTEST_TRAP_PROLOG, RVTEST_TRAP_HANDLER, RVTEST_TRAP_EPILOG
-// These are macros instead of inline because they need to be replicated per mode
-// These are passed the privmode as an argument to properly rename labels
-// The helper INSTANTIATE_MODE_MACRO actually handles the replication
-//==============================================================================
-
-.macro  RVTEST_TRAP_PROLOG __MODE__
-.option push
-.option norvc
-  /******************************************************************************/
-  /**** this is a mode-configured version of the prolog, which either saves and */
-  /**** replaces xtvec, or saves and replaces the code located at xtvec if it   */
-  /**** it xtvec isn't arbitrarily writable. If not writable, restore & exit    */
-  /******************************************************************************/
-
-  /******************************************************************************/
-  /****                 Prolog, to be run before any tests                   ****/
-  /****       #include 1 copy of this per mode in rvmodel_boot code?         ****/
-  /**** -------------------------------------------------------------------  ****/
-  /**** if xTVEC isn't completely RW, then we need to change the code at its ****/
-  /**** target. The entire trap trampoline and mtrap handler replaces the    ****/
-  /**** area pointed to by mtvec, after saving its original contents first.  ****/
-  /**** If it isn't possible to fully write that area, restore and fail.     ****/
-  /******************************************************************************/
-
-  // RVTEST_TRAP_PROLOG trap_handler_prolog; enter with T1..T6 available; define specific handler
-  // sp will immediately point to the current mode's save area and must not be touched
-  //NOTE: this is run in M-mode, so can't use aliased S,V CSR names
-
-.global \__MODE__\()trampoline
-//.global mtrap_sigptr
-
-        XCSR_VRENAME \__MODE__          //retarget XCSR names to this modes CSRs, separate V/S copies
-
-        LA(     T1, \__MODE__\()tramptbl_sv)    // get  ptr to save area (will be stored in xSCRATCH)
-//----------------------------------------------------------------------
-init_\__MODE__\()scratch:
-        csrrw   T3, CSR_XSCRATCH, T1    // swap xscratch with save area ptr (will be used by handler)
-        SREG    T3, xscr_save_off(T1)   // save old mscratch in xscratch_save
-//----------------------------------------------------------------------
-init_\__MODE__\()edeleg:
-        li      T2, 0                   // save and clear edeleg so we can exit to Mmode
-.ifc \__MODE__ , V
-        csrrw   T2, CSR_VEDELEG, T2     // special case: VS EDELEG available from Vmode
-.else
-  .ifc \__MODE__ , M
-    #ifdef rvtest_strap_routine
-        csrrw   T2, CSR_XEDELEG, T2     // this handles M  mode save, but only if Smode exists
-    #endif
-  .else
-//FIXME: if N-extension or anything like it is implemented, uncomment the following
-//      csrrw   T2, CSR_XEDELEG, T2     // this handles S mode
-  .endif
-.endif
-        SREG    T2, xedeleg_sv_off(T1)  // now do the save
-//----------------------------------------------------------------------
-init_\__MODE__\()satp:
-.ifnc \__MODE__ , M                      // if S or VS mode **FIXME: fixed offset frm trapreg_sv?
-        LA(     T4, rvtest_\__MODE__\()root_pg_tbl)     // rplc xsatp w/ identity-mapped pg table 
-        srli T4, T4, 12
-      #if (XLEN==32)
-        LI(T3, SATP32_MODE)
-      #else
-        LI(T3, (SATP64_MODE) & (SATP_MODE_SV39 << 60))
-      #endif
-        or      T4, T4, T3
-        csrrw   T4, CSR_XSATP, T4
-        SREG    T4, xsatp_sv_off(T1)
-.endif
-//----------------------------------------------------------------------
-init_\__MODE__\()tvec:
-//        LA(     T4, \__MODE__\()trampoline)     //this is a code-relative pointer
-//        ADDI(   T3, T4, actual_tramp_sz)
-//        SREG    T3, tentry_addr(T1)   // initialize to original common entry point
-        csrr    T3, CSR_XTVEC
-        SREG    T3, xtvec_sav_off(T1)   // save orig mtvec+mode in tvec_save
-        andi    T2, T3, WDBYTMSK        // extract mode bits
-        LREG    T4, tentry_addr(T1)
-        addi    T4, T4, -actual_tramp_sz// load trampoline addr (common entry pt) avoiding an LA()
-        or      T2, T4, T2              // merge .mode & tramp ptr and store to both XTVEC, tvec_new
-        SREG    T2, xtvec_new_off(T1)
-        csrw    CSR_XTVEC, T2           // write xtvec with trap_trampoline+mode, so trap will go to the trampoline
-
-        csrr    T5, CSR_XTVEC           // now read new_mtval back & make sure we could write it
-#ifndef HANDLER_TESTCODE_ONLY
-        beq     T5, T2, rvtest_\__MODE__\()prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue
-#endif
-        csrw    CSR_XTVEC, T3           // xTVEC not completely writable, restore old value & exit if uninitialized
-        beqz    T3, abort\__MODE__\()test
-        SREG    T3, xtvec_new_off(T1)   // else update tvect_new with orig mtvec
-
-  /*****************************************************************/
-  /**** fixed mtvec, can't move it so move trampoline instead   ****/
-  /**** T1=tramp sv, T2=orig tvec, T3=sv end, T4=tramp          ****/
-  /*****************************************************************/
-
-init_\__MODE__\()tramp: /**** copy trampoline at mtvec tgt; T4->T2->T1  T3=end of save ****/
-        andi    T2, T3, ~WDBYTMSK               // calc bgn of orig tramp area by clring mode bits
-        addi    T3, T2, actual_tramp_sz         // calc end of orig tramp area (+4 maybe so bldwd aligned)
-//        addi    T1, T1, tramp_sv_off          // calc bgn of tramp save area <--buggy!!
-//----------------------------------------------------------------------
-        overwt_tt_\__MODE__\()loop:             // now build new tramp table w/ local offsets
-        lw      T6, 0(T2)                       //  move original mtvec target to save area
-        sw      T6, 0(T1)
-        lw      T5, 0(T4)                       //  move traphandler trampoline into orig mtvec target
-        sw      T5, 0(T2)
-        lw      T6, 0(T2)                       // rd it back to make sure it was written
-        bne     T6, T5, endcopy_\__MODE__\()tramp // table isn't fully writable, restore and give up
-#ifdef HANDLER_TESTCODE_ONLY
-        csrr    T5, CSR_XSCRATCH                // load trapreg_sv from scratch
-        addi    T5, T5,256                      // calculate some offset into the save area
-        bgt     T5, T1, endcopy_\__MODE__\()tramp // and pretend if couldnt be written
-#endif
-        addi    T2, T2, WDBYTSZ                    // next tvec  inst. index
-        addi    T1, T1, WDBYTSZ                    // next save  inst. index
-        addi    T4, T4, WDBYTSZ                    // next tramp inst. index
-        bne     T3, T2, overwt_tt_\__MODE__\()loop      // haven't reached end of save area,  loop
-//----------------------------------------------------------------------
-  endcopy_\__MODE__\()tramp:                    // vector table not writeable, restore
-        RVMODEL_FENCEI                          // By default it is defined as nop. See the definition above
-        csrr    T1, CSR_XSCRATCH                // reload trapreg_sv from scratch
-        SREG    T2, trampend_off(T1)            // save copy progress; used to restore orig tramp
-        SREG    T4, tentry_addr(T1)             // this is common entry point address, end of orig trampoline
-        beq     T3,T2, rvtest_\__MODE__\()prolog_done //full loop, don't exit
-abort\__MODE__\()test:
-        LA(     T6, exit_\__MODE__\()cleanup)   // trampoline rplc failure **FIXME:  precalc& put into savearea?
-        jalr    x0, T6                          // this branch may be too far away, so longjmp
-
-rvtest_\__MODE__\()prolog_done:
-
-.option pop
-.endm                                           //end of PROLOG
-/*******************************************************************************/
-/***************                 end of prolog macro                ************/
-/*******************************************************************************/
-
-.macro RVTEST_TRAP_HANDLER __MODE__
-.option push
-.option rvc             // temporarily allow compress to allow c.nop alignment
-.align MTVEC_ALIGN      // ensure that a trampoline is on a model defined or reasonable boundary
-.option pop
-
-  /**********************************************************************/
-  /**** This is the entry point for all x-modetraps, vectored or not.****/
-  /**** xtvec should either point here, or trampoline code does and  ****/
-  /**** trampoline code was copied to whereever xtvec pointed to.    ****/
-  /**** At entry, xscratch will contain a pointer to a scratch area. ****/
-  /**** This is an array of branches at 4B intevals that spreads out ****/
-  /**** to an array of 12B xhandler stubs for specd int causes, and  ****/
-  /**** to a return for anything above that (which causes a mismatch)****/
-  /**********************************************************************/
-
-  XCSR_RENAME \__MODE__                 //retarget XCSR names to this modes CSRs
-
-.global \__MODE__\()trampoline                  // define the label and make it available
-.global common_\__MODE__\()entry
-.option push
-.option norvc
-
-\__MODE__\()trampoline: //****GLOBAL:*****
-   .set  value, 0
-  .rept NUM_SPECD_INTCAUSES                     // located at each possible int vectors
-        j    trap_\__MODE__\()handler+ value    // offset < +/- 1MB
-        .set value, value + 12                  // length of xhandler trampoline spreader code
-  .endr
-
-  .rept XLEN-NUM_SPECD_INTCAUSES                // fill at each impossible entry
-        j rvtest_\__MODE__\()endtest            // end test if this happens
-  .endr
-
-  /*********************************************************************/
-  /**** this is spreader stub array; it saves enough info (sp &     ****/
-  /**** vec-offset) to enable branch to common routine to save rest ****/
-  /*********************************************************************/
-  /**** !!CSR_xSCRATCH is preloaded w/ xtrapreg_sv in init_xscratch:****/
-
- trap_\__MODE__\()handler:                      // on exit sp swapped w/ save ptr, T6 is vector addr
-  .rept NUM_SPECD_INTCAUSES
-        csrrw   sp, CSR_XSCRATCH, sp            // save sp, replace w/trapreg_sv regtmp save ptr
-        SREG    T6, trap_sv_off+6*REGWIDTH(sp)  // save T6 in temp save area offset 6
-        jal     T6, common_\__MODE__\()handler  // jmp to common code, saving vector in T6
-  .endr
-
-   /*********************************************************************/
-  /**** common code for all ints & exceptions, will fork to handle  ****/
-  /**** each separately. The common handler first stores trap mode+ ****/
-  /**** vector, & mcause signatures. Most traps have 4wd sigs, but  ****/
-  /**** sw and timer ints only store 3 of the 4, & some hypervisor  ****/
-  /**** traps will set store 6 ops                                  ****/
-  /**** sig offset Exception    ExtInt       SWInt        TimerInt  ****/
-  /****         0: <---------------------  Vect+mode  ---------->   ****/
-  /****         4: <----------------------  xcause ------------->   ****/
-  /****         8: xepc      <-------------  xip  -------------->   ****/
-  /****        12: tval         IntID   <---- x ---------------->   ****/
-  /****        16: tval2/x * <--------------  x ---------------->   ****/
-  /****        20: tinst/x * <--------------  x ---------------->   ****/
-  /****  *  only loaded for Mmode traps when hypervisor implemented ****/
-  /*********************************************************************/
-  /*   in general, CSRs loaded in T2, addresses into T3                */
-
-        //If we can distinguish between HS and S mode, we can share S and V code.
-        //except for prolog code which needs to initialize CSRs, and the save area
-        //To do this, we need to read one of the CSRs (e.g. xSCRATCH) and compare
-        //it to either Strapreg_sv or Vtrapreg_sv to determine which it is.
-
-common_\__MODE__\()handler:                     // enter with vector addr in T6 (orig T6 is at offset 6*REGWIDTH)
-        SREG    T5, trap_sv_off+5*REGWIDTH(sp)  // x30  save remaining regs, starting with T5
-        csrrw   T5, CSR_XSCRATCH, sp            // restore ptr to reg sv area, and get old sp
-        SREG    T5, trap_sv_off+7*REGWIDTH(sp)  // save old sp
-        LREG    T5, tentry_addr(sp)             //  get the address of the common entry point
-        jr      T5                              // needed if trampoline gets moved elsewhere, else it's effectively a noop
-
-common_\__MODE__\()entry:
-        SREG    T4, trap_sv_off+4*REGWIDTH(sp)  //x29
-        SREG    T3, trap_sv_off+3*REGWIDTH(sp)  //x28
-        SREG    T2, trap_sv_off+2*REGWIDTH(sp)  //x7
-        SREG    T1, trap_sv_off+1*REGWIDTH(sp)  //x6  save other temporaries
-
-//spcl case handling for ECALL in GOTO_MMODE mode,)  ****tests can't use ECALL T2=0****
-spcl_\__MODE__\()2mmode_test:
-        csrr    T5, CSR_XCAUSE
-        addi    T4, T5, -8                      // is cause 8..11? Mmode should avoid ECALL 0
-        andi    T4, T4, -4                      // NOTE: cause 10 is RSVD.  Sail will diverge, but buggy anyway  
-        bnez    T4, \__MODE__\()trapsig_ptr_upd // no, not in special mode, just continue
-        LREG    T2, trap_sv_off+7*REGWIDTH(sp)  // get test x2 (which is sp, which has been saved in the trap_sv area
-        beqz    T2, rtn2mmode                   // spcl code 0 in T2 means spcl ECALL goto_mmode, just rtn after ECALL
-//------pre-update trap_sig pointer so handlers can themselves trap-----
-\__MODE__\()trapsig_ptr_upd:                    // calculate entry size based on int vs. excpt, int type, and h mode
-        li      T2, 4*REGWIDTH                  // standard entry length
-        bgez    T5, \__MODE__\()xcpt_sig_sv     // Keep std length if cause is an exception for now (MSB==0)
-\__MODE__\()int_sig_sv:
-        slli    T3, T5, 1                       // remove MSB, cause<<1
-        addi    T3, T3, -(IRQ_M_TIMER)<<1       // is cause (w/o MSB) an extint or larger? ( (cause<<1) > (8<<1) )?
-        bgez    T3, \__MODE__\()trap_sig_sv     // yes, keep std length
-        li      T2, 3*REGWIDTH                  // no,  its a timer or swint, overrride preinc to 3*regsz
-        j       \__MODE__\()trap_sig_sv
-
- /**********************************************************************/
-  /**** FIXME: could this simply instantiate RVMODEL_HALT instead of ****/
-  /**** branching to it?  might need to instantiate GOTO_MMODE here  ****/
-  /**** to take care of  VM issues that RVMODEL_HALT can't deal with ****/
-  /**********************************************************************/
-
-rvtest_\__MODE__\()endtest:                     // target may be too far away, so longjmp       
-        LA(     T1, rvtest_\__MODE__\()end)     // FIXME: must be identity mapped if its a VA
-        jalr    x0, T1
-
-\__MODE__\()xcpt_sig_sv:
-.ifc \__MODE__ , M                               // exception case, don't adjust if hypervisor mode disabled
-        csrr    T1, CSR_MISA
-        slli    T1, T1, XLEN-8                  // shift H bit into msb
-        bgez    T1, \__MODE__\()trap_sig_sv     // no hypervisor mode, keep std width
-        li      T2, 6*REGWIDTH                  // Hmode implemented &  Mmode trap, override preinc to be 6*regsz
-.endif
-
-\__MODE__\()trap_sig_sv:
-        // This replaces an LA(rvtest_trap_sig) calculating initial_Xtrap_sigptr +
-        // + (Mtrap_sigptr-initial_Mtrap-sigptr) 
-        // The delta between Mmode_sigptr and Xmode_sigptr are constants
-        // Xtrap_sigptr (current priv mode) are in the save area ponted to by sp
-        // ****FIXME - this breaks if the signature area cross a page boundary and the mapping isn't contiguous
-
-        .set sv_area_off, (-0*sv_area_sz)       // get trapsig ptr val offset  for Mmode, (M)
-.ifc \__MODE__ , S
-        .set sv_area_off, (-1*sv_area_sz)       // get trapsig_ptr val  up 1 save areas   (M<-S)
-.else
-  .ifc \__MODE__ , V
-        .set sv_area_off, (-2*sv_area_sz)       // get trapsig ptr val  up 2 save areas,  (M<-S<-V))
-  .endif
-.endif
-//------this should be atomic-------------------------------------
-        LREG    T1, trapsig_ptr_off+sv_area_off(sp)
-        add     T4, T1, T2
-        SREG    T4, trapsig_ptr_off+sv_area_off(sp)
-
-//------end atomic------------------------------------------------
-//  convert mtrap_sigptr to curr_mode trap_sigptr
-        LREG    T3, sig_bgn_off+sv_area_off(sp) // load     Mmode sig begin addr
-        sub     T1, T1, T3                      // cvt to offset from sig begin
-        LREG    T3, sig_bgn_off+          0(sp) // load <currmode>sig begin addr
-        add     T1, T1, T3                      // add offset from sig_begin to curr sig_begin addr
-
-        LREG    T3, xtvec_new_off(sp)           // get pointer to actual tramp table
-//----------------------------------------------------------------
-
-  /*************************************************************************/
-  /****   This first entry has this format.                             ****/
-  /****   The #entries is useful for parsing and is really #bytes/entry ****/
-  /**** +---------------+-----------+----------+------+                 ****/
-  /**** | XLEN-1     16 | 15      6 | 5      2 | 1  0 |                 ****/
-  /**** +---------------+-----------+----------+------+                 ****/
-  /**** |   zeroes      | vector    | #entries | mode |                 ****/
-  /**** +---------------+-----------+----------+------+                 ****/
-  /*************************************************************************/
-
-sv_\__MODE__\()vect:                            // **FIXME?: breaks if tramp crosses pg && MMU enabled
-        sub     T6, T6, T3                      // cvt spreader-addr to vector offset fm top of tramptable 
-        slli    T6, T6, 4                       // make room for 4 bits; vector is 10b max  **FIXME: broken for SV64!)
-        or      T6, T6, T2                      // insert entry size into bits 5:2
-        addi    T6, T6, \__MODE__\()MODE_SIG    // insert mode# into 1:0
-        SREG    T6, 0*REGWIDTH(T1)              // save 1st sig value, (vec-offset, entrysz, trapmode)
-//----------------------------------------------------------------
-sv_\__MODE__\()cause:
-        SREG    T5, 1*REGWIDTH(T1)              // save 2nd sig value, (mcause)
-//----------------------------------------------------------------
-        bltz    T5, common_\__MODE__\()int_handler // split off if this is an interrupt
-
-  /*******************************************************************************/
-  /**** This is exception specific code, storing relative mepc & tval sigs    ****/
-  /**** The mepc sig is relocated by data or code start, depending on whether ****/
-  /**** on whether it's in the data area or not, & restored bumped by 2..6B   ****/
-  /**** depending op alignment so trapped op isn't re-executed                ****/
-  /*******************************************************************************/
-
-common_\__MODE__\()excpt_handler:
-
-  //********************************************************************************
-  // calculate the delta between trap mode and handler mode sv areas & add to sp
-  // This code calculates this table: (H-ext is determined by Vtrap_routine variable
-
-  // +-------+-------+-------+-------+---------+
-  // | Hndlr | vMPP | M.GVA | H-ext | sv area |
-  // | Mode  |  =3  |       |       |  delta  |
-  // +-------+------+-------+-------+---------+
-  // |   M   |   0  |   1   |   1   |   2     |
-  // |   M   |   0  |   0   |   x   |   1     |
-  // |   M   |   1  |   0   |   x   |   0     |
-  // |   M   |   x  |   1   |   0   | illegal |
-  // |   M   |   1  |   1   |   x   | illegal |
-  // +-------+------+-------+-------+---------+
-  // |       |      | H.GVA | H-ext | sv area |
-  // +-------+------+-------+-------+---------+
-  // | S/HS  |   0* |   1   |   1   |   1     |
-  // | S/HS  |   0* |   0   |   1   |   0     |
-  // | S/HS  |   0* |   *   |   0   |   0     |
-  // +-------+------+-------+-------+---------+
-  // |       |      | noGVA | H-ext | sv area |                 |
-  // +-------+------+-------+-------+---------+
-  // |   VS  |   0* |   -   |   1*  |   0     |
-  // +-------+------+-------+-------+---------+
-// where vMPP is
-  // +-------+-------+-------+-------+------+
-  // | Hndlr |       |       | sved  |      |
-  // | Mode  | MPRV  | MPP=3 | MPP=3 | vMPP |
-  // +-------+-------+-------+-------+------+
-  // |   M   |   0   |   1   |   x   |   1  |
-  // |   M   |   0   |   0   |   x   |   0  |
-  // |   M   |   1   |   1   |   0   |   1  |
-  // |   M   |   1   |   1   |   1   |   0  |
-  // |   M   |   1   |   0   |   x   |illegl|
-  // +-------+-------+-------+-------+------+
-  // |S/HS/VS|   0*  |   1*  |   x   |   1  |
-  // +-------+-------+-------+-------+------+
-
-  // * means can't be read, but must or would have value indicated
-  // all other values are illegal
-  // lvs result in T4 to be used during relocation, (so doesn't touch sp)
-  // can use T3, T6 because relocation will overwrite them
-  //********************************************************************************
-        
-        // create an index from these values: vMPP, x.GVA , H-ext
-        // where vMPP = m.PRV ? svedMPP : m.MPP & svedMPP
-        
-  .ifc \__MODE__ ,  M
-        csrr    T6, CSR_MSTATUS
-        LREG    T4, mpp_sv_off(sp)      /* saved MPP, overwritten if MPRV=1     */
-// extract MPRV into bit0. Note that only Mmode cares; all other modes can have garbage
-        slli    T3, T6, XLEN-MPRV_LSB-1 /* put MPRV into sign bit & test        */
-        bge     T3, x0, 1f
-        and     T4, T4, T6              /* MPP=11 if MPRV=0, so AND w/ prevMPP  */
-1:
-        // FIXME: add code here to end test if MPRV=1 & MPP<3
-        // e.g.   rt justify, extract, add mprv, end if <4
-// now convert 2 bit xMPP field into a single bit 2
-        srli    T4, T4, MPP_LSB         /* now cvt MPP (in its natural position)*/
-        andi    T4, T4, 3               /* to a single bit in bit2 iff ==3      */
-        addi    T4, T4, 1
-        andi    T4, T4, 4               
-// extract GVA into bit 1
-    #if (rvtest_vtrap_routine)
-      #if (XLEN==32)
-        csrr    T3, CSR_MSTATUSH        /* get CSR with GVA bit, but only H-ext */
-        srli    T3, T3, GVA_LSB-1       /* reposition RV32 mstatush into bit1   */
-      #else
-        srli    T3, T6, GVA_LSB-1+32    /* reposition RV32 mstatus  into bit1   */
-      #endif
-        andi    T3, T3, 1<<1
-        or      T4, T4, T3              /* extract GVA in bit1, insert into msk */
-// put H-extension implemented into bit 0       
-        ori     T4, T4, 1               /* set LSB if H-ext present             */
-        //****FIXME: this doesn't work if misa.H is RW but set to zero ****/
-    #endif
-// chk for illegal combination
-        LI(     T6, 0x3B)                /*lgl msk(vMPP,GVA,H)= 011,00x,10x=0x3B */
-        srl     T6, T6, T4
-        andi    T6, T6, 1
-        beq     T6, x0, rvtest_\__MODE__\()endtest    /* illegal combination */
-//determine sv offset multiplier
-        LI(     T6, sv_area_sz)
-        andi    T3, T4, 2
-        srli    T3, T3, 1               /* extract GVA & move to bito cases     */
-        srl     T6, T6, T3              /* mul by 2 if GVAelse mul by 1         */ 
-        slli    T3, T4, XLEN-3
-        srai    T3, T3, XLEN-1          /* sg ext vMPP, user it to clr delta    */
-        and     T6, T6, T3
-        
-  .else       // do it again, but from VS or HS mode
-    .ifc \__MODE__ ,  S
-// vMPP cannot be 11 because you it cannot handle at a lower mode than trap mode
-// MPRV cannot be 1  because that only applies to Mmode
-// GVA can only exist if there is H-ext
-      #if rvtest_vtrap_routine
-        LI(     T6, sv_area_sz)
-        csrr    T3, CSR_HSTATUS         /* get CSR with GVA bit, but only H-ext */
-        slli    T3, T3, XLEN-1-GVA_LSB  /* sign extend rt justified GVA bit     */
-        slri    T3, T3, XLEN-1
-        and     T4, T3, T6              /* clr delta if GVA=0                   */
-      #else
-        li      T4,0                    /* clr delta if no H-ext                */
-      #endif
-    .else       // handler is in VS mode, vtrap_routine must be defined, offset must be 0
-        li      T4,0
-    .endif
-  .endif
-
-  //********************************************************************************
-
-vmem_adj_\__MODE__\()epc:
-        add     T4, T4, sp              /* calc address of correct sv_area      */
-        csrr    T2, CSR_XEPC            /* T4 now pts to trapping sv_area mode  */
-
-        LREG    T3, vmem_bgn_off(T4)            // see if epc is in the vmem area
-        LREG    T6, vmem_seg_siz(T4)
-        add     T6, T6, T3                      // construct vmem seg end
-        bgeu    T2, T6, code_adj_\__MODE__\()epc// epc > rvtest_vmem_end, try data adj
-        bgeu    T2, T3,      adj_\__MODE__\()epc// epc >=rvtest_vmem_begin, adj and save
-        
-code_adj_\__MODE__\()epc:
-        LREG    T3, code_bgn_off(T4)            // see if epc is in the code area
-        LREG    T6, code_seg_siz(T4)
-        add     T6, T6, T3                      // construct code seg end
-        bgeu    T2, T6, data_adj_\__MODE__\()epc// epc > rvtest_code_end, try data adj
-        bgeu    T2, T3,      adj_\__MODE__\()epc// epc >=rvtest_code_begin, adj and save
-
-data_adj_\__MODE__\()epc:
-        LREG    T3, data_bgn_off(T4)            // see if epc is in the data area
-        LREG    T6, data_seg_siz(T4)
-        add     T6, T6, T3                      // construct data seg end
-        bgeu    T2, T6, cleanup_epilogs         // mepc > rvtest_code_end,  (outside data seg), abort
-        bltu    T2, T3, cleanup_epilogs         // mepc < rvtest_code_begin (outside data seg), abort
-
-adj_\__MODE__\()epc:
-        sub     T3, T2, T3                      // Offset adjustment
-
-sv_\__MODE__\()epc:
-        SREG    T3, 2*REGWIDTH(T1)      // save 3rd sig value, (rel mepc) into trap sig area
-
-adj_\__MODE__\()epc_rtn:                // adj mepc so there is at least 4B of padding after op
-        andi    T6, T2, ~WDBYTMSK       // adjust mepc to prev 4B alignment (if 2B aligned)
-        addi    T6, T6,  2*WDBYTSZ         // adjust mepc so it skips past op, has padding & 4B aligned
-        csrw    CSR_XEPC, T6            // restore adjusted value, w/ 2,4 or 6B of padding
-
-  /****WARNING needs updating when insts>32b are ratified, only 4 or 6B of padding;
-        for 64b insts,  2B or 4B of padding   ****/
-
-  /******************************************************************************/
-  /* Relocate mtval if it’s an addr (by sig, data or code regions) else by zero */
-  /* error if exception address isn't inside code, data or signature segments   */
-  /* Enter with rvtest_code_begin (which is start of actual test) in T3         */
-  /* FUTURE FIXME: this may need to be updated to handle 48 or 64b opcodes      */
-  /* This uses offset sp in T4 from epc relocation                              */
-  /******************************************************************************/
-
-/**** FIXME: if in Mmode and mode!=bare & MPRV=1, then T4 be altered to point to
-             the mode of the mstatus.mpp that is stored in Xtrampend_sv ****/
-
-        csrr    T2, CSR_XTVAL
-
-chk_\__MODE__\()tval:
-        andi    T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range
-        LI(     T3, SET_REL_TVAL_MSK)   // now check if code or data (or sig) region adjustment
-        srl     T3, T3, T5              // put mcause bit# into LSB
-        slli    T3, T3, XLEN-1          // put mcause bit# into MSB
-        bge     T3, x0, sv_\__MODE__\()tval     // if MSB=0, no adj, sv to ensure tval was cleared
-
-vmem_adj_\__MODE__\()tval:         /* T4 still points to sv area of trapping mode */
-        LREG    T3, vmem_bgn_off(T4)            // fetch sig_begin addr
-        LREG    T6, vmem_seg_siz(T4)
-        add     T6, T6, T3                      // construct vmem seg end
-        bgeu    T2, T6,  sig_adj_\__MODE__\()tval// tval > rvtest_sig_end, chk code seg
-        bgeu    T2, T3,      adj_\__MODE__\()tval// tval >=rvtest_sig_begin, adj & save
-
-sig_adj_\__MODE__\()tval:
-        LREG    T3, sig_bgn_off(T4)            // fetch sig_begin addr
-        LREG    T6, sig_seg_siz(T4)
-        add     T6, T6, T3                      // construct sig seg end
-        bgeu    T2, T6, code_adj_\__MODE__\()tval// tval > rvtest_sig_end, chk code seg
-        bgeu    T2, T3,      adj_\__MODE__\()tval// tval >=rvtest_sig_begin, adj & save
-
-code_adj_\__MODE__\()tval:
-        LREG    T3, code_bgn_off(T4)            // fetch code_begin addr
-        LREG    T6, code_seg_siz(T4)
-        add     T6, T6, T3                      // construct code seg end
-        bgeu    T2, T6, data_adj_\__MODE__\()tval// tval > rvtest_code_end, chk data seg
-        bgeu    T2, T3,      adj_\__MODE__\()tval// tval >=rvtest_code_begin, adj & save
-
-data_adj_\__MODE__\()tval:
-        LREG    T3, data_bgn_off(T4)            // fetch data_begin addr
-        LREG    T6, data_seg_siz(T4)
-        add     T6, T6, T3                      // construct data seg end
-        bgeu    T2, T6, cleanup_epilogs         // tval > rvtest_data_end,  (outside data seg), abort
-        bltu    T2, T3, cleanup_epilogs         // tval < rvtest_data_begin (outside data seg), abort
-
-adj_\__MODE__\()tval:
-        sub     T3, T2, T3              // perform mtval adjust by either code, data, or sig position in T3
-
-sv_\__MODE__\()tval:
-        SREG    T3, 3*REGWIDTH(T1)      // save 4th sig value, (rel tval)
-
-skp_\__MODE__\()tval:
-
-  .ifc \__MODE__ , M
-    .ifdef  __H_EXT__
-        csrr    T2, CSR_MTVAL2          // **** FIXME: does this need reloc also? Its a guest phys addr
-        SREG    T2, 4*REGWIDTH(T1)      // store 5th sig value, only if mmode handler and VS mode exists
-        csrr    T2, CSR_MTINST
-        SREG    T2, 5*REGWIDTH(T1)      // store 6th sig value, only if mmode handler and VS mode exists
-    .endif
-  .endif
-
-chk_\__MODE__\()trapsig_overrun:        // sv_area_off is defined above at Xtrap_sig_sv:
- //This is the same code used at xtrap_sig_sv to get the shared copy of trap signature pointer
-        LREG    T4, sv_area_off+trapsig_ptr_off(sp)
-        LREG    T2, sv_area_off+sig_bgn_off(sp)
-        LREG    T1, sv_area_off+sig_seg_siz(sp)
-
-// now see if the pointer has overrun sig_end
-        add     T1, T1, T2                      // construct segment end address
-        bgtu    T4, T1, cleanup_epilogs         // abort test if pre-incremented value overruns
-
-  /**** vector to exception special handling routines ****/
-        li      T2, int_hndlr_tblsz             // offset of exception dispatch table base
-        j       spcl_\__MODE__\()handler        // jump to shared int/excpt spcl handling dispatcher
-
- /**** common return code for both interrupts and exceptions ****/
-resto_\__MODE__\()rtn:                  // restore and return
-        LREG    T1, trap_sv_off+1*REGWIDTH(sp)
-        LREG    T2, trap_sv_off+2*REGWIDTH(sp)
-        LREG    T3, trap_sv_off+3*REGWIDTH(sp)
-        LREG    T4, trap_sv_off+4*REGWIDTH(sp)
-        LREG    T5, trap_sv_off+5*REGWIDTH(sp)
-        LREG    T6, trap_sv_off+6*REGWIDTH(sp)
-        LREG    sp, trap_sv_off+7*REGWIDTH(sp)      // restore temporaries
-
-        \__MODE__\()RET                 // return to test, after padding adjustment (macro to handle case)
-
- /***************************************************/
- /**** This is the interrupt specific code. It   ****/
- /**** clears the int and saves int-specific CSRS****/
- /***************************************************/
-common_\__MODE__\()int_handler:         // T1 has sig ptr, T5 has mcause, sp has save area
-        li      T3, 1
- //**FIXME** - make sure this is kept up-to-date with fast int extension and others
-        andi    T2, T5, INT_CAUSE_MSK   // clr INT & unarched arched bits (**NOTE expand if future extns use them)
-        sll     T3, T3, T2              // create mask 1<<xcause **NOTE**: that MSB is ignored in shift amt
-        csrrc   T4, CSR_XIE, T3         // read, then attempt to clear int enable bit??
-        csrrc   T4, CSR_XIP, T3         // read, then attempt to clear int pend bit
-sv_\__MODE__\()ip:                      // note: clear has no effect on MxIP
-        SREG    T4, 2*REGWIDTH(T1)      // save 3rd sig value, (xip)
-
-        li      T2, 0                   // index of interrupt dispatch table base
-
-/**************************************************************/
-/**** spcl int/excp dispatcher. T5 has mcause, T2          ****/
-/**** holds int table (0) or excpt tbl (int_tbl_sz) offset ****/
-/**** this loads an entry @ table_base+table_off+mcause<<8 ****/
-/**** if entry=0, it should never be taken, error return   ****/
-/**** if entry is odd, it has cause<<1,  skip disptaching  ****/
-/**** otherwise if even & >0, it is the handler address    ****/
-/**** There is an optional check that cause==mcause        ****/
-/**************************************************************/
-
-spcl_\__MODE__\()handler:               // case table branch to special handler code, depending on mcause
-        auipc   T3, 0                   // shortcut for LA(clrint_\__MODE__\()tbl) (might be 4 too large)
-        addi    T3, T3, 15*4            // shortcut to avoid LA clrint_xtbl - this is might be 4 too large
-        add     T3, T3, T2              // offset into the correct int/excpt dispatch table
-        slli    T2, T5, 3               // index into 8b aligned dispatch entry and jump through it
-        add     T3, T3, T2
-        andi    T3, T3, -8              // make sure this is dblwd aligned, correct if it is 4 too large
-        LREG    T3, 0(T3)
-spcl_\__MODE__\()dispatch_hndling:        
-        beqz    T3, abort_tests         // if address is 0, this is an error, exit test
-        slli    T2, T3, XLEN-1          // look at LSB and dispatch if even
-        bge     T2, x0, spcl_\__MODE__\()dispatch
-        srli    T3, T3,1                //odd entry>0, remove LSB, normalizing to cause range
-        beq     T5, T3, resto_\__MODE__\()rtn // case range matches, not an error, just noop
-        j       abort_tests             //FIXME: this needs to report an error somehow
-        
-spcl_\__MODE__\()dispatch:
-        jr      T3                      // not a default, jump to handler
-
-/**** this is the table of interrupt clearing routine pointers  ****/
-/**** They could include special handlers                       ****/
-/**** They default to model supplied RVMODEL macros above,      ****/
-/**** Note that the external interrupt routines are expected to ****/
-/**** return with an interrupt ID in T3                         ****/
-
-        .align 3                        //make sure this is a dblwd boundary
-clrint_\__MODE__\()tbl:                 //this code should only touch T2..T6
-#ifdef rvtest_vtrap_routine  //  M/S/V/U
-        .dword  0                       // int cause  0 is reserved, error
-        .dword  \__MODE__\()clr_Ssw_int         // int cause  1  Smode SW int
-        .dword  \__MODE__\()clr_Vsw_int         // int cause  2  Vmode SW int
-        .dword  \__MODE__\()clr_Msw_int         // int cause  3  Mmode SW int
-//****************************************************************
-        .dword  0                       // int cause  4 is reserved, error
-        .dword  \__MODE__\()clr_Stmr_int                // int cause  5  Smode Tmr int
-        .dword  \__MODE__\()clr_Vtmr_int                // int cause  6  Vmode Tmr int
-        .dword  \__MODE__\()clr_Mtmr_int                // int cause  7  Mmode Tmr int
-//****************************************************************
-        .dword  0                      // int cause  8 is reserved, error
-        .dword  \__MODE__\()clr_Sext_int                // int cause  9  Smode Ext int
-        .dword  \__MODE__\()clr_Vext_int                // int cause  A  Vmode Ext int
-        .dword  \__MODE__\()clr_Mext_int                // int cause  B  Mmode Ext int
-//****************************************************************
-#elseif rvtest_dtrap_routine  // M/S/U only
-        .dword  0                       // int cause  0 is reserved, error
-        .dword  \__MODE__\()clr_Ssw_int         // int cause  1  Smode SW int
-        .dword  1                       // int cause  2  no Vmode
-        .dword  \__MODE__\()clr_Msw_int         // int cause  3  Mmode SW int
-//****************************************************************
-        .dword  0                       // int cause  4 is reserved, error
-        .dword  \__MODE__\()clr_Stmr_int                // int cause  5  Smode Tmr int
-        .dword  1                       // int cause  6 no vmode
-        .dword  \__MODE__\()clr_Mtmr_int                // int cause  7  Mmode Tmr int
-//****************************************************************
-        .dword  0                                       // int cause  8 is reserved, error
-        .dword  \__MODE__\()clr_Sext_int                // int cause  9  Smode Ext int
-        .dword  1                       // int cause  A no vmode
-        .dword  \__MODE__\()clr_Mext_int                // int cause  B  Mmode Ext int
-//****************************************************************
-#else  // M(/U)mode only
-        .dword  0                       // int cause  0 is reserved, error
-        .dword  1                       // int cause  1  no Smode
-        .dword  1                       // int cause  2  no Vmode
-        .dword  \__MODE__\()clr_Msw_int         // int cause  3  Mmode SW int
-//****************************************************************
-        .dword  0                       // int cause  4 is reserved, error
-        .dword  1                       // int cause  5 no Smode
-        .dword  1                       // int cause  6 no vmode
-        .dword  \__MODE__\()clr_Mtmr_int                // int cause  7  Mmode Tmr int
-//****************************************************************
-        .dword  0                       // int cause  8 is reserved, error
-        .dword  1                       // int cause  9 no Smode
-        .dword  1                       // int cause  A no vmode
-        .dword  \__MODE__\()clr_Mext_int                // int cause  B  Mmode Ext int
-//****************************************************************
-#endif
- .rept NUM_SPECD_INTCAUSES-0xC
-        .dword  1                       // int cause c..NUM_SPECD_INTCAUSES is reserved, just return
- .endr
- .rept XLEN-NUM_SPECD_INTCAUSES
-        .dword  0                       // impossible, quit test by jumping to  epilogs
- .endr
-//****************************************************************
-
-/**** this is the table of exception handling routine pointers, which ****/
-/****  could include special handlers. They default to the rtn code   ****/
-excpt_\__MODE__\()hndlr_tbl:            // handler code should only touch T2..T6 ****<<--must be speced!****
- .set causeidx, 0
- .rept NUM_SPECD_EXCPTCAUSES
-        .dword  causeidx*2+1            // default, marked by @*cause+2just return
-        .set    causeidx, causeidx+1
- .endr
- .rept XLEN-NUM_SPECD_EXCPTCAUSES
-        .dword  0                       // impossible, quit test by jumping to epilogs
- .endr
-
-/**** These are invocations of the model supplied interrupt clearing macros ****/
-/**** Note there is a copy per mode, though they could all be the same code ****/
-/**** !!! Note: These macros should only touch T2..T6, unless test is aware ****/
-/****  of other modified registers and knows they are dead-                 ****/ 
-/****  but T1 must not be modified under any circumstances                  ****/                               
-/**** !!! Note: the ext interrupt clearing macros must leave intID in T3 !!!****/
-// **FIXME** : the spec needs to be updated with the per/mode versions, not just one
-// **FIXME**: move these outside the handler so it can copied per mode using INSTANTIATE_MODE_MACRO
-
-//------------- MMode----------------
-\__MODE__\()clr_Msw_int:                // int 3 default to just return if not defined
-        RVMODEL_CLR_MSW_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Mtmr_int:               // int 7 default to just return
-        RVMODEL_CLR_MTIMER_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Mext_int:               // inT11 default to just return after saving IntID in T3
-        RVMODEL_CLR_MEXT_INT
-        SREG    T3, 3*REGWIDTH(T1)      // save 4rd sig value, (intID)
-        j       resto_\__MODE__\()rtn
-
-//------------- SMode----------------
-\__MODE__\()clr_Ssw_int:                // int 1 default to just return if not defined
-        RVMODEL_CLR_SSW_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Stmr_int:               // int 5 default to just return
-        RVMODEL_CLR_STIMER_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Sext_int:               // int 9 default to just return after saving IntID in T3
-        RVMODEL_CLR_SEXT_INT
-        SREG    T3, 3*REGWIDTH(T1)      // save 4rd sig value, (intID)
-        j       resto_\__MODE__\()rtn
-
-//------------- VSmode----------------
-\__MODE__\()clr_Vsw_int:                // int 2 default to just return if not defined
-        RVMODEL_CLR_VSW_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Vtmr_int:               // int 6 default to just return
-        RVMODEL_CLR_VTIMER_INT
-        j       resto_\__MODE__\()rtn
-
-\__MODE__\()clr_Vext_int:               // int 8 default to just return after saving IntID in T3
-        RVMODEL_CLR_VEXT_INT
-        SREG    T3, 3*REGWIDTH(T1)      // save 4rd sig value, (intID)
-        j       resto_\__MODE__\()rtn
-
-.ifc \__MODE__ , M
-
-/***************  Spcl handler for returning from GOTO_MMODE.            ********/
-/***************  Only gets executed if GOTO_MMODE not called from Mmode ********/
-/***************  Executed in M-mode. Enter w/ T1=ptr to Mregsave, T2=0  ********/
-/***************  NOTE: Ecall must NOT delegate when T2=0 or this fails  ********/
-
-rtn2mmode:
-        addi    T4,T5, -CAUSE_MACHINE_ECALL
-        beqz    T4, rtn_fm_mmode        /* shortcut if called from Mmode        */
-#if (rvtest_vtrap_routine)
-  #if (XLEN==32)
-        csrr    T2, CSR_MSTATUSH        /* find out originating mode if  RV32   */
-  #else
-        csrr    T2, CSR_MSTATUS         /* find out originating mode if RV64/128*/
-  #endif
-        slli    T2, T2, WDSZ-MPV_LSB-1  /* but V into MSB  ****FIXME if RV128   */ 
-#endif
-        LREG    T6, code_bgn_off+1*sv_area_sz(sp)    /* get U/S mode code begin */
-        bgez    T2, from_u_s            /* V==0, not virtualized, *1 offset     */
-from_v:
-        LREG    T6, code_bgn_off+2*sv_area_sz(sp)/* get VU/VS   mode code begin */
-from_u_s:                               /* get u/s modes CODE_BEGIN             */
-        LREG    T4, code_bgn_off+0*sv_area_sz(sp)    /* get M   mode code begin */
-        sub     T4, T4, T6              /* calc relocation amount               */
-rtn_fm_mmode:
-        csrr    T2, CSR_MEPC            /* get return address in orig mode's VM */
-        add     T2, T2, T4              /* calc rtn_addr in Mmode VM            */
-
-        LREG    T1, trap_sv_off+1*REGWIDTH(sp)
- //     LREG    T2, trap_sv_off+2*REGWIDTH(sp) /*this holds the return address  */
-        LREG    T3, trap_sv_off+3*REGWIDTH(sp)
-        LREG    T4, trap_sv_off+4*REGWIDTH(sp)
-        LREG    T5, trap_sv_off+5*REGWIDTH(sp)
-        LREG    T6, trap_sv_off+6*REGWIDTH(sp)
-        LREG    sp, trap_sv_off+7*REGWIDTH(sp)      // restore temporaries
-        jr      4(T2)                   /* return after GOTO_MMODE in M-mode    */
-.endif
-.option pop
-.endm                                   // end of HANDLER
-
-/*******************************************************************************/
-/***************                 end of handler macro               ************/
-/*******************************************************************************/
-/*******************************************************************************/
-/**************** cleanup code; restore xtvec or where it points to ************/
-/********* Assumption: in M-mode, because GOTO_MMODE always ends tests *********/
-/********* Assumption: XSCRATCH pnts to save area for appropriate mode *********/
-/*******************************************************************************/
-
-.macro RVTEST_TRAP_EPILOG __MODE__
-.option push
-.option norvc
-
-        XCSR_VRENAME \__MODE__                  // retarget XCSR names to this modes CSRs, no V/S aiasing
-
-exit_\__MODE__\()cleanup:
-        csrr    T1, mscratch                // pointer to save area
-      .ifc \__MODE__ , S
-        addi T1, T1, 1*sv_area_sz
-      .else
-        .ifc \__MODE__ , V
-           addi T1, T1, 2*sv_area_sz
-        .endif
-      .endif
-
-resto_\__MODE__\()edeleg:
-        LREG    T2, xedeleg_sv_off(T1)          // get saved xedeleg at offset -32
-
-.ifc \__MODE__ , V
-        csrw    CSR_VEDELEG, T2 //special case: VS EDELEG available from Vmode
-.else
-  .ifc \__MODE__ , M
-#ifdef rvtest_strap_routine
-        csrw    CSR_XEDELEG, T2 //this handles M  mode restore, but only if Smode exists
-#endif
-  .else
-//FIXME: if Umode-int-extension or anything like it is implemented, uncomment the following
-//      csrw    CSR_XEDELEG, T2 //this handles S  mode restore
-  .endif
-.endif
-
-.ifnc \__MODE__ , M
-resto_\__MODE__\()satp:
-        LREG    T2, xsatp_sv_off(T1)            // restore saved xsatp
-        csrw    CSR_XSATP,  T2
-.endif
-resto_\__MODE__\()scratch:
-        LREG    T5, xscr_save_off(T1)           // restore saved xscratch
-        csrw    CSR_XSCRATCH, T5
-resto_\__MODE__\()xtvec:
-        LREG    T4, xtvec_sav_off(T1)           // restore  orig xtvec addr & load current one
-        csrrw   T2, CSR_XTVEC, T4
-        andi    T4, T4, ~WDBYTMSK               // remove mode, so both word aligned 
-        andi    T2, T2, ~WDBYTMSK
-        bne     T4, T2, 1f                      // if saved!=curr mtvec, done, else need to restore tramp
-
-resto_\__MODE__\()tramp:                        // T2 now contains where to restore to
-        addi    T4, T1, tramp_sv_off            // T4 now contains where to restore from
-        LREG    T3, trampend_off(T1)            // T3 tracks how much to restore
-
-resto_\__MODE__\()loop:
-        lw      T6, 0(T4)                       // read saved tramp entry
-        sw      T6, 0(T2)                       // restore original tramp entry
-        addi    T2, T2, WDBYTSZ                 // next tgt  index
-        addi    T4, T4, WDBYTSZ                 // next save index
-        blt     T2, T3, resto_\__MODE__\()loop  // didn't get to end, continue
-  1:
-.global rvtest_\__MODE__\()end
-rvtest_\__MODE__\()end:
-
-#ifdef HANDLER_TESTCODE_ONLY
-        //**FIXME**: add conditional code to compare original trampoline with
-        // restored trampoline and store the deltas in the trap signature region
-        // as an added check? must work for each mode
-#endif
- .option pop
- .endm                                          //end of EPILOG
-/*******************************************************************************/
-/**** end epilog cleanup code; should fall from V->S->M into RVMODEL_HALT ******/
-/*******************************************************************************/
-
-/*******************************************************************************/
-/**** This macro defines per/mode save areas for mmode for each mode        ****/
-/**** note that it is the code area, not the data area, and                 ****/
-/**** must be mulitple of 8B, so multiple instantiations stay aligned       ****/
-/**** This is preceded by the current signature pointer, (@Mtrpreg_sv -64?  ****/
-/*******************************************************************************/
-.macro RVTEST_TRAP_SAVEAREA __MODE__
-
-.option push
-.option norvc
-.global \__MODE__\()tramptbl_sv
-
-//****ASSERT: this should be a 64B boundary******//
-\__MODE__\()tramptbl_sv:        // save area of existing trampoline table,     // also stored in XSCRATCH!!!
-.rept (tramp_sz>>2)             // size in words (technically, length of j op) padded to be 8B aligned
-        j       .+0             // prototype jump instruction, offset to be filled in
-.endr
-
-\__MODE__\()code_bgn_ptr:
-        .dword rvtest_code_begin    // ptr to code bgn area using this mode's mapping trampsvend+0*8
-\__MODE__\()code_seg_sz:
-        .dword rvtest_code_end-rvtest_code_begin         // code seg size in any mode trampsvend+1*8
-\__MODE__\()data_bgn_ptr:
-        .dword rvtest_data_begin    // ptr to data bgn area using this mode's mapping trampsvend+2*8
-\__MODE__\()data_seg_sz:
-        .dword rvtest_data_end-rvtest_data_begin         // code seg size in any mode trampsvend+3*8
-\__MODE__\()sig_bgn_ptr:
-        .dword rvtest_sig_begin     // ptr to sig  bgn area using this mode's mapping trampsvend+4*8
-\__MODE__\()sig_seg_sz:
-        .dword rvtest_sig_end-rvtest_sig_begin           // code seg size in any mode trampsvend+5*8
-\__MODE__\()vmem_bgn_ptr:
-        .dword rvtest_code_begin   // default to code bgn area w/ this mode's mapping trampsvend+6*8
-\__MODE__\()vmem_seg_sz:
-        .dword rvtest_code_end-rvtest_code_begin         // vmem seg size in any mode trampsvend+7*8
-
-\__MODE__\()mpp_sv:
-                                // save mpp=3<<1 during test for mprv spcl case,***only Smode vers
-\__MODE__\()trap_sig:
-        .dword  mtrap_sigptr    // ptr to next trapsig  ***GLBL(only Mmode ver. used) trampsvend+8*8
-\__MODE__\()satp_sv:
-        .dword 0                // save area for incoming xsatp                       trampsvend+9*8
-\__MODE__\()trampend_sv:
-        .dword  0               // save loc of end of sved trampoline prolog/epilog   trampsvend+10*8
-\__MODE__\()tentry_sv:
-        .dword  \__MODE__\()trampoline + actual_tramp_sz  // save comm entry loc pt   trampsvend+11*8
-\__MODE__\()edeleg_sv:
-        .dword  0               // save loc for edeleg CSR                            trampsvend+12*8:
-\__MODE__\()tvec_new:
-        .dword  0               // points to in-use tvec, actual tramp table used     trampsvend+13*8
-\__MODE__\()tvec_save:
-        .dword  0               // save area for incoming mtvec                       trampsvend+14*8
-\__MODE__\()scratch_save:
-        .dword  0               // save area for incoming mscratch                    trampsvend+15*8
-                                //****GLOBAL:*****  onlyMMode version used
-\__MODE__\()trapreg_sv:         // hndler regsave area, T1..T6,sp+spare keep dbl algn trampsvend+16*8
-        .fill   8, REGWIDTH, 0xdeadbeef
-
-\__MODE__\()sv_area_end:        // used to calc size, which is used to avoid CSR read trampsvend+24/32+8
-
-.option pop
-.endm                           // end of TRAP_SAVEAREA
-
-//==============================================================================
-// This section defines the required test format spec macros:
-// RVTEST_[CODE/DATA/SIG]_[BEGIN/END]
-//==============================================================================
-
-
-/**************************** CODE BEGIN w/ TRAP HANDLER START  *********************/
-/**** instantiate prologs using RVTEST_TRAP_PROLOG() if rvtests_xtrap_routine is ****/
-/**** is defined, then initializes regs & defines rvtest_code_begin global label ****/
-/************************************************************************************/
-.macro RVTEST_CODE_BEGIN
- .option push
- .option rvc
- .align UNROLLSZ
- .option norvc
- .section .text.init
- .globl  rvtest_init
- .global rvtest_code_begin              //define the label and make it available
-
-rvtest_init:                            //instantiate prologs here
-  INSTANTIATE_MODE_MACRO RVTEST_TRAP_PROLOG
-  RVTEST_INIT_GPRS                      // 0xF0E1D2C3B4A59687
-rvtest_code_begin:
- .option pop
-.endm                                   //end of RVTEST_CODE_BEGIN
-/*********************** end of RVTEST_CODE_BEGIN ***********************************/
-
-/************************************************************************************/
-/****        The above is instantiated at the start of the actual test           ****/
-/****                    So the test is here                                     ****/
-/****        the below is instantiated at the end   of the actual test           ****/
-/************************************************************************************/
-
-/**************************************************************************************/
-/**** RVTEST_CODE_END macro  defines end of test code: saves regs, transitions to  ****/
-/**** Mmode, & instantiates epilog using RVTEST_TRAP_EPILOG() macros. Test code    ****/
-/**** falls through to this else must branch to label rvtest_code_end. This must   ****/
-/**** branch to a RVMODEL_HALT macro at the end. The actual trap handlers for each ****/
-/**** mode are instantiated immediately following with RVTEST_TRAP_HANDLER() macro ****/
-/**************************************************************************************/
-
-.macro RVTEST_CODE_END          // test is ended, but in no particular mode
-  .option push
-  .option norvc
-  .global rvtest_code_end       // define the label and make it available
-  .global cleanup_epilogs       // ****ALERT: tests must populate x1 with a point to the end of regular sig area
-/**** MPRV must be clear here !!! ****/
-rvtest_code_end:                // RVMODEL_HALT should get here
-  #ifdef rvtest_gpr_save        // gpr_save area is instantiated at end of signature
-    RVTEST_SAVE_GPRS  x1        gpr_save
-  #endif
-    RVTEST_GOTO_MMODE           // if only Mmode used by tests, this has no effect
-cleanup_epilogs:                // jump here to quit, will restore state for each mode
-
-//restore xTVEC, trampoline, regs for each mode in opposite order that they were saved
-#ifdef rvtest_mtrap_routine
-    #ifdef rvtest_strap_routine
-        #ifdef rvtest_vtrap_routine
-          RVTEST_TRAP_EPILOG V  // actual v-mode prolog/epilog/handler code
-        #endif
-      RVTEST_TRAP_EPILOG S      // actual s-mode prolog/epilog/handler code
-    #endif
-   RVTEST_TRAP_EPILOG M         // actual m-mode prolog/epilog/handler code
-#endif
-
-/************* test done, epilog has restored everying, jump to halt ****************/
-  j     exit_cleanup            //skip around handlers, go to RVMODEL_HALT
-
-abort_tests:
-  LREG    T4, sig_bgn_off(sp)   // calculate Mmode sig_end addr in handler's mode
-  LREG    T1, sig_seg_siz(sp)
-  add     T1, T1, T4            // construct sig seg end
-  LI(     T1, 0xBAD0DAD0)       // early abort signature value at sig_end, independent of mtrap_sigptr
-  SREG    T1, -4(T4)            // save into last signature canary
-  j     exit_cleanup            // skip around handlers, go to RVMODEL_HALT
-/********************** trap handlers inserted here ***********************************/
-
-    INSTANTIATE_MODE_MACRO RVTEST_TRAP_HANDLER
-
-exit_cleanup:                   // *** RVMODEL_HALT MUST follow this***, then data
-
-  .option pop
-.endm                           // end of RVTEST_CODE_END
-
-/************************************************************************************/
-/**** RVTEST_CODE_END macros must fall thru or jump to an RVMODEL_HALT macro here ***/
-/************************************************************************************/
-
-/*===================================data section starts here========================*/
-
-/************************************************************************************/
-/**** RVTEST_DATA_BEGIN macro defines end of input data & rvtest_data_end label  ****/
-/**** this is a data area, so we instantiate trap save areas for each mode here  ****/
-/************************************************************************************/
-
-.macro RVTEST_DATA_BEGIN
-.data
-
-.align 4        //ensure dbl alignment
-/**************************************************************************************/
-/**** this is the pointer to the current trap signature part of the signature area ****/
-/**** it is shared by all trap modes, but shouldn't be instantiated unless at least****/
-/**** 1 trap mode is defined (which is covered if m-mode trap handlers are defined ****/
-/**************************************************************************************/
-
-/**** now instantiate separate save areas for each modes state     ****/
-/**** strictly speaking, should only be needed for reentrant traps ****/
-
-        INSTANTIATE_MODE_MACRO RVTEST_TRAP_SAVEAREA
-
-/************************************************************************************/
-/**************** end of RVTEST_DATA_BEGIN; input data should follow ****************/
-/************************************************************************************/
-
-.global rvtest_data_begin
-rvtest_data_begin:
-.endm
-
-/************************************************************************************/
-/**************** RVTEST_DATA_END macro; defines global label rvtest_data_end    ****/
-/************************************************************************************/
-.macro RVTEST_DATA_END
-.global rvtest_data_end
- #ifndef rvtest_mtrap_routine
-  mtrap_sigptr:
-    .fill 2,4,0xdeadbeef
- #endif
-
-/**** create identity mapped page tables here if mmu is present ****/
-.align 12
-
-#ifndef RVTEST_NO_IDENTY_MAP
-  #ifdef rvtest_strap_routine
-    rvtest_Sroot_pg_tbl:
-      RVTEST_PTE_IDENT_MAP
-
-    #ifdef rvtest_vtrap_routine
-    rvtest_Vroot_pg_tbl:
-      RVTEST_PTE_IDENT_MAP
-    #endif
-  #endif
-#endif
-rvtest_data_end:
-.endm
+#include "encoding.h"
+// TODO the following should come from the YAML.
+#ifndef NUM_SPECD_INTCAUSES 
+  #define NUM_SPECD_INTCAUSES 16
+#endif
+//#define RVTEST_FIXED_LEN
+#ifndef UNROLLSZ
+  #define UNROLLSZ 5
+#endif
+// #ifndef rvtest_gpr_save
+//   #define rvtest_gpr_save
+// #endif
+
+// #define TEST_CASE_1
+
+//-----------------------------------------------------------------------
+// RV Arch Test Macros
+//-----------------------------------------------------------------------
+#ifndef RVMODEL_SET_MSW_INT
+  #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro"
+  #define RVMODEL_SET_MSW_INT       
+#endif
+
+#ifndef RVMODEL_CLEAR_MSW_INT     
+  #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro"
+  #define RVMODEL_CLEAR_MSW_INT     
+#endif
+
+#ifndef RVMODEL_CLEAR_MTIMER_INT
+  #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro"
+  #define RVMODEL_CLEAR_MTIMER_INT
+#endif
+
+#ifndef RVMODEL_CLEAR_MEXT_INT
+  #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro"
+  #define RVMODEL_CLEAR_MEXT_INT
+#endif
+
+#ifdef RVTEST_FIXED_LEN
+    #define LI(reg, val)\
+    .option push;\
+    .option norvc;\
+    .align UNROLLSZ;\
+        li reg,val;\
+    .align UNROLLSZ;\
+    .option pop;
+
+    #define LA(reg, val)\
+    .option push;\
+    .option norvc;\
+    .align UNROLLSZ;\
+        la reg,val;\
+    .align UNROLLSZ;\
+    .option pop;
+
+#else
+    #define LI(reg,val);\
+        .option push;\
+        .option norvc;\
+        li reg,val;\
+        .option pop;
+
+    #define LA(reg,val);\
+        .option push;\
+        .option norvc;\
+        la reg,val;\
+        .option pop;
+#endif
+#if XLEN==64
+  #define SREG sd
+  #define LREG ld
+  #define REGWIDTH 8
+  #define MASK 0xFFFFFFFFFFFFFFFF
+
+#else 
+  #if XLEN==32
+    #define SREG sw
+    #define LREG lw
+    #define REGWIDTH 4
+  #define MASK 0xFFFFFFFF
+
+  #endif
+#endif
+
+#if FLEN==64
+  #define FLREG fld
+  #define FSREG fsd
+  #define FREGWIDTH 8
+
+#else 
+  #if FLEN==32
+    #define FLREG flw
+    #define FSREG fsw
+    #define FREGWIDTH 4
+  #endif
+#endif
+
+// #if XLEN==64
+//   #if FLEN==32
+//     #define SREG sw
+//     #define LREG lW
+//     #define REGWIDTH 4
+//     #define MASK 0xFFFFFFFF
+//   #endif
+// #endif
+
+#define MMODE_SIG 3
+#define RLENG (REGWIDTH<<3)
+
+#define RVTEST_ISA(_STR)
+
+#ifndef DATA_REL_TVAL_MSK
+  #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16)
+#endif
+
+#ifndef CODE_REL_TVAL_MSK
+  #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16)
+#endif
+
+
+// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ //
+
+.macro RVTEST_CODE_BEGIN
+  .align UNROLLSZ
+  .section .text.init;
+  .globl rvtest_init;                                                  \
+  rvtest_init:
+#ifdef rvtest_mtrap_routine
+  LA(x1, rvtest_trap_prolog );
+  jalr ra, x1
+  rvtest_prolog_done:
+#endif
+     LI (x1,  (0xFEEDBEADFEEDBEAD & MASK));
+     LI (x2,  (0xFF76DF56FF76DF56 & MASK));
+     LI (x3,  (0x7FBB6FAB7FBB6FAB & MASK));
+     LI (x4,  (0xBFDDB7D5BFDDB7D5 & MASK));
+     LA (x5, rvtest_code_begin);
+     LA (x6, rvtest_data_begin);
+     LI (x7,  (0xB7FBB6FAB7FBB6FA & MASK));
+     LI (x8,  (0x5BFDDB7D5BFDDB7D & MASK));
+     LI (x9,  (0xADFEEDBEADFEEDBE & MASK));
+     LI (x10, (0x56FF76DF56FF76DF & MASK));
+     LI (x11, (0xAB7FBB6FAB7FBB6F & MASK));
+     LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK));
+     LI (x13, (0xEADFEEDBEADFEEDB & MASK));
+     LI (x14, (0xF56FF76DF56FF76D & MASK));
+     LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK));
+     #ifndef RVTEST_E
+     LI (x16, (0x7D5BFDDB7D5BFDDB & MASK));
+     LI (x17, (0xBEADFEEDBEADFEED & MASK));
+     LI (x18, (0xDF56FF76DF56FF76 & MASK));
+     LI (x19, (0x6FAB7FBB6FAB7FBB & MASK));
+     LI (x20, (0xB7D5BFDDB7D5BFDD & MASK));
+     LI (x21, (0xDBEADFEEDBEADFEE & MASK));
+     LI (x22, (0x6DF56FF76DF56FF7 & MASK));
+     LI (x23, (0xB6FAB7FBB6FAB7FB & MASK));
+     LI (x24, (0xDB7D5BFDDB7D5BFD & MASK));
+     LI (x25, (0xEDBEADFEEDBEADFE & MASK));
+     LI (x26, (0x76DF56FF76DF56FF & MASK));
+     LI (x27, (0xBB6FAB7FBB6FAB7F & MASK));
+     LI (x28, (0xDDB7D5BFDDB7D5BF & MASK));
+     LI (x29, (0xEEDBEADFEEDBEADF & MASK));
+     LI (x30, (0xF76DF56FF76DF56F & MASK));
+     LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK));
+     #endif
+  .globl rvtest_code_begin
+  rvtest_code_begin:
+.endm
+
+// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------//
+
+.macro RVTEST_CODE_END
+  .align 4; 
+  .global rvtest_code_end
+  rvtest_code_end:
+#ifdef rvtest_mtrap_routine
+  .option push
+  .option norvc 
+  j exit_cleanup
+
+  rvtest_trap_prolog:
+  /******************************************************************************/
+  /****                 Prolog, to be run before any tests                   ****/
+  /****       #include 1 copy of this per mode in rvmodel_boot code?         ****/
+  /**** -------------------------------------------------------------------  ****/
+  /**** if xTVEC isn't completely RW, then we need to change the code at its ****/
+  /**** target. The entire trap trampoline and mtrap handler replaces the    ****/
+  /**** area pointed to by mtvec, after saving its original contents first.  ****/
+  /**** If it isn't possible to fully write that area, restore and fail.     ****/
+  /******************************************************************************/
+
+  //trap_handler_prolog; enter with t1..t6 available
+  
+  init_mscratch:
+  	la	t1, trapreg_sv
+  	csrrw	t1, CSR_MSCRATCH, t1	// swap old mscratch. mscratch not points to trapreg_sv
+  	la	t2, mscratch_save    
+  	SREG	t1, 0(t2)		        // save old mscratch in mscratch_save region
+    csrr t1, CSR_MSCRATCH       // read the trapreg_sv address
+    LA( t2, mtrap_sigptr   ) // locate the start of the trap signature
+    SREG  t2, 0(t1)           // save mtrap_sigptr at first location of trapreg_sv
+  init_mtvec:	
+  	la	t1, mtrampoline    
+  	la	t4, mtvec_save
+  	csrrw	t2, CSR_MTVEC, t1		          // swap mtvec and trap_trampoline
+  	SREG	t2, 0(t4)		              // save orig mtvec
+  	csrr	t3, CSR_MTVEC		              // now read new_mtval back
+  	beq	t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue
+  	
+  /****************************************************************/
+  /**** fixed mtvec, can't move it so move trampoline instead  ****/
+  /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end  ****/
+  /****************************************************************/
+  
+  // t2 = dut's original mtvec setting
+  // t1 = mtrampoline address
+  init_tramp:	/**** copy trampoline at mtvec tgt ****/
+  
+  	csrw	CSR_MTVEC, t2		// restore orig mtvec, will now attemp to copy trampoline to it
+  	la	t3, tramptbl_sv		// addr of save area
+  	addi	t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area
+  
+  overwrite_tt:			            // now build new trampoline table with offsets base from curr mtvec
+  	lw	t6, 0(t2)		            // get original mtvec target
+  	sw	t6, 0(t3)		            // save it
+  	lw	t5, 0(t1)		            // get trampoline src
+  	sw	t5, 0(t2)		            // overwrite mtvec target
+  	lw	t6, 0(t2)		            // rd it back to make sure it was written
+  	bne	t6, t5, resto_tramp		  // table isn't fully writable, restore and give up
+  	addi	t1, t1, 4		          // next src  index
+  	addi	t2, t2, 4		          // next tgt  index
+  	addi	t3, t3, 4		          // next save index
+  	bne	t3, t4, overwrite_tt		// not done,  loop
+  	j rvtest_prolog_done 
+  
+  resto_tramp:			                      // vector table not writeable, restore
+  	LREG	t1, 16(t4)            // load mscratch_SAVE at fixed offset from table end
+  	csrw	CSR_MSCRATCH, t1		                // restore mscratch
+  	LREG	t4, 8(t4)             // load mtvec_SAVE (used as end of loop marker)
+  
+  
+  resto_loop:	              // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin
+  	lw	t6, 0(t3)		        // read saved tgt entry
+  	sw	t6, 0(t2)		        // restore original tgt
+  	addi	t2, t2, -4		    // prev tgt  index
+  	addi	t3, t3, -4		    // prev save index
+  	bne	t2, t4, resto_loop  // didn't restore to begining yet,  loop
+  	
+  	j	rvtest_end // failure to replace trampoline
+  
+
+  #define mhandler			\
+    csrrw   sp, CSR_MSCRATCH, sp;	\
+    SREG      t6, 6*REGWIDTH(sp);	\
+    jal t6, common_prolog;
+  
+  /**********************************************************************/
+  /**** This is the entry point for all m-modetraps, vectored or not.****/
+  /**** At entry, mscratch will contain a pointer to a scratch area. ****/
+  /**** This is an array of branches at 4B intevals that spreads out ****/
+  /**** to an array of 32B mhandler macros for specd int causes, and ****/
+  /**** to a return for anything above that (which causes a mismatch)****/
+  /**********************************************************************/
+  mtrampoline:		// 64 or 32 entry table
+  value = 0
+  .rept NUM_SPECD_INTCAUSES     	  // located at each possible int vectors
+     j	mtrap_handler + 12*(value)  //offset < +/- 1MB
+     value = value + 1
+  .endr
+  .rept RLENG-NUM_SPECD_INTCAUSES   // fill at each impossible entry
+  	mret
+  .endr
+  
+  mtrap_handler:		/* after executing, sp points to temp save area, t4 is PC */
+  .rept NUM_SPECD_INTCAUSES
+    mhandler
+  .endr
+
+  common_prolog:
+    la t5, common_mhandler
+    jr t5
+  /*********************************************************************/
+  /**** common code for all ints & exceptions, will fork to handle  ****/ 
+  /**** each separately. The common handler first stores trap mode+ ****/ 
+  /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/
+  /**** sw and timer ints only store 3 of the 4.                    ****/
+  /**** sig offset Exception    ExtInt       SWInt        TimerInt  ****/
+  /****         0: tval         IntID        -1           -1        ****/
+  /****         4: mepc         mip          mip          mip       ****/
+  /****         8: <----------------------  mcause ------------->   ****/
+  /****        12: <---------------------  Vect+mode  ---------->   ****/
+  /*********************************************************************/
+  /*   in general, CSRs loaded in t2, addresses into t3                */
+  
+  common_mhandler:                 /* enter with link in t6 */
+          SREG      t5, 5*REGWIDTH(sp)
+          SREG      t4, 4*REGWIDTH(sp)
+          SREG      t3, 3*REGWIDTH(sp)
+          SREG      t2, 2*REGWIDTH(sp)
+          SREG      t1, 1*REGWIDTH(sp)  /* save other temporaries */
+  
+          LREG      t1, 0(sp)        /* load trap sig pointer (runs backwards from DATA_END) */
+          
+          LA(     t3, mtrampoline)
+          sub     t2, t6, t3       /* reloc “link” to 0..63 to show which int vector was taken */
+          addi    t2, t2, MMODE_SIG   /* insert mode# into 1:0  */
+          SREG      t2, 0*REGWIDTH(t1)        /* save 1st sig value, (vect, trapmode) */
+  sv_mcause:	
+          csrr   t2, CSR_MCAUSE
+          SREG      t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause)  */
+  
+          bltz    t2, common_mint_handler /* this is a interrupt, not a trap */
+  
+  /********************************************************************/ 
+  /**** This is the exceptions specific code, storing relative mepc****/ 
+  /**** & relative tval signatures. tval is relocated by code or   ****/ 
+  /**** data start, or 0 depending on mcause. mepc signature value ****/ 
+  /**** is relocated by code start, and restored adjusted depending****/ 
+  /**** on op alignment so trapped op isn't re-executed.           ****/ 
+  /********************************************************************/ 
+  common_mexcpt_handler:
+          csrr   t2, CSR_MEPC
+  sv_mepc:	
+          LA(     t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */
+          sub     t4, t2, t3      /* convert mepc to rel offset of beginning of test*/
+          SREG      t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */
+  adj_mepc:   		//adj mepc so there is padding after op, and its 8B aligned
+        andi    t4, t2, 0x2     /* set to 2 if mepc was misaligned */
+        sub     t2, t2, t4      /* adjust mepc to prev 4B alignment */
+        addi    t2, t2, 0x8     /* adjust mepc, so it skips past the op, has padding & is 4B aligned */
+        csrw    CSR_MEPC, t2	/* restore adjusted value, has 1,2, or 3 bytes of padding */
+  
+  
+  /* calculate relative mtval if it’s an address  (by code_begin or data_begin amt)  */
+  /* note that masks that determine this are implementation specific from YAML */
+  
+  /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */
+  
+  adj_mtval:
+        	csrr   t2, CSR_MCAUSE  /* code begin adjustment amount already in t3 */
+  
+          LI(t4, CODE_REL_TVAL_MSK)   /* trap#s 12, 3,1,0, -- adjust w/ code_begin */
+          sll     t4, t4, t2		          /* put bit# in MSB */
+          bltz    t4, sv_mtval		        /* correct adjustment is code_begin in t3 */
+  
+          LA(     t3, mtrap_sigptr) /* adjustment assuming access is to signature region */
+          LI(t4, DATA_REL_TVAL_MSK)       /* trap#s not 14, 11..8, 2 adjust w/ data_begin */
+          sll     t4, t4, t2		          /* put bit# in MSB */
+          bgez    t4, no_adj		          /* correct adjustment is data_begin in t3 */
+  sigbound_chk:
+          csrr t4, CSR_MTVAL                  /* do a bounds check on mtval */
+          bge   t3, t4, sv_mtval          /* if mtval is greater than the rvmodel_data_begin then use that as anchor */
+          LA( t3, rvtest_data_begin)      /* else change anchor to rvtest_data_begin  */
+          blt   t3, t4, sv_mtval          /* before the signature, use data_begin adj */
+          mv t4, t3                       /* use sig relative adjust */
+  no_adj: 
+          LI(t3, 0)			/* else zero adjustment amt */
+
+  // For Illegal op handling
+          addi    t2, t2, -2            /* check if mcause==2 (illegal op) */
+          bnez    t2, sv_mtval          /* not illegal op, no special treatment */
+          csrr    t2, CSR_MTVAL
+          bnez    t2, sv_mtval          /* mtval isn’t zero, no special treatment */
+  illop:
+          LI(t5, 0x20000)           /* get mprv mask */
+          csrrs   t5, CSR_MSTATUS, t5       /* set mprv while saving the old value */
+          csrr    t3, CSR_MEPC
+          lhu     t2, 0(t3)             /* load 1st 16b of opc w/ old priv, endianess*/
+          andi    t4, t2,  0x3
+          addi    t4, t4, -0x3          /* does opcode[1:0]==0b11? (Meaning >16b op) */
+          bnez    t4, sv_mtval          /* entire mtval is in tt2, adj amt will be set to zero */
+          lhu     t4, 2(t3)           
+          sll     t4, t4, 16
+          or      t3, t2, t4            /* get 2nd  hwd, align it & insert it into opcode */
+          csrw    CSR_MSTATUS, t5           /* restore mstatus */
+
+/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/
+
+  sv_mtval:
+          csrr   t2, CSR_MTVAL
+          sub    t2, t2, t3		/* perform mtval adjust by either code or data position or zero*/
+          SREG   t2, 3*REGWIDTH(t1)	/* save 4th sig value, (rel mtval) into trap signature area */
+  
+  resto_rtn:		/* restore and return */
+          addi    t1, t1,4*REGWIDTH		/* adjust trap signature ptr (traps always save 4 words) */
+          SREG      t1, 0*REGWIDTH(sp) 	/* save updated trap sig pointer (pts to trap_sigptr */
+  
+          LREG      t1, 1*REGWIDTH(sp)
+          LREG      t2, 2*REGWIDTH(sp)
+          LREG      t3, 3*REGWIDTH(sp)
+          LREG      t4, 4*REGWIDTH(sp)
+          LREG      t5, 5*REGWIDTH(sp)
+          LREG      t6, 6*REGWIDTH(sp)  /* restore temporaries */
+  
+          csrrw   sp, CSR_MSCRATCH, sp /* restore sp from scratch */
+          mret
+  
+  common_mint_handler:    /* t1 has sig ptr, t2 has mcause */
+  
+          LI(t3, 1)
+          sll     t3, t3, t2      /* create mask 1<<mcause */
+          csrrc   t4, CSR_MIP, t3     /* read, then attempt to clear int pend bit */
+          csrrc   t4, CSR_MIE, t3     /* read, then attempt to clear int pend bit */
+  sv_mip:	/* note: clear has no effect on MxIP */
+          SREG      t4, 2*REGWIDTH(t1) /* save 3rd sig value, (mip)  */
+  
+  /* case table branch to interrupt clearing code, depending on mcause */
+  	slli	t2, t2, 3       /* convert mcause to 8B offset */
+  	LA(	t3, clrint_tbl ) /* load jump table address */
+  	add	t3, t3, t2      /* index into to it, load vector, then jump to it */
+  	LREG	t3, 0(t3)       
+  	jr	t3
+  
+  clr_sw_int:
+          RVMODEL_CLEAR_MSW_INT
+          j       resto_rtn   
+  
+  clr_tmr_int:
+          RVMODEL_CLEAR_MTIMER_INT
+          j       resto_rtn   
+  
+  clr_ext_int:
+          RVMODEL_CLEAR_MEXT_INT
+          SREG      t3, -3*REGWIDTH(t1) /* save 4rd sig value, (intID)  */
+          j       resto_rtn   
+  .align 3	
+  clrint_tbl:
+  	.dword	resto_rtn	/* int cause 0 is reserved, just return */
+  	.dword	clr_sw_int	/* int cause 1  Smode SW int            */
+  	.dword	resto_rtn	/* int cause 2 is reserved, just return */
+  	.dword	clr_sw_int	/* int cause 3  Mmode SW int            */
+  	.dword	resto_rtn	/* int cause 4 is reserved, just return */
+  	.dword	clr_tmr_int	/* int cause 5  Smode Tmr int           */
+  	.dword	resto_rtn	/* int cause 6 is reserved, just return */
+  	.dword	clr_tmr_int	/* int cause 7  Mmode Tmr int           */
+  	.dword	resto_rtn	/* int cause 8 is reserved, just return */
+  	.dword	clr_ext_int	/* int cause 9  Smode Ext int           */
+  	.dword	resto_rtn	/* int cause A is reserved, just return */
+  	.dword	clr_ext_int	/* int cause B  Mmode Ext int           */
+  	.dword	resto_rtn	/* int cause C is reserved, just return */
+  	.dword	resto_rtn	/* int cause D is reserved, just return */
+  	.dword	resto_rtn	/* int cause E is reserved, just return */
+  	.dword	resto_rtn	/* int cause F is reserved, just return */
+  	.dword	resto_rtn	/* int cause 10 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 11 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 12 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 13 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 14 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 15 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 16 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 17 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 18 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 19 is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1A is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1B is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1C is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1D is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1E is reserved, just return */
+  	.dword	resto_rtn	/* int cause 1F is reserved, just return */
+  	
+  1:	// xtvec_installed:
+  ret
+
+  // ----------------------------------------------------------------------------------------------
+  // ----------------------------------------------------------------------------------------------
+  // ----------------------------------------------------------------------------------------------
+  // ----------------------------------------------------------------------------------------------
+
+  exit_cleanup://COMPLIANCE_HALT should get here
+  	la	t3, tramptbl_sv+ NUM_SPECD_INTCAUSES*4	// end of save area
+  
+  	la	t5, mtvec_save
+  	LREG	t1, 8(t5)
+  	csrw	 CSR_MSCRATCH, t1		        // restore mscratch
+  	LREG	t4, 0(t5)		              // load orig mtvec
+  	csrrw	t2, CSR_MTVEC, t4		        // restore mtvec (not redundant)
+  	bne	t4, t2, 1f// if saved!=mtvec, done, else need to restore
+  	
+  	addi	t2, t4, NUM_SPECD_INTCAUSES*4  // start pt is end of vect area
+  resto_vec:	                              // goes backwards, t2= dest vec tbl ptr, 
+                                            // t3=src save area ptr, t4=vec tbl begin
+  	lw	t6, 0(t3)		                        // read saved tgt entry
+  	sw	t6, 0(t2)		                        // restore original tgt
+  	addi	t2, t2, -4		                    // prev tgt  index
+  	addi	t3, t3, -4		                    // prev save index
+  	bne	t2, t4, resto_vec	                  // didn't get to end, continue
+  1: 
+  rvtest_end:
+  .option pop
+#endif
+#ifdef rvtest_gpr_save
+  csrw CSR_MSCRATCH, x31       //save x31, get temp pointer
+  LA(x31, gpr_save) 
+  SREG x0, 0*REGWIDTH(x31)
+  SREG x1, 1*REGWIDTH(x31)
+  SREG x2, 2*REGWIDTH(x31)
+  SREG x3, 3*REGWIDTH(x31)
+  SREG x4, 4*REGWIDTH(x31)
+  SREG x5, 5*REGWIDTH(x31)
+  SREG x6, 6*REGWIDTH(x31)
+  SREG x7, 7*REGWIDTH(x31)
+  SREG x8, 8*REGWIDTH(x31)
+  SREG x9, 9*REGWIDTH(x31)
+  SREG x10, 10*REGWIDTH(x31)
+  SREG x11, 11*REGWIDTH(x31)
+  SREG x12, 12*REGWIDTH(x31)
+  SREG x13, 13*REGWIDTH(x31)
+  SREG x14, 14*REGWIDTH(x31)
+  SREG x15, 15*REGWIDTH(x31)
+  SREG x16, 16*REGWIDTH(x31)
+  SREG x17, 17*REGWIDTH(x31)
+  SREG x18, 18*REGWIDTH(x31)
+  SREG x19, 19*REGWIDTH(x31)
+  SREG x20, 20*REGWIDTH(x31)
+  SREG x21, 21*REGWIDTH(x31)
+  SREG x22, 22*REGWIDTH(x31)
+  SREG x23, 23*REGWIDTH(x31)
+  SREG x24, 24*REGWIDTH(x31)
+  SREG x25, 25*REGWIDTH(x31)
+  SREG x26, 26*REGWIDTH(x31)
+  SREG x27, 27*REGWIDTH(x31)
+  SREG x28, 28*REGWIDTH(x31)
+  SREG x29, 29*REGWIDTH(x31)
+  SREG x30, 30*REGWIDTH(x31)
+  addi x30, x31, 0                // mv gpr pointer to x30
+  csrr x31, CSR_MSCRATCH              // restore value of x31
+  SREG x31, 31*REGWIDTH(x30)      // store x31
+#endif
+.endm
+
+
+.macro RVTEST_DATA_BEGIN
+.data
+.align 4
+.global rvtest_data_begin
+rvtest_data_begin:
+#ifdef rvtest_mtrap_routine
+trapreg_sv:	
+      .fill    7, REGWIDTH, 0xdeadbeef     /* handler reg save area, 1 extra wd just in case */
+tramptbl_sv:	// save area of existing trampoline table
+.rept NUM_SPECD_INTCAUSES
+	J	.+0		  /* prototype jump instruction, offset to be filled in */
+.endr
+mtvec_save:
+	.dword	0		  /* save area for incoming mtvec */
+mscratch_save:	
+	.dword  0		  /* save area for incoming mscratch */
+#endif
+
+.endm
+
+.macro RVTEST_DATA_END
+.global rvtest_data_end
+rvtest_data_end:
+.endm
+
+
+#define RVTEST_CASE(_PNAME,_DSTR,...)                               
+
+#define RVTEST_FP_ENABLE()\
+    LI x2, MSTATUS_FS;\
+    csrrs x3, mstatus,x0;\
+    or x2, x3, x2;\
+    csrrw x0,mstatus,x2;                      
+
+#define RVTEST_SIGBASE(_R,_TAG) \
+  LA(_R,_TAG);\
+  .set offset,0;
+
+.set offset,0;
+#define _ARG5(_1ST,_2ND, _3RD,_4TH,_5TH,...) _5TH
+#define _ARG4(_1ST,_2ND, _3RD,_4TH,...) _4TH
+#define _ARG3(_1ST,_2ND, _3RD, ...) _3RD
+#define _ARG2(_1ST,_2ND, ...) _2ND
+#define _ARG1(_1ST,...) _1ST
+#define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0)
+#define RVTEST_SIGUPD(_BR,_R,...)\
+  .if NARG(__VA_ARGS__) == 1;\
+    SREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
+    .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,)0)+REGWIDTH;\
+  .endif;\
+  .if NARG(__VA_ARGS__) == 0;\
+    SREG _R,offset(_BR);\
+  .set offset,offset+REGWIDTH;\
+  .endif;
+
+#define RVTEST_SIGUPD_F(_BR,_R,_F,...)\
+  .if NARG(__VA_ARGS__) == 1;\
+    FSREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
+    SREG _F,_ARG1(__VA_ARGS__,0)+REGWIDTH(_BR);\
+    .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,)0)+(REGWIDTH+REGWIDTH);\
+  .endif;\
+  .if NARG(__VA_ARGS__) == 0;\
+    FSREG _R,offset(_BR);\
+    SREG _F,offset+REGWIDTH(_BR);\
+    .set offset,offset+(REGWIDTH+REGWIDTH);\
+  .endif;
+  
+#define RVTEST_SIGUPD_FID(_BR,_R,_F,...)\
+  .if NARG(__VA_ARGS__) == 1;\
+    SREG _R,_ARG1(__VA_ARGS__,0)(_BR);\
+    SREG _F,_ARG1(__VA_ARGS__,0)+REGWIDTH(_BR);\
+    .set offset,_ARG1(__VA_ARGS__,0)+(2*REGWIDTH);\
+  .endif;\
+  .if NARG(__VA_ARGS__) == 0;\
+    SREG _R,offset(_BR);\
+    SREG _F,offset+REGWIDTH(_BR);\
+    .set offset,offset+(2*REGWIDTH);\
+  .endif;
+  
+#define RVTEST_VALBASEUPD(_BR,...)\
+  .if NARG(__VA_ARGS__) == 0;\
+      addi _BR,_BR,2040;\
+  .endif;\
+  .if NARG(__VA_ARGS__) == 1;\
+      LA(_BR,_ARG1(__VA_ARGS__,x0));\
+  .endif;
+
+#define RVTEST_VALBASEMOV(_NR,_BR)\
+  add _NR, _BR, x0;
+/*
+ * RVTEST_BASEUPD(base reg) - updates the base register the last signature address + REGWIDTH
+ * RVTEST_BASEUPD(base reg, new reg) - moves value of the next signature region to update into new reg
+ * The hidden variable offset is reset always
+*/
+
+#define RVTEST_BASEUPD(_BR,...)\
+    .if NARG(__VA_ARGS__) == 0;\
+        addi _BR,_BR,offset;\
+    .endif;\
+    .if NARG(__VA_ARGS__) == 1;\
+        addi _ARG1(__VA_ARGS__,x0),_BR,offset;\
+    .endif;\
+    .set offset,0;
+
+
+
+//------------------------------ BORROWED FROM ANDREW's RISC-V TEST MACROS -----------------------//
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj) \
+5:                                            ;\
+    LA(rd,5b                                 ) ;\
+    .if adj & 1 == 1                          ;\
+    LA(rs1, 3f-imm+adj-1  )                    ;\
+    jalr rd, imm+1(rs1)                      ;\
+    .else                                     ;\
+    LA(rs1, 3f-imm+adj)                        ;\
+    jalr rd, imm(rs1)                         ;\
+    .endif                                    ;\
+    nop                                       ;\
+    nop                                       ;\
+    xori rd,rd, 0x2                           ;\
+    j 4f                                      ;\
+                                              ;\
+3:  .if adj & 2 == 2                              ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    xori rd,rd, 0x3                           ;\
+    j 4f                                      ;\
+    .if adj&2 == 2                              ;\
+    .fill 2,1,0x00                     ;\
+    .endif                                    ;\
+                                              ;\
+4: LA(tempreg, 5b                            ) ;\
+   andi tempreg,tempreg,~(3)                  ;\
+    sub rd,rd,tempreg                          ;\
+    RVTEST_SIGUPD(swreg,rd,offset) 
+//SREG rd, offset(swreg);
+
+#define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)\
+5:                                           ;\
+    LA(tempreg, 2f                          ) ;\
+    jalr x0,0(tempreg)                       ;\
+6:  LA(tempreg, 4f                          ) ;\
+    jalr x0,0(tempreg)                        ;\
+1:  .if adj & 2 == 2                         ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    xori rd,rd, 0x1                           ;\
+    beq x0,x0,6b                               ;\
+    .if adj & 2 == 2                              ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    .if (imm/2) - 2 >= 0                      ;\
+        .set num,(imm/2)-2                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 3f                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    nop                                       ;\
+    .endr                                     ;\
+                                              ;\
+2:  jal rd, label+(adj)                    ;\
+    .if adj & 2 == 2                              ;\
+    nop                                       ;\
+    nop                                       ;\
+    .endif                                    ;\
+    xori rd,rd, 0x2                           ;\
+    j 4f                                      ;\
+    .if (imm/2) - 3 >= 0                      ;\
+        .set num,(imm/2)-3                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .if label == 1b                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    nop                                       ;\
+    .endr                                     ;\
+3:  .if adj & 2 == 2                              ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    xori rd,rd, 0x3                           ;\
+    LA(tempreg, 4f                          ) ;\
+    jalr x0,0(tempreg)                        ;\
+    .if adj&2 == 2                              ;\
+    .fill 2,1,0x00                     ;\
+    .endif                                    ;\
+4: LA(tempreg, 5b                            ) ;\
+   andi tempreg,tempreg,~(3)                  ;\
+    sub rd,rd,tempreg                          ;\
+    RVTEST_SIGUPD(swreg,rd,offset) 
+//SREG rd, offset(swreg);
+
+#define TEST_BRANCH_OP(inst, tempreg, reg1, reg2, val1, val2, imm, label, swreg, offset,adj) \
+    LI(reg1, MASK_XLEN(val1))                  ;\
+    LI(reg2, MASK_XLEN(val2))                  ;\
+    addi tempreg,x0,0                         ;\
+    j 2f                                      ;\
+                                              ;\
+1:  .if adj & 2 == 2                         ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    addi tempreg,tempreg, 0x1                           ;\
+    j 4f                                      ;\
+    .if adj & 2 == 2                              ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    .if (imm/2) - 2 >= 0                      ;\
+        .set num,(imm/2)-2                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 3f                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    nop                                       ;\
+    .endr                                     ;\
+                                              ;\
+2:  inst reg1, reg2, label+adj                ;\
+    addi tempreg, tempreg,0x2                   ;\
+    j 4f                                      ;\
+    .if (imm/4) - 3 >= 0                      ;\
+        .set num,(imm/4)-3                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 1b                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    nop                                       ;\
+    .endr                                     ;\
+                                              ;\
+3:  .if adj & 2 == 2                              ;\
+    .fill 2,1,0x00                          ;\
+    .endif                                    ;\
+    addi tempreg, tempreg,0x3                           ;\
+    j 4f                                      ;\
+    .if adj&2 == 2                              ;\
+    .fill 2,1,0x00                     ;\
+    .endif                                    ;\
+                                              ;\
+4:   RVTEST_SIGUPD(swreg,tempreg,offset) 
+//SREG tempreg, offset(swreg);                
+
+#define TEST_STORE(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj)   ;\
+LI(rs2,rs2_val)                                                             ;\
+addi rs1,swreg,offset+adj                                                     ;\
+LI(testreg,imm_val)                                                         ;\
+sub rs1,rs1,testreg                                                          ;\
+inst rs2, imm_val(rs1)                                                      ;\
+nop                                                                         ;\
+nop                                                                         
+
+#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj)   ;\
+LA(rs1,rvtest_data+(index*4)+adj-imm_val)                                      ;\
+inst destreg, imm_val(rs1)                                                   ;\
+nop                                                                         ;\
+nop                                                                         ;\
+RVTEST_SIGUPD(swreg,destreg,offset) 
+//SREG destreg, offset(swreg);
+
+#define TEST_STORE_F(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj,flagreg)   ;\
+LI(flagreg,rs2_val)                                                           ;\
+fmv.w.x rs2, flagreg                                                          ;\
+addi rs1,swreg,offset+adj                                                     ;\
+LI(testreg,imm_val)                                                         ;\
+sub rs1,rs1,testreg                                                          ;\
+inst rs2, imm_val(rs1)                                                      ;\
+nop                                                                         ;\
+nop                                                                         ;\
+csrrs flagreg, fflags, x0                                                   ;\
+RVTEST_SIGUPD(swreg,flagreg,offset)
+
+#define TEST_LOAD_F(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj,flagreg)   ;\
+LA(rs1,rvtest_data+(index*4)+adj-imm_val)                                      ;\
+inst destreg, imm_val(rs1)                                                   ;\
+nop                                                                         ;\
+nop                                                                         ;\
+csrrs flagreg, fflags, x0                                                   ;\
+RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset) 
+
+#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \
+    LI(TEMP_REG,VAL);\
+    and TEMP_REG,TEMP_REG,MASK_REG;\
+    csrr DEST_REG,ADDRESS;\
+    and DEST_REG,DEST_REG,NEG_MASK_REG;\
+    or TEMP_REG,TEMP_REG,DEST_REG;\
+    csrw ADDRESS,TEMP_REG;\
+    csrr DEST_REG,ADDRESS;\
+    RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET)
+
+
+#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \
+    code; \
+    RVTEST_SIGUPD(swreg,destreg,offset); \
+    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
+
+#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
+    code; \
+    RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset); \
+    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
+    
+#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
+    code; \
+    RVTEST_SIGUPD_FID(swreg,destreg,flagreg,offset); \
+    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
+
+#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LA testreg, 1f; \
+      1: \
+      inst destreg, imm; \
+      sub destreg, destreg, testreg; \
+      )
+
+//Tests for a instructions with register-immediate operand
+#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg, MASK_XLEN(val)); \
+      inst destreg, reg, SEXT_IMM(imm); \
+    )
+
+//Tests for floating-point instructions with a single register operand
+#define TEST_FPSR_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
+      FLREG freg, val_offset(valaddr_reg); \
+      csrrwi x0, frm, rm; \
+      inst destreg, freg; \
+      csrrs flagreg, fflags, x0; \
+    )
+    
+//Tests for floating-point instructions with a single register operand and integer destination register
+#define TEST_FPID_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
+      FLREG freg, val_offset(valaddr_reg); \
+      csrrwi x0, frm, rm; \
+      inst destreg, freg; \
+      csrrs flagreg, fflags, x0; \
+    )
+    
+//Tests for floating-point instructions with a single register operand and integer operand register
+#define TEST_FPIO_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
+      LREG freg, val_offset(valaddr_reg); \
+      csrrwi x0, frm, rm; \
+      inst destreg, freg; \
+      csrrs flagreg, fflags, x0; \
+    )
+//Tests for a instructions with register-register operand
+#define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg1, MASK_XLEN(val1)); \
+      LI(reg2, MASK_XLEN(val2)); \
+      inst destreg, reg1, reg2, imm; \
+    )
+
+//Tests for a instructions with register-register operand
+#define TEST_RI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg1, MASK_XLEN(val1)); \
+      LI(reg2, MASK_XLEN(val2)); \
+      inst destreg, reg1, reg2, imm; \
+    )
+
+//Tests for a instructions with register-register operand
+#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg1, MASK_XLEN(val1)); \
+      LI(reg2, MASK_XLEN(val2)); \
+      inst destreg, reg1, reg2; \
+    )
+//Tests for floating-point instructions with register-register operand
+#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
+      FLREG freg1, val_offset(valaddr_reg); \
+      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
+      csrrwi x0, frm, rm; \
+      inst destreg, freg1, freg2; \
+      csrrs flagreg, fflags, x0; \
+    )
+    
+//Tests for floating-point CMP instructions with register-register operand
+#define TEST_FCMP_OP(inst, destreg, freg1, freg2, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
+      FLREG freg1, val_offset(valaddr_reg); \
+      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
+      inst destreg, freg1, freg2; \
+      csrrs flagreg, fflags, x0; \
+    )
+
+//Tests for floating-point R4 type instructions
+#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
+      FLREG freg1, val_offset(valaddr_reg); \
+      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
+      FLREG freg3, val_offset+2*FREGWIDTH(valaddr_reg); \
+      csrrwi x0, frm, rm; \
+      inst destreg, freg1, freg2, freg3; \
+      csrrs flagreg, fflags, x0; \
+    )
+
+#define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \
+    TEST_CASE(testreg, x0, 0, swreg, offset, \
+      inst imm_val; \
+      )
+
+#define TEST_CMV_OP( inst, destreg, reg, correctval, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg, MASK_XLEN(val2)); \
+      inst destreg, reg; \
+      )
+
+#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(reg, MASK_XLEN(val2)); \
+      LI(destreg, MASK_XLEN(val1)); \
+      inst destreg, reg; \
+      )
+
+#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(destreg, MASK_XLEN(val)); \
+      inst destreg, imm; \
+      )
+
+#define TEST_CADDI4SPN_OP( inst, destreg, correctval, imm, swreg, offset, testreg) \
+    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
+      LI(x2, 0); \
+      inst destreg, x2,imm; \
+      )
+
+#define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \
+    LI(reg2, MASK_XLEN(val2))                  ;\
+    j 2f                                      ;\
+    addi tempreg, x0,0                        ;\
+    .option push                              ;\
+    .option norvc                             ;\
+1:  addi tempreg, tempreg,0x1                 ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 4 >= 0                      ;\
+        .set num,(imm/2)-4                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .if label == 3f                           ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+2:  inst reg2, label                          ;\
+    .option push                              ;\
+    .option norvc                             ;\
+    addi tempreg, tempreg, 0x2                ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 5 >= 0                      ;\
+        .set num,(imm/2)-5                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 1b                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+                                              ;\
+3:  addi tempreg, tempreg ,0x3                ;\
+                                              ;\
+4:  RVTEST_SIGUPD(swreg,tempreg,offset) 
+//SREG tempreg, offset(swreg);              
+
+
+#define TEST_CJ_OP(inst, tempreg, imm, label, swreg, offset) \
+    .option push                              ;\
+    .option norvc                             ;\
+    j 2f                                      ;\
+    addi tempreg,x0,0                         ;\
+1:  addi tempreg, tempreg,0x1                 ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 4 >= 0                      ;\
+        .set num,(imm/2)-4                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .if label == 3f                           ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+2:  inst label                          ;\
+    .option push                              ;\
+    .option norvc                             ;\
+    addi tempreg, tempreg, 0x2                           ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 5 >= 0                      ;\
+        .set num,(imm/2)-5                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 1b                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+                                              ;\
+3:  addi tempreg, tempreg, 0x3                ;\
+                                              ;\
+4:  RVTEST_SIGUPD(swreg,tempreg,offset) 
+//SREG tempreg, offset(swreg);
+
+#define TEST_CJAL_OP(inst, tempreg, imm, label, swreg, offset) \
+5:                                            ;\
+    j 2f                                      ;\
+                                              ;\
+    .option push                              ;\
+    .option norvc                             ;\
+1:  xori x1,x1, 0x1                           ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 4 >= 0                      ;\
+        .set num,(imm/2)-4                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .if label == 3f                           ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+2:  inst label                          ;\
+    .option push                              ;\
+    .option norvc                             ;\
+    xori x1,x1, 0x2                           ;\
+    j 4f                                      ;\
+    .option pop                               ;\
+    .if (imm/2) - 5 >= 0                      ;\
+        .set num,(imm/2)-5                    ;\
+    .else                                     ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+     .if label == 1b                          ;\
+        .set num,0                            ;\
+    .endif                                    ;\
+    .rept num                                 ;\
+    c.nop                                     ;\
+    .endr                                     ;\
+                                              ;\
+3:  xori x1,x1, 0x3                           ;\
+                                              ;\
+4: LA(tempreg, 5b)                             ;\
+   andi tempreg,tempreg,~(3)                  ;\
+    sub x1,x1,tempreg                          ;\
+  RVTEST_SIGUPD(swreg,x1,offset) 
+//SREG x1, offset(swreg);
+
+#define TEST_CJR_OP(tempreg, rs1, swreg, offset) \
+5:                                            ;\
+    LA(rs1, 3f)                                ;\
+                                              ;\
+2:  c.jr rs1                                  ;\
+    xori rs1,rs1, 0x2                           ;\
+    j 4f                                      ;\
+                                              ;\
+3:  xori rs1,rs1, 0x3                           ;\
+                                              ;\
+4: LA(tempreg, 5b)                             ;\
+   andi tempreg,tempreg,~(3)                  ;\
+    sub rs1,rs1,tempreg                          ;\
+    RVTEST_SIGUPD(swreg,rs1,offset) 
+//SREG rs1, offset(swreg);
+
+#define TEST_CJALR_OP(tempreg, rs1, swreg, offset) \
+5:                                            ;\
+    LA(rs1, 3f                               ) ;\
+                                              ;\
+2:  c.jalr rs1                                  ;\
+    xori x1,x1, 0x2                           ;\
+    j 4f                                      ;\
+                                              ;\
+3:  xori x1,x1, 0x3                           ;\
+                                              ;\
+4: LA(tempreg, 5b                            ) ;\
+   andi tempreg,tempreg,~(3)                  ;\
+    sub x1,x1,tempreg                          ;\
+    RVTEST_SIGUPD(swreg,x1,offset) 
+//SREG x1, offset(swreg);
+
+
+//--------------------------------- Migration aliases ------------------------------------------
+#ifdef RV_COMPLIANCE_RV32M
+  #warning "RV_COMPLIANCE_RV32M macro will be deprecated."
+  #define RVMODEL_BOOT \
+    RVTEST_IO_INIT; \
+    RV_COMPLIANCE_RV32M ; \
+    RV_COMPLIANCE_CODE_BEGIN
+#endif
+
+#define SWSIG(a, b)
+  
+#ifdef RV_COMPLIANCE_DATA_BEGIN
+  #warning "RV_COMPLIANCE_DATA_BEGIN macro deprecated in v0.2. Please use RVMODEL_DATA_BEGIN instead"
+  #define RVMODEL_DATA_BEGIN \
+    RV_COMPLIANCE_DATA_BEGIN
+#endif
+
+#ifdef RV_COMPLIANCE_DATA_END
+  #warning "RV_COMPLIANCE_DATA_END macro deprecated in v0.2. Please use RVMODEL_DATA_END instead"
+  #define RVMODEL_DATA_END \
+    RV_COMPLIANCE_DATA_END
+#endif
+
+#ifdef RV_COMPLIANCE_HALT
+  #warning "RV_COMPLIANCE_HALT macro deprecated in v0.2. Please use RVMODEL_HALT instead"
+  #define RVMODEL_HALT \
+    RV_COMPLIANCE_HALT
+#endif
+
+#ifdef RVTEST_IO_ASSERT_GPR_EQ
+  #warning "RVTEST_IO_ASSERT_GPR_EQ macro deprecated in v0.2. Please use RVMODEL_IO_ASSERT_GPR_EQ instead"
+  #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \
+    RVTEST_IO_ASSERT_GPR_EQ(_SP,_R, _I)
+#endif
+
+#ifdef RVTEST_IO_WRITE_STR 
+  #warning "RVTEST_IO_WRITE_STR macro deprecated in v0.2. Please use RVMODEL_IO_WRITE_STR instead"
+  #define RVMODEL_IO_WRITE_STR(_SP, _STR) \
+    RVTEST_IO_WRITE_STR(_SP, _STR)
+#endif
+
+#ifdef RVTEST_IO_INIT
+  #warning "RVTEST_IO_INIT is deprecated in v0.2. Please use RVMODEL_BOOT for initialization"
+#endif
+  
+#ifdef RVTEST_IO_CHECK
+  #warning "RVTEST_IO_CHECK is deprecated in v0.2.
+#endif
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/encoding.h
index 1ee1285be..88b2ac8fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/env/encoding.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/encoding.h
@@ -37,7 +37,6 @@
 #define MSTATUS_HPP         0x00000600
 #define MSTATUS_MPP         0x00001800
 #define MSTATUS_FS          0x00006000
-#define MSTATUS_VS          0x00000600
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
 #define MSTATUS_SUM         0x00040000
@@ -777,7 +776,6 @@
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
 #define CSR_INSTRET 0xc02
-#define CSR_HEDELEG 0x602
 #define CSR_HPMCOUNTER3 0xc03
 #define CSR_HPMCOUNTER4 0xc04
 #define CSR_HPMCOUNTER5 0xc05
@@ -807,8 +805,6 @@
 #define CSR_HPMCOUNTER29 0xc1d
 #define CSR_HPMCOUNTER30 0xc1e
 #define CSR_HPMCOUNTER31 0xc1f
-#define CSR_VSATP 0x280
-#define CSR_HSTATUS 0x600
 #define CSR_SSTATUS 0x100
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
@@ -819,9 +815,7 @@
 #define CSR_STVAL 0x143
 #define CSR_SIP 0x144
 #define CSR_SATP 0x180
-#define CSR_SEDELEG 0x102
 #define CSR_MSTATUS 0x300
-#define CSR_MSTATUSH 0x310
 #define CSR_MISA 0x301
 #define CSR_MEDELEG 0x302
 #define CSR_MIDELEG 0x303
@@ -1316,8 +1310,6 @@ DECLARE_CSR(stval, CSR_STVAL)
 DECLARE_CSR(sip, CSR_SIP)
 DECLARE_CSR(satp, CSR_SATP)
 DECLARE_CSR(mstatus, CSR_MSTATUS)
-DECLARE_CSR(mstatush, CSR_MSTATUSH)
-DECLARE_CSR(hstatus, CSR_HSTATUS)
 DECLARE_CSR(misa, CSR_MISA)
 DECLARE_CSR(medeleg, CSR_MEDELEG)
 DECLARE_CSR(mideleg, CSR_MIDELEG)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h
deleted file mode 100644
index be19bf88e..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/env/test_macros.h
+++ /dev/null
@@ -1,1139 +0,0 @@
-/* These are macros to manage storing signatures, selecting what to save       */
-/* keeping track of the hidden offset, and ensuring it doesn't overflow	       */
-/* They're useful across many tests, but generally for specific classes of ops */
-
-
-/* This function set up the Page table entry for Sv32 Translation scheme
-    Arguments:
-    _PAR: Register containing Physical Address
-    _PR: Register containing Permissions for Leaf PTE. 
-        (Note: No-leaf PTE (if-any) has only valid permssion (pte.v) set)
-    _TR0, _TR1, _TR2: Temporary registers used and modified by function
-    VA: Virtual address 
-    level: Level at which PTE would be setup
-        0: Two level translation
-        1: Superpage
-*/
-
-#define LEVEL0 0x00
-#define LEVEL1 0x01
-#define LEVEL2 0x02
-#define LEVEL3 0x03
-#define LEVEL4 0x04
-
-#define sv39 0x00
-#define sv48 0x01
-#define sv57 0x02
-
-#define CODE code_bgn_off
-#define DATA data_bgn_off
-#define SIG  sig_bgn_off
-#define VMEM vmem_bgn_off
-
-#define ALL_MEM_PMP                                               ;\
-    	li t2, -1                                                 ;\
-    	csrw pmpaddr0, t2                                         ;\
-    	li t2, 0x0F	                                          ;\
-    	csrw pmpcfg0, t2                                          ;\
-    	sfence.vma                                                ;
-
-#define SIGNATURE_AREA(TYPE,ARG1,ARG2, ...)                       ;\
-	LI (t0, ARG1)                                             ;\
-	.if(TYPE == CODE)                                         ;\
-        LI (t1, ARG2)                                             ;\
-	    sub t0, t0, t1                                        ;\
-            csrr sp, mscratch                                     ;\
-	    add t1,sp,t0                                          ;\
-	    csrw sscratch, t1                                     ;\
-    .else                                                         ;\
-        LA (t1, ARG2)                                             ;\
-	    sub t0, t0, t1                                        ;\
-    .endif                                                        ;\
-	LREG t1, TYPE+0*sv_area_sz(sp)                            ;\
-	add t2, t1, t0                                            ;\
-	SREG t2, TYPE+1*sv_area_sz(sp)                            ;
-
-//****NOTE: label `rvtest_Sroot_pg_tbl` must be declared after RVTEST_DATA_END
-//          in the test aligned at 4kiB (use .align 12)
-
-#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level)  	;\
-    srli _PAR, _PAR, 12                                         ;\
-    slli _PAR, _PAR, 10                                         ;\
-    or _PAR, _PAR, _PR                                          ;\
-    .if (level==1)                                              ;\
-        LA(_TR1, rvtest_Sroot_pg_tbl)                           ;\
-        .set vpn, ((VA>>22)&0x3FF)<<2                           ;\
-    .endif                                                      ;\
-    .if (level==0)                                              ;\
-        LA(_TR1, rvtest_slvl1_pg_tbl)                           ;\
-        .set vpn, ((VA>>12)&0x3FF)<<2                           ;\
-    .endif                                                      ;\
-    LI(_TR0, vpn)                                               ;\
-    add _TR1, _TR1, _TR0                                        ;\
-    SREG _PAR, 0(_TR1);                                          
-
-#define PTE_SETUP_RV64(_PAR, _PR, _TR0, _TR1, VA, level, mode)  ;\
-    srli _PAR, _PAR, 12                                         ;\
-    slli _PAR, _PAR, 10                                         ;\
-    or _PAR, _PAR, _PR                                          ;\
-    .if (mode == sv39)                                          ;\
-        .if (level == 2)                                        ;\
-            LA(_TR1, rvtest_Sroot_pg_tbl)                       ;\
-            .set vpn, ((VA >> 30) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 1)                                        ;\
-            LA(_TR1, rvtest_slvl1_pg_tbl)                       ;\
-            .set vpn, ((VA >> 21) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 0)                                        ;\
-            LA(_TR1, rvtest_slvl2_pg_tbl)                       ;\
-            .set vpn, ((VA >> 12) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-    .endif                                                      ;\
-    .if (mode == sv48)                                          ;\
-        .if (level == 3)                                        ;\
-            LA(_TR1, rvtest_Sroot_pg_tbl)                       ;\
-            .set vpn, ((VA >> 39) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 2)                                        ;\
-            LA(_TR1, rvtest_slvl1_pg_tbl)                       ;\
-            .set vpn, ((VA >> 30) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 1)                                        ;\
-            LA(_TR1, rvtest_slvl2_pg_tbl)                       ;\
-            .set vpn, ((VA >> 21) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 0)                                        ;\
-            LA(_TR1, rvtest_slvl3_pg_tbl)                       ;\
-            .set vpn, ((VA >> 12) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-    .endif                                                      ;\
-    .if (mode == sv57)                                          ;\
-        .if (level == 4)                                        ;\
-            LA(_TR1, rvtest_Sroot_pg_tbl)                       ;\
-            .set vpn, ((VA >> 48) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 3)                                        ;\
-            LA(_TR1, rvtest_slvl1_pg_tbl)                       ;\
-            .set vpn, ((VA >> 39) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 2)                                        ;\
-            LA(_TR1, rvtest_slvl2_pg_tbl)                       ;\
-            .set vpn, ((VA >> 30) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 1)                                        ;\
-            LA(_TR1, rvtest_slvl3_pg_tbl)                       ;\
-            .set vpn, ((VA >> 21) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-        .if (level == 0)                                        ;\
-            LA(_TR1, rvtest_slvl3_pg_tbl)                       ;\
-            .set vpn, ((VA >> 12) & 0x1FF) << 3                 ;\
-        .endif                                                  ;\
-    .endif                                                      ;\
-    LI(_TR0, vpn)                                               ;\
-    add _TR1, _TR1, _TR0                                        ;\
-    SREG _PAR, 0(_TR1)                                          ;
-
-#define PTE_PERMUPD_RV32(_PR, _TR0, _TR1, VA, level)          	;\
-    .if (level==1)                                              ;\
-        LA(_TR1, rvtest_Sroot_pg_tbl)                           ;\
-        .set vpn, ((VA>>22)&0x3FF)<<2                           ;\
-    .endif                                                      ;\
-    .if (level==0)                                              ;\
-        LA(_TR1, rvtest_slvl1_pg_tbl)                           ;\
-        .set vpn, ((VA>>12)&0x3FF)<<2                           ;\
-    .endif                                                      ;\
-    LI(_TR0, vpn)                                               ;\
-    add _TR1, _TR1, _TR0                                        ;\
-    LREG _TR0, 0(_TR1)                                          ;\
-    srli _TR0, _TR0, 10                                         ;\
-    slli _TR0, _TR0, 10                                         ;\
-    or _TR0, _TR0, _PR                                          ;\
-    SREG _TR0, 0(_TR1)                                          ;   
-
-#define SATP_SETUP_SV32 ;\
-    LA(t6, rvtest_Sroot_pg_tbl) ;\
-    LI(t5, SATP32_MODE) ;\
-    srli t6, t6, 12 ;\
-    or t6, t6, t5  ;\
-    csrw satp, t6   ;
-
-#define SATP_SETUP_RV64(MODE)                                   ;\
-    LA(t6, rvtest_Sroot_pg_tbl)                                 ;\
-    .if (MODE == sv39)                                          ;\
-    LI(t5, (SATP64_MODE) & (SATP_MODE_SV39 << 60))              ;\
-    .endif                                                      ;\
-    .if (MODE == sv48)                                          ;\
-    LI(t5, (SATP64_MODE) & (SATP_MODE_SV48 << 60))              ;\
-    .endif                                                      ;\
-    .if (MODE == sv57)                                          ;\
-    LI(t5, (SATP64_MODE) & (SATP_MODE_SV57 << 60))              ;\
-    .endif                                                      ;\
-    .if (MODE == sv64)                                          ;\
-    LI(t5, (SATP64_MODE) & (SATP_MODE_SV64 << 60))              ;\
-    .endif                                                      ;\
-    srli t6, t6, 12                                             ;\
-    or t6, t6, t5                                               ;\
-    csrw satp, t6                                               ;
-
-//Tests for atomic memory operation(AMO) instructions
-#define TEST_AMO_OP(inst, destreg, origptr, reg2, origval, updval, sigptr, ...) ;\
-      .if NARG(__VA_ARGS__) == 1			;\
-	.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
-      .endif						;\
-      LI(reg2, MASK_XLEN(origval))			;\
-      RVTEST_SIGUPD(sigptr, reg2) /*Write original AMO src */ ;\
-      LI(reg2, MASK_XLEN(updval)) ;\
-      addi origptr, sigptr, offset-REGWIDTH /* Calculate where orig AMO src is stored */ ;\
-      inst destreg, reg2, (origptr) /*origval -> destreg; updated val -> (origptr) */ ;\
-      RVTEST_SIGUPD(sigptr, destreg) /* write original AMO val */
-
-
-
-#define NAN_BOXED(__val__,__width__,__max__)	;\
-    .if __width__ == 32				;\
-	.word __val__				;\
-    .else					;\
-	.dword __val__				;\
-    .endif					;\
-    .if __max__ > __width__			;\
-	.set pref_bytes,(__max__-__width__)/32	;\
-    .else					;\
-	.set pref_bytes, 0			;\
-    .endif					;\
-    .rept pref_bytes				;\
-	.word 0xffffffff			;\
-    .endr					;
-
-#define ZERO_EXTEND(__val__,__width__,__max__)	;\
-    .if __max__ > __width__			;\
-	.set pref_bytes,(__max__-__width__)/32	;\
-    .else					;\
-	.set pref_bytes, 0			;\
-    .endif					;\
-    .rept pref_bytes				;\
-	.word 0					;\
-    .endr					;\
-    .if __width__ == 32				;\
-	.word __val__				;\
-    .else					;\
-	.dword __val__				;\
-    .endif;
-
-#define RVTEST_FP_ENABLE()			;\
- LI(a0, (MSTATUS_FS & (MSTATUS_FS >> 1)))	;\
- csrs mstatus, a0				;\
- csrwi fcsr, 0
-
-// This macro is for vector 
-#define RVTEST_VXSAT_ENABLE()			;\
- LI(a0, (MSTATUS_VS & (MSTATUS_VS >> 1)))	;\
- csrs mstatus, a0				;\
- clrov
-
-/* RVTEST_SIGBASE(reg, label) initializes to label and clears offset */
-#define RVTEST_SIGBASE(_R,_TAG)			;\
-  LA(_R,_TAG)					;\
-  .set offset,0
-
-// This macro is loading data from memory with any offset value
-// This macro is loading data from memory with any offset value
-#define LOAD_MEM_VAL(_LINST, _AREG, _RD, _OFF, _TREG) ;\
-   .if (((_OFF & ~0x07FF)==  0) |((_OFF |  0x07FF)== -1))                       ;\
-   _LINST _RD, _OFF(_AREG) /* yes, it fits */         ;\
-  .else                    /* no, needs base adj   */ ;\
-  .set  _off,  SEXT_IMM(_OFF) /* strip off hi bits */ ;\
-  .set cry, BIT(_off,11)<<12    ;\
-   LI(  _TREG, (_OFF & ~0x0FFF)+cry) /* strip off hi bits*/ ;\
-    add  _AREG, _AREG, _TREG /* modified temp base*/ ;\
-    _LINST _RD, _off(_AREG)                          ;\
-    sub  _AREG, _AREG, _TREG /* undo modification */ ;\
- .endif
-  /* this function ensures individual sig stores don't exceed offset limits  */
-  /* if they would, update the base and reduce offset by 2048 - _SZ	     */
-  /* an option is to pre-incr offset if there was a previous signature store */
-#define CHK_OFFSET(_BREG, _SZ, _PRE_INC)		;\
-  .if (_PRE_INC!=0)					;\
-    .set offset, offset+_SZ				;\
-  .endif						;\
-  .if offset >= 2048					;\
-     addi   _BREG,  _BREG,   (2048 - _SZ)		;\
-     .set   offset, offset - (2048 - _SZ)		;\
-  .endif
-
- /* automatically adjust base and offset if offset gets too big, resetting offset				 */
- /* RVTEST_SIGUPD(basereg, sigreg)	  stores sigreg at offset(basereg) and updates offset by regwidth	 */
- /* RVTEST_SIGUPD(basereg, sigreg,newoff) stores sigreg at newoff(basereg) and updates offset to regwidth+newoff */
-#define RVTEST_SIGUPD(_BR,_R,...)			;\
-  .if NARG(__VA_ARGS__) == 1				;\
-	.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
-  .endif						;\
-  CHK_OFFSET(_BR, REGWIDTH,0)				;\
-  SREG _R,offset(_BR)					;\
-  .set offset,offset+REGWIDTH
-
-/* RVTEST_SIGUPD_F(basereg, sigreg,flagreg,newoff)			 */
-/* This macro is used to store the signature values of (32 & 64) F and D */
-/* teats which use TEST_(FPSR_OP, FPIO_OP, FPRR_OP, FPR4_OP) opcodes	 */
-/* It stores both an Xreg and an Freg, first adjusting base & offset to	 */
-/* to keep offset < 2048. SIGALIGN is set to the max(FREGWIDTH, REGWIDTH)*/
-/* _BR - Base Reg, _R - FReg, _F - Fstatus Xreg				 */
-#define RVTEST_SIGUPD_F(_BR,_R,_F,...)			;\
-  .if NARG(__VA_ARGS__) == 1				;\
-     .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
-  .endif						;\
-  .if (offset&(SIGALIGN-1))!=0				;\
-/* Throw warnings then modify offset to target */	;\
-     .warning "Incorrect signature Offset Alignment."	;\
-     .set offset, offset&(SIGALIGN-1)+SIGALIGN		;\
-  .endif						;\
-  CHK_OFFSET(_BR, SIGALIGN, 0)				;\
-  FSREG _R,offset(_BR)					;\
-  CHK_OFFSET(_BR, SIGALIGN, 1)				;\
-  SREG _F,offset(_BR)					;\
-  .set offset,offset+SIGALIGN
- 
-/* RVTEST_SIGUPD_FID(basereg, sigreg,flagreg,newoff)			*/
-/* This macro stores the signature values of (32 & 64) F & D insts	*/
-/* which uses TEST_(FPID_OP, FCMP_OP) ops				*/
-/* It stores two integer registers. SigReg is stored @offset[BaseReg],	*/
-/* FlagReg at offset+Regwidth[BaseReg]. It updates offset by 2*regwidth	*/
-/* and post increments so repeated uses store sig values sequentially	*/
-/*  _BR - Base Reg, _R - Signature reg, _F - Flag reg			*/
-#define RVTEST_SIGUPD_FID(_BR,_R,_F,...)		;\
-  .if NARG(__VA_ARGS__) == 1				;\
-     .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
-  .endif						;\
-  .if (offset&(SIGALIGN-1))!=0				;\
-/* Throw warnings then modify offset to target */	;\
-     .warning "Signature Incorrect Offset Alignment."	;\
-     .set offset, offset&(SIGALIGN-1)+SIGALIGN		;\
-  .endif						;\
-  CHK_OFFSET(_BR, REGWIDTH, 0)				;\
-  SREG _R,offset(_BR)					;\
-  CHK_OFFSET(_BR, REGWIDTH, 1)				;\
-  SREG _F,offset(_BR)					;\
-  .set offset,offset+REGWIDTH
-
-
-// for updating signatures that include flagreg for P-ext saturation instructions (RV32/RV64).
-#define RVTEST_SIGUPD_PK(_BR,_R,_F,...)			;\
-  .if NARG(__VA_ARGS__) == 1				;\
-      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
-  .endif						;\
-  .if (offset & (REGWIDTH-1)) != 0			;\
-      .warning "Signature Incorrect Offset Alignment."	;\
-     .set offset, offset&(SIGALIGN-1)+SIGALIGN		;\
-  .endif						;\
-      CHK_OFFSET(_BR,REGWIDTH,0)			;\
-      SREG _R,offset(_BR)				;\
-      CHK_OFFSET(_BR,REGWIDTH,1)			;\
-      SREG _F,offset(_BR)				;\
-      .set offset,offset+(REGWIDTH)
-
-// for updating signatures when 'rd' is a paired register (64-bit)
-//  in Zpsfoperand extension in RV32; this reuses RVTEST_SIGUPD_PK()
-#define RVTEST_SIGUPD_P64(_BR,_R,_R_HI,...)				;\
-  .if NARG(__VA_ARGS__) == 0						;\
-      RVTEST_SIGUPD_PK(_BR,_R,_R_HI)					;\
-  .else									;\
-      RVTEST_SIGUPD_PK(_BR,_R,_R_HI,_ARG1(__VA_OPT__(__VA_ARGS__,0)))	;\
-  .endif
-
-// for updating signatures that include flagreg when 'rd' is a 
-// paired register (64-bit) in Zpsfoperand extension in RV32.
-#define RVTEST_SIGUPD_PK64(_BR,_R,_R_HI,_F,...)			;\
-      rdov _F							;\
-  .if NARG(__VA_ARGS__) == 1					;\
-      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))		;\
-  .endif							;\
-  .if (offset & (REGWIDTH-1)) != 0				;\
-      .warning "Incorrect Offset Alignment for Signature."	;\
-     .set offset, offset&(SIGALIGN-1)+SIGALIGN			;\
-  .endif							;\
-      CHK_OFFSET(_BR,REGWIDTH,0)				;\
-      SREG _R,offset(_BR)					;\
-      CHK_OFFSET(_BR,REGWIDTH,1)				;\
-      SREG _R_HI,offset(_BR)					;\
-      CHK_OFFSET(_BR,REGWIDTH,1)				;\
-      SREG _F,offset(_BR)					;\
-      .set offset,offset+(REGWIDTH)
-
-
-
-  /* DEPRECATE this is redundant with RVTEST_BASEUPD(BR,_NR),	*/
-  /* except it doesn't correct for offset overflow while moving */
-#define RVTEST_VALBASEMOV(_NR,_BR)			;\
-  add _NR, _BR, x0;
-
-#define RVTEST_VALBASEUPD(_BR,...)			;\
-  .if NARG(__VA_ARGS__) == 0				;\
-      addi _BR,_BR,2040					;\
-  .endif						;\
-  .if NARG(__VA_ARGS__) == 1				;\
-      LA(_BR,_ARG1(__VA_ARGS__,x0))			;\
-  .endif
-
-/*
- * RVTEST_BASEUPD(base reg) - updates the base register the last signature address + REGWIDTH
- * RVTEST_BASEUPD(base reg, new reg) - moves value of the next signature region to update into new reg
- * The hidden variable offset is reset always
-*/
-
-#define RVTEST_BASEUPD(_BR,...)				;\
- /* deal with case where offset>=2047 */		;\
-       .set corr 2048-REGWIDTH				;\
-    .if offset <2048 					;\
-       .set corr offset					;\
-    .endif						;\
-    .set offset, offset-corr				;\
-							;\
-    .if NARG(__VA_ARGS__) == 0				;\
-	addi _BR,		    _BR, corr		;\
-    .else						;\
-	addi _ARG1(__VA_ARGS__,x0) ,_BR, corr		;\
-    .endif				
-
-//==============================================================================
-// This section borrows from Andrew's from Andrew Waterman's risc-v test macros
-// They are used to generate tests; some are op specific, some format specific
-//==============================================================================
-
-#define TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj)	;\
-5:					;\
-    LA(rd,5b)				;\
-    .if adj & 1 == 1			;\
-    LA(rs1, 3f-imm+adj-1)		;\
-    jalr rd, imm+1(rs1)			;\
-    .else				;\
-    LA(rs1, 3f-imm+adj)			;\
-    jalr rd, imm(rs1)			;\
-    .endif				;\
-    nop					;\
-    nop					;\
-    xori rd,rd, 0x2			;\
-    j 4f				;\
-					;\
-3:  .if adj & 2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    xori rd,rd, 0x3			;\
-    j 4f				;\
-    .if adj&2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-					;\
-4: LA(tempreg, 5b)			;\
-   andi tempreg,tempreg,~(3)		;\
-    sub rd,rd,tempreg			;\
-    RVTEST_SIGUPD(swreg,rd,offset) 
-
-
-#define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)	;\
-5:					;\
-    LA(tempreg, 2f)			;\
-    jalr x0,0(tempreg)			;\
-6:  LA(tempreg, 4f)			;\
-    jalr x0,0(tempreg)			;\
-1:  .if adj & 2 == 2			;\
-    .ifc label, 1b			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    .endif				;\
-    xori rd,rd, 0x1			;\
-    beq x0,x0,6b			;\
-    .if adj & 2 == 2			;\
-    .ifc label, 1b			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    .endif				;\
-    .if (imm/2) - 2 >= 0		;\
-	.set num,(imm/2)-2		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 3f			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    nop					;\
-    .endr				;\
-					;\
-2:  jal rd, label+(adj)			;\
-    .if adj & 2 == 2			;\
-    nop					;\
-    nop					;\
-    .endif				;\
-    xori rd,rd, 0x2			;\
-    j 4f				;\
-    .if (imm/2) - 3 >= 0		;\
-	.set num,(imm/2)-3		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-    .ifc label, 1b			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    nop					;\
-    .endr				;\
-3:  .if adj & 2 == 2			;\
-    .ifc label, 3f			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    .endif				;\
-    xori rd,rd, 0x3			;\
-    LA(tempreg, 4f)			;\
-    jalr x0,0(tempreg)			;\
-    .if adj & 2 == 2			;\
-    .ifc label, 3f			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    .endif				;\
-4: LA(tempreg, 5b)			;\
-   andi tempreg,tempreg,~(3)		;\
-    sub rd,rd,tempreg			;\
-    RVTEST_SIGUPD(swreg,rd,offset) 
-//SREG rd, offset(swreg);
-
-#define TEST_BRANCH_OP(inst, tempreg, reg1, reg2, val1, val2, imm, label, swreg, offset,adj) \
-    LI(reg1, MASK_XLEN(val1))		;\
-    LI(reg2, MASK_XLEN(val2))		;\
-    addi tempreg,x0,0			;\
-    j 2f				;\
-					;\
-1:  .if adj & 2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    addi tempreg,tempreg, 0x1		;\
-    j 4f				;\
-    .if adj & 2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    .if (imm/2) - 2 >= 0		;\
-	.set num,(imm/2)-2		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 3f			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    nop					;\
-    .endr				;\
-					;\
-2:  inst reg1, reg2, label+adj		;\
-    addi tempreg, tempreg,0x2		;\
-    j 4f				;\
-    .if (imm/4) - 3 >= 0		;\
-	.set num,(imm/4)-3		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 1b			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    nop					;\
-    .endr				;\
-					;\
-3:  .if adj & 2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-    addi tempreg, tempreg,0x3		;\
-    j 4f				;\
-    .if adj&2 == 2			;\
-    .fill 2,1,0x00			;\
-    .endif				;\
-					;\
-4:   RVTEST_SIGUPD(swreg,tempreg,offset) 
-
-
-#define TEST_STORE(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj)	;\
-LI(rs2,rs2_val)				;\
-addi rs1,swreg,offset+adj		;\
-LI(testreg,imm_val)			;\
-sub rs1,rs1,testreg			;\
-inst rs2, imm_val(rs1)			;\
-nop					;\
-nop									    
-
-#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj);\
-LA(rs1,rvtest_data+(index*4)+adj-imm_val);\
-inst destreg, imm_val(rs1)		;\
-nop					;\
-nop					;\
-RVTEST_SIGUPD(swreg,destreg,offset) 
-
-#define TEST_STORE_F(swreg,testreg,fcsr_val,rs1,rs2,imm_val,offset,inst,adj,flagreg,valaddr_reg, val_offset);\
-LOAD_MEM_VAL(FLREG, valaddr_reg, rs2, val_offset, testreg);\
-addi rs1,swreg,offset+adj		;\
-LI(testreg,imm_val)			;\
-sub rs1,rs1,testreg			;\
-inst rs2, imm_val(rs1)			;\
-nop					;\
-nop					;\
-csrr flagreg, fcsr			;\
-RVTEST_SIGUPD(swreg,flagreg,offset+SIGALIGN)
-
-#define TEST_LOAD_F(swreg,testreg,fcsr_val,rs1,destreg,imm_val,inst,adj,flagreg)	;\
-LA(rs1,rvtest_data+adj-imm_val)		;\
-LI(testreg, fcsr_val)			;\
-csrw fcsr, testreg			;\
-inst destreg, imm_val(rs1)		;\
-nop					;\
-nop					;\
-csrr flagreg, fcsr			;\
-RVTEST_SIGUPD_F(swreg,destreg,flagreg) 
-
-#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val)                               ;\
-LI(rs1,imm_val&(RVMODEL_CBZ_BLOCKSIZE-1))                                   ;\
-add rs1,rs1,swreg                                                           ;\
-inst (rs1)                                                                  ;\
-nop                                                                         ;\
-nop                                                                         ;\
-ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
-
-#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\
-    LI(TEMP_REG,VAL)			;\
-    and TEMP_REG,TEMP_REG,MASK_REG	;\
-    csrr DEST_REG,ADDRESS		;\
-    and DEST_REG,DEST_REG,NEG_MASK_REG	;\
-    or TEMP_REG,TEMP_REG,DEST_REG	;\
-    csrw ADDRESS,TEMP_REG		;\
-    csrr DEST_REG,ADDRESS		;\
-    RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET)
-
-
-#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... )	;\
-    code				;\
-    RVTEST_SIGUPD(swreg,destreg,offset)	;\
-    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
-
-#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, code... )	;\
-    code					;\
-    RVTEST_SIGUPD_F(swreg,destreg,flagreg)	;\
-    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
-    
-#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, code... )	;\
-    code; \
-    RVTEST_SIGUPD_FID(swreg,destreg,flagreg)	;\
-    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
-
-#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg)	;\
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LA testreg, 1f			;\
-      1:				;\
-      inst destreg, imm			;\
-      sub destreg, destreg, testreg	;\
-      )
-
-//Tests for instructions with register-immediate operand
-#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg)	;\
-    TEST_CASE(testreg, destreg, correctval, swreg, offset,	 ;\
-      LI(reg, MASK_XLEN(val))		;\
-      inst destreg, reg, SEXT_IMM(imm)	;\
-    )
-
-//Tests for floating-point instructions with a single register operand
-#define TEST_FPSR_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
-      LI(testreg, fcsr_val)	;\
-      csrw fcsr, testreg	;\
-      inst destreg, freg, rm	;\
-      csrr flagreg, fcsr	;\
-    )
-
-//Tests for floating-point instructions with a single register operand
-//This variant does not take the rm field and set it while writing the instruction
-#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,		 \
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg			;\
-      csrr flagreg, fcsr			;\
-    )
-    
-//Tests for floating-point instructions with a single register operand and integer destination register
-#define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \
-    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg,		 \
-      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg, rm			;\
-      csrr flagreg, fcsr			;\
-      )
-    
-//Tests for floating-point instructions with a single register operand and integer operand register
-#define TEST_FPIO_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,		 \
-      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg, rm			;\
-      csrr flagreg, fcsr			;\
-    )
-
-//Tests for floating-point instructions with a single register operand and integer destination register
-//This variant does not take the rm field and set it while writing the instruction
-#define TEST_FPID_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg,		 \
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg			;\
-      csrr flagreg, fcsr			;\
-      )
-    
-//Tests for floating-point instructions with a single register operand and integer operand register
-//This variant does not take the rm field and set it while writing the instruction
-#define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,		 \
-      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg			;\
-      csrr flagreg, fcsr			;\
-    )
-
-//Tests for instructions with register-register-immediate operands
-#define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg1, MASK_XLEN(val1))			;\
-      LI(reg2, MASK_XLEN(val2))			;\
-      inst destreg, reg1, reg2, imm		;\
-    )
-
-//Tests for a instructions with register-register operand
-#define TEST_RI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg1, MASK_XLEN(val1))			;\
-      LI(reg2, MASK_XLEN(val2))			;\
-      inst destreg, reg1, reg2, imm		;\
-    )
-
-//Tests for a instructions with register-register operand
-#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg1, MASK_XLEN(val1))			;\
-      LI(reg2, MASK_XLEN(val2))			;\
-      inst destreg, reg1, reg2			;\
-    )
-//Tests for floating-point instructions with register-register operand
-//This variant does not take the rm field and set it while writing the instruction
-#define TEST_FPRR_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,			 \
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg)		;\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg1, freg2		;\
-      csrr flagreg, fcsr			;\
-    )
-
-//Tests for floating-point instructions with register-register operand
-#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,			\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg)		;\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg1, freg2, rm		;\
-      csrr flagreg, fcsr			;\
-    )
-    
-//Tests for floating-point CMP instructions with register-register operand
-#define TEST_FCMP_OP(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg,			 \
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg)		;\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg)	;\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg1, freg2		;\
-      csrr flagreg, fcsr			;\
-    )
-
-//Tests for floating-point R4 type instructions
-#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm , fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,			\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg)		;\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg)	;\
-      LOAD_MEM_VAL(FLREG, valaddr_reg, freg3, (val_offset+2*FREGWIDTH), testreg);\
-      li testreg, fcsr_val; csrw fcsr, testreg	;\
-      inst destreg, freg1, freg2, freg3, rm	;\
-      csrr flagreg, fcsr			;\
-    )
-
-#define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \
-    TEST_CASE(testreg, x0, 0, swreg, offset,	 \
-      inst imm_val				;\
-      )
-
-//Tests for instructions with register-immediate operand and update the saturation flag
-#define TEST_PKIMM_OP( inst, destreg, reg, correctval, val, imm, flagreg, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg, MASK_XLEN(val))		;\
-      inst destreg, reg, SEXT_IMM(imm)	;\
-      rdov flagreg			;\
-    )
-
-//Tests for instructions with register-register operand and update the saturation flag
-#define TEST_PKRR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, flagreg, swreg, offset, testreg) \
-    LI(reg1, MASK_XLEN(val1))		;\
-    LI(reg2, MASK_XLEN(val2))		;\
-    inst destreg, reg1, reg2		;\
-    rdov flagreg			;\
-    RVTEST_SIGUPD_PK(swreg, destreg, flagreg, offset)	;\
-    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
-
-//Tests for instructions with a single register operand and update the saturation flag
-#define TEST_PKR_OP( inst, destreg, reg, correctval, val, flagreg, swreg, offset, testreg) \
-    LI(reg, MASK_XLEN(val))	;\
-    inst destreg, reg		;\
-    rdov flagreg		;\
-    RVTEST_SIGUPD_PK(swreg,destreg,flagreg,offset)	;\
-    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
-
-#if __riscv_xlen == 32
-//Tests for a instruction with register pair operands for all its three operands
-#define TEST_P64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))		;\
-      LI(reg1_hi, MASK_XLEN(val1_hi))	;\
-      LI(reg2, MASK_XLEN(val2))		;\
-      LI(reg2_hi, MASK_XLEN(val2_hi))	;\
-      inst destreg, reg1, reg2		;\
-      RVTEST_SIGUPD_P64(swreg,destreg, destreg_hi, offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi)
-
-#define TEST_PK64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, flagreg, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))		;\
-      LI(reg1_hi, MASK_XLEN(val1_hi))	;\
-      LI(reg2, MASK_XLEN(val2))		;\
-      LI(reg2_hi, MASK_XLEN(val2_hi))	;\
-      inst destreg, reg1, reg2		;\
-      RVTEST_SIGUPD_PK64(swreg,destreg, destreg_hi, flagreg, offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)		;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi)
-
-#define TEST_P64_PPN_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, correctval, correctval_hi, val1, val1_hi, val2, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))		;\
-      LI(reg1_hi, MASK_XLEN(val1_hi))	;\
-      LI(reg2, MASK_XLEN(val2))		;\
-      inst destreg, reg1, reg2		;\
-      RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi)
-
-#define TEST_P64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))		;\
-      LI(reg2, MASK_XLEN(val2))		;\
-      inst destreg, reg1, reg2		;\
-      RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi)
-
-#define TEST_PK64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, flagreg, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))		;\
-      LI(reg2, MASK_XLEN(val2))		;\
-      inst destreg, reg1, reg2		;\
-      RVTEST_SIGUPD_PK64(swreg, destreg, destreg_hi, flagreg, offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)		;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi)
-
-#define TEST_P64_NPN_OP_32(inst, destreg, reg1, reg1_hi, reg2, correctval, val1, val1_hi, val2, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))			;\
-      LI(reg1_hi, MASK_XLEN(val1_hi))		;\
-      LI(reg2, MASK_XLEN(val2))			;\
-      inst destreg, reg1, reg2			;\
-      RVTEST_SIGUPD(swreg,destreg,offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval);
-
-#define TEST_P64_NP_OP_32(inst, destreg, reg1, reg1_hi, correctval, val1, val1_hi, imm_val, swreg, offset, testreg) \
-      LI(reg1, MASK_XLEN(val1))			;\
-      LI(reg1_hi, MASK_XLEN(val1_hi))		;\
-      inst destreg, reg1, imm_val		;\
-      RVTEST_SIGUPD(swreg,destreg,offset)	;\
-      RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval);
-
-//Tests for a instruction with pair register rd, pair register rs1 and pair register rs2
-#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \
-    TEST_P64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg)
-#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \
-    TEST_PK64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg)
-//Tests for a instruction with pair register rd, pair register rs1 and normal register rs2
-#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \
-    TEST_P64_PPN_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg)
-//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2
-#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \
-    TEST_P64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg)
-//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2
-#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \
-    TEST_PK64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg)
-//Tests for a instruction with normal register rd, pair register rs1 and normal register rs2
-#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \
-    TEST_P64_NPN_OP_32(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg)
-//Tests for a instruction with normal register rd, pair register rs1
-#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \
-    TEST_P64_NP_OP_32(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg)
-
-#else
-
-// When in rv64, there are no instructions with pair operand, so Macro is redefined to normal TEST_RR_OP
-#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \
-    TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg)
-#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \
-    TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg)
-#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \
-    TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg)
-#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \
-    TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg)
-#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \
-    TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg)
-#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \
-    TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg)
-#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \
-    TEST_IMM_OP(inst, rd, rs1, correctval, rs1_val, imm_val, swreg, offset, testreg)
-
-#endif
-
-
-
-
-#define TEST_CMV_OP( inst, destreg, reg, correctval, val2, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg, MASK_XLEN(val2))		;\
-      inst destreg, reg			;\
-      )
-
-#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(reg, MASK_XLEN(val2))		;\
-      LI(destreg, MASK_XLEN(val1))	;\
-      inst destreg, reg			;\
-      )
-
-#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(destreg, MASK_XLEN(val))	;\
-      inst destreg, imm			;\
-      )
-
-#define TEST_CADDI4SPN_OP( inst, destreg, correctval, imm, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(x2, 0)				;\
-      inst destreg, x2,imm		;\
-      )
-
-//Tests for instructions with single (rd/rs1) register operand.
-#define TEST_CRD_OP(inst, destreg, correctval, val1, swreg, offset, testreg) \
-    TEST_CASE(testreg, destreg, correctval, swreg, offset, \
-      LI(destreg, MASK_XLEN(val1))		;\
-      inst destreg		;\
-      )
-
-//Tests for instructions with a destination and single source register operand
-#define TEST_RD_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) \
-  TEST_CMV_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg)
-
-#define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \
-    LI(reg2, MASK_XLEN(val2))		;\
-    j 2f				;\
-    addi tempreg, x0,0			;\
-    .option push			;\
-    .option norvc			;\
-1:  addi tempreg, tempreg,0x1		;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 4 >= 0		;\
-	.set num,(imm/2)-4		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-    .ifc label, 3f			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-2:  inst reg2, label			;\
-    .option push			;\
-    .option norvc			;\
-    addi tempreg, tempreg, 0x2		;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 5 >= 0		;\
-	.set num,(imm/2)-5		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 1b			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-					;\
-3:  addi tempreg, tempreg ,0x3		;\
-					;\
-4:  RVTEST_SIGUPD(swreg,tempreg,offset) 
-
-#define TEST_CJ_OP(inst, tempreg, imm, label, swreg, offset) \
-    .option push			;\
-    .option norvc			;\
-    j 2f				;\
-    addi tempreg,x0,0			;\
-1:  addi tempreg, tempreg,0x1		;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 4 >= 0		;\
-	.set num,(imm/2)-4		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-    .ifc label, 3f			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-2:  inst label				;\
-    .option push			;\
-    .option norvc			;\
-    addi tempreg, tempreg, 0x2		;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 5 >= 0		;\
-	.set num,(imm/2)-5		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 1b			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-					;\
-3:  addi tempreg, tempreg, 0x3		;\
-					;\
-4:  RVTEST_SIGUPD(swreg,tempreg,offset) 
-
-#define TEST_CJAL_OP(inst, tempreg, imm, label, swreg, offset) \
-5:					;\
-    j 2f				;\
-					;\
-    .option push			;\
-    .option norvc			;\
-1:  xori x1,x1, 0x1			;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 4 >= 0		;\
-	.set num,(imm/2)-4		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-    .ifc label, 3f			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-2:  inst label				;\
-    .option push			;\
-    .option norvc			;\
-    xori x1,x1, 0x2			;\
-    j 4f				;\
-    .option pop				;\
-    .if (imm/2) - 5 >= 0		;\
-	.set num,(imm/2)-5		;\
-    .else				;\
-	.set num,0			;\
-    .endif				;\
-     .ifc label, 1b			;\
-	.set num,0			;\
-    .endif				;\
-    .rept num				;\
-    c.nop				;\
-    .endr				;\
-					;\
-3:  xori x1,x1, 0x3			;\
-					;\
-4: LA(tempreg, 5b)			;\
-   andi tempreg,tempreg,~(3)		;\
-    sub x1,x1,tempreg			;\
-  RVTEST_SIGUPD(swreg,x1,offset) 
-
-#define TEST_CJR_OP(tempreg, rs1, swreg, offset) \
-5:					;\
-    LA(rs1, 3f)				;\
-					;\
-2:  c.jr rs1				;\
-    xori rs1,rs1, 0x2			;\
-    j 4f				;\
-					;\
-3:  xori rs1,rs1, 0x3			;\
-					;\
-4: LA(tempreg, 5b)			;\
-   andi tempreg,tempreg,~(3)		;\
-    sub rs1,rs1,tempreg			;\
-    RVTEST_SIGUPD(swreg,rs1,offset) 
-
-#define TEST_CJALR_OP(tempreg, rs1, swreg, offset) \
-5:					;\
-    LA(rs1, 3f)				;\
-					;\
-2:  c.jalr rs1				;\
-    xori x1,x1, 0x2			;\
-    j 4f				;\
-					;\
-3:  xori x1,x1, 0x3			;\
-					;\
-4: LA(tempreg, 5b)			;\
-   andi tempreg,tempreg,~(3)		;\
-    sub x1,x1,tempreg			;\
-    RVTEST_SIGUPD(swreg,x1,offset) 
-
-
-//--------------------------------- Migration aliases ------------------------------------------
-#ifdef RV_COMPLIANCE_RV32M
-  #warning "RV_COMPLIANCE_RV32M macro will be deprecated."
-  #define RVMODEL_BOOT	 \
-    RVTEST_IO_INIT	;\
-    RV_COMPLIANCE_RV32M ;\
-    RV_COMPLIANCE_CODE_BEGIN
-#endif
-
-#define SWSIG(a, b)
-  
-#ifdef RV_COMPLIANCE_DATA_BEGIN
-  #warning "RV_COMPLIANCE_DATA_BEGIN macro deprecated in v0.2. Please use RVMODEL_DATA_BEGIN instead"
-  #define RVMODEL_DATA_BEGIN \
-    RV_COMPLIANCE_DATA_BEGIN
-#endif
-
-#ifdef RV_COMPLIANCE_DATA_END
-  #warning "RV_COMPLIANCE_DATA_END macro deprecated in v0.2. Please use RVMODEL_DATA_END instead"
-  #define RVMODEL_DATA_END \
-    RV_COMPLIANCE_DATA_END
-#endif
-
-#ifdef RV_COMPLIANCE_HALT
-  #warning "RV_COMPLIANCE_HALT macro deprecated in v0.2. Please use RVMODEL_HALT instead"
-  #define RVMODEL_HALT \
-    RV_COMPLIANCE_HALT
-#endif
-
-#ifdef RVTEST_IO_ASSERT_GPR_EQ
-  #warning "RVTEST_IO_ASSERT_GPR_EQ macro deprecated in v0.2. Please use RVMODEL_IO_ASSERT_GPR_EQ instead"
-  #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \
-    RVTEST_IO_ASSERT_GPR_EQ(_SP,_R, _I)
-#endif
-
-#ifdef RVTEST_IO_WRITE_STR 
-  #warning "RVTEST_IO_WRITE_STR macro deprecated in v0.2. Please use RVMODEL_IO_WRITE_STR instead"
-  #define RVMODEL_IO_WRITE_STR(_SP, _STR) \
-    RVTEST_IO_WRITE_STR(_SP, _STR)
-#endif
-
-#ifdef RVTEST_IO_INIT
-  #warning "RVTEST_IO_INIT is deprecated in v0.2. Please use RVMODEL_BOOT for initialization"
-#endif
-  
-#ifdef RVTEST_IO_CHECK
-  #warning "RVTEST_IO_CHECK is deprecated in v0.2.
-#endif
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile
new file mode 100644
index 000000000..c7b3e8946
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32ec -mabi=ilp32e -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefrag
new file mode 100644
index 000000000..b04dac3fc
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/Makefrag
@@ -0,0 +1,61 @@
+# RISC-V Architecture Test RV32E Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32E architectural tests
+
+rv32e_sc_tests = \
+  cadd-01 \
+  caddi-01 \
+  caddi16sp-01 \
+  caddi4spn-01 \
+  cand-01 \
+  candi-01 \
+  cbeqz-01 \
+  cbnez-01 \
+  cj-01 \
+  cjal-01 \
+  cjalr-01 \
+  cjr-01 \
+  cli-01 \
+  clui-01 \
+  clw-01 \
+  clwsp-01 \
+  cmv-01 \
+  cnop-01 \
+  cor-01 \
+  cslli-01 \
+  csrai-01 \
+  csrli-01 \
+  csub-01 \
+  csw-01 \
+  cswsp-01 \
+  cxor-01
+
+
+rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests))
+
+target_tests += $(rv32e_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
new file mode 100644
index 000000000..fbdfa17f9
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cadd-01.reference_output
@@ -0,0 +1,580 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
new file mode 100644
index 000000000..168266e00
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/caddi-01.reference_output
@@ -0,0 +1,375 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/candi-01.reference_output
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new file mode 100644
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/csw-01.reference_output
new file mode 100644
index 000000000..92cbdd427
--- /dev/null
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cswsp-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/references/cxor-01.reference_output
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+00000003
+55555551
+5555e056
+55555555
+33333330
+66666667
+00000001
+55555557
+5555e051
+aaaa1fa9
+33333333
+66666666
+55555550
+ffffffff
+00000000
+55555556
+0000b506
+ffff4afe
+66666664
+33333337
+00000005
+aaaaaaa8
+55555555
+00000007
+0000b500
+00000003
+66666666
+33333331
+55555557
+00000001
+0000b507
+ffff4aff
+66666665
+33333330
+00000006
+aaaaaaa9
+55555556
+00000000
+6666d366
+66666665
+00000000
+55555557
+33333331
+66666667
+6666d361
+99992c99
+00000003
+55555556
+66666660
+cccccccf
+33333330
+66666666
+33338637
+cccc79cf
+55555555
+00000006
+33333334
+99999999
+66666664
+33333336
+33338631
+33333332
+55555557
+00000000
+66666666
+33333330
+33338636
+cccc79ce
+55555554
+00000001
+33333337
+99999998
+66666667
+33333331
+5555e051
+aaaa1fa9
+33333333
+66666660
+55555552
+ffffffff
+00000002
+55555550
+5555e057
+55555554
+33333331
+66666666
+00000000
+55555556
+5555e050
+aaaa1fa8
+33333332
+66666667
+55555551
+fffffffe
+00000001
+55555557
+0000b507
+ffff4aff
+66666665
+33333336
+aaaaaaa9
+55555554
+00000006
+0000b501
+00000002
+66666667
+33333330
+55555556
+00000000
+0000b506
+ffff4afe
+66666664
+33333331
+00000007
+aaaaaaa8
+55555557
+00000001
+00000001
+fffffff9
+6666d363
+33338630
+0000b502
+aaaa1faf
+5555e052
+0000b500
+00000007
+0000b504
+6666d361
+33338636
+5555e050
+0000b506
+00000000
+fffffff8
+6666d362
+33338637
+0000b501
+aaaa1fae
+5555e051
+0000b507
+fffffff9
+00000001
+99992c9b
+cccc79c8
+ffff4afa
+5555e057
+aaaa1faa
+ffff4af8
+ffffffff
+ffff4afc
+99992c99
+cccc79ce
+aaaa1fa8
+ffff4afe
+fffffff8
+00000000
+99992c9a
+cccc79cf
+ffff4af9
+5555e056
+aaaa1fa9
+ffff4aff
+6666d363
+99992c9b
+00000001
+55555552
+66666660
+cccccccd
+33333330
+66666662
+6666d365
+66666666
+00000003
+55555554
+33333332
+66666664
+6666d362
+99992c9a
+00000000
+55555555
+66666663
+cccccccc
+33333333
+66666665
+33338636
+cccc79ce
+55555554
+00000007
+33333335
+99999998
+66666665
+33333337
+33338630
+7fffffbf
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cadd-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cadd-01.S
new file mode 100644
index 000000000..2e79673e2
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cadd-01.S
@@ -0,0 +1,2980 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.add instruction of the RISC-V C extension for the cadd covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cadd)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x3, rs2==x7, rs1_val == (-2**(xlen-1)), rs1_val == -2147483648, rs2_val > 0
+// opcode: c.add; op1:x3; op2:x7; op1val:-0x80000000; op2val:0x3fffffff
+TEST_CR_OP( c.add, x3, x7, 0xbfffffff, -0x80000000, 0x3fffffff, x1, 0, x2)
+
+inst_1:
+// rs1 == rs2, rs1==x4, rs2==x4, rs2_val == 2147483647, rs1_val == 8192, rs2_val == (2**(xlen-1)-1)
+// opcode: c.add; op1:x4; op2:x4; op1val:0x2000; op2val:0x2000
+TEST_CR_OP( c.add, x4, x4, 0x4000, 0x2000, 0x2000, x1, 4, x2)
+
+inst_2:
+// rs1==x9, rs2==x12, rs2_val == -1073741825, rs2_val < 0, rs1_val == -8193
+// opcode: c.add; op1:x9; op2:x12; op1val:-0x2001; op2val:-0x40000001
+TEST_CR_OP( c.add, x9, x12, 0xbfffdffe, -0x2001, -0x40000001, x1, 8, x2)
+
+inst_3:
+// rs1==x10, rs2==x13, rs2_val == -536870913, rs1_val == 64
+// opcode: c.add; op1:x10; op2:x13; op1val:0x40; op2val:-0x20000001
+TEST_CR_OP( c.add, x10, x13, 0xe000003f, 0x40, -0x20000001, x1, 12, x2)
+
+inst_4:
+// rs1==x11, rs2==x15, rs2_val == -268435457, 
+// opcode: c.add; op1:x11; op2:x15; op1val:0x66666666; op2val:-0x10000001
+TEST_CR_OP( c.add, x11, x15, 0x56666665, 0x66666666, -0x10000001, x1, 16, x2)
+
+inst_5:
+// rs1==x15, rs2==x8, rs2_val == -134217729, rs1_val == -5
+// opcode: c.add; op1:x15; op2:x8; op1val:-0x5; op2val:-0x8000001
+TEST_CR_OP( c.add, x15, x8, 0xf7fffffa, -0x5, -0x8000001, x1, 20, x2)
+
+inst_6:
+// rs1==x6, rs2==x3, rs2_val == -67108865, 
+// opcode: c.add; op1:x6; op2:x3; op1val:-0xb503; op2val:-0x4000001
+TEST_CR_OP( c.add, x6, x3, 0xfbff4afc, -0xb503, -0x4000001, x1, 24, x2)
+
+inst_7:
+// rs1==x8, rs2==x10, rs2_val == -33554433, rs1_val == 33554432
+// opcode: c.add; op1:x8; op2:x10; op1val:0x2000000; op2val:-0x2000001
+TEST_CR_OP( c.add, x8, x10, 0xffffffff, 0x2000000, -0x2000001, x1, 28, x4)
+
+inst_8:
+// rs1==x0, rs2==x9, rs2_val == -16777217, rs1_val == -32769
+// opcode: c.add; op1:x0; op2:x9; op1val:0x0; op2val:-0x1000001
+TEST_CR_OP( c.add, x0, x9, 0, 0x0, -0x1000001, x1, 32, x4)
+
+inst_9:
+// rs1==x14, rs2==x11, rs2_val == -8388609, rs1_val == -268435457
+// opcode: c.add; op1:x14; op2:x11; op1val:-0x10000001; op2val:-0x800001
+TEST_CR_OP( c.add, x14, x11, 0xef7ffffe, -0x10000001, -0x800001, x1, 36, x4)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_10:
+// rs1==x7, rs2==x5, rs2_val == -4194305, rs1_val == 65536
+// opcode: c.add; op1:x7; op2:x5; op1val:0x10000; op2val:-0x400001
+TEST_CR_OP( c.add, x7, x5, 0xffc0ffff, 0x10000, -0x400001, x3, 0, x4)
+
+inst_11:
+// rs1==x13, rs2==x2, rs2_val == -2097153, rs1_val == 536870912
+// opcode: c.add; op1:x13; op2:x2; op1val:0x20000000; op2val:-0x200001
+TEST_CR_OP( c.add, x13, x2, 0x1fdfffff, 0x20000000, -0x200001, x3, 4, x4)
+
+inst_12:
+// rs1==x5, rs2==x14, rs2_val == -1048577, 
+// opcode: c.add; op1:x5; op2:x14; op1val:0x3; op2val:-0x100001
+TEST_CR_OP( c.add, x5, x14, 0xfff00002, 0x3, -0x100001, x3, 8, x4)
+
+inst_13:
+// rs1==x2, rs2==x6, rs2_val == -524289, 
+// opcode: c.add; op1:x2; op2:x6; op1val:-0xb503; op2val:-0x80001
+TEST_CR_OP( c.add, x2, x6, 0xfff74afc, -0xb503, -0x80001, x3, 12, x4)
+
+inst_14:
+// rs1==x12, rs2==x1, rs2_val == -262145, rs1_val == 4194304
+// opcode: c.add; op1:x12; op2:x1; op1val:0x400000; op2val:-0x40001
+TEST_CR_OP( c.add, x12, x1, 0x3bffff, 0x400000, -0x40001, x3, 16, x4)
+
+inst_15:
+// rs1==x1, rs2_val == -131073, rs1_val == 32
+// opcode: c.add; op1:x1; op2:x2; op1val:0x20; op2val:-0x20001
+TEST_CR_OP( c.add, x1, x2, 0xfffe001f, 0x20, -0x20001, x3, 20, x4)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:-0x10001
+TEST_CR_OP( c.add, x10, x11, 0xffff0005, 0x6, -0x10001, x3, 24, x4)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x8001
+TEST_CR_OP( c.add, x10, x11, 0x3332b333, 0x33333334, -0x8001, x3, 28, x4)
+
+inst_18:
+// rs2_val == -16385, rs1_val == 1073741824
+// opcode: c.add; op1:x10; op2:x11; op1val:0x40000000; op2val:-0x4001
+TEST_CR_OP( c.add, x10, x11, 0x3fffbfff, 0x40000000, -0x4001, x3, 32, x4)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -67108865
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x4000001; op2val:-0x2001
+TEST_CR_OP( c.add, x10, x11, 0xfbffdffe, -0x4000001, -0x2001, x3, 36, x4)
+
+inst_20:
+// rs2_val == -4097, rs1_val == -65537
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x10001; op2val:-0x1001
+TEST_CR_OP( c.add, x10, x11, 0xfffeeffe, -0x10001, -0x1001, x3, 40, x4)
+
+inst_21:
+// rs2_val == -2049, rs1_val == 131072
+// opcode: c.add; op1:x10; op2:x11; op1val:0x20000; op2val:-0x801
+TEST_CR_OP( c.add, x10, x11, 0x1f7ff, 0x20000, -0x801, x3, 44, x4)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x401
+TEST_CR_OP( c.add, x10, x11, 0x66666265, 0x66666666, -0x401, x3, 48, x4)
+
+inst_23:
+// rs2_val == -513, rs1_val == -536870913
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x201
+TEST_CR_OP( c.add, x10, x11, 0xdffffdfe, -0x20000001, -0x201, x3, 52, x4)
+
+inst_24:
+// rs2_val == -257, rs1_val == 8
+// opcode: c.add; op1:x10; op2:x11; op1val:0x8; op2val:-0x101
+TEST_CR_OP( c.add, x10, x11, 0xffffff07, 0x8, -0x101, x3, 56, x4)
+
+inst_25:
+// rs2_val == -129, rs1_val == -65
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x41; op2val:-0x81
+TEST_CR_OP( c.add, x10, x11, 0xffffff3e, -0x41, -0x81, x3, 60, x4)
+
+inst_26:
+// rs2_val == -65, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: c.add; op1:x10; op2:x11; op1val:0x7fffffff; op2val:-0x41
+TEST_CR_OP( c.add, x10, x11, 0x7fffffbe, 0x7fffffff, -0x41, x3, 64, x4)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x21
+TEST_CR_OP( c.add, x10, x11, 0x66666646, 0x66666667, -0x21, x3, 68, x4)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x11
+TEST_CR_OP( c.add, x10, x11, 0x55555545, 0x55555556, -0x11, x3, 72, x4)
+
+inst_29:
+// rs2_val == -9, rs1_val == 2
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:-0x9
+TEST_CR_OP( c.add, x10, x11, 0xfffffff9, 0x2, -0x9, x3, 76, x4)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x8001; op2val:-0x5
+TEST_CR_OP( c.add, x10, x11, 0xffff7ffa, -0x8001, -0x5, x3, 80, x4)
+
+inst_31:
+// rs2_val == -3, rs1_val == 268435456
+// opcode: c.add; op1:x10; op2:x11; op1val:0x10000000; op2val:-0x3
+TEST_CR_OP( c.add, x10, x11, 0xffffffd, 0x10000000, -0x3, x3, 84, x4)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x2
+TEST_CR_OP( c.add, x10, x11, 0x66666665, 0x66666667, -0x2, x3, 88, x4)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 536870912
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x40000001; op2val:0x20000000
+TEST_CR_OP( c.add, x10, x11, 0xdfffffff, -0x40000001, 0x20000000, x3, 92, x4)
+
+inst_34:
+// rs1_val == -134217729, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x8000001; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x5e666665, -0x8000001, 0x66666666, x3, 96, x4)
+
+inst_35:
+// rs1_val == -33554433, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x2000001; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xfdff4afc, -0x2000001, -0xb503, x3, 100, x4)
+
+inst_36:
+// rs1_val == -16777217, rs2_val == 1048576
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x1000001; op2val:0x100000
+TEST_CR_OP( c.add, x10, x11, 0xff0fffff, -0x1000001, 0x100000, x3, 104, x4)
+
+inst_37:
+// rs1_val == -8388609, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x800001; op2val:-0x40000000
+TEST_CR_OP( c.add, x10, x11, 0xbf7fffff, -0x800001, -0x40000000, x3, 108, x4)
+
+inst_38:
+// rs1_val == -4194305, rs2_val == 16777216
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x400001; op2val:0x1000000
+TEST_CR_OP( c.add, x10, x11, 0xbfffff, -0x400001, 0x1000000, x3, 112, x4)
+
+inst_39:
+// rs1_val == -2097153, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x200001; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55355555, -0x200001, 0x55555556, x3, 116, x4)
+
+inst_40:
+// rs1_val == -1048577, rs2_val == 4194304
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x100001; op2val:0x400000
+TEST_CR_OP( c.add, x10, x11, 0x2fffff, -0x100001, 0x400000, x3, 120, x4)
+
+inst_41:
+// rs1_val == -524289, rs2_val == 524288
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x80001; op2val:0x80000
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, -0x80001, 0x80000, x3, 124, x4)
+
+inst_42:
+// rs1_val == -262145, rs2_val == 8388608
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x40001; op2val:0x800000
+TEST_CR_OP( c.add, x10, x11, 0x7bffff, -0x40001, 0x800000, x3, 128, x4)
+
+inst_43:
+// rs1_val == -131073, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x20001; op2val:-0x40000000
+TEST_CR_OP( c.add, x10, x11, 0xbffdffff, -0x20001, -0x40000000, x3, 132, x4)
+
+inst_44:
+// rs1_val == -16385, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x4001; op2val:0x400000
+TEST_CR_OP( c.add, x10, x11, 0x3fbfff, -0x4001, 0x400000, x3, 136, x4)
+
+inst_45:
+// rs1_val == -4097, rs2_val == 64
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x1001; op2val:0x40
+TEST_CR_OP( c.add, x10, x11, 0xfffff03f, -0x1001, 0x40, x3, 140, x4)
+
+inst_46:
+// rs1_val == -2049, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x801; op2val:0x20000000
+TEST_CR_OP( c.add, x10, x11, 0x1ffff7ff, -0x801, 0x20000000, x3, 144, x4)
+
+inst_47:
+// rs1_val == -1025, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x401; op2val:-0x8001
+TEST_CR_OP( c.add, x10, x11, 0xffff7bfe, -0x401, -0x8001, x3, 148, x4)
+
+inst_48:
+// rs1_val == -513, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x201; op2val:-0x2001
+TEST_CR_OP( c.add, x10, x11, 0xffffddfe, -0x201, -0x2001, x3, 152, x4)
+
+inst_49:
+// rs1_val == -257, rs2_val == 4
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x101; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xffffff03, -0x101, 0x4, x3, 156, x4)
+
+inst_50:
+// rs1_val == -129, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x81; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x333332b1, -0x81, 0x33333332, x3, 160, x4)
+
+inst_51:
+// rs1_val == -33, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x21; op2val:0x40
+TEST_CR_OP( c.add, x10, x11, 0x1f, -0x21, 0x40, x3, 164, x4)
+
+inst_52:
+// rs1_val == -17, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x11; op2val:-0x10000001
+TEST_CR_OP( c.add, x10, x11, 0xefffffee, -0x11, -0x10000001, x3, 168, x4)
+
+inst_53:
+// rs1_val == -9, rs2_val == 33554432
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x9; op2val:0x2000000
+TEST_CR_OP( c.add, x10, x11, 0x1fffff7, -0x9, 0x2000000, x3, 172, x4)
+
+inst_54:
+// rs1_val == -3, rs2_val == 1431655765
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x3; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555552, -0x3, 0x55555555, x3, 176, x4)
+
+inst_55:
+// rs1_val == -2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x2; op2val:0x20000000
+TEST_CR_OP( c.add, x10, x11, 0x1ffffffe, -0x2, 0x20000000, x3, 180, x4)
+
+inst_56:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1)), rs1_val == 4
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:-0x80000000
+TEST_CR_OP( c.add, x10, x11, 0x80000004, 0x4, -0x80000000, x3, 184, x4)
+
+inst_57:
+// rs2_val == 1073741824, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x6; op2val:0x40000000
+TEST_CR_OP( c.add, x10, x11, 0x3ffffffa, -0x6, 0x40000000, x3, 188, x4)
+
+inst_58:
+// rs2_val == 268435456, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x8; op2val:0x10000000
+TEST_CR_OP( c.add, x10, x11, 0xffffff8, -0x8, 0x10000000, x3, 192, x4)
+
+inst_59:
+// rs2_val == 134217728, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x6; op2val:0x8000000
+TEST_CR_OP( c.add, x10, x11, 0x7fffffa, -0x6, 0x8000000, x3, 196, x4)
+
+inst_60:
+// rs2_val == 67108864, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x5; op2val:0x4000000
+TEST_CR_OP( c.add, x10, x11, 0x3fffffb, -0x5, 0x4000000, x3, 200, x4)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x200000
+TEST_CR_OP( c.add, x10, x11, 0x55755556, 0x55555556, 0x200000, x3, 204, x4)
+
+inst_62:
+// rs2_val == 262144, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x40000
+TEST_CR_OP( c.add, x10, x11, 0x40002, 0x2, 0x40000, x3, 208, x4)
+
+inst_63:
+// rs2_val == 131072, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x20; op2val:0x20000
+TEST_CR_OP( c.add, x10, x11, 0x20020, 0x20, 0x20000, x3, 212, x4)
+
+inst_64:
+// rs2_val == 65536, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x201; op2val:0x10000
+TEST_CR_OP( c.add, x10, x11, 0xfdff, -0x201, 0x10000, x3, 216, x4)
+
+inst_65:
+// rs2_val == 32768, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x2000001; op2val:0x8000
+TEST_CR_OP( c.add, x10, x11, 0xfe007fff, -0x2000001, 0x8000, x3, 220, x4)
+
+inst_66:
+// rs2_val == 16384, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x1001; op2val:0x4000
+TEST_CR_OP( c.add, x10, x11, 0x2fff, -0x1001, 0x4000, x3, 224, x4)
+
+inst_67:
+// rs2_val == 8192, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x8001; op2val:0x2000
+TEST_CR_OP( c.add, x10, x11, 0xffff9fff, -0x8001, 0x2000, x3, 228, x4)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x1000
+TEST_CR_OP( c.add, x10, x11, 0xffff5afc, -0xb504, 0x1000, x3, 232, x4)
+
+inst_69:
+// rs2_val == 2048, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x4000001; op2val:0x800
+TEST_CR_OP( c.add, x10, x11, 0xfc0007ff, -0x4000001, 0x800, x3, 236, x4)
+
+inst_70:
+// rs2_val == 1024, rs1_val == 4096
+// opcode: c.add; op1:x10; op2:x11; op1val:0x1000; op2val:0x400
+TEST_CR_OP( c.add, x10, x11, 0x1400, 0x1000, 0x400, x3, 240, x4)
+
+inst_71:
+// rs2_val == 512, rs1_val == -1431655766
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x200
+TEST_CR_OP( c.add, x10, x11, 0xaaaaacaa, -0x55555556, 0x200, x3, 244, x4)
+
+inst_72:
+// rs2_val == 256, rs1_val == 262144
+// opcode: c.add; op1:x10; op2:x11; op1val:0x40000; op2val:0x100
+TEST_CR_OP( c.add, x10, x11, 0x40100, 0x40000, 0x100, x3, 248, x4)
+
+inst_73:
+// rs2_val == 128, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x4000001; op2val:0x80
+TEST_CR_OP( c.add, x10, x11, 0xfc00007f, -0x4000001, 0x80, x3, 252, x4)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x11; op2val:0x20
+TEST_CR_OP( c.add, x10, x11, 0xf, -0x11, 0x20, x3, 256, x4)
+
+inst_75:
+// rs2_val == 16, rs1_val == 256
+// opcode: c.add; op1:x10; op2:x11; op1val:0x100; op2val:0x10
+TEST_CR_OP( c.add, x10, x11, 0x110, 0x100, 0x10, x3, 260, x4)
+
+inst_76:
+// rs2_val == 8, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x8
+TEST_CR_OP( c.add, x10, x11, 0xa, 0x2, 0x8, x3, 264, x4)
+
+inst_77:
+// rs2_val == 2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x10000; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x10002, 0x10000, 0x2, x3, 268, x4)
+
+inst_78:
+// rs2_val == 1, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x1
+TEST_CR_OP( c.add, x10, x11, 0x5, 0x4, 0x1, x3, 272, x4)
+
+inst_79:
+// rs1_val == 134217728, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x8000000; op2val:-0xa
+TEST_CR_OP( c.add, x10, x11, 0x7fffff6, 0x8000000, -0xa, x3, 276, x4)
+
+inst_80:
+// rs1_val == 67108864, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4000000; op2val:-0x200001
+TEST_CR_OP( c.add, x10, x11, 0x3dfffff, 0x4000000, -0x200001, x3, 280, x4)
+
+inst_81:
+// rs1_val == 16777216, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x1000000; op2val:-0x4
+TEST_CR_OP( c.add, x10, x11, 0xfffffc, 0x1000000, -0x4, x3, 284, x4)
+
+inst_82:
+// rs1_val == 8388608, rs2_val == 0
+// opcode: c.add; op1:x10; op2:x11; op1val:0x800000; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x800000, 0x800000, 0x0, x3, 288, x4)
+
+inst_83:
+// rs1_val == 2097152, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x200000; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66866666, 0x200000, 0x66666666, x3, 292, x4)
+
+inst_84:
+// rs1_val == 1048576, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x100000; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55655556, 0x100000, 0x55555556, x3, 296, x4)
+
+inst_85:
+// rs1_val == 524288, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x80000; op2val:0x200
+TEST_CR_OP( c.add, x10, x11, 0x80200, 0x80000, 0x200, x3, 300, x4)
+
+inst_86:
+// rs1_val == 32768, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x8000; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaab2aab, 0x8000, -0x55555555, x3, 304, x4)
+
+inst_87:
+// rs1_val == 16384, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4000; op2val:0x100
+TEST_CR_OP( c.add, x10, x11, 0x4100, 0x4000, 0x100, x3, 308, x4)
+
+inst_88:
+// rs1_val == 2048, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x800; op2val:0x8000
+TEST_CR_OP( c.add, x10, x11, 0x8800, 0x800, 0x8000, x3, 312, x4)
+
+inst_89:
+// rs1_val == 1024, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x400; op2val:0x1000000
+TEST_CR_OP( c.add, x10, x11, 0x1000400, 0x400, 0x1000000, x3, 316, x4)
+
+inst_90:
+// rs1_val == 512, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x200; op2val:0x40000
+TEST_CR_OP( c.add, x10, x11, 0x40200, 0x200, 0x40000, x3, 320, x4)
+
+inst_91:
+// rs1_val == 128, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x80; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb585, 0x80, 0xb505, x3, 324, x4)
+
+inst_92:
+// rs1_val == 16, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x10; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb514, 0x10, 0xb504, x3, 328, x4)
+
+inst_93:
+// rs1_val == 1, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x1; op2val:-0x81
+TEST_CR_OP( c.add, x10, x11, 0xffffff80, 0x1, -0x81, x3, 332, x4)
+
+inst_94:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x16a0a, 0xb505, 0xb505, x3, 336, x4)
+
+inst_95:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x2, 0xb505, -0xb503, x3, 340, x4)
+
+inst_96:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x66671b6c, 0xb505, 0x66666667, x3, 344, x4)
+
+inst_97:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x3333e839, 0xb505, 0x33333334, x3, 348, x4)
+
+inst_98:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xb50b, 0xb505, 0x6, x3, 352, x4)
+
+inst_99:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fb0, 0xb505, -0x55555555, x3, 356, x4)
+
+inst_100:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55560a5b, 0xb505, 0x55555556, x3, 360, x4)
+
+inst_101:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0xb505, 0x4, x3, 364, x4)
+
+inst_102:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x16a08, 0xb505, 0xb503, x3, 368, x4)
+
+inst_103:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xb505, 0xb505, 0x0, x3, 372, x4)
+
+inst_104:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0xb505, 0x66666665, x3, 376, x4)
+
+inst_105:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0xb505, 0x33333332, x3, 380, x4)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0xb505, 0x55555554, x3, 384, x4)
+
+inst_107:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0xb505, 0x2, x3, 388, x4)
+
+inst_108:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x16a09, 0xb505, 0xb504, x3, 392, x4)
+
+inst_109:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x1, 0xb505, -0xb504, x3, 396, x4)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66671b6b, 0xb505, 0x66666666, x3, 400, x4)
+
+inst_111:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x3333e838, 0xb505, 0x33333333, x3, 404, x4)
+
+inst_112:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xb50a, 0xb505, 0x5, x3, 408, x4)
+
+inst_113:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaab5faf, 0xb505, -0x55555556, x3, 412, x4)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55560a5a, 0xb505, 0x55555555, x3, 416, x4)
+
+inst_115:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb505; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0xb505, 0x3, x3, 420, x4)
+
+inst_116:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x2, -0xb503, 0xb505, x3, 424, x4)
+
+inst_117:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xfffe95fa, -0xb503, -0xb503, x3, 428, x4)
+
+inst_118:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6665b164, -0xb503, 0x66666667, x3, 432, x4)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33327e31, -0xb503, 0x33333334, x3, 436, x4)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xffff4b03, -0xb503, 0x6, x3, 440, x4)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a8, -0xb503, -0x55555555, x3, 444, x4)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x5554a053, -0xb503, 0x55555556, x3, 448, x4)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xffff4b01, -0xb503, 0x4, x3, 452, x4)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x0, -0xb503, 0xb503, x3, 456, x4)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xffff4afd, -0xb503, 0x0, x3, 460, x4)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x6665b162, -0xb503, 0x66666665, x3, 464, x4)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33327e2f, -0xb503, 0x33333332, x3, 468, x4)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x5554a051, -0xb503, 0x55555554, x3, 472, x4)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xffff4aff, -0xb503, 0x2, x3, 476, x4)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x1, -0xb503, 0xb504, x3, 480, x4)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xfffe95f9, -0xb503, -0xb504, x3, 484, x4)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x6665b163, -0xb503, 0x66666666, x3, 488, x4)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33327e30, -0xb503, 0x33333333, x3, 492, x4)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xffff4b02, -0xb503, 0x5, x3, 496, x4)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a7, -0xb503, -0x55555556, x3, 500, x4)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x5554a052, -0xb503, 0x55555555, x3, 504, x4)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb503; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xffff4b00, -0xb503, 0x3, x3, 508, x4)
+
+inst_138:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x66671b6c, 0x66666667, 0xb505, x3, 512, x4)
+
+inst_139:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x6665b164, 0x66666667, -0xb503, x3, 516, x4)
+
+inst_140:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xccccccce, 0x66666667, 0x66666667, x3, 520, x4)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x9999999b, 0x66666667, 0x33333334, x3, 524, x4)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x6666666d, 0x66666667, 0x6, x3, 528, x4)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x11111112, 0x66666667, -0x55555555, x3, 532, x4)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbd, 0x66666667, 0x55555556, x3, 536, x4)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x66666667, 0x4, x3, 540, x4)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0x66666667, 0xb503, x3, 544, x4)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x66666667, 0x0, x3, 548, x4)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xcccccccc, 0x66666667, 0x66666665, x3, 552, x4)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x66666667, 0x33333332, x3, 556, x4)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x66666667, 0x55555554, x3, 560, x4)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x66666667, 0x2, x3, 564, x4)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x66671b6b, 0x66666667, 0xb504, x3, 568, x4)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x6665b163, 0x66666667, -0xb504, x3, 572, x4)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xcccccccd, 0x66666667, 0x66666666, x3, 576, x4)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x9999999a, 0x66666667, 0x33333333, x3, 580, x4)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x6666666c, 0x66666667, 0x5, x3, 584, x4)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x11111111, 0x66666667, -0x55555556, x3, 588, x4)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbc, 0x66666667, 0x55555555, x3, 592, x4)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666667; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x66666667, 0x3, x3, 596, x4)
+
+inst_160:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x3333e839, 0x33333334, 0xb505, x3, 600, x4)
+
+inst_161:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x33327e31, 0x33333334, -0xb503, x3, 604, x4)
+
+inst_162:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x9999999b, 0x33333334, 0x66666667, x3, 608, x4)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x66666668, 0x33333334, 0x33333334, x3, 612, x4)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x3333333a, 0x33333334, 0x6, x3, 616, x4)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xdddddddf, 0x33333334, -0x55555555, x3, 620, x4)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x8888888a, 0x33333334, 0x55555556, x3, 624, x4)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x33333334, 0x4, x3, 628, x4)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0x33333334, 0xb503, x3, 632, x4)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x33333334, 0x33333334, 0x0, x3, 636, x4)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x33333334, 0x66666665, x3, 640, x4)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x66666666, 0x33333334, 0x33333332, x3, 644, x4)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x33333334, 0x55555554, x3, 648, x4)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x33333334, 0x2, x3, 652, x4)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x3333e838, 0x33333334, 0xb504, x3, 656, x4)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x33327e30, 0x33333334, -0xb504, x3, 660, x4)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x9999999a, 0x33333334, 0x66666666, x3, 664, x4)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x33333334, 0x33333333, x3, 668, x4)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x33333339, 0x33333334, 0x5, x3, 672, x4)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xddddddde, 0x33333334, -0x55555556, x3, 676, x4)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x88888889, 0x33333334, 0x55555555, x3, 680, x4)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333334; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x33333334, 0x3, x3, 684, x4)
+
+inst_182:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb50b, 0x6, 0xb505, x3, 688, x4)
+
+inst_183:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4b03, 0x6, -0xb503, x3, 692, x4)
+
+inst_184:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6666666d, 0x6, 0x66666667, x3, 696, x4)
+
+inst_185:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x3333333a, 0x6, 0x33333334, x3, 700, x4)
+
+inst_186:
+// rs1_val==6 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xc, 0x6, 0x6, x3, 704, x4)
+
+inst_187:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab1, 0x6, -0x55555555, x3, 708, x4)
+
+inst_188:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x5555555c, 0x6, 0x55555556, x3, 712, x4)
+
+inst_189:
+// rs1_val==6 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xa, 0x6, 0x4, x3, 716, x4)
+
+inst_190:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0x6, 0xb503, x3, 720, x4)
+
+inst_191:
+// rs1_val==6 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x6, 0x6, 0x0, x3, 724, x4)
+
+inst_192:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x6, 0x66666665, x3, 728, x4)
+
+inst_193:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x6, 0x33333332, x3, 732, x4)
+
+inst_194:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x6, 0x55555554, x3, 736, x4)
+
+inst_195:
+// rs1_val==6 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x8, 0x6, 0x2, x3, 740, x4)
+
+inst_196:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb50a, 0x6, 0xb504, x3, 744, x4)
+
+inst_197:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4b02, 0x6, -0xb504, x3, 748, x4)
+
+inst_198:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x6666666c, 0x6, 0x66666666, x3, 752, x4)
+
+inst_199:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333339, 0x6, 0x33333333, x3, 756, x4)
+
+inst_200:
+// rs1_val==6 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xb, 0x6, 0x5, x3, 760, x4)
+
+inst_201:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab0, 0x6, -0x55555556, x3, 764, x4)
+
+inst_202:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x5555555b, 0x6, 0x55555555, x3, 768, x4)
+
+inst_203:
+// rs1_val==6 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x6; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x9, 0x6, 0x3, x3, 772, x4)
+
+inst_204:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fb0, -0x55555555, 0xb505, x3, 776, x4)
+
+inst_205:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a8, -0x55555555, -0xb503, x3, 780, x4)
+
+inst_206:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x11111112, -0x55555555, 0x66666667, x3, 784, x4)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0xdddddddf, -0x55555555, 0x33333334, x3, 788, x4)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab1, -0x55555555, 0x6, x3, 792, x4)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555556, -0x55555555, -0x55555555, x3, 796, x4)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x1, -0x55555555, 0x55555556, x3, 800, x4)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x3, 804, x4)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fae, -0x55555555, 0xb503, x3, 808, x4)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x3, 812, x4)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x11111110, -0x55555555, 0x66666665, x3, 816, x4)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0xdddddddd, -0x55555555, 0x33333332, x3, 820, x4)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x3, 824, x4)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaad, -0x55555555, 0x2, x3, 828, x4)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xaaab5faf, -0x55555555, 0xb504, x3, 832, x4)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a7, -0x55555555, -0xb504, x3, 836, x4)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x11111111, -0x55555555, 0x66666666, x3, 840, x4)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0xddddddde, -0x55555555, 0x33333333, x3, 844, x4)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab0, -0x55555555, 0x5, x3, 848, x4)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55555555, -0x55555555, -0x55555556, x3, 852, x4)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x0, -0x55555555, 0x55555555, x3, 856, x4)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaae, -0x55555555, 0x3, x3, 860, x4)
+
+inst_226:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x55560a5b, 0x55555556, 0xb505, x3, 864, x4)
+
+inst_227:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x5554a053, 0x55555556, -0xb503, x3, 868, x4)
+
+inst_228:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbd, 0x55555556, 0x66666667, x3, 872, x4)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x8888888a, 0x55555556, 0x33333334, x3, 876, x4)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x5555555c, 0x55555556, 0x6, x3, 880, x4)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x1, 0x55555556, -0x55555555, x3, 884, x4)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaac, 0x55555556, 0x55555556, x3, 888, x4)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x55555556, 0x4, x3, 892, x4)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0x55555556, 0xb503, x3, 896, x4)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x55555556, 0x55555556, 0x0, x3, 900, x4)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x55555556, 0x66666665, x3, 904, x4)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x55555556, 0x33333332, x3, 908, x4)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaa, 0x55555556, 0x55555554, x3, 912, x4)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x55555556, 0x2, x3, 916, x4)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x55560a5a, 0x55555556, 0xb504, x3, 920, x4)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x5554a052, 0x55555556, -0xb504, x3, 924, x4)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbc, 0x55555556, 0x66666666, x3, 928, x4)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x88888889, 0x55555556, 0x33333333, x3, 932, x4)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x5555555b, 0x55555556, 0x5, x3, 936, x4)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x0, 0x55555556, -0x55555556, x3, 940, x4)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaab, 0x55555556, 0x55555555, x3, 944, x4)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555556; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x55555556, 0x3, x3, 948, x4)
+
+inst_248:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0x4, 0xb505, x3, 952, x4)
+
+inst_249:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4b01, 0x4, -0xb503, x3, 956, x4)
+
+inst_250:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x4, 0x66666667, x3, 960, x4)
+
+inst_251:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x4, 0x33333334, x3, 964, x4)
+
+inst_252:
+// rs1_val==4 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xa, 0x4, 0x6, x3, 968, x4)
+
+inst_253:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x3, 972, x4)
+
+inst_254:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x4, 0x55555556, x3, 976, x4)
+
+inst_255:
+// rs1_val==4 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x8, 0x4, 0x4, x3, 980, x4)
+
+inst_256:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0x4, 0xb503, x3, 984, x4)
+
+inst_257:
+// rs1_val==4 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x4, 0x4, 0x0, x3, 988, x4)
+
+inst_258:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x4, 0x66666665, x3, 992, x4)
+
+inst_259:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x4, 0x33333332, x3, 996, x4)
+
+inst_260:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x4, 0x55555554, x3, 1000, x4)
+
+inst_261:
+// rs1_val==4 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x6, 0x4, 0x2, x3, 1004, x4)
+
+inst_262:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0x4, 0xb504, x3, 1008, x4)
+
+inst_263:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4b00, 0x4, -0xb504, x3, 1012, x4)
+
+inst_264:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x4, 0x66666666, x3, 1016, x4)
+
+inst_265:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x4, 0x33333333, x3, 1020, x4)
+
+inst_266:
+// rs1_val==4 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x9, 0x4, 0x5, x3, 1024, x4)
+
+inst_267:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x3, 1028, x4)
+
+inst_268:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x4, 0x55555555, x3, 1032, x4)
+
+inst_269:
+// rs1_val==4 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x4; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x7, 0x4, 0x3, x3, 1036, x4)
+
+inst_270:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x16a08, 0xb503, 0xb505, x3, 1040, x4)
+
+inst_271:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x0, 0xb503, -0xb503, x3, 1044, x4)
+
+inst_272:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0xb503, 0x66666667, x3, 1048, x4)
+
+inst_273:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0xb503, 0x33333334, x3, 1052, x4)
+
+inst_274:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0xb503, 0x6, x3, 1056, x4)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fae, 0xb503, -0x55555555, x3, 1060, x4)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0xb503, 0x55555556, x3, 1064, x4)
+
+inst_277:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0xb503, 0x4, x3, 1068, x4)
+
+inst_278:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x16a06, 0xb503, 0xb503, x3, 1072, x4)
+
+inst_279:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xb503, 0xb503, 0x0, x3, 1076, x4)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66671b68, 0xb503, 0x66666665, x3, 1080, x4)
+
+inst_281:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x3333e835, 0xb503, 0x33333332, x3, 1084, x4)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55560a57, 0xb503, 0x55555554, x3, 1088, x4)
+
+inst_283:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xb505, 0xb503, 0x2, x3, 1092, x4)
+
+inst_284:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x16a07, 0xb503, 0xb504, x3, 1096, x4)
+
+inst_285:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, 0xb503, -0xb504, x3, 1100, x4)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66671b69, 0xb503, 0x66666666, x3, 1104, x4)
+
+inst_287:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x3333e836, 0xb503, 0x33333333, x3, 1108, x4)
+
+inst_288:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0xb503, 0x5, x3, 1112, x4)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fad, 0xb503, -0x55555556, x3, 1116, x4)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55560a58, 0xb503, 0x55555555, x3, 1120, x4)
+
+inst_291:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb503; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xb506, 0xb503, 0x3, x3, 1124, x4)
+
+inst_292:
+// rs1_val==0 and rs2_val==46341, rs1_val == 0
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb505, 0x0, 0xb505, x3, 1128, x4)
+
+inst_293:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4afd, 0x0, -0xb503, x3, 1132, x4)
+
+inst_294:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x0, 0x66666667, x3, 1136, x4)
+
+inst_295:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33333334, 0x0, 0x33333334, x3, 1140, x4)
+
+inst_296:
+// rs1_val==0 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x6, 0x0, 0x6, x3, 1144, x4)
+
+inst_297:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x3, 1148, x4)
+
+inst_298:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55555556, 0x0, 0x55555556, x3, 1152, x4)
+
+inst_299:
+// rs1_val==0 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x4, 0x0, 0x4, x3, 1156, x4)
+
+inst_300:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb503, 0x0, 0xb503, x3, 1160, x4)
+
+inst_301:
+// rs1_val==0 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x0, 0x0, 0x0, x3, 1164, x4)
+
+inst_302:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66666665, 0x0, 0x66666665, x3, 1168, x4)
+
+inst_303:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333332, 0x0, 0x33333332, x3, 1172, x4)
+
+inst_304:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55555554, 0x0, 0x55555554, x3, 1176, x4)
+
+inst_305:
+// rs1_val==0 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x2, 0x0, 0x2, x3, 1180, x4)
+
+inst_306:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb504, 0x0, 0xb504, x3, 1184, x4)
+
+inst_307:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4afc, 0x0, -0xb504, x3, 1188, x4)
+
+inst_308:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66666666, 0x0, 0x66666666, x3, 1192, x4)
+
+inst_309:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333333, 0x0, 0x33333333, x3, 1196, x4)
+
+inst_310:
+// rs1_val==0 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x5, 0x0, 0x5, x3, 1200, x4)
+
+inst_311:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x3, 1204, x4)
+
+inst_312:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555555, 0x0, 0x55555555, x3, 1208, x4)
+
+inst_313:
+// rs1_val==0 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x0; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x3, 0x0, 0x3, x3, 1212, x4)
+
+inst_314:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0x66666665, 0xb505, x3, 1216, x4)
+
+inst_315:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x6665b162, 0x66666665, -0xb503, x3, 1220, x4)
+
+inst_316:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xcccccccc, 0x66666665, 0x66666667, x3, 1224, x4)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x66666665, 0x33333334, x3, 1228, x4)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x66666665, 0x6, x3, 1232, x4)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x11111110, 0x66666665, -0x55555555, x3, 1236, x4)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x66666665, 0x55555556, x3, 1240, x4)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x66666665, 0x4, x3, 1244, x4)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x66671b68, 0x66666665, 0xb503, x3, 1248, x4)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x66666665, 0x66666665, 0x0, x3, 1252, x4)
+
+inst_324:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x33333333, 0x33333333, 0x0, x3, 1256, x4)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x99999998, 0x33333333, 0x66666665, x3, 1260, x4)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x66666665, 0x33333333, 0x33333332, x3, 1264, x4)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x88888887, 0x33333333, 0x55555554, x3, 1268, x4)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x33333335, 0x33333333, 0x2, x3, 1272, x4)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0x33333333, 0xb504, x3, 1276, x4)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x33327e2f, 0x33333333, -0xb504, x3, 1280, x4)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x33333333, 0x66666666, x3, 1284, x4)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x66666666, 0x33333333, 0x33333333, x3, 1288, x4)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x33333333, 0x5, x3, 1292, x4)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xdddddddd, 0x33333333, -0x55555556, x3, 1296, x4)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x33333333, 0x55555555, x3, 1300, x4)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x33333333, 0x3, x3, 1304, x4)
+
+inst_337:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb50a, 0x5, 0xb505, x3, 1308, x4)
+
+inst_338:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4b02, 0x5, -0xb503, x3, 1312, x4)
+
+inst_339:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6666666c, 0x5, 0x66666667, x3, 1316, x4)
+
+inst_340:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33333339, 0x5, 0x33333334, x3, 1320, x4)
+
+inst_341:
+// rs1_val==5 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xb, 0x5, 0x6, x3, 1324, x4)
+
+inst_342:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab0, 0x5, -0x55555555, x3, 1328, x4)
+
+inst_343:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x5555555b, 0x5, 0x55555556, x3, 1332, x4)
+
+inst_344:
+// rs1_val==5 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x9, 0x5, 0x4, x3, 1336, x4)
+
+inst_345:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0x5, 0xb503, x3, 1340, x4)
+
+inst_346:
+// rs1_val==5 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x5, 0x5, 0x0, x3, 1344, x4)
+
+inst_347:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x5, 0x66666665, x3, 1348, x4)
+
+inst_348:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x5, 0x33333332, x3, 1352, x4)
+
+inst_349:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x5, 0x55555554, x3, 1356, x4)
+
+inst_350:
+// rs1_val==5 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x7, 0x5, 0x2, x3, 1360, x4)
+
+inst_351:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0x5, 0xb504, x3, 1364, x4)
+
+inst_352:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4b01, 0x5, -0xb504, x3, 1368, x4)
+
+inst_353:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x5, 0x66666666, x3, 1372, x4)
+
+inst_354:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x5, 0x33333333, x3, 1376, x4)
+
+inst_355:
+// rs1_val==5 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xa, 0x5, 0x5, x3, 1380, x4)
+
+inst_356:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x3, 1384, x4)
+
+inst_357:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x5, 0x55555555, x3, 1388, x4)
+
+inst_358:
+// rs1_val==5 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x5; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x8, 0x5, 0x3, x3, 1392, x4)
+
+inst_359:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xaaab5faf, -0x55555556, 0xb505, x3, 1396, x4)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a7, -0x55555556, -0xb503, x3, 1400, x4)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x11111111, -0x55555556, 0x66666667, x3, 1404, x4)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0xddddddde, -0x55555556, 0x33333334, x3, 1408, x4)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaab0, -0x55555556, 0x6, x3, 1412, x4)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555555, -0x55555556, -0x55555555, x3, 1416, x4)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x0, -0x55555556, 0x55555556, x3, 1420, x4)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x3, 1424, x4)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fad, -0x55555556, 0xb503, x3, 1428, x4)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x3, 1432, x4)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x1111110f, -0x55555556, 0x66666665, x3, 1436, x4)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0xdddddddc, -0x55555556, 0x33333332, x3, 1440, x4)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x3, 1444, x4)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaac, -0x55555556, 0x2, x3, 1448, x4)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fae, -0x55555556, 0xb504, x3, 1452, x4)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a6, -0x55555556, -0xb504, x3, 1456, x4)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x11111110, -0x55555556, 0x66666666, x3, 1460, x4)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0xdddddddd, -0x55555556, 0x33333333, x3, 1464, x4)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x3, 1468, x4)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55555554, -0x55555556, -0x55555556, x3, 1472, x4)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x3, 1476, x4)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaad, -0x55555556, 0x3, x3, 1480, x4)
+
+inst_381:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x55560a5a, 0x55555555, 0xb505, x3, 1484, x4)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x5554a052, 0x55555555, -0xb503, x3, 1488, x4)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbc, 0x55555555, 0x66666667, x3, 1492, x4)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x88888889, 0x55555555, 0x33333334, x3, 1496, x4)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x5555555b, 0x55555555, 0x6, x3, 1500, x4)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x0, 0x55555555, -0x55555555, x3, 1504, x4)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaab, 0x55555555, 0x55555556, x3, 1508, x4)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x55555555, 0x4, x3, 1512, x4)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x55560a58, 0x55555555, 0xb503, x3, 1516, x4)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x55555555, 0x55555555, 0x0, x3, 1520, x4)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbba, 0x55555555, 0x66666665, x3, 1524, x4)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x88888887, 0x55555555, 0x33333332, x3, 1528, x4)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaa9, 0x55555555, 0x55555554, x3, 1532, x4)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x55555557, 0x55555555, 0x2, x3, 1536, x4)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0x55555555, 0xb504, x3, 1540, x4)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x5554a051, 0x55555555, -0xb504, x3, 1544, x4)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x55555555, 0x66666666, x3, 1548, x4)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x55555555, 0x33333333, x3, 1552, x4)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x55555555, 0x5, x3, 1556, x4)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x3, 1560, x4)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaa, 0x55555555, 0x55555555, x3, 1564, x4)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555555; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x55555555, 0x3, x3, 1568, x4)
+
+inst_403:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0x3, 0xb505, x3, 1572, x4)
+
+inst_404:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4b00, 0x3, -0xb503, x3, 1576, x4)
+
+inst_405:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x3, 0x66666667, x3, 1580, x4)
+
+inst_406:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x3, 0x33333334, x3, 1584, x4)
+
+inst_407:
+// rs1_val==3 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x9, 0x3, 0x6, x3, 1588, x4)
+
+inst_408:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaae, 0x3, -0x55555555, x3, 1592, x4)
+
+inst_409:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x3, 0x55555556, x3, 1596, x4)
+
+inst_410:
+// rs1_val==3 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x7, 0x3, 0x4, x3, 1600, x4)
+
+inst_411:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb506, 0x3, 0xb503, x3, 1604, x4)
+
+inst_412:
+// rs1_val==3 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x3, 0x3, 0x0, x3, 1608, x4)
+
+inst_413:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66666668, 0x3, 0x66666665, x3, 1612, x4)
+
+inst_414:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333335, 0x3, 0x33333332, x3, 1616, x4)
+
+inst_415:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55555557, 0x3, 0x55555554, x3, 1620, x4)
+
+inst_416:
+// rs1_val==3 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x5, 0x3, 0x2, x3, 1624, x4)
+
+inst_417:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0x3, 0xb504, x3, 1628, x4)
+
+inst_418:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4aff, 0x3, -0xb504, x3, 1632, x4)
+
+inst_419:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x3, 0x66666666, x3, 1636, x4)
+
+inst_420:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x3, 0x33333333, x3, 1640, x4)
+
+inst_421:
+// rs1_val==3 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x8, 0x3, 0x5, x3, 1644, x4)
+
+inst_422:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaad, 0x3, -0x55555556, x3, 1648, x4)
+
+inst_423:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x3, 0x55555555, x3, 1652, x4)
+
+inst_424:
+// rs1_val==3 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x3; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x6, 0x3, 0x3, x3, 1656, x4)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xccccccca, 0x66666665, 0x66666665, x3, 1660, x4)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x99999997, 0x66666665, 0x33333332, x3, 1664, x4)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbb9, 0x66666665, 0x55555554, x3, 1668, x4)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x66666665, 0x2, x3, 1672, x4)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x66671b69, 0x66666665, 0xb504, x3, 1676, x4)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x6665b161, 0x66666665, -0xb504, x3, 1680, x4)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xcccccccb, 0x66666665, 0x66666666, x3, 1684, x4)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x99999998, 0x66666665, 0x33333333, x3, 1688, x4)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x66666665, 0x5, x3, 1692, x4)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x1111110f, 0x66666665, -0x55555556, x3, 1696, x4)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbba, 0x66666665, 0x55555555, x3, 1700, x4)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666665; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x66666668, 0x66666665, 0x3, x3, 1704, x4)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0x33333332, 0xb505, x3, 1708, x4)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x33327e2f, 0x33333332, -0xb503, x3, 1712, x4)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x33333332, 0x66666667, x3, 1716, x4)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x66666666, 0x33333332, 0x33333334, x3, 1720, x4)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x33333338, 0x33333332, 0x6, x3, 1724, x4)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xdddddddd, 0x33333332, -0x55555555, x3, 1728, x4)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x33333332, 0x55555556, x3, 1732, x4)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x33333332, 0x4, x3, 1736, x4)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x3333e835, 0x33333332, 0xb503, x3, 1740, x4)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x33333332, 0x33333332, 0x0, x3, 1744, x4)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x99999997, 0x33333332, 0x66666665, x3, 1748, x4)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x66666664, 0x33333332, 0x33333332, x3, 1752, x4)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x88888886, 0x33333332, 0x55555554, x3, 1756, x4)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x33333334, 0x33333332, 0x2, x3, 1760, x4)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x3333e836, 0x33333332, 0xb504, x3, 1764, x4)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x33327e2e, 0x33333332, -0xb504, x3, 1768, x4)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x99999998, 0x33333332, 0x66666666, x3, 1772, x4)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x66666665, 0x33333332, 0x33333333, x3, 1776, x4)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x33333332, 0x5, x3, 1780, x4)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xdddddddc, 0x33333332, -0x55555556, x3, 1784, x4)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x88888887, 0x33333332, 0x55555555, x3, 1788, x4)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333332; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x33333335, 0x33333332, 0x3, x3, 1792, x4)
+
+inst_459:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0x55555554, 0xb505, x3, 1796, x4)
+
+inst_460:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x5554a051, 0x55555554, -0xb503, x3, 1800, x4)
+
+inst_461:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x55555554, 0x66666667, x3, 1804, x4)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x88888888, 0x55555554, 0x33333334, x3, 1808, x4)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x5555555a, 0x55555554, 0x6, x3, 1812, x4)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x3, 1816, x4)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaaa, 0x55555554, 0x55555556, x3, 1820, x4)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x55555554, 0x4, x3, 1824, x4)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x55560a57, 0x55555554, 0xb503, x3, 1828, x4)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x55555554, 0x55555554, 0x0, x3, 1832, x4)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbb9, 0x55555554, 0x66666665, x3, 1836, x4)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x88888886, 0x55555554, 0x33333332, x3, 1840, x4)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaa8, 0x55555554, 0x55555554, x3, 1844, x4)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x55555556, 0x55555554, 0x2, x3, 1848, x4)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x55560a58, 0x55555554, 0xb504, x3, 1852, x4)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x5554a050, 0x55555554, -0xb504, x3, 1856, x4)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbba, 0x55555554, 0x66666666, x3, 1860, x4)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x88888887, 0x55555554, 0x33333333, x3, 1864, x4)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x55555559, 0x55555554, 0x5, x3, 1868, x4)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x3, 1872, x4)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaa9, 0x55555554, 0x55555555, x3, 1876, x4)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x55555554; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x55555557, 0x55555554, 0x3, x3, 1880, x4)
+
+inst_481:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0x2, 0xb505, x3, 1884, x4)
+
+inst_482:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffff4aff, 0x2, -0xb503, x3, 1888, x4)
+
+inst_483:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x2, 0x66666667, x3, 1892, x4)
+
+inst_484:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33333336, 0x2, 0x33333334, x3, 1896, x4)
+
+inst_485:
+// rs1_val==2 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x8, 0x2, 0x6, x3, 1900, x4)
+
+inst_486:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaad, 0x2, -0x55555555, x3, 1904, x4)
+
+inst_487:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55555558, 0x2, 0x55555556, x3, 1908, x4)
+
+inst_488:
+// rs1_val==2 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x6, 0x2, 0x4, x3, 1912, x4)
+
+inst_489:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xb505, 0x2, 0xb503, x3, 1916, x4)
+
+inst_490:
+// rs1_val==2 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x2, 0x2, 0x0, x3, 1920, x4)
+
+inst_491:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x2, 0x66666665, x3, 1924, x4)
+
+inst_492:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33333334, 0x2, 0x33333332, x3, 1928, x4)
+
+inst_493:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55555556, 0x2, 0x55555554, x3, 1932, x4)
+
+inst_494:
+// rs1_val==2 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x4, 0x2, 0x2, x3, 1936, x4)
+
+inst_495:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0xb506, 0x2, 0xb504, x3, 1940, x4)
+
+inst_496:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xffff4afe, 0x2, -0xb504, x3, 1944, x4)
+
+inst_497:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66666668, 0x2, 0x66666666, x3, 1948, x4)
+
+inst_498:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33333335, 0x2, 0x33333333, x3, 1952, x4)
+
+inst_499:
+// rs1_val==2 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x7, 0x2, 0x5, x3, 1956, x4)
+
+inst_500:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaaaaaac, 0x2, -0x55555556, x3, 1960, x4)
+
+inst_501:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55555557, 0x2, 0x55555555, x3, 1964, x4)
+
+inst_502:
+// rs1_val==2 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x5, 0x2, 0x3, x3, 1968, x4)
+
+inst_503:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x16a09, 0xb504, 0xb505, x3, 1972, x4)
+
+inst_504:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x1, 0xb504, -0xb503, x3, 1976, x4)
+
+inst_505:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x66671b6b, 0xb504, 0x66666667, x3, 1980, x4)
+
+inst_506:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x3333e838, 0xb504, 0x33333334, x3, 1984, x4)
+
+inst_507:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xb50a, 0xb504, 0x6, x3, 1988, x4)
+
+inst_508:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaab5faf, 0xb504, -0x55555555, x3, 1992, x4)
+
+inst_509:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x55560a5a, 0xb504, 0x55555556, x3, 1996, x4)
+
+inst_510:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xb508, 0xb504, 0x4, x3, 2000, x4)
+
+inst_511:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x16a07, 0xb504, 0xb503, x3, 2004, x4)
+
+inst_512:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xb504, 0xb504, 0x0, x3, 2008, x4)
+
+inst_513:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x66671b69, 0xb504, 0x66666665, x3, 2012, x4)
+
+inst_514:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x3333e836, 0xb504, 0x33333332, x3, 2016, x4)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x55560a58, 0xb504, 0x55555554, x3, 2020, x4)
+
+inst_516:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xb506, 0xb504, 0x2, x3, 2024, x4)
+
+inst_517:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x16a08, 0xb504, 0xb504, x3, 2028, x4)
+
+inst_518:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x0, 0xb504, -0xb504, x3, 2032, x4)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0xb504, 0x66666666, x3, 2036, x4)
+
+inst_520:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x3333e837, 0xb504, 0x33333333, x3, 2040, x4)
+
+inst_521:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xb509, 0xb504, 0x5, x3, 2044, x4)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_522:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaab5fae, 0xb504, -0x55555556, x3, 0, x4)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x55560a59, 0xb504, 0x55555555, x3, 4, x4)
+
+inst_524:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0xb504; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xb507, 0xb504, 0x3, x3, 8, x4)
+
+inst_525:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x1, -0xb504, 0xb505, x3, 12, x4)
+
+inst_526:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0xfffe95f9, -0xb504, -0xb503, x3, 16, x4)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x6665b163, -0xb504, 0x66666667, x3, 20, x4)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x33327e30, -0xb504, 0x33333334, x3, 24, x4)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0xffff4b02, -0xb504, 0x6, x3, 28, x4)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a7, -0xb504, -0x55555555, x3, 32, x4)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x5554a052, -0xb504, 0x55555556, x3, 36, x4)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0xffff4b00, -0xb504, 0x4, x3, 40, x4)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0xffffffff, -0xb504, 0xb503, x3, 44, x4)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0xffff4afc, -0xb504, 0x0, x3, 48, x4)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0x6665b161, -0xb504, 0x66666665, x3, 52, x4)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x33327e2e, -0xb504, 0x33333332, x3, 56, x4)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0x5554a050, -0xb504, 0x55555554, x3, 60, x4)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0xffff4afe, -0xb504, 0x2, x3, 64, x4)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x0, -0xb504, 0xb504, x3, 68, x4)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0xfffe95f8, -0xb504, -0xb504, x3, 72, x4)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0x6665b162, -0xb504, 0x66666666, x3, 76, x4)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x33327e2f, -0xb504, 0x33333333, x3, 80, x4)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0xffff4b01, -0xb504, 0x5, x3, 84, x4)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xaaa9f5a6, -0xb504, -0x55555556, x3, 88, x4)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x5554a051, -0xb504, 0x55555555, x3, 92, x4)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:-0xb504; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0xffff4aff, -0xb504, 0x3, x3, 96, x4)
+
+inst_547:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x66671b6b, 0x66666666, 0xb505, x3, 100, x4)
+
+inst_548:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x6665b163, 0x66666666, -0xb503, x3, 104, x4)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0xcccccccd, 0x66666666, 0x66666667, x3, 108, x4)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x9999999a, 0x66666666, 0x33333334, x3, 112, x4)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x6666666c, 0x66666666, 0x6, x3, 116, x4)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0x11111111, 0x66666666, -0x55555555, x3, 120, x4)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbc, 0x66666666, 0x55555556, x3, 124, x4)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x6666666a, 0x66666666, 0x4, x3, 128, x4)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x66671b69, 0x66666666, 0xb503, x3, 132, x4)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x0
+TEST_CR_OP( c.add, x10, x11, 0x66666666, 0x66666666, 0x0, x3, 136, x4)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665
+TEST_CR_OP( c.add, x10, x11, 0xcccccccb, 0x66666666, 0x66666665, x3, 140, x4)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332
+TEST_CR_OP( c.add, x10, x11, 0x99999998, 0x66666666, 0x33333332, x3, 144, x4)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbba, 0x66666666, 0x55555554, x3, 148, x4)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x2
+TEST_CR_OP( c.add, x10, x11, 0x66666668, 0x66666666, 0x2, x3, 152, x4)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504
+TEST_CR_OP( c.add, x10, x11, 0x66671b6a, 0x66666666, 0xb504, x3, 156, x4)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504
+TEST_CR_OP( c.add, x10, x11, 0x6665b162, 0x66666666, -0xb504, x3, 160, x4)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666
+TEST_CR_OP( c.add, x10, x11, 0xcccccccc, 0x66666666, 0x66666666, x3, 164, x4)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333
+TEST_CR_OP( c.add, x10, x11, 0x99999999, 0x66666666, 0x33333333, x3, 168, x4)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x5
+TEST_CR_OP( c.add, x10, x11, 0x6666666b, 0x66666666, 0x5, x3, 172, x4)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x11111110, 0x66666666, -0x55555556, x3, 176, x4)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xbbbbbbbb, 0x66666666, 0x55555555, x3, 180, x4)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x66666666; op2val:0x3
+TEST_CR_OP( c.add, x10, x11, 0x66666669, 0x66666666, 0x3, x3, 184, x4)
+
+inst_569:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505
+TEST_CR_OP( c.add, x10, x11, 0x3333e838, 0x33333333, 0xb505, x3, 188, x4)
+
+inst_570:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503
+TEST_CR_OP( c.add, x10, x11, 0x33327e30, 0x33333333, -0xb503, x3, 192, x4)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667
+TEST_CR_OP( c.add, x10, x11, 0x9999999a, 0x33333333, 0x66666667, x3, 196, x4)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334
+TEST_CR_OP( c.add, x10, x11, 0x66666667, 0x33333333, 0x33333334, x3, 200, x4)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x6
+TEST_CR_OP( c.add, x10, x11, 0x33333339, 0x33333333, 0x6, x3, 204, x4)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555
+TEST_CR_OP( c.add, x10, x11, 0xddddddde, 0x33333333, -0x55555555, x3, 208, x4)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556
+TEST_CR_OP( c.add, x10, x11, 0x88888889, 0x33333333, 0x55555556, x3, 212, x4)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0x4
+TEST_CR_OP( c.add, x10, x11, 0x33333337, 0x33333333, 0x4, x3, 216, x4)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: c.add; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503
+TEST_CR_OP( c.add, x10, x11, 0x3333e836, 0x33333333, 0xb503, x3, 220, x4)
+
+inst_578:
+// rs2_val == 2147483647, rs1_val == 8192, rs2_val == (2**(xlen-1)-1)
+// opcode: c.add; op1:x10; op2:x11; op1val:0x2000; op2val:0x7fffffff
+TEST_CR_OP( c.add, x10, x11, 0x80001fff, 0x2000, 0x7fffffff, x3, 224, x4)
+
+inst_579:
+// rs2_val == -16777217, rs1_val == -32769
+// opcode: c.add; op1:x10; op2:x11; op1val:-0x8001; op2val:-0x1000001
+TEST_CR_OP( c.add, x10, x11, 0xfeff7ffe, -0x8001, -0x1000001, x3, 228, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 10*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 58*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi-01.S
new file mode 100644
index 000000000..e66b5b4e7
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi-01.S
@@ -0,0 +1,1950 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.addi instruction of the RISC-V C extension for the caddi covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi)
+
+RVTEST_SIGBASE( x10,signature_x10_1)
+
+inst_0:
+// rd==x13, imm_val == (-2**(6-1)), rs1_val != imm_val, rs1_val > 0 and imm_val < 0, imm_val == -32, rs1_val == 8388608
+// opcode:c.addi; op1:x13; dest:x13 op1val:0x800000; immval:-0x20
+TEST_CI_OP( c.addi, x13, 0x7fffe0, 0x800000, -0x20, x10, 0, x8)
+
+inst_1:
+// rd==x2, rs1_val == 2147483647, imm_val == 4, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val > 0
+// opcode:c.addi; op1:x2; dest:x2 op1val:0x7fffffff; immval:0x4
+TEST_CI_OP( c.addi, x2, 0x80000003, 0x7fffffff, 0x4, x10, 4, x8)
+
+inst_2:
+// rd==x4, rs1_val == -1073741825, rs1_val < 0 and imm_val < 0
+// opcode:c.addi; op1:x4; dest:x4 op1val:-0x40000001; immval:-0x1
+TEST_CI_OP( c.addi, x4, 0xbffffffe, -0x40000001, -0x1, x10, 8, x8)
+
+inst_3:
+// rd==x7, rs1_val == -536870913, imm_val == 8, rs1_val < 0 and imm_val > 0
+// opcode:c.addi; op1:x7; dest:x7 op1val:-0x20000001; immval:0x8
+TEST_CI_OP( c.addi, x7, 0xe0000007, -0x20000001, 0x8, x10, 12, x8)
+
+inst_4:
+// rd==x11, rs1_val == -268435457, 
+// opcode:c.addi; op1:x11; dest:x11 op1val:-0x10000001; immval:0x4
+TEST_CI_OP( c.addi, x11, 0xf0000003, -0x10000001, 0x4, x10, 16, x8)
+
+inst_5:
+// rd==x6, rs1_val == -134217729, 
+// opcode:c.addi; op1:x6; dest:x6 op1val:-0x8000001; immval:0x5
+TEST_CI_OP( c.addi, x6, 0xf8000004, -0x8000001, 0x5, x10, 20, x8)
+
+inst_6:
+// rd==x9, rs1_val == -67108865, 
+// opcode:c.addi; op1:x9; dest:x9 op1val:-0x4000001; immval:0x4
+TEST_CI_OP( c.addi, x9, 0xfc000003, -0x4000001, 0x4, x10, 24, x8)
+
+inst_7:
+// rd==x5, rs1_val == -33554433, imm_val == -5
+// opcode:c.addi; op1:x5; dest:x5 op1val:-0x2000001; immval:-0x5
+TEST_CI_OP( c.addi, x5, 0xfdfffffa, -0x2000001, -0x5, x10, 28, x8)
+
+inst_8:
+// rd==x12, rs1_val == -16777217, imm_val == 16
+// opcode:c.addi; op1:x12; dest:x12 op1val:-0x1000001; immval:0x10
+TEST_CI_OP( c.addi, x12, 0xff00000f, -0x1000001, 0x10, x10, 32, x8)
+
+inst_9:
+// rd==x3, rs1_val == -8388609, 
+// opcode:c.addi; op1:x3; dest:x3 op1val:-0x800001; immval:-0x5
+TEST_CI_OP( c.addi, x3, 0xff7ffffa, -0x800001, -0x5, x10, 36, x8)
+
+inst_10:
+// rd==x1, rs1_val == -4194305, 
+// opcode:c.addi; op1:x1; dest:x1 op1val:-0x400001; immval:-0x20
+TEST_CI_OP( c.addi, x1, 0xffbfffdf, -0x400001, -0x20, x10, 40, x8)
+
+inst_11:
+// rd==x8, rs1_val == -2097153, imm_val == -2
+// opcode:c.addi; op1:x8; dest:x8 op1val:-0x200001; immval:-0x2
+TEST_CI_OP( c.addi, x8, 0xffdffffd, -0x200001, -0x2, x10, 44, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_12:
+// rd==x15, rs1_val == -1048577, 
+// opcode:c.addi; op1:x15; dest:x15 op1val:-0x100001; immval:-0x2
+TEST_CI_OP( c.addi, x15, 0xffeffffd, -0x100001, -0x2, x1, 0, x2)
+
+inst_13:
+// rd==x14, rs1_val == -524289, 
+// opcode:c.addi; op1:x14; dest:x14 op1val:-0x80001; immval:0x5
+TEST_CI_OP( c.addi, x14, 0xfff80004, -0x80001, 0x5, x1, 4, x2)
+
+inst_14:
+// rd==x10, rs1_val == -262145, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x40001; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xfffc0004, -0x40001, 0x5, x1, 8, x2)
+
+inst_15:
+// rs1_val == -131073, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x20001; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xfffe0003, -0x20001, 0x4, x1, 12, x2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x10001; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xfffefffa, -0x10001, -0x5, x1, 16, x2)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x8001; immval:-0x8
+TEST_CI_OP( c.addi, x10, 0xffff7ff7, -0x8001, -0x8, x1, 20, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x4001; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xffffc005, -0x4001, 0x6, x1, 24, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x2001; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xffffe002, -0x2001, 0x3, x1, 28, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x1001; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xffffeffd, -0x1001, -0x2, x1, 32, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x801; immval:-0x20
+TEST_CI_OP( c.addi, x10, 0xfffff7df, -0x801, -0x20, x1, 36, x2)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x401; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xfffffc03, -0x401, 0x4, x1, 40, x2)
+
+inst_23:
+// rs1_val == -513, imm_val == -17
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x201; immval:-0x11
+TEST_CI_OP( c.addi, x10, 0xfffffdee, -0x201, -0x11, x1, 44, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x101; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xfffffefe, -0x101, -0x1, x1, 48, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x81; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xffffff82, -0x81, 0x3, x1, 52, x2)
+
+inst_26:
+// rs1_val == -65, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x41; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xffffffba, -0x41, -0x5, x1, 56, x2)
+
+inst_27:
+// rs1_val == -33, imm_val == -22
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x21; immval:-0x16
+TEST_CI_OP( c.addi, x10, 0xffffffc9, -0x21, -0x16, x1, 60, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x11; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xffffffeb, -0x11, -0x4, x1, 64, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x9; immval:-0x10
+TEST_CI_OP( c.addi, x10, 0xffffffe7, -0x9, -0x10, x1, 68, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x5; immval:-0x10
+TEST_CI_OP( c.addi, x10, 0xffffffeb, -0x5, -0x10, x1, 72, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x3; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x1, -0x3, 0x4, x1, 76, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x2; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x5, -0x2, 0x7, x1, 80, x2)
+
+inst_33:
+// imm_val == 31, imm_val == (2**(6-1)-1)
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x3; immval:0x1f
+TEST_CI_OP( c.addi, x10, 0x1c, -0x3, 0x1f, x1, 84, x2)
+
+inst_34:
+// imm_val == -9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x10000001; immval:-0x9
+TEST_CI_OP( c.addi, x10, 0xeffffff6, -0x10000001, -0x9, x1, 88, x2)
+
+inst_35:
+// imm_val == -3, rs1_val == 524288
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x80000; immval:-0x3
+TEST_CI_OP( c.addi, x10, 0x7fffd, 0x80000, -0x3, x1, 92, x2)
+
+inst_36:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x80000000; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x80000009, -0x80000000, 0x9, x1, 96, x2)
+
+inst_37:
+// rs1_val == 1073741824, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x40000000; immval:-0x16
+TEST_CI_OP( c.addi, x10, 0x3fffffea, 0x40000000, -0x16, x1, 100, x2)
+
+inst_38:
+// rs1_val == 536870912, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x20000000; immval:0x10
+TEST_CI_OP( c.addi, x10, 0x20000010, 0x20000000, 0x10, x1, 104, x2)
+
+inst_39:
+// rs1_val == 268435456, imm_val == 0
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x10000000; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x10000000, 0x10000000, 0x0, x1, 108, x2)
+
+inst_40:
+// rs1_val == 134217728, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x8000000; immval:0x10
+TEST_CI_OP( c.addi, x10, 0x8000010, 0x8000000, 0x10, x1, 112, x2)
+
+inst_41:
+// rs1_val == 67108864, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4000000; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x4000005, 0x4000000, 0x5, x1, 116, x2)
+
+inst_42:
+// rs1_val == 33554432, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2000000; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x2000006, 0x2000000, 0x6, x1, 120, x2)
+
+inst_43:
+// rs1_val == 16777216, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x1000000; immval:0x8
+TEST_CI_OP( c.addi, x10, 0x1000008, 0x1000000, 0x8, x1, 124, x2)
+
+inst_44:
+// rs1_val == 4194304, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x400000; immval:0xf
+TEST_CI_OP( c.addi, x10, 0x40000f, 0x400000, 0xf, x1, 128, x2)
+
+inst_45:
+// rs1_val == 2097152, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x200000; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x200009, 0x200000, 0x9, x1, 132, x2)
+
+inst_46:
+// rs1_val == 1048576, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x100000; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x100009, 0x100000, 0x9, x1, 136, x2)
+
+inst_47:
+// rs1_val == 262144, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x40000; immval:0xf
+TEST_CI_OP( c.addi, x10, 0x4000f, 0x40000, 0xf, x1, 140, x2)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x20000; immval:-0x16
+TEST_CI_OP( c.addi, x10, 0x1ffea, 0x20000, -0x16, x1, 144, x2)
+
+inst_49:
+// rs1_val == 65536, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x10000; immval:-0x10
+TEST_CI_OP( c.addi, x10, 0xfff0, 0x10000, -0x10, x1, 148, x2)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x8000; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x8006, 0x8000, 0x6, x1, 152, x2)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4000; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x4005, 0x4000, 0x5, x1, 156, x2)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2000; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x2007, 0x2000, 0x7, x1, 160, x2)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x1000; immval:-0x7
+TEST_CI_OP( c.addi, x10, 0xff9, 0x1000, -0x7, x1, 164, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x800; immval:-0xa
+TEST_CI_OP( c.addi, x10, 0x7f6, 0x800, -0xa, x1, 168, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x400; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x3fe, 0x400, -0x2, x1, 172, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x200; immval:-0x11
+TEST_CI_OP( c.addi, x10, 0x1ef, 0x200, -0x11, x1, 176, x2)
+
+inst_57:
+// rs1_val == 256, imm_val == 1
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x100; immval:0x1
+TEST_CI_OP( c.addi, x10, 0x101, 0x100, 0x1, x1, 180, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x80; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x84, 0x80, 0x4, x1, 184, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x40; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x46, 0x40, 0x6, x1, 188, x2)
+
+inst_60:
+// rs1_val == 32, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x20; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x24, 0x20, 0x4, x1, 192, x2)
+
+inst_61:
+// rs1_val == 16, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x10; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x13, 0x10, 0x3, x1, 196, x2)
+
+inst_62:
+// rs1_val == 8, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x8; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xc, 0x8, 0x4, x1, 200, x2)
+
+inst_63:
+// rs1_val == 4, rs1_val==4 and imm_val==0
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x4, 0x4, 0x0, x1, 204, x2)
+
+inst_64:
+// rs1_val == 2, rs1_val==2 and imm_val==-1
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x1, 0x2, -0x1, x1, 208, x2)
+
+inst_65:
+// rs1_val == 1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x1; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x5, 0x1, 0x4, x1, 212, x2)
+
+inst_66:
+// imm_val == 2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x1; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x1, -0x1, 0x2, x1, 216, x2)
+
+inst_67:
+// rs1_val==46341 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xb50b, 0xb505, 0x6, x1, 220, x2)
+
+inst_68:
+// rs1_val==46341 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xb501, 0xb505, -0x4, x1, 224, x2)
+
+inst_69:
+// rs1_val==46341 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xb504, 0xb505, -0x1, x1, 228, x2)
+
+inst_70:
+// rs1_val==46341 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xb50c, 0xb505, 0x7, x1, 232, x2)
+
+inst_71:
+// rs1_val==46341 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xb509, 0xb505, 0x4, x1, 236, x2)
+
+inst_72:
+// rs1_val==46341 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xb510, 0xb505, 0xb, x1, 240, x2)
+
+inst_73:
+// rs1_val==46341 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xb505, 0xb505, 0x0, x1, 244, x2)
+
+inst_74:
+// rs1_val==46341 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xb50a, 0xb505, 0x5, x1, 248, x2)
+
+inst_75:
+// rs1_val==46341 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xb507, 0xb505, 0x2, x1, 252, x2)
+
+inst_76:
+// rs1_val==46341 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xb50e, 0xb505, 0x9, x1, 256, x2)
+
+inst_77:
+// rs1_val==46341 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xb500, 0xb505, -0x5, x1, 260, x2)
+
+inst_78:
+// rs1_val==46341 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xb503, 0xb505, -0x2, x1, 264, x2)
+
+inst_79:
+// rs1_val==46341 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xb508, 0xb505, 0x3, x1, 268, x2)
+
+inst_80:
+// rs1_val==46341 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb505; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xb50f, 0xb505, 0xa, x1, 272, x2)
+
+inst_81:
+// rs1_val==-46339 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xffff4b03, -0xb503, 0x6, x1, 276, x2)
+
+inst_82:
+// rs1_val==-46339 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xffff4af9, -0xb503, -0x4, x1, 280, x2)
+
+inst_83:
+// rs1_val==-46339 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xffff4afc, -0xb503, -0x1, x1, 284, x2)
+
+inst_84:
+// rs1_val==-46339 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xffff4b04, -0xb503, 0x7, x1, 288, x2)
+
+inst_85:
+// rs1_val==-46339 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xffff4b01, -0xb503, 0x4, x1, 292, x2)
+
+inst_86:
+// rs1_val==-46339 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xffff4b08, -0xb503, 0xb, x1, 296, x2)
+
+inst_87:
+// rs1_val==-46339 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xffff4afd, -0xb503, 0x0, x1, 300, x2)
+
+inst_88:
+// rs1_val==-46339 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xffff4b02, -0xb503, 0x5, x1, 304, x2)
+
+inst_89:
+// rs1_val==-46339 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xffff4aff, -0xb503, 0x2, x1, 308, x2)
+
+inst_90:
+// rs1_val==-46339 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xffff4b06, -0xb503, 0x9, x1, 312, x2)
+
+inst_91:
+// rs1_val==-46339 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xffff4af8, -0xb503, -0x5, x1, 316, x2)
+
+inst_92:
+// rs1_val==-46339 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xffff4afb, -0xb503, -0x2, x1, 320, x2)
+
+inst_93:
+// rs1_val==-46339 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xffff4b00, -0xb503, 0x3, x1, 324, x2)
+
+inst_94:
+// rs1_val==-46339 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb503; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xffff4b07, -0xb503, 0xa, x1, 328, x2)
+
+inst_95:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x6666666d, 0x66666667, 0x6, x1, 332, x2)
+
+inst_96:
+// rs1_val==1717986919 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x66666663, 0x66666667, -0x4, x1, 336, x2)
+
+inst_97:
+// rs1_val==1717986919 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x66666666, 0x66666667, -0x1, x1, 340, x2)
+
+inst_98:
+// rs1_val==1717986919 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x6666666e, 0x66666667, 0x7, x1, 344, x2)
+
+inst_99:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x6666666b, 0x66666667, 0x4, x1, 348, x2)
+
+inst_100:
+// rs1_val==1717986919 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x66666672, 0x66666667, 0xb, x1, 352, x2)
+
+inst_101:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x66666667, 0x66666667, 0x0, x1, 356, x2)
+
+inst_102:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x6666666c, 0x66666667, 0x5, x1, 360, x2)
+
+inst_103:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x66666669, 0x66666667, 0x2, x1, 364, x2)
+
+inst_104:
+// rs1_val==1717986919 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x66666670, 0x66666667, 0x9, x1, 368, x2)
+
+inst_105:
+// rs1_val==1717986919 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x66666662, 0x66666667, -0x5, x1, 372, x2)
+
+inst_106:
+// rs1_val==1717986919 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x66666665, 0x66666667, -0x2, x1, 376, x2)
+
+inst_107:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x6666666a, 0x66666667, 0x3, x1, 380, x2)
+
+inst_108:
+// rs1_val==1717986919 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666667; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x66666671, 0x66666667, 0xa, x1, 384, x2)
+
+inst_109:
+// rs1_val==858993460 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x3333333a, 0x33333334, 0x6, x1, 388, x2)
+
+inst_110:
+// rs1_val==858993460 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x33333330, 0x33333334, -0x4, x1, 392, x2)
+
+inst_111:
+// rs1_val==858993460 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x33333333, 0x33333334, -0x1, x1, 396, x2)
+
+inst_112:
+// rs1_val==858993460 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x3333333b, 0x33333334, 0x7, x1, 400, x2)
+
+inst_113:
+// rs1_val==858993460 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x33333338, 0x33333334, 0x4, x1, 404, x2)
+
+inst_114:
+// rs1_val==858993460 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x3333333f, 0x33333334, 0xb, x1, 408, x2)
+
+inst_115:
+// rs1_val==858993460 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x33333334, 0x33333334, 0x0, x1, 412, x2)
+
+inst_116:
+// rs1_val==858993460 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x33333339, 0x33333334, 0x5, x1, 416, x2)
+
+inst_117:
+// rs1_val==858993460 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x33333336, 0x33333334, 0x2, x1, 420, x2)
+
+inst_118:
+// rs1_val==858993460 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x3333333d, 0x33333334, 0x9, x1, 424, x2)
+
+inst_119:
+// rs1_val==858993460 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x3333332f, 0x33333334, -0x5, x1, 428, x2)
+
+inst_120:
+// rs1_val==858993460 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x33333332, 0x33333334, -0x2, x1, 432, x2)
+
+inst_121:
+// rs1_val==858993460 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x33333337, 0x33333334, 0x3, x1, 436, x2)
+
+inst_122:
+// rs1_val==858993460 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333334; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x3333333e, 0x33333334, 0xa, x1, 440, x2)
+
+inst_123:
+// rs1_val==6 and imm_val==6, rs1_val == imm_val
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xc, 0x6, 0x6, x1, 444, x2)
+
+inst_124:
+// rs1_val==6 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x2, 0x6, -0x4, x1, 448, x2)
+
+inst_125:
+// rs1_val==6 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x5, 0x6, -0x1, x1, 452, x2)
+
+inst_126:
+// rs1_val==6 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xd, 0x6, 0x7, x1, 456, x2)
+
+inst_127:
+// rs1_val==6 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xa, 0x6, 0x4, x1, 460, x2)
+
+inst_128:
+// rs1_val==6 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x11, 0x6, 0xb, x1, 464, x2)
+
+inst_129:
+// rs1_val==6 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x6, 0x6, 0x0, x1, 468, x2)
+
+inst_130:
+// rs1_val==6 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xb, 0x6, 0x5, x1, 472, x2)
+
+inst_131:
+// rs1_val==6 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x8, 0x6, 0x2, x1, 476, x2)
+
+inst_132:
+// rs1_val==6 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xf, 0x6, 0x9, x1, 480, x2)
+
+inst_133:
+// rs1_val==6 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x1, 0x6, -0x5, x1, 484, x2)
+
+inst_134:
+// rs1_val==6 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x4, 0x6, -0x2, x1, 488, x2)
+
+inst_135:
+// rs1_val==6 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x9, 0x6, 0x3, x1, 492, x2)
+
+inst_136:
+// rs1_val==6 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x10, 0x6, 0xa, x1, 496, x2)
+
+inst_137:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xaaaaaab1, -0x55555555, 0x6, x1, 500, x2)
+
+inst_138:
+// rs1_val==-1431655765 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa7, -0x55555555, -0x4, x1, 504, x2)
+
+inst_139:
+// rs1_val==-1431655765 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xaaaaaaaa, -0x55555555, -0x1, x1, 508, x2)
+
+inst_140:
+// rs1_val==-1431655765 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xaaaaaab2, -0x55555555, 0x7, x1, 512, x2)
+
+inst_141:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xaaaaaaaf, -0x55555555, 0x4, x1, 516, x2)
+
+inst_142:
+// rs1_val==-1431655765 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xaaaaaab6, -0x55555555, 0xb, x1, 520, x2)
+
+inst_143:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xaaaaaaab, -0x55555555, 0x0, x1, 524, x2)
+
+inst_144:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xaaaaaab0, -0x55555555, 0x5, x1, 528, x2)
+
+inst_145:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xaaaaaaad, -0x55555555, 0x2, x1, 532, x2)
+
+inst_146:
+// rs1_val==-1431655765 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xaaaaaab4, -0x55555555, 0x9, x1, 536, x2)
+
+inst_147:
+// rs1_val==-1431655765 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa6, -0x55555555, -0x5, x1, 540, x2)
+
+inst_148:
+// rs1_val==-1431655765 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa9, -0x55555555, -0x2, x1, 544, x2)
+
+inst_149:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xaaaaaaae, -0x55555555, 0x3, x1, 548, x2)
+
+inst_150:
+// rs1_val==-1431655765 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555555; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xaaaaaab5, -0x55555555, 0xa, x1, 552, x2)
+
+inst_151:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x5555555c, 0x55555556, 0x6, x1, 556, x2)
+
+inst_152:
+// rs1_val==1431655766 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x55555552, 0x55555556, -0x4, x1, 560, x2)
+
+inst_153:
+// rs1_val==1431655766 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x55555555, 0x55555556, -0x1, x1, 564, x2)
+
+inst_154:
+// rs1_val==1431655766 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x5555555d, 0x55555556, 0x7, x1, 568, x2)
+
+inst_155:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x5555555a, 0x55555556, 0x4, x1, 572, x2)
+
+inst_156:
+// rs1_val==1431655766 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x55555561, 0x55555556, 0xb, x1, 576, x2)
+
+inst_157:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x55555556, 0x55555556, 0x0, x1, 580, x2)
+
+inst_158:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x5555555b, 0x55555556, 0x5, x1, 584, x2)
+
+inst_159:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x55555558, 0x55555556, 0x2, x1, 588, x2)
+
+inst_160:
+// rs1_val==1431655766 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x5555555f, 0x55555556, 0x9, x1, 592, x2)
+
+inst_161:
+// rs1_val==1431655766 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x55555551, 0x55555556, -0x5, x1, 596, x2)
+
+inst_162:
+// rs1_val==1431655766 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x55555554, 0x55555556, -0x2, x1, 600, x2)
+
+inst_163:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x55555559, 0x55555556, 0x3, x1, 604, x2)
+
+inst_164:
+// rs1_val==1431655766 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555556; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x55555560, 0x55555556, 0xa, x1, 608, x2)
+
+inst_165:
+// rs1_val==4 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xa, 0x4, 0x6, x1, 612, x2)
+
+inst_166:
+// rs1_val==4 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x0, 0x4, -0x4, x1, 616, x2)
+
+inst_167:
+// rs1_val==4 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x3, 0x4, -0x1, x1, 620, x2)
+
+inst_168:
+// rs1_val==4 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xb, 0x4, 0x7, x1, 624, x2)
+
+inst_169:
+// rs1_val==4 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x8, 0x4, 0x4, x1, 628, x2)
+
+inst_170:
+// rs1_val==4 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xf, 0x4, 0xb, x1, 632, x2)
+
+inst_171:
+// rs1_val==4 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x9, 0x4, 0x5, x1, 636, x2)
+
+inst_172:
+// rs1_val==4 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x6, 0x4, 0x2, x1, 640, x2)
+
+inst_173:
+// rs1_val==4 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xd, 0x4, 0x9, x1, 644, x2)
+
+inst_174:
+// rs1_val==4 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xffffffff, 0x4, -0x5, x1, 648, x2)
+
+inst_175:
+// rs1_val==4 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x2, 0x4, -0x2, x1, 652, x2)
+
+inst_176:
+// rs1_val==4 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x7, 0x4, 0x3, x1, 656, x2)
+
+inst_177:
+// rs1_val==4 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x4; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xe, 0x4, 0xa, x1, 660, x2)
+
+inst_178:
+// rs1_val==46339 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xb509, 0xb503, 0x6, x1, 664, x2)
+
+inst_179:
+// rs1_val==46339 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xb4ff, 0xb503, -0x4, x1, 668, x2)
+
+inst_180:
+// rs1_val==46339 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xb502, 0xb503, -0x1, x1, 672, x2)
+
+inst_181:
+// rs1_val==46339 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xb50a, 0xb503, 0x7, x1, 676, x2)
+
+inst_182:
+// rs1_val==46339 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xb507, 0xb503, 0x4, x1, 680, x2)
+
+inst_183:
+// rs1_val==46339 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xb50e, 0xb503, 0xb, x1, 684, x2)
+
+inst_184:
+// rs1_val==46339 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xb503, 0xb503, 0x0, x1, 688, x2)
+
+inst_185:
+// rs1_val==46339 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xb508, 0xb503, 0x5, x1, 692, x2)
+
+inst_186:
+// rs1_val==46339 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xb505, 0xb503, 0x2, x1, 696, x2)
+
+inst_187:
+// rs1_val==46339 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xb50c, 0xb503, 0x9, x1, 700, x2)
+
+inst_188:
+// rs1_val==46339 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xb4fe, 0xb503, -0x5, x1, 704, x2)
+
+inst_189:
+// rs1_val==46339 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xb501, 0xb503, -0x2, x1, 708, x2)
+
+inst_190:
+// rs1_val==46339 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xb506, 0xb503, 0x3, x1, 712, x2)
+
+inst_191:
+// rs1_val==46339 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb503; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xb50d, 0xb503, 0xa, x1, 716, x2)
+
+inst_192:
+// rs1_val==0 and imm_val==6, rs1_val == 0
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x6, 0x0, 0x6, x1, 720, x2)
+
+inst_193:
+// rs1_val==0 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xfffffffc, 0x0, -0x4, x1, 724, x2)
+
+inst_194:
+// rs1_val==0 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xffffffff, 0x0, -0x1, x1, 728, x2)
+
+inst_195:
+// rs1_val==0 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x7, 0x0, 0x7, x1, 732, x2)
+
+inst_196:
+// rs1_val==0 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x4, 0x0, 0x4, x1, 736, x2)
+
+inst_197:
+// rs1_val==0 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xb, 0x0, 0xb, x1, 740, x2)
+
+inst_198:
+// rs1_val==0 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x0, 0x0, 0x0, x1, 744, x2)
+
+inst_199:
+// rs1_val==0 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x5, 0x0, 0x5, x1, 748, x2)
+
+inst_200:
+// rs1_val==0 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x2, 0x0, 0x2, x1, 752, x2)
+
+inst_201:
+// rs1_val==0 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x9, 0x0, 0x9, x1, 756, x2)
+
+inst_202:
+// rs1_val==0 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xfffffffb, 0x0, -0x5, x1, 760, x2)
+
+inst_203:
+// rs1_val==0 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xfffffffe, 0x0, -0x2, x1, 764, x2)
+
+inst_204:
+// rs1_val==0 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x3, 0x0, 0x3, x1, 768, x2)
+
+inst_205:
+// rs1_val==0 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x0; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xa, 0x0, 0xa, x1, 772, x2)
+
+inst_206:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x6666666b, 0x66666665, 0x6, x1, 776, x2)
+
+inst_207:
+// rs1_val==1717986917 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x66666661, 0x66666665, -0x4, x1, 780, x2)
+
+inst_208:
+// rs1_val==1717986917 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x66666664, 0x66666665, -0x1, x1, 784, x2)
+
+inst_209:
+// rs1_val==1717986917 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x6666666c, 0x66666665, 0x7, x1, 788, x2)
+
+inst_210:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x66666669, 0x66666665, 0x4, x1, 792, x2)
+
+inst_211:
+// rs1_val==1717986917 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x66666670, 0x66666665, 0xb, x1, 796, x2)
+
+inst_212:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x66666665, 0x66666665, 0x0, x1, 800, x2)
+
+inst_213:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x6666666a, 0x66666665, 0x5, x1, 804, x2)
+
+inst_214:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x66666667, 0x66666665, 0x2, x1, 808, x2)
+
+inst_215:
+// rs1_val==1717986917 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x6666666e, 0x66666665, 0x9, x1, 812, x2)
+
+inst_216:
+// rs1_val==1717986917 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x66666660, 0x66666665, -0x5, x1, 816, x2)
+
+inst_217:
+// rs1_val==1717986917 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x66666663, 0x66666665, -0x2, x1, 820, x2)
+
+inst_218:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x66666668, 0x66666665, 0x3, x1, 824, x2)
+
+inst_219:
+// rs1_val==1717986917 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666665; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x6666666f, 0x66666665, 0xa, x1, 828, x2)
+
+inst_220:
+// rs1_val==858993458 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x33333338, 0x33333332, 0x6, x1, 832, x2)
+
+inst_221:
+// rs1_val==858993458 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x3333332e, 0x33333332, -0x4, x1, 836, x2)
+
+inst_222:
+// rs1_val==858993458 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x33333331, 0x33333332, -0x1, x1, 840, x2)
+
+inst_223:
+// rs1_val==858993458 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x33333339, 0x33333332, 0x7, x1, 844, x2)
+
+inst_224:
+// rs1_val==858993458 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x33333336, 0x33333332, 0x4, x1, 848, x2)
+
+inst_225:
+// rs1_val==858993458 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x3333333d, 0x33333332, 0xb, x1, 852, x2)
+
+inst_226:
+// rs1_val==858993458 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x33333332, 0x33333332, 0x0, x1, 856, x2)
+
+inst_227:
+// rs1_val==858993458 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x33333337, 0x33333332, 0x5, x1, 860, x2)
+
+inst_228:
+// rs1_val==858993458 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x33333334, 0x33333332, 0x2, x1, 864, x2)
+
+inst_229:
+// rs1_val==858993458 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x3333333b, 0x33333332, 0x9, x1, 868, x2)
+
+inst_230:
+// rs1_val==858993458 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x3333332d, 0x33333332, -0x5, x1, 872, x2)
+
+inst_231:
+// rs1_val==858993458 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x33333330, 0x33333332, -0x2, x1, 876, x2)
+
+inst_232:
+// rs1_val==858993458 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x33333335, 0x33333332, 0x3, x1, 880, x2)
+
+inst_233:
+// rs1_val==858993458 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333332; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x3333333c, 0x33333332, 0xa, x1, 884, x2)
+
+inst_234:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x5555555a, 0x55555554, 0x6, x1, 888, x2)
+
+inst_235:
+// rs1_val==1431655764 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x55555550, 0x55555554, -0x4, x1, 892, x2)
+
+inst_236:
+// rs1_val==1431655764 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x55555553, 0x55555554, -0x1, x1, 896, x2)
+
+inst_237:
+// rs1_val==1431655764 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x5555555b, 0x55555554, 0x7, x1, 900, x2)
+
+inst_238:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x55555558, 0x55555554, 0x4, x1, 904, x2)
+
+inst_239:
+// rs1_val==1431655764 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x5555555f, 0x55555554, 0xb, x1, 908, x2)
+
+inst_240:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x55555554, 0x55555554, 0x0, x1, 912, x2)
+
+inst_241:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x55555559, 0x55555554, 0x5, x1, 916, x2)
+
+inst_242:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x55555556, 0x55555554, 0x2, x1, 920, x2)
+
+inst_243:
+// rs1_val==1431655764 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x5555555d, 0x55555554, 0x9, x1, 924, x2)
+
+inst_244:
+// rs1_val==1431655764 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x5555554f, 0x55555554, -0x5, x1, 928, x2)
+
+inst_245:
+// rs1_val==1431655764 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x55555552, 0x55555554, -0x2, x1, 932, x2)
+
+inst_246:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x55555557, 0x55555554, 0x3, x1, 936, x2)
+
+inst_247:
+// rs1_val==1431655764 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555554; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x5555555e, 0x55555554, 0xa, x1, 940, x2)
+
+inst_248:
+// rs1_val==2 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x8, 0x2, 0x6, x1, 944, x2)
+
+inst_249:
+// rs1_val==2 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xfffffffe, 0x2, -0x4, x1, 948, x2)
+
+inst_250:
+// rs1_val==2 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x9, 0x2, 0x7, x1, 952, x2)
+
+inst_251:
+// rs1_val==2 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x6, 0x2, 0x4, x1, 956, x2)
+
+inst_252:
+// rs1_val==2 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xd, 0x2, 0xb, x1, 960, x2)
+
+inst_253:
+// rs1_val==2 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x2, 0x2, 0x0, x1, 964, x2)
+
+inst_254:
+// rs1_val==2 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x7, 0x2, 0x5, x1, 968, x2)
+
+inst_255:
+// rs1_val==2 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x4, 0x2, 0x2, x1, 972, x2)
+
+inst_256:
+// rs1_val==2 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xb, 0x2, 0x9, x1, 976, x2)
+
+inst_257:
+// rs1_val==2 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xfffffffd, 0x2, -0x5, x1, 980, x2)
+
+inst_258:
+// rs1_val==2 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x0, 0x2, -0x2, x1, 984, x2)
+
+inst_259:
+// rs1_val==2 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x5, 0x2, 0x3, x1, 988, x2)
+
+inst_260:
+// rs1_val==2 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x2; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xc, 0x2, 0xa, x1, 992, x2)
+
+inst_261:
+// rs1_val==46340 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xb50a, 0xb504, 0x6, x1, 996, x2)
+
+inst_262:
+// rs1_val==46340 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xb500, 0xb504, -0x4, x1, 1000, x2)
+
+inst_263:
+// rs1_val==46340 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xb503, 0xb504, -0x1, x1, 1004, x2)
+
+inst_264:
+// rs1_val==46340 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xb50b, 0xb504, 0x7, x1, 1008, x2)
+
+inst_265:
+// rs1_val==46340 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xb508, 0xb504, 0x4, x1, 1012, x2)
+
+inst_266:
+// rs1_val==46340 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xb50f, 0xb504, 0xb, x1, 1016, x2)
+
+inst_267:
+// rs1_val==46340 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xb504, 0xb504, 0x0, x1, 1020, x2)
+
+inst_268:
+// rs1_val==46340 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xb509, 0xb504, 0x5, x1, 1024, x2)
+
+inst_269:
+// rs1_val==46340 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xb506, 0xb504, 0x2, x1, 1028, x2)
+
+inst_270:
+// rs1_val==46340 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xb50d, 0xb504, 0x9, x1, 1032, x2)
+
+inst_271:
+// rs1_val==46340 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xb4ff, 0xb504, -0x5, x1, 1036, x2)
+
+inst_272:
+// rs1_val==46340 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xb502, 0xb504, -0x2, x1, 1040, x2)
+
+inst_273:
+// rs1_val==46340 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xb507, 0xb504, 0x3, x1, 1044, x2)
+
+inst_274:
+// rs1_val==46340 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0xb504; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xb50e, 0xb504, 0xa, x1, 1048, x2)
+
+inst_275:
+// rs1_val==-46340 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xffff4b02, -0xb504, 0x6, x1, 1052, x2)
+
+inst_276:
+// rs1_val==-46340 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xffff4af8, -0xb504, -0x4, x1, 1056, x2)
+
+inst_277:
+// rs1_val==-46340 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xffff4afb, -0xb504, -0x1, x1, 1060, x2)
+
+inst_278:
+// rs1_val==-46340 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xffff4b03, -0xb504, 0x7, x1, 1064, x2)
+
+inst_279:
+// rs1_val==-46340 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xffff4b00, -0xb504, 0x4, x1, 1068, x2)
+
+inst_280:
+// rs1_val==-46340 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xffff4b07, -0xb504, 0xb, x1, 1072, x2)
+
+inst_281:
+// rs1_val==-46340 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xffff4afc, -0xb504, 0x0, x1, 1076, x2)
+
+inst_282:
+// rs1_val==-46340 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xffff4b01, -0xb504, 0x5, x1, 1080, x2)
+
+inst_283:
+// rs1_val==-46340 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xffff4afe, -0xb504, 0x2, x1, 1084, x2)
+
+inst_284:
+// rs1_val==-46340 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xffff4b05, -0xb504, 0x9, x1, 1088, x2)
+
+inst_285:
+// rs1_val==-46340 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xffff4af7, -0xb504, -0x5, x1, 1092, x2)
+
+inst_286:
+// rs1_val==-46340 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xffff4afa, -0xb504, -0x2, x1, 1096, x2)
+
+inst_287:
+// rs1_val==-46340 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xffff4aff, -0xb504, 0x3, x1, 1100, x2)
+
+inst_288:
+// rs1_val==-46340 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0xb504; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xffff4b06, -0xb504, 0xa, x1, 1104, x2)
+
+inst_289:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x6666666c, 0x66666666, 0x6, x1, 1108, x2)
+
+inst_290:
+// rs1_val==1717986918 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x66666662, 0x66666666, -0x4, x1, 1112, x2)
+
+inst_291:
+// rs1_val==1717986918 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x66666665, 0x66666666, -0x1, x1, 1116, x2)
+
+inst_292:
+// rs1_val==1717986918 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x6666666d, 0x66666666, 0x7, x1, 1120, x2)
+
+inst_293:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x6666666a, 0x66666666, 0x4, x1, 1124, x2)
+
+inst_294:
+// rs1_val==1717986918 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x66666671, 0x66666666, 0xb, x1, 1128, x2)
+
+inst_295:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x66666666, 0x66666666, 0x0, x1, 1132, x2)
+
+inst_296:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x6666666b, 0x66666666, 0x5, x1, 1136, x2)
+
+inst_297:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x66666668, 0x66666666, 0x2, x1, 1140, x2)
+
+inst_298:
+// rs1_val==1717986918 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x6666666f, 0x66666666, 0x9, x1, 1144, x2)
+
+inst_299:
+// rs1_val==1717986918 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x66666661, 0x66666666, -0x5, x1, 1148, x2)
+
+inst_300:
+// rs1_val==1717986918 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x66666664, 0x66666666, -0x2, x1, 1152, x2)
+
+inst_301:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x66666669, 0x66666666, 0x3, x1, 1156, x2)
+
+inst_302:
+// rs1_val==1717986918 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x66666666; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x66666670, 0x66666666, 0xa, x1, 1160, x2)
+
+inst_303:
+// rs1_val==858993459 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x33333339, 0x33333333, 0x6, x1, 1164, x2)
+
+inst_304:
+// rs1_val==858993459 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x3333332f, 0x33333333, -0x4, x1, 1168, x2)
+
+inst_305:
+// rs1_val==858993459 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x33333332, 0x33333333, -0x1, x1, 1172, x2)
+
+inst_306:
+// rs1_val==858993459 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x3333333a, 0x33333333, 0x7, x1, 1176, x2)
+
+inst_307:
+// rs1_val==858993459 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x33333337, 0x33333333, 0x4, x1, 1180, x2)
+
+inst_308:
+// rs1_val==858993459 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x3333333e, 0x33333333, 0xb, x1, 1184, x2)
+
+inst_309:
+// rs1_val==858993459 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x33333333, 0x33333333, 0x0, x1, 1188, x2)
+
+inst_310:
+// rs1_val==858993459 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x33333338, 0x33333333, 0x5, x1, 1192, x2)
+
+inst_311:
+// rs1_val==858993459 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x33333335, 0x33333333, 0x2, x1, 1196, x2)
+
+inst_312:
+// rs1_val==858993459 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x3333333c, 0x33333333, 0x9, x1, 1200, x2)
+
+inst_313:
+// rs1_val==3 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xd, 0x3, 0xa, x1, 1204, x2)
+
+inst_314:
+// rs1_val == -1431655766, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:-0x7
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa3, -0x55555556, -0x7, x1, 1208, x2)
+
+inst_315:
+// rs1_val == 1431655765, rs1_val==1431655765 and imm_val==9
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x9
+TEST_CI_OP( c.addi, x10, 0x5555555e, 0x55555555, 0x9, x1, 1212, x2)
+
+inst_316:
+// imm_val == 21, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x6; immval:0x15
+TEST_CI_OP( c.addi, x10, 0x1b, 0x6, 0x15, x1, 1216, x2)
+
+inst_317:
+// rs1_val==858993459 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x3333332e, 0x33333333, -0x5, x1, 1220, x2)
+
+inst_318:
+// rs1_val==858993459 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x33333331, 0x33333333, -0x2, x1, 1224, x2)
+
+inst_319:
+// rs1_val==858993459 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x33333336, 0x33333333, 0x3, x1, 1228, x2)
+
+inst_320:
+// rs1_val==858993459 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x33333333; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x3333333d, 0x33333333, 0xa, x1, 1232, x2)
+
+inst_321:
+// rs1_val==5 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xb, 0x5, 0x6, x1, 1236, x2)
+
+inst_322:
+// rs1_val==5 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x1, 0x5, -0x4, x1, 1240, x2)
+
+inst_323:
+// rs1_val==5 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x4, 0x5, -0x1, x1, 1244, x2)
+
+inst_324:
+// rs1_val==5 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xc, 0x5, 0x7, x1, 1248, x2)
+
+inst_325:
+// rs1_val==5 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x9, 0x5, 0x4, x1, 1252, x2)
+
+inst_326:
+// rs1_val==5 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x10, 0x5, 0xb, x1, 1256, x2)
+
+inst_327:
+// rs1_val==5 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x5, 0x5, 0x0, x1, 1260, x2)
+
+inst_328:
+// rs1_val==5 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xa, 0x5, 0x5, x1, 1264, x2)
+
+inst_329:
+// rs1_val==5 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x7, 0x5, 0x2, x1, 1268, x2)
+
+inst_330:
+// rs1_val==5 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xe, 0x5, 0x9, x1, 1272, x2)
+
+inst_331:
+// rs1_val==5 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x0, 0x5, -0x5, x1, 1276, x2)
+
+inst_332:
+// rs1_val==5 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x3, 0x5, -0x2, x1, 1280, x2)
+
+inst_333:
+// rs1_val==5 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x8, 0x5, 0x3, x1, 1284, x2)
+
+inst_334:
+// rs1_val==5 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x5; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xf, 0x5, 0xa, x1, 1288, x2)
+
+inst_335:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x6
+TEST_CI_OP( c.addi, x10, 0xaaaaaab0, -0x55555556, 0x6, x1, 1292, x2)
+
+inst_336:
+// rs1_val==-1431655766 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa6, -0x55555556, -0x4, x1, 1296, x2)
+
+inst_337:
+// rs1_val==-1431655766 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa9, -0x55555556, -0x1, x1, 1300, x2)
+
+inst_338:
+// rs1_val==-1431655766 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xaaaaaab1, -0x55555556, 0x7, x1, 1304, x2)
+
+inst_339:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x4
+TEST_CI_OP( c.addi, x10, 0xaaaaaaae, -0x55555556, 0x4, x1, 1308, x2)
+
+inst_340:
+// rs1_val==-1431655766 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xaaaaaab5, -0x55555556, 0xb, x1, 1312, x2)
+
+inst_341:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x0
+TEST_CI_OP( c.addi, x10, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1316, x2)
+
+inst_342:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x5
+TEST_CI_OP( c.addi, x10, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1320, x2)
+
+inst_343:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x2
+TEST_CI_OP( c.addi, x10, 0xaaaaaaac, -0x55555556, 0x2, x1, 1324, x2)
+
+inst_344:
+// rs1_val==-1431655766 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xaaaaaab3, -0x55555556, 0x9, x1, 1328, x2)
+
+inst_345:
+// rs1_val==-1431655766 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa5, -0x55555556, -0x5, x1, 1332, x2)
+
+inst_346:
+// rs1_val==-1431655766 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0xaaaaaaa8, -0x55555556, -0x2, x1, 1336, x2)
+
+inst_347:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0x3
+TEST_CI_OP( c.addi, x10, 0xaaaaaaad, -0x55555556, 0x3, x1, 1340, x2)
+
+inst_348:
+// rs1_val==-1431655766 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:-0x55555556; immval:0xa
+TEST_CI_OP( c.addi, x10, 0xaaaaaab4, -0x55555556, 0xa, x1, 1344, x2)
+
+inst_349:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x5555555b, 0x55555555, 0x6, x1, 1348, x2)
+
+inst_350:
+// rs1_val==1431655765 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0x55555551, 0x55555555, -0x4, x1, 1352, x2)
+
+inst_351:
+// rs1_val==1431655765 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x55555554, 0x55555555, -0x1, x1, 1356, x2)
+
+inst_352:
+// rs1_val==1431655765 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x7
+TEST_CI_OP( c.addi, x10, 0x5555555c, 0x55555555, 0x7, x1, 1360, x2)
+
+inst_353:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x55555559, 0x55555555, 0x4, x1, 1364, x2)
+
+inst_354:
+// rs1_val==1431655765 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0xb
+TEST_CI_OP( c.addi, x10, 0x55555560, 0x55555555, 0xb, x1, 1368, x2)
+
+inst_355:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x55555555, 0x55555555, 0x0, x1, 1372, x2)
+
+inst_356:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x5555555a, 0x55555555, 0x5, x1, 1376, x2)
+
+inst_357:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x55555557, 0x55555555, 0x2, x1, 1380, x2)
+
+inst_358:
+// rs1_val==1431655765 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0x55555550, 0x55555555, -0x5, x1, 1384, x2)
+
+inst_359:
+// rs1_val==1431655765 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x55555553, 0x55555555, -0x2, x1, 1388, x2)
+
+inst_360:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x55555558, 0x55555555, 0x3, x1, 1392, x2)
+
+inst_361:
+// rs1_val==1431655765 and imm_val==10, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x55555555; immval:0xa
+TEST_CI_OP( c.addi, x10, 0x5555555f, 0x55555555, 0xa, x1, 1396, x2)
+
+inst_362:
+// rs1_val==3 and imm_val==6, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x6
+TEST_CI_OP( c.addi, x10, 0x9, 0x3, 0x6, x1, 1400, x2)
+
+inst_363:
+// rs1_val==3 and imm_val==-4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:-0x4
+TEST_CI_OP( c.addi, x10, 0xffffffff, 0x3, -0x4, x1, 1404, x2)
+
+inst_364:
+// rs1_val==3 and imm_val==-1, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:-0x1
+TEST_CI_OP( c.addi, x10, 0x2, 0x3, -0x1, x1, 1408, x2)
+
+inst_365:
+// rs1_val==3 and imm_val==7, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x7
+TEST_CI_OP( c.addi, x10, 0xa, 0x3, 0x7, x1, 1412, x2)
+
+inst_366:
+// rs1_val==3 and imm_val==4, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x4
+TEST_CI_OP( c.addi, x10, 0x7, 0x3, 0x4, x1, 1416, x2)
+
+inst_367:
+// rs1_val==3 and imm_val==11, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0xb
+TEST_CI_OP( c.addi, x10, 0xe, 0x3, 0xb, x1, 1420, x2)
+
+inst_368:
+// rs1_val==3 and imm_val==0, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x0
+TEST_CI_OP( c.addi, x10, 0x3, 0x3, 0x0, x1, 1424, x2)
+
+inst_369:
+// rs1_val==3 and imm_val==5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x5
+TEST_CI_OP( c.addi, x10, 0x8, 0x3, 0x5, x1, 1428, x2)
+
+inst_370:
+// rs1_val==3 and imm_val==2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x2
+TEST_CI_OP( c.addi, x10, 0x5, 0x3, 0x2, x1, 1432, x2)
+
+inst_371:
+// rs1_val==3 and imm_val==9, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x9
+TEST_CI_OP( c.addi, x10, 0xc, 0x3, 0x9, x1, 1436, x2)
+
+inst_372:
+// rs1_val==3 and imm_val==-5, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:-0x5
+TEST_CI_OP( c.addi, x10, 0xfffffffe, 0x3, -0x5, x1, 1440, x2)
+
+inst_373:
+// rs1_val==3 and imm_val==-2, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:-0x2
+TEST_CI_OP( c.addi, x10, 0x1, 0x3, -0x2, x1, 1444, x2)
+
+inst_374:
+// rs1_val==3 and imm_val==3, 
+// opcode:c.addi; op1:x10; dest:x10 op1val:0x3; immval:0x3
+TEST_CI_OP( c.addi, x10, 0x6, 0x3, 0x3, x1, 1448, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x10_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_1:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 363*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi16sp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi16sp-01.S
new file mode 100644
index 000000000..886fd1476
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi16sp-01.S
@@ -0,0 +1,430 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.addi16sp instruction of the RISC-V C extension for the caddi16sp covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi16sp)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rd==x2, imm_val == -512, rs1_val == 4194304, rs1_val != imm_val, rs1_val > 0 and imm_val < 0
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:-0x200
+TEST_CI_OP( c.addi16sp, x2, 0x3ffe00, 0x400000, -0x200, x1, 0, x3)
+
+inst_1:
+// rs1_val == 2147483647, imm_val == 128, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x7fffffff; immval:0x80
+TEST_CI_OP( c.addi16sp, x2, 0x8000007f, 0x7fffffff, 0x80, x1, 4, x3)
+
+inst_2:
+// rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40000001; immval:0x60
+TEST_CI_OP( c.addi16sp, x2, 0xc000005f, -0x40000001, 0x60, x1, 8, x3)
+
+inst_3:
+// rs1_val == -536870913, rs1_val < 0 and imm_val < 0
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20000001; immval:-0x60
+TEST_CI_OP( c.addi16sp, x2, 0xdfffff9f, -0x20000001, -0x60, x1, 12, x3)
+
+inst_4:
+// rs1_val == -268435457, imm_val == -352
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10000001; immval:-0x160
+TEST_CI_OP( c.addi16sp, x2, 0xeffffe9f, -0x10000001, -0x160, x1, 16, x3)
+
+inst_5:
+// rs1_val == -134217729, imm_val == -80
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8000001; immval:-0x50
+TEST_CI_OP( c.addi16sp, x2, 0xf7ffffaf, -0x8000001, -0x50, x1, 20, x3)
+
+inst_6:
+// rs1_val == -67108865, imm_val == -144
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4000001; immval:-0x90
+TEST_CI_OP( c.addi16sp, x2, 0xfbffff6f, -0x4000001, -0x90, x1, 24, x3)
+
+inst_7:
+// rs1_val == -33554433, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2000001; immval:0xf0
+TEST_CI_OP( c.addi16sp, x2, 0xfe0000ef, -0x2000001, 0xf0, x1, 28, x3)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1000001; immval:-0x80
+TEST_CI_OP( c.addi16sp, x2, 0xfeffff7f, -0x1000001, -0x80, x1, 32, x3)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x800001; immval:-0x70
+TEST_CI_OP( c.addi16sp, x2, 0xff7fff8f, -0x800001, -0x70, x1, 36, x3)
+
+inst_10:
+// rs1_val == -4194305, imm_val == 64
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:0x40
+TEST_CI_OP( c.addi16sp, x2, 0xffc0003f, -0x400001, 0x40, x1, 40, x3)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x200001; immval:-0x160
+TEST_CI_OP( c.addi16sp, x2, 0xffdffe9f, -0x200001, -0x160, x1, 44, x3)
+
+inst_12:
+// rs1_val == -1048577, imm_val == 16
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x100001; immval:0x10
+TEST_CI_OP( c.addi16sp, x2, 0xfff0000f, -0x100001, 0x10, x1, 48, x3)
+
+inst_13:
+// rs1_val == -524289, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80001; immval:0x10
+TEST_CI_OP( c.addi16sp, x2, 0xfff8000f, -0x80001, 0x10, x1, 52, x3)
+
+inst_14:
+// rs1_val == -262145, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x40001; immval:-0x100
+TEST_CI_OP( c.addi16sp, x2, 0xfffbfeff, -0x40001, -0x100, x1, 56, x3)
+
+inst_15:
+// rs1_val == -131073, imm_val == 336
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x20001; immval:0x150
+TEST_CI_OP( c.addi16sp, x2, 0xfffe014f, -0x20001, 0x150, x1, 60, x3)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x10001; immval:-0x50
+TEST_CI_OP( c.addi16sp, x2, 0xfffeffaf, -0x10001, -0x50, x1, 64, x3)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x8001; immval:0x40
+TEST_CI_OP( c.addi16sp, x2, 0xffff803f, -0x8001, 0x40, x1, 68, x3)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x4001; immval:0x50
+TEST_CI_OP( c.addi16sp, x2, 0xffffc04f, -0x4001, 0x50, x1, 72, x3)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2001; immval:-0x40
+TEST_CI_OP( c.addi16sp, x2, 0xffffdfbf, -0x2001, -0x40, x1, 76, x3)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x1001; immval:0x80
+TEST_CI_OP( c.addi16sp, x2, 0xfffff07f, -0x1001, 0x80, x1, 80, x3)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x801; immval:0x80
+TEST_CI_OP( c.addi16sp, x2, 0xfffff87f, -0x801, 0x80, x1, 84, x3)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x401; immval:-0x10
+TEST_CI_OP( c.addi16sp, x2, 0xfffffbef, -0x401, -0x10, x1, 88, x3)
+
+inst_23:
+// rs1_val == -513, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x201; immval:0x150
+TEST_CI_OP( c.addi16sp, x2, 0xffffff4f, -0x201, 0x150, x1, 92, x3)
+
+inst_24:
+// rs1_val == -257, imm_val == -32
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x101; immval:-0x20
+TEST_CI_OP( c.addi16sp, x2, 0xfffffedf, -0x101, -0x20, x1, 96, x3)
+
+inst_25:
+// rs1_val == -129, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x81; immval:-0x20
+TEST_CI_OP( c.addi16sp, x2, 0xffffff5f, -0x81, -0x20, x1, 100, x3)
+
+inst_26:
+// rs1_val == -65, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x41; immval:0x90
+TEST_CI_OP( c.addi16sp, x2, 0x4f, -0x41, 0x90, x1, 104, x3)
+
+inst_27:
+// rs1_val == -33, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x21; immval:0x10
+TEST_CI_OP( c.addi16sp, x2, 0xffffffef, -0x21, 0x10, x1, 108, x3)
+
+inst_28:
+// rs1_val == -17, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x11; immval:-0x160
+TEST_CI_OP( c.addi16sp, x2, 0xfffffe8f, -0x11, -0x160, x1, 112, x3)
+
+inst_29:
+// rs1_val == -9, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x9; immval:-0x60
+TEST_CI_OP( c.addi16sp, x2, 0xffffff97, -0x9, -0x60, x1, 116, x3)
+
+inst_30:
+// rs1_val == -5, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x100
+TEST_CI_OP( c.addi16sp, x2, 0xfffffefb, -0x5, -0x100, x1, 120, x3)
+
+inst_31:
+// rs1_val == -3, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x3; immval:-0x90
+TEST_CI_OP( c.addi16sp, x2, 0xffffff6d, -0x3, -0x90, x1, 124, x3)
+
+inst_32:
+// rs1_val == -2, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x2; immval:0x70
+TEST_CI_OP( c.addi16sp, x2, 0x6e, -0x2, 0x70, x1, 128, x3)
+
+inst_33:
+// imm_val == 496, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400000; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x4001f0, 0x400000, 0x1f0, x1, 132, x3)
+
+inst_34:
+// imm_val == -272, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x5; immval:-0x110
+TEST_CI_OP( c.addi16sp, x2, 0xfffffeeb, -0x5, -0x110, x1, 136, x3)
+
+inst_35:
+// imm_val == -48, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x400001; immval:-0x30
+TEST_CI_OP( c.addi16sp, x2, 0xffbfffcf, -0x400001, -0x30, x1, 140, x3)
+
+inst_36:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x80000000; immval:-0xa0
+TEST_CI_OP( c.addi16sp, x2, 0x7fffff60, -0x80000000, -0xa0, x1, 144, x3)
+
+inst_37:
+// rs1_val == 1073741824, imm_val == 256
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000000; immval:0x100
+TEST_CI_OP( c.addi16sp, x2, 0x40000100, 0x40000000, 0x100, x1, 148, x3)
+
+inst_38:
+// rs1_val == 536870912, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000000; immval:-0x10
+TEST_CI_OP( c.addi16sp, x2, 0x1ffffff0, 0x20000000, -0x10, x1, 152, x3)
+
+inst_39:
+// rs1_val == 268435456, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000000; immval:0x30
+TEST_CI_OP( c.addi16sp, x2, 0x10000030, 0x10000000, 0x30, x1, 156, x3)
+
+inst_40:
+// rs1_val == 134217728, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000000; immval:-0xa0
+TEST_CI_OP( c.addi16sp, x2, 0x7ffff60, 0x8000000, -0xa0, x1, 160, x3)
+
+inst_41:
+// rs1_val == 64, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x80
+TEST_CI_OP( c.addi16sp, x2, 0xc0, 0x40, 0x80, x1, 164, x3)
+
+inst_42:
+// rs1_val == 32, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x210, 0x20, 0x1f0, x1, 168, x3)
+
+inst_43:
+// rs1_val == 16, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x200, 0x10, 0x1f0, x1, 172, x3)
+
+inst_44:
+// rs1_val == 8, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8; immval:0x70
+TEST_CI_OP( c.addi16sp, x2, 0x78, 0x8, 0x70, x1, 176, x3)
+
+inst_45:
+// rs1_val == 4, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4; immval:-0x110
+TEST_CI_OP( c.addi16sp, x2, 0xfffffef4, 0x4, -0x110, x1, 180, x3)
+
+inst_46:
+// rs1_val == 2, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2; immval:-0x50
+TEST_CI_OP( c.addi16sp, x2, 0xffffffb2, 0x2, -0x50, x1, 184, x3)
+
+inst_47:
+// rs1_val == 1, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1; immval:0x50
+TEST_CI_OP( c.addi16sp, x2, 0x51, 0x1, 0x50, x1, 188, x3)
+
+inst_48:
+// imm_val == 32, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x9; immval:0x20
+TEST_CI_OP( c.addi16sp, x2, 0x29, 0x9, 0x20, x1, 192, x3)
+
+inst_49:
+// rs1_val == -1431655766, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:-0x55555556; immval:0x30
+TEST_CI_OP( c.addi16sp, x2, 0xaaaaaada, -0x55555556, 0x30, x1, 196, x3)
+
+inst_50:
+// rs1_val == 1431655765, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x55555555; immval:0x60
+TEST_CI_OP( c.addi16sp, x2, 0x555555b5, 0x55555555, 0x60, x1, 200, x3)
+
+inst_51:
+// rs1_val == 0, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x0; immval:-0x100
+TEST_CI_OP( c.addi16sp, x2, 0xffffff00, 0x0, -0x100, x1, 204, x3)
+
+inst_52:
+// rs1_val == imm_val, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40; immval:0x40
+TEST_CI_OP( c.addi16sp, x2, 0x80, 0x40, 0x40, x1, 208, x3)
+
+inst_53:
+// rs1_val == 67108864, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000000; immval:-0x200
+TEST_CI_OP( c.addi16sp, x2, 0x3fffe00, 0x4000000, -0x200, x1, 212, x3)
+
+inst_54:
+// rs1_val == 33554432, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000000; immval:-0x200
+TEST_CI_OP( c.addi16sp, x2, 0x1fffe00, 0x2000000, -0x200, x1, 216, x3)
+
+inst_55:
+// rs1_val == 16777216, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000000; immval:-0x40
+TEST_CI_OP( c.addi16sp, x2, 0xffffc0, 0x1000000, -0x40, x1, 220, x3)
+
+inst_56:
+// rs1_val == 8388608, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800000; immval:0x10
+TEST_CI_OP( c.addi16sp, x2, 0x800010, 0x800000, 0x10, x1, 224, x3)
+
+inst_57:
+// rs1_val == 2097152, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200000; immval:0x20
+TEST_CI_OP( c.addi16sp, x2, 0x200020, 0x200000, 0x20, x1, 228, x3)
+
+inst_58:
+// rs1_val == 1048576, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100000; immval:0x90
+TEST_CI_OP( c.addi16sp, x2, 0x100090, 0x100000, 0x90, x1, 232, x3)
+
+inst_59:
+// rs1_val == 524288, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80000; immval:0x50
+TEST_CI_OP( c.addi16sp, x2, 0x80050, 0x80000, 0x50, x1, 236, x3)
+
+inst_60:
+// rs1_val == 262144, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x40000; immval:-0x160
+TEST_CI_OP( c.addi16sp, x2, 0x3fea0, 0x40000, -0x160, x1, 240, x3)
+
+inst_61:
+// rs1_val == 131072, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x20000; immval:-0xa0
+TEST_CI_OP( c.addi16sp, x2, 0x1ff60, 0x20000, -0xa0, x1, 244, x3)
+
+inst_62:
+// rs1_val == 65536, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x10000; immval:0x150
+TEST_CI_OP( c.addi16sp, x2, 0x10150, 0x10000, 0x150, x1, 248, x3)
+
+inst_63:
+// rs1_val == 32768, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x8000; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x81f0, 0x8000, 0x1f0, x1, 252, x3)
+
+inst_64:
+// rs1_val == 16384, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x4000; immval:0x40
+TEST_CI_OP( c.addi16sp, x2, 0x4040, 0x4000, 0x40, x1, 256, x3)
+
+inst_65:
+// rs1_val == 8192, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x2000; immval:0x80
+TEST_CI_OP( c.addi16sp, x2, 0x2080, 0x2000, 0x80, x1, 260, x3)
+
+inst_66:
+// rs1_val == 4096, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x1000; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x11f0, 0x1000, 0x1f0, x1, 264, x3)
+
+inst_67:
+// rs1_val == 2048, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x800; immval:0x100
+TEST_CI_OP( c.addi16sp, x2, 0x900, 0x800, 0x100, x1, 268, x3)
+
+inst_68:
+// rs1_val == 1024, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x400; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x5f0, 0x400, 0x1f0, x1, 272, x3)
+
+inst_69:
+// rs1_val == 512, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x200; immval:0x150
+TEST_CI_OP( c.addi16sp, x2, 0x350, 0x200, 0x150, x1, 276, x3)
+
+inst_70:
+// rs1_val == 256, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x100; immval:0x1f0
+TEST_CI_OP( c.addi16sp, x2, 0x2f0, 0x100, 0x1f0, x1, 280, x3)
+
+inst_71:
+// rs1_val == 128, 
+// opcode:c.addi16sp; op1:x2; dest:x2 op1val:0x80; immval:0x30
+TEST_CI_OP( c.addi16sp, x2, 0xb0, 0x80, 0x30, x1, 284, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 72*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S
new file mode 100644
index 000000000..9ecd98f0f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/caddi4spn-01.S
@@ -0,0 +1,165 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.addi4spn instruction of the RISC-V C extension for the caddi4spn covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",caddi4spn)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rd==x10, imm_val == 1020, imm_val > 0
+// opcode:c.addi4spn; dest:x10; immval:0x3fc
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3fc, 0x3fc, x1, 0, x2)
+
+inst_1:
+// rd==x13, imm_val == 508, 
+// opcode:c.addi4spn; dest:x13; immval:0x1fc
+TEST_CADDI4SPN_OP( c.addi4spn, x13, 0x1fc, 0x1fc, x1, 4, x2)
+
+inst_2:
+// rd==x9, imm_val == 764, 
+// opcode:c.addi4spn; dest:x9; immval:0x2fc
+TEST_CADDI4SPN_OP( c.addi4spn, x9, 0x2fc, 0x2fc, x1, 8, x2)
+
+inst_3:
+// rd==x8, imm_val == 892, 
+// opcode:c.addi4spn; dest:x8; immval:0x37c
+TEST_CADDI4SPN_OP( c.addi4spn, x8, 0x37c, 0x37c, x1, 12, x2)
+
+inst_4:
+// rd==x14, imm_val == 956, 
+// opcode:c.addi4spn; dest:x14; immval:0x3bc
+TEST_CADDI4SPN_OP( c.addi4spn, x14, 0x3bc, 0x3bc, x1, 16, x2)
+
+inst_5:
+// rd==x11, imm_val == 988, 
+// opcode:c.addi4spn; dest:x11; immval:0x3dc
+TEST_CADDI4SPN_OP( c.addi4spn, x11, 0x3dc, 0x3dc, x1, 20, x2)
+
+inst_6:
+// rd==x15, imm_val == 1004, 
+// opcode:c.addi4spn; dest:x15; immval:0x3ec
+TEST_CADDI4SPN_OP( c.addi4spn, x15, 0x3ec, 0x3ec, x1, 24, x2)
+
+inst_7:
+// rd==x12, imm_val == 1012, 
+// opcode:c.addi4spn; dest:x12; immval:0x3f4
+TEST_CADDI4SPN_OP( c.addi4spn, x12, 0x3f4, 0x3f4, x1, 28, x2)
+
+inst_8:
+// imm_val == 1016, 
+// opcode:c.addi4spn; dest:x10; immval:0x3f8
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x3f8, 0x3f8, x1, 32, x2)
+
+inst_9:
+// imm_val == 512, 
+// opcode:c.addi4spn; dest:x10; immval:0x200
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x200, 0x200, x1, 36, x2)
+
+inst_10:
+// imm_val == 256, 
+// opcode:c.addi4spn; dest:x10; immval:0x100
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x100, 0x100, x1, 40, x2)
+
+inst_11:
+// imm_val == 128, 
+// opcode:c.addi4spn; dest:x10; immval:0x80
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x80, 0x80, x1, 44, x2)
+
+inst_12:
+// imm_val == 4, 
+// opcode:c.addi4spn; dest:x10; immval:0x4
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x4, 0x4, x1, 48, x2)
+
+inst_13:
+// imm_val == 680, 
+// opcode:c.addi4spn; dest:x10; immval:0x2a8
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x2a8, 0x2a8, x1, 52, x2)
+
+inst_14:
+// imm_val == 340, 
+// opcode:c.addi4spn; dest:x10; immval:0x154
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x154, 0x154, x1, 56, x2)
+
+inst_15:
+// imm_val == 64, 
+// opcode:c.addi4spn; dest:x10; immval:0x40
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x40, 0x40, x1, 60, x2)
+
+inst_16:
+// imm_val == 32, 
+// opcode:c.addi4spn; dest:x10; immval:0x20
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x20, 0x20, x1, 64, x2)
+
+inst_17:
+// imm_val == 16, 
+// opcode:c.addi4spn; dest:x10; immval:0x10
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x10, 0x10, x1, 68, x2)
+
+inst_18:
+// imm_val == 8, 
+// opcode:c.addi4spn; dest:x10; immval:0x8
+TEST_CADDI4SPN_OP( c.addi4spn, x10, 0x8, 0x8, x1, 72, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cand-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cand-01.S
new file mode 100644
index 000000000..06dbde15d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cand-01.S
@@ -0,0 +1,3005 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.and instruction of the RISC-V C extension for the cand covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cand)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x14, rs2==x10, rs1_val == (-2**(xlen-1)), rs2_val < 0, rs1_val == -2147483648, rs2_val == -8193
+// opcode: c.and; op1:x14; op2:x10; op1val:-0x80000000; op2val:-0x2001
+TEST_CR_OP( c.and, x14, x10, 0x80000000, -0x80000000, -0x2001, x1, 0, x2)
+
+inst_1:
+// rs1 == rs2, rs1==x11, rs2==x11, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.and; op1:x11; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.and, x11, x11, 0xb503, 0xb503, 0xb503, x1, 4, x2)
+
+inst_2:
+// rs1==x12, rs2==x9, rs2_val == -1073741825, 
+// opcode: c.and; op1:x12; op2:x9; op1val:-0xb504; op2val:-0x40000001
+TEST_CR_OP( c.and, x12, x9, 0xbfff4afc, -0xb504, -0x40000001, x1, 8, x2)
+
+inst_3:
+// rs1==x13, rs2==x12, rs2_val == -536870913, 
+// opcode: c.and; op1:x13; op2:x12; op1val:0x3; op2val:-0x20000001
+TEST_CR_OP( c.and, x13, x12, 0x3, 0x3, -0x20000001, x1, 12, x2)
+
+inst_4:
+// rs1==x8, rs2==x14, rs2_val == -268435457, rs1_val == 512
+// opcode: c.and; op1:x8; op2:x14; op1val:0x200; op2val:-0x10000001
+TEST_CR_OP( c.and, x8, x14, 0x200, 0x200, -0x10000001, x1, 16, x2)
+
+inst_5:
+// rs1==x10, rs2==x13, rs2_val == -134217729, rs1_val == 1431655765
+// opcode: c.and; op1:x10; op2:x13; op1val:0x55555555; op2val:-0x8000001
+TEST_CR_OP( c.and, x10, x13, 0x55555555, 0x55555555, -0x8000001, x1, 20, x2)
+
+inst_6:
+// rs1==x15, rs2==x8, rs2_val == -67108865, rs1_val == 4096
+// opcode: c.and; op1:x15; op2:x8; op1val:0x1000; op2val:-0x4000001
+TEST_CR_OP( c.and, x15, x8, 0x1000, 0x1000, -0x4000001, x1, 24, x2)
+
+inst_7:
+// rs1==x9, rs2==x15, rs2_val == -33554433, rs1_val == -32769
+// opcode: c.and; op1:x9; op2:x15; op1val:-0x8001; op2val:-0x2000001
+TEST_CR_OP( c.and, x9, x15, 0xfdff7fff, -0x8001, -0x2000001, x1, 28, x2)
+
+inst_8:
+// rs2_val == -16777217, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x7; op2val:-0x1000001
+TEST_CR_OP( c.and, x10, x11, 0xfefffff9, -0x7, -0x1000001, x1, 32, x2)
+
+inst_9:
+// rs2_val == -8388609, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x6; op2val:-0x800001
+TEST_CR_OP( c.and, x10, x11, 0xff7ffffa, -0x6, -0x800001, x1, 36, x2)
+
+inst_10:
+// rs2_val == -4194305, rs1_val == 1073741824
+// opcode: c.and; op1:x10; op2:x11; op1val:0x40000000; op2val:-0x400001
+TEST_CR_OP( c.and, x10, x11, 0x40000000, 0x40000000, -0x400001, x1, 40, x2)
+
+inst_11:
+// rs2_val == -2097153, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:-0x200001
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x6, -0x200001, x1, 44, x2)
+
+inst_12:
+// rs2_val == -1048577, rs1_val == 32
+// opcode: c.and; op1:x10; op2:x11; op1val:0x20; op2val:-0x100001
+TEST_CR_OP( c.and, x10, x11, 0x20, 0x20, -0x100001, x1, 48, x2)
+
+inst_13:
+// rs2_val == -524289, rs1_val == 536870912
+// opcode: c.and; op1:x10; op2:x11; op1val:0x20000000; op2val:-0x80001
+TEST_CR_OP( c.and, x10, x11, 0x20000000, 0x20000000, -0x80001, x1, 52, x2)
+
+inst_14:
+// rs2_val == -262145, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x20; op2val:-0x40001
+TEST_CR_OP( c.and, x10, x11, 0x20, 0x20, -0x40001, x1, 56, x2)
+
+inst_15:
+// rs2_val == -131073, rs1_val == -33
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x21; op2val:-0x20001
+TEST_CR_OP( c.and, x10, x11, 0xfffdffdf, -0x21, -0x20001, x1, 60, x2)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x10001
+TEST_CR_OP( c.and, x10, x11, 0x66666665, 0x66666665, -0x10001, x1, 64, x2)
+
+inst_17:
+// rs2_val == -32769, rs1_val == 0
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:-0x8001
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, -0x8001, x1, 68, x2)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x8; op2val:-0x4001
+TEST_CR_OP( c.and, x10, x11, 0xffffbff8, -0x8, -0x4001, x1, 72, x2)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0x1001
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, -0x1001, x1, 76, x2)
+
+inst_20:
+// rs2_val == -2049, rs1_val == -3
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x3; op2val:-0x801
+TEST_CR_OP( c.and, x10, x11, 0xfffff7fd, -0x3, -0x801, x1, 80, x2)
+
+inst_21:
+// rs2_val == -1025, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0x401
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, -0x401, x1, 84, x2)
+
+inst_22:
+// rs2_val == -513, rs1_val == 2097152
+// opcode: c.and; op1:x10; op2:x11; op1val:0x200000; op2val:-0x201
+TEST_CR_OP( c.and, x10, x11, 0x200000, 0x200000, -0x201, x1, 88, x2)
+
+inst_23:
+// rs2_val == -257, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x101
+TEST_CR_OP( c.and, x10, x11, 0x55555456, 0x55555556, -0x101, x1, 92, x2)
+
+inst_24:
+// rs2_val == -129, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x4; op2val:-0x81
+TEST_CR_OP( c.and, x10, x11, 0xffffff7c, -0x4, -0x81, x1, 96, x2)
+
+inst_25:
+// rs2_val == -65, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x41
+TEST_CR_OP( c.and, x10, x11, 0xffff4abd, -0xb503, -0x41, x1, 100, x2)
+
+inst_26:
+// rs2_val == -33, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x20000000; op2val:-0x21
+TEST_CR_OP( c.and, x10, x11, 0x20000000, 0x20000000, -0x21, x1, 104, x2)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x11
+TEST_CR_OP( c.and, x10, x11, 0x55555545, 0x55555555, -0x11, x1, 108, x2)
+
+inst_28:
+// rs2_val == -9, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x9
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaa3, -0x55555555, -0x9, x1, 112, x2)
+
+inst_29:
+// rs2_val == -5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x80000000; op2val:-0x5
+TEST_CR_OP( c.and, x10, x11, 0x80000000, -0x80000000, -0x5, x1, 116, x2)
+
+inst_30:
+// rs2_val == -3, rs1_val == -536870913
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x3
+TEST_CR_OP( c.and, x10, x11, 0xdffffffd, -0x20000001, -0x3, x1, 120, x2)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x2
+TEST_CR_OP( c.and, x10, x11, 0x33333334, 0x33333334, -0x2, x1, 124, x2)
+
+inst_32:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs2_val == 2048
+// opcode: c.and; op1:x10; op2:x11; op1val:0x7fffffff; op2val:0x800
+TEST_CR_OP( c.and, x10, x11, 0x800, 0x7fffffff, 0x800, x1, 128, x2)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 1431655765
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x40000001; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x15555555, -0x40000001, 0x55555555, x1, 132, x2)
+
+inst_34:
+// rs1_val == -268435457, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x10000001; op2val:0x3fffffff
+TEST_CR_OP( c.and, x10, x11, 0x2fffffff, -0x10000001, 0x3fffffff, x1, 136, x2)
+
+inst_35:
+// rs1_val == -134217729, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x8000001; op2val:-0x10001
+TEST_CR_OP( c.and, x10, x11, 0xf7feffff, -0x8000001, -0x10001, x1, 140, x2)
+
+inst_36:
+// rs1_val == -67108865, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x4000001; op2val:0x9
+TEST_CR_OP( c.and, x10, x11, 0x9, -0x4000001, 0x9, x1, 144, x2)
+
+inst_37:
+// rs1_val == -33554433, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x2000001; op2val:-0x20000001
+TEST_CR_OP( c.and, x10, x11, 0xddffffff, -0x2000001, -0x20000001, x1, 148, x2)
+
+inst_38:
+// rs1_val == -16777217, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x6
+TEST_CR_OP( c.and, x10, x11, 0xfefffffa, -0x1000001, -0x6, x1, 152, x2)
+
+inst_39:
+// rs1_val == -8388609, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x800001; op2val:-0x40000000
+TEST_CR_OP( c.and, x10, x11, 0xc0000000, -0x800001, -0x40000000, x1, 156, x2)
+
+inst_40:
+// rs1_val == -4194305, rs2_val == 32768
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x400001; op2val:0x8000
+TEST_CR_OP( c.and, x10, x11, 0x8000, -0x400001, 0x8000, x1, 160, x2)
+
+inst_41:
+// rs1_val == -2097153, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x200001; op2val:-0x8001
+TEST_CR_OP( c.and, x10, x11, 0xffdf7fff, -0x200001, -0x8001, x1, 164, x2)
+
+inst_42:
+// rs1_val == -1048577, rs2_val == 2097152
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x100001; op2val:0x200000
+TEST_CR_OP( c.and, x10, x11, 0x200000, -0x100001, 0x200000, x1, 168, x2)
+
+inst_43:
+// rs1_val == -524289, rs2_val == 256
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x80001; op2val:0x100
+TEST_CR_OP( c.and, x10, x11, 0x100, -0x80001, 0x100, x1, 172, x2)
+
+inst_44:
+// rs1_val == -262145, rs2_val == 0
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x40001; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x40001, 0x0, x1, 176, x2)
+
+inst_45:
+// rs1_val == -131073, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x20001; op2val:-0x4
+TEST_CR_OP( c.and, x10, x11, 0xfffdfffc, -0x20001, -0x4, x1, 180, x2)
+
+inst_46:
+// rs1_val == -65537, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x10001; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, -0x10001, 0x6, x1, 184, x2)
+
+inst_47:
+// rs1_val == -16385, rs2_val == 131072
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x4001; op2val:0x20000
+TEST_CR_OP( c.and, x10, x11, 0x20000, -0x4001, 0x20000, x1, 188, x2)
+
+inst_48:
+// rs1_val == -8193, rs2_val == 1073741824
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x2001; op2val:0x40000000
+TEST_CR_OP( c.and, x10, x11, 0x40000000, -0x2001, 0x40000000, x1, 192, x2)
+
+inst_49:
+// rs1_val == -4097, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x1001; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55554554, -0x1001, 0x55555554, x1, 196, x2)
+
+inst_50:
+// rs1_val == -2049, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x801; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0xffff42fd, -0x801, -0xb503, x1, 200, x2)
+
+inst_51:
+// rs1_val == -1025, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x401; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55555156, -0x401, 0x55555556, x1, 204, x2)
+
+inst_52:
+// rs1_val == -513, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x201; op2val:-0x81
+TEST_CR_OP( c.and, x10, x11, 0xfffffd7f, -0x201, -0x81, x1, 208, x2)
+
+inst_53:
+// rs1_val == -257, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x101; op2val:-0x3
+TEST_CR_OP( c.and, x10, x11, 0xfffffefd, -0x101, -0x3, x1, 212, x2)
+
+inst_54:
+// rs1_val == -129, rs2_val == 4
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x81; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, -0x81, 0x4, x1, 216, x2)
+
+inst_55:
+// rs1_val == -65, rs2_val == 512
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x41; op2val:0x200
+TEST_CR_OP( c.and, x10, x11, 0x200, -0x41, 0x200, x1, 220, x2)
+
+inst_56:
+// rs1_val == -17, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x11; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, -0x11, 0x6, x1, 224, x2)
+
+inst_57:
+// rs1_val == -9, rs2_val == 1048576
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x9; op2val:0x100000
+TEST_CR_OP( c.and, x10, x11, 0x100000, -0x9, 0x100000, x1, 228, x2)
+
+inst_58:
+// rs1_val == -5, rs2_val == -1431655766
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x5; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaaa, -0x5, -0x55555556, x1, 232, x2)
+
+inst_59:
+// rs1_val == -2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x2; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x2, 0x3, x1, 236, x2)
+
+inst_60:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x4; op2val:-0x80000000
+TEST_CR_OP( c.and, x10, x11, 0x80000000, -0x4, -0x80000000, x1, 240, x2)
+
+inst_61:
+// rs2_val == 536870912, rs1_val == 33554432
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2000000; op2val:0x20000000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2000000, 0x20000000, x1, 244, x2)
+
+inst_62:
+// rs2_val == 268435456, rs1_val == 8
+// opcode: c.and; op1:x10; op2:x11; op1val:0x8; op2val:0x10000000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x8, 0x10000000, x1, 248, x2)
+
+inst_63:
+// rs2_val == 134217728, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x401; op2val:0x8000000
+TEST_CR_OP( c.and, x10, x11, 0x8000000, -0x401, 0x8000000, x1, 252, x2)
+
+inst_64:
+// rs2_val == 67108864, rs1_val == 64
+// opcode: c.and; op1:x10; op2:x11; op1val:0x40; op2val:0x4000000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x40, 0x4000000, x1, 256, x2)
+
+inst_65:
+// rs2_val == 33554432, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x200000; op2val:0x2000000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x200000, 0x2000000, x1, 260, x2)
+
+inst_66:
+// rs2_val == 16777216, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x8; op2val:0x1000000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x8, 0x1000000, x1, 264, x2)
+
+inst_67:
+// rs2_val == 8388608, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x800000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555555, 0x800000, x1, 268, x2)
+
+inst_68:
+// rs2_val == 4194304, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x80001; op2val:0x400000
+TEST_CR_OP( c.and, x10, x11, 0x400000, -0x80001, 0x400000, x1, 272, x2)
+
+inst_69:
+// rs2_val == 524288, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x80000
+TEST_CR_OP( c.and, x10, x11, 0x80000, -0x55555555, 0x80000, x1, 276, x2)
+
+inst_70:
+// rs2_val == 262144, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x40000
+TEST_CR_OP( c.and, x10, x11, 0x40000, 0x55555555, 0x40000, x1, 280, x2)
+
+inst_71:
+// rs2_val == 65536, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x10000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0x10000, x1, 284, x2)
+
+inst_72:
+// rs2_val == 16384, rs1_val == 8388608
+// opcode: c.and; op1:x10; op2:x11; op1val:0x800000; op2val:0x4000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x800000, 0x4000, x1, 288, x2)
+
+inst_73:
+// rs2_val == 8192, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3fffffff; op2val:0x2000
+TEST_CR_OP( c.and, x10, x11, 0x2000, 0x3fffffff, 0x2000, x1, 292, x2)
+
+inst_74:
+// rs2_val == 4096, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x1000; op2val:0x1000
+TEST_CR_OP( c.and, x10, x11, 0x1000, 0x1000, 0x1000, x1, 296, x2)
+
+inst_75:
+// rs2_val == 1024, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x100001; op2val:0x400
+TEST_CR_OP( c.and, x10, x11, 0x400, -0x100001, 0x400, x1, 300, x2)
+
+inst_76:
+// rs2_val == 128, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x2; op2val:0x80
+TEST_CR_OP( c.and, x10, x11, 0x80, -0x2, 0x80, x1, 304, x2)
+
+inst_77:
+// rs2_val == 64, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x9; op2val:0x40
+TEST_CR_OP( c.and, x10, x11, 0x40, -0x9, 0x40, x1, 308, x2)
+
+inst_78:
+// rs2_val == 32, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x20
+TEST_CR_OP( c.and, x10, x11, 0x20, 0x33333334, 0x20, x1, 312, x2)
+
+inst_79:
+// rs2_val == 16, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x4001; op2val:0x10
+TEST_CR_OP( c.and, x10, x11, 0x10, -0x4001, 0x10, x1, 316, x2)
+
+inst_80:
+// rs2_val == 8, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x8
+TEST_CR_OP( c.and, x10, x11, 0x8, -0xb503, 0x8, x1, 320, x2)
+
+inst_81:
+// rs2_val == 2, rs1_val==1717986917 and rs2_val==2
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x66666665, 0x2, x1, 324, x2)
+
+inst_82:
+// rs2_val == 1, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x1
+TEST_CR_OP( c.and, x10, x11, 0x1, 0xb505, 0x1, x1, 328, x2)
+
+inst_83:
+// rs1_val == 268435456, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x10000000; op2val:0x3fffffff
+TEST_CR_OP( c.and, x10, x11, 0x10000000, 0x10000000, 0x3fffffff, x1, 332, x2)
+
+inst_84:
+// rs1_val == 134217728, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x8000000; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x8000000, 0x3, x1, 336, x2)
+
+inst_85:
+// rs1_val == 67108864, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4000000; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x4000000, 0x4000000, 0x55555555, x1, 340, x2)
+
+inst_86:
+// rs1_val == 16777216, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x1000000; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x1000000, 0x1000000, 0x33333332, x1, 344, x2)
+
+inst_87:
+// rs1_val == 4194304, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x400000; op2val:0x20000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x400000, 0x20000, x1, 348, x2)
+
+inst_88:
+// rs1_val == 1048576, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x100000; op2val:0x7fffffff
+TEST_CR_OP( c.and, x10, x11, 0x100000, 0x100000, 0x7fffffff, x1, 352, x2)
+
+inst_89:
+// rs1_val == 524288, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x80000; op2val:0x20
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x80000, 0x20, x1, 356, x2)
+
+inst_90:
+// rs1_val == 262144, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x40000; op2val:-0x8
+TEST_CR_OP( c.and, x10, x11, 0x40000, 0x40000, -0x8, x1, 360, x2)
+
+inst_91:
+// rs1_val == 131072, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x20000; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x20000, 0x20000, -0x55555556, x1, 364, x2)
+
+inst_92:
+// rs1_val == 65536, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x10000; op2val:-0x401
+TEST_CR_OP( c.and, x10, x11, 0x10000, 0x10000, -0x401, x1, 368, x2)
+
+inst_93:
+// rs1_val == 32768, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x8000; op2val:0x10
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x8000, 0x10, x1, 372, x2)
+
+inst_94:
+// rs1_val == 16384, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4000; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4000, -0x55555556, x1, 376, x2)
+
+inst_95:
+// rs1_val == 8192, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2000; op2val:-0x21
+TEST_CR_OP( c.and, x10, x11, 0x2000, 0x2000, -0x21, x1, 380, x2)
+
+inst_96:
+// rs1_val == 2048, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x800; op2val:0x1
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x800, 0x1, x1, 384, x2)
+
+inst_97:
+// rs1_val == 1024, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x400; op2val:-0x400001
+TEST_CR_OP( c.and, x10, x11, 0x400, 0x400, -0x400001, x1, 388, x2)
+
+inst_98:
+// rs1_val == 256, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x100; op2val:-0x10000001
+TEST_CR_OP( c.and, x10, x11, 0x100, 0x100, -0x10000001, x1, 392, x2)
+
+inst_99:
+// rs1_val == 128, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x80; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x80, 0x80, -0x55555556, x1, 396, x2)
+
+inst_100:
+// rs1_val == 16, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x10; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x10, 0x66666667, x1, 400, x2)
+
+inst_101:
+// rs1_val == 4, rs1_val==4 and rs2_val==1431655766
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x55555556, x1, 404, x2)
+
+inst_102:
+// rs1_val == 2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x20000
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x20000, x1, 408, x2)
+
+inst_103:
+// rs1_val == 1, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x1; op2val:0x10
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x1, 0x10, x1, 412, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0xb505, 0xb505, 0xb505, x1, 416, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x5, 0xb505, -0xb503, x1, 420, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x2405, 0xb505, 0x66666667, x1, 424, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x3104, 0xb505, 0x33333334, x1, 428, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb505, 0x6, x1, 432, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xa001, 0xb505, -0x55555555, x1, 436, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0xb505, 0x55555556, x1, 440, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb505, 0x4, x1, 444, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0xb501, 0xb505, 0xb503, x1, 448, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb505, 0x0, x1, 452, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x2405, 0xb505, 0x66666665, x1, 456, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0xb505, 0x33333332, x1, 460, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0xb505, 0x55555554, x1, 464, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb505, 0x2, x1, 468, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0xb504, 0xb505, 0xb504, x1, 472, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb505, -0xb504, x1, 476, x2)
+
+inst_120:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0xb505, 0x66666666, x1, 480, x2)
+
+inst_121:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x3101, 0xb505, 0x33333333, x1, 484, x2)
+
+inst_122:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, 0xb505, 0x5, x1, 488, x2)
+
+inst_123:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xa000, 0xb505, -0x55555556, x1, 492, x2)
+
+inst_124:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1505, 0xb505, 0x55555555, x1, 496, x2)
+
+inst_125:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb505; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x1, 0xb505, 0x3, x1, 500, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x5, -0xb503, 0xb505, x1, 504, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0xffff4afd, -0xb503, -0xb503, x1, 508, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x66664265, -0xb503, 0x66666667, x1, 512, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x33330234, -0xb503, 0x33333334, x1, 516, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb503, 0x6, x1, 520, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa9, -0xb503, -0x55555555, x1, 524, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55554054, -0xb503, 0x55555556, x1, 528, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb503, 0x4, x1, 532, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1, -0xb503, 0xb503, x1, 536, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb503, 0x0, x1, 540, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x66664265, -0xb503, 0x66666665, x1, 544, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x33330230, -0xb503, 0x33333332, x1, 548, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55554054, -0xb503, 0x55555554, x1, 552, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb503, 0x2, x1, 556, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb503, 0xb504, x1, 560, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0xffff4afc, -0xb503, -0xb504, x1, 564, x2)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x66664264, -0xb503, 0x66666666, x1, 568, x2)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x33330231, -0xb503, 0x33333333, x1, 572, x2)
+
+inst_144:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, -0xb503, 0x5, x1, 576, x2)
+
+inst_145:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0xb503, -0x55555556, x1, 580, x2)
+
+inst_146:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x55554055, -0xb503, 0x55555555, x1, 584, x2)
+
+inst_147:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb503; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x1, -0xb503, 0x3, x1, 588, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x2405, 0x66666667, 0xb505, x1, 592, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x66664265, 0x66666667, -0xb503, x1, 596, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x66666667, 0x66666667, 0x66666667, x1, 600, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x66666667, 0x33333334, x1, 604, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x66666667, 0x6, x1, 608, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222223, 0x66666667, -0x55555555, x1, 612, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x44444446, 0x66666667, 0x55555556, x1, 616, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x66666667, 0x4, x1, 620, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x2403, 0x66666667, 0xb503, x1, 624, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x66666667, 0x0, x1, 628, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x66666665, 0x66666667, 0x66666665, x1, 632, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666667, 0x33333332, x1, 636, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x66666667, 0x55555554, x1, 640, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x66666667, 0x2, x1, 644, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0x66666667, 0xb504, x1, 648, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x66664264, 0x66666667, -0xb504, x1, 652, x2)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x66666666, 0x66666667, 0x66666666, x1, 656, x2)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x22222223, 0x66666667, 0x33333333, x1, 660, x2)
+
+inst_166:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x66666667, 0x5, x1, 664, x2)
+
+inst_167:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666667, -0x55555556, x1, 668, x2)
+
+inst_168:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x44444445, 0x66666667, 0x55555555, x1, 672, x2)
+
+inst_169:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666667; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x66666667, 0x3, x1, 676, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x3104, 0x33333334, 0xb505, x1, 680, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x33330234, 0x33333334, -0xb503, x1, 684, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x33333334, 0x66666667, x1, 688, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x33333334, 0x33333334, 0x33333334, x1, 692, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x33333334, 0x6, x1, 696, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222220, 0x33333334, -0x55555555, x1, 700, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x33333334, 0x55555556, x1, 704, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x33333334, 0x4, x1, 708, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0x33333334, 0xb503, x1, 712, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333334, 0x0, x1, 716, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x33333334, 0x66666665, x1, 720, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x33333330, 0x33333334, 0x33333332, x1, 724, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x33333334, 0x55555554, x1, 728, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333334, 0x2, x1, 732, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x3104, 0x33333334, 0xb504, x1, 736, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x33330234, 0x33333334, -0xb504, x1, 740, x2)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x33333334, 0x66666666, x1, 744, x2)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x33333330, 0x33333334, 0x33333333, x1, 748, x2)
+
+inst_188:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x33333334, 0x5, x1, 752, x2)
+
+inst_189:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222220, 0x33333334, -0x55555556, x1, 756, x2)
+
+inst_190:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x33333334, 0x55555555, x1, 760, x2)
+
+inst_191:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333334; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333334, 0x3, x1, 764, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0xb505, x1, 768, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, -0xb503, x1, 772, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x6, 0x66666667, x1, 776, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x33333334, x1, 780, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x6, 0x6, x1, 784, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, -0x55555555, x1, 788, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x6, 0x55555556, x1, 792, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x4, x1, 796, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, 0xb503, x1, 800, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x6, 0x0, x1, 804, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x66666665, x1, 808, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, 0x33333332, x1, 812, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x55555554, x1, 816, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, 0x2, x1, 820, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0xb504, x1, 824, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, -0xb504, x1, 828, x2)
+
+inst_208:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x6, 0x66666666, x1, 832, x2)
+
+inst_209:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, 0x33333333, x1, 836, x2)
+
+inst_210:
+// rs1_val==6 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x5, x1, 840, x2)
+
+inst_211:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, -0x55555556, x1, 844, x2)
+
+inst_212:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x6, 0x55555555, x1, 848, x2)
+
+inst_213:
+// rs1_val==6 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x6; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x6, 0x3, x1, 852, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0xa001, -0x55555555, 0xb505, x1, 856, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa9, -0x55555555, -0xb503, x1, 860, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x22222223, -0x55555555, 0x66666667, x1, 864, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x22222220, -0x55555555, 0x33333334, x1, 868, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555555, 0x6, x1, 872, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555555, x1, 876, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555555, 0x55555556, x1, 880, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555555, 0x4, x1, 884, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0xa003, -0x55555555, 0xb503, x1, 888, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555555, 0x0, x1, 892, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x22222221, -0x55555555, 0x66666665, x1, 896, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555555, 0x33333332, x1, 900, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555555, 0x55555554, x1, 904, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555555, 0x2, x1, 908, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0xa000, -0x55555555, 0xb504, x1, 912, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0x55555555, -0xb504, x1, 916, x2)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555555, 0x66666666, x1, 920, x2)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x22222223, -0x55555555, 0x33333333, x1, 924, x2)
+
+inst_232:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x1, -0x55555555, 0x5, x1, 928, x2)
+
+inst_233:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaaa, -0x55555555, -0x55555556, x1, 932, x2)
+
+inst_234:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1, -0x55555555, 0x55555555, x1, 936, x2)
+
+inst_235:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x3, -0x55555555, 0x3, x1, 940, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0x55555556, 0xb505, x1, 944, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x55554054, 0x55555556, -0xb503, x1, 948, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x44444446, 0x55555556, 0x66666667, x1, 952, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x55555556, 0x33333334, x1, 956, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x55555556, 0x6, x1, 960, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x55555556, -0x55555555, x1, 964, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55555556, 0x55555556, 0x55555556, x1, 968, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555556, 0x4, x1, 972, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1502, 0x55555556, 0xb503, x1, 976, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555556, 0x0, x1, 980, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x55555556, 0x66666665, x1, 984, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x11111112, 0x55555556, 0x33333332, x1, 988, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555556, 0x55555554, x1, 992, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x55555556, 0x2, x1, 996, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0x55555556, 0xb504, x1, 1000, x2)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x55554054, 0x55555556, -0xb504, x1, 1004, x2)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x44444446, 0x55555556, 0x66666666, x1, 1008, x2)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x11111112, 0x55555556, 0x33333333, x1, 1012, x2)
+
+inst_254:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555556, 0x5, x1, 1016, x2)
+
+inst_255:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x55555556, -0x55555556, x1, 1020, x2)
+
+inst_256:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555556, 0x55555555, x1, 1024, x2)
+
+inst_257:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555556; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x55555556, 0x3, x1, 1028, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0xb505, x1, 1032, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, -0xb503, x1, 1036, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x66666667, x1, 1040, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x33333334, x1, 1044, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x6, x1, 1048, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, -0x55555555, x1, 1052, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x4, x1, 1056, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0xb503, x1, 1060, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0x0, x1, 1064, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x66666665, x1, 1068, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0x33333332, x1, 1072, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x55555554, x1, 1076, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0x2, x1, 1080, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0xb504, x1, 1084, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, -0xb504, x1, 1088, x2)
+
+inst_273:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x66666666, x1, 1092, x2)
+
+inst_274:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0x33333333, x1, 1096, x2)
+
+inst_275:
+// rs1_val==4 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x5, x1, 1100, x2)
+
+inst_276:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, -0x55555556, x1, 1104, x2)
+
+inst_277:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x4, 0x55555555, x1, 1108, x2)
+
+inst_278:
+// rs1_val==4 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x4; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x4, 0x3, x1, 1112, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0xb501, 0xb503, 0xb505, x1, 1116, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1, 0xb503, -0xb503, x1, 1120, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x2403, 0xb503, 0x66666667, x1, 1124, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0xb503, 0x33333334, x1, 1128, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, 0xb503, 0x6, x1, 1132, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xa003, 0xb503, -0x55555555, x1, 1136, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x1502, 0xb503, 0x55555556, x1, 1140, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb503, 0x4, x1, 1144, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0xb503, 0xb503, 0xb503, x1, 1148, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb503, 0x0, x1, 1152, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x2401, 0xb503, 0x66666665, x1, 1156, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x3102, 0xb503, 0x33333332, x1, 1160, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x1500, 0xb503, 0x55555554, x1, 1164, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0xb503, 0x2, x1, 1168, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0xb500, 0xb503, 0xb504, x1, 1172, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb503, -0xb504, x1, 1176, x2)
+
+inst_295:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x2402, 0xb503, 0x66666666, x1, 1180, x2)
+
+inst_296:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x3103, 0xb503, 0x33333333, x1, 1184, x2)
+
+inst_297:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x1, 0xb503, 0x5, x1, 1188, x2)
+
+inst_298:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xa002, 0xb503, -0x55555556, x1, 1192, x2)
+
+inst_299:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1501, 0xb503, 0x55555555, x1, 1196, x2)
+
+inst_300:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb503; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x3, 0xb503, 0x3, x1, 1200, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0xb505, x1, 1204, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, -0xb503, x1, 1208, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x66666667, x1, 1212, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x33333334, x1, 1216, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x6, x1, 1220, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, -0x55555555, x1, 1224, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x55555556, x1, 1228, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x4, x1, 1232, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0xb503, x1, 1236, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x0, x1, 1240, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x66666665, x1, 1244, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x33333332, x1, 1248, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x55555554, x1, 1252, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x2, x1, 1256, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0xb504, x1, 1260, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, -0xb504, x1, 1264, x2)
+
+inst_317:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x66666666, x1, 1268, x2)
+
+inst_318:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x33333333, x1, 1272, x2)
+
+inst_319:
+// rs1_val==0 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x5, x1, 1276, x2)
+
+inst_320:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, -0x55555556, x1, 1280, x2)
+
+inst_321:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x55555555, x1, 1284, x2)
+
+inst_322:
+// rs1_val==0 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x0; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x0, 0x3, x1, 1288, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x2405, 0x66666665, 0xb505, x1, 1292, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x66664265, 0x66666665, -0xb503, x1, 1296, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x66666665, 0x66666665, 0x66666667, x1, 1300, x2)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x66666665, 0x33333334, x1, 1304, x2)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x66666665, 0x6, x1, 1308, x2)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222221, 0x66666665, -0x55555555, x1, 1312, x2)
+
+inst_329:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x66666665, 0x55555556, x1, 1316, x2)
+
+inst_330:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x66666665, 0x4, x1, 1320, x2)
+
+inst_331:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x2401, 0x66666665, 0xb503, x1, 1324, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333333, 0x0, x1, 1328, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x22222221, 0x33333333, 0x66666665, x1, 1332, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x33333332, 0x33333333, 0x33333332, x1, 1336, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x33333333, 0x55555554, x1, 1340, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x33333333, 0x2, x1, 1344, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0x33333333, 0xb504, x1, 1348, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x33330230, 0x33333333, -0xb504, x1, 1352, x2)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333333, 0x66666666, x1, 1356, x2)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x33333333, 0x33333333, 0x33333333, x1, 1360, x2)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x33333333, 0x5, x1, 1364, x2)
+
+inst_342:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333333, -0x55555556, x1, 1368, x2)
+
+inst_343:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x11111111, 0x33333333, 0x55555555, x1, 1372, x2)
+
+inst_344:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x33333333, 0x3, x1, 1376, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, 0xb505, x1, 1380, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, -0xb503, x1, 1384, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, 0x66666667, x1, 1388, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x33333334, x1, 1392, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x6, x1, 1396, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x5, -0x55555555, x1, 1400, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x55555556, x1, 1404, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x4, x1, 1408, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x5, 0xb503, x1, 1412, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x5, 0x0, x1, 1416, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, 0x66666665, x1, 1420, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x5, 0x33333332, x1, 1424, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x55555554, x1, 1428, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x5, 0x2, x1, 1432, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0xb504, x1, 1436, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, -0xb504, x1, 1440, x2)
+
+inst_361:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x5, 0x66666666, x1, 1444, x2)
+
+inst_362:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x5, 0x33333333, x1, 1448, x2)
+
+inst_363:
+// rs1_val==5 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, 0x5, x1, 1452, x2)
+
+inst_364:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x5, -0x55555556, x1, 1456, x2)
+
+inst_365:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x5, 0x55555555, x1, 1460, x2)
+
+inst_366:
+// rs1_val==5 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x5; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x5, 0x3, x1, 1464, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0xa000, -0x55555556, 0xb505, x1, 1468, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0x55555556, -0xb503, x1, 1472, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555556, 0x66666667, x1, 1476, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x22222220, -0x55555556, 0x33333334, x1, 1480, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555556, 0x6, x1, 1484, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555555, x1, 1488, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555556, 0x55555556, x1, 1492, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555556, 0x4, x1, 1496, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0xa002, -0x55555556, 0xb503, x1, 1500, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555556, 0x0, x1, 1504, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x22222220, -0x55555556, 0x66666665, x1, 1508, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555556, 0x33333332, x1, 1512, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555556, 0x55555554, x1, 1516, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555556, 0x2, x1, 1520, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0xa000, -0x55555556, 0xb504, x1, 1524, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0x55555556, -0xb504, x1, 1528, x2)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555556, 0x66666666, x1, 1532, x2)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x22222222, -0x55555556, 0x33333333, x1, 1536, x2)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555556, 0x5, x1, 1540, x2)
+
+inst_386:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555556, x1, 1544, x2)
+
+inst_387:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, -0x55555556, 0x55555555, x1, 1548, x2)
+
+inst_388:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, -0x55555556, 0x3, x1, 1552, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x1505, 0x55555555, 0xb505, x1, 1556, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x55554055, 0x55555555, -0xb503, x1, 1560, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x44444445, 0x55555555, 0x66666667, x1, 1564, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x55555555, 0x33333334, x1, 1568, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555555, 0x6, x1, 1572, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x55555555, -0x55555555, x1, 1576, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555555, 0x55555556, x1, 1580, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555555, 0x4, x1, 1584, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1501, 0x55555555, 0xb503, x1, 1588, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555555, 0x0, x1, 1592, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x44444445, 0x55555555, 0x66666665, x1, 1596, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x55555555, 0x33333332, x1, 1600, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555555, 0x55555554, x1, 1604, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555555, 0x2, x1, 1608, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0x55555555, 0xb504, x1, 1612, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x55554054, 0x55555555, -0xb504, x1, 1616, x2)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x55555555, 0x66666666, x1, 1620, x2)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x11111111, 0x55555555, 0x33333333, x1, 1624, x2)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x55555555, 0x5, x1, 1628, x2)
+
+inst_408:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555555, -0x55555556, x1, 1632, x2)
+
+inst_409:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x55555555, 0x55555555, 0x55555555, x1, 1636, x2)
+
+inst_410:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555555; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x55555555, 0x3, x1, 1640, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x3, 0xb505, x1, 1644, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x3, -0xb503, x1, 1648, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, 0x66666667, x1, 1652, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0x33333334, x1, 1656, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, 0x6, x1, 1660, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, -0x55555555, x1, 1664, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, 0x55555556, x1, 1668, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0x4, x1, 1672, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, 0xb503, x1, 1676, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0x0, x1, 1680, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x3, 0x66666665, x1, 1684, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, 0x33333332, x1, 1688, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0x55555554, x1, 1692, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, 0x2, x1, 1696, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, 0xb504, x1, 1700, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x3, -0xb504, x1, 1704, x2)
+
+inst_427:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, 0x66666666, x1, 1708, x2)
+
+inst_428:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, 0x33333333, x1, 1712, x2)
+
+inst_429:
+// rs1_val==3 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x3, 0x5, x1, 1716, x2)
+
+inst_430:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x3, -0x55555556, x1, 1720, x2)
+
+inst_431:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x3, 0x55555555, x1, 1724, x2)
+
+inst_432:
+// rs1_val==3 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x3; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x3, 0x3, 0x3, x1, 1728, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x66666665, 0x0, x1, 1732, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x66666665, 0x66666665, 0x66666665, x1, 1736, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x22222220, 0x66666665, 0x33333332, x1, 1740, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x66666665, 0x55555554, x1, 1744, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0x66666665, 0xb504, x1, 1748, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x66664264, 0x66666665, -0xb504, x1, 1752, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x66666664, 0x66666665, 0x66666666, x1, 1756, x2)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x22222221, 0x66666665, 0x33333333, x1, 1760, x2)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x5, 0x66666665, 0x5, x1, 1764, x2)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222220, 0x66666665, -0x55555556, x1, 1768, x2)
+
+inst_443:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x44444445, 0x66666665, 0x55555555, x1, 1772, x2)
+
+inst_444:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666665; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x1, 0x66666665, 0x3, x1, 1776, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0x33333332, 0xb505, x1, 1780, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x33330230, 0x33333332, -0xb503, x1, 1784, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333332, 0x66666667, x1, 1788, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x33333330, 0x33333332, 0x33333334, x1, 1792, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x33333332, 0x6, x1, 1796, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333332, -0x55555555, x1, 1800, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x11111112, 0x33333332, 0x55555556, x1, 1804, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333332, 0x4, x1, 1808, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x3102, 0x33333332, 0xb503, x1, 1812, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333332, 0x0, x1, 1816, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x22222220, 0x33333332, 0x66666665, x1, 1820, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x33333332, 0x33333332, 0x33333332, x1, 1824, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x33333332, 0x55555554, x1, 1828, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x33333332, 0x2, x1, 1832, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0x33333332, 0xb504, x1, 1836, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x33330230, 0x33333332, -0xb504, x1, 1840, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333332, 0x66666666, x1, 1844, x2)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x33333332, 0x33333332, 0x33333333, x1, 1848, x2)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333332, 0x5, x1, 1852, x2)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x33333332, -0x55555556, x1, 1856, x2)
+
+inst_465:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x33333332, 0x55555555, x1, 1860, x2)
+
+inst_466:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333332; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x33333332, 0x3, x1, 1864, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0x55555554, 0xb505, x1, 1868, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x55554054, 0x55555554, -0xb503, x1, 1872, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x55555554, 0x66666667, x1, 1876, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x11111114, 0x55555554, 0x33333334, x1, 1880, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555554, 0x6, x1, 1884, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555554, -0x55555555, x1, 1888, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555554, 0x55555556, x1, 1892, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555554, 0x4, x1, 1896, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x1500, 0x55555554, 0xb503, x1, 1900, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555554, 0x0, x1, 1904, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x55555554, 0x66666665, x1, 1908, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x55555554, 0x33333332, x1, 1912, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555554, 0x55555554, x1, 1916, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555554, 0x2, x1, 1920, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0x55555554, 0xb504, x1, 1924, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x55554054, 0x55555554, -0xb504, x1, 1928, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x55555554, 0x66666666, x1, 1932, x2)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x11111110, 0x55555554, 0x33333333, x1, 1936, x2)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x55555554, 0x5, x1, 1940, x2)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555554, -0x55555556, x1, 1944, x2)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x55555554, 0x55555554, 0x55555555, x1, 1948, x2)
+
+inst_488:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x55555554; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x55555554, 0x3, x1, 1952, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0xb505, x1, 1956, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, -0xb503, x1, 1960, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x66666667, x1, 1964, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x33333334, x1, 1968, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x6, x1, 1972, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, -0x55555555, x1, 1976, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x55555556, x1, 1980, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x4, x1, 1984, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0xb503, x1, 1988, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x0, x1, 1992, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x66666665, x1, 1996, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x33333332, x1, 2000, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x55555554, x1, 2004, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x2, x1, 2008, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0xb504, x1, 2012, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, -0xb504, x1, 2016, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x66666666, x1, 2020, x2)
+
+inst_506:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x33333333, x1, 2024, x2)
+
+inst_507:
+// rs1_val==2 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x5, x1, 2028, x2)
+
+inst_508:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, -0x55555556, x1, 2032, x2)
+
+inst_509:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x2, 0x55555555, x1, 2036, x2)
+
+inst_510:
+// rs1_val==2 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x2; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x2, 0x3, x1, 2040, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0xb504, 0xb504, 0xb505, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb504, -0xb503, x1, 0, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0xb504, 0x66666667, x1, 4, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x3104, 0xb504, 0x33333334, x1, 8, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb504, 0x6, x1, 12, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xa000, 0xb504, -0x55555555, x1, 16, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0xb504, 0x55555556, x1, 20, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb504, 0x4, x1, 24, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0xb500, 0xb504, 0xb503, x1, 28, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb504, 0x0, x1, 32, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0xb504, 0x66666665, x1, 36, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0xb504, 0x33333332, x1, 40, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0xb504, 0x55555554, x1, 44, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb504, 0x2, x1, 48, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0xb504, 0xb504, 0xb504, x1, 52, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb504, -0xb504, x1, 56, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0xb504, 0x66666666, x1, 60, x2)
+
+inst_528:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x3100, 0xb504, 0x33333333, x1, 64, x2)
+
+inst_529:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0xb504, 0x5, x1, 68, x2)
+
+inst_530:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xa000, 0xb504, -0x55555556, x1, 72, x2)
+
+inst_531:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x1504, 0xb504, 0x55555555, x1, 76, x2)
+
+inst_532:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0xb504; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, 0xb504, 0x3, x1, 80, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb504, 0xb505, x1, 84, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0xffff4afc, -0xb504, -0xb503, x1, 88, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x66664264, -0xb504, 0x66666667, x1, 92, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x33330234, -0xb504, 0x33333334, x1, 96, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb504, 0x6, x1, 100, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0xb504, -0x55555555, x1, 104, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x55554054, -0xb504, 0x55555556, x1, 108, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb504, 0x4, x1, 112, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb504, 0xb503, x1, 116, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb504, 0x0, x1, 120, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x66664264, -0xb504, 0x66666665, x1, 124, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x33330230, -0xb504, 0x33333332, x1, 128, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x55554054, -0xb504, 0x55555554, x1, 132, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb504, 0x2, x1, 136, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb504, 0xb504, x1, 140, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0xffff4afc, -0xb504, -0xb504, x1, 144, x2)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x66664264, -0xb504, 0x66666666, x1, 148, x2)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x33330230, -0xb504, 0x33333333, x1, 152, x2)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, -0xb504, 0x5, x1, 156, x2)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0xaaaa0aa8, -0xb504, -0x55555556, x1, 160, x2)
+
+inst_553:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x55554054, -0xb504, 0x55555555, x1, 164, x2)
+
+inst_554:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:-0xb504; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x0, -0xb504, 0x3, x1, 168, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0x66666666, 0xb505, x1, 172, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x66664264, 0x66666666, -0xb503, x1, 176, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x66666666, 0x66666666, 0x66666667, x1, 180, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x22222224, 0x66666666, 0x33333334, x1, 184, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x6, 0x66666666, 0x6, x1, 188, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666666, -0x55555555, x1, 192, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x44444446, 0x66666666, 0x55555556, x1, 196, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x66666666, 0x4, x1, 200, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x2402, 0x66666666, 0xb503, x1, 204, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x0
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x66666666, 0x0, x1, 208, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665
+TEST_CR_OP( c.and, x10, x11, 0x66666664, 0x66666666, 0x66666665, x1, 212, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666666, 0x33333332, x1, 216, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x66666666, 0x55555554, x1, 220, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x2
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x66666666, 0x2, x1, 224, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504
+TEST_CR_OP( c.and, x10, x11, 0x2404, 0x66666666, 0xb504, x1, 228, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504
+TEST_CR_OP( c.and, x10, x11, 0x66664264, 0x66666666, -0xb504, x1, 232, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666
+TEST_CR_OP( c.and, x10, x11, 0x66666666, 0x66666666, 0x66666666, x1, 236, x2)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666666, 0x33333333, x1, 240, x2)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x5
+TEST_CR_OP( c.and, x10, x11, 0x4, 0x66666666, 0x5, x1, 244, x2)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x22222222, 0x66666666, -0x55555556, x1, 248, x2)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x44444444, 0x66666666, 0x55555555, x1, 252, x2)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x66666666; op2val:0x3
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x66666666, 0x3, x1, 256, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505
+TEST_CR_OP( c.and, x10, x11, 0x3101, 0x33333333, 0xb505, x1, 260, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503
+TEST_CR_OP( c.and, x10, x11, 0x33330231, 0x33333333, -0xb503, x1, 264, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667
+TEST_CR_OP( c.and, x10, x11, 0x22222223, 0x33333333, 0x66666667, x1, 268, x2)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334
+TEST_CR_OP( c.and, x10, x11, 0x33333330, 0x33333333, 0x33333334, x1, 272, x2)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x6
+TEST_CR_OP( c.and, x10, x11, 0x2, 0x33333333, 0x6, x1, 276, x2)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555
+TEST_CR_OP( c.and, x10, x11, 0x22222223, 0x33333333, -0x55555555, x1, 280, x2)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556
+TEST_CR_OP( c.and, x10, x11, 0x11111112, 0x33333333, 0x55555556, x1, 284, x2)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0x4
+TEST_CR_OP( c.and, x10, x11, 0x0, 0x33333333, 0x4, x1, 288, x2)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: c.and; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503
+TEST_CR_OP( c.and, x10, x11, 0x3103, 0x33333333, 0xb503, x1, 292, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 74*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/candi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/candi-01.S
new file mode 100644
index 000000000..ff2c2a5ba
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/candi-01.S
@@ -0,0 +1,1940 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.andi instruction of the RISC-V C extension for the candi covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",candi)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x14, imm_val == (-2**(6-1)), rs1_val != imm_val, rs1_val == 512, rs1_val > 0 and imm_val < 0, imm_val == -32
+// opcode: c.andi; op1:x14; immval:-0x20
+TEST_CI_OP( c.andi, x14, 0x200, 0x200, -0x20, x1, 0, x2)
+
+inst_1:
+// rs1==x11, rs1_val == 2147483647, imm_val == 4, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val > 0
+// opcode: c.andi; op1:x11; immval:0x4
+TEST_CI_OP( c.andi, x11, 0x4, 0x7fffffff, 0x4, x1, 4, x2)
+
+inst_2:
+// rs1==x8, rs1_val == -1073741825, imm_val == 0
+// opcode: c.andi; op1:x8; immval:0x0
+TEST_CI_OP( c.andi, x8, 0x0, -0x40000001, 0x0, x1, 8, x2)
+
+inst_3:
+// rs1==x9, rs1_val == -536870913, rs1_val < 0 and imm_val > 0
+// opcode: c.andi; op1:x9; immval:0x7
+TEST_CI_OP( c.andi, x9, 0x7, -0x20000001, 0x7, x1, 12, x2)
+
+inst_4:
+// rs1==x12, rs1_val == -268435457, 
+// opcode: c.andi; op1:x12; immval:0x3
+TEST_CI_OP( c.andi, x12, 0x3, -0x10000001, 0x3, x1, 16, x2)
+
+inst_5:
+// rs1==x15, rs1_val == -134217729, 
+// opcode: c.andi; op1:x15; immval:0x6
+TEST_CI_OP( c.andi, x15, 0x6, -0x8000001, 0x6, x1, 20, x2)
+
+inst_6:
+// rs1==x10, rs1_val == -67108865, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x9, -0x4000001, 0x9, x1, 24, x2)
+
+inst_7:
+// rs1==x13, rs1_val == -33554433, 
+// opcode: c.andi; op1:x13; immval:0x4
+TEST_CI_OP( c.andi, x13, 0x4, -0x2000001, 0x4, x1, 28, x2)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0x1000001, 0x0, x1, 32, x2)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, -0x800001, 0x5, x1, 36, x2)
+
+inst_10:
+// rs1_val == -4194305, rs1_val < 0 and imm_val < 0
+// opcode: c.andi; op1:x10; immval:-0x8
+TEST_CI_OP( c.andi, x10, 0xffbffff8, -0x400001, -0x8, x1, 40, x2)
+
+inst_11:
+// rs1_val == -2097153, imm_val == -3
+// opcode: c.andi; op1:x10; immval:-0x3
+TEST_CI_OP( c.andi, x10, 0xffdffffd, -0x200001, -0x3, x1, 44, x2)
+
+inst_12:
+// rs1_val == -1048577, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, -0x100001, 0x4, x1, 48, x2)
+
+inst_13:
+// rs1_val == -524289, imm_val == 2
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, -0x80001, 0x2, x1, 52, x2)
+
+inst_14:
+// rs1_val == -262145, 
+// opcode: c.andi; op1:x10; immval:-0x8
+TEST_CI_OP( c.andi, x10, 0xfffbfff8, -0x40001, -0x8, x1, 56, x2)
+
+inst_15:
+// rs1_val == -131073, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x7, -0x20001, 0x7, x1, 60, x2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, -0x10001, 0x6, x1, 64, x2)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, -0x8001, 0x5, x1, 68, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, -0x4001, 0x4, x1, 72, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, -0x2001, 0x3, x1, 76, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode: c.andi; op1:x10; immval:-0x6
+TEST_CI_OP( c.andi, x10, 0xffffeffa, -0x1001, -0x6, x1, 80, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, -0x801, 0x6, x1, 84, x2)
+
+inst_22:
+// rs1_val == -1025, imm_val == -5
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xfffffbfb, -0x401, -0x5, x1, 88, x2)
+
+inst_23:
+// rs1_val == -513, imm_val == -22
+// opcode: c.andi; op1:x10; immval:-0x16
+TEST_CI_OP( c.andi, x10, 0xfffffdea, -0x201, -0x16, x1, 92, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, -0x101, 0x6, x1, 96, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: c.andi; op1:x10; immval:-0x16
+TEST_CI_OP( c.andi, x10, 0xffffff6a, -0x81, -0x16, x1, 100, x2)
+
+inst_26:
+// rs1_val == -65, imm_val == -2
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xffffffbe, -0x41, -0x2, x1, 104, x2)
+
+inst_27:
+// rs1_val == -33, 
+// opcode: c.andi; op1:x10; immval:-0x10
+TEST_CI_OP( c.andi, x10, 0xffffffd0, -0x21, -0x10, x1, 108, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, -0x11, 0x4, x1, 112, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0x9, 0x0, x1, 116, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, -0x5, 0x2, x1, 120, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, -0x3, 0x2, x1, 124, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, -0x2, 0x6, x1, 128, x2)
+
+inst_33:
+// imm_val == 31, imm_val == (2**(6-1)-1)
+// opcode: c.andi; op1:x10; immval:0x1f
+TEST_CI_OP( c.andi, x10, 0x1f, -0x8000001, 0x1f, x1, 132, x2)
+
+inst_34:
+// imm_val == -17, rs1_val == 2048
+// opcode: c.andi; op1:x10; immval:-0x11
+TEST_CI_OP( c.andi, x10, 0x800, 0x800, -0x11, x1, 136, x2)
+
+inst_35:
+// imm_val == -9, 
+// opcode: c.andi; op1:x10; immval:-0x9
+TEST_CI_OP( c.andi, x10, 0x5, 0x5, -0x9, x1, 140, x2)
+
+inst_36:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, -0x80000000, 0x3, x1, 144, x2)
+
+inst_37:
+// rs1_val == 1073741824, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x40000000, 0x0, x1, 148, x2)
+
+inst_38:
+// rs1_val == 536870912, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x20000000, 0x5, x1, 152, x2)
+
+inst_39:
+// rs1_val == 268435456, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x10000000, 0x10000000, -0x2, x1, 156, x2)
+
+inst_40:
+// rs1_val == 134217728, imm_val == 1
+// opcode: c.andi; op1:x10; immval:0x1
+TEST_CI_OP( c.andi, x10, 0x0, 0x8000000, 0x1, x1, 160, x2)
+
+inst_41:
+// rs1_val == 67108864, imm_val == 16
+// opcode: c.andi; op1:x10; immval:0x10
+TEST_CI_OP( c.andi, x10, 0x0, 0x4000000, 0x10, x1, 164, x2)
+
+inst_42:
+// rs1_val == 33554432, 
+// opcode: c.andi; op1:x10; immval:-0x20
+TEST_CI_OP( c.andi, x10, 0x2000000, 0x2000000, -0x20, x1, 168, x2)
+
+inst_43:
+// rs1_val == 16777216, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x1000000, 0x1000000, -0x4, x1, 172, x2)
+
+inst_44:
+// rs1_val == 8388608, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x800000, 0x2, x1, 176, x2)
+
+inst_45:
+// rs1_val == 4194304, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x400000, 0x0, x1, 180, x2)
+
+inst_46:
+// rs1_val == 2097152, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x200000, 0x4, x1, 184, x2)
+
+inst_47:
+// rs1_val == 1048576, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x100000, 0x4, x1, 188, x2)
+
+inst_48:
+// rs1_val == 524288, 
+// opcode: c.andi; op1:x10; immval:0xf
+TEST_CI_OP( c.andi, x10, 0x0, 0x80000, 0xf, x1, 192, x2)
+
+inst_49:
+// rs1_val == 262144, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x40000, 0x2, x1, 196, x2)
+
+inst_50:
+// rs1_val == 131072, 
+// opcode: c.andi; op1:x10; immval:0x1f
+TEST_CI_OP( c.andi, x10, 0x0, 0x20000, 0x1f, x1, 200, x2)
+
+inst_51:
+// rs1_val == 65536, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x10000, 0x0, x1, 204, x2)
+
+inst_52:
+// rs1_val == 32768, 
+// opcode: c.andi; op1:x10; immval:-0xa
+TEST_CI_OP( c.andi, x10, 0x8000, 0x8000, -0xa, x1, 208, x2)
+
+inst_53:
+// rs1_val == 16384, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0x4000, 0xb, x1, 212, x2)
+
+inst_54:
+// rs1_val == 8192, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x0, 0x2000, 0x6, x1, 216, x2)
+
+inst_55:
+// rs1_val == 4096, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x0, 0x1000, 0x6, x1, 220, x2)
+
+inst_56:
+// rs1_val == 1024, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x0, 0x400, 0x6, x1, 224, x2)
+
+inst_57:
+// rs1_val == 256, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x0, 0x100, 0x6, x1, 228, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode: c.andi; op1:x10; immval:-0x8
+TEST_CI_OP( c.andi, x10, 0x80, 0x80, -0x8, x1, 232, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x40, 0xa, x1, 236, x2)
+
+inst_60:
+// rs1_val == 32, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x20, 0x4, x1, 240, x2)
+
+inst_61:
+// rs1_val == 16, imm_val == 8
+// opcode: c.andi; op1:x10; immval:0x8
+TEST_CI_OP( c.andi, x10, 0x0, 0x10, 0x8, x1, 244, x2)
+
+inst_62:
+// rs1_val == 8, 
+// opcode: c.andi; op1:x10; immval:-0x11
+TEST_CI_OP( c.andi, x10, 0x8, 0x8, -0x11, x1, 248, x2)
+
+inst_63:
+// rs1_val == 4, rs1_val==4 and imm_val==0
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0x0, x1, 252, x2)
+
+inst_64:
+// rs1_val == 2, 
+// opcode: c.andi; op1:x10; immval:0x8
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, 0x8, x1, 256, x2)
+
+inst_65:
+// rs1_val == 1, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x1, 0x0, x1, 260, x2)
+
+inst_66:
+// rs1_val==46341 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0xb505, 0x6, x1, 264, x2)
+
+inst_67:
+// rs1_val==46341 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xb504, 0xb505, -0x4, x1, 268, x2)
+
+inst_68:
+// rs1_val==46341 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xb505, 0xb505, -0x1, x1, 272, x2)
+
+inst_69:
+// rs1_val==46341 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x5, 0xb505, 0x7, x1, 276, x2)
+
+inst_70:
+// rs1_val==46341 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0xb505, 0x4, x1, 280, x2)
+
+inst_71:
+// rs1_val==46341 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x1, 0xb505, 0xb, x1, 284, x2)
+
+inst_72:
+// rs1_val==46341 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0xb505, 0x0, x1, 288, x2)
+
+inst_73:
+// rs1_val==46341 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, 0xb505, 0x5, x1, 292, x2)
+
+inst_74:
+// rs1_val==46341 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0xb505, 0x2, x1, 296, x2)
+
+inst_75:
+// rs1_val==46341 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0xb505, 0x9, x1, 300, x2)
+
+inst_76:
+// rs1_val==46341 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xb501, 0xb505, -0x5, x1, 304, x2)
+
+inst_77:
+// rs1_val==46341 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xb504, 0xb505, -0x2, x1, 308, x2)
+
+inst_78:
+// rs1_val==46341 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x1, 0xb505, 0x3, x1, 312, x2)
+
+inst_79:
+// rs1_val==46341 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0xb505, 0xa, x1, 316, x2)
+
+inst_80:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, -0xb503, 0x6, x1, 320, x2)
+
+inst_81:
+// rs1_val==-46339 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xffff4afc, -0xb503, -0x4, x1, 324, x2)
+
+inst_82:
+// rs1_val==-46339 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xffff4afd, -0xb503, -0x1, x1, 328, x2)
+
+inst_83:
+// rs1_val==-46339 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x5, -0xb503, 0x7, x1, 332, x2)
+
+inst_84:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, -0xb503, 0x4, x1, 336, x2)
+
+inst_85:
+// rs1_val==-46339 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x9, -0xb503, 0xb, x1, 340, x2)
+
+inst_86:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0xb503, 0x0, x1, 344, x2)
+
+inst_87:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, -0xb503, 0x5, x1, 348, x2)
+
+inst_88:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, -0xb503, 0x2, x1, 352, x2)
+
+inst_89:
+// rs1_val==-46339 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x9, -0xb503, 0x9, x1, 356, x2)
+
+inst_90:
+// rs1_val==-46339 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xffff4af9, -0xb503, -0x5, x1, 360, x2)
+
+inst_91:
+// rs1_val==-46339 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xffff4afc, -0xb503, -0x2, x1, 364, x2)
+
+inst_92:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x1, -0xb503, 0x3, x1, 368, x2)
+
+inst_93:
+// rs1_val==-46339 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x8, -0xb503, 0xa, x1, 372, x2)
+
+inst_94:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, 0x66666667, 0x6, x1, 376, x2)
+
+inst_95:
+// rs1_val==1717986919 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x66666664, 0x66666667, -0x4, x1, 380, x2)
+
+inst_96:
+// rs1_val==1717986919 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x66666667, 0x66666667, -0x1, x1, 384, x2)
+
+inst_97:
+// rs1_val==1717986919 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x7, 0x66666667, 0x7, x1, 388, x2)
+
+inst_98:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x66666667, 0x4, x1, 392, x2)
+
+inst_99:
+// rs1_val==1717986919 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x3, 0x66666667, 0xb, x1, 396, x2)
+
+inst_100:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666667, 0x0, x1, 400, x2)
+
+inst_101:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, 0x66666667, 0x5, x1, 404, x2)
+
+inst_102:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666667, 0x2, x1, 408, x2)
+
+inst_103:
+// rs1_val==1717986919 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x66666667, 0x9, x1, 412, x2)
+
+inst_104:
+// rs1_val==1717986919 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x66666663, 0x66666667, -0x5, x1, 416, x2)
+
+inst_105:
+// rs1_val==1717986919 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x66666666, 0x66666667, -0x2, x1, 420, x2)
+
+inst_106:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, 0x66666667, 0x3, x1, 424, x2)
+
+inst_107:
+// rs1_val==1717986919 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666667, 0xa, x1, 428, x2)
+
+inst_108:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x33333334, 0x6, x1, 432, x2)
+
+inst_109:
+// rs1_val==858993460 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x33333334, 0x33333334, -0x4, x1, 436, x2)
+
+inst_110:
+// rs1_val==858993460 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x33333334, 0x33333334, -0x1, x1, 440, x2)
+
+inst_111:
+// rs1_val==858993460 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x4, 0x33333334, 0x7, x1, 444, x2)
+
+inst_112:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x33333334, 0x4, x1, 448, x2)
+
+inst_113:
+// rs1_val==858993460 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0xb, x1, 452, x2)
+
+inst_114:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0x0, x1, 456, x2)
+
+inst_115:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x33333334, 0x5, x1, 460, x2)
+
+inst_116:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0x2, x1, 464, x2)
+
+inst_117:
+// rs1_val==858993460 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0x9, x1, 468, x2)
+
+inst_118:
+// rs1_val==858993460 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x33333330, 0x33333334, -0x5, x1, 472, x2)
+
+inst_119:
+// rs1_val==858993460 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x33333334, 0x33333334, -0x2, x1, 476, x2)
+
+inst_120:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0x3, x1, 480, x2)
+
+inst_121:
+// rs1_val==858993460 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333334, 0xa, x1, 484, x2)
+
+inst_122:
+// rs1_val==6 and imm_val==6, rs1_val == imm_val
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, 0x6, 0x6, x1, 488, x2)
+
+inst_123:
+// rs1_val==6 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x6, -0x4, x1, 492, x2)
+
+inst_124:
+// rs1_val==6 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x6, 0x6, -0x1, x1, 496, x2)
+
+inst_125:
+// rs1_val==6 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x6, 0x6, 0x7, x1, 500, x2)
+
+inst_126:
+// rs1_val==6 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x6, 0x4, x1, 504, x2)
+
+inst_127:
+// rs1_val==6 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x2, 0x6, 0xb, x1, 508, x2)
+
+inst_128:
+// rs1_val==6 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x6, 0x0, x1, 512, x2)
+
+inst_129:
+// rs1_val==6 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x6, 0x5, x1, 516, x2)
+
+inst_130:
+// rs1_val==6 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x6, 0x2, x1, 520, x2)
+
+inst_131:
+// rs1_val==6 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x6, 0x9, x1, 524, x2)
+
+inst_132:
+// rs1_val==6 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x2, 0x6, -0x5, x1, 528, x2)
+
+inst_133:
+// rs1_val==6 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x6, 0x6, -0x2, x1, 532, x2)
+
+inst_134:
+// rs1_val==6 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, 0x6, 0x3, x1, 536, x2)
+
+inst_135:
+// rs1_val==6 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x6, 0xa, x1, 540, x2)
+
+inst_136:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555555, 0x6, x1, 544, x2)
+
+inst_137:
+// rs1_val==-1431655765 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xaaaaaaa8, -0x55555555, -0x4, x1, 548, x2)
+
+inst_138:
+// rs1_val==-1431655765 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xaaaaaaab, -0x55555555, -0x1, x1, 552, x2)
+
+inst_139:
+// rs1_val==-1431655765 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x3, -0x55555555, 0x7, x1, 556, x2)
+
+inst_140:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555555, 0x4, x1, 560, x2)
+
+inst_141:
+// rs1_val==-1431655765 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0xb, -0x55555555, 0xb, x1, 564, x2)
+
+inst_142:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555555, 0x0, x1, 568, x2)
+
+inst_143:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x1, -0x55555555, 0x5, x1, 572, x2)
+
+inst_144:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555555, 0x2, x1, 576, x2)
+
+inst_145:
+// rs1_val==-1431655765 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x9, -0x55555555, 0x9, x1, 580, x2)
+
+inst_146:
+// rs1_val==-1431655765 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xaaaaaaab, -0x55555555, -0x5, x1, 584, x2)
+
+inst_147:
+// rs1_val==-1431655765 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xaaaaaaaa, -0x55555555, -0x2, x1, 588, x2)
+
+inst_148:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, -0x55555555, 0x3, x1, 592, x2)
+
+inst_149:
+// rs1_val==-1431655765 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0xa, -0x55555555, 0xa, x1, 596, x2)
+
+inst_150:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, 0x55555556, 0x6, x1, 600, x2)
+
+inst_151:
+// rs1_val==1431655766 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555556, -0x4, x1, 604, x2)
+
+inst_152:
+// rs1_val==1431655766 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x55555556, 0x55555556, -0x1, x1, 608, x2)
+
+inst_153:
+// rs1_val==1431655766 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x6, 0x55555556, 0x7, x1, 612, x2)
+
+inst_154:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555556, 0x4, x1, 616, x2)
+
+inst_155:
+// rs1_val==1431655766 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x2, 0x55555556, 0xb, x1, 620, x2)
+
+inst_156:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555556, 0x0, x1, 624, x2)
+
+inst_157:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555556, 0x5, x1, 628, x2)
+
+inst_158:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x55555556, 0x2, x1, 632, x2)
+
+inst_159:
+// rs1_val==1431655766 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555556, 0x9, x1, 636, x2)
+
+inst_160:
+// rs1_val==1431655766 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x55555552, 0x55555556, -0x5, x1, 640, x2)
+
+inst_161:
+// rs1_val==1431655766 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x55555556, 0x55555556, -0x2, x1, 644, x2)
+
+inst_162:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, 0x55555556, 0x3, x1, 648, x2)
+
+inst_163:
+// rs1_val==1431655766 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x55555556, 0xa, x1, 652, x2)
+
+inst_164:
+// rs1_val==4 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, 0x6, x1, 656, x2)
+
+inst_165:
+// rs1_val==4 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, -0x4, x1, 660, x2)
+
+inst_166:
+// rs1_val==4 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, -0x1, x1, 664, x2)
+
+inst_167:
+// rs1_val==4 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, 0x7, x1, 668, x2)
+
+inst_168:
+// rs1_val==4 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, 0x4, x1, 672, x2)
+
+inst_169:
+// rs1_val==4 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0xb, x1, 676, x2)
+
+inst_170:
+// rs1_val==4 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, 0x5, x1, 680, x2)
+
+inst_171:
+// rs1_val==4 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0x2, x1, 684, x2)
+
+inst_172:
+// rs1_val==4 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0x9, x1, 688, x2)
+
+inst_173:
+// rs1_val==4 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, -0x5, x1, 692, x2)
+
+inst_174:
+// rs1_val==4 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x4, 0x4, -0x2, x1, 696, x2)
+
+inst_175:
+// rs1_val==4 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0x3, x1, 700, x2)
+
+inst_176:
+// rs1_val==4 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x4, 0xa, x1, 704, x2)
+
+inst_177:
+// rs1_val==46339 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, 0xb503, 0x6, x1, 708, x2)
+
+inst_178:
+// rs1_val==46339 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xb500, 0xb503, -0x4, x1, 712, x2)
+
+inst_179:
+// rs1_val==46339 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xb503, 0xb503, -0x1, x1, 716, x2)
+
+inst_180:
+// rs1_val==46339 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x3, 0xb503, 0x7, x1, 720, x2)
+
+inst_181:
+// rs1_val==46339 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0xb503, 0x4, x1, 724, x2)
+
+inst_182:
+// rs1_val==46339 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x3, 0xb503, 0xb, x1, 728, x2)
+
+inst_183:
+// rs1_val==46339 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0xb503, 0x0, x1, 732, x2)
+
+inst_184:
+// rs1_val==46339 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x1, 0xb503, 0x5, x1, 736, x2)
+
+inst_185:
+// rs1_val==46339 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0xb503, 0x2, x1, 740, x2)
+
+inst_186:
+// rs1_val==46339 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0xb503, 0x9, x1, 744, x2)
+
+inst_187:
+// rs1_val==46339 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xb503, 0xb503, -0x5, x1, 748, x2)
+
+inst_188:
+// rs1_val==46339 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xb502, 0xb503, -0x2, x1, 752, x2)
+
+inst_189:
+// rs1_val==46339 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, 0xb503, 0x3, x1, 756, x2)
+
+inst_190:
+// rs1_val==46339 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0xb503, 0xa, x1, 760, x2)
+
+inst_191:
+// rs1_val==0 and imm_val==6, rs1_val == 0
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x6, x1, 764, x2)
+
+inst_192:
+// rs1_val==0 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, -0x4, x1, 768, x2)
+
+inst_193:
+// rs1_val==0 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, -0x1, x1, 772, x2)
+
+inst_194:
+// rs1_val==0 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x7, x1, 776, x2)
+
+inst_195:
+// rs1_val==0 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x4, x1, 780, x2)
+
+inst_196:
+// rs1_val==0 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0xb, x1, 784, x2)
+
+inst_197:
+// rs1_val==0 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x0, x1, 788, x2)
+
+inst_198:
+// rs1_val==0 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x5, x1, 792, x2)
+
+inst_199:
+// rs1_val==0 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x2, x1, 796, x2)
+
+inst_200:
+// rs1_val==0 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x9, x1, 800, x2)
+
+inst_201:
+// rs1_val==0 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, -0x5, x1, 804, x2)
+
+inst_202:
+// rs1_val==0 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, -0x2, x1, 808, x2)
+
+inst_203:
+// rs1_val==0 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0x3, x1, 812, x2)
+
+inst_204:
+// rs1_val==0 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x0, 0xa, x1, 816, x2)
+
+inst_205:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x66666665, 0x6, x1, 820, x2)
+
+inst_206:
+// rs1_val==1717986917 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x66666664, 0x66666665, -0x4, x1, 824, x2)
+
+inst_207:
+// rs1_val==1717986917 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x66666665, 0x66666665, -0x1, x1, 828, x2)
+
+inst_208:
+// rs1_val==1717986917 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x5, 0x66666665, 0x7, x1, 832, x2)
+
+inst_209:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x66666665, 0x4, x1, 836, x2)
+
+inst_210:
+// rs1_val==1717986917 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x1, 0x66666665, 0xb, x1, 840, x2)
+
+inst_211:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666665, 0x0, x1, 844, x2)
+
+inst_212:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, 0x66666665, 0x5, x1, 848, x2)
+
+inst_213:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666665, 0x2, x1, 852, x2)
+
+inst_214:
+// rs1_val==1717986917 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x66666665, 0x9, x1, 856, x2)
+
+inst_215:
+// rs1_val==1717986917 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x66666661, 0x66666665, -0x5, x1, 860, x2)
+
+inst_216:
+// rs1_val==1717986917 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x66666664, 0x66666665, -0x2, x1, 864, x2)
+
+inst_217:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x1, 0x66666665, 0x3, x1, 868, x2)
+
+inst_218:
+// rs1_val==1717986917 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666665, 0xa, x1, 872, x2)
+
+inst_219:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0x6, x1, 876, x2)
+
+inst_220:
+// rs1_val==858993458 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x33333330, 0x33333332, -0x4, x1, 880, x2)
+
+inst_221:
+// rs1_val==858993458 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x33333332, 0x33333332, -0x1, x1, 884, x2)
+
+inst_222:
+// rs1_val==858993458 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0x7, x1, 888, x2)
+
+inst_223:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333332, 0x4, x1, 892, x2)
+
+inst_224:
+// rs1_val==858993458 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0xb, x1, 896, x2)
+
+inst_225:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333332, 0x0, x1, 900, x2)
+
+inst_226:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333332, 0x5, x1, 904, x2)
+
+inst_227:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0x2, x1, 908, x2)
+
+inst_228:
+// rs1_val==858993458 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333332, 0x9, x1, 912, x2)
+
+inst_229:
+// rs1_val==858993458 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x33333332, 0x33333332, -0x5, x1, 916, x2)
+
+inst_230:
+// rs1_val==858993458 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x33333332, 0x33333332, -0x2, x1, 920, x2)
+
+inst_231:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0x3, x1, 924, x2)
+
+inst_232:
+// rs1_val==858993458 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333332, 0xa, x1, 928, x2)
+
+inst_233:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555554, 0x6, x1, 932, x2)
+
+inst_234:
+// rs1_val==1431655764 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555554, -0x4, x1, 936, x2)
+
+inst_235:
+// rs1_val==1431655764 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555554, -0x1, x1, 940, x2)
+
+inst_236:
+// rs1_val==1431655764 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555554, 0x7, x1, 944, x2)
+
+inst_237:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555554, 0x4, x1, 948, x2)
+
+inst_238:
+// rs1_val==1431655764 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0xb, x1, 952, x2)
+
+inst_239:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0x0, x1, 956, x2)
+
+inst_240:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555554, 0x5, x1, 960, x2)
+
+inst_241:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0x2, x1, 964, x2)
+
+inst_242:
+// rs1_val==1431655764 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0x9, x1, 968, x2)
+
+inst_243:
+// rs1_val==1431655764 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x55555550, 0x55555554, -0x5, x1, 972, x2)
+
+inst_244:
+// rs1_val==1431655764 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555554, -0x2, x1, 976, x2)
+
+inst_245:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0x3, x1, 980, x2)
+
+inst_246:
+// rs1_val==1431655764 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555554, 0xa, x1, 984, x2)
+
+inst_247:
+// rs1_val==2 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0x6, x1, 988, x2)
+
+inst_248:
+// rs1_val==2 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, -0x4, x1, 992, x2)
+
+inst_249:
+// rs1_val==2 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, -0x1, x1, 996, x2)
+
+inst_250:
+// rs1_val==2 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0x7, x1, 1000, x2)
+
+inst_251:
+// rs1_val==2 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, 0x4, x1, 1004, x2)
+
+inst_252:
+// rs1_val==2 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0xb, x1, 1008, x2)
+
+inst_253:
+// rs1_val==2 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, 0x0, x1, 1012, x2)
+
+inst_254:
+// rs1_val==2 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, 0x5, x1, 1016, x2)
+
+inst_255:
+// rs1_val==2 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0x2, x1, 1020, x2)
+
+inst_256:
+// rs1_val==2 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x2, 0x9, x1, 1024, x2)
+
+inst_257:
+// rs1_val==2 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, -0x5, x1, 1028, x2)
+
+inst_258:
+// rs1_val==2 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, -0x2, x1, 1032, x2)
+
+inst_259:
+// rs1_val==2 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0x3, x1, 1036, x2)
+
+inst_260:
+// rs1_val==2 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x2, 0xa, x1, 1040, x2)
+
+inst_261:
+// rs1_val==46340 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0xb504, 0x6, x1, 1044, x2)
+
+inst_262:
+// rs1_val==46340 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xb504, 0xb504, -0x4, x1, 1048, x2)
+
+inst_263:
+// rs1_val==46340 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xb504, 0xb504, -0x1, x1, 1052, x2)
+
+inst_264:
+// rs1_val==46340 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x4, 0xb504, 0x7, x1, 1056, x2)
+
+inst_265:
+// rs1_val==46340 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0xb504, 0x4, x1, 1060, x2)
+
+inst_266:
+// rs1_val==46340 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0xb, x1, 1064, x2)
+
+inst_267:
+// rs1_val==46340 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0x0, x1, 1068, x2)
+
+inst_268:
+// rs1_val==46340 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0xb504, 0x5, x1, 1072, x2)
+
+inst_269:
+// rs1_val==46340 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0x2, x1, 1076, x2)
+
+inst_270:
+// rs1_val==46340 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0x9, x1, 1080, x2)
+
+inst_271:
+// rs1_val==46340 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xb500, 0xb504, -0x5, x1, 1084, x2)
+
+inst_272:
+// rs1_val==46340 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xb504, 0xb504, -0x2, x1, 1088, x2)
+
+inst_273:
+// rs1_val==46340 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0x3, x1, 1092, x2)
+
+inst_274:
+// rs1_val==46340 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0xb504, 0xa, x1, 1096, x2)
+
+inst_275:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, -0xb504, 0x6, x1, 1100, x2)
+
+inst_276:
+// rs1_val==-46340 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xffff4afc, -0xb504, -0x4, x1, 1104, x2)
+
+inst_277:
+// rs1_val==-46340 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xffff4afc, -0xb504, -0x1, x1, 1108, x2)
+
+inst_278:
+// rs1_val==-46340 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x4, -0xb504, 0x7, x1, 1112, x2)
+
+inst_279:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, -0xb504, 0x4, x1, 1116, x2)
+
+inst_280:
+// rs1_val==-46340 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x8, -0xb504, 0xb, x1, 1120, x2)
+
+inst_281:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0xb504, 0x0, x1, 1124, x2)
+
+inst_282:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, -0xb504, 0x5, x1, 1128, x2)
+
+inst_283:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, -0xb504, 0x2, x1, 1132, x2)
+
+inst_284:
+// rs1_val==-46340 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x8, -0xb504, 0x9, x1, 1136, x2)
+
+inst_285:
+// rs1_val==-46340 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xffff4af8, -0xb504, -0x5, x1, 1140, x2)
+
+inst_286:
+// rs1_val==-46340 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xffff4afc, -0xb504, -0x2, x1, 1144, x2)
+
+inst_287:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x0, -0xb504, 0x3, x1, 1148, x2)
+
+inst_288:
+// rs1_val==-46340 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x8, -0xb504, 0xa, x1, 1152, x2)
+
+inst_289:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x6, 0x66666666, 0x6, x1, 1156, x2)
+
+inst_290:
+// rs1_val==1717986918 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x66666664, 0x66666666, -0x4, x1, 1160, x2)
+
+inst_291:
+// rs1_val==1717986918 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x66666666, 0x66666666, -0x1, x1, 1164, x2)
+
+inst_292:
+// rs1_val==1717986918 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x6, 0x66666666, 0x7, x1, 1168, x2)
+
+inst_293:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x66666666, 0x4, x1, 1172, x2)
+
+inst_294:
+// rs1_val==1717986918 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666666, 0xb, x1, 1176, x2)
+
+inst_295:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666666, 0x0, x1, 1180, x2)
+
+inst_296:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x4, 0x66666666, 0x5, x1, 1184, x2)
+
+inst_297:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666666, 0x2, x1, 1188, x2)
+
+inst_298:
+// rs1_val==1717986918 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x0, 0x66666666, 0x9, x1, 1192, x2)
+
+inst_299:
+// rs1_val==1717986918 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x66666662, 0x66666666, -0x5, x1, 1196, x2)
+
+inst_300:
+// rs1_val==1717986918 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x66666666, 0x66666666, -0x2, x1, 1200, x2)
+
+inst_301:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666666, 0x3, x1, 1204, x2)
+
+inst_302:
+// rs1_val==1717986918 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x66666666, 0xa, x1, 1208, x2)
+
+inst_303:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333333, 0x6, x1, 1212, x2)
+
+inst_304:
+// rs1_val==858993459 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x33333330, 0x33333333, -0x4, x1, 1216, x2)
+
+inst_305:
+// rs1_val==858993459 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x33333333, 0x33333333, -0x1, x1, 1220, x2)
+
+inst_306:
+// rs1_val==858993459 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x3, 0x33333333, 0x7, x1, 1224, x2)
+
+inst_307:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333333, 0x4, x1, 1228, x2)
+
+inst_308:
+// rs1_val==858993459 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x3, 0x33333333, 0xb, x1, 1232, x2)
+
+inst_309:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x33333333, 0x0, x1, 1236, x2)
+
+inst_310:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x1, 0x33333333, 0x5, x1, 1240, x2)
+
+inst_311:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333333, 0x2, x1, 1244, x2)
+
+inst_312:
+// rs1_val==858993459 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x33333333, 0x9, x1, 1248, x2)
+
+inst_313:
+// rs1_val==3 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x3, 0xa, x1, 1252, x2)
+
+inst_314:
+// rs1_val == -1431655766, rs1_val==-1431655766 and imm_val==5
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555556, 0x5, x1, 1256, x2)
+
+inst_315:
+// rs1_val == 1431655765, rs1_val==1431655765 and imm_val==4
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555555, 0x4, x1, 1260, x2)
+
+inst_316:
+// imm_val == 21, 
+// opcode: c.andi; op1:x10; immval:0x15
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555556, 0x15, x1, 1264, x2)
+
+inst_317:
+// rs1_val==858993459 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x33333333, 0x33333333, -0x5, x1, 1268, x2)
+
+inst_318:
+// rs1_val==858993459 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x33333332, 0x33333333, -0x2, x1, 1272, x2)
+
+inst_319:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, 0x33333333, 0x3, x1, 1276, x2)
+
+inst_320:
+// rs1_val==858993459 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x2, 0x33333333, 0xa, x1, 1280, x2)
+
+inst_321:
+// rs1_val==5 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x5, 0x6, x1, 1284, x2)
+
+inst_322:
+// rs1_val==5 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x5, -0x4, x1, 1288, x2)
+
+inst_323:
+// rs1_val==5 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x5, 0x5, -0x1, x1, 1292, x2)
+
+inst_324:
+// rs1_val==5 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x5, 0x5, 0x7, x1, 1296, x2)
+
+inst_325:
+// rs1_val==5 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x4, 0x5, 0x4, x1, 1300, x2)
+
+inst_326:
+// rs1_val==5 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x1, 0x5, 0xb, x1, 1304, x2)
+
+inst_327:
+// rs1_val==5 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x5, 0x0, x1, 1308, x2)
+
+inst_328:
+// rs1_val==5 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, 0x5, 0x5, x1, 1312, x2)
+
+inst_329:
+// rs1_val==5 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x5, 0x2, x1, 1316, x2)
+
+inst_330:
+// rs1_val==5 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x5, 0x9, x1, 1320, x2)
+
+inst_331:
+// rs1_val==5 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x1, 0x5, -0x5, x1, 1324, x2)
+
+inst_332:
+// rs1_val==5 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x4, 0x5, -0x2, x1, 1328, x2)
+
+inst_333:
+// rs1_val==5 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x1, 0x5, 0x3, x1, 1332, x2)
+
+inst_334:
+// rs1_val==5 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x5, 0xa, x1, 1336, x2)
+
+inst_335:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555556, 0x6, x1, 1340, x2)
+
+inst_336:
+// rs1_val==-1431655766 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0xaaaaaaa8, -0x55555556, -0x4, x1, 1344, x2)
+
+inst_337:
+// rs1_val==-1431655766 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0xaaaaaaaa, -0x55555556, -0x1, x1, 1348, x2)
+
+inst_338:
+// rs1_val==-1431655766 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555556, 0x7, x1, 1352, x2)
+
+inst_339:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555556, 0x4, x1, 1356, x2)
+
+inst_340:
+// rs1_val==-1431655766 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0xa, -0x55555556, 0xb, x1, 1360, x2)
+
+inst_341:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, -0x55555556, 0x0, x1, 1364, x2)
+
+inst_342:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555556, 0x2, x1, 1368, x2)
+
+inst_343:
+// rs1_val==-1431655766 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x8, -0x55555556, 0x9, x1, 1372, x2)
+
+inst_344:
+// rs1_val==-1431655766 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0xaaaaaaaa, -0x55555556, -0x5, x1, 1376, x2)
+
+inst_345:
+// rs1_val==-1431655766 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0xaaaaaaaa, -0x55555556, -0x2, x1, 1380, x2)
+
+inst_346:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x2, -0x55555556, 0x3, x1, 1384, x2)
+
+inst_347:
+// rs1_val==-1431655766 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0xa, -0x55555556, 0xa, x1, 1388, x2)
+
+inst_348:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x4, 0x55555555, 0x6, x1, 1392, x2)
+
+inst_349:
+// rs1_val==1431655765 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555555, -0x4, x1, 1396, x2)
+
+inst_350:
+// rs1_val==1431655765 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x55555555, 0x55555555, -0x1, x1, 1400, x2)
+
+inst_351:
+// rs1_val==1431655765 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x5, 0x55555555, 0x7, x1, 1404, x2)
+
+inst_352:
+// rs1_val==1431655765 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x1, 0x55555555, 0xb, x1, 1408, x2)
+
+inst_353:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555555, 0x0, x1, 1412, x2)
+
+inst_354:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x5, 0x55555555, 0x5, x1, 1416, x2)
+
+inst_355:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555555, 0x2, x1, 1420, x2)
+
+inst_356:
+// rs1_val==1431655765 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x55555555, 0x9, x1, 1424, x2)
+
+inst_357:
+// rs1_val==1431655765 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x55555551, 0x55555555, -0x5, x1, 1428, x2)
+
+inst_358:
+// rs1_val==1431655765 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x55555554, 0x55555555, -0x2, x1, 1432, x2)
+
+inst_359:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x1, 0x55555555, 0x3, x1, 1436, x2)
+
+inst_360:
+// rs1_val==1431655765 and imm_val==10, 
+// opcode: c.andi; op1:x10; immval:0xa
+TEST_CI_OP( c.andi, x10, 0x0, 0x55555555, 0xa, x1, 1440, x2)
+
+inst_361:
+// rs1_val==3 and imm_val==6, 
+// opcode: c.andi; op1:x10; immval:0x6
+TEST_CI_OP( c.andi, x10, 0x2, 0x3, 0x6, x1, 1444, x2)
+
+inst_362:
+// rs1_val==3 and imm_val==-4, 
+// opcode: c.andi; op1:x10; immval:-0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x3, -0x4, x1, 1448, x2)
+
+inst_363:
+// rs1_val==3 and imm_val==-1, 
+// opcode: c.andi; op1:x10; immval:-0x1
+TEST_CI_OP( c.andi, x10, 0x3, 0x3, -0x1, x1, 1452, x2)
+
+inst_364:
+// rs1_val==3 and imm_val==7, 
+// opcode: c.andi; op1:x10; immval:0x7
+TEST_CI_OP( c.andi, x10, 0x3, 0x3, 0x7, x1, 1456, x2)
+
+inst_365:
+// rs1_val==3 and imm_val==4, 
+// opcode: c.andi; op1:x10; immval:0x4
+TEST_CI_OP( c.andi, x10, 0x0, 0x3, 0x4, x1, 1460, x2)
+
+inst_366:
+// rs1_val==3 and imm_val==11, 
+// opcode: c.andi; op1:x10; immval:0xb
+TEST_CI_OP( c.andi, x10, 0x3, 0x3, 0xb, x1, 1464, x2)
+
+inst_367:
+// rs1_val==3 and imm_val==0, 
+// opcode: c.andi; op1:x10; immval:0x0
+TEST_CI_OP( c.andi, x10, 0x0, 0x3, 0x0, x1, 1468, x2)
+
+inst_368:
+// rs1_val==3 and imm_val==5, 
+// opcode: c.andi; op1:x10; immval:0x5
+TEST_CI_OP( c.andi, x10, 0x1, 0x3, 0x5, x1, 1472, x2)
+
+inst_369:
+// rs1_val==3 and imm_val==2, 
+// opcode: c.andi; op1:x10; immval:0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x3, 0x2, x1, 1476, x2)
+
+inst_370:
+// rs1_val==3 and imm_val==9, 
+// opcode: c.andi; op1:x10; immval:0x9
+TEST_CI_OP( c.andi, x10, 0x1, 0x3, 0x9, x1, 1480, x2)
+
+inst_371:
+// rs1_val==3 and imm_val==-5, 
+// opcode: c.andi; op1:x10; immval:-0x5
+TEST_CI_OP( c.andi, x10, 0x3, 0x3, -0x5, x1, 1484, x2)
+
+inst_372:
+// rs1_val==3 and imm_val==-2, 
+// opcode: c.andi; op1:x10; immval:-0x2
+TEST_CI_OP( c.andi, x10, 0x2, 0x3, -0x2, x1, 1488, x2)
+
+inst_373:
+// rs1_val==3 and imm_val==3, 
+// opcode: c.andi; op1:x10; immval:0x3
+TEST_CI_OP( c.andi, x10, 0x3, 0x3, 0x3, x1, 1492, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 374*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbeqz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbeqz-01.S
new file mode 100644
index 000000000..a0a21cd3c
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbeqz-01.S
@@ -0,0 +1,490 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.beqz instruction of the RISC-V C extension for the cbeqz covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbeqz)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x10, rs1_val < 0 and imm_val < 0, rs1_val == -4097
+// opcode:c.beqz; op1:x10; op1val:-0x1001; immval:0xac
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1001, 0xac, 1b, x1, 0)
+
+inst_1:
+// rs1==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and imm_val < 0
+// opcode:c.beqz; op1:x14; op1val:0x7fffffff; immval:0x14
+TEST_CBRANCH_OP(c.beqz, x2, x14, 0x7fffffff, 0x14, 1b, x1, 4)
+
+inst_2:
+// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
+// opcode:c.beqz; op1:x8; op1val:-0x40000001; immval:0x20
+TEST_CBRANCH_OP(c.beqz, x2, x8, -0x40000001, 0x20, 3f, x1, 8)
+
+inst_3:
+// rs1==x15, rs1_val == -536870913, 
+// opcode:c.beqz; op1:x15; op1val:-0x20000001; immval:0xac
+TEST_CBRANCH_OP(c.beqz, x2, x15, -0x20000001, 0xac, 1b, x1, 12)
+
+inst_4:
+// rs1==x12, rs1_val == -268435457, 
+// opcode:c.beqz; op1:x12; op1val:-0x10000001; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x12, -0x10000001, 0x12, 3f, x1, 16)
+
+inst_5:
+// rs1==x13, rs1_val == -134217729, 
+// opcode:c.beqz; op1:x13; op1val:-0x8000001; immval:0x7e
+TEST_CBRANCH_OP(c.beqz, x2, x13, -0x8000001, 0x7e, 3f, x1, 20)
+
+inst_6:
+// rs1==x11, rs1_val == -67108865, 
+// opcode:c.beqz; op1:x11; op1val:-0x4000001; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x11, -0x4000001, 0xe, 1b, x1, 24)
+
+inst_7:
+// rs1==x9, rs1_val == -33554433, 
+// opcode:c.beqz; op1:x9; op1val:-0x2000001; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x9, -0x2000001, 0xc, 1b, x1, 28)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode:c.beqz; op1:x10; op1val:-0x1000001; immval:0x20
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x1000001, 0x20, 3f, x1, 32)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode:c.beqz; op1:x10; op1val:-0x800001; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x800001, 0x80, 1b, x1, 36)
+
+inst_10:
+// rs1_val == -4194305, 
+// opcode:c.beqz; op1:x10; op1val:-0x400001; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x400001, 0xe, 1b, x1, 40)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode:c.beqz; op1:x10; op1val:-0x200001; immval:0x40
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x200001, 0x40, 3f, x1, 44)
+
+inst_12:
+// rs1_val == -1048577, 
+// opcode:c.beqz; op1:x10; op1val:-0x100001; immval:0x22
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x100001, 0x22, 1b, x1, 48)
+
+inst_13:
+// rs1_val == -524289, 
+// opcode:c.beqz; op1:x10; op1val:-0x80001; immval:0x82
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80001, 0x82, 1b, x1, 52)
+
+inst_14:
+// rs1_val == -262145, 
+// opcode:c.beqz; op1:x10; op1val:-0x40001; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x40001, 0xc, 3f, x1, 56)
+
+inst_15:
+// rs1_val == -131073, 
+// opcode:c.beqz; op1:x10; op1val:-0x20001; immval:0x6
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x20001, 0x6, 3f, x1, 60)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode:c.beqz; op1:x10; op1val:-0x10001; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x10001, 0x12, 3f, x1, 64)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode:c.beqz; op1:x10; op1val:-0x8001; immval:0x42
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x8001, 0x42, 1b, x1, 68)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode:c.beqz; op1:x10; op1val:-0x4001; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x4001, 0x80, 3f, x1, 72)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode:c.beqz; op1:x10; op1val:-0x2001; immval:0x7e
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2001, 0x7e, 3f, x1, 76)
+
+inst_20:
+// rs1_val == -2049, 
+// opcode:c.beqz; op1:x10; op1val:-0x801; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x801, 0xe, 1b, x1, 80)
+
+inst_21:
+// rs1_val == -1025, 
+// opcode:c.beqz; op1:x10; op1val:-0x401; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x401, 0x80, 1b, x1, 84)
+
+inst_22:
+// rs1_val == -513, 
+// opcode:c.beqz; op1:x10; op1val:-0x201; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x201, 0xc, 3f, x1, 88)
+
+inst_23:
+// rs1_val == -257, 
+// opcode:c.beqz; op1:x10; op1val:-0x101; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x101, 0xa, 1b, x1, 92)
+
+inst_24:
+// rs1_val == -129, 
+// opcode:c.beqz; op1:x10; op1val:-0x81; immval:0x14
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x81, 0x14, 1b, x1, 96)
+
+inst_25:
+// rs1_val == -65, 
+// opcode:c.beqz; op1:x10; op1val:-0x41; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x41, 0xa, 1b, x1, 100)
+
+inst_26:
+// rs1_val == -33, 
+// opcode:c.beqz; op1:x10; op1val:-0x21; immval:0xac
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x21, 0xac, 1b, x1, 104)
+
+inst_27:
+// rs1_val == -17, 
+// opcode:c.beqz; op1:x10; op1val:-0x11; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x11, 0x12, 1b, x1, 108)
+
+inst_28:
+// rs1_val == -9, 
+// opcode:c.beqz; op1:x10; op1val:-0x9; immval:0x20
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x9, 0x20, 3f, x1, 112)
+
+inst_29:
+// rs1_val == -5, 
+// opcode:c.beqz; op1:x10; op1val:-0x5; immval:0x42
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x5, 0x42, 1b, x1, 116)
+
+inst_30:
+// rs1_val == -3, 
+// opcode:c.beqz; op1:x10; op1val:-0x3; immval:0x42
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x3, 0x42, 1b, x1, 120)
+
+inst_31:
+// rs1_val == -2, 
+// opcode:c.beqz; op1:x10; op1val:-0x2; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x2, 0xa, 3f, x1, 124)
+
+inst_32:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode:c.beqz; op1:x10; op1val:-0x80000000; immval:0x6
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x80000000, 0x6, 3f, x1, 128)
+
+inst_33:
+// rs1_val == 1073741824, rs1_val > 0 and imm_val > 0
+// opcode:c.beqz; op1:x10; op1val:0x40000000; immval:0x7e
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
+
+inst_34:
+// rs1_val == 536870912, 
+// opcode:c.beqz; op1:x10; op1val:0x20000000; immval:0x22
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000000, 0x22, 1b, x1, 136)
+
+inst_35:
+// rs1_val == 268435456, 
+// opcode:c.beqz; op1:x10; op1val:0x10000000; immval:0x40
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000000, 0x40, 3f, x1, 140)
+
+inst_36:
+// rs1_val == 134217728, 
+// opcode:c.beqz; op1:x10; op1val:0x8000000; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000000, 0x80, 3f, x1, 144)
+
+inst_37:
+// rs1_val == 67108864, 
+// opcode:c.beqz; op1:x10; op1val:0x4000000; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000000, 0x80, 3f, x1, 148)
+
+inst_38:
+// rs1_val == 33554432, 
+// opcode:c.beqz; op1:x10; op1val:0x2000000; immval:0x22
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000000, 0x22, 1b, x1, 152)
+
+inst_39:
+// rs1_val == 16777216, 
+// opcode:c.beqz; op1:x10; op1val:0x1000000; immval:0x40
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000000, 0x40, 3f, x1, 156)
+
+inst_40:
+// rs1_val == 8388608, 
+// opcode:c.beqz; op1:x10; op1val:0x800000; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800000, 0xe, 3f, x1, 160)
+
+inst_41:
+// rs1_val == 4194304, 
+// opcode:c.beqz; op1:x10; op1val:0x400000; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400000, 0x80, 3f, x1, 164)
+
+inst_42:
+// rs1_val == 2097152, 
+// opcode:c.beqz; op1:x10; op1val:0x200000; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200000, 0xe, 3f, x1, 168)
+
+inst_43:
+// rs1_val == 1048576, 
+// opcode:c.beqz; op1:x10; op1val:0x100000; immval:0x6
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100000, 0x6, 1b, x1, 172)
+
+inst_44:
+// rs1_val == 524288, 
+// opcode:c.beqz; op1:x10; op1val:0x80000; immval:0x82
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80000, 0x82, 1b, x1, 176)
+
+inst_45:
+// rs1_val == 262144, 
+// opcode:c.beqz; op1:x10; op1val:0x40000; immval:0x42
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40000, 0x42, 1b, x1, 180)
+
+inst_46:
+// rs1_val == 131072, 
+// opcode:c.beqz; op1:x10; op1val:0x20000; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20000, 0xc, 1b, x1, 184)
+
+inst_47:
+// rs1_val == 65536, 
+// opcode:c.beqz; op1:x10; op1val:0x10000; immval:0x82
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10000, 0x82, 1b, x1, 188)
+
+inst_48:
+// rs1_val == 32768, 
+// opcode:c.beqz; op1:x10; op1val:0x8000; immval:0x4
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8000, 0x4, 1b, x1, 192)
+
+inst_49:
+// rs1_val == 16384, 
+// opcode:c.beqz; op1:x10; op1val:0x4000; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4000, 0xa, 1b, x1, 196)
+
+inst_50:
+// rs1_val == 8192, 
+// opcode:c.beqz; op1:x10; op1val:0x2000; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2000, 0x80, 1b, x1, 200)
+
+inst_51:
+// rs1_val == 4096, 
+// opcode:c.beqz; op1:x10; op1val:0x1000; immval:0x40
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1000, 0x40, 3f, x1, 204)
+
+inst_52:
+// rs1_val == 2048, 
+// opcode:c.beqz; op1:x10; op1val:0x800; immval:0x20
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x800, 0x20, 3f, x1, 208)
+
+inst_53:
+// rs1_val == 1024, 
+// opcode:c.beqz; op1:x10; op1val:0x400; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x400, 0xc, 3f, x1, 212)
+
+inst_54:
+// rs1_val == 512, 
+// opcode:c.beqz; op1:x10; op1val:0x200; immval:0x10
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x200, 0x10, 1b, x1, 216)
+
+inst_55:
+// rs1_val == 256, 
+// opcode:c.beqz; op1:x10; op1val:0x100; immval:0x7e
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x100, 0x7e, 3f, x1, 220)
+
+inst_56:
+// rs1_val == 128, 
+// opcode:c.beqz; op1:x10; op1val:0x80; immval:0x6
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x80, 0x6, 3f, x1, 224)
+
+inst_57:
+// rs1_val == 64, 
+// opcode:c.beqz; op1:x10; op1val:0x40; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x40, 0xa, 3f, x1, 228)
+
+inst_58:
+// rs1_val == 32, 
+// opcode:c.beqz; op1:x10; op1val:0x20; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x20, 0x12, 1b, x1, 232)
+
+inst_59:
+// rs1_val == 16, 
+// opcode:c.beqz; op1:x10; op1val:0x10; immval:0x4
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x10, 0x4, 1b, x1, 236)
+
+inst_60:
+// rs1_val == 1, 
+// opcode:c.beqz; op1:x10; op1val:0x1; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x1, 0xe, 3f, x1, 240)
+
+inst_61:
+// rs1_val==46341, 
+// opcode:c.beqz; op1:x10; op1val:0xb505; immval:0x10
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb505, 0x10, 1b, x1, 244)
+
+inst_62:
+// rs1_val==-46339, 
+// opcode:c.beqz; op1:x10; op1val:-0xb503; immval:0x82
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb503, 0x82, 1b, x1, 248)
+
+inst_63:
+// rs1_val==1717986919, 
+// opcode:c.beqz; op1:x10; op1val:0x66666667; immval:0x8
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
+
+inst_64:
+// rs1_val==858993460, 
+// opcode:c.beqz; op1:x10; op1val:0x33333334; immval:0x8
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333334, 0x8, 3f, x1, 256)
+
+inst_65:
+// rs1_val==6, 
+// opcode:c.beqz; op1:x10; op1val:0x6; immval:0x6
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x6, 0x6, 1b, x1, 260)
+
+inst_66:
+// rs1_val==-1431655765, 
+// opcode:c.beqz; op1:x10; op1val:-0x55555555; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555555, 0x80, 3f, x1, 264)
+
+inst_67:
+// rs1_val==1431655766, 
+// opcode:c.beqz; op1:x10; op1val:0x55555556; immval:0x14
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555556, 0x14, 1b, x1, 268)
+
+inst_68:
+// rs1_val==4, rs1_val == 4
+// opcode:c.beqz; op1:x10; op1val:0x4; immval:0x82
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x4, 0x82, 1b, x1, 272)
+
+inst_69:
+// rs1_val==46339, 
+// opcode:c.beqz; op1:x10; op1val:0xb503; immval:0x14
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb503, 0x14, 1b, x1, 276)
+
+inst_70:
+// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val > 0
+// opcode:c.beqz; op1:x10; op1val:0x0; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x0, 0xe, 3f, x1, 280)
+
+inst_71:
+// rs1_val==1717986917, 
+// opcode:c.beqz; op1:x10; op1val:0x66666665; immval:0x80
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666665, 0x80, 3f, x1, 284)
+
+inst_72:
+// rs1_val==858993458, 
+// opcode:c.beqz; op1:x10; op1val:0x33333332; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333332, 0xa, 1b, x1, 288)
+
+inst_73:
+// rs1_val==1431655764, 
+// opcode:c.beqz; op1:x10; op1val:0x55555554; immval:0xc
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555554, 0xc, 1b, x1, 292)
+
+inst_74:
+// rs1_val==2, rs1_val == 2
+// opcode:c.beqz; op1:x10; op1val:0x2; immval:0xa
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x2, 0xa, 1b, x1, 296)
+
+inst_75:
+// rs1_val==46340, 
+// opcode:c.beqz; op1:x10; op1val:0xb504; immval:0x8
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0xb504, 0x8, 1b, x1, 300)
+
+inst_76:
+// rs1_val==-46340, 
+// opcode:c.beqz; op1:x10; op1val:-0xb504; immval:0x7e
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0xb504, 0x7e, 3f, x1, 304)
+
+inst_77:
+// rs1_val==1717986918, 
+// opcode:c.beqz; op1:x10; op1val:0x66666666; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x66666666, 0xe, 3f, x1, 308)
+
+inst_78:
+// rs1_val==858993459, 
+// opcode:c.beqz; op1:x10; op1val:0x33333333; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x33333333, 0x12, 3f, x1, 312)
+
+inst_79:
+// rs1_val==5, 
+// opcode:c.beqz; op1:x10; op1val:0x5; immval:0x10
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x5, 0x10, 1b, x1, 316)
+
+inst_80:
+// rs1_val==-1431655766, rs1_val == -1431655766
+// opcode:c.beqz; op1:x10; op1val:-0x55555556; immval:0x40
+TEST_CBRANCH_OP(c.beqz, x2, x10, -0x55555556, 0x40, 3f, x1, 320)
+
+inst_81:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode:c.beqz; op1:x10; op1val:0x55555555; immval:0x12
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x55555555, 0x12, 1b, x1, 324)
+
+inst_82:
+// rs1_val == 8, 
+// opcode:c.beqz; op1:x10; op1val:0x8; immval:0xe
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x8, 0xe, 1b, x1, 328)
+
+inst_83:
+// rs1_val==3, 
+// opcode:c.beqz; op1:x10; op1val:0x3; immval:0x4
+TEST_CBRANCH_OP(c.beqz, x2, x10, 0x3, 0x4, 1b, x1, 332)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 84*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S
new file mode 100644
index 000000000..b59b696f5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cbnez-01.S
@@ -0,0 +1,490 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.bnez instruction of the RISC-V C extension for the cbnez covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cbnez)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x11, rs1_val < 0 and imm_val < 0, rs1_val == -524289
+// opcode: c.bnez; op1:x11; op1val:-0x80001; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x11, -0x80001, 0x4, 1b, x1, 0)
+
+inst_1:
+// rs1==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: c.bnez; op1:x10; op1val:0x7fffffff; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x7fffffff, 0x7e, 3f, x1, 4)
+
+inst_2:
+// rs1==x8, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0
+// opcode: c.bnez; op1:x8; op1val:-0x40000001; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x8, -0x40000001, 0xaa, 3f, x1, 8)
+
+inst_3:
+// rs1==x12, rs1_val == -536870913, 
+// opcode: c.bnez; op1:x12; op1val:-0x20000001; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x12, -0x20000001, 0xe, 1b, x1, 12)
+
+inst_4:
+// rs1==x15, rs1_val == -268435457, 
+// opcode: c.bnez; op1:x15; op1val:-0x10000001; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x15, -0x10000001, 0x8, 3f, x1, 16)
+
+inst_5:
+// rs1==x13, rs1_val == -134217729, 
+// opcode: c.bnez; op1:x13; op1val:-0x8000001; immval:0xa
+TEST_CBRANCH_OP(c.bnez, x2, x13, -0x8000001, 0xa, 1b, x1, 20)
+
+inst_6:
+// rs1==x9, rs1_val == -67108865, 
+// opcode: c.bnez; op1:x9; op1val:-0x4000001; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x9, -0x4000001, 0xe, 1b, x1, 24)
+
+inst_7:
+// rs1==x14, rs1_val == -33554433, 
+// opcode: c.bnez; op1:x14; op1val:-0x2000001; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x14, -0x2000001, 0x4, 3f, x1, 28)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode: c.bnez; op1:x10; op1val:-0x1000001; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1000001, 0xaa, 3f, x1, 32)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode: c.bnez; op1:x10; op1val:-0x800001; immval:0xc
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x800001, 0xc, 3f, x1, 36)
+
+inst_10:
+// rs1_val == -4194305, 
+// opcode: c.bnez; op1:x10; op1val:-0x400001; immval:0x6
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x400001, 0x6, 1b, x1, 40)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode: c.bnez; op1:x10; op1val:-0x200001; immval:0x40
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x200001, 0x40, 3f, x1, 44)
+
+inst_12:
+// rs1_val == -1048577, 
+// opcode: c.bnez; op1:x10; op1val:-0x100001; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x100001, 0xaa, 3f, x1, 48)
+
+inst_13:
+// rs1_val == -262145, 
+// opcode: c.bnez; op1:x10; op1val:-0x40001; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x40001, 0xe, 3f, x1, 52)
+
+inst_14:
+// rs1_val == -131073, 
+// opcode: c.bnez; op1:x10; op1val:-0x20001; immval:0x20
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x20001, 0x20, 3f, x1, 56)
+
+inst_15:
+// rs1_val == -65537, 
+// opcode: c.bnez; op1:x10; op1val:-0x10001; immval:0x40
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x10001, 0x40, 3f, x1, 60)
+
+inst_16:
+// rs1_val == -32769, 
+// opcode: c.bnez; op1:x10; op1val:-0x8001; immval:0xa
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x8001, 0xa, 1b, x1, 64)
+
+inst_17:
+// rs1_val == -16385, 
+// opcode: c.bnez; op1:x10; op1val:-0x4001; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x4001, 0x12, 3f, x1, 68)
+
+inst_18:
+// rs1_val == -8193, 
+// opcode: c.bnez; op1:x10; op1val:-0x2001; immval:0xc
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2001, 0xc, 1b, x1, 72)
+
+inst_19:
+// rs1_val == -4097, 
+// opcode: c.bnez; op1:x10; op1val:-0x1001; immval:0x42
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x1001, 0x42, 1b, x1, 76)
+
+inst_20:
+// rs1_val == -2049, 
+// opcode: c.bnez; op1:x10; op1val:-0x801; immval:0x80
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x801, 0x80, 3f, x1, 80)
+
+inst_21:
+// rs1_val == -1025, 
+// opcode: c.bnez; op1:x10; op1val:-0x401; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x401, 0x12, 3f, x1, 84)
+
+inst_22:
+// rs1_val == -513, 
+// opcode: c.bnez; op1:x10; op1val:-0x201; immval:0x82
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x201, 0x82, 1b, x1, 88)
+
+inst_23:
+// rs1_val == -257, 
+// opcode: c.bnez; op1:x10; op1val:-0x101; immval:0x80
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x101, 0x80, 1b, x1, 92)
+
+inst_24:
+// rs1_val == -129, 
+// opcode: c.bnez; op1:x10; op1val:-0x81; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x81, 0xe, 3f, x1, 96)
+
+inst_25:
+// rs1_val == -65, 
+// opcode: c.bnez; op1:x10; op1val:-0x41; immval:0x10
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x41, 0x10, 3f, x1, 100)
+
+inst_26:
+// rs1_val == -33, 
+// opcode: c.bnez; op1:x10; op1val:-0x21; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x21, 0x7e, 3f, x1, 104)
+
+inst_27:
+// rs1_val == -17, 
+// opcode: c.bnez; op1:x10; op1val:-0x11; immval:0x20
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x11, 0x20, 3f, x1, 108)
+
+inst_28:
+// rs1_val == -9, 
+// opcode: c.bnez; op1:x10; op1val:-0x9; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x9, 0x4, 1b, x1, 112)
+
+inst_29:
+// rs1_val == -5, 
+// opcode: c.bnez; op1:x10; op1val:-0x5; immval:0x80
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x5, 0x80, 1b, x1, 116)
+
+inst_30:
+// rs1_val == -3, 
+// opcode: c.bnez; op1:x10; op1val:-0x3; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x3, 0xaa, 3f, x1, 120)
+
+inst_31:
+// rs1_val == -2, 
+// opcode: c.bnez; op1:x10; op1val:-0x2; immval:0x10
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x2, 0x10, 1b, x1, 124)
+
+inst_32:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: c.bnez; op1:x10; op1val:-0x80000000; immval:0x80
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x80000000, 0x80, 1b, x1, 128)
+
+inst_33:
+// rs1_val == 1073741824, 
+// opcode: c.bnez; op1:x10; op1val:0x40000000; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000000, 0x7e, 3f, x1, 132)
+
+inst_34:
+// rs1_val == 536870912, rs1_val > 0 and imm_val < 0
+// opcode: c.bnez; op1:x10; op1val:0x20000000; immval:0xc
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000000, 0xc, 1b, x1, 136)
+
+inst_35:
+// rs1_val == 268435456, 
+// opcode: c.bnez; op1:x10; op1val:0x10000000; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000000, 0x7e, 3f, x1, 140)
+
+inst_36:
+// rs1_val == 134217728, 
+// opcode: c.bnez; op1:x10; op1val:0x8000000; immval:0x82
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000000, 0x82, 1b, x1, 144)
+
+inst_37:
+// rs1_val == 67108864, 
+// opcode: c.bnez; op1:x10; op1val:0x4000000; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000000, 0xaa, 3f, x1, 148)
+
+inst_38:
+// rs1_val == 33554432, 
+// opcode: c.bnez; op1:x10; op1val:0x2000000; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000000, 0xe, 1b, x1, 152)
+
+inst_39:
+// rs1_val == 16777216, 
+// opcode: c.bnez; op1:x10; op1val:0x1000000; immval:0xc
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000000, 0xc, 3f, x1, 156)
+
+inst_40:
+// rs1_val == 8388608, 
+// opcode: c.bnez; op1:x10; op1val:0x800000; immval:0x20
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800000, 0x20, 3f, x1, 160)
+
+inst_41:
+// rs1_val == 4194304, 
+// opcode: c.bnez; op1:x10; op1val:0x400000; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400000, 0x8, 3f, x1, 164)
+
+inst_42:
+// rs1_val == 2097152, 
+// opcode: c.bnez; op1:x10; op1val:0x200000; immval:0x22
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200000, 0x22, 1b, x1, 168)
+
+inst_43:
+// rs1_val == 1048576, 
+// opcode: c.bnez; op1:x10; op1val:0x100000; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100000, 0x4, 1b, x1, 172)
+
+inst_44:
+// rs1_val == 524288, 
+// opcode: c.bnez; op1:x10; op1val:0x80000; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80000, 0x8, 1b, x1, 176)
+
+inst_45:
+// rs1_val == 262144, 
+// opcode: c.bnez; op1:x10; op1val:0x40000; immval:0x6
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40000, 0x6, 1b, x1, 180)
+
+inst_46:
+// rs1_val == 131072, 
+// opcode: c.bnez; op1:x10; op1val:0x20000; immval:0x6
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20000, 0x6, 1b, x1, 184)
+
+inst_47:
+// rs1_val == 65536, 
+// opcode: c.bnez; op1:x10; op1val:0x10000; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10000, 0x7e, 3f, x1, 188)
+
+inst_48:
+// rs1_val == 32768, 
+// opcode: c.bnez; op1:x10; op1val:0x8000; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8000, 0x7e, 3f, x1, 192)
+
+inst_49:
+// rs1_val == 16384, 
+// opcode: c.bnez; op1:x10; op1val:0x4000; immval:0xac
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4000, 0xac, 1b, x1, 196)
+
+inst_50:
+// rs1_val == 8192, 
+// opcode: c.bnez; op1:x10; op1val:0x2000; immval:0x10
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2000, 0x10, 3f, x1, 200)
+
+inst_51:
+// rs1_val == 4096, 
+// opcode: c.bnez; op1:x10; op1val:0x1000; immval:0xc
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1000, 0xc, 1b, x1, 204)
+
+inst_52:
+// rs1_val == 2048, 
+// opcode: c.bnez; op1:x10; op1val:0x800; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x800, 0x7e, 3f, x1, 208)
+
+inst_53:
+// rs1_val == 1024, 
+// opcode: c.bnez; op1:x10; op1val:0x400; immval:0xa
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x400, 0xa, 1b, x1, 212)
+
+inst_54:
+// rs1_val == 512, 
+// opcode: c.bnez; op1:x10; op1val:0x200; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x200, 0x12, 3f, x1, 216)
+
+inst_55:
+// rs1_val == 256, 
+// opcode: c.bnez; op1:x10; op1val:0x100; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x100, 0xe, 3f, x1, 220)
+
+inst_56:
+// rs1_val == 128, 
+// opcode: c.bnez; op1:x10; op1val:0x80; immval:0xe
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x80, 0xe, 1b, x1, 224)
+
+inst_57:
+// rs1_val == 64, 
+// opcode: c.bnez; op1:x10; op1val:0x40; immval:0x22
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x40, 0x22, 1b, x1, 228)
+
+inst_58:
+// rs1_val == 32, 
+// opcode: c.bnez; op1:x10; op1val:0x20; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x20, 0x4, 1b, x1, 232)
+
+inst_59:
+// rs1_val == 16, 
+// opcode: c.bnez; op1:x10; op1val:0x10; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x10, 0x8, 3f, x1, 236)
+
+inst_60:
+// rs1_val == 1, 
+// opcode: c.bnez; op1:x10; op1val:0x1; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x1, 0x4, 3f, x1, 240)
+
+inst_61:
+// rs1_val==46341, 
+// opcode: c.bnez; op1:x10; op1val:0xb505; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb505, 0x12, 1b, x1, 244)
+
+inst_62:
+// rs1_val==-46339, 
+// opcode: c.bnez; op1:x10; op1val:-0xb503; immval:0x22
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb503, 0x22, 1b, x1, 248)
+
+inst_63:
+// rs1_val==1717986919, 
+// opcode: c.bnez; op1:x10; op1val:0x66666667; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666667, 0x8, 3f, x1, 252)
+
+inst_64:
+// rs1_val==858993460, 
+// opcode: c.bnez; op1:x10; op1val:0x33333334; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333334, 0x4, 1b, x1, 256)
+
+inst_65:
+// rs1_val==6, 
+// opcode: c.bnez; op1:x10; op1val:0x6; immval:0x6
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x6, 0x6, 1b, x1, 260)
+
+inst_66:
+// rs1_val==-1431655765, 
+// opcode: c.bnez; op1:x10; op1val:-0x55555555; immval:0x20
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555555, 0x20, 3f, x1, 264)
+
+inst_67:
+// rs1_val==1431655766, 
+// opcode: c.bnez; op1:x10; op1val:0x55555556; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555556, 0x12, 3f, x1, 268)
+
+inst_68:
+// rs1_val==4, rs1_val == 4
+// opcode: c.bnez; op1:x10; op1val:0x4; immval:0xac
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x4, 0xac, 1b, x1, 272)
+
+inst_69:
+// rs1_val==46339, 
+// opcode: c.bnez; op1:x10; op1val:0xb503; immval:0x7e
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb503, 0x7e, 3f, x1, 276)
+
+inst_70:
+// rs1_val==0, rs1_val == 0, rs1_val == 0 and imm_val < 0
+// opcode: c.bnez; op1:x10; op1val:0x0; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x0, 0x12, 1b, x1, 280)
+
+inst_71:
+// rs1_val==1717986917, 
+// opcode: c.bnez; op1:x10; op1val:0x66666665; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666665, 0x8, 3f, x1, 284)
+
+inst_72:
+// rs1_val==858993458, 
+// opcode: c.bnez; op1:x10; op1val:0x33333332; immval:0x80
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333332, 0x80, 1b, x1, 288)
+
+inst_73:
+// rs1_val==1431655764, 
+// opcode: c.bnez; op1:x10; op1val:0x55555554; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555554, 0x12, 3f, x1, 292)
+
+inst_74:
+// rs1_val==2, rs1_val == 2
+// opcode: c.bnez; op1:x10; op1val:0x2; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x2, 0x12, 1b, x1, 296)
+
+inst_75:
+// rs1_val==46340, 
+// opcode: c.bnez; op1:x10; op1val:0xb504; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0xb504, 0xaa, 3f, x1, 300)
+
+inst_76:
+// rs1_val==-46340, 
+// opcode: c.bnez; op1:x10; op1val:-0xb504; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0xb504, 0x4, 1b, x1, 304)
+
+inst_77:
+// rs1_val==1717986918, 
+// opcode: c.bnez; op1:x10; op1val:0x66666666; immval:0x8
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x66666666, 0x8, 3f, x1, 308)
+
+inst_78:
+// rs1_val==858993459, 
+// opcode: c.bnez; op1:x10; op1val:0x33333333; immval:0x22
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x33333333, 0x22, 1b, x1, 312)
+
+inst_79:
+// rs1_val==5, 
+// opcode: c.bnez; op1:x10; op1val:0x5; immval:0x12
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x5, 0x12, 1b, x1, 316)
+
+inst_80:
+// rs1_val==-1431655766, rs1_val == -1431655766
+// opcode: c.bnez; op1:x10; op1val:-0x55555556; immval:0xac
+TEST_CBRANCH_OP(c.bnez, x2, x10, -0x55555556, 0xac, 1b, x1, 320)
+
+inst_81:
+// rs1_val==1431655765, rs1_val == 1431655765
+// opcode: c.bnez; op1:x10; op1val:0x55555555; immval:0x4
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x55555555, 0x4, 1b, x1, 324)
+
+inst_82:
+// rs1_val == 8, 
+// opcode: c.bnez; op1:x10; op1val:0x8; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x8, 0xaa, 3f, x1, 328)
+
+inst_83:
+// rs1_val==3, 
+// opcode: c.bnez; op1:x10; op1val:0x3; immval:0xaa
+TEST_CBRANCH_OP(c.bnez, x2, x10, 0x3, 0xaa, 3f, x1, 332)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 84*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cj-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cj-01.S
new file mode 100644
index 000000000..4797626b6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cj-01.S
@@ -0,0 +1,155 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.j instruction of the RISC-V C extension for the cj covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cj)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// imm_val < 0, imm_val == -66
+// opcode:c.j; immval:0x42
+TEST_CJ_OP(c.j, x2, 0x42, 1b, x1, 0)
+
+inst_1:
+// imm_val == -1026, 
+// opcode:c.j; immval:0x402
+TEST_CJ_OP(c.j, x2, 0x402, 1b, x1, 4)
+
+inst_2:
+// imm_val == -514, 
+// opcode:c.j; immval:0x202
+TEST_CJ_OP(c.j, x2, 0x202, 1b, x1, 8)
+
+inst_3:
+// imm_val == -258, 
+// opcode:c.j; immval:0x102
+TEST_CJ_OP(c.j, x2, 0x102, 1b, x1, 12)
+
+inst_4:
+// imm_val == -130, 
+// opcode:c.j; immval:0x82
+TEST_CJ_OP(c.j, x2, 0x82, 1b, x1, 16)
+
+inst_5:
+// imm_val == -34, 
+// opcode:c.j; immval:0x22
+TEST_CJ_OP(c.j, x2, 0x22, 1b, x1, 20)
+
+inst_6:
+// imm_val == -18, 
+// opcode:c.j; immval:0x12
+TEST_CJ_OP(c.j, x2, 0x12, 1b, x1, 24)
+
+inst_7:
+// imm_val == -10, 
+// opcode:c.j; immval:0xa
+TEST_CJ_OP(c.j, x2, 0xa, 1b, x1, 28)
+
+inst_8:
+// imm_val == 1024, imm_val > 0
+// opcode:c.j; immval:0x400
+TEST_CJ_OP(c.j, x2, 0x400, 3f, x1, 32)
+
+inst_9:
+// imm_val == 512, 
+// opcode:c.j; immval:0x200
+TEST_CJ_OP(c.j, x2, 0x200, 3f, x1, 36)
+
+inst_10:
+// imm_val == 1364, 
+// opcode:c.j; immval:0x554
+TEST_CJ_OP(c.j, x2, 0x554, 3f, x1, 40)
+
+inst_11:
+// imm_val == -1366, 
+// opcode:c.j; immval:0x556
+TEST_CJ_OP(c.j, x2, 0x556, 1b, x1, 44)
+
+inst_12:
+// imm_val == 256, 
+// opcode:c.j; immval:0x100
+TEST_CJ_OP(c.j, x2, 0x100, 3f, x1, 48)
+
+inst_13:
+// imm_val == 128, 
+// opcode:c.j; immval:0x80
+TEST_CJ_OP(c.j, x2, 0x80, 3f, x1, 52)
+
+inst_14:
+// imm_val == 64, 
+// opcode:c.j; immval:0x40
+TEST_CJ_OP(c.j, x2, 0x40, 3f, x1, 56)
+
+inst_15:
+// imm_val == 32, 
+// opcode:c.j; immval:0x20
+TEST_CJ_OP(c.j, x2, 0x20, 3f, x1, 60)
+
+inst_16:
+// imm_val == 16, 
+// opcode:c.j; immval:0x10
+TEST_CJ_OP(c.j, x2, 0x10, 3f, x1, 64)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjal-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjal-01.S
new file mode 100644
index 000000000..a55b5d7c0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjal-01.S
@@ -0,0 +1,160 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.jal instruction of the RISC-V C extension for the cjal covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjal)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// imm_val < 0, 
+// opcode:c.jal; immval:0x10
+TEST_CJAL_OP(c.jal, x3, 0x10, 1b, x2, 0)
+
+inst_1:
+// imm_val == -1026, 
+// opcode:c.jal; immval:0x402
+TEST_CJAL_OP(c.jal, x3, 0x402, 1b, x2, 4)
+
+inst_2:
+// imm_val == -514, 
+// opcode:c.jal; immval:0x202
+TEST_CJAL_OP(c.jal, x3, 0x202, 1b, x2, 8)
+
+inst_3:
+// imm_val == -258, 
+// opcode:c.jal; immval:0x102
+TEST_CJAL_OP(c.jal, x3, 0x102, 1b, x2, 12)
+
+inst_4:
+// imm_val == -130, 
+// opcode:c.jal; immval:0x82
+TEST_CJAL_OP(c.jal, x3, 0x82, 1b, x2, 16)
+
+inst_5:
+// imm_val == -66, 
+// opcode:c.jal; immval:0x42
+TEST_CJAL_OP(c.jal, x3, 0x42, 1b, x2, 20)
+
+inst_6:
+// imm_val == -34, 
+// opcode:c.jal; immval:0x22
+TEST_CJAL_OP(c.jal, x3, 0x22, 1b, x2, 24)
+
+inst_7:
+// imm_val == -18, 
+// opcode:c.jal; immval:0x12
+TEST_CJAL_OP(c.jal, x3, 0x12, 1b, x2, 28)
+
+inst_8:
+// imm_val == -10, 
+// opcode:c.jal; immval:0xa
+TEST_CJAL_OP(c.jal, x3, 0xa, 1b, x2, 32)
+
+inst_9:
+// imm_val == 1024, imm_val > 0
+// opcode:c.jal; immval:0x400
+TEST_CJAL_OP(c.jal, x3, 0x400, 3f, x2, 36)
+
+inst_10:
+// imm_val == 512, 
+// opcode:c.jal; immval:0x200
+TEST_CJAL_OP(c.jal, x3, 0x200, 3f, x2, 40)
+
+inst_11:
+// imm_val == 1364, 
+// opcode:c.jal; immval:0x554
+TEST_CJAL_OP(c.jal, x3, 0x554, 3f, x2, 44)
+
+inst_12:
+// imm_val == -1366, 
+// opcode:c.jal; immval:0x556
+TEST_CJAL_OP(c.jal, x3, 0x556, 1b, x2, 48)
+
+inst_13:
+// imm_val == 256, 
+// opcode:c.jal; immval:0x100
+TEST_CJAL_OP(c.jal, x3, 0x100, 3f, x2, 52)
+
+inst_14:
+// imm_val == 128, 
+// opcode:c.jal; immval:0x80
+TEST_CJAL_OP(c.jal, x3, 0x80, 3f, x2, 56)
+
+inst_15:
+// imm_val == 64, 
+// opcode:c.jal; immval:0x40
+TEST_CJAL_OP(c.jal, x3, 0x40, 3f, x2, 60)
+
+inst_16:
+// imm_val == 32, 
+// opcode:c.jal; immval:0x20
+TEST_CJAL_OP(c.jal, x3, 0x20, 3f, x2, 64)
+
+inst_17:
+// imm_val == 16, 
+// opcode:c.jal; immval:0x10
+TEST_CJAL_OP(c.jal, x3, 0x10, 3f, x2, 68)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjalr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjalr-01.S
new file mode 100644
index 000000000..9940ec9eb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjalr-01.S
@@ -0,0 +1,150 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.jalr instruction of the RISC-V C extension for the cjalr covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjalr)
+
+RVTEST_SIGBASE( x10,signature_x10_1)
+
+inst_0:
+// rs1==x6, 
+// opcode:c.jalr; op1:x6
+TEST_CJALR_OP(x11, x6, x10, 0)
+
+inst_1:
+// rs1==x4, 
+// opcode:c.jalr; op1:x4
+TEST_CJALR_OP(x11, x4, x10, 4)
+
+inst_2:
+// rs1==x3, 
+// opcode:c.jalr; op1:x3
+TEST_CJALR_OP(x11, x3, x10, 8)
+
+inst_3:
+// rs1==x1, 
+// opcode:c.jalr; op1:x1
+TEST_CJALR_OP(x11, x1, x10, 12)
+
+inst_4:
+// rs1==x12, 
+// opcode:c.jalr; op1:x12
+TEST_CJALR_OP(x11, x12, x10, 16)
+
+inst_5:
+// rs1==x2, 
+// opcode:c.jalr; op1:x2
+TEST_CJALR_OP(x11, x2, x10, 20)
+
+inst_6:
+// rs1==x8, 
+// opcode:c.jalr; op1:x8
+TEST_CJALR_OP(x11, x8, x10, 24)
+
+inst_7:
+// rs1==x7, 
+// opcode:c.jalr; op1:x7
+TEST_CJALR_OP(x11, x7, x10, 28)
+
+inst_8:
+// rs1==x15, 
+// opcode:c.jalr; op1:x15
+TEST_CJALR_OP(x11, x15, x10, 32)
+
+inst_9:
+// rs1==x5, 
+// opcode:c.jalr; op1:x5
+TEST_CJALR_OP(x11, x5, x10, 36)
+
+inst_10:
+// rs1==x9, 
+// opcode:c.jalr; op1:x9
+TEST_CJALR_OP(x11, x9, x10, 40)
+
+inst_11:
+// rs1==x14, 
+// opcode:c.jalr; op1:x14
+TEST_CJALR_OP(x3, x14, x10, 44)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_12:
+// rs1==x11, 
+// opcode:c.jalr; op1:x11
+TEST_CJALR_OP(x3, x11, x2, 0)
+
+inst_13:
+// rs1==x13, 
+// opcode:c.jalr; op1:x13
+TEST_CJALR_OP(x3, x13, x2, 4)
+
+inst_14:
+// rs1==x10, 
+// opcode:c.jalr; op1:x10
+TEST_CJALR_OP(x3, x10, x2, 8)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x10_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_1:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 3*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjr-01.S
new file mode 100644
index 000000000..9a6186778
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cjr-01.S
@@ -0,0 +1,150 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.jr instruction of the RISC-V C extension for the cjr covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cjr)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x6, 
+// opcode: c.jr; op1:x6
+TEST_CJR_OP(x7, x6, x1, 0)
+
+inst_1:
+// rs1==x15, 
+// opcode: c.jr; op1:x15
+TEST_CJR_OP(x7, x15, x1, 4)
+
+inst_2:
+// rs1==x14, 
+// opcode: c.jr; op1:x14
+TEST_CJR_OP(x7, x14, x1, 8)
+
+inst_3:
+// rs1==x13, 
+// opcode: c.jr; op1:x13
+TEST_CJR_OP(x7, x13, x1, 12)
+
+inst_4:
+// rs1==x3, 
+// opcode: c.jr; op1:x3
+TEST_CJR_OP(x7, x3, x1, 16)
+
+inst_5:
+// rs1==x8, 
+// opcode: c.jr; op1:x8
+TEST_CJR_OP(x7, x8, x1, 20)
+
+inst_6:
+// rs1==x2, 
+// opcode: c.jr; op1:x2
+TEST_CJR_OP(x7, x2, x1, 24)
+
+inst_7:
+// rs1==x4, 
+// opcode: c.jr; op1:x4
+TEST_CJR_OP(x7, x4, x1, 28)
+
+inst_8:
+// rs1==x12, 
+// opcode: c.jr; op1:x12
+TEST_CJR_OP(x7, x12, x1, 32)
+
+inst_9:
+// rs1==x5, 
+// opcode: c.jr; op1:x5
+TEST_CJR_OP(x7, x5, x1, 36)
+
+inst_10:
+// rs1==x7, 
+// opcode: c.jr; op1:x7
+TEST_CJR_OP(x3, x7, x1, 40)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_11:
+// rs1==x9, 
+// opcode: c.jr; op1:x9
+TEST_CJR_OP(x3, x9, x2, 0)
+
+inst_12:
+// rs1==x1, 
+// opcode: c.jr; op1:x1
+TEST_CJR_OP(x3, x1, x2, 4)
+
+inst_13:
+// rs1==x11, 
+// opcode: c.jr; op1:x11
+TEST_CJR_OP(x3, x11, x2, 8)
+
+inst_14:
+// rs1==x10, 
+// opcode: c.jr; op1:x10
+TEST_CJR_OP(x3, x10, x2, 12)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 11*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 4*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S
new file mode 100644
index 000000000..15653ea5e
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S
@@ -0,0 +1,160 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.li instruction of the RISC-V C extension for the cli covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cli)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rd==x15, imm_val == (-2**(6-1)), imm_val == -32
+// opcode:c.li; dest:x15; immval:-0x20
+TEST_CASE(x7, x15, -0x20, x4, 0, c.li x15, -0x20;)
+
+inst_1:
+// rd==x8, imm_val == 31, imm_val == (2**(6-1)-1)
+// opcode:c.li; dest:x8; immval:0x1f
+TEST_CASE(x7, x8, 0x1f, x4, 4, c.li x8, 0x1f;)
+
+inst_2:
+// rd==x13, imm_val == -17, 
+// opcode:c.li; dest:x13; immval:-0x11
+TEST_CASE(x7, x13, -0x11, x4, 8, c.li x13, -0x11;)
+
+inst_3:
+// rd==x6, imm_val == -9, 
+// opcode:c.li; dest:x6; immval:-0x9
+TEST_CASE(x7, x6, -0x9, x4, 12, c.li x6, -0x9;)
+
+inst_4:
+// rd==x2, imm_val == -5, 
+// opcode:c.li; dest:x2; immval:-0x5
+TEST_CASE(x7, x2, -0x5, x4, 16, c.li x2, -0x5;)
+
+inst_5:
+// rd==x12, imm_val == -3, 
+// opcode:c.li; dest:x12; immval:-0x3
+TEST_CASE(x7, x12, -0x3, x4, 20, c.li x12, -0x3;)
+
+inst_6:
+// rd==x1, imm_val == -2, 
+// opcode:c.li; dest:x1; immval:-0x2
+TEST_CASE(x7, x1, -0x2, x4, 24, c.li x1, -0x2;)
+
+inst_7:
+// rd==x14, imm_val == 16, 
+// opcode:c.li; dest:x14; immval:0x10
+TEST_CASE(x7, x14, 0x10, x4, 28, c.li x14, 0x10;)
+
+inst_8:
+// rd==x3, imm_val == 0, 
+// opcode:c.li; dest:x3; immval:0x0
+TEST_CASE(x7, x3, 0x0, x4, 32, c.li x3, 0x0;)
+
+inst_9:
+// rd==x5, imm_val == 8, 
+// opcode:c.li; dest:x5; immval:0x8
+TEST_CASE(x7, x5, 0x8, x4, 36, c.li x5, 0x8;)
+
+inst_10:
+// rd==x10, imm_val == 4, 
+// opcode:c.li; dest:x10; immval:0x4
+TEST_CASE(x7, x10, 0x4, x4, 40, c.li x10, 0x4;)
+
+inst_11:
+// rd==x0, imm_val == 2, 
+// opcode:c.li; dest:x0; immval:0x2
+TEST_CASE(x2, x0, 0, x4, 44, c.li x0, 0x2;)
+
+inst_12:
+// rd==x11, imm_val == 1, 
+// opcode:c.li; dest:x11; immval:0x1
+TEST_CASE(x2, x11, 0x1, x4, 48, c.li x11, 0x1;)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_13:
+// rd==x7, imm_val == -22, 
+// opcode:c.li; dest:x7; immval:-0x16
+TEST_CASE(x2, x7, -0x16, x1, 0, c.li x7, -0x16;)
+
+inst_14:
+// rd==x4, imm_val == 21, 
+// opcode:c.li; dest:x4; immval:0x15
+TEST_CASE(x2, x4, 0x15, x1, 4, c.li x4, 0x15;)
+
+inst_15:
+// rd==x9, 
+// opcode:c.li; dest:x9; immval:0x0
+TEST_CASE(x2, x9, 0x0, x1, 8, c.li x9, 0x0;)
+
+inst_16:
+// imm_val == 2, 
+// opcode:c.li; dest:x10; immval:0x2
+TEST_CASE(x2, x10, 0x2, x1, 12, c.li x10, 0x2;)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 4*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S
new file mode 100644
index 000000000..79746a15b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clui-01.S
@@ -0,0 +1,150 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.lui instruction of the RISC-V C extension for the clui covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clui)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rd==x8, rs1_val < 0 and imm_val < 32 and imm_val !=0 , imm_val == 4
+// opcode:c.lui; op1:x8; dest:x8 op1val:-0x1000001; immval:0x4
+TEST_CI_OP( c.lui, x8, 0x4000, -0x1000001, 0x4, x2, 0, x5)
+
+inst_1:
+// rd==x10, imm_val == 31, 
+// opcode:c.lui; op1:x10; dest:x10 op1val:-0x4; immval:0x1f
+TEST_CI_OP( c.lui, x10, 0x1f000, -0x4, 0x1f, x2, 4, x5)
+
+inst_2:
+// rd==x6, imm_val == 47, rs1_val > 0 and imm_val > 32
+// opcode:c.lui; op1:x6; dest:x6 op1val:0x4000; immval:0xfffef
+TEST_CI_OP( c.lui, x6, -0x11000, 0x4000, 0xfffef, x2, 8, x5)
+
+inst_3:
+// rd==x9, imm_val == 55, rs1_val < 0 and imm_val > 32
+// opcode:c.lui; op1:x9; dest:x9 op1val:-0x3; immval:0xffff7
+TEST_CI_OP( c.lui, x9, -0x9000, -0x3, 0xffff7, x2, 12, x5)
+
+inst_4:
+// rd==x15, imm_val == 59, 
+// opcode:c.lui; op1:x15; dest:x15 op1val:0x4; immval:0xffffb
+TEST_CI_OP( c.lui, x15, -0x5000, 0x4, 0xffffb, x2, 16, x5)
+
+inst_5:
+// rd==x1, imm_val == 61, 
+// opcode:c.lui; op1:x1; dest:x1 op1val:-0x20000001; immval:0xffffd
+TEST_CI_OP( c.lui, x1, -0x3000, -0x20000001, 0xffffd, x2, 20, x5)
+
+inst_6:
+// rd==x0, imm_val == 62, 
+// opcode:c.lui; op1:x0; dest:x0 op1val:-0x20000001; immval:0xffffe
+TEST_CI_OP( c.lui, x0, 0, -0x20000001, 0xffffe, x2, 24, x5)
+
+inst_7:
+// rd==x7, imm_val == 32, 
+// opcode:c.lui; op1:x7; dest:x7 op1val:0x4000; immval:0xfffe0
+TEST_CI_OP( c.lui, x7, -0x20000, 0x4000, 0xfffe0, x2, 28, x5)
+
+inst_8:
+// rd==x3, rs1_val > 0 and imm_val < 32 and imm_val !=0 , 
+// opcode:c.lui; op1:x3; dest:x3 op1val:0x10; immval:0xc
+TEST_CI_OP( c.lui, x3, 0xc000, 0x10, 0xc, x2, 32, x5)
+
+inst_9:
+// rd==x4, imm_val == 16, 
+// opcode:c.lui; op1:x4; dest:x4 op1val:0x7fffffff; immval:0x10
+TEST_CI_OP( c.lui, x4, 0x10000, 0x7fffffff, 0x10, x2, 36, x5)
+
+inst_10:
+// rd==x11, imm_val == 8, 
+// opcode:c.lui; op1:x11; dest:x11 op1val:-0x20001; immval:0x8
+TEST_CI_OP( c.lui, x11, 0x8000, -0x20001, 0x8, x2, 40, x5)
+
+inst_11:
+// rd==x12, imm_val == 2, 
+// opcode:c.lui; op1:x12; dest:x12 op1val:0x200000; immval:0x2
+TEST_CI_OP( c.lui, x12, 0x2000, 0x200000, 0x2, x2, 44, x5)
+
+inst_12:
+// rd==x13, imm_val == 1, 
+// opcode:c.lui; op1:x13; dest:x13 op1val:-0x2001; immval:0x1
+TEST_CI_OP( c.lui, x13, 0x1000, -0x2001, 0x1, x2, 48, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_13:
+// rd==x14, imm_val == 42, 
+// opcode:c.lui; op1:x14; dest:x14 op1val:0x400000; immval:0xfffea
+TEST_CI_OP( c.lui, x14, -0x16000, 0x400000, 0xfffea, x1, 0, x3)
+
+inst_14:
+// rd==x5, imm_val == 21, 
+// opcode:c.lui; op1:x5; dest:x5 op1val:-0x10001; immval:0x15
+TEST_CI_OP( c.lui, x5, 0x15000, -0x10001, 0x15, x1, 4, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 2*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clw-01.S
new file mode 100644
index 000000000..246cbb8ac
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clw-01.S
@@ -0,0 +1,135 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.lw instruction of the RISC-V C extension for the clw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clw)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 == rd, rd==x8, rs1==x8, imm_val == 0, 
+// opcode: c.lw; op1:x8; dest:x8; immval:0x0
+TEST_LOAD(x1,x2,0,x8,x8,0x0,0,c.lw,0)
+
+inst_1:
+// rs1 != rd, rd==x14, rs1==x12, imm_val == 60, imm_val > 0
+// opcode: c.lw; op1:x12; dest:x14; immval:0x3c
+TEST_LOAD(x1,x2,0,x12,x14,0x3c,4,c.lw,0)
+
+inst_2:
+// rd==x15, rs1==x11, imm_val == 92, 
+// opcode: c.lw; op1:x11; dest:x15; immval:0x5c
+TEST_LOAD(x1,x2,0,x11,x15,0x5c,8,c.lw,0)
+
+inst_3:
+// rd==x10, rs1==x15, imm_val == 108, 
+// opcode: c.lw; op1:x15; dest:x10; immval:0x6c
+TEST_LOAD(x1,x2,0,x15,x10,0x6c,12,c.lw,0)
+
+inst_4:
+// rd==x13, rs1==x14, imm_val == 116, 
+// opcode: c.lw; op1:x14; dest:x13; immval:0x74
+TEST_LOAD(x1,x2,0,x14,x13,0x74,16,c.lw,0)
+
+inst_5:
+// rd==x11, rs1==x13, imm_val == 120, 
+// opcode: c.lw; op1:x13; dest:x11; immval:0x78
+TEST_LOAD(x1,x2,0,x13,x11,0x78,20,c.lw,0)
+
+inst_6:
+// rd==x12, rs1==x10, imm_val == 64, 
+// opcode: c.lw; op1:x10; dest:x12; immval:0x40
+TEST_LOAD(x1,x2,0,x10,x12,0x40,24,c.lw,0)
+
+inst_7:
+// rd==x9, imm_val == 32, 
+// opcode: c.lw; op1:x10; dest:x9; immval:0x20
+TEST_LOAD(x1,x2,0,x10,x9,0x20,28,c.lw,0)
+
+inst_8:
+// rs1==x9, imm_val == 16, 
+// opcode: c.lw; op1:x9; dest:x8; immval:0x10
+TEST_LOAD(x1,x2,0,x9,x8,0x10,32,c.lw,0)
+
+inst_9:
+// imm_val == 8, 
+// opcode: c.lw; op1:x11; dest:x10; immval:0x8
+TEST_LOAD(x1,x2,0,x11,x10,0x8,36,c.lw,0)
+
+inst_10:
+// imm_val == 4, 
+// opcode: c.lw; op1:x11; dest:x10; immval:0x4
+TEST_LOAD(x1,x2,0,x11,x10,0x4,40,c.lw,0)
+
+inst_11:
+// imm_val == 40, 
+// opcode: c.lw; op1:x11; dest:x10; immval:0x28
+TEST_LOAD(x1,x2,0,x11,x10,0x28,44,c.lw,0)
+
+inst_12:
+// imm_val == 84, 
+// opcode: c.lw; op1:x11; dest:x10; immval:0x54
+TEST_LOAD(x1,x2,0,x11,x10,0x54,48,c.lw,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S
new file mode 100644
index 000000000..49f3f6409
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/clwsp-01.S
@@ -0,0 +1,150 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.lwsp instruction of the RISC-V C extension for the clwsp covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",clwsp)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rd==x2, imm_val == 0, 
+// opcode: c.lwsp; op1:x2; dest:x2; immval:0x0
+TEST_LOAD(x5,x7,0,x2,x2,0x0,0,c.lwsp,0)
+
+inst_1:
+// rd==x11, imm_val == 124, imm_val > 0
+// opcode: c.lwsp; op1:x2; dest:x11; immval:0x7c
+TEST_LOAD(x5,x7,0,x2,x11,0x7c,4,c.lwsp,0)
+
+inst_2:
+// rd==x3, imm_val == 188, 
+// opcode: c.lwsp; op1:x2; dest:x3; immval:0xbc
+TEST_LOAD(x5,x7,0,x2,x3,0xbc,8,c.lwsp,0)
+
+inst_3:
+// rd==x6, imm_val == 220, 
+// opcode: c.lwsp; op1:x2; dest:x6; immval:0xdc
+TEST_LOAD(x5,x7,0,x2,x6,0xdc,12,c.lwsp,0)
+
+inst_4:
+// rd==x9, imm_val == 236, 
+// opcode: c.lwsp; op1:x2; dest:x9; immval:0xec
+TEST_LOAD(x5,x7,0,x2,x9,0xec,16,c.lwsp,0)
+
+inst_5:
+// rd==x1, imm_val == 244, 
+// opcode: c.lwsp; op1:x2; dest:x1; immval:0xf4
+TEST_LOAD(x5,x7,0,x2,x1,0xf4,20,c.lwsp,0)
+
+inst_6:
+// rd==x4, imm_val == 248, 
+// opcode: c.lwsp; op1:x2; dest:x4; immval:0xf8
+TEST_LOAD(x5,x7,0,x2,x4,0xf8,24,c.lwsp,0)
+
+inst_7:
+// rd==x8, imm_val == 128, 
+// opcode: c.lwsp; op1:x2; dest:x8; immval:0x80
+TEST_LOAD(x5,x7,0,x2,x8,0x80,28,c.lwsp,0)
+
+inst_8:
+// rd==x15, imm_val == 64, 
+// opcode: c.lwsp; op1:x2; dest:x15; immval:0x40
+TEST_LOAD(x5,x7,0,x2,x15,0x40,32,c.lwsp,0)
+
+inst_9:
+// rd==x12, imm_val == 32, 
+// opcode: c.lwsp; op1:x2; dest:x12; immval:0x20
+TEST_LOAD(x5,x7,0,x2,x12,0x20,36,c.lwsp,0)
+
+inst_10:
+// rd==x10, imm_val == 16, 
+// opcode: c.lwsp; op1:x2; dest:x10; immval:0x10
+TEST_LOAD(x5,x7,0,x2,x10,0x10,40,c.lwsp,0)
+
+inst_11:
+// rd==x14, imm_val == 8, 
+// opcode: c.lwsp; op1:x2; dest:x14; immval:0x8
+TEST_LOAD(x5,x3,0,x2,x14,0x8,44,c.lwsp,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_12:
+// rd==x13, imm_val == 4, 
+// opcode: c.lwsp; op1:x2; dest:x13; immval:0x4
+TEST_LOAD(x1,x3,0,x2,x13,0x4,0,c.lwsp,0)
+
+inst_13:
+// rd==x5, imm_val == 168, 
+// opcode: c.lwsp; op1:x2; dest:x5; immval:0xa8
+TEST_LOAD(x1,x3,0,x2,x5,0xa8,4,c.lwsp,0)
+
+inst_14:
+// rd==x7, imm_val == 84, 
+// opcode: c.lwsp; op1:x2; dest:x7; immval:0x54
+TEST_LOAD(x1,x3,0,x2,x7,0x54,8,c.lwsp,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 3*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S
new file mode 100644
index 000000000..ae1c87f68
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cmv-01.S
@@ -0,0 +1,500 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.mv instruction of the RISC-V C extension for the cmv covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cmv)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs2 == rd and rs2 != 0, rd==x13, rs2==x13, rs2_val == (-2**(xlen-1)), rs2_val == -2147483648
+// opcode: c.mv; op2:x13; dest:x13; op2val:-0x80000000
+TEST_CMV_OP( c.mv, x13, x13, -0x80000000, -0x80000000, x4, 0, x10)
+
+inst_1:
+// rs2 != rd and rs2 != 0, rd==x3, rs2==x14, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
+// opcode: c.mv; op2:x14; dest:x3; op2val:0x7fffffff
+TEST_CMV_OP( c.mv, x3, x14, 0x7fffffff, 0x7fffffff, x4, 4, x10)
+
+inst_2:
+// rd==x15, rs2==x5, rs2_val == -1073741825, 
+// opcode: c.mv; op2:x5; dest:x15; op2val:-0x40000001
+TEST_CMV_OP( c.mv, x15, x5, -0x40000001, -0x40000001, x4, 8, x10)
+
+inst_3:
+// rd==x6, rs2==x2, rs2_val == -536870913, 
+// opcode: c.mv; op2:x2; dest:x6; op2val:-0x20000001
+TEST_CMV_OP( c.mv, x6, x2, -0x20000001, -0x20000001, x4, 12, x10)
+
+inst_4:
+// rd==x9, rs2==x7, rs2_val == -268435457, 
+// opcode: c.mv; op2:x7; dest:x9; op2val:-0x10000001
+TEST_CMV_OP( c.mv, x9, x7, -0x10000001, -0x10000001, x4, 16, x10)
+
+inst_5:
+// rd==x2, rs2==x11, rs2_val == -134217729, 
+// opcode: c.mv; op2:x11; dest:x2; op2val:-0x8000001
+TEST_CMV_OP( c.mv, x2, x11, -0x8000001, -0x8000001, x4, 20, x10)
+
+inst_6:
+// rd==x5, rs2==x15, rs2_val == -67108865, 
+// opcode: c.mv; op2:x15; dest:x5; op2val:-0x4000001
+TEST_CMV_OP( c.mv, x5, x15, -0x4000001, -0x4000001, x4, 24, x10)
+
+inst_7:
+// rd==x11, rs2==x9, rs2_val == -33554433, 
+// opcode: c.mv; op2:x9; dest:x11; op2val:-0x2000001
+TEST_CMV_OP( c.mv, x11, x9, -0x2000001, -0x2000001, x4, 28, x10)
+
+inst_8:
+// rd==x1, rs2==x8, rs2_val == -16777217, 
+// opcode: c.mv; op2:x8; dest:x1; op2val:-0x1000001
+TEST_CMV_OP( c.mv, x1, x8, -0x1000001, -0x1000001, x4, 32, x10)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_9:
+// rd==x7, rs2==x6, rs2_val == -8388609, 
+// opcode: c.mv; op2:x6; dest:x7; op2val:-0x800001
+TEST_CMV_OP( c.mv, x7, x6, -0x800001, -0x800001, x2, 0, x5)
+
+inst_10:
+// rd==x12, rs2==x1, rs2_val == -4194305, 
+// opcode: c.mv; op2:x1; dest:x12; op2val:-0x400001
+TEST_CMV_OP( c.mv, x12, x1, -0x400001, -0x400001, x2, 4, x5)
+
+inst_11:
+// rd==x14, rs2==x4, rs2_val == -2097153, 
+// opcode: c.mv; op2:x4; dest:x14; op2val:-0x200001
+TEST_CMV_OP( c.mv, x14, x4, -0x200001, -0x200001, x2, 8, x5)
+
+inst_12:
+// rd==x10, rs2==x12, rs2_val == -1048577, 
+// opcode: c.mv; op2:x12; dest:x10; op2val:-0x100001
+TEST_CMV_OP( c.mv, x10, x12, -0x100001, -0x100001, x2, 12, x5)
+
+inst_13:
+// rd==x8, rs2==x3, rs2_val == -524289, 
+// opcode: c.mv; op2:x3; dest:x8; op2val:-0x80001
+TEST_CMV_OP( c.mv, x8, x3, -0x80001, -0x80001, x2, 16, x5)
+
+inst_14:
+// rd==x0, rs2==x10, rs2_val == -262145, 
+// opcode: c.mv; op2:x10; dest:x0; op2val:-0x40001
+TEST_CMV_OP( c.mv, x0, x10, 0, -0x40001, x2, 20, x5)
+
+inst_15:
+// rd==x4, rs2_val == -131073, 
+// opcode: c.mv; op2:x12; dest:x4; op2val:-0x20001
+TEST_CMV_OP( c.mv, x4, x12, -0x20001, -0x20001, x2, 24, x5)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x10001
+TEST_CMV_OP( c.mv, x10, x11, -0x10001, -0x10001, x2, 28, x5)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x8001
+TEST_CMV_OP( c.mv, x10, x11, -0x8001, -0x8001, x2, 32, x5)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x4001
+TEST_CMV_OP( c.mv, x10, x11, -0x4001, -0x4001, x2, 36, x5)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2001
+TEST_CMV_OP( c.mv, x10, x11, -0x2001, -0x2001, x2, 40, x5)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x1001
+TEST_CMV_OP( c.mv, x10, x11, -0x1001, -0x1001, x2, 44, x5)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x801
+TEST_CMV_OP( c.mv, x10, x11, -0x801, -0x801, x2, 48, x5)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x401
+TEST_CMV_OP( c.mv, x10, x11, -0x401, -0x401, x2, 52, x5)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x201
+TEST_CMV_OP( c.mv, x10, x11, -0x201, -0x201, x2, 56, x5)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x101
+TEST_CMV_OP( c.mv, x10, x11, -0x101, -0x101, x2, 60, x5)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x81
+TEST_CMV_OP( c.mv, x10, x11, -0x81, -0x81, x2, 64, x5)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x41
+TEST_CMV_OP( c.mv, x10, x11, -0x41, -0x41, x2, 68, x5)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x21
+TEST_CMV_OP( c.mv, x10, x11, -0x21, -0x21, x2, 72, x5)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x11
+TEST_CMV_OP( c.mv, x10, x11, -0x11, -0x11, x2, 76, x5)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x9
+TEST_CMV_OP( c.mv, x10, x11, -0x9, -0x9, x2, 80, x5)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x5
+TEST_CMV_OP( c.mv, x10, x11, -0x5, -0x5, x2, 84, x5)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x3
+TEST_CMV_OP( c.mv, x10, x11, -0x3, -0x3, x2, 88, x5)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x2
+TEST_CMV_OP( c.mv, x10, x11, -0x2, -0x2, x2, 92, x5)
+
+inst_33:
+// rs2_val == 1073741824, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000000
+TEST_CMV_OP( c.mv, x10, x11, 0x40000000, 0x40000000, x2, 96, x5)
+
+inst_34:
+// rs2_val == 536870912, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000000
+TEST_CMV_OP( c.mv, x10, x11, 0x20000000, 0x20000000, x2, 100, x5)
+
+inst_35:
+// rs2_val == 268435456, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000000
+TEST_CMV_OP( c.mv, x10, x11, 0x10000000, 0x10000000, x2, 104, x5)
+
+inst_36:
+// rs2_val == 134217728, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000000
+TEST_CMV_OP( c.mv, x10, x11, 0x8000000, 0x8000000, x2, 108, x5)
+
+inst_37:
+// rs2_val == 67108864, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000000
+TEST_CMV_OP( c.mv, x10, x11, 0x4000000, 0x4000000, x2, 112, x5)
+
+inst_38:
+// rs2_val == 33554432, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000000
+TEST_CMV_OP( c.mv, x10, x11, 0x2000000, 0x2000000, x2, 116, x5)
+
+inst_39:
+// rs2_val == 16777216, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000000
+TEST_CMV_OP( c.mv, x10, x11, 0x1000000, 0x1000000, x2, 120, x5)
+
+inst_40:
+// rs2_val == 8388608, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x800000
+TEST_CMV_OP( c.mv, x10, x11, 0x800000, 0x800000, x2, 124, x5)
+
+inst_41:
+// rs2_val == 4194304, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x400000
+TEST_CMV_OP( c.mv, x10, x11, 0x400000, 0x400000, x2, 128, x5)
+
+inst_42:
+// rs2_val == 2097152, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x200000
+TEST_CMV_OP( c.mv, x10, x11, 0x200000, 0x200000, x2, 132, x5)
+
+inst_43:
+// rs2_val == 1048576, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x100000
+TEST_CMV_OP( c.mv, x10, x11, 0x100000, 0x100000, x2, 136, x5)
+
+inst_44:
+// rs2_val == 524288, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x80000
+TEST_CMV_OP( c.mv, x10, x11, 0x80000, 0x80000, x2, 140, x5)
+
+inst_45:
+// rs2_val == 262144, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x40000
+TEST_CMV_OP( c.mv, x10, x11, 0x40000, 0x40000, x2, 144, x5)
+
+inst_46:
+// rs2_val == 131072, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x20000
+TEST_CMV_OP( c.mv, x10, x11, 0x20000, 0x20000, x2, 148, x5)
+
+inst_47:
+// rs2_val == 65536, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x10000
+TEST_CMV_OP( c.mv, x10, x11, 0x10000, 0x10000, x2, 152, x5)
+
+inst_48:
+// rs2_val == 32768, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x8000
+TEST_CMV_OP( c.mv, x10, x11, 0x8000, 0x8000, x2, 156, x5)
+
+inst_49:
+// rs2_val == 16384, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x4000
+TEST_CMV_OP( c.mv, x10, x11, 0x4000, 0x4000, x2, 160, x5)
+
+inst_50:
+// rs2_val == 8192, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x2000
+TEST_CMV_OP( c.mv, x10, x11, 0x2000, 0x2000, x2, 164, x5)
+
+inst_51:
+// rs2_val == 4096, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x1000
+TEST_CMV_OP( c.mv, x10, x11, 0x1000, 0x1000, x2, 168, x5)
+
+inst_52:
+// rs2_val == 2048, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x800
+TEST_CMV_OP( c.mv, x10, x11, 0x800, 0x800, x2, 172, x5)
+
+inst_53:
+// rs2_val == 1024, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x400
+TEST_CMV_OP( c.mv, x10, x11, 0x400, 0x400, x2, 176, x5)
+
+inst_54:
+// rs2_val == 512, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x200
+TEST_CMV_OP( c.mv, x10, x11, 0x200, 0x200, x2, 180, x5)
+
+inst_55:
+// rs2_val == 256, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x100
+TEST_CMV_OP( c.mv, x10, x11, 0x100, 0x100, x2, 184, x5)
+
+inst_56:
+// rs2_val == 128, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x80
+TEST_CMV_OP( c.mv, x10, x11, 0x80, 0x80, x2, 188, x5)
+
+inst_57:
+// rs2_val == 64, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x40
+TEST_CMV_OP( c.mv, x10, x11, 0x40, 0x40, x2, 192, x5)
+
+inst_58:
+// rs2_val == 1, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x1
+TEST_CMV_OP( c.mv, x10, x11, 0x1, 0x1, x2, 196, x5)
+
+inst_59:
+// rs2_val==46341, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0xb505
+TEST_CMV_OP( c.mv, x10, x11, 0xb505, 0xb505, x2, 200, x5)
+
+inst_60:
+// rs2_val==-46339, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb503
+TEST_CMV_OP( c.mv, x10, x11, -0xb503, -0xb503, x2, 204, x5)
+
+inst_61:
+// rs2_val==1717986919, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666667
+TEST_CMV_OP( c.mv, x10, x11, 0x66666667, 0x66666667, x2, 208, x5)
+
+inst_62:
+// rs2_val==858993460, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333334
+TEST_CMV_OP( c.mv, x10, x11, 0x33333334, 0x33333334, x2, 212, x5)
+
+inst_63:
+// rs2_val==6, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x6
+TEST_CMV_OP( c.mv, x10, x11, 0x6, 0x6, x2, 216, x5)
+
+inst_64:
+// rs2_val==-1431655765, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555555
+TEST_CMV_OP( c.mv, x10, x11, -0x55555555, -0x55555555, x2, 220, x5)
+
+inst_65:
+// rs2_val==1431655766, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555556
+TEST_CMV_OP( c.mv, x10, x11, 0x55555556, 0x55555556, x2, 224, x5)
+
+inst_66:
+// rs2_val==4, rs2_val == 4
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x4
+TEST_CMV_OP( c.mv, x10, x11, 0x4, 0x4, x2, 228, x5)
+
+inst_67:
+// rs2_val==46339, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0xb503
+TEST_CMV_OP( c.mv, x10, x11, 0xb503, 0xb503, x2, 232, x5)
+
+inst_68:
+// rs2_val==0, rs2_val == 0
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x0
+TEST_CMV_OP( c.mv, x10, x11, 0x0, 0x0, x2, 236, x5)
+
+inst_69:
+// rs2_val==1717986917, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666665
+TEST_CMV_OP( c.mv, x10, x11, 0x66666665, 0x66666665, x2, 240, x5)
+
+inst_70:
+// rs2_val==858993458, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333332
+TEST_CMV_OP( c.mv, x10, x11, 0x33333332, 0x33333332, x2, 244, x5)
+
+inst_71:
+// rs2_val==1431655764, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555554
+TEST_CMV_OP( c.mv, x10, x11, 0x55555554, 0x55555554, x2, 248, x5)
+
+inst_72:
+// rs2_val==2, rs2_val == 2
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x2
+TEST_CMV_OP( c.mv, x10, x11, 0x2, 0x2, x2, 252, x5)
+
+inst_73:
+// rs2_val==46340, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0xb504
+TEST_CMV_OP( c.mv, x10, x11, 0xb504, 0xb504, x2, 256, x5)
+
+inst_74:
+// rs2_val==-46340, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0xb504
+TEST_CMV_OP( c.mv, x10, x11, -0xb504, -0xb504, x2, 260, x5)
+
+inst_75:
+// rs2_val==1717986918, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x66666666
+TEST_CMV_OP( c.mv, x10, x11, 0x66666666, 0x66666666, x2, 264, x5)
+
+inst_76:
+// rs2_val==858993459, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x33333333
+TEST_CMV_OP( c.mv, x10, x11, 0x33333333, 0x33333333, x2, 268, x5)
+
+inst_77:
+// rs2_val==5, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x5
+TEST_CMV_OP( c.mv, x10, x11, 0x5, 0x5, x2, 272, x5)
+
+inst_78:
+// rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x55555556
+TEST_CMV_OP( c.mv, x10, x11, -0x55555556, -0x55555556, x2, 276, x5)
+
+inst_79:
+// rs2_val==1431655765, rs2_val == 1431655765
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x55555555
+TEST_CMV_OP( c.mv, x10, x11, 0x55555555, 0x55555555, x2, 280, x5)
+
+inst_80:
+// rs2_val == 32, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x20
+TEST_CMV_OP( c.mv, x10, x11, 0x20, 0x20, x2, 284, x5)
+
+inst_81:
+// rs2_val == 16, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x10
+TEST_CMV_OP( c.mv, x10, x11, 0x10, 0x10, x2, 288, x5)
+
+inst_82:
+// rs2_val == 8, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x8
+TEST_CMV_OP( c.mv, x10, x11, 0x8, 0x8, x2, 292, x5)
+
+inst_83:
+// rs2_val==3, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:0x3
+TEST_CMV_OP( c.mv, x10, x11, 0x3, 0x3, x2, 296, x5)
+
+inst_84:
+// rs2_val == -262145, 
+// opcode: c.mv; op2:x11; dest:x10; op2val:-0x40001
+TEST_CMV_OP( c.mv, x10, x11, -0x40001, -0x40001, x2, 300, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 76*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cnop-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cnop-01.S
new file mode 100644
index 000000000..387aff04f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cnop-01.S
@@ -0,0 +1,140 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.nop instruction of the RISC-V C extension for the cnop covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*)  ;def RVTEST_E = True;def TEST_CASE_1=True;",cnop)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// imm_val == 21, 
+// opcode:c.nop; immval:0x15
+TEST_CNOP_OP(c.nop, x2, 0x15, x1, 0)
+
+inst_1:
+// imm_val == 31, 
+// opcode:c.nop; immval:0x1f
+TEST_CNOP_OP(c.nop, x2, 0x1f, x1, 4)
+
+inst_2:
+// imm_val == -17, 
+// opcode:c.nop; immval:-0x11
+TEST_CNOP_OP(c.nop, x2, -0x11, x1, 8)
+
+inst_3:
+// imm_val == -9, 
+// opcode:c.nop; immval:-0x9
+TEST_CNOP_OP(c.nop, x2, -0x9, x1, 12)
+
+inst_4:
+// imm_val == -5, 
+// opcode:c.nop; immval:-0x5
+TEST_CNOP_OP(c.nop, x2, -0x5, x1, 16)
+
+inst_5:
+// imm_val == -3, 
+// opcode:c.nop; immval:-0x3
+TEST_CNOP_OP(c.nop, x2, -0x3, x1, 20)
+
+inst_6:
+// imm_val == -2, 
+// opcode:c.nop; immval:-0x2
+TEST_CNOP_OP(c.nop, x2, -0x2, x1, 24)
+
+inst_7:
+// imm_val == -32, 
+// opcode:c.nop; immval:-0x20
+TEST_CNOP_OP(c.nop, x2, -0x20, x1, 28)
+
+inst_8:
+// imm_val == 16, 
+// opcode:c.nop; immval:0x10
+TEST_CNOP_OP(c.nop, x2, 0x10, x1, 32)
+
+inst_9:
+// imm_val == 8, 
+// opcode:c.nop; immval:0x8
+TEST_CNOP_OP(c.nop, x2, 0x8, x1, 36)
+
+inst_10:
+// imm_val == 4, 
+// opcode:c.nop; immval:0x4
+TEST_CNOP_OP(c.nop, x2, 0x4, x1, 40)
+
+inst_11:
+// imm_val == 2, 
+// opcode:c.nop; immval:0x2
+TEST_CNOP_OP(c.nop, x2, 0x2, x1, 44)
+
+inst_12:
+// imm_val == 1, 
+// opcode:c.nop; immval:0x1
+TEST_CNOP_OP(c.nop, x2, 0x1, x1, 48)
+
+inst_13:
+// imm_val == -22, 
+// opcode:c.nop; immval:-0x16
+TEST_CNOP_OP(c.nop, x2, -0x16, x1, 52)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 14*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cor-01.S
new file mode 100644
index 000000000..770219fd0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cor-01.S
@@ -0,0 +1,2985 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.or instruction of the RISC-V C extension for the cor covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cor)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x12, rs2==x10, rs1_val == (-2**(xlen-1)), rs1_val == -2147483648, rs2_val == 0
+// opcode: c.or; op1:x12; op2:x10; op1val:-0x80000000; op2val:0x0
+TEST_CR_OP( c.or, x12, x10, 0x80000000, -0x80000000, 0x0, x1, 0, x2)
+
+inst_1:
+// rs1 == rs2, rs1==x9, rs2==x9, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.or; op1:x9; op2:x9; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.or, x9, x9, 0x33333334, 0x33333334, 0x33333334, x1, 4, x2)
+
+inst_2:
+// rs1==x14, rs2==x12, rs2_val == -1073741825, rs2_val < 0, rs1_val == 8
+// opcode: c.or; op1:x14; op2:x12; op1val:0x8; op2val:-0x40000001
+TEST_CR_OP( c.or, x14, x12, 0xbfffffff, 0x8, -0x40000001, x1, 8, x2)
+
+inst_3:
+// rs1==x15, rs2==x13, rs2_val == -536870913, rs1_val == 32768
+// opcode: c.or; op1:x15; op2:x13; op1val:0x8000; op2val:-0x20000001
+TEST_CR_OP( c.or, x15, x13, 0xdfffffff, 0x8000, -0x20000001, x1, 12, x2)
+
+inst_4:
+// rs1==x10, rs2==x15, rs2_val == -268435457, 
+// opcode: c.or; op1:x10; op2:x15; op1val:-0x6; op2val:-0x10000001
+TEST_CR_OP( c.or, x10, x15, 0xffffffff, -0x6, -0x10000001, x1, 16, x2)
+
+inst_5:
+// rs1==x11, rs2==x8, rs2_val == -134217729, 
+// opcode: c.or; op1:x11; op2:x8; op1val:0xb505; op2val:-0x8000001
+TEST_CR_OP( c.or, x11, x8, 0xf7ffffff, 0xb505, -0x8000001, x1, 20, x2)
+
+inst_6:
+// rs1==x13, rs2==x11, rs2_val == -67108865, 
+// opcode: c.or; op1:x13; op2:x11; op1val:0x55555554; op2val:-0x4000001
+TEST_CR_OP( c.or, x13, x11, 0xffffffff, 0x55555554, -0x4000001, x1, 24, x2)
+
+inst_7:
+// rs1==x8, rs2==x14, rs2_val == -33554433, rs1_val == 2
+// opcode: c.or; op1:x8; op2:x14; op1val:0x2; op2val:-0x2000001
+TEST_CR_OP( c.or, x8, x14, 0xfdffffff, 0x2, -0x2000001, x1, 28, x2)
+
+inst_8:
+// rs2_val == -16777217, rs1_val == -33
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x21; op2val:-0x1000001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x21, -0x1000001, x1, 32, x2)
+
+inst_9:
+// rs2_val == -8388609, rs1_val == -1431655766
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x800001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x55555556, -0x800001, x1, 36, x2)
+
+inst_10:
+// rs2_val == -4194305, rs1_val == -4194305
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x400001; op2val:-0x400001
+TEST_CR_OP( c.or, x10, x11, 0xffbfffff, -0x400001, -0x400001, x1, 40, x2)
+
+inst_11:
+// rs2_val == -2097153, rs1_val == -1073741825
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x40000001; op2val:-0x200001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x40000001, -0x200001, x1, 44, x2)
+
+inst_12:
+// rs2_val == -1048577, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x100001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x55555556, -0x100001, x1, 48, x2)
+
+inst_13:
+// rs2_val == -524289, rs1_val == 8192
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2000; op2val:-0x80001
+TEST_CR_OP( c.or, x10, x11, 0xfff7ffff, 0x2000, -0x80001, x1, 52, x2)
+
+inst_14:
+// rs2_val == -262145, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:-0x40001
+TEST_CR_OP( c.or, x10, x11, 0xfffbffff, 0x6, -0x40001, x1, 56, x2)
+
+inst_15:
+// rs2_val == -131073, rs1_val == 32
+// opcode: c.or; op1:x10; op2:x11; op1val:0x20; op2val:-0x20001
+TEST_CR_OP( c.or, x10, x11, 0xfffdffff, 0x20, -0x20001, x1, 60, x2)
+
+inst_16:
+// rs2_val == -65537, rs1_val == -524289
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x80001; op2val:-0x10001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x80001, -0x10001, x1, 64, x2)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:-0x8001
+TEST_CR_OP( c.or, x10, x11, 0xffff7fff, 0x2, -0x8001, x1, 68, x2)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:-0x4001
+TEST_CR_OP( c.or, x10, x11, 0xffffbfff, 0x3, -0x4001, x1, 72, x2)
+
+inst_19:
+// rs2_val == -8193, rs1_val == 16
+// opcode: c.or; op1:x10; op2:x11; op1val:0x10; op2val:-0x2001
+TEST_CR_OP( c.or, x10, x11, 0xffffdfff, 0x10, -0x2001, x1, 76, x2)
+
+inst_20:
+// rs2_val == -4097, rs1_val == -8388609
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x800001; op2val:-0x1001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x800001, -0x1001, x1, 80, x2)
+
+inst_21:
+// rs2_val == -2049, rs1_val == -262145
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x40001; op2val:-0x801
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x40001, -0x801, x1, 84, x2)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x7; op2val:-0x401
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x7, -0x401, x1, 88, x2)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x40001; op2val:-0x201
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x40001, -0x201, x1, 92, x2)
+
+inst_24:
+// rs2_val == -257, rs1_val == 64
+// opcode: c.or; op1:x10; op2:x11; op1val:0x40; op2val:-0x101
+TEST_CR_OP( c.or, x10, x11, 0xfffffeff, 0x40, -0x101, x1, 96, x2)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x81
+TEST_CR_OP( c.or, x10, x11, 0xffffff7f, 0x66666665, -0x81, x1, 100, x2)
+
+inst_26:
+// rs2_val == -65, rs1_val == 8388608
+// opcode: c.or; op1:x10; op2:x11; op1val:0x800000; op2val:-0x41
+TEST_CR_OP( c.or, x10, x11, 0xffffffbf, 0x800000, -0x41, x1, 104, x2)
+
+inst_27:
+// rs2_val == -33, rs1_val == -3
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x3; op2val:-0x21
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x3, -0x21, x1, 108, x2)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x3; op2val:-0x11
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x3, -0x11, x1, 112, x2)
+
+inst_29:
+// rs2_val == -9, rs1_val == 4
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:-0x9
+TEST_CR_OP( c.or, x10, x11, 0xfffffff7, 0x4, -0x9, x1, 116, x2)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x8; op2val:-0x5
+TEST_CR_OP( c.or, x10, x11, 0xfffffffb, 0x8, -0x5, x1, 120, x2)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x8000; op2val:-0x3
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, 0x8000, -0x3, x1, 124, x2)
+
+inst_32:
+// rs2_val == -2, rs1_val == 134217728
+// opcode: c.or; op1:x10; op2:x11; op1val:0x8000000; op2val:-0x2
+TEST_CR_OP( c.or, x10, x11, 0xfffffffe, 0x8000000, -0x2, x1, 128, x2)
+
+inst_33:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: c.or; op1:x10; op2:x11; op1val:0x7fffffff; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x7fffffff, 0x7fffffff, 0x3, x1, 132, x2)
+
+inst_34:
+// rs1_val == -536870913, rs2_val == 256
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x20000001; op2val:0x100
+TEST_CR_OP( c.or, x10, x11, 0xdfffffff, -0x20000001, 0x100, x1, 136, x2)
+
+inst_35:
+// rs1_val == -268435457, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x10000001; op2val:-0x4001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x10000001, -0x4001, x1, 140, x2)
+
+inst_36:
+// rs1_val == -134217729, rs2_val == 67108864
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x8000001; op2val:0x4000000
+TEST_CR_OP( c.or, x10, x11, 0xf7ffffff, -0x8000001, 0x4000000, x1, 144, x2)
+
+inst_37:
+// rs1_val == -67108865, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x4000001; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0xfbffffff, -0x4000001, 0x33333334, x1, 148, x2)
+
+inst_38:
+// rs1_val == -33554433, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x2000001; op2val:0x100
+TEST_CR_OP( c.or, x10, x11, 0xfdffffff, -0x2000001, 0x100, x1, 152, x2)
+
+inst_39:
+// rs1_val == -16777217, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x40000000
+TEST_CR_OP( c.or, x10, x11, 0xfeffffff, -0x1000001, -0x40000000, x1, 156, x2)
+
+inst_40:
+// rs1_val == -2097153, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x200001; op2val:-0x11
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x200001, -0x11, x1, 160, x2)
+
+inst_41:
+// rs1_val == -1048577, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x100001; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xffefffff, -0x100001, 0x3, x1, 164, x2)
+
+inst_42:
+// rs1_val == -131073, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x20001; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xfffdffff, -0x20001, 0x6, x1, 168, x2)
+
+inst_43:
+// rs1_val == -65537, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x10001; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xfffeffff, -0x10001, 0x0, x1, 172, x2)
+
+inst_44:
+// rs1_val == -32769, rs2_val == 2
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x8001; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xffff7fff, -0x8001, 0x2, x1, 176, x2)
+
+inst_45:
+// rs1_val == -16385, rs2_val == 4
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x4001; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xffffbfff, -0x4001, 0x4, x1, 180, x2)
+
+inst_46:
+// rs1_val == -8193, rs2_val == 2048
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x2001; op2val:0x800
+TEST_CR_OP( c.or, x10, x11, 0xffffdfff, -0x2001, 0x800, x1, 184, x2)
+
+inst_47:
+// rs1_val == -4097, rs2_val == 32
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x1001; op2val:0x20
+TEST_CR_OP( c.or, x10, x11, 0xffffefff, -0x1001, 0x20, x1, 188, x2)
+
+inst_48:
+// rs1_val == -2049, rs2_val == 16384
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x801; op2val:0x4000
+TEST_CR_OP( c.or, x10, x11, 0xfffff7ff, -0x801, 0x4000, x1, 192, x2)
+
+inst_49:
+// rs1_val == -1025, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x401; op2val:-0x2
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x401, -0x2, x1, 196, x2)
+
+inst_50:
+// rs1_val == -513, rs2_val == 8
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x201; op2val:0x8
+TEST_CR_OP( c.or, x10, x11, 0xfffffdff, -0x201, 0x8, x1, 200, x2)
+
+inst_51:
+// rs1_val == -257, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x101; op2val:-0x3
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x101, -0x3, x1, 204, x2)
+
+inst_52:
+// rs1_val == -129, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x81; op2val:-0x20001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x81, -0x20001, x1, 208, x2)
+
+inst_53:
+// rs1_val == -65, rs2_val == 128
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x41; op2val:0x80
+TEST_CR_OP( c.or, x10, x11, 0xffffffbf, -0x41, 0x80, x1, 212, x2)
+
+inst_54:
+// rs1_val == -17, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x11; op2val:-0x201
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x11, -0x201, x1, 216, x2)
+
+inst_55:
+// rs1_val == -9, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x9; op2val:0x7fffffff
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x9, 0x7fffffff, x1, 220, x2)
+
+inst_56:
+// rs1_val == -5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x5; op2val:-0x3
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x5, -0x3, x1, 224, x2)
+
+inst_57:
+// rs1_val == -2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x2; op2val:-0x10001
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x2, -0x10001, x1, 228, x2)
+
+inst_58:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:-0x80000000
+TEST_CR_OP( c.or, x10, x11, 0x8000b503, 0xb503, -0x80000000, x1, 232, x2)
+
+inst_59:
+// rs2_val == 1073741824, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x40000000
+TEST_CR_OP( c.or, x10, x11, 0x40000003, 0x3, 0x40000000, x1, 236, x2)
+
+inst_60:
+// rs2_val == 536870912, rs1_val == 0
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x20000000
+TEST_CR_OP( c.or, x10, x11, 0x20000000, 0x0, 0x20000000, x1, 240, x2)
+
+inst_61:
+// rs2_val == 268435456, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x10000000
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x55555554, 0x10000000, x1, 244, x2)
+
+inst_62:
+// rs2_val == 134217728, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x1000001; op2val:0x8000000
+TEST_CR_OP( c.or, x10, x11, 0xfeffffff, -0x1000001, 0x8000000, x1, 248, x2)
+
+inst_63:
+// rs2_val == 33554432, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x801; op2val:0x2000000
+TEST_CR_OP( c.or, x10, x11, 0xfffff7ff, -0x801, 0x2000000, x1, 252, x2)
+
+inst_64:
+// rs2_val == 16777216, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x40000000; op2val:0x1000000
+TEST_CR_OP( c.or, x10, x11, 0xc1000000, -0x40000000, 0x1000000, x1, 256, x2)
+
+inst_65:
+// rs2_val == 8388608, rs1_val == 268435456
+// opcode: c.or; op1:x10; op2:x11; op1val:0x10000000; op2val:0x800000
+TEST_CR_OP( c.or, x10, x11, 0x10800000, 0x10000000, 0x800000, x1, 260, x2)
+
+inst_66:
+// rs2_val == 4194304, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x2000001; op2val:0x400000
+TEST_CR_OP( c.or, x10, x11, 0xfdffffff, -0x2000001, 0x400000, x1, 264, x2)
+
+inst_67:
+// rs2_val == 2097152, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x200000
+TEST_CR_OP( c.or, x10, x11, 0x55755554, 0x55555554, 0x200000, x1, 268, x2)
+
+inst_68:
+// rs2_val == 1048576, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x40000001; op2val:0x100000
+TEST_CR_OP( c.or, x10, x11, 0xbfffffff, -0x40000001, 0x100000, x1, 272, x2)
+
+inst_69:
+// rs2_val == 524288, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x7; op2val:0x80000
+TEST_CR_OP( c.or, x10, x11, 0xfffffff9, -0x7, 0x80000, x1, 276, x2)
+
+inst_70:
+// rs2_val == 262144, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2000; op2val:0x40000
+TEST_CR_OP( c.or, x10, x11, 0x42000, 0x2000, 0x40000, x1, 280, x2)
+
+inst_71:
+// rs2_val == 131072, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x20000
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x33333332, 0x20000, x1, 284, x2)
+
+inst_72:
+// rs2_val == 65536, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2000; op2val:0x10000
+TEST_CR_OP( c.or, x10, x11, 0x12000, 0x2000, 0x10000, x1, 288, x2)
+
+inst_73:
+// rs2_val == 32768, rs1_val == 16384
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4000; op2val:0x8000
+TEST_CR_OP( c.or, x10, x11, 0xc000, 0x4000, 0x8000, x1, 292, x2)
+
+inst_74:
+// rs2_val == 8192, rs1_val == 512
+// opcode: c.or; op1:x10; op2:x11; op1val:0x200; op2val:0x2000
+TEST_CR_OP( c.or, x10, x11, 0x2200, 0x200, 0x2000, x1, 296, x2)
+
+inst_75:
+// rs2_val == 4096, rs1_val == 67108864
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4000000; op2val:0x1000
+TEST_CR_OP( c.or, x10, x11, 0x4001000, 0x4000000, 0x1000, x1, 300, x2)
+
+inst_76:
+// rs2_val == 1024, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x5; op2val:0x400
+TEST_CR_OP( c.or, x10, x11, 0xfffffffb, -0x5, 0x400, x1, 304, x2)
+
+inst_77:
+// rs2_val == 512, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x200
+TEST_CR_OP( c.or, x10, x11, 0x200, 0x0, 0x200, x1, 308, x2)
+
+inst_78:
+// rs2_val == 64, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x4000001; op2val:0x40
+TEST_CR_OP( c.or, x10, x11, 0xfbffffff, -0x4000001, 0x40, x1, 312, x2)
+
+inst_79:
+// rs2_val == 16, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4000000; op2val:0x10
+TEST_CR_OP( c.or, x10, x11, 0x4000010, 0x4000000, 0x10, x1, 316, x2)
+
+inst_80:
+// rs2_val == 1, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x41; op2val:0x1
+TEST_CR_OP( c.or, x10, x11, 0xffffffbf, -0x41, 0x1, x1, 320, x2)
+
+inst_81:
+// rs1_val == 1073741824, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x40000000; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x40000000, 0x40000000, 0x0, x1, 324, x2)
+
+inst_82:
+// rs1_val == 536870912, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x20000000; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, 0x20000000, -0xb504, x1, 328, x2)
+
+inst_83:
+// rs1_val == 33554432, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2000000; op2val:0x10
+TEST_CR_OP( c.or, x10, x11, 0x2000010, 0x2000000, 0x10, x1, 332, x2)
+
+inst_84:
+// rs1_val == 16777216, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x1000000; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x1000004, 0x1000000, 0x4, x1, 336, x2)
+
+inst_85:
+// rs1_val == 4194304, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x400000; op2val:-0x1
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x400000, -0x1, x1, 340, x2)
+
+inst_86:
+// rs1_val == 2097152, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x200000; op2val:-0x2001
+TEST_CR_OP( c.or, x10, x11, 0xffffdfff, 0x200000, -0x2001, x1, 344, x2)
+
+inst_87:
+// rs1_val == 1048576, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x100000; op2val:0x200000
+TEST_CR_OP( c.or, x10, x11, 0x300000, 0x100000, 0x200000, x1, 348, x2)
+
+inst_88:
+// rs1_val == 524288, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x80000; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x80003, 0x80000, 0x3, x1, 352, x2)
+
+inst_89:
+// rs1_val == 262144, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x40000; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x40006, 0x40000, 0x6, x1, 356, x2)
+
+inst_90:
+// rs1_val == 131072, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x20000; op2val:-0x10001
+TEST_CR_OP( c.or, x10, x11, 0xfffeffff, 0x20000, -0x10001, x1, 360, x2)
+
+inst_91:
+// rs1_val == 65536, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x10000; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaabaaab, 0x10000, -0x55555555, x1, 364, x2)
+
+inst_92:
+// rs1_val == 4096, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x1000; op2val:0x1
+TEST_CR_OP( c.or, x10, x11, 0x1001, 0x1000, 0x1, x1, 368, x2)
+
+inst_93:
+// rs1_val == 2048, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x800; op2val:0x100000
+TEST_CR_OP( c.or, x10, x11, 0x100800, 0x800, 0x100000, x1, 372, x2)
+
+inst_94:
+// rs1_val == 1024, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x400; op2val:0x20000
+TEST_CR_OP( c.or, x10, x11, 0x20400, 0x400, 0x20000, x1, 376, x2)
+
+inst_95:
+// rs1_val == 256, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x100; op2val:-0x4001
+TEST_CR_OP( c.or, x10, x11, 0xffffbfff, 0x100, -0x4001, x1, 380, x2)
+
+inst_96:
+// rs1_val == 128, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x80; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x85, 0x80, 0x5, x1, 384, x2)
+
+inst_97:
+// rs1_val == 1, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x1; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0x1, 0xb505, x1, 388, x2)
+
+inst_98:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb505, 0xb505, x1, 392, x2)
+
+inst_99:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, 0xb505, -0xb503, x1, 396, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb505, 0x66666667, x1, 400, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x3333b735, 0xb505, 0x33333334, x1, 404, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb505, 0x6, x1, 408, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, 0xb505, -0x55555555, x1, 412, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0xb505, 0x55555556, x1, 416, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb505, 0x4, x1, 420, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb505, 0xb503, x1, 424, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb505, 0x0, x1, 428, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x6666f765, 0xb505, 0x66666665, x1, 432, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0xb505, 0x33333332, x1, 436, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0xb505, 0x55555554, x1, 440, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb505, 0x2, x1, 444, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb505, 0xb504, x1, 448, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, 0xb505, -0xb504, x1, 452, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb505, 0x66666666, x1, 456, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0xb505, 0x33333333, x1, 460, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb505, 0x5, x1, 464, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, 0xb505, -0x55555556, x1, 468, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0xb505, 0x55555555, x1, 472, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb505; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb505, 0x3, x1, 476, x2)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, -0xb503, 0xb505, x1, 480, x2)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb503, -0xb503, x1, 484, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, -0xb503, 0x66666667, x1, 488, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfd, -0xb503, 0x33333334, x1, 492, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, -0xb503, 0x6, x1, 496, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0xb503, -0x55555555, x1, 500, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffff5fff, -0xb503, 0x55555556, x1, 504, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb503, 0x4, x1, 508, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0xb503, 0xb503, x1, 512, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 516, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0xffff6efd, -0xb503, 0x66666665, x1, 520, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, -0xb503, 0x33333332, x1, 524, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, -0xb503, 0x55555554, x1, 528, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, -0xb503, 0x2, x1, 532, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, -0xb503, 0xb504, x1, 536, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb503, -0xb504, x1, 540, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, -0xb503, 0x66666666, x1, 544, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, -0xb503, 0x33333333, x1, 548, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb503, 0x5, x1, 552, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0xb503, -0x55555556, x1, 556, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, -0xb503, 0x55555555, x1, 560, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb503; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, -0xb503, 0x3, x1, 564, x2)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666667, 0xb505, x1, 568, x2)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, 0x66666667, -0xb503, x1, 572, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x66666667, x1, 576, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x33333334, x1, 580, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x6, x1, 584, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, 0x66666667, -0x55555555, x1, 588, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x55555556, x1, 592, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x4, x1, 596, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666667, 0xb503, x1, 600, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 604, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x66666665, x1, 608, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x33333332, x1, 612, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x55555554, x1, 616, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x2, x1, 620, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666667, 0xb504, x1, 624, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, 0x66666667, -0xb504, x1, 628, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x66666666, x1, 632, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x33333333, x1, 636, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x5, x1, 640, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, 0x66666667, -0x55555556, x1, 644, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666667, 0x55555555, x1, 648, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666667; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666667, 0x3, x1, 652, x2)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x3333b735, 0x33333334, 0xb505, x1, 656, x2)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfd, 0x33333334, -0xb503, x1, 660, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333334, 0x66666667, x1, 664, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333334, 0x33333334, 0x33333334, x1, 668, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333334, 0x6, x1, 672, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbf, 0x33333334, -0x55555555, x1, 676, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x33333334, 0x55555556, x1, 680, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x33333334, 0x33333334, 0x4, x1, 684, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0x33333334, 0xb503, x1, 688, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 692, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x33333334, 0x66666665, x1, 696, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333334, 0x33333332, x1, 700, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777774, 0x33333334, 0x55555554, x1, 704, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333334, 0x2, x1, 708, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x3333b734, 0x33333334, 0xb504, x1, 712, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfc, 0x33333334, -0xb504, x1, 716, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x33333334, 0x66666666, x1, 720, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333334, 0x33333333, x1, 724, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x33333335, 0x33333334, 0x5, x1, 728, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbe, 0x33333334, -0x55555556, x1, 732, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x33333334, 0x55555555, x1, 736, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333334; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333334, 0x3, x1, 740, x2)
+
+inst_186:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x6, 0xb505, x1, 744, x2)
+
+inst_187:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, 0x6, -0xb503, x1, 748, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x6, 0x66666667, x1, 752, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x6, 0x33333334, x1, 756, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x6, 0x6, x1, 760, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, 0x6, -0x55555555, x1, 764, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x6, 0x55555556, x1, 768, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x6, 0x4, x1, 772, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x6, 0xb503, x1, 776, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x6, 0x0, x1, 780, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x6, 0x66666665, x1, 784, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x6, 0x33333332, x1, 788, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x6, 0x55555554, x1, 792, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x6, 0x2, x1, 796, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb506, 0x6, 0xb504, x1, 800, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afe, 0x6, -0xb504, x1, 804, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x6, 0x66666666, x1, 808, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x6, 0x33333333, x1, 812, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x6, 0x5, x1, 816, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaae, 0x6, -0x55555556, x1, 820, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x6, 0x55555555, x1, 824, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x6; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x6, 0x3, x1, 828, x2)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, -0x55555555, 0xb505, x1, 832, x2)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0x55555555, -0xb503, x1, 836, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666667, x1, 840, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbf, -0x55555555, 0x33333334, x1, 844, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, -0x55555555, 0x6, x1, 848, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555555, x1, 852, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x55555555, 0x55555556, x1, 856, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x1, 860, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfab, -0x55555555, 0xb503, x1, 864, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 868, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666665, x1, 872, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, -0x55555555, 0x33333332, x1, 876, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x1, 880, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555555, 0x2, x1, 884, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, -0x55555555, 0xb504, x1, 888, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0x55555555, -0xb504, x1, 892, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666666, x1, 896, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, -0x55555555, 0x33333333, x1, 900, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, -0x55555555, 0x5, x1, 904, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555556, x1, 908, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x55555555, 0x55555555, x1, 912, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555555, 0x3, x1, 916, x2)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0x55555556, 0xb505, x1, 920, x2)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff5fff, 0x55555556, -0xb503, x1, 924, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555556, 0x66666667, x1, 928, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x55555556, 0x33333334, x1, 932, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x6, x1, 936, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x55555556, -0x55555555, x1, 940, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x55555556, x1, 944, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x4, x1, 948, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0x55555556, 0xb503, x1, 952, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 956, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555556, 0x66666665, x1, 960, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x55555556, 0x33333332, x1, 964, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x55555554, x1, 968, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555556, 0x2, x1, 972, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x5555f556, 0x55555556, 0xb504, x1, 976, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffe, 0x55555556, -0xb504, x1, 980, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x55555556, 0x66666666, x1, 984, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555556, 0x33333333, x1, 988, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555556, 0x5, x1, 992, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xfffffffe, 0x55555556, -0x55555556, x1, 996, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555556, 0x55555555, x1, 1000, x2)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555556; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555556, 0x3, x1, 1004, x2)
+
+inst_252:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0x4, 0xb505, x1, 1008, x2)
+
+inst_253:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, 0x4, -0xb503, x1, 1012, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x4, 0x66666667, x1, 1016, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333334, 0x4, 0x33333334, x1, 1020, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x4, 0x6, x1, 1024, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x1, 1028, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x4, 0x55555556, x1, 1032, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x4, 0x4, 0x4, x1, 1036, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x4, 0xb503, x1, 1040, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x4, 0x4, 0x0, x1, 1044, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x4, 0x66666665, x1, 1048, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x4, 0x33333332, x1, 1052, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x4, 0x55555554, x1, 1056, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x4, 0x2, x1, 1060, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb504, 0x4, 0xb504, x1, 1064, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, 0x4, -0xb504, x1, 1068, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x4, 0x66666666, x1, 1072, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x4, 0x33333333, x1, 1076, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x5, 0x4, 0x5, x1, 1080, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x1, 1084, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x4, 0x55555555, x1, 1088, x2)
+
+inst_273:
+// rs1_val==4 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x4; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x4, 0x3, x1, 1092, x2)
+
+inst_274:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb503, 0xb505, x1, 1096, x2)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0xb503, -0xb503, x1, 1100, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb503, 0x66666667, x1, 1104, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0xb503, 0x33333334, x1, 1108, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb503, 0x6, x1, 1112, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfab, 0xb503, -0x55555555, x1, 1116, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0xb503, 0x55555556, x1, 1120, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb503, 0x4, x1, 1124, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0xb503, 0xb503, x1, 1128, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0xb503, 0x0, x1, 1132, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb503, 0x66666665, x1, 1136, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x3333b733, 0xb503, 0x33333332, x1, 1140, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0xb503, 0x55555554, x1, 1144, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0xb503, 0x2, x1, 1148, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb503, 0xb504, x1, 1152, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0xb503, -0xb504, x1, 1156, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb503, 0x66666666, x1, 1160, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x3333b733, 0xb503, 0x33333333, x1, 1164, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb503, 0x5, x1, 1168, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfab, 0xb503, -0x55555556, x1, 1172, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0xb503, 0x55555555, x1, 1176, x2)
+
+inst_295:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb503; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0xb503, 0x3, x1, 1180, x2)
+
+inst_296:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0x0, 0xb505, x1, 1184, x2)
+
+inst_297:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, 0x0, -0xb503, x1, 1188, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x0, 0x66666667, x1, 1192, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333334, 0x0, 0x33333334, x1, 1196, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x0, 0x6, x1, 1200, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x1, 1204, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x0, 0x55555556, x1, 1208, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x4, 0x0, 0x4, x1, 1212, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0x0, 0xb503, x1, 1216, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x0, 0x0, 0x0, x1, 1220, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x0, 0x66666665, x1, 1224, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x0, 0x33333332, x1, 1228, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x0, 0x55555554, x1, 1232, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x2, 0x0, 0x2, x1, 1236, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb504, 0x0, 0xb504, x1, 1240, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, 0x0, -0xb504, x1, 1244, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x0, 0x66666666, x1, 1248, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x0, 0x33333333, x1, 1252, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x5, 0x0, 0x5, x1, 1256, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x1, 1260, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x0, 0x55555555, x1, 1264, x2)
+
+inst_317:
+// rs1_val==0 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x0; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x3, 0x0, 0x3, x1, 1268, x2)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x6666f765, 0x66666665, 0xb505, x1, 1272, x2)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff6efd, 0x66666665, -0xb503, x1, 1276, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666665, 0x66666667, x1, 1280, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x66666665, 0x33333334, x1, 1284, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666665, 0x6, x1, 1288, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, 0x66666665, -0x55555555, x1, 1292, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666665, 0x55555556, x1, 1296, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x66666665, 0x4, x1, 1300, x2)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666665, 0xb503, x1, 1304, x2)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1308, x2)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1312, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x66666665, x1, 1316, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333333, 0x33333332, x1, 1320, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x55555554, x1, 1324, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333333, 0x2, x1, 1328, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0x33333333, 0xb504, x1, 1332, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, 0x33333333, -0xb504, x1, 1336, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x66666666, x1, 1340, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333333, 0x33333333, x1, 1344, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333333, 0x5, x1, 1348, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, 0x33333333, -0x55555556, x1, 1352, x2)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x55555555, x1, 1356, x2)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333333, 0x3, x1, 1360, x2)
+
+inst_341:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0x5, 0xb505, x1, 1364, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, 0x5, -0xb503, x1, 1368, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x5, 0x66666667, x1, 1372, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333335, 0x5, 0x33333334, x1, 1376, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x5, 0x6, x1, 1380, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, 0x5, -0x55555555, x1, 1384, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x5, 0x55555556, x1, 1388, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x5, 0x5, 0x4, x1, 1392, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x5, 0xb503, x1, 1396, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x5, 0x5, 0x0, x1, 1400, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x5, 0x66666665, x1, 1404, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x5, 0x33333332, x1, 1408, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x5, 0x55555554, x1, 1412, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x5, 0x2, x1, 1416, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0x5, 0xb504, x1, 1420, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, 0x5, -0xb504, x1, 1424, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x5, 0x66666666, x1, 1428, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x5, 0x33333333, x1, 1432, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x5, 0x5, 0x5, x1, 1436, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x1, 1440, x2)
+
+inst_361:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x5, 0x55555555, x1, 1444, x2)
+
+inst_362:
+// rs1_val==5 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x5; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x5, 0x3, x1, 1448, x2)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, -0x55555556, 0xb505, x1, 1452, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0x55555556, -0xb503, x1, 1456, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, -0x55555556, 0x66666667, x1, 1460, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbe, -0x55555556, 0x33333334, x1, 1464, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaae, -0x55555556, 0x6, x1, 1468, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555556, -0x55555555, x1, 1472, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xfffffffe, -0x55555556, 0x55555556, x1, 1476, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x1, 1480, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfab, -0x55555556, 0xb503, x1, 1484, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1488, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, -0x55555556, 0x66666665, x1, 1492, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbba, -0x55555556, 0x33333332, x1, 1496, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x1, 1500, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaa, -0x55555556, 0x2, x1, 1504, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfae, -0x55555556, 0xb504, x1, 1508, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffffeafe, -0x55555556, -0xb504, x1, 1512, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeee, -0x55555556, 0x66666666, x1, 1516, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, -0x55555556, 0x33333333, x1, 1520, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1524, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555556, x1, 1528, x2)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x1, 1532, x2)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, -0x55555556, 0x3, x1, 1536, x2)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0x55555555, 0xb505, x1, 1540, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, 0x55555555, -0xb503, x1, 1544, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555555, 0x66666667, x1, 1548, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x55555555, 0x33333334, x1, 1552, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555555, 0x6, x1, 1556, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x55555555, -0x55555555, x1, 1560, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555555, 0x55555556, x1, 1564, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555555, 0x4, x1, 1568, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0x55555555, 0xb503, x1, 1572, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1576, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x55555555, 0x66666665, x1, 1580, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555555, 0x33333332, x1, 1584, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555555, 0x55555554, x1, 1588, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555555, 0x2, x1, 1592, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0x55555555, 0xb504, x1, 1596, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, 0x55555555, -0xb504, x1, 1600, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555555, 0x66666666, x1, 1604, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555555, 0x33333333, x1, 1608, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555555, 0x5, x1, 1612, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x1, 1616, x2)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555555, 0x55555555, x1, 1620, x2)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555555; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555555, 0x3, x1, 1624, x2)
+
+inst_407:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x3, 0xb505, x1, 1628, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, 0x3, -0xb503, x1, 1632, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x3, 0x66666667, x1, 1636, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x3, 0x33333334, x1, 1640, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x3, 0x6, x1, 1644, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, 0x3, -0x55555555, x1, 1648, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x3, 0x55555556, x1, 1652, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x3, 0x4, x1, 1656, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0x3, 0xb503, x1, 1660, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x3, 0x3, 0x0, x1, 1664, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x3, 0x66666665, x1, 1668, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x3, 0x33333332, x1, 1672, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x3, 0x55555554, x1, 1676, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x3, 0x3, 0x2, x1, 1680, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x3, 0xb504, x1, 1684, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, 0x3, -0xb504, x1, 1688, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x3, 0x66666666, x1, 1692, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x3, 0x33333333, x1, 1696, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x3, 0x5, x1, 1700, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, 0x3, -0x55555556, x1, 1704, x2)
+
+inst_427:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x3, 0x55555555, x1, 1708, x2)
+
+inst_428:
+// rs1_val==3 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x3; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x3, 0x3, 0x3, x1, 1712, x2)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x66666665, 0x66666665, x1, 1716, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666665, 0x33333332, x1, 1720, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x66666665, 0x55555554, x1, 1724, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666665, 0x2, x1, 1728, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x6666f765, 0x66666665, 0xb504, x1, 1732, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff6efd, 0x66666665, -0xb504, x1, 1736, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666665, 0x66666666, x1, 1740, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666665, 0x33333333, x1, 1744, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x66666665, 0x66666665, 0x5, x1, 1748, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, 0x66666665, -0x55555556, x1, 1752, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x66666665, 0x55555555, x1, 1756, x2)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666665; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666665, 0x3, x1, 1760, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0x33333332, 0xb505, x1, 1764, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, 0x33333332, -0xb503, x1, 1768, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333332, 0x66666667, x1, 1772, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333332, 0x33333334, x1, 1776, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333332, 0x6, x1, 1780, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, 0x33333332, -0x55555555, x1, 1784, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x33333332, 0x55555556, x1, 1788, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x33333332, 0x4, x1, 1792, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x3333b733, 0x33333332, 0xb503, x1, 1796, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1800, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333332, 0x66666665, x1, 1804, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x33333332, 0x33333332, x1, 1808, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x33333332, 0x55555554, x1, 1812, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x33333332, 0x2, x1, 1816, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x3333b736, 0x33333332, 0xb504, x1, 1820, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfe, 0x33333332, -0xb504, x1, 1824, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x33333332, 0x66666666, x1, 1828, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333332, 0x33333333, x1, 1832, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333332, 0x5, x1, 1836, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbba, 0x33333332, -0x55555556, x1, 1840, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333332, 0x55555555, x1, 1844, x2)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333332; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x33333332, 0x3, x1, 1848, x2)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0x55555554, 0xb505, x1, 1852, x2)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, 0x55555554, -0xb503, x1, 1856, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555554, 0x66666667, x1, 1860, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777774, 0x55555554, 0x33333334, x1, 1864, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555554, 0x6, x1, 1868, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x1, 1872, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555554, 0x55555556, x1, 1876, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x55555554, 0x4, x1, 1880, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x5555f557, 0x55555554, 0xb503, x1, 1884, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1888, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x77777775, 0x55555554, 0x66666665, x1, 1892, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x55555554, 0x33333332, x1, 1896, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555554, 0x55555554, 0x55555554, x1, 1900, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x55555554, 0x2, x1, 1904, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x5555f554, 0x55555554, 0xb504, x1, 1908, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffc, 0x55555554, -0xb504, x1, 1912, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x55555554, 0x66666666, x1, 1916, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x55555554, 0x33333333, x1, 1920, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555554, 0x5, x1, 1924, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x1, 1928, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555555, 0x55555554, 0x55555555, x1, 1932, x2)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x55555554; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x55555554, 0x3, x1, 1936, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0x2, 0xb505, x1, 1940, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, 0x2, -0xb503, x1, 1944, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x2, 0x66666667, x1, 1948, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333336, 0x2, 0x33333334, x1, 1952, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x2, 0x6, x1, 1956, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaab, 0x2, -0x55555555, x1, 1960, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x2, 0x55555556, x1, 1964, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x6, 0x2, 0x4, x1, 1968, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb503, 0x2, 0xb503, x1, 1972, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x2, 0x2, 0x0, x1, 1976, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x2, 0x66666665, x1, 1980, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x33333332, 0x2, 0x33333332, x1, 1984, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x55555556, 0x2, 0x55555554, x1, 1988, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x2, 0x2, 0x2, x1, 1992, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb506, 0x2, 0xb504, x1, 1996, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afe, 0x2, -0xb504, x1, 2000, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x2, 0x66666666, x1, 2004, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x33333333, 0x2, 0x33333333, x1, 2008, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x7, 0x2, 0x5, x1, 2012, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaaaaaa, 0x2, -0x55555556, x1, 2016, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x55555557, 0x2, 0x55555555, x1, 2020, x2)
+
+inst_506:
+// rs1_val==2 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x2; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x3, 0x2, 0x3, x1, 2024, x2)
+
+inst_507:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb504, 0xb505, x1, 2028, x2)
+
+inst_508:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, 0xb504, -0xb503, x1, 2032, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0xb504, 0x66666667, x1, 2036, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x3333b734, 0xb504, 0x33333334, x1, 2040, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xb506, 0xb504, 0x6, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfaf, 0xb504, -0x55555555, x1, 0, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x5555f556, 0xb504, 0x55555556, x1, 4, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xb504, 0xb504, 0x4, x1, 8, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb504, 0xb503, x1, 12, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xb504, 0xb504, 0x0, x1, 16, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x6666f765, 0xb504, 0x66666665, x1, 20, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x3333b736, 0xb504, 0x33333332, x1, 24, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x5555f554, 0xb504, 0x55555554, x1, 28, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xb506, 0xb504, 0x2, x1, 32, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xb504, 0xb504, 0xb504, x1, 36, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xfffffffc, 0xb504, -0xb504, x1, 40, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x6666f766, 0xb504, 0x66666666, x1, 44, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0xb504, 0x33333333, x1, 48, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xb505, 0xb504, 0x5, x1, 52, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xaaaabfae, 0xb504, -0x55555556, x1, 56, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x5555f555, 0xb504, 0x55555555, x1, 60, x2)
+
+inst_528:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0xb504; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xb507, 0xb504, 0x3, x1, 64, x2)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0xfffffffd, -0xb504, 0xb505, x1, 68, x2)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb504, -0xb503, x1, 72, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, -0xb504, 0x66666667, x1, 76, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfc, -0xb504, 0x33333334, x1, 80, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0xffff4afe, -0xb504, 0x6, x1, 84, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffffeaff, -0xb504, -0x55555555, x1, 88, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffe, -0xb504, 0x55555556, x1, 92, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, -0xb504, 0x4, x1, 96, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 100, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 104, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0xffff6efd, -0xb504, 0x66666665, x1, 108, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0xffff7bfe, -0xb504, 0x33333332, x1, 112, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffc, -0xb504, 0x55555554, x1, 116, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0xffff4afe, -0xb504, 0x2, x1, 120, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0xfffffffc, -0xb504, 0xb504, x1, 124, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff4afc, -0xb504, -0xb504, x1, 128, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0xffff6efe, -0xb504, 0x66666666, x1, 132, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, -0xb504, 0x33333333, x1, 136, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0xffff4afd, -0xb504, 0x5, x1, 140, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xffffeafe, -0xb504, -0x55555556, x1, 144, x2)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xffff5ffd, -0xb504, 0x55555555, x1, 148, x2)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:-0xb504; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0xffff4aff, -0xb504, 0x3, x1, 152, x2)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666666, 0xb505, x1, 156, x2)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff6eff, 0x66666666, -0xb503, x1, 160, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666666, 0x66666667, x1, 164, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x66666666, 0x33333334, x1, 168, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x66666666, 0x6, x1, 172, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeef, 0x66666666, -0x55555555, x1, 176, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x66666666, 0x55555556, x1, 180, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x66666666, 0x4, x1, 184, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x6666f767, 0x66666666, 0xb503, x1, 188, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x0
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 192, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666666, 0x66666665, x1, 196, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x66666666, 0x33333332, x1, 200, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554
+TEST_CR_OP( c.or, x10, x11, 0x77777776, 0x66666666, 0x55555554, x1, 204, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x2
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x66666666, 0x2, x1, 208, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504
+TEST_CR_OP( c.or, x10, x11, 0x6666f766, 0x66666666, 0xb504, x1, 212, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504
+TEST_CR_OP( c.or, x10, x11, 0xffff6efe, 0x66666666, -0xb504, x1, 216, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666
+TEST_CR_OP( c.or, x10, x11, 0x66666666, 0x66666666, 0x66666666, x1, 220, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666666, 0x33333333, x1, 224, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x5
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666666, 0x5, x1, 228, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556
+TEST_CR_OP( c.or, x10, x11, 0xeeeeeeee, 0x66666666, -0x55555556, x1, 232, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x66666666, 0x55555555, x1, 236, x2)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x66666666; op2val:0x3
+TEST_CR_OP( c.or, x10, x11, 0x66666667, 0x66666666, 0x3, x1, 240, x2)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505
+TEST_CR_OP( c.or, x10, x11, 0x3333b737, 0x33333333, 0xb505, x1, 244, x2)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503
+TEST_CR_OP( c.or, x10, x11, 0xffff7bff, 0x33333333, -0xb503, x1, 248, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x66666667, x1, 252, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333333, 0x33333334, x1, 256, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x6
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333333, 0x6, x1, 260, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555
+TEST_CR_OP( c.or, x10, x11, 0xbbbbbbbb, 0x33333333, -0x55555555, x1, 264, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556
+TEST_CR_OP( c.or, x10, x11, 0x77777777, 0x33333333, 0x55555556, x1, 268, x2)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0x4
+TEST_CR_OP( c.or, x10, x11, 0x33333337, 0x33333333, 0x4, x1, 272, x2)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: c.or; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503
+TEST_CR_OP( c.or, x10, x11, 0x3333b733, 0x33333333, 0xb503, x1, 276, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 70*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cslli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cslli-01.S
new file mode 100644
index 000000000..33b37b62b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cslli-01.S
@@ -0,0 +1,500 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.slli instruction of the RISC-V C extension for the cslli covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cslli)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rd==x11, rs1_val < 0 and imm_val < xlen, rs1_val == -65537, imm_val == 29
+// opcode:c.slli; op1:x11; dest:x11 op1val:-0x10001; immval:0x1d
+TEST_CI_OP( c.slli, x11, 0xe0000000, -0x10001, 0x1d, x1, 0, x2)
+
+inst_1:
+// rd==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
+// opcode:c.slli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0xb
+TEST_CI_OP( c.slli, x8, 0xfffff800, 0x7fffffff, 0xb, x1, 4, x2)
+
+inst_2:
+// rd==x9, rs1_val == -1073741825, 
+// opcode:c.slli; op1:x9; dest:x9 op1val:-0x40000001; immval:0xc
+TEST_CI_OP( c.slli, x9, 0xfffff000, -0x40000001, 0xc, x1, 8, x2)
+
+inst_3:
+// rd==x12, rs1_val == -536870913, 
+// opcode:c.slli; op1:x12; dest:x12 op1val:-0x20000001; immval:0x7
+TEST_CI_OP( c.slli, x12, 0xffffff80, -0x20000001, 0x7, x1, 12, x2)
+
+inst_4:
+// rd==x14, rs1_val == -268435457, 
+// opcode:c.slli; op1:x14; dest:x14 op1val:-0x10000001; immval:0x3
+TEST_CI_OP( c.slli, x14, 0x7ffffff8, -0x10000001, 0x3, x1, 16, x2)
+
+inst_5:
+// rd==x10, rs1_val == -134217729, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8000001; immval:0x1f
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x8000001, 0x1f, x1, 20, x2)
+
+inst_6:
+// rd==x13, rs1_val == -67108865, 
+// opcode:c.slli; op1:x13; dest:x13 op1val:-0x4000001; immval:0x13
+TEST_CI_OP( c.slli, x13, 0xfff80000, -0x4000001, 0x13, x1, 24, x2)
+
+inst_7:
+// rd==x15, rs1_val == -33554433, imm_val == 10
+// opcode:c.slli; op1:x15; dest:x15 op1val:-0x2000001; immval:0xa
+TEST_CI_OP( c.slli, x15, 0xfffffc00, -0x2000001, 0xa, x1, 28, x2)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x5
+TEST_CI_OP( c.slli, x10, 0xdfffffe0, -0x1000001, 0x5, x1, 32, x2)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x800001; immval:0x1f
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x800001, 0x1f, x1, 36, x2)
+
+inst_10:
+// rs1_val == -4194305, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x400001; immval:0x13
+TEST_CI_OP( c.slli, x10, 0xfff80000, -0x400001, 0x13, x1, 40, x2)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x200001; immval:0x11
+TEST_CI_OP( c.slli, x10, 0xfffe0000, -0x200001, 0x11, x1, 44, x2)
+
+inst_12:
+// rs1_val == -1048577, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x100001; immval:0x9
+TEST_CI_OP( c.slli, x10, 0xdffffe00, -0x100001, 0x9, x1, 48, x2)
+
+inst_13:
+// rs1_val == -524289, imm_val == 21
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80001; immval:0x15
+TEST_CI_OP( c.slli, x10, 0xffe00000, -0x80001, 0x15, x1, 52, x2)
+
+inst_14:
+// rs1_val == -262145, imm_val == 27
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x40001; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0xf8000000, -0x40001, 0x1b, x1, 56, x2)
+
+inst_15:
+// rs1_val == -131073, imm_val == 2
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x20001; immval:0x2
+TEST_CI_OP( c.slli, x10, 0xfff7fffc, -0x20001, 0x2, x1, 60, x2)
+
+inst_16:
+// rs1_val == -32769, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x1f
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x8001, 0x1f, x1, 64, x2)
+
+inst_17:
+// rs1_val == -16385, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x4001; immval:0xd
+TEST_CI_OP( c.slli, x10, 0xf7ffe000, -0x4001, 0xd, x1, 68, x2)
+
+inst_18:
+// rs1_val == -8193, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2001; immval:0x1d
+TEST_CI_OP( c.slli, x10, 0xe0000000, -0x2001, 0x1d, x1, 72, x2)
+
+inst_19:
+// rs1_val == -4097, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x1001; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0xf8000000, -0x1001, 0x1b, x1, 76, x2)
+
+inst_20:
+// rs1_val == -2049, imm_val == 15
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x801; immval:0xf
+TEST_CI_OP( c.slli, x10, 0xfbff8000, -0x801, 0xf, x1, 80, x2)
+
+inst_21:
+// rs1_val == -1025, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x401; immval:0x1f
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x401, 0x1f, x1, 84, x2)
+
+inst_22:
+// rs1_val == -513, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x201; immval:0x5
+TEST_CI_OP( c.slli, x10, 0xffffbfe0, -0x201, 0x5, x1, 88, x2)
+
+inst_23:
+// rs1_val == -257, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x101; immval:0x1f
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x101, 0x1f, x1, 92, x2)
+
+inst_24:
+// rs1_val == -129, imm_val == 30
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x81; immval:0x1e
+TEST_CI_OP( c.slli, x10, 0xc0000000, -0x81, 0x1e, x1, 96, x2)
+
+inst_25:
+// rs1_val == -65, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x41; immval:0x3
+TEST_CI_OP( c.slli, x10, 0xfffffdf8, -0x41, 0x3, x1, 100, x2)
+
+inst_26:
+// rs1_val == -33, imm_val == 23
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x21; immval:0x17
+TEST_CI_OP( c.slli, x10, 0xef800000, -0x21, 0x17, x1, 104, x2)
+
+inst_27:
+// rs1_val == -17, imm_val == 1
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x11; immval:0x1
+TEST_CI_OP( c.slli, x10, 0xffffffde, -0x11, 0x1, x1, 108, x2)
+
+inst_28:
+// rs1_val == -9, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x9; immval:0x1d
+TEST_CI_OP( c.slli, x10, 0xe0000000, -0x9, 0x1d, x1, 112, x2)
+
+inst_29:
+// rs1_val == -5, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x5; immval:0x17
+TEST_CI_OP( c.slli, x10, 0xfd800000, -0x5, 0x17, x1, 116, x2)
+
+inst_30:
+// rs1_val == -3, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x3; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0xe8000000, -0x3, 0x1b, x1, 120, x2)
+
+inst_31:
+// rs1_val == -2, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x2; immval:0x1e
+TEST_CI_OP( c.slli, x10, 0x80000000, -0x2, 0x1e, x1, 124, x2)
+
+inst_32:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x1d
+TEST_CI_OP( c.slli, x10, 0x0, -0x80000000, 0x1d, x1, 128, x2)
+
+inst_33:
+// rs1_val == 1073741824, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000000; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x0, 0x40000000, 0x1b, x1, 132, x2)
+
+inst_34:
+// rs1_val == 536870912, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000000; immval:0x13
+TEST_CI_OP( c.slli, x10, 0x0, 0x20000000, 0x13, x1, 136, x2)
+
+inst_35:
+// rs1_val == 268435456, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000000; immval:0x1e
+TEST_CI_OP( c.slli, x10, 0x0, 0x10000000, 0x1e, x1, 140, x2)
+
+inst_36:
+// rs1_val == 134217728, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000000; immval:0x9
+TEST_CI_OP( c.slli, x10, 0x0, 0x8000000, 0x9, x1, 144, x2)
+
+inst_37:
+// rs1_val == 67108864, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000000; immval:0x2
+TEST_CI_OP( c.slli, x10, 0x10000000, 0x4000000, 0x2, x1, 148, x2)
+
+inst_38:
+// rs1_val == 33554432, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000000; immval:0x5
+TEST_CI_OP( c.slli, x10, 0x40000000, 0x2000000, 0x5, x1, 152, x2)
+
+inst_39:
+// rs1_val == 16777216, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000000; immval:0x5
+TEST_CI_OP( c.slli, x10, 0x20000000, 0x1000000, 0x5, x1, 156, x2)
+
+inst_40:
+// rs1_val == 8388608, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x800000; immval:0x6
+TEST_CI_OP( c.slli, x10, 0x20000000, 0x800000, 0x6, x1, 160, x2)
+
+inst_41:
+// rs1_val == 4194304, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0xe
+TEST_CI_OP( c.slli, x10, 0x0, 0x400000, 0xe, x1, 164, x2)
+
+inst_42:
+// rs1_val == 2097152, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x200000; immval:0x7
+TEST_CI_OP( c.slli, x10, 0x10000000, 0x200000, 0x7, x1, 168, x2)
+
+inst_43:
+// rs1_val == 1048576, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x100000; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x0, 0x100000, 0x1b, x1, 172, x2)
+
+inst_44:
+// rs1_val == 524288, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x80000; immval:0x13
+TEST_CI_OP( c.slli, x10, 0x0, 0x80000, 0x13, x1, 176, x2)
+
+inst_45:
+// rs1_val == 262144, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x40000; immval:0x9
+TEST_CI_OP( c.slli, x10, 0x8000000, 0x40000, 0x9, x1, 180, x2)
+
+inst_46:
+// rs1_val == 131072, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x20000; immval:0x12
+TEST_CI_OP( c.slli, x10, 0x0, 0x20000, 0x12, x1, 184, x2)
+
+inst_47:
+// rs1_val == 65536, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x10000; immval:0xb
+TEST_CI_OP( c.slli, x10, 0x8000000, 0x10000, 0xb, x1, 188, x2)
+
+inst_48:
+// rs1_val == 32768, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x8000; immval:0x1
+TEST_CI_OP( c.slli, x10, 0x10000, 0x8000, 0x1, x1, 192, x2)
+
+inst_49:
+// rs1_val == 16384, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x4000; immval:0x1e
+TEST_CI_OP( c.slli, x10, 0x0, 0x4000, 0x1e, x1, 196, x2)
+
+inst_50:
+// rs1_val == 8192, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x2000; immval:0x1
+TEST_CI_OP( c.slli, x10, 0x4000, 0x2000, 0x1, x1, 200, x2)
+
+inst_51:
+// rs1_val == 4096, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x1000; immval:0x9
+TEST_CI_OP( c.slli, x10, 0x200000, 0x1000, 0x9, x1, 204, x2)
+
+inst_52:
+// rs1_val == 2048, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x800; immval:0x11
+TEST_CI_OP( c.slli, x10, 0x10000000, 0x800, 0x11, x1, 208, x2)
+
+inst_53:
+// rs1_val == 1024, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x400; immval:0x1d
+TEST_CI_OP( c.slli, x10, 0x0, 0x400, 0x1d, x1, 212, x2)
+
+inst_54:
+// rs1_val == 512, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x200; immval:0xd
+TEST_CI_OP( c.slli, x10, 0x400000, 0x200, 0xd, x1, 216, x2)
+
+inst_55:
+// rs1_val == 256, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x100; immval:0x12
+TEST_CI_OP( c.slli, x10, 0x4000000, 0x100, 0x12, x1, 220, x2)
+
+inst_56:
+// rs1_val == 128, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x80; immval:0x6
+TEST_CI_OP( c.slli, x10, 0x2000, 0x80, 0x6, x1, 224, x2)
+
+inst_57:
+// rs1_val == 64, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x40; immval:0x9
+TEST_CI_OP( c.slli, x10, 0x8000, 0x40, 0x9, x1, 228, x2)
+
+inst_58:
+// rs1_val == 32, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x20; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x0, 0x20, 0x1b, x1, 232, x2)
+
+inst_59:
+// rs1_val == 16, rs1_val == imm_val and imm_val != 0  and imm_val < xlen, imm_val == 16
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x10; immval:0x10
+TEST_CI_OP( c.slli, x10, 0x100000, 0x10, 0x10, x1, 236, x2)
+
+inst_60:
+// rs1_val == 8, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x8; immval:0x13
+TEST_CI_OP( c.slli, x10, 0x400000, 0x8, 0x13, x1, 240, x2)
+
+inst_61:
+// rs1_val == 4, rs1_val==4
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x4; immval:0x15
+TEST_CI_OP( c.slli, x10, 0x800000, 0x4, 0x15, x1, 244, x2)
+
+inst_62:
+// rs1_val == 2, rs1_val==2
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x2; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x10000000, 0x2, 0x1b, x1, 248, x2)
+
+inst_63:
+// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x1; immval:0x13
+TEST_CI_OP( c.slli, x10, 0x80000, 0x1, 0x13, x1, 252, x2)
+
+inst_64:
+// imm_val == 8, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x400000; immval:0x8
+TEST_CI_OP( c.slli, x10, 0x40000000, 0x400000, 0x8, x1, 256, x2)
+
+inst_65:
+// imm_val == 4, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x8001; immval:0x4
+TEST_CI_OP( c.slli, x10, 0xfff7fff0, -0x8001, 0x4, x1, 260, x2)
+
+inst_66:
+// rs1_val==46341, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0xb505; immval:0xf
+TEST_CI_OP( c.slli, x10, 0x5a828000, 0xb505, 0xf, x1, 264, x2)
+
+inst_67:
+// rs1_val==-46339, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb503; immval:0xa
+TEST_CI_OP( c.slli, x10, 0xfd2bf400, -0xb503, 0xa, x1, 268, x2)
+
+inst_68:
+// rs1_val==1717986919, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666667; immval:0x1e
+TEST_CI_OP( c.slli, x10, 0xc0000000, 0x66666667, 0x1e, x1, 272, x2)
+
+inst_69:
+// rs1_val==858993460, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333334; immval:0x4
+TEST_CI_OP( c.slli, x10, 0x33333340, 0x33333334, 0x4, x1, 276, x2)
+
+inst_70:
+// rs1_val==6, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x6; immval:0x3
+TEST_CI_OP( c.slli, x10, 0x30, 0x6, 0x3, x1, 280, x2)
+
+inst_71:
+// rs1_val==-1431655765, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x17
+TEST_CI_OP( c.slli, x10, 0x55800000, -0x55555555, 0x17, x1, 284, x2)
+
+inst_72:
+// rs1_val==1431655766, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555556; immval:0x8
+TEST_CI_OP( c.slli, x10, 0x55555600, 0x55555556, 0x8, x1, 288, x2)
+
+inst_73:
+// rs1_val==46339, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0xb503; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x18000000, 0xb503, 0x1b, x1, 292, x2)
+
+inst_74:
+// rs1_val==3, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x3; immval:0x1b
+TEST_CI_OP( c.slli, x10, 0x18000000, 0x3, 0x1b, x1, 296, x2)
+
+inst_75:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x3
+TEST_CI_OP( c.slli, x10, 0x55555550, -0x55555556, 0x3, x1, 300, x2)
+
+inst_76:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555555; immval:0x4
+TEST_CI_OP( c.slli, x10, 0x55555550, 0x55555555, 0x4, x1, 304, x2)
+
+inst_77:
+// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x0; immval:0x15
+TEST_CI_OP( c.slli, x10, 0x0, 0x0, 0x15, x1, 308, x2)
+
+inst_78:
+// rs1_val==1717986917, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
+TEST_CI_OP( c.slli, x10, 0xcccccca0, 0x66666665, 0x5, x1, 312, x2)
+
+inst_79:
+// rs1_val==858993458, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333332; immval:0x10
+TEST_CI_OP( c.slli, x10, 0x33320000, 0x33333332, 0x10, x1, 316, x2)
+
+inst_80:
+// rs1_val==1431655764, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x55555554; immval:0x17
+TEST_CI_OP( c.slli, x10, 0xaa000000, 0x55555554, 0x17, x1, 320, x2)
+
+inst_81:
+// rs1_val==46340, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0xb504; immval:0x6
+TEST_CI_OP( c.slli, x10, 0x2d4100, 0xb504, 0x6, x1, 324, x2)
+
+inst_82:
+// rs1_val==-46340, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:-0xb504; immval:0xa
+TEST_CI_OP( c.slli, x10, 0xfd2bf000, -0xb504, 0xa, x1, 328, x2)
+
+inst_83:
+// rs1_val==1717986918, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x66666666; immval:0x12
+TEST_CI_OP( c.slli, x10, 0x99980000, 0x66666666, 0x12, x1, 332, x2)
+
+inst_84:
+// rs1_val==858993459, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1
+TEST_CI_OP( c.slli, x10, 0x66666666, 0x33333333, 0x1, x1, 336, x2)
+
+inst_85:
+// rs1_val==5, 
+// opcode:c.slli; op1:x10; dest:x10 op1val:0x5; immval:0x4
+TEST_CI_OP( c.slli, x10, 0x50, 0x5, 0x4, x1, 340, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 86*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S
new file mode 100644
index 000000000..36fd20f35
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrai-01.S
@@ -0,0 +1,495 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.srai instruction of the RISC-V C extension for the csrai covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrai)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x10, rs1_val < 0 and imm_val < xlen, rs1_val == -1431655766, rs1_val==-1431655766
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555556; immval:0xe
+TEST_CI_OP( c.srai, x10, 0xfffeaaaa, -0x55555556, 0xe, x1, 0, x2)
+
+inst_1:
+// rs1==x9, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
+// opcode:c.srai; op1:x9; dest:x9 op1val:0x7fffffff; immval:0x9
+TEST_CI_OP( c.srai, x9, 0x3fffff, 0x7fffffff, 0x9, x1, 4, x2)
+
+inst_2:
+// rs1==x11, rs1_val == -1073741825, 
+// opcode:c.srai; op1:x11; dest:x11 op1val:-0x40000001; immval:0x5
+TEST_CI_OP( c.srai, x11, 0xfdffffff, -0x40000001, 0x5, x1, 8, x2)
+
+inst_3:
+// rs1==x12, rs1_val == -536870913, imm_val == 4
+// opcode:c.srai; op1:x12; dest:x12 op1val:-0x20000001; immval:0x4
+TEST_CI_OP( c.srai, x12, 0xfdffffff, -0x20000001, 0x4, x1, 12, x2)
+
+inst_4:
+// rs1==x14, rs1_val == -268435457, imm_val == 21
+// opcode:c.srai; op1:x14; dest:x14 op1val:-0x10000001; immval:0x15
+TEST_CI_OP( c.srai, x14, 0xffffff7f, -0x10000001, 0x15, x1, 16, x2)
+
+inst_5:
+// rs1==x8, rs1_val == -134217729, 
+// opcode:c.srai; op1:x8; dest:x8 op1val:-0x8000001; immval:0x13
+TEST_CI_OP( c.srai, x8, 0xfffffeff, -0x8000001, 0x13, x1, 20, x2)
+
+inst_6:
+// rs1==x13, rs1_val == -67108865, 
+// opcode:c.srai; op1:x13; dest:x13 op1val:-0x4000001; immval:0xc
+TEST_CI_OP( c.srai, x13, 0xffffbfff, -0x4000001, 0xc, x1, 24, x2)
+
+inst_7:
+// rs1==x15, rs1_val == -33554433, imm_val == 29
+// opcode:c.srai; op1:x15; dest:x15 op1val:-0x2000001; immval:0x1d
+TEST_CI_OP( c.srai, x15, 0xffffffff, -0x2000001, 0x1d, x1, 28, x2)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1000001; immval:0xd
+TEST_CI_OP( c.srai, x10, 0xfffff7ff, -0x1000001, 0xd, x1, 32, x2)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x800001; immval:0x3
+TEST_CI_OP( c.srai, x10, 0xffefffff, -0x800001, 0x3, x1, 36, x2)
+
+inst_10:
+// rs1_val == -4194305, imm_val == 10
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x400001; immval:0xa
+TEST_CI_OP( c.srai, x10, 0xffffefff, -0x400001, 0xa, x1, 40, x2)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x200001; immval:0xd
+TEST_CI_OP( c.srai, x10, 0xfffffeff, -0x200001, 0xd, x1, 44, x2)
+
+inst_12:
+// rs1_val == -1048577, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x100001; immval:0xd
+TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x100001, 0xd, x1, 48, x2)
+
+inst_13:
+// rs1_val == -524289, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80001; immval:0x5
+TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x80001, 0x5, x1, 52, x2)
+
+inst_14:
+// rs1_val == -262145, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x40001; immval:0x4
+TEST_CI_OP( c.srai, x10, 0xffffbfff, -0x40001, 0x4, x1, 56, x2)
+
+inst_15:
+// rs1_val == -131073, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x20001; immval:0x1d
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x20001, 0x1d, x1, 60, x2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x10001; immval:0x15
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x10001, 0x15, x1, 64, x2)
+
+inst_17:
+// rs1_val == -32769, imm_val == 2
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x8001; immval:0x2
+TEST_CI_OP( c.srai, x10, 0xffffdfff, -0x8001, 0x2, x1, 68, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x4001; immval:0x7
+TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x4001, 0x7, x1, 72, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2001; immval:0x12
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2001, 0x12, x1, 76, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x1001; immval:0x6
+TEST_CI_OP( c.srai, x10, 0xffffffbf, -0x1001, 0x6, x1, 80, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x13
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x13, x1, 84, x2)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x401; immval:0x3
+TEST_CI_OP( c.srai, x10, 0xffffff7f, -0x401, 0x3, x1, 88, x2)
+
+inst_23:
+// rs1_val == -513, imm_val == 15
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x201; immval:0xf
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x201, 0xf, x1, 92, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x101; immval:0x7
+TEST_CI_OP( c.srai, x10, 0xfffffffd, -0x101, 0x7, x1, 96, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x81; immval:0xa
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x81, 0xa, x1, 100, x2)
+
+inst_26:
+// rs1_val == -65, imm_val == 23
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x41; immval:0x17
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x41, 0x17, x1, 104, x2)
+
+inst_27:
+// rs1_val == -33, imm_val == 30
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x21; immval:0x1e
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x21, 0x1e, x1, 108, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x11; immval:0x1e
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x11, 0x1e, x1, 112, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x9; immval:0x7
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x9, 0x7, x1, 116, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x5; immval:0x9
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x5, 0x9, x1, 120, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x3; immval:0x13
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x3, 0x13, x1, 124, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x2; immval:0x17
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x2, 0x17, x1, 128, x2)
+
+inst_33:
+// imm_val == 27, rs1_val == 32
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x20; immval:0x1b
+TEST_CI_OP( c.srai, x10, 0x0, 0x20, 0x1b, x1, 132, x2)
+
+inst_34:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x80000000; immval:0x12
+TEST_CI_OP( c.srai, x10, 0xffffe000, -0x80000000, 0x12, x1, 136, x2)
+
+inst_35:
+// rs1_val == 1073741824, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000000; immval:0x11
+TEST_CI_OP( c.srai, x10, 0x2000, 0x40000000, 0x11, x1, 140, x2)
+
+inst_36:
+// rs1_val == 536870912, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000000; immval:0x1b
+TEST_CI_OP( c.srai, x10, 0x4, 0x20000000, 0x1b, x1, 144, x2)
+
+inst_37:
+// rs1_val == 268435456, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000000; immval:0x15
+TEST_CI_OP( c.srai, x10, 0x80, 0x10000000, 0x15, x1, 148, x2)
+
+inst_38:
+// rs1_val == 134217728, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000000; immval:0x12
+TEST_CI_OP( c.srai, x10, 0x200, 0x8000000, 0x12, x1, 152, x2)
+
+inst_39:
+// rs1_val == 67108864, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000000; immval:0x15
+TEST_CI_OP( c.srai, x10, 0x20, 0x4000000, 0x15, x1, 156, x2)
+
+inst_40:
+// rs1_val == 33554432, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000000; immval:0x4
+TEST_CI_OP( c.srai, x10, 0x200000, 0x2000000, 0x4, x1, 160, x2)
+
+inst_41:
+// rs1_val == 16777216, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000000; immval:0x1e
+TEST_CI_OP( c.srai, x10, 0x0, 0x1000000, 0x1e, x1, 164, x2)
+
+inst_42:
+// rs1_val == 8388608, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x800000; immval:0x1e
+TEST_CI_OP( c.srai, x10, 0x0, 0x800000, 0x1e, x1, 168, x2)
+
+inst_43:
+// rs1_val == 4194304, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x400000; immval:0xd
+TEST_CI_OP( c.srai, x10, 0x200, 0x400000, 0xd, x1, 172, x2)
+
+inst_44:
+// rs1_val == 2097152, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x200000; immval:0xd
+TEST_CI_OP( c.srai, x10, 0x100, 0x200000, 0xd, x1, 176, x2)
+
+inst_45:
+// rs1_val == 1048576, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x100000; immval:0x13
+TEST_CI_OP( c.srai, x10, 0x2, 0x100000, 0x13, x1, 180, x2)
+
+inst_46:
+// rs1_val == 524288, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x80000; immval:0x9
+TEST_CI_OP( c.srai, x10, 0x400, 0x80000, 0x9, x1, 184, x2)
+
+inst_47:
+// rs1_val == 262144, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x40000; immval:0x13
+TEST_CI_OP( c.srai, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x20000; immval:0x4
+TEST_CI_OP( c.srai, x10, 0x2000, 0x20000, 0x4, x1, 192, x2)
+
+inst_49:
+// rs1_val == 65536, imm_val == 8
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x10000; immval:0x8
+TEST_CI_OP( c.srai, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x8000; immval:0x5
+TEST_CI_OP( c.srai, x10, 0x400, 0x8000, 0x5, x1, 200, x2)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x4000; immval:0x17
+TEST_CI_OP( c.srai, x10, 0x0, 0x4000, 0x17, x1, 204, x2)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x2000; immval:0x5
+TEST_CI_OP( c.srai, x10, 0x100, 0x2000, 0x5, x1, 208, x2)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x1000; immval:0x17
+TEST_CI_OP( c.srai, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x800; immval:0xa
+TEST_CI_OP( c.srai, x10, 0x2, 0x800, 0xa, x1, 216, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x400; immval:0x1e
+TEST_CI_OP( c.srai, x10, 0x0, 0x400, 0x1e, x1, 220, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x200; immval:0xb
+TEST_CI_OP( c.srai, x10, 0x0, 0x200, 0xb, x1, 224, x2)
+
+inst_57:
+// rs1_val == 256, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x100; immval:0x1f
+TEST_CI_OP( c.srai, x10, 0x0, 0x100, 0x1f, x1, 228, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x80; immval:0x3
+TEST_CI_OP( c.srai, x10, 0x10, 0x80, 0x3, x1, 232, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x40; immval:0x1b
+TEST_CI_OP( c.srai, x10, 0x0, 0x40, 0x1b, x1, 236, x2)
+
+inst_60:
+// rs1_val == 16, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x10; immval:0x6
+TEST_CI_OP( c.srai, x10, 0x0, 0x10, 0x6, x1, 240, x2)
+
+inst_61:
+// rs1_val == 8, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x8; immval:0x11
+TEST_CI_OP( c.srai, x10, 0x0, 0x8, 0x11, x1, 244, x2)
+
+inst_62:
+// rs1_val == 4, rs1_val==4
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x4; immval:0x13
+TEST_CI_OP( c.srai, x10, 0x0, 0x4, 0x13, x1, 248, x2)
+
+inst_63:
+// rs1_val == 2, rs1_val==2
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x2; immval:0x4
+TEST_CI_OP( c.srai, x10, 0x0, 0x2, 0x4, x1, 252, x2)
+
+inst_64:
+// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x1; immval:0x1f
+TEST_CI_OP( c.srai, x10, 0x0, 0x1, 0x1f, x1, 256, x2)
+
+inst_65:
+// imm_val == 16, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x801; immval:0x10
+TEST_CI_OP( c.srai, x10, 0xffffffff, -0x801, 0x10, x1, 260, x2)
+
+inst_66:
+// imm_val == 1, rs1_val == 1431655765, rs1_val==1431655765
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555555; immval:0x1
+TEST_CI_OP( c.srai, x10, 0x2aaaaaaa, 0x55555555, 0x1, x1, 264, x2)
+
+inst_67:
+// rs1_val==46341, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0xb505; immval:0xd
+TEST_CI_OP( c.srai, x10, 0x5, 0xb505, 0xd, x1, 268, x2)
+
+inst_68:
+// rs1_val==-46339, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb503; immval:0x5
+TEST_CI_OP( c.srai, x10, 0xfffffa57, -0xb503, 0x5, x1, 272, x2)
+
+inst_69:
+// rs1_val==1717986919, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666667; immval:0x15
+TEST_CI_OP( c.srai, x10, 0x333, 0x66666667, 0x15, x1, 276, x2)
+
+inst_70:
+// rs1_val==858993460, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333334; immval:0x17
+TEST_CI_OP( c.srai, x10, 0x66, 0x33333334, 0x17, x1, 280, x2)
+
+inst_71:
+// rs1_val==6, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x6; immval:0x3
+TEST_CI_OP( c.srai, x10, 0x0, 0x6, 0x3, x1, 284, x2)
+
+inst_72:
+// rs1_val==3, rs1_val == imm_val and imm_val != 0  and imm_val < xlen
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x3; immval:0x3
+TEST_CI_OP( c.srai, x10, 0x0, 0x3, 0x3, x1, 288, x2)
+
+inst_73:
+// rs1_val == 0 and imm_val != 0 and imm_val < xlen, rs1_val==0
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x0; immval:0x12
+TEST_CI_OP( c.srai, x10, 0x0, 0x0, 0x12, x1, 292, x2)
+
+inst_74:
+// rs1_val==-1431655765, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0x55555555; immval:0x6
+TEST_CI_OP( c.srai, x10, 0xfeaaaaaa, -0x55555555, 0x6, x1, 296, x2)
+
+inst_75:
+// rs1_val==1431655766, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555556; immval:0x11
+TEST_CI_OP( c.srai, x10, 0x2aaa, 0x55555556, 0x11, x1, 300, x2)
+
+inst_76:
+// rs1_val==46339, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0xb503; immval:0xe
+TEST_CI_OP( c.srai, x10, 0x2, 0xb503, 0xe, x1, 304, x2)
+
+inst_77:
+// rs1_val==1717986917, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666665; immval:0x5
+TEST_CI_OP( c.srai, x10, 0x3333333, 0x66666665, 0x5, x1, 308, x2)
+
+inst_78:
+// rs1_val==858993458, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333332; immval:0x8
+TEST_CI_OP( c.srai, x10, 0x333333, 0x33333332, 0x8, x1, 312, x2)
+
+inst_79:
+// rs1_val==1431655764, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x55555554; immval:0x8
+TEST_CI_OP( c.srai, x10, 0x555555, 0x55555554, 0x8, x1, 316, x2)
+
+inst_80:
+// rs1_val==46340, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0xb504; immval:0x1f
+TEST_CI_OP( c.srai, x10, 0x0, 0xb504, 0x1f, x1, 320, x2)
+
+inst_81:
+// rs1_val==-46340, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:-0xb504; immval:0x8
+TEST_CI_OP( c.srai, x10, 0xffffff4a, -0xb504, 0x8, x1, 324, x2)
+
+inst_82:
+// rs1_val==1717986918, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x66666666; immval:0xd
+TEST_CI_OP( c.srai, x10, 0x33333, 0x66666666, 0xd, x1, 328, x2)
+
+inst_83:
+// rs1_val==858993459, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x33333333; immval:0x17
+TEST_CI_OP( c.srai, x10, 0x66, 0x33333333, 0x17, x1, 332, x2)
+
+inst_84:
+// rs1_val==5, 
+// opcode:c.srai; op1:x10; dest:x10 op1val:0x5; immval:0x1
+TEST_CI_OP( c.srai, x10, 0x2, 0x5, 0x1, x1, 336, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 85*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S
new file mode 100644
index 000000000..63505ca17
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csrli-01.S
@@ -0,0 +1,505 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.srli instruction of the RISC-V C extension for the csrli covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csrli)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1==x15, rs1_val < 0 and imm_val < xlen, rs1_val == -2
+// opcode:c.srli; op1:x15; dest:x15 op1val:-0x2; immval:0xe
+TEST_CI_OP( c.srli, x15, 0x3ffff, -0x2, 0xe, x1, 0, x2)
+
+inst_1:
+// rs1==x8, rs1_val == 2147483647, rs1_val > 0 and imm_val < xlen, rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen
+// opcode:c.srli; op1:x8; dest:x8 op1val:0x7fffffff; immval:0x7
+TEST_CI_OP( c.srli, x8, 0xffffff, 0x7fffffff, 0x7, x1, 4, x2)
+
+inst_2:
+// rs1==x11, rs1_val == -1073741825, imm_val == 15
+// opcode:c.srli; op1:x11; dest:x11 op1val:-0x40000001; immval:0xf
+TEST_CI_OP( c.srli, x11, 0x17fff, -0x40000001, 0xf, x1, 8, x2)
+
+inst_3:
+// rs1==x10, rs1_val == -536870913, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20000001; immval:0xb
+TEST_CI_OP( c.srli, x10, 0x1bffff, -0x20000001, 0xb, x1, 12, x2)
+
+inst_4:
+// rs1==x9, rs1_val == -268435457, 
+// opcode:c.srli; op1:x9; dest:x9 op1val:-0x10000001; immval:0xc
+TEST_CI_OP( c.srli, x9, 0xeffff, -0x10000001, 0xc, x1, 16, x2)
+
+inst_5:
+// rs1==x13, rs1_val == -134217729, imm_val == 4
+// opcode:c.srli; op1:x13; dest:x13 op1val:-0x8000001; immval:0x4
+TEST_CI_OP( c.srli, x13, 0xf7fffff, -0x8000001, 0x4, x1, 20, x2)
+
+inst_6:
+// rs1==x12, rs1_val == -67108865, 
+// opcode:c.srli; op1:x12; dest:x12 op1val:-0x4000001; immval:0x3
+TEST_CI_OP( c.srli, x12, 0x1f7fffff, -0x4000001, 0x3, x1, 24, x2)
+
+inst_7:
+// rs1==x14, rs1_val == -33554433, 
+// opcode:c.srli; op1:x14; dest:x14 op1val:-0x2000001; immval:0x11
+TEST_CI_OP( c.srli, x14, 0x7eff, -0x2000001, 0x11, x1, 28, x2)
+
+inst_8:
+// rs1_val == -16777217, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1000001; immval:0x6
+TEST_CI_OP( c.srli, x10, 0x3fbffff, -0x1000001, 0x6, x1, 32, x2)
+
+inst_9:
+// rs1_val == -8388609, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x800001; immval:0xf
+TEST_CI_OP( c.srli, x10, 0x1feff, -0x800001, 0xf, x1, 36, x2)
+
+inst_10:
+// rs1_val == -4194305, imm_val == 21
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x400001; immval:0x15
+TEST_CI_OP( c.srli, x10, 0x7fd, -0x400001, 0x15, x1, 40, x2)
+
+inst_11:
+// rs1_val == -2097153, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x200001; immval:0x3
+TEST_CI_OP( c.srli, x10, 0x1ffbffff, -0x200001, 0x3, x1, 44, x2)
+
+inst_12:
+// rs1_val == -1048577, imm_val == 2
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x100001; immval:0x2
+TEST_CI_OP( c.srli, x10, 0x3ffbffff, -0x100001, 0x2, x1, 48, x2)
+
+inst_13:
+// rs1_val == -524289, imm_val == 16
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80001; immval:0x10
+TEST_CI_OP( c.srli, x10, 0xfff7, -0x80001, 0x10, x1, 52, x2)
+
+inst_14:
+// rs1_val == -262145, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x40001; immval:0x6
+TEST_CI_OP( c.srli, x10, 0x3ffefff, -0x40001, 0x6, x1, 56, x2)
+
+inst_15:
+// rs1_val == -131073, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x20001; immval:0x10
+TEST_CI_OP( c.srli, x10, 0xfffd, -0x20001, 0x10, x1, 60, x2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x10001; immval:0x9
+TEST_CI_OP( c.srli, x10, 0x7fff7f, -0x10001, 0x9, x1, 64, x2)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x8001; immval:0x9
+TEST_CI_OP( c.srli, x10, 0x7fffbf, -0x8001, 0x9, x1, 68, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x4001; immval:0xc
+TEST_CI_OP( c.srli, x10, 0xffffb, -0x4001, 0xc, x1, 72, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x2001; immval:0xe
+TEST_CI_OP( c.srli, x10, 0x3ffff, -0x2001, 0xe, x1, 76, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x1001; immval:0x5
+TEST_CI_OP( c.srli, x10, 0x7ffff7f, -0x1001, 0x5, x1, 80, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x801; immval:0x15
+TEST_CI_OP( c.srli, x10, 0x7ff, -0x801, 0x15, x1, 84, x2)
+
+inst_22:
+// rs1_val == -1025, imm_val == 29
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x401; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x7, -0x401, 0x1d, x1, 88, x2)
+
+inst_23:
+// rs1_val == -513, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x201; immval:0xc
+TEST_CI_OP( c.srli, x10, 0xfffff, -0x201, 0xc, x1, 92, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x101; immval:0xc
+TEST_CI_OP( c.srli, x10, 0xfffff, -0x101, 0xc, x1, 96, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x7
+TEST_CI_OP( c.srli, x10, 0x1fffffe, -0x81, 0x7, x1, 100, x2)
+
+inst_26:
+// rs1_val == -65, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x41; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x7, -0x41, 0x1d, x1, 104, x2)
+
+inst_27:
+// rs1_val == -33, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x21; immval:0xf
+TEST_CI_OP( c.srli, x10, 0x1ffff, -0x21, 0xf, x1, 108, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x11; immval:0xc
+TEST_CI_OP( c.srli, x10, 0xfffff, -0x11, 0xc, x1, 112, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x9; immval:0x7
+TEST_CI_OP( c.srli, x10, 0x1ffffff, -0x9, 0x7, x1, 116, x2)
+
+inst_30:
+// rs1_val == -5, imm_val == 30
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x5; immval:0x1e
+TEST_CI_OP( c.srli, x10, 0x3, -0x5, 0x1e, x1, 120, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x3; immval:0xb
+TEST_CI_OP( c.srli, x10, 0x1fffff, -0x3, 0xb, x1, 124, x2)
+
+inst_32:
+// imm_val == 23, rs1_val==5
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x5; immval:0x17
+TEST_CI_OP( c.srli, x10, 0x0, 0x5, 0x17, x1, 128, x2)
+
+inst_33:
+// imm_val == 27, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x81; immval:0x1b
+TEST_CI_OP( c.srli, x10, 0x1f, -0x81, 0x1b, x1, 132, x2)
+
+inst_34:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x80000000; immval:0x9
+TEST_CI_OP( c.srli, x10, 0x400000, -0x80000000, 0x9, x1, 136, x2)
+
+inst_35:
+// rs1_val == 1073741824, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000000; immval:0x7
+TEST_CI_OP( c.srli, x10, 0x800000, 0x40000000, 0x7, x1, 140, x2)
+
+inst_36:
+// rs1_val == 536870912, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000000; immval:0x6
+TEST_CI_OP( c.srli, x10, 0x800000, 0x20000000, 0x6, x1, 144, x2)
+
+inst_37:
+// rs1_val == 268435456, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000000; immval:0x9
+TEST_CI_OP( c.srli, x10, 0x80000, 0x10000000, 0x9, x1, 148, x2)
+
+inst_38:
+// rs1_val == 134217728, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000000; immval:0x1e
+TEST_CI_OP( c.srli, x10, 0x0, 0x8000000, 0x1e, x1, 152, x2)
+
+inst_39:
+// rs1_val == 67108864, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000000; immval:0x11
+TEST_CI_OP( c.srli, x10, 0x200, 0x4000000, 0x11, x1, 156, x2)
+
+inst_40:
+// rs1_val == 33554432, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000000; immval:0x15
+TEST_CI_OP( c.srli, x10, 0x10, 0x2000000, 0x15, x1, 160, x2)
+
+inst_41:
+// rs1_val == 16777216, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000000; immval:0x10
+TEST_CI_OP( c.srli, x10, 0x100, 0x1000000, 0x10, x1, 164, x2)
+
+inst_42:
+// rs1_val == 8388608, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x800000; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x0, 0x800000, 0x1d, x1, 168, x2)
+
+inst_43:
+// rs1_val == 4194304, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x400000; immval:0xc
+TEST_CI_OP( c.srli, x10, 0x400, 0x400000, 0xc, x1, 172, x2)
+
+inst_44:
+// rs1_val == 2097152, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x200000; immval:0xc
+TEST_CI_OP( c.srli, x10, 0x200, 0x200000, 0xc, x1, 176, x2)
+
+inst_45:
+// rs1_val == 1048576, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x100000; immval:0x17
+TEST_CI_OP( c.srli, x10, 0x0, 0x100000, 0x17, x1, 180, x2)
+
+inst_46:
+// rs1_val == 524288, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x80000; immval:0x1f
+TEST_CI_OP( c.srli, x10, 0x0, 0x80000, 0x1f, x1, 184, x2)
+
+inst_47:
+// rs1_val == 262144, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x40000; immval:0x13
+TEST_CI_OP( c.srli, x10, 0x0, 0x40000, 0x13, x1, 188, x2)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x20000; immval:0x1f
+TEST_CI_OP( c.srli, x10, 0x0, 0x20000, 0x1f, x1, 192, x2)
+
+inst_49:
+// rs1_val == 65536, imm_val == 8
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x10000; immval:0x8
+TEST_CI_OP( c.srli, x10, 0x100, 0x10000, 0x8, x1, 196, x2)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x8000; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x0, 0x8000, 0x1d, x1, 200, x2)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x4000; immval:0x3
+TEST_CI_OP( c.srli, x10, 0x800, 0x4000, 0x3, x1, 204, x2)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x2000; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x0, 0x2000, 0x1d, x1, 208, x2)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x1000; immval:0x17
+TEST_CI_OP( c.srli, x10, 0x0, 0x1000, 0x17, x1, 212, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x800; immval:0x7
+TEST_CI_OP( c.srli, x10, 0x10, 0x800, 0x7, x1, 216, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x400; immval:0x10
+TEST_CI_OP( c.srli, x10, 0x0, 0x400, 0x10, x1, 220, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x200; immval:0x1d
+TEST_CI_OP( c.srli, x10, 0x0, 0x200, 0x1d, x1, 224, x2)
+
+inst_57:
+// rs1_val == 256, imm_val == 1
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x100; immval:0x1
+TEST_CI_OP( c.srli, x10, 0x80, 0x100, 0x1, x1, 228, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x80; immval:0x7
+TEST_CI_OP( c.srli, x10, 0x1, 0x80, 0x7, x1, 232, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x40; immval:0xd
+TEST_CI_OP( c.srli, x10, 0x0, 0x40, 0xd, x1, 236, x2)
+
+inst_60:
+// rs1_val == 32, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x20; immval:0x1e
+TEST_CI_OP( c.srli, x10, 0x0, 0x20, 0x1e, x1, 240, x2)
+
+inst_61:
+// rs1_val == 16, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x10; immval:0x11
+TEST_CI_OP( c.srli, x10, 0x0, 0x10, 0x11, x1, 244, x2)
+
+inst_62:
+// rs1_val == 8, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x8; immval:0x1b
+TEST_CI_OP( c.srli, x10, 0x0, 0x8, 0x1b, x1, 248, x2)
+
+inst_63:
+// rs1_val == 4, rs1_val==4
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x11
+TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x11, x1, 252, x2)
+
+inst_64:
+// rs1_val == 2, rs1_val==2
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x2; immval:0x15
+TEST_CI_OP( c.srli, x10, 0x0, 0x2, 0x15, x1, 256, x2)
+
+inst_65:
+// rs1_val == 1, rs1_val == 1 and imm_val != 0 and imm_val < xlen
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x1; immval:0x12
+TEST_CI_OP( c.srli, x10, 0x0, 0x1, 0x12, x1, 260, x2)
+
+inst_66:
+// rs1_val==46341, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0xb505; immval:0x10
+TEST_CI_OP( c.srli, x10, 0x0, 0xb505, 0x10, x1, 264, x2)
+
+inst_67:
+// rs1_val==-46339, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb503; immval:0x15
+TEST_CI_OP( c.srli, x10, 0x7ff, -0xb503, 0x15, x1, 268, x2)
+
+inst_68:
+// rs1_val==1717986919, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666667; immval:0x9
+TEST_CI_OP( c.srli, x10, 0x333333, 0x66666667, 0x9, x1, 272, x2)
+
+inst_69:
+// rs1_val==858993460, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333334; immval:0xf
+TEST_CI_OP( c.srli, x10, 0x6666, 0x33333334, 0xf, x1, 276, x2)
+
+inst_70:
+// rs1_val==6, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x6; immval:0x10
+TEST_CI_OP( c.srli, x10, 0x0, 0x6, 0x10, x1, 280, x2)
+
+inst_71:
+// rs1_val==-1431655765, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555555; immval:0x5
+TEST_CI_OP( c.srli, x10, 0x5555555, -0x55555555, 0x5, x1, 284, x2)
+
+inst_72:
+// rs1_val==1431655766, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555556; immval:0xf
+TEST_CI_OP( c.srli, x10, 0xaaaa, 0x55555556, 0xf, x1, 288, x2)
+
+inst_73:
+// rs1_val==46339, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0xb503; immval:0x2
+TEST_CI_OP( c.srli, x10, 0x2d40, 0xb503, 0x2, x1, 292, x2)
+
+inst_74:
+// rs1_val==0, rs1_val == 0 and imm_val != 0 and imm_val < xlen
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xf
+TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xf, x1, 296, x2)
+
+inst_75:
+// rs1_val==3, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x3; immval:0x6
+TEST_CI_OP( c.srli, x10, 0x0, 0x3, 0x6, x1, 300, x2)
+
+inst_76:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0x55555556; immval:0x2
+TEST_CI_OP( c.srli, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 304, x2)
+
+inst_77:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555555; immval:0xb
+TEST_CI_OP( c.srli, x10, 0xaaaaa, 0x55555555, 0xb, x1, 308, x2)
+
+inst_78:
+// imm_val == 10, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x0; immval:0xa
+TEST_CI_OP( c.srli, x10, 0x0, 0x0, 0xa, x1, 312, x2)
+
+inst_79:
+// rs1_val == imm_val and imm_val != 0  and imm_val < xlen, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x4; immval:0x4
+TEST_CI_OP( c.srli, x10, 0x0, 0x4, 0x4, x1, 316, x2)
+
+inst_80:
+// rs1_val==1717986917, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666665; immval:0xe
+TEST_CI_OP( c.srli, x10, 0x19999, 0x66666665, 0xe, x1, 320, x2)
+
+inst_81:
+// rs1_val==858993458, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333332; immval:0x6
+TEST_CI_OP( c.srli, x10, 0xcccccc, 0x33333332, 0x6, x1, 324, x2)
+
+inst_82:
+// rs1_val==1431655764, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x55555554; immval:0x3
+TEST_CI_OP( c.srli, x10, 0xaaaaaaa, 0x55555554, 0x3, x1, 328, x2)
+
+inst_83:
+// rs1_val==46340, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0xb504; immval:0x11
+TEST_CI_OP( c.srli, x10, 0x0, 0xb504, 0x11, x1, 332, x2)
+
+inst_84:
+// rs1_val==-46340, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:-0xb504; immval:0x5
+TEST_CI_OP( c.srli, x10, 0x7fffa57, -0xb504, 0x5, x1, 336, x2)
+
+inst_85:
+// rs1_val==1717986918, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x66666666; immval:0x3
+TEST_CI_OP( c.srli, x10, 0xccccccc, 0x66666666, 0x3, x1, 340, x2)
+
+inst_86:
+// rs1_val==858993459, 
+// opcode:c.srli; op1:x10; dest:x10 op1val:0x33333333; immval:0x1f
+TEST_CI_OP( c.srli, x10, 0x0, 0x33333333, 0x1f, x1, 344, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 87*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S
new file mode 100644
index 000000000..c38bd6537
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csub-01.S
@@ -0,0 +1,2980 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.sub instruction of the RISC-V C extension for the csub covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csub)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x10, rs2==x8, rs1_val == (-2**(xlen-1)), rs1_val == -2147483648, rs2_val < 0, rs2_val == -1431655766
+// opcode: c.sub; op1:x10; op2:x8; op1val:-0x80000000; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x8, 0xd5555556, -0x80000000, -0x55555556, x1, 0, x2)
+
+inst_1:
+// rs1 == rs2, rs1==x15, rs2==x15, rs2_val == 2147483647, rs1_val == -257, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.sub; op1:x15; op2:x15; op1val:-0x101; op2val:-0x101
+TEST_CR_OP( c.sub, x15, x15, 0x0, -0x101, -0x101, x1, 4, x2)
+
+inst_2:
+// rs1==x14, rs2==x10, rs2_val == -1073741825, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: c.sub; op1:x14; op2:x10; op1val:0x7fffffff; op2val:-0x40000001
+TEST_CR_OP( c.sub, x14, x10, 0xc0000000, 0x7fffffff, -0x40000001, x1, 8, x2)
+
+inst_3:
+// rs1==x11, rs2==x9, rs2_val == -536870913, 
+// opcode: c.sub; op1:x11; op2:x9; op1val:-0xa; op2val:-0x20000001
+TEST_CR_OP( c.sub, x11, x9, 0x1ffffff7, -0xa, -0x20000001, x1, 12, x2)
+
+inst_4:
+// rs1==x13, rs2==x12, rs2_val == -268435457, 
+// opcode: c.sub; op1:x13; op2:x12; op1val:-0xb504; op2val:-0x10000001
+TEST_CR_OP( c.sub, x13, x12, 0xfff4afd, -0xb504, -0x10000001, x1, 16, x2)
+
+inst_5:
+// rs1==x9, rs2==x11, rs2_val == -134217729, 
+// opcode: c.sub; op1:x9; op2:x11; op1val:0x66666665; op2val:-0x8000001
+TEST_CR_OP( c.sub, x9, x11, 0x6e666666, 0x66666665, -0x8000001, x1, 20, x2)
+
+inst_6:
+// rs1==x8, rs2==x13, rs2_val == -67108865, 
+// opcode: c.sub; op1:x8; op2:x13; op1val:-0x7; op2val:-0x4000001
+TEST_CR_OP( c.sub, x8, x13, 0x3fffffa, -0x7, -0x4000001, x1, 24, x2)
+
+inst_7:
+// rs1==x12, rs2==x14, rs2_val == -33554433, rs1_val == -268435457
+// opcode: c.sub; op1:x12; op2:x14; op1val:-0x10000001; op2val:-0x2000001
+TEST_CR_OP( c.sub, x12, x14, 0xf2000000, -0x10000001, -0x2000001, x1, 28, x2)
+
+inst_8:
+// rs2_val == -16777217, rs1_val == -2049
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x801; op2val:-0x1000001
+TEST_CR_OP( c.sub, x10, x11, 0xfff800, -0x801, -0x1000001, x1, 32, x2)
+
+inst_9:
+// rs2_val == -8388609, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x800001
+TEST_CR_OP( c.sub, x10, x11, 0x33b33333, 0x33333332, -0x800001, x1, 36, x2)
+
+inst_10:
+// rs2_val == -4194305, rs1_val == -524289
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x80001; op2val:-0x400001
+TEST_CR_OP( c.sub, x10, x11, 0x380000, -0x80001, -0x400001, x1, 40, x2)
+
+inst_11:
+// rs2_val == -2097153, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x4; op2val:-0x200001
+TEST_CR_OP( c.sub, x10, x11, 0x1ffffd, -0x4, -0x200001, x1, 44, x2)
+
+inst_12:
+// rs2_val == -1048577, rs1_val == -65
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x41; op2val:-0x100001
+TEST_CR_OP( c.sub, x10, x11, 0xfffc0, -0x41, -0x100001, x1, 48, x2)
+
+inst_13:
+// rs2_val == -524289, rs1_val == -129
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x81; op2val:-0x80001
+TEST_CR_OP( c.sub, x10, x11, 0x7ff80, -0x81, -0x80001, x1, 52, x2)
+
+inst_14:
+// rs2_val == -262145, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x8; op2val:-0x40001
+TEST_CR_OP( c.sub, x10, x11, 0x3fff9, -0x8, -0x40001, x1, 56, x2)
+
+inst_15:
+// rs2_val == -131073, rs1_val == 33554432
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2000000; op2val:-0x20001
+TEST_CR_OP( c.sub, x10, x11, 0x2020001, 0x2000000, -0x20001, x1, 60, x2)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x4; op2val:-0x10001
+TEST_CR_OP( c.sub, x10, x11, 0xfffd, -0x4, -0x10001, x1, 64, x2)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3fffffff; op2val:-0x8001
+TEST_CR_OP( c.sub, x10, x11, 0x40008000, 0x3fffffff, -0x8001, x1, 68, x2)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x4001
+TEST_CR_OP( c.sub, x10, x11, 0xffff8afe, -0xb503, -0x4001, x1, 72, x2)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -262145
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x40001; op2val:-0x2001
+TEST_CR_OP( c.sub, x10, x11, 0xfffc2000, -0x40001, -0x2001, x1, 76, x2)
+
+inst_20:
+// rs2_val == -4097, rs1_val == 4
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:-0x1001
+TEST_CR_OP( c.sub, x10, x11, 0x1005, 0x4, -0x1001, x1, 80, x2)
+
+inst_21:
+// rs2_val == -2049, rs1_val == -16385
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x4001; op2val:-0x801
+TEST_CR_OP( c.sub, x10, x11, 0xffffc800, -0x4001, -0x801, x1, 84, x2)
+
+inst_22:
+// rs2_val == -1025, rs1_val == -2097153
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x200001; op2val:-0x401
+TEST_CR_OP( c.sub, x10, x11, 0xffe00400, -0x200001, -0x401, x1, 88, x2)
+
+inst_23:
+// rs2_val == -513, rs1_val == 16777216
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x1000000; op2val:-0x201
+TEST_CR_OP( c.sub, x10, x11, 0x1000201, 0x1000000, -0x201, x1, 92, x2)
+
+inst_24:
+// rs2_val == -257, rs1_val == 256
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x100; op2val:-0x101
+TEST_CR_OP( c.sub, x10, x11, 0x201, 0x100, -0x101, x1, 96, x2)
+
+inst_25:
+// rs2_val == -129, rs1_val == -2
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x2; op2val:-0x81
+TEST_CR_OP( c.sub, x10, x11, 0x7f, -0x2, -0x81, x1, 100, x2)
+
+inst_26:
+// rs2_val == -65, rs1_val == 64
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x40; op2val:-0x41
+TEST_CR_OP( c.sub, x10, x11, 0x81, 0x40, -0x41, x1, 104, x2)
+
+inst_27:
+// rs2_val == -33, rs1_val == -3
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x3; op2val:-0x21
+TEST_CR_OP( c.sub, x10, x11, 0x1e, -0x3, -0x21, x1, 108, x2)
+
+inst_28:
+// rs2_val == -17, rs1_val == -32769
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x8001; op2val:-0x11
+TEST_CR_OP( c.sub, x10, x11, 0xffff8010, -0x8001, -0x11, x1, 112, x2)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x41; op2val:-0x9
+TEST_CR_OP( c.sub, x10, x11, 0xffffffc8, -0x41, -0x9, x1, 116, x2)
+
+inst_30:
+// rs2_val == -5, rs1_val == 32
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x20; op2val:-0x5
+TEST_CR_OP( c.sub, x10, x11, 0x25, 0x20, -0x5, x1, 120, x2)
+
+inst_31:
+// rs2_val == -3, rs1_val == -8193
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x2001; op2val:-0x3
+TEST_CR_OP( c.sub, x10, x11, 0xffffe002, -0x2001, -0x3, x1, 124, x2)
+
+inst_32:
+// rs2_val == -2, rs1_val == -1025
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x401; op2val:-0x2
+TEST_CR_OP( c.sub, x10, x11, 0xfffffc01, -0x401, -0x2, x1, 128, x2)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 64
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x40000001; op2val:0x40
+TEST_CR_OP( c.sub, x10, x11, 0xbfffffbf, -0x40000001, 0x40, x1, 132, x2)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x6
+TEST_CR_OP( c.sub, x10, x11, 0xe0000005, -0x20000001, -0x6, x1, 136, x2)
+
+inst_35:
+// rs1_val == -134217729, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x8000001; op2val:0x7fffffff
+TEST_CR_OP( c.sub, x10, x11, 0x78000000, -0x8000001, 0x7fffffff, x1, 140, x2)
+
+inst_36:
+// rs1_val == -67108865, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x4000001; op2val:-0x21
+TEST_CR_OP( c.sub, x10, x11, 0xfc000020, -0x4000001, -0x21, x1, 144, x2)
+
+inst_37:
+// rs1_val == -33554433, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x2000001; op2val:-0x8
+TEST_CR_OP( c.sub, x10, x11, 0xfe000007, -0x2000001, -0x8, x1, 148, x2)
+
+inst_38:
+// rs1_val == -16777217, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x11
+TEST_CR_OP( c.sub, x10, x11, 0xff000010, -0x1000001, -0x11, x1, 152, x2)
+
+inst_39:
+// rs1_val == -8388609, rs2_val == 2048
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x800001; op2val:0x800
+TEST_CR_OP( c.sub, x10, x11, 0xff7ff7ff, -0x800001, 0x800, x1, 156, x2)
+
+inst_40:
+// rs1_val == -4194305, rs2_val == 1073741824
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x400001; op2val:0x40000000
+TEST_CR_OP( c.sub, x10, x11, 0xbfbfffff, -0x400001, 0x40000000, x1, 160, x2)
+
+inst_41:
+// rs1_val == -1048577, rs2_val == 0
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x100001; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xffefffff, -0x100001, 0x0, x1, 164, x2)
+
+inst_42:
+// rs1_val == -131073, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x20001; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xfffeb503, -0x20001, -0xb504, x1, 168, x2)
+
+inst_43:
+// rs1_val == -65537, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x10001; op2val:-0x101
+TEST_CR_OP( c.sub, x10, x11, 0xffff0100, -0x10001, -0x101, x1, 172, x2)
+
+inst_44:
+// rs1_val == -4097, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x1001; op2val:0x7fffffff
+TEST_CR_OP( c.sub, x10, x11, 0x7ffff000, -0x1001, 0x7fffffff, x1, 176, x2)
+
+inst_45:
+// rs1_val == -513, rs2_val == 67108864
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x201; op2val:0x4000000
+TEST_CR_OP( c.sub, x10, x11, 0xfbfffdff, -0x201, 0x4000000, x1, 180, x2)
+
+inst_46:
+// rs1_val == -33, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x21; op2val:-0x100001
+TEST_CR_OP( c.sub, x10, x11, 0xfffe0, -0x21, -0x100001, x1, 184, x2)
+
+inst_47:
+// rs1_val == -17, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x11; op2val:-0x801
+TEST_CR_OP( c.sub, x10, x11, 0x7f0, -0x11, -0x801, x1, 188, x2)
+
+inst_48:
+// rs1_val == -9, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x9; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xfffffff2, -0x9, 0x5, x1, 192, x2)
+
+inst_49:
+// rs1_val == -5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x5; op2val:-0x6
+TEST_CR_OP( c.sub, x10, x11, 0x1, -0x5, -0x6, x1, 196, x2)
+
+inst_50:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x80000000
+TEST_CR_OP( c.sub, x10, x11, 0x5fffffff, -0x20000001, -0x80000000, x1, 200, x2)
+
+inst_51:
+// rs2_val == 536870912, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x3; op2val:0x20000000
+TEST_CR_OP( c.sub, x10, x11, 0xdffffffd, -0x3, 0x20000000, x1, 204, x2)
+
+inst_52:
+// rs2_val == 268435456, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x10000000
+TEST_CR_OP( c.sub, x10, x11, 0xf000b504, 0xb504, 0x10000000, x1, 208, x2)
+
+inst_53:
+// rs2_val == 134217728, rs1_val == 16384
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4000; op2val:0x8000000
+TEST_CR_OP( c.sub, x10, x11, 0xf8004000, 0x4000, 0x8000000, x1, 212, x2)
+
+inst_54:
+// rs2_val == 33554432, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x20; op2val:0x2000000
+TEST_CR_OP( c.sub, x10, x11, 0xfe000020, 0x20, 0x2000000, x1, 216, x2)
+
+inst_55:
+// rs2_val == 16777216, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x9; op2val:0x1000000
+TEST_CR_OP( c.sub, x10, x11, 0xfefffff7, -0x9, 0x1000000, x1, 220, x2)
+
+inst_56:
+// rs2_val == 8388608, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2000000; op2val:0x800000
+TEST_CR_OP( c.sub, x10, x11, 0x1800000, 0x2000000, 0x800000, x1, 224, x2)
+
+inst_57:
+// rs2_val == 4194304, rs1_val == 4194304
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x400000; op2val:0x400000
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x400000, 0x400000, x1, 228, x2)
+
+inst_58:
+// rs2_val == 2097152, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x20; op2val:0x200000
+TEST_CR_OP( c.sub, x10, x11, 0xffe00020, 0x20, 0x200000, x1, 232, x2)
+
+inst_59:
+// rs2_val == 1048576, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x100000
+TEST_CR_OP( c.sub, x10, x11, 0x66566666, 0x66666666, 0x100000, x1, 236, x2)
+
+inst_60:
+// rs2_val == 524288, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x10001; op2val:0x80000
+TEST_CR_OP( c.sub, x10, x11, 0xfff6ffff, -0x10001, 0x80000, x1, 240, x2)
+
+inst_61:
+// rs2_val == 262144, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x9; op2val:0x40000
+TEST_CR_OP( c.sub, x10, x11, 0xfffc0009, 0x9, 0x40000, x1, 244, x2)
+
+inst_62:
+// rs2_val == 131072, rs1_val == 0
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x20000
+TEST_CR_OP( c.sub, x10, x11, 0xfffe0000, 0x0, 0x20000, x1, 248, x2)
+
+inst_63:
+// rs2_val == 65536, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x9; op2val:0x10000
+TEST_CR_OP( c.sub, x10, x11, 0xffff0009, 0x9, 0x10000, x1, 252, x2)
+
+inst_64:
+// rs2_val == 32768, rs1_val == 512
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x200; op2val:0x8000
+TEST_CR_OP( c.sub, x10, x11, 0xffff8200, 0x200, 0x8000, x1, 256, x2)
+
+inst_65:
+// rs2_val == 16384, rs1_val == -1431655766
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4000
+TEST_CR_OP( c.sub, x10, x11, 0xaaaa6aaa, -0x55555556, 0x4000, x1, 260, x2)
+
+inst_66:
+// rs2_val == 8192, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x9; op2val:0x2000
+TEST_CR_OP( c.sub, x10, x11, 0xffffdff7, -0x9, 0x2000, x1, 264, x2)
+
+inst_67:
+// rs2_val == 4096, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x1; op2val:0x1000
+TEST_CR_OP( c.sub, x10, x11, 0xffffefff, -0x1, 0x1000, x1, 268, x2)
+
+inst_68:
+// rs2_val == 1024, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x400
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaa6aa, -0x55555556, 0x400, x1, 272, x2)
+
+inst_69:
+// rs2_val == 512, rs1_val == 1024
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x400; op2val:0x200
+TEST_CR_OP( c.sub, x10, x11, 0x200, 0x400, 0x200, x1, 276, x2)
+
+inst_70:
+// rs2_val == 256, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x2001; op2val:0x100
+TEST_CR_OP( c.sub, x10, x11, 0xffffdeff, -0x2001, 0x100, x1, 280, x2)
+
+inst_71:
+// rs2_val == 128, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x401; op2val:0x80
+TEST_CR_OP( c.sub, x10, x11, 0xfffffb7f, -0x401, 0x80, x1, 284, x2)
+
+inst_72:
+// rs2_val == 32, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x8001; op2val:0x20
+TEST_CR_OP( c.sub, x10, x11, 0xffff7fdf, -0x8001, 0x20, x1, 288, x2)
+
+inst_73:
+// rs2_val == 16, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x10
+TEST_CR_OP( c.sub, x10, x11, 0xfffffff0, 0x0, 0x10, x1, 292, x2)
+
+inst_74:
+// rs2_val == 8, rs1_val == 1431655765
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x8
+TEST_CR_OP( c.sub, x10, x11, 0x5555554d, 0x55555555, 0x8, x1, 296, x2)
+
+inst_75:
+// rs2_val == 4, rs1_val==-46340 and rs2_val==4
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af8, -0xb504, 0x4, x1, 300, x2)
+
+inst_76:
+// rs2_val == 2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x1000001; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xfefffffd, -0x1000001, 0x2, x1, 304, x2)
+
+inst_77:
+// rs2_val == 1, rs1_val == 268435456
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x10000000; op2val:0x1
+TEST_CR_OP( c.sub, x10, x11, 0xfffffff, 0x10000000, 0x1, x1, 308, x2)
+
+inst_78:
+// rs1_val == 1073741824, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x40000000; op2val:0x20
+TEST_CR_OP( c.sub, x10, x11, 0x3fffffe0, 0x40000000, 0x20, x1, 312, x2)
+
+inst_79:
+// rs1_val == 536870912, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x20000000; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x1ffffffe, 0x20000000, 0x2, x1, 316, x2)
+
+inst_80:
+// rs1_val == 134217728, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x8000000; op2val:0x20000
+TEST_CR_OP( c.sub, x10, x11, 0x7fe0000, 0x8000000, 0x20000, x1, 320, x2)
+
+inst_81:
+// rs1_val == 67108864, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4000000; op2val:-0x11
+TEST_CR_OP( c.sub, x10, x11, 0x4000011, 0x4000000, -0x11, x1, 324, x2)
+
+inst_82:
+// rs1_val == 8388608, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x800000; op2val:0x8000000
+TEST_CR_OP( c.sub, x10, x11, 0xf8800000, 0x800000, 0x8000000, x1, 328, x2)
+
+inst_83:
+// rs1_val == 2097152, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x200000; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x200000, 0x200000, 0x0, x1, 332, x2)
+
+inst_84:
+// rs1_val == 1048576, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x100000; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xffffc, 0x100000, 0x4, x1, 336, x2)
+
+inst_85:
+// rs1_val == 524288, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x80000; op2val:0x10000000
+TEST_CR_OP( c.sub, x10, x11, 0xf0080000, 0x80000, 0x10000000, x1, 340, x2)
+
+inst_86:
+// rs1_val == 262144, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x40000; op2val:-0x1
+TEST_CR_OP( c.sub, x10, x11, 0x40001, 0x40000, -0x1, x1, 344, x2)
+
+inst_87:
+// rs1_val == 131072, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x20000; op2val:-0x201
+TEST_CR_OP( c.sub, x10, x11, 0x20201, 0x20000, -0x201, x1, 348, x2)
+
+inst_88:
+// rs1_val == 65536, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x10000; op2val:0x20000000
+TEST_CR_OP( c.sub, x10, x11, 0xe0010000, 0x10000, 0x20000000, x1, 352, x2)
+
+inst_89:
+// rs1_val == 32768, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x8000; op2val:-0x8
+TEST_CR_OP( c.sub, x10, x11, 0x8008, 0x8000, -0x8, x1, 356, x2)
+
+inst_90:
+// rs1_val == 8192, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2000; op2val:-0x10000001
+TEST_CR_OP( c.sub, x10, x11, 0x10002001, 0x2000, -0x10000001, x1, 360, x2)
+
+inst_91:
+// rs1_val == 4096, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x1000; op2val:-0x10000001
+TEST_CR_OP( c.sub, x10, x11, 0x10001001, 0x1000, -0x10000001, x1, 364, x2)
+
+inst_92:
+// rs1_val == 2048, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x800; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x7fb, 0x800, 0x5, x1, 368, x2)
+
+inst_93:
+// rs1_val == 128, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x80; op2val:-0x8
+TEST_CR_OP( c.sub, x10, x11, 0x88, 0x80, -0x8, x1, 372, x2)
+
+inst_94:
+// rs1_val == 16, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x10; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b0d, 0x10, 0xb503, x1, 376, x2)
+
+inst_95:
+// rs1_val == 8, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x8; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x3, 0x8, 0x5, x1, 380, x2)
+
+inst_96:
+// rs1_val == 2, rs1_val==2 and rs2_val==2
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x2, 0x2, x1, 384, x2)
+
+inst_97:
+// rs1_val == 1, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x1; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999b, 0x1, 0x66666666, x1, 388, x2)
+
+inst_98:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0xb505, 0xb505, x1, 392, x2)
+
+inst_99:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x16a08, 0xb505, -0xb503, x1, 396, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9e, 0xb505, 0x66666667, x1, 400, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d1, 0xb505, 0x33333334, x1, 404, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xb4ff, 0xb505, 0x6, x1, 408, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55560a5a, 0xb505, -0x55555555, x1, 412, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5faf, 0xb505, 0x55555556, x1, 416, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xb501, 0xb505, 0x4, x1, 420, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0xb505, 0xb503, x1, 424, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xb505, 0xb505, 0x0, x1, 428, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x999a4ea0, 0xb505, 0x66666665, x1, 432, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d3, 0xb505, 0x33333332, x1, 436, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fb1, 0xb505, 0x55555554, x1, 440, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xb503, 0xb505, 0x2, x1, 444, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0xb505, 0xb504, x1, 448, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x16a09, 0xb505, -0xb504, x1, 452, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9f, 0xb505, 0x66666666, x1, 456, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d2, 0xb505, 0x33333333, x1, 460, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xb500, 0xb505, 0x5, x1, 464, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55560a5b, 0xb505, -0x55555556, x1, 468, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fb0, 0xb505, 0x55555555, x1, 472, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb505; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xb502, 0xb505, 0x3, x1, 476, x2)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95f8, -0xb503, 0xb505, x1, 480, x2)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x0, -0xb503, -0xb503, x1, 484, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9998e496, -0xb503, 0x66666667, x1, 488, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17c9, -0xb503, 0x33333334, x1, 492, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af7, -0xb503, 0x6, x1, 496, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x5554a052, -0xb503, -0x55555555, x1, 500, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a7, -0xb503, 0x55555556, x1, 504, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af9, -0xb503, 0x4, x1, 508, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95fa, -0xb503, 0xb503, x1, 512, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 516, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9998e498, -0xb503, 0x66666665, x1, 520, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17cb, -0xb503, 0x33333332, x1, 524, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a9, -0xb503, 0x55555554, x1, 528, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afb, -0xb503, 0x2, x1, 532, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95f9, -0xb503, 0xb504, x1, 536, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x1, -0xb503, -0xb504, x1, 540, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9998e497, -0xb503, 0x66666666, x1, 544, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17ca, -0xb503, 0x33333333, x1, 548, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af8, -0xb503, 0x5, x1, 552, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x5554a053, -0xb503, -0x55555556, x1, 556, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a8, -0xb503, 0x55555555, x1, 560, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb503; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afa, -0xb503, 0x3, x1, 564, x2)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x6665b162, 0x66666667, 0xb505, x1, 568, x2)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x66671b6a, 0x66666667, -0xb503, x1, 572, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x66666667, 0x66666667, x1, 576, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x33333333, 0x66666667, 0x33333334, x1, 580, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x66666661, 0x66666667, 0x6, x1, 584, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbbc, 0x66666667, -0x55555555, x1, 588, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x11111111, 0x66666667, 0x55555556, x1, 592, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x66666663, 0x66666667, 0x4, x1, 596, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x6665b164, 0x66666667, 0xb503, x1, 600, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 604, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x66666667, 0x66666665, x1, 608, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x33333335, 0x66666667, 0x33333332, x1, 612, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x11111113, 0x66666667, 0x55555554, x1, 616, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x66666665, 0x66666667, 0x2, x1, 620, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x6665b163, 0x66666667, 0xb504, x1, 624, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x66671b6b, 0x66666667, -0xb504, x1, 628, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 632, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x33333334, 0x66666667, 0x33333333, x1, 636, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x66666662, 0x66666667, 0x5, x1, 640, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbbd, 0x66666667, -0x55555556, x1, 644, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x11111112, 0x66666667, 0x55555555, x1, 648, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666667; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x66666664, 0x66666667, 0x3, x1, 652, x2)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2f, 0x33333334, 0xb505, x1, 656, x2)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x3333e837, 0x33333334, -0xb503, x1, 660, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccd, 0x33333334, 0x66666667, x1, 664, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x33333334, 0x33333334, x1, 668, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x3333332e, 0x33333334, 0x6, x1, 672, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x88888889, 0x33333334, -0x55555555, x1, 676, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xddddddde, 0x33333334, 0x55555556, x1, 680, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x33333330, 0x33333334, 0x4, x1, 684, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x33327e31, 0x33333334, 0xb503, x1, 688, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 692, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccf, 0x33333334, 0x66666665, x1, 696, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x33333334, 0x33333332, x1, 700, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xdddddde0, 0x33333334, 0x55555554, x1, 704, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x33333332, 0x33333334, 0x2, x1, 708, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x33327e30, 0x33333334, 0xb504, x1, 712, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x3333e838, 0x33333334, -0xb504, x1, 716, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xccccccce, 0x33333334, 0x66666666, x1, 720, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x33333334, 0x33333333, x1, 724, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x3333332f, 0x33333334, 0x5, x1, 728, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x8888888a, 0x33333334, -0x55555556, x1, 732, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xdddddddf, 0x33333334, 0x55555555, x1, 736, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333334; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x33333331, 0x33333334, 0x3, x1, 740, x2)
+
+inst_186:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b01, 0x6, 0xb505, x1, 744, x2)
+
+inst_187:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb509, 0x6, -0xb503, x1, 748, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9999999f, 0x6, 0x66666667, x1, 752, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd2, 0x6, 0x33333334, x1, 756, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x6, 0x6, x1, 760, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x5555555b, 0x6, -0x55555555, x1, 764, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab0, 0x6, 0x55555556, x1, 768, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x6, 0x4, x1, 772, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b03, 0x6, 0xb503, x1, 776, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x6, 0x6, 0x0, x1, 780, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x999999a1, 0x6, 0x66666665, x1, 784, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd4, 0x6, 0x33333332, x1, 788, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab2, 0x6, 0x55555554, x1, 792, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x4, 0x6, 0x2, x1, 796, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b02, 0x6, 0xb504, x1, 800, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb50a, 0x6, -0xb504, x1, 804, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x999999a0, 0x6, 0x66666666, x1, 808, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd3, 0x6, 0x33333333, x1, 812, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x6, 0x5, x1, 816, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x5555555c, 0x6, -0x55555556, x1, 820, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab1, 0x6, 0x55555555, x1, 824, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x6; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x3, 0x6, 0x3, x1, 828, x2)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a6, -0x55555555, 0xb505, x1, 832, x2)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fae, -0x55555555, -0xb503, x1, 836, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x44444444, -0x55555555, 0x66666667, x1, 840, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x77777777, -0x55555555, 0x33333334, x1, 844, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa5, -0x55555555, 0x6, x1, 848, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x0, -0x55555555, -0x55555555, x1, 852, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55555555, -0x55555555, 0x55555556, x1, 856, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa7, -0x55555555, 0x4, x1, 860, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a8, -0x55555555, 0xb503, x1, 864, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 868, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x44444446, -0x55555555, 0x66666665, x1, 872, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x77777779, -0x55555555, 0x33333332, x1, 876, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x55555557, -0x55555555, 0x55555554, x1, 880, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa9, -0x55555555, 0x2, x1, 884, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a7, -0x55555555, 0xb504, x1, 888, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5faf, -0x55555555, -0xb504, x1, 892, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x44444445, -0x55555555, 0x66666666, x1, 896, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x77777778, -0x55555555, 0x33333333, x1, 900, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa6, -0x55555555, 0x5, x1, 904, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x1, -0x55555555, -0x55555556, x1, 908, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555556, -0x55555555, 0x55555555, x1, 912, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa8, -0x55555555, 0x3, x1, 916, x2)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x5554a051, 0x55555556, 0xb505, x1, 920, x2)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x55560a59, 0x55555556, -0xb503, x1, 924, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeef, 0x55555556, 0x66666667, x1, 928, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x22222222, 0x55555556, 0x33333334, x1, 932, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x55555550, 0x55555556, 0x6, x1, 936, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaab, 0x55555556, -0x55555555, x1, 940, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x55555556, 0x55555556, x1, 944, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x55555552, 0x55555556, 0x4, x1, 948, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x5554a053, 0x55555556, 0xb503, x1, 952, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 956, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeef1, 0x55555556, 0x66666665, x1, 960, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x22222224, 0x55555556, 0x33333332, x1, 964, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x55555556, 0x55555554, x1, 968, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x55555554, 0x55555556, 0x2, x1, 972, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x5554a052, 0x55555556, 0xb504, x1, 976, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x55560a5a, 0x55555556, -0xb504, x1, 980, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeef0, 0x55555556, 0x66666666, x1, 984, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x22222223, 0x55555556, 0x33333333, x1, 988, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x55555551, 0x55555556, 0x5, x1, 992, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaac, 0x55555556, -0x55555556, x1, 996, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x55555556, 0x55555555, x1, 1000, x2)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555556; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x55555553, 0x55555556, 0x3, x1, 1004, x2)
+
+inst_252:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4aff, 0x4, 0xb505, x1, 1008, x2)
+
+inst_253:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb507, 0x4, -0xb503, x1, 1012, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9999999d, 0x4, 0x66666667, x1, 1016, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd0, 0x4, 0x33333334, x1, 1020, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x4, 0x6, x1, 1024, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555559, 0x4, -0x55555555, x1, 1028, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaae, 0x4, 0x55555556, x1, 1032, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x4, 0x4, x1, 1036, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b01, 0x4, 0xb503, x1, 1040, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x4, 0x4, 0x0, x1, 1044, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9999999f, 0x4, 0x66666665, x1, 1048, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd2, 0x4, 0x33333332, x1, 1052, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab0, 0x4, 0x55555554, x1, 1056, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x4, 0x2, x1, 1060, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b00, 0x4, 0xb504, x1, 1064, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb508, 0x4, -0xb504, x1, 1068, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999e, 0x4, 0x66666666, x1, 1072, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd1, 0x4, 0x33333333, x1, 1076, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x4, 0x5, x1, 1080, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x5555555a, 0x4, -0x55555556, x1, 1084, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaf, 0x4, 0x55555555, x1, 1088, x2)
+
+inst_273:
+// rs1_val==4 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x4; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x4, 0x3, x1, 1092, x2)
+
+inst_274:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0xb503, 0xb505, x1, 1096, x2)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x16a06, 0xb503, -0xb503, x1, 1100, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9c, 0xb503, 0x66666667, x1, 1104, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81cf, 0xb503, 0x33333334, x1, 1108, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xb4fd, 0xb503, 0x6, x1, 1112, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55560a58, 0xb503, -0x55555555, x1, 1116, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fad, 0xb503, 0x55555556, x1, 1120, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xb4ff, 0xb503, 0x4, x1, 1124, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0xb503, 0xb503, x1, 1128, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xb503, 0xb503, 0x0, x1, 1132, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9e, 0xb503, 0x66666665, x1, 1136, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d1, 0xb503, 0x33333332, x1, 1140, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5faf, 0xb503, 0x55555554, x1, 1144, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xb501, 0xb503, 0x2, x1, 1148, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0xb503, 0xb504, x1, 1152, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x16a07, 0xb503, -0xb504, x1, 1156, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9d, 0xb503, 0x66666666, x1, 1160, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d0, 0xb503, 0x33333333, x1, 1164, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xb4fe, 0xb503, 0x5, x1, 1168, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55560a59, 0xb503, -0x55555556, x1, 1172, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fae, 0xb503, 0x55555555, x1, 1176, x2)
+
+inst_295:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb503; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xb500, 0xb503, 0x3, x1, 1180, x2)
+
+inst_296:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afb, 0x0, 0xb505, x1, 1184, x2)
+
+inst_297:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb503, 0x0, -0xb503, x1, 1188, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x99999999, 0x0, 0x66666667, x1, 1192, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccc, 0x0, 0x33333334, x1, 1196, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffa, 0x0, 0x6, x1, 1200, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555555, 0x0, -0x55555555, x1, 1204, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaa, 0x0, 0x55555556, x1, 1208, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffc, 0x0, 0x4, x1, 1212, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afd, 0x0, 0xb503, x1, 1216, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x0, 0x0, x1, 1220, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9999999b, 0x0, 0x66666665, x1, 1224, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccce, 0x0, 0x33333332, x1, 1228, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaac, 0x0, 0x55555554, x1, 1232, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x0, 0x2, x1, 1236, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afc, 0x0, 0xb504, x1, 1240, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb504, 0x0, -0xb504, x1, 1244, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999a, 0x0, 0x66666666, x1, 1248, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccd, 0x0, 0x33333333, x1, 1252, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffb, 0x0, 0x5, x1, 1256, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55555556, 0x0, -0x55555556, x1, 1260, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaab, 0x0, 0x55555555, x1, 1264, x2)
+
+inst_317:
+// rs1_val==0 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x0; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffd, 0x0, 0x3, x1, 1268, x2)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x6665b160, 0x66666665, 0xb505, x1, 1272, x2)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x66671b68, 0x66666665, -0xb503, x1, 1276, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x66666665, 0x66666667, x1, 1280, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x33333331, 0x66666665, 0x33333334, x1, 1284, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x6666665f, 0x66666665, 0x6, x1, 1288, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbba, 0x66666665, -0x55555555, x1, 1292, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x1111110f, 0x66666665, 0x55555556, x1, 1296, x2)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1300, x2)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xccccccce, 0x33333333, 0x66666665, x1, 1304, x2)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 1308, x2)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xdddddddf, 0x33333333, 0x55555554, x1, 1312, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x33333331, 0x33333333, 0x2, x1, 1316, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2f, 0x33333333, 0xb504, x1, 1320, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x3333e837, 0x33333333, -0xb504, x1, 1324, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccd, 0x33333333, 0x66666666, x1, 1328, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x33333333, 0x33333333, x1, 1332, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x3333332e, 0x33333333, 0x5, x1, 1336, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x88888889, 0x33333333, -0x55555556, x1, 1340, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xddddddde, 0x33333333, 0x55555555, x1, 1344, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x33333330, 0x33333333, 0x3, x1, 1348, x2)
+
+inst_338:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b00, 0x5, 0xb505, x1, 1352, x2)
+
+inst_339:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb508, 0x5, -0xb503, x1, 1356, x2)
+
+inst_340:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9999999e, 0x5, 0x66666667, x1, 1360, x2)
+
+inst_341:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd1, 0x5, 0x33333334, x1, 1364, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x5, 0x6, x1, 1368, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x5555555a, 0x5, -0x55555555, x1, 1372, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaf, 0x5, 0x55555556, x1, 1376, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x5, 0x4, x1, 1380, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b02, 0x5, 0xb503, x1, 1384, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x5, 0x5, 0x0, x1, 1388, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x999999a0, 0x5, 0x66666665, x1, 1392, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd3, 0x5, 0x33333332, x1, 1396, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab1, 0x5, 0x55555554, x1, 1400, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x3, 0x5, 0x2, x1, 1404, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b01, 0x5, 0xb504, x1, 1408, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb509, 0x5, -0xb504, x1, 1412, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999f, 0x5, 0x66666666, x1, 1416, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd2, 0x5, 0x33333333, x1, 1420, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x5, 0x5, x1, 1424, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x5555555b, 0x5, -0x55555556, x1, 1428, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaab0, 0x5, 0x55555555, x1, 1432, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x5; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x5, 0x3, x1, 1436, x2)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a5, -0x55555556, 0xb505, x1, 1440, x2)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fad, -0x55555556, -0xb503, x1, 1444, x2)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x44444443, -0x55555556, 0x66666667, x1, 1448, x2)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x77777776, -0x55555556, 0x33333334, x1, 1452, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa4, -0x55555556, 0x6, x1, 1456, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, -0x55555556, -0x55555555, x1, 1460, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55555554, -0x55555556, 0x55555556, x1, 1464, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa6, -0x55555556, 0x4, x1, 1468, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a7, -0x55555556, 0xb503, x1, 1472, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1476, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x44444445, -0x55555556, 0x66666665, x1, 1480, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x77777778, -0x55555556, 0x33333332, x1, 1484, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x55555556, -0x55555556, 0x55555554, x1, 1488, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa8, -0x55555556, 0x2, x1, 1492, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a6, -0x55555556, 0xb504, x1, 1496, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fae, -0x55555556, -0xb504, x1, 1500, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x44444444, -0x55555556, 0x66666666, x1, 1504, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x77777777, -0x55555556, 0x33333333, x1, 1508, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa5, -0x55555556, 0x5, x1, 1512, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x0, -0x55555556, -0x55555556, x1, 1516, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555555, -0x55555556, 0x55555555, x1, 1520, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa7, -0x55555556, 0x3, x1, 1524, x2)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x5554a050, 0x55555555, 0xb505, x1, 1528, x2)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x55560a58, 0x55555555, -0xb503, x1, 1532, x2)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeee, 0x55555555, 0x66666667, x1, 1536, x2)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x22222221, 0x55555555, 0x33333334, x1, 1540, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x5555554f, 0x55555555, 0x6, x1, 1544, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaa, 0x55555555, -0x55555555, x1, 1548, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x55555555, 0x55555556, x1, 1552, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x55555551, 0x55555555, 0x4, x1, 1556, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x5554a052, 0x55555555, 0xb503, x1, 1560, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1564, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeef0, 0x55555555, 0x66666665, x1, 1568, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x22222223, 0x55555555, 0x33333332, x1, 1572, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 1576, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x55555553, 0x55555555, 0x2, x1, 1580, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x5554a051, 0x55555555, 0xb504, x1, 1584, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x55560a59, 0x55555555, -0xb504, x1, 1588, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeef, 0x55555555, 0x66666666, x1, 1592, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x22222222, 0x55555555, 0x33333333, x1, 1596, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x55555550, 0x55555555, 0x5, x1, 1600, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaab, 0x55555555, -0x55555556, x1, 1604, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x55555555, 0x55555555, x1, 1608, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555555; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x55555552, 0x55555555, 0x3, x1, 1612, x2)
+
+inst_404:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afe, 0x3, 0xb505, x1, 1616, x2)
+
+inst_405:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb506, 0x3, -0xb503, x1, 1620, x2)
+
+inst_406:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9999999c, 0x3, 0x66666667, x1, 1624, x2)
+
+inst_407:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccf, 0x3, 0x33333334, x1, 1628, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffd, 0x3, 0x6, x1, 1632, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555558, 0x3, -0x55555555, x1, 1636, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaad, 0x3, 0x55555556, x1, 1640, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x3, 0x4, x1, 1644, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4b00, 0x3, 0xb503, x1, 1648, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x3, 0x3, 0x0, x1, 1652, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9999999e, 0x3, 0x66666665, x1, 1656, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd1, 0x3, 0x33333332, x1, 1660, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaf, 0x3, 0x55555554, x1, 1664, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x3, 0x2, x1, 1668, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4aff, 0x3, 0xb504, x1, 1672, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb507, 0x3, -0xb504, x1, 1676, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999d, 0x3, 0x66666666, x1, 1680, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd0, 0x3, 0x33333333, x1, 1684, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x3, 0x5, x1, 1688, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55555559, 0x3, -0x55555556, x1, 1692, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaae, 0x3, 0x55555555, x1, 1696, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x3; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x3, 0x3, x1, 1700, x2)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x66666661, 0x66666665, 0x4, x1, 1704, x2)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x6665b162, 0x66666665, 0xb503, x1, 1708, x2)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1712, x2)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x66666665, 0x66666665, x1, 1716, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x33333333, 0x66666665, 0x33333332, x1, 1720, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x11111111, 0x66666665, 0x55555554, x1, 1724, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x66666663, 0x66666665, 0x2, x1, 1728, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x6665b161, 0x66666665, 0xb504, x1, 1732, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x66671b69, 0x66666665, -0xb504, x1, 1736, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x66666665, 0x66666666, x1, 1740, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x33333332, 0x66666665, 0x33333333, x1, 1744, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x66666660, 0x66666665, 0x5, x1, 1748, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbbb, 0x66666665, -0x55555556, x1, 1752, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x11111110, 0x66666665, 0x55555555, x1, 1756, x2)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666665; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x66666662, 0x66666665, 0x3, x1, 1760, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2d, 0x33333332, 0xb505, x1, 1764, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x3333e835, 0x33333332, -0xb503, x1, 1768, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccb, 0x33333332, 0x66666667, x1, 1772, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x33333332, 0x33333334, x1, 1776, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x3333332c, 0x33333332, 0x6, x1, 1780, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x88888887, 0x33333332, -0x55555555, x1, 1784, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xdddddddc, 0x33333332, 0x55555556, x1, 1788, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x3333332e, 0x33333332, 0x4, x1, 1792, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2f, 0x33333332, 0xb503, x1, 1796, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1800, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccd, 0x33333332, 0x66666665, x1, 1804, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x33333332, 0x33333332, x1, 1808, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xddddddde, 0x33333332, 0x55555554, x1, 1812, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x33333330, 0x33333332, 0x2, x1, 1816, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2e, 0x33333332, 0xb504, x1, 1820, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x3333e836, 0x33333332, -0xb504, x1, 1824, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccc, 0x33333332, 0x66666666, x1, 1828, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x33333332, 0x33333333, x1, 1832, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x3333332d, 0x33333332, 0x5, x1, 1836, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x88888888, 0x33333332, -0x55555556, x1, 1840, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xdddddddd, 0x33333332, 0x55555555, x1, 1844, x2)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333332; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x3333332f, 0x33333332, 0x3, x1, 1848, x2)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x5554a04f, 0x55555554, 0xb505, x1, 1852, x2)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x55560a57, 0x55555554, -0xb503, x1, 1856, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeed, 0x55555554, 0x66666667, x1, 1860, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x22222220, 0x55555554, 0x33333334, x1, 1864, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x5555554e, 0x55555554, 0x6, x1, 1868, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaa9, 0x55555554, -0x55555555, x1, 1872, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x55555554, 0x55555556, x1, 1876, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x55555550, 0x55555554, 0x4, x1, 1880, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x5554a051, 0x55555554, 0xb503, x1, 1884, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1888, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeef, 0x55555554, 0x66666665, x1, 1892, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x22222222, 0x55555554, 0x33333332, x1, 1896, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x55555554, 0x55555554, x1, 1900, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x55555552, 0x55555554, 0x2, x1, 1904, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x5554a050, 0x55555554, 0xb504, x1, 1908, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x55560a58, 0x55555554, -0xb504, x1, 1912, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0xeeeeeeee, 0x55555554, 0x66666666, x1, 1916, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x22222221, 0x55555554, 0x33333333, x1, 1920, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x5555554f, 0x55555554, 0x5, x1, 1924, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaaa, 0x55555554, -0x55555556, x1, 1928, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x55555554, 0x55555555, x1, 1932, x2)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x55555554; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x55555551, 0x55555554, 0x3, x1, 1936, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afd, 0x2, 0xb505, x1, 1940, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xb505, 0x2, -0xb503, x1, 1944, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9999999b, 0x2, 0x66666667, x1, 1948, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xccccccce, 0x2, 0x33333334, x1, 1952, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffc, 0x2, 0x6, x1, 1956, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55555557, 0x2, -0x55555555, x1, 1960, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaac, 0x2, 0x55555556, x1, 1964, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffe, 0x2, 0x4, x1, 1968, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffff4aff, 0x2, 0xb503, x1, 1972, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x2, 0x2, 0x0, x1, 1976, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9999999d, 0x2, 0x66666665, x1, 1980, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xccccccd0, 0x2, 0x33333332, x1, 1984, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaae, 0x2, 0x55555554, x1, 1988, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afe, 0x2, 0xb504, x1, 1992, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xb506, 0x2, -0xb504, x1, 1996, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9999999c, 0x2, 0x66666666, x1, 2000, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccf, 0x2, 0x33333333, x1, 2004, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xfffffffd, 0x2, 0x5, x1, 2008, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55555558, 0x2, -0x55555556, x1, 2012, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaaaaaad, 0x2, 0x55555555, x1, 2016, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x2; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x2, 0x3, x1, 2020, x2)
+
+inst_506:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0xb504, 0xb505, x1, 2024, x2)
+
+inst_507:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x16a07, 0xb504, -0xb503, x1, 2028, x2)
+
+inst_508:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9d, 0xb504, 0x66666667, x1, 2032, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d0, 0xb504, 0x33333334, x1, 2036, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xb4fe, 0xb504, 0x6, x1, 2040, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x55560a59, 0xb504, -0x55555555, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fae, 0xb504, 0x55555556, x1, 0, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0xb500, 0xb504, 0x4, x1, 4, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0xb504, 0xb503, x1, 8, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xb504, 0xb504, 0x0, x1, 12, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9f, 0xb504, 0x66666665, x1, 16, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d2, 0xb504, 0x33333332, x1, 20, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5fb0, 0xb504, 0x55555554, x1, 24, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xb502, 0xb504, 0x2, x1, 28, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0xb504, 0xb504, x1, 32, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x16a08, 0xb504, -0xb504, x1, 36, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x999a4e9e, 0xb504, 0x66666666, x1, 40, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccd81d1, 0xb504, 0x33333333, x1, 44, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xb4ff, 0xb504, 0x5, x1, 48, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x55560a5a, 0xb504, -0x55555556, x1, 52, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaab5faf, 0xb504, 0x55555555, x1, 56, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0xb504; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xb501, 0xb504, 0x3, x1, 60, x2)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95f7, -0xb504, 0xb505, x1, 64, x2)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, -0xb504, -0xb503, x1, 68, x2)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0x9998e495, -0xb504, 0x66666667, x1, 72, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17c8, -0xb504, 0x33333334, x1, 76, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af6, -0xb504, 0x6, x1, 80, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x5554a051, -0xb504, -0x55555555, x1, 84, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a6, -0xb504, 0x55555556, x1, 88, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95f9, -0xb504, 0xb503, x1, 92, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 96, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x9998e497, -0xb504, 0x66666665, x1, 100, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17ca, -0xb504, 0x33333332, x1, 104, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a8, -0xb504, 0x55555554, x1, 108, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0xffff4afa, -0xb504, 0x2, x1, 112, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0xfffe95f8, -0xb504, 0xb504, x1, 116, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x0, -0xb504, -0xb504, x1, 120, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x9998e496, -0xb504, 0x66666666, x1, 124, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0xcccc17c9, -0xb504, 0x33333333, x1, 128, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af7, -0xb504, 0x5, x1, 132, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x5554a052, -0xb504, -0x55555556, x1, 136, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xaaa9f5a7, -0xb504, 0x55555555, x1, 140, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0xb504; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0xffff4af9, -0xb504, 0x3, x1, 144, x2)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x6665b161, 0x66666666, 0xb505, x1, 148, x2)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x66671b69, 0x66666666, -0xb503, x1, 152, x2)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x66666666, 0x66666667, x1, 156, x2)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0x33333332, 0x66666666, 0x33333334, x1, 160, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x66666660, 0x66666666, 0x6, x1, 164, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbbb, 0x66666666, -0x55555555, x1, 168, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0x11111110, 0x66666666, 0x55555556, x1, 172, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x66666662, 0x66666666, 0x4, x1, 176, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x6665b163, 0x66666666, 0xb503, x1, 180, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x0
+TEST_CR_OP( c.sub, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 184, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665
+TEST_CR_OP( c.sub, x10, x11, 0x1, 0x66666666, 0x66666665, x1, 188, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332
+TEST_CR_OP( c.sub, x10, x11, 0x33333334, 0x66666666, 0x33333332, x1, 192, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554
+TEST_CR_OP( c.sub, x10, x11, 0x11111112, 0x66666666, 0x55555554, x1, 196, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x2
+TEST_CR_OP( c.sub, x10, x11, 0x66666664, 0x66666666, 0x2, x1, 200, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x6665b162, 0x66666666, 0xb504, x1, 204, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504
+TEST_CR_OP( c.sub, x10, x11, 0x66671b6a, 0x66666666, -0xb504, x1, 208, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666
+TEST_CR_OP( c.sub, x10, x11, 0x0, 0x66666666, 0x66666666, x1, 212, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333
+TEST_CR_OP( c.sub, x10, x11, 0x33333333, 0x66666666, 0x33333333, x1, 216, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x5
+TEST_CR_OP( c.sub, x10, x11, 0x66666661, 0x66666666, 0x5, x1, 220, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xbbbbbbbc, 0x66666666, -0x55555556, x1, 224, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x11111111, 0x66666666, 0x55555555, x1, 228, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x66666666; op2val:0x3
+TEST_CR_OP( c.sub, x10, x11, 0x66666663, 0x66666666, 0x3, x1, 232, x2)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505
+TEST_CR_OP( c.sub, x10, x11, 0x33327e2e, 0x33333333, 0xb505, x1, 236, x2)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x3333e836, 0x33333333, -0xb503, x1, 240, x2)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667
+TEST_CR_OP( c.sub, x10, x11, 0xcccccccc, 0x33333333, 0x66666667, x1, 244, x2)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334
+TEST_CR_OP( c.sub, x10, x11, 0xffffffff, 0x33333333, 0x33333334, x1, 248, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x6
+TEST_CR_OP( c.sub, x10, x11, 0x3333332d, 0x33333333, 0x6, x1, 252, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555
+TEST_CR_OP( c.sub, x10, x11, 0x88888888, 0x33333333, -0x55555555, x1, 256, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556
+TEST_CR_OP( c.sub, x10, x11, 0xdddddddd, 0x33333333, 0x55555556, x1, 260, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0x4
+TEST_CR_OP( c.sub, x10, x11, 0x3333332f, 0x33333333, 0x4, x1, 264, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: c.sub; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503
+TEST_CR_OP( c.sub, x10, x11, 0x33327e30, 0x33333333, 0xb503, x1, 268, x2)
+
+inst_580:
+// rs2_val == 2147483647, rs1_val == -257, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.sub; op1:x10; op2:x11; op1val:-0x101; op2val:0x7fffffff
+TEST_CR_OP( c.sub, x10, x11, 0x7fffff00, -0x101, 0x7fffffff, x1, 272, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 69*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csw-01.S
new file mode 100644
index 000000000..addb0aaa6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/csw-01.S
@@ -0,0 +1,410 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.sw instruction of the RISC-V C extension for the csw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",csw)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x15, rs2==x14, imm_val == 0, rs2_val == -16385
+// opcode:c.sw; op1:x15; op2:x14; op2val:-0x4001; immval:0x0
+TEST_STORE(x1,x2,0,x15,x14,-0x4001,0x0,0,c.sw,0)
+
+inst_1:
+// rs1==x11, rs2==x10, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1), imm_val > 0
+// opcode:c.sw; op1:x11; op2:x10; op2val:0x7fffffff; immval:0x14
+TEST_STORE(x1,x2,0,x11,x10,0x7fffffff,0x14,4,c.sw,0)
+
+inst_2:
+// rs1==x13, rs2==x8, rs2_val == -1073741825, 
+// opcode:c.sw; op1:x13; op2:x8; op2val:-0x40000001; immval:0x14
+TEST_STORE(x1,x2,0,x13,x8,-0x40000001,0x14,8,c.sw,0)
+
+inst_3:
+// rs1==x9, rs2==x13, rs2_val == -536870913, 
+// opcode:c.sw; op1:x9; op2:x13; op2val:-0x20000001; immval:0x24
+TEST_STORE(x1,x2,0,x9,x13,-0x20000001,0x24,12,c.sw,0)
+
+inst_4:
+// rs1==x10, rs2==x12, rs2_val == -268435457, imm_val == 32
+// opcode:c.sw; op1:x10; op2:x12; op2val:-0x10000001; immval:0x20
+TEST_STORE(x1,x2,0,x10,x12,-0x10000001,0x20,16,c.sw,0)
+
+inst_5:
+// rs1==x14, rs2==x15, rs2_val == -134217729, 
+// opcode:c.sw; op1:x14; op2:x15; op2val:-0x8000001; immval:0x4c
+TEST_STORE(x1,x2,0,x14,x15,-0x8000001,0x4c,20,c.sw,0)
+
+inst_6:
+// rs1==x8, rs2==x9, rs2_val == -67108865, 
+// opcode:c.sw; op1:x8; op2:x9; op2val:-0x4000001; immval:0x48
+TEST_STORE(x1,x2,0,x8,x9,-0x4000001,0x48,24,c.sw,0)
+
+inst_7:
+// rs1==x12, rs2==x11, rs2_val == -33554433, imm_val == 84
+// opcode:c.sw; op1:x12; op2:x11; op2val:-0x2000001; immval:0x54
+TEST_STORE(x1,x2,0,x12,x11,-0x2000001,0x54,28,c.sw,0)
+
+inst_8:
+// rs2_val == -16777217, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1000001; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,-0x1000001,0x7c,32,c.sw,0)
+
+inst_9:
+// rs2_val == -8388609, imm_val == 4
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x800001; immval:0x4
+TEST_STORE(x1,x2,0,x10,x11,-0x800001,0x4,36,c.sw,0)
+
+inst_10:
+// rs2_val == -4194305, imm_val == 60
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x400001; immval:0x3c
+TEST_STORE(x1,x2,0,x10,x11,-0x400001,0x3c,40,c.sw,0)
+
+inst_11:
+// rs2_val == -2097153, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x200001; immval:0x30
+TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x30,44,c.sw,0)
+
+inst_12:
+// rs2_val == -1048577, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x7c,48,c.sw,0)
+
+inst_13:
+// rs2_val == -524289, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80001; immval:0x18
+TEST_STORE(x1,x2,0,x10,x11,-0x80001,0x18,52,c.sw,0)
+
+inst_14:
+// rs2_val == -262145, imm_val == 40
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x40001; immval:0x28
+TEST_STORE(x1,x2,0,x10,x11,-0x40001,0x28,56,c.sw,0)
+
+inst_15:
+// rs2_val == -131073, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x20001; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,-0x20001,0x7c,60,c.sw,0)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x10001; immval:0x14
+TEST_STORE(x1,x2,0,x10,x11,-0x10001,0x14,64,c.sw,0)
+
+inst_17:
+// rs2_val == -32769, imm_val == 64
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x8001; immval:0x40
+TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x40,68,c.sw,0)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x0
+TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x0,72,c.sw,0)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x48
+TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x48,76,c.sw,0)
+
+inst_20:
+// rs2_val == -2049, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x801; immval:0x24
+TEST_STORE(x1,x2,0,x10,x11,-0x801,0x24,80,c.sw,0)
+
+inst_21:
+// rs2_val == -1025, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x401; immval:0x28
+TEST_STORE(x1,x2,0,x10,x11,-0x401,0x28,84,c.sw,0)
+
+inst_22:
+// rs2_val == -513, imm_val == 120
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x201; immval:0x78
+TEST_STORE(x1,x2,0,x10,x11,-0x201,0x78,88,c.sw,0)
+
+inst_23:
+// rs2_val == -257, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x101; immval:0x24
+TEST_STORE(x1,x2,0,x10,x11,-0x101,0x24,92,c.sw,0)
+
+inst_24:
+// rs2_val == -129, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x81; immval:0x4c
+TEST_STORE(x1,x2,0,x10,x11,-0x81,0x4c,96,c.sw,0)
+
+inst_25:
+// rs2_val == -65, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x41; immval:0x14
+TEST_STORE(x1,x2,0,x10,x11,-0x41,0x14,100,c.sw,0)
+
+inst_26:
+// rs2_val == -33, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x21; immval:0x28
+TEST_STORE(x1,x2,0,x10,x11,-0x21,0x28,104,c.sw,0)
+
+inst_27:
+// rs2_val == -17, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x11; immval:0x34
+TEST_STORE(x1,x2,0,x10,x11,-0x11,0x34,108,c.sw,0)
+
+inst_28:
+// rs2_val == -9, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x9; immval:0x28
+TEST_STORE(x1,x2,0,x10,x11,-0x9,0x28,112,c.sw,0)
+
+inst_29:
+// rs2_val == -5, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x5; immval:0xc
+TEST_STORE(x1,x2,0,x10,x11,-0x5,0xc,116,c.sw,0)
+
+inst_30:
+// rs2_val == -3, imm_val == 108
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x3; immval:0x6c
+TEST_STORE(x1,x2,0,x10,x11,-0x3,0x6c,120,c.sw,0)
+
+inst_31:
+// rs2_val == -2, imm_val == 92
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x2; immval:0x5c
+TEST_STORE(x1,x2,0,x10,x11,-0x2,0x5c,124,c.sw,0)
+
+inst_32:
+// imm_val == 116, rs2_val == 32768
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000; immval:0x74
+TEST_STORE(x1,x2,0,x10,x11,0x8000,0x74,128,c.sw,0)
+
+inst_33:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,-0x80000000,0x7c,132,c.sw,0)
+
+inst_34:
+// rs2_val == 1073741824, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000000; immval:0x38
+TEST_STORE(x1,x2,0,x10,x11,0x40000000,0x38,136,c.sw,0)
+
+inst_35:
+// rs2_val == 536870912, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000000; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,0x20000000,0x7c,140,c.sw,0)
+
+inst_36:
+// rs2_val == 268435456, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000000; immval:0x1c
+TEST_STORE(x1,x2,0,x10,x11,0x10000000,0x1c,144,c.sw,0)
+
+inst_37:
+// rs2_val == 134217728, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x5c
+TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x5c,148,c.sw,0)
+
+inst_38:
+// rs2_val == 32, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x20; immval:0x2c
+TEST_STORE(x1,x2,0,x10,x11,0x20,0x2c,152,c.sw,0)
+
+inst_39:
+// rs2_val == 16, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x10; immval:0x30
+TEST_STORE(x1,x2,0,x10,x11,0x10,0x30,156,c.sw,0)
+
+inst_40:
+// rs2_val == 8, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x8; immval:0x24
+TEST_STORE(x1,x2,0,x10,x11,0x8,0x24,160,c.sw,0)
+
+inst_41:
+// rs2_val == 4, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x4; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,0x4,0x7c,164,c.sw,0)
+
+inst_42:
+// rs2_val == 2, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x2; immval:0x34
+TEST_STORE(x1,x2,0,x10,x11,0x2,0x34,168,c.sw,0)
+
+inst_43:
+// rs2_val == 1, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x1; immval:0x54
+TEST_STORE(x1,x2,0,x10,x11,0x1,0x54,172,c.sw,0)
+
+inst_44:
+// imm_val == 16, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x100001; immval:0x10
+TEST_STORE(x1,x2,0,x10,x11,-0x100001,0x10,176,c.sw,0)
+
+inst_45:
+// imm_val == 8, rs2_val == 524288
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x80000; immval:0x8
+TEST_STORE(x1,x2,0,x10,x11,0x80000,0x8,180,c.sw,0)
+
+inst_46:
+// rs2_val == -1431655766, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:-0x55555556; immval:0x3c
+TEST_STORE(x1,x2,0,x10,x11,-0x55555556,0x3c,184,c.sw,0)
+
+inst_47:
+// rs2_val == 1431655765, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x10
+TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x10,188,c.sw,0)
+
+inst_48:
+// rs2_val == 0, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x0; immval:0x38
+TEST_STORE(x1,x2,0,x10,x11,0x0,0x38,192,c.sw,0)
+
+inst_49:
+// rs2_val == 67108864, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000000; immval:0xc
+TEST_STORE(x1,x2,0,x10,x11,0x4000000,0xc,196,c.sw,0)
+
+inst_50:
+// rs2_val == 33554432, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x3c
+TEST_STORE(x1,x2,0,x10,x11,0x2000000,0x3c,200,c.sw,0)
+
+inst_51:
+// rs2_val == 16777216, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x20
+TEST_STORE(x1,x2,0,x10,x11,0x1000000,0x20,204,c.sw,0)
+
+inst_52:
+// rs2_val == 8388608, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x800000; immval:0x10
+TEST_STORE(x1,x2,0,x10,x11,0x800000,0x10,208,c.sw,0)
+
+inst_53:
+// rs2_val == 4194304, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x400000; immval:0x0
+TEST_STORE(x1,x2,0,x10,x11,0x400000,0x0,212,c.sw,0)
+
+inst_54:
+// rs2_val == 2097152, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x200000; immval:0x24
+TEST_STORE(x1,x2,0,x10,x11,0x200000,0x24,216,c.sw,0)
+
+inst_55:
+// rs2_val == 1048576, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x100000; immval:0x34
+TEST_STORE(x1,x2,0,x10,x11,0x100000,0x34,220,c.sw,0)
+
+inst_56:
+// rs2_val == 262144, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x40000; immval:0x14
+TEST_STORE(x1,x2,0,x10,x11,0x40000,0x14,224,c.sw,0)
+
+inst_57:
+// rs2_val == 131072, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x20000; immval:0x20
+TEST_STORE(x1,x2,0,x10,x11,0x20000,0x20,228,c.sw,0)
+
+inst_58:
+// rs2_val == 65536, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x10000; immval:0x44
+TEST_STORE(x1,x2,0,x10,x11,0x10000,0x44,232,c.sw,0)
+
+inst_59:
+// rs2_val == 16384, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x4000; immval:0x20
+TEST_STORE(x1,x2,0,x10,x11,0x4000,0x20,236,c.sw,0)
+
+inst_60:
+// rs2_val == 8192, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x2000; immval:0x78
+TEST_STORE(x1,x2,0,x10,x11,0x2000,0x78,240,c.sw,0)
+
+inst_61:
+// rs2_val == 4096, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7c
+TEST_STORE(x1,x2,0,x10,x11,0x1000,0x7c,244,c.sw,0)
+
+inst_62:
+// rs2_val == 2048, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x800; immval:0x6c
+TEST_STORE(x1,x2,0,x10,x11,0x800,0x6c,248,c.sw,0)
+
+inst_63:
+// rs2_val == 1024, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x400; immval:0x4c
+TEST_STORE(x1,x2,0,x10,x11,0x400,0x4c,252,c.sw,0)
+
+inst_64:
+// rs2_val == 512, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x200; immval:0x5c
+TEST_STORE(x1,x2,0,x10,x11,0x200,0x5c,256,c.sw,0)
+
+inst_65:
+// rs2_val == 256, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x100; immval:0x28
+TEST_STORE(x1,x2,0,x10,x11,0x100,0x28,260,c.sw,0)
+
+inst_66:
+// rs2_val == 128, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x80; immval:0x78
+TEST_STORE(x1,x2,0,x10,x11,0x80,0x78,264,c.sw,0)
+
+inst_67:
+// rs2_val == 64, 
+// opcode:c.sw; op1:x10; op2:x11; op2val:0x40; immval:0x3c
+TEST_STORE(x1,x2,0,x10,x11,0x40,0x3c,268,c.sw,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 68*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S
new file mode 100644
index 000000000..ce3908049
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cswsp-01.S
@@ -0,0 +1,425 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Sep 13 07:01:20 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.swsp instruction of the RISC-V C extension for the cswsp covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cswsp)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs2==x12, imm_val == 0, 
+// opcode:c.swsp; op1:x2; op2:x12; op2val:0x3; immval:0x0
+TEST_STORE(x8,x9,0,x2,x12,0x3,0x0,0,c.swsp,0)
+
+inst_1:
+// rs2==x1, rs2_val == 2147483647, imm_val > 0, rs2_val == (2**(xlen-1)-1), imm_val == 236
+// opcode:c.swsp; op1:x2; op2:x1; op2val:0x7fffffff; immval:0xec
+TEST_STORE(x8,x9,0,x2,x1,0x7fffffff,0xec,4,c.swsp,0)
+
+inst_2:
+// rs2==x7, rs2_val == -1073741825, 
+// opcode:c.swsp; op1:x2; op2:x7; op2val:-0x40000001; immval:0x48
+TEST_STORE(x8,x9,0,x2,x7,-0x40000001,0x48,8,c.swsp,0)
+
+inst_3:
+// rs2==x13, rs2_val == -536870913, 
+// opcode:c.swsp; op1:x2; op2:x13; op2val:-0x20000001; immval:0x48
+TEST_STORE(x8,x9,0,x2,x13,-0x20000001,0x48,12,c.swsp,0)
+
+inst_4:
+// rs2==x2, rs2_val == -268435457, imm_val == 8
+// opcode:c.swsp; op1:x2; op2:x2; op2val:-0x10000001; immval:0x8
+TEST_STORE(x8,x9,0,x2,x2,-0x10000001,0x8,16,c.swsp,0)
+
+inst_5:
+// rs2==x4, rs2_val == -134217729, 
+// opcode:c.swsp; op1:x2; op2:x4; op2val:-0x8000001; immval:0x28
+TEST_STORE(x8,x9,0,x2,x4,-0x8000001,0x28,20,c.swsp,0)
+
+inst_6:
+// rs2==x10, rs2_val == -67108865, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4000001; immval:0x4c
+TEST_STORE(x8,x9,0,x2,x10,-0x4000001,0x4c,24,c.swsp,0)
+
+inst_7:
+// rs2==x15, rs2_val == -33554433, 
+// opcode:c.swsp; op1:x2; op2:x15; op2val:-0x2000001; immval:0x18
+TEST_STORE(x8,x9,0,x2,x15,-0x2000001,0x18,28,c.swsp,0)
+
+inst_8:
+// rs2==x5, rs2_val == -16777217, imm_val == 244
+// opcode:c.swsp; op1:x2; op2:x5; op2val:-0x1000001; immval:0xf4
+TEST_STORE(x8,x9,0,x2,x5,-0x1000001,0xf4,32,c.swsp,0)
+
+inst_9:
+// rs2==x3, rs2_val == -8388609, 
+// opcode:c.swsp; op1:x2; op2:x3; op2val:-0x800001; immval:0x4c
+TEST_STORE(x8,x9,0,x2,x3,-0x800001,0x4c,36,c.swsp,0)
+
+inst_10:
+// rs2==x6, rs2_val == -4194305, 
+// opcode:c.swsp; op1:x2; op2:x6; op2val:-0x400001; immval:0x30
+TEST_STORE(x8,x9,0,x2,x6,-0x400001,0x30,40,c.swsp,0)
+
+inst_11:
+// rs2==x9, rs2_val == -2097153, imm_val == 128
+// opcode:c.swsp; op1:x2; op2:x9; op2val:-0x200001; immval:0x80
+TEST_STORE(x8,x3,0,x2,x9,-0x200001,0x80,44,c.swsp,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_12:
+// rs2==x11, rs2_val == -1048577, imm_val == 124
+// opcode:c.swsp; op1:x2; op2:x11; op2val:-0x100001; immval:0x7c
+TEST_STORE(x1,x3,0,x2,x11,-0x100001,0x7c,0,c.swsp,0)
+
+inst_13:
+// rs2==x14, rs2_val == -524289, 
+// opcode:c.swsp; op1:x2; op2:x14; op2val:-0x80001; immval:0x34
+TEST_STORE(x1,x3,0,x2,x14,-0x80001,0x34,4,c.swsp,0)
+
+inst_14:
+// rs2==x8, rs2_val == -262145, imm_val == 168
+// opcode:c.swsp; op1:x2; op2:x8; op2val:-0x40001; immval:0xa8
+TEST_STORE(x1,x3,0,x2,x8,-0x40001,0xa8,8,c.swsp,0)
+
+inst_15:
+// rs2_val == -131073, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x20001; immval:0xf4
+TEST_STORE(x1,x3,0,x2,x10,-0x20001,0xf4,12,c.swsp,0)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10001; immval:0x3c
+TEST_STORE(x1,x3,0,x2,x10,-0x10001,0x3c,16,c.swsp,0)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0x1c
+TEST_STORE(x1,x3,0,x2,x10,-0x8001,0x1c,20,c.swsp,0)
+
+inst_18:
+// rs2_val == -16385, imm_val == 4
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x4001; immval:0x4
+TEST_STORE(x1,x3,0,x2,x10,-0x4001,0x4,24,c.swsp,0)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2001; immval:0xa8
+TEST_STORE(x1,x3,0,x2,x10,-0x2001,0xa8,28,c.swsp,0)
+
+inst_20:
+// rs2_val == -4097, imm_val == 248
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x1001; immval:0xf8
+TEST_STORE(x1,x3,0,x2,x10,-0x1001,0xf8,32,c.swsp,0)
+
+inst_21:
+// rs2_val == -2049, imm_val == 64
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x801; immval:0x40
+TEST_STORE(x1,x3,0,x2,x10,-0x801,0x40,36,c.swsp,0)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x401; immval:0xc
+TEST_STORE(x1,x3,0,x2,x10,-0x401,0xc,40,c.swsp,0)
+
+inst_23:
+// rs2_val == -513, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x201; immval:0x38
+TEST_STORE(x1,x3,0,x2,x10,-0x201,0x38,44,c.swsp,0)
+
+inst_24:
+// rs2_val == -257, imm_val == 220
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x101; immval:0xdc
+TEST_STORE(x1,x3,0,x2,x10,-0x101,0xdc,48,c.swsp,0)
+
+inst_25:
+// rs2_val == -129, imm_val == 32
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x81; immval:0x20
+TEST_STORE(x1,x3,0,x2,x10,-0x81,0x20,52,c.swsp,0)
+
+inst_26:
+// rs2_val == -65, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x41; immval:0x34
+TEST_STORE(x1,x3,0,x2,x10,-0x41,0x34,56,c.swsp,0)
+
+inst_27:
+// rs2_val == -33, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x21; immval:0xf8
+TEST_STORE(x1,x3,0,x2,x10,-0x21,0xf8,60,c.swsp,0)
+
+inst_28:
+// rs2_val == -17, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x11; immval:0x4c
+TEST_STORE(x1,x3,0,x2,x10,-0x11,0x4c,64,c.swsp,0)
+
+inst_29:
+// rs2_val == -9, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x9; immval:0x30
+TEST_STORE(x1,x3,0,x2,x10,-0x9,0x30,68,c.swsp,0)
+
+inst_30:
+// rs2_val == -5, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x5; immval:0x3c
+TEST_STORE(x1,x3,0,x2,x10,-0x5,0x3c,72,c.swsp,0)
+
+inst_31:
+// rs2_val == -3, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x3; immval:0x80
+TEST_STORE(x1,x3,0,x2,x10,-0x3,0x80,76,c.swsp,0)
+
+inst_32:
+// rs2_val == -2, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x2; immval:0x24
+TEST_STORE(x1,x3,0,x2,x10,-0x2,0x24,80,c.swsp,0)
+
+inst_33:
+// imm_val == 188, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x8001; immval:0xbc
+TEST_STORE(x1,x3,0,x2,x10,-0x8001,0xbc,84,c.swsp,0)
+
+inst_34:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x80000000; immval:0x20
+TEST_STORE(x1,x3,0,x2,x10,-0x80000000,0x20,88,c.swsp,0)
+
+inst_35:
+// rs2_val == 1073741824, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000000; immval:0x38
+TEST_STORE(x1,x3,0,x2,x10,0x40000000,0x38,92,c.swsp,0)
+
+inst_36:
+// rs2_val == 536870912, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000000; immval:0x7c
+TEST_STORE(x1,x3,0,x2,x10,0x20000000,0x7c,96,c.swsp,0)
+
+inst_37:
+// rs2_val == 268435456, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000000; immval:0xfc
+TEST_STORE(x1,x3,0,x2,x10,0x10000000,0xfc,100,c.swsp,0)
+
+inst_38:
+// rs2_val == 134217728, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000000; immval:0x48
+TEST_STORE(x1,x3,0,x2,x10,0x8000000,0x48,104,c.swsp,0)
+
+inst_39:
+// rs2_val == 67108864, imm_val == 84
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000000; immval:0x54
+TEST_STORE(x1,x3,0,x2,x10,0x4000000,0x54,108,c.swsp,0)
+
+inst_40:
+// rs2_val == 64, imm_val == 16
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40; immval:0x10
+TEST_STORE(x1,x3,0,x2,x10,0x40,0x10,112,c.swsp,0)
+
+inst_41:
+// rs2_val == 32, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20; immval:0x14
+TEST_STORE(x1,x3,0,x2,x10,0x20,0x14,116,c.swsp,0)
+
+inst_42:
+// rs2_val == 16, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10; immval:0x4c
+TEST_STORE(x1,x3,0,x2,x10,0x10,0x4c,120,c.swsp,0)
+
+inst_43:
+// rs2_val == 8, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8; immval:0x4c
+TEST_STORE(x1,x3,0,x2,x10,0x8,0x4c,124,c.swsp,0)
+
+inst_44:
+// rs2_val == 4, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4; immval:0xf8
+TEST_STORE(x1,x3,0,x2,x10,0x4,0xf8,128,c.swsp,0)
+
+inst_45:
+// rs2_val == 2, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2; immval:0x2c
+TEST_STORE(x1,x3,0,x2,x10,0x2,0x2c,132,c.swsp,0)
+
+inst_46:
+// rs2_val == 1, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1; immval:0xbc
+TEST_STORE(x1,x3,0,x2,x10,0x1,0xbc,136,c.swsp,0)
+
+inst_47:
+// rs2_val == -1431655766, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x55555556; immval:0xdc
+TEST_STORE(x1,x3,0,x2,x10,-0x55555556,0xdc,140,c.swsp,0)
+
+inst_48:
+// rs2_val == 1431655765, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x55555555; immval:0x4c
+TEST_STORE(x1,x3,0,x2,x10,0x55555555,0x4c,144,c.swsp,0)
+
+inst_49:
+// rs2_val == 0, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x0; immval:0x40
+TEST_STORE(x1,x3,0,x2,x10,0x0,0x40,148,c.swsp,0)
+
+inst_50:
+// rs2_val == 33554432, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000000; immval:0x4
+TEST_STORE(x1,x3,0,x2,x10,0x2000000,0x4,152,c.swsp,0)
+
+inst_51:
+// rs2_val == 16777216, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000000; immval:0x7c
+TEST_STORE(x1,x3,0,x2,x10,0x1000000,0x7c,156,c.swsp,0)
+
+inst_52:
+// rs2_val == 8388608, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800000; immval:0x18
+TEST_STORE(x1,x3,0,x2,x10,0x800000,0x18,160,c.swsp,0)
+
+inst_53:
+// rs2_val == 4194304, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400000; immval:0x40
+TEST_STORE(x1,x3,0,x2,x10,0x400000,0x40,164,c.swsp,0)
+
+inst_54:
+// rs2_val == 2097152, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200000; immval:0x54
+TEST_STORE(x1,x3,0,x2,x10,0x200000,0x54,168,c.swsp,0)
+
+inst_55:
+// rs2_val == 1048576, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100000; immval:0x34
+TEST_STORE(x1,x3,0,x2,x10,0x100000,0x34,172,c.swsp,0)
+
+inst_56:
+// rs2_val == 524288, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80000; immval:0x20
+TEST_STORE(x1,x3,0,x2,x10,0x80000,0x20,176,c.swsp,0)
+
+inst_57:
+// rs2_val == 262144, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x40000; immval:0x44
+TEST_STORE(x1,x3,0,x2,x10,0x40000,0x44,180,c.swsp,0)
+
+inst_58:
+// rs2_val == 131072, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x20000; immval:0xa8
+TEST_STORE(x1,x3,0,x2,x10,0x20000,0xa8,184,c.swsp,0)
+
+inst_59:
+// rs2_val == 65536, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x10000; immval:0x3c
+TEST_STORE(x1,x3,0,x2,x10,0x10000,0x3c,188,c.swsp,0)
+
+inst_60:
+// rs2_val == 32768, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x8000; immval:0x34
+TEST_STORE(x1,x3,0,x2,x10,0x8000,0x34,192,c.swsp,0)
+
+inst_61:
+// rs2_val == 16384, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x4000; immval:0xc
+TEST_STORE(x1,x3,0,x2,x10,0x4000,0xc,196,c.swsp,0)
+
+inst_62:
+// rs2_val == 8192, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x2000; immval:0x4
+TEST_STORE(x1,x3,0,x2,x10,0x2000,0x4,200,c.swsp,0)
+
+inst_63:
+// rs2_val == 4096, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x1000; immval:0x30
+TEST_STORE(x1,x3,0,x2,x10,0x1000,0x30,204,c.swsp,0)
+
+inst_64:
+// rs2_val == 2048, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x800; immval:0x38
+TEST_STORE(x1,x3,0,x2,x10,0x800,0x38,208,c.swsp,0)
+
+inst_65:
+// rs2_val == 1024, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x400; immval:0x10
+TEST_STORE(x1,x3,0,x2,x10,0x400,0x10,212,c.swsp,0)
+
+inst_66:
+// rs2_val == 512, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x200; immval:0x3c
+TEST_STORE(x1,x3,0,x2,x10,0x200,0x3c,216,c.swsp,0)
+
+inst_67:
+// rs2_val == 256, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x100; immval:0x1c
+TEST_STORE(x1,x3,0,x2,x10,0x100,0x1c,220,c.swsp,0)
+
+inst_68:
+// rs2_val == 128, 
+// opcode:c.swsp; op1:x2; op2:x10; op2val:0x80; immval:0xf8
+TEST_STORE(x1,x3,0,x2,x10,0x80,0xf8,224,c.swsp,0)
+
+inst_69:
+// rs2_val == -268435457, imm_val == 8
+// opcode:c.swsp; op1:x2; op2:x10; op2val:-0x10000001; immval:0x8
+TEST_STORE(x1,x3,0,x2,x10,-0x10000001,0x8,228,c.swsp,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 58*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cxor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cxor-01.S
new file mode 100644
index 000000000..d53cb36ba
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cxor-01.S
@@ -0,0 +1,2975 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 06:39:00 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the c.xor instruction of the RISC-V C extension for the cxor covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EC")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cxor)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2, rs1==x14, rs2==x10, rs1_val == (-2**(xlen-1)), rs2_val == -32769, rs2_val < 0, rs1_val == -2147483648
+// opcode: c.xor; op1:x14; op2:x10; op1val:-0x80000000; op2val:-0x8001
+TEST_CR_OP( c.xor, x14, x10, 0x7fff7fff, -0x80000000, -0x8001, x1, 0, x2)
+
+inst_1:
+// rs1 == rs2, rs1==x8, rs2==x8, rs2_val == 2147483647, rs1_val == 64, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.xor; op1:x8; op2:x8; op1val:0x40; op2val:0x40
+TEST_CR_OP( c.xor, x8, x8, 0x0, 0x40, 0x40, x1, 4, x2)
+
+inst_2:
+// rs1==x10, rs2==x13, rs2_val == -1073741825, rs1_val == 1073741824
+// opcode: c.xor; op1:x10; op2:x13; op1val:0x40000000; op2val:-0x40000001
+TEST_CR_OP( c.xor, x10, x13, 0xffffffff, 0x40000000, -0x40000001, x1, 8, x2)
+
+inst_3:
+// rs1==x13, rs2==x9, rs2_val == -536870913, rs1_val == 32
+// opcode: c.xor; op1:x13; op2:x9; op1val:0x20; op2val:-0x20000001
+TEST_CR_OP( c.xor, x13, x9, 0xdfffffdf, 0x20, -0x20000001, x1, 12, x2)
+
+inst_4:
+// rs1==x12, rs2==x11, rs2_val == -268435457, 
+// opcode: c.xor; op1:x12; op2:x11; op1val:-0xb504; op2val:-0x10000001
+TEST_CR_OP( c.xor, x12, x11, 0x1000b503, -0xb504, -0x10000001, x1, 16, x2)
+
+inst_5:
+// rs1==x11, rs2==x12, rs2_val == -134217729, rs1_val == -8193
+// opcode: c.xor; op1:x11; op2:x12; op1val:-0x2001; op2val:-0x8000001
+TEST_CR_OP( c.xor, x11, x12, 0x8002000, -0x2001, -0x8000001, x1, 20, x2)
+
+inst_6:
+// rs1==x9, rs2==x15, rs2_val == -67108865, rs1_val == -134217729
+// opcode: c.xor; op1:x9; op2:x15; op1val:-0x8000001; op2val:-0x4000001
+TEST_CR_OP( c.xor, x9, x15, 0xc000000, -0x8000001, -0x4000001, x1, 24, x2)
+
+inst_7:
+// rs1==x15, rs2==x14, rs2_val == -33554433, rs1_val == -2049
+// opcode: c.xor; op1:x15; op2:x14; op1val:-0x801; op2val:-0x2000001
+TEST_CR_OP( c.xor, x15, x14, 0x2000800, -0x801, -0x2000001, x1, 28, x2)
+
+inst_8:
+// rs2_val == -16777217, rs1_val == 1048576
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x100000; op2val:-0x1000001
+TEST_CR_OP( c.xor, x10, x11, 0xfeefffff, 0x100000, -0x1000001, x1, 32, x2)
+
+inst_9:
+// rs2_val == -8388609, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x800001
+TEST_CR_OP( c.xor, x10, x11, 0xaa2aaaab, 0x55555554, -0x800001, x1, 36, x2)
+
+inst_10:
+// rs2_val == -4194305, rs1_val == -262145
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x40001; op2val:-0x400001
+TEST_CR_OP( c.xor, x10, x11, 0x440000, -0x40001, -0x400001, x1, 40, x2)
+
+inst_11:
+// rs2_val == -2097153, rs1_val == 256
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x100; op2val:-0x200001
+TEST_CR_OP( c.xor, x10, x11, 0xffdffeff, 0x100, -0x200001, x1, 44, x2)
+
+inst_12:
+// rs2_val == -1048577, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x7; op2val:-0x100001
+TEST_CR_OP( c.xor, x10, x11, 0x100006, -0x7, -0x100001, x1, 48, x2)
+
+inst_13:
+// rs2_val == -524289, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:-0x80001
+TEST_CR_OP( c.xor, x10, x11, 0xfff7fff9, 0x6, -0x80001, x1, 52, x2)
+
+inst_14:
+// rs2_val == -262145, rs1_val == 134217728
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x8000000; op2val:-0x40001
+TEST_CR_OP( c.xor, x10, x11, 0xf7fbffff, 0x8000000, -0x40001, x1, 56, x2)
+
+inst_15:
+// rs2_val == -131073, rs1_val == -3
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x3; op2val:-0x20001
+TEST_CR_OP( c.xor, x10, x11, 0x20002, -0x3, -0x20001, x1, 60, x2)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x9; op2val:-0x10001
+TEST_CR_OP( c.xor, x10, x11, 0xfffefff6, 0x9, -0x10001, x1, 64, x2)
+
+inst_17:
+// rs2_val == -16385, rs1_val == -4097
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x1001; op2val:-0x4001
+TEST_CR_OP( c.xor, x10, x11, 0x5000, -0x1001, -0x4001, x1, 68, x2)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0x2001
+TEST_CR_OP( c.xor, x10, x11, 0xffffdffa, 0x5, -0x2001, x1, 72, x2)
+
+inst_19:
+// rs2_val == -4097, rs1_val == 268435456
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x10000000; op2val:-0x1001
+TEST_CR_OP( c.xor, x10, x11, 0xefffefff, 0x10000000, -0x1001, x1, 76, x2)
+
+inst_20:
+// rs2_val == -2049, rs1_val == -268435457
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x10000001; op2val:-0x801
+TEST_CR_OP( c.xor, x10, x11, 0x10000800, -0x10000001, -0x801, x1, 80, x2)
+
+inst_21:
+// rs2_val == -1025, rs1_val == 0
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:-0x401
+TEST_CR_OP( c.xor, x10, x11, 0xfffffbff, 0x0, -0x401, x1, 84, x2)
+
+inst_22:
+// rs2_val == -513, rs1_val == 4194304
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x400000; op2val:-0x201
+TEST_CR_OP( c.xor, x10, x11, 0xffbffdff, 0x400000, -0x201, x1, 88, x2)
+
+inst_23:
+// rs2_val == -257, rs1_val == -513
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x201; op2val:-0x101
+TEST_CR_OP( c.xor, x10, x11, 0x300, -0x201, -0x101, x1, 92, x2)
+
+inst_24:
+// rs2_val == -129, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xa; op2val:-0x81
+TEST_CR_OP( c.xor, x10, x11, 0x89, -0xa, -0x81, x1, 96, x2)
+
+inst_25:
+// rs2_val == -65, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0x41
+TEST_CR_OP( c.xor, x10, x11, 0xffffffba, 0x5, -0x41, x1, 100, x2)
+
+inst_26:
+// rs2_val == -33, rs1_val == 524288
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x80000; op2val:-0x21
+TEST_CR_OP( c.xor, x10, x11, 0xfff7ffdf, 0x80000, -0x21, x1, 104, x2)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:-0x11
+TEST_CR_OP( c.xor, x10, x11, 0xffff4aec, 0xb503, -0x11, x1, 108, x2)
+
+inst_28:
+// rs2_val == -9, rs1_val == -67108865
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x4000001; op2val:-0x9
+TEST_CR_OP( c.xor, x10, x11, 0x4000008, -0x4000001, -0x9, x1, 112, x2)
+
+inst_29:
+// rs2_val == -5, rs1_val == -5
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x5; op2val:-0x5
+TEST_CR_OP( c.xor, x10, x11, 0x0, -0x5, -0x5, x1, 116, x2)
+
+inst_30:
+// rs2_val == -3, rs1_val == 2097152
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x200000; op2val:-0x3
+TEST_CR_OP( c.xor, x10, x11, 0xffdffffd, 0x200000, -0x3, x1, 120, x2)
+
+inst_31:
+// rs2_val == -2, rs1_val == 131072
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x20000; op2val:-0x2
+TEST_CR_OP( c.xor, x10, x11, 0xfffdfffe, 0x20000, -0x2, x1, 124, x2)
+
+inst_32:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs2_val == 0
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x7fffffff; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x7fffffff, 0x7fffffff, 0x0, x1, 128, x2)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 131072
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x40000001; op2val:0x20000
+TEST_CR_OP( c.xor, x10, x11, 0xbffdffff, -0x40000001, 0x20000, x1, 132, x2)
+
+inst_34:
+// rs1_val == -536870913, rs2_val == 1073741824
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x20000001; op2val:0x40000000
+TEST_CR_OP( c.xor, x10, x11, 0x9fffffff, -0x20000001, 0x40000000, x1, 136, x2)
+
+inst_35:
+// rs1_val == -33554433, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x2000001; op2val:0x7
+TEST_CR_OP( c.xor, x10, x11, 0xfdfffff8, -0x2000001, 0x7, x1, 140, x2)
+
+inst_36:
+// rs1_val == -16777217, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x1000001; op2val:0x7fffffff
+TEST_CR_OP( c.xor, x10, x11, 0x81000000, -0x1000001, 0x7fffffff, x1, 144, x2)
+
+inst_37:
+// rs1_val == -8388609, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x800001; op2val:-0x80001
+TEST_CR_OP( c.xor, x10, x11, 0x880000, -0x800001, -0x80001, x1, 148, x2)
+
+inst_38:
+// rs1_val == -4194305, rs2_val == 4
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x400001; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xffbffffb, -0x400001, 0x4, x1, 152, x2)
+
+inst_39:
+// rs1_val == -2097153, rs2_val == 524288
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x200001; op2val:0x80000
+TEST_CR_OP( c.xor, x10, x11, 0xffd7ffff, -0x200001, 0x80000, x1, 156, x2)
+
+inst_40:
+// rs1_val == -1048577, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x100001; op2val:-0x801
+TEST_CR_OP( c.xor, x10, x11, 0x100800, -0x100001, -0x801, x1, 160, x2)
+
+inst_41:
+// rs1_val == -524289, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x80001; op2val:-0x40000001
+TEST_CR_OP( c.xor, x10, x11, 0x40080000, -0x80001, -0x40000001, x1, 164, x2)
+
+inst_42:
+// rs1_val == -131073, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x20001; op2val:-0x2000001
+TEST_CR_OP( c.xor, x10, x11, 0x2020000, -0x20001, -0x2000001, x1, 168, x2)
+
+inst_43:
+// rs1_val == -65537, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x10001; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xfffefffb, -0x10001, 0x4, x1, 172, x2)
+
+inst_44:
+// rs1_val == -32769, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x8001; op2val:-0x7
+TEST_CR_OP( c.xor, x10, x11, 0x8006, -0x8001, -0x7, x1, 176, x2)
+
+inst_45:
+// rs1_val == -16385, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x4001; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xffff0afa, -0x4001, 0xb505, x1, 180, x2)
+
+inst_46:
+// rs1_val == -1025, rs2_val == 4194304
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x401; op2val:0x400000
+TEST_CR_OP( c.xor, x10, x11, 0xffbffbff, -0x401, 0x400000, x1, 184, x2)
+
+inst_47:
+// rs1_val == -257, rs2_val == 2048
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x101; op2val:0x800
+TEST_CR_OP( c.xor, x10, x11, 0xfffff6ff, -0x101, 0x800, x1, 188, x2)
+
+inst_48:
+// rs1_val == -129, rs2_val == 67108864
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x81; op2val:0x4000000
+TEST_CR_OP( c.xor, x10, x11, 0xfbffff7f, -0x81, 0x4000000, x1, 192, x2)
+
+inst_49:
+// rs1_val == -65, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x41; op2val:0x7fffffff
+TEST_CR_OP( c.xor, x10, x11, 0x80000040, -0x41, 0x7fffffff, x1, 196, x2)
+
+inst_50:
+// rs1_val == -33, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x21; op2val:-0x401
+TEST_CR_OP( c.xor, x10, x11, 0x420, -0x21, -0x401, x1, 200, x2)
+
+inst_51:
+// rs1_val == -17, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x11; op2val:0x7fffffff
+TEST_CR_OP( c.xor, x10, x11, 0x80000010, -0x11, 0x7fffffff, x1, 204, x2)
+
+inst_52:
+// rs1_val == -9, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x9; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x99999992, -0x9, 0x66666665, x1, 208, x2)
+
+inst_53:
+// rs1_val == -2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x2; op2val:0x9
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff7, -0x2, 0x9, x1, 212, x2)
+
+inst_54:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x80000000
+TEST_CR_OP( c.xor, x10, x11, 0xd5555556, 0x55555556, -0x80000000, x1, 216, x2)
+
+inst_55:
+// rs2_val == 536870912, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x200000; op2val:0x20000000
+TEST_CR_OP( c.xor, x10, x11, 0x20200000, 0x200000, 0x20000000, x1, 220, x2)
+
+inst_56:
+// rs2_val == 268435456, rs1_val == 4
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x10000000
+TEST_CR_OP( c.xor, x10, x11, 0x10000004, 0x4, 0x10000000, x1, 224, x2)
+
+inst_57:
+// rs2_val == 134217728, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x8000000
+TEST_CR_OP( c.xor, x10, x11, 0x3b333334, 0x33333334, 0x8000000, x1, 228, x2)
+
+inst_58:
+// rs2_val == 33554432, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x2000001; op2val:0x2000000
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, -0x2000001, 0x2000000, x1, 232, x2)
+
+inst_59:
+// rs2_val == 16777216, rs1_val == 1431655765
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x1000000
+TEST_CR_OP( c.xor, x10, x11, 0x54555555, 0x55555555, 0x1000000, x1, 236, x2)
+
+inst_60:
+// rs2_val == 8388608, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x800000
+TEST_CR_OP( c.xor, x10, x11, 0x33b33334, 0x33333334, 0x800000, x1, 240, x2)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x40001; op2val:0x200000
+TEST_CR_OP( c.xor, x10, x11, 0xffdbffff, -0x40001, 0x200000, x1, 244, x2)
+
+inst_62:
+// rs2_val == 1048576, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x800001; op2val:0x100000
+TEST_CR_OP( c.xor, x10, x11, 0xff6fffff, -0x800001, 0x100000, x1, 248, x2)
+
+inst_63:
+// rs2_val == 262144, rs1_val == -1431655766
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x40000
+TEST_CR_OP( c.xor, x10, x11, 0xaaaeaaaa, -0x55555556, 0x40000, x1, 252, x2)
+
+inst_64:
+// rs2_val == 65536, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x800001; op2val:0x10000
+TEST_CR_OP( c.xor, x10, x11, 0xff7effff, -0x800001, 0x10000, x1, 256, x2)
+
+inst_65:
+// rs2_val == 32768, rs1_val == 67108864
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4000000; op2val:0x8000
+TEST_CR_OP( c.xor, x10, x11, 0x4008000, 0x4000000, 0x8000, x1, 260, x2)
+
+inst_66:
+// rs2_val == 16384, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4000000; op2val:0x4000
+TEST_CR_OP( c.xor, x10, x11, 0x4004000, 0x4000000, 0x4000, x1, 264, x2)
+
+inst_67:
+// rs2_val == 8192, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2000
+TEST_CR_OP( c.xor, x10, x11, 0x55557555, 0x55555555, 0x2000, x1, 268, x2)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x100001; op2val:0x1000
+TEST_CR_OP( c.xor, x10, x11, 0xffefefff, -0x100001, 0x1000, x1, 272, x2)
+
+inst_69:
+// rs2_val == 1024, rs1_val == 65536
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x10000; op2val:0x400
+TEST_CR_OP( c.xor, x10, x11, 0x10400, 0x10000, 0x400, x1, 276, x2)
+
+inst_70:
+// rs2_val == 512, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x8000000; op2val:0x200
+TEST_CR_OP( c.xor, x10, x11, 0x8000200, 0x8000000, 0x200, x1, 280, x2)
+
+inst_71:
+// rs2_val == 256, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x80000; op2val:0x100
+TEST_CR_OP( c.xor, x10, x11, 0x80100, 0x80000, 0x100, x1, 284, x2)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x3; op2val:0x80
+TEST_CR_OP( c.xor, x10, x11, 0xffffff7d, -0x3, 0x80, x1, 288, x2)
+
+inst_73:
+// rs2_val == 64, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x100; op2val:0x40
+TEST_CR_OP( c.xor, x10, x11, 0x140, 0x100, 0x40, x1, 292, x2)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x20
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaa8b, -0x55555555, 0x20, x1, 296, x2)
+
+inst_75:
+// rs2_val == 16, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3fffffff; op2val:0x10
+TEST_CR_OP( c.xor, x10, x11, 0x3fffffef, 0x3fffffff, 0x10, x1, 300, x2)
+
+inst_76:
+// rs2_val == 8, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x400001; op2val:0x8
+TEST_CR_OP( c.xor, x10, x11, 0xffbffff7, -0x400001, 0x8, x1, 304, x2)
+
+inst_77:
+// rs2_val == 2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xa; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff4, -0xa, 0x2, x1, 308, x2)
+
+inst_78:
+// rs2_val == 1, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x3; op2val:0x1
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffc, -0x3, 0x1, x1, 312, x2)
+
+inst_79:
+// rs1_val == 536870912, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x20000000; op2val:-0x80000000
+TEST_CR_OP( c.xor, x10, x11, 0xa0000000, 0x20000000, -0x80000000, x1, 316, x2)
+
+inst_80:
+// rs1_val == 33554432, rs2_val == 1431655765
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2000000; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x57555555, 0x2000000, 0x55555555, x1, 320, x2)
+
+inst_81:
+// rs1_val == 16777216, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x1000000; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x32333332, 0x1000000, 0x33333332, x1, 324, x2)
+
+inst_82:
+// rs1_val == 8388608, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x800000; op2val:-0x1000001
+TEST_CR_OP( c.xor, x10, x11, 0xfe7fffff, 0x800000, -0x1000001, x1, 328, x2)
+
+inst_83:
+// rs1_val == 262144, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x40000; op2val:0x40000000
+TEST_CR_OP( c.xor, x10, x11, 0x40040000, 0x40000, 0x40000000, x1, 332, x2)
+
+inst_84:
+// rs1_val == 32768, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x8000; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x6666e666, 0x8000, 0x66666666, x1, 336, x2)
+
+inst_85:
+// rs1_val == 16384, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4000; op2val:-0x2001
+TEST_CR_OP( c.xor, x10, x11, 0xffff9fff, 0x4000, -0x2001, x1, 340, x2)
+
+inst_86:
+// rs1_val == 8192, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2000; op2val:0x8000
+TEST_CR_OP( c.xor, x10, x11, 0xa000, 0x2000, 0x8000, x1, 344, x2)
+
+inst_87:
+// rs1_val == 4096, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x1000; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff5afc, 0x1000, -0xb504, x1, 348, x2)
+
+inst_88:
+// rs1_val == 2048, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x800; op2val:-0x401
+TEST_CR_OP( c.xor, x10, x11, 0xfffff3ff, 0x800, -0x401, x1, 352, x2)
+
+inst_89:
+// rs1_val == 1024, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x400; op2val:0x8
+TEST_CR_OP( c.xor, x10, x11, 0x408, 0x400, 0x8, x1, 356, x2)
+
+inst_90:
+// rs1_val == 512, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x200; op2val:-0x100001
+TEST_CR_OP( c.xor, x10, x11, 0xffeffdff, 0x200, -0x100001, x1, 360, x2)
+
+inst_91:
+// rs1_val == 128, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x80; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb584, 0x80, 0xb504, x1, 364, x2)
+
+inst_92:
+// rs1_val == 16, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x10; op2val:-0x20000001
+TEST_CR_OP( c.xor, x10, x11, 0xdfffffef, 0x10, -0x20000001, x1, 368, x2)
+
+inst_93:
+// rs1_val == 8, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x8; op2val:-0x1000001
+TEST_CR_OP( c.xor, x10, x11, 0xfefffff7, 0x8, -0x1000001, x1, 372, x2)
+
+inst_94:
+// rs1_val == 2, rs1_val==2 and rs2_val==6
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x4, 0x2, 0x6, x1, 376, x2)
+
+inst_95:
+// rs1_val == 1, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x1; op2val:-0x20001
+TEST_CR_OP( c.xor, x10, x11, 0xfffdfffe, 0x1, -0x20001, x1, 380, x2)
+
+inst_96:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0xb505, 0xb505, x1, 384, x2)
+
+inst_97:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff8, 0xb505, -0xb503, x1, 388, x2)
+
+inst_98:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x6666d362, 0xb505, 0x66666667, x1, 392, x2)
+
+inst_99:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33338631, 0xb505, 0x33333334, x1, 396, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xb503, 0xb505, 0x6, x1, 400, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fae, 0xb505, -0x55555555, x1, 404, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x5555e053, 0xb505, 0x55555556, x1, 408, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0xb505, 0x4, x1, 412, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0xb505, 0xb503, x1, 416, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xb505, 0xb505, 0x0, x1, 420, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x6666d360, 0xb505, 0x66666665, x1, 424, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0xb505, 0x33333332, x1, 428, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x5555e051, 0xb505, 0x55555554, x1, 432, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0xb505, 0x2, x1, 436, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0xb505, 0xb504, x1, 440, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff9, 0xb505, -0xb504, x1, 444, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x6666d363, 0xb505, 0x66666666, x1, 448, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33338636, 0xb505, 0x33333333, x1, 452, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0xb505, 0x5, x1, 456, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faf, 0xb505, -0x55555556, x1, 460, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x5555e050, 0xb505, 0x55555555, x1, 464, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb505; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0xb505, 0x3, x1, 468, x2)
+
+inst_118:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff8, -0xb503, 0xb505, x1, 472, x2)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x0, -0xb503, -0xb503, x1, 476, x2)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9a, -0xb503, 0x66666667, x1, 480, x2)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79c9, -0xb503, 0x33333334, x1, 484, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afb, -0xb503, 0x6, x1, 488, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, -0xb503, -0x55555555, x1, 492, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fab, -0xb503, 0x55555556, x1, 496, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af9, -0xb503, 0x4, x1, 500, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, -0xb503, 0xb503, x1, 504, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 508, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x99992c98, -0xb503, 0x66666665, x1, 512, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79cf, -0xb503, 0x33333332, x1, 516, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, -0xb503, 0x55555554, x1, 520, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xffff4aff, -0xb503, 0x2, x1, 524, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff9, -0xb503, 0xb504, x1, 528, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x1, -0xb503, -0xb504, x1, 532, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9b, -0xb503, 0x66666666, x1, 536, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79ce, -0xb503, 0x33333333, x1, 540, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af8, -0xb503, 0x5, x1, 544, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, -0xb503, -0x55555556, x1, 548, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, -0xb503, 0x55555555, x1, 552, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb503; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afe, -0xb503, 0x3, x1, 556, x2)
+
+inst_140:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x6666d362, 0x66666667, 0xb505, x1, 560, x2)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9a, 0x66666667, -0xb503, x1, 564, x2)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x66666667, 0x66666667, x1, 568, x2)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x66666667, 0x33333334, x1, 572, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x66666667, 0x6, x1, 576, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccc, 0x66666667, -0x55555555, x1, 580, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x66666667, 0x55555556, x1, 584, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x66666667, 0x4, x1, 588, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x6666d364, 0x66666667, 0xb503, x1, 592, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 596, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x66666667, 0x66666665, x1, 600, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x66666667, 0x33333332, x1, 604, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x66666667, 0x55555554, x1, 608, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x66666667, 0x2, x1, 612, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x6666d363, 0x66666667, 0xb504, x1, 616, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9b, 0x66666667, -0xb504, x1, 620, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 624, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x66666667, 0x33333333, x1, 628, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x66666667, 0x5, x1, 632, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccd, 0x66666667, -0x55555556, x1, 636, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x66666667, 0x55555555, x1, 640, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666667; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x66666667, 0x3, x1, 644, x2)
+
+inst_162:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x33338631, 0x33333334, 0xb505, x1, 648, x2)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79c9, 0x33333334, -0xb503, x1, 652, x2)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x33333334, 0x66666667, x1, 656, x2)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x33333334, 0x33333334, x1, 660, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x33333334, 0x6, x1, 664, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x9999999f, 0x33333334, -0x55555555, x1, 668, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x33333334, 0x55555556, x1, 672, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x33333334, 0x4, x1, 676, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0x33333334, 0xb503, x1, 680, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 684, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x33333334, 0x66666665, x1, 688, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x33333334, 0x33333332, x1, 692, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x33333334, 0x55555554, x1, 696, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x33333334, 0x2, x1, 700, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x33338630, 0x33333334, 0xb504, x1, 704, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79c8, 0x33333334, -0xb504, x1, 708, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x33333334, 0x66666666, x1, 712, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x33333334, 0x33333333, x1, 716, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x33333334, 0x5, x1, 720, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x9999999e, 0x33333334, -0x55555556, x1, 724, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x33333334, 0x55555555, x1, 728, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333334; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x33333334, 0x3, x1, 732, x2)
+
+inst_184:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb503, 0x6, 0xb505, x1, 736, x2)
+
+inst_185:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afb, 0x6, -0xb503, x1, 740, x2)
+
+inst_186:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x6, 0x66666667, x1, 744, x2)
+
+inst_187:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x6, 0x33333334, x1, 748, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x6, 0x6, x1, 752, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaad, 0x6, -0x55555555, x1, 756, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x6, 0x55555556, x1, 760, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x6, 0x4, x1, 764, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb505, 0x6, 0xb503, x1, 768, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x6, 0x0, x1, 772, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x6, 0x66666665, x1, 776, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333334, 0x6, 0x33333332, x1, 780, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x6, 0x55555554, x1, 784, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x4, 0x6, 0x2, x1, 788, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb502, 0x6, 0xb504, x1, 792, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afa, 0x6, -0xb504, x1, 796, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x6, 0x66666666, x1, 800, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333335, 0x6, 0x33333333, x1, 804, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x6, 0x5, x1, 808, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaac, 0x6, -0x55555556, x1, 812, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x6, 0x55555555, x1, 816, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x6; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x5, 0x6, 0x3, x1, 820, x2)
+
+inst_206:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fae, -0x55555555, 0xb505, x1, 824, x2)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, -0x55555555, -0xb503, x1, 828, x2)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccc, -0x55555555, 0x66666667, x1, 832, x2)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x9999999f, -0x55555555, 0x33333334, x1, 836, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaad, -0x55555555, 0x6, x1, 840, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x0, -0x55555555, -0x55555555, x1, 844, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffd, -0x55555555, 0x55555556, x1, 848, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x1, 852, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, -0x55555555, 0xb503, x1, 856, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 860, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0xccccccce, -0x55555555, 0x66666665, x1, 864, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x99999999, -0x55555555, 0x33333332, x1, 868, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x1, 872, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa9, -0x55555555, 0x2, x1, 876, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faf, -0x55555555, 0xb504, x1, 880, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, -0x55555555, -0xb504, x1, 884, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccd, -0x55555555, 0x66666666, x1, 888, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x99999998, -0x55555555, 0x33333333, x1, 892, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaae, -0x55555555, 0x5, x1, 896, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x1, -0x55555555, -0x55555556, x1, 900, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, -0x55555555, 0x55555555, x1, 904, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa8, -0x55555555, 0x3, x1, 908, x2)
+
+inst_228:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x5555e053, 0x55555556, 0xb505, x1, 912, x2)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fab, 0x55555556, -0xb503, x1, 916, x2)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x55555556, 0x66666667, x1, 920, x2)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x55555556, 0x33333334, x1, 924, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x55555556, 0x6, x1, 928, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffd, 0x55555556, -0x55555555, x1, 932, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x55555556, 0x55555556, x1, 936, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x55555556, 0x4, x1, 940, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x5555e055, 0x55555556, 0xb503, x1, 944, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 948, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x55555556, 0x66666665, x1, 952, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x55555556, 0x33333332, x1, 956, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x55555556, 0x55555554, x1, 960, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x55555556, 0x2, x1, 964, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x5555e052, 0x55555556, 0xb504, x1, 968, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faa, 0x55555556, -0xb504, x1, 972, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x55555556, 0x66666666, x1, 976, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x55555556, 0x33333333, x1, 980, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x55555556, 0x5, x1, 984, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffc, 0x55555556, -0x55555556, x1, 988, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x55555556, 0x55555555, x1, 992, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555556; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x55555556, 0x3, x1, 996, x2)
+
+inst_250:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0x4, 0xb505, x1, 1000, x2)
+
+inst_251:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af9, 0x4, -0xb503, x1, 1004, x2)
+
+inst_252:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x4, 0x66666667, x1, 1008, x2)
+
+inst_253:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x4, 0x33333334, x1, 1012, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x4, 0x6, x1, 1016, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x1, 1020, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x4, 0x55555556, x1, 1024, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x4, 0x4, x1, 1028, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0x4, 0xb503, x1, 1032, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x4, 0x4, 0x0, x1, 1036, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x4, 0x66666665, x1, 1040, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x4, 0x33333332, x1, 1044, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x4, 0x55555554, x1, 1048, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x4, 0x2, x1, 1052, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0x4, 0xb504, x1, 1056, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af8, 0x4, -0xb504, x1, 1060, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x4, 0x66666666, x1, 1064, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x4, 0x33333333, x1, 1068, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x4, 0x5, x1, 1072, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x1, 1076, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x4, 0x55555555, x1, 1080, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x4; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x4, 0x3, x1, 1084, x2)
+
+inst_272:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0xb503, 0xb505, x1, 1088, x2)
+
+inst_273:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, 0xb503, -0xb503, x1, 1092, x2)
+
+inst_274:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x6666d364, 0xb503, 0x66666667, x1, 1096, x2)
+
+inst_275:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0xb503, 0x33333334, x1, 1100, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xb505, 0xb503, 0x6, x1, 1104, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, 0xb503, -0x55555555, x1, 1108, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x5555e055, 0xb503, 0x55555556, x1, 1112, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0xb503, 0x4, x1, 1116, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0xb503, 0xb503, x1, 1120, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xb503, 0xb503, 0x0, x1, 1124, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x6666d366, 0xb503, 0x66666665, x1, 1128, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33338631, 0xb503, 0x33333332, x1, 1132, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, 0xb503, 0x55555554, x1, 1136, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0xb503, 0x2, x1, 1140, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0xb503, 0xb504, x1, 1144, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, 0xb503, -0xb504, x1, 1148, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x6666d365, 0xb503, 0x66666666, x1, 1152, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33338630, 0xb503, 0x33333333, x1, 1156, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0xb503, 0x5, x1, 1160, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, 0xb503, -0x55555556, x1, 1164, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, 0xb503, 0x55555555, x1, 1168, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb503; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0xb503, 0x3, x1, 1172, x2)
+
+inst_294:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb505, 0x0, 0xb505, x1, 1176, x2)
+
+inst_295:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afd, 0x0, -0xb503, x1, 1180, x2)
+
+inst_296:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x0, 0x66666667, x1, 1184, x2)
+
+inst_297:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333334, 0x0, 0x33333334, x1, 1188, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x0, 0x6, x1, 1192, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x1, 1196, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x0, 0x55555556, x1, 1200, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x4, 0x0, 0x4, x1, 1204, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb503, 0x0, 0xb503, x1, 1208, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x0, 0x0, x1, 1212, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x0, 0x66666665, x1, 1216, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x0, 0x33333332, x1, 1220, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x0, 0x55555554, x1, 1224, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x0, 0x2, x1, 1228, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb504, 0x0, 0xb504, x1, 1232, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afc, 0x0, -0xb504, x1, 1236, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x0, 0x66666666, x1, 1240, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x0, 0x33333333, x1, 1244, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x5, 0x0, 0x5, x1, 1248, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x1, 1252, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x0, 0x55555555, x1, 1256, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x0; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x0, 0x3, x1, 1260, x2)
+
+inst_316:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x6666d360, 0x66666665, 0xb505, x1, 1264, x2)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x99992c98, 0x66666665, -0xb503, x1, 1268, x2)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x66666665, 0x66666667, x1, 1272, x2)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x66666665, 0x33333334, x1, 1276, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x66666665, 0x6, x1, 1280, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xccccccce, 0x66666665, -0x55555555, x1, 1284, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x66666665, 0x55555556, x1, 1288, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x66666665, 0x4, x1, 1292, x2)
+
+inst_324:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1296, x2)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x33333333, 0x66666665, x1, 1300, x2)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 1304, x2)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x33333333, 0x55555554, x1, 1308, x2)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x33333333, 0x2, x1, 1312, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0x33333333, 0xb504, x1, 1316, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79cf, 0x33333333, -0xb504, x1, 1320, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x33333333, 0x66666666, x1, 1324, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x33333333, 0x33333333, x1, 1328, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x33333333, 0x5, x1, 1332, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x99999999, 0x33333333, -0x55555556, x1, 1336, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x33333333, 0x55555555, x1, 1340, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x33333333, 0x3, x1, 1344, x2)
+
+inst_337:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0x5, 0xb505, x1, 1348, x2)
+
+inst_338:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af8, 0x5, -0xb503, x1, 1352, x2)
+
+inst_339:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x5, 0x66666667, x1, 1356, x2)
+
+inst_340:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x5, 0x33333334, x1, 1360, x2)
+
+inst_341:
+// rs1_val==5 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x5, 0x6, x1, 1364, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaae, 0x5, -0x55555555, x1, 1368, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x5, 0x55555556, x1, 1372, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x5, 0x4, x1, 1376, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0x5, 0xb503, x1, 1380, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x5, 0x5, 0x0, x1, 1384, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x5, 0x66666665, x1, 1388, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x5, 0x33333332, x1, 1392, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x5, 0x55555554, x1, 1396, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x5, 0x2, x1, 1400, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0x5, 0xb504, x1, 1404, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af9, 0x5, -0xb504, x1, 1408, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x5, 0x66666666, x1, 1412, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x5, 0x33333333, x1, 1416, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x5, 0x5, x1, 1420, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x1, 1424, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x5, 0x55555555, x1, 1428, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x5; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x5, 0x3, x1, 1432, x2)
+
+inst_359:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faf, -0x55555556, 0xb505, x1, 1436, x2)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, -0x55555556, -0xb503, x1, 1440, x2)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccd, -0x55555556, 0x66666667, x1, 1444, x2)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x9999999e, -0x55555556, 0x33333334, x1, 1448, x2)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaac, -0x55555556, 0x6, x1, 1452, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x1, -0x55555556, -0x55555555, x1, 1456, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffc, -0x55555556, 0x55555556, x1, 1460, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x1, 1464, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, -0x55555556, 0xb503, x1, 1468, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1472, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccf, -0x55555556, 0x66666665, x1, 1476, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x99999998, -0x55555556, 0x33333332, x1, 1480, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x1, 1484, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa8, -0x55555556, 0x2, x1, 1488, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fae, -0x55555556, 0xb504, x1, 1492, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, -0x55555556, -0xb504, x1, 1496, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccc, -0x55555556, 0x66666666, x1, 1500, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x99999999, -0x55555556, 0x33333333, x1, 1504, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1508, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x0, -0x55555556, -0x55555556, x1, 1512, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x1, 1516, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa9, -0x55555556, 0x3, x1, 1520, x2)
+
+inst_381:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x5555e050, 0x55555555, 0xb505, x1, 1524, x2)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, 0x55555555, -0xb503, x1, 1528, x2)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x55555555, 0x66666667, x1, 1532, x2)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x66666661, 0x55555555, 0x33333334, x1, 1536, x2)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x55555553, 0x55555555, 0x6, x1, 1540, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, 0x55555555, -0x55555555, x1, 1544, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x55555555, 0x55555556, x1, 1548, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x55555555, 0x4, x1, 1552, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, 0x55555555, 0xb503, x1, 1556, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1560, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x55555555, 0x66666665, x1, 1564, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x55555555, 0x33333332, x1, 1568, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 1572, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x55555555, 0x2, x1, 1576, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x5555e051, 0x55555555, 0xb504, x1, 1580, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, 0x55555555, -0xb504, x1, 1584, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x55555555, 0x66666666, x1, 1588, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x55555555, 0x33333333, x1, 1592, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x55555555, 0x5, x1, 1596, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x1, 1600, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x55555555, 0x55555555, x1, 1604, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555555; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x55555555, 0x3, x1, 1608, x2)
+
+inst_403:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0x3, 0xb505, x1, 1612, x2)
+
+inst_404:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afe, 0x3, -0xb503, x1, 1616, x2)
+
+inst_405:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x3, 0x66666667, x1, 1620, x2)
+
+inst_406:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x3, 0x33333334, x1, 1624, x2)
+
+inst_407:
+// rs1_val==3 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x5, 0x3, 0x6, x1, 1628, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa8, 0x3, -0x55555555, x1, 1632, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x3, 0x55555556, x1, 1636, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x3, 0x4, x1, 1640, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0x3, 0xb503, x1, 1644, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x3, 0x0, x1, 1648, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x3, 0x66666665, x1, 1652, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x3, 0x33333332, x1, 1656, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x3, 0x55555554, x1, 1660, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x3, 0x2, x1, 1664, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0x3, 0xb504, x1, 1668, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4aff, 0x3, -0xb504, x1, 1672, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x3, 0x66666666, x1, 1676, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x3, 0x33333333, x1, 1680, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x3, 0x5, x1, 1684, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa9, 0x3, -0x55555556, x1, 1688, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x3, 0x55555555, x1, 1692, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x3; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x3, 0x3, x1, 1696, x2)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x6666d366, 0x66666665, 0xb503, x1, 1700, x2)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1704, x2)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x66666665, 0x66666665, x1, 1708, x2)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x66666665, 0x33333332, x1, 1712, x2)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x66666665, 0x55555554, x1, 1716, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x66666665, 0x2, x1, 1720, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x6666d361, 0x66666665, 0xb504, x1, 1724, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x99992c99, 0x66666665, -0xb504, x1, 1728, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x66666665, 0x66666666, x1, 1732, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x66666665, 0x33333333, x1, 1736, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x66666665, 0x5, x1, 1740, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccf, 0x66666665, -0x55555556, x1, 1744, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x66666665, 0x55555555, x1, 1748, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666665; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x66666665, 0x3, x1, 1752, x2)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0x33333332, 0xb505, x1, 1756, x2)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79cf, 0x33333332, -0xb503, x1, 1760, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x33333332, 0x66666667, x1, 1764, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x33333332, 0x33333334, x1, 1768, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x33333334, 0x33333332, 0x6, x1, 1772, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x99999999, 0x33333332, -0x55555555, x1, 1776, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x33333332, 0x55555556, x1, 1780, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x33333332, 0x4, x1, 1784, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x33338631, 0x33333332, 0xb503, x1, 1788, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1792, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x33333332, 0x66666665, x1, 1796, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x33333332, 0x33333332, x1, 1800, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x33333332, 0x55555554, x1, 1804, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x33333332, 0x2, x1, 1808, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x33338636, 0x33333332, 0xb504, x1, 1812, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79ce, 0x33333332, -0xb504, x1, 1816, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x33333332, 0x66666666, x1, 1820, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x33333332, 0x33333333, x1, 1824, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x33333332, 0x5, x1, 1828, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x99999998, 0x33333332, -0x55555556, x1, 1832, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x33333332, 0x55555555, x1, 1836, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333332; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x33333332, 0x3, x1, 1840, x2)
+
+inst_461:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x5555e051, 0x55555554, 0xb505, x1, 1844, x2)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, 0x55555554, -0xb503, x1, 1848, x2)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x55555554, 0x66666667, x1, 1852, x2)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x55555554, 0x33333334, x1, 1856, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x55555554, 0x6, x1, 1860, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x1, 1864, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x55555554, 0x55555556, x1, 1868, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x55555550, 0x55555554, 0x4, x1, 1872, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, 0x55555554, 0xb503, x1, 1876, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1880, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x55555554, 0x66666665, x1, 1884, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x55555554, 0x33333332, x1, 1888, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x55555554, 0x55555554, x1, 1892, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x55555554, 0x2, x1, 1896, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x5555e050, 0x55555554, 0xb504, x1, 1900, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, 0x55555554, -0xb504, x1, 1904, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x55555554, 0x66666666, x1, 1908, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x55555554, 0x33333333, x1, 1912, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x55555551, 0x55555554, 0x5, x1, 1916, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x1, 1920, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x55555554, 0x55555555, x1, 1924, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x55555554; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x55555554, 0x3, x1, 1928, x2)
+
+inst_483:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0x2, 0xb505, x1, 1932, x2)
+
+inst_484:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffff4aff, 0x2, -0xb503, x1, 1936, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x2, 0x66666667, x1, 1940, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33333336, 0x2, 0x33333334, x1, 1944, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa9, 0x2, -0x55555555, x1, 1948, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x2, 0x55555556, x1, 1952, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x6, 0x2, 0x4, x1, 1956, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0x2, 0xb503, x1, 1960, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x2, 0x2, 0x0, x1, 1964, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x66666667, 0x2, 0x66666665, x1, 1968, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x2, 0x33333332, x1, 1972, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x55555556, 0x2, 0x55555554, x1, 1976, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x2, 0x2, x1, 1980, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0x2, 0xb504, x1, 1984, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afe, 0x2, -0xb504, x1, 1988, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x2, 0x66666666, x1, 1992, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33333331, 0x2, 0x33333333, x1, 1996, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x2, 0x5, x1, 2000, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaaaaa8, 0x2, -0x55555556, x1, 2004, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x55555557, 0x2, 0x55555555, x1, 2008, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x2; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x2, 0x3, x1, 2012, x2)
+
+inst_504:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0xb504, 0xb505, x1, 2016, x2)
+
+inst_505:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff9, 0xb504, -0xb503, x1, 2020, x2)
+
+inst_506:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x6666d363, 0xb504, 0x66666667, x1, 2024, x2)
+
+inst_507:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x33338630, 0xb504, 0x33333334, x1, 2028, x2)
+
+inst_508:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xb502, 0xb504, 0x6, x1, 2032, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faf, 0xb504, -0x55555555, x1, 2036, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x5555e052, 0xb504, 0x55555556, x1, 2040, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xb500, 0xb504, 0x4, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0xb504, 0xb503, x1, 0, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xb504, 0xb504, 0x0, x1, 4, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x6666d361, 0xb504, 0x66666665, x1, 8, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x33338636, 0xb504, 0x33333332, x1, 12, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x5555e050, 0xb504, 0x55555554, x1, 16, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xb506, 0xb504, 0x2, x1, 20, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0xb504, 0xb504, x1, 24, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff8, 0xb504, -0xb504, x1, 28, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x6666d362, 0xb504, 0x66666666, x1, 32, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x33338637, 0xb504, 0x33333333, x1, 36, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xb501, 0xb504, 0x5, x1, 40, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fae, 0xb504, -0x55555556, x1, 44, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x5555e051, 0xb504, 0x55555555, x1, 48, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0xb504; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xb507, 0xb504, 0x3, x1, 52, x2)
+
+inst_526:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff9, -0xb504, 0xb505, x1, 56, x2)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x1, -0xb504, -0xb503, x1, 60, x2)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9b, -0xb504, 0x66666667, x1, 64, x2)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79c8, -0xb504, 0x33333334, x1, 68, x2)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afa, -0xb504, 0x6, x1, 72, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x5555e057, -0xb504, -0x55555555, x1, 76, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1faa, -0xb504, 0x55555556, x1, 80, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af8, -0xb504, 0x4, x1, 84, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 88, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 92, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x99992c99, -0xb504, 0x66666665, x1, 96, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79ce, -0xb504, 0x33333332, x1, 100, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa8, -0xb504, 0x55555554, x1, 104, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0xffff4afe, -0xb504, 0x2, x1, 108, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0xfffffff8, -0xb504, 0xb504, x1, 112, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x0, -0xb504, -0xb504, x1, 116, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9a, -0xb504, 0x66666666, x1, 120, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79cf, -0xb504, 0x33333333, x1, 124, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0xffff4af9, -0xb504, 0x5, x1, 128, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x5555e056, -0xb504, -0x55555556, x1, 132, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xaaaa1fa9, -0xb504, 0x55555555, x1, 136, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:-0xb504; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0xffff4aff, -0xb504, 0x3, x1, 140, x2)
+
+inst_548:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x6666d363, 0x66666666, 0xb505, x1, 144, x2)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9b, 0x66666666, -0xb503, x1, 148, x2)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x1, 0x66666666, 0x66666667, x1, 152, x2)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x55555552, 0x66666666, 0x33333334, x1, 156, x2)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x66666660, 0x66666666, 0x6, x1, 160, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccd, 0x66666666, -0x55555555, x1, 164, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x33333330, 0x66666666, 0x55555556, x1, 168, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x66666662, 0x66666666, 0x4, x1, 172, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x6666d365, 0x66666666, 0xb503, x1, 176, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x0
+TEST_CR_OP( c.xor, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 180, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665
+TEST_CR_OP( c.xor, x10, x11, 0x3, 0x66666666, 0x66666665, x1, 184, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x66666666, 0x33333332, x1, 188, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554
+TEST_CR_OP( c.xor, x10, x11, 0x33333332, 0x66666666, 0x55555554, x1, 192, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x2
+TEST_CR_OP( c.xor, x10, x11, 0x66666664, 0x66666666, 0x2, x1, 196, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x6666d362, 0x66666666, 0xb504, x1, 200, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504
+TEST_CR_OP( c.xor, x10, x11, 0x99992c9a, 0x66666666, -0xb504, x1, 204, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666
+TEST_CR_OP( c.xor, x10, x11, 0x0, 0x66666666, 0x66666666, x1, 208, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333
+TEST_CR_OP( c.xor, x10, x11, 0x55555555, 0x66666666, 0x33333333, x1, 212, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x5
+TEST_CR_OP( c.xor, x10, x11, 0x66666663, 0x66666666, 0x5, x1, 216, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0xcccccccc, 0x66666666, -0x55555556, x1, 220, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x33333333, 0x66666666, 0x55555555, x1, 224, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x66666666; op2val:0x3
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x66666666, 0x3, x1, 228, x2)
+
+inst_570:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505
+TEST_CR_OP( c.xor, x10, x11, 0x33338636, 0x33333333, 0xb505, x1, 232, x2)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503
+TEST_CR_OP( c.xor, x10, x11, 0xcccc79ce, 0x33333333, -0xb503, x1, 236, x2)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667
+TEST_CR_OP( c.xor, x10, x11, 0x55555554, 0x33333333, 0x66666667, x1, 240, x2)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334
+TEST_CR_OP( c.xor, x10, x11, 0x7, 0x33333333, 0x33333334, x1, 244, x2)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x6
+TEST_CR_OP( c.xor, x10, x11, 0x33333335, 0x33333333, 0x6, x1, 248, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555
+TEST_CR_OP( c.xor, x10, x11, 0x99999998, 0x33333333, -0x55555555, x1, 252, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556
+TEST_CR_OP( c.xor, x10, x11, 0x66666665, 0x33333333, 0x55555556, x1, 256, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0x4
+TEST_CR_OP( c.xor, x10, x11, 0x33333337, 0x33333333, 0x4, x1, 260, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503
+TEST_CR_OP( c.xor, x10, x11, 0x33338630, 0x33333333, 0xb503, x1, 264, x2)
+
+inst_579:
+// rs2_val == 2147483647, rs1_val == 64, rs2_val == (2**(xlen-1)-1), rs2_val > 0
+// opcode: c.xor; op1:x10; op2:x11; op1val:0x40; op2val:0x7fffffff
+TEST_CR_OP( c.xor, x10, x11, 0x7fffffbf, 0x40, 0x7fffffff, x1, 268, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 68*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefile
new file mode 100644
index 000000000..69e58e890
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32em -mabi=ilp32e -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefrag
new file mode 100644
index 000000000..fc4cc1989
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/Makefrag
@@ -0,0 +1,43 @@
+# RISC-V Architecture Test RV32EM Makefrag
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32EM architectural tests
+
+rv32em_sc_tests = \
+  div-01 \
+  divu-01 \
+  mul-01 \
+  mulh-01 \
+  mulhsu-01 \
+  mulhu-01 \
+  rem-01 \
+  remu-01
+
+rv32em_tests = $(addsuffix .elf, $(rv32em_sc_tests))
+
+target_tests += $(rv32em_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output
new file mode 100644
index 000000000..68ea59019
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/div-01.reference_output
@@ -0,0 +1,581 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output
new file mode 100644
index 000000000..76f0e23b0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/divu-01.reference_output
@@ -0,0 +1,729 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output
new file mode 100644
index 000000000..66fcf6049
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mul-01.reference_output
@@ -0,0 +1,585 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output
new file mode 100644
index 000000000..dba60c2eb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulh-01.reference_output
@@ -0,0 +1,591 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output
new file mode 100644
index 000000000..197dc32c5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhsu-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output
new file mode 100644
index 000000000..4143c8c36
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/mulhu-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output
new file mode 100644
index 000000000..37ac3dfc4
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/rem-01.reference_output
@@ -0,0 +1,586 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output
new file mode 100644
index 000000000..e8914d920
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/references/remu-01.reference_output
@@ -0,0 +1,725 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/div-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/div-01.S
new file mode 100644
index 000000000..4b1fbcac7
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/div-01.S
@@ -0,0 +1,2990 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the div instruction of the RISC-V M extension for the div covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",div)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x7, rs2==x11, rd==x11, rs1_val != rs2_val, rs1_val > 0 and rs2_val > 0, rs2_val == 128
+// opcode: div ; op1:x7; op2:x11; dest:x11; op1val:0x6;  op2val:0x80
+TEST_RR_OP(div, x11, x7, x11, 0x0, 0x6, 0x80, x2, 0, x3)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x15, rs2==x8, rd==x15, rs2_val == 2147483647, rs1_val < 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1), rs1_val == -131073
+// opcode: div ; op1:x15; op2:x8; dest:x15; op1val:-0x20001;  op2val:0x7fffffff
+TEST_RR_OP(div, x15, x15, x8, 0x0, -0x20001, 0x7fffffff, x2, 4, x3)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x9, rs2==x9, rd==x9, rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0
+// opcode: div ; op1:x9; op2:x9; dest:x9; op1val:-0x8;  op2val:-0x8
+TEST_RR_OP(div, x9, x9, x9, 0x1, -0x8, -0x8, x2, 8, x3)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x5, rs2_val == -536870913, rs1_val == 16384, rs1_val > 0 and rs2_val < 0
+// opcode: div ; op1:x4; op2:x4; dest:x5; op1val:0x4000;  op2val:0x4000
+TEST_RR_OP(div, x5, x4, x4, 0x1, 0x4000, 0x4000, x2, 12, x3)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x12, rs2==x0, rd==x7, rs2_val == -268435457, rs1_val == -4194305
+// opcode: div ; op1:x12; op2:x0; dest:x7; op1val:-0x400001;  op2val:0x0
+TEST_RR_OP(div, x7, x12, x0, 0xFFFFFFFF, -0x400001, 0x0, x2, 16, x3)
+
+inst_5:
+// rs1==x6, rs2==x1, rd==x8, rs2_val == -134217729, rs1_val == 16
+// opcode: div ; op1:x6; op2:x1; dest:x8; op1val:0x10;  op2val:-0x8000001
+TEST_RR_OP(div, x8, x6, x1, 0x0, 0x10, -0x8000001, x2, 20, x3)
+
+inst_6:
+// rs1==x13, rs2==x15, rd==x0, rs2_val == -67108865, 
+// opcode: div ; op1:x13; op2:x15; dest:x0; op1val:0x66666666;  op2val:-0x4000001
+TEST_RR_OP(div, x0, x13, x15, 0, 0x66666666, -0x4000001, x2, 24, x3)
+
+inst_7:
+// rs1==x14, rs2==x13, rd==x6, rs2_val == -33554433, rs1_val == 4096
+// opcode: div ; op1:x14; op2:x13; dest:x6; op1val:0x1000;  op2val:-0x2000001
+TEST_RR_OP(div, x6, x14, x13, 0x0, 0x1000, -0x2000001, x2, 28, x9)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_8:
+// rs1==x1, rs2==x5, rd==x10, rs2_val == -16777217, 
+// opcode: div ; op1:x1; op2:x5; dest:x10; op1val:-0x20001;  op2val:-0x1000001
+TEST_RR_OP(div, x10, x1, x5, 0x0, -0x20001, -0x1000001, x4, 0, x9)
+
+inst_9:
+// rs1==x8, rs2==x12, rd==x2, rs2_val == -8388609, rs1_val == 4
+// opcode: div ; op1:x8; op2:x12; dest:x2; op1val:0x4;  op2val:-0x800001
+TEST_RR_OP(div, x2, x8, x12, 0x0, 0x4, -0x800001, x4, 4, x9)
+
+inst_10:
+// rs1==x10, rs2==x3, rd==x1, rs2_val == -4194305, rs1_val == -32769
+// opcode: div ; op1:x10; op2:x3; dest:x1; op1val:-0x8001;  op2val:-0x400001
+TEST_RR_OP(div, x1, x10, x3, 0x0, -0x8001, -0x400001, x4, 8, x9)
+
+inst_11:
+// rs1==x3, rs2==x14, rd==x12, rs2_val == -2097153, rs1_val == 1431655765
+// opcode: div ; op1:x3; op2:x14; dest:x12; op1val:0x55555555;  op2val:-0x200001
+TEST_RR_OP(div, x12, x3, x14, -0x2aa, 0x55555555, -0x200001, x4, 12, x9)
+
+inst_12:
+// rs1==x0, rs2==x6, rd==x13, rs2_val == -1048577, 
+// opcode: div ; op1:x0; op2:x6; dest:x13; op1val:0x0;  op2val:-0x100001
+TEST_RR_OP(div, x13, x0, x6, 0x0, 0x0, -0x100001, x4, 16, x9)
+
+inst_13:
+// rs1==x11, rs2==x7, rd==x3, rs2_val == -524289, rs1_val == -17
+// opcode: div ; op1:x11; op2:x7; dest:x3; op1val:-0x11;  op2val:-0x80001
+TEST_RR_OP(div, x3, x11, x7, 0x0, -0x11, -0x80001, x4, 20, x9)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_14:
+// rs1==x2, rs2==x10, rd==x4, rs2_val == -262145, 
+// opcode: div ; op1:x2; op2:x10; dest:x4; op1val:-0xb503;  op2val:-0x40001
+TEST_RR_OP(div, x4, x2, x10, 0x0, -0xb503, -0x40001, x1, 0, x3)
+
+inst_15:
+// rs1==x5, rs2==x2, rd==x14, rs2_val == -131073, rs1_val == rs2_val
+// opcode: div ; op1:x5; op2:x2; dest:x14; op1val:-0x20001;  op2val:-0x20001
+TEST_RR_OP(div, x14, x5, x2, 0x1, -0x20001, -0x20001, x1, 4, x3)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x8;  op2val:-0x10001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x8, -0x10001, x1, 8, x3)
+
+inst_17:
+// rs2_val == -32769, rs1_val == 16777216
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:-0x8001
+TEST_RR_OP(div, x12, x10, x11, -0x1ff, 0x1000000, -0x8001, x1, 12, x3)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:-0x4001
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x7, -0x4001, x1, 16, x3)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -3
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x2001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x3, -0x2001, x1, 20, x3)
+
+inst_20:
+// rs2_val == -4097, rs1_val == 512
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x1001
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x200, -0x1001, x1, 24, x3)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x801
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, -0x801, x1, 28, x3)
+
+inst_22:
+// rs2_val == -1025, rs1_val == -513
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:-0x401
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x201, -0x401, x1, 32, x3)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x201
+TEST_RR_OP(div, x12, x10, x11, 0x1ff0, -0x400001, -0x201, x1, 36, x3)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x101
+TEST_RR_OP(div, x12, x10, x11, -0x330033, 0x33333333, -0x101, x1, 40, x3)
+
+inst_25:
+// rs2_val == -129, rs1_val == -8193
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x81
+TEST_RR_OP(div, x12, x10, x11, 0x3f, -0x2001, -0x81, x1, 44, x3)
+
+inst_26:
+// rs2_val == -65, rs1_val == 1073741824
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x41
+TEST_RR_OP(div, x12, x10, x11, -0xfc0fc0, 0x40000000, -0x41, x1, 48, x3)
+
+inst_27:
+// rs2_val == -33, rs1_val == -536870913
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:-0x21
+TEST_RR_OP(div, x12, x10, x11, 0xf83e0f, -0x20000001, -0x21, x1, 52, x3)
+
+inst_28:
+// rs2_val == -17, rs1_val == 4194304
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:-0x11
+TEST_RR_OP(div, x12, x10, x11, -0x3c3c3, 0x400000, -0x11, x1, 56, x3)
+
+inst_29:
+// rs2_val == -9, rs1_val == -33554433
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:-0x9
+TEST_RR_OP(div, x12, x10, x11, 0x38e38e, -0x2000001, -0x9, x1, 60, x3)
+
+inst_30:
+// rs2_val == -5, rs1_val == -524289
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x5
+TEST_RR_OP(div, x12, x10, x11, 0x19999, -0x80001, -0x5, x1, 64, x3)
+
+inst_31:
+// rs2_val == -3, rs1_val == -2097153
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x3
+TEST_RR_OP(div, x12, x10, x11, 0xaaaab, -0x200001, -0x3, x1, 68, x3)
+
+inst_32:
+// rs2_val == -2, rs1_val == 134217728
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:-0x2
+TEST_RR_OP(div, x12, x10, x11, -0x4000000, 0x8000000, -0x2, x1, 72, x3)
+
+inst_33:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x2000001
+TEST_RR_OP(div, x12, x10, x11, -0x3f, 0x7fffffff, -0x2000001, x1, 76, x3)
+
+inst_34:
+// rs1_val == -1073741825, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:-0x8001
+TEST_RR_OP(div, x12, x10, x11, 0x7fff, -0x40000001, -0x8001, x1, 80, x3)
+
+inst_35:
+// rs1_val == -268435457, rs2_val == 2048
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0x800
+TEST_RR_OP(div, x12, x10, x11, -0x20000, -0x10000001, 0x800, x1, 84, x3)
+
+inst_36:
+// rs1_val == -134217729, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x3
+TEST_RR_OP(div, x12, x10, x11, 0x2aaaaab, -0x8000001, -0x3, x1, 88, x3)
+
+inst_37:
+// rs1_val == -67108865, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:-0x4000001
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0x4000001, -0x4000001, x1, 92, x3)
+
+inst_38:
+// rs1_val == -16777217, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:-0x40001
+TEST_RR_OP(div, x12, x10, x11, 0x3f, -0x1000001, -0x40001, x1, 96, x3)
+
+inst_39:
+// rs1_val == -8388609, rs2_val == 256
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:0x100
+TEST_RR_OP(div, x12, x10, x11, -0x8000, -0x800001, 0x100, x1, 100, x3)
+
+inst_40:
+// rs1_val == -1048577, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x100001, 0x66666665, x1, 104, x3)
+
+inst_41:
+// rs1_val == -262145, rs2_val == 524288
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x80000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x40001, 0x80000, x1, 108, x3)
+
+inst_42:
+// rs1_val == -65537, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x100001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x10001, -0x100001, x1, 112, x3)
+
+inst_43:
+// rs1_val == -16385, rs2_val == 2097152
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x200000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x4001, 0x200000, x1, 116, x3)
+
+inst_44:
+// rs1_val == -4097, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:-0x201
+TEST_RR_OP(div, x12, x10, x11, 0x7, -0x1001, -0x201, x1, 120, x3)
+
+inst_45:
+// rs1_val == -2049, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0x9
+TEST_RR_OP(div, x12, x10, x11, 0xe3, -0x801, -0x9, x1, 124, x3)
+
+inst_46:
+// rs1_val == -1025, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:-0x7
+TEST_RR_OP(div, x12, x10, x11, 0x92, -0x401, -0x7, x1, 128, x3)
+
+inst_47:
+// rs1_val == -257, rs2_val == 4194304
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x400000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x101, 0x400000, x1, 132, x3)
+
+inst_48:
+// rs1_val == -129, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:-0x1
+TEST_RR_OP(div, x12, x10, x11, 0x81, -0x81, -0x1, x1, 136, x3)
+
+inst_49:
+// rs1_val == -65, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x40001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x41, -0x40001, x1, 140, x3)
+
+inst_50:
+// rs1_val == -33, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x40001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x21, -0x40001, x1, 144, x3)
+
+inst_51:
+// rs1_val == -9, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x9, 0x66666665, x1, 148, x3)
+
+inst_52:
+// rs1_val == -5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:-0x400001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x5, -0x400001, x1, 152, x3)
+
+inst_53:
+// rs1_val == -2, rs2_val == 64
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x40
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x2, 0x40, x1, 156, x3)
+
+inst_54:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x80000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x3, -0x80000000, x1, 160, x3)
+
+inst_55:
+// rs2_val == 1073741824, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x40000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x2001, 0x40000000, x1, 164, x3)
+
+inst_56:
+// rs2_val == 536870912, rs1_val == 1048576
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x20000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x100000, 0x20000000, x1, 168, x3)
+
+inst_57:
+// rs2_val == 268435456, rs1_val == 2
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x10000000, x1, 172, x3)
+
+inst_58:
+// rs2_val == 134217728, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x8000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x4000001, 0x8000000, x1, 176, x3)
+
+inst_59:
+// rs2_val == 67108864, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x4000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x21, 0x4000000, x1, 180, x3)
+
+inst_60:
+// rs2_val == 33554432, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x2000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x101, 0x2000000, x1, 184, x3)
+
+inst_61:
+// rs2_val == 16777216, rs1_val == 256
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x1000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x100, 0x1000000, x1, 188, x3)
+
+inst_62:
+// rs2_val == 8388608, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x800000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x400000, 0x800000, x1, 192, x3)
+
+inst_63:
+// rs2_val == 1048576, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x100000
+TEST_RR_OP(div, x12, x10, x11, 0x333, 0x33333334, 0x100000, x1, 196, x3)
+
+inst_64:
+// rs2_val == 262144, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x40000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x40000, x1, 200, x3)
+
+inst_65:
+// rs2_val == 131072, rs1_val == 0
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x20000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x20000, x1, 204, x3)
+
+inst_66:
+// rs2_val == 65536, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x10000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x1000, 0x10000, x1, 208, x3)
+
+inst_67:
+// rs2_val == 32768, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x8000
+TEST_RR_OP(div, x12, x10, x11, 0xaaaa, 0x55555555, 0x8000, x1, 212, x3)
+
+inst_68:
+// rs2_val == 16384, rs1_val == 1
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x4000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x1, 0x4000, x1, 216, x3)
+
+inst_69:
+// rs2_val == 8192, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x2000, x1, 220, x3)
+
+inst_70:
+// rs2_val == 4096, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1000
+TEST_RR_OP(div, x12, x10, x11, 0x33333, 0x33333334, 0x1000, x1, 224, x3)
+
+inst_71:
+// rs2_val == 1024, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0x400
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x41, 0x400, x1, 228, x3)
+
+inst_72:
+// rs2_val == 512, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x200
+TEST_RR_OP(div, x12, x10, x11, 0x8, 0x1000, 0x200, x1, 232, x3)
+
+inst_73:
+// rs2_val == 32, rs1_val == 128
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x20
+TEST_RR_OP(div, x12, x10, x11, 0x4, 0x80, 0x20, x1, 236, x3)
+
+inst_74:
+// rs2_val == 16, rs1_val == 32
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x10
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x20, 0x10, x1, 240, x3)
+
+inst_75:
+// rs2_val == 8, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x8
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x8, x1, 244, x3)
+
+inst_76:
+// rs2_val == 4, rs1_val == 536870912
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x8000000, 0x20000000, 0x4, x1, 248, x3)
+
+inst_77:
+// rs2_val == 2, rs1_val==5 and rs2_val==2
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x5, 0x2, x1, 252, x3)
+
+inst_78:
+// rs2_val == 1, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x1
+TEST_RR_OP(div, x12, x10, x11, 0x40000000, 0x40000000, 0x1, x1, 256, x3)
+
+inst_79:
+// rs1_val == -2147483648, rs2_val == 0, rs1_val == (-2**(xlen-1))
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, -0x80000000, 0x0, x1, 260, x3)
+
+inst_80:
+// rs1_val == 268435456, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x10000000, 0x66666667, x1, 264, x3)
+
+inst_81:
+// rs1_val == 67108864, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x40000
+TEST_RR_OP(div, x12, x10, x11, 0x100, 0x4000000, 0x40000, x1, 268, x3)
+
+inst_82:
+// rs1_val == 33554432, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2000000, 0x55555556, x1, 272, x3)
+
+inst_83:
+// rs1_val == 8388608, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:-0x801
+TEST_RR_OP(div, x12, x10, x11, -0xffe, 0x800000, -0x801, x1, 276, x3)
+
+inst_84:
+// rs1_val == 2097152, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x80000000
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x200000, -0x80000000, x1, 280, x3)
+
+inst_85:
+// rs1_val == 524288, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:-0x401
+TEST_RR_OP(div, x12, x10, x11, -0x1ff, 0x80000, -0x401, x1, 284, x3)
+
+inst_86:
+// rs1_val == 262144, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x40000, 0x33333333, x1, 288, x3)
+
+inst_87:
+// rs1_val == 131072, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x800
+TEST_RR_OP(div, x12, x10, x11, 0x40, 0x20000, 0x800, x1, 292, x3)
+
+inst_88:
+// rs1_val == 65536, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x2aaa, 0x10000, 0x6, x1, 296, x3)
+
+inst_89:
+// rs1_val == 32768, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:-0x40001
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x8000, -0x40001, x1, 300, x3)
+
+inst_90:
+// rs1_val == 8192, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x201
+TEST_RR_OP(div, x12, x10, x11, -0xf, 0x2000, -0x201, x1, 304, x3)
+
+inst_91:
+// rs1_val == 2048, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x800, 0x33333333, x1, 308, x3)
+
+inst_92:
+// rs1_val == 1024, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:-0x20001
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x400, -0x20001, x1, 312, x3)
+
+inst_93:
+// rs1_val == 64, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x20, 0x40, 0x2, x1, 316, x3)
+
+inst_94:
+// rs1_val == 8, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x8, 0x66666667, x1, 320, x3)
+
+inst_95:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb505, 0xb505, x1, 324, x3)
+
+inst_96:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0xb505, -0xb503, x1, 328, x3)
+
+inst_97:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x66666667, x1, 332, x3)
+
+inst_98:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x33333334, x1, 336, x3)
+
+inst_99:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x1e2b, 0xb505, 0x6, x1, 340, x3)
+
+inst_100:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, -0x55555555, x1, 344, x3)
+
+inst_101:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x55555556, x1, 348, x3)
+
+inst_102:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x2d41, 0xb505, 0x4, x1, 352, x3)
+
+inst_103:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb505, 0xb503, x1, 356, x3)
+
+inst_104:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0xb505, 0x0, x1, 360, x3)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x66666665, x1, 364, x3)
+
+inst_106:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x33333332, x1, 368, x3)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x55555554, x1, 372, x3)
+
+inst_108:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x5a82, 0xb505, 0x2, x1, 376, x3)
+
+inst_109:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb505, 0xb504, x1, 380, x3)
+
+inst_110:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0xb505, -0xb504, x1, 384, x3)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x66666666, x1, 388, x3)
+
+inst_112:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x33333333, x1, 392, x3)
+
+inst_113:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x2434, 0xb505, 0x5, x1, 396, x3)
+
+inst_114:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, -0x55555556, x1, 400, x3)
+
+inst_115:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb505, 0x55555555, x1, 404, x3)
+
+inst_116:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x3c57, 0xb505, 0x3, x1, 408, x3)
+
+inst_117:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0xb505, x1, 412, x3)
+
+inst_118:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0xb503, -0xb503, x1, 416, x3)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x66666667, x1, 420, x3)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x33333334, x1, 424, x3)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, -0x1e2b, -0xb503, 0x6, x1, 428, x3)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, -0x55555555, x1, 432, x3)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x55555556, x1, 436, x3)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, -0x2d40, -0xb503, 0x4, x1, 440, x3)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0xb503, 0xb503, x1, 444, x3)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, -0xb503, 0x0, x1, 448, x3)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x66666665, x1, 452, x3)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x33333332, x1, 456, x3)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x55555554, x1, 460, x3)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, -0x5a81, -0xb503, 0x2, x1, 464, x3)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0xb504, x1, 468, x3)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, -0xb504, x1, 472, x3)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x66666666, x1, 476, x3)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x33333333, x1, 480, x3)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, -0x2433, -0xb503, 0x5, x1, 484, x3)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, -0x55555556, x1, 488, x3)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb503, 0x55555555, x1, 492, x3)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, -0x3c56, -0xb503, 0x3, x1, 496, x3)
+
+inst_139:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x90d0, 0x66666667, 0xb505, x1, 500, x3)
+
+inst_140:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x90d2, 0x66666667, -0xb503, x1, 504, x3)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x66666667, x1, 508, x3)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x33333334, x1, 512, x3)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x66666667, 0x6, x1, 516, x3)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666667, -0x55555555, x1, 520, x3)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x55555556, x1, 524, x3)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x19999999, 0x66666667, 0x4, x1, 528, x3)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x90d2, 0x66666667, 0xb503, x1, 532, x3)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x66666667, 0x0, x1, 536, x3)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x66666665, x1, 540, x3)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x66666667, 0x33333332, x1, 544, x3)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x55555554, x1, 548, x3)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x33333333, 0x66666667, 0x2, x1, 552, x3)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x90d1, 0x66666667, 0xb504, x1, 556, x3)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x90d1, 0x66666667, -0xb504, x1, 560, x3)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 564, x3)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x66666667, 0x33333333, x1, 568, x3)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x147ae147, 0x66666667, 0x5, x1, 572, x3)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666667, -0x55555556, x1, 576, x3)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666667, 0x55555555, x1, 580, x3)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x22222222, 0x66666667, 0x3, x1, 584, x3)
+
+inst_161:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333334, 0xb505, x1, 588, x3)
+
+inst_162:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x4869, 0x33333334, -0xb503, x1, 592, x3)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x66666667, x1, 596, x3)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333334, 0x33333334, x1, 600, x3)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x8888888, 0x33333334, 0x6, x1, 604, x3)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, -0x55555555, x1, 608, x3)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x55555556, x1, 612, x3)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0xccccccd, 0x33333334, 0x4, x1, 616, x3)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x4869, 0x33333334, 0xb503, x1, 620, x3)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x33333334, 0x0, x1, 624, x3)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x66666665, x1, 628, x3)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333334, 0x33333332, x1, 632, x3)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x55555554, x1, 636, x3)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x1999999a, 0x33333334, 0x2, x1, 640, x3)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333334, 0xb504, x1, 644, x3)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x4868, 0x33333334, -0xb504, x1, 648, x3)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x66666666, x1, 652, x3)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333334, 0x33333333, x1, 656, x3)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0xa3d70a4, 0x33333334, 0x5, x1, 660, x3)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, -0x55555556, x1, 664, x3)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333334, 0x55555555, x1, 668, x3)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x33333334, 0x3, x1, 672, x3)
+
+inst_183:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0xb505, x1, 676, x3)
+
+inst_184:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, -0xb503, x1, 680, x3)
+
+inst_185:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x66666667, x1, 684, x3)
+
+inst_186:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x33333334, x1, 688, x3)
+
+inst_187:
+// rs1_val==6 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x6, 0x6, x1, 692, x3)
+
+inst_188:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, -0x55555555, x1, 696, x3)
+
+inst_189:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x55555556, x1, 700, x3)
+
+inst_190:
+// rs1_val==6 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x6, 0x4, x1, 704, x3)
+
+inst_191:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0xb503, x1, 708, x3)
+
+inst_192:
+// rs1_val==6 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x6, 0x0, x1, 712, x3)
+
+inst_193:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x66666665, x1, 716, x3)
+
+inst_194:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x33333332, x1, 720, x3)
+
+inst_195:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x55555554, x1, 724, x3)
+
+inst_196:
+// rs1_val==6 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x3, 0x6, 0x2, x1, 728, x3)
+
+inst_197:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0xb504, x1, 732, x3)
+
+inst_198:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, -0xb504, x1, 736, x3)
+
+inst_199:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x66666666, x1, 740, x3)
+
+inst_200:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x33333333, x1, 744, x3)
+
+inst_201:
+// rs1_val==6 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x6, 0x5, x1, 748, x3)
+
+inst_202:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, -0x55555556, x1, 752, x3)
+
+inst_203:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x6, 0x55555555, x1, 756, x3)
+
+inst_204:
+// rs1_val==6 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x6, 0x3, x1, 760, x3)
+
+inst_205:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, -0x78ad, -0x55555555, 0xb505, x1, 764, x3)
+
+inst_206:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x78af, -0x55555555, -0xb503, x1, 768, x3)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555555, 0x66666667, x1, 772, x3)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555555, 0x33333334, x1, 776, x3)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, -0xe38e38e, -0x55555555, 0x6, x1, 780, x3)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0x55555555, -0x55555555, x1, 784, x3)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555555, 0x55555556, x1, 788, x3)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, -0x15555555, -0x55555555, 0x4, x1, 792, x3)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x78af, -0x55555555, 0xb503, x1, 796, x3)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, -0x55555555, 0x0, x1, 800, x3)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555555, 0x66666665, x1, 804, x3)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555555, 0x33333332, x1, 808, x3)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555555, 0x55555554, x1, 812, x3)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, -0x2aaaaaaa, -0x55555555, 0x2, x1, 816, x3)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x78ae, -0x55555555, 0xb504, x1, 820, x3)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x78ae, -0x55555555, -0xb504, x1, 824, x3)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555555, 0x66666666, x1, 828, x3)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555555, 0x33333333, x1, 832, x3)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, -0x11111111, -0x55555555, 0x5, x1, 836, x3)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555555, -0x55555556, x1, 840, x3)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555555, 0x55555555, x1, 844, x3)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, -0x1c71c71c, -0x55555555, 0x3, x1, 848, x3)
+
+inst_227:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x78ad, 0x55555556, 0xb505, x1, 852, x3)
+
+inst_228:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x78af, 0x55555556, -0xb503, x1, 856, x3)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555556, 0x66666667, x1, 860, x3)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x33333334, x1, 864, x3)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0xe38e38e, 0x55555556, 0x6, x1, 868, x3)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x55555556, -0x55555555, x1, 872, x3)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x55555556, x1, 876, x3)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x15555555, 0x55555556, 0x4, x1, 880, x3)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x78af, 0x55555556, 0xb503, x1, 884, x3)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x55555556, 0x0, x1, 888, x3)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555556, 0x66666665, x1, 892, x3)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x33333332, x1, 896, x3)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x55555554, x1, 900, x3)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x2aaaaaab, 0x55555556, 0x2, x1, 904, x3)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x78ae, 0x55555556, 0xb504, x1, 908, x3)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x78ae, 0x55555556, -0xb504, x1, 912, x3)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555556, 0x66666666, x1, 916, x3)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x33333333, x1, 920, x3)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x55555556, 0x5, x1, 924, x3)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x55555556, -0x55555556, x1, 928, x3)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555556, 0x55555555, x1, 932, x3)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x3, x1, 936, x3)
+
+inst_249:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0xb505, x1, 940, x3)
+
+inst_250:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, -0xb503, x1, 944, x3)
+
+inst_251:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x66666667, x1, 948, x3)
+
+inst_252:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x33333334, x1, 952, x3)
+
+inst_253:
+// rs1_val==4 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x6, x1, 956, x3)
+
+inst_254:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, -0x55555555, x1, 960, x3)
+
+inst_255:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x55555556, x1, 964, x3)
+
+inst_256:
+// rs1_val==4 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x4, 0x4, x1, 968, x3)
+
+inst_257:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0xb503, x1, 972, x3)
+
+inst_258:
+// rs1_val==4 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x4, 0x0, x1, 976, x3)
+
+inst_259:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x66666665, x1, 980, x3)
+
+inst_260:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x33333332, x1, 984, x3)
+
+inst_261:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x55555554, x1, 988, x3)
+
+inst_262:
+// rs1_val==4 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x4, 0x2, x1, 992, x3)
+
+inst_263:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0xb504, x1, 996, x3)
+
+inst_264:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, -0xb504, x1, 1000, x3)
+
+inst_265:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x66666666, x1, 1004, x3)
+
+inst_266:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x33333333, x1, 1008, x3)
+
+inst_267:
+// rs1_val==4 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x5, x1, 1012, x3)
+
+inst_268:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, -0x55555556, x1, 1016, x3)
+
+inst_269:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4, 0x55555555, x1, 1020, x3)
+
+inst_270:
+// rs1_val==4 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x4, 0x3, x1, 1024, x3)
+
+inst_271:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0xb505, x1, 1028, x3)
+
+inst_272:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0xb503, -0xb503, x1, 1032, x3)
+
+inst_273:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x66666667, x1, 1036, x3)
+
+inst_274:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x33333334, x1, 1040, x3)
+
+inst_275:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x1e2b, 0xb503, 0x6, x1, 1044, x3)
+
+inst_276:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, -0x55555555, x1, 1048, x3)
+
+inst_277:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x55555556, x1, 1052, x3)
+
+inst_278:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x2d40, 0xb503, 0x4, x1, 1056, x3)
+
+inst_279:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb503, 0xb503, x1, 1060, x3)
+
+inst_280:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0xb503, 0x0, x1, 1064, x3)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x66666665, x1, 1068, x3)
+
+inst_282:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x33333332, x1, 1072, x3)
+
+inst_283:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x55555554, x1, 1076, x3)
+
+inst_284:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x5a81, 0xb503, 0x2, x1, 1080, x3)
+
+inst_285:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0xb504, x1, 1084, x3)
+
+inst_286:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, -0xb504, x1, 1088, x3)
+
+inst_287:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x66666666, x1, 1092, x3)
+
+inst_288:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x33333333, x1, 1096, x3)
+
+inst_289:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x2433, 0xb503, 0x5, x1, 1100, x3)
+
+inst_290:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, -0x55555556, x1, 1104, x3)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb503, 0x55555555, x1, 1108, x3)
+
+inst_292:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x3c56, 0xb503, 0x3, x1, 1112, x3)
+
+inst_293:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1116, x3)
+
+inst_294:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, -0xb503, x1, 1120, x3)
+
+inst_295:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1124, x3)
+
+inst_296:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1128, x3)
+
+inst_297:
+// rs1_val==0 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1132, x3)
+
+inst_298:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, -0x55555555, x1, 1136, x3)
+
+inst_299:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1140, x3)
+
+inst_300:
+// rs1_val==0 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1144, x3)
+
+inst_301:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1148, x3)
+
+inst_302:
+// rs1_val==0 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x0, 0x0, x1, 1152, x3)
+
+inst_303:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1156, x3)
+
+inst_304:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1160, x3)
+
+inst_305:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1164, x3)
+
+inst_306:
+// rs1_val==0 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x2, x1, 1168, x3)
+
+inst_307:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1172, x3)
+
+inst_308:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, -0xb504, x1, 1176, x3)
+
+inst_309:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1180, x3)
+
+inst_310:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1184, x3)
+
+inst_311:
+// rs1_val==0 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1188, x3)
+
+inst_312:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, -0x55555556, x1, 1192, x3)
+
+inst_313:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1196, x3)
+
+inst_314:
+// rs1_val==0 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1200, x3)
+
+inst_315:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x90d0, 0x66666665, 0xb505, x1, 1204, x3)
+
+inst_316:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x90d2, 0x66666665, -0xb503, x1, 1208, x3)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x66666665, 0x66666667, x1, 1212, x3)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x33333334, x1, 1216, x3)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x11111110, 0x66666665, 0x6, x1, 1220, x3)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666665, -0x55555555, x1, 1224, x3)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x55555556, x1, 1228, x3)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x19999999, 0x66666665, 0x4, x1, 1232, x3)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x90d2, 0x66666665, 0xb503, x1, 1236, x3)
+
+inst_324:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x33333333, 0x0, x1, 1240, x3)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x66666665, x1, 1244, x3)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 1248, x3)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x55555554, x1, 1252, x3)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x19999999, 0x33333333, 0x2, x1, 1256, x3)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333333, 0xb504, x1, 1260, x3)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x4868, 0x33333333, -0xb504, x1, 1264, x3)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x66666666, x1, 1268, x3)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333333, 0x33333333, x1, 1272, x3)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x5, x1, 1276, x3)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, -0x55555556, x1, 1280, x3)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x55555555, x1, 1284, x3)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x33333333, 0x3, x1, 1288, x3)
+
+inst_337:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0xb505, x1, 1292, x3)
+
+inst_338:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, -0xb503, x1, 1296, x3)
+
+inst_339:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x66666667, x1, 1300, x3)
+
+inst_340:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x33333334, x1, 1304, x3)
+
+inst_341:
+// rs1_val==5 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x6, x1, 1308, x3)
+
+inst_342:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, -0x55555555, x1, 1312, x3)
+
+inst_343:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x55555556, x1, 1316, x3)
+
+inst_344:
+// rs1_val==5 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x5, 0x4, x1, 1320, x3)
+
+inst_345:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0xb503, x1, 1324, x3)
+
+inst_346:
+// rs1_val==5 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x5, 0x0, x1, 1328, x3)
+
+inst_347:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x66666665, x1, 1332, x3)
+
+inst_348:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x33333332, x1, 1336, x3)
+
+inst_349:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x55555554, x1, 1340, x3)
+
+inst_350:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0xb504, x1, 1344, x3)
+
+inst_351:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, -0xb504, x1, 1348, x3)
+
+inst_352:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x66666666, x1, 1352, x3)
+
+inst_353:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x33333333, x1, 1356, x3)
+
+inst_354:
+// rs1_val==5 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x5, 0x5, x1, 1360, x3)
+
+inst_355:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, -0x55555556, x1, 1364, x3)
+
+inst_356:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x5, 0x55555555, x1, 1368, x3)
+
+inst_357:
+// rs1_val==5 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x5, 0x3, x1, 1372, x3)
+
+inst_358:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, -0x78ad, -0x55555556, 0xb505, x1, 1376, x3)
+
+inst_359:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x78af, -0x55555556, -0xb503, x1, 1380, x3)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555556, 0x66666667, x1, 1384, x3)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x33333334, x1, 1388, x3)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, -0xe38e38e, -0x55555556, 0x6, x1, 1392, x3)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0x55555556, -0x55555555, x1, 1396, x3)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x55555556, x1, 1400, x3)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, -0x15555555, -0x55555556, 0x4, x1, 1404, x3)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x78af, -0x55555556, 0xb503, x1, 1408, x3)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, -0x55555556, 0x0, x1, 1412, x3)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555556, 0x66666665, x1, 1416, x3)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x33333332, x1, 1420, x3)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x55555554, x1, 1424, x3)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, -0x2aaaaaab, -0x55555556, 0x2, x1, 1428, x3)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x78ae, -0x55555556, 0xb504, x1, 1432, x3)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x78ae, -0x55555556, -0xb504, x1, 1436, x3)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x55555556, 0x66666666, x1, 1440, x3)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x33333333, x1, 1444, x3)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, -0x11111111, -0x55555556, 0x5, x1, 1448, x3)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0x55555556, -0x55555556, x1, 1452, x3)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0x55555556, 0x55555555, x1, 1456, x3)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, -0x1c71c71c, -0x55555556, 0x3, x1, 1460, x3)
+
+inst_380:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x78ad, 0x55555555, 0xb505, x1, 1464, x3)
+
+inst_381:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x78af, 0x55555555, -0xb503, x1, 1468, x3)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555555, 0x66666667, x1, 1472, x3)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555555, 0x33333334, x1, 1476, x3)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0xe38e38e, 0x55555555, 0x6, x1, 1480, x3)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x55555555, -0x55555555, x1, 1484, x3)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555555, 0x55555556, x1, 1488, x3)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x15555555, 0x55555555, 0x4, x1, 1492, x3)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x78af, 0x55555555, 0xb503, x1, 1496, x3)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x55555555, 0x0, x1, 1500, x3)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555555, 0x66666665, x1, 1504, x3)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555555, 0x33333332, x1, 1508, x3)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 1512, x3)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x2aaaaaaa, 0x55555555, 0x2, x1, 1516, x3)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x78ae, 0x55555555, 0xb504, x1, 1520, x3)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x78ae, 0x55555555, -0xb504, x1, 1524, x3)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555555, 0x66666666, x1, 1528, x3)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555555, 0x33333333, x1, 1532, x3)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x55555555, 0x5, x1, 1536, x3)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555555, -0x55555556, x1, 1540, x3)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555555, 0x55555555, x1, 1544, x3)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x3, x1, 1548, x3)
+
+inst_402:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0xb505, x1, 1552, x3)
+
+inst_403:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, -0xb503, x1, 1556, x3)
+
+inst_404:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x66666667, x1, 1560, x3)
+
+inst_405:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x33333334, x1, 1564, x3)
+
+inst_406:
+// rs1_val==3 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x6, x1, 1568, x3)
+
+inst_407:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, -0x55555555, x1, 1572, x3)
+
+inst_408:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x55555556, x1, 1576, x3)
+
+inst_409:
+// rs1_val==3 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x4, x1, 1580, x3)
+
+inst_410:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0xb503, x1, 1584, x3)
+
+inst_411:
+// rs1_val==3 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x3, 0x0, x1, 1588, x3)
+
+inst_412:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x66666665, x1, 1592, x3)
+
+inst_413:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x33333332, x1, 1596, x3)
+
+inst_414:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x55555554, x1, 1600, x3)
+
+inst_415:
+// rs1_val==3 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x3, 0x2, x1, 1604, x3)
+
+inst_416:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0xb504, x1, 1608, x3)
+
+inst_417:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, -0xb504, x1, 1612, x3)
+
+inst_418:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x66666666, x1, 1616, x3)
+
+inst_419:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x33333333, x1, 1620, x3)
+
+inst_420:
+// rs1_val==3 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x5, x1, 1624, x3)
+
+inst_421:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, -0x55555556, x1, 1628, x3)
+
+inst_422:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x3, 0x55555555, x1, 1632, x3)
+
+inst_423:
+// rs1_val==3 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x3, 0x3, x1, 1636, x3)
+
+inst_424:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x66666665, 0x0, x1, 1640, x3)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x66666665, x1, 1644, x3)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x66666665, 0x33333332, x1, 1648, x3)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x55555554, x1, 1652, x3)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x33333332, 0x66666665, 0x2, x1, 1656, x3)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x90d1, 0x66666665, 0xb504, x1, 1660, x3)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x90d1, 0x66666665, -0xb504, x1, 1664, x3)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x66666665, 0x66666666, x1, 1668, x3)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x33333333, x1, 1672, x3)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x147ae147, 0x66666665, 0x5, x1, 1676, x3)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666665, -0x55555556, x1, 1680, x3)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666665, 0x55555555, x1, 1684, x3)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x22222221, 0x66666665, 0x3, x1, 1688, x3)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333332, 0xb505, x1, 1692, x3)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x4869, 0x33333332, -0xb503, x1, 1696, x3)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x66666667, x1, 1700, x3)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x33333334, x1, 1704, x3)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x8888888, 0x33333332, 0x6, x1, 1708, x3)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, -0x55555555, x1, 1712, x3)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x55555556, x1, 1716, x3)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0xccccccc, 0x33333332, 0x4, x1, 1720, x3)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x4869, 0x33333332, 0xb503, x1, 1724, x3)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x33333332, 0x0, x1, 1728, x3)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x66666665, x1, 1732, x3)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x33333332, 0x33333332, x1, 1736, x3)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x55555554, x1, 1740, x3)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x19999999, 0x33333332, 0x2, x1, 1744, x3)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333332, 0xb504, x1, 1748, x3)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x4868, 0x33333332, -0xb504, x1, 1752, x3)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x66666666, x1, 1756, x3)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x33333333, x1, 1760, x3)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x5, x1, 1764, x3)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, -0x55555556, x1, 1768, x3)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333332, 0x55555555, x1, 1772, x3)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x11111110, 0x33333332, 0x3, x1, 1776, x3)
+
+inst_459:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x78ad, 0x55555554, 0xb505, x1, 1780, x3)
+
+inst_460:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x78af, 0x55555554, -0xb503, x1, 1784, x3)
+
+inst_461:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, 0x66666667, x1, 1788, x3)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555554, 0x33333334, x1, 1792, x3)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0xe38e38e, 0x55555554, 0x6, x1, 1796, x3)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, -0x55555555, x1, 1800, x3)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, 0x55555556, x1, 1804, x3)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x15555555, 0x55555554, 0x4, x1, 1808, x3)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x78af, 0x55555554, 0xb503, x1, 1812, x3)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x55555554, 0x0, x1, 1816, x3)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, 0x66666665, x1, 1820, x3)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555554, 0x33333332, x1, 1824, x3)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555554, 0x55555554, x1, 1828, x3)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x2aaaaaaa, 0x55555554, 0x2, x1, 1832, x3)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x78ae, 0x55555554, 0xb504, x1, 1836, x3)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x78ae, 0x55555554, -0xb504, x1, 1840, x3)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, 0x66666666, x1, 1844, x3)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x55555554, 0x33333333, x1, 1848, x3)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x11111110, 0x55555554, 0x5, x1, 1852, x3)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, -0x55555556, x1, 1856, x3)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x55555554, 0x55555555, x1, 1860, x3)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x1c71c71c, 0x55555554, 0x3, x1, 1864, x3)
+
+inst_481:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0xb505, x1, 1868, x3)
+
+inst_482:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, -0xb503, x1, 1872, x3)
+
+inst_483:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x66666667, x1, 1876, x3)
+
+inst_484:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x33333334, x1, 1880, x3)
+
+inst_485:
+// rs1_val==2 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x6, x1, 1884, x3)
+
+inst_486:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, -0x55555555, x1, 1888, x3)
+
+inst_487:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x55555556, x1, 1892, x3)
+
+inst_488:
+// rs1_val==2 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x4, x1, 1896, x3)
+
+inst_489:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0xb503, x1, 1900, x3)
+
+inst_490:
+// rs1_val==2 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x2, 0x0, x1, 1904, x3)
+
+inst_491:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x66666665, x1, 1908, x3)
+
+inst_492:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x33333332, x1, 1912, x3)
+
+inst_493:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x55555554, x1, 1916, x3)
+
+inst_494:
+// rs1_val==2 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x2, 0x2, x1, 1920, x3)
+
+inst_495:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0xb504, x1, 1924, x3)
+
+inst_496:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, -0xb504, x1, 1928, x3)
+
+inst_497:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x66666666, x1, 1932, x3)
+
+inst_498:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x33333333, x1, 1936, x3)
+
+inst_499:
+// rs1_val==2 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x5, x1, 1940, x3)
+
+inst_500:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, -0x55555556, x1, 1944, x3)
+
+inst_501:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x55555555, x1, 1948, x3)
+
+inst_502:
+// rs1_val==2 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x2, 0x3, x1, 1952, x3)
+
+inst_503:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0xb505, x1, 1956, x3)
+
+inst_504:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0xb504, -0xb503, x1, 1960, x3)
+
+inst_505:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x66666667, x1, 1964, x3)
+
+inst_506:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x33333334, x1, 1968, x3)
+
+inst_507:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x1e2b, 0xb504, 0x6, x1, 1972, x3)
+
+inst_508:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, -0x55555555, x1, 1976, x3)
+
+inst_509:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x55555556, x1, 1980, x3)
+
+inst_510:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x2d41, 0xb504, 0x4, x1, 1984, x3)
+
+inst_511:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb504, 0xb503, x1, 1988, x3)
+
+inst_512:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0xb504, 0x0, x1, 1992, x3)
+
+inst_513:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x66666665, x1, 1996, x3)
+
+inst_514:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x33333332, x1, 2000, x3)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x55555554, x1, 2004, x3)
+
+inst_516:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x5a82, 0xb504, 0x2, x1, 2008, x3)
+
+inst_517:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0xb504, 0xb504, x1, 2012, x3)
+
+inst_518:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0xb504, -0xb504, x1, 2016, x3)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x66666666, x1, 2020, x3)
+
+inst_520:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x33333333, x1, 2024, x3)
+
+inst_521:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x2434, 0xb504, 0x5, x1, 2028, x3)
+
+inst_522:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, -0x55555556, x1, 2032, x3)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0xb504, 0x55555555, x1, 2036, x3)
+
+inst_524:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x3c56, 0xb504, 0x3, x1, 2040, x3)
+
+inst_525:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0xb505, x1, 2044, x3)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_526:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0xb504, -0xb503, x1, 0, x3)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x66666667, x1, 4, x3)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x33333334, x1, 8, x3)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, -0x1e2b, -0xb504, 0x6, x1, 12, x3)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, -0x55555555, x1, 16, x3)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x55555556, x1, 20, x3)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, -0x2d41, -0xb504, 0x4, x1, 24, x3)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0xb504, 0xb503, x1, 28, x3)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, -0xb504, 0x0, x1, 32, x3)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x66666665, x1, 36, x3)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x33333332, x1, 40, x3)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x55555554, x1, 44, x3)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, -0x5a82, -0xb504, 0x2, x1, 48, x3)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x1, -0xb504, 0xb504, x1, 52, x3)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x1, -0xb504, -0xb504, x1, 56, x3)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x66666666, x1, 60, x3)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x33333333, x1, 64, x3)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, -0x2434, -0xb504, 0x5, x1, 68, x3)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, -0x55555556, x1, 72, x3)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0xb504, 0x55555555, x1, 76, x3)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, -0x3c56, -0xb504, 0x3, x1, 80, x3)
+
+inst_547:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x90d0, 0x66666666, 0xb505, x1, 84, x3)
+
+inst_548:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x90d2, 0x66666666, -0xb503, x1, 88, x3)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x66666666, 0x66666667, x1, 92, x3)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x33333334, x1, 96, x3)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x11111111, 0x66666666, 0x6, x1, 100, x3)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666666, -0x55555555, x1, 104, x3)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x55555556, x1, 108, x3)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0x19999999, 0x66666666, 0x4, x1, 112, x3)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x90d2, 0x66666666, 0xb503, x1, 116, x3)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(div, x12, x10, x11, 0xFFFFFFFF, 0x66666666, 0x0, x1, 120, x3)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x66666665, x1, 124, x3)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x66666666, 0x33333332, x1, 128, x3)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x55555554, x1, 132, x3)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(div, x12, x10, x11, 0x33333333, 0x66666666, 0x2, x1, 136, x3)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(div, x12, x10, x11, 0x90d1, 0x66666666, 0xb504, x1, 140, x3)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(div, x12, x10, x11, -0x90d1, 0x66666666, -0xb504, x1, 144, x3)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x66666666, x1, 148, x3)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(div, x12, x10, x11, 0x2, 0x66666666, 0x33333333, x1, 152, x3)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(div, x12, x10, x11, 0x147ae147, 0x66666666, 0x5, x1, 156, x3)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(div, x12, x10, x11, -0x1, 0x66666666, -0x55555556, x1, 160, x3)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x1, 0x66666666, 0x55555555, x1, 164, x3)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(div, x12, x10, x11, 0x22222222, 0x66666666, 0x3, x1, 168, x3)
+
+inst_569:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(div, x12, x10, x11, 0x4868, 0x33333333, 0xb505, x1, 172, x3)
+
+inst_570:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(div, x12, x10, x11, -0x4869, 0x33333333, -0xb503, x1, 176, x3)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x66666667, x1, 180, x3)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x33333334, x1, 184, x3)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(div, x12, x10, x11, 0x8888888, 0x33333333, 0x6, x1, 188, x3)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, -0x55555555, x1, 192, x3)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x33333333, 0x55555556, x1, 196, x3)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(div, x12, x10, x11, 0xccccccc, 0x33333333, 0x4, x1, 200, x3)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(div, x12, x10, x11, 0x4869, 0x33333333, 0xb503, x1, 204, x3)
+
+inst_578:
+// rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x8;  op2val:-0x40000001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x8, -0x40000001, x1, 208, x3)
+
+inst_579:
+// rs2_val == -536870913, rs1_val == 16384, rs1_val > 0 and rs2_val < 0
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x20000001
+TEST_RR_OP(div, x12, x10, x11, 0x0, 0x4000, -0x20000001, x1, 212, x3)
+
+inst_580:
+// rs2_val == -268435457, rs1_val == -4194305
+// opcode: div ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x10000001
+TEST_RR_OP(div, x12, x10, x11, 0x0, -0x400001, -0x10000001, x1, 216, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 55*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/divu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/divu-01.S
new file mode 100644
index 000000000..1519ccfde
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/divu-01.S
@@ -0,0 +1,3730 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the divu instruction of the RISC-V M extension for the divu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",divu)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x2, rs2==x9, rd==x9, rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0, rs2_val == 4286578687, rs1_val > 0 and rs2_val > 0, rs1_val == 1431655765
+// opcode: divu ; op1:x2; op2:x9; dest:x9; op1val:0x55555555;  op2val:0xff7fffff
+TEST_RR_OP(divu, x9, x2, x9, 0x0, 0x55555555, 0xff7fffff, x1, 0, x3)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x14, rs2==x12, rd==x14, rs2_val == 2147483647, 
+// opcode: divu ; op1:x14; op2:x12; dest:x14; op1val:0x13;  op2val:0x7fffffff
+TEST_RR_OP(divu, x14, x14, x12, 0x0, 0x13, 0x7fffffff, x1, 4, x3)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x11, rs2==x11, rd==x11, rs2_val == 3221225471, rs1_val == 4294836223
+// opcode: divu ; op1:x11; op2:x11; dest:x11; op1val:0xfffdffff;  op2val:0xfffdffff
+TEST_RR_OP(divu, x11, x11, x11, 0x1, 0xfffdffff, 0xfffdffff, x1, 8, x3)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x15, rs2_val == 3758096383, rs1_val == 4294967263
+// opcode: divu ; op1:x4; op2:x4; dest:x15; op1val:0xffffffdf;  op2val:0xffffffdf
+TEST_RR_OP(divu, x15, x4, x4, 0x1, 0xffffffdf, 0xffffffdf, x1, 12, x3)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x9, rs2==x8, rd==x13, rs2_val == 4026531839, 
+// opcode: divu ; op1:x9; op2:x8; dest:x13; op1val:0xfffe;  op2val:0xefffffff
+TEST_RR_OP(divu, x13, x9, x8, 0x0, 0xfffe, 0xefffffff, x1, 16, x3)
+
+inst_5:
+// rs1==x12, rs2==x0, rd==x6, rs2_val == 4160749567, rs1_val == 1048576
+// opcode: divu ; op1:x12; op2:x0; dest:x6; op1val:0x100000;  op2val:0x0
+TEST_RR_OP(divu, x6, x12, x0, 0xFFFFFFFF, 0x100000, 0x0, x1, 20, x3)
+
+inst_6:
+// rs1==x7, rs2==x13, rd==x12, rs2_val == 4227858431, rs1_val == 32768
+// opcode: divu ; op1:x7; op2:x13; dest:x12; op1val:0x8000;  op2val:0xfbffffff
+TEST_RR_OP(divu, x12, x7, x13, 0x0, 0x8000, 0xfbffffff, x1, 24, x3)
+
+inst_7:
+// rs1==x10, rs2==x5, rd==x8, rs2_val == 4261412863, rs1_val == 8
+// opcode: divu ; op1:x10; op2:x5; dest:x8; op1val:0x8;  op2val:0xfdffffff
+TEST_RR_OP(divu, x8, x10, x5, 0x0, 0x8, 0xfdffffff, x1, 28, x6)
+RVTEST_SIGBASE( x9,signature_x9_0)
+
+inst_8:
+// rs1==x13, rs2==x7, rd==x3, rs2_val == 4278190079, 
+// opcode: divu ; op1:x13; op2:x7; dest:x3; op1val:0x12;  op2val:0xfeffffff
+TEST_RR_OP(divu, x3, x13, x7, 0x0, 0x12, 0xfeffffff, x9, 0, x6)
+
+inst_9:
+// rs1==x3, rs2==x14, rd==x2, rs2_val == 4290772991, rs1_val == 4294967167
+// opcode: divu ; op1:x3; op2:x14; dest:x2; op1val:0xffffff7f;  op2val:0xffbfffff
+TEST_RR_OP(divu, x2, x3, x14, 0x1, 0xffffff7f, 0xffbfffff, x9, 4, x6)
+
+inst_10:
+// rs1==x5, rs2==x10, rd==x0, rs2_val == 4292870143, rs1_val == 4294443007
+// opcode: divu ; op1:x5; op2:x10; dest:x0; op1val:0xfff7ffff;  op2val:0xffdfffff
+TEST_RR_OP(divu, x0, x5, x10, 0, 0xfff7ffff, 0xffdfffff, x9, 8, x6)
+
+inst_11:
+// rs1==x15, rs2==x3, rd==x1, rs2_val == 4293918719, 
+// opcode: divu ; op1:x15; op2:x3; dest:x1; op1val:0xfff7ffff;  op2val:0xffefffff
+TEST_RR_OP(divu, x1, x15, x3, 0x1, 0xfff7ffff, 0xffefffff, x9, 12, x6)
+
+inst_12:
+// rs1==x8, rs2==x1, rd==x10, rs2_val == 4294443007, rs1_val == 1
+// opcode: divu ; op1:x8; op2:x1; dest:x10; op1val:0x1;  op2val:0xfff7ffff
+TEST_RR_OP(divu, x10, x8, x1, 0x0, 0x1, 0xfff7ffff, x9, 16, x6)
+
+inst_13:
+// rs1==x1, rs2==x15, rd==x4, rs2_val == 4294705151, 
+// opcode: divu ; op1:x1; op2:x15; dest:x4; op1val:0x3;  op2val:0xfffbffff
+TEST_RR_OP(divu, x4, x1, x15, 0x0, 0x3, 0xfffbffff, x9, 20, x6)
+
+inst_14:
+// rs1==x0, rs2==x2, rd==x5, rs2_val == 4294836223, rs1_val == 4294967231
+// opcode: divu ; op1:x0; op2:x2; dest:x5; op1val:0x0;  op2val:0xfffdffff
+TEST_RR_OP(divu, x5, x0, x2, 0x0, 0x0, 0xfffdffff, x9, 24, x3)
+
+inst_15:
+// rs1==x6, rs2_val == 4294901759, 
+// opcode: divu ; op1:x6; op2:x12; dest:x7; op1val:0x55555555;  op2val:0xfffeffff
+TEST_RR_OP(divu, x7, x6, x12, 0x0, 0x55555555, 0xfffeffff, x9, 28, x3)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_16:
+// rs2==x6, rs2_val == 4294934527, 
+// opcode: divu ; op1:x14; op2:x6; dest:x13; op1val:0x8000;  op2val:0xffff7fff
+TEST_RR_OP(divu, x13, x14, x6, 0x0, 0x8000, 0xffff7fff, x1, 0, x3)
+
+inst_17:
+// rs2_val == 4294950911, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffffbfff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0xffffbfff, x1, 4, x3)
+
+inst_18:
+// rs2_val == 4294959103, rs1_val == 0
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffffdfff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xffffdfff, x1, 8, x3)
+
+inst_19:
+// rs2_val == 4294963199, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffffefff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xffffefff, x1, 12, x3)
+
+inst_20:
+// rs2_val == 4294965247, rs1_val == 4292870143
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffdfffff;  op2val:0xfffff7ff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffdfffff, 0xfffff7ff, x1, 16, x3)
+
+inst_21:
+// rs2_val == 4294966271, rs1_val == 2
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffffbff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xfffffbff, x1, 20, x3)
+
+inst_22:
+// rs2_val == 4294966783, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xfffffdff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0xfffffdff, x1, 24, x3)
+
+inst_23:
+// rs2_val == 4294967039, rs1_val == 4
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffffeff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xfffffeff, x1, 28, x3)
+
+inst_24:
+// rs2_val == 4294967167, rs1_val == 536870912
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0xffffff7f
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x20000000, 0xffffff7f, x1, 32, x3)
+
+inst_25:
+// rs2_val == 4294967231, rs1_val == 4294963199
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffefff;  op2val:0xffffffbf
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffffefff, 0xffffffbf, x1, 36, x3)
+
+inst_26:
+// rs2_val == 4294967263, rs1_val == 4294959103
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0xffffffdf
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffffdfff, 0xffffffdf, x1, 40, x3)
+
+inst_27:
+// rs2_val == 4294967279, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffefff;  op2val:0xffffffef
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffffefff, 0xffffffef, x1, 44, x3)
+
+inst_28:
+// rs2_val == 4294967287, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xe;  op2val:0xfffffff7
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xe, 0xfffffff7, x1, 48, x3)
+
+inst_29:
+// rs2_val == 4294967291, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffffffb
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xfffffffb, x1, 52, x3)
+
+inst_30:
+// rs2_val == 4294967293, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0xfffffffd
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffffffbf, 0xfffffffd, x1, 56, x3)
+
+inst_31:
+// rs2_val == 4294967294, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffffffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666667, 0xfffffffe, x1, 60, x3)
+
+inst_32:
+// rs1_val == 2147483647, rs2_val == 1073741824
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x40000000
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x7fffffff, 0x40000000, x1, 64, x3)
+
+inst_33:
+// rs1_val == 3221225471, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffff;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x3fffffff, 0xbfffffff, 0x3, x1, 68, x3)
+
+inst_34:
+// rs1_val == 3758096383, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffff;  op2val:0xffdfffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xdfffffff, 0xffdfffff, x1, 72, x3)
+
+inst_35:
+// rs1_val == 4026531839, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1536c, 0xefffffff, 0xb503, x1, 76, x3)
+
+inst_36:
+// rs1_val == 4160749567, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xf7ffffff;  op2val:0xff7fffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xf7ffffff, 0xff7fffff, x1, 80, x3)
+
+inst_37:
+// rs1_val == 4227858431, rs2_val == 536870912
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfbffffff;  op2val:0x20000000
+TEST_RR_OP(divu, x12, x10, x11, 0x7, 0xfbffffff, 0x20000000, x1, 84, x3)
+
+inst_38:
+// rs1_val == 4261412863, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0xfbffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfdffffff, 0xfbffffff, x1, 88, x3)
+
+inst_39:
+// rs1_val == 4278190079, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfeffffff;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xfeffffff, 0x66666667, x1, 92, x3)
+
+inst_40:
+// rs1_val == 4286578687, rs2_val == 67108864
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xff7fffff;  op2val:0x4000000
+TEST_RR_OP(divu, x12, x10, x11, 0x3f, 0xff7fffff, 0x4000000, x1, 96, x3)
+
+inst_41:
+// rs1_val == 4290772991, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffff;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffbfffff, 0xaaaaaaa9, x1, 100, x3)
+
+inst_42:
+// rs1_val == 4293918719, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffefffff;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x2aa7ffff, 0xffefffff, 0x6, x1, 104, x3)
+
+inst_43:
+// rs1_val == 4294705151, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffbffff;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x33326666, 0xfffbffff, 0x5, x1, 108, x3)
+
+inst_44:
+// rs1_val == 4294901759, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffeffff;  op2val:0x11
+TEST_RR_OP(divu, x12, x10, x11, 0xf0effff, 0xfffeffff, 0x11, x1, 112, x3)
+
+inst_45:
+// rs1_val == 4294934527, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fff;  op2val:0xfffffffd
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff7fff, 0xfffffffd, x1, 116, x3)
+
+inst_46:
+// rs1_val == 4294950911, rs2_val == 8
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfff;  op2val:0x8
+TEST_RR_OP(divu, x12, x10, x11, 0x1ffff7ff, 0xffffbfff, 0x8, x1, 120, x3)
+
+inst_47:
+// rs1_val == 4294965247, rs2_val == 2147483648
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ff;  op2val:0x80000000
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffff7ff, 0x80000000, x1, 124, x3)
+
+inst_48:
+// rs1_val == 4294966271, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffbff;  op2val:0xffffffbf
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffffbff, 0xffffffbf, x1, 128, x3)
+
+inst_49:
+// rs1_val == 4294966783, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdff;  op2val:0x7
+TEST_RR_OP(divu, x12, x10, x11, 0x249248db, 0xfffffdff, 0x7, x1, 132, x3)
+
+inst_50:
+// rs1_val == 4294967039, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffeff;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xfffffeff, 0x66666667, x1, 136, x3)
+
+inst_51:
+// rs1_val == 4294967279, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffef;  op2val:0x7
+TEST_RR_OP(divu, x12, x10, x11, 0x24924922, 0xffffffef, 0x7, x1, 140, x3)
+
+inst_52:
+// rs1_val == 4294967287, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0xff7fffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffffff7, 0xff7fffff, x1, 144, x3)
+
+inst_53:
+// rs1_val == 4294967291, rs2_val == 4
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffb;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x3ffffffe, 0xfffffffb, 0x4, x1, 148, x3)
+
+inst_54:
+// rs1_val == 4294967293, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffd;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xfffffffd, 0x66666665, x1, 152, x3)
+
+inst_55:
+// rs1_val == 4294967294, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffe;  op2val:0xffdfffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffffffe, 0xffdfffff, x1, 156, x3)
+
+inst_56:
+// rs2_val == 268435456, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xa;  op2val:0x10000000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xa, 0x10000000, x1, 160, x3)
+
+inst_57:
+// rs2_val == 134217728, rs1_val == 16777216
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x8000000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1000000, 0x8000000, x1, 164, x3)
+
+inst_58:
+// rs2_val == 33554432, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0x2000000
+TEST_RR_OP(divu, x12, x10, x11, 0x7f, 0xffffdfff, 0x2000000, x1, 168, x3)
+
+inst_59:
+// rs2_val == 16777216, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1000000
+TEST_RR_OP(divu, x12, x10, x11, 0x55, 0x55555555, 0x1000000, x1, 172, x3)
+
+inst_60:
+// rs2_val == 8388608, rs1_val == 67108864
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x800000
+TEST_RR_OP(divu, x12, x10, x11, 0x8, 0x4000000, 0x800000, x1, 176, x3)
+
+inst_61:
+// rs2_val == 4194304, rs1_val == 262144
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x400000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x40000, 0x400000, x1, 180, x3)
+
+inst_62:
+// rs2_val == 2097152, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x12;  op2val:0x200000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x12, 0x200000, x1, 184, x3)
+
+inst_63:
+// rs2_val == 1048576, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x100000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x100000, x1, 188, x3)
+
+inst_64:
+// rs2_val == 524288, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x80000
+TEST_RR_OP(divu, x12, x10, x11, 0xaaa, 0x55555555, 0x80000, x1, 192, x3)
+
+inst_65:
+// rs2_val == 262144, rs1_val == 32
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x40000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x20, 0x40000, x1, 196, x3)
+
+inst_66:
+// rs2_val == 131072, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x20000
+TEST_RR_OP(divu, x12, x10, x11, 0x1999, 0x33333333, 0x20000, x1, 200, x3)
+
+inst_67:
+// rs2_val == 65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0xffff, 0xffffffdf, 0x10000, x1, 204, x3)
+
+inst_68:
+// rs2_val == 32768, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0x8000
+TEST_RR_OP(divu, x12, x10, x11, 0x1ffff, 0xffffdfff, 0x8000, x1, 208, x3)
+
+inst_69:
+// rs2_val == 16384, rs1_val == 134217728
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x4000
+TEST_RR_OP(divu, x12, x10, x11, 0x2000, 0x8000000, 0x4000, x1, 212, x3)
+
+inst_70:
+// rs2_val == 8192, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0x2000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x7, 0x2000, x1, 216, x3)
+
+inst_71:
+// rs2_val == 4096, rs1_val == (2**(xlen)-1)
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff;  op2val:0x1000
+TEST_RR_OP(divu, x12, x10, x11, 0xfffff, 0xffffffff, 0x1000, x1, 220, x3)
+
+inst_72:
+// rs2_val == 2048, rs1_val == 131072
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x800
+TEST_RR_OP(divu, x12, x10, x11, 0x40, 0x20000, 0x800, x1, 224, x3)
+
+inst_73:
+// rs2_val == 1024, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x400
+TEST_RR_OP(divu, x12, x10, x11, 0x80, 0x20000, 0x400, x1, 228, x3)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x200
+TEST_RR_OP(divu, x12, x10, x11, 0x800, 0x100000, 0x200, x1, 232, x3)
+
+inst_75:
+// rs2_val == 256, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0x100
+TEST_RR_OP(divu, x12, x10, x11, 0xefffff, 0xefffffff, 0x100, x1, 236, x3)
+
+inst_76:
+// rs2_val == 128, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x80
+TEST_RR_OP(divu, x12, x10, x11, 0x16a, 0xb503, 0x80, x1, 240, x3)
+
+inst_77:
+// rs2_val == 64, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xc;  op2val:0x40
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xc, 0x40, x1, 244, x3)
+
+inst_78:
+// rs2_val == 32, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x20
+TEST_RR_OP(divu, x12, x10, x11, 0x1000000, 0x20000000, 0x20, x1, 248, x3)
+
+inst_79:
+// rs2_val == 16, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffeffff;  op2val:0x10
+TEST_RR_OP(divu, x12, x10, x11, 0xfffefff, 0xfffeffff, 0x10, x1, 252, x3)
+
+inst_80:
+// rs2_val == 2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x7fffffdf, 0xffffffbf, 0x2, x1, 256, x3)
+
+inst_81:
+// rs2_val == 1, rs1_val == 524288
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x80000, 0x80000, 0x1, x1, 260, x3)
+
+inst_82:
+// rs1_val == 2147483648, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x80000000;  op2val:0xb
+TEST_RR_OP(divu, x12, x10, x11, 0xba2e8ba, 0x80000000, 0xb, x1, 264, x3)
+
+inst_83:
+// rs1_val == 1073741824, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x1000
+TEST_RR_OP(divu, x12, x10, x11, 0x40000, 0x40000000, 0x1000, x1, 268, x3)
+
+inst_84:
+// rs1_val == 268435456, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1000, 0x10000000, 0xffff, x1, 272, x3)
+
+inst_85:
+// rs1_val == 33554432, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2000000, 0x55555556, x1, 276, x3)
+
+inst_86:
+// rs1_val == 8388608, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x800000, 0x800000, 0x1, x1, 280, x3)
+
+inst_87:
+// rs1_val == 4194304, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xffffefff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x400000, 0xffffefff, x1, 284, x3)
+
+inst_88:
+// rs1_val == 2097152, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0xfdffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x200000, 0xfdffffff, x1, 288, x3)
+
+inst_89:
+// rs1_val == 65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x2000000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x2000000, x1, 292, x3)
+
+inst_90:
+// rs1_val == 16384, rs2_val == (2**(xlen)-1)
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xffffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4000, 0xffffffff, x1, 296, x3)
+
+inst_91:
+// rs1_val == 8192, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x666, 0x2000, 0x5, x1, 300, x3)
+
+inst_92:
+// rs1_val == 4096, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x11
+TEST_RR_OP(divu, x12, x10, x11, 0xf0, 0x1000, 0x11, x1, 304, x3)
+
+inst_93:
+// rs1_val == 2048, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x800, 0xaaaaaaa9, x1, 308, x3)
+
+inst_94:
+// rs1_val == 1024, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0xffffffef
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x400, 0xffffffef, x1, 312, x3)
+
+inst_95:
+// rs1_val == 512, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0xfffffffd
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x200, 0xfffffffd, x1, 316, x3)
+
+inst_96:
+// rs1_val == 256, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x40000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x100, 0x40000, x1, 320, x3)
+
+inst_97:
+// rs1_val == 128, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0xfffbffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x80, 0xfffbffff, x1, 324, x3)
+
+inst_98:
+// rs1_val == 64, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x40, 0x10000, x1, 328, x3)
+
+inst_99:
+// rs1_val == 16, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0xff7fffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10, 0xff7fffff, x1, 332, x3)
+
+inst_100:
+// rs1_val==65536 and rs2_val==65536, rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0x10000, x1, 336, x3)
+
+inst_101:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x10000, 0x10000, 0x1, x1, 340, x3)
+
+inst_102:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0xb505, x1, 344, x3)
+
+inst_103:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x66666667, x1, 348, x3)
+
+inst_104:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x33333334, x1, 352, x3)
+
+inst_105:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaa, 0x10000, 0x6, x1, 356, x3)
+
+inst_106:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0xaaaaaaab, x1, 360, x3)
+
+inst_107:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x55555556, x1, 364, x3)
+
+inst_108:
+// rs1_val==65536 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x4000, 0x10000, 0x4, x1, 368, x3)
+
+inst_109:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0xfffe, x1, 372, x3)
+
+inst_110:
+// rs1_val==65536 and rs2_val==0, rs2_val == 0
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x10000, 0x0, x1, 376, x3)
+
+inst_111:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0xb503, x1, 380, x3)
+
+inst_112:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x66666665, x1, 384, x3)
+
+inst_113:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x33333332, x1, 388, x3)
+
+inst_114:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0xaaaaaaa9, x1, 392, x3)
+
+inst_115:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x55555554, x1, 396, x3)
+
+inst_116:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x8000, 0x10000, 0x2, x1, 400, x3)
+
+inst_117:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0xffff, x1, 404, x3)
+
+inst_118:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x10000, 0xb504, x1, 408, x3)
+
+inst_119:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x66666666, x1, 412, x3)
+
+inst_120:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x33333333, x1, 416, x3)
+
+inst_121:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x10000, 0x5, x1, 420, x3)
+
+inst_122:
+// rs1_val==65536 and rs2_val==2863311530, rs2_val == 2863311530
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0xaaaaaaaa, x1, 424, x3)
+
+inst_123:
+// rs1_val==65536 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x10000, 0x55555555, x1, 428, x3)
+
+inst_124:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x10000, 0x3, x1, 432, x3)
+
+inst_125:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x10000, x1, 436, x3)
+
+inst_126:
+// rs1_val==1 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x1, 0x1, x1, 440, x3)
+
+inst_127:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xb505, x1, 444, x3)
+
+inst_128:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x66666667, x1, 448, x3)
+
+inst_129:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x33333334, x1, 452, x3)
+
+inst_130:
+// rs1_val==1 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x6, x1, 456, x3)
+
+inst_131:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaab, x1, 460, x3)
+
+inst_132:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x55555556, x1, 464, x3)
+
+inst_133:
+// rs1_val==1 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x4, x1, 468, x3)
+
+inst_134:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xfffe, x1, 472, x3)
+
+inst_135:
+// rs1_val==1 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x1, 0x0, x1, 476, x3)
+
+inst_136:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xb503, x1, 480, x3)
+
+inst_137:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x66666665, x1, 484, x3)
+
+inst_138:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x33333332, x1, 488, x3)
+
+inst_139:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaa9, x1, 492, x3)
+
+inst_140:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x55555554, x1, 496, x3)
+
+inst_141:
+// rs1_val==1 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x2, x1, 500, x3)
+
+inst_142:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xffff, x1, 504, x3)
+
+inst_143:
+// rs1_val==1 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xb504, x1, 508, x3)
+
+inst_144:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x66666666, x1, 512, x3)
+
+inst_145:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x33333333, x1, 516, x3)
+
+inst_146:
+// rs1_val==1 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x5, x1, 520, x3)
+
+inst_147:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaaa, x1, 524, x3)
+
+inst_148:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x55555555, x1, 528, x3)
+
+inst_149:
+// rs1_val==1 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x1, 0x3, x1, 532, x3)
+
+inst_150:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x10000, x1, 536, x3)
+
+inst_151:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xb505, 0xb505, 0x1, x1, 540, x3)
+
+inst_152:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb505, 0xb505, x1, 544, x3)
+
+inst_153:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x66666667, x1, 548, x3)
+
+inst_154:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x33333334, x1, 552, x3)
+
+inst_155:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1e2b, 0xb505, 0x6, x1, 556, x3)
+
+inst_156:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0xaaaaaaab, x1, 560, x3)
+
+inst_157:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x55555556, x1, 564, x3)
+
+inst_158:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2d41, 0xb505, 0x4, x1, 568, x3)
+
+inst_159:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0xfffe, x1, 572, x3)
+
+inst_160:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xb505, 0x0, x1, 576, x3)
+
+inst_161:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb505, 0xb503, x1, 580, x3)
+
+inst_162:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x66666665, x1, 584, x3)
+
+inst_163:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x33333332, x1, 588, x3)
+
+inst_164:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0xaaaaaaa9, x1, 592, x3)
+
+inst_165:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x55555554, x1, 596, x3)
+
+inst_166:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x5a82, 0xb505, 0x2, x1, 600, x3)
+
+inst_167:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0xffff, x1, 604, x3)
+
+inst_168:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb505, 0xb504, x1, 608, x3)
+
+inst_169:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x66666666, x1, 612, x3)
+
+inst_170:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x33333333, x1, 616, x3)
+
+inst_171:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x2434, 0xb505, 0x5, x1, 620, x3)
+
+inst_172:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0xaaaaaaaa, x1, 624, x3)
+
+inst_173:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb505, 0x55555555, x1, 628, x3)
+
+inst_174:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x3c57, 0xb505, 0x3, x1, 632, x3)
+
+inst_175:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666667, 0x10000, x1, 636, x3)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x66666667, 0x66666667, 0x1, x1, 640, x3)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x90d0, 0x66666667, 0xb505, x1, 644, x3)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x66666667, x1, 648, x3)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x33333334, x1, 652, x3)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x66666667, 0x6, x1, 656, x3)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666667, 0xaaaaaaab, x1, 660, x3)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x55555556, x1, 664, x3)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x19999999, 0x66666667, 0x4, x1, 668, x3)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x6667, 0x66666667, 0xfffe, x1, 672, x3)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x66666667, 0x0, x1, 676, x3)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x90d2, 0x66666667, 0xb503, x1, 680, x3)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x66666665, x1, 684, x3)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x66666667, 0x33333332, x1, 688, x3)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666667, 0xaaaaaaa9, x1, 692, x3)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x55555554, x1, 696, x3)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x33333333, 0x66666667, 0x2, x1, 700, x3)
+
+inst_192:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666667, 0xffff, x1, 704, x3)
+
+inst_193:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x90d1, 0x66666667, 0xb504, x1, 708, x3)
+
+inst_194:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 712, x3)
+
+inst_195:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x66666667, 0x33333333, x1, 716, x3)
+
+inst_196:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x147ae147, 0x66666667, 0x5, x1, 720, x3)
+
+inst_197:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666667, 0xaaaaaaaa, x1, 724, x3)
+
+inst_198:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666667, 0x55555555, x1, 728, x3)
+
+inst_199:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x22222222, 0x66666667, 0x3, x1, 732, x3)
+
+inst_200:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333334, 0x10000, x1, 736, x3)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x33333334, 0x33333334, 0x1, x1, 740, x3)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333334, 0xb505, x1, 744, x3)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x66666667, x1, 748, x3)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333334, 0x33333334, x1, 752, x3)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x8888888, 0x33333334, 0x6, x1, 756, x3)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0xaaaaaaab, x1, 760, x3)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x55555556, x1, 764, x3)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0xccccccd, 0x33333334, 0x4, x1, 768, x3)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333334, 0xfffe, x1, 772, x3)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x33333334, 0x0, x1, 776, x3)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x4869, 0x33333334, 0xb503, x1, 780, x3)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x66666665, x1, 784, x3)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333334, 0x33333332, x1, 788, x3)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0xaaaaaaa9, x1, 792, x3)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x55555554, x1, 796, x3)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x1999999a, 0x33333334, 0x2, x1, 800, x3)
+
+inst_217:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333334, 0xffff, x1, 804, x3)
+
+inst_218:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333334, 0xb504, x1, 808, x3)
+
+inst_219:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x66666666, x1, 812, x3)
+
+inst_220:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333334, 0x33333333, x1, 816, x3)
+
+inst_221:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0xa3d70a4, 0x33333334, 0x5, x1, 820, x3)
+
+inst_222:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0xaaaaaaaa, x1, 824, x3)
+
+inst_223:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333334, 0x55555555, x1, 828, x3)
+
+inst_224:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x33333334, 0x3, x1, 832, x3)
+
+inst_225:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x10000, x1, 836, x3)
+
+inst_226:
+// rs1_val==6 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x6, 0x6, 0x1, x1, 840, x3)
+
+inst_227:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xb505, x1, 844, x3)
+
+inst_228:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x66666667, x1, 848, x3)
+
+inst_229:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x33333334, x1, 852, x3)
+
+inst_230:
+// rs1_val==6 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x6, 0x6, x1, 856, x3)
+
+inst_231:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xaaaaaaab, x1, 860, x3)
+
+inst_232:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x55555556, x1, 864, x3)
+
+inst_233:
+// rs1_val==6 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x6, 0x4, x1, 868, x3)
+
+inst_234:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xfffe, x1, 872, x3)
+
+inst_235:
+// rs1_val==6 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x6, 0x0, x1, 876, x3)
+
+inst_236:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xb503, x1, 880, x3)
+
+inst_237:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x66666665, x1, 884, x3)
+
+inst_238:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x33333332, x1, 888, x3)
+
+inst_239:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xaaaaaaa9, x1, 892, x3)
+
+inst_240:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x55555554, x1, 896, x3)
+
+inst_241:
+// rs1_val==6 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0x6, 0x2, x1, 900, x3)
+
+inst_242:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xffff, x1, 904, x3)
+
+inst_243:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xb504, x1, 908, x3)
+
+inst_244:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x66666666, x1, 912, x3)
+
+inst_245:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x33333333, x1, 916, x3)
+
+inst_246:
+// rs1_val==6 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x6, 0x5, x1, 920, x3)
+
+inst_247:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0xaaaaaaaa, x1, 924, x3)
+
+inst_248:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x6, 0x55555555, x1, 928, x3)
+
+inst_249:
+// rs1_val==6 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x6, 0x3, x1, 932, x3)
+
+inst_250:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaa, 0xaaaaaaab, 0x10000, x1, 936, x3)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaaaaab, 0xaaaaaaab, 0x1, x1, 940, x3)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0xf15b, 0xaaaaaaab, 0xb505, x1, 944, x3)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x66666667, x1, 948, x3)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x33333334, x1, 952, x3)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0xaaaaaaab, 0x6, x1, 956, x3)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0xaaaaaaab, x1, 960, x3)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x55555556, x1, 964, x3)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaaa, 0xaaaaaaab, 0x4, x1, 968, x3)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0xaaac, 0xaaaaaaab, 0xfffe, x1, 972, x3)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xaaaaaaab, 0x0, x1, 976, x3)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0xf15e, 0xaaaaaaab, 0xb503, x1, 980, x3)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x66666665, x1, 984, x3)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x33333332, x1, 988, x3)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0xaaaaaaa9, x1, 992, x3)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xaaaaaaab, 0x55555554, x1, 996, x3)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x55555555, 0xaaaaaaab, 0x2, x1, 1000, x3)
+
+inst_267:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0xaaab, 0xaaaaaaab, 0xffff, x1, 1004, x3)
+
+inst_268:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0xf15d, 0xaaaaaaab, 0xb504, x1, 1008, x3)
+
+inst_269:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x66666666, x1, 1012, x3)
+
+inst_270:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x33333333, x1, 1016, x3)
+
+inst_271:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x22222222, 0xaaaaaaab, 0x5, x1, 1020, x3)
+
+inst_272:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaab, 0xaaaaaaaa, x1, 1024, x3)
+
+inst_273:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xaaaaaaab, 0x55555555, x1, 1028, x3)
+
+inst_274:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x38e38e39, 0xaaaaaaab, 0x3, x1, 1032, x3)
+
+inst_275:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555556, 0x10000, x1, 1036, x3)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x55555556, 0x55555556, 0x1, x1, 1040, x3)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x78ad, 0x55555556, 0xb505, x1, 1044, x3)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0x66666667, x1, 1048, x3)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x33333334, x1, 1052, x3)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0xe38e38e, 0x55555556, 0x6, x1, 1056, x3)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0xaaaaaaab, x1, 1060, x3)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x55555556, x1, 1064, x3)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x15555555, 0x55555556, 0x4, x1, 1068, x3)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x5556, 0x55555556, 0xfffe, x1, 1072, x3)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x55555556, 0x0, x1, 1076, x3)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x78af, 0x55555556, 0xb503, x1, 1080, x3)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0x66666665, x1, 1084, x3)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x33333332, x1, 1088, x3)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0xaaaaaaa9, x1, 1092, x3)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x55555554, x1, 1096, x3)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaab, 0x55555556, 0x2, x1, 1100, x3)
+
+inst_292:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555556, 0xffff, x1, 1104, x3)
+
+inst_293:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x78ae, 0x55555556, 0xb504, x1, 1108, x3)
+
+inst_294:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0x66666666, x1, 1112, x3)
+
+inst_295:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x33333333, x1, 1116, x3)
+
+inst_296:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x55555556, 0x5, x1, 1120, x3)
+
+inst_297:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555556, 0xaaaaaaaa, x1, 1124, x3)
+
+inst_298:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555556, 0x55555555, x1, 1128, x3)
+
+inst_299:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x3, x1, 1132, x3)
+
+inst_300:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x10000, x1, 1136, x3)
+
+inst_301:
+// rs1_val==4 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x4, 0x4, 0x1, x1, 1140, x3)
+
+inst_302:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xb505, x1, 1144, x3)
+
+inst_303:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x66666667, x1, 1148, x3)
+
+inst_304:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x33333334, x1, 1152, x3)
+
+inst_305:
+// rs1_val==4 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x6, x1, 1156, x3)
+
+inst_306:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xaaaaaaab, x1, 1160, x3)
+
+inst_307:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x55555556, x1, 1164, x3)
+
+inst_308:
+// rs1_val==4 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x4, 0x4, x1, 1168, x3)
+
+inst_309:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xfffe, x1, 1172, x3)
+
+inst_310:
+// rs1_val==4 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x4, 0x0, x1, 1176, x3)
+
+inst_311:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xb503, x1, 1180, x3)
+
+inst_312:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x66666665, x1, 1184, x3)
+
+inst_313:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x33333332, x1, 1188, x3)
+
+inst_314:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xaaaaaaa9, x1, 1192, x3)
+
+inst_315:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x55555554, x1, 1196, x3)
+
+inst_316:
+// rs1_val==4 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x4, 0x2, x1, 1200, x3)
+
+inst_317:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xffff, x1, 1204, x3)
+
+inst_318:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xb504, x1, 1208, x3)
+
+inst_319:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x66666666, x1, 1212, x3)
+
+inst_320:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x33333333, x1, 1216, x3)
+
+inst_321:
+// rs1_val==4 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x5, x1, 1220, x3)
+
+inst_322:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0xaaaaaaaa, x1, 1224, x3)
+
+inst_323:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x4, 0x55555555, x1, 1228, x3)
+
+inst_324:
+// rs1_val==4 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x4, 0x3, x1, 1232, x3)
+
+inst_325:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x10000, x1, 1236, x3)
+
+inst_326:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xfffe, 0xfffe, 0x1, x1, 1240, x3)
+
+inst_327:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffe, 0xb505, x1, 1244, x3)
+
+inst_328:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x66666667, x1, 1248, x3)
+
+inst_329:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x33333334, x1, 1252, x3)
+
+inst_330:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaa, 0xfffe, 0x6, x1, 1256, x3)
+
+inst_331:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0xaaaaaaab, x1, 1260, x3)
+
+inst_332:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x55555556, x1, 1264, x3)
+
+inst_333:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x3fff, 0xfffe, 0x4, x1, 1268, x3)
+
+inst_334:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffe, 0xfffe, x1, 1272, x3)
+
+inst_335:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xfffe, 0x0, x1, 1276, x3)
+
+inst_336:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffe, 0xb503, x1, 1280, x3)
+
+inst_337:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x66666665, x1, 1284, x3)
+
+inst_338:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x33333332, x1, 1288, x3)
+
+inst_339:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0xaaaaaaa9, x1, 1292, x3)
+
+inst_340:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x55555554, x1, 1296, x3)
+
+inst_341:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x7fff, 0xfffe, 0x2, x1, 1300, x3)
+
+inst_342:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0xffff, x1, 1304, x3)
+
+inst_343:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffe, 0xb504, x1, 1308, x3)
+
+inst_344:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x66666666, x1, 1312, x3)
+
+inst_345:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x33333333, x1, 1316, x3)
+
+inst_346:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x3332, 0xfffe, 0x5, x1, 1320, x3)
+
+inst_347:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0xaaaaaaaa, x1, 1324, x3)
+
+inst_348:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xfffe, 0x55555555, x1, 1328, x3)
+
+inst_349:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x5554, 0xfffe, 0x3, x1, 1332, x3)
+
+inst_350:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x10000, x1, 1336, x3)
+
+inst_351:
+// rs1_val==0 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x1, x1, 1340, x3)
+
+inst_352:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1344, x3)
+
+inst_353:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1348, x3)
+
+inst_354:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1352, x3)
+
+inst_355:
+// rs1_val==0 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1356, x3)
+
+inst_356:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaab, x1, 1360, x3)
+
+inst_357:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1364, x3)
+
+inst_358:
+// rs1_val==0 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1368, x3)
+
+inst_359:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xfffe, x1, 1372, x3)
+
+inst_360:
+// rs1_val==0 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x0, 0x0, x1, 1376, x3)
+
+inst_361:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1380, x3)
+
+inst_362:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1384, x3)
+
+inst_363:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1388, x3)
+
+inst_364:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaa9, x1, 1392, x3)
+
+inst_365:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1396, x3)
+
+inst_366:
+// rs1_val==0 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x2, x1, 1400, x3)
+
+inst_367:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xffff, x1, 1404, x3)
+
+inst_368:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1408, x3)
+
+inst_369:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1412, x3)
+
+inst_370:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1416, x3)
+
+inst_371:
+// rs1_val==0 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1420, x3)
+
+inst_372:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaaa, x1, 1424, x3)
+
+inst_373:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1428, x3)
+
+inst_374:
+// rs1_val==0 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1432, x3)
+
+inst_375:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x10000, x1, 1436, x3)
+
+inst_376:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xb503, 0xb503, 0x1, x1, 1440, x3)
+
+inst_377:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xb505, x1, 1444, x3)
+
+inst_378:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x66666667, x1, 1448, x3)
+
+inst_379:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x33333334, x1, 1452, x3)
+
+inst_380:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1e2b, 0xb503, 0x6, x1, 1456, x3)
+
+inst_381:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xaaaaaaab, x1, 1460, x3)
+
+inst_382:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x55555556, x1, 1464, x3)
+
+inst_383:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2d40, 0xb503, 0x4, x1, 1468, x3)
+
+inst_384:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xfffe, x1, 1472, x3)
+
+inst_385:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xb503, 0x0, x1, 1476, x3)
+
+inst_386:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb503, 0xb503, x1, 1480, x3)
+
+inst_387:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x66666665, x1, 1484, x3)
+
+inst_388:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x33333332, x1, 1488, x3)
+
+inst_389:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xaaaaaaa9, x1, 1492, x3)
+
+inst_390:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x55555554, x1, 1496, x3)
+
+inst_391:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x5a81, 0xb503, 0x2, x1, 1500, x3)
+
+inst_392:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xffff, x1, 1504, x3)
+
+inst_393:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xb504, x1, 1508, x3)
+
+inst_394:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x66666666, x1, 1512, x3)
+
+inst_395:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x33333333, x1, 1516, x3)
+
+inst_396:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x2433, 0xb503, 0x5, x1, 1520, x3)
+
+inst_397:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0xaaaaaaaa, x1, 1524, x3)
+
+inst_398:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb503, 0x55555555, x1, 1528, x3)
+
+inst_399:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x3c56, 0xb503, 0x3, x1, 1532, x3)
+
+inst_400:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666665, 0x10000, x1, 1536, x3)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x66666665, 0x66666665, 0x1, x1, 1540, x3)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x90d0, 0x66666665, 0xb505, x1, 1544, x3)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666665, 0x66666667, x1, 1548, x3)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x33333334, x1, 1552, x3)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x11111110, 0x66666665, 0x6, x1, 1556, x3)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666665, 0xaaaaaaab, x1, 1560, x3)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x55555556, x1, 1564, x3)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x19999999, 0x66666665, 0x4, x1, 1568, x3)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x6667, 0x66666665, 0xfffe, x1, 1572, x3)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x66666665, 0x0, x1, 1576, x3)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x90d2, 0x66666665, 0xb503, x1, 1580, x3)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x66666665, x1, 1584, x3)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x66666665, 0x33333332, x1, 1588, x3)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666665, 0xaaaaaaa9, x1, 1592, x3)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x55555554, x1, 1596, x3)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x33333332, 0x66666665, 0x2, x1, 1600, x3)
+
+inst_417:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666665, 0xffff, x1, 1604, x3)
+
+inst_418:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x90d1, 0x66666665, 0xb504, x1, 1608, x3)
+
+inst_419:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666665, 0x66666666, x1, 1612, x3)
+
+inst_420:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x33333333, x1, 1616, x3)
+
+inst_421:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x147ae147, 0x66666665, 0x5, x1, 1620, x3)
+
+inst_422:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666665, 0xaaaaaaaa, x1, 1624, x3)
+
+inst_423:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666665, 0x55555555, x1, 1628, x3)
+
+inst_424:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x22222221, 0x66666665, 0x3, x1, 1632, x3)
+
+inst_425:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333332, 0x10000, x1, 1636, x3)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x33333332, 0x33333332, 0x1, x1, 1640, x3)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333332, 0xb505, x1, 1644, x3)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x66666667, x1, 1648, x3)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x33333334, x1, 1652, x3)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x8888888, 0x33333332, 0x6, x1, 1656, x3)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0xaaaaaaab, x1, 1660, x3)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x55555556, x1, 1664, x3)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0xccccccc, 0x33333332, 0x4, x1, 1668, x3)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333332, 0xfffe, x1, 1672, x3)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x33333332, 0x0, x1, 1676, x3)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x4869, 0x33333332, 0xb503, x1, 1680, x3)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x66666665, x1, 1684, x3)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333332, 0x33333332, x1, 1688, x3)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0xaaaaaaa9, x1, 1692, x3)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x55555554, x1, 1696, x3)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x19999999, 0x33333332, 0x2, x1, 1700, x3)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333332, 0xffff, x1, 1704, x3)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333332, 0xb504, x1, 1708, x3)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x66666666, x1, 1712, x3)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x33333333, x1, 1716, x3)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x5, x1, 1720, x3)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0xaaaaaaaa, x1, 1724, x3)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333332, 0x55555555, x1, 1728, x3)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x11111110, 0x33333332, 0x3, x1, 1732, x3)
+
+inst_450:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaa, 0xaaaaaaa9, 0x10000, x1, 1736, x3)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0x1, x1, 1740, x3)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0xf15b, 0xaaaaaaa9, 0xb505, x1, 1744, x3)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x66666667, x1, 1748, x3)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaa9, 0x33333334, x1, 1752, x3)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0xaaaaaaa9, 0x6, x1, 1756, x3)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xaaaaaaab, x1, 1760, x3)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x55555556, x1, 1764, x3)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaaa, 0xaaaaaaa9, 0x4, x1, 1768, x3)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0xaaac, 0xaaaaaaa9, 0xfffe, x1, 1772, x3)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xaaaaaaa9, 0x0, x1, 1776, x3)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0xf15e, 0xaaaaaaa9, 0xb503, x1, 1780, x3)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x66666665, x1, 1784, x3)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaa9, 0x33333332, x1, 1788, x3)
+
+inst_464:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0xaaaaaaa9, x1, 1792, x3)
+
+inst_465:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xaaaaaaa9, 0x55555554, x1, 1796, x3)
+
+inst_466:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x55555554, 0xaaaaaaa9, 0x2, x1, 1800, x3)
+
+inst_467:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0xaaab, 0xaaaaaaa9, 0xffff, x1, 1804, x3)
+
+inst_468:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0xf15d, 0xaaaaaaa9, 0xb504, x1, 1808, x3)
+
+inst_469:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x66666666, x1, 1812, x3)
+
+inst_470:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaa9, 0x33333333, x1, 1816, x3)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x15555555, 0x55555554, 0x4, x1, 1820, x3)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x5556, 0x55555554, 0xfffe, x1, 1824, x3)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x55555554, 0x0, x1, 1828, x3)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x78af, 0x55555554, 0xb503, x1, 1832, x3)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0x66666665, x1, 1836, x3)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555554, 0x33333332, x1, 1840, x3)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0xaaaaaaa9, x1, 1844, x3)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555554, 0x55555554, x1, 1848, x3)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaaa, 0x55555554, 0x2, x1, 1852, x3)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555554, 0xffff, x1, 1856, x3)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x78ae, 0x55555554, 0xb504, x1, 1860, x3)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0x66666666, x1, 1864, x3)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555554, 0x33333333, x1, 1868, x3)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x11111110, 0x55555554, 0x5, x1, 1872, x3)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0xaaaaaaaa, x1, 1876, x3)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0x55555555, x1, 1880, x3)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0x55555554, 0x3, x1, 1884, x3)
+
+inst_488:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x10000, x1, 1888, x3)
+
+inst_489:
+// rs1_val==2 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x2, 0x1, x1, 1892, x3)
+
+inst_490:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xb505, x1, 1896, x3)
+
+inst_491:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x66666667, x1, 1900, x3)
+
+inst_492:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x33333334, x1, 1904, x3)
+
+inst_493:
+// rs1_val==2 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x6, x1, 1908, x3)
+
+inst_494:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xaaaaaaab, x1, 1912, x3)
+
+inst_495:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x55555556, x1, 1916, x3)
+
+inst_496:
+// rs1_val==2 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x4, x1, 1920, x3)
+
+inst_497:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xfffe, x1, 1924, x3)
+
+inst_498:
+// rs1_val==2 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x2, 0x0, x1, 1928, x3)
+
+inst_499:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xb503, x1, 1932, x3)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x66666665, x1, 1936, x3)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x33333332, x1, 1940, x3)
+
+inst_502:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xaaaaaaa9, x1, 1944, x3)
+
+inst_503:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x55555554, x1, 1948, x3)
+
+inst_504:
+// rs1_val==2 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x2, 0x2, x1, 1952, x3)
+
+inst_505:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xffff, x1, 1956, x3)
+
+inst_506:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xb504, x1, 1960, x3)
+
+inst_507:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x66666666, x1, 1964, x3)
+
+inst_508:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x33333333, x1, 1968, x3)
+
+inst_509:
+// rs1_val==2 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x5, x1, 1972, x3)
+
+inst_510:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0xaaaaaaaa, x1, 1976, x3)
+
+inst_511:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x55555555, x1, 1980, x3)
+
+inst_512:
+// rs1_val==2 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x2, 0x3, x1, 1984, x3)
+
+inst_513:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x10000, x1, 1988, x3)
+
+inst_514:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xffff, 0xffff, 0x1, x1, 1992, x3)
+
+inst_515:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffff, 0xb505, x1, 1996, x3)
+
+inst_516:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x66666667, x1, 2000, x3)
+
+inst_517:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x33333334, x1, 2004, x3)
+
+inst_518:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaa, 0xffff, 0x6, x1, 2008, x3)
+
+inst_519:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0xaaaaaaab, x1, 2012, x3)
+
+inst_520:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x55555556, x1, 2016, x3)
+
+inst_521:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x3fff, 0xffff, 0x4, x1, 2020, x3)
+
+inst_522:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffff, 0xfffe, x1, 2024, x3)
+
+inst_523:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xffff, 0x0, x1, 2028, x3)
+
+inst_524:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffff, 0xb503, x1, 2032, x3)
+
+inst_525:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x66666665, x1, 2036, x3)
+
+inst_526:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x33333332, x1, 2040, x3)
+
+inst_527:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0xaaaaaaa9, x1, 2044, x3)
+RVTEST_SIGBASE( x1,signature_x1_3)
+
+inst_528:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x55555554, x1, 0, x3)
+
+inst_529:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x7fff, 0xffff, 0x2, x1, 4, x3)
+
+inst_530:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffff, 0xffff, x1, 8, x3)
+
+inst_531:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffff, 0xb504, x1, 12, x3)
+
+inst_532:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x66666666, x1, 16, x3)
+
+inst_533:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x33333333, x1, 20, x3)
+
+inst_534:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0xffff, 0x5, x1, 24, x3)
+
+inst_535:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0xaaaaaaaa, x1, 28, x3)
+
+inst_536:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xffff, 0x55555555, x1, 32, x3)
+
+inst_537:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0xffff, 0x3, x1, 36, x3)
+
+inst_538:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x10000, x1, 40, x3)
+
+inst_539:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xb504, 0xb504, 0x1, x1, 44, x3)
+
+inst_540:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xb505, x1, 48, x3)
+
+inst_541:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x66666667, x1, 52, x3)
+
+inst_542:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x33333334, x1, 56, x3)
+
+inst_543:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1e2b, 0xb504, 0x6, x1, 60, x3)
+
+inst_544:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xaaaaaaab, x1, 64, x3)
+
+inst_545:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x55555556, x1, 68, x3)
+
+inst_546:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2d41, 0xb504, 0x4, x1, 72, x3)
+
+inst_547:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xfffe, x1, 76, x3)
+
+inst_548:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xb504, 0x0, x1, 80, x3)
+
+inst_549:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb504, 0xb503, x1, 84, x3)
+
+inst_550:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x66666665, x1, 88, x3)
+
+inst_551:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x33333332, x1, 92, x3)
+
+inst_552:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xaaaaaaa9, x1, 96, x3)
+
+inst_553:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x55555554, x1, 100, x3)
+
+inst_554:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x5a82, 0xb504, 0x2, x1, 104, x3)
+
+inst_555:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xffff, x1, 108, x3)
+
+inst_556:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xb504, 0xb504, x1, 112, x3)
+
+inst_557:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x66666666, x1, 116, x3)
+
+inst_558:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x33333333, x1, 120, x3)
+
+inst_559:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x2434, 0xb504, 0x5, x1, 124, x3)
+
+inst_560:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0xaaaaaaaa, x1, 128, x3)
+
+inst_561:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xb504, 0x55555555, x1, 132, x3)
+
+inst_562:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x3c56, 0xb504, 0x3, x1, 136, x3)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666666, 0x10000, x1, 140, x3)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x66666666, 0x66666666, 0x1, x1, 144, x3)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x90d0, 0x66666666, 0xb505, x1, 148, x3)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666666, 0x66666667, x1, 152, x3)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x33333334, x1, 156, x3)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x66666666, 0x6, x1, 160, x3)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666666, 0xaaaaaaab, x1, 164, x3)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x55555556, x1, 168, x3)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x19999999, 0x66666666, 0x4, x1, 172, x3)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x6667, 0x66666666, 0xfffe, x1, 176, x3)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x66666666, 0x0, x1, 180, x3)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x90d2, 0x66666666, 0xb503, x1, 184, x3)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x66666665, x1, 188, x3)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x66666666, 0x33333332, x1, 192, x3)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666666, 0xaaaaaaa9, x1, 196, x3)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x55555554, x1, 200, x3)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x33333333, 0x66666666, 0x2, x1, 204, x3)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x6666, 0x66666666, 0xffff, x1, 208, x3)
+
+inst_581:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x90d1, 0x66666666, 0xb504, x1, 212, x3)
+
+inst_582:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x66666666, x1, 216, x3)
+
+inst_583:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x66666666, 0x33333333, x1, 220, x3)
+
+inst_584:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x147ae147, 0x66666666, 0x5, x1, 224, x3)
+
+inst_585:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x66666666, 0xaaaaaaaa, x1, 228, x3)
+
+inst_586:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x66666666, 0x55555555, x1, 232, x3)
+
+inst_587:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x22222222, 0x66666666, 0x3, x1, 236, x3)
+
+inst_588:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333333, 0x10000, x1, 240, x3)
+
+inst_589:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x33333333, 0x33333333, 0x1, x1, 244, x3)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333333, 0xb505, x1, 248, x3)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x66666667, x1, 252, x3)
+
+inst_592:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x33333334, x1, 256, x3)
+
+inst_593:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x8888888, 0x33333333, 0x6, x1, 260, x3)
+
+inst_594:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0xaaaaaaab, x1, 264, x3)
+
+inst_595:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x55555556, x1, 268, x3)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0xccccccc, 0x33333333, 0x4, x1, 272, x3)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333333, 0xfffe, x1, 276, x3)
+
+inst_598:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x33333333, 0x0, x1, 280, x3)
+
+inst_599:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x38e38e38, 0xaaaaaaa9, 0x3, x1, 284, x3)
+
+inst_600:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x4869, 0x33333333, 0xb503, x1, 288, x3)
+
+inst_601:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x66666665, x1, 292, x3)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 296, x3)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0xaaaaaaa9, x1, 300, x3)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x55555554, x1, 304, x3)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x19999999, 0x33333333, 0x2, x1, 308, x3)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x3333, 0x33333333, 0xffff, x1, 312, x3)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x4868, 0x33333333, 0xb504, x1, 316, x3)
+
+inst_608:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x66666666, x1, 320, x3)
+
+inst_609:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x33333333, 0x33333333, x1, 324, x3)
+
+inst_610:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x5, x1, 328, x3)
+
+inst_611:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0xaaaaaaaa, x1, 332, x3)
+
+inst_612:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x33333333, 0x55555555, x1, 336, x3)
+
+inst_613:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x33333333, 0x3, x1, 340, x3)
+
+inst_614:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x10000, x1, 344, x3)
+
+inst_615:
+// rs1_val==5 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x5, 0x5, 0x1, x1, 348, x3)
+
+inst_616:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xb505, x1, 352, x3)
+
+inst_617:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x66666667, x1, 356, x3)
+
+inst_618:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x33333334, x1, 360, x3)
+
+inst_619:
+// rs1_val==5 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x6, x1, 364, x3)
+
+inst_620:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xaaaaaaab, x1, 368, x3)
+
+inst_621:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x55555556, x1, 372, x3)
+
+inst_622:
+// rs1_val==5 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x5, 0x4, x1, 376, x3)
+
+inst_623:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xfffe, x1, 380, x3)
+
+inst_624:
+// rs1_val==5 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x5, 0x0, x1, 384, x3)
+
+inst_625:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xb503, x1, 388, x3)
+
+inst_626:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x66666665, x1, 392, x3)
+
+inst_627:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x33333332, x1, 396, x3)
+
+inst_628:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xaaaaaaa9, x1, 400, x3)
+
+inst_629:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x55555554, x1, 404, x3)
+
+inst_630:
+// rs1_val==5 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0x5, 0x2, x1, 408, x3)
+
+inst_631:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xffff, x1, 412, x3)
+
+inst_632:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xb504, x1, 416, x3)
+
+inst_633:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x66666666, x1, 420, x3)
+
+inst_634:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x33333333, x1, 424, x3)
+
+inst_635:
+// rs1_val==5 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x5, 0x5, x1, 428, x3)
+
+inst_636:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0xaaaaaaaa, x1, 432, x3)
+
+inst_637:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x5, 0x55555555, x1, 436, x3)
+
+inst_638:
+// rs1_val==5 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x5, 0x3, x1, 440, x3)
+
+inst_639:
+// rs1_val==2863311530 and rs2_val==65536, rs1_val == 2863311530
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaa, 0xaaaaaaaa, 0x10000, x1, 444, x3)
+
+inst_640:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0xaaaaaaaa, 0xaaaaaaaa, 0x1, x1, 448, x3)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0xf15b, 0xaaaaaaaa, 0xb505, x1, 452, x3)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x66666667, x1, 456, x3)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaaa, 0x33333334, x1, 460, x3)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0xaaaaaaaa, 0x6, x1, 464, x3)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xaaaaaaab, x1, 468, x3)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x55555556, x1, 472, x3)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaaa, 0xaaaaaaaa, 0x4, x1, 476, x3)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0xaaac, 0xaaaaaaaa, 0xfffe, x1, 480, x3)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0xaaaaaaaa, 0x0, x1, 484, x3)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0xf15e, 0xaaaaaaaa, 0xb503, x1, 488, x3)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x66666665, x1, 492, x3)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaaa, 0x33333332, x1, 496, x3)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0xaaaaaaa9, x1, 500, x3)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x55555554, x1, 504, x3)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x55555555, 0xaaaaaaaa, 0x2, x1, 508, x3)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0xaaab, 0xaaaaaaaa, 0xffff, x1, 512, x3)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0xf15d, 0xaaaaaaaa, 0xb504, x1, 516, x3)
+
+inst_658:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x66666666, x1, 520, x3)
+
+inst_659:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0xaaaaaaaa, 0x33333333, x1, 524, x3)
+
+inst_660:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x22222222, 0xaaaaaaaa, 0x5, x1, 528, x3)
+
+inst_661:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0xaaaaaaaa, x1, 532, x3)
+
+inst_662:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x55555555, x1, 536, x3)
+
+inst_663:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x38e38e38, 0xaaaaaaaa, 0x3, x1, 540, x3)
+
+inst_664:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555555, 0x10000, x1, 544, x3)
+
+inst_665:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x55555555, 0x55555555, 0x1, x1, 548, x3)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x78ad, 0x55555555, 0xb505, x1, 552, x3)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0x66666667, x1, 556, x3)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555555, 0x33333334, x1, 560, x3)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0xe38e38e, 0x55555555, 0x6, x1, 564, x3)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0xaaaaaaab, x1, 568, x3)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0x55555556, x1, 572, x3)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x15555555, 0x55555555, 0x4, x1, 576, x3)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x5556, 0x55555555, 0xfffe, x1, 580, x3)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x55555555, 0x0, x1, 584, x3)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x78af, 0x55555555, 0xb503, x1, 588, x3)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0x66666665, x1, 592, x3)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555555, 0x33333332, x1, 596, x3)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0xaaaaaaa9, x1, 600, x3)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 604, x3)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x2aaaaaaa, 0x55555555, 0x2, x1, 608, x3)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555555, 0xffff, x1, 612, x3)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x78ae, 0x55555555, 0xb504, x1, 616, x3)
+
+inst_683:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0x66666666, x1, 620, x3)
+
+inst_684:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555555, 0x33333333, x1, 624, x3)
+
+inst_685:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x11111111, 0x55555555, 0x5, x1, 628, x3)
+
+inst_686:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555555, 0xaaaaaaaa, x1, 632, x3)
+
+inst_687:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555555, 0x55555555, x1, 636, x3)
+
+inst_688:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x3, x1, 640, x3)
+
+inst_689:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x10000, x1, 644, x3)
+
+inst_690:
+// rs1_val==3 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x3, 0x3, 0x1, x1, 648, x3)
+
+inst_691:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xb505, x1, 652, x3)
+
+inst_692:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x66666667, x1, 656, x3)
+
+inst_693:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x33333334, x1, 660, x3)
+
+inst_694:
+// rs1_val==3 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x6, x1, 664, x3)
+
+inst_695:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xaaaaaaab, x1, 668, x3)
+
+inst_696:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x55555556, x1, 672, x3)
+
+inst_697:
+// rs1_val==3 and rs2_val==4, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x4, x1, 676, x3)
+
+inst_698:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xfffe
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xfffe, x1, 680, x3)
+
+inst_699:
+// rs1_val==3 and rs2_val==0, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(divu, x12, x10, x11, 0xFFFFFFFF, 0x3, 0x0, x1, 684, x3)
+
+inst_700:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xb503, x1, 688, x3)
+
+inst_701:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x66666665, x1, 692, x3)
+
+inst_702:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x33333332, x1, 696, x3)
+
+inst_703:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaa9
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xaaaaaaa9, x1, 700, x3)
+
+inst_704:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x55555554, x1, 704, x3)
+
+inst_705:
+// rs1_val==3 and rs2_val==2, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x3, 0x2, x1, 708, x3)
+
+inst_706:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xffff, x1, 712, x3)
+
+inst_707:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xb504, x1, 716, x3)
+
+inst_708:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x66666666, x1, 720, x3)
+
+inst_709:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x33333333, x1, 724, x3)
+
+inst_710:
+// rs1_val==3 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x5, x1, 728, x3)
+
+inst_711:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0xaaaaaaaa, x1, 732, x3)
+
+inst_712:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x3, 0x55555555, x1, 736, x3)
+
+inst_713:
+// rs1_val==3 and rs2_val==3, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x3, 0x3, x1, 740, x3)
+
+inst_714:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x5
+TEST_RR_OP(divu, x12, x10, x11, 0x22222221, 0xaaaaaaa9, 0x5, x1, 744, x3)
+
+inst_715:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaaa
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xaaaaaaaa, x1, 748, x3)
+
+inst_716:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555555
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x55555555, x1, 752, x3)
+
+inst_717:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x10000
+TEST_RR_OP(divu, x12, x10, x11, 0x5555, 0x55555554, 0x10000, x1, 756, x3)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(divu, x12, x10, x11, 0x55555554, 0x55555554, 0x1, x1, 760, x3)
+
+inst_719:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(divu, x12, x10, x11, 0x78ad, 0x55555554, 0xb505, x1, 764, x3)
+
+inst_720:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0x66666667, x1, 768, x3)
+
+inst_721:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0x55555554, 0x33333334, x1, 772, x3)
+
+inst_722:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(divu, x12, x10, x11, 0xe38e38e, 0x55555554, 0x6, x1, 776, x3)
+
+inst_723:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaab
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0xaaaaaaab, x1, 780, x3)
+
+inst_724:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x55555554, 0x55555556, x1, 784, x3)
+
+inst_725:
+// rs2_val == 3221225471, rs1_val == 4294836223
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffff;  op2val:0xbfffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xfffdffff, 0xbfffffff, x1, 788, x3)
+
+inst_726:
+// rs2_val == 3758096383, rs1_val == 4294967263
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0xdfffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffffffdf, 0xdfffffff, x1, 792, x3)
+
+inst_727:
+// rs2_val == 4160749567, rs1_val == 1048576
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0xf7ffffff
+TEST_RR_OP(divu, x12, x10, x11, 0x0, 0x100000, 0xf7ffffff, x1, 796, x3)
+
+inst_728:
+// rs2_val == 4294836223, rs1_val == 4294967231
+// opcode: divu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0xfffdffff
+TEST_RR_OP(divu, x12, x10, x11, 0x1, 0xffffffbf, 0xfffdffff, x1, 800, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x9_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_3:
+    .fill 201*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mul-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mul-01.S
new file mode 100644
index 000000000..8177ccfe9
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mul-01.S
@@ -0,0 +1,3010 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the mul instruction of the RISC-V M extension for the mul covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",mul)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x6, rs2==x10, rd==x10, rs1_val != rs2_val, rs1_val==6 and rs2_val==-1431655765, rs1_val > 0 and rs2_val < 0
+// opcode: mul ; op1:x6; op2:x10; dest:x10; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(mul, x10, x6, x10, 0x2, 0x6, -0x55555555, x2, 0, x11)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x7, rs2==x1, rd==x7, rs2_val == 2147483647, rs1_val == 1431655765, rs2_val == (2**(xlen-1)-1), rs1_val > 0 and rs2_val > 0
+// opcode: mul ; op1:x7; op2:x1; dest:x7; op1val:0x55555555;  op2val:0x7fffffff
+TEST_RR_OP(mul, x7, x7, x1, 0x2aaaaaab, 0x55555555, 0x7fffffff, x2, 4, x11)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14, rs2_val == -1073741825, rs1_val == 134217728
+// opcode: mul ; op1:x14; op2:x14; dest:x14; op1val:0x8000000;  op2val:0x8000000
+TEST_RR_OP(mul, x14, x14, x14, 0x0, 0x8000000, 0x8000000, x2, 8, x11)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x15, rs2==x15, rd==x1, rs2_val == -536870913, rs1_val == 8
+// opcode: mul ; op1:x15; op2:x15; dest:x1; op1val:0x8;  op2val:0x8
+TEST_RR_OP(mul, x1, x15, x15, 0x40, 0x8, 0x8, x2, 12, x11)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x3, rs2==x9, rd==x4, rs2_val == -268435457, rs1_val == -257, rs1_val < 0 and rs2_val < 0
+// opcode: mul ; op1:x3; op2:x9; dest:x4; op1val:-0x101;  op2val:-0x10000001
+TEST_RR_OP(mul, x4, x3, x9, 0x10000101, -0x101, -0x10000001, x2, 16, x11)
+
+inst_5:
+// rs1==x5, rs2==x0, rd==x8, rs2_val == -134217729, rs1_val == 4
+// opcode: mul ; op1:x5; op2:x0; dest:x8; op1val:0x4;  op2val:0x0
+TEST_RR_OP(mul, x8, x5, x0, 0x0, 0x4, 0x0, x2, 20, x11)
+
+inst_6:
+// rs1==x12, rs2==x13, rd==x15, rs2_val == -67108865, rs1_val == -524289
+// opcode: mul ; op1:x12; op2:x13; dest:x15; op1val:-0x80001;  op2val:-0x4000001
+TEST_RR_OP(mul, x15, x12, x13, 0x4080001, -0x80001, -0x4000001, x2, 24, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_7:
+// rs1==x9, rs2==x4, rd==x11, rs2_val == -33554433, 
+// opcode: mul ; op1:x9; op2:x4; dest:x11; op1val:0x9;  op2val:-0x2000001
+TEST_RR_OP(mul, x11, x9, x4, 0xedfffff7, 0x9, -0x2000001, x1, 0, x3)
+
+inst_8:
+// rs1==x10, rs2==x5, rd==x6, rs2_val == -16777217, rs1_val == 0
+// opcode: mul ; op1:x10; op2:x5; dest:x6; op1val:0x0;  op2val:-0x1000001
+TEST_RR_OP(mul, x6, x10, x5, 0x0, 0x0, -0x1000001, x1, 4, x3)
+
+inst_9:
+// rs1==x13, rs2==x8, rd==x0, rs2_val == -8388609, 
+// opcode: mul ; op1:x13; op2:x8; dest:x0; op1val:0x9;  op2val:-0x800001
+TEST_RR_OP(mul, x0, x13, x8, 0, 0x9, -0x800001, x1, 8, x3)
+
+inst_10:
+// rs1==x0, rs2==x6, rd==x5, rs2_val == -4194305, rs1_val == 32
+// opcode: mul ; op1:x0; op2:x6; dest:x5; op1val:0x0;  op2val:-0x400001
+TEST_RR_OP(mul, x5, x0, x6, 0x0, 0x0, -0x400001, x1, 12, x10)
+
+inst_11:
+// rs1==x8, rs2==x2, rd==x13, rs2_val == -2097153, 
+// opcode: mul ; op1:x8; op2:x2; dest:x13; op1val:0x33333333;  op2val:-0x200001
+TEST_RR_OP(mul, x13, x8, x2, 0x666ccccd, 0x33333333, -0x200001, x1, 16, x10)
+
+inst_12:
+// rs1==x4, rs2==x11, rd==x3, rs2_val == -1048577, 
+// opcode: mul ; op1:x4; op2:x11; dest:x3; op1val:0x0;  op2val:-0x100001
+TEST_RR_OP(mul, x3, x4, x11, 0x0, 0x0, -0x100001, x1, 20, x10)
+
+inst_13:
+// rs1==x2, rs2==x3, rd==x9, rs2_val == -524289, rs1_val == -16777217
+// opcode: mul ; op1:x2; op2:x3; dest:x9; op1val:-0x1000001;  op2val:-0x80001
+TEST_RR_OP(mul, x9, x2, x3, 0x1080001, -0x1000001, -0x80001, x1, 24, x10)
+
+inst_14:
+// rs1==x11, rs2==x7, rd==x12, rs2_val == -262145, 
+// opcode: mul ; op1:x11; op2:x7; dest:x12; op1val:0x66666666;  op2val:-0x40001
+TEST_RR_OP(mul, x12, x11, x7, 0x1999a, 0x66666666, -0x40001, x1, 28, x10)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_15:
+// rs1==x1, rs2==x12, rd==x2, rs2_val == -131073, rs1_val == 128
+// opcode: mul ; op1:x1; op2:x12; dest:x2; op1val:0x80;  op2val:-0x20001
+TEST_RR_OP(mul, x2, x1, x12, 0xfeffff80, 0x80, -0x20001, x3, 0, x4)
+
+inst_16:
+// rs2_val == -65537, rs1_val == -1431655766
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x10001
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab5556, -0x55555556, -0x10001, x3, 4, x4)
+
+inst_17:
+// rs2_val == -32769, rs1_val == -1048577
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:-0x8001
+TEST_RR_OP(mul, x12, x10, x11, 0x108001, -0x100001, -0x8001, x3, 8, x4)
+
+inst_18:
+// rs2_val == -16385, rs1_val == 16
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:-0x4001
+TEST_RR_OP(mul, x12, x10, x11, 0xfffbfff0, 0x10, -0x4001, x3, 12, x4)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -134217729
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x2001
+TEST_RR_OP(mul, x12, x10, x11, 0x8002001, -0x8000001, -0x2001, x3, 16, x4)
+
+inst_20:
+// rs2_val == -4097, rs1_val == -33554433
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:-0x1001
+TEST_RR_OP(mul, x12, x10, x11, 0x2001001, -0x2000001, -0x1001, x3, 20, x4)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:-0x801
+TEST_RR_OP(mul, x12, x10, x11, 0xffffc7f9, 0x7, -0x801, x3, 24, x4)
+
+inst_22:
+// rs2_val == -1025, rs1_val == 268435456
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:-0x401
+TEST_RR_OP(mul, x12, x10, x11, 0xf0000000, 0x10000000, -0x401, x3, 28, x4)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x201
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccb99, 0x66666667, -0x201, x3, 32, x4)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x4;  op2val:-0x101
+TEST_RR_OP(mul, x12, x10, x11, 0x404, -0x4, -0x101, x3, 36, x4)
+
+inst_25:
+// rs2_val == -129, rs1_val == 32768
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:-0x81
+TEST_RR_OP(mul, x12, x10, x11, 0xffbf8000, 0x8000, -0x81, x3, 40, x4)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:-0x41
+TEST_RR_OP(mul, x12, x10, x11, 0x4100041, -0x100001, -0x41, x3, 44, x4)
+
+inst_27:
+// rs2_val == -33, rs1_val == 536870912
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:-0x21
+TEST_RR_OP(mul, x12, x10, x11, 0xe0000000, 0x20000000, -0x21, x3, 48, x4)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x11
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa5, -0x55555555, -0x11, x3, 52, x4)
+
+inst_29:
+// rs2_val == -9, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x9
+TEST_RR_OP(mul, x12, x10, x11, 0x80000009, 0x7fffffff, -0x9, x3, 56, x4)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffe2, 0x6, -0x5, x3, 60, x4)
+
+inst_31:
+// rs2_val == -3, rs1_val == -17
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:-0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x33, -0x11, -0x3, x3, 64, x4)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, -0x2, x3, 68, x4)
+
+inst_33:
+// rs1_val == -1073741825, rs1_val < 0 and rs2_val > 0, rs2_val == 262144
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x40000
+TEST_RR_OP(mul, x12, x10, x11, 0xfffc0000, -0x40000001, 0x40000, x3, 72, x4)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x5ffffffb, -0x20000001, 0x5, x3, 76, x4)
+
+inst_35:
+// rs1_val == -268435457, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x4aaaaaaa, -0x10000001, 0x55555556, x3, 80, x4)
+
+inst_36:
+// rs1_val == -67108865, rs2_val == 65536
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x10000
+TEST_RR_OP(mul, x12, x10, x11, 0xffff0000, -0x4000001, 0x10000, x3, 84, x4)
+
+inst_37:
+// rs1_val == -8388609, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:0x3fffffff
+TEST_RR_OP(mul, x12, x10, x11, 0xc0800001, -0x800001, 0x3fffffff, x3, 88, x4)
+
+inst_38:
+// rs1_val == -4194305, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xffcccccc, -0x400001, 0x33333334, x3, 92, x4)
+
+inst_39:
+// rs1_val == -2097153, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x20001
+TEST_RR_OP(mul, x12, x10, x11, 0x220001, -0x200001, -0x20001, x3, 96, x4)
+
+inst_40:
+// rs1_val == -262145, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:-0x4001
+TEST_RR_OP(mul, x12, x10, x11, 0x44001, -0x40001, -0x4001, x3, 100, x4)
+
+inst_41:
+// rs1_val == -131073, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:-0x80001
+TEST_RR_OP(mul, x12, x10, x11, 0xa0001, -0x20001, -0x80001, x3, 104, x4)
+
+inst_42:
+// rs1_val == -65537, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x1001
+TEST_RR_OP(mul, x12, x10, x11, 0x10011001, -0x10001, -0x1001, x3, 108, x4)
+
+inst_43:
+// rs1_val == -32769, rs2_val == 131072
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x20000
+TEST_RR_OP(mul, x12, x10, x11, 0xfffe0000, -0x8001, 0x20000, x3, 112, x4)
+
+inst_44:
+// rs1_val == -16385, rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x80000000
+TEST_RR_OP(mul, x12, x10, x11, 0x80000000, -0x4001, -0x80000000, x3, 116, x4)
+
+inst_45:
+// rs1_val == -8193, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x200001
+TEST_RR_OP(mul, x12, x10, x11, 0x202001, -0x2001, -0x200001, x3, 120, x4)
+
+inst_46:
+// rs1_val == -4097, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:-0x1
+TEST_RR_OP(mul, x12, x10, x11, 0x1001, -0x1001, -0x1, x3, 124, x4)
+
+inst_47:
+// rs1_val == -2049, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xaac, -0x801, 0x55555554, x3, 128, x4)
+
+inst_48:
+// rs1_val == -1025, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffccc, -0x401, 0x33333334, x3, 132, x4)
+
+inst_49:
+// rs1_val == -513, rs2_val == 2
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffbfe, -0x201, 0x2, x3, 136, x4)
+
+inst_50:
+// rs1_val == -129, rs2_val == 1024
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x400
+TEST_RR_OP(mul, x12, x10, x11, 0xfffdfc00, -0x81, 0x400, x3, 140, x4)
+
+inst_51:
+// rs1_val == -65, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffd209fc, -0x41, 0xb504, x3, 144, x4)
+
+inst_52:
+// rs1_val == -33, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xa5, -0x21, -0x5, x3, 148, x4)
+
+inst_53:
+// rs1_val == -9, rs2_val == 8
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x8
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffb8, -0x9, 0x8, x3, 152, x4)
+
+inst_54:
+// rs1_val == -5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff1, -0x5, 0x3, x3, 156, x4)
+
+inst_55:
+// rs1_val == -3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x8
+TEST_RR_OP(mul, x12, x10, x11, 0x18, -0x3, -0x8, x3, 160, x4)
+
+inst_56:
+// rs1_val == -2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x8
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff0, -0x2, 0x8, x3, 164, x4)
+
+inst_57:
+// rs2_val == 1073741824, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x40000000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x33333334, 0x40000000, x3, 168, x4)
+
+inst_58:
+// rs2_val == 536870912, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x20000000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x10, 0x20000000, x3, 172, x4)
+
+inst_59:
+// rs2_val == 268435456, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x10000000
+TEST_RR_OP(mul, x12, x10, x11, 0xf0000000, -0x4001, 0x10000000, x3, 176, x4)
+
+inst_60:
+// rs2_val == 134217728, rs1_val == 1048576
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x8000000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x100000, 0x8000000, x3, 180, x4)
+
+inst_61:
+// rs2_val == 67108864, rs1_val == 256
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x4000000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x100, 0x4000000, x3, 184, x4)
+
+inst_62:
+// rs2_val == 33554432, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:0x2000000
+TEST_RR_OP(mul, x12, x10, x11, 0xec000000, -0xa, 0x2000000, x3, 188, x4)
+
+inst_63:
+// rs2_val == 16777216, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x1000000
+TEST_RR_OP(mul, x12, x10, x11, 0xff000000, -0x40001, 0x1000000, x3, 192, x4)
+
+inst_64:
+// rs2_val == 8388608, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x800000
+TEST_RR_OP(mul, x12, x10, x11, 0x99800000, 0x33333333, 0x800000, x3, 196, x4)
+
+inst_65:
+// rs2_val == 4194304, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x400000
+TEST_RR_OP(mul, x12, x10, x11, 0x1800000, 0x6, 0x400000, x3, 200, x4)
+
+inst_66:
+// rs2_val == 2097152, rs1_val == 4096
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x200000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x1000, 0x200000, x3, 204, x4)
+
+inst_67:
+// rs2_val == 1048576, rs1_val == 16777216
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x100000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x1000000, 0x100000, x3, 208, x4)
+
+inst_68:
+// rs2_val == 524288, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x80000
+TEST_RR_OP(mul, x12, x10, x11, 0xfff80000, -0x40000001, 0x80000, x3, 212, x4)
+
+inst_69:
+// rs2_val == 32768, rs1_val == 1024
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x8000
+TEST_RR_OP(mul, x12, x10, x11, 0x2000000, 0x400, 0x8000, x3, 216, x4)
+
+inst_70:
+// rs2_val == 16384, rs1_val == 524288
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x4000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x80000, 0x4000, x3, 220, x4)
+
+inst_71:
+// rs2_val == 8192, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x2000
+TEST_RR_OP(mul, x12, x10, x11, 0x20000, 0x10, 0x2000, x3, 224, x4)
+
+inst_72:
+// rs2_val == 4096, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x1000
+TEST_RR_OP(mul, x12, x10, x11, 0xfffff000, 0x7fffffff, 0x1000, x3, 228, x4)
+
+inst_73:
+// rs2_val == 2048, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x800
+TEST_RR_OP(mul, x12, x10, x11, 0xfa57e000, -0xb504, 0x800, x3, 232, x4)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x200
+TEST_RR_OP(mul, x12, x10, x11, 0xa00, 0x5, 0x200, x3, 236, x4)
+
+inst_75:
+// rs2_val == 256, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:0x100
+TEST_RR_OP(mul, x12, x10, x11, 0xfffff600, -0xa, 0x100, x3, 240, x4)
+
+inst_76:
+// rs2_val == 128, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x80
+TEST_RR_OP(mul, x12, x10, x11, 0x20000, 0x400, 0x80, x3, 244, x4)
+
+inst_77:
+// rs2_val == 64, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x40
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x40, x3, 248, x4)
+
+inst_78:
+// rs2_val == 32, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x20
+TEST_RR_OP(mul, x12, x10, x11, 0xc0, 0x6, 0x20, x3, 252, x4)
+
+inst_79:
+// rs2_val == 16, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10
+TEST_RR_OP(mul, x12, x10, x11, 0x40, 0x4, 0x10, x3, 256, x4)
+
+inst_80:
+// rs2_val == 4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x4000000, 0x1000000, 0x4, x3, 260, x4)
+
+inst_81:
+// rs2_val == 1, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x1
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffb, -0x5, 0x1, x3, 264, x4)
+
+inst_82:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x9
+TEST_RR_OP(mul, x12, x10, x11, 0x80000000, -0x80000000, 0x9, x3, 268, x4)
+
+inst_83:
+// rs1_val == 1073741824, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x100000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x40000000, 0x100000, x3, 272, x4)
+
+inst_84:
+// rs1_val == 67108864, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:-0x101
+TEST_RR_OP(mul, x12, x10, x11, 0xfc000000, 0x4000000, -0x101, x3, 276, x4)
+
+inst_85:
+// rs1_val == 33554432, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x6000000, 0x2000000, 0x3, x3, 280, x4)
+
+inst_86:
+// rs1_val == 8388608, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:-0x20001
+TEST_RR_OP(mul, x12, x10, x11, 0xff800000, 0x800000, -0x20001, x3, 284, x4)
+
+inst_87:
+// rs1_val == 4194304, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:-0x8000001
+TEST_RR_OP(mul, x12, x10, x11, 0xffc00000, 0x400000, -0x8000001, x3, 288, x4)
+
+inst_88:
+// rs1_val == 2097152, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x2000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x200000, 0x2000, x3, 292, x4)
+
+inst_89:
+// rs1_val == 262144, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x140000, 0x40000, 0x5, x3, 296, x4)
+
+inst_90:
+// rs1_val == 131072, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x6a080000, 0x20000, 0xb504, x3, 300, x4)
+
+inst_91:
+// rs1_val == 65536, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10
+TEST_RR_OP(mul, x12, x10, x11, 0x100000, 0x10000, 0x10, x3, 304, x4)
+
+inst_92:
+// rs1_val == 16384, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x2000
+TEST_RR_OP(mul, x12, x10, x11, 0x8000000, 0x4000, 0x2000, x3, 308, x4)
+
+inst_93:
+// rs1_val == 8192, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x80
+TEST_RR_OP(mul, x12, x10, x11, 0x100000, 0x2000, 0x80, x3, 312, x4)
+
+inst_94:
+// rs1_val == 2048, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x2000000
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x800, 0x2000000, x3, 316, x4)
+
+inst_95:
+// rs1_val == 512, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x7
+TEST_RR_OP(mul, x12, x10, x11, 0xfffff200, 0x200, -0x7, x3, 320, x4)
+
+inst_96:
+// rs1_val == 64, rs2_val == 1431655765
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x55555540, 0x40, 0x55555555, x3, 324, x4)
+
+inst_97:
+// rs1_val == 2, rs1_val==2 and rs2_val==6
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xc, 0x2, 0x6, x3, 328, x4)
+
+inst_98:
+// rs1_val == 1, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x21
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffdf, 0x1, -0x21, x3, 332, x4)
+
+inst_99:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x80001219, 0xb505, 0xb505, x3, 336, x4)
+
+inst_100:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x800157f1, 0xb505, -0xb503, x3, 340, x4)
+
+inst_101:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x6666d303, 0xb505, 0x66666667, x3, 344, x4)
+
+inst_102:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x3333c404, 0xb505, 0x33333334, x3, 348, x4)
+
+inst_103:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x43e1e, 0xb505, 0x6, x3, 352, x4)
+
+inst_104:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x3c57, 0xb505, -0x55555555, x3, 356, x4)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x78ae, 0xb505, 0x55555556, x3, 360, x4)
+
+inst_106:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x2d414, 0xb505, 0x4, x3, 364, x4)
+
+inst_107:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffea80f, 0xb505, 0xb503, x3, 368, x4)
+
+inst_108:
+// rs1_val==46341 and rs2_val==0, rs2_val == 0
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0xb505, 0x0, x3, 372, x4)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x666568f9, 0xb505, 0x66666665, x3, 376, x4)
+
+inst_110:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x333259fa, 0xb505, 0x33333332, x3, 380, x4)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xffff0ea4, 0xb505, 0x55555554, x3, 384, x4)
+
+inst_112:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x16a0a, 0xb505, 0x2, x3, 388, x4)
+
+inst_113:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x7fff5d14, 0xb505, 0xb504, x3, 392, x4)
+
+inst_114:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x8000a2ec, 0xb505, -0xb504, x3, 396, x4)
+
+inst_115:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x66661dfe, 0xb505, 0x66666666, x3, 400, x4)
+
+inst_116:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x33330eff, 0xb505, 0x33333333, x3, 404, x4)
+
+inst_117:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x38919, 0xb505, 0x5, x3, 408, x4)
+
+inst_118:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xffff8752, 0xb505, -0x55555556, x3, 412, x4)
+
+inst_119:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xffffc3a9, 0xb505, 0x55555555, x3, 416, x4)
+
+inst_120:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x21f0f, 0xb505, 0x3, x3, 420, x4)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x800157f1, -0xb503, 0xb505, x3, 424, x4)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffd3e09, -0xb503, -0xb503, x3, 428, x4)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x6665f9cb, -0xb503, 0x66666667, x3, 432, x4)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x3332a264, -0xb503, 0x33333334, x3, 436, x4)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xfffbc1ee, -0xb503, 0x6, x3, 440, x4)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x555518ff, -0xb503, -0x55555555, x3, 444, x4)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa31fe, -0xb503, 0x55555556, x3, 448, x4)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xfffd2bf4, -0xb503, 0x4, x3, 452, x4)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x8002c1f7, -0xb503, 0xb503, x3, 456, x4)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, -0xb503, 0x0, x3, 460, x4)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x666763d1, -0xb503, 0x66666665, x3, 464, x4)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x33340c6a, -0xb503, 0x33333332, x3, 468, x4)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab9c04, -0xb503, 0x55555554, x3, 472, x4)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xfffe95fa, -0xb503, 0x2, x3, 476, x4)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x80020cf4, -0xb503, 0xb504, x3, 480, x4)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffdf30c, -0xb503, -0xb504, x3, 484, x4)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x6666aece, -0xb503, 0x66666666, x3, 488, x4)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x33335767, -0xb503, 0x33333333, x3, 492, x4)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xfffc76f1, -0xb503, 0x5, x3, 496, x4)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x5555ce02, -0xb503, -0x55555556, x3, 500, x4)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaae701, -0xb503, 0x55555555, x3, 504, x4)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xfffde0f7, -0xb503, 0x3, x3, 508, x4)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x6666d303, 0x66666667, 0xb505, x3, 512, x4)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x6665f9cb, 0x66666667, -0xb503, x3, 516, x4)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xd70a3d71, 0x66666667, 0x66666667, x3, 520, x4)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x1eb851ec, 0x66666667, 0x33333334, x3, 524, x4)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x6666666a, 0x66666667, 0x6, x3, 528, x4)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccd, 0x66666667, -0x55555555, x3, 532, x4)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999a, 0x66666667, 0x55555556, x3, 536, x4)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999c, 0x66666667, 0x4, x3, 540, x4)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x999a0635, 0x66666667, 0xb503, x3, 544, x4)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x66666667, 0x0, x3, 548, x4)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xa3d70a3, 0x66666667, 0x66666665, x3, 552, x4)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x51eb851e, 0x66666667, 0x33333332, x3, 556, x4)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x66666667, 0x55555554, x3, 560, x4)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccce, 0x66666667, 0x2, x3, 564, x4)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x6c9c, 0x66666667, 0xb504, x3, 568, x4)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffff9364, 0x66666667, -0xb504, x3, 572, x4)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x70a3d70a, 0x66666667, 0x66666666, x3, 576, x4)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xb851eb85, 0x66666667, 0x33333333, x3, 580, x4)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x3, 0x66666667, 0x5, x3, 584, x4)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, 0x66666667, -0x55555556, x3, 588, x4)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x33333333, 0x66666667, 0x55555555, x3, 592, x4)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x33333335, 0x66666667, 0x3, x3, 596, x4)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x3333c404, 0x33333334, 0xb505, x3, 600, x4)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x3332a264, 0x33333334, -0xb503, x3, 604, x4)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x1eb851ec, 0x33333334, 0x66666667, x3, 608, x4)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x28f5c290, 0x33333334, 0x33333334, x3, 612, x4)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x33333338, 0x33333334, 0x6, x3, 616, x4)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, 0x33333334, -0x55555555, x3, 620, x4)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x77777778, 0x33333334, 0x55555556, x3, 624, x4)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccd0, 0x33333334, 0x4, x3, 628, x4)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xcccd5d9c, 0x33333334, 0xb503, x3, 632, x4)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x33333334, 0x0, x3, 636, x4)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xb851eb84, 0x33333334, 0x66666665, x3, 640, x4)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xc28f5c28, 0x33333334, 0x33333332, x3, 644, x4)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x11111110, 0x33333334, 0x55555554, x3, 648, x4)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x66666668, 0x33333334, 0x2, x3, 652, x4)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x90d0, 0x33333334, 0xb504, x3, 656, x4)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffff6f30, 0x33333334, -0xb504, x3, 660, x4)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xeb851eb8, 0x33333334, 0x66666666, x3, 664, x4)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xf5c28f5c, 0x33333334, 0x33333333, x3, 668, x4)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x4, 0x33333334, 0x5, x3, 672, x4)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x88888888, 0x33333334, -0x55555556, x3, 676, x4)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x44444444, 0x33333334, 0x55555555, x3, 680, x4)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999c, 0x33333334, 0x3, x3, 684, x4)
+
+inst_187:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x43e1e, 0x6, 0xb505, x3, 688, x4)
+
+inst_188:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xfffbc1ee, 0x6, -0xb503, x3, 692, x4)
+
+inst_189:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x6666666a, 0x6, 0x66666667, x3, 696, x4)
+
+inst_190:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x33333338, 0x6, 0x33333334, x3, 700, x4)
+
+inst_191:
+// rs1_val==6 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x24, 0x6, 0x6, x3, 704, x4)
+
+inst_192:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x4, 0x6, 0x55555556, x3, 708, x4)
+
+inst_193:
+// rs1_val==6 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x18, 0x6, 0x4, x3, 712, x4)
+
+inst_194:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x43e12, 0x6, 0xb503, x3, 716, x4)
+
+inst_195:
+// rs1_val==6 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x6, 0x0, x3, 720, x4)
+
+inst_196:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x6666665e, 0x6, 0x66666665, x3, 724, x4)
+
+inst_197:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x3333332c, 0x6, 0x33333332, x3, 728, x4)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff8, 0x6, 0x55555554, x3, 732, x4)
+
+inst_199:
+// rs1_val==6 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xc, 0x6, 0x2, x3, 736, x4)
+
+inst_200:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x43e18, 0x6, 0xb504, x3, 740, x4)
+
+inst_201:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfffbc1e8, 0x6, -0xb504, x3, 744, x4)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x66666664, 0x6, 0x66666666, x3, 748, x4)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x33333332, 0x6, 0x33333333, x3, 752, x4)
+
+inst_204:
+// rs1_val==6 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x1e, 0x6, 0x5, x3, 756, x4)
+
+inst_205:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffc, 0x6, -0x55555556, x3, 760, x4)
+
+inst_206:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, 0x6, 0x55555555, x3, 764, x4)
+
+inst_207:
+// rs1_val==6 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x12, 0x6, 0x3, x3, 768, x4)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x3c57, -0x55555555, 0xb505, x3, 772, x4)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x555518ff, -0x55555555, -0xb503, x3, 776, x4)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccd, -0x55555555, 0x66666667, x3, 780, x4)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, -0x55555555, 0x33333334, x3, 784, x4)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x2, -0x55555555, 0x6, x3, 788, x4)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x38e38e39, -0x55555555, -0x55555555, x3, 792, x4)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x71c71c72, -0x55555555, 0x55555556, x3, 796, x4)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaac, -0x55555555, 0x4, x3, 800, x4)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaae701, -0x55555555, 0xb503, x3, 804, x4)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, -0x55555555, 0x0, x3, 808, x4)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x77777777, -0x55555555, 0x66666665, x3, 812, x4)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, -0x55555555, 0x33333332, x3, 816, x4)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x1c71c71c, -0x55555555, 0x55555554, x3, 820, x4)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x55555556, -0x55555555, 0x2, x3, 824, x4)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x555591ac, -0x55555555, 0xb504, x3, 828, x4)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa6e54, -0x55555555, -0xb504, x3, 832, x4)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x22222222, -0x55555555, 0x66666666, x3, 836, x4)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x11111111, -0x55555555, 0x33333333, x3, 840, x4)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x55555557, -0x55555555, 0x5, x3, 844, x4)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x8e38e38e, -0x55555555, -0x55555556, x3, 848, x4)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xc71c71c7, -0x55555555, 0x55555555, x3, 852, x4)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x1, -0x55555555, 0x3, x3, 856, x4)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x78ae, 0x55555556, 0xb505, x3, 860, x4)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa31fe, 0x55555556, -0xb503, x3, 864, x4)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999a, 0x55555556, 0x66666667, x3, 868, x4)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x77777778, 0x55555556, 0x33333334, x3, 872, x4)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x4, 0x55555556, 0x6, x3, 876, x4)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x71c71c72, 0x55555556, -0x55555555, x3, 880, x4)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xe38e38e4, 0x55555556, 0x55555556, x3, 884, x4)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x55555558, 0x55555556, 0x4, x3, 888, x4)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x5555ce02, 0x55555556, 0xb503, x3, 892, x4)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x55555556, 0x0, x3, 896, x4)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xeeeeeeee, 0x55555556, 0x66666665, x3, 900, x4)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x55555556, 0x33333332, x3, 904, x4)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x38e38e38, 0x55555556, 0x55555554, x3, 908, x4)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaac, 0x55555556, 0x2, x3, 912, x4)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab2358, 0x55555556, 0xb504, x3, 916, x4)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x5554dca8, 0x55555556, -0xb504, x3, 920, x4)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x44444444, 0x55555556, 0x66666666, x3, 924, x4)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x22222222, 0x55555556, 0x33333333, x3, 928, x4)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaae, 0x55555556, 0x5, x3, 932, x4)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x1c71c71c, 0x55555556, -0x55555556, x3, 936, x4)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x8e38e38e, 0x55555556, 0x55555555, x3, 940, x4)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x2, 0x55555556, 0x3, x3, 944, x4)
+
+inst_252:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x2d414, 0x4, 0xb505, x3, 948, x4)
+
+inst_253:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xfffd2bf4, 0x4, -0xb503, x3, 952, x4)
+
+inst_254:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999c, 0x4, 0x66666667, x3, 956, x4)
+
+inst_255:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccd0, 0x4, 0x33333334, x3, 960, x4)
+
+inst_256:
+// rs1_val==4 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x18, 0x4, 0x6, x3, 964, x4)
+
+inst_257:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaac, 0x4, -0x55555555, x3, 968, x4)
+
+inst_258:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x55555558, 0x4, 0x55555556, x3, 972, x4)
+
+inst_259:
+// rs1_val==4 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x10, 0x4, 0x4, x3, 976, x4)
+
+inst_260:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x2d40c, 0x4, 0xb503, x3, 980, x4)
+
+inst_261:
+// rs1_val==4 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x4, 0x0, x3, 984, x4)
+
+inst_262:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x99999994, 0x4, 0x66666665, x3, 988, x4)
+
+inst_263:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccc8, 0x4, 0x33333332, x3, 992, x4)
+
+inst_264:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x55555550, 0x4, 0x55555554, x3, 996, x4)
+
+inst_265:
+// rs1_val==4 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x8, 0x4, 0x2, x3, 1000, x4)
+
+inst_266:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x2d410, 0x4, 0xb504, x3, 1004, x4)
+
+inst_267:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfffd2bf0, 0x4, -0xb504, x3, 1008, x4)
+
+inst_268:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x99999998, 0x4, 0x66666666, x3, 1012, x4)
+
+inst_269:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x4, 0x33333333, x3, 1016, x4)
+
+inst_270:
+// rs1_val==4 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x14, 0x4, 0x5, x3, 1020, x4)
+
+inst_271:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa8, 0x4, -0x55555556, x3, 1024, x4)
+
+inst_272:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x55555554, 0x4, 0x55555555, x3, 1028, x4)
+
+inst_273:
+// rs1_val==4 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xc, 0x4, 0x3, x3, 1032, x4)
+
+inst_274:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffea80f, 0xb503, 0xb505, x3, 1036, x4)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x8002c1f7, 0xb503, -0xb503, x3, 1040, x4)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x999a0635, 0xb503, 0x66666667, x3, 1044, x4)
+
+inst_277:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xcccd5d9c, 0xb503, 0x33333334, x3, 1048, x4)
+
+inst_278:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x43e12, 0xb503, 0x6, x3, 1052, x4)
+
+inst_279:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaae701, 0xb503, -0x55555555, x3, 1056, x4)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x5555ce02, 0xb503, 0x55555556, x3, 1060, x4)
+
+inst_281:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x2d40c, 0xb503, 0x4, x3, 1064, x4)
+
+inst_282:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffd3e09, 0xb503, 0xb503, x3, 1068, x4)
+
+inst_283:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0xb503, 0x0, x3, 1072, x4)
+
+inst_284:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x99989c2f, 0xb503, 0x66666665, x3, 1076, x4)
+
+inst_285:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xcccbf396, 0xb503, 0x33333332, x3, 1080, x4)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x555463fc, 0xb503, 0x55555554, x3, 1084, x4)
+
+inst_287:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x16a06, 0xb503, 0x2, x3, 1088, x4)
+
+inst_288:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffdf30c, 0xb503, 0xb504, x3, 1092, x4)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x80020cf4, 0xb503, -0xb504, x3, 1096, x4)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x99995132, 0xb503, 0x66666666, x3, 1100, x4)
+
+inst_291:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xcccca899, 0xb503, 0x33333333, x3, 1104, x4)
+
+inst_292:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x3890f, 0xb503, 0x5, x3, 1108, x4)
+
+inst_293:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa31fe, 0xb503, -0x55555556, x3, 1112, x4)
+
+inst_294:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x555518ff, 0xb503, 0x55555555, x3, 1116, x4)
+
+inst_295:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x21f09, 0xb503, 0x3, x3, 1120, x4)
+
+inst_296:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0xb505, x3, 1124, x4)
+
+inst_297:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, -0xb503, x3, 1128, x4)
+
+inst_298:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x66666667, x3, 1132, x4)
+
+inst_299:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x33333334, x3, 1136, x4)
+
+inst_300:
+// rs1_val==0 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x6, x3, 1140, x4)
+
+inst_301:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, -0x55555555, x3, 1144, x4)
+
+inst_302:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x55555556, x3, 1148, x4)
+
+inst_303:
+// rs1_val==0 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x4, x3, 1152, x4)
+
+inst_304:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0xb503, x3, 1156, x4)
+
+inst_305:
+// rs1_val==0 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x0, x3, 1160, x4)
+
+inst_306:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x66666665, x3, 1164, x4)
+
+inst_307:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x33333332, x3, 1168, x4)
+
+inst_308:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x55555554, x3, 1172, x4)
+
+inst_309:
+// rs1_val==0 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x2, x3, 1176, x4)
+
+inst_310:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0xb504, x3, 1180, x4)
+
+inst_311:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, -0xb504, x3, 1184, x4)
+
+inst_312:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x66666666, x3, 1188, x4)
+
+inst_313:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x33333333, x3, 1192, x4)
+
+inst_314:
+// rs1_val==0 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x5, x3, 1196, x4)
+
+inst_315:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, -0x55555556, x3, 1200, x4)
+
+inst_316:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x55555555, x3, 1204, x4)
+
+inst_317:
+// rs1_val==0 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x0, 0x3, x3, 1208, x4)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x666568f9, 0x66666665, 0xb505, x3, 1212, x4)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x666763d1, 0x66666665, -0xb503, x3, 1216, x4)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xa3d70a3, 0x66666665, 0x66666667, x3, 1220, x4)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xb851eb84, 0x66666665, 0x33333334, x3, 1224, x4)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x6666665e, 0x66666665, 0x6, x3, 1228, x4)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x77777777, 0x66666665, -0x55555555, x3, 1232, x4)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xeeeeeeee, 0x66666665, 0x55555556, x3, 1236, x4)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x99999994, 0x66666665, 0x4, x3, 1240, x4)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x33333333, 0x0, x3, 1244, x4)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x51eb851f, 0x33333333, 0x66666665, x3, 1248, x4)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x8f5c28f6, 0x33333333, 0x33333332, x3, 1252, x4)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, 0x33333333, 0x55555554, x3, 1256, x4)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, 0x33333333, 0x2, x3, 1260, x4)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffffdbcc, 0x33333333, 0xb504, x3, 1264, x4)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x2434, 0x33333333, -0xb504, x3, 1268, x4)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x851eb852, 0x33333333, 0x66666666, x3, 1272, x4)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xc28f5c29, 0x33333333, 0x33333333, x3, 1276, x4)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffff, 0x33333333, 0x5, x3, 1280, x4)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xddddddde, 0x33333333, -0x55555556, x3, 1284, x4)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xeeeeeeef, 0x33333333, 0x55555555, x3, 1288, x4)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x99999999, 0x33333333, 0x3, x3, 1292, x4)
+
+inst_339:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x38919, 0x5, 0xb505, x3, 1296, x4)
+
+inst_340:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xfffc76f1, 0x5, -0xb503, x3, 1300, x4)
+
+inst_341:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x3, 0x5, 0x66666667, x3, 1304, x4)
+
+inst_342:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x4, 0x5, 0x33333334, x3, 1308, x4)
+
+inst_343:
+// rs1_val==5 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x1e, 0x5, 0x6, x3, 1312, x4)
+
+inst_344:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x55555557, 0x5, -0x55555555, x3, 1316, x4)
+
+inst_345:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaae, 0x5, 0x55555556, x3, 1320, x4)
+
+inst_346:
+// rs1_val==5 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x14, 0x5, 0x4, x3, 1324, x4)
+
+inst_347:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x3890f, 0x5, 0xb503, x3, 1328, x4)
+
+inst_348:
+// rs1_val==5 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x5, 0x0, x3, 1332, x4)
+
+inst_349:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff9, 0x5, 0x66666665, x3, 1336, x4)
+
+inst_350:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffa, 0x5, 0x33333332, x3, 1340, x4)
+
+inst_351:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa4, 0x5, 0x55555554, x3, 1344, x4)
+
+inst_352:
+// rs1_val==5 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xa, 0x5, 0x2, x3, 1348, x4)
+
+inst_353:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x38914, 0x5, 0xb504, x3, 1352, x4)
+
+inst_354:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfffc76ec, 0x5, -0xb504, x3, 1356, x4)
+
+inst_355:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, 0x5, 0x66666666, x3, 1360, x4)
+
+inst_356:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffff, 0x5, 0x33333333, x3, 1364, x4)
+
+inst_357:
+// rs1_val==5 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x19, 0x5, 0x5, x3, 1368, x4)
+
+inst_358:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x55555552, 0x5, -0x55555556, x3, 1372, x4)
+
+inst_359:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa9, 0x5, 0x55555555, x3, 1376, x4)
+
+inst_360:
+// rs1_val==5 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xf, 0x5, 0x3, x3, 1380, x4)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0xffff8752, -0x55555556, 0xb505, x3, 1384, x4)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x5555ce02, -0x55555556, -0xb503, x3, 1388, x4)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, -0x55555556, 0x66666667, x3, 1392, x4)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x88888888, -0x55555556, 0x33333334, x3, 1396, x4)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffc, -0x55555556, 0x6, x3, 1400, x4)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x8e38e38e, -0x55555556, -0x55555555, x3, 1404, x4)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x1c71c71c, -0x55555556, 0x55555556, x3, 1408, x4)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa8, -0x55555556, 0x4, x3, 1412, x4)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa31fe, -0x55555556, 0xb503, x3, 1416, x4)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, -0x55555556, 0x0, x3, 1420, x4)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x11111112, -0x55555556, 0x66666665, x3, 1424, x4)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x33333334, -0x55555556, 0x33333332, x3, 1428, x4)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xc71c71c8, -0x55555556, 0x55555554, x3, 1432, x4)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x55555554, -0x55555556, 0x2, x3, 1436, x4)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x5554dca8, -0x55555556, 0xb504, x3, 1440, x4)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab2358, -0x55555556, -0xb504, x3, 1444, x4)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, -0x55555556, 0x66666666, x3, 1448, x4)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xddddddde, -0x55555556, 0x33333333, x3, 1452, x4)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x55555552, -0x55555556, 0x5, x3, 1456, x4)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xe38e38e4, -0x55555556, -0x55555556, x3, 1460, x4)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x71c71c72, -0x55555556, 0x55555555, x3, 1464, x4)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, -0x55555556, 0x3, x3, 1468, x4)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0xffffc3a9, 0x55555555, 0xb505, x3, 1472, x4)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaae701, 0x55555555, -0xb503, x3, 1476, x4)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x33333333, 0x55555555, 0x66666667, x3, 1480, x4)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x44444444, 0x55555555, 0x33333334, x3, 1484, x4)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, 0x55555555, 0x6, x3, 1488, x4)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xc71c71c7, 0x55555555, -0x55555555, x3, 1492, x4)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x8e38e38e, 0x55555555, 0x55555556, x3, 1496, x4)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x55555554, 0x55555555, 0x4, x3, 1500, x4)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x555518ff, 0x55555555, 0xb503, x3, 1504, x4)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x55555555, 0x0, x3, 1508, x4)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x88888889, 0x55555555, 0x66666665, x3, 1512, x4)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999a, 0x55555555, 0x33333332, x3, 1516, x4)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xe38e38e4, 0x55555555, 0x55555554, x3, 1520, x4)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaaa, 0x55555555, 0x2, x3, 1524, x4)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa6e54, 0x55555555, 0xb504, x3, 1528, x4)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x555591ac, 0x55555555, -0xb504, x3, 1532, x4)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xddddddde, 0x55555555, 0x66666666, x3, 1536, x4)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xeeeeeeef, 0x55555555, 0x33333333, x3, 1540, x4)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa9, 0x55555555, 0x5, x3, 1544, x4)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x71c71c72, 0x55555555, -0x55555556, x3, 1548, x4)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x38e38e39, 0x55555555, 0x55555555, x3, 1552, x4)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffff, 0x55555555, 0x3, x3, 1556, x4)
+
+inst_405:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x21f0f, 0x3, 0xb505, x3, 1560, x4)
+
+inst_406:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xfffde0f7, 0x3, -0xb503, x3, 1564, x4)
+
+inst_407:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x33333335, 0x3, 0x66666667, x3, 1568, x4)
+
+inst_408:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999c, 0x3, 0x33333334, x3, 1572, x4)
+
+inst_409:
+// rs1_val==3 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x12, 0x3, 0x6, x3, 1576, x4)
+
+inst_410:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x1, 0x3, -0x55555555, x3, 1580, x4)
+
+inst_411:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x2, 0x3, 0x55555556, x3, 1584, x4)
+
+inst_412:
+// rs1_val==3 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xc, 0x3, 0x4, x3, 1588, x4)
+
+inst_413:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x21f09, 0x3, 0xb503, x3, 1592, x4)
+
+inst_414:
+// rs1_val==3 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x3, 0x0, x3, 1596, x4)
+
+inst_415:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x3333332f, 0x3, 0x66666665, x3, 1600, x4)
+
+inst_416:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x99999996, 0x3, 0x33333332, x3, 1604, x4)
+
+inst_417:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffc, 0x3, 0x55555554, x3, 1608, x4)
+
+inst_418:
+// rs1_val==3 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x6, 0x3, 0x2, x3, 1612, x4)
+
+inst_419:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x21f0c, 0x3, 0xb504, x3, 1616, x4)
+
+inst_420:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfffde0f4, 0x3, -0xb504, x3, 1620, x4)
+
+inst_421:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x33333332, 0x3, 0x66666666, x3, 1624, x4)
+
+inst_422:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x99999999, 0x3, 0x33333333, x3, 1628, x4)
+
+inst_423:
+// rs1_val==3 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xf, 0x3, 0x5, x3, 1632, x4)
+
+inst_424:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, 0x3, -0x55555556, x3, 1636, x4)
+
+inst_425:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xffffffff, 0x3, 0x55555555, x3, 1640, x4)
+
+inst_426:
+// rs1_val==3 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x9, 0x3, 0x3, x3, 1644, x4)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x99989c2f, 0x66666665, 0xb503, x3, 1648, x4)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x66666665, 0x0, x3, 1652, x4)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x3d70a3d9, 0x66666665, 0x66666665, x3, 1656, x4)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xeb851eba, 0x66666665, 0x33333332, x3, 1660, x4)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x22222224, 0x66666665, 0x55555554, x3, 1664, x4)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccca, 0x66666665, 0x2, x3, 1668, x4)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffff0294, 0x66666665, 0xb504, x3, 1672, x4)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfd6c, 0x66666665, -0xb504, x3, 1676, x4)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xa3d70a3e, 0x66666665, 0x66666666, x3, 1680, x4)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x51eb851f, 0x66666665, 0x33333333, x3, 1684, x4)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff9, 0x66666665, 0x5, x3, 1688, x4)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x11111112, 0x66666665, -0x55555556, x3, 1692, x4)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x88888889, 0x66666665, 0x55555555, x3, 1696, x4)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x3333332f, 0x66666665, 0x3, x3, 1700, x4)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x333259fa, 0x33333332, 0xb505, x3, 1704, x4)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x33340c6a, 0x33333332, -0xb503, x3, 1708, x4)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x51eb851e, 0x33333332, 0x66666667, x3, 1712, x4)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xc28f5c28, 0x33333332, 0x33333334, x3, 1716, x4)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x3333332c, 0x33333332, 0x6, x3, 1720, x4)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, 0x33333332, -0x55555555, x3, 1724, x4)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x33333332, 0x55555556, x3, 1728, x4)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccc8, 0x33333332, 0x4, x3, 1732, x4)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xcccbf396, 0x33333332, 0xb503, x3, 1736, x4)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x33333332, 0x0, x3, 1740, x4)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xeb851eba, 0x33333332, 0x66666665, x3, 1744, x4)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x5c28f5c4, 0x33333332, 0x33333332, x3, 1748, x4)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x66666668, 0x33333332, 0x55555554, x3, 1752, x4)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x66666664, 0x33333332, 0x2, x3, 1756, x4)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffff26c8, 0x33333332, 0xb504, x3, 1760, x4)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xd938, 0x33333332, -0xb504, x3, 1764, x4)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x1eb851ec, 0x33333332, 0x66666666, x3, 1768, x4)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x8f5c28f6, 0x33333332, 0x33333333, x3, 1772, x4)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffa, 0x33333332, 0x5, x3, 1776, x4)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x33333334, 0x33333332, -0x55555556, x3, 1780, x4)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x9999999a, 0x33333332, 0x55555555, x3, 1784, x4)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x99999996, 0x33333332, 0x3, x3, 1788, x4)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0xffff0ea4, 0x55555554, 0xb505, x3, 1792, x4)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab9c04, 0x55555554, -0xb503, x3, 1796, x4)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x55555554, 0x66666667, x3, 1800, x4)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x11111110, 0x55555554, 0x33333334, x3, 1804, x4)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff8, 0x55555554, 0x6, x3, 1808, x4)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x1c71c71c, 0x55555554, -0x55555555, x3, 1812, x4)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x38e38e38, 0x55555554, 0x55555556, x3, 1816, x4)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x55555550, 0x55555554, 0x4, x3, 1820, x4)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x555463fc, 0x55555554, 0xb503, x3, 1824, x4)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x55555554, 0x0, x3, 1828, x4)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0x22222224, 0x55555554, 0x66666665, x3, 1832, x4)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x66666668, 0x55555554, 0x33333332, x3, 1836, x4)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x8e38e390, 0x55555554, 0x55555554, x3, 1840, x4)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa8, 0x55555554, 0x2, x3, 1844, x4)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xaaa9b950, 0x55555554, 0xb504, x3, 1848, x4)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x555646b0, 0x55555554, -0xb504, x3, 1852, x4)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x77777778, 0x55555554, 0x66666666, x3, 1856, x4)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, 0x55555554, 0x33333333, x3, 1860, x4)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa4, 0x55555554, 0x5, x3, 1864, x4)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xc71c71c8, 0x55555554, -0x55555556, x3, 1868, x4)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xe38e38e4, 0x55555554, 0x55555555, x3, 1872, x4)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffc, 0x55555554, 0x3, x3, 1876, x4)
+
+inst_485:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x16a0a, 0x2, 0xb505, x3, 1880, x4)
+
+inst_486:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xfffe95fa, 0x2, -0xb503, x3, 1884, x4)
+
+inst_487:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccce, 0x2, 0x66666667, x3, 1888, x4)
+
+inst_488:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x66666668, 0x2, 0x33333334, x3, 1892, x4)
+
+inst_489:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x55555556, 0x2, -0x55555555, x3, 1896, x4)
+
+inst_490:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaac, 0x2, 0x55555556, x3, 1900, x4)
+
+inst_491:
+// rs1_val==2 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x8, 0x2, 0x4, x3, 1904, x4)
+
+inst_492:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x16a06, 0x2, 0xb503, x3, 1908, x4)
+
+inst_493:
+// rs1_val==2 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x2, 0x0, x3, 1912, x4)
+
+inst_494:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xccccccca, 0x2, 0x66666665, x3, 1916, x4)
+
+inst_495:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x66666664, 0x2, 0x33333332, x3, 1920, x4)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaa8, 0x2, 0x55555554, x3, 1924, x4)
+
+inst_497:
+// rs1_val==2 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x4, 0x2, 0x2, x3, 1928, x4)
+
+inst_498:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x16a08, 0x2, 0xb504, x3, 1932, x4)
+
+inst_499:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xfffe95f8, 0x2, -0xb504, x3, 1936, x4)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x2, 0x66666666, x3, 1940, x4)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x66666666, 0x2, 0x33333333, x3, 1944, x4)
+
+inst_502:
+// rs1_val==2 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xa, 0x2, 0x5, x3, 1948, x4)
+
+inst_503:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x55555554, 0x2, -0x55555556, x3, 1952, x4)
+
+inst_504:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaaaaaa, 0x2, 0x55555555, x3, 1956, x4)
+
+inst_505:
+// rs1_val==2 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x6, 0x2, 0x3, x3, 1960, x4)
+
+inst_506:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x7fff5d14, 0xb504, 0xb505, x3, 1964, x4)
+
+inst_507:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x80020cf4, 0xb504, -0xb503, x3, 1968, x4)
+
+inst_508:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x6c9c, 0xb504, 0x66666667, x3, 1972, x4)
+
+inst_509:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0x90d0, 0xb504, 0x33333334, x3, 1976, x4)
+
+inst_510:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x43e18, 0xb504, 0x6, x3, 1980, x4)
+
+inst_511:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x555591ac, 0xb504, -0x55555555, x3, 1984, x4)
+
+inst_512:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab2358, 0xb504, 0x55555556, x3, 1988, x4)
+
+inst_513:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x2d410, 0xb504, 0x4, x3, 1992, x4)
+
+inst_514:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffdf30c, 0xb504, 0xb503, x3, 1996, x4)
+
+inst_515:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0xb504, 0x0, x3, 2000, x4)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xffff0294, 0xb504, 0x66666665, x3, 2004, x4)
+
+inst_517:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xffff26c8, 0xb504, 0x33333332, x3, 2008, x4)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0xaaa9b950, 0xb504, 0x55555554, x3, 2012, x4)
+
+inst_519:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0x16a08, 0xb504, 0x2, x3, 2016, x4)
+
+inst_520:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffea810, 0xb504, 0xb504, x3, 2020, x4)
+
+inst_521:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x800157f0, 0xb504, -0xb504, x3, 2024, x4)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xffffb798, 0xb504, 0x66666666, x3, 2028, x4)
+
+inst_523:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0xffffdbcc, 0xb504, 0x33333333, x3, 2032, x4)
+
+inst_524:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0x38914, 0xb504, 0x5, x3, 2036, x4)
+
+inst_525:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x5554dca8, 0xb504, -0x55555556, x3, 2040, x4)
+
+inst_526:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa6e54, 0xb504, 0x55555555, x3, 2044, x4)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_527:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x21f0c, 0xb504, 0x3, x3, 0, x4)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x8000a2ec, -0xb504, 0xb505, x3, 4, x4)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffdf30c, -0xb504, -0xb503, x3, 8, x4)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xffff9364, -0xb504, 0x66666667, x3, 12, x4)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xffff6f30, -0xb504, 0x33333334, x3, 16, x4)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0xfffbc1e8, -0xb504, 0x6, x3, 20, x4)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xaaaa6e54, -0xb504, -0x55555555, x3, 24, x4)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x5554dca8, -0xb504, 0x55555556, x3, 28, x4)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xfffd2bf0, -0xb504, 0x4, x3, 32, x4)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x80020cf4, -0xb504, 0xb503, x3, 36, x4)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, -0xb504, 0x0, x3, 40, x4)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xfd6c, -0xb504, 0x66666665, x3, 44, x4)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0xd938, -0xb504, 0x33333332, x3, 48, x4)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x555646b0, -0xb504, 0x55555554, x3, 52, x4)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xfffe95f8, -0xb504, 0x2, x3, 56, x4)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x800157f0, -0xb504, 0xb504, x3, 60, x4)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x7ffea810, -0xb504, -0xb504, x3, 64, x4)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0x4868, -0xb504, 0x66666666, x3, 68, x4)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x2434, -0xb504, 0x33333333, x3, 72, x4)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xfffc76ec, -0xb504, 0x5, x3, 76, x4)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xaaab2358, -0xb504, -0x55555556, x3, 80, x4)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x555591ac, -0xb504, 0x55555555, x3, 84, x4)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0xfffde0f4, -0xb504, 0x3, x3, 88, x4)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x66661dfe, 0x66666666, 0xb505, x3, 92, x4)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x6666aece, 0x66666666, -0xb503, x3, 96, x4)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0x70a3d70a, 0x66666666, 0x66666667, x3, 100, x4)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xeb851eb8, 0x66666666, 0x33333334, x3, 104, x4)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x66666664, 0x66666666, 0x6, x3, 108, x4)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x22222222, 0x66666666, -0x55555555, x3, 112, x4)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x44444444, 0x66666666, 0x55555556, x3, 116, x4)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0x99999998, 0x66666666, 0x4, x3, 120, x4)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x99995132, 0x66666666, 0xb503, x3, 124, x4)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(mul, x12, x10, x11, 0x0, 0x66666666, 0x0, x3, 128, x4)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(mul, x12, x10, x11, 0xa3d70a3e, 0x66666666, 0x66666665, x3, 132, x4)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(mul, x12, x10, x11, 0x1eb851ec, 0x66666666, 0x33333332, x3, 136, x4)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(mul, x12, x10, x11, 0x77777778, 0x66666666, 0x55555554, x3, 140, x4)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x66666666, 0x2, x3, 144, x4)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0xffffb798, 0x66666666, 0xb504, x3, 148, x4)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(mul, x12, x10, x11, 0x4868, 0x66666666, -0xb504, x3, 152, x4)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(mul, x12, x10, x11, 0xa3d70a4, 0x66666666, 0x66666666, x3, 156, x4)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(mul, x12, x10, x11, 0x851eb852, 0x66666666, 0x33333333, x3, 160, x4)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffffe, 0x66666666, 0x5, x3, 164, x4)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0xbbbbbbbc, 0x66666666, -0x55555556, x3, 168, x4)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0xddddddde, 0x66666666, 0x55555555, x3, 172, x4)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(mul, x12, x10, x11, 0x33333332, 0x66666666, 0x3, x3, 176, x4)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(mul, x12, x10, x11, 0x33330eff, 0x33333333, 0xb505, x3, 180, x4)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0x33335767, 0x33333333, -0xb503, x3, 184, x4)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(mul, x12, x10, x11, 0xb851eb85, 0x33333333, 0x66666667, x3, 188, x4)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(mul, x12, x10, x11, 0xf5c28f5c, 0x33333333, 0x33333334, x3, 192, x4)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(mul, x12, x10, x11, 0x33333332, 0x33333333, 0x6, x3, 196, x4)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(mul, x12, x10, x11, 0x11111111, 0x33333333, -0x55555555, x3, 200, x4)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(mul, x12, x10, x11, 0x22222222, 0x33333333, 0x55555556, x3, 204, x4)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(mul, x12, x10, x11, 0xcccccccc, 0x33333333, 0x4, x3, 208, x4)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(mul, x12, x10, x11, 0xcccca899, 0x33333333, 0xb503, x3, 212, x4)
+
+inst_581:
+// rs2_val == -1073741825, rs1_val == 134217728
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:-0x40000001
+TEST_RR_OP(mul, x12, x10, x11, 0xf8000000, 0x8000000, -0x40000001, x3, 216, x4)
+
+inst_582:
+// rs2_val == -536870913, rs1_val == 8
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x20000001
+TEST_RR_OP(mul, x12, x10, x11, 0xfffffff8, 0x8, -0x20000001, x3, 220, x4)
+
+inst_583:
+// rs2_val == -8388609, 
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x800001
+TEST_RR_OP(mul, x12, x10, x11, 0xfb7ffff7, 0x9, -0x800001, x3, 224, x4)
+
+inst_584:
+// rs2_val == -4194305, rs1_val == 32
+// opcode: mul ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:-0x400001
+TEST_RR_OP(mul, x12, x10, x11, 0xf7ffffe0, 0x20, -0x400001, x3, 228, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 58*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulh-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulh-01.S
new file mode 100644
index 000000000..8de953dbe
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulh-01.S
@@ -0,0 +1,3040 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the mulh instruction of the RISC-V M extension for the mulh covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",mulh)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x8, rs2==x5, rd==x5, rs1_val != rs2_val, rs1_val == 4, rs2_val == -67108865, rs1_val > 0 and rs2_val < 0
+// opcode: mulh ; op1:x8; op2:x5; dest:x5; op1val:0x4;  op2val:-0x4000001
+TEST_RR_OP(mulh, x5, x8, x5, 0xffffffff, 0x4, -0x4000001, x2, 0, x3)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x13, rs2==x6, rd==x13, rs2_val == 2147483647, rs1_val > 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: mulh ; op1:x13; op2:x6; dest:x13; op1val:0xb504;  op2val:0x7fffffff
+TEST_RR_OP(mulh, x13, x13, x6, 0x5a81, 0xb504, 0x7fffffff, x2, 4, x3)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14, rs2_val == -1073741825, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: mulh ; op1:x14; op2:x14; dest:x14; op1val:0x7fffffff;  op2val:0x7fffffff
+TEST_RR_OP(mulh, x14, x14, x14, 0x3fffffff, 0x7fffffff, 0x7fffffff, x2, 8, x3)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x1, rs2_val == -536870913, rs1_val < 0 and rs2_val < 0, rs1_val == -4194305
+// opcode: mulh ; op1:x4; op2:x4; dest:x1; op1val:-0x400001;  op2val:-0x400001
+TEST_RR_OP(mulh, x1, x4, x4, 0x1000, -0x400001, -0x400001, x2, 12, x3)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x13, rd==x7, rs2_val == -268435457, 
+// opcode: mulh ; op1:x10; op2:x13; dest:x7; op1val:0x33333333;  op2val:-0x10000001
+TEST_RR_OP(mulh, x7, x10, x13, 0xfccccccc, 0x33333333, -0x10000001, x2, 16, x3)
+
+inst_5:
+// rs1==x11, rs2==x12, rd==x15, rs2_val == -134217729, 
+// opcode: mulh ; op1:x11; op2:x12; dest:x15; op1val:0xb505;  op2val:-0x8000001
+TEST_RR_OP(mulh, x15, x11, x12, 0xfffffa57, 0xb505, -0x8000001, x2, 20, x3)
+RVTEST_SIGBASE( x5,signature_x5_0)
+
+inst_6:
+// rs1==x0, rs2==x15, rd==x10, rs2_val == -33554433, rs1_val == -4097
+// opcode: mulh ; op1:x0; op2:x15; dest:x10; op1val:0x0;  op2val:-0x2000001
+TEST_RR_OP(mulh, x10, x0, x15, 0x0, 0x0, -0x2000001, x5, 0, x11)
+
+inst_7:
+// rs1==x6, rs2==x2, rd==x8, rs2_val == -16777217, rs1_val == -134217729
+// opcode: mulh ; op1:x6; op2:x2; dest:x8; op1val:-0x8000001;  op2val:-0x1000001
+TEST_RR_OP(mulh, x8, x6, x2, 0x80000, -0x8000001, -0x1000001, x5, 4, x11)
+
+inst_8:
+// rs1==x2, rs2==x0, rd==x9, rs2_val == -8388609, rs1_val == 256
+// opcode: mulh ; op1:x2; op2:x0; dest:x9; op1val:0x100;  op2val:0x0
+TEST_RR_OP(mulh, x9, x2, x0, 0x0, 0x100, 0x0, x5, 8, x11)
+
+inst_9:
+// rs1==x9, rs2==x3, rd==x2, rs2_val == -4194305, 
+// opcode: mulh ; op1:x9; op2:x3; dest:x2; op1val:0x7fffffff;  op2val:-0x400001
+TEST_RR_OP(mulh, x2, x9, x3, 0xffdfffff, 0x7fffffff, -0x400001, x5, 12, x11)
+
+inst_10:
+// rs1==x15, rs2==x7, rd==x4, rs2_val == -2097153, 
+// opcode: mulh ; op1:x15; op2:x7; dest:x4; op1val:0x7fffffff;  op2val:-0x200001
+TEST_RR_OP(mulh, x4, x15, x7, 0xffefffff, 0x7fffffff, -0x200001, x5, 16, x11)
+
+inst_11:
+// rs1==x1, rs2==x8, rd==x12, rs2_val == -1048577, rs1_val == -1073741825
+// opcode: mulh ; op1:x1; op2:x8; dest:x12; op1val:-0x40000001;  op2val:-0x100001
+TEST_RR_OP(mulh, x12, x1, x8, 0x40000, -0x40000001, -0x100001, x5, 20, x11)
+
+inst_12:
+// rs1==x3, rs2==x10, rd==x11, rs2_val == -524289, 
+// opcode: mulh ; op1:x3; op2:x10; dest:x11; op1val:0x66666665;  op2val:-0x80001
+TEST_RR_OP(mulh, x11, x3, x10, 0xfffccccc, 0x66666665, -0x80001, x5, 24, x4)
+RVTEST_SIGBASE( x2,signature_x2_2)
+
+inst_13:
+// rs1==x12, rs2==x9, rd==x6, rs2_val == -262145, 
+// opcode: mulh ; op1:x12; op2:x9; dest:x6; op1val:-0xb504;  op2val:-0x40001
+TEST_RR_OP(mulh, x6, x12, x9, 0x2, -0xb504, -0x40001, x2, 0, x4)
+
+inst_14:
+// rs1==x7, rs2==x1, rd==x3, rs2_val == -131073, rs1_val == 33554432
+// opcode: mulh ; op1:x7; op2:x1; dest:x3; op1val:0x2000000;  op2val:-0x20001
+TEST_RR_OP(mulh, x3, x7, x1, 0xfffffbff, 0x2000000, -0x20001, x2, 4, x4)
+
+inst_15:
+// rs1==x5, rs2==x11, rd==x0, rs2_val == -65537, 
+// opcode: mulh ; op1:x5; op2:x11; dest:x0; op1val:0x66666667;  op2val:-0x10001
+TEST_RR_OP(mulh, x0, x5, x11, 0, 0x66666667, -0x10001, x2, 8, x4)
+
+inst_16:
+// rs2_val == -32769, rs1_val == 1073741824
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x8001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdfff, 0x40000000, -0x8001, x2, 12, x4)
+
+inst_17:
+// rs2_val == -16385, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x4001
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffff333, 0x33333333, -0x4001, x2, 16, x4)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x2001
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffff999, 0x33333332, -0x2001, x2, 20, x4)
+
+inst_19:
+// rs2_val == -4097, rs1_val == 8
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x1001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x8, -0x1001, x2, 24, x4)
+
+inst_20:
+// rs2_val == -2049, rs1_val == 0
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x801
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0x801, x2, 28, x4)
+
+inst_21:
+// rs2_val == -1025, rs1_val == 32768
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:-0x401
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x8000, -0x401, x2, 32, x4)
+
+inst_22:
+// rs2_val == -513, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x201
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x9, -0x201, x2, 36, x4)
+
+inst_23:
+// rs2_val == -257, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x101
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x8, -0x101, x2, 40, x4)
+
+inst_24:
+// rs2_val == -129, rs1_val == 268435456
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:-0x81
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffff7, 0x10000000, -0x81, x2, 44, x4)
+
+inst_25:
+// rs2_val == -65, rs1_val == -32769
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:-0x41
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x8001, -0x41, x2, 48, x4)
+
+inst_26:
+// rs2_val == -33, rs1_val == 1
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x21
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x1, -0x21, x2, 52, x4)
+
+inst_27:
+// rs2_val == -17, rs1_val == 2048
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:-0x11
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x800, -0x11, x2, 56, x4)
+
+inst_28:
+// rs2_val == -9, rs1_val == 2097152
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x9
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x200000, -0x9, x2, 60, x4)
+
+inst_29:
+// rs2_val == -5, rs1_val == -8193
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x2001, -0x5, x2, 64, x4)
+
+inst_30:
+// rs2_val == -3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x2001, -0x3, x2, 68, x4)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0x2, x2, 72, x4)
+
+inst_32:
+// rs1_val == -536870913, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x16a0, -0x20000001, -0xb503, x2, 76, x4)
+
+inst_33:
+// rs1_val == -268435457, rs1_val < 0 and rs2_val > 0
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffff4af, -0x10000001, 0xb504, x2, 80, x4)
+
+inst_34:
+// rs1_val == -67108865, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x2d4, -0x4000001, -0xb503, x2, 84, x4)
+
+inst_35:
+// rs1_val == -33554433, rs2_val == 1431655765
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xff555555, -0x2000001, 0x55555555, x2, 88, x4)
+
+inst_36:
+// rs1_val == -16777217, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:-0x200001
+TEST_RR_OP(mulh, x12, x10, x11, 0x2000, -0x1000001, -0x200001, x2, 92, x4)
+
+inst_37:
+// rs1_val == -8388609, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xffe66666, -0x800001, 0x33333332, x2, 96, x4)
+
+inst_38:
+// rs1_val == -2097153, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0xa
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x200001, -0xa, x2, 100, x4)
+
+inst_39:
+// rs1_val == -1048577, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x100001, 0x5, x2, 104, x4)
+
+inst_40:
+// rs1_val == -524289, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x80001, -0x4, x2, 108, x4)
+
+inst_41:
+// rs1_val == -262145, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffeaaaa, -0x40001, 0x55555556, x2, 112, x4)
+
+inst_42:
+// rs1_val == -131073, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:-0x100001
+TEST_RR_OP(mulh, x12, x10, x11, 0x20, -0x20001, -0x100001, x2, 116, x4)
+
+inst_43:
+// rs1_val == -65537, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffaaaa, -0x10001, 0x55555554, x2, 120, x4)
+
+inst_44:
+// rs1_val == -16385, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x1
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x4001, -0x1, x2, 124, x4)
+
+inst_45:
+// rs1_val == -2049, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffd55, -0x801, 0x55555554, x2, 128, x4)
+
+inst_46:
+// rs1_val == -1025, rs2_val == 4
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x401, 0x4, x2, 132, x4)
+
+inst_47:
+// rs1_val == -513, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:-0x1000001
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, -0x201, -0x1000001, x2, 136, x4)
+
+inst_48:
+// rs1_val == -257, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:-0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x101, -0x5, x2, 140, x4)
+
+inst_49:
+// rs1_val == -129, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffd5, -0x81, 0x55555555, x2, 144, x4)
+
+inst_50:
+// rs1_val == -65, rs2_val == -1431655766
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x15, -0x41, -0x55555556, x2, 148, x4)
+
+inst_51:
+// rs1_val == -33, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x21, -0x4, x2, 152, x4)
+
+inst_52:
+// rs1_val == -17, rs2_val == 8388608
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x800000
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x11, 0x800000, x2, 156, x4)
+
+inst_53:
+// rs1_val == -9, rs2_val == 128
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x80
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x9, 0x80, x2, 160, x4)
+
+inst_54:
+// rs1_val == -5, rs2_val == 65536
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x10000
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x5, 0x10000, x2, 164, x4)
+
+inst_55:
+// rs1_val == -3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x4001
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x3, -0x4001, x2, 168, x4)
+
+inst_56:
+// rs1_val == -2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0x9
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x2, -0x9, x2, 172, x4)
+
+inst_57:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000;  op2val:-0x80000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x20000000, -0x40000000, -0x80000000, x2, 176, x4)
+
+inst_58:
+// rs2_val == 1073741824, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x40000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x40000000, x2, 180, x4)
+
+inst_59:
+// rs2_val == 536870912, rs1_val == 1024
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x20000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x80, 0x400, 0x20000000, x2, 184, x4)
+
+inst_60:
+// rs2_val == 268435456, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x10000000
+TEST_RR_OP(mulh, x12, x10, x11, 0xffbfffff, -0x4000001, 0x10000000, x2, 188, x4)
+
+inst_61:
+// rs2_val == 134217728, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x8000000
+TEST_RR_OP(mulh, x12, x10, x11, 0xfff7ffff, -0x1000001, 0x8000000, x2, 192, x4)
+
+inst_62:
+// rs2_val == 67108864, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4000000
+TEST_RR_OP(mulh, x12, x10, x11, 0xcccccc, 0x33333334, 0x4000000, x2, 196, x4)
+
+inst_63:
+// rs2_val == 33554432, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x2000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x200000, 0x10000000, 0x2000000, x2, 200, x4)
+
+inst_64:
+// rs2_val == 16777216, rs1_val == 1431655765
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x555555, 0x55555555, 0x1000000, x2, 204, x4)
+
+inst_65:
+// rs2_val == 4194304, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x400000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x400000, x2, 208, x4)
+
+inst_66:
+// rs2_val == 2097152, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x200000
+TEST_RR_OP(mulh, x12, x10, x11, 0x16, 0xb503, 0x200000, x2, 212, x4)
+
+inst_67:
+// rs2_val == 1048576, rs1_val == 2
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x100000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x100000, x2, 216, x4)
+
+inst_68:
+// rs2_val == 524288, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x80000
+TEST_RR_OP(mulh, x12, x10, x11, 0x3ffff, 0x7fffffff, 0x80000, x2, 220, x4)
+
+inst_69:
+// rs2_val == 262144, rs1_val == 512
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x40000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x200, 0x40000, x2, 224, x4)
+
+inst_70:
+// rs2_val == 131072, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x20000
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x5, 0x20000, x2, 228, x4)
+
+inst_71:
+// rs2_val == 32768, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x8000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x8000, x2, 232, x4)
+
+inst_72:
+// rs2_val == 16384, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3fffffff;  op2val:0x4000
+TEST_RR_OP(mulh, x12, x10, x11, 0xfff, 0x3fffffff, 0x4000, x2, 236, x4)
+
+inst_73:
+// rs2_val == 8192, rs1_val == 1048576
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x2000
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x100000, 0x2000, x2, 240, x4)
+
+inst_74:
+// rs2_val == 4096, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x1000
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x81, 0x1000, x2, 244, x4)
+
+inst_75:
+// rs2_val == 2048, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000;  op2val:0x800
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffe00, -0x40000000, 0x800, x2, 248, x4)
+
+inst_76:
+// rs2_val == 1024, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x400
+TEST_RR_OP(mulh, x12, x10, x11, 0x40, 0x10000000, 0x400, x2, 252, x4)
+
+inst_77:
+// rs2_val == 512, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x200
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x200, x2, 256, x4)
+
+inst_78:
+// rs2_val == 256, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x100
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x100000, 0x100, x2, 260, x4)
+
+inst_79:
+// rs2_val == 64, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:0x40
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x7, 0x40, x2, 264, x4)
+
+inst_80:
+// rs2_val == 32, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x20
+TEST_RR_OP(mulh, x12, x10, x11, 0xc, 0x66666666, 0x20, x2, 268, x4)
+
+inst_81:
+// rs2_val == 16, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x10
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x1000001, 0x10, x2, 272, x4)
+
+inst_82:
+// rs2_val == 8, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0x8
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x41, 0x8, x2, 276, x4)
+
+inst_83:
+// rs2_val == 2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x100001, 0x2, x2, 280, x4)
+
+inst_84:
+// rs2_val == 1, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3fffffff;  op2val:0x1
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3fffffff, 0x1, x2, 284, x4)
+
+inst_85:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x5a81, -0x80000000, -0xb503, x2, 288, x4)
+
+inst_86:
+// rs1_val == 536870912, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x20000000, 0x3, x2, 292, x4)
+
+inst_87:
+// rs1_val == 134217728, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x20
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x8000000, 0x20, x2, 296, x4)
+
+inst_88:
+// rs1_val == 67108864, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:-0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x4000000, -0x3, x2, 300, x4)
+
+inst_89:
+// rs1_val == 16777216, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffaaaaaa, 0x1000000, -0x55555555, x2, 304, x4)
+
+inst_90:
+// rs1_val == 8388608, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffd55555, 0x800000, -0x55555556, x2, 308, x4)
+
+inst_91:
+// rs1_val == 4194304, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x20000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x80000, 0x400000, 0x20000000, x2, 312, x4)
+
+inst_92:
+// rs1_val == 524288, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x1000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x80000, 0x1000, x2, 316, x4)
+
+inst_93:
+// rs1_val == 262144, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x200
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x40000, 0x200, x2, 320, x4)
+
+inst_94:
+// rs1_val == 131072, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x20000, 0x2, x2, 324, x4)
+
+inst_95:
+// rs1_val == 65536, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1000000
+TEST_RR_OP(mulh, x12, x10, x11, 0x100, 0x10000, 0x1000000, x2, 328, x4)
+
+inst_96:
+// rs1_val == 16384, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x40000001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffefff, 0x4000, -0x40000001, x2, 332, x4)
+
+inst_97:
+// rs1_val == 8192, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x2000001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffbf, 0x2000, -0x2000001, x2, 336, x4)
+
+inst_98:
+// rs1_val == 4096, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffaaa, 0x1000, -0x55555555, x2, 340, x4)
+
+inst_99:
+// rs1_val == 128, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x3fffffff
+TEST_RR_OP(mulh, x12, x10, x11, 0x1f, 0x80, 0x3fffffff, x2, 344, x4)
+
+inst_100:
+// rs1_val == 64, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x19, 0x40, 0x66666665, x2, 348, x4)
+
+inst_101:
+// rs1_val == 32, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:-0x40000000
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffff8, 0x20, -0x40000000, x2, 352, x4)
+
+inst_102:
+// rs1_val == 16, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x40000
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x10, 0x40000, x2, 356, x4)
+
+inst_103:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0xb505, x2, 360, x4)
+
+inst_104:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb505, -0xb503, x2, 364, x4)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0xb505, 0x66666667, x2, 368, x4)
+
+inst_106:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0xb505, 0x33333334, x2, 372, x4)
+
+inst_107:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x6, x2, 376, x4)
+
+inst_108:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0xb505, -0x55555555, x2, 380, x4)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c57, 0xb505, 0x55555556, x2, 384, x4)
+
+inst_110:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x4, x2, 388, x4)
+
+inst_111:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0xb503, x2, 392, x4)
+
+inst_112:
+// rs1_val==46341 and rs2_val==0, rs2_val == 0
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x0, x2, 396, x4)
+
+inst_113:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0xb505, 0x66666665, x2, 400, x4)
+
+inst_114:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0xb505, 0x33333332, x2, 404, x4)
+
+inst_115:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb505, 0x55555554, x2, 408, x4)
+
+inst_116:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x2, x2, 412, x4)
+
+inst_117:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0xb504, x2, 416, x4)
+
+inst_118:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb505, -0xb504, x2, 420, x4)
+
+inst_119:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0xb505, 0x66666666, x2, 424, x4)
+
+inst_120:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0xb505, 0x33333333, x2, 428, x4)
+
+inst_121:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x5, x2, 432, x4)
+
+inst_122:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a8, 0xb505, -0x55555556, x2, 436, x4)
+
+inst_123:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb505, 0x55555555, x2, 440, x4)
+
+inst_124:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb505, 0x3, x2, 444, x4)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0xb505, x2, 448, x4)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb503, -0xb503, x2, 452, x4)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, -0xb503, 0x66666667, x2, 456, x4)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333334, x2, 460, x4)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0x6, x2, 464, x4)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0xb503, -0x55555555, x2, 468, x4)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555556, x2, 472, x4)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0x4, x2, 476, x4)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0xb503, x2, 480, x4)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb503, 0x0, x2, 484, x4)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, -0xb503, 0x66666665, x2, 488, x4)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333332, x2, 492, x4)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555554, x2, 496, x4)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0x2, x2, 500, x4)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0xb504, x2, 504, x4)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb503, -0xb504, x2, 508, x4)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, -0xb503, 0x66666666, x2, 512, x4)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333333, x2, 516, x4)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0x5, x2, 520, x4)
+
+inst_144:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0xb503, -0x55555556, x2, 524, x4)
+
+inst_145:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555555, x2, 528, x4)
+
+inst_146:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb503, 0x3, x2, 532, x4)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0x66666667, 0xb505, x2, 536, x4)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, 0x66666667, -0xb503, x2, 540, x4)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666667, x2, 544, x4)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae148, 0x66666667, 0x33333334, x2, 548, x4)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x66666667, 0x6, x2, 552, x4)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, 0x66666667, -0x55555555, x2, 556, x4)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x66666667, 0x55555556, x2, 560, x4)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666667, 0x4, x2, 564, x4)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0x66666667, 0xb503, x2, 568, x4)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666667, 0x0, x2, 572, x4)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666665, x2, 576, x4)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333332, x2, 580, x4)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666667, 0x55555554, x2, 584, x4)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666667, 0x2, x2, 588, x4)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0x66666667, 0xb504, x2, 592, x4)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb797, 0x66666667, -0xb504, x2, 596, x4)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666666, x2, 600, x4)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333333, x2, 604, x4)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x66666667, 0x5, x2, 608, x4)
+
+inst_166:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, 0x66666667, -0x55555556, x2, 612, x4)
+
+inst_167:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x66666667, 0x55555555, x2, 616, x4)
+
+inst_168:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666667, 0x3, x2, 620, x4)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0x33333334, 0xb505, x2, 624, x4)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, 0x33333334, -0xb503, x2, 628, x4)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae148, 0x33333334, 0x66666667, x2, 632, x4)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a4, 0x33333334, 0x33333334, x2, 636, x4)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x33333334, 0x6, x2, 640, x4)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, 0x33333334, -0x55555555, x2, 644, x4)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x33333334, 0x55555556, x2, 648, x4)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333334, 0x4, x2, 652, x4)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0x33333334, 0xb503, x2, 656, x4)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333334, 0x0, x2, 660, x4)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666665, x2, 664, x4)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333332, x2, 668, x4)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x33333334, 0x55555554, x2, 672, x4)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333334, 0x2, x2, 676, x4)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0x33333334, 0xb504, x2, 680, x4)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcb, 0x33333334, -0xb504, x2, 684, x4)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666666, x2, 688, x4)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333333, x2, 692, x4)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x33333334, 0x5, x2, 696, x4)
+
+inst_188:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, 0x33333334, -0x55555556, x2, 700, x4)
+
+inst_189:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x33333334, 0x55555555, x2, 704, x4)
+
+inst_190:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333334, 0x3, x2, 708, x4)
+
+inst_191:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0xb505, x2, 712, x4)
+
+inst_192:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x6, -0xb503, x2, 716, x4)
+
+inst_193:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x6, 0x66666667, x2, 720, x4)
+
+inst_194:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x6, 0x33333334, x2, 724, x4)
+
+inst_195:
+// rs1_val==6 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x6, x2, 728, x4)
+
+inst_196:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x6, -0x55555555, x2, 732, x4)
+
+inst_197:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x6, 0x55555556, x2, 736, x4)
+
+inst_198:
+// rs1_val==6 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x4, x2, 740, x4)
+
+inst_199:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0xb503, x2, 744, x4)
+
+inst_200:
+// rs1_val==6 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x0, x2, 748, x4)
+
+inst_201:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x6, 0x66666665, x2, 752, x4)
+
+inst_202:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x6, 0x33333332, x2, 756, x4)
+
+inst_203:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x6, 0x55555554, x2, 760, x4)
+
+inst_204:
+// rs1_val==6 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x2, x2, 764, x4)
+
+inst_205:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0xb504, x2, 768, x4)
+
+inst_206:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x6, -0xb504, x2, 772, x4)
+
+inst_207:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x6, 0x66666666, x2, 776, x4)
+
+inst_208:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x6, 0x33333333, x2, 780, x4)
+
+inst_209:
+// rs1_val==6 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x5, x2, 784, x4)
+
+inst_210:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffd, 0x6, -0x55555556, x2, 788, x4)
+
+inst_211:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x6, 0x55555555, x2, 792, x4)
+
+inst_212:
+// rs1_val==6 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x6, 0x3, x2, 796, x4)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb505, x2, 800, x4)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0x55555555, -0xb503, x2, 804, x4)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, -0x55555555, 0x66666667, x2, 808, x4)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, -0x55555555, 0x33333334, x2, 812, x4)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555555, 0x6, x2, 816, x4)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, -0x55555555, -0x55555555, x2, 820, x4)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, -0x55555555, 0x55555556, x2, 824, x4)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555555, 0x4, x2, 828, x4)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb503, x2, 832, x4)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x55555555, 0x0, x2, 836, x4)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, -0x55555555, 0x66666665, x2, 840, x4)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x33333332, x2, 844, x4)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e4, -0x55555555, 0x55555554, x2, 848, x4)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x55555555, 0x2, x2, 852, x4)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb504, x2, 856, x4)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0x55555555, -0xb504, x2, 860, x4)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, -0x55555555, 0x66666666, x2, 864, x4)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x33333333, x2, 868, x4)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555555, 0x5, x2, 872, x4)
+
+inst_232:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, -0x55555555, -0x55555556, x2, 876, x4)
+
+inst_233:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, -0x55555555, 0x55555555, x2, 880, x4)
+
+inst_234:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x55555555, 0x3, x2, 884, x4)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c57, 0x55555556, 0xb505, x2, 888, x4)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555556, -0xb503, x2, 892, x4)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x55555556, 0x66666667, x2, 896, x4)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x55555556, 0x33333334, x2, 900, x4)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x55555556, 0x6, x2, 904, x4)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, 0x55555556, -0x55555555, x2, 908, x4)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555556, x2, 912, x4)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555556, 0x4, x2, 916, x4)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555556, 0xb503, x2, 920, x4)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555556, 0x0, x2, 924, x4)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555556, 0x66666665, x2, 928, x4)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x55555556, 0x33333332, x2, 932, x4)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555554, x2, 936, x4)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555556, 0x2, x2, 940, x4)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555556, 0xb504, x2, 944, x4)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555556, -0xb504, x2, 948, x4)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x55555556, 0x66666666, x2, 952, x4)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x55555556, 0x33333333, x2, 956, x4)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555556, 0x5, x2, 960, x4)
+
+inst_254:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, 0x55555556, -0x55555556, x2, 964, x4)
+
+inst_255:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555555, x2, 968, x4)
+
+inst_256:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555556, 0x3, x2, 972, x4)
+
+inst_257:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0xb505, x2, 976, x4)
+
+inst_258:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x4, -0xb503, x2, 980, x4)
+
+inst_259:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x66666667, x2, 984, x4)
+
+inst_260:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x33333334, x2, 988, x4)
+
+inst_261:
+// rs1_val==4 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x6, x2, 992, x4)
+
+inst_262:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x4, -0x55555555, x2, 996, x4)
+
+inst_263:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x55555556, x2, 1000, x4)
+
+inst_264:
+// rs1_val==4 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x4, x2, 1004, x4)
+
+inst_265:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0xb503, x2, 1008, x4)
+
+inst_266:
+// rs1_val==4 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x0, x2, 1012, x4)
+
+inst_267:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x66666665, x2, 1016, x4)
+
+inst_268:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x33333332, x2, 1020, x4)
+
+inst_269:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x55555554, x2, 1024, x4)
+
+inst_270:
+// rs1_val==4 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x2, x2, 1028, x4)
+
+inst_271:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0xb504, x2, 1032, x4)
+
+inst_272:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x4, -0xb504, x2, 1036, x4)
+
+inst_273:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x66666666, x2, 1040, x4)
+
+inst_274:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x33333333, x2, 1044, x4)
+
+inst_275:
+// rs1_val==4 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x5, x2, 1048, x4)
+
+inst_276:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x4, -0x55555556, x2, 1052, x4)
+
+inst_277:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x4, 0x55555555, x2, 1056, x4)
+
+inst_278:
+// rs1_val==4 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x4, 0x3, x2, 1060, x4)
+
+inst_279:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0xb505, x2, 1064, x4)
+
+inst_280:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb503, -0xb503, x2, 1068, x4)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0xb503, 0x66666667, x2, 1072, x4)
+
+inst_282:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0xb503, 0x33333334, x2, 1076, x4)
+
+inst_283:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x6, x2, 1080, x4)
+
+inst_284:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0xb503, -0x55555555, x2, 1084, x4)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb503, 0x55555556, x2, 1088, x4)
+
+inst_286:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x4, x2, 1092, x4)
+
+inst_287:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0xb503, x2, 1096, x4)
+
+inst_288:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x0, x2, 1100, x4)
+
+inst_289:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0xb503, 0x66666665, x2, 1104, x4)
+
+inst_290:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0xb503, 0x33333332, x2, 1108, x4)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb503, 0x55555554, x2, 1112, x4)
+
+inst_292:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x2, x2, 1116, x4)
+
+inst_293:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0xb504, x2, 1120, x4)
+
+inst_294:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb503, -0xb504, x2, 1124, x4)
+
+inst_295:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0xb503, 0x66666666, x2, 1128, x4)
+
+inst_296:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0xb503, 0x33333333, x2, 1132, x4)
+
+inst_297:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x5, x2, 1136, x4)
+
+inst_298:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0xb503, -0x55555556, x2, 1140, x4)
+
+inst_299:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb503, 0x55555555, x2, 1144, x4)
+
+inst_300:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb503, 0x3, x2, 1148, x4)
+
+inst_301:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0xb505, x2, 1152, x4)
+
+inst_302:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0xb503, x2, 1156, x4)
+
+inst_303:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x66666667, x2, 1160, x4)
+
+inst_304:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x33333334, x2, 1164, x4)
+
+inst_305:
+// rs1_val==0 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x6, x2, 1168, x4)
+
+inst_306:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0x55555555, x2, 1172, x4)
+
+inst_307:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x55555556, x2, 1176, x4)
+
+inst_308:
+// rs1_val==0 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x4, x2, 1180, x4)
+
+inst_309:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0xb503, x2, 1184, x4)
+
+inst_310:
+// rs1_val==0 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x0, x2, 1188, x4)
+
+inst_311:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x66666665, x2, 1192, x4)
+
+inst_312:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x33333332, x2, 1196, x4)
+
+inst_313:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x55555554, x2, 1200, x4)
+
+inst_314:
+// rs1_val==0 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x2, x2, 1204, x4)
+
+inst_315:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0xb504, x2, 1208, x4)
+
+inst_316:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0xb504, x2, 1212, x4)
+
+inst_317:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x66666666, x2, 1216, x4)
+
+inst_318:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x33333333, x2, 1220, x4)
+
+inst_319:
+// rs1_val==0 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x5, x2, 1224, x4)
+
+inst_320:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, -0x55555556, x2, 1228, x4)
+
+inst_321:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x55555555, x2, 1232, x4)
+
+inst_322:
+// rs1_val==0 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x0, 0x3, x2, 1236, x4)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0x66666665, 0xb505, x2, 1240, x4)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, 0x66666665, -0xb503, x2, 1244, x4)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666665, 0x66666667, x2, 1248, x4)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333334, x2, 1252, x4)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x66666665, 0x6, x2, 1256, x4)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, 0x66666665, -0x55555555, x2, 1260, x4)
+
+inst_329:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666665, 0x55555556, x2, 1264, x4)
+
+inst_330:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666665, 0x4, x2, 1268, x4)
+
+inst_331:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0x66666665, 0xb503, x2, 1272, x4)
+
+inst_332:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666665, 0x0, x2, 1276, x4)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333333, 0x0, x2, 1280, x4)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666665, x2, 1284, x4)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333332, x2, 1288, x4)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x33333333, 0x55555554, x2, 1292, x4)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333333, 0x2, x2, 1296, x4)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0x33333333, 0xb504, x2, 1300, x4)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, 0x33333333, -0xb504, x2, 1304, x4)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666666, x2, 1308, x4)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333333, x2, 1312, x4)
+
+inst_342:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333333, 0x5, x2, 1316, x4)
+
+inst_343:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, 0x33333333, -0x55555556, x2, 1320, x4)
+
+inst_344:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x33333333, 0x55555555, x2, 1324, x4)
+
+inst_345:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333333, 0x3, x2, 1328, x4)
+
+inst_346:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0xb505, x2, 1332, x4)
+
+inst_347:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x5, -0xb503, x2, 1336, x4)
+
+inst_348:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x5, 0x66666667, x2, 1340, x4)
+
+inst_349:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x33333334, x2, 1344, x4)
+
+inst_350:
+// rs1_val==5 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x6, x2, 1348, x4)
+
+inst_351:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x5, -0x55555555, x2, 1352, x4)
+
+inst_352:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x55555556, x2, 1356, x4)
+
+inst_353:
+// rs1_val==5 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x4, x2, 1360, x4)
+
+inst_354:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0xb503, x2, 1364, x4)
+
+inst_355:
+// rs1_val==5 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x0, x2, 1368, x4)
+
+inst_356:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x66666665, x2, 1372, x4)
+
+inst_357:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x33333332, x2, 1376, x4)
+
+inst_358:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x55555554, x2, 1380, x4)
+
+inst_359:
+// rs1_val==5 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x2, x2, 1384, x4)
+
+inst_360:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0xb504, x2, 1388, x4)
+
+inst_361:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x5, -0xb504, x2, 1392, x4)
+
+inst_362:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x66666666, x2, 1396, x4)
+
+inst_363:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x33333333, x2, 1400, x4)
+
+inst_364:
+// rs1_val==5 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x5, x2, 1404, x4)
+
+inst_365:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x5, -0x55555556, x2, 1408, x4)
+
+inst_366:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x5, 0x55555555, x2, 1412, x4)
+
+inst_367:
+// rs1_val==5 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x5, 0x3, x2, 1416, x4)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a8, -0x55555556, 0xb505, x2, 1420, x4)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0x55555556, -0xb503, x2, 1424, x4)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, -0x55555556, 0x66666667, x2, 1428, x4)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, -0x55555556, 0x33333334, x2, 1432, x4)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffd, -0x55555556, 0x6, x2, 1436, x4)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, -0x55555556, -0x55555555, x2, 1440, x4)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555556, x2, 1444, x4)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555556, 0x4, x2, 1448, x4)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0x55555556, 0xb503, x2, 1452, x4)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0x55555556, 0x0, x2, 1456, x4)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, -0x55555556, 0x66666665, x2, 1460, x4)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, -0x55555556, 0x33333332, x2, 1464, x4)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555554, x2, 1468, x4)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0x55555556, 0x2, x2, 1472, x4)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0x55555556, 0xb504, x2, 1476, x4)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0x55555556, -0xb504, x2, 1480, x4)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, -0x55555556, 0x66666666, x2, 1484, x4)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeee, -0x55555556, 0x33333333, x2, 1488, x4)
+
+inst_386:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555556, 0x5, x2, 1492, x4)
+
+inst_387:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, -0x55555556, -0x55555556, x2, 1496, x4)
+
+inst_388:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555555, x2, 1500, x4)
+
+inst_389:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, -0x55555556, 0x3, x2, 1504, x4)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555555, 0xb505, x2, 1508, x4)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555555, -0xb503, x2, 1512, x4)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x55555555, 0x66666667, x2, 1516, x4)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x55555555, 0x33333334, x2, 1520, x4)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555555, 0x6, x2, 1524, x4)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, 0x55555555, -0x55555555, x2, 1528, x4)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555556, x2, 1532, x4)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555555, 0x4, x2, 1536, x4)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555555, 0xb503, x2, 1540, x4)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555555, 0x0, x2, 1544, x4)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555555, 0x66666665, x2, 1548, x4)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x55555555, 0x33333332, x2, 1552, x4)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71b, 0x55555555, 0x55555554, x2, 1556, x4)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555555, 0x2, x2, 1560, x4)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555555, 0xb504, x2, 1564, x4)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555555, -0xb504, x2, 1568, x4)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555555, 0x66666666, x2, 1572, x4)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x55555555, 0x33333333, x2, 1576, x4)
+
+inst_408:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555555, 0x5, x2, 1580, x4)
+
+inst_409:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, 0x55555555, -0x55555556, x2, 1584, x4)
+
+inst_410:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555555, x2, 1588, x4)
+
+inst_411:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555555, 0x3, x2, 1592, x4)
+
+inst_412:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0xb505, x2, 1596, x4)
+
+inst_413:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x3, -0xb503, x2, 1600, x4)
+
+inst_414:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x3, 0x66666667, x2, 1604, x4)
+
+inst_415:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x33333334, x2, 1608, x4)
+
+inst_416:
+// rs1_val==3 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x6, x2, 1612, x4)
+
+inst_417:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x3, -0x55555555, x2, 1616, x4)
+
+inst_418:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x3, 0x55555556, x2, 1620, x4)
+
+inst_419:
+// rs1_val==3 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x4, x2, 1624, x4)
+
+inst_420:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0xb503, x2, 1628, x4)
+
+inst_421:
+// rs1_val==3 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x0, x2, 1632, x4)
+
+inst_422:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x3, 0x66666665, x2, 1636, x4)
+
+inst_423:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x33333332, x2, 1640, x4)
+
+inst_424:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x55555554, x2, 1644, x4)
+
+inst_425:
+// rs1_val==3 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x2, x2, 1648, x4)
+
+inst_426:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0xb504, x2, 1652, x4)
+
+inst_427:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x3, -0xb504, x2, 1656, x4)
+
+inst_428:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x3, 0x66666666, x2, 1660, x4)
+
+inst_429:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x33333333, x2, 1664, x4)
+
+inst_430:
+// rs1_val==3 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x5, x2, 1668, x4)
+
+inst_431:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xfffffffe, 0x3, -0x55555556, x2, 1672, x4)
+
+inst_432:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x55555555, x2, 1676, x4)
+
+inst_433:
+// rs1_val==3 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x3, 0x3, x2, 1680, x4)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666665, x2, 1684, x4)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae146, 0x66666665, 0x33333332, x2, 1688, x4)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666665, 0x55555554, x2, 1692, x4)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666665, 0x2, x2, 1696, x4)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0x66666665, 0xb504, x2, 1700, x4)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, 0x66666665, -0xb504, x2, 1704, x4)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666666, x2, 1708, x4)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333333, x2, 1712, x4)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666665, 0x5, x2, 1716, x4)
+
+inst_443:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, 0x66666665, -0x55555556, x2, 1720, x4)
+
+inst_444:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666665, 0x55555555, x2, 1724, x4)
+
+inst_445:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666665, 0x3, x2, 1728, x4)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0x33333332, 0xb505, x2, 1732, x4)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, 0x33333332, -0xb503, x2, 1736, x4)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666667, x2, 1740, x4)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333334, x2, 1744, x4)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x33333332, 0x6, x2, 1748, x4)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, 0x33333332, -0x55555555, x2, 1752, x4)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x33333332, 0x55555556, x2, 1756, x4)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333332, 0x4, x2, 1760, x4)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0x33333332, 0xb503, x2, 1764, x4)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333332, 0x0, x2, 1768, x4)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae146, 0x33333332, 0x66666665, x2, 1772, x4)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333332, x2, 1776, x4)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x33333332, 0x55555554, x2, 1780, x4)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333332, 0x2, x2, 1784, x4)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0x33333332, 0xb504, x2, 1788, x4)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, 0x33333332, -0xb504, x2, 1792, x4)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666666, x2, 1796, x4)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333333, x2, 1800, x4)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333332, 0x5, x2, 1804, x4)
+
+inst_465:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, 0x33333332, -0x55555556, x2, 1808, x4)
+
+inst_466:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x33333332, 0x55555555, x2, 1812, x4)
+
+inst_467:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333332, 0x3, x2, 1816, x4)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555554, 0xb505, x2, 1820, x4)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555554, -0xb503, x2, 1824, x4)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555554, 0x66666667, x2, 1828, x4)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x55555554, 0x33333334, x2, 1832, x4)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555554, 0x6, x2, 1836, x4)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e4, 0x55555554, -0x55555555, x2, 1840, x4)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71c, 0x55555554, 0x55555556, x2, 1844, x4)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555554, 0x4, x2, 1848, x4)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555554, 0xb503, x2, 1852, x4)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555554, 0x0, x2, 1856, x4)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555554, 0x66666665, x2, 1860, x4)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x55555554, 0x33333332, x2, 1864, x4)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555554, x2, 1868, x4)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555554, 0x2, x2, 1872, x4)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0x55555554, 0xb504, x2, 1876, x4)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0x55555554, -0xb504, x2, 1880, x4)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x55555554, 0x66666666, x2, 1884, x4)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111110, 0x55555554, 0x33333333, x2, 1888, x4)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x55555554, 0x5, x2, 1892, x4)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xe38e38e3, 0x55555554, -0x55555556, x2, 1896, x4)
+
+inst_488:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555555, x2, 1900, x4)
+
+inst_489:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x55555554, 0x3, x2, 1904, x4)
+
+inst_490:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0xb505, x2, 1908, x4)
+
+inst_491:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x2, -0xb503, x2, 1912, x4)
+
+inst_492:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x66666667, x2, 1916, x4)
+
+inst_493:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x33333334, x2, 1920, x4)
+
+inst_494:
+// rs1_val==2 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x6, x2, 1924, x4)
+
+inst_495:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x2, -0x55555555, x2, 1928, x4)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x55555556, x2, 1932, x4)
+
+inst_497:
+// rs1_val==2 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x4, x2, 1936, x4)
+
+inst_498:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0xb503, x2, 1940, x4)
+
+inst_499:
+// rs1_val==2 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x0, x2, 1944, x4)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x66666665, x2, 1948, x4)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x33333332, x2, 1952, x4)
+
+inst_502:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x55555554, x2, 1956, x4)
+
+inst_503:
+// rs1_val==2 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x2, x2, 1960, x4)
+
+inst_504:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0xb504, x2, 1964, x4)
+
+inst_505:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x2, -0xb504, x2, 1968, x4)
+
+inst_506:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x66666666, x2, 1972, x4)
+
+inst_507:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x33333333, x2, 1976, x4)
+
+inst_508:
+// rs1_val==2 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x5, x2, 1980, x4)
+
+inst_509:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x2, -0x55555556, x2, 1984, x4)
+
+inst_510:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x55555555, x2, 1988, x4)
+
+inst_511:
+// rs1_val==2 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x2, 0x3, x2, 1992, x4)
+
+inst_512:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0xb505, x2, 1996, x4)
+
+inst_513:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb504, -0xb503, x2, 2000, x4)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0xb504, 0x66666667, x2, 2004, x4)
+
+inst_515:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0xb504, 0x33333334, x2, 2008, x4)
+
+inst_516:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x6, x2, 2012, x4)
+
+inst_517:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0xb504, -0x55555555, x2, 2016, x4)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb504, 0x55555556, x2, 2020, x4)
+
+inst_519:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x4, x2, 2024, x4)
+
+inst_520:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0xb503, x2, 2028, x4)
+
+inst_521:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x0, x2, 2032, x4)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0xb504, 0x66666665, x2, 2036, x4)
+
+inst_523:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0xb504, 0x33333332, x2, 2040, x4)
+
+inst_524:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb504, 0x55555554, x2, 2044, x4)
+RVTEST_SIGBASE( x2,signature_x2_3)
+
+inst_525:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x2, x2, 0, x4)
+
+inst_526:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0xb504, x2, 4, x4)
+
+inst_527:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0xb504, -0xb504, x2, 8, x4)
+
+inst_528:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0xb504, 0x66666666, x2, 12, x4)
+
+inst_529:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0xb504, 0x33333333, x2, 16, x4)
+
+inst_530:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x5, x2, 20, x4)
+
+inst_531:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, 0xb504, -0x55555556, x2, 24, x4)
+
+inst_532:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, 0xb504, 0x55555555, x2, 28, x4)
+
+inst_533:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0xb504, 0x3, x2, 32, x4)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0xb505, x2, 36, x4)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb504, -0xb503, x2, 40, x4)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb797, -0xb504, 0x66666667, x2, 44, x4)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcb, -0xb504, 0x33333334, x2, 48, x4)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0x6, x2, 52, x4)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0xb504, -0x55555555, x2, 56, x4)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555556, x2, 60, x4)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0x4, x2, 64, x4)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0xb503, x2, 68, x4)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb504, 0x0, x2, 72, x4)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, -0xb504, 0x66666665, x2, 76, x4)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, -0xb504, 0x33333332, x2, 80, x4)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555554, x2, 84, x4)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0x2, x2, 88, x4)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0xb504, x2, 92, x4)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, -0xb504, -0xb504, x2, 96, x4)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, -0xb504, 0x66666666, x2, 100, x4)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, -0xb504, 0x33333333, x2, 104, x4)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0x5, x2, 108, x4)
+
+inst_553:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x3c56, -0xb504, -0x55555556, x2, 112, x4)
+
+inst_554:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555555, x2, 116, x4)
+
+inst_555:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, -0xb504, 0x3, x2, 120, x4)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x4868, 0x66666666, 0xb505, x2, 124, x4)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, 0x66666666, -0xb503, x2, 128, x4)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666667, x2, 132, x4)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333334, x2, 136, x4)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x2, 0x66666666, 0x6, x2, 140, x4)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xddddddde, 0x66666666, -0x55555555, x2, 144, x4)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222222, 0x66666666, 0x55555556, x2, 148, x4)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666666, 0x4, x2, 152, x4)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0x66666666, 0xb503, x2, 156, x4)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666666, 0x0, x2, 160, x4)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28e, 0x66666666, 0x66666665, x2, 164, x4)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333332, x2, 168, x4)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666666, 0x55555554, x2, 172, x4)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x66666666, 0x2, x2, 176, x4)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0x4867, 0x66666666, 0xb504, x2, 180, x4)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffb798, 0x66666666, -0xb504, x2, 184, x4)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(mulh, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666666, x2, 188, x4)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333333, x2, 192, x4)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666666, 0x5, x2, 196, x4)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0xdddddddd, 0x66666666, -0x55555556, x2, 200, x4)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0x22222221, 0x66666666, 0x55555555, x2, 204, x4)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x66666666, 0x3, x2, 208, x4)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(mulh, x12, x10, x11, 0x2434, 0x33333333, 0xb505, x2, 212, x4)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffdbcc, 0x33333333, -0xb503, x2, 216, x4)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(mulh, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666667, x2, 220, x4)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(mulh, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333334, x2, 224, x4)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(mulh, x12, x10, x11, 0x1, 0x33333333, 0x6, x2, 228, x4)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(mulh, x12, x10, x11, 0xeeeeeeef, 0x33333333, -0x55555555, x2, 232, x4)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(mulh, x12, x10, x11, 0x11111111, 0x33333333, 0x55555556, x2, 236, x4)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(mulh, x12, x10, x11, 0x0, 0x33333333, 0x4, x2, 240, x4)
+
+inst_586:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(mulh, x12, x10, x11, 0x2433, 0x33333333, 0xb503, x2, 244, x4)
+
+inst_587:
+// rs2_val == -536870913, rs1_val < 0 and rs2_val < 0, rs1_val == -4194305
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x20000001
+TEST_RR_OP(mulh, x12, x10, x11, 0x80000, -0x400001, -0x20000001, x2, 248, x4)
+
+inst_588:
+// rs2_val == -33554433, rs1_val == -4097
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:-0x2000001
+TEST_RR_OP(mulh, x12, x10, x11, 0x20, -0x1001, -0x2000001, x2, 252, x4)
+
+inst_589:
+// rs2_val == -8388609, rs1_val == 256
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:-0x800001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffffffff, 0x100, -0x800001, x2, 256, x4)
+
+inst_590:
+// rs2_val == -65537, 
+// opcode: mulh ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x10001
+TEST_RR_OP(mulh, x12, x10, x11, 0xffff9999, 0x66666667, -0x10001, x2, 260, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_2:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_3:
+    .fill 66*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhsu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhsu-01.S
new file mode 100644
index 000000000..e4b07c6e2
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhsu-01.S
@@ -0,0 +1,3355 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the mulhsu instruction of the RISC-V M extension for the mulhsu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",mulhsu)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x11, rs2==x15, rd==x15, rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0, rs1_val > 0 and rs2_val > 0, rs2_val == 131072
+// opcode: mulhsu ; op1:x11; op2:x15; dest:x15; op1val:0x55555556;  op2val:0x20000
+TEST_RR_OP(mulhsu, x15, x11, x15, 0xaaaa, 0x55555556, 0x20000, x4, 0, x7)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x6, rs2==x9, rd==x6, rs2_val == 2147483647, rs1_val == -1431655766
+// opcode: mulhsu ; op1:x6; op2:x9; dest:x6; op1val:-0x55555556;  op2val:0x7fffffff
+TEST_RR_OP(mulhsu, x6, x6, x9, 0xd5555555, -0x55555556, 0x7fffffff, x4, 4, x7)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8, rs2_val == 3221225471, rs1_val == 1048576
+// opcode: mulhsu ; op1:x8; op2:x8; dest:x8; op1val:0x100000;  op2val:0x100000
+TEST_RR_OP(mulhsu, x8, x8, x8, 0x100, 0x100000, 0x100000, x4, 8, x7)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x0, rs2==x0, rd==x11, rs2_val == 3758096383, 
+// opcode: mulhsu ; op1:x0; op2:x0; dest:x11; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mulhsu, x11, x0, x0, 0x0, 0x0, 0x0, x4, 12, x7)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x9, rs2==x12, rd==x13, rs2_val == 4026531839, rs1_val == -17
+// opcode: mulhsu ; op1:x9; op2:x12; dest:x13; op1val:-0x11;  op2val:0xefffffff
+TEST_RR_OP(mulhsu, x13, x9, x12, 0xfffffff0, -0x11, 0xefffffff, x4, 16, x7)
+
+inst_5:
+// rs1==x2, rs2==x14, rd==x0, rs2_val == 4160749567, 
+// opcode: mulhsu ; op1:x2; op2:x14; dest:x0; op1val:0x5;  op2val:0xf7ffffff
+TEST_RR_OP(mulhsu, x0, x2, x14, 0, 0x5, 0xf7ffffff, x4, 20, x7)
+
+inst_6:
+// rs1==x3, rs2==x11, rd==x12, rs2_val == 4227858431, rs1_val == -1025
+// opcode: mulhsu ; op1:x3; op2:x11; dest:x12; op1val:-0x401;  op2val:0xfbffffff
+TEST_RR_OP(mulhsu, x12, x3, x11, 0xfffffc0f, -0x401, 0xfbffffff, x4, 24, x7)
+
+inst_7:
+// rs1==x5, rs2==x13, rd==x1, rs2_val == 4261412863, rs1_val == 2
+// opcode: mulhsu ; op1:x5; op2:x13; dest:x1; op1val:0x2;  op2val:0xfdffffff
+TEST_RR_OP(mulhsu, x1, x5, x13, 0x1, 0x2, 0xfdffffff, x4, 28, x7)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_8:
+// rs1==x15, rs2==x7, rd==x4, rs2_val == 4278190079, rs1_val == -2
+// opcode: mulhsu ; op1:x15; op2:x7; dest:x4; op1val:-0x2;  op2val:0xfeffffff
+TEST_RR_OP(mulhsu, x4, x15, x7, 0xfffffffe, -0x2, 0xfeffffff, x3, 0, x8)
+
+inst_9:
+// rs1==x7, rs2==x10, rd==x9, rs2_val == 4286578687, rs1_val == 524288
+// opcode: mulhsu ; op1:x7; op2:x10; dest:x9; op1val:0x80000;  op2val:0xff7fffff
+TEST_RR_OP(mulhsu, x9, x7, x10, 0x7fbff, 0x80000, 0xff7fffff, x3, 4, x8)
+
+inst_10:
+// rs1==x14, rs2==x2, rd==x5, rs2_val == 4290772991, rs1_val == 512
+// opcode: mulhsu ; op1:x14; op2:x2; dest:x5; op1val:0x200;  op2val:0xffbfffff
+TEST_RR_OP(mulhsu, x5, x14, x2, 0x1ff, 0x200, 0xffbfffff, x3, 8, x8)
+
+inst_11:
+// rs1==x1, rs2==x4, rd==x10, rs2_val == 4292870143, rs1_val == 1431655765
+// opcode: mulhsu ; op1:x1; op2:x4; dest:x10; op1val:0x55555555;  op2val:0xffdfffff
+TEST_RR_OP(mulhsu, x10, x1, x4, 0x554aaaaa, 0x55555555, 0xffdfffff, x3, 12, x8)
+
+inst_12:
+// rs1==x12, rs2==x6, rd==x2, rs2_val == 4293918719, 
+// opcode: mulhsu ; op1:x12; op2:x6; dest:x2; op1val:0x55555556;  op2val:0xffefffff
+TEST_RR_OP(mulhsu, x2, x12, x6, 0x55500000, 0x55555556, 0xffefffff, x3, 16, x8)
+
+inst_13:
+// rs1==x13, rs2==x1, rd==x14, rs2_val == 4294443007, 
+// opcode: mulhsu ; op1:x13; op2:x1; dest:x14; op1val:-0x401;  op2val:0xfff7ffff
+TEST_RR_OP(mulhsu, x14, x13, x1, 0xfffffbff, -0x401, 0xfff7ffff, x3, 20, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_14:
+// rs1==x4, rs2==x5, rd==x3, rs2_val == 4294705151, rs1_val == -1073741825
+// opcode: mulhsu ; op1:x4; op2:x5; dest:x3; op1val:-0x40000001;  op2val:0xfffbffff
+TEST_RR_OP(mulhsu, x3, x4, x5, 0xc000ffff, -0x40000001, 0xfffbffff, x1, 0, x2)
+
+inst_15:
+// rs1==x10, rs2==x3, rd==x7, rs2_val == 4294836223, rs1_val == 0
+// opcode: mulhsu ; op1:x10; op2:x3; dest:x7; op1val:0x0;  op2val:0xfffdffff
+TEST_RR_OP(mulhsu, x7, x10, x3, 0x0, 0x0, 0xfffdffff, x1, 4, x2)
+
+inst_16:
+// rs2_val == 4294901759, rs1_val == -5
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0xfffeffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffb, -0x5, 0xfffeffff, x1, 8, x2)
+
+inst_17:
+// rs2_val == 4294934527, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff7fff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xb503, 0xb504, 0xffff7fff, x1, 12, x2)
+
+inst_18:
+// rs2_val == 4294950911, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffffbfff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x3, 0xffffbfff, x1, 16, x2)
+
+inst_19:
+// rs2_val == 4294959103, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:0xffffdfff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffff9, -0x7, 0xffffdfff, x1, 20, x2)
+
+inst_20:
+// rs2_val == 4294963199, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffffefff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xb504, 0xb505, 0xffffefff, x1, 24, x2)
+
+inst_21:
+// rs2_val == 4294965247, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xfffff7ff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xaaaaad55, -0x55555556, 0xfffff7ff, x1, 28, x2)
+
+inst_22:
+// rs2_val == 4294966271, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0xfffffbff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x2, 0xfffffbff, x1, 32, x2)
+
+inst_23:
+// rs2_val == 4294966783, rs1_val == -65537
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0xfffffdff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffeffff, -0x10001, 0xfffffdff, x1, 36, x2)
+
+inst_24:
+// rs2_val == 4294967039, rs1_val == 67108864
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xfffffeff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3fffffb, 0x4000000, 0xfffffeff, x1, 40, x2)
+
+inst_25:
+// rs2_val == 4294967167, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffffff7f
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x66666632, 0x66666666, 0xffffff7f, x1, 44, x2)
+
+inst_26:
+// rs2_val == 4294967231, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffffffbf
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x3, 0xffffffbf, x1, 48, x2)
+
+inst_27:
+// rs2_val == 4294967263, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffffffdf
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x66666658, 0x66666666, 0xffffffdf, x1, 52, x2)
+
+inst_28:
+// rs2_val == 4294967279, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffffffef
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5, 0x6, 0xffffffef, x1, 56, x2)
+
+inst_29:
+// rs2_val == 4294967287, rs1_val == -268435457
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0xfffffff7
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xefffffff, -0x10000001, 0xfffffff7, x1, 60, x2)
+
+inst_30:
+// rs2_val == 4294967291, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xfffffffb
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff4afd, -0xb503, 0xfffffffb, x1, 64, x2)
+
+inst_31:
+// rs2_val == 4294967293, rs1_val == 4
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffffffd
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x4, 0xfffffffd, x1, 68, x2)
+
+inst_32:
+// rs2_val == 4294967294, rs1_val == -134217729
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:0xfffffffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xf7ffffff, -0x8000001, 0xfffffffe, x1, 72, x2)
+
+inst_33:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0xffefffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x7ff7fffe, 0x7fffffff, 0xffefffff, x1, 76, x2)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0xa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x20000001, 0xa, x1, 80, x2)
+
+inst_35:
+// rs1_val == -67108865, rs2_val == 8
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x8
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x4000001, 0x8, x1, 84, x2)
+
+inst_36:
+// rs1_val == -33554433, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x7
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x2000001, 0x7, x1, 88, x2)
+
+inst_37:
+// rs1_val == -16777217, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0xfffffdff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xff000001, -0x1000001, 0xfffffdff, x1, 92, x2)
+
+inst_38:
+// rs1_val == -8388609, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:0xfffff7ff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xff800003, -0x800001, 0xfffff7ff, x1, 96, x2)
+
+inst_39:
+// rs1_val == -4194305, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffc0, -0x400001, 0xfffe, x1, 100, x2)
+
+inst_40:
+// rs1_val == -2097153, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0xefffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffe1ffff, -0x200001, 0xefffffff, x1, 104, x2)
+
+inst_41:
+// rs1_val == -1048577, rs2_val == 4096
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x1000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x100001, 0x1000, x1, 108, x2)
+
+inst_42:
+// rs1_val == -524289, rs2_val == 2097152
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0x200000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffeff, -0x80001, 0x200000, x1, 112, x2)
+
+inst_43:
+// rs1_val == -262145, rs2_val == 33554432
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x2000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffff7ff, -0x40001, 0x2000000, x1, 116, x2)
+
+inst_44:
+// rs1_val == -131073, rs2_val == 8192
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x2000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x20001, 0x2000, x1, 120, x2)
+
+inst_45:
+// rs1_val == -32769, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x1000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x8001, 0x1000, x1, 124, x2)
+
+inst_46:
+// rs1_val == -16385, rs2_val == 256
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x100
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x4001, 0x100, x1, 128, x2)
+
+inst_47:
+// rs1_val == -8193, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0xffffdfff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdfff, -0x2001, 0xffffdfff, x1, 132, x2)
+
+inst_48:
+// rs1_val == -4097, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x1001, 0xb504, x1, 136, x2)
+
+inst_49:
+// rs1_val == -2049, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0xfffffffb
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffff7ff, -0x801, 0xfffffffb, x1, 140, x2)
+
+inst_50:
+// rs1_val == -513, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0xfffffbff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffdff, -0x201, 0xfffffbff, x1, 144, x2)
+
+inst_51:
+// rs1_val == -257, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0xffffff7f
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffeff, -0x101, 0xffffff7f, x1, 148, x2)
+
+inst_52:
+// rs1_val == -129, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0xf
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x81, 0xf, x1, 152, x2)
+
+inst_53:
+// rs1_val == -65, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0xffffffdf
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffbf, -0x41, 0xffffffdf, x1, 156, x2)
+
+inst_54:
+// rs1_val == -33, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0xfbffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffdf, -0x21, 0xfbffffff, x1, 160, x2)
+
+inst_55:
+// rs1_val == -9, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffd, -0x9, 0x55555554, x1, 164, x2)
+
+inst_56:
+// rs1_val == -3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0xfff7ffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffd, -0x3, 0xfff7ffff, x1, 168, x2)
+
+inst_57:
+// rs2_val == 2147483648, rs1_val == 128
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x80000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x40, 0x80, 0x80000000, x1, 172, x2)
+
+inst_58:
+// rs2_val == 1073741824, rs1_val == 4096
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x40000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x400, 0x1000, 0x40000000, x1, 176, x2)
+
+inst_59:
+// rs2_val == 536870912, rs1_val == 1073741824
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x20000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x8000000, 0x40000000, 0x20000000, x1, 180, x2)
+
+inst_60:
+// rs2_val == 268435456, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0x10000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff7fff, -0x80001, 0x10000000, x1, 184, x2)
+
+inst_61:
+// rs2_val == 134217728, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x8000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffbf, -0x801, 0x8000000, x1, 188, x2)
+
+inst_62:
+// rs2_val == 67108864, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1555555, 0x55555556, 0x4000000, x1, 192, x2)
+
+inst_63:
+// rs2_val == 16777216, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x1000000, x1, 196, x2)
+
+inst_64:
+// rs2_val == 8388608, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x800000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x201, 0x800000, x1, 200, x2)
+
+inst_65:
+// rs2_val == 4194304, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x400000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xccccc, 0x33333334, 0x400000, x1, 204, x2)
+
+inst_66:
+// rs2_val == 1048576, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x100000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x200, 0x100000, x1, 208, x2)
+
+inst_67:
+// rs2_val == 524288, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x80000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2aaaa, 0x55555555, 0x80000, x1, 212, x2)
+
+inst_68:
+// rs2_val == 262144, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x40000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x15555, 0x55555554, 0x40000, x1, 216, x2)
+
+inst_69:
+// rs2_val == 65536, rs1_val == 134217728
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x800, 0x8000000, 0x10000, x1, 220, x2)
+
+inst_70:
+// rs2_val == 32768, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x8000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffdff, -0x4000001, 0x8000, x1, 224, x2)
+
+inst_71:
+// rs2_val == 16384, rs1_val == 1024
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x4000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x400, 0x4000, x1, 228, x2)
+
+inst_72:
+// rs2_val == 2048, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x800
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x800, x1, 232, x2)
+
+inst_73:
+// rs2_val == 1024, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x400
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x400, x1, 236, x2)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x200
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x11, 0x200, x1, 240, x2)
+
+inst_75:
+// rs2_val == 128, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x80
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x801, 0x80, x1, 244, x2)
+
+inst_76:
+// rs2_val == 64, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x40
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x19, 0x66666665, 0x40, x1, 248, x2)
+
+inst_77:
+// rs2_val == 32, rs1_val == 64
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x20
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x40, 0x20, x1, 252, x2)
+
+inst_78:
+// rs2_val == 16, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x10
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffd, -0x20000001, 0x10, x1, 256, x2)
+
+inst_79:
+// rs2_val == 4, rs1_val==858993458 and rs2_val==4
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x4, x1, 260, x2)
+
+inst_80:
+// rs2_val == 2, rs1_val==0 and rs2_val==2
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x2, x1, 264, x2)
+
+inst_81:
+// rs2_val == 1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x7fffffff, 0x1, x1, 268, x2)
+
+inst_82:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x100
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffff80, -0x80000000, 0x100, x1, 272, x2)
+
+inst_83:
+// rs1_val == 536870912, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x20000000, 0x9, x1, 276, x2)
+
+inst_84:
+// rs1_val == 268435456, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x400000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x40000, 0x10000000, 0x400000, x1, 280, x2)
+
+inst_85:
+// rs1_val == 33554432, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2000000, 0x6, x1, 284, x2)
+
+inst_86:
+// rs1_val == 16777216, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x100
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x1000000, 0x100, x1, 288, x2)
+
+inst_87:
+// rs1_val == 8388608, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2aaaaa, 0x800000, 0x55555556, x1, 292, x2)
+
+inst_88:
+// rs1_val == 4194304, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xfff7ffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3ffdff, 0x400000, 0xfff7ffff, x1, 296, x2)
+
+inst_89:
+// rs1_val == 2097152, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0xffff7fff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1fffef, 0x200000, 0xffff7fff, x1, 300, x2)
+
+inst_90:
+// rs1_val == 262144, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x100000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x40, 0x40000, 0x100000, x1, 304, x2)
+
+inst_91:
+// rs1_val == 131072, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0xffffffef
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1ffff, 0x20000, 0xffffffef, x1, 308, x2)
+
+inst_92:
+// rs1_val == 65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x10000, 0x6, x1, 312, x2)
+
+inst_93:
+// rs1_val == 32768, rs2_val == 1431655765
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2aaa, 0x8000, 0x55555555, x1, 316, x2)
+
+inst_94:
+// rs1_val == 16384, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xb
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4000, 0xb, x1, 320, x2)
+
+inst_95:
+// rs1_val == 8192, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x200
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2000, 0x200, x1, 324, x2)
+
+inst_96:
+// rs1_val == 2048, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x800, 0x10000, x1, 328, x2)
+
+inst_97:
+// rs1_val == 256, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x100, 0x4, x1, 332, x2)
+
+inst_98:
+// rs1_val == 32, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x4000000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x20, 0x4000000, x1, 336, x2)
+
+inst_99:
+// rs1_val == 16, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x10, 0x10000, x1, 340, x2)
+
+inst_100:
+// rs1_val == 8, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0xfffffff7
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x7, 0x8, 0xfffffff7, x1, 344, x2)
+
+inst_101:
+// rs1_val == 1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffefffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x1, 0xffefffff, x1, 348, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x10000, x1, 352, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x1, x1, 356, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0xb505, x1, 360, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0xb505, 0x66666667, x1, 364, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0xb505, 0x33333334, x1, 368, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x6, x1, 372, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ae, 0xb505, 0xaaaaaaab, x1, 376, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c57, 0xb505, 0x55555556, x1, 380, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x4, x1, 384, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0xfffe, x1, 388, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==0, rs2_val == 0
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x0, x1, 392, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0xb503, x1, 396, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0xb505, 0x66666665, x1, 400, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0xb505, 0x33333332, x1, 404, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ad, 0xb505, 0xaaaaaaa9, x1, 408, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb505, 0x55555554, x1, 412, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x2, x1, 416, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0xffff, x1, 420, x2)
+
+inst_120:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0xb504, x1, 424, x2)
+
+inst_121:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0xb505, 0x66666666, x1, 428, x2)
+
+inst_122:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0xb505, 0x33333333, x1, 432, x2)
+
+inst_123:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x5, x1, 436, x2)
+
+inst_124:
+// rs1_val==46341 and rs2_val==2863311530, rs2_val == 2863311530
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ad, 0xb505, 0xaaaaaaaa, x1, 440, x2)
+
+inst_125:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb505, 0x55555555, x1, 444, x2)
+
+inst_126:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb505, 0x3, x1, 448, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x10000, x1, 452, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x1, x1, 456, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0xb505, x1, 460, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb798, -0xb503, 0x66666667, x1, 464, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333334, x1, 468, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x6, x1, 472, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8753, -0xb503, 0xaaaaaaab, x1, 476, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555556, x1, 480, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x4, x1, 484, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0xfffe, x1, 488, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, -0xb503, 0x0, x1, 492, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0xb503, x1, 496, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb798, -0xb503, 0x66666665, x1, 500, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333332, x1, 504, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8753, -0xb503, 0xaaaaaaa9, x1, 508, x2)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555554, x1, 512, x2)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x2, x1, 516, x2)
+
+inst_144:
+// rs1_val==-46339 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0xffff, x1, 520, x2)
+
+inst_145:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0xb504, x1, 524, x2)
+
+inst_146:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb798, -0xb503, 0x66666666, x1, 528, x2)
+
+inst_147:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcc, -0xb503, 0x33333333, x1, 532, x2)
+
+inst_148:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x5, x1, 536, x2)
+
+inst_149:
+// rs1_val==-46339 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8753, -0xb503, 0xaaaaaaaa, x1, 540, x2)
+
+inst_150:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb503, 0x55555555, x1, 544, x2)
+
+inst_151:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb503, 0x3, x1, 548, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6666, 0x66666667, 0x10000, x1, 552, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666667, 0x1, x1, 556, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0x66666667, 0xb505, x1, 560, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666667, x1, 564, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae148, 0x66666667, 0x33333334, x1, 568, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x66666667, 0x6, x1, 572, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444444, 0x66666667, 0xaaaaaaab, x1, 576, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x66666667, 0x55555556, x1, 580, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666667, 0x4, x1, 584, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6665, 0x66666667, 0xfffe, x1, 588, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666667, 0x0, x1, 592, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0x66666667, 0xb503, x1, 596, x2)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666665, x1, 600, x2)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333332, x1, 604, x2)
+
+inst_166:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444443, 0x66666667, 0xaaaaaaa9, x1, 608, x2)
+
+inst_167:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666667, 0x55555554, x1, 612, x2)
+
+inst_168:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666667, 0x2, x1, 616, x2)
+
+inst_169:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6666, 0x66666667, 0xffff, x1, 620, x2)
+
+inst_170:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0x66666667, 0xb504, x1, 624, x2)
+
+inst_171:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666666, x1, 628, x2)
+
+inst_172:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333333, x1, 632, x2)
+
+inst_173:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x66666667, 0x5, x1, 636, x2)
+
+inst_174:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444444, 0x66666667, 0xaaaaaaaa, x1, 640, x2)
+
+inst_175:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x66666667, 0x55555555, x1, 644, x2)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666667, 0x3, x1, 648, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3333, 0x33333334, 0x10000, x1, 652, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333334, 0x1, x1, 656, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0x33333334, 0xb505, x1, 660, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae148, 0x33333334, 0x66666667, x1, 664, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a4, 0x33333334, 0x33333334, x1, 668, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x33333334, 0x6, x1, 672, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaab, x1, 676, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555556, x1, 680, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333334, 0x4, x1, 684, x2)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3332, 0x33333334, 0xfffe, x1, 688, x2)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333334, 0x0, x1, 692, x2)
+
+inst_188:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0x33333334, 0xb503, x1, 696, x2)
+
+inst_189:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666665, x1, 700, x2)
+
+inst_190:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333332, x1, 704, x2)
+
+inst_191:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaa9, x1, 708, x2)
+
+inst_192:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555554, x1, 712, x2)
+
+inst_193:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333334, 0x2, x1, 716, x2)
+
+inst_194:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3333, 0x33333334, 0xffff, x1, 720, x2)
+
+inst_195:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0x33333334, 0xb504, x1, 724, x2)
+
+inst_196:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666666, x1, 728, x2)
+
+inst_197:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333333, x1, 732, x2)
+
+inst_198:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x33333334, 0x5, x1, 736, x2)
+
+inst_199:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaaa, x1, 740, x2)
+
+inst_200:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555555, x1, 744, x2)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333334, 0x3, x1, 748, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x10000, x1, 752, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x1, x1, 756, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0xb505, x1, 760, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x6, 0x66666667, x1, 764, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x6, 0x33333334, x1, 768, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x6, x1, 772, x2)
+
+inst_208:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4, 0x6, 0xaaaaaaab, x1, 776, x2)
+
+inst_209:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x6, 0x55555556, x1, 780, x2)
+
+inst_210:
+// rs1_val==6 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x4, x1, 784, x2)
+
+inst_211:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0xfffe, x1, 788, x2)
+
+inst_212:
+// rs1_val==6 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x0, x1, 792, x2)
+
+inst_213:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0xb503, x1, 796, x2)
+
+inst_214:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x6, 0x66666665, x1, 800, x2)
+
+inst_215:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x6, 0x33333332, x1, 804, x2)
+
+inst_216:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x6, 0xaaaaaaa9, x1, 808, x2)
+
+inst_217:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x6, 0x55555554, x1, 812, x2)
+
+inst_218:
+// rs1_val==6 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x2, x1, 816, x2)
+
+inst_219:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0xffff, x1, 820, x2)
+
+inst_220:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0xb504, x1, 824, x2)
+
+inst_221:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x6, 0x66666666, x1, 828, x2)
+
+inst_222:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x6, 0x33333333, x1, 832, x2)
+
+inst_223:
+// rs1_val==6 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x5, x1, 836, x2)
+
+inst_224:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x6, 0xaaaaaaaa, x1, 840, x2)
+
+inst_225:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x6, 0x55555555, x1, 844, x2)
+
+inst_226:
+// rs1_val==6 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x6, 0x3, x1, 848, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaaa, -0x55555555, 0x10000, x1, 852, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x55555555, 0x1, x1, 856, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb505, x1, 860, x2)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xdddddddd, -0x55555555, 0x66666667, x1, 864, x2)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeee, -0x55555555, 0x33333334, x1, 868, x2)
+
+inst_232:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555555, 0x6, x1, 872, x2)
+
+inst_233:
+// rs1_val==-1431655765 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c7, -0x55555555, 0xaaaaaaab, x1, 876, x2)
+
+inst_234:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e3, -0x55555555, 0x55555556, x1, 880, x2)
+
+inst_235:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555555, 0x4, x1, 884, x2)
+
+inst_236:
+// rs1_val==-1431655765 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaab, -0x55555555, 0xfffe, x1, 888, x2)
+
+inst_237:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, -0x55555555, 0x0, x1, 892, x2)
+
+inst_238:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb503, x1, 896, x2)
+
+inst_239:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xddddddde, -0x55555555, 0x66666665, x1, 900, x2)
+
+inst_240:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x33333332, x1, 904, x2)
+
+inst_241:
+// rs1_val==-1431655765 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c7, -0x55555555, 0xaaaaaaa9, x1, 908, x2)
+
+inst_242:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e4, -0x55555555, 0x55555554, x1, 912, x2)
+
+inst_243:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x55555555, 0x2, x1, 916, x2)
+
+inst_244:
+// rs1_val==-1431655765 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaab, -0x55555555, 0xffff, x1, 920, x2)
+
+inst_245:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0x55555555, 0xb504, x1, 924, x2)
+
+inst_246:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xddddddde, -0x55555555, 0x66666666, x1, 928, x2)
+
+inst_247:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x33333333, x1, 932, x2)
+
+inst_248:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555555, 0x5, x1, 936, x2)
+
+inst_249:
+// rs1_val==-1431655765 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c7, -0x55555555, 0xaaaaaaaa, x1, 940, x2)
+
+inst_250:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e3, -0x55555555, 0x55555555, x1, 944, x2)
+
+inst_251:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x55555555, 0x3, x1, 948, x2)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5555, 0x55555556, 0x10000, x1, 952, x2)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555556, 0x1, x1, 956, x2)
+
+inst_254:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c57, 0x55555556, 0xb505, x1, 960, x2)
+
+inst_255:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x55555556, 0x66666667, x1, 964, x2)
+
+inst_256:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x55555556, 0x33333334, x1, 968, x2)
+
+inst_257:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x55555556, 0x6, x1, 972, x2)
+
+inst_258:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e39, 0x55555556, 0xaaaaaaab, x1, 976, x2)
+
+inst_259:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555556, x1, 980, x2)
+
+inst_260:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555556, 0x4, x1, 984, x2)
+
+inst_261:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5554, 0x55555556, 0xfffe, x1, 988, x2)
+
+inst_262:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555556, 0x0, x1, 992, x2)
+
+inst_263:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555556, 0xb503, x1, 996, x2)
+
+inst_264:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555556, 0x66666665, x1, 1000, x2)
+
+inst_265:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x55555556, 0x33333332, x1, 1004, x2)
+
+inst_266:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e38, 0x55555556, 0xaaaaaaa9, x1, 1008, x2)
+
+inst_267:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555554, x1, 1012, x2)
+
+inst_268:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555556, 0x2, x1, 1016, x2)
+
+inst_269:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5555, 0x55555556, 0xffff, x1, 1020, x2)
+
+inst_270:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555556, 0xb504, x1, 1024, x2)
+
+inst_271:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x55555556, 0x66666666, x1, 1028, x2)
+
+inst_272:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x55555556, 0x33333333, x1, 1032, x2)
+
+inst_273:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555556, 0x5, x1, 1036, x2)
+
+inst_274:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e39, 0x55555556, 0xaaaaaaaa, x1, 1040, x2)
+
+inst_275:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555555, x1, 1044, x2)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555556, 0x3, x1, 1048, x2)
+
+inst_277:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x10000, x1, 1052, x2)
+
+inst_278:
+// rs1_val==4 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x1, x1, 1056, x2)
+
+inst_279:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0xb505, x1, 1060, x2)
+
+inst_280:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x66666667, x1, 1064, x2)
+
+inst_281:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x33333334, x1, 1068, x2)
+
+inst_282:
+// rs1_val==4 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x6, x1, 1072, x2)
+
+inst_283:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaab, x1, 1076, x2)
+
+inst_284:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x55555556, x1, 1080, x2)
+
+inst_285:
+// rs1_val==4 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x4, x1, 1084, x2)
+
+inst_286:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0xfffe, x1, 1088, x2)
+
+inst_287:
+// rs1_val==4 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x0, x1, 1092, x2)
+
+inst_288:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0xb503, x1, 1096, x2)
+
+inst_289:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x66666665, x1, 1100, x2)
+
+inst_290:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x33333332, x1, 1104, x2)
+
+inst_291:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaa9, x1, 1108, x2)
+
+inst_292:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x55555554, x1, 1112, x2)
+
+inst_293:
+// rs1_val==4 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x2, x1, 1116, x2)
+
+inst_294:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0xffff, x1, 1120, x2)
+
+inst_295:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0xb504, x1, 1124, x2)
+
+inst_296:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x66666666, x1, 1128, x2)
+
+inst_297:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x33333333, x1, 1132, x2)
+
+inst_298:
+// rs1_val==4 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x5, x1, 1136, x2)
+
+inst_299:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaaa, x1, 1140, x2)
+
+inst_300:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x4, 0x55555555, x1, 1144, x2)
+
+inst_301:
+// rs1_val==4 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x4, 0x3, x1, 1148, x2)
+
+inst_302:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x10000, x1, 1152, x2)
+
+inst_303:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x1, x1, 1156, x2)
+
+inst_304:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0xb505, x1, 1160, x2)
+
+inst_305:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0xb503, 0x66666667, x1, 1164, x2)
+
+inst_306:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0xb503, 0x33333334, x1, 1168, x2)
+
+inst_307:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x6, x1, 1172, x2)
+
+inst_308:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaab, x1, 1176, x2)
+
+inst_309:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb503, 0x55555556, x1, 1180, x2)
+
+inst_310:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x4, x1, 1184, x2)
+
+inst_311:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0xfffe, x1, 1188, x2)
+
+inst_312:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x0, x1, 1192, x2)
+
+inst_313:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0xb503, x1, 1196, x2)
+
+inst_314:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0xb503, 0x66666665, x1, 1200, x2)
+
+inst_315:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0xb503, 0x33333332, x1, 1204, x2)
+
+inst_316:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaa9, x1, 1208, x2)
+
+inst_317:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb503, 0x55555554, x1, 1212, x2)
+
+inst_318:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x2, x1, 1216, x2)
+
+inst_319:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0xffff, x1, 1220, x2)
+
+inst_320:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0xb504, x1, 1224, x2)
+
+inst_321:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0xb503, 0x66666666, x1, 1228, x2)
+
+inst_322:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0xb503, 0x33333333, x1, 1232, x2)
+
+inst_323:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x5, x1, 1236, x2)
+
+inst_324:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaaa, x1, 1240, x2)
+
+inst_325:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb503, 0x55555555, x1, 1244, x2)
+
+inst_326:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb503, 0x3, x1, 1248, x2)
+
+inst_327:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x10000, x1, 1252, x2)
+
+inst_328:
+// rs1_val==0 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x1, x1, 1256, x2)
+
+inst_329:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1260, x2)
+
+inst_330:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1264, x2)
+
+inst_331:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1268, x2)
+
+inst_332:
+// rs1_val==0 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1272, x2)
+
+inst_333:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaab, x1, 1276, x2)
+
+inst_334:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1280, x2)
+
+inst_335:
+// rs1_val==0 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1284, x2)
+
+inst_336:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xfffe, x1, 1288, x2)
+
+inst_337:
+// rs1_val==0 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1292, x2)
+
+inst_338:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1296, x2)
+
+inst_339:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1300, x2)
+
+inst_340:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1304, x2)
+
+inst_341:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaa9, x1, 1308, x2)
+
+inst_342:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1312, x2)
+
+inst_343:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xffff, x1, 1316, x2)
+
+inst_344:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1320, x2)
+
+inst_345:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1324, x2)
+
+inst_346:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1328, x2)
+
+inst_347:
+// rs1_val==0 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1332, x2)
+
+inst_348:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaaa, x1, 1336, x2)
+
+inst_349:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1340, x2)
+
+inst_350:
+// rs1_val==0 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1344, x2)
+
+inst_351:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6666, 0x66666665, 0x10000, x1, 1348, x2)
+
+inst_352:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666665, 0x1, x1, 1352, x2)
+
+inst_353:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0x66666665, 0xb505, x1, 1356, x2)
+
+inst_354:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666665, 0x66666667, x1, 1360, x2)
+
+inst_355:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333334, x1, 1364, x2)
+
+inst_356:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x66666665, 0x6, x1, 1368, x2)
+
+inst_357:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444443, 0x66666665, 0xaaaaaaab, x1, 1372, x2)
+
+inst_358:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555556, x1, 1376, x2)
+
+inst_359:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666665, 0x4, x1, 1380, x2)
+
+inst_360:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6665, 0x66666665, 0xfffe, x1, 1384, x2)
+
+inst_361:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666665, 0x0, x1, 1388, x2)
+
+inst_362:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0x66666665, 0xb503, x1, 1392, x2)
+
+inst_363:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666665, x1, 1396, x2)
+
+inst_364:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae146, 0x66666665, 0x33333332, x1, 1400, x2)
+
+inst_365:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444442, 0x66666665, 0xaaaaaaa9, x1, 1404, x2)
+
+inst_366:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555554, x1, 1408, x2)
+
+inst_367:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666665, 0x2, x1, 1412, x2)
+
+inst_368:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6665, 0x66666665, 0xffff, x1, 1416, x2)
+
+inst_369:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0x66666665, 0xb504, x1, 1420, x2)
+
+inst_370:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666666, x1, 1424, x2)
+
+inst_371:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333333, x1, 1428, x2)
+
+inst_372:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666665, 0x5, x1, 1432, x2)
+
+inst_373:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444443, 0x66666665, 0xaaaaaaaa, x1, 1436, x2)
+
+inst_374:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555555, x1, 1440, x2)
+
+inst_375:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666665, 0x3, x1, 1444, x2)
+
+inst_376:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3333, 0x33333332, 0x10000, x1, 1448, x2)
+
+inst_377:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x1, x1, 1452, x2)
+
+inst_378:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0x33333332, 0xb505, x1, 1456, x2)
+
+inst_379:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666667, x1, 1460, x2)
+
+inst_380:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333334, x1, 1464, x2)
+
+inst_381:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x33333332, 0x6, x1, 1468, x2)
+
+inst_382:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaab, x1, 1472, x2)
+
+inst_383:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555556, x1, 1476, x2)
+
+inst_384:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3332, 0x33333332, 0xfffe, x1, 1480, x2)
+
+inst_385:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x0, x1, 1484, x2)
+
+inst_386:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0x33333332, 0xb503, x1, 1488, x2)
+
+inst_387:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae146, 0x33333332, 0x66666665, x1, 1492, x2)
+
+inst_388:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333332, x1, 1496, x2)
+
+inst_389:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaa9, x1, 1500, x2)
+
+inst_390:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555554, x1, 1504, x2)
+
+inst_391:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x2, x1, 1508, x2)
+
+inst_392:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3332, 0x33333332, 0xffff, x1, 1512, x2)
+
+inst_393:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0x33333332, 0xb504, x1, 1516, x2)
+
+inst_394:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666666, x1, 1520, x2)
+
+inst_395:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333333, x1, 1524, x2)
+
+inst_396:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x4, x1, 1528, x2)
+
+inst_397:
+// rs1_val==-46340 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0xfffe, x1, 1532, x2)
+
+inst_398:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, -0xb504, 0x0, x1, 1536, x2)
+
+inst_399:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 1540, x2)
+
+inst_400:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb798, -0xb504, 0x66666665, x1, 1544, x2)
+
+inst_401:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcc, -0xb504, 0x33333332, x1, 1548, x2)
+
+inst_402:
+// rs1_val==-46340 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8752, -0xb504, 0xaaaaaaa9, x1, 1552, x2)
+
+inst_403:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555554, x1, 1556, x2)
+
+inst_404:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x2, x1, 1560, x2)
+
+inst_405:
+// rs1_val==-46340 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0xffff, x1, 1564, x2)
+
+inst_406:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0xb504, x1, 1568, x2)
+
+inst_407:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb798, -0xb504, 0x66666666, x1, 1572, x2)
+
+inst_408:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcc, -0xb504, 0x33333333, x1, 1576, x2)
+
+inst_409:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x5, x1, 1580, x2)
+
+inst_410:
+// rs1_val==-46340 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8752, -0xb504, 0xaaaaaaaa, x1, 1584, x2)
+
+inst_411:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555555, x1, 1588, x2)
+
+inst_412:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x3, x1, 1592, x2)
+
+inst_413:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6666, 0x66666666, 0x10000, x1, 1596, x2)
+
+inst_414:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666666, 0x1, x1, 1600, x2)
+
+inst_415:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0x66666666, 0xb505, x1, 1604, x2)
+
+inst_416:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666667, x1, 1608, x2)
+
+inst_417:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333334, x1, 1612, x2)
+
+inst_418:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x66666666, 0x6, x1, 1616, x2)
+
+inst_419:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444444, 0x66666666, 0xaaaaaaab, x1, 1620, x2)
+
+inst_420:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x66666666, 0x55555556, x1, 1624, x2)
+
+inst_421:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666666, 0x4, x1, 1628, x2)
+
+inst_422:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6665, 0x66666666, 0xfffe, x1, 1632, x2)
+
+inst_423:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666666, 0x0, x1, 1636, x2)
+
+inst_424:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0x66666666, 0xb503, x1, 1640, x2)
+
+inst_425:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28e, 0x66666666, 0x66666665, x1, 1644, x2)
+
+inst_426:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333332, x1, 1648, x2)
+
+inst_427:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444443, 0x66666666, 0xaaaaaaa9, x1, 1652, x2)
+
+inst_428:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666666, 0x55555554, x1, 1656, x2)
+
+inst_429:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x66666666, 0x2, x1, 1660, x2)
+
+inst_430:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x6665, 0x66666666, 0xffff, x1, 1664, x2)
+
+inst_431:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0x66666666, 0xb504, x1, 1668, x2)
+
+inst_432:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666666, x1, 1672, x2)
+
+inst_433:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333333, x1, 1676, x2)
+
+inst_434:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666666, 0x5, x1, 1680, x2)
+
+inst_435:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x44444443, 0x66666666, 0xaaaaaaaa, x1, 1684, x2)
+
+inst_436:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x66666666, 0x55555555, x1, 1688, x2)
+
+inst_437:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x66666666, 0x3, x1, 1692, x2)
+
+inst_438:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3333, 0x33333333, 0x10000, x1, 1696, x2)
+
+inst_439:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x1, x1, 1700, x2)
+
+inst_440:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0x33333333, 0xb505, x1, 1704, x2)
+
+inst_441:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666667, x1, 1708, x2)
+
+inst_442:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333334, x1, 1712, x2)
+
+inst_443:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x33333333, 0x6, x1, 1716, x2)
+
+inst_444:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x33333333, 0xaaaaaaab, x1, 1720, x2)
+
+inst_445:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x33333333, 0x55555556, x1, 1724, x2)
+
+inst_446:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x4, x1, 1728, x2)
+
+inst_447:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3332, 0x33333333, 0xfffe, x1, 1732, x2)
+
+inst_448:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x0, x1, 1736, x2)
+
+inst_449:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0x33333333, 0xb503, x1, 1740, x2)
+
+inst_450:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666665, x1, 1744, x2)
+
+inst_451:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333332, x1, 1748, x2)
+
+inst_452:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x33333333, 0xaaaaaaa9, x1, 1752, x2)
+
+inst_453:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x33333333, 0x55555554, x1, 1756, x2)
+
+inst_454:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x2, x1, 1760, x2)
+
+inst_455:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3332, 0x33333333, 0xffff, x1, 1764, x2)
+
+inst_456:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0x33333333, 0xb504, x1, 1768, x2)
+
+inst_457:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666666, x1, 1772, x2)
+
+inst_458:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333333, x1, 1776, x2)
+
+inst_459:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x5, x1, 1780, x2)
+
+inst_460:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x33333333, 0xaaaaaaaa, x1, 1784, x2)
+
+inst_461:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x33333333, 0x55555555, x1, 1788, x2)
+
+inst_462:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333333, 0x3, x1, 1792, x2)
+
+inst_463:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x10000, x1, 1796, x2)
+
+inst_464:
+// rs1_val==5 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x1, x1, 1800, x2)
+
+inst_465:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0xb505, x1, 1804, x2)
+
+inst_466:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x5, 0x66666667, x1, 1808, x2)
+
+inst_467:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x33333334, x1, 1812, x2)
+
+inst_468:
+// rs1_val==5 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x6, x1, 1816, x2)
+
+inst_469:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaab, x1, 1820, x2)
+
+inst_470:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x55555556, x1, 1824, x2)
+
+inst_471:
+// rs1_val==5 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x4, x1, 1828, x2)
+
+inst_472:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0xfffe, x1, 1832, x2)
+
+inst_473:
+// rs1_val==5 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x0, x1, 1836, x2)
+
+inst_474:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0xb503, x1, 1840, x2)
+
+inst_475:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x66666665, x1, 1844, x2)
+
+inst_476:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x33333332, x1, 1848, x2)
+
+inst_477:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaa9, x1, 1852, x2)
+
+inst_478:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x55555554, x1, 1856, x2)
+
+inst_479:
+// rs1_val==5 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x2, x1, 1860, x2)
+
+inst_480:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0xffff, x1, 1864, x2)
+
+inst_481:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0xb504, x1, 1868, x2)
+
+inst_482:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x66666666, x1, 1872, x2)
+
+inst_483:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x33333333, x1, 1876, x2)
+
+inst_484:
+// rs1_val==5 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x5, x1, 1880, x2)
+
+inst_485:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaaa, x1, 1884, x2)
+
+inst_486:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x5, 0x55555555, x1, 1888, x2)
+
+inst_487:
+// rs1_val==5 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x5, 0x3, x1, 1892, x2)
+
+inst_488:
+// rs1_val==-1431655766 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaaa, -0x55555556, 0x10000, x1, 1896, x2)
+
+inst_489:
+// rs1_val==-1431655766 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x55555556, 0x1, x1, 1900, x2)
+
+inst_490:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a8, -0x55555556, 0xb505, x1, 1904, x2)
+
+inst_491:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xdddddddd, -0x55555556, 0x66666667, x1, 1908, x2)
+
+inst_492:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeee, -0x55555556, 0x33333334, x1, 1912, x2)
+
+inst_493:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffd, -0x55555556, 0x6, x1, 1916, x2)
+
+inst_494:
+// rs1_val==-1431655766 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c6, -0x55555556, 0xaaaaaaab, x1, 1920, x2)
+
+inst_495:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555556, x1, 1924, x2)
+
+inst_496:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555556, 0x4, x1, 1928, x2)
+
+inst_497:
+// rs1_val==-1431655766 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaab, -0x55555556, 0xfffe, x1, 1932, x2)
+
+inst_498:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, -0x55555556, 0x0, x1, 1936, x2)
+
+inst_499:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0x55555556, 0xb503, x1, 1940, x2)
+
+inst_500:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xddddddde, -0x55555556, 0x66666665, x1, 1944, x2)
+
+inst_501:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeef, -0x55555556, 0x33333332, x1, 1948, x2)
+
+inst_502:
+// rs1_val==-1431655766 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c7, -0x55555556, 0xaaaaaaa9, x1, 1952, x2)
+
+inst_503:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555554, x1, 1956, x2)
+
+inst_504:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0x55555556, 0x2, x1, 1960, x2)
+
+inst_505:
+// rs1_val==-1431655766 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffaaaa, -0x55555556, 0xffff, x1, 1964, x2)
+
+inst_506:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0x55555556, 0xb504, x1, 1968, x2)
+
+inst_507:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xdddddddd, -0x55555556, 0x66666666, x1, 1972, x2)
+
+inst_508:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xeeeeeeee, -0x55555556, 0x33333333, x1, 1976, x2)
+
+inst_509:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555556, 0x5, x1, 1980, x2)
+
+inst_510:
+// rs1_val==-1431655766 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xc71c71c6, -0x55555556, 0xaaaaaaaa, x1, 1984, x2)
+
+inst_511:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xe38e38e3, -0x55555556, 0x55555555, x1, 1988, x2)
+
+inst_512:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x55555556, 0x3, x1, 1992, x2)
+
+inst_513:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5555, 0x55555555, 0x10000, x1, 1996, x2)
+
+inst_514:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555555, 0x1, x1, 2000, x2)
+
+inst_515:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555555, 0xb505, x1, 2004, x2)
+
+inst_516:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222222, 0x55555555, 0x66666667, x1, 2008, x2)
+
+inst_517:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x55555555, 0x33333334, x1, 2012, x2)
+
+inst_518:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555555, 0x6, x1, 2016, x2)
+
+inst_519:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaab, x1, 2020, x2)
+
+inst_520:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555556, x1, 2024, x2)
+
+inst_521:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555555, 0x4, x1, 2028, x2)
+
+inst_522:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5554, 0x55555555, 0xfffe, x1, 2032, x2)
+
+inst_523:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555555, 0x0, x1, 2036, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x3, x1, 2040, x2)
+
+inst_525:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555555, 0xb503, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_526:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555555, 0x66666665, x1, 0, x2)
+
+inst_527:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x55555555, 0x33333332, x1, 4, x2)
+
+inst_528:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaa9, x1, 8, x2)
+
+inst_529:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71b, 0x55555555, 0x55555554, x1, 12, x2)
+
+inst_530:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555555, 0x2, x1, 16, x2)
+
+inst_531:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5554, 0x55555555, 0xffff, x1, 20, x2)
+
+inst_532:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555555, 0xb504, x1, 24, x2)
+
+inst_533:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555555, 0x66666666, x1, 28, x2)
+
+inst_534:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x55555555, 0x33333333, x1, 32, x2)
+
+inst_535:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555555, 0x5, x1, 36, x2)
+
+inst_536:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaaa, x1, 40, x2)
+
+inst_537:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555555, x1, 44, x2)
+
+inst_538:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555555, 0x3, x1, 48, x2)
+
+inst_539:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x10000, x1, 52, x2)
+
+inst_540:
+// rs1_val==3 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x1, x1, 56, x2)
+
+inst_541:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0xb505, x1, 60, x2)
+
+inst_542:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0x66666667, x1, 64, x2)
+
+inst_543:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x33333334, x1, 68, x2)
+
+inst_544:
+// rs1_val==3 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x6, x1, 72, x2)
+
+inst_545:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2, 0x3, 0xaaaaaaab, x1, 76, x2)
+
+inst_546:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0x55555556, x1, 80, x2)
+
+inst_547:
+// rs1_val==3 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x4, x1, 84, x2)
+
+inst_548:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0xfffe, x1, 88, x2)
+
+inst_549:
+// rs1_val==3 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x0, x1, 92, x2)
+
+inst_550:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0xb503, x1, 96, x2)
+
+inst_551:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0x66666665, x1, 100, x2)
+
+inst_552:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x33333332, x1, 104, x2)
+
+inst_553:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaa9, x1, 108, x2)
+
+inst_554:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x55555554, x1, 112, x2)
+
+inst_555:
+// rs1_val==3 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x2, x1, 116, x2)
+
+inst_556:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0xffff, x1, 120, x2)
+
+inst_557:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0xb504, x1, 124, x2)
+
+inst_558:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0x66666666, x1, 128, x2)
+
+inst_559:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x33333333, x1, 132, x2)
+
+inst_560:
+// rs1_val==3 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x5, x1, 136, x2)
+
+inst_561:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaaa, x1, 140, x2)
+
+inst_562:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x55555555, x1, 144, x2)
+
+inst_563:
+// rs1_val==3 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x3, 0x3, x1, 148, x2)
+
+inst_564:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x5, x1, 152, x2)
+
+inst_565:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaaa, x1, 156, x2)
+
+inst_566:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555555, x1, 160, x2)
+
+inst_567:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x33333332, 0x3, x1, 164, x2)
+
+inst_568:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5555, 0x55555554, 0x10000, x1, 168, x2)
+
+inst_569:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555554, 0x1, x1, 172, x2)
+
+inst_570:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555554, 0xb505, x1, 176, x2)
+
+inst_571:
+// rs2_val == (2**(xlen)-1), 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0xffffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xfffffffe, -0x2, 0xffffffff, x1, 180, x2)
+
+inst_572:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666667, x1, 184, x2)
+
+inst_573:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111111, 0x55555554, 0x33333334, x1, 188, x2)
+
+inst_574:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555554, 0x6, x1, 192, x2)
+
+inst_575:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e38, 0x55555554, 0xaaaaaaab, x1, 196, x2)
+
+inst_576:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71c, 0x55555554, 0x55555556, x1, 200, x2)
+
+inst_577:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555554, 0x4, x1, 204, x2)
+
+inst_578:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5554, 0x55555554, 0xfffe, x1, 208, x2)
+
+inst_579:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555554, 0x0, x1, 212, x2)
+
+inst_580:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555554, 0xb503, x1, 216, x2)
+
+inst_581:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666665, x1, 220, x2)
+
+inst_582:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x55555554, 0x33333332, x1, 224, x2)
+
+inst_583:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e37, 0x55555554, 0xaaaaaaa9, x1, 228, x2)
+
+inst_584:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555554, x1, 232, x2)
+
+inst_585:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555554, 0x2, x1, 236, x2)
+
+inst_586:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x5554, 0x55555554, 0xffff, x1, 240, x2)
+
+inst_587:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0x55555554, 0xb504, x1, 244, x2)
+
+inst_588:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666666, x1, 248, x2)
+
+inst_589:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x11111110, 0x55555554, 0x33333333, x1, 252, x2)
+
+inst_590:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x55555554, 0x5, x1, 256, x2)
+
+inst_591:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x38e38e37, 0x55555554, 0xaaaaaaaa, x1, 260, x2)
+
+inst_592:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555555, x1, 264, x2)
+
+inst_593:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x55555554, 0x3, x1, 268, x2)
+
+inst_594:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x10000, x1, 272, x2)
+
+inst_595:
+// rs1_val==2 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x1, x1, 276, x2)
+
+inst_596:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0xb505, x1, 280, x2)
+
+inst_597:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x66666667, x1, 284, x2)
+
+inst_598:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x33333334, x1, 288, x2)
+
+inst_599:
+// rs1_val==2 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x6, x1, 292, x2)
+
+inst_600:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaab, x1, 296, x2)
+
+inst_601:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x55555556, x1, 300, x2)
+
+inst_602:
+// rs1_val==2 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x4, x1, 304, x2)
+
+inst_603:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0xfffe, x1, 308, x2)
+
+inst_604:
+// rs1_val==2 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x0, x1, 312, x2)
+
+inst_605:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0xb503, x1, 316, x2)
+
+inst_606:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x66666665, x1, 320, x2)
+
+inst_607:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x33333332, x1, 324, x2)
+
+inst_608:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaa9, x1, 328, x2)
+
+inst_609:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x55555554, x1, 332, x2)
+
+inst_610:
+// rs1_val==2 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x2, x1, 336, x2)
+
+inst_611:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0xffff, x1, 340, x2)
+
+inst_612:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0xb504, x1, 344, x2)
+
+inst_613:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x66666666, x1, 348, x2)
+
+inst_614:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x33333333, x1, 352, x2)
+
+inst_615:
+// rs1_val==2 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x5, x1, 356, x2)
+
+inst_616:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaaa, x1, 360, x2)
+
+inst_617:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x55555555, x1, 364, x2)
+
+inst_618:
+// rs1_val==2 and rs2_val==3, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0x2, 0x3, x1, 368, x2)
+
+inst_619:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x10000, x1, 372, x2)
+
+inst_620:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x1, x1, 376, x2)
+
+inst_621:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0xb505, x1, 380, x2)
+
+inst_622:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4868, 0xb504, 0x66666667, x1, 384, x2)
+
+inst_623:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2434, 0xb504, 0x33333334, x1, 388, x2)
+
+inst_624:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x6, x1, 392, x2)
+
+inst_625:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaab, x1, 396, x2)
+
+inst_626:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb504, 0x55555556, x1, 400, x2)
+
+inst_627:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x4, x1, 404, x2)
+
+inst_628:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xfffe
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0xfffe, x1, 408, x2)
+
+inst_629:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x0, x1, 412, x2)
+
+inst_630:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0xb503, x1, 416, x2)
+
+inst_631:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0xb504, 0x66666665, x1, 420, x2)
+
+inst_632:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0xb504, 0x33333332, x1, 424, x2)
+
+inst_633:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaa9, x1, 428, x2)
+
+inst_634:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb504, 0x55555554, x1, 432, x2)
+
+inst_635:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x2, x1, 436, x2)
+
+inst_636:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0xffff, x1, 440, x2)
+
+inst_637:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0xb504, x1, 444, x2)
+
+inst_638:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4867, 0xb504, 0x66666666, x1, 448, x2)
+
+inst_639:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x2433, 0xb504, 0x33333333, x1, 452, x2)
+
+inst_640:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x0, 0xb504, 0x5, x1, 456, x2)
+
+inst_641:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaaa, x1, 460, x2)
+
+inst_642:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x3c56, 0xb504, 0x55555555, x1, 464, x2)
+
+inst_643:
+// rs1_val==-46340 and rs2_val==65536, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x10000
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x10000, x1, 468, x2)
+
+inst_644:
+// rs1_val==-46340 and rs2_val==1, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x1
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x1, x1, 472, x2)
+
+inst_645:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0xb505, x1, 476, x2)
+
+inst_646:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffb797, -0xb504, 0x66666667, x1, 480, x2)
+
+inst_647:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffdbcb, -0xb504, 0x33333334, x1, 484, x2)
+
+inst_648:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffffff, -0xb504, 0x6, x1, 488, x2)
+
+inst_649:
+// rs1_val==-46340 and rs2_val==2863311531, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffff8752, -0xb504, 0xaaaaaaab, x1, 492, x2)
+
+inst_650:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xffffc3a9, -0xb504, 0x55555556, x1, 496, x2)
+
+inst_651:
+// rs2_val == 3221225471, rs1_val == 1048576
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0xbfffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0xbffff, 0x100000, 0xbfffffff, x1, 500, x2)
+
+inst_652:
+// rs2_val == 3758096383, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xdfffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x59999997, 0x66666665, 0xdfffffff, x1, 504, x2)
+
+inst_653:
+// rs2_val == 4160749567, 
+// opcode: mulhsu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xf7ffffff
+TEST_RR_OP(mulhsu, x12, x10, x11, 0x4, 0x5, 0xf7ffffff, x1, 508, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhu-01.S
new file mode 100644
index 000000000..8b6564009
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/mulhu-01.S
@@ -0,0 +1,3700 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the mulhu instruction of the RISC-V M extension for the mulhu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",mulhu)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x10, rs2==x14, rd==x14, rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0, rs1_val == 65536, rs1_val > 0 and rs2_val > 0, rs2_val == 64
+// opcode: mulhu ; op1:x10; op2:x14; dest:x14; op1val:0x10000;  op2val:0x40
+TEST_RR_OP(mulhu, x14, x10, x14, 0x0, 0x10000, 0x40, x8, 0, x4)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x6, rs2==x13, rd==x6, rs2_val == 2147483647, rs1_val == 32768
+// opcode: mulhu ; op1:x6; op2:x13; dest:x6; op1val:0x8000;  op2val:0x7fffffff
+TEST_RR_OP(mulhu, x6, x6, x13, 0x3fff, 0x8000, 0x7fffffff, x8, 4, x4)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x5, rs2==x5, rd==x5, rs2_val == 3221225471, rs1_val == 4294443007
+// opcode: mulhu ; op1:x5; op2:x5; dest:x5; op1val:0xfff7ffff;  op2val:0xfff7ffff
+TEST_RR_OP(mulhu, x5, x5, x5, 0xfff0003e, 0xfff7ffff, 0xfff7ffff, x8, 8, x4)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x0, rs2==x0, rd==x2, rs2_val == 3758096383, rs1_val == 524288
+// opcode: mulhu ; op1:x0; op2:x0; dest:x2; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mulhu, x2, x0, x0, 0x0, 0x0, 0x0, x8, 12, x4)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x1, rs2==x6, rd==x13, rs2_val == 4026531839, rs1_val == 134217728
+// opcode: mulhu ; op1:x1; op2:x6; dest:x13; op1val:0x8000000;  op2val:0xefffffff
+TEST_RR_OP(mulhu, x13, x1, x6, 0x77fffff, 0x8000000, 0xefffffff, x8, 16, x4)
+
+inst_5:
+// rs1==x7, rs2==x3, rd==x15, rs2_val == 4160749567, rs1_val == 32
+// opcode: mulhu ; op1:x7; op2:x3; dest:x15; op1val:0x20;  op2val:0xf7ffffff
+TEST_RR_OP(mulhu, x15, x7, x3, 0x1e, 0x20, 0xf7ffffff, x8, 20, x4)
+
+inst_6:
+// rs1==x13, rs2==x11, rd==x7, rs2_val == 4227858431, rs1_val == 4294967231
+// opcode: mulhu ; op1:x13; op2:x11; dest:x7; op1val:0xffffffbf;  op2val:0xfbffffff
+TEST_RR_OP(mulhu, x7, x13, x11, 0xfbffffbf, 0xffffffbf, 0xfbffffff, x8, 24, x4)
+
+inst_7:
+// rs1==x11, rs2==x1, rd==x0, rs2_val == 4261412863, 
+// opcode: mulhu ; op1:x11; op2:x1; dest:x0; op1val:0x55555554;  op2val:0xfdffffff
+TEST_RR_OP(mulhu, x0, x11, x1, 0, 0x55555554, 0xfdffffff, x8, 28, x5)
+
+inst_8:
+// rs1==x14, rs2==x4, rd==x1, rs2_val == 4278190079, 
+// opcode: mulhu ; op1:x14; op2:x4; dest:x1; op1val:0xfffe;  op2val:0xfeffffff
+TEST_RR_OP(mulhu, x1, x14, x4, 0xfefe, 0xfffe, 0xfeffffff, x8, 32, x5)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_9:
+// rs1==x15, rs2==x12, rd==x8, rs2_val == 4286578687, rs1_val == 4294967263
+// opcode: mulhu ; op1:x15; op2:x12; dest:x8; op1val:0xffffffdf;  op2val:0xff7fffff
+TEST_RR_OP(mulhu, x8, x15, x12, 0xff7fffde, 0xffffffdf, 0xff7fffff, x1, 0, x5)
+
+inst_10:
+// rs1==x8, rs2==x10, rd==x9, rs2_val == 4290772991, 
+// opcode: mulhu ; op1:x8; op2:x10; dest:x9; op1val:0x33333332;  op2val:0xffbfffff
+TEST_RR_OP(mulhu, x9, x8, x10, 0x33266665, 0x33333332, 0xffbfffff, x1, 4, x5)
+
+inst_11:
+// rs1==x3, rs2==x7, rd==x12, rs2_val == 4292870143, rs1_val == 64
+// opcode: mulhu ; op1:x3; op2:x7; dest:x12; op1val:0x40;  op2val:0xffdfffff
+TEST_RR_OP(mulhu, x12, x3, x7, 0x3f, 0x40, 0xffdfffff, x1, 8, x5)
+
+inst_12:
+// rs1==x9, rs2==x8, rd==x11, rs2_val == 4293918719, rs1_val == 4227858431
+// opcode: mulhu ; op1:x9; op2:x8; dest:x11; op1val:0xfbffffff;  op2val:0xffefffff
+TEST_RR_OP(mulhu, x11, x9, x8, 0xfbf03ffe, 0xfbffffff, 0xffefffff, x1, 12, x5)
+
+inst_13:
+// rs1==x12, rs2==x2, rd==x4, rs2_val == 4294443007, 
+// opcode: mulhu ; op1:x12; op2:x2; dest:x4; op1val:0xb503;  op2val:0xfff7ffff
+TEST_RR_OP(mulhu, x4, x12, x2, 0xb4fd, 0xb503, 0xfff7ffff, x1, 16, x5)
+
+inst_14:
+// rs1==x4, rs2==x15, rd==x3, rs2_val == 4294705151, 
+// opcode: mulhu ; op1:x4; op2:x15; dest:x3; op1val:0x8000;  op2val:0xfffbffff
+TEST_RR_OP(mulhu, x3, x4, x15, 0x7ffd, 0x8000, 0xfffbffff, x1, 20, x5)
+
+inst_15:
+// rs1==x2, rs2==x9, rd==x10, rs2_val == 4294836223, 
+// opcode: mulhu ; op1:x2; op2:x9; dest:x10; op1val:0x33333333;  op2val:0xfffdffff
+TEST_RR_OP(mulhu, x10, x2, x9, 0x3332cccc, 0x33333333, 0xfffdffff, x1, 24, x5)
+
+inst_16:
+// rs2_val == 4294901759, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x11;  op2val:0xfffeffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x10, 0x11, 0xfffeffff, x1, 28, x5)
+
+inst_17:
+// rs2_val == 4294934527, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffff7fff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfffd, 0xfffe, 0xffff7fff, x1, 32, x5)
+
+inst_18:
+// rs2_val == 4294950911, rs1_val == 4194304
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xffffbfff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3fffef, 0x400000, 0xffffbfff, x1, 36, x5)
+
+inst_19:
+// rs2_val == 4294959103, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x13;  op2val:0xffffdfff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x12, 0x13, 0xffffdfff, x1, 40, x5)
+
+inst_20:
+// rs2_val == 4294963199, rs1_val == 4286578687
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xff7fffff;  op2val:0xffffefff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xff7ff006, 0xff7fffff, 0xffffefff, x1, 44, x5)
+
+inst_21:
+// rs2_val == 4294965247, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffff7ff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4, 0x5, 0xfffff7ff, x1, 48, x5)
+
+inst_22:
+// rs2_val == 4294966271, rs1_val == 4294959103
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0xfffffbff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffffdbfe, 0xffffdfff, 0xfffffbff, x1, 52, x5)
+
+inst_23:
+// rs2_val == 4294966783, rs1_val == 4294934527
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fff;  op2val:0xfffffdff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffff7dfe, 0xffff7fff, 0xfffffdff, x1, 56, x5)
+
+inst_24:
+// rs2_val == 4294967039, rs1_val == 128
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0xfffffeff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7f, 0x80, 0xfffffeff, x1, 60, x5)
+
+inst_25:
+// rs2_val == 4294967167, rs1_val == 4294965247
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ff;  op2val:0xffffff7f
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfffff77e, 0xfffff7ff, 0xffffff7f, x1, 64, x5)
+
+inst_26:
+// rs2_val == 4294967231, rs1_val == 4294966783
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdff;  op2val:0xffffffbf
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfffffdbe, 0xfffffdff, 0xffffffbf, x1, 68, x5)
+
+inst_27:
+// rs2_val == 4294967263, rs1_val == 4294967039
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffeff;  op2val:0xffffffdf
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfffffede, 0xfffffeff, 0xffffffdf, x1, 72, x5)
+
+inst_28:
+// rs2_val == 4294967279, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x13;  op2val:0xffffffef
+TEST_RR_OP(mulhu, x12, x10, x11, 0x12, 0x13, 0xffffffef, x1, 76, x5)
+
+inst_29:
+// rs2_val == 4294967287, rs1_val == 262144
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0xfffffff7
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3ffff, 0x40000, 0xfffffff7, x1, 80, x5)
+
+inst_30:
+// rs2_val == 4294967291, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffffffb
+TEST_RR_OP(mulhu, x12, x10, x11, 0xb504, 0xb505, 0xfffffffb, x1, 84, x5)
+
+inst_31:
+// rs2_val == 4294967293, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0xfffffffd
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffffffdc, 0xffffffdf, 0xfffffffd, x1, 88, x5)
+
+inst_32:
+// rs2_val == 4294967294, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0xfffffffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1f, 0x20, 0xfffffffe, x1, 92, x5)
+
+inst_33:
+// rs1_val == 2147483647, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0xfffbffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7ffdfffe, 0x7fffffff, 0xfffbffff, x1, 96, x5)
+
+inst_34:
+// rs1_val == 3221225471, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffff;  op2val:0xefffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xb3fffffe, 0xbfffffff, 0xefffffff, x1, 100, x5)
+
+inst_35:
+// rs1_val == 3758096383, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffff;  op2val:0xffffefff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xdffff1fe, 0xdfffffff, 0xffffefff, x1, 104, x5)
+
+inst_36:
+// rs1_val == 4026531839, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0x7fffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x77fffffe, 0xefffffff, 0x7fffffff, x1, 108, x5)
+
+inst_37:
+// rs1_val == 4160749567, rs2_val == 0
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xf7ffffff;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xf7ffffff, 0x0, x1, 112, x5)
+
+inst_38:
+// rs1_val == 4261412863, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfdfe, 0xfdffffff, 0xfffe, x1, 116, x5)
+
+inst_39:
+// rs1_val == 4278190079, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfeffffff;  op2val:0xfffeffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfeff00fe, 0xfeffffff, 0xfffeffff, x1, 120, x5)
+
+inst_40:
+// rs1_val == 4290772991, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffff;  op2val:0xfffffffb
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffbffffa, 0xffbfffff, 0xfffffffb, x1, 124, x5)
+
+inst_41:
+// rs1_val == 4292870143, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffdfffff;  op2val:0xffff7fff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffdf800e, 0xffdfffff, 0xffff7fff, x1, 128, x5)
+
+inst_42:
+// rs1_val == 4293918719, rs2_val == 16777216
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffefffff;  op2val:0x1000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffefff, 0xffefffff, 0x1000000, x1, 132, x5)
+
+inst_43:
+// rs1_val == 4294705151, rs2_val == 8
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffbffff;  op2val:0x8
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7, 0xfffbffff, 0x8, x1, 136, x5)
+
+inst_44:
+// rs1_val == 4294836223, rs2_val == 1048576
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffff;  op2val:0x100000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xfffdf, 0xfffdffff, 0x100000, x1, 140, x5)
+
+inst_45:
+// rs1_val == 4294901759, rs2_val == 536870912
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffeffff;  op2val:0x20000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1fffdfff, 0xfffeffff, 0x20000000, x1, 144, x5)
+
+inst_46:
+// rs1_val == 4294950911, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfff;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffffbfff, 0x0, x1, 148, x5)
+
+inst_47:
+// rs1_val == 4294963199, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffefff;  op2val:0xfffffdff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffffedfe, 0xffffefff, 0xfffffdff, x1, 152, x5)
+
+inst_48:
+// rs1_val == 4294966271, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffbff;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x666664cc, 0xfffffbff, 0x66666667, x1, 156, x5)
+
+inst_49:
+// rs1_val == 4294967167, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffff7f;  op2val:0xff7fffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xff7fff7e, 0xffffff7f, 0xff7fffff, x1, 160, x5)
+
+inst_50:
+// rs1_val == 4294967279, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffef;  op2val:0x7fffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7ffffff6, 0xffffffef, 0x7fffffff, x1, 164, x5)
+
+inst_51:
+// rs1_val == 4294967287, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0xffffffbf
+TEST_RR_OP(mulhu, x12, x10, x11, 0xffffffb6, 0xfffffff7, 0xffffffbf, x1, 168, x5)
+
+inst_52:
+// rs1_val == 4294967291, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffb;  op2val:0x40
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3f, 0xfffffffb, 0x40, x1, 172, x5)
+
+inst_53:
+// rs1_val == 4294967293, rs2_val == 256
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffd;  op2val:0x100
+TEST_RR_OP(mulhu, x12, x10, x11, 0xff, 0xfffffffd, 0x100, x1, 176, x5)
+
+inst_54:
+// rs1_val == 4294967294, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffe;  op2val:0xefffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xeffffffd, 0xfffffffe, 0xefffffff, x1, 180, x5)
+
+inst_55:
+// rs2_val == 2147483648, rs1_val == 2097152
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x80000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x100000, 0x200000, 0x80000000, x1, 184, x5)
+
+inst_56:
+// rs2_val == 1073741824, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x40000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x15555555, 0x55555554, 0x40000000, x1, 188, x5)
+
+inst_57:
+// rs2_val == 268435456, rs1_val == 2048
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x10000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x80, 0x800, 0x10000000, x1, 192, x5)
+
+inst_58:
+// rs2_val == 134217728, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0x8000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7efffff, 0xfdffffff, 0x8000000, x1, 196, x5)
+
+inst_59:
+// rs2_val == 67108864, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0x4000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3bfffff, 0xefffffff, 0x4000000, x1, 200, x5)
+
+inst_60:
+// rs2_val == 33554432, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0x2000000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1ffffff, 0xffffffdf, 0x2000000, x1, 204, x5)
+
+inst_61:
+// rs2_val == 8388608, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x800000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5a, 0xb504, 0x800000, x1, 208, x5)
+
+inst_62:
+// rs2_val == 4194304, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffff7f;  op2val:0x400000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3fffff, 0xffffff7f, 0x400000, x1, 212, x5)
+
+inst_63:
+// rs2_val == 2097152, rs1_val == 1431655765
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x200000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaaa, 0x55555555, 0x200000, x1, 216, x5)
+
+inst_64:
+// rs2_val == 524288, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x80000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x200, 0x400000, 0x80000, x1, 220, x5)
+
+inst_65:
+// rs2_val == 262144, rs1_val == 8388608
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x40000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x200, 0x800000, 0x40000, x1, 224, x5)
+
+inst_66:
+// rs2_val == 131072, rs1_val == 16777216
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x20000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x200, 0x1000000, 0x20000, x1, 228, x5)
+
+inst_67:
+// rs2_val == 65536, rs1_val == 536870912
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2000, 0x20000000, 0x10000, x1, 232, x5)
+
+inst_68:
+// rs2_val == 32768, rs1_val == 2147483648
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x80000000;  op2val:0x8000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4000, 0x80000000, 0x8000, x1, 236, x5)
+
+inst_69:
+// rs2_val == 16384, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0x4000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3f7f, 0xfdffffff, 0x4000, x1, 240, x5)
+
+inst_70:
+// rs2_val == 8192, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x666, 0x33333332, 0x2000, x1, 244, x5)
+
+inst_71:
+// rs2_val == 4096, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x555, 0x55555554, 0x1000, x1, 248, x5)
+
+inst_72:
+// rs2_val == 2048, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffff;  op2val:0x800
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7fd, 0xffbfffff, 0x800, x1, 252, x5)
+
+inst_73:
+// rs2_val == 1024, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x400
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x400, x1, 256, x5)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x200
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaa, 0x55555555, 0x200, x1, 260, x5)
+
+inst_75:
+// rs2_val == 128, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfff;  op2val:0x80
+TEST_RR_OP(mulhu, x12, x10, x11, 0x7f, 0xffffbfff, 0x80, x1, 264, x5)
+
+inst_76:
+// rs2_val == 32, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x20
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x8000, 0x20, x1, 268, x5)
+
+inst_77:
+// rs2_val == 16, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb;  op2val:0x10
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb, 0x10, x1, 272, x5)
+
+inst_78:
+// rs2_val == 4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xd;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xd, 0x4, x1, 276, x5)
+
+inst_79:
+// rs2_val == 2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfff;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xffffbfff, 0x2, x1, 280, x5)
+
+inst_80:
+// rs2_val == 1, rs1_val==858993460 and rs2_val==1
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333334, 0x1, x1, 284, x5)
+
+inst_81:
+// rs1_val == 1073741824, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0xd
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x40000000, 0xd, x1, 288, x5)
+
+inst_82:
+// rs1_val == 268435456, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x800000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x80000, 0x10000000, 0x800000, x1, 292, x5)
+
+inst_83:
+// rs1_val == 67108864, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4000000, 0x9, x1, 296, x5)
+
+inst_84:
+// rs1_val == 33554432, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0xff7fffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1feffff, 0x2000000, 0xff7fffff, x1, 300, x5)
+
+inst_85:
+// rs1_val == 1048576, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x100000, 0x6, x1, 304, x5)
+
+inst_86:
+// rs1_val == 131072, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x20000, 0x1, x1, 308, x5)
+
+inst_87:
+// rs1_val == 16384, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xffdfffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3ff7, 0x4000, 0xffdfffff, x1, 312, x5)
+
+inst_88:
+// rs1_val == 8192, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2000, 0x10000, x1, 316, x5)
+
+inst_89:
+// rs1_val == 4096, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x2000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1000, 0x2000, x1, 320, x5)
+
+inst_90:
+// rs1_val == 1024, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x400, 0x3, x1, 324, x5)
+
+inst_91:
+// rs1_val == 512, rs2_val == (2**(xlen)-1)
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0xffffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1ff, 0x200, 0xffffffff, x1, 328, x5)
+
+inst_92:
+// rs1_val == 256, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x100, 0x3, x1, 332, x5)
+
+inst_93:
+// rs1_val == 16, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0xfbffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xf, 0x10, 0xfbffffff, x1, 336, x5)
+
+inst_94:
+// rs1_val == 8, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x8, 0x10000, x1, 340, x5)
+
+inst_95:
+// rs1_val == 4, rs1_val==4 and rs2_val==65534
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0xfffe, x1, 344, x5)
+
+inst_96:
+// rs1_val == 2, rs1_val==2 and rs2_val==4
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x4, x1, 348, x5)
+
+inst_97:
+// rs1_val == 1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffffff7
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xfffffff7, x1, 352, x5)
+
+inst_98:
+// rs1_val==65536 and rs2_val==65536, rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x10000, 0x10000, x1, 356, x5)
+
+inst_99:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x1, x1, 360, x5)
+
+inst_100:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0xb505, x1, 364, x5)
+
+inst_101:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x10000, 0x66666667, x1, 368, x5)
+
+inst_102:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x10000, 0x33333334, x1, 372, x5)
+
+inst_103:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x6, x1, 376, x5)
+
+inst_104:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0x10000, 0xaaaaaaab, x1, 380, x5)
+
+inst_105:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x10000, 0x55555556, x1, 384, x5)
+
+inst_106:
+// rs1_val==65536 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x4, x1, 388, x5)
+
+inst_107:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0xfffe, x1, 392, x5)
+
+inst_108:
+// rs1_val==65536 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x0, x1, 396, x5)
+
+inst_109:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0xb503, x1, 400, x5)
+
+inst_110:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x10000, 0x66666665, x1, 404, x5)
+
+inst_111:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x10000, 0x33333332, x1, 408, x5)
+
+inst_112:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0x10000, 0xaaaaaaa9, x1, 412, x5)
+
+inst_113:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x10000, 0x55555554, x1, 416, x5)
+
+inst_114:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x2, x1, 420, x5)
+
+inst_115:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0xffff, x1, 424, x5)
+
+inst_116:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0xb504, x1, 428, x5)
+
+inst_117:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x10000, 0x66666666, x1, 432, x5)
+
+inst_118:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x10000, 0x33333333, x1, 436, x5)
+
+inst_119:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x5, x1, 440, x5)
+
+inst_120:
+// rs1_val==65536 and rs2_val==2863311530, rs2_val == 2863311530
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0x10000, 0xaaaaaaaa, x1, 444, x5)
+
+inst_121:
+// rs1_val==65536 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x10000, 0x55555555, x1, 448, x5)
+
+inst_122:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x10000, 0x3, x1, 452, x5)
+
+inst_123:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x10000, x1, 456, x5)
+
+inst_124:
+// rs1_val==1 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x1, x1, 460, x5)
+
+inst_125:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xb505, x1, 464, x5)
+
+inst_126:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x66666667, x1, 468, x5)
+
+inst_127:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x33333334, x1, 472, x5)
+
+inst_128:
+// rs1_val==1 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x6, x1, 476, x5)
+
+inst_129:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaab, x1, 480, x5)
+
+inst_130:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x55555556, x1, 484, x5)
+
+inst_131:
+// rs1_val==1 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x4, x1, 488, x5)
+
+inst_132:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xfffe, x1, 492, x5)
+
+inst_133:
+// rs1_val==1 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x0, x1, 496, x5)
+
+inst_134:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xb503, x1, 500, x5)
+
+inst_135:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x66666665, x1, 504, x5)
+
+inst_136:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x33333332, x1, 508, x5)
+
+inst_137:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaa9, x1, 512, x5)
+
+inst_138:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x55555554, x1, 516, x5)
+
+inst_139:
+// rs1_val==1 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x2, x1, 520, x5)
+
+inst_140:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xffff, x1, 524, x5)
+
+inst_141:
+// rs1_val==1 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xb504, x1, 528, x5)
+
+inst_142:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x66666666, x1, 532, x5)
+
+inst_143:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x33333333, x1, 536, x5)
+
+inst_144:
+// rs1_val==1 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x5, x1, 540, x5)
+
+inst_145:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0xaaaaaaaa, x1, 544, x5)
+
+inst_146:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x55555555, x1, 548, x5)
+
+inst_147:
+// rs1_val==1 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x1, 0x3, x1, 552, x5)
+
+inst_148:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x10000, x1, 556, x5)
+
+inst_149:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x1, x1, 560, x5)
+
+inst_150:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0xb505, x1, 564, x5)
+
+inst_151:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0xb505, 0x66666667, x1, 568, x5)
+
+inst_152:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0xb505, 0x33333334, x1, 572, x5)
+
+inst_153:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x6, x1, 576, x5)
+
+inst_154:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ae, 0xb505, 0xaaaaaaab, x1, 580, x5)
+
+inst_155:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c57, 0xb505, 0x55555556, x1, 584, x5)
+
+inst_156:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x4, x1, 588, x5)
+
+inst_157:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0xfffe, x1, 592, x5)
+
+inst_158:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x0, x1, 596, x5)
+
+inst_159:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0xb503, x1, 600, x5)
+
+inst_160:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0xb505, 0x66666665, x1, 604, x5)
+
+inst_161:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0xb505, 0x33333332, x1, 608, x5)
+
+inst_162:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xb505, 0xaaaaaaa9, x1, 612, x5)
+
+inst_163:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb505, 0x55555554, x1, 616, x5)
+
+inst_164:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x2, x1, 620, x5)
+
+inst_165:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0xffff, x1, 624, x5)
+
+inst_166:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0xb504, x1, 628, x5)
+
+inst_167:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0xb505, 0x66666666, x1, 632, x5)
+
+inst_168:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0xb505, 0x33333333, x1, 636, x5)
+
+inst_169:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x5, x1, 640, x5)
+
+inst_170:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xb505, 0xaaaaaaaa, x1, 644, x5)
+
+inst_171:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb505, 0x55555555, x1, 648, x5)
+
+inst_172:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb505, 0x3, x1, 652, x5)
+
+inst_173:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x66666667, 0x10000, x1, 656, x5)
+
+inst_174:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666667, 0x1, x1, 660, x5)
+
+inst_175:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0x66666667, 0xb505, x1, 664, x5)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666667, x1, 668, x5)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae148, 0x66666667, 0x33333334, x1, 672, x5)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x66666667, 0x6, x1, 676, x5)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0x66666667, 0xaaaaaaab, x1, 680, x5)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x66666667, 0x55555556, x1, 684, x5)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666667, 0x4, x1, 688, x5)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0x66666667, 0xfffe, x1, 692, x5)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666667, 0x0, x1, 696, x5)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0x66666667, 0xb503, x1, 700, x5)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666665, x1, 704, x5)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333332, x1, 708, x5)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0x66666667, 0xaaaaaaa9, x1, 712, x5)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666667, 0x55555554, x1, 716, x5)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666667, 0x2, x1, 720, x5)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x66666667, 0xffff, x1, 724, x5)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0x66666667, 0xb504, x1, 728, x5)
+
+inst_192:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666667, 0x66666666, x1, 732, x5)
+
+inst_193:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666667, 0x33333333, x1, 736, x5)
+
+inst_194:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x66666667, 0x5, x1, 740, x5)
+
+inst_195:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0x66666667, 0xaaaaaaaa, x1, 744, x5)
+
+inst_196:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x66666667, 0x55555555, x1, 748, x5)
+
+inst_197:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666667, 0x3, x1, 752, x5)
+
+inst_198:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x33333334, 0x10000, x1, 756, x5)
+
+inst_199:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0x33333334, 0xb505, x1, 760, x5)
+
+inst_200:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae148, 0x33333334, 0x66666667, x1, 764, x5)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a4, 0x33333334, 0x33333334, x1, 768, x5)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x33333334, 0x6, x1, 772, x5)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaab, x1, 776, x5)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555556, x1, 780, x5)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333334, 0x4, x1, 784, x5)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0x33333334, 0xfffe, x1, 788, x5)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333334, 0x0, x1, 792, x5)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0x33333334, 0xb503, x1, 796, x5)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666665, x1, 800, x5)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333332, x1, 804, x5)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaa9, x1, 808, x5)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555554, x1, 812, x5)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333334, 0x2, x1, 816, x5)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x33333334, 0xffff, x1, 820, x5)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0x33333334, 0xb504, x1, 824, x5)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333334, 0x66666666, x1, 828, x5)
+
+inst_217:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333334, 0x33333333, x1, 832, x5)
+
+inst_218:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x33333334, 0x5, x1, 836, x5)
+
+inst_219:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x33333334, 0xaaaaaaaa, x1, 840, x5)
+
+inst_220:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x33333334, 0x55555555, x1, 844, x5)
+
+inst_221:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333334, 0x3, x1, 848, x5)
+
+inst_222:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x10000, x1, 852, x5)
+
+inst_223:
+// rs1_val==6 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x1, x1, 856, x5)
+
+inst_224:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0xb505, x1, 860, x5)
+
+inst_225:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x6, 0x66666667, x1, 864, x5)
+
+inst_226:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x6, 0x33333334, x1, 868, x5)
+
+inst_227:
+// rs1_val==6 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x6, x1, 872, x5)
+
+inst_228:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4, 0x6, 0xaaaaaaab, x1, 876, x5)
+
+inst_229:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x6, 0x55555556, x1, 880, x5)
+
+inst_230:
+// rs1_val==6 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x4, x1, 884, x5)
+
+inst_231:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0xfffe, x1, 888, x5)
+
+inst_232:
+// rs1_val==6 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x0, x1, 892, x5)
+
+inst_233:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0xb503, x1, 896, x5)
+
+inst_234:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x6, 0x66666665, x1, 900, x5)
+
+inst_235:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x6, 0x33333332, x1, 904, x5)
+
+inst_236:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x6, 0xaaaaaaa9, x1, 908, x5)
+
+inst_237:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x6, 0x55555554, x1, 912, x5)
+
+inst_238:
+// rs1_val==6 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x2, x1, 916, x5)
+
+inst_239:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0xffff, x1, 920, x5)
+
+inst_240:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0xb504, x1, 924, x5)
+
+inst_241:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x6, 0x66666666, x1, 928, x5)
+
+inst_242:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x6, 0x33333333, x1, 932, x5)
+
+inst_243:
+// rs1_val==6 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x5, x1, 936, x5)
+
+inst_244:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x6, 0xaaaaaaaa, x1, 940, x5)
+
+inst_245:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x6, 0x55555555, x1, 944, x5)
+
+inst_246:
+// rs1_val==6 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x6, 0x3, x1, 948, x5)
+
+inst_247:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0xaaaaaaab, 0x10000, x1, 952, x5)
+
+inst_248:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x1, x1, 956, x5)
+
+inst_249:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ae, 0xaaaaaaab, 0xb505, x1, 960, x5)
+
+inst_250:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0xaaaaaaab, 0x66666667, x1, 964, x5)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0xaaaaaaab, 0x33333334, x1, 968, x5)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4, 0xaaaaaaab, 0x6, x1, 972, x5)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c72, 0xaaaaaaab, 0xaaaaaaab, x1, 976, x5)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e39, 0xaaaaaaab, 0x55555556, x1, 980, x5)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0xaaaaaaab, 0x4, x1, 984, x5)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xaaaaaaab, 0xfffe, x1, 988, x5)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x0, x1, 992, x5)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xaaaaaaab, 0xb503, x1, 996, x5)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0xaaaaaaab, 0x66666665, x1, 1000, x5)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0xaaaaaaab, 0x33333332, x1, 1004, x5)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c70, 0xaaaaaaab, 0xaaaaaaa9, x1, 1008, x5)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0xaaaaaaab, 0x55555554, x1, 1012, x5)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x2, x1, 1016, x5)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0xaaaaaaab, 0xffff, x1, 1020, x5)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xaaaaaaab, 0xb504, x1, 1024, x5)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0xaaaaaaab, 0x66666666, x1, 1028, x5)
+
+inst_267:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0xaaaaaaab, 0x33333333, x1, 1032, x5)
+
+inst_268:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x5, x1, 1036, x5)
+
+inst_269:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c71, 0xaaaaaaab, 0xaaaaaaaa, x1, 1040, x5)
+
+inst_270:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0xaaaaaaab, 0x55555555, x1, 1044, x5)
+
+inst_271:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0xaaaaaaab, 0x3, x1, 1048, x5)
+
+inst_272:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x55555556, 0x10000, x1, 1052, x5)
+
+inst_273:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555556, 0x1, x1, 1056, x5)
+
+inst_274:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c57, 0x55555556, 0xb505, x1, 1060, x5)
+
+inst_275:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x55555556, 0x66666667, x1, 1064, x5)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x55555556, 0x33333334, x1, 1068, x5)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x55555556, 0x6, x1, 1072, x5)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e39, 0x55555556, 0xaaaaaaab, x1, 1076, x5)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555556, x1, 1080, x5)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555556, 0x4, x1, 1084, x5)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0x55555556, 0xfffe, x1, 1088, x5)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555556, 0x0, x1, 1092, x5)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555556, 0xb503, x1, 1096, x5)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555556, 0x66666665, x1, 1100, x5)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x55555556, 0x33333332, x1, 1104, x5)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0x55555556, 0xaaaaaaa9, x1, 1108, x5)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555554, x1, 1112, x5)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555556, 0x2, x1, 1116, x5)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x55555556, 0xffff, x1, 1120, x5)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555556, 0xb504, x1, 1124, x5)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x55555556, 0x66666666, x1, 1128, x5)
+
+inst_292:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x55555556, 0x33333333, x1, 1132, x5)
+
+inst_293:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555556, 0x5, x1, 1136, x5)
+
+inst_294:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e39, 0x55555556, 0xaaaaaaaa, x1, 1140, x5)
+
+inst_295:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555556, 0x55555555, x1, 1144, x5)
+
+inst_296:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555556, 0x3, x1, 1148, x5)
+
+inst_297:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x10000, x1, 1152, x5)
+
+inst_298:
+// rs1_val==4 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x1, x1, 1156, x5)
+
+inst_299:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0xb505, x1, 1160, x5)
+
+inst_300:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x66666667, x1, 1164, x5)
+
+inst_301:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x33333334, x1, 1168, x5)
+
+inst_302:
+// rs1_val==4 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x6, x1, 1172, x5)
+
+inst_303:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaab, x1, 1176, x5)
+
+inst_304:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x55555556, x1, 1180, x5)
+
+inst_305:
+// rs1_val==4 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x4, x1, 1184, x5)
+
+inst_306:
+// rs1_val==4 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x0, x1, 1188, x5)
+
+inst_307:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0xb503, x1, 1192, x5)
+
+inst_308:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x66666665, x1, 1196, x5)
+
+inst_309:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x33333332, x1, 1200, x5)
+
+inst_310:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaa9, x1, 1204, x5)
+
+inst_311:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x55555554, x1, 1208, x5)
+
+inst_312:
+// rs1_val==4 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x2, x1, 1212, x5)
+
+inst_313:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0xffff, x1, 1216, x5)
+
+inst_314:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0xb504, x1, 1220, x5)
+
+inst_315:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x66666666, x1, 1224, x5)
+
+inst_316:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x33333333, x1, 1228, x5)
+
+inst_317:
+// rs1_val==4 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x5, x1, 1232, x5)
+
+inst_318:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x4, 0xaaaaaaaa, x1, 1236, x5)
+
+inst_319:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x4, 0x55555555, x1, 1240, x5)
+
+inst_320:
+// rs1_val==4 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x4, 0x3, x1, 1244, x5)
+
+inst_321:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x10000, x1, 1248, x5)
+
+inst_322:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x1, x1, 1252, x5)
+
+inst_323:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0xb505, x1, 1256, x5)
+
+inst_324:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0xfffe, 0x66666667, x1, 1260, x5)
+
+inst_325:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0xfffe, 0x33333334, x1, 1264, x5)
+
+inst_326:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x6, x1, 1268, x5)
+
+inst_327:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xfffe, 0xaaaaaaab, x1, 1272, x5)
+
+inst_328:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0xfffe, 0x55555556, x1, 1276, x5)
+
+inst_329:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x4, x1, 1280, x5)
+
+inst_330:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0xfffe, x1, 1284, x5)
+
+inst_331:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x0, x1, 1288, x5)
+
+inst_332:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0xb503, x1, 1292, x5)
+
+inst_333:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0xfffe, 0x66666665, x1, 1296, x5)
+
+inst_334:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0xfffe, 0x33333332, x1, 1300, x5)
+
+inst_335:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xfffe, 0xaaaaaaa9, x1, 1304, x5)
+
+inst_336:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0xfffe, 0x55555554, x1, 1308, x5)
+
+inst_337:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x2, x1, 1312, x5)
+
+inst_338:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0xffff, x1, 1316, x5)
+
+inst_339:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0xb504, x1, 1320, x5)
+
+inst_340:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0xfffe, 0x66666666, x1, 1324, x5)
+
+inst_341:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0xfffe, 0x33333333, x1, 1328, x5)
+
+inst_342:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x5, x1, 1332, x5)
+
+inst_343:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xfffe, 0xaaaaaaaa, x1, 1336, x5)
+
+inst_344:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0xfffe, 0x55555555, x1, 1340, x5)
+
+inst_345:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xfffe, 0x3, x1, 1344, x5)
+
+inst_346:
+// rs1_val==0 and rs2_val==65536, rs1_val == 0
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x10000, x1, 1348, x5)
+
+inst_347:
+// rs1_val==0 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x1, x1, 1352, x5)
+
+inst_348:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1356, x5)
+
+inst_349:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1360, x5)
+
+inst_350:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1364, x5)
+
+inst_351:
+// rs1_val==0 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1368, x5)
+
+inst_352:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaab, x1, 1372, x5)
+
+inst_353:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1376, x5)
+
+inst_354:
+// rs1_val==0 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1380, x5)
+
+inst_355:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xfffe, x1, 1384, x5)
+
+inst_356:
+// rs1_val==0 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1388, x5)
+
+inst_357:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1392, x5)
+
+inst_358:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1396, x5)
+
+inst_359:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1400, x5)
+
+inst_360:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaa9, x1, 1404, x5)
+
+inst_361:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1408, x5)
+
+inst_362:
+// rs1_val==0 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x2, x1, 1412, x5)
+
+inst_363:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xffff, x1, 1416, x5)
+
+inst_364:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1420, x5)
+
+inst_365:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1424, x5)
+
+inst_366:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1428, x5)
+
+inst_367:
+// rs1_val==0 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1432, x5)
+
+inst_368:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaaa, x1, 1436, x5)
+
+inst_369:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1440, x5)
+
+inst_370:
+// rs1_val==0 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1444, x5)
+
+inst_371:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x10000, x1, 1448, x5)
+
+inst_372:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x1, x1, 1452, x5)
+
+inst_373:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0xb505, x1, 1456, x5)
+
+inst_374:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0xb503, 0x66666667, x1, 1460, x5)
+
+inst_375:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0xb503, 0x33333334, x1, 1464, x5)
+
+inst_376:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x6, x1, 1468, x5)
+
+inst_377:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaab, x1, 1472, x5)
+
+inst_378:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb503, 0x55555556, x1, 1476, x5)
+
+inst_379:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x4, x1, 1480, x5)
+
+inst_380:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0xfffe, x1, 1484, x5)
+
+inst_381:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x0, x1, 1488, x5)
+
+inst_382:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0xb503, x1, 1492, x5)
+
+inst_383:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0xb503, 0x66666665, x1, 1496, x5)
+
+inst_384:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0xb503, 0x33333332, x1, 1500, x5)
+
+inst_385:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaa9, x1, 1504, x5)
+
+inst_386:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb503, 0x55555554, x1, 1508, x5)
+
+inst_387:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x2, x1, 1512, x5)
+
+inst_388:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0xffff, x1, 1516, x5)
+
+inst_389:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0xb504, x1, 1520, x5)
+
+inst_390:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0xb503, 0x66666666, x1, 1524, x5)
+
+inst_391:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0xb503, 0x33333333, x1, 1528, x5)
+
+inst_392:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x5, x1, 1532, x5)
+
+inst_393:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xb503, 0xaaaaaaaa, x1, 1536, x5)
+
+inst_394:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb503, 0x55555555, x1, 1540, x5)
+
+inst_395:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb503, 0x3, x1, 1544, x5)
+
+inst_396:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x66666665, 0x10000, x1, 1548, x5)
+
+inst_397:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666665, 0x1, x1, 1552, x5)
+
+inst_398:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0x66666665, 0xb505, x1, 1556, x5)
+
+inst_399:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666665, 0x66666667, x1, 1560, x5)
+
+inst_400:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333334, x1, 1564, x5)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x66666665, 0x6, x1, 1568, x5)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0x66666665, 0xaaaaaaab, x1, 1572, x5)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555556, x1, 1576, x5)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666665, 0x4, x1, 1580, x5)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0x66666665, 0xfffe, x1, 1584, x5)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666665, 0x0, x1, 1588, x5)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0x66666665, 0xb503, x1, 1592, x5)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666665, x1, 1596, x5)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae146, 0x66666665, 0x33333332, x1, 1600, x5)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444442, 0x66666665, 0xaaaaaaa9, x1, 1604, x5)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555554, x1, 1608, x5)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666665, 0x2, x1, 1612, x5)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0x66666665, 0xffff, x1, 1616, x5)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0x66666665, 0xb504, x1, 1620, x5)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28e, 0x66666665, 0x66666666, x1, 1624, x5)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666665, 0x33333333, x1, 1628, x5)
+
+inst_417:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666665, 0x5, x1, 1632, x5)
+
+inst_418:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0x66666665, 0xaaaaaaaa, x1, 1636, x5)
+
+inst_419:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666665, 0x55555555, x1, 1640, x5)
+
+inst_420:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666665, 0x3, x1, 1644, x5)
+
+inst_421:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x33333332, 0x10000, x1, 1648, x5)
+
+inst_422:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x1, x1, 1652, x5)
+
+inst_423:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0x33333332, 0xb505, x1, 1656, x5)
+
+inst_424:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666667, x1, 1660, x5)
+
+inst_425:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333334, x1, 1664, x5)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x33333332, 0x6, x1, 1668, x5)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaab, x1, 1672, x5)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555556, x1, 1676, x5)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x4, x1, 1680, x5)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0x33333332, 0xfffe, x1, 1684, x5)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x0, x1, 1688, x5)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0x33333332, 0xb503, x1, 1692, x5)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae146, 0x33333332, 0x66666665, x1, 1696, x5)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333332, x1, 1700, x5)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaa9, x1, 1704, x5)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555554, x1, 1708, x5)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x2, x1, 1712, x5)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0x33333332, 0xffff, x1, 1716, x5)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0x33333332, 0xb504, x1, 1720, x5)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333332, 0x66666666, x1, 1724, x5)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333332, 0x33333333, x1, 1728, x5)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x5, x1, 1732, x5)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x33333332, 0xaaaaaaaa, x1, 1736, x5)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x33333332, 0x55555555, x1, 1740, x5)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333332, 0x3, x1, 1744, x5)
+
+inst_446:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0xaaaaaaa9, 0x10000, x1, 1748, x5)
+
+inst_447:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x1, x1, 1752, x5)
+
+inst_448:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xaaaaaaa9, 0xb505, x1, 1756, x5)
+
+inst_449:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0xaaaaaaa9, 0x66666667, x1, 1760, x5)
+
+inst_450:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0xaaaaaaa9, 0x33333334, x1, 1764, x5)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0xaaaaaaa9, 0x6, x1, 1768, x5)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c70, 0xaaaaaaa9, 0xaaaaaaab, x1, 1772, x5)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0xaaaaaaa9, 0x55555556, x1, 1776, x5)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0xaaaaaaa9, 0x4, x1, 1780, x5)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xaaaaaaa9, 0xfffe, x1, 1784, x5)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x0, x1, 1788, x5)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xaaaaaaa9, 0xb503, x1, 1792, x5)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444442, 0xaaaaaaa9, 0x66666665, x1, 1796, x5)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0xaaaaaaa9, 0x33333332, x1, 1800, x5)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c6f, 0xaaaaaaa9, 0xaaaaaaa9, x1, 1804, x5)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e37, 0xaaaaaaa9, 0x55555554, x1, 1808, x5)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x2, x1, 1812, x5)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xaaaaaaa9, 0xffff, x1, 1816, x5)
+
+inst_464:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xaaaaaaa9, 0xb504, x1, 1820, x5)
+
+inst_465:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0xaaaaaaa9, 0x66666666, x1, 1824, x5)
+
+inst_466:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0xaaaaaaa9, 0x33333333, x1, 1828, x5)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555554, 0x4, x1, 1832, x5)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0x55555554, 0xfffe, x1, 1836, x5)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555554, 0x0, x1, 1840, x5)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555554, 0xb503, x1, 1844, x5)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666665, x1, 1848, x5)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x55555554, 0x33333332, x1, 1852, x5)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e37, 0x55555554, 0xaaaaaaa9, x1, 1856, x5)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555554, x1, 1860, x5)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555554, 0x2, x1, 1864, x5)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0x55555554, 0xffff, x1, 1868, x5)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555554, 0xb504, x1, 1872, x5)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666666, x1, 1876, x5)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x55555554, 0x33333333, x1, 1880, x5)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555554, 0x5, x1, 1884, x5)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e37, 0x55555554, 0xaaaaaaaa, x1, 1888, x5)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71b, 0x55555554, 0x55555555, x1, 1892, x5)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555554, 0x3, x1, 1896, x5)
+
+inst_484:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x10000, x1, 1900, x5)
+
+inst_485:
+// rs1_val==2 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x1, x1, 1904, x5)
+
+inst_486:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0xb505, x1, 1908, x5)
+
+inst_487:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x66666667, x1, 1912, x5)
+
+inst_488:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x33333334, x1, 1916, x5)
+
+inst_489:
+// rs1_val==2 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x6, x1, 1920, x5)
+
+inst_490:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaab, x1, 1924, x5)
+
+inst_491:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x55555556, x1, 1928, x5)
+
+inst_492:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0xfffe, x1, 1932, x5)
+
+inst_493:
+// rs1_val==2 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x0, x1, 1936, x5)
+
+inst_494:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0xb503, x1, 1940, x5)
+
+inst_495:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x66666665, x1, 1944, x5)
+
+inst_496:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x33333332, x1, 1948, x5)
+
+inst_497:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaa9, x1, 1952, x5)
+
+inst_498:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x55555554, x1, 1956, x5)
+
+inst_499:
+// rs1_val==2 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x2, x1, 1960, x5)
+
+inst_500:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0xffff, x1, 1964, x5)
+
+inst_501:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0xb504, x1, 1968, x5)
+
+inst_502:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x66666666, x1, 1972, x5)
+
+inst_503:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x33333333, x1, 1976, x5)
+
+inst_504:
+// rs1_val==2 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x5, x1, 1980, x5)
+
+inst_505:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaaa, x1, 1984, x5)
+
+inst_506:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x55555555, x1, 1988, x5)
+
+inst_507:
+// rs1_val==2 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x2, 0x3, x1, 1992, x5)
+
+inst_508:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x10000, x1, 1996, x5)
+
+inst_509:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x1, x1, 2000, x5)
+
+inst_510:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0xb505, x1, 2004, x5)
+
+inst_511:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0xffff, 0x66666667, x1, 2008, x5)
+
+inst_512:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0xffff, 0x33333334, x1, 2012, x5)
+
+inst_513:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x6, x1, 2016, x5)
+
+inst_514:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0xffff, 0xaaaaaaab, x1, 2020, x5)
+
+inst_515:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0xffff, 0x55555556, x1, 2024, x5)
+
+inst_516:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x4, x1, 2028, x5)
+
+inst_517:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0xfffe, x1, 2032, x5)
+
+inst_518:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x0, x1, 2036, x5)
+
+inst_519:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0xb503, x1, 2040, x5)
+
+inst_520:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0xffff, 0x66666665, x1, 2044, x5)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_521:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0xffff, 0x33333332, x1, 0, x5)
+
+inst_522:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xffff, 0xaaaaaaa9, x1, 4, x5)
+
+inst_523:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0xffff, 0x55555554, x1, 8, x5)
+
+inst_524:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x2, x1, 12, x5)
+
+inst_525:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0xffff, x1, 16, x5)
+
+inst_526:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0xb504, x1, 20, x5)
+
+inst_527:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0xffff, 0x66666666, x1, 24, x5)
+
+inst_528:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0xffff, 0x33333333, x1, 28, x5)
+
+inst_529:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x5, x1, 32, x5)
+
+inst_530:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xffff, 0xaaaaaaaa, x1, 36, x5)
+
+inst_531:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0xffff, 0x55555555, x1, 40, x5)
+
+inst_532:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xffff, 0x3, x1, 44, x5)
+
+inst_533:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x10000, x1, 48, x5)
+
+inst_534:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x1, x1, 52, x5)
+
+inst_535:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0xb505, x1, 56, x5)
+
+inst_536:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0xb504, 0x66666667, x1, 60, x5)
+
+inst_537:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0xb504, 0x33333334, x1, 64, x5)
+
+inst_538:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x6, x1, 68, x5)
+
+inst_539:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaab, x1, 72, x5)
+
+inst_540:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb504, 0x55555556, x1, 76, x5)
+
+inst_541:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x4, x1, 80, x5)
+
+inst_542:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0xfffe, x1, 84, x5)
+
+inst_543:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x0, x1, 88, x5)
+
+inst_544:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0xb503, x1, 92, x5)
+
+inst_545:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0xb504, 0x66666665, x1, 96, x5)
+
+inst_546:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0xb504, 0x33333332, x1, 100, x5)
+
+inst_547:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaa9, x1, 104, x5)
+
+inst_548:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb504, 0x55555554, x1, 108, x5)
+
+inst_549:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x2, x1, 112, x5)
+
+inst_550:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0xffff, x1, 116, x5)
+
+inst_551:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0xb504, x1, 120, x5)
+
+inst_552:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0xb504, 0x66666666, x1, 124, x5)
+
+inst_553:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0xb504, 0x33333333, x1, 128, x5)
+
+inst_554:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x5, x1, 132, x5)
+
+inst_555:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xb504, 0xaaaaaaaa, x1, 136, x5)
+
+inst_556:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0xb504, 0x55555555, x1, 140, x5)
+
+inst_557:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xb504, 0x3, x1, 144, x5)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6666, 0x66666666, 0x10000, x1, 148, x5)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666666, 0x1, x1, 152, x5)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4868, 0x66666666, 0xb505, x1, 156, x5)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666667, x1, 160, x5)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333334, x1, 164, x5)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x66666666, 0x6, x1, 168, x5)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0x66666666, 0xaaaaaaab, x1, 172, x5)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x66666666, 0x55555556, x1, 176, x5)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666666, 0x4, x1, 180, x5)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0x66666666, 0xfffe, x1, 184, x5)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666666, 0x0, x1, 188, x5)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0x66666666, 0xb503, x1, 192, x5)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28e, 0x66666666, 0x66666665, x1, 196, x5)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333332, x1, 200, x5)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0x66666666, 0xaaaaaaa9, x1, 204, x5)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666666, 0x55555554, x1, 208, x5)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x66666666, 0x2, x1, 212, x5)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6665, 0x66666666, 0xffff, x1, 216, x5)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x4867, 0x66666666, 0xb504, x1, 220, x5)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x28f5c28f, 0x66666666, 0x66666666, x1, 224, x5)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x66666666, 0x33333333, x1, 228, x5)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666666, 0x5, x1, 232, x5)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0x66666666, 0xaaaaaaaa, x1, 236, x5)
+
+inst_581:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x66666666, 0x55555555, x1, 240, x5)
+
+inst_582:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x66666666, 0x3, x1, 244, x5)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3333, 0x33333333, 0x10000, x1, 248, x5)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x1, x1, 252, x5)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2434, 0x33333333, 0xb505, x1, 256, x5)
+
+inst_586:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666667, x1, 260, x5)
+
+inst_587:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333334, x1, 264, x5)
+
+inst_588:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x33333333, 0x6, x1, 268, x5)
+
+inst_589:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x33333333, 0xaaaaaaab, x1, 272, x5)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x33333333, 0x55555556, x1, 276, x5)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x4, x1, 280, x5)
+
+inst_592:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0x33333333, 0xfffe, x1, 284, x5)
+
+inst_593:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x0, x1, 288, x5)
+
+inst_594:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0x33333333, 0xb503, x1, 292, x5)
+
+inst_595:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x55555554, 0x10000, x1, 296, x5)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666665, x1, 300, x5)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333332, x1, 304, x5)
+
+inst_598:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555554, 0x66666667, x1, 308, x5)
+
+inst_599:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x33333333, 0xaaaaaaa9, x1, 312, x5)
+
+inst_600:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x33333333, 0x55555554, x1, 316, x5)
+
+inst_601:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x2, x1, 320, x5)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3332, 0x33333333, 0xffff, x1, 324, x5)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2433, 0x33333333, 0xb504, x1, 328, x5)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x147ae147, 0x33333333, 0x66666666, x1, 332, x5)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0xa3d70a3, 0x33333333, 0x33333333, x1, 336, x5)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x5, x1, 340, x5)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x33333333, 0xaaaaaaaa, x1, 344, x5)
+
+inst_608:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x33333333, 0x55555555, x1, 348, x5)
+
+inst_609:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x33333333, 0x3, x1, 352, x5)
+
+inst_610:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x10000, x1, 356, x5)
+
+inst_611:
+// rs1_val==5 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x1, x1, 360, x5)
+
+inst_612:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0xb505, x1, 364, x5)
+
+inst_613:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x5, 0x66666667, x1, 368, x5)
+
+inst_614:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x33333334, x1, 372, x5)
+
+inst_615:
+// rs1_val==5 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x6, x1, 376, x5)
+
+inst_616:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaab, x1, 380, x5)
+
+inst_617:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x55555556, x1, 384, x5)
+
+inst_618:
+// rs1_val==5 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x4, x1, 388, x5)
+
+inst_619:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0xfffe, x1, 392, x5)
+
+inst_620:
+// rs1_val==5 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x0, x1, 396, x5)
+
+inst_621:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0xb503, x1, 400, x5)
+
+inst_622:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x66666665, x1, 404, x5)
+
+inst_623:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x33333332, x1, 408, x5)
+
+inst_624:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaa9, x1, 412, x5)
+
+inst_625:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x55555554, x1, 416, x5)
+
+inst_626:
+// rs1_val==5 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x2, x1, 420, x5)
+
+inst_627:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0xffff, x1, 424, x5)
+
+inst_628:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0xb504, x1, 428, x5)
+
+inst_629:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x66666666, x1, 432, x5)
+
+inst_630:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x33333333, x1, 436, x5)
+
+inst_631:
+// rs1_val==5 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x5, x1, 440, x5)
+
+inst_632:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0x5, 0xaaaaaaaa, x1, 444, x5)
+
+inst_633:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x5, 0x55555555, x1, 448, x5)
+
+inst_634:
+// rs1_val==5 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x5, 0x3, x1, 452, x5)
+
+inst_635:
+// rs1_val==2863311530 and rs2_val==65536, rs1_val == 2863311530
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaaa, 0xaaaaaaaa, 0x10000, x1, 456, x5)
+
+inst_636:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x1, x1, 460, x5)
+
+inst_637:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xaaaaaaaa, 0xb505, x1, 464, x5)
+
+inst_638:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444444, 0xaaaaaaaa, 0x66666667, x1, 468, x5)
+
+inst_639:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0xaaaaaaaa, 0x33333334, x1, 472, x5)
+
+inst_640:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0xaaaaaaaa, 0x6, x1, 476, x5)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c71, 0xaaaaaaaa, 0xaaaaaaab, x1, 480, x5)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e39, 0xaaaaaaaa, 0x55555556, x1, 484, x5)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x4, x1, 488, x5)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xaaaaaaaa, 0xfffe, x1, 492, x5)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x0, x1, 496, x5)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ac, 0xaaaaaaaa, 0xb503, x1, 500, x5)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0xaaaaaaaa, 0x66666665, x1, 504, x5)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0xaaaaaaaa, 0x33333332, x1, 508, x5)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c70, 0xaaaaaaaa, 0xaaaaaaa9, x1, 512, x5)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e37, 0xaaaaaaaa, 0x55555554, x1, 516, x5)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x2, x1, 520, x5)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xaaa9, 0xaaaaaaaa, 0xffff, x1, 524, x5)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x78ad, 0xaaaaaaaa, 0xb504, x1, 528, x5)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x44444443, 0xaaaaaaaa, 0x66666666, x1, 532, x5)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0xaaaaaaaa, 0x33333333, x1, 536, x5)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0xaaaaaaaa, 0x5, x1, 540, x5)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c70, 0xaaaaaaaa, 0xaaaaaaaa, x1, 544, x5)
+
+inst_658:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0xaaaaaaaa, 0x55555555, x1, 548, x5)
+
+inst_659:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0x3, x1, 552, x5)
+
+inst_660:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5555, 0x55555555, 0x10000, x1, 556, x5)
+
+inst_661:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555555, 0x1, x1, 560, x5)
+
+inst_662:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555555, 0xb505, x1, 564, x5)
+
+inst_663:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222222, 0x55555555, 0x66666667, x1, 568, x5)
+
+inst_664:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x55555555, 0x33333334, x1, 572, x5)
+
+inst_665:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555555, 0x6, x1, 576, x5)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaab, x1, 580, x5)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555556, x1, 584, x5)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555555, 0x4, x1, 588, x5)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0x55555555, 0xfffe, x1, 592, x5)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555555, 0x0, x1, 596, x5)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555555, 0xb503, x1, 600, x5)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555555, 0x66666665, x1, 604, x5)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x55555555, 0x33333332, x1, 608, x5)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaa9, x1, 612, x5)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71b, 0x55555555, 0x55555554, x1, 616, x5)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555555, 0x2, x1, 620, x5)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x5554, 0x55555555, 0xffff, x1, 624, x5)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555555, 0xb504, x1, 628, x5)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x22222221, 0x55555555, 0x66666666, x1, 632, x5)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111110, 0x55555555, 0x33333333, x1, 636, x5)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555555, 0x5, x1, 640, x5)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0x55555555, 0xaaaaaaaa, x1, 644, x5)
+
+inst_683:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555555, 0x55555555, x1, 648, x5)
+
+inst_684:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555555, 0x3, x1, 652, x5)
+
+inst_685:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x10000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x10000, x1, 656, x5)
+
+inst_686:
+// rs1_val==3 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x1, x1, 660, x5)
+
+inst_687:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0xb505, x1, 664, x5)
+
+inst_688:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0x66666667, x1, 668, x5)
+
+inst_689:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x33333334, x1, 672, x5)
+
+inst_690:
+// rs1_val==3 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x6, x1, 676, x5)
+
+inst_691:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x2, 0x3, 0xaaaaaaab, x1, 680, x5)
+
+inst_692:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0x55555556, x1, 684, x5)
+
+inst_693:
+// rs1_val==3 and rs2_val==4, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x4, x1, 688, x5)
+
+inst_694:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xfffe
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0xfffe, x1, 692, x5)
+
+inst_695:
+// rs1_val==3 and rs2_val==0, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x0, x1, 696, x5)
+
+inst_696:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0xb503, x1, 700, x5)
+
+inst_697:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0x66666665, x1, 704, x5)
+
+inst_698:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x33333332, x1, 708, x5)
+
+inst_699:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaa9
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaa9, x1, 712, x5)
+
+inst_700:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x55555554, x1, 716, x5)
+
+inst_701:
+// rs1_val==3 and rs2_val==2, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x2, x1, 720, x5)
+
+inst_702:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0xffff, x1, 724, x5)
+
+inst_703:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0xb504, x1, 728, x5)
+
+inst_704:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0x66666666, x1, 732, x5)
+
+inst_705:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x33333333, x1, 736, x5)
+
+inst_706:
+// rs1_val==3 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x5, x1, 740, x5)
+
+inst_707:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaaa, x1, 744, x5)
+
+inst_708:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x55555555, x1, 748, x5)
+
+inst_709:
+// rs1_val==3 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x3, 0x3, x1, 752, x5)
+
+inst_710:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x5
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3, 0xaaaaaaa9, 0x5, x1, 756, x5)
+
+inst_711:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaaa
+TEST_RR_OP(mulhu, x12, x10, x11, 0x71c71c70, 0xaaaaaaa9, 0xaaaaaaaa, x1, 760, x5)
+
+inst_712:
+// rs1_val == (2**(xlen)-1), 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff;  op2val:0x2000
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1fff, 0xffffffff, 0x2000, x1, 764, x5)
+
+inst_713:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555555
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0xaaaaaaa9, 0x55555555, x1, 768, x5)
+
+inst_714:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x3
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x3, x1, 772, x5)
+
+inst_715:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(mulhu, x12, x10, x11, 0x0, 0x55555554, 0x1, x1, 776, x5)
+
+inst_716:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(mulhu, x12, x10, x11, 0x3c56, 0x55555554, 0xb505, x1, 780, x5)
+
+inst_717:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(mulhu, x12, x10, x11, 0x11111111, 0x55555554, 0x33333334, x1, 784, x5)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1, 0x55555554, 0x6, x1, 788, x5)
+
+inst_719:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaab
+TEST_RR_OP(mulhu, x12, x10, x11, 0x38e38e38, 0x55555554, 0xaaaaaaab, x1, 792, x5)
+
+inst_720:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(mulhu, x12, x10, x11, 0x1c71c71c, 0x55555554, 0x55555556, x1, 796, x5)
+
+inst_721:
+// rs2_val == 3221225471, rs1_val == 4294443007
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0xfff7ffff;  op2val:0xbfffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0xbff9fffe, 0xfff7ffff, 0xbfffffff, x1, 800, x5)
+
+inst_722:
+// rs2_val == 3758096383, rs1_val == 524288
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0xdfffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x6ffff, 0x80000, 0xdfffffff, x1, 804, x5)
+
+inst_723:
+// rs2_val == 4261412863, 
+// opcode: mulhu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfdffffff
+TEST_RR_OP(mulhu, x12, x10, x11, 0x54aaaaa9, 0x55555554, 0xfdffffff, x1, 808, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 203*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/rem-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/rem-01.S
new file mode 100644
index 000000000..e677078d3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/rem-01.S
@@ -0,0 +1,3015 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the rem instruction of the RISC-V M extension for the rem covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",rem)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x11, rs2==x12, rd==x12, rs1_val != rs2_val, rs2_val == -4194305, rs1_val > 0 and rs2_val < 0
+// opcode: rem ; op1:x11; op2:x12; dest:x12; op1val:0xb503;  op2val:-0x400001
+TEST_RR_OP(rem, x12, x11, x12, 0xb503, 0xb503, -0x400001, x1, 0, x3)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x8, rs2==x7, rd==x8, rs2_val == 2147483647, rs1_val > 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1), rs1_val == 2048
+// opcode: rem ; op1:x8; op2:x7; dest:x8; op1val:0x800;  op2val:0x7fffffff
+TEST_RR_OP(rem, x8, x8, x7, 0x800, 0x800, 0x7fffffff, x1, 4, x3)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x15, rs2==x15, rd==x15, rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0, rs1_val == -67108865
+// opcode: rem ; op1:x15; op2:x15; dest:x15; op1val:-0x4000001;  op2val:-0x4000001
+TEST_RR_OP(rem, x15, x15, x15, 0x0, -0x4000001, -0x4000001, x1, 8, x3)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x13, rs2==x13, rd==x9, rs2_val == -536870913, rs1_val == -131073
+// opcode: rem ; op1:x13; op2:x13; dest:x9; op1val:-0x20001;  op2val:-0x20001
+TEST_RR_OP(rem, x9, x13, x13, 0x0, -0x20001, -0x20001, x1, 12, x3)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x6, rs2==x14, rd==x2, rs2_val == -268435457, rs1_val == -257
+// opcode: rem ; op1:x6; op2:x14; dest:x2; op1val:-0x101;  op2val:-0x10000001
+TEST_RR_OP(rem, x2, x6, x14, -0x101, -0x101, -0x10000001, x1, 16, x3)
+
+inst_5:
+// rs1==x10, rs2==x2, rd==x5, rs2_val == -134217729, rs1_val == -8388609
+// opcode: rem ; op1:x10; op2:x2; dest:x5; op1val:-0x800001;  op2val:-0x8000001
+TEST_RR_OP(rem, x5, x10, x2, -0x800001, -0x800001, -0x8000001, x1, 20, x3)
+RVTEST_SIGBASE( x8,signature_x8_0)
+
+inst_6:
+// rs1==x1, rs2==x11, rd==x3, rs2_val == -67108865, 
+// opcode: rem ; op1:x1; op2:x11; dest:x3; op1val:0x33333332;  op2val:-0x4000001
+TEST_RR_OP(rem, x3, x1, x11, 0x3333326, 0x33333332, -0x4000001, x8, 0, x12)
+
+inst_7:
+// rs1==x14, rs2==x0, rd==x4, rs2_val == -33554433, rs1_val == 67108864
+// opcode: rem ; op1:x14; op2:x0; dest:x4; op1val:0x4000000;  op2val:0x0
+TEST_RR_OP(rem, x4, x14, x0, 0x4000000, 0x4000000, 0x0, x8, 4, x12)
+
+inst_8:
+// rs1==x9, rs2==x6, rd==x14, rs2_val == -16777217, rs1_val == 1024
+// opcode: rem ; op1:x9; op2:x6; dest:x14; op1val:0x400;  op2val:-0x1000001
+TEST_RR_OP(rem, x14, x9, x6, 0x400, 0x400, -0x1000001, x8, 8, x12)
+
+inst_9:
+// rs1==x2, rs2==x5, rd==x11, rs2_val == -8388609, rs1_val == -17
+// opcode: rem ; op1:x2; op2:x5; dest:x11; op1val:-0x11;  op2val:-0x800001
+TEST_RR_OP(rem, x11, x2, x5, -0x11, -0x11, -0x800001, x8, 12, x12)
+
+inst_10:
+// rs1==x5, rs2==x9, rd==x13, rs2_val == -2097153, rs1_val == 2
+// opcode: rem ; op1:x5; op2:x9; dest:x13; op1val:0x2;  op2val:-0x200001
+TEST_RR_OP(rem, x13, x5, x9, 0x2, 0x2, -0x200001, x8, 16, x12)
+
+inst_11:
+// rs1==x7, rs2==x10, rd==x1, rs2_val == -1048577, 
+// opcode: rem ; op1:x7; op2:x10; dest:x1; op1val:-0x40000000;  op2val:-0x100001
+TEST_RR_OP(rem, x1, x7, x10, -0xffc01, -0x40000000, -0x100001, x8, 20, x12)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_12:
+// rs1==x0, rs2==x1, rd==x6, rs2_val == -524289, 
+// opcode: rem ; op1:x0; op2:x1; dest:x6; op1val:0x0;  op2val:-0x80001
+TEST_RR_OP(rem, x6, x0, x1, 0x0, 0x0, -0x80001, x2, 0, x5)
+
+inst_13:
+// rs1==x4, rs2==x3, rd==x10, rs2_val == -262145, 
+// opcode: rem ; op1:x4; op2:x3; dest:x10; op1val:0x33333334;  op2val:-0x40001
+TEST_RR_OP(rem, x10, x4, x3, 0x32668, 0x33333334, -0x40001, x2, 4, x5)
+
+inst_14:
+// rs1==x3, rs2==x8, rd==x7, rs2_val == -131073, rs1_val == 4
+// opcode: rem ; op1:x3; op2:x8; dest:x7; op1val:0x4;  op2val:-0x20001
+TEST_RR_OP(rem, x7, x3, x8, 0x4, 0x4, -0x20001, x2, 8, x5)
+
+inst_15:
+// rs1==x12, rs2==x4, rd==x0, rs2_val == -65537, 
+// opcode: rem ; op1:x12; op2:x4; dest:x0; op1val:-0x55555555;  op2val:-0x10001
+TEST_RR_OP(rem, x0, x12, x4, 0, -0x55555555, -0x10001, x2, 12, x5)
+
+inst_16:
+// rs2_val == -32769, rs1_val == -536870913
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:-0x8001
+TEST_RR_OP(rem, x12, x10, x11, -0x4002, -0x20000001, -0x8001, x2, 16, x5)
+
+inst_17:
+// rs2_val == -16385, rs1_val == 1431655765
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x4001
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x55555555, -0x4001, x2, 20, x5)
+
+inst_18:
+// rs2_val == -8193, rs1_val == 0
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x2001
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0x2001, x2, 24, x5)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x1001
+TEST_RR_OP(rem, x12, x10, x11, -0x4f9, -0xb504, -0x1001, x2, 28, x5)
+
+inst_20:
+// rs2_val == -2049, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x801
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0x801, x2, 32, x5)
+
+inst_21:
+// rs2_val == -1025, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x401
+TEST_RR_OP(rem, x12, x10, x11, 0x3fe, 0x7fffffff, -0x401, x2, 36, x5)
+
+inst_22:
+// rs2_val == -513, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x201
+TEST_RR_OP(rem, x12, x10, x11, 0x60, 0x33333333, -0x201, x2, 40, x5)
+
+inst_23:
+// rs2_val == -257, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:-0x101
+TEST_RR_OP(rem, x12, x10, x11, -0x3, -0x20001, -0x101, x2, 44, x5)
+
+inst_24:
+// rs2_val == -129, rs1_val == -65537
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x81
+TEST_RR_OP(rem, x12, x10, x11, -0x5, -0x10001, -0x81, x2, 48, x5)
+
+inst_25:
+// rs2_val == -65, rs1_val == 131072
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:-0x41
+TEST_RR_OP(rem, x12, x10, x11, 0x20, 0x20000, -0x41, x2, 52, x5)
+
+inst_26:
+// rs2_val == -33, rs1_val == -524289
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x21
+TEST_RR_OP(rem, x12, x10, x11, -0x12, -0x80001, -0x21, x2, 56, x5)
+
+inst_27:
+// rs2_val == -17, rs1_val == 8
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x11
+TEST_RR_OP(rem, x12, x10, x11, 0x8, 0x8, -0x11, x2, 60, x5)
+
+inst_28:
+// rs2_val == -9, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x9
+TEST_RR_OP(rem, x12, x10, x11, 0x8, 0x8, -0x9, x2, 64, x5)
+
+inst_29:
+// rs2_val == -5, rs1_val == -129
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:-0x5
+TEST_RR_OP(rem, x12, x10, x11, -0x4, -0x81, -0x5, x2, 68, x5)
+
+inst_30:
+// rs2_val == -3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x3
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, -0x3, x2, 72, x5)
+
+inst_31:
+// rs2_val == -2, rs1_val == 32768
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:-0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x8000, -0x2, x2, 76, x5)
+
+inst_32:
+// rs1_val == -1073741825, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:-0x10001
+TEST_RR_OP(rem, x12, x10, x11, -0xc002, -0x40000001, -0x10001, x2, 80, x5)
+
+inst_33:
+// rs1_val == -268435457, rs1_val < 0 and rs2_val > 0, rs2_val == 2
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x10000001, 0x2, x2, 84, x5)
+
+inst_34:
+// rs1_val == -134217729, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x801
+TEST_RR_OP(rem, x12, x10, x11, -0x21, -0x8000001, -0x801, x2, 88, x5)
+
+inst_35:
+// rs1_val == -33554433, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, -0x2000001, -0x2000001, 0x33333333, x2, 92, x5)
+
+inst_36:
+// rs1_val == -16777217, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0x1000001, -0x1000001, 0x33333334, x2, 96, x5)
+
+inst_37:
+// rs1_val == -4194305, rs2_val == 268435456
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x10000000
+TEST_RR_OP(rem, x12, x10, x11, -0x400001, -0x400001, 0x10000000, x2, 100, x5)
+
+inst_38:
+// rs1_val == -2097153, rs2_val == 1431655765
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0x200001, -0x200001, 0x55555555, x2, 104, x5)
+
+inst_39:
+// rs1_val == -1048577, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:-0x40000000
+TEST_RR_OP(rem, x12, x10, x11, -0x100001, -0x100001, -0x40000000, x2, 108, x5)
+
+inst_40:
+// rs1_val == -262145, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x76ed, -0x40001, -0xb504, x2, 112, x5)
+
+inst_41:
+// rs1_val == -32769, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x10000000
+TEST_RR_OP(rem, x12, x10, x11, -0x8001, -0x8001, 0x10000000, x2, 116, x5)
+
+inst_42:
+// rs1_val == -16385, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x7
+TEST_RR_OP(rem, x12, x10, x11, -0x5, -0x4001, 0x7, x2, 120, x5)
+
+inst_43:
+// rs1_val == -8193, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x4
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x2001, -0x4, x2, 124, x5)
+
+inst_44:
+// rs1_val == -4097, rs2_val == 4096
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x1000
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x1001, 0x1000, x2, 128, x5)
+
+inst_45:
+// rs1_val == -2049, rs2_val == 536870912
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x20000000
+TEST_RR_OP(rem, x12, x10, x11, -0x801, -0x801, 0x20000000, x2, 132, x5)
+
+inst_46:
+// rs1_val == -1025, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0x401, -0x401, 0x33333334, x2, 136, x5)
+
+inst_47:
+// rs1_val == -513, rs2_val == 0
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, -0x201, -0x201, 0x0, x2, 140, x5)
+
+inst_48:
+// rs1_val == -65, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x41, -0x41, 0xb504, x2, 144, x5)
+
+inst_49:
+// rs1_val == -33, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0x21, -0x21, -0x55555555, x2, 148, x5)
+
+inst_50:
+// rs1_val == -9, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, -0x9, -0x9, 0x55555554, x2, 152, x5)
+
+inst_51:
+// rs1_val == -5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x9
+TEST_RR_OP(rem, x12, x10, x11, -0x5, -0x5, 0x9, x2, 156, x5)
+
+inst_52:
+// rs1_val == -3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x6
+TEST_RR_OP(rem, x12, x10, x11, -0x3, -0x3, -0x6, x2, 160, x5)
+
+inst_53:
+// rs1_val == -2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0x2, 0x66666665, x2, 164, x5)
+
+inst_54:
+// rs2_val == -2147483648, rs1_val == 256, rs2_val == (-2**(xlen-1))
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:-0x80000000
+TEST_RR_OP(rem, x12, x10, x11, 0x100, 0x100, -0x80000000, x2, 168, x5)
+
+inst_55:
+// rs2_val == 1073741824, rs1_val == -1431655766
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x40000000
+TEST_RR_OP(rem, x12, x10, x11, -0x15555556, -0x55555556, 0x40000000, x2, 172, x5)
+
+inst_56:
+// rs2_val == 134217728, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x8000000
+TEST_RR_OP(rem, x12, x10, x11, -0x21, -0x21, 0x8000000, x2, 176, x5)
+
+inst_57:
+// rs2_val == 67108864, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4000000
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x4000000, x2, 180, x5)
+
+inst_58:
+// rs2_val == 33554432, rs1_val == 16
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x2000000
+TEST_RR_OP(rem, x12, x10, x11, 0x10, 0x10, 0x2000000, x2, 184, x5)
+
+inst_59:
+// rs2_val == 16777216, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1000000
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x1000000, x2, 188, x5)
+
+inst_60:
+// rs2_val == 8388608, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x800000
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x800000, x2, 192, x5)
+
+inst_61:
+// rs2_val == 4194304, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x400000
+TEST_RR_OP(rem, x12, x10, x11, 0x266667, 0x66666667, 0x400000, x2, 196, x5)
+
+inst_62:
+// rs2_val == 2097152, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x200000
+TEST_RR_OP(rem, x12, x10, x11, -0x155556, -0x55555556, 0x200000, x2, 200, x5)
+
+inst_63:
+// rs2_val == 1048576, rs1_val == 32
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x100000
+TEST_RR_OP(rem, x12, x10, x11, 0x20, 0x20, 0x100000, x2, 204, x5)
+
+inst_64:
+// rs2_val == 524288, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0x80000
+TEST_RR_OP(rem, x12, x10, x11, 0x7, 0x7, 0x80000, x2, 208, x5)
+
+inst_65:
+// rs2_val == 262144, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x40000
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x40000, x2, 212, x5)
+
+inst_66:
+// rs2_val == 131072, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x20000
+TEST_RR_OP(rem, x12, x10, x11, 0x6667, 0x66666667, 0x20000, x2, 216, x5)
+
+inst_67:
+// rs2_val == 65536, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x10000, x2, 220, x5)
+
+inst_68:
+// rs2_val == 32768, rs1_val == 65536
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x8000
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x10000, 0x8000, x2, 224, x5)
+
+inst_69:
+// rs2_val == 16384, rs1_val == 1048576
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x4000
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x100000, 0x4000, x2, 228, x5)
+
+inst_70:
+// rs2_val == 8192, rs1_val == 33554432
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x2000
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x2000000, 0x2000, x2, 232, x5)
+
+inst_71:
+// rs2_val == 2048, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x800
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x2000000, 0x800, x2, 236, x5)
+
+inst_72:
+// rs2_val == 1024, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x400
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x1000001, 0x400, x2, 240, x5)
+
+inst_73:
+// rs2_val == 512, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x200
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x10001, 0x200, x2, 244, x5)
+
+inst_74:
+// rs2_val == 256, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:0x100
+TEST_RR_OP(rem, x12, x10, x11, -0x7, -0x7, 0x100, x2, 248, x5)
+
+inst_75:
+// rs2_val == 128, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x80
+TEST_RR_OP(rem, x12, x10, x11, 0x8, 0x8, 0x80, x2, 252, x5)
+
+inst_76:
+// rs2_val == 64, rs1_val == 8192
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x40
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x2000, 0x40, x2, 256, x5)
+
+inst_77:
+// rs2_val == 32, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x20
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x66666665, 0x20, x2, 260, x5)
+
+inst_78:
+// rs2_val == 16, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x10
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x100000, 0x10, x2, 264, x5)
+
+inst_79:
+// rs2_val == 8, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x8
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x20, 0x8, x2, 268, x5)
+
+inst_80:
+// rs2_val == 4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x4;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x4, 0x4, x2, 272, x5)
+
+inst_81:
+// rs2_val == 1, rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x1
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x80000000, 0x1, x2, 276, x5)
+
+inst_82:
+// rs1_val == 1073741824, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x101
+TEST_RR_OP(rem, x12, x10, x11, 0xc1, 0x40000000, -0x101, x2, 280, x5)
+
+inst_83:
+// rs1_val == 536870912, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x3fffffff
+TEST_RR_OP(rem, x12, x10, x11, 0x20000000, 0x20000000, 0x3fffffff, x2, 284, x5)
+
+inst_84:
+// rs1_val == 268435456, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x10000000, 0x4, x2, 288, x5)
+
+inst_85:
+// rs1_val == 134217728, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x2000000
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x8000000, 0x2000000, x2, 292, x5)
+
+inst_86:
+// rs1_val == 16777216, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x3fffffff
+TEST_RR_OP(rem, x12, x10, x11, 0x1000000, 0x1000000, 0x3fffffff, x2, 296, x5)
+
+inst_87:
+// rs1_val == 8388608, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x800000, 0x800000, 0x66666667, x2, 300, x5)
+
+inst_88:
+// rs1_val == 4194304, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x200
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x400000, 0x200, x2, 304, x5)
+
+inst_89:
+// rs1_val == 2097152, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x400001
+TEST_RR_OP(rem, x12, x10, x11, 0x200000, 0x200000, -0x400001, x2, 308, x5)
+
+inst_90:
+// rs1_val == 524288, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x80000, 0x80000, 0x33333333, x2, 312, x5)
+
+inst_91:
+// rs1_val == 262144, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x8
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x40000, 0x8, x2, 316, x5)
+
+inst_92:
+// rs1_val == 16384, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x4000, 0x3, x2, 320, x5)
+
+inst_93:
+// rs1_val == 4096, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:-0x11
+TEST_RR_OP(rem, x12, x10, x11, 0x10, 0x1000, -0x11, x2, 324, x5)
+
+inst_94:
+// rs1_val == 512, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x2000001
+TEST_RR_OP(rem, x12, x10, x11, 0x200, 0x200, -0x2000001, x2, 328, x5)
+
+inst_95:
+// rs1_val == 128, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:-0x1
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x80, -0x1, x2, 332, x5)
+
+inst_96:
+// rs1_val == 64, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x40, -0x3, x2, 336, x5)
+
+inst_97:
+// rs1_val == 1, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x1, -0x3, x2, 340, x5)
+
+inst_98:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb505, 0xb505, x2, 344, x5)
+
+inst_99:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0xb505, -0xb503, x2, 348, x5)
+
+inst_100:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x66666667, x2, 352, x5)
+
+inst_101:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x33333334, x2, 356, x5)
+
+inst_102:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0xb505, 0x6, x2, 360, x5)
+
+inst_103:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, -0x55555555, x2, 364, x5)
+
+inst_104:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x55555556, x2, 368, x5)
+
+inst_105:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb505, 0x4, x2, 372, x5)
+
+inst_106:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0xb505, 0xb503, x2, 376, x5)
+
+inst_107:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x0, x2, 380, x5)
+
+inst_108:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x66666665, x2, 384, x5)
+
+inst_109:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x33333332, x2, 388, x5)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x55555554, x2, 392, x5)
+
+inst_111:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb505, 0x2, x2, 396, x5)
+
+inst_112:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb505, 0xb504, x2, 400, x5)
+
+inst_113:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb505, -0xb504, x2, 404, x5)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x66666666, x2, 408, x5)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x33333333, x2, 412, x5)
+
+inst_116:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb505, 0x5, x2, 416, x5)
+
+inst_117:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, -0x55555556, x2, 420, x5)
+
+inst_118:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb505, 0xb505, 0x55555555, x2, 424, x5)
+
+inst_119:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb505, 0x3, x2, 428, x5)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0xb505, x2, 432, x5)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb503, -0xb503, x2, 436, x5)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x66666667, x2, 440, x5)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x33333334, x2, 444, x5)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0xb503, 0x6, x2, 448, x5)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, -0x55555555, x2, 452, x5)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x55555556, x2, 456, x5)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, -0x3, -0xb503, 0x4, x2, 460, x5)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb503, 0xb503, x2, 464, x5)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x0, x2, 468, x5)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x66666665, x2, 472, x5)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x33333332, x2, 476, x5)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x55555554, x2, 480, x5)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0xb503, 0x2, x2, 484, x5)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0xb504, x2, 488, x5)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, -0xb504, x2, 492, x5)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x66666666, x2, 496, x5)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x33333333, x2, 500, x5)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, -0x4, -0xb503, 0x5, x2, 504, x5)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, -0x55555556, x2, 508, x5)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0xb503, -0xb503, 0x55555555, x2, 512, x5)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0xb503, 0x3, x2, 516, x5)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x8257, 0x66666667, 0xb505, x2, 520, x5)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39f1, 0x66666667, -0xb503, x2, 524, x5)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x2, 528, x5)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x66666667, 0x33333334, x2, 532, x5)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666667, 0x6, x2, 536, x5)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111112, 0x66666667, -0x55555555, x2, 540, x5)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x11111111, 0x66666667, 0x55555556, x2, 544, x5)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x66666667, 0x4, x2, 548, x5)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39f1, 0x66666667, 0xb503, x2, 552, x5)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x2, 556, x5)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x66666667, 0x66666665, x2, 560, x5)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x66666667, 0x33333332, x2, 564, x5)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x11111113, 0x66666667, 0x55555554, x2, 568, x5)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666667, 0x2, x2, 572, x5)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e23, 0x66666667, 0xb504, x2, 576, x5)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e23, 0x66666667, -0xb504, x2, 580, x5)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x2, 584, x5)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666667, 0x33333333, x2, 588, x5)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x66666667, 0x5, x2, 592, x5)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x11111111, 0x66666667, -0x55555556, x2, 596, x5)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111112, 0x66666667, 0x55555555, x2, 600, x5)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666667, 0x3, x2, 604, x5)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x412c, 0x33333334, 0xb505, x2, 608, x5)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf9, 0x33333334, -0xb503, x2, 612, x5)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x66666667, x2, 616, x5)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x2, 620, x5)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x33333334, 0x6, x2, 624, x5)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, -0x55555555, x2, 628, x5)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x55555556, x2, 632, x5)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333334, 0x4, x2, 636, x5)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf9, 0x33333334, 0xb503, x2, 640, x5)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x2, 644, x5)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x66666665, x2, 648, x5)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x33333334, 0x33333332, x2, 652, x5)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x55555554, x2, 656, x5)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333334, 0x2, x2, 660, x5)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8994, 0x33333334, 0xb504, x2, 664, x5)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8994, 0x33333334, -0xb504, x2, 668, x5)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x66666666, x2, 672, x5)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x33333334, 0x33333333, x2, 676, x5)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333334, 0x5, x2, 680, x5)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, -0x55555556, x2, 684, x5)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333334, 0x33333334, 0x55555555, x2, 688, x5)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x33333334, 0x3, x2, 692, x5)
+
+inst_186:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0xb505, x2, 696, x5)
+
+inst_187:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, -0xb503, x2, 700, x5)
+
+inst_188:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x66666667, x2, 704, x5)
+
+inst_189:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x33333334, x2, 708, x5)
+
+inst_190:
+// rs1_val==6 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x6, 0x6, x2, 712, x5)
+
+inst_191:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, -0x55555555, x2, 716, x5)
+
+inst_192:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x55555556, x2, 720, x5)
+
+inst_193:
+// rs1_val==6 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x6, 0x4, x2, 724, x5)
+
+inst_194:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0xb503, x2, 728, x5)
+
+inst_195:
+// rs1_val==6 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x0, x2, 732, x5)
+
+inst_196:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x66666665, x2, 736, x5)
+
+inst_197:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x33333332, x2, 740, x5)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x55555554, x2, 744, x5)
+
+inst_199:
+// rs1_val==6 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x6, 0x2, x2, 748, x5)
+
+inst_200:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0xb504, x2, 752, x5)
+
+inst_201:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, -0xb504, x2, 756, x5)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x66666666, x2, 760, x5)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x33333333, x2, 764, x5)
+
+inst_204:
+// rs1_val==6 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x6, 0x5, x2, 768, x5)
+
+inst_205:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, -0x55555556, x2, 772, x5)
+
+inst_206:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x6, 0x6, 0x55555555, x2, 776, x5)
+
+inst_207:
+// rs1_val==6 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x6, 0x3, x2, 780, x5)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, -0xa8f4, -0x55555555, 0xb505, x2, 784, x5)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x3048, -0x55555555, -0xb503, x2, 788, x5)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, 0x66666667, x2, 792, x5)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0x22222221, -0x55555555, 0x33333334, x2, 796, x5)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, 0x6, x2, 800, x5)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555555, -0x55555555, x2, 804, x5)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, 0x55555556, x2, 808, x5)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, 0x4, x2, 812, x5)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x3048, -0x55555555, 0xb503, x2, 816, x5)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, 0x0, x2, 820, x5)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, 0x66666665, x2, 824, x5)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, -0x22222223, -0x55555555, 0x33333332, x2, 828, x5)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, 0x55555554, x2, 832, x5)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, 0x2, x2, 836, x5)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x6c9d, -0x55555555, 0xb504, x2, 840, x5)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x6c9d, -0x55555555, -0xb504, x2, 844, x5)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, 0x66666666, x2, 848, x5)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, -0x22222222, -0x55555555, 0x33333333, x2, 852, x5)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555555, 0x5, x2, 856, x5)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0x55555555, -0x55555555, -0x55555556, x2, 860, x5)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555555, 0x55555555, x2, 864, x5)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555555, 0x3, x2, 868, x5)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0xa8f5, 0x55555556, 0xb505, x2, 872, x5)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3049, 0x55555556, -0xb503, x2, 876, x5)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x55555556, 0x55555556, 0x66666667, x2, 880, x5)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x22222222, 0x55555556, 0x33333334, x2, 884, x5)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x55555556, 0x6, x2, 888, x5)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555556, -0x55555555, x2, 892, x5)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x2, 896, x5)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x55555556, 0x4, x2, 900, x5)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3049, 0x55555556, 0xb503, x2, 904, x5)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x2, 908, x5)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x55555556, 0x55555556, 0x66666665, x2, 912, x5)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x22222224, 0x55555556, 0x33333332, x2, 916, x5)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x55555556, 0x55555554, x2, 920, x5)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555556, 0x2, x2, 924, x5)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9e, 0x55555556, 0xb504, x2, 928, x5)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9e, 0x55555556, -0xb504, x2, 932, x5)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x55555556, 0x55555556, 0x66666666, x2, 936, x5)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x22222223, 0x55555556, 0x33333333, x2, 940, x5)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555556, 0x5, x2, 944, x5)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555556, -0x55555556, x2, 948, x5)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555556, 0x55555555, x2, 952, x5)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x55555556, 0x3, x2, 956, x5)
+
+inst_252:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0xb505, x2, 960, x5)
+
+inst_253:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, -0xb503, x2, 964, x5)
+
+inst_254:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x66666667, x2, 968, x5)
+
+inst_255:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x33333334, x2, 972, x5)
+
+inst_256:
+// rs1_val==4 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x6, x2, 976, x5)
+
+inst_257:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, -0x55555555, x2, 980, x5)
+
+inst_258:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x55555556, x2, 984, x5)
+
+inst_259:
+// rs1_val==4 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x4, 0x4, x2, 988, x5)
+
+inst_260:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0xb503, x2, 992, x5)
+
+inst_261:
+// rs1_val==4 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x0, x2, 996, x5)
+
+inst_262:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x66666665, x2, 1000, x5)
+
+inst_263:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x33333332, x2, 1004, x5)
+
+inst_264:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x55555554, x2, 1008, x5)
+
+inst_265:
+// rs1_val==4 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x4, 0x2, x2, 1012, x5)
+
+inst_266:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0xb504, x2, 1016, x5)
+
+inst_267:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, -0xb504, x2, 1020, x5)
+
+inst_268:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x66666666, x2, 1024, x5)
+
+inst_269:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x33333333, x2, 1028, x5)
+
+inst_270:
+// rs1_val==4 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x5, x2, 1032, x5)
+
+inst_271:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, -0x55555556, x2, 1036, x5)
+
+inst_272:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x4, 0x55555555, x2, 1040, x5)
+
+inst_273:
+// rs1_val==4 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x4, 0x3, x2, 1044, x5)
+
+inst_274:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0xb505, x2, 1048, x5)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb503, -0xb503, x2, 1052, x5)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x66666667, x2, 1056, x5)
+
+inst_277:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x33333334, x2, 1060, x5)
+
+inst_278:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb503, 0x6, x2, 1064, x5)
+
+inst_279:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, -0x55555555, x2, 1068, x5)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x55555556, x2, 1072, x5)
+
+inst_281:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0xb503, 0x4, x2, 1076, x5)
+
+inst_282:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb503, 0xb503, x2, 1080, x5)
+
+inst_283:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x0, x2, 1084, x5)
+
+inst_284:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x66666665, x2, 1088, x5)
+
+inst_285:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x33333332, x2, 1092, x5)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x55555554, x2, 1096, x5)
+
+inst_287:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb503, 0x2, x2, 1100, x5)
+
+inst_288:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0xb504, x2, 1104, x5)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, -0xb504, x2, 1108, x5)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x66666666, x2, 1112, x5)
+
+inst_291:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x33333333, x2, 1116, x5)
+
+inst_292:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0xb503, 0x5, x2, 1120, x5)
+
+inst_293:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, -0x55555556, x2, 1124, x5)
+
+inst_294:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb503, 0xb503, 0x55555555, x2, 1128, x5)
+
+inst_295:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb503, 0x3, x2, 1132, x5)
+
+inst_296:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0xb505, x2, 1136, x5)
+
+inst_297:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0xb503, x2, 1140, x5)
+
+inst_298:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x66666667, x2, 1144, x5)
+
+inst_299:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x33333334, x2, 1148, x5)
+
+inst_300:
+// rs1_val==0 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x6, x2, 1152, x5)
+
+inst_301:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0x55555555, x2, 1156, x5)
+
+inst_302:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x55555556, x2, 1160, x5)
+
+inst_303:
+// rs1_val==0 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x4, x2, 1164, x5)
+
+inst_304:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0xb503, x2, 1168, x5)
+
+inst_305:
+// rs1_val==0 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x0, x2, 1172, x5)
+
+inst_306:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x66666665, x2, 1176, x5)
+
+inst_307:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x33333332, x2, 1180, x5)
+
+inst_308:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x55555554, x2, 1184, x5)
+
+inst_309:
+// rs1_val==0 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x2, x2, 1188, x5)
+
+inst_310:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0xb504, x2, 1192, x5)
+
+inst_311:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0xb504, x2, 1196, x5)
+
+inst_312:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x66666666, x2, 1200, x5)
+
+inst_313:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x33333333, x2, 1204, x5)
+
+inst_314:
+// rs1_val==0 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x5, x2, 1208, x5)
+
+inst_315:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, -0x55555556, x2, 1212, x5)
+
+inst_316:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x55555555, x2, 1216, x5)
+
+inst_317:
+// rs1_val==0 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x0, 0x3, x2, 1220, x5)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x8255, 0x66666665, 0xb505, x2, 1224, x5)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39ef, 0x66666665, -0xb503, x2, 1228, x5)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x66666665, 0x66666665, 0x66666667, x2, 1232, x5)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x33333331, 0x66666665, 0x33333334, x2, 1236, x5)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x66666665, 0x6, x2, 1240, x5)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111110, 0x66666665, -0x55555555, x2, 1244, x5)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x1111110f, 0x66666665, 0x55555556, x2, 1248, x5)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666665, 0x4, x2, 1252, x5)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39ef, 0x66666665, 0xb503, x2, 1256, x5)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x2, 1260, x5)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x66666665, x2, 1264, x5)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x2, 1268, x5)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x55555554, x2, 1272, x5)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x33333333, 0x2, x2, 1276, x5)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8993, 0x33333333, 0xb504, x2, 1280, x5)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8993, 0x33333333, -0xb504, x2, 1284, x5)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x66666666, x2, 1288, x5)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x2, 1292, x5)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x33333333, 0x5, x2, 1296, x5)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, -0x55555556, x2, 1300, x5)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x55555555, x2, 1304, x5)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333333, 0x3, x2, 1308, x5)
+
+inst_340:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0xb505, x2, 1312, x5)
+
+inst_341:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, -0xb503, x2, 1316, x5)
+
+inst_342:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x66666667, x2, 1320, x5)
+
+inst_343:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x33333334, x2, 1324, x5)
+
+inst_344:
+// rs1_val==5 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x6, x2, 1328, x5)
+
+inst_345:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, -0x55555555, x2, 1332, x5)
+
+inst_346:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x55555556, x2, 1336, x5)
+
+inst_347:
+// rs1_val==5 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x5, 0x4, x2, 1340, x5)
+
+inst_348:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0xb503, x2, 1344, x5)
+
+inst_349:
+// rs1_val==5 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x0, x2, 1348, x5)
+
+inst_350:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x66666665, x2, 1352, x5)
+
+inst_351:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x33333332, x2, 1356, x5)
+
+inst_352:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x55555554, x2, 1360, x5)
+
+inst_353:
+// rs1_val==5 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x5, 0x2, x2, 1364, x5)
+
+inst_354:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0xb504, x2, 1368, x5)
+
+inst_355:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, -0xb504, x2, 1372, x5)
+
+inst_356:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x66666666, x2, 1376, x5)
+
+inst_357:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x33333333, x2, 1380, x5)
+
+inst_358:
+// rs1_val==5 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x5, 0x5, x2, 1384, x5)
+
+inst_359:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, -0x55555556, x2, 1388, x5)
+
+inst_360:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x5, 0x5, 0x55555555, x2, 1392, x5)
+
+inst_361:
+// rs1_val==5 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x5, 0x3, x2, 1396, x5)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, -0xa8f5, -0x55555556, 0xb505, x2, 1400, x5)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x3049, -0x55555556, -0xb503, x2, 1404, x5)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, -0x55555556, -0x55555556, 0x66666667, x2, 1408, x5)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0x22222222, -0x55555556, 0x33333334, x2, 1412, x5)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0x55555556, 0x6, x2, 1416, x5)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555556, -0x55555555, x2, 1420, x5)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555556, 0x55555556, x2, 1424, x5)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0x55555556, 0x4, x2, 1428, x5)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x3049, -0x55555556, 0xb503, x2, 1432, x5)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, -0x55555556, -0x55555556, 0x0, x2, 1436, x5)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, -0x55555556, -0x55555556, 0x66666665, x2, 1440, x5)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, -0x22222224, -0x55555556, 0x33333332, x2, 1444, x5)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0x55555556, 0x55555554, x2, 1448, x5)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555556, 0x2, x2, 1452, x5)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x6c9e, -0x55555556, 0xb504, x2, 1456, x5)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, -0x6c9e, -0x55555556, -0xb504, x2, 1460, x5)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, -0x55555556, -0x55555556, 0x66666666, x2, 1464, x5)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, -0x22222223, -0x55555556, 0x33333333, x2, 1468, x5)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555556, 0x5, x2, 1472, x5)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0x55555556, -0x55555556, x2, 1476, x5)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0x55555556, 0x55555555, x2, 1480, x5)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0x55555556, 0x3, x2, 1484, x5)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0xa8f4, 0x55555555, 0xb505, x2, 1488, x5)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3048, 0x55555555, -0xb503, x2, 1492, x5)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, 0x66666667, x2, 1496, x5)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x22222221, 0x55555555, 0x33333334, x2, 1500, x5)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555555, 0x6, x2, 1504, x5)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555555, -0x55555555, x2, 1508, x5)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, 0x55555556, x2, 1512, x5)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555555, 0x4, x2, 1516, x5)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3048, 0x55555555, 0xb503, x2, 1520, x5)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x2, 1524, x5)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, 0x66666665, x2, 1528, x5)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x22222223, 0x55555555, 0x33333332, x2, 1532, x5)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x2, 1536, x5)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555555, 0x2, x2, 1540, x5)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9d, 0x55555555, 0xb504, x2, 1544, x5)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9d, 0x55555555, -0xb504, x2, 1548, x5)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, 0x66666666, x2, 1552, x5)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x22222222, 0x55555555, 0x33333333, x2, 1556, x5)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555555, 0x5, x2, 1560, x5)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x55555555, 0x55555555, -0x55555556, x2, 1564, x5)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x2, 1568, x5)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x55555555, 0x3, x2, 1572, x5)
+
+inst_406:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0xb505, x2, 1576, x5)
+
+inst_407:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, -0xb503, x2, 1580, x5)
+
+inst_408:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x66666667, x2, 1584, x5)
+
+inst_409:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x33333334, x2, 1588, x5)
+
+inst_410:
+// rs1_val==3 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x6, x2, 1592, x5)
+
+inst_411:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, -0x55555555, x2, 1596, x5)
+
+inst_412:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x55555556, x2, 1600, x5)
+
+inst_413:
+// rs1_val==3 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x4, x2, 1604, x5)
+
+inst_414:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0xb503, x2, 1608, x5)
+
+inst_415:
+// rs1_val==3 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x0, x2, 1612, x5)
+
+inst_416:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x66666665, x2, 1616, x5)
+
+inst_417:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x33333332, x2, 1620, x5)
+
+inst_418:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x55555554, x2, 1624, x5)
+
+inst_419:
+// rs1_val==3 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x3, 0x2, x2, 1628, x5)
+
+inst_420:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0xb504, x2, 1632, x5)
+
+inst_421:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, -0xb504, x2, 1636, x5)
+
+inst_422:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x66666666, x2, 1640, x5)
+
+inst_423:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x33333333, x2, 1644, x5)
+
+inst_424:
+// rs1_val==3 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x5, x2, 1648, x5)
+
+inst_425:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, -0x55555556, x2, 1652, x5)
+
+inst_426:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x3, 0x55555555, x2, 1656, x5)
+
+inst_427:
+// rs1_val==3 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x3, 0x3, x2, 1660, x5)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x2, 1664, x5)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x2, 1668, x5)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666665, 0x33333332, x2, 1672, x5)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x11111111, 0x66666665, 0x55555554, x2, 1676, x5)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666665, 0x2, x2, 1680, x5)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e21, 0x66666665, 0xb504, x2, 1684, x5)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e21, 0x66666665, -0xb504, x2, 1688, x5)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x66666665, 0x66666665, 0x66666666, x2, 1692, x5)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x66666665, 0x33333333, x2, 1696, x5)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x66666665, 0x5, x2, 1700, x5)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x1111110f, 0x66666665, -0x55555556, x2, 1704, x5)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111110, 0x66666665, 0x55555555, x2, 1708, x5)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x66666665, 0x3, x2, 1712, x5)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x412a, 0x33333332, 0xb505, x2, 1716, x5)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf7, 0x33333332, -0xb503, x2, 1720, x5)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x66666667, x2, 1724, x5)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x33333334, x2, 1728, x5)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x33333332, 0x6, x2, 1732, x5)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, -0x55555555, x2, 1736, x5)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x55555556, x2, 1740, x5)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x33333332, 0x4, x2, 1744, x5)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf7, 0x33333332, 0xb503, x2, 1748, x5)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x2, 1752, x5)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x66666665, x2, 1756, x5)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x2, 1760, x5)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x55555554, x2, 1764, x5)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x33333332, 0x2, x2, 1768, x5)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8992, 0x33333332, 0xb504, x2, 1772, x5)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x8992, 0x33333332, -0xb504, x2, 1776, x5)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x66666666, x2, 1780, x5)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x33333333, x2, 1784, x5)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x33333332, 0x5, x2, 1788, x5)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, -0x55555556, x2, 1792, x5)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x33333332, 0x55555555, x2, 1796, x5)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x33333332, 0x3, x2, 1800, x5)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0xa8f3, 0x55555554, 0xb505, x2, 1804, x5)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3047, 0x55555554, -0xb503, x2, 1808, x5)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x66666667, x2, 1812, x5)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x22222220, 0x55555554, 0x33333334, x2, 1816, x5)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555554, 0x6, x2, 1820, x5)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, -0x55555555, x2, 1824, x5)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x55555556, x2, 1828, x5)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555554, 0x4, x2, 1832, x5)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x3047, 0x55555554, 0xb503, x2, 1836, x5)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x2, 1840, x5)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x66666665, x2, 1844, x5)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x22222222, 0x55555554, 0x33333332, x2, 1848, x5)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x2, 1852, x5)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555554, 0x2, x2, 1856, x5)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9c, 0x55555554, 0xb504, x2, 1860, x5)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x6c9c, 0x55555554, -0xb504, x2, 1864, x5)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x66666666, x2, 1868, x5)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x22222221, 0x55555554, 0x33333333, x2, 1872, x5)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x4, 0x55555554, 0x5, x2, 1876, x5)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, -0x55555556, x2, 1880, x5)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x55555554, 0x55555554, 0x55555555, x2, 1884, x5)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x55555554, 0x3, x2, 1888, x5)
+
+inst_485:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0xb505, x2, 1892, x5)
+
+inst_486:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, -0xb503, x2, 1896, x5)
+
+inst_487:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x66666667, x2, 1900, x5)
+
+inst_488:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x33333334, x2, 1904, x5)
+
+inst_489:
+// rs1_val==2 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x6, x2, 1908, x5)
+
+inst_490:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, -0x55555555, x2, 1912, x5)
+
+inst_491:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x55555556, x2, 1916, x5)
+
+inst_492:
+// rs1_val==2 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x4, x2, 1920, x5)
+
+inst_493:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0xb503, x2, 1924, x5)
+
+inst_494:
+// rs1_val==2 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x0, x2, 1928, x5)
+
+inst_495:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x66666665, x2, 1932, x5)
+
+inst_496:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x33333332, x2, 1936, x5)
+
+inst_497:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x55555554, x2, 1940, x5)
+
+inst_498:
+// rs1_val==2 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x2, 0x2, x2, 1944, x5)
+
+inst_499:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0xb504, x2, 1948, x5)
+
+inst_500:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, -0xb504, x2, 1952, x5)
+
+inst_501:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x66666666, x2, 1956, x5)
+
+inst_502:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x33333333, x2, 1960, x5)
+
+inst_503:
+// rs1_val==2 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x5, x2, 1964, x5)
+
+inst_504:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, -0x55555556, x2, 1968, x5)
+
+inst_505:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x55555555, x2, 1972, x5)
+
+inst_506:
+// rs1_val==2 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x2, 0x3, x2, 1976, x5)
+
+inst_507:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0xb505, x2, 1980, x5)
+
+inst_508:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb504, -0xb503, x2, 1984, x5)
+
+inst_509:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x66666667, x2, 1988, x5)
+
+inst_510:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x33333334, x2, 1992, x5)
+
+inst_511:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0xb504, 0x6, x2, 1996, x5)
+
+inst_512:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, -0x55555555, x2, 2000, x5)
+
+inst_513:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x55555556, x2, 2004, x5)
+
+inst_514:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb504, 0x4, x2, 2008, x5)
+
+inst_515:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0xb504, 0xb503, x2, 2012, x5)
+
+inst_516:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x0, x2, 2016, x5)
+
+inst_517:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x66666665, x2, 2020, x5)
+
+inst_518:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x33333332, x2, 2024, x5)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x55555554, x2, 2028, x5)
+
+inst_520:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb504, 0x2, x2, 2032, x5)
+
+inst_521:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb504, 0xb504, x2, 2036, x5)
+
+inst_522:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb504, -0xb504, x2, 2040, x5)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x66666666, x2, 2044, x5)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_524:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x33333333, x2, 0, x5)
+
+inst_525:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0xb504, 0x5, x2, 4, x5)
+
+inst_526:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, -0x55555556, x2, 8, x5)
+
+inst_527:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0xb504, 0xb504, 0x55555555, x2, 12, x5)
+
+inst_528:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0xb504, 0x3, x2, 16, x5)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0xb505, x2, 20, x5)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0xb504, -0xb503, x2, 24, x5)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x66666667, x2, 28, x5)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x33333334, x2, 32, x5)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0xb504, 0x6, x2, 36, x5)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, -0x55555555, x2, 40, x5)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x55555556, x2, 44, x5)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb504, 0x4, x2, 48, x5)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, -0x1, -0xb504, 0xb503, x2, 52, x5)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x0, x2, 56, x5)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x66666665, x2, 60, x5)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x33333332, x2, 64, x5)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x55555554, x2, 68, x5)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb504, 0x2, x2, 72, x5)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb504, 0xb504, x2, 76, x5)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb504, -0xb504, x2, 80, x5)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x66666666, x2, 84, x5)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x33333333, x2, 88, x5)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x0, -0xb504, 0x5, x2, 92, x5)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, -0x55555556, x2, 96, x5)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, -0xb504, -0xb504, 0x55555555, x2, 100, x5)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, -0x2, -0xb504, 0x3, x2, 104, x5)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x8256, 0x66666666, 0xb505, x2, 108, x5)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39f0, 0x66666666, -0xb503, x2, 112, x5)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x66666666, 0x66666666, 0x66666667, x2, 116, x5)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x33333332, 0x66666666, 0x33333334, x2, 120, x5)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666666, 0x6, x2, 124, x5)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111111, 0x66666666, -0x55555555, x2, 128, x5)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x11111110, 0x66666666, 0x55555556, x2, 132, x5)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x66666666, 0x4, x2, 136, x5)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x39f0, 0x66666666, 0xb503, x2, 140, x5)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(rem, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x2, 144, x5)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(rem, x12, x10, x11, 0x1, 0x66666666, 0x66666665, x2, 148, x5)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(rem, x12, x10, x11, 0x2, 0x66666666, 0x33333332, x2, 152, x5)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(rem, x12, x10, x11, 0x11111112, 0x66666666, 0x55555554, x2, 156, x5)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666666, 0x2, x2, 160, x5)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e22, 0x66666666, 0xb504, x2, 164, x5)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(rem, x12, x10, x11, 0x5e22, 0x66666666, -0xb504, x2, 168, x5)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x2, 172, x5)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666666, 0x33333333, x2, 176, x5)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x66666666, 0x5, x2, 180, x5)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x11111110, 0x66666666, -0x55555556, x2, 184, x5)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x11111111, 0x66666666, 0x55555555, x2, 188, x5)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(rem, x12, x10, x11, 0x0, 0x66666666, 0x3, x2, 192, x5)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(rem, x12, x10, x11, 0x412b, 0x33333333, 0xb505, x2, 196, x5)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf8, 0x33333333, -0xb503, x2, 200, x5)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x66666667, x2, 204, x5)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x33333334, x2, 208, x5)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x33333333, 0x6, x2, 212, x5)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, -0x55555555, x2, 216, x5)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(rem, x12, x10, x11, 0x33333333, 0x33333333, 0x55555556, x2, 220, x5)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(rem, x12, x10, x11, 0x3, 0x33333333, 0x4, x2, 224, x5)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(rem, x12, x10, x11, 0x1cf8, 0x33333333, 0xb503, x2, 228, x5)
+
+inst_582:
+// rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0, rs1_val == -67108865
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:-0x40000001
+TEST_RR_OP(rem, x12, x10, x11, -0x4000001, -0x4000001, -0x40000001, x2, 232, x5)
+
+inst_583:
+// rs2_val == -536870913, rs1_val == -131073
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:-0x20000001
+TEST_RR_OP(rem, x12, x10, x11, -0x20001, -0x20001, -0x20000001, x2, 236, x5)
+
+inst_584:
+// rs2_val == -33554433, rs1_val == 67108864
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:-0x2000001
+TEST_RR_OP(rem, x12, x10, x11, 0x1ffffff, 0x4000000, -0x2000001, x2, 240, x5)
+
+inst_585:
+// rs2_val == -524289, 
+// opcode: rem ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:-0x80001
+TEST_RR_OP(rem, x12, x10, x11, -0x7, -0x7, -0x80001, x2, 244, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 62*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/remu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/remu-01.S
new file mode 100644
index 000000000..f14717295
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/M/src/remu-01.S
@@ -0,0 +1,3715 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Wed Aug  4 07:22:49 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32em.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the remu instruction of the RISC-V M extension for the remu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32EM")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",remu)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x3, rs2==x10, rd==x10, rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0, rs1_val > 0 and rs2_val > 0, rs1_val == 32, rs2_val == 4294966783
+// opcode: remu ; op1:x3; op2:x10; dest:x10; op1val:0x20;  op2val:0xfffffdff
+TEST_RR_OP(remu, x10, x3, x10, 0x20, 0x20, 0xfffffdff, x2, 0, x6)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x1, rs2==x13, rd==x1, rs2_val == 2147483647, 
+// opcode: remu ; op1:x1; op2:x13; dest:x1; op1val:0x33333332;  op2val:0x7fffffff
+TEST_RR_OP(remu, x1, x1, x13, 0x33333332, 0x33333332, 0x7fffffff, x2, 4, x6)
+
+inst_2:
+// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4, rs2_val == 3221225471, rs1_val == 32768
+// opcode: remu ; op1:x4; op2:x4; dest:x4; op1val:0x8000;  op2val:0x8000
+TEST_RR_OP(remu, x4, x4, x4, 0x0, 0x8000, 0x8000, x2, 8, x6)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x12, rs2==x12, rd==x11, rs2_val == 3758096383, 
+// opcode: remu ; op1:x12; op2:x12; dest:x11; op1val:0xc;  op2val:0xc
+TEST_RR_OP(remu, x11, x12, x12, 0x0, 0xc, 0xc, x2, 12, x6)
+
+inst_4:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x7, rs2==x1, rd==x8, rs2_val == 4026531839, rs1_val == 4294705151
+// opcode: remu ; op1:x7; op2:x1; dest:x8; op1val:0xfffbffff;  op2val:0xefffffff
+TEST_RR_OP(remu, x8, x7, x1, 0xffc0000, 0xfffbffff, 0xefffffff, x2, 16, x6)
+
+inst_5:
+// rs1==x15, rs2==x7, rd==x5, rs2_val == 4160749567, rs1_val == 131072
+// opcode: remu ; op1:x15; op2:x7; dest:x5; op1val:0x20000;  op2val:0xf7ffffff
+TEST_RR_OP(remu, x5, x15, x7, 0x20000, 0x20000, 0xf7ffffff, x2, 20, x6)
+
+inst_6:
+// rs1==x9, rs2==x5, rd==x0, rs2_val == 4227858431, rs1_val == 1431655765
+// opcode: remu ; op1:x9; op2:x5; dest:x0; op1val:0x55555555;  op2val:0xfbffffff
+TEST_RR_OP(remu, x0, x9, x5, 0, 0x55555555, 0xfbffffff, x2, 24, x4)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_7:
+// rs1==x0, rs2==x3, rd==x7, rs2_val == 4261412863, rs1_val == 3758096383
+// opcode: remu ; op1:x0; op2:x3; dest:x7; op1val:0x0;  op2val:0xfdffffff
+TEST_RR_OP(remu, x7, x0, x3, 0x0, 0x0, 0xfdffffff, x1, 0, x4)
+
+inst_8:
+// rs1==x2, rs2==x15, rd==x3, rs2_val == 4278190079, 
+// opcode: remu ; op1:x2; op2:x15; dest:x3; op1val:0x3;  op2val:0xfeffffff
+TEST_RR_OP(remu, x3, x2, x15, 0x3, 0x3, 0xfeffffff, x1, 4, x4)
+
+inst_9:
+// rs1==x5, rs2==x9, rd==x2, rs2_val == 4286578687, rs1_val == 4294967263
+// opcode: remu ; op1:x5; op2:x9; dest:x2; op1val:0xffffffdf;  op2val:0xff7fffff
+TEST_RR_OP(remu, x2, x5, x9, 0x7fffe0, 0xffffffdf, 0xff7fffff, x1, 8, x4)
+
+inst_10:
+// rs1==x13, rs2==x6, rd==x9, rs2_val == 4290772991, rs1_val == 16
+// opcode: remu ; op1:x13; op2:x6; dest:x9; op1val:0x10;  op2val:0xffbfffff
+TEST_RR_OP(remu, x9, x13, x6, 0x10, 0x10, 0xffbfffff, x1, 12, x4)
+
+inst_11:
+// rs1==x6, rs2==x0, rd==x12, rs2_val == 4292870143, rs1_val == 4294967291
+// opcode: remu ; op1:x6; op2:x0; dest:x12; op1val:0xfffffffb;  op2val:0x0
+TEST_RR_OP(remu, x12, x6, x0, 0xfffffffb, 0xfffffffb, 0x0, x1, 16, x4)
+
+inst_12:
+// rs1==x10, rs2==x8, rd==x14, rs2_val == 4293918719, rs1_val == 4286578687
+// opcode: remu ; op1:x10; op2:x8; dest:x14; op1val:0xff7fffff;  op2val:0xffefffff
+TEST_RR_OP(remu, x14, x10, x8, 0xff7fffff, 0xff7fffff, 0xffefffff, x1, 20, x4)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_13:
+// rs1==x14, rs2==x2, rd==x15, rs2_val == 4294443007, 
+// opcode: remu ; op1:x14; op2:x2; dest:x15; op1val:0xb503;  op2val:0xfff7ffff
+TEST_RR_OP(remu, x15, x14, x2, 0xb503, 0xb503, 0xfff7ffff, x3, 0, x5)
+
+inst_14:
+// rs1==x8, rs2==x14, rd==x13, rs2_val == 4294705151, rs1_val == 4227858431
+// opcode: remu ; op1:x8; op2:x14; dest:x13; op1val:0xfbffffff;  op2val:0xfffbffff
+TEST_RR_OP(remu, x13, x8, x14, 0xfbffffff, 0xfbffffff, 0xfffbffff, x3, 4, x5)
+
+inst_15:
+// rs1==x11, rs2_val == 4294836223, rs1_val == 4292870143
+// opcode: remu ; op1:x11; op2:x4; dest:x2; op1val:0xffdfffff;  op2val:0xfffdffff
+TEST_RR_OP(remu, x2, x11, x4, 0xffdfffff, 0xffdfffff, 0xfffdffff, x3, 8, x5)
+
+inst_16:
+// rs2==x11, rs2_val == 4294901759, rs1_val == 4294901759, rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0
+// opcode: remu ; op1:x1; op2:x11; dest:x9; op1val:0xfffeffff;  op2val:0xfffeffff
+TEST_RR_OP(remu, x9, x1, x11, 0x0, 0xfffeffff, 0xfffeffff, x3, 12, x5)
+
+inst_17:
+// rd==x6, rs2_val == 4294934527, rs1_val == 4294950911
+// opcode: remu ; op1:x7; op2:x2; dest:x6; op1val:0xffffbfff;  op2val:0xffff7fff
+TEST_RR_OP(remu, x6, x7, x2, 0x4000, 0xffffbfff, 0xffff7fff, x3, 16, x5)
+
+inst_18:
+// rs2_val == 4294950911, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xc;  op2val:0xffffbfff
+TEST_RR_OP(remu, x12, x10, x11, 0xc, 0xc, 0xffffbfff, x3, 20, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_19:
+// rs2_val == 4294959103, rs1_val == 0
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffffdfff
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xffffdfff, x1, 0, x2)
+
+inst_20:
+// rs2_val == 4294963199, rs1_val == 4294967287
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0xffffefff
+TEST_RR_OP(remu, x12, x10, x11, 0xff8, 0xfffffff7, 0xffffefff, x1, 4, x2)
+
+inst_21:
+// rs2_val == 4294965247, rs1_val == 536870912
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0xfffff7ff
+TEST_RR_OP(remu, x12, x10, x11, 0x20000000, 0x20000000, 0xfffff7ff, x1, 8, x2)
+
+inst_22:
+// rs2_val == 4294966271, rs1_val == 65536
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xfffffbff
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0xfffffbff, x1, 12, x2)
+
+inst_23:
+// rs2_val == 4294967039, rs1_val == 4294967231
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0xfffffeff
+TEST_RR_OP(remu, x12, x10, x11, 0xc0, 0xffffffbf, 0xfffffeff, x1, 16, x2)
+
+inst_24:
+// rs2_val == 4294967167, rs1_val == 1024
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0xffffff7f
+TEST_RR_OP(remu, x12, x10, x11, 0x400, 0x400, 0xffffff7f, x1, 20, x2)
+
+inst_25:
+// rs2_val == 4294967231, rs1_val == 1
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffffffbf
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xffffffbf, x1, 24, x2)
+
+inst_26:
+// rs2_val == 4294967263, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffffffdf
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0xffffffdf, x1, 28, x2)
+
+inst_27:
+// rs2_val == 4294967279, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0xffffffef
+TEST_RR_OP(remu, x12, x10, x11, 0xffffffbf, 0xffffffbf, 0xffffffef, x1, 32, x2)
+
+inst_28:
+// rs2_val == 4294967287, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffffff7
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xfffffff7, x1, 36, x2)
+
+inst_29:
+// rs2_val == 4294967291, rs1_val == 4294934527
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fff;  op2val:0xfffffffb
+TEST_RR_OP(remu, x12, x10, x11, 0xffff7fff, 0xffff7fff, 0xfffffffb, x1, 40, x2)
+
+inst_30:
+// rs2_val == 4294967293, rs1_val == 4294967294
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffe;  op2val:0xfffffffd
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xfffffffe, 0xfffffffd, x1, 44, x2)
+
+inst_31:
+// rs2_val == 4294967294, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0xfffffffe
+TEST_RR_OP(remu, x12, x10, x11, 0x400, 0x400, 0xfffffffe, x1, 48, x2)
+
+inst_32:
+// rs1_val == 2147483647, rs2_val == 2097152
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x200000
+TEST_RR_OP(remu, x12, x10, x11, 0x1fffff, 0x7fffffff, 0x200000, x1, 52, x2)
+
+inst_33:
+// rs1_val == 3221225471, rs2_val == 512
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffff;  op2val:0x200
+TEST_RR_OP(remu, x12, x10, x11, 0x1ff, 0xbfffffff, 0x200, x1, 56, x2)
+
+inst_34:
+// rs1_val == 4026531839, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0xa9bb, 0xefffffff, 0xb503, x1, 60, x2)
+
+inst_35:
+// rs1_val == 4160749567, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xf7ffffff;  op2val:0xfffffffe
+TEST_RR_OP(remu, x12, x10, x11, 0xf7ffffff, 0xf7ffffff, 0xfffffffe, x1, 64, x2)
+
+inst_36:
+// rs1_val == 4261412863, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0xffffefff
+TEST_RR_OP(remu, x12, x10, x11, 0xfdffffff, 0xfdffffff, 0xffffefff, x1, 68, x2)
+
+inst_37:
+// rs1_val == 4278190079, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfeffffff;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x32333335, 0xfeffffff, 0x66666665, x1, 72, x2)
+
+inst_38:
+// rs1_val == 4290772991, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffff;  op2val:0x12
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0xffbfffff, 0x12, x1, 76, x2)
+
+inst_39:
+// rs1_val == 4293918719, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffefffff;  op2val:0xe
+TEST_RR_OP(remu, x12, x10, x11, 0xd, 0xffefffff, 0xe, x1, 80, x2)
+
+inst_40:
+// rs1_val == 4294443007, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfff7ffff;  op2val:0xffffffbf
+TEST_RR_OP(remu, x12, x10, x11, 0xfff7ffff, 0xfff7ffff, 0xffffffbf, x1, 84, x2)
+
+inst_41:
+// rs1_val == 4294836223, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffff;  op2val:0xfffffffd
+TEST_RR_OP(remu, x12, x10, x11, 0xfffdffff, 0xfffdffff, 0xfffffffd, x1, 88, x2)
+
+inst_42:
+// rs1_val == 4294959103, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0xffdfffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1fe000, 0xffffdfff, 0xffdfffff, x1, 92, x2)
+
+inst_43:
+// rs1_val == 4294963199, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffefff;  op2val:0xa
+TEST_RR_OP(remu, x12, x10, x11, 0x9, 0xffffefff, 0xa, x1, 96, x2)
+
+inst_44:
+// rs1_val == 4294965247, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ff;  op2val:0xfdffffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1fff800, 0xfffff7ff, 0xfdffffff, x1, 100, x2)
+
+inst_45:
+// rs1_val == 4294966271, rs2_val == 4
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffbff;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xfffffbff, 0x4, x1, 104, x2)
+
+inst_46:
+// rs1_val == 4294966783, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdff;  op2val:0xfffffff7
+TEST_RR_OP(remu, x12, x10, x11, 0xfffffdff, 0xfffffdff, 0xfffffff7, x1, 108, x2)
+
+inst_47:
+// rs1_val == 4294967039, rs2_val == 16
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffeff;  op2val:0x10
+TEST_RR_OP(remu, x12, x10, x11, 0xf, 0xfffffeff, 0x10, x1, 112, x2)
+
+inst_48:
+// rs1_val == 4294967167, rs2_val == 4096
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffff7f;  op2val:0x1000
+TEST_RR_OP(remu, x12, x10, x11, 0xf7f, 0xffffff7f, 0x1000, x1, 116, x2)
+
+inst_49:
+// rs1_val == 4294967279, rs2_val == 0
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffef;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xffffffef, 0xffffffef, 0x0, x1, 120, x2)
+
+inst_50:
+// rs1_val == 4294967293, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffd;  op2val:0xffffdfff
+TEST_RR_OP(remu, x12, x10, x11, 0x1ffe, 0xfffffffd, 0xffffdfff, x1, 124, x2)
+
+inst_51:
+// rs2_val == 2147483648, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x80000000
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x80000000, x1, 128, x2)
+
+inst_52:
+// rs2_val == 1073741824, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x40000000
+TEST_RR_OP(remu, x12, x10, x11, 0x20, 0x20, 0x40000000, x1, 132, x2)
+
+inst_53:
+// rs2_val == 536870912, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fff;  op2val:0x20000000
+TEST_RR_OP(remu, x12, x10, x11, 0x1fff7fff, 0xffff7fff, 0x20000000, x1, 136, x2)
+
+inst_54:
+// rs2_val == 268435456, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb;  op2val:0x10000000
+TEST_RR_OP(remu, x12, x10, x11, 0xb, 0xb, 0x10000000, x1, 140, x2)
+
+inst_55:
+// rs2_val == 134217728, rs1_val == 2
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x8000000
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x8000000, x1, 144, x2)
+
+inst_56:
+// rs2_val == 67108864, rs1_val == 4194304
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x4000000
+TEST_RR_OP(remu, x12, x10, x11, 0x400000, 0x400000, 0x4000000, x1, 148, x2)
+
+inst_57:
+// rs2_val == 33554432, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2000000
+TEST_RR_OP(remu, x12, x10, x11, 0x1333332, 0x33333332, 0x2000000, x1, 152, x2)
+
+inst_58:
+// rs2_val == 16777216, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1000000
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x1000000, x1, 156, x2)
+
+inst_59:
+// rs2_val == 8388608, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x800000
+TEST_RR_OP(remu, x12, x10, x11, 0x10, 0x10, 0x800000, x1, 160, x2)
+
+inst_60:
+// rs2_val == 4194304, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ff;  op2val:0x400000
+TEST_RR_OP(remu, x12, x10, x11, 0x3ff7ff, 0xfffff7ff, 0x400000, x1, 164, x2)
+
+inst_61:
+// rs2_val == 1048576, rs1_val == 134217728
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x100000
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x8000000, 0x100000, x1, 168, x2)
+
+inst_62:
+// rs2_val == 524288, rs1_val == 128
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x80000
+TEST_RR_OP(remu, x12, x10, x11, 0x80, 0x80, 0x80000, x1, 172, x2)
+
+inst_63:
+// rs2_val == 262144, rs1_val == 256
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x40000
+TEST_RR_OP(remu, x12, x10, x11, 0x100, 0x100, 0x40000, x1, 176, x2)
+
+inst_64:
+// rs2_val == 131072, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffff;  op2val:0x20000
+TEST_RR_OP(remu, x12, x10, x11, 0x1ffff, 0xfffdffff, 0x20000, x1, 180, x2)
+
+inst_65:
+// rs2_val == 65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffff7f;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xff7f, 0xffffff7f, 0x10000, x1, 184, x2)
+
+inst_66:
+// rs2_val == 32768, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0x8000
+TEST_RR_OP(remu, x12, x10, x11, 0x7ff7, 0xfffffff7, 0x8000, x1, 188, x2)
+
+inst_67:
+// rs2_val == 16384, rs1_val == 1048576
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x4000
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x100000, 0x4000, x1, 192, x2)
+
+inst_68:
+// rs2_val == 8192, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0x2000
+TEST_RR_OP(remu, x12, x10, x11, 0x1fdf, 0xffffffdf, 0x2000, x1, 196, x2)
+
+inst_69:
+// rs2_val == 2048, rs1_val == 4
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x800
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x800, x1, 200, x2)
+
+inst_70:
+// rs2_val == 1024, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0x400
+TEST_RR_OP(remu, x12, x10, x11, 0x3ff, 0xefffffff, 0x400, x1, 204, x2)
+
+inst_71:
+// rs2_val == 256, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x100
+TEST_RR_OP(remu, x12, x10, x11, 0x67, 0x66666667, 0x100, x1, 208, x2)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x80
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x400, 0x80, x1, 212, x2)
+
+inst_73:
+// rs2_val == 64, rs1_val == 8
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x40
+TEST_RR_OP(remu, x12, x10, x11, 0x8, 0x8, 0x40, x1, 216, x2)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x20
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x20, x1, 220, x2)
+
+inst_75:
+// rs2_val == 8, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x8
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x33333333, 0x8, x1, 224, x2)
+
+inst_76:
+// rs2_val == 2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x8000, 0x2, x1, 228, x2)
+
+inst_77:
+// rs2_val == 1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xefffffff, 0x1, x1, 232, x2)
+
+inst_78:
+// rs1_val == 2147483648, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x80000000;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x80000000, 0x80000000, 0xaaaaaaab, x1, 236, x2)
+
+inst_79:
+// rs1_val == 1073741824, rs2_val == (2**(xlen)-1)
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0xffffffff
+TEST_RR_OP(remu, x12, x10, x11, 0x40000000, 0x40000000, 0xffffffff, x1, 240, x2)
+
+inst_80:
+// rs1_val == 268435456, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x10000000, 0x10000000, 0x33333334, x1, 244, x2)
+
+inst_81:
+// rs1_val == 67108864, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x2160, 0x4000000, 0xb504, x1, 248, x2)
+
+inst_82:
+// rs1_val == 33554432, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x20
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x2000000, 0x20, x1, 252, x2)
+
+inst_83:
+// rs1_val == 16777216, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0xfff7ffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1000000, 0x1000000, 0xfff7ffff, x1, 256, x2)
+
+inst_84:
+// rs1_val == 8388608, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x800000, 0x2, x1, 260, x2)
+
+inst_85:
+// rs1_val == 2097152, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0xffdfffff
+TEST_RR_OP(remu, x12, x10, x11, 0x200000, 0x200000, 0xffdfffff, x1, 264, x2)
+
+inst_86:
+// rs1_val == 524288, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0xfdffffff
+TEST_RR_OP(remu, x12, x10, x11, 0x80000, 0x80000, 0xfdffffff, x1, 268, x2)
+
+inst_87:
+// rs1_val == 262144, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x40000, 0x40000, 0x66666666, x1, 272, x2)
+
+inst_88:
+// rs1_val == 16384, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xfffffeff
+TEST_RR_OP(remu, x12, x10, x11, 0x4000, 0x4000, 0xfffffeff, x1, 276, x2)
+
+inst_89:
+// rs1_val == 8192, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0xfffffffb
+TEST_RR_OP(remu, x12, x10, x11, 0x2000, 0x2000, 0xfffffffb, x1, 280, x2)
+
+inst_90:
+// rs1_val == 4096, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0xfffbffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1000, 0x1000, 0xfffbffff, x1, 284, x2)
+
+inst_91:
+// rs1_val == 2048, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0xfffbffff
+TEST_RR_OP(remu, x12, x10, x11, 0x800, 0x800, 0xfffbffff, x1, 288, x2)
+
+inst_92:
+// rs1_val == 512, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0xf
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x200, 0xf, x1, 292, x2)
+
+inst_93:
+// rs1_val == 64, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0xff7fffff
+TEST_RR_OP(remu, x12, x10, x11, 0x40, 0x40, 0xff7fffff, x1, 296, x2)
+
+inst_94:
+// rs1_val==65536 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x10000, 0x10000, x1, 300, x2)
+
+inst_95:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x10000, 0x1, x1, 304, x2)
+
+inst_96:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x4afb, 0x10000, 0xb505, x1, 308, x2)
+
+inst_97:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x66666667, x1, 312, x2)
+
+inst_98:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x33333334, x1, 316, x2)
+
+inst_99:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x10000, 0x6, x1, 320, x2)
+
+inst_100:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0xaaaaaaab, x1, 324, x2)
+
+inst_101:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x55555556, x1, 328, x2)
+
+inst_102:
+// rs1_val==65536 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x10000, 0x4, x1, 332, x2)
+
+inst_103:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x10000, 0xfffe, x1, 336, x2)
+
+inst_104:
+// rs1_val==65536 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x0, x1, 340, x2)
+
+inst_105:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x4afd, 0x10000, 0xb503, x1, 344, x2)
+
+inst_106:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x66666665, x1, 348, x2)
+
+inst_107:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x33333332, x1, 352, x2)
+
+inst_108:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0xaaaaaaa9, x1, 356, x2)
+
+inst_109:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x55555554, x1, 360, x2)
+
+inst_110:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x10000, 0x2, x1, 364, x2)
+
+inst_111:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x10000, 0xffff, x1, 368, x2)
+
+inst_112:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x4afc, 0x10000, 0xb504, x1, 372, x2)
+
+inst_113:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x66666666, x1, 376, x2)
+
+inst_114:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x33333333, x1, 380, x2)
+
+inst_115:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x10000, 0x5, x1, 384, x2)
+
+inst_116:
+// rs1_val==65536 and rs2_val==2863311530, rs2_val == 2863311530
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0xaaaaaaaa, x1, 388, x2)
+
+inst_117:
+// rs1_val==65536 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x10000, 0x10000, 0x55555555, x1, 392, x2)
+
+inst_118:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x10000, 0x3, x1, 396, x2)
+
+inst_119:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x10000, x1, 400, x2)
+
+inst_120:
+// rs1_val==1 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x1, 0x1, x1, 404, x2)
+
+inst_121:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xb505, x1, 408, x2)
+
+inst_122:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x66666667, x1, 412, x2)
+
+inst_123:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x33333334, x1, 416, x2)
+
+inst_124:
+// rs1_val==1 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x6, x1, 420, x2)
+
+inst_125:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaab, x1, 424, x2)
+
+inst_126:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x55555556, x1, 428, x2)
+
+inst_127:
+// rs1_val==1 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x4, x1, 432, x2)
+
+inst_128:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xfffe, x1, 436, x2)
+
+inst_129:
+// rs1_val==1 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x0, x1, 440, x2)
+
+inst_130:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xb503, x1, 444, x2)
+
+inst_131:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x66666665, x1, 448, x2)
+
+inst_132:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x33333332, x1, 452, x2)
+
+inst_133:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaa9, x1, 456, x2)
+
+inst_134:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x55555554, x1, 460, x2)
+
+inst_135:
+// rs1_val==1 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x2, x1, 464, x2)
+
+inst_136:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xffff, x1, 468, x2)
+
+inst_137:
+// rs1_val==1 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xb504, x1, 472, x2)
+
+inst_138:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x66666666, x1, 476, x2)
+
+inst_139:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x33333333, x1, 480, x2)
+
+inst_140:
+// rs1_val==1 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x5, x1, 484, x2)
+
+inst_141:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaaa, x1, 488, x2)
+
+inst_142:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x55555555, x1, 492, x2)
+
+inst_143:
+// rs1_val==1 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x1, 0x3, x1, 496, x2)
+
+inst_144:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x10000, x1, 500, x2)
+
+inst_145:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb505, 0x1, x1, 504, x2)
+
+inst_146:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb505, 0xb505, x1, 508, x2)
+
+inst_147:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x66666667, x1, 512, x2)
+
+inst_148:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x33333334, x1, 516, x2)
+
+inst_149:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xb505, 0x6, x1, 520, x2)
+
+inst_150:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0xaaaaaaab, x1, 524, x2)
+
+inst_151:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x55555556, x1, 528, x2)
+
+inst_152:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb505, 0x4, x1, 532, x2)
+
+inst_153:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0xfffe, x1, 536, x2)
+
+inst_154:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x0, x1, 540, x2)
+
+inst_155:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xb505, 0xb503, x1, 544, x2)
+
+inst_156:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x66666665, x1, 548, x2)
+
+inst_157:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x33333332, x1, 552, x2)
+
+inst_158:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0xaaaaaaa9, x1, 556, x2)
+
+inst_159:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x55555554, x1, 560, x2)
+
+inst_160:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb505, 0x2, x1, 564, x2)
+
+inst_161:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0xffff, x1, 568, x2)
+
+inst_162:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb505, 0xb504, x1, 572, x2)
+
+inst_163:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x66666666, x1, 576, x2)
+
+inst_164:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x33333333, x1, 580, x2)
+
+inst_165:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb505, 0x5, x1, 584, x2)
+
+inst_166:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0xaaaaaaaa, x1, 588, x2)
+
+inst_167:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0xb505, 0xb505, 0x55555555, x1, 592, x2)
+
+inst_168:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb505, 0x3, x1, 596, x2)
+
+inst_169:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x6667, 0x66666667, 0x10000, x1, 600, x2)
+
+inst_170:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666667, 0x1, x1, 604, x2)
+
+inst_171:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x8257, 0x66666667, 0xb505, x1, 608, x2)
+
+inst_172:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x1, 612, x2)
+
+inst_173:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x66666667, 0x33333334, x1, 616, x2)
+
+inst_174:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666667, 0x6, x1, 620, x2)
+
+inst_175:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x66666667, 0x66666667, 0xaaaaaaab, x1, 624, x2)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x11111111, 0x66666667, 0x55555556, x1, 628, x2)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x66666667, 0x4, x1, 632, x2)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x3335, 0x66666667, 0xfffe, x1, 636, x2)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 640, x2)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x39f1, 0x66666667, 0xb503, x1, 644, x2)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x66666667, 0x66666665, x1, 648, x2)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x66666667, 0x33333332, x1, 652, x2)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x66666667, 0x66666667, 0xaaaaaaa9, x1, 656, x2)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x11111113, 0x66666667, 0x55555554, x1, 660, x2)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666667, 0x2, x1, 664, x2)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xcccd, 0x66666667, 0xffff, x1, 668, x2)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x5e23, 0x66666667, 0xb504, x1, 672, x2)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 676, x2)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666667, 0x33333333, x1, 680, x2)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x66666667, 0x5, x1, 684, x2)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x66666667, 0x66666667, 0xaaaaaaaa, x1, 688, x2)
+
+inst_192:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x11111112, 0x66666667, 0x55555555, x1, 692, x2)
+
+inst_193:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666667, 0x3, x1, 696, x2)
+
+inst_194:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x3334, 0x33333334, 0x10000, x1, 700, x2)
+
+inst_195:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333334, 0x1, x1, 704, x2)
+
+inst_196:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x412c, 0x33333334, 0xb505, x1, 708, x2)
+
+inst_197:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x66666667, x1, 712, x2)
+
+inst_198:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x1, 716, x2)
+
+inst_199:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x33333334, 0x6, x1, 720, x2)
+
+inst_200:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0xaaaaaaab, x1, 724, x2)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x55555556, x1, 728, x2)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333334, 0x4, x1, 732, x2)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x999a, 0x33333334, 0xfffe, x1, 736, x2)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 740, x2)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x1cf9, 0x33333334, 0xb503, x1, 744, x2)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x66666665, x1, 748, x2)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x33333334, 0x33333332, x1, 752, x2)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0xaaaaaaa9, x1, 756, x2)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x55555554, x1, 760, x2)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333334, 0x2, x1, 764, x2)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x6667, 0x33333334, 0xffff, x1, 768, x2)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x8994, 0x33333334, 0xb504, x1, 772, x2)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x66666666, x1, 776, x2)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x33333334, 0x33333333, x1, 780, x2)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333334, 0x5, x1, 784, x2)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0xaaaaaaaa, x1, 788, x2)
+
+inst_217:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x33333334, 0x33333334, 0x55555555, x1, 792, x2)
+
+inst_218:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x33333334, 0x3, x1, 796, x2)
+
+inst_219:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x10000, x1, 800, x2)
+
+inst_220:
+// rs1_val==6 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x6, 0x1, x1, 804, x2)
+
+inst_221:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xb505, x1, 808, x2)
+
+inst_222:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x66666667, x1, 812, x2)
+
+inst_223:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x33333334, x1, 816, x2)
+
+inst_224:
+// rs1_val==6 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x6, 0x6, x1, 820, x2)
+
+inst_225:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xaaaaaaab, x1, 824, x2)
+
+inst_226:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x55555556, x1, 828, x2)
+
+inst_227:
+// rs1_val==6 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x6, 0x4, x1, 832, x2)
+
+inst_228:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xfffe, x1, 836, x2)
+
+inst_229:
+// rs1_val==6 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x0, x1, 840, x2)
+
+inst_230:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xb503, x1, 844, x2)
+
+inst_231:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x66666665, x1, 848, x2)
+
+inst_232:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x33333332, x1, 852, x2)
+
+inst_233:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xaaaaaaa9, x1, 856, x2)
+
+inst_234:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x55555554, x1, 860, x2)
+
+inst_235:
+// rs1_val==6 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x6, 0x2, x1, 864, x2)
+
+inst_236:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xffff, x1, 868, x2)
+
+inst_237:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xb504, x1, 872, x2)
+
+inst_238:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x66666666, x1, 876, x2)
+
+inst_239:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x33333333, x1, 880, x2)
+
+inst_240:
+// rs1_val==6 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x6, 0x5, x1, 884, x2)
+
+inst_241:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0xaaaaaaaa, x1, 888, x2)
+
+inst_242:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x6, 0x6, 0x55555555, x1, 892, x2)
+
+inst_243:
+// rs1_val==6 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x6, 0x3, x1, 896, x2)
+
+inst_244:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xaaab, 0xaaaaaaab, 0x10000, x1, 900, x2)
+
+inst_245:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x1, x1, 904, x2)
+
+inst_246:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x9ce4, 0xaaaaaaab, 0xb505, x1, 908, x2)
+
+inst_247:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x44444444, 0xaaaaaaab, 0x66666667, x1, 912, x2)
+
+inst_248:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x1111110f, 0xaaaaaaab, 0x33333334, x1, 916, x2)
+
+inst_249:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x6, x1, 920, x2)
+
+inst_250:
+// rs1_val==2863311531 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xaaaaaaab, x1, 924, x2)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0xaaaaaaab, 0x55555556, x1, 928, x2)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x4, x1, 932, x2)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xaaaaaaab, 0xfffe, x1, 936, x2)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaab, 0xaaaaaaab, 0x0, x1, 940, x2)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x6091, 0xaaaaaaab, 0xb503, x1, 944, x2)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x44444446, 0xaaaaaaab, 0x66666665, x1, 948, x2)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x11111115, 0xaaaaaaab, 0x33333332, x1, 952, x2)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaab, 0xaaaaaaa9, x1, 956, x2)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xaaaaaaab, 0x55555554, x1, 960, x2)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x2, x1, 964, x2)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x5556, 0xaaaaaaab, 0xffff, x1, 968, x2)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x2437, 0xaaaaaaab, 0xb504, x1, 972, x2)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x44444445, 0xaaaaaaab, 0x66666666, x1, 976, x2)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x11111112, 0xaaaaaaab, 0x33333333, x1, 980, x2)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x5, x1, 984, x2)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaab, 0xaaaaaaaa, x1, 988, x2)
+
+inst_267:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaab, 0x55555555, x1, 992, x2)
+
+inst_268:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x3, x1, 996, x2)
+
+inst_269:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x5556, 0x55555556, 0x10000, x1, 1000, x2)
+
+inst_270:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555556, 0x1, x1, 1004, x2)
+
+inst_271:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0xa8f5, 0x55555556, 0xb505, x1, 1008, x2)
+
+inst_272:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0x66666667, x1, 1012, x2)
+
+inst_273:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x22222222, 0x55555556, 0x33333334, x1, 1016, x2)
+
+inst_274:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x55555556, 0x6, x1, 1020, x2)
+
+inst_275:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0xaaaaaaab, x1, 1024, x2)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x1, 1028, x2)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x55555556, 0x4, x1, 1032, x2)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x55555556, 0xfffe, x1, 1036, x2)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 1040, x2)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x3049, 0x55555556, 0xb503, x1, 1044, x2)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0x66666665, x1, 1048, x2)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x22222224, 0x55555556, 0x33333332, x1, 1052, x2)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0xaaaaaaa9, x1, 1056, x2)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x55555556, 0x55555554, x1, 1060, x2)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555556, 0x2, x1, 1064, x2)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xaaab, 0x55555556, 0xffff, x1, 1068, x2)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x6c9e, 0x55555556, 0xb504, x1, 1072, x2)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0x66666666, x1, 1076, x2)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x22222223, 0x55555556, 0x33333333, x1, 1080, x2)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555556, 0x5, x1, 1084, x2)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x55555556, 0x55555556, 0xaaaaaaaa, x1, 1088, x2)
+
+inst_292:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555556, 0x55555555, x1, 1092, x2)
+
+inst_293:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x55555556, 0x3, x1, 1096, x2)
+
+inst_294:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x10000, x1, 1100, x2)
+
+inst_295:
+// rs1_val==4 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x4, 0x1, x1, 1104, x2)
+
+inst_296:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xb505, x1, 1108, x2)
+
+inst_297:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x66666667, x1, 1112, x2)
+
+inst_298:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x33333334, x1, 1116, x2)
+
+inst_299:
+// rs1_val==4 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x6, x1, 1120, x2)
+
+inst_300:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xaaaaaaab, x1, 1124, x2)
+
+inst_301:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x55555556, x1, 1128, x2)
+
+inst_302:
+// rs1_val==4 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x4, 0x4, x1, 1132, x2)
+
+inst_303:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xfffe, x1, 1136, x2)
+
+inst_304:
+// rs1_val==4 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x0, x1, 1140, x2)
+
+inst_305:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xb503, x1, 1144, x2)
+
+inst_306:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x66666665, x1, 1148, x2)
+
+inst_307:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x33333332, x1, 1152, x2)
+
+inst_308:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xaaaaaaa9, x1, 1156, x2)
+
+inst_309:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x55555554, x1, 1160, x2)
+
+inst_310:
+// rs1_val==4 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x4, 0x2, x1, 1164, x2)
+
+inst_311:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xffff, x1, 1168, x2)
+
+inst_312:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xb504, x1, 1172, x2)
+
+inst_313:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x66666666, x1, 1176, x2)
+
+inst_314:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x33333333, x1, 1180, x2)
+
+inst_315:
+// rs1_val==4 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x5, x1, 1184, x2)
+
+inst_316:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0xaaaaaaaa, x1, 1188, x2)
+
+inst_317:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x4, 0x55555555, x1, 1192, x2)
+
+inst_318:
+// rs1_val==4 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x4, 0x3, x1, 1196, x2)
+
+inst_319:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x10000, x1, 1200, x2)
+
+inst_320:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xfffe, 0x1, x1, 1204, x2)
+
+inst_321:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x4af9, 0xfffe, 0xb505, x1, 1208, x2)
+
+inst_322:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x66666667, x1, 1212, x2)
+
+inst_323:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x33333334, x1, 1216, x2)
+
+inst_324:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xfffe, 0x6, x1, 1220, x2)
+
+inst_325:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0xaaaaaaab, x1, 1224, x2)
+
+inst_326:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x55555556, x1, 1228, x2)
+
+inst_327:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xfffe, 0x4, x1, 1232, x2)
+
+inst_328:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xfffe, 0xfffe, x1, 1236, x2)
+
+inst_329:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x0, x1, 1240, x2)
+
+inst_330:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x4afb, 0xfffe, 0xb503, x1, 1244, x2)
+
+inst_331:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x66666665, x1, 1248, x2)
+
+inst_332:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x33333332, x1, 1252, x2)
+
+inst_333:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0xaaaaaaa9, x1, 1256, x2)
+
+inst_334:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x55555554, x1, 1260, x2)
+
+inst_335:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xfffe, 0x2, x1, 1264, x2)
+
+inst_336:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0xffff, x1, 1268, x2)
+
+inst_337:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x4afa, 0xfffe, 0xb504, x1, 1272, x2)
+
+inst_338:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x66666666, x1, 1276, x2)
+
+inst_339:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x33333333, x1, 1280, x2)
+
+inst_340:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0xfffe, 0x5, x1, 1284, x2)
+
+inst_341:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0xaaaaaaaa, x1, 1288, x2)
+
+inst_342:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0xfffe, 0xfffe, 0x55555555, x1, 1292, x2)
+
+inst_343:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xfffe, 0x3, x1, 1296, x2)
+
+inst_344:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x10000, x1, 1300, x2)
+
+inst_345:
+// rs1_val==0 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x1, x1, 1304, x2)
+
+inst_346:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1308, x2)
+
+inst_347:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1312, x2)
+
+inst_348:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1316, x2)
+
+inst_349:
+// rs1_val==0 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1320, x2)
+
+inst_350:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaab, x1, 1324, x2)
+
+inst_351:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1328, x2)
+
+inst_352:
+// rs1_val==0 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1332, x2)
+
+inst_353:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xfffe, x1, 1336, x2)
+
+inst_354:
+// rs1_val==0 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1340, x2)
+
+inst_355:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1344, x2)
+
+inst_356:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1348, x2)
+
+inst_357:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1352, x2)
+
+inst_358:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaa9, x1, 1356, x2)
+
+inst_359:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1360, x2)
+
+inst_360:
+// rs1_val==0 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x2, x1, 1364, x2)
+
+inst_361:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xffff, x1, 1368, x2)
+
+inst_362:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1372, x2)
+
+inst_363:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1376, x2)
+
+inst_364:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1380, x2)
+
+inst_365:
+// rs1_val==0 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1384, x2)
+
+inst_366:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0xaaaaaaaa, x1, 1388, x2)
+
+inst_367:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1392, x2)
+
+inst_368:
+// rs1_val==0 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1396, x2)
+
+inst_369:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x10000, x1, 1400, x2)
+
+inst_370:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb503, 0x1, x1, 1404, x2)
+
+inst_371:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xb505, x1, 1408, x2)
+
+inst_372:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x66666667, x1, 1412, x2)
+
+inst_373:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x33333334, x1, 1416, x2)
+
+inst_374:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb503, 0x6, x1, 1420, x2)
+
+inst_375:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xaaaaaaab, x1, 1424, x2)
+
+inst_376:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x55555556, x1, 1428, x2)
+
+inst_377:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xb503, 0x4, x1, 1432, x2)
+
+inst_378:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xfffe, x1, 1436, x2)
+
+inst_379:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 1440, x2)
+
+inst_380:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb503, 0xb503, x1, 1444, x2)
+
+inst_381:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x66666665, x1, 1448, x2)
+
+inst_382:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x33333332, x1, 1452, x2)
+
+inst_383:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xaaaaaaa9, x1, 1456, x2)
+
+inst_384:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x55555554, x1, 1460, x2)
+
+inst_385:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb503, 0x2, x1, 1464, x2)
+
+inst_386:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xffff, x1, 1468, x2)
+
+inst_387:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xb504, x1, 1472, x2)
+
+inst_388:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x66666666, x1, 1476, x2)
+
+inst_389:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x33333333, x1, 1480, x2)
+
+inst_390:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0xb503, 0x5, x1, 1484, x2)
+
+inst_391:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0xaaaaaaaa, x1, 1488, x2)
+
+inst_392:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0xb503, 0xb503, 0x55555555, x1, 1492, x2)
+
+inst_393:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb503, 0x3, x1, 1496, x2)
+
+inst_394:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x6665, 0x66666665, 0x10000, x1, 1500, x2)
+
+inst_395:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666665, 0x1, x1, 1504, x2)
+
+inst_396:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x8255, 0x66666665, 0xb505, x1, 1508, x2)
+
+inst_397:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0x66666667, x1, 1512, x2)
+
+inst_398:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x33333331, 0x66666665, 0x33333334, x1, 1516, x2)
+
+inst_399:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x66666665, 0x6, x1, 1520, x2)
+
+inst_400:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0xaaaaaaab, x1, 1524, x2)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x1111110f, 0x66666665, 0x55555556, x1, 1528, x2)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666665, 0x4, x1, 1532, x2)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x3333, 0x66666665, 0xfffe, x1, 1536, x2)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1540, x2)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x39ef, 0x66666665, 0xb503, x1, 1544, x2)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x1, 1548, x2)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666665, 0x33333332, x1, 1552, x2)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0xaaaaaaa9, x1, 1556, x2)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x11111111, 0x66666665, 0x55555554, x1, 1560, x2)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666665, 0x2, x1, 1564, x2)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xcccb, 0x66666665, 0xffff, x1, 1568, x2)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x5e21, 0x66666665, 0xb504, x1, 1572, x2)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0x66666666, x1, 1576, x2)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x66666665, 0x33333333, x1, 1580, x2)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x66666665, 0x5, x1, 1584, x2)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x66666665, 0x66666665, 0xaaaaaaaa, x1, 1588, x2)
+
+inst_417:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x11111110, 0x66666665, 0x55555555, x1, 1592, x2)
+
+inst_418:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x66666665, 0x3, x1, 1596, x2)
+
+inst_419:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x3332, 0x33333332, 0x10000, x1, 1600, x2)
+
+inst_420:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333332, 0x1, x1, 1604, x2)
+
+inst_421:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x412a, 0x33333332, 0xb505, x1, 1608, x2)
+
+inst_422:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x66666667, x1, 1612, x2)
+
+inst_423:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x33333334, x1, 1616, x2)
+
+inst_424:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x33333332, 0x6, x1, 1620, x2)
+
+inst_425:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0xaaaaaaab, x1, 1624, x2)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x55555556, x1, 1628, x2)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x33333332, 0x4, x1, 1632, x2)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x9998, 0x33333332, 0xfffe, x1, 1636, x2)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1640, x2)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x1cf7, 0x33333332, 0xb503, x1, 1644, x2)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x66666665, x1, 1648, x2)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x1, 1652, x2)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0xaaaaaaa9, x1, 1656, x2)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x55555554, x1, 1660, x2)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333332, 0x2, x1, 1664, x2)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x6665, 0x33333332, 0xffff, x1, 1668, x2)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x8992, 0x33333332, 0xb504, x1, 1672, x2)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x66666666, x1, 1676, x2)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x33333333, x1, 1680, x2)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x33333332, 0x5, x1, 1684, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0xaaaaaaaa, x1, 1688, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x33333332, 0x55555555, x1, 1692, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x33333332, 0x3, x1, 1696, x2)
+
+inst_444:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xaaa9, 0xaaaaaaa9, 0x10000, x1, 1700, x2)
+
+inst_445:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x1, x1, 1704, x2)
+
+inst_446:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x9ce2, 0xaaaaaaa9, 0xb505, x1, 1708, x2)
+
+inst_447:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x44444442, 0xaaaaaaa9, 0x66666667, x1, 1712, x2)
+
+inst_448:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x1111110d, 0xaaaaaaa9, 0x33333334, x1, 1716, x2)
+
+inst_449:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x6, x1, 1720, x2)
+
+inst_450:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0xaaaaaaab, x1, 1724, x2)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x55555553, 0xaaaaaaa9, 0x55555556, x1, 1728, x2)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x4, x1, 1732, x2)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0xfffe, x1, 1736, x2)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0x0, x1, 1740, x2)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x608f, 0xaaaaaaa9, 0xb503, x1, 1744, x2)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x44444444, 0xaaaaaaa9, 0x66666665, x1, 1748, x2)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x11111113, 0xaaaaaaa9, 0x33333332, x1, 1752, x2)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xaaaaaaa9, x1, 1756, x2)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x55555554, x1, 1760, x2)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x2, x1, 1764, x2)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x5554, 0xaaaaaaa9, 0xffff, x1, 1768, x2)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x2435, 0xaaaaaaa9, 0xb504, x1, 1772, x2)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x44444443, 0xaaaaaaa9, 0x66666666, x1, 1776, x2)
+
+inst_464:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x11111110, 0xaaaaaaa9, 0x33333333, x1, 1780, x2)
+
+inst_465:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0xaaaaaaa9, 0x5, x1, 1784, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x4, x1, 1788, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0xfffe, x1, 1792, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1796, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x3047, 0x55555554, 0xb503, x1, 1800, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x66666665, x1, 1804, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x22222222, 0x55555554, 0x33333332, x1, 1808, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0xaaaaaaa9, x1, 1812, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x1, 1816, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x2, x1, 1820, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xaaa9, 0x55555554, 0xffff, x1, 1824, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x6c9c, 0x55555554, 0xb504, x1, 1828, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x66666666, x1, 1832, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x22222221, 0x55555554, 0x33333333, x1, 1836, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x55555554, 0x5, x1, 1840, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0xaaaaaaaa, x1, 1844, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x55555555, x1, 1848, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x3, x1, 1852, x2)
+
+inst_483:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x10000, x1, 1856, x2)
+
+inst_484:
+// rs1_val==2 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x2, 0x1, x1, 1860, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xb505, x1, 1864, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x66666667, x1, 1868, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x33333334, x1, 1872, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x6, x1, 1876, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xaaaaaaab, x1, 1880, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x55555556, x1, 1884, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x4, x1, 1888, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xfffe, x1, 1892, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x0, x1, 1896, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xb503, x1, 1900, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x66666665, x1, 1904, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x33333332, x1, 1908, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xaaaaaaa9, x1, 1912, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x55555554, x1, 1916, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x2, 0x2, x1, 1920, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xffff, x1, 1924, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xb504, x1, 1928, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x66666666, x1, 1932, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x33333333, x1, 1936, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x5, x1, 1940, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0xaaaaaaaa, x1, 1944, x2)
+
+inst_506:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x55555555, x1, 1948, x2)
+
+inst_507:
+// rs1_val==2 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x2, 0x3, x1, 1952, x2)
+
+inst_508:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x10000, x1, 1956, x2)
+
+inst_509:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xffff, 0x1, x1, 1960, x2)
+
+inst_510:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x4afa, 0xffff, 0xb505, x1, 1964, x2)
+
+inst_511:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x66666667, x1, 1968, x2)
+
+inst_512:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x33333334, x1, 1972, x2)
+
+inst_513:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xffff, 0x6, x1, 1976, x2)
+
+inst_514:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0xaaaaaaab, x1, 1980, x2)
+
+inst_515:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x55555556, x1, 1984, x2)
+
+inst_516:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0xffff, 0x4, x1, 1988, x2)
+
+inst_517:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xffff, 0xfffe, x1, 1992, x2)
+
+inst_518:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x0, x1, 1996, x2)
+
+inst_519:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x4afc, 0xffff, 0xb503, x1, 2000, x2)
+
+inst_520:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x66666665, x1, 2004, x2)
+
+inst_521:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x33333332, x1, 2008, x2)
+
+inst_522:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0xaaaaaaa9, x1, 2012, x2)
+
+inst_523:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x55555554, x1, 2016, x2)
+
+inst_524:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xffff, 0x2, x1, 2020, x2)
+
+inst_525:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xffff, 0xffff, x1, 2024, x2)
+
+inst_526:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x4afb, 0xffff, 0xb504, x1, 2028, x2)
+
+inst_527:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x66666666, x1, 2032, x2)
+
+inst_528:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x33333333, x1, 2036, x2)
+
+inst_529:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xffff, 0x5, x1, 2040, x2)
+
+inst_530:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0xaaaaaaaa, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_531:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0xffff, 0xffff, 0x55555555, x1, 0, x2)
+
+inst_532:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xffff, 0x3, x1, 4, x2)
+
+inst_533:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x10000, x1, 8, x2)
+
+inst_534:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb504, 0x1, x1, 12, x2)
+
+inst_535:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xb505, x1, 16, x2)
+
+inst_536:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x66666667, x1, 20, x2)
+
+inst_537:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x33333334, x1, 24, x2)
+
+inst_538:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xb504, 0x6, x1, 28, x2)
+
+inst_539:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xaaaaaaab, x1, 32, x2)
+
+inst_540:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x55555556, x1, 36, x2)
+
+inst_541:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb504, 0x4, x1, 40, x2)
+
+inst_542:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xfffe, x1, 44, x2)
+
+inst_543:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x0, x1, 48, x2)
+
+inst_544:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xb504, 0xb503, x1, 52, x2)
+
+inst_545:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x66666665, x1, 56, x2)
+
+inst_546:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x33333332, x1, 60, x2)
+
+inst_547:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xaaaaaaa9, x1, 64, x2)
+
+inst_548:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x55555554, x1, 68, x2)
+
+inst_549:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb504, 0x2, x1, 72, x2)
+
+inst_550:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xffff, x1, 76, x2)
+
+inst_551:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb504, 0xb504, x1, 80, x2)
+
+inst_552:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x66666666, x1, 84, x2)
+
+inst_553:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x33333333, x1, 88, x2)
+
+inst_554:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xb504, 0x5, x1, 92, x2)
+
+inst_555:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0xaaaaaaaa, x1, 96, x2)
+
+inst_556:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0xb504, 0xb504, 0x55555555, x1, 100, x2)
+
+inst_557:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xb504, 0x3, x1, 104, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x6666, 0x66666666, 0x10000, x1, 108, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x1, x1, 112, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x8256, 0x66666666, 0xb505, x1, 116, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x66666666, 0x66666666, 0x66666667, x1, 120, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x33333332, 0x66666666, 0x33333334, x1, 124, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x6, x1, 128, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x66666666, 0x66666666, 0xaaaaaaab, x1, 132, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x11111110, 0x66666666, 0x55555556, x1, 136, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x66666666, 0x4, x1, 140, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x3334, 0x66666666, 0xfffe, x1, 144, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 148, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x39f0, 0x66666666, 0xb503, x1, 152, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x66666666, 0x66666665, x1, 156, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x66666666, 0x33333332, x1, 160, x2)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x66666666, 0x66666666, 0xaaaaaaa9, x1, 164, x2)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x11111112, 0x66666666, 0x55555554, x1, 168, x2)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x2, x1, 172, x2)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xcccc, 0x66666666, 0xffff, x1, 176, x2)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x5e22, 0x66666666, 0xb504, x1, 180, x2)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x1, 184, x2)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x33333333, x1, 188, x2)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x66666666, 0x5, x1, 192, x2)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x66666666, 0x66666666, 0xaaaaaaaa, x1, 196, x2)
+
+inst_581:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x11111111, 0x66666666, 0x55555555, x1, 200, x2)
+
+inst_582:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x66666666, 0x3, x1, 204, x2)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x3333, 0x33333333, 0x10000, x1, 208, x2)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333333, 0x1, x1, 212, x2)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x412b, 0x33333333, 0xb505, x1, 216, x2)
+
+inst_586:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x66666667, x1, 220, x2)
+
+inst_587:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x33333334, x1, 224, x2)
+
+inst_588:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x33333333, 0x6, x1, 228, x2)
+
+inst_589:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0xaaaaaaab, x1, 232, x2)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x55555556, x1, 236, x2)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x33333333, 0x4, x1, 240, x2)
+
+inst_592:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x9999, 0x33333333, 0xfffe, x1, 244, x2)
+
+inst_593:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 248, x2)
+
+inst_594:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0x3, x1, 252, x2)
+
+inst_595:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x1cf8, 0x33333333, 0xb503, x1, 256, x2)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x66666665, x1, 260, x2)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 264, x2)
+
+inst_598:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0xaaaaaaa9, x1, 268, x2)
+
+inst_599:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x55555554, x1, 272, x2)
+
+inst_600:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x33333333, 0x2, x1, 276, x2)
+
+inst_601:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x6666, 0x33333333, 0xffff, x1, 280, x2)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x8993, 0x33333333, 0xb504, x1, 284, x2)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x66666666, x1, 288, x2)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x1, 292, x2)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x4, 0x33333333, 0x5, x1, 296, x2)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0xaaaaaaaa, x1, 300, x2)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x33333333, 0x33333333, 0x55555555, x1, 304, x2)
+
+inst_608:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x33333333, 0x3, x1, 308, x2)
+
+inst_609:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x10000, x1, 312, x2)
+
+inst_610:
+// rs1_val==5 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x5, 0x1, x1, 316, x2)
+
+inst_611:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xb505, x1, 320, x2)
+
+inst_612:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x66666667, x1, 324, x2)
+
+inst_613:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x33333334, x1, 328, x2)
+
+inst_614:
+// rs1_val==5 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x6, x1, 332, x2)
+
+inst_615:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xaaaaaaab, x1, 336, x2)
+
+inst_616:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x55555556, x1, 340, x2)
+
+inst_617:
+// rs1_val==5 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x5, 0x4, x1, 344, x2)
+
+inst_618:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xfffe, x1, 348, x2)
+
+inst_619:
+// rs1_val==5 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x0, x1, 352, x2)
+
+inst_620:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xb503, x1, 356, x2)
+
+inst_621:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x66666665, x1, 360, x2)
+
+inst_622:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x33333332, x1, 364, x2)
+
+inst_623:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xaaaaaaa9, x1, 368, x2)
+
+inst_624:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x55555554, x1, 372, x2)
+
+inst_625:
+// rs1_val==5 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x5, 0x2, x1, 376, x2)
+
+inst_626:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xffff, x1, 380, x2)
+
+inst_627:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xb504, x1, 384, x2)
+
+inst_628:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x66666666, x1, 388, x2)
+
+inst_629:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x33333333, x1, 392, x2)
+
+inst_630:
+// rs1_val==5 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x5, 0x5, x1, 396, x2)
+
+inst_631:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0xaaaaaaaa, x1, 400, x2)
+
+inst_632:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x5, 0x5, 0x55555555, x1, 404, x2)
+
+inst_633:
+// rs1_val==5 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0x5, 0x3, x1, 408, x2)
+
+inst_634:
+// rs1_val==2863311530 and rs2_val==65536, rs1_val == 2863311530
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaa, 0xaaaaaaaa, 0x10000, x1, 412, x2)
+
+inst_635:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x1, x1, 416, x2)
+
+inst_636:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x9ce3, 0xaaaaaaaa, 0xb505, x1, 420, x2)
+
+inst_637:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x44444443, 0xaaaaaaaa, 0x66666667, x1, 424, x2)
+
+inst_638:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x1111110e, 0xaaaaaaaa, 0x33333334, x1, 428, x2)
+
+inst_639:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x6, x1, 432, x2)
+
+inst_640:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaab, x1, 436, x2)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0xaaaaaaaa, 0x55555556, x1, 440, x2)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x4, x1, 444, x2)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0xfffe, x1, 448, x2)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaaa, 0xaaaaaaaa, 0x0, x1, 452, x2)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x6090, 0xaaaaaaaa, 0xb503, x1, 456, x2)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x44444445, 0xaaaaaaaa, 0x66666665, x1, 460, x2)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x11111114, 0xaaaaaaaa, 0x33333332, x1, 464, x2)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0xaaaaaaa9, x1, 468, x2)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x55555554, x1, 472, x2)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x2, x1, 476, x2)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x5555, 0xaaaaaaaa, 0xffff, x1, 480, x2)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x2436, 0xaaaaaaaa, 0xb504, x1, 484, x2)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x44444444, 0xaaaaaaaa, 0x66666666, x1, 488, x2)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x11111111, 0xaaaaaaaa, 0x33333333, x1, 492, x2)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x5, x1, 496, x2)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xaaaaaaaa, x1, 500, x2)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x55555555, x1, 504, x2)
+
+inst_658:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x2, 0xaaaaaaaa, 0x3, x1, 508, x2)
+
+inst_659:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x5555, 0x55555555, 0x10000, x1, 512, x2)
+
+inst_660:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555555, 0x1, x1, 516, x2)
+
+inst_661:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0xa8f4, 0x55555555, 0xb505, x1, 520, x2)
+
+inst_662:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0x66666667, x1, 524, x2)
+
+inst_663:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x22222221, 0x55555555, 0x33333334, x1, 528, x2)
+
+inst_664:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0x6, x1, 532, x2)
+
+inst_665:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0xaaaaaaab, x1, 536, x2)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0x55555556, x1, 540, x2)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0x4, x1, 544, x2)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0xfffe, x1, 548, x2)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 552, x2)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x3048, 0x55555555, 0xb503, x1, 556, x2)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0x66666665, x1, 560, x2)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x22222223, 0x55555555, 0x33333332, x1, 564, x2)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0xaaaaaaa9, x1, 568, x2)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 572, x2)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0x2, x1, 576, x2)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaa, 0x55555555, 0xffff, x1, 580, x2)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x6c9d, 0x55555555, 0xb504, x1, 584, x2)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0x66666666, x1, 588, x2)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x22222222, 0x55555555, 0x33333333, x1, 592, x2)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555555, 0x5, x1, 596, x2)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0xaaaaaaaa, x1, 600, x2)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x1, 604, x2)
+
+inst_683:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x55555555, 0x3, x1, 608, x2)
+
+inst_684:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x10000, x1, 612, x2)
+
+inst_685:
+// rs1_val==3 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x3, 0x1, x1, 616, x2)
+
+inst_686:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xb505, x1, 620, x2)
+
+inst_687:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x66666667, x1, 624, x2)
+
+inst_688:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x33333334, x1, 628, x2)
+
+inst_689:
+// rs1_val==3 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x6, x1, 632, x2)
+
+inst_690:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xaaaaaaab, x1, 636, x2)
+
+inst_691:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x55555556, x1, 640, x2)
+
+inst_692:
+// rs1_val==3 and rs2_val==4, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x4, x1, 644, x2)
+
+inst_693:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xfffe
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xfffe, x1, 648, x2)
+
+inst_694:
+// rs1_val==3 and rs2_val==0, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x0, x1, 652, x2)
+
+inst_695:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xb503, x1, 656, x2)
+
+inst_696:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x66666665, x1, 660, x2)
+
+inst_697:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x33333332, x1, 664, x2)
+
+inst_698:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaa9
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xaaaaaaa9, x1, 668, x2)
+
+inst_699:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x55555554, x1, 672, x2)
+
+inst_700:
+// rs1_val==3 and rs2_val==2, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(remu, x12, x10, x11, 0x1, 0x3, 0x2, x1, 676, x2)
+
+inst_701:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffff
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xffff, x1, 680, x2)
+
+inst_702:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xb504, x1, 684, x2)
+
+inst_703:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x66666666, x1, 688, x2)
+
+inst_704:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x33333333, x1, 692, x2)
+
+inst_705:
+// rs1_val==3 and rs2_val==5, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x5, x1, 696, x2)
+
+inst_706:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0xaaaaaaaa, x1, 700, x2)
+
+inst_707:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x3, 0x3, 0x55555555, x1, 704, x2)
+
+inst_708:
+// rs1_val==3 and rs2_val==3, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x3, 0x3, x1, 708, x2)
+
+inst_709:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaaa
+TEST_RR_OP(remu, x12, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0xaaaaaaaa, x1, 712, x2)
+
+inst_710:
+// rs1_val == (2**(xlen)-1), 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff;  op2val:0xffffffef
+TEST_RR_OP(remu, x12, x10, x11, 0x10, 0xffffffff, 0xffffffef, x1, 716, x2)
+
+inst_711:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555555
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0xaaaaaaa9, 0x55555555, x1, 720, x2)
+
+inst_712:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x10000
+TEST_RR_OP(remu, x12, x10, x11, 0x5554, 0x55555554, 0x10000, x1, 724, x2)
+
+inst_713:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x1, x1, 728, x2)
+
+inst_714:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(remu, x12, x10, x11, 0xa8f3, 0x55555554, 0xb505, x1, 732, x2)
+
+inst_715:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x66666667, x1, 736, x2)
+
+inst_716:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(remu, x12, x10, x11, 0x22222220, 0x55555554, 0x33333334, x1, 740, x2)
+
+inst_717:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(remu, x12, x10, x11, 0x0, 0x55555554, 0x6, x1, 744, x2)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaab
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0xaaaaaaab, x1, 748, x2)
+
+inst_719:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(remu, x12, x10, x11, 0x55555554, 0x55555554, 0x55555556, x1, 752, x2)
+
+inst_720:
+// rs2_val == 3221225471, rs1_val == 32768
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0xbfffffff
+TEST_RR_OP(remu, x12, x10, x11, 0x8000, 0x8000, 0xbfffffff, x1, 756, x2)
+
+inst_721:
+// rs2_val == 3758096383, 
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xc;  op2val:0xdfffffff
+TEST_RR_OP(remu, x12, x10, x11, 0xc, 0xc, 0xdfffffff, x1, 760, x2)
+
+inst_722:
+// rs2_val == 4227858431, rs1_val == 1431655765
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfbffffff
+TEST_RR_OP(remu, x12, x10, x11, 0x55555555, 0x55555555, 0xfbffffff, x1, 764, x2)
+
+inst_723:
+// rs2_val == 4261412863, rs1_val == 3758096383
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffff;  op2val:0xfdffffff
+TEST_RR_OP(remu, x12, x10, x11, 0xdfffffff, 0xdfffffff, 0xfdffffff, x1, 768, x2)
+
+inst_724:
+// rs2_val == 4292870143, rs1_val == 4294967291
+// opcode: remu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffb;  op2val:0xffdfffff
+TEST_RR_OP(remu, x12, x10, x11, 0x1ffffc, 0xfffffffb, 0xffdfffff, x1, 772, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 194*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/.gitgnore b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/.gitgnore
new file mode 100644
index 000000000..618bc413b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/.gitgnore
@@ -0,0 +1,6 @@
+I/src/env
+M/src/env
+C/src/env
+privilege/src/env
+Zicsr/src/env
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile
new file mode 100644
index 000000000..d8449d851
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32ic -mabi=ilp32 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag
new file mode 100644
index 000000000..79d1bd169
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/C/Makefrag
@@ -0,0 +1,34 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output
new file mode 100644
index 000000000..ab5658348
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld-01.reference_output
@@ -0,0 +1,3 @@
+00000000
+40000000
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S
new file mode 100644
index 000000000..79b1c963e
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld-01.S
@@ -0,0 +1,81 @@
+///////////////////////////////////////////
+// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-07-07 16:55:21.991349//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_FP_ENABLE()
+RVTEST_VALBASEUPD(x7,test_fp)
+RVTEST_SIGBASE( x6, wally_signature)
+RVTEST_ISA("RV32IFD")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*F.*D.*);def TEST_CASE_1=True;",WALLY-fld)
+inst_0:
+ li x1,2
+ fcvt.d.w f3, x1
+ la x16, rvtest_data
+ fsd f3,0(x16)
+ fld f4,0(x16)
+ fsd f4,0(x6)
+
+ #endif
+
+.EQU NUMTESTS,3
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+.word 0x55555555
+test_fp:
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile
new file mode 100644
index 000000000..4079d3013
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32if -mabi=ilp32 -DXLEN=$(XLEN) -DFLEN=32))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag
new file mode 100644
index 000000000..253e9e0d3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F/Makefrag
@@ -0,0 +1,14 @@
+# RISC-V Architecture Test RV32IF Makefrag
+#
+# Copyright (c) 2021. IIT Madras. All rights reserved.
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Description: Makefrag for RV32IF architectural tests
+
+rv32if_sc_tests = \
+
+
+
+rv32if_tests = $(addsuffix .elf, $(rv32if_sc_tests))
+
+target_tests += $(rv32if_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/.gitignore b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/.gitignore
new file mode 100644
index 000000000..e69de29bb
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile
new file mode 100644
index 000000000..74d788175
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag
new file mode 100644
index 000000000..792ea2e24
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag
@@ -0,0 +1,76 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+ E-add-01 \
+   E-addi-01 \
+   E-and-01 \
+   E-andi-01 \
+   E-auipc-01 \
+   E-beq-01 \
+   E-bge-01 \
+   E-bgeu-01 \
+   E-blt-01 \
+   E-bltu-01 \
+   E-bne-01 \
+   E-jal-01 \
+   E-jalr-01 \
+   E-lb-align-01 \
+   E-lbu-align-01 \
+   E-lh-align-01 \
+   E-lhu-align-01 \
+   E-lui-01 \
+   E-lw-align-01 \
+   E-or-01 \
+   E-ori-01 \
+   E-sb-align-01 \
+   E-sh-align-01 \
+   E-sll-01 \
+   E-slli-01 \
+   E-slt-01 \
+   E-slti-01 \
+   E-sltiu-01 \
+   E-sltu-01 \
+   E-sra-01 \
+   E-srai-01 \
+   E-srl-01 \
+   E-srli-01 \
+   E-sub-01 \
+   E-sw-align-01 \
+   E-xor-01 \
+   E-xori-01 \
+	WALLY-ADD \
+	WALLY-SLT \
+	WALLY-SLTU \
+	WALLY-SUB \
+	WALLY-XOR
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output
new file mode 100644
index 000000000..b364d3f1a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output
@@ -0,0 +1,584 @@
+ffffb7fe
+7ffbfffe
+bfbffffe
+00000040
+00000000
+f6fffffe
+fc000006
+31333332
+ff0007ff
+ff7fffee
+ffbffffa
+fddffffe
+ffedfffe
+ffd7fffe
+fffc007f
+fdfdfffe
+aaa9aaa9
+3332b331
+ffffe002
+fffff008
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+55555454
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+dfff7ffe
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+dddddddf
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+00000001
+aaaaaaaf
+aaab5fae
+aaaaaaab
+11111110
+dddddddd
+ffffffff
+aaaaaaad
+aaab5faf
+aaa9f5a7
+11111111
+ddddddde
+aaaaaab0
+55555555
+00000000
+aaaaaaae
+55560a5b
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+5555555c
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+6666666b
+11111110
+bbbbbbbb
+66666669
+66671b68
+33333333
+99999998
+66666665
+88888887
+33333335
+3333e837
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+66666666
+33333338
+dddddddd
+88888888
+33333336
+0000b50a
+ffff4b02
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+33333339
+0000000b
+aaaaaab0
+5555555b
+00000009
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+33333337
+55555559
+00000007
+0000b509
+ffff4b01
+6666666b
+33333338
+0000000a
+aaaaaaaf
+5555555a
+00000008
+aaab5faf
+aaa9f5a7
+11111111
+ddddddde
+aaaaaab0
+55555555
+00000000
+aaaaaaae
+aaab5fad
+aaaaaaaa
+1111110f
+dddddddc
+fffffffe
+aaaaaaac
+aaab5fae
+aaa9f5a6
+11111110
+dddddddd
+aaaaaaaf
+55555554
+ffffffff
+aaaaaaad
+55560a5a
+5554a052
+bbbbbbbc
+88888889
+5555555b
+00000000
+aaaaaaab
+55555559
+55560a58
+55555555
+bbbbbbba
+88888887
+aaaaaaa9
+55555557
+55560a59
+5554a051
+bbbbbbbb
+88888888
+5555555a
+ffffffff
+aaaaaaaa
+55555558
+0000b508
+ffff4b00
+6666666a
+33333337
+00000009
+aaaaaaae
+55555559
+00000007
+0000b506
+00000003
+66666668
+33333335
+55555557
+00000005
+0000b507
+ffff4aff
+66666669
+33333336
+00000008
+aaaaaaad
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
new file mode 100644
index 000000000..1052749cb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output
new file mode 100644
index 000000000..e8e6b49d4
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output
new file mode 100644
index 000000000..aefc28d98
--- /dev/null
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output
new file mode 100644
index 000000000..5f432d03a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output
new file mode 100644
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--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output
new file mode 100644
index 000000000..fe7d8af34
--- /dev/null
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output
new file mode 100644
index 000000000..14516e603
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output
new file mode 100644
index 000000000..3fff83574
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output
@@ -0,0 +1,68 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output
new file mode 100644
index 000000000..848bc88e3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output
new file mode 100644
index 000000000..a17012ecf
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output
new file mode 100644
index 000000000..f9c1b5659
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-ADD.reference_output
@@ -0,0 +1,12 @@
+00000000
+00000001
+ffffffff
+00000001
+00000002
+00000000
+ffffffff
+00000000
+fffffffe
+b6944260
+83edeb47
+0c939c34
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output
new file mode 100644
index 000000000..6e9ae61d7
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLT.reference_output
@@ -0,0 +1,12 @@
+00000000
+00000001
+00000000
+00000000
+00000000
+00000000
+00000001
+00000001
+00000000
+00000000
+00000001
+00000001
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output
new file mode 100644
index 000000000..993b67cd3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SLTU.reference_output
@@ -0,0 +1,12 @@
+00000000
+00000001
+00000001
+00000000
+00000000
+00000001
+00000000
+00000000
+00000000
+00000001
+00000001
+00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output
new file mode 100644
index 000000000..d35fb3fdb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-SUB.reference_output
@@ -0,0 +1,12 @@
+00000000
+ffffffff
+00000001
+00000001
+00000000
+00000002
+ffffffff
+fffffffe
+00000000
+ebb7926c
+e2aa20ca
+63a59ba8
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output
new file mode 100644
index 000000000..2448d94c1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/WALLY-XOR.reference_output
@@ -0,0 +1,12 @@
+00000000
+00000001
+ffffffff
+00000001
+00000000
+fffffffe
+ffffffff
+fffffffe
+00000000
+674f4c2c
+d1bb1e6e
+3395fef6
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S
new file mode 100644
index 000000000..4abf30fdf
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S
@@ -0,0 +1,3001 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the add instruction of the RISC-V E extension for the add covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",add)
+
+RVTEST_SIGBASE( x10,signature_x10_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x7, rs2==x9, rd==x5, rs1_val != rs2_val, rs1_val < 0 and rs2_val < 0, rs2_val == -16385, rs1_val == -2049
+// opcode: add ; op1:x7; op2:x9; dest:x5; op1val:-0x801;  op2val:-0x4001
+TEST_RR_OP(add, x5, x7, x9, 0xffffb7fe, -0x801, -0x4001, x10, 0, x11)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x12, rs2==x3, rd==x12, rs2_val == 2147483647, rs1_val < 0 and rs2_val > 0, rs1_val == -262145, rs2_val == (2**(xlen-1)-1)
+// opcode: add ; op1:x12; op2:x3; dest:x12; op1val:-0x40001;  op2val:0x7fffffff
+TEST_RR_OP(add, x12, x12, x3, 0x7ffbfffe, -0x40001, 0x7fffffff, x10, 4, x11)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x6, rs2==x1, rd==x1, rs2_val == -1073741825, rs1_val == -4194305
+// opcode: add ; op1:x6; op2:x1; dest:x1; op1val:-0x400001;  op2val:-0x40000001
+TEST_RR_OP(add, x1, x6, x1, 0xbfbffffe, -0x400001, -0x40000001, x10, 8, x11)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x2, rs2==x2, rd==x7, rs2_val == -536870913, rs1_val == 32, rs1_val > 0 and rs2_val < 0
+// opcode: add ; op1:x2; op2:x2; dest:x7; op1val:0x20;  op2val:0x20
+TEST_RR_OP(add, x7, x2, x2, 0x40, 0x20, 0x20, x10, 12, x11)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0, rs2_val == -268435457, rs1_val == 4
+// opcode: add ; op1:x0; op2:x0; dest:x0; op1val:0x0;  op2val:0x0
+TEST_RR_OP(add, x0, x0, x0, 0, 0x0, 0x0, x10, 16, x11)
+
+inst_5:
+// rs1==x8, rs2==x4, rd==x14, rs2_val == -134217729, rs1_val == -16777217
+// opcode: add ; op1:x8; op2:x4; dest:x14; op1val:-0x1000001;  op2val:-0x8000001
+TEST_RR_OP(add, x14, x8, x4, 0xf6fffffe, -0x1000001, -0x8000001, x10, 20, x11)
+
+inst_6:
+// rs1==x4, rs2==x5, rd==x15, rs2_val == -67108865, 
+// opcode: add ; op1:x4; op2:x5; dest:x15; op1val:0x7;  op2val:-0x4000001
+TEST_RR_OP(add, x15, x4, x5, 0xfc000006, 0x7, -0x4000001, x10, 24, x1)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_7:
+// rs1==x14, rs2==x11, rd==x6, rs2_val == -33554433, 
+// opcode: add ; op1:x14; op2:x11; dest:x6; op1val:0x33333333;  op2val:-0x2000001
+TEST_RR_OP(add, x6, x14, x11, 0x31333332, 0x33333333, -0x2000001, x4, 0, x1)
+
+inst_8:
+// rs1==x3, rs2==x10, rd==x2, rs2_val == -16777217, rs1_val == 2048
+// opcode: add ; op1:x3; op2:x10; dest:x2; op1val:0x800;  op2val:-0x1000001
+TEST_RR_OP(add, x2, x3, x10, 0xff0007ff, 0x800, -0x1000001, x4, 4, x1)
+
+inst_9:
+// rs1==x13, rs2==x6, rd==x9, rs2_val == -8388609, rs1_val == -17
+// opcode: add ; op1:x13; op2:x6; dest:x9; op1val:-0x11;  op2val:-0x800001
+TEST_RR_OP(add, x9, x13, x6, 0xff7fffee, -0x11, -0x800001, x4, 8, x1)
+
+inst_10:
+// rs1==x15, rs2==x14, rd==x13, rs2_val == -4194305, rs1_val == -5
+// opcode: add ; op1:x15; op2:x14; dest:x13; op1val:-0x5;  op2val:-0x400001
+TEST_RR_OP(add, x13, x15, x14, 0xffbffffa, -0x5, -0x400001, x4, 12, x1)
+
+inst_11:
+// rs1==x11, rs2==x12, rd==x3, rs2_val == -2097153, rs1_val == -33554433
+// opcode: add ; op1:x11; op2:x12; dest:x3; op1val:-0x2000001;  op2val:-0x200001
+TEST_RR_OP(add, x3, x11, x12, 0xfddffffe, -0x2000001, -0x200001, x4, 16, x1)
+
+inst_12:
+// rs1==x5, rs2==x15, rd==x11, rs2_val == -1048577, rs1_val == -131073
+// opcode: add ; op1:x5; op2:x15; dest:x11; op1val:-0x20001;  op2val:-0x100001
+TEST_RR_OP(add, x11, x5, x15, 0xffedfffe, -0x20001, -0x100001, x4, 20, x2)
+
+inst_13:
+// rs1==x1, rs2==x13, rd==x10, rs2_val == -524289, rs1_val == -2097153
+// opcode: add ; op1:x1; op2:x13; dest:x10; op1val:-0x200001;  op2val:-0x80001
+TEST_RR_OP(add, x10, x1, x13, 0xffd7fffe, -0x200001, -0x80001, x4, 24, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_14:
+// rs1==x10, rs2==x8, rd==x4, rs2_val == -262145, rs1_val == 128
+// opcode: add ; op1:x10; op2:x8; dest:x4; op1val:0x80;  op2val:-0x40001
+TEST_RR_OP(add, x4, x10, x8, 0xfffc007f, 0x80, -0x40001, x1, 0, x2)
+
+inst_15:
+// rs1==x9, rs2==x7, rd==x8, rs2_val == -131073, 
+// opcode: add ; op1:x9; op2:x7; dest:x8; op1val:-0x2000001;  op2val:-0x20001
+TEST_RR_OP(add, x8, x9, x7, 0xfdfdfffe, -0x2000001, -0x20001, x1, 4, x2)
+
+inst_16:
+// rs2_val == -65537, rs1_val == -1431655766
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x10001
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9aaa9, -0x55555556, -0x10001, x1, 8, x2)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x8001
+TEST_RR_OP(add, x12, x10, x11, 0x3332b331, 0x33333332, -0x8001, x1, 12, x2)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x2001
+TEST_RR_OP(add, x12, x10, x11, 0xffffe002, 0x3, -0x2001, x1, 16, x2)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x1001
+TEST_RR_OP(add, x12, x10, x11, 0xfffff008, 0x9, -0x1001, x1, 20, x2)
+
+inst_20:
+// rs2_val == -2049, rs1_val == -524289
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x801
+TEST_RR_OP(add, x12, x10, x11, 0xfff7f7fe, -0x80001, -0x801, x1, 24, x2)
+
+inst_21:
+// rs2_val == -1025, rs1_val == 0
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x401
+TEST_RR_OP(add, x12, x10, x11, 0xfffffbff, 0x0, -0x401, x1, 28, x2)
+
+inst_22:
+// rs2_val == -513, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0x201
+TEST_RR_OP(add, x12, x10, x11, 0xfffff5fe, -0x801, -0x201, x1, 32, x2)
+
+inst_23:
+// rs2_val == -257, rs1_val == 1431655765
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x101
+TEST_RR_OP(add, x12, x10, x11, 0x55555454, 0x55555555, -0x101, x1, 36, x2)
+
+inst_24:
+// rs2_val == -129, rs1_val == -3
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x81
+TEST_RR_OP(add, x12, x10, x11, 0xffffff7c, -0x3, -0x81, x1, 40, x2)
+
+inst_25:
+// rs2_val == -65, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x41
+TEST_RR_OP(add, x12, x10, x11, 0xffdfffbe, -0x200001, -0x41, x1, 44, x2)
+
+inst_26:
+// rs2_val == -33, rs1_val == -129
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:-0x21
+TEST_RR_OP(add, x12, x10, x11, 0xffffff5e, -0x81, -0x21, x1, 48, x2)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x11
+TEST_RR_OP(add, x12, x10, x11, 0xfffffff8, 0x9, -0x11, x1, 52, x2)
+
+inst_28:
+// rs2_val == -9, rs1_val == -16385
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x9
+TEST_RR_OP(add, x12, x10, x11, 0xffffbff6, -0x4001, -0x9, x1, 56, x2)
+
+inst_29:
+// rs2_val == -5, rs1_val == 134217728
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:-0x5
+TEST_RR_OP(add, x12, x10, x11, 0x7fffffb, 0x8000000, -0x5, x1, 60, x2)
+
+inst_30:
+// rs2_val == -3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x3
+TEST_RR_OP(add, x12, x10, x11, 0xffdffffc, -0x200001, -0x3, x1, 64, x2)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x2
+TEST_RR_OP(add, x12, x10, x11, 0xffffbffd, -0x4001, -0x2, x1, 68, x2)
+
+inst_32:
+// rs1_val == 2147483647, rs1_val > 0 and rs2_val > 0, rs1_val == (2**(xlen-1)-1), rs2_val == 131072
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x20000
+TEST_RR_OP(add, x12, x10, x11, 0x8001ffff, 0x7fffffff, 0x20000, x1, 72, x2)
+
+inst_33:
+// rs1_val == -1073741825, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x26666664, -0x40000001, 0x66666665, x1, 76, x2)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:-0x8001
+TEST_RR_OP(add, x12, x10, x11, 0xdfff7ffe, -0x20000001, -0x8001, x1, 80, x2)
+
+inst_35:
+// rs1_val == -268435457, rs2_val == 32
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0x20
+TEST_RR_OP(add, x12, x10, x11, 0xf000001f, -0x10000001, 0x20, x1, 84, x2)
+
+inst_36:
+// rs1_val == -134217729, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x81
+TEST_RR_OP(add, x12, x10, x11, 0xf7ffff7e, -0x8000001, -0x81, x1, 88, x2)
+
+inst_37:
+// rs1_val == -67108865, rs2_val == 1048576
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x100000
+TEST_RR_OP(add, x12, x10, x11, 0xfc0fffff, -0x4000001, 0x100000, x1, 92, x2)
+
+inst_38:
+// rs1_val == -8388609, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:-0x4
+TEST_RR_OP(add, x12, x10, x11, 0xff7ffffb, -0x800001, -0x4, x1, 96, x2)
+
+inst_39:
+// rs1_val == -1048577, rs2_val == 0
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xffefffff, -0x100001, 0x0, x1, 100, x2)
+
+inst_40:
+// rs1_val == -65537, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x1001
+TEST_RR_OP(add, x12, x10, x11, 0xfffeeffe, -0x10001, -0x1001, x1, 104, x2)
+
+inst_41:
+// rs1_val == -32769, rs2_val == 524288
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x80000
+TEST_RR_OP(add, x12, x10, x11, 0x77fff, -0x8001, 0x80000, x1, 108, x2)
+
+inst_42:
+// rs1_val == -8193, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xffffdfff, -0x2001, 0x0, x1, 112, x2)
+
+inst_43:
+// rs1_val == -4097, rs2_val == 262144
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x40000
+TEST_RR_OP(add, x12, x10, x11, 0x3efff, -0x1001, 0x40000, x1, 116, x2)
+
+inst_44:
+// rs1_val == -1025, rs2_val == 256
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x100
+TEST_RR_OP(add, x12, x10, x11, 0xfffffcff, -0x401, 0x100, x1, 120, x2)
+
+inst_45:
+// rs1_val == -513, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:-0x2001
+TEST_RR_OP(add, x12, x10, x11, 0xffffddfe, -0x201, -0x2001, x1, 124, x2)
+
+inst_46:
+// rs1_val == -257, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:-0x1001
+TEST_RR_OP(add, x12, x10, x11, 0xffffeefe, -0x101, -0x1001, x1, 128, x2)
+
+inst_47:
+// rs1_val == -65, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x11
+TEST_RR_OP(add, x12, x10, x11, 0xffffffae, -0x41, -0x11, x1, 132, x2)
+
+inst_48:
+// rs1_val == -33, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x7
+TEST_RR_OP(add, x12, x10, x11, 0xffffffe6, -0x21, 0x7, x1, 136, x2)
+
+inst_49:
+// rs1_val == -9, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:-0x2000001
+TEST_RR_OP(add, x12, x10, x11, 0xfdfffff6, -0x9, -0x2000001, x1, 140, x2)
+
+inst_50:
+// rs1_val == -2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0x6
+TEST_RR_OP(add, x12, x10, x11, 0xfffffff8, -0x2, -0x6, x1, 144, x2)
+
+inst_51:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x80000000
+TEST_RR_OP(add, x12, x10, x11, 0x80000006, 0x6, -0x80000000, x1, 148, x2)
+
+inst_52:
+// rs2_val == 1073741824, rs1_val == 536870912
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x40000000
+TEST_RR_OP(add, x12, x10, x11, 0x60000000, 0x20000000, 0x40000000, x1, 152, x2)
+
+inst_53:
+// rs2_val == 536870912, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000;  op2val:0x20000000
+TEST_RR_OP(add, x12, x10, x11, 0xe0000000, -0x40000000, 0x20000000, x1, 156, x2)
+
+inst_54:
+// rs2_val == 268435456, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x10000000
+TEST_RR_OP(add, x12, x10, x11, 0xbaaaaaaa, -0x55555556, 0x10000000, x1, 160, x2)
+
+inst_55:
+// rs2_val == 134217728, rs1_val == 1
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x8000000
+TEST_RR_OP(add, x12, x10, x11, 0x8000001, 0x1, 0x8000000, x1, 164, x2)
+
+inst_56:
+// rs2_val == 67108864, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4000000
+TEST_RR_OP(add, x12, x10, x11, 0x59555554, 0x55555554, 0x4000000, x1, 168, x2)
+
+inst_57:
+// rs2_val == 33554432, rs1_val == 64
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x2000000
+TEST_RR_OP(add, x12, x10, x11, 0x2000040, 0x40, 0x2000000, x1, 172, x2)
+
+inst_58:
+// rs2_val == 16777216, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1000000
+TEST_RR_OP(add, x12, x10, x11, 0x1000003, 0x3, 0x1000000, x1, 176, x2)
+
+inst_59:
+// rs2_val == 8388608, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x6;  op2val:0x800000
+TEST_RR_OP(add, x12, x10, x11, 0x7ffffa, -0x6, 0x800000, x1, 180, x2)
+
+inst_60:
+// rs2_val == 4194304, rs1_val == 16
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x400000
+TEST_RR_OP(add, x12, x10, x11, 0x400010, 0x10, 0x400000, x1, 184, x2)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x200000
+TEST_RR_OP(add, x12, x10, x11, 0xfffff, -0x100001, 0x200000, x1, 188, x2)
+
+inst_62:
+// rs2_val == 65536, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(add, x12, x10, x11, 0x10000, 0x0, 0x10000, x1, 192, x2)
+
+inst_63:
+// rs2_val == 32768, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x8000
+TEST_RR_OP(add, x12, x10, x11, 0xffff7fff, -0x10001, 0x8000, x1, 196, x2)
+
+inst_64:
+// rs2_val == 16384, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4000
+TEST_RR_OP(add, x12, x10, x11, 0xffff8afd, -0xb503, 0x4000, x1, 200, x2)
+
+inst_65:
+// rs2_val == 8192, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2000
+TEST_RR_OP(add, x12, x10, x11, 0x55557555, 0x55555555, 0x2000, x1, 204, x2)
+
+inst_66:
+// rs2_val == 4096, rs1_val == 65536
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1000
+TEST_RR_OP(add, x12, x10, x11, 0x11000, 0x10000, 0x1000, x1, 208, x2)
+
+inst_67:
+// rs2_val == 2048, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x800
+TEST_RR_OP(add, x12, x10, x11, 0x800, 0x0, 0x800, x1, 212, x2)
+
+inst_68:
+// rs2_val == 1024, rs1_val == 524288
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x400
+TEST_RR_OP(add, x12, x10, x11, 0x80400, 0x80000, 0x400, x1, 216, x2)
+
+inst_69:
+// rs2_val == 512, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0x200
+TEST_RR_OP(add, x12, x10, x11, 0x1fd, -0x3, 0x200, x1, 220, x2)
+
+inst_70:
+// rs2_val == 128, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x80
+TEST_RR_OP(add, x12, x10, x11, 0xfffffe7f, -0x201, 0x80, x1, 224, x2)
+
+inst_71:
+// rs2_val == 64, rs1_val == 2
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x40
+TEST_RR_OP(add, x12, x10, x11, 0x42, 0x2, 0x40, x1, 228, x2)
+
+inst_72:
+// rs2_val == 16, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0x10
+TEST_RR_OP(add, x12, x10, x11, 0xffe0000f, -0x200001, 0x10, x1, 232, x2)
+
+inst_73:
+// rs2_val == 8, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x8
+TEST_RR_OP(add, x12, x10, x11, 0xfffffff7, -0x11, 0x8, x1, 236, x2)
+
+inst_74:
+// rs2_val == 4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xfffffffb, -0x9, 0x4, x1, 240, x2)
+
+inst_75:
+// rs2_val == 2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xffffffc1, -0x41, 0x2, x1, 244, x2)
+
+inst_76:
+// rs2_val == 1, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3fffffff;  op2val:0x1
+TEST_RR_OP(add, x12, x10, x11, 0x40000000, 0x3fffffff, 0x1, x1, 248, x2)
+
+inst_77:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x80000006, -0x80000000, 0x6, x1, 252, x2)
+
+inst_78:
+// rs1_val == 1073741824, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x40000005, 0x40000000, 0x5, x1, 256, x2)
+
+inst_79:
+// rs1_val == 268435456, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xfff4afc, 0x10000000, -0xb504, x1, 260, x2)
+
+inst_80:
+// rs1_val == 67108864, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x4000006, 0x4000000, 0x6, x1, 264, x2)
+
+inst_81:
+// rs1_val == 33554432, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:-0x9
+TEST_RR_OP(add, x12, x10, x11, 0x1fffff7, 0x2000000, -0x9, x1, 268, x2)
+
+inst_82:
+// rs1_val == 16777216, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:-0x7
+TEST_RR_OP(add, x12, x10, x11, 0xfffff9, 0x1000000, -0x7, x1, 272, x2)
+
+inst_83:
+// rs1_val == 8388608, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:-0x2
+TEST_RR_OP(add, x12, x10, x11, 0x7ffffe, 0x800000, -0x2, x1, 276, x2)
+
+inst_84:
+// rs1_val == 4194304, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:-0x201
+TEST_RR_OP(add, x12, x10, x11, 0x3ffdff, 0x400000, -0x201, x1, 280, x2)
+
+inst_85:
+// rs1_val == 2097152, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x8
+TEST_RR_OP(add, x12, x10, x11, 0x1ffff8, 0x200000, -0x8, x1, 284, x2)
+
+inst_86:
+// rs1_val == 1048576, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:-0x40000001
+TEST_RR_OP(add, x12, x10, x11, 0xc00fffff, 0x100000, -0x40000001, x1, 288, x2)
+
+inst_87:
+// rs1_val == 262144, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:-0x81
+TEST_RR_OP(add, x12, x10, x11, 0x3ff7f, 0x40000, -0x81, x1, 292, x2)
+
+inst_88:
+// rs1_val == 131072, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:-0x40000001
+TEST_RR_OP(add, x12, x10, x11, 0xc001ffff, 0x20000, -0x40000001, x1, 296, x2)
+
+inst_89:
+// rs1_val == 32768, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x1000000
+TEST_RR_OP(add, x12, x10, x11, 0x1008000, 0x8000, 0x1000000, x1, 300, x2)
+
+inst_90:
+// rs1_val == 16384, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x40000000
+TEST_RR_OP(add, x12, x10, x11, 0xc0004000, 0x4000, -0x40000000, x1, 304, x2)
+
+inst_91:
+// rs1_val == 8192, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x40000
+TEST_RR_OP(add, x12, x10, x11, 0x42000, 0x2000, 0x40000, x1, 308, x2)
+
+inst_92:
+// rs1_val == 4096, rs2_val == -1431655766
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaabaaa, 0x1000, -0x55555556, x1, 312, x2)
+
+inst_93:
+// rs1_val == 1024, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:-0x8000001
+TEST_RR_OP(add, x12, x10, x11, 0xf80003ff, 0x400, -0x8000001, x1, 316, x2)
+
+inst_94:
+// rs1_val == 512, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x1
+TEST_RR_OP(add, x12, x10, x11, 0x201, 0x200, 0x1, x1, 320, x2)
+
+inst_95:
+// rs1_val == 256, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:-0x10001
+TEST_RR_OP(add, x12, x10, x11, 0xffff00ff, 0x100, -0x10001, x1, 324, x2)
+
+inst_96:
+// rs1_val == 8, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x80001
+TEST_RR_OP(add, x12, x10, x11, 0xfff80007, 0x8, -0x80001, x1, 328, x2)
+
+inst_97:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x16a0a, 0xb505, 0xb505, x1, 332, x2)
+
+inst_98:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x2, 0xb505, -0xb503, x1, 336, x2)
+
+inst_99:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6c, 0xb505, 0x66666667, x1, 340, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x3333e839, 0xb505, 0x33333334, x1, 344, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xb50b, 0xb505, 0x6, x1, 348, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fb0, 0xb505, -0x55555555, x1, 352, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5b, 0xb505, 0x55555556, x1, 356, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0xb505, 0x4, x1, 360, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x16a08, 0xb505, 0xb503, x1, 364, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xb505, 0xb505, 0x0, x1, 368, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0xb505, 0x66666665, x1, 372, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0xb505, 0x33333332, x1, 376, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0xb505, 0x55555554, x1, 380, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0xb505, 0x2, x1, 384, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x16a09, 0xb505, 0xb504, x1, 388, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x1, 0xb505, -0xb504, x1, 392, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6b, 0xb505, 0x66666666, x1, 396, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x3333e838, 0xb505, 0x33333333, x1, 400, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xb50a, 0xb505, 0x5, x1, 404, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5faf, 0xb505, -0x55555556, x1, 408, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5a, 0xb505, 0x55555555, x1, 412, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0xb505, 0x3, x1, 416, x2)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x2, -0xb503, 0xb505, x1, 420, x2)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xfffe95fa, -0xb503, -0xb503, x1, 424, x2)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6665b164, -0xb503, 0x66666667, x1, 428, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33327e31, -0xb503, 0x33333334, x1, 432, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b03, -0xb503, 0x6, x1, 436, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a8, -0xb503, -0x55555555, x1, 440, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x5554a053, -0xb503, 0x55555556, x1, 444, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b01, -0xb503, 0x4, x1, 448, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x0, -0xb503, 0xb503, x1, 452, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 456, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x6665b162, -0xb503, 0x66666665, x1, 460, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2f, -0xb503, 0x33333332, x1, 464, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x5554a051, -0xb503, 0x55555554, x1, 468, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xffff4aff, -0xb503, 0x2, x1, 472, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x1, -0xb503, 0xb504, x1, 476, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xfffe95f9, -0xb503, -0xb504, x1, 480, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x6665b163, -0xb503, 0x66666666, x1, 484, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33327e30, -0xb503, 0x33333333, x1, 488, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b02, -0xb503, 0x5, x1, 492, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a7, -0xb503, -0x55555556, x1, 496, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x5554a052, -0xb503, 0x55555555, x1, 500, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b00, -0xb503, 0x3, x1, 504, x2)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6c, 0x66666667, 0xb505, x1, 508, x2)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x6665b164, 0x66666667, -0xb503, x1, 512, x2)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xccccccce, 0x66666667, 0x66666667, x1, 516, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x9999999b, 0x66666667, 0x33333334, x1, 520, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x6666666d, 0x66666667, 0x6, x1, 524, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x11111112, 0x66666667, -0x55555555, x1, 528, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbd, 0x66666667, 0x55555556, x1, 532, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x66666667, 0x4, x1, 536, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0x66666667, 0xb503, x1, 540, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 544, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccc, 0x66666667, 0x66666665, x1, 548, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x66666667, 0x33333332, x1, 552, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x66666667, 0x55555554, x1, 556, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x66666667, 0x2, x1, 560, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6b, 0x66666667, 0xb504, x1, 564, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x6665b163, 0x66666667, -0xb504, x1, 568, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccd, 0x66666667, 0x66666666, x1, 572, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x9999999a, 0x66666667, 0x33333333, x1, 576, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x6666666c, 0x66666667, 0x5, x1, 580, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x11111111, 0x66666667, -0x55555556, x1, 584, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbc, 0x66666667, 0x55555555, x1, 588, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x66666667, 0x3, x1, 592, x2)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x3333e839, 0x33333334, 0xb505, x1, 596, x2)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x33327e31, 0x33333334, -0xb503, x1, 600, x2)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x9999999b, 0x33333334, 0x66666667, x1, 604, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x66666668, 0x33333334, 0x33333334, x1, 608, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x3333333a, 0x33333334, 0x6, x1, 612, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddf, 0x33333334, -0x55555555, x1, 616, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x8888888a, 0x33333334, 0x55555556, x1, 620, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x33333334, 0x4, x1, 624, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0x33333334, 0xb503, x1, 628, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 632, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x33333334, 0x66666665, x1, 636, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x66666666, 0x33333334, 0x33333332, x1, 640, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x33333334, 0x55555554, x1, 644, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x33333334, 0x2, x1, 648, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x3333e838, 0x33333334, 0xb504, x1, 652, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x33327e30, 0x33333334, -0xb504, x1, 656, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x9999999a, 0x33333334, 0x66666666, x1, 660, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x33333334, 0x33333333, x1, 664, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x33333339, 0x33333334, 0x5, x1, 668, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xddddddde, 0x33333334, -0x55555556, x1, 672, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x88888889, 0x33333334, 0x55555555, x1, 676, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x33333334, 0x3, x1, 680, x2)
+
+inst_185:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb50b, 0x6, 0xb505, x1, 684, x2)
+
+inst_186:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b03, 0x6, -0xb503, x1, 688, x2)
+
+inst_187:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6666666d, 0x6, 0x66666667, x1, 692, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x3333333a, 0x6, 0x33333334, x1, 696, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xc, 0x6, 0x6, x1, 700, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab1, 0x6, -0x55555555, x1, 704, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x5555555c, 0x6, 0x55555556, x1, 708, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xa, 0x6, 0x4, x1, 712, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0x6, 0xb503, x1, 716, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x6, 0x6, 0x0, x1, 720, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x6, 0x66666665, x1, 724, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x6, 0x33333332, x1, 728, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x6, 0x55555554, x1, 732, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x8, 0x6, 0x2, x1, 736, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb50a, 0x6, 0xb504, x1, 740, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b02, 0x6, -0xb504, x1, 744, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x6666666c, 0x6, 0x66666666, x1, 748, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333339, 0x6, 0x33333333, x1, 752, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xb, 0x6, 0x5, x1, 756, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab0, 0x6, -0x55555556, x1, 760, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x5555555b, 0x6, 0x55555555, x1, 764, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x9, 0x6, 0x3, x1, 768, x2)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fb0, -0x55555555, 0xb505, x1, 772, x2)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a8, -0x55555555, -0xb503, x1, 776, x2)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x11111112, -0x55555555, 0x66666667, x1, 780, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddf, -0x55555555, 0x33333334, x1, 784, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab1, -0x55555555, 0x6, x1, 788, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555556, -0x55555555, -0x55555555, x1, 792, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x1, -0x55555555, 0x55555556, x1, 796, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x1, 800, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fae, -0x55555555, 0xb503, x1, 804, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 808, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x11111110, -0x55555555, 0x66666665, x1, 812, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddd, -0x55555555, 0x33333332, x1, 816, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x1, 820, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaad, -0x55555555, 0x2, x1, 824, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5faf, -0x55555555, 0xb504, x1, 828, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a7, -0x55555555, -0xb504, x1, 832, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x11111111, -0x55555555, 0x66666666, x1, 836, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0xddddddde, -0x55555555, 0x33333333, x1, 840, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab0, -0x55555555, 0x5, x1, 844, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55555555, -0x55555555, -0x55555556, x1, 848, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x0, -0x55555555, 0x55555555, x1, 852, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaae, -0x55555555, 0x3, x1, 856, x2)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5b, 0x55555556, 0xb505, x1, 860, x2)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x5554a053, 0x55555556, -0xb503, x1, 864, x2)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbd, 0x55555556, 0x66666667, x1, 868, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x8888888a, 0x55555556, 0x33333334, x1, 872, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x5555555c, 0x55555556, 0x6, x1, 876, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x1, 0x55555556, -0x55555555, x1, 880, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaac, 0x55555556, 0x55555556, x1, 884, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x55555556, 0x4, x1, 888, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0x55555556, 0xb503, x1, 892, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 896, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x55555556, 0x66666665, x1, 900, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x55555556, 0x33333332, x1, 904, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaa, 0x55555556, 0x55555554, x1, 908, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x55555556, 0x2, x1, 912, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5a, 0x55555556, 0xb504, x1, 916, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x5554a052, 0x55555556, -0xb504, x1, 920, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbc, 0x55555556, 0x66666666, x1, 924, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x88888889, 0x55555556, 0x33333333, x1, 928, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x5555555b, 0x55555556, 0x5, x1, 932, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x0, 0x55555556, -0x55555556, x1, 936, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaab, 0x55555556, 0x55555555, x1, 940, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x55555556, 0x3, x1, 944, x2)
+
+inst_251:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0x4, 0xb505, x1, 948, x2)
+
+inst_252:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b01, 0x4, -0xb503, x1, 952, x2)
+
+inst_253:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x4, 0x66666667, x1, 956, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x4, 0x33333334, x1, 960, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xa, 0x4, 0x6, x1, 964, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x1, 968, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x4, 0x55555556, x1, 972, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x8, 0x4, 0x4, x1, 976, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0x4, 0xb503, x1, 980, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x4, 0x4, 0x0, x1, 984, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x4, 0x66666665, x1, 988, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x4, 0x33333332, x1, 992, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x4, 0x55555554, x1, 996, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x6, 0x4, 0x2, x1, 1000, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0x4, 0xb504, x1, 1004, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b00, 0x4, -0xb504, x1, 1008, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x4, 0x66666666, x1, 1012, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x4, 0x33333333, x1, 1016, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x9, 0x4, 0x5, x1, 1020, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x1, 1024, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x4, 0x55555555, x1, 1028, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x7, 0x4, 0x3, x1, 1032, x2)
+
+inst_273:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x16a08, 0xb503, 0xb505, x1, 1036, x2)
+
+inst_274:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x0, 0xb503, -0xb503, x1, 1040, x2)
+
+inst_275:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0xb503, 0x66666667, x1, 1044, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0xb503, 0x33333334, x1, 1048, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0xb503, 0x6, x1, 1052, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fae, 0xb503, -0x55555555, x1, 1056, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0xb503, 0x55555556, x1, 1060, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0xb503, 0x4, x1, 1064, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x16a06, 0xb503, 0xb503, x1, 1068, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 1072, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66671b68, 0xb503, 0x66666665, x1, 1076, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x3333e835, 0xb503, 0x33333332, x1, 1080, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55560a57, 0xb503, 0x55555554, x1, 1084, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xb505, 0xb503, 0x2, x1, 1088, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x16a07, 0xb503, 0xb504, x1, 1092, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, 0xb503, -0xb504, x1, 1096, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66671b69, 0xb503, 0x66666666, x1, 1100, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x3333e836, 0xb503, 0x33333333, x1, 1104, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0xb503, 0x5, x1, 1108, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fad, 0xb503, -0x55555556, x1, 1112, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55560a58, 0xb503, 0x55555555, x1, 1116, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xb506, 0xb503, 0x3, x1, 1120, x2)
+
+inst_295:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb505, 0x0, 0xb505, x1, 1124, x2)
+
+inst_296:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afd, 0x0, -0xb503, x1, 1128, x2)
+
+inst_297:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x0, 0x66666667, x1, 1132, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33333334, 0x0, 0x33333334, x1, 1136, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x6, 0x0, 0x6, x1, 1140, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x1, 1144, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55555556, 0x0, 0x55555556, x1, 1148, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x4, 0x0, 0x4, x1, 1152, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb503, 0x0, 0xb503, x1, 1156, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1160, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66666665, 0x0, 0x66666665, x1, 1164, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333332, 0x0, 0x33333332, x1, 1168, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55555554, 0x0, 0x55555554, x1, 1172, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x2, 0x0, 0x2, x1, 1176, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb504, 0x0, 0xb504, x1, 1180, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afc, 0x0, -0xb504, x1, 1184, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66666666, 0x0, 0x66666666, x1, 1188, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333333, 0x0, 0x33333333, x1, 1192, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x5, 0x0, 0x5, x1, 1196, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x1, 1200, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555555, 0x0, 0x55555555, x1, 1204, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x3, 0x0, 0x3, x1, 1208, x2)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0x66666665, 0xb505, x1, 1212, x2)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x6665b162, 0x66666665, -0xb503, x1, 1216, x2)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccc, 0x66666665, 0x66666667, x1, 1220, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x66666665, 0x33333334, x1, 1224, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x66666665, 0x6, x1, 1228, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x11111110, 0x66666665, -0x55555555, x1, 1232, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x66666665, 0x55555556, x1, 1236, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x66666665, 0x4, x1, 1240, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x66671b68, 0x66666665, 0xb503, x1, 1244, x2)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1248, x2)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x99999998, 0x33333333, 0x66666665, x1, 1252, x2)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x66666665, 0x33333333, 0x33333332, x1, 1256, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x88888887, 0x33333333, 0x55555554, x1, 1260, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x33333335, 0x33333333, 0x2, x1, 1264, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0x33333333, 0xb504, x1, 1268, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2f, 0x33333333, -0xb504, x1, 1272, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x33333333, 0x66666666, x1, 1276, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x66666666, 0x33333333, 0x33333333, x1, 1280, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x33333333, 0x5, x1, 1284, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddd, 0x33333333, -0x55555556, x1, 1288, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x33333333, 0x55555555, x1, 1292, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x33333333, 0x3, x1, 1296, x2)
+
+inst_339:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb50a, 0x5, 0xb505, x1, 1300, x2)
+
+inst_340:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b02, 0x5, -0xb503, x1, 1304, x2)
+
+inst_341:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6666666c, 0x5, 0x66666667, x1, 1308, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33333339, 0x5, 0x33333334, x1, 1312, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xb, 0x5, 0x6, x1, 1316, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab0, 0x5, -0x55555555, x1, 1320, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x5555555b, 0x5, 0x55555556, x1, 1324, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x9, 0x5, 0x4, x1, 1328, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0x5, 0xb503, x1, 1332, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x5, 0x5, 0x0, x1, 1336, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x5, 0x66666665, x1, 1340, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x5, 0x33333332, x1, 1344, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x5, 0x55555554, x1, 1348, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x7, 0x5, 0x2, x1, 1352, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0x5, 0xb504, x1, 1356, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b01, 0x5, -0xb504, x1, 1360, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x5, 0x66666666, x1, 1364, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x5, 0x33333333, x1, 1368, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xa, 0x5, 0x5, x1, 1372, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x1, 1376, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x5, 0x55555555, x1, 1380, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x8, 0x5, 0x3, x1, 1384, x2)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5faf, -0x55555556, 0xb505, x1, 1388, x2)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a7, -0x55555556, -0xb503, x1, 1392, x2)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x11111111, -0x55555556, 0x66666667, x1, 1396, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0xddddddde, -0x55555556, 0x33333334, x1, 1400, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaab0, -0x55555556, 0x6, x1, 1404, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555555, -0x55555556, -0x55555555, x1, 1408, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x0, -0x55555556, 0x55555556, x1, 1412, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x1, 1416, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fad, -0x55555556, 0xb503, x1, 1420, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1424, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x1111110f, -0x55555556, 0x66666665, x1, 1428, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddc, -0x55555556, 0x33333332, x1, 1432, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x1, 1436, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaac, -0x55555556, 0x2, x1, 1440, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fae, -0x55555556, 0xb504, x1, 1444, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a6, -0x55555556, -0xb504, x1, 1448, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x11111110, -0x55555556, 0x66666666, x1, 1452, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddd, -0x55555556, 0x33333333, x1, 1456, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1460, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55555554, -0x55555556, -0x55555556, x1, 1464, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x1, 1468, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaad, -0x55555556, 0x3, x1, 1472, x2)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5a, 0x55555555, 0xb505, x1, 1476, x2)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x5554a052, 0x55555555, -0xb503, x1, 1480, x2)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbc, 0x55555555, 0x66666667, x1, 1484, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x88888889, 0x55555555, 0x33333334, x1, 1488, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x5555555b, 0x55555555, 0x6, x1, 1492, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x0, 0x55555555, -0x55555555, x1, 1496, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaab, 0x55555555, 0x55555556, x1, 1500, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x55555555, 0x4, x1, 1504, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x55560a58, 0x55555555, 0xb503, x1, 1508, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1512, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbba, 0x55555555, 0x66666665, x1, 1516, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x88888887, 0x55555555, 0x33333332, x1, 1520, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaa9, 0x55555555, 0x55555554, x1, 1524, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x55555557, 0x55555555, 0x2, x1, 1528, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0x55555555, 0xb504, x1, 1532, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x5554a051, 0x55555555, -0xb504, x1, 1536, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x55555555, 0x66666666, x1, 1540, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x55555555, 0x33333333, x1, 1544, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x55555555, 0x5, x1, 1548, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x1, 1552, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaa, 0x55555555, 0x55555555, x1, 1556, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x55555555, 0x3, x1, 1560, x2)
+
+inst_405:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0x3, 0xb505, x1, 1564, x2)
+
+inst_406:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b00, 0x3, -0xb503, x1, 1568, x2)
+
+inst_407:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x3, 0x66666667, x1, 1572, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x3, 0x33333334, x1, 1576, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x9, 0x3, 0x6, x1, 1580, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaae, 0x3, -0x55555555, x1, 1584, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x3, 0x55555556, x1, 1588, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x7, 0x3, 0x4, x1, 1592, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb506, 0x3, 0xb503, x1, 1596, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x3, 0x3, 0x0, x1, 1600, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66666668, 0x3, 0x66666665, x1, 1604, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333335, 0x3, 0x33333332, x1, 1608, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55555557, 0x3, 0x55555554, x1, 1612, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x5, 0x3, 0x2, x1, 1616, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0x3, 0xb504, x1, 1620, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4aff, 0x3, -0xb504, x1, 1624, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x3, 0x66666666, x1, 1628, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x3, 0x33333333, x1, 1632, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x8, 0x3, 0x5, x1, 1636, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaad, 0x3, -0x55555556, x1, 1640, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x3, 0x55555555, x1, 1644, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x6, 0x3, 0x3, x1, 1648, x2)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1652, x2)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xccccccca, 0x66666665, 0x66666665, x1, 1656, x2)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x99999997, 0x66666665, 0x33333332, x1, 1660, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbb9, 0x66666665, 0x55555554, x1, 1664, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x66666665, 0x2, x1, 1668, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x66671b69, 0x66666665, 0xb504, x1, 1672, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x6665b161, 0x66666665, -0xb504, x1, 1676, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccb, 0x66666665, 0x66666666, x1, 1680, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x99999998, 0x66666665, 0x33333333, x1, 1684, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x66666665, 0x5, x1, 1688, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x1111110f, 0x66666665, -0x55555556, x1, 1692, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbba, 0x66666665, 0x55555555, x1, 1696, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x66666668, 0x66666665, 0x3, x1, 1700, x2)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0x33333332, 0xb505, x1, 1704, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2f, 0x33333332, -0xb503, x1, 1708, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x33333332, 0x66666667, x1, 1712, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x66666666, 0x33333332, 0x33333334, x1, 1716, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x33333338, 0x33333332, 0x6, x1, 1720, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddd, 0x33333332, -0x55555555, x1, 1724, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x33333332, 0x55555556, x1, 1728, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x33333332, 0x4, x1, 1732, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x3333e835, 0x33333332, 0xb503, x1, 1736, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1740, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x99999997, 0x33333332, 0x66666665, x1, 1744, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x66666664, 0x33333332, 0x33333332, x1, 1748, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x88888886, 0x33333332, 0x55555554, x1, 1752, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x33333334, 0x33333332, 0x2, x1, 1756, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x3333e836, 0x33333332, 0xb504, x1, 1760, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2e, 0x33333332, -0xb504, x1, 1764, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x99999998, 0x33333332, 0x66666666, x1, 1768, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x66666665, 0x33333332, 0x33333333, x1, 1772, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x33333332, 0x5, x1, 1776, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xdddddddc, 0x33333332, -0x55555556, x1, 1780, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x88888887, 0x33333332, 0x55555555, x1, 1784, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x33333335, 0x33333332, 0x3, x1, 1788, x2)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0x55555554, 0xb505, x1, 1792, x2)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x5554a051, 0x55555554, -0xb503, x1, 1796, x2)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x55555554, 0x66666667, x1, 1800, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x88888888, 0x55555554, 0x33333334, x1, 1804, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x5555555a, 0x55555554, 0x6, x1, 1808, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x1, 1812, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaaa, 0x55555554, 0x55555556, x1, 1816, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x55555554, 0x4, x1, 1820, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x55560a57, 0x55555554, 0xb503, x1, 1824, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1828, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbb9, 0x55555554, 0x66666665, x1, 1832, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x88888886, 0x55555554, 0x33333332, x1, 1836, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaa8, 0x55555554, 0x55555554, x1, 1840, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x55555556, 0x55555554, 0x2, x1, 1844, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x55560a58, 0x55555554, 0xb504, x1, 1848, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x5554a050, 0x55555554, -0xb504, x1, 1852, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbba, 0x55555554, 0x66666666, x1, 1856, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x88888887, 0x55555554, 0x33333333, x1, 1860, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x55555559, 0x55555554, 0x5, x1, 1864, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x1, 1868, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaa9, 0x55555554, 0x55555555, x1, 1872, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x55555557, 0x55555554, 0x3, x1, 1876, x2)
+
+inst_484:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0x2, 0xb505, x1, 1880, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffff4aff, 0x2, -0xb503, x1, 1884, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x2, 0x66666667, x1, 1888, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33333336, 0x2, 0x33333334, x1, 1892, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x8, 0x2, 0x6, x1, 1896, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaad, 0x2, -0x55555555, x1, 1900, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55555558, 0x2, 0x55555556, x1, 1904, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x6, 0x2, 0x4, x1, 1908, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xb505, 0x2, 0xb503, x1, 1912, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x2, 0x2, 0x0, x1, 1916, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x2, 0x66666665, x1, 1920, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33333334, 0x2, 0x33333332, x1, 1924, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55555556, 0x2, 0x55555554, x1, 1928, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x4, 0x2, 0x2, x1, 1932, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xb506, 0x2, 0xb504, x1, 1936, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afe, 0x2, -0xb504, x1, 1940, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66666668, 0x2, 0x66666666, x1, 1944, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33333335, 0x2, 0x33333333, x1, 1948, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x7, 0x2, 0x5, x1, 1952, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaaaaaac, 0x2, -0x55555556, x1, 1956, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55555557, 0x2, 0x55555555, x1, 1960, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x5, 0x2, 0x3, x1, 1964, x2)
+
+inst_506:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x16a09, 0xb504, 0xb505, x1, 1968, x2)
+
+inst_507:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x1, 0xb504, -0xb503, x1, 1972, x2)
+
+inst_508:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6b, 0xb504, 0x66666667, x1, 1976, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x3333e838, 0xb504, 0x33333334, x1, 1980, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xb50a, 0xb504, 0x6, x1, 1984, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5faf, 0xb504, -0x55555555, x1, 1988, x2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x55560a5a, 0xb504, 0x55555556, x1, 1992, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xb508, 0xb504, 0x4, x1, 1996, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x16a07, 0xb504, 0xb503, x1, 2000, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xb504, 0xb504, 0x0, x1, 2004, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x66671b69, 0xb504, 0x66666665, x1, 2008, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x3333e836, 0xb504, 0x33333332, x1, 2012, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x55560a58, 0xb504, 0x55555554, x1, 2016, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xb506, 0xb504, 0x2, x1, 2020, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x16a08, 0xb504, 0xb504, x1, 2024, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x0, 0xb504, -0xb504, x1, 2028, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0xb504, 0x66666666, x1, 2032, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x3333e837, 0xb504, 0x33333333, x1, 2036, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xb509, 0xb504, 0x5, x1, 2040, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaab5fae, 0xb504, -0x55555556, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_526:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x55560a59, 0xb504, 0x55555555, x1, 0, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xb507, 0xb504, 0x3, x1, 4, x2)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x1, -0xb504, 0xb505, x1, 8, x2)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xfffe95f9, -0xb504, -0xb503, x1, 12, x2)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x6665b163, -0xb504, 0x66666667, x1, 16, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x33327e30, -0xb504, 0x33333334, x1, 20, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b02, -0xb504, 0x6, x1, 24, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a7, -0xb504, -0x55555555, x1, 28, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x5554a052, -0xb504, 0x55555556, x1, 32, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b00, -0xb504, 0x4, x1, 36, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 40, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 44, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0x6665b161, -0xb504, 0x66666665, x1, 48, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2e, -0xb504, 0x33333332, x1, 52, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0x5554a050, -0xb504, 0x55555554, x1, 56, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0xffff4afe, -0xb504, 0x2, x1, 60, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x0, -0xb504, 0xb504, x1, 64, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0xfffe95f8, -0xb504, -0xb504, x1, 68, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0x6665b162, -0xb504, 0x66666666, x1, 72, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x33327e2f, -0xb504, 0x33333333, x1, 76, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0xffff4b01, -0xb504, 0x5, x1, 80, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xaaa9f5a6, -0xb504, -0x55555556, x1, 84, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x5554a051, -0xb504, 0x55555555, x1, 88, x2)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0xffff4aff, -0xb504, 0x3, x1, 92, x2)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6b, 0x66666666, 0xb505, x1, 96, x2)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x6665b163, 0x66666666, -0xb503, x1, 100, x2)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccd, 0x66666666, 0x66666667, x1, 104, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x9999999a, 0x66666666, 0x33333334, x1, 108, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x6666666c, 0x66666666, 0x6, x1, 112, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0x11111111, 0x66666666, -0x55555555, x1, 116, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbc, 0x66666666, 0x55555556, x1, 120, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x6666666a, 0x66666666, 0x4, x1, 124, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x66671b69, 0x66666666, 0xb503, x1, 128, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(add, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 132, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccb, 0x66666666, 0x66666665, x1, 136, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(add, x12, x10, x11, 0x99999998, 0x66666666, 0x33333332, x1, 140, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbba, 0x66666666, 0x55555554, x1, 144, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(add, x12, x10, x11, 0x66666668, 0x66666666, 0x2, x1, 148, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x66671b6a, 0x66666666, 0xb504, x1, 152, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(add, x12, x10, x11, 0x6665b162, 0x66666666, -0xb504, x1, 156, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(add, x12, x10, x11, 0xcccccccc, 0x66666666, 0x66666666, x1, 160, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(add, x12, x10, x11, 0x99999999, 0x66666666, 0x33333333, x1, 164, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(add, x12, x10, x11, 0x6666666b, 0x66666666, 0x5, x1, 168, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x11111110, 0x66666666, -0x55555556, x1, 172, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xbbbbbbbb, 0x66666666, 0x55555555, x1, 176, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(add, x12, x10, x11, 0x66666669, 0x66666666, 0x3, x1, 180, x2)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(add, x12, x10, x11, 0x3333e838, 0x33333333, 0xb505, x1, 184, x2)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x33327e30, 0x33333333, -0xb503, x1, 188, x2)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(add, x12, x10, x11, 0x9999999a, 0x33333333, 0x66666667, x1, 192, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(add, x12, x10, x11, 0x66666667, 0x33333333, 0x33333334, x1, 196, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(add, x12, x10, x11, 0x33333339, 0x33333333, 0x6, x1, 200, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(add, x12, x10, x11, 0xddddddde, 0x33333333, -0x55555555, x1, 204, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(add, x12, x10, x11, 0x88888889, 0x33333333, 0x55555556, x1, 208, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(add, x12, x10, x11, 0x33333337, 0x33333333, 0x4, x1, 212, x2)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(add, x12, x10, x11, 0x3333e836, 0x33333333, 0xb503, x1, 216, x2)
+
+inst_581:
+// rs2_val == -536870913, rs1_val == 32, rs1_val > 0 and rs2_val < 0
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:-0x20000001
+TEST_RR_OP(add, x12, x10, x11, 0xe000001f, 0x20, -0x20000001, x1, 220, x2)
+
+inst_582:
+// rs2_val == -268435457, rs1_val == 4
+// opcode: add ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x10000001
+TEST_RR_OP(add, x12, x10, x11, 0xf0000003, 0x4, -0x10000001, x1, 224, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x10_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 57*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S
new file mode 100644
index 000000000..87ce8463e
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S
@@ -0,0 +1,2891 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the addi instruction of the RISC-V E extension for the addi covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",addi)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x6, rd==x5, imm_val == (-2**(12-1)), rs1_val > 0 and imm_val < 0, rs1_val != imm_val, imm_val == -2048, rs1_val == 536870912
+// opcode: addi ; op1:x6; dest:x5; op1val:0x20000000;  immval:-0x800
+TEST_IMM_OP( addi, x5, x6, 0x1ffff800, 0x20000000, -0x800, x4, 0, x8)
+
+inst_1:
+// rs1 == rd, rs1==x10, rd==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: addi ; op1:x10; dest:x10; op1val:0x7fffffff;  immval:0x667
+TEST_IMM_OP( addi, x10, x10, 0x80000666, 0x7fffffff, 0x667, x4, 4, x8)
+
+inst_2:
+// rs1==x14, rd==x0, rs1_val == -1073741825, imm_val == 64, rs1_val < 0 and imm_val > 0
+// opcode: addi ; op1:x14; dest:x0; op1val:-0x40000001;  immval:0x40
+TEST_IMM_OP( addi, x0, x14, 0, -0x40000001, 0x40, x4, 8, x8)
+
+inst_3:
+// rs1==x2, rd==x11, rs1_val == -536870913, 
+// opcode: addi ; op1:x2; dest:x11; op1val:-0x20000001;  immval:0x556
+TEST_IMM_OP( addi, x11, x2, 0xe0000555, -0x20000001, 0x556, x4, 12, x8)
+
+inst_4:
+// rs1==x15, rd==x6, rs1_val == -268435457, imm_val == -17, rs1_val < 0 and imm_val < 0
+// opcode: addi ; op1:x15; dest:x6; op1val:-0x10000001;  immval:-0x11
+TEST_IMM_OP( addi, x6, x15, 0xefffffee, -0x10000001, -0x11, x4, 16, x8)
+
+inst_5:
+// rs1==x13, rd==x1, rs1_val == -134217729, 
+// opcode: addi ; op1:x13; dest:x1; op1val:-0x8000001;  immval:-0x4
+TEST_IMM_OP( addi, x1, x13, 0xf7fffffb, -0x8000001, -0x4, x4, 20, x8)
+
+inst_6:
+// rs1==x5, rd==x3, rs1_val == -67108865, imm_val == 0
+// opcode: addi ; op1:x5; dest:x3; op1val:-0x4000001;  immval:0x0
+TEST_IMM_OP( addi, x3, x5, 0xfbffffff, -0x4000001, 0x0, x4, 24, x8)
+
+inst_7:
+// rs1==x0, rd==x15, rs1_val == -33554433, 
+// opcode: addi ; op1:x0; dest:x15; op1val:0x0;  immval:0x0
+TEST_IMM_OP( addi, x15, x0, 0x0, 0x0, 0x0, x4, 28, x8)
+
+inst_8:
+// rs1==x12, rd==x7, rs1_val == -16777217, imm_val == 4
+// opcode: addi ; op1:x12; dest:x7; op1val:-0x1000001;  immval:0x4
+TEST_IMM_OP( addi, x7, x12, 0xff000003, -0x1000001, 0x4, x4, 32, x8)
+RVTEST_SIGBASE( x5,signature_x5_0)
+
+inst_9:
+// rs1==x1, rd==x8, rs1_val == -8388609, 
+// opcode: addi ; op1:x1; dest:x8; op1val:-0x800001;  immval:0x40
+TEST_IMM_OP( addi, x8, x1, 0xff80003f, -0x800001, 0x40, x5, 0, x6)
+
+inst_10:
+// rs1==x11, rd==x4, rs1_val == -4194305, imm_val == -5
+// opcode: addi ; op1:x11; dest:x4; op1val:-0x400001;  immval:-0x5
+TEST_IMM_OP( addi, x4, x11, 0xffbffffa, -0x400001, -0x5, x5, 4, x6)
+
+inst_11:
+// rs1==x7, rd==x13, rs1_val == -2097153, imm_val == 1365
+// opcode: addi ; op1:x7; dest:x13; op1val:-0x200001;  immval:0x555
+TEST_IMM_OP( addi, x13, x7, 0xffe00554, -0x200001, 0x555, x5, 8, x6)
+
+inst_12:
+// rs1==x3, rd==x14, rs1_val == -1048577, 
+// opcode: addi ; op1:x3; dest:x14; op1val:-0x100001;  immval:-0x11
+TEST_IMM_OP( addi, x14, x3, 0xffefffee, -0x100001, -0x11, x5, 12, x6)
+
+inst_13:
+// rs1==x4, rd==x2, rs1_val == -524289, 
+// opcode: addi ; op1:x4; dest:x2; op1val:-0x80001;  immval:-0xa
+TEST_IMM_OP( addi, x2, x4, 0xfff7fff5, -0x80001, -0xa, x5, 16, x6)
+
+inst_14:
+// rs1==x8, rd==x9, rs1_val == -262145, imm_val == -513
+// opcode: addi ; op1:x8; dest:x9; op1val:-0x40001;  immval:-0x201
+TEST_IMM_OP( addi, x9, x8, 0xfffbfdfe, -0x40001, -0x201, x5, 20, x6)
+
+inst_15:
+// rs1==x9, rd==x12, rs1_val == -131073, 
+// opcode: addi ; op1:x9; dest:x12; op1val:-0x20001;  immval:0x3
+TEST_IMM_OP( addi, x12, x9, 0xfffe0002, -0x20001, 0x3, x5, 24, x6)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x10001;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xffff0004, -0x10001, 0x5, x5, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xffff8005, -0x8001, 0x6, x1, 0, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x4001;  immval:-0x8
+TEST_IMM_OP( addi, x11, x10, 0xffffbff7, -0x4001, -0x8, x1, 4, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x2001;  immval:-0x6
+TEST_IMM_OP( addi, x11, x10, 0xffffdff9, -0x2001, -0x6, x1, 8, x2)
+
+inst_20:
+// rs1_val == -4097, imm_val == -33
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x21
+TEST_IMM_OP( addi, x11, x10, 0xffffefde, -0x1001, -0x21, x1, 12, x2)
+
+inst_21:
+// rs1_val == -2049, imm_val == 512
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x801;  immval:0x200
+TEST_IMM_OP( addi, x11, x10, 0xfffff9ff, -0x801, 0x200, x1, 16, x2)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x401;  immval:-0x6
+TEST_IMM_OP( addi, x11, x10, 0xfffffbf9, -0x401, -0x6, x1, 20, x2)
+
+inst_23:
+// rs1_val == -513, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x201;  immval:-0x21
+TEST_IMM_OP( addi, x11, x10, 0xfffffdde, -0x201, -0x21, x1, 24, x2)
+
+inst_24:
+// rs1_val == -257, imm_val == 2
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x101;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xffffff01, -0x101, 0x2, x1, 28, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x81;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffac, -0x81, 0x2d, x1, 32, x2)
+
+inst_26:
+// rs1_val == -65, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x41;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffeb, -0x41, 0x2c, x1, 36, x2)
+
+inst_27:
+// rs1_val == -33, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x21;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xffffffe1, -0x21, 0x2, x1, 40, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x11;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xfffffff5, -0x11, 0x6, x1, 44, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x9;  immval:-0x5
+TEST_IMM_OP( addi, x11, x10, 0xfffffff2, -0x9, -0x5, x1, 48, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x5;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x27, -0x5, 0x2c, x1, 52, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x3;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd1, -0x3, -0x2c, x1, 56, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x2;  immval:-0xa
+TEST_IMM_OP( addi, x11, x10, 0xfffffff4, -0x2, -0xa, x1, 60, x2)
+
+inst_33:
+// imm_val == 2047, imm_val == (2**(12-1)-1)
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x7ff
+TEST_IMM_OP( addi, x11, x10, 0xbd02, 0xb503, 0x7ff, x1, 64, x2)
+
+inst_34:
+// imm_val == -1025, rs1_val == 1024
+// opcode: addi ; op1:x10; dest:x11; op1val:0x400;  immval:-0x401
+TEST_IMM_OP( addi, x11, x10, 0xffffffff, 0x400, -0x401, x1, 68, x2)
+
+inst_35:
+// imm_val == -257, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x101
+TEST_IMM_OP( addi, x11, x10, 0xffffeefe, -0x1001, -0x101, x1, 72, x2)
+
+inst_36:
+// imm_val == -129, rs1_val == 134217728
+// opcode: addi ; op1:x10; dest:x11; op1val:0x8000000;  immval:-0x81
+TEST_IMM_OP( addi, x11, x10, 0x7ffff7f, 0x8000000, -0x81, x1, 76, x2)
+
+inst_37:
+// imm_val == -65, rs1_val == 4
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x41
+TEST_IMM_OP( addi, x11, x10, 0xffffffc3, 0x4, -0x41, x1, 80, x2)
+
+inst_38:
+// imm_val == -9, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x41;  immval:-0x9
+TEST_IMM_OP( addi, x11, x10, 0xffffffb6, -0x41, -0x9, x1, 84, x2)
+
+inst_39:
+// imm_val == -3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x3
+TEST_IMM_OP( addi, x11, x10, 0x3, 0x6, -0x3, x1, 88, x2)
+
+inst_40:
+// imm_val == -2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x5;  immval:-0x2
+TEST_IMM_OP( addi, x11, x10, 0xfffffff9, -0x5, -0x2, x1, 92, x2)
+
+inst_41:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x80000556, -0x80000000, 0x556, x1, 96, x2)
+
+inst_42:
+// rs1_val == 1073741824, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x40000000;  immval:-0x400
+TEST_IMM_OP( addi, x11, x10, 0x3ffffc00, 0x40000000, -0x400, x1, 100, x2)
+
+inst_43:
+// rs1_val == 268435456, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x10000000, 0x10000000, 0x0, x1, 104, x2)
+
+inst_44:
+// rs1_val == 67108864, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4000000;  immval:-0xa
+TEST_IMM_OP( addi, x11, x10, 0x3fffff6, 0x4000000, -0xa, x1, 108, x2)
+
+inst_45:
+// rs1_val == 33554432, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x200002e, 0x2000000, 0x2e, x1, 112, x2)
+
+inst_46:
+// rs1_val == 16777216, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x1000000;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x1000667, 0x1000000, 0x667, x1, 116, x2)
+
+inst_47:
+// rs1_val == 8388608, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x800000;  immval:-0x41
+TEST_IMM_OP( addi, x11, x10, 0x7fffbf, 0x800000, -0x41, x1, 120, x2)
+
+inst_48:
+// rs1_val == 4194304, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x400000;  immval:-0x101
+TEST_IMM_OP( addi, x11, x10, 0x3ffeff, 0x400000, -0x101, x1, 124, x2)
+
+inst_49:
+// rs1_val == 2097152, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x200000;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x200555, 0x200000, 0x555, x1, 128, x2)
+
+inst_50:
+// rs1_val == 1048576, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x100000;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x100000, 0x100000, 0x0, x1, 132, x2)
+
+inst_51:
+// rs1_val == 524288, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x80000;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x80005, 0x80000, 0x5, x1, 136, x2)
+
+inst_52:
+// rs1_val == 262144, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x40000;  immval:0x3ff
+TEST_IMM_OP( addi, x11, x10, 0x403ff, 0x40000, 0x3ff, x1, 140, x2)
+
+inst_53:
+// rs1_val == 131072, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x20000;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x20000, 0x20000, 0x0, x1, 144, x2)
+
+inst_54:
+// rs1_val == 65536, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x10000;  immval:0x200
+TEST_IMM_OP( addi, x11, x10, 0x10200, 0x10000, 0x200, x1, 148, x2)
+
+inst_55:
+// rs1_val == 32768, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x8000;  immval:-0x7
+TEST_IMM_OP( addi, x11, x10, 0x7ff9, 0x8000, -0x7, x1, 152, x2)
+
+inst_56:
+// rs1_val == 16384, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4000;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x4333, 0x4000, 0x333, x1, 156, x2)
+
+inst_57:
+// rs1_val == 8192, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2000;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x2555, 0x2000, 0x555, x1, 160, x2)
+
+inst_58:
+// rs1_val == 4096, imm_val == -1366
+// opcode: addi ; op1:x10; dest:x11; op1val:0x1000;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xaaa, 0x1000, -0x556, x1, 164, x2)
+
+inst_59:
+// rs1_val == 2048, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x800;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xe65, 0x800, 0x665, x1, 168, x2)
+
+inst_60:
+// rs1_val == 512, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x200;  immval:-0x41
+TEST_IMM_OP( addi, x11, x10, 0x1bf, 0x200, -0x41, x1, 172, x2)
+
+inst_61:
+// rs1_val == 256, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x100;  immval:0x3ff
+TEST_IMM_OP( addi, x11, x10, 0x4ff, 0x100, 0x3ff, x1, 176, x2)
+
+inst_62:
+// rs1_val == 128, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x80;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x6e6, 0x80, 0x666, x1, 180, x2)
+
+inst_63:
+// rs1_val == 64, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x40;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x373, 0x40, 0x333, x1, 184, x2)
+
+inst_64:
+// rs1_val == 32, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x20;  immval:0x7ff
+TEST_IMM_OP( addi, x11, x10, 0x81f, 0x20, 0x7ff, x1, 188, x2)
+
+inst_65:
+// rs1_val == 16, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x10;  immval:0x200
+TEST_IMM_OP( addi, x11, x10, 0x210, 0x10, 0x200, x1, 192, x2)
+
+inst_66:
+// rs1_val == 8, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x8;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x8, 0x0, x1, 196, x2)
+
+inst_67:
+// rs1_val == 2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x3
+TEST_IMM_OP( addi, x11, x10, 0xffffffff, 0x2, -0x3, x1, 200, x2)
+
+inst_68:
+// rs1_val == 1, imm_val == 256
+// opcode: addi ; op1:x10; dest:x11; op1val:0x1;  immval:0x100
+TEST_IMM_OP( addi, x11, x10, 0x101, 0x1, 0x100, x1, 204, x2)
+
+inst_69:
+// imm_val == 1024, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x41;  immval:0x400
+TEST_IMM_OP( addi, x11, x10, 0x3bf, -0x41, 0x400, x1, 208, x2)
+
+inst_70:
+// imm_val == 128, rs1_val == 0
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x80
+TEST_IMM_OP( addi, x11, x10, 0x80, 0x0, 0x80, x1, 212, x2)
+
+inst_71:
+// imm_val == 32, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x20
+TEST_IMM_OP( addi, x11, x10, 0x20, 0x0, 0x20, x1, 216, x2)
+
+inst_72:
+// imm_val == 16, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x8000;  immval:0x10
+TEST_IMM_OP( addi, x11, x10, 0x8010, 0x8000, 0x10, x1, 220, x2)
+
+inst_73:
+// imm_val == 8, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x8;  immval:0x8
+TEST_IMM_OP( addi, x11, x10, 0x0, -0x8, 0x8, x1, 224, x2)
+
+inst_74:
+// imm_val == 1, rs1_val == 1431655765
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x1
+TEST_IMM_OP( addi, x11, x10, 0x55555556, 0x55555555, 0x1, x1, 228, x2)
+
+inst_75:
+// rs1_val==46341 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xb533, 0xb505, 0x2e, x1, 232, x2)
+
+inst_76:
+// rs1_val==46341 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb4d9, 0xb505, -0x2c, x1, 236, x2)
+
+inst_77:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xbb6c, 0xb505, 0x667, x1, 240, x2)
+
+inst_78:
+// rs1_val==46341 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xb839, 0xb505, 0x334, x1, 244, x2)
+
+inst_79:
+// rs1_val==46341 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xb50b, 0xb505, 0x6, x1, 248, x2)
+
+inst_80:
+// rs1_val==46341 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xafb0, 0xb505, -0x555, x1, 252, x2)
+
+inst_81:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xba5b, 0xb505, 0x556, x1, 256, x2)
+
+inst_82:
+// rs1_val==46341 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xb509, 0xb505, 0x4, x1, 260, x2)
+
+inst_83:
+// rs1_val==46341 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb531, 0xb505, 0x2c, x1, 264, x2)
+
+inst_84:
+// rs1_val==46341 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xb505, 0xb505, 0x0, x1, 268, x2)
+
+inst_85:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xbb6a, 0xb505, 0x665, x1, 272, x2)
+
+inst_86:
+// rs1_val==46341 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xb837, 0xb505, 0x332, x1, 276, x2)
+
+inst_87:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xba59, 0xb505, 0x554, x1, 280, x2)
+
+inst_88:
+// rs1_val==46341 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xb507, 0xb505, 0x2, x1, 284, x2)
+
+inst_89:
+// rs1_val==46341 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb532, 0xb505, 0x2d, x1, 288, x2)
+
+inst_90:
+// rs1_val==46341 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb4d8, 0xb505, -0x2d, x1, 292, x2)
+
+inst_91:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xbb6b, 0xb505, 0x666, x1, 296, x2)
+
+inst_92:
+// rs1_val==46341 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xb838, 0xb505, 0x333, x1, 300, x2)
+
+inst_93:
+// rs1_val==46341 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xb50a, 0xb505, 0x5, x1, 304, x2)
+
+inst_94:
+// rs1_val==46341 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xafaf, 0xb505, -0x556, x1, 308, x2)
+
+inst_95:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xba5a, 0xb505, 0x555, x1, 312, x2)
+
+inst_96:
+// rs1_val==46341 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xb508, 0xb505, 0x3, x1, 316, x2)
+
+inst_97:
+// rs1_val==-46339 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xffff4b2b, -0xb503, 0x2e, x1, 320, x2)
+
+inst_98:
+// rs1_val==-46339 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffff4ad1, -0xb503, -0x2c, x1, 324, x2)
+
+inst_99:
+// rs1_val==-46339 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xffff5164, -0xb503, 0x667, x1, 328, x2)
+
+inst_100:
+// rs1_val==-46339 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xffff4e31, -0xb503, 0x334, x1, 332, x2)
+
+inst_101:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xffff4b03, -0xb503, 0x6, x1, 336, x2)
+
+inst_102:
+// rs1_val==-46339 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xffff45a8, -0xb503, -0x555, x1, 340, x2)
+
+inst_103:
+// rs1_val==-46339 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xffff5053, -0xb503, 0x556, x1, 344, x2)
+
+inst_104:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xffff4b01, -0xb503, 0x4, x1, 348, x2)
+
+inst_105:
+// rs1_val==-46339 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffff4b29, -0xb503, 0x2c, x1, 352, x2)
+
+inst_106:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xffff4afd, -0xb503, 0x0, x1, 356, x2)
+
+inst_107:
+// rs1_val==-46339 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xffff5162, -0xb503, 0x665, x1, 360, x2)
+
+inst_108:
+// rs1_val==-46339 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xffff4e2f, -0xb503, 0x332, x1, 364, x2)
+
+inst_109:
+// rs1_val==-46339 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xffff5051, -0xb503, 0x554, x1, 368, x2)
+
+inst_110:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xffff4aff, -0xb503, 0x2, x1, 372, x2)
+
+inst_111:
+// rs1_val==-46339 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffff4b2a, -0xb503, 0x2d, x1, 376, x2)
+
+inst_112:
+// rs1_val==-46339 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffff4ad0, -0xb503, -0x2d, x1, 380, x2)
+
+inst_113:
+// rs1_val==-46339 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xffff5163, -0xb503, 0x666, x1, 384, x2)
+
+inst_114:
+// rs1_val==-46339 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xffff4e30, -0xb503, 0x333, x1, 388, x2)
+
+inst_115:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xffff4b02, -0xb503, 0x5, x1, 392, x2)
+
+inst_116:
+// rs1_val==-46339 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xffff45a7, -0xb503, -0x556, x1, 396, x2)
+
+inst_117:
+// rs1_val==-46339 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xffff5052, -0xb503, 0x555, x1, 400, x2)
+
+inst_118:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xffff4b00, -0xb503, 0x3, x1, 404, x2)
+
+inst_119:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x66666695, 0x66666667, 0x2e, x1, 408, x2)
+
+inst_120:
+// rs1_val==1717986919 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x6666663b, 0x66666667, -0x2c, x1, 412, x2)
+
+inst_121:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66666cce, 0x66666667, 0x667, x1, 416, x2)
+
+inst_122:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x6666699b, 0x66666667, 0x334, x1, 420, x2)
+
+inst_123:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x6666666d, 0x66666667, 0x6, x1, 424, x2)
+
+inst_124:
+// rs1_val==1717986919 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666112, 0x66666667, -0x555, x1, 428, x2)
+
+inst_125:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x66666bbd, 0x66666667, 0x556, x1, 432, x2)
+
+inst_126:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x6666666b, 0x66666667, 0x4, x1, 436, x2)
+
+inst_127:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x66666693, 0x66666667, 0x2c, x1, 440, x2)
+
+inst_128:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x66666667, 0x66666667, 0x0, x1, 444, x2)
+
+inst_129:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x66666ccc, 0x66666667, 0x665, x1, 448, x2)
+
+inst_130:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x66666999, 0x66666667, 0x332, x1, 452, x2)
+
+inst_131:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x66666bbb, 0x66666667, 0x554, x1, 456, x2)
+
+inst_132:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x66666669, 0x66666667, 0x2, x1, 460, x2)
+
+inst_133:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x66666694, 0x66666667, 0x2d, x1, 464, x2)
+
+inst_134:
+// rs1_val==1717986919 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x6666663a, 0x66666667, -0x2d, x1, 468, x2)
+
+inst_135:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66666ccd, 0x66666667, 0x666, x1, 472, x2)
+
+inst_136:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x6666699a, 0x66666667, 0x333, x1, 476, x2)
+
+inst_137:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x6666666c, 0x66666667, 0x5, x1, 480, x2)
+
+inst_138:
+// rs1_val==1717986919 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x66666111, 0x66666667, -0x556, x1, 484, x2)
+
+inst_139:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666bbc, 0x66666667, 0x555, x1, 488, x2)
+
+inst_140:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x6666666a, 0x66666667, 0x3, x1, 492, x2)
+
+inst_141:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x33333362, 0x33333334, 0x2e, x1, 496, x2)
+
+inst_142:
+// rs1_val==858993460 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x33333308, 0x33333334, -0x2c, x1, 500, x2)
+
+inst_143:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x3333399b, 0x33333334, 0x667, x1, 504, x2)
+
+inst_144:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x33333668, 0x33333334, 0x334, x1, 508, x2)
+
+inst_145:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x3333333a, 0x33333334, 0x6, x1, 512, x2)
+
+inst_146:
+// rs1_val==858993460 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x33332ddf, 0x33333334, -0x555, x1, 516, x2)
+
+inst_147:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x3333388a, 0x33333334, 0x556, x1, 520, x2)
+
+inst_148:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x33333338, 0x33333334, 0x4, x1, 524, x2)
+
+inst_149:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x33333360, 0x33333334, 0x2c, x1, 528, x2)
+
+inst_150:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x33333334, 0x33333334, 0x0, x1, 532, x2)
+
+inst_151:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x33333999, 0x33333334, 0x665, x1, 536, x2)
+
+inst_152:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x33333666, 0x33333334, 0x332, x1, 540, x2)
+
+inst_153:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x33333888, 0x33333334, 0x554, x1, 544, x2)
+
+inst_154:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x33333336, 0x33333334, 0x2, x1, 548, x2)
+
+inst_155:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33333361, 0x33333334, 0x2d, x1, 552, x2)
+
+inst_156:
+// rs1_val==858993460 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33333307, 0x33333334, -0x2d, x1, 556, x2)
+
+inst_157:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x3333399a, 0x33333334, 0x666, x1, 560, x2)
+
+inst_158:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x33333667, 0x33333334, 0x333, x1, 564, x2)
+
+inst_159:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x33333339, 0x33333334, 0x5, x1, 568, x2)
+
+inst_160:
+// rs1_val==858993460 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x33332dde, 0x33333334, -0x556, x1, 572, x2)
+
+inst_161:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x33333889, 0x33333334, 0x555, x1, 576, x2)
+
+inst_162:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x33333337, 0x33333334, 0x3, x1, 580, x2)
+
+inst_163:
+// rs1_val==6 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x34, 0x6, 0x2e, x1, 584, x2)
+
+inst_164:
+// rs1_val==6 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffda, 0x6, -0x2c, x1, 588, x2)
+
+inst_165:
+// rs1_val==6 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66d, 0x6, 0x667, x1, 592, x2)
+
+inst_166:
+// rs1_val==6 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x33a, 0x6, 0x334, x1, 596, x2)
+
+inst_167:
+// rs1_val==6 and imm_val==6, rs1_val == imm_val
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xc, 0x6, 0x6, x1, 600, x2)
+
+inst_168:
+// rs1_val==6 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffab1, 0x6, -0x555, x1, 604, x2)
+
+inst_169:
+// rs1_val==6 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55c, 0x6, 0x556, x1, 608, x2)
+
+inst_170:
+// rs1_val==6 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xa, 0x6, 0x4, x1, 612, x2)
+
+inst_171:
+// rs1_val==6 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x32, 0x6, 0x2c, x1, 616, x2)
+
+inst_172:
+// rs1_val==6 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x6, 0x6, 0x0, x1, 620, x2)
+
+inst_173:
+// rs1_val==6 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x66b, 0x6, 0x665, x1, 624, x2)
+
+inst_174:
+// rs1_val==6 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x338, 0x6, 0x332, x1, 628, x2)
+
+inst_175:
+// rs1_val==6 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x55a, 0x6, 0x554, x1, 632, x2)
+
+inst_176:
+// rs1_val==6 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x6, 0x2, x1, 636, x2)
+
+inst_177:
+// rs1_val==6 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33, 0x6, 0x2d, x1, 640, x2)
+
+inst_178:
+// rs1_val==6 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd9, 0x6, -0x2d, x1, 644, x2)
+
+inst_179:
+// rs1_val==6 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66c, 0x6, 0x666, x1, 648, x2)
+
+inst_180:
+// rs1_val==6 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x339, 0x6, 0x333, x1, 652, x2)
+
+inst_181:
+// rs1_val==6 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xb, 0x6, 0x5, x1, 656, x2)
+
+inst_182:
+// rs1_val==6 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffab0, 0x6, -0x556, x1, 660, x2)
+
+inst_183:
+// rs1_val==6 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x55b, 0x6, 0x555, x1, 664, x2)
+
+inst_184:
+// rs1_val==6 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x9, 0x6, 0x3, x1, 668, x2)
+
+inst_185:
+// rs1_val==-1431655765 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad9, -0x55555555, 0x2e, x1, 672, x2)
+
+inst_186:
+// rs1_val==-1431655765 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaa7f, -0x55555555, -0x2c, x1, 676, x2)
+
+inst_187:
+// rs1_val==-1431655765 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xaaaab112, -0x55555555, 0x667, x1, 680, x2)
+
+inst_188:
+// rs1_val==-1431655765 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaddf, -0x55555555, 0x334, x1, 684, x2)
+
+inst_189:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaab1, -0x55555555, 0x6, x1, 688, x2)
+
+inst_190:
+// rs1_val==-1431655765 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xaaaaa556, -0x55555555, -0x555, x1, 692, x2)
+
+inst_191:
+// rs1_val==-1431655765 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xaaaab001, -0x55555555, 0x556, x1, 696, x2)
+
+inst_192:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaaf, -0x55555555, 0x4, x1, 700, x2)
+
+inst_193:
+// rs1_val==-1431655765 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad7, -0x55555555, 0x2c, x1, 704, x2)
+
+inst_194:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaab, -0x55555555, 0x0, x1, 708, x2)
+
+inst_195:
+// rs1_val==-1431655765 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xaaaab110, -0x55555555, 0x665, x1, 712, x2)
+
+inst_196:
+// rs1_val==-1431655765 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaddd, -0x55555555, 0x332, x1, 716, x2)
+
+inst_197:
+// rs1_val==-1431655765 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xaaaaafff, -0x55555555, 0x554, x1, 720, x2)
+
+inst_198:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaad, -0x55555555, 0x2, x1, 724, x2)
+
+inst_199:
+// rs1_val==-1431655765 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad8, -0x55555555, 0x2d, x1, 728, x2)
+
+inst_200:
+// rs1_val==-1431655765 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaa7e, -0x55555555, -0x2d, x1, 732, x2)
+
+inst_201:
+// rs1_val==-1431655765 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xaaaab111, -0x55555555, 0x666, x1, 736, x2)
+
+inst_202:
+// rs1_val==-1431655765 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xaaaaadde, -0x55555555, 0x333, x1, 740, x2)
+
+inst_203:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaab0, -0x55555555, 0x5, x1, 744, x2)
+
+inst_204:
+// rs1_val==-1431655765 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xaaaaa555, -0x55555555, -0x556, x1, 748, x2)
+
+inst_205:
+// rs1_val==-1431655765 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xaaaab000, -0x55555555, 0x555, x1, 752, x2)
+
+inst_206:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaae, -0x55555555, 0x3, x1, 756, x2)
+
+inst_207:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x55555584, 0x55555556, 0x2e, x1, 760, x2)
+
+inst_208:
+// rs1_val==1431655766 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x5555552a, 0x55555556, -0x2c, x1, 764, x2)
+
+inst_209:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x55555bbd, 0x55555556, 0x667, x1, 768, x2)
+
+inst_210:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x5555588a, 0x55555556, 0x334, x1, 772, x2)
+
+inst_211:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x5555555c, 0x55555556, 0x6, x1, 776, x2)
+
+inst_212:
+// rs1_val==1431655766 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x55555001, 0x55555556, -0x555, x1, 780, x2)
+
+inst_213:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55555aac, 0x55555556, 0x556, x1, 784, x2)
+
+inst_214:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x5555555a, 0x55555556, 0x4, x1, 788, x2)
+
+inst_215:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x55555582, 0x55555556, 0x2c, x1, 792, x2)
+
+inst_216:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x55555556, 0x55555556, 0x0, x1, 796, x2)
+
+inst_217:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x55555bbb, 0x55555556, 0x665, x1, 800, x2)
+
+inst_218:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x55555888, 0x55555556, 0x332, x1, 804, x2)
+
+inst_219:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x55555aaa, 0x55555556, 0x554, x1, 808, x2)
+
+inst_220:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x55555558, 0x55555556, 0x2, x1, 812, x2)
+
+inst_221:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555583, 0x55555556, 0x2d, x1, 816, x2)
+
+inst_222:
+// rs1_val==1431655766 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555529, 0x55555556, -0x2d, x1, 820, x2)
+
+inst_223:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x55555bbc, 0x55555556, 0x666, x1, 824, x2)
+
+inst_224:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x55555889, 0x55555556, 0x333, x1, 828, x2)
+
+inst_225:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x5555555b, 0x55555556, 0x5, x1, 832, x2)
+
+inst_226:
+// rs1_val==1431655766 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x55555000, 0x55555556, -0x556, x1, 836, x2)
+
+inst_227:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x55555aab, 0x55555556, 0x555, x1, 840, x2)
+
+inst_228:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x55555559, 0x55555556, 0x3, x1, 844, x2)
+
+inst_229:
+// rs1_val==4 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x32, 0x4, 0x2e, x1, 848, x2)
+
+inst_230:
+// rs1_val==4 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd8, 0x4, -0x2c, x1, 852, x2)
+
+inst_231:
+// rs1_val==4 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66b, 0x4, 0x667, x1, 856, x2)
+
+inst_232:
+// rs1_val==4 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x338, 0x4, 0x334, x1, 860, x2)
+
+inst_233:
+// rs1_val==4 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xa, 0x4, 0x6, x1, 864, x2)
+
+inst_234:
+// rs1_val==4 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffaaf, 0x4, -0x555, x1, 868, x2)
+
+inst_235:
+// rs1_val==4 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55a, 0x4, 0x556, x1, 872, x2)
+
+inst_236:
+// rs1_val==4 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x4, 0x4, x1, 876, x2)
+
+inst_237:
+// rs1_val==4 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x30, 0x4, 0x2c, x1, 880, x2)
+
+inst_238:
+// rs1_val==4 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x4, 0x4, 0x0, x1, 884, x2)
+
+inst_239:
+// rs1_val==4 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x669, 0x4, 0x665, x1, 888, x2)
+
+inst_240:
+// rs1_val==4 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x336, 0x4, 0x332, x1, 892, x2)
+
+inst_241:
+// rs1_val==4 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x558, 0x4, 0x554, x1, 896, x2)
+
+inst_242:
+// rs1_val==4 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x6, 0x4, 0x2, x1, 900, x2)
+
+inst_243:
+// rs1_val==4 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x31, 0x4, 0x2d, x1, 904, x2)
+
+inst_244:
+// rs1_val==4 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd7, 0x4, -0x2d, x1, 908, x2)
+
+inst_245:
+// rs1_val==4 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66a, 0x4, 0x666, x1, 912, x2)
+
+inst_246:
+// rs1_val==4 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x337, 0x4, 0x333, x1, 916, x2)
+
+inst_247:
+// rs1_val==4 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x9, 0x4, 0x5, x1, 920, x2)
+
+inst_248:
+// rs1_val==4 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffaae, 0x4, -0x556, x1, 924, x2)
+
+inst_249:
+// rs1_val==4 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x559, 0x4, 0x555, x1, 928, x2)
+
+inst_250:
+// rs1_val==4 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x7, 0x4, 0x3, x1, 932, x2)
+
+inst_251:
+// rs1_val==46339 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xb531, 0xb503, 0x2e, x1, 936, x2)
+
+inst_252:
+// rs1_val==46339 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb4d7, 0xb503, -0x2c, x1, 940, x2)
+
+inst_253:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xbb6a, 0xb503, 0x667, x1, 944, x2)
+
+inst_254:
+// rs1_val==46339 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xb837, 0xb503, 0x334, x1, 948, x2)
+
+inst_255:
+// rs1_val==46339 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xb509, 0xb503, 0x6, x1, 952, x2)
+
+inst_256:
+// rs1_val==46339 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xafae, 0xb503, -0x555, x1, 956, x2)
+
+inst_257:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xba59, 0xb503, 0x556, x1, 960, x2)
+
+inst_258:
+// rs1_val==46339 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xb507, 0xb503, 0x4, x1, 964, x2)
+
+inst_259:
+// rs1_val==46339 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb52f, 0xb503, 0x2c, x1, 968, x2)
+
+inst_260:
+// rs1_val==46339 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xb503, 0xb503, 0x0, x1, 972, x2)
+
+inst_261:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xbb68, 0xb503, 0x665, x1, 976, x2)
+
+inst_262:
+// rs1_val==46339 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xb835, 0xb503, 0x332, x1, 980, x2)
+
+inst_263:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xba57, 0xb503, 0x554, x1, 984, x2)
+
+inst_264:
+// rs1_val==46339 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xb505, 0xb503, 0x2, x1, 988, x2)
+
+inst_265:
+// rs1_val==46339 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb530, 0xb503, 0x2d, x1, 992, x2)
+
+inst_266:
+// rs1_val==46339 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb4d6, 0xb503, -0x2d, x1, 996, x2)
+
+inst_267:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xbb69, 0xb503, 0x666, x1, 1000, x2)
+
+inst_268:
+// rs1_val==46339 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xb836, 0xb503, 0x333, x1, 1004, x2)
+
+inst_269:
+// rs1_val==46339 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xb508, 0xb503, 0x5, x1, 1008, x2)
+
+inst_270:
+// rs1_val==46339 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xafad, 0xb503, -0x556, x1, 1012, x2)
+
+inst_271:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xba58, 0xb503, 0x555, x1, 1016, x2)
+
+inst_272:
+// rs1_val==46339 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xb506, 0xb503, 0x3, x1, 1020, x2)
+
+inst_273:
+// rs1_val==0 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x2e, 0x0, 0x2e, x1, 1024, x2)
+
+inst_274:
+// rs1_val==0 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd4, 0x0, -0x2c, x1, 1028, x2)
+
+inst_275:
+// rs1_val==0 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x667, 0x0, 0x667, x1, 1032, x2)
+
+inst_276:
+// rs1_val==0 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x334, 0x0, 0x334, x1, 1036, x2)
+
+inst_277:
+// rs1_val==0 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x6, 0x0, 0x6, x1, 1040, x2)
+
+inst_278:
+// rs1_val==0 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffaab, 0x0, -0x555, x1, 1044, x2)
+
+inst_279:
+// rs1_val==0 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x556, 0x0, 0x556, x1, 1048, x2)
+
+inst_280:
+// rs1_val==0 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x4, 0x0, 0x4, x1, 1052, x2)
+
+inst_281:
+// rs1_val==0 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x2c, 0x0, 0x2c, x1, 1056, x2)
+
+inst_282:
+// rs1_val==0 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x0, 0x0, 0x0, x1, 1060, x2)
+
+inst_283:
+// rs1_val==0 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x665, 0x0, 0x665, x1, 1064, x2)
+
+inst_284:
+// rs1_val==0 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x332, 0x0, 0x332, x1, 1068, x2)
+
+inst_285:
+// rs1_val==0 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x554, 0x0, 0x554, x1, 1072, x2)
+
+inst_286:
+// rs1_val==0 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x2, 0x0, 0x2, x1, 1076, x2)
+
+inst_287:
+// rs1_val==0 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x2d, 0x0, 0x2d, x1, 1080, x2)
+
+inst_288:
+// rs1_val==0 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd3, 0x0, -0x2d, x1, 1084, x2)
+
+inst_289:
+// rs1_val==0 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x666, 0x0, 0x666, x1, 1088, x2)
+
+inst_290:
+// rs1_val==0 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x333, 0x0, 0x333, x1, 1092, x2)
+
+inst_291:
+// rs1_val==0 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x5, 0x0, 0x5, x1, 1096, x2)
+
+inst_292:
+// rs1_val==0 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffaaa, 0x0, -0x556, x1, 1100, x2)
+
+inst_293:
+// rs1_val==0 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x555, 0x0, 0x555, x1, 1104, x2)
+
+inst_294:
+// rs1_val==0 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x3, 0x0, 0x3, x1, 1108, x2)
+
+inst_295:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x66666693, 0x66666665, 0x2e, x1, 1112, x2)
+
+inst_296:
+// rs1_val==1717986917 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x66666639, 0x66666665, -0x2c, x1, 1116, x2)
+
+inst_297:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66666ccc, 0x66666665, 0x667, x1, 1120, x2)
+
+inst_298:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x66666999, 0x66666665, 0x334, x1, 1124, x2)
+
+inst_299:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x6666666b, 0x66666665, 0x6, x1, 1128, x2)
+
+inst_300:
+// rs1_val==1717986917 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666110, 0x66666665, -0x555, x1, 1132, x2)
+
+inst_301:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x66666bbb, 0x66666665, 0x556, x1, 1136, x2)
+
+inst_302:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x66666669, 0x66666665, 0x4, x1, 1140, x2)
+
+inst_303:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x66666691, 0x66666665, 0x2c, x1, 1144, x2)
+
+inst_304:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x66666665, 0x66666665, 0x0, x1, 1148, x2)
+
+inst_305:
+// rs1_val==-1431655766 and imm_val==-1365, rs1_val == -1431655766
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xaaaaa555, -0x55555556, -0x555, x1, 1152, x2)
+
+inst_306:
+// rs1_val==-1431655766 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xaaaab000, -0x55555556, 0x556, x1, 1156, x2)
+
+inst_307:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaae, -0x55555556, 0x4, x1, 1160, x2)
+
+inst_308:
+// rs1_val==-1431655766 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad6, -0x55555556, 0x2c, x1, 1164, x2)
+
+inst_309:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1168, x2)
+
+inst_310:
+// rs1_val==-1431655766 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xaaaab10f, -0x55555556, 0x665, x1, 1172, x2)
+
+inst_311:
+// rs1_val==-1431655766 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaddc, -0x55555556, 0x332, x1, 1176, x2)
+
+inst_312:
+// rs1_val==-1431655766 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaffe, -0x55555556, 0x554, x1, 1180, x2)
+
+inst_313:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaac, -0x55555556, 0x2, x1, 1184, x2)
+
+inst_314:
+// rs1_val==-1431655766 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad7, -0x55555556, 0x2d, x1, 1188, x2)
+
+inst_315:
+// rs1_val==-1431655766 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaa7d, -0x55555556, -0x2d, x1, 1192, x2)
+
+inst_316:
+// rs1_val==-1431655766 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xaaaab110, -0x55555556, 0x666, x1, 1196, x2)
+
+inst_317:
+// rs1_val==-1431655766 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaddd, -0x55555556, 0x333, x1, 1200, x2)
+
+inst_318:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1204, x2)
+
+inst_319:
+// rs1_val==-1431655766 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xaaaaa554, -0x55555556, -0x556, x1, 1208, x2)
+
+inst_320:
+// rs1_val==-1431655766 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xaaaaafff, -0x55555556, 0x555, x1, 1212, x2)
+
+inst_321:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaaad, -0x55555556, 0x3, x1, 1216, x2)
+
+inst_322:
+// rs1_val==1431655765 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x55555583, 0x55555555, 0x2e, x1, 1220, x2)
+
+inst_323:
+// rs1_val==1431655765 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x55555529, 0x55555555, -0x2c, x1, 1224, x2)
+
+inst_324:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x55555bbc, 0x55555555, 0x667, x1, 1228, x2)
+
+inst_325:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x55555889, 0x55555555, 0x334, x1, 1232, x2)
+
+inst_326:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x5555555b, 0x55555555, 0x6, x1, 1236, x2)
+
+inst_327:
+// rs1_val==1431655765 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x55555000, 0x55555555, -0x555, x1, 1240, x2)
+
+inst_328:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55555aab, 0x55555555, 0x556, x1, 1244, x2)
+
+inst_329:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x55555559, 0x55555555, 0x4, x1, 1248, x2)
+
+inst_330:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x55555581, 0x55555555, 0x2c, x1, 1252, x2)
+
+inst_331:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x55555555, 0x55555555, 0x0, x1, 1256, x2)
+
+inst_332:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x55555bba, 0x55555555, 0x665, x1, 1260, x2)
+
+inst_333:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x55555887, 0x55555555, 0x332, x1, 1264, x2)
+
+inst_334:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x55555aa9, 0x55555555, 0x554, x1, 1268, x2)
+
+inst_335:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x55555557, 0x55555555, 0x2, x1, 1272, x2)
+
+inst_336:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555582, 0x55555555, 0x2d, x1, 1276, x2)
+
+inst_337:
+// rs1_val==1431655765 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555528, 0x55555555, -0x2d, x1, 1280, x2)
+
+inst_338:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x55555bbb, 0x55555555, 0x666, x1, 1284, x2)
+
+inst_339:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x55555888, 0x55555555, 0x333, x1, 1288, x2)
+
+inst_340:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x5555555a, 0x55555555, 0x5, x1, 1292, x2)
+
+inst_341:
+// rs1_val==1431655765 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x55554fff, 0x55555555, -0x556, x1, 1296, x2)
+
+inst_342:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x55555aaa, 0x55555555, 0x555, x1, 1300, x2)
+
+inst_343:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x55555558, 0x55555555, 0x3, x1, 1304, x2)
+
+inst_344:
+// rs1_val==3 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x31, 0x3, 0x2e, x1, 1308, x2)
+
+inst_345:
+// rs1_val==3 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd7, 0x3, -0x2c, x1, 1312, x2)
+
+inst_346:
+// rs1_val==3 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66a, 0x3, 0x667, x1, 1316, x2)
+
+inst_347:
+// rs1_val==3 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x337, 0x3, 0x334, x1, 1320, x2)
+
+inst_348:
+// rs1_val==3 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x9, 0x3, 0x6, x1, 1324, x2)
+
+inst_349:
+// rs1_val==3 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffaae, 0x3, -0x555, x1, 1328, x2)
+
+inst_350:
+// rs1_val==3 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x559, 0x3, 0x556, x1, 1332, x2)
+
+inst_351:
+// rs1_val==3 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x7, 0x3, 0x4, x1, 1336, x2)
+
+inst_352:
+// rs1_val==3 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x2f, 0x3, 0x2c, x1, 1340, x2)
+
+inst_353:
+// rs1_val==3 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x3, 0x3, 0x0, x1, 1344, x2)
+
+inst_354:
+// rs1_val==3 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x668, 0x3, 0x665, x1, 1348, x2)
+
+inst_355:
+// rs1_val==3 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x335, 0x3, 0x332, x1, 1352, x2)
+
+inst_356:
+// rs1_val==3 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x557, 0x3, 0x554, x1, 1356, x2)
+
+inst_357:
+// rs1_val==3 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x5, 0x3, 0x2, x1, 1360, x2)
+
+inst_358:
+// rs1_val==3 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x30, 0x3, 0x2d, x1, 1364, x2)
+
+inst_359:
+// rs1_val==3 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd6, 0x3, -0x2d, x1, 1368, x2)
+
+inst_360:
+// rs1_val==3 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x669, 0x3, 0x666, x1, 1372, x2)
+
+inst_361:
+// rs1_val==3 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x336, 0x3, 0x333, x1, 1376, x2)
+
+inst_362:
+// rs1_val==3 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x3, 0x5, x1, 1380, x2)
+
+inst_363:
+// rs1_val==3 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffaad, 0x3, -0x556, x1, 1384, x2)
+
+inst_364:
+// rs1_val==3 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x558, 0x3, 0x555, x1, 1388, x2)
+
+inst_365:
+// rs1_val==3 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x6, 0x3, 0x3, x1, 1392, x2)
+
+inst_366:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x66666cca, 0x66666665, 0x665, x1, 1396, x2)
+
+inst_367:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x66666997, 0x66666665, 0x332, x1, 1400, x2)
+
+inst_368:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x66666bb9, 0x66666665, 0x554, x1, 1404, x2)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x66666667, 0x66666665, 0x2, x1, 1408, x2)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x66666692, 0x66666665, 0x2d, x1, 1412, x2)
+
+inst_371:
+// rs1_val==1717986917 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x66666638, 0x66666665, -0x2d, x1, 1416, x2)
+
+inst_372:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66666ccb, 0x66666665, 0x666, x1, 1420, x2)
+
+inst_373:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x66666998, 0x66666665, 0x333, x1, 1424, x2)
+
+inst_374:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x6666666a, 0x66666665, 0x5, x1, 1428, x2)
+
+inst_375:
+// rs1_val==1717986917 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x6666610f, 0x66666665, -0x556, x1, 1432, x2)
+
+inst_376:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666bba, 0x66666665, 0x555, x1, 1436, x2)
+
+inst_377:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x66666668, 0x66666665, 0x3, x1, 1440, x2)
+
+inst_378:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x33333360, 0x33333332, 0x2e, x1, 1444, x2)
+
+inst_379:
+// rs1_val==858993458 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x33333306, 0x33333332, -0x2c, x1, 1448, x2)
+
+inst_380:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x33333999, 0x33333332, 0x667, x1, 1452, x2)
+
+inst_381:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x33333666, 0x33333332, 0x334, x1, 1456, x2)
+
+inst_382:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x33333338, 0x33333332, 0x6, x1, 1460, x2)
+
+inst_383:
+// rs1_val==858993458 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x33332ddd, 0x33333332, -0x555, x1, 1464, x2)
+
+inst_384:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x33333888, 0x33333332, 0x556, x1, 1468, x2)
+
+inst_385:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x33333336, 0x33333332, 0x4, x1, 1472, x2)
+
+inst_386:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x3333335e, 0x33333332, 0x2c, x1, 1476, x2)
+
+inst_387:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x33333332, 0x33333332, 0x0, x1, 1480, x2)
+
+inst_388:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x33333997, 0x33333332, 0x665, x1, 1484, x2)
+
+inst_389:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x33333664, 0x33333332, 0x332, x1, 1488, x2)
+
+inst_390:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x33333886, 0x33333332, 0x554, x1, 1492, x2)
+
+inst_391:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x33333334, 0x33333332, 0x2, x1, 1496, x2)
+
+inst_392:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x3333335f, 0x33333332, 0x2d, x1, 1500, x2)
+
+inst_393:
+// rs1_val==858993458 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33333305, 0x33333332, -0x2d, x1, 1504, x2)
+
+inst_394:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x33333998, 0x33333332, 0x666, x1, 1508, x2)
+
+inst_395:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x33333665, 0x33333332, 0x333, x1, 1512, x2)
+
+inst_396:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x33333337, 0x33333332, 0x5, x1, 1516, x2)
+
+inst_397:
+// rs1_val==858993458 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x33332ddc, 0x33333332, -0x556, x1, 1520, x2)
+
+inst_398:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x33333887, 0x33333332, 0x555, x1, 1524, x2)
+
+inst_399:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x33333335, 0x33333332, 0x3, x1, 1528, x2)
+
+inst_400:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x55555582, 0x55555554, 0x2e, x1, 1532, x2)
+
+inst_401:
+// rs1_val==1431655764 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x55555528, 0x55555554, -0x2c, x1, 1536, x2)
+
+inst_402:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x55555bbb, 0x55555554, 0x667, x1, 1540, x2)
+
+inst_403:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x55555888, 0x55555554, 0x334, x1, 1544, x2)
+
+inst_404:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x5555555a, 0x55555554, 0x6, x1, 1548, x2)
+
+inst_405:
+// rs1_val==1431655764 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x55554fff, 0x55555554, -0x555, x1, 1552, x2)
+
+inst_406:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55555aaa, 0x55555554, 0x556, x1, 1556, x2)
+
+inst_407:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x55555558, 0x55555554, 0x4, x1, 1560, x2)
+
+inst_408:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x55555580, 0x55555554, 0x2c, x1, 1564, x2)
+
+inst_409:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x55555554, 0x55555554, 0x0, x1, 1568, x2)
+
+inst_410:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x55555bb9, 0x55555554, 0x665, x1, 1572, x2)
+
+inst_411:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x55555886, 0x55555554, 0x332, x1, 1576, x2)
+
+inst_412:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x55555aa8, 0x55555554, 0x554, x1, 1580, x2)
+
+inst_413:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x55555556, 0x55555554, 0x2, x1, 1584, x2)
+
+inst_414:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555581, 0x55555554, 0x2d, x1, 1588, x2)
+
+inst_415:
+// rs1_val==1431655764 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x55555527, 0x55555554, -0x2d, x1, 1592, x2)
+
+inst_416:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x55555bba, 0x55555554, 0x666, x1, 1596, x2)
+
+inst_417:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x55555887, 0x55555554, 0x333, x1, 1600, x2)
+
+inst_418:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x55555559, 0x55555554, 0x5, x1, 1604, x2)
+
+inst_419:
+// rs1_val==1431655764 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x55554ffe, 0x55555554, -0x556, x1, 1608, x2)
+
+inst_420:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x55555aa9, 0x55555554, 0x555, x1, 1612, x2)
+
+inst_421:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x55555557, 0x55555554, 0x3, x1, 1616, x2)
+
+inst_422:
+// rs1_val==2 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x30, 0x2, 0x2e, x1, 1620, x2)
+
+inst_423:
+// rs1_val==2 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd6, 0x2, -0x2c, x1, 1624, x2)
+
+inst_424:
+// rs1_val==2 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x669, 0x2, 0x667, x1, 1628, x2)
+
+inst_425:
+// rs1_val==2 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x336, 0x2, 0x334, x1, 1632, x2)
+
+inst_426:
+// rs1_val==2 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x2, 0x6, x1, 1636, x2)
+
+inst_427:
+// rs1_val==2 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffaad, 0x2, -0x555, x1, 1640, x2)
+
+inst_428:
+// rs1_val==2 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x558, 0x2, 0x556, x1, 1644, x2)
+
+inst_429:
+// rs1_val==2 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x6, 0x2, 0x4, x1, 1648, x2)
+
+inst_430:
+// rs1_val==2 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x2e, 0x2, 0x2c, x1, 1652, x2)
+
+inst_431:
+// rs1_val==2 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x2, 0x2, 0x0, x1, 1656, x2)
+
+inst_432:
+// rs1_val==2 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x667, 0x2, 0x665, x1, 1660, x2)
+
+inst_433:
+// rs1_val==2 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x334, 0x2, 0x332, x1, 1664, x2)
+
+inst_434:
+// rs1_val==2 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x556, 0x2, 0x554, x1, 1668, x2)
+
+inst_435:
+// rs1_val==2 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x4, 0x2, 0x2, x1, 1672, x2)
+
+inst_436:
+// rs1_val==2 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x2f, 0x2, 0x2d, x1, 1676, x2)
+
+inst_437:
+// rs1_val==2 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd5, 0x2, -0x2d, x1, 1680, x2)
+
+inst_438:
+// rs1_val==2 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x668, 0x2, 0x666, x1, 1684, x2)
+
+inst_439:
+// rs1_val==2 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x335, 0x2, 0x333, x1, 1688, x2)
+
+inst_440:
+// rs1_val==2 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x7, 0x2, 0x5, x1, 1692, x2)
+
+inst_441:
+// rs1_val==2 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffaac, 0x2, -0x556, x1, 1696, x2)
+
+inst_442:
+// rs1_val==2 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x557, 0x2, 0x555, x1, 1700, x2)
+
+inst_443:
+// rs1_val==2 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x5, 0x2, 0x3, x1, 1704, x2)
+
+inst_444:
+// rs1_val==46340 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xb532, 0xb504, 0x2e, x1, 1708, x2)
+
+inst_445:
+// rs1_val==46340 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb4d8, 0xb504, -0x2c, x1, 1712, x2)
+
+inst_446:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xbb6b, 0xb504, 0x667, x1, 1716, x2)
+
+inst_447:
+// rs1_val==46340 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xb838, 0xb504, 0x334, x1, 1720, x2)
+
+inst_448:
+// rs1_val==46340 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xb50a, 0xb504, 0x6, x1, 1724, x2)
+
+inst_449:
+// rs1_val==46340 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xafaf, 0xb504, -0x555, x1, 1728, x2)
+
+inst_450:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xba5a, 0xb504, 0x556, x1, 1732, x2)
+
+inst_451:
+// rs1_val==46340 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xb508, 0xb504, 0x4, x1, 1736, x2)
+
+inst_452:
+// rs1_val==46340 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xb530, 0xb504, 0x2c, x1, 1740, x2)
+
+inst_453:
+// rs1_val==46340 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xb504, 0xb504, 0x0, x1, 1744, x2)
+
+inst_454:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xbb69, 0xb504, 0x665, x1, 1748, x2)
+
+inst_455:
+// rs1_val==46340 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xb836, 0xb504, 0x332, x1, 1752, x2)
+
+inst_456:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xba58, 0xb504, 0x554, x1, 1756, x2)
+
+inst_457:
+// rs1_val==46340 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xb506, 0xb504, 0x2, x1, 1760, x2)
+
+inst_458:
+// rs1_val==46340 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb531, 0xb504, 0x2d, x1, 1764, x2)
+
+inst_459:
+// rs1_val==46340 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xb4d7, 0xb504, -0x2d, x1, 1768, x2)
+
+inst_460:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xbb6a, 0xb504, 0x666, x1, 1772, x2)
+
+inst_461:
+// rs1_val==46340 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xb837, 0xb504, 0x333, x1, 1776, x2)
+
+inst_462:
+// rs1_val==46340 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xb509, 0xb504, 0x5, x1, 1780, x2)
+
+inst_463:
+// rs1_val==46340 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xafae, 0xb504, -0x556, x1, 1784, x2)
+
+inst_464:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xba59, 0xb504, 0x555, x1, 1788, x2)
+
+inst_465:
+// rs1_val==46340 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xb507, 0xb504, 0x3, x1, 1792, x2)
+
+inst_466:
+// rs1_val==-46340 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xffff4b2a, -0xb504, 0x2e, x1, 1796, x2)
+
+inst_467:
+// rs1_val==-46340 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffff4ad0, -0xb504, -0x2c, x1, 1800, x2)
+
+inst_468:
+// rs1_val==-46340 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xffff5163, -0xb504, 0x667, x1, 1804, x2)
+
+inst_469:
+// rs1_val==-46340 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xffff4e30, -0xb504, 0x334, x1, 1808, x2)
+
+inst_470:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xffff4b02, -0xb504, 0x6, x1, 1812, x2)
+
+inst_471:
+// rs1_val==-46340 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xffff45a7, -0xb504, -0x555, x1, 1816, x2)
+
+inst_472:
+// rs1_val==-46340 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0xffff5052, -0xb504, 0x556, x1, 1820, x2)
+
+inst_473:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0xffff4b00, -0xb504, 0x4, x1, 1824, x2)
+
+inst_474:
+// rs1_val==-46340 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffff4b28, -0xb504, 0x2c, x1, 1828, x2)
+
+inst_475:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xffff4afc, -0xb504, 0x0, x1, 1832, x2)
+
+inst_476:
+// rs1_val==-46340 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0xffff5161, -0xb504, 0x665, x1, 1836, x2)
+
+inst_477:
+// rs1_val==-46340 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0xffff4e2e, -0xb504, 0x332, x1, 1840, x2)
+
+inst_478:
+// rs1_val==-46340 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0xffff5050, -0xb504, 0x554, x1, 1844, x2)
+
+inst_479:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0xffff4afe, -0xb504, 0x2, x1, 1848, x2)
+
+inst_480:
+// rs1_val==-46340 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffff4b29, -0xb504, 0x2d, x1, 1852, x2)
+
+inst_481:
+// rs1_val==-46340 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffff4acf, -0xb504, -0x2d, x1, 1856, x2)
+
+inst_482:
+// rs1_val==-46340 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0xffff5162, -0xb504, 0x666, x1, 1860, x2)
+
+inst_483:
+// rs1_val==-46340 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0xffff4e2f, -0xb504, 0x333, x1, 1864, x2)
+
+inst_484:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xffff4b01, -0xb504, 0x5, x1, 1868, x2)
+
+inst_485:
+// rs1_val==-46340 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xffff45a6, -0xb504, -0x556, x1, 1872, x2)
+
+inst_486:
+// rs1_val==-46340 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0xffff5051, -0xb504, 0x555, x1, 1876, x2)
+
+inst_487:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0xffff4aff, -0xb504, 0x3, x1, 1880, x2)
+
+inst_488:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x66666694, 0x66666666, 0x2e, x1, 1884, x2)
+
+inst_489:
+// rs1_val==1717986918 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x6666663a, 0x66666666, -0x2c, x1, 1888, x2)
+
+inst_490:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66666ccd, 0x66666666, 0x667, x1, 1892, x2)
+
+inst_491:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x6666699a, 0x66666666, 0x334, x1, 1896, x2)
+
+inst_492:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x6666666c, 0x66666666, 0x6, x1, 1900, x2)
+
+inst_493:
+// rs1_val==1717986918 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666111, 0x66666666, -0x555, x1, 1904, x2)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x66666bbc, 0x66666666, 0x556, x1, 1908, x2)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x6666666a, 0x66666666, 0x4, x1, 1912, x2)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x66666692, 0x66666666, 0x2c, x1, 1916, x2)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x66666666, 0x66666666, 0x0, x1, 1920, x2)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x66666ccb, 0x66666666, 0x665, x1, 1924, x2)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x66666998, 0x66666666, 0x332, x1, 1928, x2)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x66666bba, 0x66666666, 0x554, x1, 1932, x2)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x66666668, 0x66666666, 0x2, x1, 1936, x2)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x66666693, 0x66666666, 0x2d, x1, 1940, x2)
+
+inst_503:
+// rs1_val==1717986918 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x66666639, 0x66666666, -0x2d, x1, 1944, x2)
+
+inst_504:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66666ccc, 0x66666666, 0x666, x1, 1948, x2)
+
+inst_505:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x66666999, 0x66666666, 0x333, x1, 1952, x2)
+
+inst_506:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x6666666b, 0x66666666, 0x5, x1, 1956, x2)
+
+inst_507:
+// rs1_val==1717986918 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x66666110, 0x66666666, -0x556, x1, 1960, x2)
+
+inst_508:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x66666bbb, 0x66666666, 0x555, x1, 1964, x2)
+
+inst_509:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x66666669, 0x66666666, 0x3, x1, 1968, x2)
+
+inst_510:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x33333361, 0x33333333, 0x2e, x1, 1972, x2)
+
+inst_511:
+// rs1_val==858993459 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0x33333307, 0x33333333, -0x2c, x1, 1976, x2)
+
+inst_512:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x3333399a, 0x33333333, 0x667, x1, 1980, x2)
+
+inst_513:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x33333667, 0x33333333, 0x334, x1, 1984, x2)
+
+inst_514:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0x33333339, 0x33333333, 0x6, x1, 1988, x2)
+
+inst_515:
+// rs1_val==858993459 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0x33332dde, 0x33333333, -0x555, x1, 1992, x2)
+
+inst_516:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x33333889, 0x33333333, 0x556, x1, 1996, x2)
+
+inst_517:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x33333337, 0x33333333, 0x4, x1, 2000, x2)
+
+inst_518:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x3333335f, 0x33333333, 0x2c, x1, 2004, x2)
+
+inst_519:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x33333333, 0x33333333, 0x0, x1, 2008, x2)
+
+inst_520:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x33333998, 0x33333333, 0x665, x1, 2012, x2)
+
+inst_521:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x33333665, 0x33333333, 0x332, x1, 2016, x2)
+
+inst_522:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x33333887, 0x33333333, 0x554, x1, 2020, x2)
+
+inst_523:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x33333335, 0x33333333, 0x2, x1, 2024, x2)
+
+inst_524:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33333360, 0x33333333, 0x2d, x1, 2028, x2)
+
+inst_525:
+// rs1_val==858993459 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0x33333306, 0x33333333, -0x2d, x1, 2032, x2)
+
+inst_526:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x33333999, 0x33333333, 0x666, x1, 2036, x2)
+
+inst_527:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x33333666, 0x33333333, 0x333, x1, 2040, x2)
+
+inst_528:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0x33333338, 0x33333333, 0x5, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_529:
+// rs1_val==858993459 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0x33332ddd, 0x33333333, -0x556, x1, 0, x2)
+
+inst_530:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x33333888, 0x33333333, 0x555, x1, 4, x2)
+
+inst_531:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x33333336, 0x33333333, 0x3, x1, 8, x2)
+
+inst_532:
+// rs1_val==5 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0x33, 0x5, 0x2e, x1, 12, x2)
+
+inst_533:
+// rs1_val==5 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xffffffd9, 0x5, -0x2c, x1, 16, x2)
+
+inst_534:
+// rs1_val==5 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0x66c, 0x5, 0x667, x1, 20, x2)
+
+inst_535:
+// rs1_val==5 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0x339, 0x5, 0x334, x1, 24, x2)
+
+inst_536:
+// rs1_val==5 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xb, 0x5, 0x6, x1, 28, x2)
+
+inst_537:
+// rs1_val==5 and imm_val==-1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x555
+TEST_IMM_OP( addi, x11, x10, 0xfffffab0, 0x5, -0x555, x1, 32, x2)
+
+inst_538:
+// rs1_val==5 and imm_val==1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( addi, x11, x10, 0x55b, 0x5, 0x556, x1, 36, x2)
+
+inst_539:
+// rs1_val==5 and imm_val==4, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( addi, x11, x10, 0x9, 0x5, 0x4, x1, 40, x2)
+
+inst_540:
+// rs1_val==5 and imm_val==44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( addi, x11, x10, 0x31, 0x5, 0x2c, x1, 44, x2)
+
+inst_541:
+// rs1_val==5 and imm_val==0, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0x5, 0x5, 0x0, x1, 48, x2)
+
+inst_542:
+// rs1_val==5 and imm_val==1637, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( addi, x11, x10, 0x66a, 0x5, 0x665, x1, 52, x2)
+
+inst_543:
+// rs1_val==5 and imm_val==818, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( addi, x11, x10, 0x337, 0x5, 0x332, x1, 56, x2)
+
+inst_544:
+// rs1_val==5 and imm_val==1364, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( addi, x11, x10, 0x559, 0x5, 0x554, x1, 60, x2)
+
+inst_545:
+// rs1_val==5 and imm_val==2, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( addi, x11, x10, 0x7, 0x5, 0x2, x1, 64, x2)
+
+inst_546:
+// rs1_val==5 and imm_val==45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( addi, x11, x10, 0x32, 0x5, 0x2d, x1, 68, x2)
+
+inst_547:
+// rs1_val==5 and imm_val==-45, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2d
+TEST_IMM_OP( addi, x11, x10, 0xffffffd8, 0x5, -0x2d, x1, 72, x2)
+
+inst_548:
+// rs1_val==5 and imm_val==1638, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( addi, x11, x10, 0x66b, 0x5, 0x666, x1, 76, x2)
+
+inst_549:
+// rs1_val==5 and imm_val==819, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( addi, x11, x10, 0x338, 0x5, 0x333, x1, 80, x2)
+
+inst_550:
+// rs1_val==5 and imm_val==5, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( addi, x11, x10, 0xa, 0x5, 0x5, x1, 84, x2)
+
+inst_551:
+// rs1_val==5 and imm_val==-1366, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x556
+TEST_IMM_OP( addi, x11, x10, 0xfffffaaf, 0x5, -0x556, x1, 88, x2)
+
+inst_552:
+// rs1_val==5 and imm_val==1365, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( addi, x11, x10, 0x55a, 0x5, 0x555, x1, 92, x2)
+
+inst_553:
+// rs1_val==5 and imm_val==3, 
+// opcode: addi ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( addi, x11, x10, 0x8, 0x5, 0x3, x1, 96, x2)
+
+inst_554:
+// rs1_val==-1431655766 and imm_val==46, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2e
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaad8, -0x55555556, 0x2e, x1, 100, x2)
+
+inst_555:
+// rs1_val==-1431655766 and imm_val==-44, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2c
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaa7e, -0x55555556, -0x2c, x1, 104, x2)
+
+inst_556:
+// rs1_val==-1431655766 and imm_val==1639, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x667
+TEST_IMM_OP( addi, x11, x10, 0xaaaab111, -0x55555556, 0x667, x1, 108, x2)
+
+inst_557:
+// rs1_val==-1431655766 and imm_val==820, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x334
+TEST_IMM_OP( addi, x11, x10, 0xaaaaadde, -0x55555556, 0x334, x1, 112, x2)
+
+inst_558:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x6
+TEST_IMM_OP( addi, x11, x10, 0xaaaaaab0, -0x55555556, 0x6, x1, 116, x2)
+
+inst_559:
+// rs1_val == -1073741825, imm_val == 64, rs1_val < 0 and imm_val > 0
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x40000001;  immval:0x40
+TEST_IMM_OP( addi, x11, x10, 0xc000003f, -0x40000001, 0x40, x1, 120, x2)
+
+inst_560:
+// rs1_val == -33554433, 
+// opcode: addi ; op1:x10; dest:x11; op1val:-0x2000001;  immval:0x0
+TEST_IMM_OP( addi, x11, x10, 0xfdffffff, -0x2000001, 0x0, x1, 124, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S
new file mode 100644
index 000000000..dca83d0f0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S
@@ -0,0 +1,3026 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the and instruction of the RISC-V E extension for the and covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",and)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x11, rs2==x3, rd==x10, rs1_val != rs2_val, rs1_val > 0 and rs2_val > 0, rs1_val == 16, rs2_val == 8
+// opcode: and ; op1:x11; op2:x3; dest:x10; op1val:0x10;  op2val:0x8
+TEST_RR_OP(and, x10, x11, x3, 0x0, 0x10, 0x8, x1, 0, x7)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x13, rs2==x11, rd==x13, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
+// opcode: and ; op1:x13; op2:x11; dest:x13; op1val:0x3;  op2val:0x7fffffff
+TEST_RR_OP(and, x13, x13, x11, 0x3, 0x3, 0x7fffffff, x1, 4, x7)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x12, rs2==x6, rd==x6, rs2_val == -1073741825, rs1_val == 256, rs1_val > 0 and rs2_val < 0
+// opcode: and ; op1:x12; op2:x6; dest:x6; op1val:0x100;  op2val:-0x40000001
+TEST_RR_OP(and, x6, x12, x6, 0x100, 0x100, -0x40000001, x1, 8, x7)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x5, rs2_val == -536870913, rs1_val == 262144
+// opcode: and ; op1:x8; op2:x8; dest:x5; op1val:0x40000;  op2val:0x40000
+TEST_RR_OP(and, x5, x8, x8, 0x40000, 0x40000, 0x40000, x1, 12, x7)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x4, rs2==x4, rd==x4, rs2_val == -268435457, rs1_val == 1048576
+// opcode: and ; op1:x4; op2:x4; dest:x4; op1val:0x100000;  op2val:0x100000
+TEST_RR_OP(and, x4, x4, x4, 0x100000, 0x100000, 0x100000, x1, 16, x7)
+
+inst_5:
+// rs1==x15, rs2==x2, rd==x12, rs2_val == -134217729, rs1_val < 0 and rs2_val < 0, rs1_val == -67108865
+// opcode: and ; op1:x15; op2:x2; dest:x12; op1val:-0x4000001;  op2val:-0x8000001
+TEST_RR_OP(and, x12, x15, x2, 0xf3ffffff, -0x4000001, -0x8000001, x1, 20, x7)
+
+inst_6:
+// rs1==x6, rs2==x15, rd==x8, rs2_val == -67108865, rs1_val == -1431655766
+// opcode: and ; op1:x6; op2:x15; dest:x8; op1val:-0x55555556;  op2val:-0x4000001
+TEST_RR_OP(and, x8, x6, x15, 0xaaaaaaaa, -0x55555556, -0x4000001, x1, 24, x3)
+
+inst_7:
+// rs1==x10, rs2==x5, rd==x9, rs2_val == -33554433, rs1_val == 4194304
+// opcode: and ; op1:x10; op2:x5; dest:x9; op1val:0x400000;  op2val:-0x2000001
+TEST_RR_OP(and, x9, x10, x5, 0x400000, 0x400000, -0x2000001, x1, 28, x3)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_8:
+// rs1==x2, rs2==x0, rd==x1, rs2_val == -16777217, 
+// opcode: and ; op1:x2; op2:x0; dest:x1; op1val:0x40000;  op2val:0x0
+TEST_RR_OP(and, x1, x2, x0, 0x0, 0x40000, 0x0, x4, 0, x3)
+
+inst_9:
+// rs1==x5, rs2==x1, rd==x15, rs2_val == -8388609, rs1_val == -65
+// opcode: and ; op1:x5; op2:x1; dest:x15; op1val:-0x41;  op2val:-0x800001
+TEST_RR_OP(and, x15, x5, x1, 0xff7fffbf, -0x41, -0x800001, x4, 4, x3)
+
+inst_10:
+// rs1==x7, rs2==x10, rd==x2, rs2_val == -4194305, rs1_val == 16777216
+// opcode: and ; op1:x7; op2:x10; dest:x2; op1val:0x1000000;  op2val:-0x400001
+TEST_RR_OP(and, x2, x7, x10, 0x1000000, 0x1000000, -0x400001, x4, 8, x3)
+
+inst_11:
+// rs1==x1, rs2==x9, rd==x14, rs2_val == -2097153, rs1_val == -16385
+// opcode: and ; op1:x1; op2:x9; dest:x14; op1val:-0x4001;  op2val:-0x200001
+TEST_RR_OP(and, x14, x1, x9, 0xffdfbfff, -0x4001, -0x200001, x4, 12, x3)
+
+inst_12:
+// rs1==x14, rs2==x13, rd==x7, rs2_val == -1048577, rs1_val == -1025
+// opcode: and ; op1:x14; op2:x13; dest:x7; op1val:-0x401;  op2val:-0x100001
+TEST_RR_OP(and, x7, x14, x13, 0xffeffbff, -0x401, -0x100001, x4, 16, x3)
+
+inst_13:
+// rs1==x3, rs2==x14, rd==x0, rs2_val == -524289, rs1_val == -3
+// opcode: and ; op1:x3; op2:x14; dest:x0; op1val:-0x3;  op2val:-0x80001
+TEST_RR_OP(and, x0, x3, x14, 0, -0x3, -0x80001, x4, 20, x2)
+
+inst_14:
+// rs1==x9, rs2==x7, rd==x11, rs2_val == -262145, rs1_val == 33554432
+// opcode: and ; op1:x9; op2:x7; dest:x11; op1val:0x2000000;  op2val:-0x40001
+TEST_RR_OP(and, x11, x9, x7, 0x2000000, 0x2000000, -0x40001, x4, 24, x2)
+
+inst_15:
+// rs1==x0, rs2==x12, rd==x3, rs2_val == -131073, 
+// opcode: and ; op1:x0; op2:x12; dest:x3; op1val:0x0;  op2val:-0x20001
+TEST_RR_OP(and, x3, x0, x12, 0x0, 0x0, -0x20001, x4, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_16:
+// rs2_val == -65537, rs1_val == 4
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x10001
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, -0x10001, x1, 0, x2)
+
+inst_17:
+// rs2_val == -32769, rs1_val == 1431655765
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x8001
+TEST_RR_OP(and, x12, x10, x11, 0x55555555, 0x55555555, -0x8001, x1, 4, x2)
+
+inst_18:
+// rs2_val == -16385, rs1_val == 1073741824
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x4001
+TEST_RR_OP(and, x12, x10, x11, 0x40000000, 0x40000000, -0x4001, x1, 8, x2)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x2001
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, -0x2001, x1, 12, x2)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:-0x1001
+TEST_RR_OP(and, x12, x10, x11, 0x100, 0x100, -0x1001, x1, 16, x2)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x801
+TEST_RR_OP(and, x12, x10, x11, 0xaaaaa2aa, -0x55555556, -0x801, x1, 20, x2)
+
+inst_22:
+// rs2_val == -1025, rs1_val == 4096
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:-0x401
+TEST_RR_OP(and, x12, x10, x11, 0x1000, 0x1000, -0x401, x1, 24, x2)
+
+inst_23:
+// rs2_val == -513, rs1_val == 1
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x201
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x1, -0x201, x1, 28, x2)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:-0x101
+TEST_RR_OP(and, x12, x10, x11, 0x7, 0x7, -0x101, x1, 32, x2)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x81
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, -0x81, x1, 36, x2)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x41
+TEST_RR_OP(and, x12, x10, x11, 0xb504, 0xb504, -0x41, x1, 40, x2)
+
+inst_27:
+// rs2_val == -33, rs1_val == 128
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:-0x21
+TEST_RR_OP(and, x12, x10, x11, 0x80, 0x80, -0x21, x1, 44, x2)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x11
+TEST_RR_OP(and, x12, x10, x11, 0xb505, 0xb505, -0x11, x1, 48, x2)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:-0x9
+TEST_RR_OP(and, x12, x10, x11, 0x100000, 0x100000, -0x9, x1, 52, x2)
+
+inst_30:
+// rs2_val == -5, rs1_val == 16384
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4000, 0x4000, -0x5, x1, 56, x2)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x3
+TEST_RR_OP(and, x12, x10, x11, 0x33333330, 0x33333332, -0x3, x1, 60, x2)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x2
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555554, -0x2, x1, 64, x2)
+
+inst_33:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x800001
+TEST_RR_OP(and, x12, x10, x11, 0x7f7fffff, 0x7fffffff, -0x800001, x1, 68, x2)
+
+inst_34:
+// rs1_val == -1073741825, rs1_val < 0 and rs2_val > 0
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x26666667, -0x40000001, 0x66666667, x1, 72, x2)
+
+inst_35:
+// rs1_val == -536870913, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, -0x20000001, 0x3, x1, 76, x2)
+
+inst_36:
+// rs1_val == -268435457, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:-0x8
+TEST_RR_OP(and, x12, x10, x11, 0xeffffff8, -0x10000001, -0x8, x1, 80, x2)
+
+inst_37:
+// rs1_val == -134217729, rs2_val == 2097152
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:0x200000
+TEST_RR_OP(and, x12, x10, x11, 0x200000, -0x8000001, 0x200000, x1, 84, x2)
+
+inst_38:
+// rs1_val == -33554433, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:-0x101
+TEST_RR_OP(and, x12, x10, x11, 0xfdfffeff, -0x2000001, -0x101, x1, 88, x2)
+
+inst_39:
+// rs1_val == -16777217, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:-0x800001
+TEST_RR_OP(and, x12, x10, x11, 0xfe7fffff, -0x1000001, -0x800001, x1, 92, x2)
+
+inst_40:
+// rs1_val == -8388609, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:-0x101
+TEST_RR_OP(and, x12, x10, x11, 0xff7ffeff, -0x800001, -0x101, x1, 96, x2)
+
+inst_41:
+// rs1_val == -4194305, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x200001
+TEST_RR_OP(and, x12, x10, x11, 0xff9fffff, -0x400001, -0x200001, x1, 100, x2)
+
+inst_42:
+// rs1_val == -2097153, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66466666, -0x200001, 0x66666666, x1, 104, x2)
+
+inst_43:
+// rs1_val == -1048577, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xffef4afd, -0x100001, -0xb503, x1, 108, x2)
+
+inst_44:
+// rs1_val == -524289, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xb504, -0x80001, 0xb504, x1, 112, x2)
+
+inst_45:
+// rs1_val == -262145, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:-0x8001
+TEST_RR_OP(and, x12, x10, x11, 0xfffb7fff, -0x40001, -0x8001, x1, 116, x2)
+
+inst_46:
+// rs1_val == -131073, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55555556, -0x20001, 0x55555556, x1, 120, x2)
+
+inst_47:
+// rs1_val == -65537, rs2_val == 524288
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x80000
+TEST_RR_OP(and, x12, x10, x11, 0x80000, -0x10001, 0x80000, x1, 124, x2)
+
+inst_48:
+// rs1_val == -32769, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:-0x4001
+TEST_RR_OP(and, x12, x10, x11, 0xffff3fff, -0x8001, -0x4001, x1, 128, x2)
+
+inst_49:
+// rs1_val == -8193, rs2_val == 2
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x2001, 0x2, x1, 132, x2)
+
+inst_50:
+// rs1_val == -4097, rs2_val == 32
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x20
+TEST_RR_OP(and, x12, x10, x11, 0x20, -0x1001, 0x20, x1, 136, x2)
+
+inst_51:
+// rs1_val == -2049, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xffff42fc, -0x801, -0xb504, x1, 140, x2)
+
+inst_52:
+// rs1_val == -513, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:-0x80001
+TEST_RR_OP(and, x12, x10, x11, 0xfff7fdff, -0x201, -0x80001, x1, 144, x2)
+
+inst_53:
+// rs1_val == -257, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:-0x8000001
+TEST_RR_OP(and, x12, x10, x11, 0xf7fffeff, -0x101, -0x8000001, x1, 148, x2)
+
+inst_54:
+// rs1_val == -129, rs2_val == 1431655765
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55555555, -0x81, 0x55555555, x1, 152, x2)
+
+inst_55:
+// rs1_val == -33, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x201
+TEST_RR_OP(and, x12, x10, x11, 0xfffffddf, -0x21, -0x201, x1, 156, x2)
+
+inst_56:
+// rs1_val == -17, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, -0x11, 0x3, x1, 160, x2)
+
+inst_57:
+// rs1_val == -9, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x6, -0x9, 0x6, x1, 164, x2)
+
+inst_58:
+// rs1_val == -5, rs2_val == 1
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x1
+TEST_RR_OP(and, x12, x10, x11, 0x1, -0x5, 0x1, x1, 168, x2)
+
+inst_59:
+// rs1_val == -2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xffff4afc, -0x2, -0xb503, x1, 172, x2)
+
+inst_60:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1)), rs1_val == 2
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x80000000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, -0x80000000, x1, 176, x2)
+
+inst_61:
+// rs2_val == 1073741824, rs1_val == 2048
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x40000000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x800, 0x40000000, x1, 180, x2)
+
+inst_62:
+// rs2_val == 536870912, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x20000000
+TEST_RR_OP(and, x12, x10, x11, 0x20000000, -0x4000001, 0x20000000, x1, 184, x2)
+
+inst_63:
+// rs2_val == 268435456, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x10000000
+TEST_RR_OP(and, x12, x10, x11, 0x10000000, -0x100001, 0x10000000, x1, 188, x2)
+
+inst_64:
+// rs2_val == 134217728, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x8000000
+TEST_RR_OP(and, x12, x10, x11, 0x8000000, -0xb503, 0x8000000, x1, 192, x2)
+
+inst_65:
+// rs2_val == 67108864, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x1;  op2val:0x4000000
+TEST_RR_OP(and, x12, x10, x11, 0x4000000, -0x1, 0x4000000, x1, 196, x2)
+
+inst_66:
+// rs2_val == 33554432, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2000000
+TEST_RR_OP(and, x12, x10, x11, 0x2000000, -0x55555555, 0x2000000, x1, 200, x2)
+
+inst_67:
+// rs2_val == 16777216, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0x1000000
+TEST_RR_OP(and, x12, x10, x11, 0x1000000, -0x10000001, 0x1000000, x1, 204, x2)
+
+inst_68:
+// rs2_val == 8388608, rs1_val == 268435456
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x800000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x10000000, 0x800000, x1, 208, x2)
+
+inst_69:
+// rs2_val == 4194304, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x400000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x800, 0x400000, x1, 212, x2)
+
+inst_70:
+// rs2_val == 1048576, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x100000
+TEST_RR_OP(and, x12, x10, x11, 0x100000, 0x55555555, 0x100000, x1, 216, x2)
+
+inst_71:
+// rs2_val == 262144, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:0x40000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x9, 0x40000, x1, 220, x2)
+
+inst_72:
+// rs2_val == 131072, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x20000
+TEST_RR_OP(and, x12, x10, x11, 0x20000, -0x55555555, 0x20000, x1, 224, x2)
+
+inst_73:
+// rs2_val == 65536, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x10000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x800, 0x10000, x1, 228, x2)
+
+inst_74:
+// rs2_val == 32768, rs1_val == 65536
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x8000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x10000, 0x8000, x1, 232, x2)
+
+inst_75:
+// rs2_val == 16384, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0x4000, x1, 236, x2)
+
+inst_76:
+// rs2_val == 8192, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:0x2000
+TEST_RR_OP(and, x12, x10, x11, 0x2000, -0xa, 0x2000, x1, 240, x2)
+
+inst_77:
+// rs2_val == 4096, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x1000
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x1000, x1, 244, x2)
+
+inst_78:
+// rs2_val == 2048, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x800
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, 0x800, x1, 248, x2)
+
+inst_79:
+// rs2_val == 1024, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x400
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb503, 0x400, x1, 252, x2)
+
+inst_80:
+// rs2_val == 512, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x200
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, 0x200, x1, 256, x2)
+
+inst_81:
+// rs2_val == 256, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x100
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb503, 0x100, x1, 260, x2)
+
+inst_82:
+// rs2_val == 128, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x80
+TEST_RR_OP(and, x12, x10, x11, 0x80, -0x20000001, 0x80, x1, 264, x2)
+
+inst_83:
+// rs2_val == 64, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x40
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333332, 0x40, x1, 268, x2)
+
+inst_84:
+// rs2_val == 16, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:0x10
+TEST_RR_OP(and, x12, x10, x11, 0x10, -0x7, 0x10, x1, 272, x2)
+
+inst_85:
+// rs2_val == 4, rs1_val==-46339 and rs2_val==4
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb503, 0x4, x1, 276, x2)
+
+inst_86:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x80000000, 0x33333334, x1, 280, x2)
+
+inst_87:
+// rs1_val == 536870912, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x20000000, 0x20000000, -0xb504, x1, 284, x2)
+
+inst_88:
+// rs1_val == 134217728, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x8000000, 0xb504, x1, 288, x2)
+
+inst_89:
+// rs1_val == 67108864, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4000000, 0x4000000, -0xb504, x1, 292, x2)
+
+inst_90:
+// rs1_val == 8388608, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x3fffffff
+TEST_RR_OP(and, x12, x10, x11, 0x800000, 0x800000, 0x3fffffff, x1, 296, x2)
+
+inst_91:
+// rs1_val == 2097152, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x9
+TEST_RR_OP(and, x12, x10, x11, 0x200000, 0x200000, -0x9, x1, 300, x2)
+
+inst_92:
+// rs1_val == 524288, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x7fffffff
+TEST_RR_OP(and, x12, x10, x11, 0x80000, 0x80000, 0x7fffffff, x1, 304, x2)
+
+inst_93:
+// rs1_val == 131072, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:-0x4
+TEST_RR_OP(and, x12, x10, x11, 0x20000, 0x20000, -0x4, x1, 308, x2)
+
+inst_94:
+// rs1_val == 32768, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x10000000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x8000, 0x10000000, x1, 312, x2)
+
+inst_95:
+// rs1_val == 8192, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x1000001
+TEST_RR_OP(and, x12, x10, x11, 0x2000, 0x2000, -0x1000001, x1, 316, x2)
+
+inst_96:
+// rs1_val == 1024, rs1_val == rs2_val
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x400
+TEST_RR_OP(and, x12, x10, x11, 0x400, 0x400, 0x400, x1, 320, x2)
+
+inst_97:
+// rs1_val == 512, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x20000001
+TEST_RR_OP(and, x12, x10, x11, 0x200, 0x200, -0x20000001, x1, 324, x2)
+
+inst_98:
+// rs1_val == 64, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x40000001
+TEST_RR_OP(and, x12, x10, x11, 0x40, 0x40, -0x40000001, x1, 328, x2)
+
+inst_99:
+// rs1_val == 32, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x2000000
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x20, 0x2000000, x1, 332, x2)
+
+inst_100:
+// rs1_val == 8, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x8, 0x66666667, x1, 336, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0xb505, 0xb505, 0xb505, x1, 340, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0xb505, -0xb503, x1, 344, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x2405, 0xb505, 0x66666667, x1, 348, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x3104, 0xb505, 0x33333334, x1, 352, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb505, 0x6, x1, 356, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xa001, 0xb505, -0x55555555, x1, 360, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0xb505, 0x55555556, x1, 364, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb505, 0x4, x1, 368, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xb501, 0xb505, 0xb503, x1, 372, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==0, rs2_val == 0
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb505, 0x0, x1, 376, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x2405, 0xb505, 0x66666665, x1, 380, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0xb505, 0x33333332, x1, 384, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0xb505, 0x55555554, x1, 388, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb505, 0x2, x1, 392, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xb504, 0xb505, 0xb504, x1, 396, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb505, -0xb504, x1, 400, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0xb505, 0x66666666, x1, 404, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x3101, 0xb505, 0x33333333, x1, 408, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0xb505, 0x5, x1, 412, x2)
+
+inst_120:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xa000, 0xb505, -0x55555556, x1, 416, x2)
+
+inst_121:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1505, 0xb505, 0x55555555, x1, 420, x2)
+
+inst_122:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0xb505, 0x3, x1, 424, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x5, -0xb503, 0xb505, x1, 428, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xffff4afd, -0xb503, -0xb503, x1, 432, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x66664265, -0xb503, 0x66666667, x1, 436, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x33330234, -0xb503, 0x33333334, x1, 440, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb503, 0x6, x1, 444, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa9, -0xb503, -0x55555555, x1, 448, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, -0xb503, 0x55555556, x1, 452, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1, -0xb503, 0xb503, x1, 456, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb503, 0x0, x1, 460, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x66664265, -0xb503, 0x66666665, x1, 464, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, -0xb503, 0x33333332, x1, 468, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, -0xb503, 0x55555554, x1, 472, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb503, 0x2, x1, 476, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb503, 0xb504, x1, 480, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xffff4afc, -0xb503, -0xb504, x1, 484, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, -0xb503, 0x66666666, x1, 488, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x33330231, -0xb503, 0x33333333, x1, 492, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, -0xb503, 0x5, x1, 496, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0xb503, -0x55555556, x1, 500, x2)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55554055, -0xb503, 0x55555555, x1, 504, x2)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x1, -0xb503, 0x3, x1, 508, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x2405, 0x66666667, 0xb505, x1, 512, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x66664265, 0x66666667, -0xb503, x1, 516, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x66666667, 0x66666667, 0x66666667, x1, 520, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x66666667, 0x33333334, x1, 524, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x66666667, 0x6, x1, 528, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, 0x66666667, -0x55555555, x1, 532, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x44444446, 0x66666667, 0x55555556, x1, 536, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x66666667, 0x4, x1, 540, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x2403, 0x66666667, 0xb503, x1, 544, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x66666667, 0x0, x1, 548, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x66666665, 0x66666667, 0x66666665, x1, 552, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666667, 0x33333332, x1, 556, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x66666667, 0x55555554, x1, 560, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x66666667, 0x2, x1, 564, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0x66666667, 0xb504, x1, 568, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, 0x66666667, -0xb504, x1, 572, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66666666, 0x66666667, 0x66666666, x1, 576, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, 0x66666667, 0x33333333, x1, 580, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x66666667, 0x5, x1, 584, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666667, -0x55555556, x1, 588, x2)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x44444445, 0x66666667, 0x55555555, x1, 592, x2)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x66666667, 0x3, x1, 596, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x3104, 0x33333334, 0xb505, x1, 600, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x33330234, 0x33333334, -0xb503, x1, 604, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x33333334, 0x66666667, x1, 608, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x33333334, 0x33333334, 0x33333334, x1, 612, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x33333334, 0x6, x1, 616, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, 0x33333334, -0x55555555, x1, 620, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x33333334, 0x55555556, x1, 624, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x33333334, 0x4, x1, 628, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0x33333334, 0xb503, x1, 632, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333334, 0x0, x1, 636, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x33333334, 0x66666665, x1, 640, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x33333330, 0x33333334, 0x33333332, x1, 644, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x33333334, 0x55555554, x1, 648, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333334, 0x2, x1, 652, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x3104, 0x33333334, 0xb504, x1, 656, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x33330234, 0x33333334, -0xb504, x1, 660, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x33333334, 0x66666666, x1, 664, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x33333330, 0x33333334, 0x33333333, x1, 668, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x33333334, 0x5, x1, 672, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, 0x33333334, -0x55555556, x1, 676, x2)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x33333334, 0x55555555, x1, 680, x2)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333334, 0x3, x1, 684, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0xb505, x1, 688, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, -0xb503, x1, 692, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x6, 0x66666667, x1, 696, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x33333334, x1, 700, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x6, 0x6, x1, 704, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, -0x55555555, x1, 708, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x6, 0x55555556, x1, 712, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x4, x1, 716, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, 0xb503, x1, 720, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x6, 0x0, x1, 724, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x66666665, x1, 728, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, 0x33333332, x1, 732, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x55555554, x1, 736, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, 0x2, x1, 740, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0xb504, x1, 744, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, -0xb504, x1, 748, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x6, 0x66666666, x1, 752, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, 0x33333333, x1, 756, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x5, x1, 760, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, -0x55555556, x1, 764, x2)
+
+inst_208:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x6, 0x55555555, x1, 768, x2)
+
+inst_209:
+// rs1_val==6 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x6, 0x3, x1, 772, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0xa001, -0x55555555, 0xb505, x1, 776, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa9, -0x55555555, -0xb503, x1, 780, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, -0x55555555, 0x66666667, x1, 784, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, -0x55555555, 0x33333334, x1, 788, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555555, 0x6, x1, 792, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555555, x1, 796, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555555, 0x55555556, x1, 800, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555555, 0x4, x1, 804, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xa003, -0x55555555, 0xb503, x1, 808, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555555, 0x0, x1, 812, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x22222221, -0x55555555, 0x66666665, x1, 816, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555555, 0x33333332, x1, 820, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555555, 0x55555554, x1, 824, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555555, 0x2, x1, 828, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xa000, -0x55555555, 0xb504, x1, 832, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0x55555555, -0xb504, x1, 836, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555555, 0x66666666, x1, 840, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, -0x55555555, 0x33333333, x1, 844, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x1, -0x55555555, 0x5, x1, 848, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xaaaaaaaa, -0x55555555, -0x55555556, x1, 852, x2)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1, -0x55555555, 0x55555555, x1, 856, x2)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, -0x55555555, 0x3, x1, 860, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0x55555556, 0xb505, x1, 864, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, 0x55555556, -0xb503, x1, 868, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x44444446, 0x55555556, 0x66666667, x1, 872, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x55555556, 0x33333334, x1, 876, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x55555556, 0x6, x1, 880, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x55555556, -0x55555555, x1, 884, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55555556, 0x55555556, 0x55555556, x1, 888, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555556, 0x4, x1, 892, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1502, 0x55555556, 0xb503, x1, 896, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555556, 0x0, x1, 900, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x55555556, 0x66666665, x1, 904, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x11111112, 0x55555556, 0x33333332, x1, 908, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555556, 0x55555554, x1, 912, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x55555556, 0x2, x1, 916, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0x55555556, 0xb504, x1, 920, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, 0x55555556, -0xb504, x1, 924, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x44444446, 0x55555556, 0x66666666, x1, 928, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x11111112, 0x55555556, 0x33333333, x1, 932, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555556, 0x5, x1, 936, x2)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x55555556, -0x55555556, x1, 940, x2)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555556, 0x55555555, x1, 944, x2)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x55555556, 0x3, x1, 948, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0xb505, x1, 952, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, -0xb503, x1, 956, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x66666667, x1, 960, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x33333334, x1, 964, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x6, x1, 968, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, -0x55555555, x1, 972, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x55555556, x1, 976, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x4, x1, 980, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0xb503, x1, 984, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0x0, x1, 988, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x66666665, x1, 992, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0x33333332, x1, 996, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x55555554, x1, 1000, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0x2, x1, 1004, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0xb504, x1, 1008, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, -0xb504, x1, 1012, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x66666666, x1, 1016, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0x33333333, x1, 1020, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x5, x1, 1024, x2)
+
+inst_273:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, -0x55555556, x1, 1028, x2)
+
+inst_274:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x4, 0x55555555, x1, 1032, x2)
+
+inst_275:
+// rs1_val==4 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x4, 0x3, x1, 1036, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0xb501, 0xb503, 0xb505, x1, 1040, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0xb503, -0xb503, x1, 1044, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x2403, 0xb503, 0x66666667, x1, 1048, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0xb503, 0x33333334, x1, 1052, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0xb503, 0x6, x1, 1056, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xa003, 0xb503, -0x55555555, x1, 1060, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x1502, 0xb503, 0x55555556, x1, 1064, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb503, 0x4, x1, 1068, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xb503, 0xb503, 0xb503, x1, 1072, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb503, 0x0, x1, 1076, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x2401, 0xb503, 0x66666665, x1, 1080, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x3102, 0xb503, 0x33333332, x1, 1084, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x1500, 0xb503, 0x55555554, x1, 1088, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0xb503, 0x2, x1, 1092, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xb500, 0xb503, 0xb504, x1, 1096, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb503, -0xb504, x1, 1100, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x2402, 0xb503, 0x66666666, x1, 1104, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x3103, 0xb503, 0x33333333, x1, 1108, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0xb503, 0x5, x1, 1112, x2)
+
+inst_295:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xa002, 0xb503, -0x55555556, x1, 1116, x2)
+
+inst_296:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1501, 0xb503, 0x55555555, x1, 1120, x2)
+
+inst_297:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0xb503, 0x3, x1, 1124, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==46341, rs1_val == 0
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0xb505, x1, 1128, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, -0xb503, x1, 1132, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x66666667, x1, 1136, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x33333334, x1, 1140, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x6, x1, 1144, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, -0x55555555, x1, 1148, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x55555556, x1, 1152, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x4, x1, 1156, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0xb503, x1, 1160, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1164, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x66666665, x1, 1168, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x33333332, x1, 1172, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x55555554, x1, 1176, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x2, x1, 1180, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0xb504, x1, 1184, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, -0xb504, x1, 1188, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x66666666, x1, 1192, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x33333333, x1, 1196, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x5, x1, 1200, x2)
+
+inst_317:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, -0x55555556, x1, 1204, x2)
+
+inst_318:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x55555555, x1, 1208, x2)
+
+inst_319:
+// rs1_val==0 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x0, 0x3, x1, 1212, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x2405, 0x66666665, 0xb505, x1, 1216, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x66664265, 0x66666665, -0xb503, x1, 1220, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x66666665, 0x66666665, 0x66666667, x1, 1224, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x66666665, 0x33333334, x1, 1228, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x66666665, 0x6, x1, 1232, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222221, 0x66666665, -0x55555555, x1, 1236, x2)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x66666665, 0x55555556, x1, 1240, x2)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x66666665, 0x4, x1, 1244, x2)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x2401, 0x66666665, 0xb503, x1, 1248, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333333, 0x0, x1, 1252, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x22222221, 0x33333333, 0x66666665, x1, 1256, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x33333332, 0x33333333, 0x33333332, x1, 1260, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x33333333, 0x55555554, x1, 1264, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x33333333, 0x2, x1, 1268, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0x33333333, 0xb504, x1, 1272, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, 0x33333333, -0xb504, x1, 1276, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333333, 0x66666666, x1, 1280, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x33333333, 0x33333333, 0x33333333, x1, 1284, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x33333333, 0x5, x1, 1288, x2)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333333, -0x55555556, x1, 1292, x2)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x11111111, 0x33333333, 0x55555555, x1, 1296, x2)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x33333333, 0x3, x1, 1300, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, 0xb505, x1, 1304, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, -0xb503, x1, 1308, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, 0x66666667, x1, 1312, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x33333334, x1, 1316, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x6, x1, 1320, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x5, -0x55555555, x1, 1324, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x55555556, x1, 1328, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x4, x1, 1332, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x5, 0xb503, x1, 1336, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, 0x0, x1, 1340, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, 0x66666665, x1, 1344, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, 0x33333332, x1, 1348, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x55555554, x1, 1352, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, 0x2, x1, 1356, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0xb504, x1, 1360, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, -0xb504, x1, 1364, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x5, 0x66666666, x1, 1368, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x5, 0x33333333, x1, 1372, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, 0x5, x1, 1376, x2)
+
+inst_361:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x5, -0x55555556, x1, 1380, x2)
+
+inst_362:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x5, 0x55555555, x1, 1384, x2)
+
+inst_363:
+// rs1_val==5 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x5, 0x3, x1, 1388, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0xa000, -0x55555556, 0xb505, x1, 1392, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0x55555556, -0xb503, x1, 1396, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555556, 0x66666667, x1, 1400, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, -0x55555556, 0x33333334, x1, 1404, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555556, 0x6, x1, 1408, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555555, x1, 1412, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555556, 0x55555556, x1, 1416, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x4, x1, 1420, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xa002, -0x55555556, 0xb503, x1, 1424, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x0, x1, 1428, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, -0x55555556, 0x66666665, x1, 1432, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555556, 0x33333332, x1, 1436, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x55555554, x1, 1440, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555556, 0x2, x1, 1444, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xa000, -0x55555556, 0xb504, x1, 1448, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0x55555556, -0xb504, x1, 1452, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555556, 0x66666666, x1, 1456, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, -0x55555556, 0x33333333, x1, 1460, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x5, x1, 1464, x2)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555556, x1, 1468, x2)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0x55555556, 0x55555555, x1, 1472, x2)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, -0x55555556, 0x3, x1, 1476, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x1505, 0x55555555, 0xb505, x1, 1480, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x55554055, 0x55555555, -0xb503, x1, 1484, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x44444445, 0x55555555, 0x66666667, x1, 1488, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x55555555, 0x33333334, x1, 1492, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555555, 0x6, x1, 1496, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x55555555, -0x55555555, x1, 1500, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555555, 0x55555556, x1, 1504, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555555, 0x4, x1, 1508, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1501, 0x55555555, 0xb503, x1, 1512, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555555, 0x0, x1, 1516, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x44444445, 0x55555555, 0x66666665, x1, 1520, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x55555555, 0x33333332, x1, 1524, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555555, 0x55555554, x1, 1528, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555555, 0x2, x1, 1532, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0x55555555, 0xb504, x1, 1536, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, 0x55555555, -0xb504, x1, 1540, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x55555555, 0x66666666, x1, 1544, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x11111111, 0x55555555, 0x33333333, x1, 1548, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x55555555, 0x5, x1, 1552, x2)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555555, -0x55555556, x1, 1556, x2)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55555555, 0x55555555, 0x55555555, x1, 1560, x2)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x55555555, 0x3, x1, 1564, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x3, 0xb505, x1, 1568, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x3, -0xb503, x1, 1572, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, 0x66666667, x1, 1576, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0x33333334, x1, 1580, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, 0x6, x1, 1584, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, -0x55555555, x1, 1588, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, 0x55555556, x1, 1592, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0x4, x1, 1596, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, 0xb503, x1, 1600, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0x0, x1, 1604, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x3, 0x66666665, x1, 1608, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, 0x33333332, x1, 1612, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0x55555554, x1, 1616, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, 0x2, x1, 1620, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, 0xb504, x1, 1624, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x3, -0xb504, x1, 1628, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, 0x66666666, x1, 1632, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, 0x33333333, x1, 1636, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x3, 0x5, x1, 1640, x2)
+
+inst_427:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x3, -0x55555556, x1, 1644, x2)
+
+inst_428:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x3, 0x55555555, x1, 1648, x2)
+
+inst_429:
+// rs1_val==3 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x3, 0x3, 0x3, x1, 1652, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x66666665, 0x0, x1, 1656, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x66666665, 0x66666665, 0x66666665, x1, 1660, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, 0x66666665, 0x33333332, x1, 1664, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x66666665, 0x55555554, x1, 1668, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x66666665, 0x2, x1, 1672, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0x66666665, 0xb504, x1, 1676, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, 0x66666665, -0xb504, x1, 1680, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66666664, 0x66666665, 0x66666666, x1, 1684, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x22222221, 0x66666665, 0x33333333, x1, 1688, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x5, 0x66666665, 0x5, x1, 1692, x2)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, 0x66666665, -0x55555556, x1, 1696, x2)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x44444445, 0x66666665, 0x55555555, x1, 1700, x2)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x1, 0x66666665, 0x3, x1, 1704, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0x33333332, 0xb505, x1, 1708, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, 0x33333332, -0xb503, x1, 1712, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333332, 0x66666667, x1, 1716, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x33333330, 0x33333332, 0x33333334, x1, 1720, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x33333332, 0x6, x1, 1724, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333332, -0x55555555, x1, 1728, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x11111112, 0x33333332, 0x55555556, x1, 1732, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333332, 0x4, x1, 1736, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x3102, 0x33333332, 0xb503, x1, 1740, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333332, 0x0, x1, 1744, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x22222220, 0x33333332, 0x66666665, x1, 1748, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x33333332, 0x33333332, 0x33333332, x1, 1752, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x33333332, 0x55555554, x1, 1756, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x33333332, 0x2, x1, 1760, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0x33333332, 0xb504, x1, 1764, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, 0x33333332, -0xb504, x1, 1768, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333332, 0x66666666, x1, 1772, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x33333332, 0x33333332, 0x33333333, x1, 1776, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333332, 0x5, x1, 1780, x2)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x33333332, -0x55555556, x1, 1784, x2)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x33333332, 0x55555555, x1, 1788, x2)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x33333332, 0x3, x1, 1792, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0x55555554, 0xb505, x1, 1796, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, 0x55555554, -0xb503, x1, 1800, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x55555554, 0x66666667, x1, 1804, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x11111114, 0x55555554, 0x33333334, x1, 1808, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555554, 0x6, x1, 1812, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555554, -0x55555555, x1, 1816, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555554, 0x55555556, x1, 1820, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555554, 0x4, x1, 1824, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x1500, 0x55555554, 0xb503, x1, 1828, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555554, 0x0, x1, 1832, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x55555554, 0x66666665, x1, 1836, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x55555554, 0x33333332, x1, 1840, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555554, 0x55555554, x1, 1844, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555554, 0x2, x1, 1848, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0x55555554, 0xb504, x1, 1852, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, 0x55555554, -0xb504, x1, 1856, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x55555554, 0x66666666, x1, 1860, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x11111110, 0x55555554, 0x33333333, x1, 1864, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x55555554, 0x5, x1, 1868, x2)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555554, -0x55555556, x1, 1872, x2)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55555554, 0x55555554, 0x55555555, x1, 1876, x2)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x55555554, 0x3, x1, 1880, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0xb505, x1, 1884, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, -0xb503, x1, 1888, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x66666667, x1, 1892, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x33333334, x1, 1896, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x6, x1, 1900, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, -0x55555555, x1, 1904, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x55555556, x1, 1908, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x4, x1, 1912, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0xb503, x1, 1916, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x0, x1, 1920, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x66666665, x1, 1924, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x33333332, x1, 1928, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x55555554, x1, 1932, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x2, x1, 1936, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0xb504, x1, 1940, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, -0xb504, x1, 1944, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x66666666, x1, 1948, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x33333333, x1, 1952, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x5, x1, 1956, x2)
+
+inst_506:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, -0x55555556, x1, 1960, x2)
+
+inst_507:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x2, 0x55555555, x1, 1964, x2)
+
+inst_508:
+// rs1_val==2 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x2, 0x3, x1, 1968, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0xb504, 0xb504, 0xb505, x1, 1972, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb504, -0xb503, x1, 1976, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0xb504, 0x66666667, x1, 1980, x2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x3104, 0xb504, 0x33333334, x1, 1984, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb504, 0x6, x1, 1988, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xa000, 0xb504, -0x55555555, x1, 1992, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0xb504, 0x55555556, x1, 1996, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb504, 0x4, x1, 2000, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xb500, 0xb504, 0xb503, x1, 2004, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb504, 0x0, x1, 2008, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0xb504, 0x66666665, x1, 2012, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0xb504, 0x33333332, x1, 2016, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0xb504, 0x55555554, x1, 2020, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb504, 0x2, x1, 2024, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xb504, 0xb504, 0xb504, x1, 2028, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb504, -0xb504, x1, 2032, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0xb504, 0x66666666, x1, 2036, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x3100, 0xb504, 0x33333333, x1, 2040, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0xb504, 0x5, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_3)
+
+inst_528:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xa000, 0xb504, -0x55555556, x1, 0, x2)
+
+inst_529:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x1504, 0xb504, 0x55555555, x1, 4, x2)
+
+inst_530:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0xb504, 0x3, x1, 8, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb504, 0xb505, x1, 12, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0xffff4afc, -0xb504, -0xb503, x1, 16, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, -0xb504, 0x66666667, x1, 20, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x33330234, -0xb504, 0x33333334, x1, 24, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb504, 0x6, x1, 28, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0xb504, -0x55555555, x1, 32, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, -0xb504, 0x55555556, x1, 36, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb504, 0x4, x1, 40, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb504, 0xb503, x1, 44, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb504, 0x0, x1, 48, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, -0xb504, 0x66666665, x1, 52, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, -0xb504, 0x33333332, x1, 56, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, -0xb504, 0x55555554, x1, 60, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb504, 0x2, x1, 64, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb504, 0xb504, x1, 68, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0xffff4afc, -0xb504, -0xb504, x1, 72, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, -0xb504, 0x66666666, x1, 76, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x33330230, -0xb504, 0x33333333, x1, 80, x2)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, -0xb504, 0x5, x1, 84, x2)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0xaaaa0aa8, -0xb504, -0x55555556, x1, 88, x2)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x55554054, -0xb504, 0x55555555, x1, 92, x2)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x0, -0xb504, 0x3, x1, 96, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0x66666666, 0xb505, x1, 100, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, 0x66666666, -0xb503, x1, 104, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x66666666, 0x66666666, 0x66666667, x1, 108, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x22222224, 0x66666666, 0x33333334, x1, 112, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x6, 0x66666666, 0x6, x1, 116, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666666, -0x55555555, x1, 120, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x44444446, 0x66666666, 0x55555556, x1, 124, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x66666666, 0x4, x1, 128, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x2402, 0x66666666, 0xb503, x1, 132, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x66666666, 0x0, x1, 136, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(and, x12, x10, x11, 0x66666664, 0x66666666, 0x66666665, x1, 140, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666666, 0x33333332, x1, 144, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x66666666, 0x55555554, x1, 148, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x66666666, 0x2, x1, 152, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x2404, 0x66666666, 0xb504, x1, 156, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(and, x12, x10, x11, 0x66664264, 0x66666666, -0xb504, x1, 160, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(and, x12, x10, x11, 0x66666666, 0x66666666, 0x66666666, x1, 164, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666666, 0x33333333, x1, 168, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(and, x12, x10, x11, 0x4, 0x66666666, 0x5, x1, 172, x2)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x22222222, 0x66666666, -0x55555556, x1, 176, x2)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x44444444, 0x66666666, 0x55555555, x1, 180, x2)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x66666666, 0x3, x1, 184, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(and, x12, x10, x11, 0x3101, 0x33333333, 0xb505, x1, 188, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x33330231, 0x33333333, -0xb503, x1, 192, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, 0x33333333, 0x66666667, x1, 196, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(and, x12, x10, x11, 0x33333330, 0x33333333, 0x33333334, x1, 200, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(and, x12, x10, x11, 0x2, 0x33333333, 0x6, x1, 204, x2)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(and, x12, x10, x11, 0x22222223, 0x33333333, -0x55555555, x1, 208, x2)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(and, x12, x10, x11, 0x11111112, 0x33333333, 0x55555556, x1, 212, x2)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(and, x12, x10, x11, 0x0, 0x33333333, 0x4, x1, 216, x2)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(and, x12, x10, x11, 0x3103, 0x33333333, 0xb503, x1, 220, x2)
+
+inst_584:
+// rs2_val == -536870913, rs1_val == 262144
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:-0x20000001
+TEST_RR_OP(and, x12, x10, x11, 0x40000, 0x40000, -0x20000001, x1, 224, x2)
+
+inst_585:
+// rs2_val == -268435457, rs1_val == 1048576
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:-0x10000001
+TEST_RR_OP(and, x12, x10, x11, 0x100000, 0x100000, -0x10000001, x1, 228, x2)
+
+inst_586:
+// rs2_val == -524289, rs1_val == -3
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x80001
+TEST_RR_OP(and, x12, x10, x11, 0xfff7fffd, -0x3, -0x80001, x1, 232, x2)
+
+inst_587:
+// rs2_val == -131073, 
+// opcode: and ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:-0x20001
+TEST_RR_OP(and, x12, x10, x11, 0xfffdfff6, -0xa, -0x20001, x1, 236, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_3:
+    .fill 60*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S
new file mode 100644
index 000000000..2114d6aee
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S
@@ -0,0 +1,2851 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the andi instruction of the RISC-V E extension for the andi covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",andi)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x14, rd==x11, imm_val == (-2**(12-1)), rs1_val == 8, rs1_val > 0 and imm_val < 0, rs1_val != imm_val, imm_val == -2048
+// opcode: andi ; op1:x14; dest:x11; op1val:0x8;  immval:-0x800
+TEST_IMM_OP( andi, x11, x14, 0x0, 0x8, -0x800, x1, 0, x8)
+
+inst_1:
+// rs1 == rd, rs1==x2, rd==x2, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: andi ; op1:x2; dest:x2; op1val:0x7fffffff;  immval:0x2c
+TEST_IMM_OP( andi, x2, x2, 0x2c, 0x7fffffff, 0x2c, x1, 4, x8)
+
+inst_2:
+// rs1==x10, rd==x5, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0, imm_val == 4
+// opcode: andi ; op1:x10; dest:x5; op1val:-0x40000001;  immval:0x4
+TEST_IMM_OP( andi, x5, x10, 0x4, -0x40000001, 0x4, x1, 8, x8)
+
+inst_3:
+// rs1==x9, rd==x14, rs1_val == -536870913, 
+// opcode: andi ; op1:x9; dest:x14; op1val:-0x20000001;  immval:0x7
+TEST_IMM_OP( andi, x14, x9, 0x7, -0x20000001, 0x7, x1, 12, x8)
+
+inst_4:
+// rs1==x12, rd==x3, rs1_val == -268435457, imm_val == 64
+// opcode: andi ; op1:x12; dest:x3; op1val:-0x10000001;  immval:0x40
+TEST_IMM_OP( andi, x3, x12, 0x40, -0x10000001, 0x40, x1, 16, x8)
+
+inst_5:
+// rs1==x4, rd==x7, rs1_val == -134217729, imm_val == -5, rs1_val < 0 and imm_val < 0
+// opcode: andi ; op1:x4; dest:x7; op1val:-0x8000001;  immval:-0x5
+TEST_IMM_OP( andi, x7, x4, 0xf7fffffb, -0x8000001, -0x5, x1, 20, x8)
+
+inst_6:
+// rs1==x6, rd==x9, rs1_val == -67108865, 
+// opcode: andi ; op1:x6; dest:x9; op1val:-0x4000001;  immval:0x332
+TEST_IMM_OP( andi, x9, x6, 0x332, -0x4000001, 0x332, x1, 24, x8)
+
+inst_7:
+// rs1==x7, rd==x15, rs1_val == -33554433, 
+// opcode: andi ; op1:x7; dest:x15; op1val:-0x2000001;  immval:0x6
+TEST_IMM_OP( andi, x15, x7, 0x6, -0x2000001, 0x6, x1, 28, x9)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_8:
+// rs1==x15, rd==x0, rs1_val == -16777217, imm_val == 2
+// opcode: andi ; op1:x15; dest:x0; op1val:-0x1000001;  immval:0x2
+TEST_IMM_OP( andi, x0, x15, 0, -0x1000001, 0x2, x2, 0, x9)
+
+inst_9:
+// rs1==x3, rd==x6, rs1_val == -8388609, 
+// opcode: andi ; op1:x3; dest:x6; op1val:-0x800001;  immval:0x2
+TEST_IMM_OP( andi, x6, x3, 0x2, -0x800001, 0x2, x2, 4, x9)
+
+inst_10:
+// rs1==x8, rd==x10, rs1_val == -4194305, imm_val == 16
+// opcode: andi ; op1:x8; dest:x10; op1val:-0x400001;  immval:0x10
+TEST_IMM_OP( andi, x10, x8, 0x10, -0x400001, 0x10, x2, 8, x9)
+
+inst_11:
+// rs1==x5, rd==x4, rs1_val == -2097153, imm_val == -65
+// opcode: andi ; op1:x5; dest:x4; op1val:-0x200001;  immval:-0x41
+TEST_IMM_OP( andi, x4, x5, 0xffdfffbf, -0x200001, -0x41, x2, 12, x9)
+
+inst_12:
+// rs1==x13, rd==x1, rs1_val == -1048577, 
+// opcode: andi ; op1:x13; dest:x1; op1val:-0x100001;  immval:0x6
+TEST_IMM_OP( andi, x1, x13, 0x6, -0x100001, 0x6, x2, 16, x9)
+
+inst_13:
+// rs1==x1, rd==x8, rs1_val == -524289, 
+// opcode: andi ; op1:x1; dest:x8; op1val:-0x80001;  immval:-0x4
+TEST_IMM_OP( andi, x8, x1, 0xfff7fffc, -0x80001, -0x4, x2, 20, x9)
+
+inst_14:
+// rs1==x11, rd==x12, rs1_val == -262145, imm_val == (2**(12-1)-1), imm_val == 2047
+// opcode: andi ; op1:x11; dest:x12; op1val:-0x40001;  immval:0x7ff
+TEST_IMM_OP( andi, x12, x11, 0x7ff, -0x40001, 0x7ff, x2, 24, x9)
+
+inst_15:
+// rs1==x0, rd==x13, rs1_val == -131073, imm_val == 1365
+// opcode: andi ; op1:x0; dest:x13; op1val:0x0;  immval:0x555
+TEST_IMM_OP( andi, x13, x0, 0x0, 0x0, 0x555, x2, 28, x1)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x10001;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x334, -0x10001, 0x334, x2, 32, x1)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, -0x8001, 0x3, x2, 36, x1)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x4001, 0x2, x2, 40, x1)
+
+inst_19:
+// rs1_val == -8193, imm_val == 512
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x200
+TEST_IMM_OP( andi, x11, x10, 0x200, -0x2001, 0x200, x2, 44, x1)
+
+inst_20:
+// rs1_val == -4097, imm_val == -1366
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xffffeaaa, -0x1001, -0x556, x2, 48, x1)
+
+inst_21:
+// rs1_val == -2049, imm_val == 8
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x801;  immval:0x8
+TEST_IMM_OP( andi, x11, x10, 0x8, -0x801, 0x8, x2, 52, x1)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x401;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x332, -0x401, 0x332, x2, 56, x1)
+
+inst_23:
+// rs1_val == -513, imm_val == 128
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x201;  immval:0x80
+TEST_IMM_OP( andi, x11, x10, 0x80, -0x201, 0x80, x2, 60, x1)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x101;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, -0x101, 0x3, x2, 64, x1)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x81;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x2d, -0x81, 0x2d, x2, 68, x1)
+
+inst_26:
+// rs1_val == -65, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x41;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xffffff93, -0x41, -0x2d, x2, 72, x1)
+
+inst_27:
+// rs1_val == -33, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x21;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xffffffd3, -0x21, -0x2d, x2, 76, x1)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x11;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xfffffaaa, -0x11, -0x556, x2, 80, x1)
+
+inst_29:
+// rs1_val == -9, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x9;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x334, -0x9, 0x334, x2, 84, x1)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x5;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x1, -0x5, 0x5, x2, 88, x1)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x3;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, -0x3, 0x4, x2, 92, x1)
+
+inst_32:
+// rs1_val == -2, imm_val == -1025
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x2;  immval:-0x401
+TEST_IMM_OP( andi, x11, x10, 0xfffffbfe, -0x2, -0x401, x2, 96, x1)
+
+inst_33:
+// imm_val == -513, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x201
+TEST_IMM_OP( andi, x11, x10, 0x66666465, 0x66666665, -0x201, x2, 100, x1)
+
+inst_34:
+// imm_val == -257, rs1_val == 33554432
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2000000;  immval:-0x101
+TEST_IMM_OP( andi, x11, x10, 0x2000000, 0x2000000, -0x101, x2, 104, x1)
+
+inst_35:
+// imm_val == -129, rs1_val == 65536
+// opcode: andi ; op1:x10; dest:x11; op1val:0x10000;  immval:-0x81
+TEST_IMM_OP( andi, x11, x10, 0x10000, 0x10000, -0x81, x2, 108, x1)
+
+inst_36:
+// imm_val == -33, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x8;  immval:-0x21
+TEST_IMM_OP( andi, x11, x10, 0x8, 0x8, -0x21, x2, 112, x1)
+
+inst_37:
+// imm_val == -17, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x11
+TEST_IMM_OP( andi, x11, x10, 0x55555546, 0x55555556, -0x11, x2, 116, x1)
+
+inst_38:
+// imm_val == -9, rs1_val == 524288
+// opcode: andi ; op1:x10; dest:x11; op1val:0x80000;  immval:-0x9
+TEST_IMM_OP( andi, x11, x10, 0x80000, 0x80000, -0x9, x2, 120, x1)
+
+inst_39:
+// imm_val == -3, rs1_val == 1
+// opcode: andi ; op1:x10; dest:x11; op1val:0x1;  immval:-0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x1, -0x3, x2, 124, x1)
+
+inst_40:
+// imm_val == -2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, -0x2, x2, 128, x1)
+
+inst_41:
+// rs1_val == -2147483648, imm_val == 0, rs1_val == (-2**(xlen-1))
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x80000000, 0x0, x2, 132, x1)
+
+inst_42:
+// rs1_val == 1073741824, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x7ff
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x40000000, 0x7ff, x2, 136, x1)
+
+inst_43:
+// rs1_val == 536870912, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x7ff
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x20000000, 0x7ff, x2, 140, x1)
+
+inst_44:
+// rs1_val == 268435456, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x7
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x10000000, 0x7, x2, 144, x1)
+
+inst_45:
+// rs1_val == 134217728, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x8000000;  immval:0x200
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x8000000, 0x200, x2, 148, x1)
+
+inst_46:
+// rs1_val == 67108864, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4000000;  immval:-0x201
+TEST_IMM_OP( andi, x11, x10, 0x4000000, 0x4000000, -0x201, x2, 152, x1)
+
+inst_47:
+// rs1_val == 16777216, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x1000000;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x1000000, 0x2, x2, 156, x1)
+
+inst_48:
+// rs1_val == 8388608, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x800000;  immval:-0x401
+TEST_IMM_OP( andi, x11, x10, 0x800000, 0x800000, -0x401, x2, 160, x1)
+
+inst_49:
+// rs1_val == 4194304, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x400000;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x400000, 0x0, x2, 164, x1)
+
+inst_50:
+// rs1_val == 2097152, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x200000;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x200000, 0x0, x2, 168, x1)
+
+inst_51:
+// rs1_val == 1048576, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x100000;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x100000, 0x4, x2, 172, x1)
+
+inst_52:
+// rs1_val == 262144, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x40000;  immval:-0x7
+TEST_IMM_OP( andi, x11, x10, 0x40000, 0x40000, -0x7, x2, 176, x1)
+
+inst_53:
+// rs1_val == 131072, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x20000;  immval:-0x5
+TEST_IMM_OP( andi, x11, x10, 0x20000, 0x20000, -0x5, x2, 180, x1)
+
+inst_54:
+// rs1_val == 32768, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x8000;  immval:-0x81
+TEST_IMM_OP( andi, x11, x10, 0x8000, 0x8000, -0x81, x2, 184, x1)
+
+inst_55:
+// rs1_val == 16384, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4000;  immval:-0x7
+TEST_IMM_OP( andi, x11, x10, 0x4000, 0x4000, -0x7, x2, 188, x1)
+
+inst_56:
+// rs1_val == 8192, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2000;  immval:0x7ff
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2000, 0x7ff, x2, 192, x1)
+
+inst_57:
+// rs1_val == 4096, imm_val == 32
+// opcode: andi ; op1:x10; dest:x11; op1val:0x1000;  immval:0x20
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x1000, 0x20, x2, 196, x1)
+
+inst_58:
+// rs1_val == 2048, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x800;  immval:-0x41
+TEST_IMM_OP( andi, x11, x10, 0x800, 0x800, -0x41, x2, 200, x1)
+
+inst_59:
+// rs1_val == 1024, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x400;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x400, 0x400, 0x666, x2, 204, x1)
+
+inst_60:
+// rs1_val == 512, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x200;  immval:-0x3
+TEST_IMM_OP( andi, x11, x10, 0x200, 0x200, -0x3, x2, 208, x1)
+
+inst_61:
+// rs1_val == 256, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x100;  immval:-0x6
+TEST_IMM_OP( andi, x11, x10, 0x100, 0x100, -0x6, x2, 212, x1)
+
+inst_62:
+// rs1_val == 128, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x80;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x80, 0x554, x2, 216, x1)
+
+inst_63:
+// rs1_val == 64, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x40;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x40, 0x40, 0x556, x2, 220, x1)
+
+inst_64:
+// rs1_val == 32, imm_val == 1024
+// opcode: andi ; op1:x10; dest:x11; op1val:0x20;  immval:0x400
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x20, 0x400, x2, 224, x1)
+
+inst_65:
+// rs1_val == 16, imm_val == 256
+// opcode: andi ; op1:x10; dest:x11; op1val:0x10;  immval:0x100
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x10, 0x100, x2, 228, x1)
+
+inst_66:
+// rs1_val == 4, rs1_val==4 and imm_val==1638
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x666, x2, 232, x1)
+
+inst_67:
+// rs1_val == 2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x10
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x10, x2, 236, x1)
+
+inst_68:
+// imm_val == 1, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x1
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x66666665, 0x1, x2, 240, x1)
+
+inst_69:
+// rs1_val==46341 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb505, 0x2e, x2, 244, x1)
+
+inst_70:
+// rs1_val==46341 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xb504, 0xb505, -0x2c, x2, 248, x1)
+
+inst_71:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x405, 0xb505, 0x667, x2, 252, x1)
+
+inst_72:
+// rs1_val==46341 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x104, 0xb505, 0x334, x2, 256, x1)
+
+inst_73:
+// rs1_val==46341 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb505, 0x6, x2, 260, x1)
+
+inst_74:
+// rs1_val==46341 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xb001, 0xb505, -0x555, x2, 264, x1)
+
+inst_75:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x504, 0xb505, 0x556, x2, 268, x1)
+
+inst_76:
+// rs1_val==46341 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb505, 0x4, x2, 272, x1)
+
+inst_77:
+// rs1_val==46341 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb505, 0x2c, x2, 276, x1)
+
+inst_78:
+// rs1_val==46341 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb505, 0x0, x2, 280, x1)
+
+inst_79:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x405, 0xb505, 0x665, x2, 284, x1)
+
+inst_80:
+// rs1_val==46341 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x100, 0xb505, 0x332, x2, 288, x1)
+
+inst_81:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x504, 0xb505, 0x554, x2, 292, x1)
+
+inst_82:
+// rs1_val==46341 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb505, 0x2, x2, 296, x1)
+
+inst_83:
+// rs1_val==46341 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x5, 0xb505, 0x2d, x2, 300, x1)
+
+inst_84:
+// rs1_val==46341 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xb501, 0xb505, -0x2d, x2, 304, x1)
+
+inst_85:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x404, 0xb505, 0x666, x2, 308, x1)
+
+inst_86:
+// rs1_val==46341 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x101, 0xb505, 0x333, x2, 312, x1)
+
+inst_87:
+// rs1_val==46341 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, 0xb505, 0x5, x2, 316, x1)
+
+inst_88:
+// rs1_val==46341 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xb000, 0xb505, -0x556, x2, 320, x1)
+
+inst_89:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x505, 0xb505, 0x555, x2, 324, x1)
+
+inst_90:
+// rs1_val==46341 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, 0xb505, 0x3, x2, 328, x1)
+
+inst_91:
+// rs1_val==-46339 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2c, -0xb503, 0x2e, x2, 332, x1)
+
+inst_92:
+// rs1_val==-46339 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xffff4ad4, -0xb503, -0x2c, x2, 336, x1)
+
+inst_93:
+// rs1_val==-46339 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x265, -0xb503, 0x667, x2, 340, x1)
+
+inst_94:
+// rs1_val==-46339 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x234, -0xb503, 0x334, x2, 344, x1)
+
+inst_95:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, -0xb503, 0x6, x2, 348, x1)
+
+inst_96:
+// rs1_val==-46339 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xffff4aa9, -0xb503, -0x555, x2, 352, x1)
+
+inst_97:
+// rs1_val==-46339 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x54, -0xb503, 0x556, x2, 356, x1)
+
+inst_98:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, -0xb503, 0x4, x2, 360, x1)
+
+inst_99:
+// rs1_val==-46339 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x2c, -0xb503, 0x2c, x2, 364, x1)
+
+inst_100:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, -0xb503, 0x0, x2, 368, x1)
+
+inst_101:
+// rs1_val==-46339 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x265, -0xb503, 0x665, x2, 372, x1)
+
+inst_102:
+// rs1_val==-46339 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x230, -0xb503, 0x332, x2, 376, x1)
+
+inst_103:
+// rs1_val==-46339 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x54, -0xb503, 0x554, x2, 380, x1)
+
+inst_104:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, -0xb503, 0x2, x2, 384, x1)
+
+inst_105:
+// rs1_val==-46339 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x2d, -0xb503, 0x2d, x2, 388, x1)
+
+inst_106:
+// rs1_val==-46339 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xffff4ad1, -0xb503, -0x2d, x2, 392, x1)
+
+inst_107:
+// rs1_val==-46339 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x264, -0xb503, 0x666, x2, 396, x1)
+
+inst_108:
+// rs1_val==-46339 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x231, -0xb503, 0x333, x2, 400, x1)
+
+inst_109:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, -0xb503, 0x5, x2, 404, x1)
+
+inst_110:
+// rs1_val==-46339 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xffff4aa8, -0xb503, -0x556, x2, 408, x1)
+
+inst_111:
+// rs1_val==-46339 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x55, -0xb503, 0x555, x2, 412, x1)
+
+inst_112:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, -0xb503, 0x3, x2, 416, x1)
+
+inst_113:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x26, 0x66666667, 0x2e, x2, 420, x1)
+
+inst_114:
+// rs1_val==1717986919 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x66666644, 0x66666667, -0x2c, x2, 424, x1)
+
+inst_115:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x667, 0x66666667, 0x667, x2, 428, x1)
+
+inst_116:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x66666667, 0x334, x2, 432, x1)
+
+inst_117:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x66666667, 0x6, x2, 436, x1)
+
+inst_118:
+// rs1_val==1717986919 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x66666223, 0x66666667, -0x555, x2, 440, x1)
+
+inst_119:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x446, 0x66666667, 0x556, x2, 444, x1)
+
+inst_120:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x66666667, 0x4, x2, 448, x1)
+
+inst_121:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x66666667, 0x2c, x2, 452, x1)
+
+inst_122:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x66666667, 0x0, x2, 456, x1)
+
+inst_123:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x665, 0x66666667, 0x665, x2, 460, x1)
+
+inst_124:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x66666667, 0x332, x2, 464, x1)
+
+inst_125:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x66666667, 0x554, x2, 468, x1)
+
+inst_126:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x66666667, 0x2, x2, 472, x1)
+
+inst_127:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x25, 0x66666667, 0x2d, x2, 476, x1)
+
+inst_128:
+// rs1_val==1717986919 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x66666643, 0x66666667, -0x2d, x2, 480, x1)
+
+inst_129:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x666, 0x66666667, 0x666, x2, 484, x1)
+
+inst_130:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x223, 0x66666667, 0x333, x2, 488, x1)
+
+inst_131:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x66666667, 0x5, x2, 492, x1)
+
+inst_132:
+// rs1_val==1717986919 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x66666222, 0x66666667, -0x556, x2, 496, x1)
+
+inst_133:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x445, 0x66666667, 0x555, x2, 500, x1)
+
+inst_134:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x66666667, 0x3, x2, 504, x1)
+
+inst_135:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x33333334, 0x2e, x2, 508, x1)
+
+inst_136:
+// rs1_val==858993460 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x33333314, 0x33333334, -0x2c, x2, 512, x1)
+
+inst_137:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x33333334, 0x667, x2, 516, x1)
+
+inst_138:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x334, 0x33333334, 0x334, x2, 520, x1)
+
+inst_139:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x33333334, 0x6, x2, 524, x1)
+
+inst_140:
+// rs1_val==858993460 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x33333220, 0x33333334, -0x555, x2, 528, x1)
+
+inst_141:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x33333334, 0x556, x2, 532, x1)
+
+inst_142:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x33333334, 0x4, x2, 536, x1)
+
+inst_143:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x33333334, 0x2c, x2, 540, x1)
+
+inst_144:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333334, 0x0, x2, 544, x1)
+
+inst_145:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x33333334, 0x665, x2, 548, x1)
+
+inst_146:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x330, 0x33333334, 0x332, x2, 552, x1)
+
+inst_147:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x33333334, 0x554, x2, 556, x1)
+
+inst_148:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333334, 0x2, x2, 560, x1)
+
+inst_149:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x33333334, 0x2d, x2, 564, x1)
+
+inst_150:
+// rs1_val==858993460 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x33333310, 0x33333334, -0x2d, x2, 568, x1)
+
+inst_151:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x33333334, 0x666, x2, 572, x1)
+
+inst_152:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x330, 0x33333334, 0x333, x2, 576, x1)
+
+inst_153:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x33333334, 0x5, x2, 580, x1)
+
+inst_154:
+// rs1_val==858993460 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x33333220, 0x33333334, -0x556, x2, 584, x1)
+
+inst_155:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x33333334, 0x555, x2, 588, x1)
+
+inst_156:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333334, 0x3, x2, 592, x1)
+
+inst_157:
+// rs1_val==6 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x6, 0x2e, x2, 596, x1)
+
+inst_158:
+// rs1_val==6 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, -0x2c, x2, 600, x1)
+
+inst_159:
+// rs1_val==6 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x6, 0x667, x2, 604, x1)
+
+inst_160:
+// rs1_val==6 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x334, x2, 608, x1)
+
+inst_161:
+// rs1_val==6 and imm_val==6, rs1_val == imm_val
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x6, 0x6, x2, 612, x1)
+
+inst_162:
+// rs1_val==6 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, -0x555, x2, 616, x1)
+
+inst_163:
+// rs1_val==6 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x6, 0x556, x2, 620, x1)
+
+inst_164:
+// rs1_val==6 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x4, x2, 624, x1)
+
+inst_165:
+// rs1_val==6 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x2c, x2, 628, x1)
+
+inst_166:
+// rs1_val==6 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x6, 0x0, x2, 632, x1)
+
+inst_167:
+// rs1_val==6 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x665, x2, 636, x1)
+
+inst_168:
+// rs1_val==6 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, 0x332, x2, 640, x1)
+
+inst_169:
+// rs1_val==6 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x554, x2, 644, x1)
+
+inst_170:
+// rs1_val==6 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, 0x2, x2, 648, x1)
+
+inst_171:
+// rs1_val==6 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x2d, x2, 652, x1)
+
+inst_172:
+// rs1_val==6 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, -0x2d, x2, 656, x1)
+
+inst_173:
+// rs1_val==6 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x6, 0x666, x2, 660, x1)
+
+inst_174:
+// rs1_val==6 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, 0x333, x2, 664, x1)
+
+inst_175:
+// rs1_val==6 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x5, x2, 668, x1)
+
+inst_176:
+// rs1_val==6 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, -0x556, x2, 672, x1)
+
+inst_177:
+// rs1_val==6 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x6, 0x555, x2, 676, x1)
+
+inst_178:
+// rs1_val==6 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x6, 0x3, x2, 680, x1)
+
+inst_179:
+// rs1_val==-1431655765 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2a, -0x55555555, 0x2e, x2, 684, x1)
+
+inst_180:
+// rs1_val==-1431655765 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaa80, -0x55555555, -0x2c, x2, 688, x1)
+
+inst_181:
+// rs1_val==-1431655765 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x223, -0x55555555, 0x667, x2, 692, x1)
+
+inst_182:
+// rs1_val==-1431655765 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x220, -0x55555555, 0x334, x2, 696, x1)
+
+inst_183:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555555, 0x6, x2, 700, x1)
+
+inst_184:
+// rs1_val==-1431655765 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaaab, -0x55555555, -0x555, x2, 704, x1)
+
+inst_185:
+// rs1_val==-1431655765 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555555, 0x556, x2, 708, x1)
+
+inst_186:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555555, 0x4, x2, 712, x1)
+
+inst_187:
+// rs1_val==-1431655765 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x28, -0x55555555, 0x2c, x2, 716, x1)
+
+inst_188:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555555, 0x0, x2, 720, x1)
+
+inst_189:
+// rs1_val==-1431655765 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x221, -0x55555555, 0x665, x2, 724, x1)
+
+inst_190:
+// rs1_val==-1431655765 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555555, 0x332, x2, 728, x1)
+
+inst_191:
+// rs1_val==-1431655765 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555555, 0x554, x2, 732, x1)
+
+inst_192:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555555, 0x2, x2, 736, x1)
+
+inst_193:
+// rs1_val==-1431655765 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x29, -0x55555555, 0x2d, x2, 740, x1)
+
+inst_194:
+// rs1_val==-1431655765 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaa83, -0x55555555, -0x2d, x2, 744, x1)
+
+inst_195:
+// rs1_val==-1431655765 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555555, 0x666, x2, 748, x1)
+
+inst_196:
+// rs1_val==-1431655765 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x223, -0x55555555, 0x333, x2, 752, x1)
+
+inst_197:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x1, -0x55555555, 0x5, x2, 756, x1)
+
+inst_198:
+// rs1_val==-1431655765 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaaaa, -0x55555555, -0x556, x2, 760, x1)
+
+inst_199:
+// rs1_val==-1431655765 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x1, -0x55555555, 0x555, x2, 764, x1)
+
+inst_200:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, -0x55555555, 0x3, x2, 768, x1)
+
+inst_201:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x55555556, 0x2e, x2, 772, x1)
+
+inst_202:
+// rs1_val==1431655766 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x55555554, 0x55555556, -0x2c, x2, 776, x1)
+
+inst_203:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x446, 0x55555556, 0x667, x2, 780, x1)
+
+inst_204:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x55555556, 0x334, x2, 784, x1)
+
+inst_205:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x55555556, 0x6, x2, 788, x1)
+
+inst_206:
+// rs1_val==1431655766 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x55555002, 0x55555556, -0x555, x2, 792, x1)
+
+inst_207:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x556, 0x55555556, 0x556, x2, 796, x1)
+
+inst_208:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555556, 0x4, x2, 800, x1)
+
+inst_209:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555556, 0x2c, x2, 804, x1)
+
+inst_210:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555556, 0x0, x2, 808, x1)
+
+inst_211:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x55555556, 0x665, x2, 812, x1)
+
+inst_212:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x112, 0x55555556, 0x332, x2, 816, x1)
+
+inst_213:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555556, 0x554, x2, 820, x1)
+
+inst_214:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x55555556, 0x2, x2, 824, x1)
+
+inst_215:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555556, 0x2d, x2, 828, x1)
+
+inst_216:
+// rs1_val==1431655766 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x55555552, 0x55555556, -0x2d, x2, 832, x1)
+
+inst_217:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x446, 0x55555556, 0x666, x2, 836, x1)
+
+inst_218:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x112, 0x55555556, 0x333, x2, 840, x1)
+
+inst_219:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555556, 0x5, x2, 844, x1)
+
+inst_220:
+// rs1_val==1431655766 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x55555002, 0x55555556, -0x556, x2, 848, x1)
+
+inst_221:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555556, 0x555, x2, 852, x1)
+
+inst_222:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x55555556, 0x3, x2, 856, x1)
+
+inst_223:
+// rs1_val==4 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x2e, x2, 860, x1)
+
+inst_224:
+// rs1_val==4 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, -0x2c, x2, 864, x1)
+
+inst_225:
+// rs1_val==4 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x667, x2, 868, x1)
+
+inst_226:
+// rs1_val==4 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x334, x2, 872, x1)
+
+inst_227:
+// rs1_val==4 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x6, x2, 876, x1)
+
+inst_228:
+// rs1_val==4 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, -0x555, x2, 880, x1)
+
+inst_229:
+// rs1_val==4 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x556, x2, 884, x1)
+
+inst_230:
+// rs1_val==4 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x4, x2, 888, x1)
+
+inst_231:
+// rs1_val==4 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x2c, x2, 892, x1)
+
+inst_232:
+// rs1_val==4 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, 0x0, x2, 896, x1)
+
+inst_233:
+// rs1_val==4 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x665, x2, 900, x1)
+
+inst_234:
+// rs1_val==4 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, 0x332, x2, 904, x1)
+
+inst_235:
+// rs1_val==4 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x554, x2, 908, x1)
+
+inst_236:
+// rs1_val==4 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, 0x2, x2, 912, x1)
+
+inst_237:
+// rs1_val==4 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x2d, x2, 916, x1)
+
+inst_238:
+// rs1_val==4 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, -0x2d, x2, 920, x1)
+
+inst_239:
+// rs1_val==4 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, 0x333, x2, 924, x1)
+
+inst_240:
+// rs1_val==4 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x5, x2, 928, x1)
+
+inst_241:
+// rs1_val==4 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, -0x556, x2, 932, x1)
+
+inst_242:
+// rs1_val==4 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x4, 0x555, x2, 936, x1)
+
+inst_243:
+// rs1_val==4 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x4, 0x3, x2, 940, x1)
+
+inst_244:
+// rs1_val==46339 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2, 0xb503, 0x2e, x2, 944, x1)
+
+inst_245:
+// rs1_val==46339 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xb500, 0xb503, -0x2c, x2, 948, x1)
+
+inst_246:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x403, 0xb503, 0x667, x2, 952, x1)
+
+inst_247:
+// rs1_val==46339 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x100, 0xb503, 0x334, x2, 956, x1)
+
+inst_248:
+// rs1_val==46339 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, 0xb503, 0x6, x2, 960, x1)
+
+inst_249:
+// rs1_val==46339 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xb003, 0xb503, -0x555, x2, 964, x1)
+
+inst_250:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x502, 0xb503, 0x556, x2, 968, x1)
+
+inst_251:
+// rs1_val==46339 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb503, 0x4, x2, 972, x1)
+
+inst_252:
+// rs1_val==46339 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb503, 0x2c, x2, 976, x1)
+
+inst_253:
+// rs1_val==46339 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb503, 0x0, x2, 980, x1)
+
+inst_254:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x401, 0xb503, 0x665, x2, 984, x1)
+
+inst_255:
+// rs1_val==46339 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x102, 0xb503, 0x332, x2, 988, x1)
+
+inst_256:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x500, 0xb503, 0x554, x2, 992, x1)
+
+inst_257:
+// rs1_val==46339 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0xb503, 0x2, x2, 996, x1)
+
+inst_258:
+// rs1_val==46339 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x1, 0xb503, 0x2d, x2, 1000, x1)
+
+inst_259:
+// rs1_val==46339 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xb503, 0xb503, -0x2d, x2, 1004, x1)
+
+inst_260:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x402, 0xb503, 0x666, x2, 1008, x1)
+
+inst_261:
+// rs1_val==46339 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x103, 0xb503, 0x333, x2, 1012, x1)
+
+inst_262:
+// rs1_val==46339 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x1, 0xb503, 0x5, x2, 1016, x1)
+
+inst_263:
+// rs1_val==46339 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xb002, 0xb503, -0x556, x2, 1020, x1)
+
+inst_264:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x501, 0xb503, 0x555, x2, 1024, x1)
+
+inst_265:
+// rs1_val==46339 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, 0xb503, 0x3, x2, 1028, x1)
+
+inst_266:
+// rs1_val==0 and imm_val==46, rs1_val == 0
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x2e, x2, 1032, x1)
+
+inst_267:
+// rs1_val==0 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, -0x2c, x2, 1036, x1)
+
+inst_268:
+// rs1_val==0 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x667, x2, 1040, x1)
+
+inst_269:
+// rs1_val==0 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x334, x2, 1044, x1)
+
+inst_270:
+// rs1_val==0 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x6, x2, 1048, x1)
+
+inst_271:
+// rs1_val==0 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, -0x555, x2, 1052, x1)
+
+inst_272:
+// rs1_val==0 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x556, x2, 1056, x1)
+
+inst_273:
+// rs1_val==0 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x4, x2, 1060, x1)
+
+inst_274:
+// rs1_val==0 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x2c, x2, 1064, x1)
+
+inst_275:
+// rs1_val==0 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x0, x2, 1068, x1)
+
+inst_276:
+// rs1_val==0 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x665, x2, 1072, x1)
+
+inst_277:
+// rs1_val==0 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x332, x2, 1076, x1)
+
+inst_278:
+// rs1_val==0 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x554, x2, 1080, x1)
+
+inst_279:
+// rs1_val==0 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x2, x2, 1084, x1)
+
+inst_280:
+// rs1_val==0 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x2d, x2, 1088, x1)
+
+inst_281:
+// rs1_val==0 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, -0x2d, x2, 1092, x1)
+
+inst_282:
+// rs1_val==0 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x666, x2, 1096, x1)
+
+inst_283:
+// rs1_val==0 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x333, x2, 1100, x1)
+
+inst_284:
+// rs1_val==0 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x5, x2, 1104, x1)
+
+inst_285:
+// rs1_val==0 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, -0x556, x2, 1108, x1)
+
+inst_286:
+// rs1_val==0 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x555, x2, 1112, x1)
+
+inst_287:
+// rs1_val==0 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x0, 0x3, x2, 1116, x1)
+
+inst_288:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x66666665, 0x2e, x2, 1120, x1)
+
+inst_289:
+// rs1_val==1717986917 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x66666644, 0x66666665, -0x2c, x2, 1124, x1)
+
+inst_290:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x665, 0x66666665, 0x667, x2, 1128, x1)
+
+inst_291:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x66666665, 0x334, x2, 1132, x1)
+
+inst_292:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x66666665, 0x6, x2, 1136, x1)
+
+inst_293:
+// rs1_val==1717986917 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x66666221, 0x66666665, -0x555, x2, 1140, x1)
+
+inst_294:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x66666665, 0x556, x2, 1144, x1)
+
+inst_295:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x66666665, 0x4, x2, 1148, x1)
+
+inst_296:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x66666665, 0x2c, x2, 1152, x1)
+
+inst_297:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x66666665, 0x0, x2, 1156, x1)
+
+inst_298:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x665, 0x66666665, 0x665, x2, 1160, x1)
+
+inst_299:
+// rs1_val==-1431655766 and imm_val==-1365, rs1_val == -1431655766
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaaaa, -0x55555556, -0x555, x2, 1164, x1)
+
+inst_300:
+// rs1_val==-1431655766 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555556, 0x556, x2, 1168, x1)
+
+inst_301:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555556, 0x4, x2, 1172, x1)
+
+inst_302:
+// rs1_val==-1431655766 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x28, -0x55555556, 0x2c, x2, 1176, x1)
+
+inst_303:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555556, 0x0, x2, 1180, x1)
+
+inst_304:
+// rs1_val==-1431655766 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x220, -0x55555556, 0x665, x2, 1184, x1)
+
+inst_305:
+// rs1_val==-1431655766 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555556, 0x332, x2, 1188, x1)
+
+inst_306:
+// rs1_val==-1431655766 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555556, 0x554, x2, 1192, x1)
+
+inst_307:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555556, 0x2, x2, 1196, x1)
+
+inst_308:
+// rs1_val==-1431655766 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x28, -0x55555556, 0x2d, x2, 1200, x1)
+
+inst_309:
+// rs1_val==-1431655766 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaa82, -0x55555556, -0x2d, x2, 1204, x1)
+
+inst_310:
+// rs1_val==-1431655766 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555556, 0x666, x2, 1208, x1)
+
+inst_311:
+// rs1_val==-1431655766 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555556, 0x333, x2, 1212, x1)
+
+inst_312:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555556, 0x5, x2, 1216, x1)
+
+inst_313:
+// rs1_val==-1431655766 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaaaa, -0x55555556, -0x556, x2, 1220, x1)
+
+inst_314:
+// rs1_val==-1431655766 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x0, -0x55555556, 0x555, x2, 1224, x1)
+
+inst_315:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555556, 0x3, x2, 1228, x1)
+
+inst_316:
+// rs1_val==1431655765 and imm_val==46, rs1_val == 1431655765
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555555, 0x2e, x2, 1232, x1)
+
+inst_317:
+// rs1_val==1431655765 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x55555554, 0x55555555, -0x2c, x2, 1236, x1)
+
+inst_318:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x445, 0x55555555, 0x667, x2, 1240, x1)
+
+inst_319:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x55555555, 0x334, x2, 1244, x1)
+
+inst_320:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555555, 0x6, x2, 1248, x1)
+
+inst_321:
+// rs1_val==1431655765 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x55555001, 0x55555555, -0x555, x2, 1252, x1)
+
+inst_322:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555555, 0x556, x2, 1256, x1)
+
+inst_323:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555555, 0x4, x2, 1260, x1)
+
+inst_324:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555555, 0x2c, x2, 1264, x1)
+
+inst_325:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555555, 0x0, x2, 1268, x1)
+
+inst_326:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x445, 0x55555555, 0x665, x2, 1272, x1)
+
+inst_327:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x55555555, 0x332, x2, 1276, x1)
+
+inst_328:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555555, 0x554, x2, 1280, x1)
+
+inst_329:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555555, 0x2, x2, 1284, x1)
+
+inst_330:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x55555555, 0x2d, x2, 1288, x1)
+
+inst_331:
+// rs1_val==1431655765 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x55555551, 0x55555555, -0x2d, x2, 1292, x1)
+
+inst_332:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x55555555, 0x666, x2, 1296, x1)
+
+inst_333:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x111, 0x55555555, 0x333, x2, 1300, x1)
+
+inst_334:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x55555555, 0x5, x2, 1304, x1)
+
+inst_335:
+// rs1_val==1431655765 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x55555000, 0x55555555, -0x556, x2, 1308, x1)
+
+inst_336:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x555, 0x55555555, 0x555, x2, 1312, x1)
+
+inst_337:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x55555555, 0x3, x2, 1316, x1)
+
+inst_338:
+// rs1_val==3 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x2e, x2, 1320, x1)
+
+inst_339:
+// rs1_val==3 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, -0x2c, x2, 1324, x1)
+
+inst_340:
+// rs1_val==3 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x3, 0x667, x2, 1328, x1)
+
+inst_341:
+// rs1_val==3 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, 0x334, x2, 1332, x1)
+
+inst_342:
+// rs1_val==3 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x6, x2, 1336, x1)
+
+inst_343:
+// rs1_val==3 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x3, -0x555, x2, 1340, x1)
+
+inst_344:
+// rs1_val==3 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x556, x2, 1344, x1)
+
+inst_345:
+// rs1_val==3 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, 0x4, x2, 1348, x1)
+
+inst_346:
+// rs1_val==3 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, 0x2c, x2, 1352, x1)
+
+inst_347:
+// rs1_val==3 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, 0x0, x2, 1356, x1)
+
+inst_348:
+// rs1_val==3 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x3, 0x665, x2, 1360, x1)
+
+inst_349:
+// rs1_val==3 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x332, x2, 1364, x1)
+
+inst_350:
+// rs1_val==3 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x3, 0x554, x2, 1368, x1)
+
+inst_351:
+// rs1_val==3 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x2, x2, 1372, x1)
+
+inst_352:
+// rs1_val==3 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x3, 0x2d, x2, 1376, x1)
+
+inst_353:
+// rs1_val==3 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x3, -0x2d, x2, 1380, x1)
+
+inst_354:
+// rs1_val==3 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, 0x666, x2, 1384, x1)
+
+inst_355:
+// rs1_val==3 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x3, 0x333, x2, 1388, x1)
+
+inst_356:
+// rs1_val==3 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x3, 0x5, x2, 1392, x1)
+
+inst_357:
+// rs1_val==3 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x3, -0x556, x2, 1396, x1)
+
+inst_358:
+// rs1_val==3 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x3, 0x555, x2, 1400, x1)
+
+inst_359:
+// rs1_val==3 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x3, 0x3, x2, 1404, x1)
+
+inst_360:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x220, 0x66666665, 0x332, x2, 1408, x1)
+
+inst_361:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x66666665, 0x554, x2, 1412, x1)
+
+inst_362:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x66666665, 0x2, x2, 1416, x1)
+
+inst_363:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x25, 0x66666665, 0x2d, x2, 1420, x1)
+
+inst_364:
+// rs1_val==1717986917 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x66666641, 0x66666665, -0x2d, x2, 1424, x1)
+
+inst_365:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x664, 0x66666665, 0x666, x2, 1428, x1)
+
+inst_366:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x221, 0x66666665, 0x333, x2, 1432, x1)
+
+inst_367:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x66666665, 0x5, x2, 1436, x1)
+
+inst_368:
+// rs1_val==1717986917 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x66666220, 0x66666665, -0x556, x2, 1440, x1)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x445, 0x66666665, 0x555, x2, 1444, x1)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x66666665, 0x3, x2, 1448, x1)
+
+inst_371:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x22, 0x33333332, 0x2e, x2, 1452, x1)
+
+inst_372:
+// rs1_val==858993458 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x33333310, 0x33333332, -0x2c, x2, 1456, x1)
+
+inst_373:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x33333332, 0x667, x2, 1460, x1)
+
+inst_374:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x330, 0x33333332, 0x334, x2, 1464, x1)
+
+inst_375:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x33333332, 0x6, x2, 1468, x1)
+
+inst_376:
+// rs1_val==858993458 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x33333222, 0x33333332, -0x555, x2, 1472, x1)
+
+inst_377:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x112, 0x33333332, 0x556, x2, 1476, x1)
+
+inst_378:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333332, 0x4, x2, 1480, x1)
+
+inst_379:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x20, 0x33333332, 0x2c, x2, 1484, x1)
+
+inst_380:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333332, 0x0, x2, 1488, x1)
+
+inst_381:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x220, 0x33333332, 0x665, x2, 1492, x1)
+
+inst_382:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x332, 0x33333332, 0x332, x2, 1496, x1)
+
+inst_383:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x33333332, 0x554, x2, 1500, x1)
+
+inst_384:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x33333332, 0x2, x2, 1504, x1)
+
+inst_385:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x20, 0x33333332, 0x2d, x2, 1508, x1)
+
+inst_386:
+// rs1_val==858993458 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x33333312, 0x33333332, -0x2d, x2, 1512, x1)
+
+inst_387:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x33333332, 0x666, x2, 1516, x1)
+
+inst_388:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x332, 0x33333332, 0x333, x2, 1520, x1)
+
+inst_389:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333332, 0x5, x2, 1524, x1)
+
+inst_390:
+// rs1_val==858993458 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x33333222, 0x33333332, -0x556, x2, 1528, x1)
+
+inst_391:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x33333332, 0x555, x2, 1532, x1)
+
+inst_392:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x33333332, 0x3, x2, 1536, x1)
+
+inst_393:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x2e, x2, 1540, x1)
+
+inst_394:
+// rs1_val==1431655764 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x55555554, 0x55555554, -0x2c, x2, 1544, x1)
+
+inst_395:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x55555554, 0x667, x2, 1548, x1)
+
+inst_396:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x114, 0x55555554, 0x334, x2, 1552, x1)
+
+inst_397:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x6, x2, 1556, x1)
+
+inst_398:
+// rs1_val==1431655764 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x55555000, 0x55555554, -0x555, x2, 1560, x1)
+
+inst_399:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555554, 0x556, x2, 1564, x1)
+
+inst_400:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x4, x2, 1568, x1)
+
+inst_401:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x2c, x2, 1572, x1)
+
+inst_402:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555554, 0x0, x2, 1576, x1)
+
+inst_403:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x55555554, 0x665, x2, 1580, x1)
+
+inst_404:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x55555554, 0x332, x2, 1584, x1)
+
+inst_405:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555554, 0x554, x2, 1588, x1)
+
+inst_406:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555554, 0x2, x2, 1592, x1)
+
+inst_407:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x2d, x2, 1596, x1)
+
+inst_408:
+// rs1_val==1431655764 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x55555550, 0x55555554, -0x2d, x2, 1600, x1)
+
+inst_409:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x55555554, 0x666, x2, 1604, x1)
+
+inst_410:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x55555554, 0x333, x2, 1608, x1)
+
+inst_411:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x55555554, 0x5, x2, 1612, x1)
+
+inst_412:
+// rs1_val==1431655764 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x55555000, 0x55555554, -0x556, x2, 1616, x1)
+
+inst_413:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x554, 0x55555554, 0x555, x2, 1620, x1)
+
+inst_414:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x55555554, 0x3, x2, 1624, x1)
+
+inst_415:
+// rs1_val==2 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x2e, x2, 1628, x1)
+
+inst_416:
+// rs1_val==2 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, -0x2c, x2, 1632, x1)
+
+inst_417:
+// rs1_val==2 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x667, x2, 1636, x1)
+
+inst_418:
+// rs1_val==2 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x334, x2, 1640, x1)
+
+inst_419:
+// rs1_val==2 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x6, x2, 1644, x1)
+
+inst_420:
+// rs1_val==2 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, -0x555, x2, 1648, x1)
+
+inst_421:
+// rs1_val==2 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x556, x2, 1652, x1)
+
+inst_422:
+// rs1_val==2 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x4, x2, 1656, x1)
+
+inst_423:
+// rs1_val==2 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x2c, x2, 1660, x1)
+
+inst_424:
+// rs1_val==2 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x0, x2, 1664, x1)
+
+inst_425:
+// rs1_val==2 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x665, x2, 1668, x1)
+
+inst_426:
+// rs1_val==2 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x332, x2, 1672, x1)
+
+inst_427:
+// rs1_val==2 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x554, x2, 1676, x1)
+
+inst_428:
+// rs1_val==2 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x2, x2, 1680, x1)
+
+inst_429:
+// rs1_val==2 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x2d, x2, 1684, x1)
+
+inst_430:
+// rs1_val==2 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, -0x2d, x2, 1688, x1)
+
+inst_431:
+// rs1_val==2 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x666, x2, 1692, x1)
+
+inst_432:
+// rs1_val==2 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x333, x2, 1696, x1)
+
+inst_433:
+// rs1_val==2 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x5, x2, 1700, x1)
+
+inst_434:
+// rs1_val==2 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, -0x556, x2, 1704, x1)
+
+inst_435:
+// rs1_val==2 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x2, 0x555, x2, 1708, x1)
+
+inst_436:
+// rs1_val==2 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x2, 0x3, x2, 1712, x1)
+
+inst_437:
+// rs1_val==46340 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x2e, x2, 1716, x1)
+
+inst_438:
+// rs1_val==46340 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xb504, 0xb504, -0x2c, x2, 1720, x1)
+
+inst_439:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x404, 0xb504, 0x667, x2, 1724, x1)
+
+inst_440:
+// rs1_val==46340 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x104, 0xb504, 0x334, x2, 1728, x1)
+
+inst_441:
+// rs1_val==46340 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x6, x2, 1732, x1)
+
+inst_442:
+// rs1_val==46340 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xb000, 0xb504, -0x555, x2, 1736, x1)
+
+inst_443:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x504, 0xb504, 0x556, x2, 1740, x1)
+
+inst_444:
+// rs1_val==46340 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x4, x2, 1744, x1)
+
+inst_445:
+// rs1_val==46340 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x2c, x2, 1748, x1)
+
+inst_446:
+// rs1_val==46340 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb504, 0x0, x2, 1752, x1)
+
+inst_447:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x404, 0xb504, 0x665, x2, 1756, x1)
+
+inst_448:
+// rs1_val==46340 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x100, 0xb504, 0x332, x2, 1760, x1)
+
+inst_449:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x504, 0xb504, 0x554, x2, 1764, x1)
+
+inst_450:
+// rs1_val==46340 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb504, 0x2, x2, 1768, x1)
+
+inst_451:
+// rs1_val==46340 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x2d, x2, 1772, x1)
+
+inst_452:
+// rs1_val==46340 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xb500, 0xb504, -0x2d, x2, 1776, x1)
+
+inst_453:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x404, 0xb504, 0x666, x2, 1780, x1)
+
+inst_454:
+// rs1_val==46340 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x100, 0xb504, 0x333, x2, 1784, x1)
+
+inst_455:
+// rs1_val==46340 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0xb504, 0x5, x2, 1788, x1)
+
+inst_456:
+// rs1_val==46340 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xb000, 0xb504, -0x556, x2, 1792, x1)
+
+inst_457:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x504, 0xb504, 0x555, x2, 1796, x1)
+
+inst_458:
+// rs1_val==46340 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, 0xb504, 0x3, x2, 1800, x1)
+
+inst_459:
+// rs1_val==-46340 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2c, -0xb504, 0x2e, x2, 1804, x1)
+
+inst_460:
+// rs1_val==-46340 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xffff4ad4, -0xb504, -0x2c, x2, 1808, x1)
+
+inst_461:
+// rs1_val==-46340 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x264, -0xb504, 0x667, x2, 1812, x1)
+
+inst_462:
+// rs1_val==-46340 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x234, -0xb504, 0x334, x2, 1816, x1)
+
+inst_463:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, -0xb504, 0x6, x2, 1820, x1)
+
+inst_464:
+// rs1_val==-46340 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0xffff4aa8, -0xb504, -0x555, x2, 1824, x1)
+
+inst_465:
+// rs1_val==-46340 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x54, -0xb504, 0x556, x2, 1828, x1)
+
+inst_466:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, -0xb504, 0x4, x2, 1832, x1)
+
+inst_467:
+// rs1_val==-46340 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x2c, -0xb504, 0x2c, x2, 1836, x1)
+
+inst_468:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, -0xb504, 0x0, x2, 1840, x1)
+
+inst_469:
+// rs1_val==-46340 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x264, -0xb504, 0x665, x2, 1844, x1)
+
+inst_470:
+// rs1_val==-46340 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x230, -0xb504, 0x332, x2, 1848, x1)
+
+inst_471:
+// rs1_val==-46340 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x54, -0xb504, 0x554, x2, 1852, x1)
+
+inst_472:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, -0xb504, 0x2, x2, 1856, x1)
+
+inst_473:
+// rs1_val==-46340 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x2c, -0xb504, 0x2d, x2, 1860, x1)
+
+inst_474:
+// rs1_val==-46340 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0xffff4ad0, -0xb504, -0x2d, x2, 1864, x1)
+
+inst_475:
+// rs1_val==-46340 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x264, -0xb504, 0x666, x2, 1868, x1)
+
+inst_476:
+// rs1_val==-46340 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x230, -0xb504, 0x333, x2, 1872, x1)
+
+inst_477:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, -0xb504, 0x5, x2, 1876, x1)
+
+inst_478:
+// rs1_val==-46340 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0xffff4aa8, -0xb504, -0x556, x2, 1880, x1)
+
+inst_479:
+// rs1_val==-46340 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x54, -0xb504, 0x555, x2, 1884, x1)
+
+inst_480:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x0, -0xb504, 0x3, x2, 1888, x1)
+
+inst_481:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x26, 0x66666666, 0x2e, x2, 1892, x1)
+
+inst_482:
+// rs1_val==1717986918 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x66666644, 0x66666666, -0x2c, x2, 1896, x1)
+
+inst_483:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x666, 0x66666666, 0x667, x2, 1900, x1)
+
+inst_484:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x224, 0x66666666, 0x334, x2, 1904, x1)
+
+inst_485:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x6, 0x66666666, 0x6, x2, 1908, x1)
+
+inst_486:
+// rs1_val==1717986918 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x66666222, 0x66666666, -0x555, x2, 1912, x1)
+
+inst_487:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x446, 0x66666666, 0x556, x2, 1916, x1)
+
+inst_488:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x66666666, 0x4, x2, 1920, x1)
+
+inst_489:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x66666666, 0x2c, x2, 1924, x1)
+
+inst_490:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x66666666, 0x0, x2, 1928, x1)
+
+inst_491:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x664, 0x66666666, 0x665, x2, 1932, x1)
+
+inst_492:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x66666666, 0x332, x2, 1936, x1)
+
+inst_493:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x66666666, 0x554, x2, 1940, x1)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x66666666, 0x2, x2, 1944, x1)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x24, 0x66666666, 0x2d, x2, 1948, x1)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x66666642, 0x66666666, -0x2d, x2, 1952, x1)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x666, 0x66666666, 0x666, x2, 1956, x1)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x66666666, 0x333, x2, 1960, x1)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x66666666, 0x5, x2, 1964, x1)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x66666222, 0x66666666, -0x556, x2, 1968, x1)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x444, 0x66666666, 0x555, x2, 1972, x1)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x66666666, 0x3, x2, 1976, x1)
+
+inst_503:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x22, 0x33333333, 0x2e, x2, 1980, x1)
+
+inst_504:
+// rs1_val==858993459 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x33333310, 0x33333333, -0x2c, x2, 1984, x1)
+
+inst_505:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x223, 0x33333333, 0x667, x2, 1988, x1)
+
+inst_506:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x330, 0x33333333, 0x334, x2, 1992, x1)
+
+inst_507:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x33333333, 0x6, x2, 1996, x1)
+
+inst_508:
+// rs1_val==858993459 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x33333223, 0x33333333, -0x555, x2, 2000, x1)
+
+inst_509:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x112, 0x33333333, 0x556, x2, 2004, x1)
+
+inst_510:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333333, 0x4, x2, 2008, x1)
+
+inst_511:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x20, 0x33333333, 0x2c, x2, 2012, x1)
+
+inst_512:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x33333333, 0x0, x2, 2016, x1)
+
+inst_513:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x221, 0x33333333, 0x665, x2, 2020, x1)
+
+inst_514:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x332, 0x33333333, 0x332, x2, 2024, x1)
+
+inst_515:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x110, 0x33333333, 0x554, x2, 2028, x1)
+
+inst_516:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, 0x33333333, 0x2, x2, 2032, x1)
+
+inst_517:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x21, 0x33333333, 0x2d, x2, 2036, x1)
+
+inst_518:
+// rs1_val==858993459 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x33333313, 0x33333333, -0x2d, x2, 2040, x1)
+
+inst_519:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x222, 0x33333333, 0x666, x2, 2044, x1)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_520:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x333, 0x33333333, 0x333, x2, 0, x1)
+
+inst_521:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x33333333, 0x5, x2, 4, x1)
+
+inst_522:
+// rs1_val==858993459 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x33333222, 0x33333333, -0x556, x2, 8, x1)
+
+inst_523:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x111, 0x33333333, 0x555, x2, 12, x1)
+
+inst_524:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x3, 0x33333333, 0x3, x2, 16, x1)
+
+inst_525:
+// rs1_val==5 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x2e, x2, 20, x1)
+
+inst_526:
+// rs1_val==5 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, -0x2c, x2, 24, x1)
+
+inst_527:
+// rs1_val==5 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x5, 0x667, x2, 28, x1)
+
+inst_528:
+// rs1_val==5 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x334, x2, 32, x1)
+
+inst_529:
+// rs1_val==5 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x6, x2, 36, x1)
+
+inst_530:
+// rs1_val==5 and imm_val==-1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x555
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x5, -0x555, x2, 40, x1)
+
+inst_531:
+// rs1_val==5 and imm_val==1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x556, x2, 44, x1)
+
+inst_532:
+// rs1_val==5 and imm_val==4, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x4, x2, 48, x1)
+
+inst_533:
+// rs1_val==5 and imm_val==44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x2c, x2, 52, x1)
+
+inst_534:
+// rs1_val==5 and imm_val==0, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x5, 0x0, x2, 56, x1)
+
+inst_535:
+// rs1_val==5 and imm_val==1637, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x5, 0x665, x2, 60, x1)
+
+inst_536:
+// rs1_val==5 and imm_val==818, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x5, 0x332, x2, 64, x1)
+
+inst_537:
+// rs1_val==5 and imm_val==1364, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x554, x2, 68, x1)
+
+inst_538:
+// rs1_val==5 and imm_val==2, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x5, 0x2, x2, 72, x1)
+
+inst_539:
+// rs1_val==5 and imm_val==45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x5, 0x2d, x2, 76, x1)
+
+inst_540:
+// rs1_val==5 and imm_val==-45, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2d
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x5, -0x2d, x2, 80, x1)
+
+inst_541:
+// rs1_val==5 and imm_val==1638, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( andi, x11, x10, 0x4, 0x5, 0x666, x2, 84, x1)
+
+inst_542:
+// rs1_val==5 and imm_val==819, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x5, 0x333, x2, 88, x1)
+
+inst_543:
+// rs1_val==5 and imm_val==5, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x5, 0x5, x2, 92, x1)
+
+inst_544:
+// rs1_val==5 and imm_val==-1366, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:-0x556
+TEST_IMM_OP( andi, x11, x10, 0x0, 0x5, -0x556, x2, 96, x1)
+
+inst_545:
+// rs1_val==5 and imm_val==1365, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x5, 0x5, 0x555, x2, 100, x1)
+
+inst_546:
+// rs1_val==5 and imm_val==3, 
+// opcode: andi ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( andi, x11, x10, 0x1, 0x5, 0x3, x2, 104, x1)
+
+inst_547:
+// rs1_val==-1431655766 and imm_val==46, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2e
+TEST_IMM_OP( andi, x11, x10, 0x2a, -0x55555556, 0x2e, x2, 108, x1)
+
+inst_548:
+// rs1_val==-1431655766 and imm_val==-44, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2c
+TEST_IMM_OP( andi, x11, x10, 0xaaaaaa80, -0x55555556, -0x2c, x2, 112, x1)
+
+inst_549:
+// rs1_val==-1431655766 and imm_val==1639, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x667
+TEST_IMM_OP( andi, x11, x10, 0x222, -0x55555556, 0x667, x2, 116, x1)
+
+inst_550:
+// rs1_val==-1431655766 and imm_val==820, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x334
+TEST_IMM_OP( andi, x11, x10, 0x220, -0x55555556, 0x334, x2, 120, x1)
+
+inst_551:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x6
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x55555556, 0x6, x2, 124, x1)
+
+inst_552:
+// rs1_val == -16777217, imm_val == 2
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x1000001;  immval:0x2
+TEST_IMM_OP( andi, x11, x10, 0x2, -0x1000001, 0x2, x2, 128, x1)
+
+inst_553:
+// rs1_val == -131073, imm_val == 1365
+// opcode: andi ; op1:x10; dest:x11; op1val:-0x20001;  immval:0x555
+TEST_IMM_OP( andi, x11, x10, 0x555, -0x20001, 0x555, x2, 132, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 34*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S
new file mode 100644
index 000000000..517a4b8d1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S
@@ -0,0 +1,391 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the auipc instruction of the RISC-V E extension for the auipc covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",auipc)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rd==x9, imm_val == ((2**20)-1), imm_val > 0
+// opcode: auipc ; dest:x9; immval:0xfffff
+TEST_AUIPC(auipc, x9, -0x1000, 0xfffff, x2, 0, x3)
+
+inst_1:
+// rd==x6, imm_val == 524287, 
+// opcode: auipc ; dest:x6; immval:0x7ffff
+TEST_AUIPC(auipc, x6, 0x7ffff000, 0x7ffff, x2, 4, x3)
+
+inst_2:
+// rd==x1, imm_val == 786431, 
+// opcode: auipc ; dest:x1; immval:0xbffff
+TEST_AUIPC(auipc, x1, -0x40001000, 0xbffff, x2, 8, x3)
+
+inst_3:
+// rd==x5, imm_val == 917503, 
+// opcode: auipc ; dest:x5; immval:0xdffff
+TEST_AUIPC(auipc, x5, -0x20001000, 0xdffff, x2, 12, x3)
+
+inst_4:
+// rd==x14, imm_val == 983039, 
+// opcode: auipc ; dest:x14; immval:0xeffff
+TEST_AUIPC(auipc, x14, -0x10001000, 0xeffff, x2, 16, x3)
+
+inst_5:
+// rd==x7, imm_val == 1015807, 
+// opcode: auipc ; dest:x7; immval:0xf7fff
+TEST_AUIPC(auipc, x7, -0x8001000, 0xf7fff, x2, 20, x3)
+
+inst_6:
+// rd==x15, imm_val == 1032191, 
+// opcode: auipc ; dest:x15; immval:0xfbfff
+TEST_AUIPC(auipc, x15, -0x4001000, 0xfbfff, x2, 24, x3)
+
+inst_7:
+// rd==x10, imm_val == 1040383, 
+// opcode: auipc ; dest:x10; immval:0xfdfff
+TEST_AUIPC(auipc, x10, -0x2001000, 0xfdfff, x2, 28, x3)
+
+inst_8:
+// rd==x12, imm_val == 1044479, 
+// opcode: auipc ; dest:x12; immval:0xfefff
+TEST_AUIPC(auipc, x12, -0x1001000, 0xfefff, x2, 32, x3)
+
+inst_9:
+// rd==x0, imm_val == 1046527, 
+// opcode: auipc ; dest:x0; immval:0xff7ff
+TEST_AUIPC(auipc, x0, 0, 0xff7ff, x2, 36, x3)
+
+inst_10:
+// rd==x8, imm_val == 1047551, 
+// opcode: auipc ; dest:x8; immval:0xffbff
+TEST_AUIPC(auipc, x8, -0x401000, 0xffbff, x2, 40, x3)
+
+inst_11:
+// rd==x4, imm_val == 1048063, 
+// opcode: auipc ; dest:x4; immval:0xffdff
+TEST_AUIPC(auipc, x4, -0x201000, 0xffdff, x2, 44, x3)
+
+inst_12:
+// rd==x13, imm_val == 1048319, 
+// opcode: auipc ; dest:x13; immval:0xffeff
+TEST_AUIPC(auipc, x13, -0x101000, 0xffeff, x2, 48, x4)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_13:
+// rd==x3, imm_val == 1048447, 
+// opcode: auipc ; dest:x3; immval:0xfff7f
+TEST_AUIPC(auipc, x3, -0x81000, 0xfff7f, x1, 0, x4)
+
+inst_14:
+// rd==x11, imm_val == 1048511, 
+// opcode: auipc ; dest:x11; immval:0xfffbf
+TEST_AUIPC(auipc, x11, -0x41000, 0xfffbf, x1, 4, x4)
+
+inst_15:
+// rd==x2, imm_val == 1048543, 
+// opcode: auipc ; dest:x2; immval:0xfffdf
+TEST_AUIPC(auipc, x2, -0x21000, 0xfffdf, x1, 8, x4)
+
+inst_16:
+// imm_val == 1048559, 
+// opcode: auipc ; dest:x10; immval:0xfffef
+TEST_AUIPC(auipc, x10, -0x11000, 0xfffef, x1, 12, x4)
+
+inst_17:
+// imm_val == 1048567, 
+// opcode: auipc ; dest:x10; immval:0xffff7
+TEST_AUIPC(auipc, x10, -0x9000, 0xffff7, x1, 16, x4)
+
+inst_18:
+// imm_val == 1048571, 
+// opcode: auipc ; dest:x10; immval:0xffffb
+TEST_AUIPC(auipc, x10, -0x5000, 0xffffb, x1, 20, x4)
+
+inst_19:
+// imm_val == 1048573, 
+// opcode: auipc ; dest:x10; immval:0xffffd
+TEST_AUIPC(auipc, x10, -0x3000, 0xffffd, x1, 24, x4)
+
+inst_20:
+// imm_val == 1048574, 
+// opcode: auipc ; dest:x10; immval:0xffffe
+TEST_AUIPC(auipc, x10, -0x2000, 0xffffe, x1, 28, x4)
+
+inst_21:
+// imm_val == 524288, 
+// opcode: auipc ; dest:x10; immval:0x80000
+TEST_AUIPC(auipc, x10, -0x80000000, 0x80000, x1, 32, x4)
+
+inst_22:
+// imm_val == 262144, 
+// opcode: auipc ; dest:x10; immval:0x40000
+TEST_AUIPC(auipc, x10, 0x40000000, 0x40000, x1, 36, x4)
+
+inst_23:
+// imm_val == 131072, 
+// opcode: auipc ; dest:x10; immval:0x20000
+TEST_AUIPC(auipc, x10, 0x20000000, 0x20000, x1, 40, x4)
+
+inst_24:
+// imm_val == 65536, 
+// opcode: auipc ; dest:x10; immval:0x10000
+TEST_AUIPC(auipc, x10, 0x10000000, 0x10000, x1, 44, x4)
+
+inst_25:
+// imm_val == 32768, 
+// opcode: auipc ; dest:x10; immval:0x8000
+TEST_AUIPC(auipc, x10, 0x8000000, 0x8000, x1, 48, x4)
+
+inst_26:
+// imm_val == 16384, 
+// opcode: auipc ; dest:x10; immval:0x4000
+TEST_AUIPC(auipc, x10, 0x4000000, 0x4000, x1, 52, x4)
+
+inst_27:
+// imm_val == 8192, 
+// opcode: auipc ; dest:x10; immval:0x2000
+TEST_AUIPC(auipc, x10, 0x2000000, 0x2000, x1, 56, x4)
+
+inst_28:
+// imm_val == 4096, 
+// opcode: auipc ; dest:x10; immval:0x1000
+TEST_AUIPC(auipc, x10, 0x1000000, 0x1000, x1, 60, x4)
+
+inst_29:
+// imm_val == 2048, 
+// opcode: auipc ; dest:x10; immval:0x800
+TEST_AUIPC(auipc, x10, 0x800000, 0x800, x1, 64, x4)
+
+inst_30:
+// imm_val == 1024, imm_val==1024
+// opcode: auipc ; dest:x10; immval:0x400
+TEST_AUIPC(auipc, x10, 0x400000, 0x400, x1, 68, x4)
+
+inst_31:
+// imm_val == 512, 
+// opcode: auipc ; dest:x10; immval:0x200
+TEST_AUIPC(auipc, x10, 0x200000, 0x200, x1, 72, x4)
+
+inst_32:
+// imm_val == 256, 
+// opcode: auipc ; dest:x10; immval:0x100
+TEST_AUIPC(auipc, x10, 0x100000, 0x100, x1, 76, x4)
+
+inst_33:
+// imm_val == 128, 
+// opcode: auipc ; dest:x10; immval:0x80
+TEST_AUIPC(auipc, x10, 0x80000, 0x80, x1, 80, x4)
+
+inst_34:
+// imm_val == 64, 
+// opcode: auipc ; dest:x10; immval:0x40
+TEST_AUIPC(auipc, x10, 0x40000, 0x40, x1, 84, x4)
+
+inst_35:
+// imm_val == 32, 
+// opcode: auipc ; dest:x10; immval:0x20
+TEST_AUIPC(auipc, x10, 0x20000, 0x20, x1, 88, x4)
+
+inst_36:
+// imm_val == 16, 
+// opcode: auipc ; dest:x10; immval:0x10
+TEST_AUIPC(auipc, x10, 0x10000, 0x10, x1, 92, x4)
+
+inst_37:
+// imm_val==349525, imm_val == 349525
+// opcode: auipc ; dest:x10; immval:0x55555
+TEST_AUIPC(auipc, x10, 0x55555000, 0x55555, x1, 96, x4)
+
+inst_38:
+// imm_val==3, 
+// opcode: auipc ; dest:x10; immval:0x3
+TEST_AUIPC(auipc, x10, 0x3000, 0x3, x1, 100, x4)
+
+inst_39:
+// imm_val == 699050, imm_val==699050
+// opcode: auipc ; dest:x10; immval:0xaaaaa
+TEST_AUIPC(auipc, x10, -0x55556000, 0xaaaaa, x1, 104, x4)
+
+inst_40:
+// imm_val == 0, imm_val==0
+// opcode: auipc ; dest:x10; immval:0x0
+TEST_AUIPC(auipc, x10, 0x0, 0x0, x1, 108, x4)
+
+inst_41:
+// imm_val == 8, 
+// opcode: auipc ; dest:x10; immval:0x8
+TEST_AUIPC(auipc, x10, 0x8000, 0x8, x1, 112, x4)
+
+inst_42:
+// imm_val == 4, imm_val==4
+// opcode: auipc ; dest:x10; immval:0x4
+TEST_AUIPC(auipc, x10, 0x4000, 0x4, x1, 116, x4)
+
+inst_43:
+// imm_val == 2, imm_val==2
+// opcode: auipc ; dest:x10; immval:0x2
+TEST_AUIPC(auipc, x10, 0x2000, 0x2, x1, 120, x4)
+
+inst_44:
+// imm_val == 1, imm_val==1
+// opcode: auipc ; dest:x10; immval:0x1
+TEST_AUIPC(auipc, x10, 0x1000, 0x1, x1, 124, x4)
+
+inst_45:
+// imm_val==725, 
+// opcode: auipc ; dest:x10; immval:0x2d5
+TEST_AUIPC(auipc, x10, 0x2d5000, 0x2d5, x1, 128, x4)
+
+inst_46:
+// imm_val==419431, 
+// opcode: auipc ; dest:x10; immval:0x66667
+TEST_AUIPC(auipc, x10, 0x66667000, 0x66667, x1, 132, x4)
+
+inst_47:
+// imm_val==209716, 
+// opcode: auipc ; dest:x10; immval:0x33334
+TEST_AUIPC(auipc, x10, 0x33334000, 0x33334, x1, 136, x4)
+
+inst_48:
+// imm_val==6, 
+// opcode: auipc ; dest:x10; immval:0x6
+TEST_AUIPC(auipc, x10, 0x6000, 0x6, x1, 140, x4)
+
+inst_49:
+// imm_val==699051, 
+// opcode: auipc ; dest:x10; immval:0xaaaab
+TEST_AUIPC(auipc, x10, -0x55555000, 0xaaaab, x1, 144, x4)
+
+inst_50:
+// imm_val==349526, 
+// opcode: auipc ; dest:x10; immval:0x55556
+TEST_AUIPC(auipc, x10, 0x55556000, 0x55556, x1, 148, x4)
+
+inst_51:
+// imm_val==1022, 
+// opcode: auipc ; dest:x10; immval:0x3fe
+TEST_AUIPC(auipc, x10, 0x3fe000, 0x3fe, x1, 152, x4)
+
+inst_52:
+// imm_val==723, 
+// opcode: auipc ; dest:x10; immval:0x2d3
+TEST_AUIPC(auipc, x10, 0x2d3000, 0x2d3, x1, 156, x4)
+
+inst_53:
+// imm_val==419429, 
+// opcode: auipc ; dest:x10; immval:0x66665
+TEST_AUIPC(auipc, x10, 0x66665000, 0x66665, x1, 160, x4)
+
+inst_54:
+// imm_val==209714, 
+// opcode: auipc ; dest:x10; immval:0x33332
+TEST_AUIPC(auipc, x10, 0x33332000, 0x33332, x1, 164, x4)
+
+inst_55:
+// imm_val==699049, 
+// opcode: auipc ; dest:x10; immval:0xaaaa9
+TEST_AUIPC(auipc, x10, -0x55557000, 0xaaaa9, x1, 168, x4)
+
+inst_56:
+// imm_val==349524, 
+// opcode: auipc ; dest:x10; immval:0x55554
+TEST_AUIPC(auipc, x10, 0x55554000, 0x55554, x1, 172, x4)
+
+inst_57:
+// imm_val==1023, 
+// opcode: auipc ; dest:x10; immval:0x3ff
+TEST_AUIPC(auipc, x10, 0x3ff000, 0x3ff, x1, 176, x4)
+
+inst_58:
+// imm_val==724, 
+// opcode: auipc ; dest:x10; immval:0x2d4
+TEST_AUIPC(auipc, x10, 0x2d4000, 0x2d4, x1, 180, x4)
+
+inst_59:
+// imm_val==419430, 
+// opcode: auipc ; dest:x10; immval:0x66666
+TEST_AUIPC(auipc, x10, 0x66666000, 0x66666, x1, 184, x4)
+
+inst_60:
+// imm_val==209715, 
+// opcode: auipc ; dest:x10; immval:0x33333
+TEST_AUIPC(auipc, x10, 0x33333000, 0x33333, x1, 188, x4)
+
+inst_61:
+// imm_val==5, 
+// opcode: auipc ; dest:x10; immval:0x5
+TEST_AUIPC(auipc, x10, 0x5000, 0x5, x1, 192, x4)
+
+inst_62:
+// imm_val == 1046527, 
+// opcode: auipc ; dest:x10; immval:0xff7ff
+TEST_AUIPC(auipc, x10, -0x801000, 0xff7ff, x1, 196, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 50*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S
new file mode 100644
index 000000000..946402467
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S
@@ -0,0 +1,3031 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the beq instruction of the RISC-V E extension for the beq covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",beq)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rs1 == rs2, rs1==x6, rs2==x6, rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs2_val == -67108865, rs1_val == -33554433
+// opcode: beq, op1:x6; op2:x6; op1val:-0x2000001; op2val:-0x2000001; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x13, x6, x6, -0x2000001, -0x2000001, 0x8, 3f, x5, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x2, rs2==x12, rs2_val == 2147483647, 
+// opcode: beq, op1:x2; op2:x12; op1val:0x0; op2val:0x7fffffff; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x13, x2, x12, 0x0, 0x7fffffff, 0x0, 3f, x5, 4,0)
+
+inst_2:
+// rs1==x10, rs2==x7, rs2_val == -1073741825, rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0, rs1_val == -1431655766
+// opcode: beq, op1:x10; op2:x7; op1val:-0x55555556; op2val:-0x40000001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x13, x10, x7, -0x55555556, -0x40000001, 0x4, 1b, x5, 8,0)
+
+inst_3:
+// rs1==x7, rs2==x11, rs2_val == -536870913, rs1_val == 2147483647, rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x7; op2:x11; op1val:0x7fffffff; op2val:-0x20000001; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x13, x7, x11, 0x7fffffff, -0x20000001, 0x100, 3f, x5, 12,0)
+
+inst_4:
+// rs1==x9, rs2==x14, rs2_val == -268435457, 
+// opcode: beq, op1:x9; op2:x14; op1val:0x3fffffff; op2val:-0x10000001; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x13, x9, x14, 0x3fffffff, -0x10000001, 0x6, 1b, x5, 16,0)
+
+inst_5:
+// rs1==x8, rs2==x2, rs2_val == -134217729, rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x8; op2:x2; op1val:-0xa; op2val:-0x8000001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x13, x8, x2, -0xa, -0x8000001, 0x4, 1b, x5, 20,0)
+
+inst_6:
+// rs1==x12, rs2==x1, rs2_val == -33554433, 
+// opcode: beq, op1:x12; op2:x1; op1val:0xb504; op2val:-0x2000001; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x13, x12, x1, 0xb504, -0x2000001, 0x2, 3f, x5, 24,0)
+
+inst_7:
+// rs1==x3, rs2==x4, rs2_val == -16777217, rs1_val == -2097153
+// opcode: beq, op1:x3; op2:x4; op1val:-0x200001; op2val:-0x1000001; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x13, x3, x4, -0x200001, -0x1000001, 0x100, 3f, x5, 28,0)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_8:
+// rs1==x0, rs2==x13, rs2_val == -8388609, 
+// opcode: beq, op1:x0; op2:x13; op1val:0x0; op2val:-0x800001; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x6, x0, x13, 0x0, -0x800001, 0x0, 3f, x2, 0,0)
+
+inst_9:
+// rs1==x14, rs2==x5, rs2_val == -4194305, rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs1_val == -268435457
+// opcode: beq, op1:x14; op2:x5; op1val:-0x10000001; op2val:-0x400001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x6, x14, x5, -0x10000001, -0x400001, 0x4, 3f, x2, 4,0)
+
+inst_10:
+// rs1==x15, rs2==x9, rs2_val == -2097153, rs1_val == 4
+// opcode: beq, op1:x15; op2:x9; op1val:0x4; op2val:-0x200001; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x6, x15, x9, 0x4, -0x200001, 0x20, 3f, x2, 8,0)
+
+inst_11:
+// rs1==x5, rs2==x15, rs2_val == -1048577, rs1_val == 512
+// opcode: beq, op1:x5; op2:x15; op1val:0x200; op2val:-0x100001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x6, x5, x15, 0x200, -0x100001, 0x4, 1b, x2, 12,0)
+
+inst_12:
+// rs1==x4, rs2==x0, rs2_val == -524289, rs1_val == -536870913
+// opcode: beq, op1:x4; op2:x0; op1val:-0x20000001; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x6, x4, x0, -0x20000001, 0x0, 0x6, 1b, x2, 16,0)
+
+inst_13:
+// rs1==x1, rs2==x8, rs2_val == -262145, rs1_val == -65
+// opcode: beq, op1:x1; op2:x8; op1val:-0x41; op2val:-0x40001; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x6, x1, x8, -0x41, -0x40001, 0x10, 3f, x2, 20,0)
+
+inst_14:
+// rs1==x11, rs2==x3, rs2_val == -131073, 
+// opcode: beq, op1:x11; op2:x3; op1val:0x4; op2val:-0x20001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x6, x11, x3, 0x4, -0x20001, 0x4, 3f, x2, 24,0)
+
+inst_15:
+// rs1==x13, rs2==x10, rs2_val == -65537, rs1_val == -8193
+// opcode: beq, op1:x13; op2:x10; op1val:-0x2001; op2val:-0x10001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x6, x13, x10, -0x2001, -0x10001, 0x4, 3f, x2, 28,0)
+
+inst_16:
+// rs2_val == -32769, rs1_val == 32
+// opcode: beq, op1:x10; op2:x11; op1val:0x20; op2val:-0x8001; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x20, -0x8001, 0x6, 1b, x2, 32,0)
+
+inst_17:
+// rs2_val == -16385, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x4; op2val:-0x4001; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x4, -0x4001, 0x8, 3f, x2, 36,0)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x200; op2val:-0x2001; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x200, -0x2001, 0x20, 3f, x2, 40,0)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x6; op2val:-0x1001; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x6, -0x1001, 0x400, 1b, x2, 44,0)
+
+inst_20:
+// rs2_val == -2049, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8; op2val:-0x801; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8, -0x801, 0xa, 1b, x2, 48,0)
+
+inst_21:
+// rs2_val == -1025, rs1_val == -129
+// opcode: beq, op1:x10; op2:x11; op1val:-0x81; op2val:-0x401; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x81, -0x401, 0x8, 1b, x2, 52,0)
+
+inst_22:
+// rs2_val == -513, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:-0x201; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, -0x201, 0x4, 1b, x2, 56,0)
+
+inst_23:
+// rs2_val == -257, rs1_val == -3
+// opcode: beq, op1:x10; op2:x11; op1val:-0x3; op2val:-0x101; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x3, -0x101, 0x2, 3f, x2, 60,0)
+
+inst_24:
+// rs2_val == -129, rs1_val == 8192
+// opcode: beq, op1:x10; op2:x11; op1val:0x2000; op2val:-0x81; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2000, -0x81, 0x4, 1b, x2, 64,0)
+
+inst_25:
+// rs2_val == -65, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3fffffff; op2val:-0x41; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3fffffff, -0x41, 0x400, 3f, x2, 68,0)
+
+inst_26:
+// rs2_val == -33, rs1_val == -262145
+// opcode: beq, op1:x10; op2:x11; op1val:-0x40001; op2val:-0x21; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x40001, -0x21, 0x400, 1b, x2, 72,0)
+
+inst_27:
+// rs2_val == -17, rs1_val == -33
+// opcode: beq, op1:x10; op2:x11; op1val:-0x21; op2val:-0x11; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x21, -0x11, 0x556, 1b, x2, 76,0)
+
+inst_28:
+// rs2_val == -9, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x7fffffff; op2val:-0x9; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x7fffffff, -0x9, 0x4, 3f, x2, 80,0)
+
+inst_29:
+// rs2_val == -5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x5; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, -0x5, 0x80, 3f, x2, 84,0)
+
+inst_30:
+// rs2_val == -3, rs1_val == 1
+// opcode: beq, op1:x10; op2:x11; op1val:0x1; op2val:-0x3; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x1, -0x3, 0x4, 1b, x2, 88,0)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x40001; op2val:-0x2; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x40001, -0x2, 0xa, 1b, x2, 92,0)
+
+inst_32:
+// rs1_val == -1073741825, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x40000001; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x40000001, 0x6, 0x556, 1b, x2, 96,0)
+
+inst_33:
+// rs1_val == -134217729, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8000001; op2val:-0x10000001; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8000001, -0x10000001, 0x8, 3f, x2, 100,0)
+
+inst_34:
+// rs1_val == -67108865, rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x10; op2:x11; op1val:-0x4000001; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x4000001, 0xb504, 0x8, 3f, x2, 104,0)
+
+inst_35:
+// rs1_val == -16777217, rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x1000001; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x1000001, -0x1000001, 0x200, 3f, x2, 108,0)
+
+inst_36:
+// rs1_val == -8388609, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x800001; op2val:-0x9; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x800001, -0x9, 0x2, 1b, x2, 112,0)
+
+inst_37:
+// rs1_val == -4194305, rs2_val == 128
+// opcode: beq, op1:x10; op2:x11; op1val:-0x400001; op2val:0x80; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x400001, 0x80, 0x400, 1b, x2, 116,0)
+
+inst_38:
+// rs1_val == -1048577, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x100001; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x100001, -0x55555555, 0x0, 1b, x2, 120,0)
+
+inst_39:
+// rs1_val == -524289, rs2_val == 131072
+// opcode: beq, op1:x10; op2:x11; op1val:-0x80001; op2val:0x20000; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x80001, 0x20000, 0x0, 1b, x2, 124,0)
+
+inst_40:
+// rs1_val == -131073, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x20001; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x20001, 0x66666667, 0x400, 1b, x2, 128,0)
+
+inst_41:
+// rs1_val == -65537, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x10001; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x10001, 0x33333334, 0x6, 1b, x2, 132,0)
+
+inst_42:
+// rs1_val == -32769, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8001; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8001, 0x0, 0x6, 1b, x2, 136,0)
+
+inst_43:
+// rs1_val == -16385, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x4001; op2val:-0x1001; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x4001, -0x1001, 0x0, 3f, x2, 140,0)
+
+inst_44:
+// rs1_val == -4097, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x1001; op2val:-0x800001; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x1001, -0x800001, 0x10, 3f, x2, 144,0)
+
+inst_45:
+// rs1_val == -2049, rs2_val == 2
+// opcode: beq, op1:x10; op2:x11; op1val:-0x801; op2val:0x2; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x801, 0x2, 0xa, 1b, x2, 148,0)
+
+inst_46:
+// rs1_val == -1025, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x401; op2val:-0x81; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x401, -0x81, 0x80, 3f, x2, 152,0)
+
+inst_47:
+// rs1_val == -513, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x201; op2val:-0x401; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x201, -0x401, 0x8, 1b, x2, 156,0)
+
+inst_48:
+// rs1_val == -257, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x101; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x101, 0xb503, 0x8, 1b, x2, 160,0)
+
+inst_49:
+// rs1_val == -17, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x11; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x11, -0xb503, 0x6, 3f, x2, 164,0)
+
+inst_50:
+// rs1_val == -9, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x9; op2val:-0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x9, -0xb504, 0x556, 1b, x2, 168,0)
+
+inst_51:
+// rs1_val == -5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x5; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x5, 0x55555554, 0x8, 3f, x2, 172,0)
+
+inst_52:
+// rs1_val == -2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x2; op2val:-0x801; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x2, -0x801, 0xa, 1b, x2, 176,0)
+
+inst_53:
+// rs2_val == -2147483648, rs1_val == 32768
+// opcode: beq, op1:x10; op2:x11; op1val:0x8000; op2val:-0x80000000; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x8000, -0x80000000, 0x0, 1b, x2, 180,0)
+
+inst_54:
+// rs2_val == 1073741824, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x40000000; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x40000000, 0x6, 3f, x2, 184,0)
+
+inst_55:
+// rs2_val == 536870912, rs1_val == 1431655765, rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x20000000; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x20000000, 0x200, 3f, x2, 188,0)
+
+inst_56:
+// rs2_val == 268435456, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x401; op2val:0x10000000; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x401, 0x10000000, 0x10, 3f, x2, 192,0)
+
+inst_57:
+// rs2_val == 134217728, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x8000000; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x8000000, 0x40, 3f, x2, 196,0)
+
+inst_58:
+// rs2_val == 67108864, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x20; op2val:0x4000000; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x20, 0x4000000, 0x4, 3f, x2, 200,0)
+
+inst_59:
+// rs2_val == 33554432, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x9; op2val:0x2000000; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x9, 0x2000000, 0x100, 3f, x2, 204,0)
+
+inst_60:
+// rs2_val == 16777216, rs1_val == 134217728
+// opcode: beq, op1:x10; op2:x11; op1val:0x8000000; op2val:0x1000000; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x8000000, 0x1000000, 0x100, 3f, x2, 208,0)
+
+inst_61:
+// rs2_val == 8388608, rs1_val == 8388608
+// opcode: beq, op1:x10; op2:x11; op1val:0x800000; op2val:0x800000; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x800000, 0x800000, 0x200, 3f, x2, 212,0)
+
+inst_62:
+// rs2_val == 4194304, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x400000; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x400000, 0x0, 3f, x2, 216,0)
+
+inst_63:
+// rs2_val == 2097152, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x401; op2val:0x200000; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x401, 0x200000, 0x4, 1b, x2, 220,0)
+
+inst_64:
+// rs2_val == 1048576, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8000001; op2val:0x100000; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8000001, 0x100000, 0x556, 1b, x2, 224,0)
+
+inst_65:
+// rs2_val == 524288, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8; op2val:0x80000; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8, 0x80000, 0x400, 1b, x2, 228,0)
+
+inst_66:
+// rs2_val == 262144, rs1_val == 256
+// opcode: beq, op1:x10; op2:x11; op1val:0x100; op2val:0x40000; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x100, 0x40000, 0x0, 1b, x2, 232,0)
+
+inst_67:
+// rs2_val == 65536, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xa; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xa, 0x10000, 0x0, 3f, x2, 236,0)
+
+inst_68:
+// rs2_val == 32768, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x8000; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x8000, 0xa, 1b, x2, 240,0)
+
+inst_69:
+// rs2_val == 16384, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x40001; op2val:0x4000; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x40001, 0x4000, 0x40, 3f, x2, 244,0)
+
+inst_70:
+// rs2_val == 8192, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x8001; op2val:0x2000; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x8001, 0x2000, 0x6, 3f, x2, 248,0)
+
+inst_71:
+// rs2_val == 4096, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x1000; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x1000, 0x400, 1b, x2, 252,0)
+
+inst_72:
+// rs2_val == 2048, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x5; op2val:0x800; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x5, 0x800, 0x4, 1b, x2, 256,0)
+
+inst_73:
+// rs2_val == 1024, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x400001; op2val:0x400; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x400001, 0x400, 0x10, 3f, x2, 260,0)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x101; op2val:0x200; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x101, 0x200, 0x400, 1b, x2, 264,0)
+
+inst_75:
+// rs2_val == 256, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x100; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x100, 0x20, 3f, x2, 268,0)
+
+inst_76:
+// rs2_val == 64, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x40; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x40, 0x40, 3f, x2, 272,0)
+
+inst_77:
+// rs2_val == 32, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x20; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x20, 0x2, 3f, x2, 276,0)
+
+inst_78:
+// rs2_val == 16, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x200001; op2val:0x10; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x200001, 0x10, 0x200, 3f, x2, 280,0)
+
+inst_79:
+// rs2_val == 8, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x8; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x8, 0x6, 1b, x2, 284,0)
+
+inst_80:
+// rs2_val == 4, rs1_val == 16384
+// opcode: beq, op1:x10; op2:x11; op1val:0x4000; op2val:0x4; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4000, 0x4, 0x200, 3f, x2, 288,0)
+
+inst_81:
+// rs2_val == 1, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x20001; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x20001, 0x1, 0x6, 3f, x2, 292,0)
+
+inst_82:
+// rs1_val == -2147483648, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x80000000; op2val:0x40000000; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x80000000, 0x40000000, 0x2, 3f, x2, 296,0)
+
+inst_83:
+// rs1_val == 1073741824, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x40000000; op2val:-0x81; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x40000000, -0x81, 0xa, 1b, x2, 300,0)
+
+inst_84:
+// rs1_val == 536870912, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x20000000; op2val:-0x40000001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x20000000, -0x40000001, 0x4, 3f, x2, 304,0)
+
+inst_85:
+// rs1_val == 268435456, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x10000000; op2val:-0x40000001; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x10000000, -0x40000001, 0x0, 3f, x2, 308,0)
+
+inst_86:
+// rs1_val == 67108864, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4000000; op2val:-0x8; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4000000, -0x8, 0x2, 1b, x2, 312,0)
+
+inst_87:
+// rs1_val == 33554432, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2000000; op2val:0x10; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2000000, 0x10, 0x100, 3f, x2, 316,0)
+
+inst_88:
+// rs1_val == 16777216, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x1000000; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x1000000, 0x6, 0x0, 1b, x2, 320,0)
+
+inst_89:
+// rs1_val == 4194304, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x400000; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x400000, 0x66666666, 0x6, 3f, x2, 324,0)
+
+inst_90:
+// rs1_val == 2097152, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x200000; op2val:-0x2; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x200000, -0x2, 0x80, 3f, x2, 328,0)
+
+inst_91:
+// rs1_val == 1048576, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x100000; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x100000, 0x66666667, 0xa, 1b, x2, 332,0)
+
+inst_92:
+// rs1_val == 524288, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x80000; op2val:-0x101; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x80000, -0x101, 0x6, 3f, x2, 336,0)
+
+inst_93:
+// rs1_val == 262144, rs2_val == 1431655765
+// opcode: beq, op1:x10; op2:x11; op1val:0x40000; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x40000, 0x55555555, 0x6, 3f, x2, 340,0)
+
+inst_94:
+// rs1_val == 131072, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x20000; op2val:-0x10000001; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x20000, -0x10000001, 0x4, 3f, x2, 344,0)
+
+inst_95:
+// rs1_val == 65536, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x10000; op2val:-0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x10000, -0x55555555, 0xa, 1b, x2, 348,0)
+
+inst_96:
+// rs1_val == 4096, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x1000; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x1000, 0x66666665, 0x4, 1b, x2, 352,0)
+
+inst_97:
+// rs1_val == 2048, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x800; op2val:-0x200001; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x800, -0x200001, 0x8, 3f, x2, 356,0)
+
+inst_98:
+// rs1_val == 1024, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x400; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x400, 0x3, 0x8, 3f, x2, 360,0)
+
+inst_99:
+// rs1_val == 128, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x80; op2val:0x2000000; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x80, 0x2000000, 0x6, 1b, x2, 364,0)
+
+inst_100:
+// rs1_val == 64, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x40; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x40, 0x3, 0x8, 1b, x2, 368,0)
+
+inst_101:
+// rs1_val == 16, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x10; op2val:-0x80000000; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x10, -0x80000000, 0x556, 1b, x2, 372,0)
+
+inst_102:
+// rs1_val == 8, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x8; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x8, 0x33333332, 0x2, 1b, x2, 376,0)
+
+inst_103:
+// rs1_val == 2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x7; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x7, 0x100, 3f, x2, 380,0)
+
+inst_104:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0xb505, 0x4, 3f, x2, 384,0)
+
+inst_105:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, -0xb503, 0x400, 1b, x2, 388,0)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x66666667, 0x2, 1b, x2, 392,0)
+
+inst_107:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x33333334, 0x40, 3f, x2, 396,0)
+
+inst_108:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x6, 0x2, 3f, x2, 400,0)
+
+inst_109:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, -0x55555555, 0x10, 3f, x2, 404,0)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x55555556, 0x40, 3f, x2, 408,0)
+
+inst_111:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x4, 0x10, 3f, x2, 412,0)
+
+inst_112:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0xb503, 0x6, 3f, x2, 416,0)
+
+inst_113:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x0, 0x10, 3f, x2, 420,0)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x66666665, 0x200, 3f, x2, 424,0)
+
+inst_115:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x33333332, 0x6, 3f, x2, 428,0)
+
+inst_116:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x55555554, 0x8, 3f, x2, 432,0)
+
+inst_117:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x2, 0x0, 3f, x2, 436,0)
+
+inst_118:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0xb504, 0x4, 3f, x2, 440,0)
+
+inst_119:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, -0xb504, 0x400, 1b, x2, 444,0)
+
+inst_120:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x66666666, 0xa, 1b, x2, 448,0)
+
+inst_121:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x33333333, 0x8, 3f, x2, 452,0)
+
+inst_122:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x5, 0x8, 3f, x2, 456,0)
+
+inst_123:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, -0x55555556, 0xa, 1b, x2, 460,0)
+
+inst_124:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x55555555, 0x0, 1b, x2, 464,0)
+
+inst_125:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb505, 0x3, 0x10, 3f, x2, 468,0)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0xb505, 0x2, 3f, x2, 472,0)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, -0xb503, 0x0, 3f, x2, 476,0)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x66666667, 0x0, 1b, x2, 480,0)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x33333334, 0xa, 1b, x2, 484,0)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x6, 0x80, 3f, x2, 488,0)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, -0x55555555, 0x20, 3f, x2, 492,0)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x55555556, 0x400, 1b, x2, 496,0)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x4, 0x80, 3f, x2, 500,0)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0xb503, 0x6, 3f, x2, 504,0)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x0, 0x400, 3f, x2, 508,0)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x66666665, 0x4, 1b, x2, 512,0)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x33333332, 0x0, 1b, x2, 516,0)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x55555554, 0x10, 3f, x2, 520,0)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x2, 0x40, 3f, x2, 524,0)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0xb504, 0x6, 1b, x2, 528,0)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, -0xb504, 0x4, 1b, x2, 532,0)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x66666666, 0x6, 1b, x2, 536,0)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x33333333, 0x556, 1b, x2, 540,0)
+
+inst_144:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x5; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x5, 0x10, 3f, x2, 544,0)
+
+inst_145:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, -0x55555556, 0xa, 1b, x2, 548,0)
+
+inst_146:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x55555555, 0x8, 3f, x2, 552,0)
+
+inst_147:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb503; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb503, 0x3, 0x10, 3f, x2, 556,0)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0xb505, 0x6, 3f, x2, 560,0)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, -0xb503, 0x80, 3f, x2, 564,0)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x66666667, 0x40, 3f, x2, 568,0)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x33333334, 0x2, 1b, x2, 572,0)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x6, 0x4, 1b, x2, 576,0)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, -0x55555555, 0x200, 3f, x2, 580,0)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x55555556, 0x2, 3f, x2, 584,0)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x4, 0xa, 1b, x2, 588,0)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0xb503, 0xa, 1b, x2, 592,0)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x0, 0x10, 3f, x2, 596,0)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x66666665, 0x200, 3f, x2, 600,0)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x33333332, 0x200, 3f, x2, 604,0)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x55555554, 0x8, 3f, x2, 608,0)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x2, 0x8, 3f, x2, 612,0)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0xb504, 0x8, 1b, x2, 616,0)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, -0xb504, 0x0, 1b, x2, 620,0)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x66666666, 0x4, 3f, x2, 624,0)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x33333333, 0x8, 3f, x2, 628,0)
+
+inst_166:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x5, 0x556, 1b, x2, 632,0)
+
+inst_167:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, -0x55555556, 0x2, 1b, x2, 636,0)
+
+inst_168:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x55555555, 0x2, 3f, x2, 640,0)
+
+inst_169:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666667, 0x3, 0x556, 1b, x2, 644,0)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0xb505, 0x0, 1b, x2, 648,0)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, -0xb503, 0x400, 3f, x2, 652,0)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x66666667, 0x400, 3f, x2, 656,0)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x33333334, 0x2, 3f, x2, 660,0)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x6, 0xa, 1b, x2, 664,0)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, -0x55555555, 0x200, 3f, x2, 668,0)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x55555556, 0x8, 1b, x2, 672,0)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x4, 0x20, 3f, x2, 676,0)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0xb503, 0x4, 1b, x2, 680,0)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x0, 0x100, 3f, x2, 684,0)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x66666665, 0x10, 3f, x2, 688,0)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x33333332, 0x200, 3f, x2, 692,0)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x55555554, 0x400, 1b, x2, 696,0)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x2, 0x4, 1b, x2, 700,0)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0xb504, 0x100, 3f, x2, 704,0)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, -0xb504, 0x0, 1b, x2, 708,0)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x66666666, 0x6, 1b, x2, 712,0)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x33333333, 0x20, 3f, x2, 716,0)
+
+inst_188:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x5, 0x200, 3f, x2, 720,0)
+
+inst_189:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, -0x55555556, 0x40, 3f, x2, 724,0)
+
+inst_190:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x55555555, 0x556, 1b, x2, 728,0)
+
+inst_191:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333334, 0x3, 0x0, 1b, x2, 732,0)
+
+inst_192:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0xb505, 0x20, 3f, x2, 736,0)
+
+inst_193:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:-0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, -0xb503, 0x40, 3f, x2, 740,0)
+
+inst_194:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x66666667, 0x2, 3f, x2, 744,0)
+
+inst_195:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x33333334, 0x556, 1b, x2, 748,0)
+
+inst_196:
+// rs1_val==6 and rs2_val==6, rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x6, 0x8, 1b, x2, 752,0)
+
+inst_197:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, -0x55555555, 0x6, 1b, x2, 756,0)
+
+inst_198:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x55555556, 0x6, 1b, x2, 760,0)
+
+inst_199:
+// rs1_val==6 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x4, 0x2, 3f, x2, 764,0)
+
+inst_200:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0xb503, 0xa, 1b, x2, 768,0)
+
+inst_201:
+// rs1_val==6 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x0, 0x2, 1b, x2, 772,0)
+
+inst_202:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x66666665, 0x80, 3f, x2, 776,0)
+
+inst_203:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x33333332, 0x200, 3f, x2, 780,0)
+
+inst_204:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x55555554, 0x2, 3f, x2, 784,0)
+
+inst_205:
+// rs1_val==6 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x2, 0x0, 1b, x2, 788,0)
+
+inst_206:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0xb504, 0x40, 3f, x2, 792,0)
+
+inst_207:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, -0xb504, 0x8, 1b, x2, 796,0)
+
+inst_208:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x66666666, 0x400, 1b, x2, 800,0)
+
+inst_209:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x33333333, 0x20, 3f, x2, 804,0)
+
+inst_210:
+// rs1_val==6 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x5, 0xa, 1b, x2, 808,0)
+
+inst_211:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, -0x55555556, 0x4, 1b, x2, 812,0)
+
+inst_212:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x55555555, 0x4, 1b, x2, 816,0)
+
+inst_213:
+// rs1_val==6 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x6, 0x3, 0x6, 3f, x2, 820,0)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0xb505, 0x20, 3f, x2, 824,0)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, -0xb503, 0x6, 1b, x2, 828,0)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x66666667, 0x556, 1b, x2, 832,0)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x33333334, 0x8, 3f, x2, 836,0)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x6, 0x40, 3f, x2, 840,0)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, -0x55555555, 0x8, 3f, x2, 844,0)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x55555556, 0xa, 1b, x2, 848,0)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x4, 0x6, 1b, x2, 852,0)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0xb503, 0xa, 1b, x2, 856,0)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x0, 0x6, 3f, x2, 860,0)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x66666665, 0x400, 1b, x2, 864,0)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x33333332, 0x10, 3f, x2, 868,0)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x55555554, 0x400, 1b, x2, 872,0)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x2, 0x0, 3f, x2, 876,0)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0xb504, 0x10, 3f, x2, 880,0)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, -0xb504, 0x0, 1b, x2, 884,0)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x66666666, 0x40, 3f, x2, 888,0)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x33333333, 0x10, 3f, x2, 892,0)
+
+inst_232:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x5, 0x2, 1b, x2, 896,0)
+
+inst_233:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, -0x55555556, 0x2, 3f, x2, 900,0)
+
+inst_234:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x55555555, 0x100, 3f, x2, 904,0)
+
+inst_235:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555555, 0x3, 0xa, 1b, x2, 908,0)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0xb505, 0x400, 3f, x2, 912,0)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, -0xb503, 0xa, 1b, x2, 916,0)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x66666667, 0x6, 1b, x2, 920,0)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x33333334, 0x2, 3f, x2, 924,0)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x6, 0x8, 3f, x2, 928,0)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, -0x55555555, 0x4, 1b, x2, 932,0)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x55555556, 0x0, 1b, x2, 936,0)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x4, 0x200, 3f, x2, 940,0)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0xb503, 0x200, 3f, x2, 944,0)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x0, 0x400, 3f, x2, 948,0)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x66666665, 0x6, 1b, x2, 952,0)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x33333332, 0x0, 1b, x2, 956,0)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x55555554, 0x6, 1b, x2, 960,0)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x2, 0x8, 3f, x2, 964,0)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0xb504, 0x100, 3f, x2, 968,0)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, -0xb504, 0xa, 1b, x2, 972,0)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x66666666, 0x4, 1b, x2, 976,0)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x33333333, 0x4, 1b, x2, 980,0)
+
+inst_254:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x5, 0x6, 1b, x2, 984,0)
+
+inst_255:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, -0x55555556, 0x200, 3f, x2, 988,0)
+
+inst_256:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x55555555, 0x6, 3f, x2, 992,0)
+
+inst_257:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555556, 0x3, 0x2, 3f, x2, 996,0)
+
+inst_258:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0xb505, 0x0, 3f, x2, 1000,0)
+
+inst_259:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:-0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, -0xb503, 0x556, 1b, x2, 1004,0)
+
+inst_260:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x66666667, 0x400, 3f, x2, 1008,0)
+
+inst_261:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x33333334, 0x6, 1b, x2, 1012,0)
+
+inst_262:
+// rs1_val==4 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x6, 0x400, 3f, x2, 1016,0)
+
+inst_263:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, -0x55555555, 0x2, 1b, x2, 1020,0)
+
+inst_264:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x55555556, 0x6, 1b, x2, 1024,0)
+
+inst_265:
+// rs1_val==4 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x4, 0x200, 3f, x2, 1028,0)
+
+inst_266:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0xb503, 0x2, 3f, x2, 1032,0)
+
+inst_267:
+// rs1_val==4 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x0, 0x100, 3f, x2, 1036,0)
+
+inst_268:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x66666665, 0xa, 1b, x2, 1040,0)
+
+inst_269:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x33333332, 0x556, 1b, x2, 1044,0)
+
+inst_270:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x55555554, 0x8, 1b, x2, 1048,0)
+
+inst_271:
+// rs1_val==4 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x2, 0x10, 3f, x2, 1052,0)
+
+inst_272:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0xb504, 0x0, 1b, x2, 1056,0)
+
+inst_273:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:-0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, -0xb504, 0xa, 1b, x2, 1060,0)
+
+inst_274:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x66666666, 0x80, 3f, x2, 1064,0)
+
+inst_275:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x33333333, 0x0, 3f, x2, 1068,0)
+
+inst_276:
+// rs1_val==4 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x5, 0x40, 3f, x2, 1072,0)
+
+inst_277:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, -0x55555556, 0x8, 1b, x2, 1076,0)
+
+inst_278:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x55555555, 0x6, 1b, x2, 1080,0)
+
+inst_279:
+// rs1_val==4 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x4, 0x3, 0x8, 1b, x2, 1084,0)
+
+inst_280:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0xb505, 0x40, 3f, x2, 1088,0)
+
+inst_281:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, -0xb503, 0x2, 1b, x2, 1092,0)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x66666667, 0x10, 3f, x2, 1096,0)
+
+inst_283:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x33333334, 0x20, 3f, x2, 1100,0)
+
+inst_284:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x6, 0x100, 3f, x2, 1104,0)
+
+inst_285:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, -0x55555555, 0x2, 3f, x2, 1108,0)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x55555556, 0x400, 3f, x2, 1112,0)
+
+inst_287:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x4, 0x4, 3f, x2, 1116,0)
+
+inst_288:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0xb503, 0x6, 1b, x2, 1120,0)
+
+inst_289:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x0, 0x556, 1b, x2, 1124,0)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x66666665, 0x400, 3f, x2, 1128,0)
+
+inst_291:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x33333332, 0x8, 1b, x2, 1132,0)
+
+inst_292:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x55555554, 0x0, 3f, x2, 1136,0)
+
+inst_293:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x2, 0x6, 3f, x2, 1140,0)
+
+inst_294:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0xb504, 0x6, 3f, x2, 1144,0)
+
+inst_295:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, -0xb504, 0x400, 1b, x2, 1148,0)
+
+inst_296:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x66666666, 0x0, 1b, x2, 1152,0)
+
+inst_297:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x33333333, 0x20, 3f, x2, 1156,0)
+
+inst_298:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x5, 0x400, 1b, x2, 1160,0)
+
+inst_299:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, -0x55555556, 0x400, 3f, x2, 1164,0)
+
+inst_300:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x55555555, 0x400, 1b, x2, 1168,0)
+
+inst_301:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb503, 0x3, 0x556, 1b, x2, 1172,0)
+
+inst_302:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0xb505, 0x556, 1b, x2, 1176,0)
+
+inst_303:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, -0xb503, 0x2, 1b, x2, 1180,0)
+
+inst_304:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x66666667, 0x10, 3f, x2, 1184,0)
+
+inst_305:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x33333334, 0x2, 1b, x2, 1188,0)
+
+inst_306:
+// rs1_val==0 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x6, 0x80, 3f, x2, 1192,0)
+
+inst_307:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, -0x55555555, 0x80, 3f, x2, 1196,0)
+
+inst_308:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x55555556, 0x400, 1b, x2, 1200,0)
+
+inst_309:
+// rs1_val==0 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x4, 0x10, 3f, x2, 1204,0)
+
+inst_310:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0xb503, 0x4, 3f, x2, 1208,0)
+
+inst_311:
+// rs1_val==0 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x0, 0x8, 1b, x2, 1212,0)
+
+inst_312:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x66666665, 0x6, 3f, x2, 1216,0)
+
+inst_313:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x33333332, 0x200, 3f, x2, 1220,0)
+
+inst_314:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x55555554, 0x100, 3f, x2, 1224,0)
+
+inst_315:
+// rs1_val==0 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x2, 0x80, 3f, x2, 1228,0)
+
+inst_316:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0xb504, 0x40, 3f, x2, 1232,0)
+
+inst_317:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, -0xb504, 0x20, 3f, x2, 1236,0)
+
+inst_318:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x66666666, 0x556, 1b, x2, 1240,0)
+
+inst_319:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x33333333, 0x0, 3f, x2, 1244,0)
+
+inst_320:
+// rs1_val==0 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x5, 0x0, 3f, x2, 1248,0)
+
+inst_321:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, -0x55555556, 0x6, 3f, x2, 1252,0)
+
+inst_322:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x55555555, 0x556, 1b, x2, 1256,0)
+
+inst_323:
+// rs1_val==0 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x0, 0x3, 0x10, 3f, x2, 1260,0)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0xb505, 0x40, 3f, x2, 1264,0)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, -0xb503, 0x6, 3f, x2, 1268,0)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x66666667, 0x8, 3f, x2, 1272,0)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x33333334, 0x4, 1b, x2, 1276,0)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x6, 0x0, 3f, x2, 1280,0)
+
+inst_329:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, -0x55555555, 0x4, 3f, x2, 1284,0)
+
+inst_330:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x55555556, 0x400, 1b, x2, 1288,0)
+
+inst_331:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x4, 0x10, 3f, x2, 1292,0)
+
+inst_332:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0xb503, 0x400, 1b, x2, 1296,0)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x0, 0x6, 3f, x2, 1300,0)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x66666665, 0x40, 3f, x2, 1304,0)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x33333332, 0x400, 3f, x2, 1308,0)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x55555554, 0x6, 1b, x2, 1312,0)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x2, 0x40, 3f, x2, 1316,0)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0xb504, 0x10, 3f, x2, 1320,0)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, -0xb504, 0x20, 3f, x2, 1324,0)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x66666666, 0x2, 3f, x2, 1328,0)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x33333333, 0x4, 3f, x2, 1332,0)
+
+inst_342:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x5, 0x0, 3f, x2, 1336,0)
+
+inst_343:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, -0x55555556, 0x200, 3f, x2, 1340,0)
+
+inst_344:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x55555555, 0x8, 3f, x2, 1344,0)
+
+inst_345:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x3, 0x4, 3f, x2, 1348,0)
+
+inst_346:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0xb505, 0x400, 3f, x2, 1352,0)
+
+inst_347:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, -0xb503, 0x4, 3f, x2, 1356,0)
+
+inst_348:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x66666667, 0x200, 3f, x2, 1360,0)
+
+inst_349:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x33333334, 0x2, 1b, x2, 1364,0)
+
+inst_350:
+// rs1_val==5 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x6, 0x4, 1b, x2, 1368,0)
+
+inst_351:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, -0x55555555, 0x8, 3f, x2, 1372,0)
+
+inst_352:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x55555556, 0x40, 3f, x2, 1376,0)
+
+inst_353:
+// rs1_val==5 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x4, 0x0, 1b, x2, 1380,0)
+
+inst_354:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0xb503, 0x8, 3f, x2, 1384,0)
+
+inst_355:
+// rs1_val==5 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x0, 0xa, 1b, x2, 1388,0)
+
+inst_356:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x66666665, 0x8, 1b, x2, 1392,0)
+
+inst_357:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x33333332, 0x400, 3f, x2, 1396,0)
+
+inst_358:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x55555554, 0x10, 3f, x2, 1400,0)
+
+inst_359:
+// rs1_val==5 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x2, 0x556, 1b, x2, 1404,0)
+
+inst_360:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0xb504, 0x0, 3f, x2, 1408,0)
+
+inst_361:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, -0xb504, 0x400, 1b, x2, 1412,0)
+
+inst_362:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x66666666, 0x2, 3f, x2, 1416,0)
+
+inst_363:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x33333333, 0x6, 3f, x2, 1420,0)
+
+inst_364:
+// rs1_val==5 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x5, 0xa, 1b, x2, 1424,0)
+
+inst_365:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, -0x55555556, 0x8, 3f, x2, 1428,0)
+
+inst_366:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x55555555, 0x2, 3f, x2, 1432,0)
+
+inst_367:
+// rs1_val==5 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x5, 0x3, 0x20, 3f, x2, 1436,0)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0xb505, 0x20, 3f, x2, 1440,0)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, -0xb503, 0x200, 3f, x2, 1444,0)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x66666667, 0x10, 3f, x2, 1448,0)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x33333334, 0x556, 1b, x2, 1452,0)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x6, 0xa, 1b, x2, 1456,0)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, -0x55555555, 0x8, 3f, x2, 1460,0)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x55555556, 0x4, 1b, x2, 1464,0)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x4, 0x6, 1b, x2, 1468,0)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0xb503, 0x8, 3f, x2, 1472,0)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x0, 0x200, 3f, x2, 1476,0)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x66666665, 0x2, 3f, x2, 1480,0)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x33333332, 0x8, 1b, x2, 1484,0)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x55555554, 0x6, 1b, x2, 1488,0)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x2, 0x200, 3f, x2, 1492,0)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0xb504, 0x8, 1b, x2, 1496,0)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, -0xb504, 0x2, 1b, x2, 1500,0)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x66666666, 0x8, 3f, x2, 1504,0)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x33333333, 0x8, 1b, x2, 1508,0)
+
+inst_386:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x5, 0x20, 3f, x2, 1512,0)
+
+inst_387:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, -0x55555556, 0x2, 1b, x2, 1516,0)
+
+inst_388:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x55555555, 0x80, 3f, x2, 1520,0)
+
+inst_389:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x55555556, 0x3, 0x4, 1b, x2, 1524,0)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0xb505, 0x0, 3f, x2, 1528,0)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, -0xb503, 0x100, 3f, x2, 1532,0)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x66666667, 0x0, 3f, x2, 1536,0)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x33333334, 0x40, 3f, x2, 1540,0)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x6, 0x8, 3f, x2, 1544,0)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, -0x55555555, 0x2, 1b, x2, 1548,0)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x55555556, 0x100, 3f, x2, 1552,0)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x4, 0x2, 1b, x2, 1556,0)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0xb503, 0x4, 3f, x2, 1560,0)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x0, 0x10, 3f, x2, 1564,0)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x66666665, 0x400, 1b, x2, 1568,0)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x33333332, 0x20, 3f, x2, 1572,0)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x55555554, 0x40, 3f, x2, 1576,0)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x2, 0x40, 3f, x2, 1580,0)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0xb504, 0x400, 1b, x2, 1584,0)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, -0xb504, 0x400, 3f, x2, 1588,0)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x66666666, 0x40, 3f, x2, 1592,0)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x33333333, 0x6, 3f, x2, 1596,0)
+
+inst_408:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x5, 0x0, 3f, x2, 1600,0)
+
+inst_409:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, -0x55555556, 0x6, 3f, x2, 1604,0)
+
+inst_410:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x55555555, 0x0, 1b, x2, 1608,0)
+
+inst_411:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555555, 0x3, 0x10, 3f, x2, 1612,0)
+
+inst_412:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0xb505, 0x2, 1b, x2, 1616,0)
+
+inst_413:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, -0xb503, 0x0, 1b, x2, 1620,0)
+
+inst_414:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x66666667, 0x0, 1b, x2, 1624,0)
+
+inst_415:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x33333334, 0x4, 1b, x2, 1628,0)
+
+inst_416:
+// rs1_val==3 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x6, 0x0, 1b, x2, 1632,0)
+
+inst_417:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, -0x55555555, 0x400, 1b, x2, 1636,0)
+
+inst_418:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x55555556, 0x8, 3f, x2, 1640,0)
+
+inst_419:
+// rs1_val==3 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x4, 0x80, 3f, x2, 1644,0)
+
+inst_420:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0xb503, 0x80, 3f, x2, 1648,0)
+
+inst_421:
+// rs1_val==3 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x0, 0x10, 3f, x2, 1652,0)
+
+inst_422:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x66666665, 0x6, 3f, x2, 1656,0)
+
+inst_423:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x33333332, 0x400, 1b, x2, 1660,0)
+
+inst_424:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x55555554, 0x0, 1b, x2, 1664,0)
+
+inst_425:
+// rs1_val==3 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x2, 0x400, 3f, x2, 1668,0)
+
+inst_426:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0xb504, 0x200, 3f, x2, 1672,0)
+
+inst_427:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, -0xb504, 0x400, 3f, x2, 1676,0)
+
+inst_428:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x66666666, 0x0, 3f, x2, 1680,0)
+
+inst_429:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x33333333, 0x10, 3f, x2, 1684,0)
+
+inst_430:
+// rs1_val==3 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x5, 0x40, 3f, x2, 1688,0)
+
+inst_431:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, -0x55555556, 0x400, 3f, x2, 1692,0)
+
+inst_432:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x55555555, 0x400, 3f, x2, 1696,0)
+
+inst_433:
+// rs1_val==3 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x3, 0x3, 0x20, 3f, x2, 1700,0)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x0, 0x8, 3f, x2, 1704,0)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x66666665, 0x10, 3f, x2, 1708,0)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x33333332, 0x10, 3f, x2, 1712,0)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x55555554, 0x556, 1b, x2, 1716,0)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x2, 0x0, 1b, x2, 1720,0)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0xb504, 0x0, 1b, x2, 1724,0)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, -0xb504, 0x6, 1b, x2, 1728,0)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x66666666, 0x8, 1b, x2, 1732,0)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x33333333, 0x2, 3f, x2, 1736,0)
+
+inst_443:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x5, 0x0, 1b, x2, 1740,0)
+
+inst_444:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, -0x55555556, 0x40, 3f, x2, 1744,0)
+
+inst_445:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x55555555, 0x6, 3f, x2, 1748,0)
+
+inst_446:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666665, 0x3, 0x4, 3f, x2, 1752,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0xb505, 0x4, 3f, x2, 1756,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, -0xb503, 0x8, 1b, x2, 1760,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x66666667, 0x4, 1b, x2, 1764,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x33333334, 0x4, 3f, x2, 1768,0)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x6, 0xa, 1b, x2, 1772,0)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, -0x55555555, 0x80, 3f, x2, 1776,0)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x55555556, 0x100, 3f, x2, 1780,0)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x4, 0x20, 3f, x2, 1784,0)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0xb503, 0x400, 3f, x2, 1788,0)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x0, 0x6, 3f, x2, 1792,0)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x66666665, 0x4, 1b, x2, 1796,0)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x33333332, 0x80, 3f, x2, 1800,0)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x55555554, 0x4, 3f, x2, 1804,0)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x2, 0x400, 3f, x2, 1808,0)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0xb504, 0x40, 3f, x2, 1812,0)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, -0xb504, 0x200, 3f, x2, 1816,0)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x66666666, 0x2, 1b, x2, 1820,0)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x33333333, 0x8, 3f, x2, 1824,0)
+
+inst_465:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x5, 0x20, 3f, x2, 1828,0)
+
+inst_466:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, -0x55555556, 0x40, 3f, x2, 1832,0)
+
+inst_467:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x55555555, 0x0, 1b, x2, 1836,0)
+
+inst_468:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333332, 0x3, 0x6, 1b, x2, 1840,0)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0xb505, 0x10, 3f, x2, 1844,0)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, -0xb503, 0x20, 3f, x2, 1848,0)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x66666667, 0x6, 3f, x2, 1852,0)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x33333334, 0x200, 3f, x2, 1856,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x6, 0x200, 3f, x2, 1860,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, -0x55555555, 0x400, 1b, x2, 1864,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x55555556, 0xa, 1b, x2, 1868,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x4, 0x20, 3f, x2, 1872,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0xb503, 0x2, 3f, x2, 1876,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x0, 0x6, 3f, x2, 1880,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x66666665, 0x0, 3f, x2, 1884,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x33333332, 0x10, 3f, x2, 1888,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x55555554, 0x0, 3f, x2, 1892,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x2, 0x6, 1b, x2, 1896,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0xb504, 0x0, 3f, x2, 1900,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, -0xb504, 0x4, 1b, x2, 1904,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x66666666, 0x20, 3f, x2, 1908,0)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x33333333, 0x8, 1b, x2, 1912,0)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x5, 0x2, 3f, x2, 1916,0)
+
+inst_488:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, -0x55555556, 0x8, 3f, x2, 1920,0)
+
+inst_489:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x55555555, 0x400, 1b, x2, 1924,0)
+
+inst_490:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x55555554, 0x3, 0x2, 3f, x2, 1928,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0xb505, 0x400, 3f, x2, 1932,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, -0xb503, 0x400, 3f, x2, 1936,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x66666667, 0x4, 3f, x2, 1940,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x33333334, 0x4, 1b, x2, 1944,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x6, 0x100, 3f, x2, 1948,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, -0x55555555, 0x556, 1b, x2, 1952,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x55555556, 0x4, 3f, x2, 1956,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x4, 0x6, 1b, x2, 1960,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0xb503, 0x556, 1b, x2, 1964,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x0, 0x4, 1b, x2, 1968,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x66666665, 0x200, 3f, x2, 1972,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x33333332, 0x0, 1b, x2, 1976,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x55555554, 0x80, 3f, x2, 1980,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x2, 0x2, 1b, x2, 1984,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0xb504, 0x556, 1b, x2, 1988,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, -0xb504, 0x0, 3f, x2, 1992,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x66666666, 0x0, 3f, x2, 1996,0)
+
+inst_508:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x33333333, 0x400, 1b, x2, 2000,0)
+
+inst_509:
+// rs1_val==2 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x5, 0x2, 3f, x2, 2004,0)
+
+inst_510:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, -0x55555556, 0x10, 3f, x2, 2008,0)
+
+inst_511:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x55555555, 0x400, 3f, x2, 2012,0)
+
+inst_512:
+// rs1_val==2 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x2, 0x3, 0x10, 3f, x2, 2016,0)
+
+inst_513:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0xb505, 0x100, 3f, x2, 2020,0)
+
+inst_514:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, -0xb503, 0x4, 1b, x2, 2024,0)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x66666667, 0x2, 3f, x2, 2028,0)
+
+inst_516:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x33333334, 0x8, 3f, x2, 2032,0)
+
+inst_517:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x6, 0x8, 1b, x2, 2036,0)
+
+inst_518:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, -0x55555555, 0x0, 1b, x2, 2040,0)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x55555556, 0x6, 3f, x2, 2044,0)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_520:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x4, 0x6, 1b, x2, 0,0)
+
+inst_521:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0xb503, 0x10, 3f, x2, 4,0)
+
+inst_522:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x0, 0x8, 1b, x2, 8,0)
+
+inst_523:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x66666665, 0x0, 1b, x2, 12,0)
+
+inst_524:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x33333332, 0x400, 3f, x2, 16,0)
+
+inst_525:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x55555554, 0x6, 1b, x2, 20,0)
+
+inst_526:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x2, 0x400, 1b, x2, 24,0)
+
+inst_527:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0xb504, 0x0, 3f, x2, 28,0)
+
+inst_528:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, -0xb504, 0x100, 3f, x2, 32,0)
+
+inst_529:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x66666666, 0x80, 3f, x2, 36,0)
+
+inst_530:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x33333333, 0x8, 1b, x2, 40,0)
+
+inst_531:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x5, 0x2, 1b, x2, 44,0)
+
+inst_532:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, -0x55555556, 0x2, 1b, x2, 48,0)
+
+inst_533:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x55555555, 0x400, 1b, x2, 52,0)
+
+inst_534:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0xb504, 0x3, 0xa, 1b, x2, 56,0)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0xb505, 0x80, 3f, x2, 60,0)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, -0xb503, 0x80, 3f, x2, 64,0)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x66666667, 0x400, 3f, x2, 68,0)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x33333334, 0x6, 3f, x2, 72,0)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x6, 0x200, 3f, x2, 76,0)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, -0x55555555, 0x2, 1b, x2, 80,0)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x55555556, 0x0, 1b, x2, 84,0)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x4, 0x4, 3f, x2, 88,0)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0xb503, 0xa, 1b, x2, 92,0)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x0, 0x0, 3f, x2, 96,0)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x66666665, 0x556, 1b, x2, 100,0)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x33333332, 0x200, 3f, x2, 104,0)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x55555554, 0x80, 3f, x2, 108,0)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x2, 0x4, 1b, x2, 112,0)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0xb504, 0x2, 3f, x2, 116,0)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, -0xb504, 0x4, 1b, x2, 120,0)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x66666666, 0x400, 1b, x2, 124,0)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x33333333, 0x10, 3f, x2, 128,0)
+
+inst_553:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x5, 0x8, 3f, x2, 132,0)
+
+inst_554:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, -0x55555556, 0x6, 3f, x2, 136,0)
+
+inst_555:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x55555555, 0x80, 3f, x2, 140,0)
+
+inst_556:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:-0xb504; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0xb504, 0x3, 0x8, 1b, x2, 144,0)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0xb505, 0x20, 3f, x2, 148,0)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, -0xb503, 0x100, 3f, x2, 152,0)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x66666667, 0x6, 1b, x2, 156,0)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x33333334, 0x100, 3f, x2, 160,0)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x6, 0x200, 3f, x2, 164,0)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, -0x55555555, 0x2, 3f, x2, 168,0)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x55555556, 0x10, 3f, x2, 172,0)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x4, 0x4, 3f, x2, 176,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0xb503, 0x100, 3f, x2, 180,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x0, 0x20, 3f, x2, 184,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x66666665, 0x556, 1b, x2, 188,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x33333332, 0x200, 3f, x2, 192,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x55555554, 0x2, 1b, x2, 196,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x2, 0x400, 1b, x2, 200,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0xb504, 0x100, 3f, x2, 204,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, -0xb504, 0x2, 3f, x2, 208,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x66666666, 0x0, 3f, x2, 212,0)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x33333333, 0x0, 3f, x2, 216,0)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x5, 0x40, 3f, x2, 220,0)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, -0x55555556, 0x556, 1b, x2, 224,0)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x55555555, 0x556, 1b, x2, 228,0)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x66666666, 0x3, 0x556, 1b, x2, 232,0)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0xb505, 0x400, 1b, x2, 236,0)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, -0xb503, 0x10, 3f, x2, 240,0)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x66666667, 0xa, 1b, x2, 244,0)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x33333334, 0x200, 3f, x2, 248,0)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x6, 0x0, 3f, x2, 252,0)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, -0x55555555, 0x4, 3f, x2, 256,0)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x55555556, 0xa, 1b, x2, 260,0)
+
+inst_586:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0x4, 0x400, 1b, x2, 264,0)
+
+inst_587:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: beq, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, 0x33333333, 0xb503, 0x400, 1b, x2, 268,0)
+
+inst_588:
+// rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs2_val == -67108865, rs1_val == -33554433
+// opcode: beq, op1:x10; op2:x11; op1val:-0x2000001; op2val:-0x4000001; immval:0x8; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x2000001, -0x4000001, 0x8, 3f, x2, 272,0)
+
+inst_589:
+// rs2_val == -524289, rs1_val == -536870913
+// opcode: beq, op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x80001; immval:0x6; align:0
+TEST_BRANCH_OP(beq, x1, x10, x11, -0x20000001, -0x80001, 0x6, 1b, x2, 276,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 70*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S
new file mode 100644
index 000000000..d8cd00477
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S
@@ -0,0 +1,3016 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the bge instruction of the RISC-V E extension for the bge covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",bge)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 == rs2, rs1==x9, rs2==x9, rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val == -65537, rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x9; op2:x9; op1val:-0x10001; op2val:-0x10001; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x14, x9, x9, -0x10001, -0x10001, 0x400, 1b, x2, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x8, rs2==x7, rs2_val == 2147483647, rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs1_val == 4, rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x8; op2:x7; op1val:0x4; op2val:0x7fffffff; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x14, x8, x7, 0x4, 0x7fffffff, 0x10, 3f, x2, 4,0)
+
+inst_2:
+// rs1==x5, rs2==x11, rs2_val == -1073741825, 
+// opcode: bge, op1:x5; op2:x11; op1val:0x4; op2val:-0x40000001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x14, x5, x11, 0x4, -0x40000001, 0x2, 1b, x2, 8,0)
+
+inst_3:
+// rs1==x12, rs2==x0, rs2_val == -536870913, rs1_val == -32769, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x12; op2:x0; op1val:-0x8001; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x14, x12, x0, -0x8001, 0x0, 0x20, 3f, x2, 12,0)
+
+inst_4:
+// rs1==x3, rs2==x4, rs2_val == -268435457, rs1_val == 536870912
+// opcode: bge, op1:x3; op2:x4; op1val:0x20000000; op2val:-0x10000001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x14, x3, x4, 0x20000000, -0x10000001, 0x2, 3f, x2, 16,0)
+
+inst_5:
+// rs1==x11, rs2==x1, rs2_val == -134217729, rs1_val == 128, rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x11; op2:x1; op1val:0x80; op2val:-0x8000001; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x14, x11, x1, 0x80, -0x8000001, 0x10, 3f, x2, 20,0)
+
+inst_6:
+// rs1==x0, rs2==x12, rs2_val == -67108865, rs1_val == 256
+// opcode: bge, op1:x0; op2:x12; op1val:0x0; op2val:-0x4000001; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x14, x0, x12, 0x0, -0x4000001, 0x556, 1b, x2, 24,0)
+
+inst_7:
+// rs1==x7, rs2==x6, rs2_val == -33554433, rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x7; op2:x6; op1val:0x80; op2val:-0x2000001; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x14, x7, x6, 0x80, -0x2000001, 0x4, 1b, x2, 28,0)
+
+inst_8:
+// rs1==x13, rs2==x10, rs2_val == -16777217, rs1_val == 8388608
+// opcode: bge, op1:x13; op2:x10; op1val:0x800000; op2val:-0x1000001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x14, x13, x10, 0x800000, -0x1000001, 0x2, 1b, x2, 32,0)
+RVTEST_SIGBASE( x7,signature_x7_0)
+
+inst_9:
+// rs1==x1, rs2==x3, rs2_val == -8388609, rs1_val == 268435456
+// opcode: bge, op1:x1; op2:x3; op1val:0x10000000; op2val:-0x800001; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x9, x1, x3, 0x10000000, -0x800001, 0x80, 3f, x7, 0,0)
+
+inst_10:
+// rs1==x2, rs2==x13, rs2_val == -4194305, rs1_val == 32768
+// opcode: bge, op1:x2; op2:x13; op1val:0x8000; op2val:-0x400001; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x9, x2, x13, 0x8000, -0x400001, 0x40, 3f, x7, 4,0)
+
+inst_11:
+// rs1==x14, rs2==x5, rs2_val == -2097153, rs1_val == 2147483647
+// opcode: bge, op1:x14; op2:x5; op1val:0x7fffffff; op2val:-0x200001; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x9, x14, x5, 0x7fffffff, -0x200001, 0x100, 3f, x7, 8,0)
+
+inst_12:
+// rs1==x10, rs2==x15, rs2_val == -1048577, rs1_val == -262145
+// opcode: bge, op1:x10; op2:x15; op1val:-0x40001; op2val:-0x100001; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x9, x10, x15, -0x40001, -0x100001, 0x8, 3f, x7, 12,0)
+
+inst_13:
+// rs1==x6, rs2==x8, rs2_val == -524289, 
+// opcode: bge, op1:x6; op2:x8; op1val:0x0; op2val:-0x80001; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x9, x6, x8, 0x0, -0x80001, 0x0, 1b, x7, 16,0)
+
+inst_14:
+// rs1==x4, rs2==x14, rs2_val == -262145, rs1_val == 65536
+// opcode: bge, op1:x4; op2:x14; op1val:0x10000; op2val:-0x40001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x9, x4, x14, 0x10000, -0x40001, 0x2, 1b, x7, 20,0)
+
+inst_15:
+// rs1==x15, rs2==x2, rs2_val == -131073, 
+// opcode: bge, op1:x15; op2:x2; op1val:0x55555554; op2val:-0x20001; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x15, x2, 0x55555554, -0x20001, 0x80, 3f, x7, 24,0)
+
+inst_16:
+// rs2_val == -65537, rs1_val == -3
+// opcode: bge, op1:x10; op2:x11; op1val:-0x3; op2val:-0x10001; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x3, -0x10001, 0x0, 1b, x7, 28,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_17:
+// rs2_val == -32769, rs1_val == 1431655765
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x8001; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0x8001, 0x8, 3f, x1, 0,0)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x4001; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0x4001, 0x100, 3f, x1, 4,0)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -131073
+// opcode: bge, op1:x10; op2:x11; op1val:-0x20001; op2val:-0x2001; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x20001, -0x2001, 0x4, 3f, x1, 8,0)
+
+inst_20:
+// rs2_val == -4097, rs1_val == -1048577
+// opcode: bge, op1:x10; op2:x11; op1val:-0x100001; op2val:-0x1001; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x100001, -0x1001, 0x400, 1b, x1, 12,0)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x801; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, -0x801, 0x20, 3f, x1, 16,0)
+
+inst_22:
+// rs2_val == -1025, rs1_val == 512
+// opcode: bge, op1:x10; op2:x11; op1val:0x200; op2val:-0x401; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x200, -0x401, 0x4, 3f, x1, 20,0)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:-0x201; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, -0x201, 0x556, 1b, x1, 24,0)
+
+inst_24:
+// rs2_val == -257, rs1_val == -16777217
+// opcode: bge, op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x101; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x1000001, -0x101, 0x40, 3f, x1, 28,0)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x81; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x1000001, -0x81, 0x0, 3f, x1, 32,0)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x80; op2val:-0x41; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x80, -0x41, 0x400, 3f, x1, 36,0)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x1; op2val:-0x21; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x1, -0x21, 0x100, 3f, x1, 40,0)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3fffffff; op2val:-0x11; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3fffffff, -0x11, 0xa, 1b, x1, 44,0)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:-0x9; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, -0x9, 0x2, 3f, x1, 48,0)
+
+inst_30:
+// rs2_val == -5, rs1_val == 67108864
+// opcode: bge, op1:x10; op2:x11; op1val:0x4000000; op2val:-0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4000000, -0x5, 0x20, 3f, x1, 52,0)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3fffffff; op2val:-0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3fffffff, -0x3, 0x10, 3f, x1, 56,0)
+
+inst_32:
+// rs2_val == -2, rs1_val == -2049
+// opcode: bge, op1:x10; op2:x11; op1val:-0x801; op2val:-0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x801, -0x2, 0x4, 3f, x1, 60,0)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 262144
+// opcode: bge, op1:x10; op2:x11; op1val:-0x40000001; op2val:0x40000; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x40000001, 0x40000, 0xa, 1b, x1, 64,0)
+
+inst_34:
+// rs1_val == -536870913, rs2_val == 32
+// opcode: bge, op1:x10; op2:x11; op1val:-0x20000001; op2val:0x20; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x20000001, 0x20, 0xa, 1b, x1, 68,0)
+
+inst_35:
+// rs1_val == -268435457, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x10000001; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x10000001, 0x0, 0x2, 1b, x1, 72,0)
+
+inst_36:
+// rs1_val == -134217729, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x8000001; op2val:-0x7; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x8000001, -0x7, 0x20, 3f, x1, 76,0)
+
+inst_37:
+// rs1_val == -67108865, rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x10; op2:x11; op1val:-0x4000001; op2val:0x7fffffff; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x4000001, 0x7fffffff, 0x400, 1b, x1, 80,0)
+
+inst_38:
+// rs1_val == -33554433, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x2000001; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x2000001, 0x33333333, 0x8, 3f, x1, 84,0)
+
+inst_39:
+// rs1_val == -8388609, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x800001; op2val:-0x40001; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x800001, -0x40001, 0x8, 3f, x1, 88,0)
+
+inst_40:
+// rs1_val == -4194305, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x400001; op2val:-0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x400001, -0x4, 0x0, 1b, x1, 92,0)
+
+inst_41:
+// rs1_val == -2097153, rs2_val == 2
+// opcode: bge, op1:x10; op2:x11; op1val:-0x200001; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x200001, 0x2, 0x0, 1b, x1, 96,0)
+
+inst_42:
+// rs1_val == -524289, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x80001; op2val:-0x4001; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x80001, -0x4001, 0xa, 1b, x1, 100,0)
+
+inst_43:
+// rs1_val == -16385, rs2_val == 1073741824
+// opcode: bge, op1:x10; op2:x11; op1val:-0x4001; op2val:0x40000000; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x4001, 0x40000000, 0x40, 3f, x1, 104,0)
+
+inst_44:
+// rs1_val == -8193, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x2001; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x2001, 0x2, 0x4, 3f, x1, 108,0)
+
+inst_45:
+// rs1_val == -4097, rs2_val == -1431655766
+// opcode: bge, op1:x10; op2:x11; op1val:-0x1001; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x1001, -0x55555556, 0xa, 1b, x1, 112,0)
+
+inst_46:
+// rs1_val == -1025, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x401; op2val:-0x10000001; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x401, -0x10000001, 0x400, 3f, x1, 116,0)
+
+inst_47:
+// rs1_val == -513, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x201; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x201, 0x0, 0x556, 1b, x1, 120,0)
+
+inst_48:
+// rs1_val == -257, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x101; op2val:0x20; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x101, 0x20, 0x4, 1b, x1, 124,0)
+
+inst_49:
+// rs1_val == -129, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x81; op2val:-0x40000001; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x81, -0x40000001, 0x8, 1b, x1, 128,0)
+
+inst_50:
+// rs1_val == -65, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x41; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x41, 0xb503, 0x8, 1b, x1, 132,0)
+
+inst_51:
+// rs1_val == -33, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x21; op2val:-0x40000000; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x21, -0x40000000, 0x2, 3f, x1, 136,0)
+
+inst_52:
+// rs1_val == -17, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x11; op2val:-0x100001; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x11, -0x100001, 0x4, 3f, x1, 140,0)
+
+inst_53:
+// rs1_val == -9, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x9; op2val:-0x2001; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x9, -0x2001, 0x200, 3f, x1, 144,0)
+
+inst_54:
+// rs1_val == -5, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x5; op2val:-0x201; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x5, -0x201, 0x2, 1b, x1, 148,0)
+
+inst_55:
+// rs1_val == -2, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x2; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x2, 0x33333334, 0x100, 3f, x1, 152,0)
+
+inst_56:
+// rs2_val == -2147483648, rs1_val == -1431655766
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x80000000; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, -0x80000000, 0x6, 1b, x1, 156,0)
+
+inst_57:
+// rs2_val == 536870912, rs1_val == 32
+// opcode: bge, op1:x10; op2:x11; op1val:0x20; op2val:0x20000000; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x20, 0x20000000, 0x6, 3f, x1, 160,0)
+
+inst_58:
+// rs2_val == 268435456, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x5; op2val:0x10000000; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x5, 0x10000000, 0x4, 1b, x1, 164,0)
+
+inst_59:
+// rs2_val == 134217728, rs1_val == 524288
+// opcode: bge, op1:x10; op2:x11; op1val:0x80000; op2val:0x8000000; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x80000, 0x8000000, 0x4, 1b, x1, 168,0)
+
+inst_60:
+// rs2_val == 67108864, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x4000000; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x4000000, 0xa, 1b, x1, 172,0)
+
+inst_61:
+// rs2_val == 33554432, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2000000; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x2000000, 0x6, 3f, x1, 176,0)
+
+inst_62:
+// rs2_val == 16777216, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x1000000; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x1000000, 0x10, 3f, x1, 180,0)
+
+inst_63:
+// rs2_val == 8388608, rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x10; op2:x11; op1val:0x800000; op2val:0x800000; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x800000, 0x800000, 0x80, 3f, x1, 184,0)
+
+inst_64:
+// rs2_val == 4194304, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x400001; op2val:0x400000; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x400001, 0x400000, 0x6, 3f, x1, 188,0)
+
+inst_65:
+// rs2_val == 2097152, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x200000; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x200000, 0x80, 3f, x1, 192,0)
+
+inst_66:
+// rs2_val == 1048576, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x3; op2val:0x100000; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x3, 0x100000, 0x40, 3f, x1, 196,0)
+
+inst_67:
+// rs2_val == 524288, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x10000000; op2val:0x80000; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x10000000, 0x80000, 0x4, 3f, x1, 200,0)
+
+inst_68:
+// rs2_val == 131072, rs1_val == 8
+// opcode: bge, op1:x10; op2:x11; op1val:0x8; op2val:0x20000; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x8, 0x20000, 0x556, 1b, x1, 204,0)
+
+inst_69:
+// rs2_val == 65536, rs1_val == 1024
+// opcode: bge, op1:x10; op2:x11; op1val:0x400; op2val:0x10000; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x400, 0x10000, 0x40, 3f, x1, 208,0)
+
+inst_70:
+// rs2_val == 32768, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x8000; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x8000, 0xa, 1b, x1, 212,0)
+
+inst_71:
+// rs2_val == 16384, rs1_val == 2048
+// opcode: bge, op1:x10; op2:x11; op1val:0x800; op2val:0x4000; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x800, 0x4000, 0x200, 3f, x1, 216,0)
+
+inst_72:
+// rs2_val == 8192, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x100; op2val:0x2000; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x100, 0x2000, 0x40, 3f, x1, 220,0)
+
+inst_73:
+// rs2_val == 4096, rs1_val == 2
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x1000; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x1000, 0x0, 3f, x1, 224,0)
+
+inst_74:
+// rs2_val == 2048, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x800; op2val:0x800; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x800, 0x800, 0x400, 3f, x1, 228,0)
+
+inst_75:
+// rs2_val == 1024, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x400; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x400, 0x8, 3f, x1, 232,0)
+
+inst_76:
+// rs2_val == 512, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x200; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x200, 0x400, 3f, x1, 236,0)
+
+inst_77:
+// rs2_val == 256, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x5; op2val:0x100; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x5, 0x100, 0x400, 3f, x1, 240,0)
+
+inst_78:
+// rs2_val == 128, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x80; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x80, 0x8, 1b, x1, 244,0)
+
+inst_79:
+// rs2_val == 64, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x10000; op2val:0x40; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x10000, 0x40, 0x100, 3f, x1, 248,0)
+
+inst_80:
+// rs2_val == 16, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x401; op2val:0x10; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x401, 0x10, 0x200, 3f, x1, 252,0)
+
+inst_81:
+// rs2_val == 8, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x8; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x8, 0x400, 3f, x1, 256,0)
+
+inst_82:
+// rs2_val == 4, rs1_val == 131072
+// opcode: bge, op1:x10; op2:x11; op1val:0x20000; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x20000, 0x4, 0x6, 3f, x1, 260,0)
+
+inst_83:
+// rs2_val == 1, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x10000; op2val:0x1; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x10000, 0x1, 0x40, 3f, x1, 264,0)
+
+inst_84:
+// rs1_val == -2147483648, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x80000000; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x80000000, 0x2, 0x8, 1b, x1, 268,0)
+
+inst_85:
+// rs1_val == 1073741824, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x40000000; op2val:-0x401; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x40000000, -0x401, 0x10, 3f, x1, 272,0)
+
+inst_86:
+// rs1_val == 134217728, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x8000000; op2val:-0x2; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x8000000, -0x2, 0xa, 1b, x1, 276,0)
+
+inst_87:
+// rs1_val == 33554432, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2000000; op2val:-0x40000001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2000000, -0x40000001, 0x2, 3f, x1, 280,0)
+
+inst_88:
+// rs1_val == 16777216, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x1000000; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x1000000, 0x0, 0x2, 3f, x1, 284,0)
+
+inst_89:
+// rs1_val == 4194304, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x400000; op2val:-0x8000001; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x400000, -0x8000001, 0x2, 3f, x1, 288,0)
+
+inst_90:
+// rs1_val == 2097152, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x200000; op2val:0x4000000; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x200000, 0x4000000, 0x0, 1b, x1, 292,0)
+
+inst_91:
+// rs1_val == 1048576, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x100000; op2val:-0x401; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x100000, -0x401, 0x0, 1b, x1, 296,0)
+
+inst_92:
+// rs1_val == 262144, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x40000; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x40000, 0x0, 0x2, 3f, x1, 300,0)
+
+inst_93:
+// rs1_val == 16384, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4000; op2val:0x8000000; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4000, 0x8000000, 0x4, 3f, x1, 304,0)
+
+inst_94:
+// rs1_val == 8192, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2000; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2000, 0x0, 0x2, 3f, x1, 308,0)
+
+inst_95:
+// rs1_val == 4096, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x1000; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x1000, -0xb503, 0x4, 3f, x1, 312,0)
+
+inst_96:
+// rs1_val == 64, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x40; op2val:-0x1000001; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x40, -0x1000001, 0x556, 1b, x1, 316,0)
+
+inst_97:
+// rs1_val == 16, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x10; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x10, 0x0, 0x4, 3f, x1, 320,0)
+
+inst_98:
+// rs1_val == 1, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x1; op2val:0x3fffffff; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x1, 0x3fffffff, 0x100, 3f, x1, 324,0)
+
+inst_99:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0xb505, 0x20, 3f, x1, 328,0)
+
+inst_100:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, -0xb503, 0x200, 3f, x1, 332,0)
+
+inst_101:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x66666667, 0x0, 3f, x1, 336,0)
+
+inst_102:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x33333334, 0x8, 3f, x1, 340,0)
+
+inst_103:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x6, 0x10, 3f, x1, 344,0)
+
+inst_104:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, -0x55555555, 0x4, 1b, x1, 348,0)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x55555556, 0xa, 1b, x1, 352,0)
+
+inst_106:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x4, 0x100, 3f, x1, 356,0)
+
+inst_107:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0xb503, 0x2, 1b, x1, 360,0)
+
+inst_108:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x0, 0x4, 1b, x1, 364,0)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x66666665, 0x80, 3f, x1, 368,0)
+
+inst_110:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x33333332, 0x0, 1b, x1, 372,0)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x55555554, 0x400, 1b, x1, 376,0)
+
+inst_112:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x2, 0x2, 1b, x1, 380,0)
+
+inst_113:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0xb504, 0x2, 3f, x1, 384,0)
+
+inst_114:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, -0xb504, 0x20, 3f, x1, 388,0)
+
+inst_115:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x66666666, 0x400, 3f, x1, 392,0)
+
+inst_116:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x33333333, 0x200, 3f, x1, 396,0)
+
+inst_117:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x5, 0x10, 3f, x1, 400,0)
+
+inst_118:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, -0x55555556, 0x20, 3f, x1, 404,0)
+
+inst_119:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x55555555, 0xa, 1b, x1, 408,0)
+
+inst_120:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb505, 0x3, 0x10, 3f, x1, 412,0)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0xb505, 0x100, 3f, x1, 416,0)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, -0xb503, 0x2, 3f, x1, 420,0)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x66666667, 0x4, 3f, x1, 424,0)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x33333334, 0x2, 1b, x1, 428,0)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x6, 0x4, 1b, x1, 432,0)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, -0x55555555, 0x4, 3f, x1, 436,0)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x55555556, 0x2, 3f, x1, 440,0)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x4, 0x8, 1b, x1, 444,0)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0xb503, 0x40, 3f, x1, 448,0)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x0, 0x80, 3f, x1, 452,0)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x66666665, 0x100, 3f, x1, 456,0)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x33333332, 0x4, 3f, x1, 460,0)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x55555554, 0x556, 1b, x1, 464,0)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x2, 0x100, 3f, x1, 468,0)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0xb504, 0x200, 3f, x1, 472,0)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, -0xb504, 0x400, 1b, x1, 476,0)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x66666666, 0x2, 3f, x1, 480,0)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x33333333, 0x0, 3f, x1, 484,0)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x5, 0x8, 3f, x1, 488,0)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, -0x55555556, 0x2, 1b, x1, 492,0)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x55555555, 0x556, 1b, x1, 496,0)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb503; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb503, 0x3, 0x4, 1b, x1, 500,0)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0xb505, 0x8, 3f, x1, 504,0)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, -0xb503, 0x2, 1b, x1, 508,0)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x66666667, 0xa, 1b, x1, 512,0)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x33333334, 0x100, 3f, x1, 516,0)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x6, 0x10, 3f, x1, 520,0)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, -0x55555555, 0x100, 3f, x1, 524,0)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x55555556, 0x0, 1b, x1, 528,0)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x4, 0x6, 1b, x1, 532,0)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0xb503, 0xa, 1b, x1, 536,0)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x0, 0x100, 3f, x1, 540,0)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x66666665, 0x2, 1b, x1, 544,0)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x33333332, 0x556, 1b, x1, 548,0)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x55555554, 0x556, 1b, x1, 552,0)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x2, 0x100, 3f, x1, 556,0)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0xb504, 0x10, 3f, x1, 560,0)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, -0xb504, 0x200, 3f, x1, 564,0)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x66666666, 0x0, 3f, x1, 568,0)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x33333333, 0x400, 1b, x1, 572,0)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x5, 0x200, 3f, x1, 576,0)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, -0x55555556, 0x2, 3f, x1, 580,0)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x55555555, 0x10, 3f, x1, 584,0)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666667, 0x3, 0x2, 3f, x1, 588,0)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0xb505, 0x0, 1b, x1, 592,0)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, -0xb503, 0x10, 3f, x1, 596,0)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x66666667, 0x100, 3f, x1, 600,0)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==858993460, rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x33333334, 0x0, 1b, x1, 604,0)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x6, 0x8, 1b, x1, 608,0)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, -0x55555555, 0x6, 1b, x1, 612,0)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x55555556, 0x8, 3f, x1, 616,0)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x4, 0x400, 1b, x1, 620,0)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0xb503, 0x556, 1b, x1, 624,0)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x0, 0x10, 3f, x1, 628,0)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x66666665, 0x400, 3f, x1, 632,0)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x33333332, 0x80, 3f, x1, 636,0)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x55555554, 0x2, 1b, x1, 640,0)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x2, 0x0, 1b, x1, 644,0)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0xb504, 0x400, 3f, x1, 648,0)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, -0xb504, 0x10, 3f, x1, 652,0)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x66666666, 0x6, 3f, x1, 656,0)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x33333333, 0x0, 3f, x1, 660,0)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x5, 0x0, 1b, x1, 664,0)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, -0x55555556, 0x6, 1b, x1, 668,0)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x55555555, 0x2, 3f, x1, 672,0)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333334, 0x3, 0x8, 3f, x1, 676,0)
+
+inst_187:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0xb505, 0x10, 3f, x1, 680,0)
+
+inst_188:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:-0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, -0xb503, 0x40, 3f, x1, 684,0)
+
+inst_189:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x66666667, 0x4, 3f, x1, 688,0)
+
+inst_190:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x33333334, 0x4, 1b, x1, 692,0)
+
+inst_191:
+// rs1_val==6 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x6, 0x0, 1b, x1, 696,0)
+
+inst_192:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, -0x55555555, 0x2, 1b, x1, 700,0)
+
+inst_193:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x55555556, 0x10, 3f, x1, 704,0)
+
+inst_194:
+// rs1_val==6 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x4, 0x400, 3f, x1, 708,0)
+
+inst_195:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0xb503, 0x10, 3f, x1, 712,0)
+
+inst_196:
+// rs1_val==6 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x0, 0x0, 1b, x1, 716,0)
+
+inst_197:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x66666665, 0x80, 3f, x1, 720,0)
+
+inst_198:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x33333332, 0x40, 3f, x1, 724,0)
+
+inst_199:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x55555554, 0xa, 1b, x1, 728,0)
+
+inst_200:
+// rs1_val==6 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x2, 0x2, 1b, x1, 732,0)
+
+inst_201:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0xb504, 0x6, 3f, x1, 736,0)
+
+inst_202:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, -0xb504, 0x400, 3f, x1, 740,0)
+
+inst_203:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x66666666, 0x6, 1b, x1, 744,0)
+
+inst_204:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x33333333, 0x2, 1b, x1, 748,0)
+
+inst_205:
+// rs1_val==6 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x5, 0x8, 3f, x1, 752,0)
+
+inst_206:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, -0x55555556, 0x0, 1b, x1, 756,0)
+
+inst_207:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x55555555, 0x400, 3f, x1, 760,0)
+
+inst_208:
+// rs1_val==6 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x6, 0x3, 0x2, 3f, x1, 764,0)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0xb505, 0x2, 1b, x1, 768,0)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, -0xb503, 0x4, 3f, x1, 772,0)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x66666667, 0x0, 3f, x1, 776,0)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x33333334, 0x0, 1b, x1, 780,0)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x6, 0x20, 3f, x1, 784,0)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, -0x55555555, 0x10, 3f, x1, 788,0)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x55555556, 0x8, 3f, x1, 792,0)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x4, 0x4, 3f, x1, 796,0)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0xb503, 0x20, 3f, x1, 800,0)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x0, 0x20, 3f, x1, 804,0)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x66666665, 0x2, 1b, x1, 808,0)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x33333332, 0x200, 3f, x1, 812,0)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x55555554, 0x400, 3f, x1, 816,0)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x2, 0x6, 3f, x1, 820,0)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0xb504, 0x6, 3f, x1, 824,0)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, -0xb504, 0x0, 3f, x1, 828,0)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x66666666, 0x400, 3f, x1, 832,0)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x33333333, 0x8, 3f, x1, 836,0)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x5, 0x8, 1b, x1, 840,0)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, -0x55555556, 0x2, 1b, x1, 844,0)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x55555555, 0x100, 3f, x1, 848,0)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555555, 0x3, 0x8, 1b, x1, 852,0)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0xb505, 0x40, 3f, x1, 856,0)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, -0xb503, 0x556, 1b, x1, 860,0)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x66666667, 0x2, 3f, x1, 864,0)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x33333334, 0x0, 3f, x1, 868,0)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x6, 0x40, 3f, x1, 872,0)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, -0x55555555, 0x6, 3f, x1, 876,0)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x55555556, 0x2, 1b, x1, 880,0)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x4, 0x10, 3f, x1, 884,0)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0xb503, 0x6, 1b, x1, 888,0)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x0, 0x10, 3f, x1, 892,0)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x66666665, 0x0, 1b, x1, 896,0)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x33333332, 0x400, 3f, x1, 900,0)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x55555554, 0x100, 3f, x1, 904,0)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x2, 0x10, 3f, x1, 908,0)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0xb504, 0x400, 3f, x1, 912,0)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, -0xb504, 0x8, 1b, x1, 916,0)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x66666666, 0x100, 3f, x1, 920,0)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x33333333, 0x4, 3f, x1, 924,0)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x5, 0xa, 1b, x1, 928,0)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, -0x55555556, 0x0, 1b, x1, 932,0)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x55555555, 0x200, 3f, x1, 936,0)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555556, 0x3, 0x400, 1b, x1, 940,0)
+
+inst_253:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0xb505, 0x20, 3f, x1, 944,0)
+
+inst_254:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:-0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, -0xb503, 0x200, 3f, x1, 948,0)
+
+inst_255:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x66666667, 0x2, 3f, x1, 952,0)
+
+inst_256:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x33333334, 0x40, 3f, x1, 956,0)
+
+inst_257:
+// rs1_val==4 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x6, 0xa, 1b, x1, 960,0)
+
+inst_258:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, -0x55555555, 0x20, 3f, x1, 964,0)
+
+inst_259:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x55555556, 0xa, 1b, x1, 968,0)
+
+inst_260:
+// rs1_val==4 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x4, 0x6, 1b, x1, 972,0)
+
+inst_261:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0xb503, 0x400, 1b, x1, 976,0)
+
+inst_262:
+// rs1_val==4 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x0, 0x100, 3f, x1, 980,0)
+
+inst_263:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x66666665, 0x100, 3f, x1, 984,0)
+
+inst_264:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x33333332, 0x400, 3f, x1, 988,0)
+
+inst_265:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x55555554, 0x200, 3f, x1, 992,0)
+
+inst_266:
+// rs1_val==4 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x2, 0x80, 3f, x1, 996,0)
+
+inst_267:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0xb504, 0x400, 1b, x1, 1000,0)
+
+inst_268:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, -0xb504, 0x0, 3f, x1, 1004,0)
+
+inst_269:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x66666666, 0x10, 3f, x1, 1008,0)
+
+inst_270:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x33333333, 0x4, 1b, x1, 1012,0)
+
+inst_271:
+// rs1_val==4 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x5, 0x80, 3f, x1, 1016,0)
+
+inst_272:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, -0x55555556, 0x6, 3f, x1, 1020,0)
+
+inst_273:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x55555555, 0x0, 1b, x1, 1024,0)
+
+inst_274:
+// rs1_val==4 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x4, 0x3, 0x40, 3f, x1, 1028,0)
+
+inst_275:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0xb505, 0x2, 1b, x1, 1032,0)
+
+inst_276:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, -0xb503, 0x400, 1b, x1, 1036,0)
+
+inst_277:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x66666667, 0x400, 1b, x1, 1040,0)
+
+inst_278:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x33333334, 0xa, 1b, x1, 1044,0)
+
+inst_279:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x6, 0x2, 3f, x1, 1048,0)
+
+inst_280:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, -0x55555555, 0x10, 3f, x1, 1052,0)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x55555556, 0x2, 1b, x1, 1056,0)
+
+inst_282:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x4, 0x2, 1b, x1, 1060,0)
+
+inst_283:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0xb503, 0x6, 3f, x1, 1064,0)
+
+inst_284:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x0, 0x20, 3f, x1, 1068,0)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x66666665, 0x0, 1b, x1, 1072,0)
+
+inst_286:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x33333332, 0x0, 1b, x1, 1076,0)
+
+inst_287:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x55555554, 0x8, 1b, x1, 1080,0)
+
+inst_288:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x2, 0x8, 1b, x1, 1084,0)
+
+inst_289:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0xb504, 0x4, 3f, x1, 1088,0)
+
+inst_290:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, -0xb504, 0x200, 3f, x1, 1092,0)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x66666666, 0x400, 3f, x1, 1096,0)
+
+inst_292:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x33333333, 0x100, 3f, x1, 1100,0)
+
+inst_293:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x5, 0x400, 1b, x1, 1104,0)
+
+inst_294:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, -0x55555556, 0x4, 1b, x1, 1108,0)
+
+inst_295:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x55555555, 0x8, 1b, x1, 1112,0)
+
+inst_296:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb503, 0x3, 0x4, 3f, x1, 1116,0)
+
+inst_297:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0xb505, 0x2, 1b, x1, 1120,0)
+
+inst_298:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, -0xb503, 0x8, 3f, x1, 1124,0)
+
+inst_299:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x66666667, 0x20, 3f, x1, 1128,0)
+
+inst_300:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x33333334, 0x0, 3f, x1, 1132,0)
+
+inst_301:
+// rs1_val==0 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x6, 0x2, 3f, x1, 1136,0)
+
+inst_302:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, -0x55555555, 0x10, 3f, x1, 1140,0)
+
+inst_303:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x55555556, 0x4, 3f, x1, 1144,0)
+
+inst_304:
+// rs1_val==0 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x4, 0x0, 1b, x1, 1148,0)
+
+inst_305:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0xb503, 0x2, 3f, x1, 1152,0)
+
+inst_306:
+// rs1_val==0 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x0, 0x8, 1b, x1, 1156,0)
+
+inst_307:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x66666665, 0x10, 3f, x1, 1160,0)
+
+inst_308:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x33333332, 0x100, 3f, x1, 1164,0)
+
+inst_309:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x55555554, 0x6, 1b, x1, 1168,0)
+
+inst_310:
+// rs1_val==0 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x2, 0x4, 3f, x1, 1172,0)
+
+inst_311:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0xb504, 0x100, 3f, x1, 1176,0)
+
+inst_312:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:-0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, -0xb504, 0x80, 3f, x1, 1180,0)
+
+inst_313:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x66666666, 0x2, 1b, x1, 1184,0)
+
+inst_314:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x33333333, 0xa, 1b, x1, 1188,0)
+
+inst_315:
+// rs1_val==0 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x5, 0x80, 3f, x1, 1192,0)
+
+inst_316:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, -0x55555556, 0x556, 1b, x1, 1196,0)
+
+inst_317:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x55555555, 0x400, 3f, x1, 1200,0)
+
+inst_318:
+// rs1_val==0 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x0, 0x3, 0x100, 3f, x1, 1204,0)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0xb505, 0x40, 3f, x1, 1208,0)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, -0xb503, 0x4, 3f, x1, 1212,0)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x66666667, 0x8, 1b, x1, 1216,0)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x33333334, 0x556, 1b, x1, 1220,0)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x6, 0x8, 1b, x1, 1224,0)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, -0x55555555, 0x4, 3f, x1, 1228,0)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x55555556, 0x4, 3f, x1, 1232,0)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x4, 0x6, 1b, x1, 1236,0)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0xb503, 0x8, 1b, x1, 1240,0)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x0, 0x80, 3f, x1, 1244,0)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x66666665, 0x4, 1b, x1, 1248,0)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x33333332, 0x10, 3f, x1, 1252,0)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x55555554, 0x40, 3f, x1, 1256,0)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x2, 0x4, 3f, x1, 1260,0)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0xb504, 0x0, 3f, x1, 1264,0)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, -0xb504, 0x8, 1b, x1, 1268,0)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x66666666, 0x8, 1b, x1, 1272,0)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x33333333, 0x556, 1b, x1, 1276,0)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x5, 0x6, 3f, x1, 1280,0)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, -0x55555556, 0x4, 3f, x1, 1284,0)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x55555555, 0x556, 1b, x1, 1288,0)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x3, 0x0, 1b, x1, 1292,0)
+
+inst_341:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0xb505, 0x556, 1b, x1, 1296,0)
+
+inst_342:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:-0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, -0xb503, 0x200, 3f, x1, 1300,0)
+
+inst_343:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x66666667, 0x0, 1b, x1, 1304,0)
+
+inst_344:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x33333334, 0x6, 1b, x1, 1308,0)
+
+inst_345:
+// rs1_val==5 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x6, 0x2, 3f, x1, 1312,0)
+
+inst_346:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, -0x55555555, 0x20, 3f, x1, 1316,0)
+
+inst_347:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x55555556, 0x400, 3f, x1, 1320,0)
+
+inst_348:
+// rs1_val==5 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x4, 0x556, 1b, x1, 1324,0)
+
+inst_349:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0xb503, 0x6, 1b, x1, 1328,0)
+
+inst_350:
+// rs1_val==5 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x0, 0x200, 3f, x1, 1332,0)
+
+inst_351:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x66666665, 0x6, 3f, x1, 1336,0)
+
+inst_352:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x33333332, 0x556, 1b, x1, 1340,0)
+
+inst_353:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x55555554, 0x2, 1b, x1, 1344,0)
+
+inst_354:
+// rs1_val==5 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x2, 0x6, 1b, x1, 1348,0)
+
+inst_355:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0xb504, 0xa, 1b, x1, 1352,0)
+
+inst_356:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, -0xb504, 0x2, 1b, x1, 1356,0)
+
+inst_357:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x66666666, 0xa, 1b, x1, 1360,0)
+
+inst_358:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x33333333, 0x80, 3f, x1, 1364,0)
+
+inst_359:
+// rs1_val==5 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x5, 0x0, 1b, x1, 1368,0)
+
+inst_360:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, -0x55555556, 0x0, 3f, x1, 1372,0)
+
+inst_361:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x55555555, 0x100, 3f, x1, 1376,0)
+
+inst_362:
+// rs1_val==5 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x5, 0x3, 0x6, 3f, x1, 1380,0)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0xb505, 0x0, 1b, x1, 1384,0)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, -0xb503, 0xa, 1b, x1, 1388,0)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x66666667, 0x400, 3f, x1, 1392,0)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x33333334, 0x200, 3f, x1, 1396,0)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x6, 0x40, 3f, x1, 1400,0)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, -0x55555555, 0x8, 1b, x1, 1404,0)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x55555556, 0x8, 1b, x1, 1408,0)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x4, 0x2, 1b, x1, 1412,0)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0xb503, 0x20, 3f, x1, 1416,0)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x0, 0x0, 1b, x1, 1420,0)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x66666665, 0x200, 3f, x1, 1424,0)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x33333332, 0xa, 1b, x1, 1428,0)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x55555554, 0x2, 3f, x1, 1432,0)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x2, 0x6, 3f, x1, 1436,0)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0xb504, 0x4, 3f, x1, 1440,0)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, -0xb504, 0x2, 3f, x1, 1444,0)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x66666666, 0x2, 3f, x1, 1448,0)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x33333333, 0x200, 3f, x1, 1452,0)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x5, 0x556, 1b, x1, 1456,0)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, -0x55555556, 0x8, 3f, x1, 1460,0)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x55555555, 0x200, 3f, x1, 1464,0)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x55555556, 0x3, 0x4, 3f, x1, 1468,0)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0xb505, 0xa, 1b, x1, 1472,0)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0xb503, 0x4, 3f, x1, 1476,0)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x66666667, 0x0, 3f, x1, 1480,0)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x33333334, 0x0, 3f, x1, 1484,0)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x6, 0x6, 3f, x1, 1488,0)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0x55555555, 0x6, 1b, x1, 1492,0)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x55555556, 0x8, 3f, x1, 1496,0)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x4, 0x200, 3f, x1, 1500,0)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0xb503, 0x0, 3f, x1, 1504,0)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x0, 0x4, 1b, x1, 1508,0)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x66666665, 0x2, 3f, x1, 1512,0)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x33333332, 0x40, 3f, x1, 1516,0)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x55555554, 0x4, 1b, x1, 1520,0)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x2, 0x10, 3f, x1, 1524,0)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0xb504, 0x8, 3f, x1, 1528,0)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0xb504, 0x2, 3f, x1, 1532,0)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x66666666, 0x20, 3f, x1, 1536,0)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x33333333, 0xa, 1b, x1, 1540,0)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x5, 0x6, 1b, x1, 1544,0)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, -0x55555556, 0x8, 3f, x1, 1548,0)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x55555555, 0x200, 3f, x1, 1552,0)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555555, 0x3, 0x6, 3f, x1, 1556,0)
+
+inst_407:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0xb505, 0x0, 1b, x1, 1560,0)
+
+inst_408:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, -0xb503, 0x80, 3f, x1, 1564,0)
+
+inst_409:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x66666667, 0x2, 3f, x1, 1568,0)
+
+inst_410:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x33333334, 0x4, 3f, x1, 1572,0)
+
+inst_411:
+// rs1_val==3 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x6, 0x8, 3f, x1, 1576,0)
+
+inst_412:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, -0x55555555, 0x10, 3f, x1, 1580,0)
+
+inst_413:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x55555556, 0x4, 3f, x1, 1584,0)
+
+inst_414:
+// rs1_val==3 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x4, 0x2, 1b, x1, 1588,0)
+
+inst_415:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0xb503, 0x8, 1b, x1, 1592,0)
+
+inst_416:
+// rs1_val==3 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x0, 0x80, 3f, x1, 1596,0)
+
+inst_417:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x66666665, 0x20, 3f, x1, 1600,0)
+
+inst_418:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x33333332, 0x0, 3f, x1, 1604,0)
+
+inst_419:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x55555554, 0x80, 3f, x1, 1608,0)
+
+inst_420:
+// rs1_val==3 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x2, 0x8, 3f, x1, 1612,0)
+
+inst_421:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0xb504, 0x400, 3f, x1, 1616,0)
+
+inst_422:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:-0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, -0xb504, 0x100, 3f, x1, 1620,0)
+
+inst_423:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x66666666, 0x8, 3f, x1, 1624,0)
+
+inst_424:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x33333333, 0x400, 3f, x1, 1628,0)
+
+inst_425:
+// rs1_val==3 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x5, 0x200, 3f, x1, 1632,0)
+
+inst_426:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, -0x55555556, 0x400, 1b, x1, 1636,0)
+
+inst_427:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x55555555, 0x400, 1b, x1, 1640,0)
+
+inst_428:
+// rs1_val==3 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x3, 0x3, 0x4, 1b, x1, 1644,0)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x0, 0x8, 1b, x1, 1648,0)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x66666665, 0xa, 1b, x1, 1652,0)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x33333332, 0x200, 3f, x1, 1656,0)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x55555554, 0x400, 1b, x1, 1660,0)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x2, 0x556, 1b, x1, 1664,0)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0xb504, 0x40, 3f, x1, 1668,0)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, -0xb504, 0x8, 1b, x1, 1672,0)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x66666666, 0x6, 1b, x1, 1676,0)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x33333333, 0x2, 3f, x1, 1680,0)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x5, 0x0, 3f, x1, 1684,0)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, -0x55555556, 0x400, 3f, x1, 1688,0)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x55555555, 0x400, 1b, x1, 1692,0)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666665, 0x3, 0x10, 3f, x1, 1696,0)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0xb505, 0x4, 1b, x1, 1700,0)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, -0xb503, 0x8, 3f, x1, 1704,0)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x66666667, 0x4, 3f, x1, 1708,0)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x33333334, 0x6, 3f, x1, 1712,0)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x6, 0x20, 3f, x1, 1716,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, -0x55555555, 0x2, 3f, x1, 1720,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x55555556, 0x2, 3f, x1, 1724,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x4, 0x0, 1b, x1, 1728,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0xb503, 0x6, 3f, x1, 1732,0)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x0, 0xa, 1b, x1, 1736,0)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x66666665, 0x8, 3f, x1, 1740,0)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x33333332, 0x80, 3f, x1, 1744,0)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x55555554, 0x556, 1b, x1, 1748,0)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x2, 0x100, 3f, x1, 1752,0)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0xb504, 0x8, 3f, x1, 1756,0)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, -0xb504, 0x100, 3f, x1, 1760,0)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x66666666, 0x400, 1b, x1, 1764,0)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x33333333, 0x400, 1b, x1, 1768,0)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x5, 0xa, 1b, x1, 1772,0)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, -0x55555556, 0x4, 3f, x1, 1776,0)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x55555555, 0x6, 1b, x1, 1780,0)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333332, 0x3, 0x10, 3f, x1, 1784,0)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0xb505, 0x4, 3f, x1, 1788,0)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, -0xb503, 0x8, 1b, x1, 1792,0)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x66666667, 0x2, 1b, x1, 1796,0)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x33333334, 0x100, 3f, x1, 1800,0)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x6, 0x2, 3f, x1, 1804,0)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, -0x55555555, 0x8, 1b, x1, 1808,0)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x55555556, 0x0, 1b, x1, 1812,0)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x4, 0x8, 1b, x1, 1816,0)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0xb503, 0x80, 3f, x1, 1820,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x0, 0x2, 3f, x1, 1824,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x66666665, 0x40, 3f, x1, 1828,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x33333332, 0x40, 3f, x1, 1832,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x55555554, 0x2, 1b, x1, 1836,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x2, 0x80, 3f, x1, 1840,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0xb504, 0x2, 1b, x1, 1844,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, -0xb504, 0x20, 3f, x1, 1848,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x66666666, 0x40, 3f, x1, 1852,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x33333333, 0x400, 1b, x1, 1856,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x5, 0x400, 1b, x1, 1860,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, -0x55555556, 0x40, 3f, x1, 1864,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x55555555, 0x0, 1b, x1, 1868,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x55555554, 0x3, 0x556, 1b, x1, 1872,0)
+
+inst_486:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0xb505, 0x400, 3f, x1, 1876,0)
+
+inst_487:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, -0xb503, 0x80, 3f, x1, 1880,0)
+
+inst_488:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x66666667, 0x4, 3f, x1, 1884,0)
+
+inst_489:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x33333334, 0x100, 3f, x1, 1888,0)
+
+inst_490:
+// rs1_val==2 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x6, 0x20, 3f, x1, 1892,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, -0x55555555, 0x200, 3f, x1, 1896,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x55555556, 0x80, 3f, x1, 1900,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x4, 0x80, 3f, x1, 1904,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0xb503, 0x8, 1b, x1, 1908,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x0, 0x2, 3f, x1, 1912,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x66666665, 0x8, 1b, x1, 1916,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x33333332, 0x2, 3f, x1, 1920,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x55555554, 0x100, 3f, x1, 1924,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x2, 0x100, 3f, x1, 1928,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0xb504, 0x2, 1b, x1, 1932,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:-0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, -0xb504, 0x4, 3f, x1, 1936,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x66666666, 0x4, 3f, x1, 1940,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x33333333, 0x80, 3f, x1, 1944,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x5, 0x6, 1b, x1, 1948,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, -0x55555556, 0x6, 1b, x1, 1952,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x55555555, 0x80, 3f, x1, 1956,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x2, 0x3, 0x0, 3f, x1, 1960,0)
+
+inst_508:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0xb505, 0x2, 1b, x1, 1964,0)
+
+inst_509:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, -0xb503, 0x100, 3f, x1, 1968,0)
+
+inst_510:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x66666667, 0x80, 3f, x1, 1972,0)
+
+inst_511:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x33333334, 0x10, 3f, x1, 1976,0)
+
+inst_512:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x6, 0x2, 3f, x1, 1980,0)
+
+inst_513:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, -0x55555555, 0x20, 3f, x1, 1984,0)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x55555556, 0x6, 3f, x1, 1988,0)
+
+inst_515:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x4, 0x8, 1b, x1, 1992,0)
+
+inst_516:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0xb503, 0x0, 1b, x1, 1996,0)
+
+inst_517:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x0, 0x400, 1b, x1, 2000,0)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x66666665, 0x100, 3f, x1, 2004,0)
+
+inst_519:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x33333332, 0x40, 3f, x1, 2008,0)
+
+inst_520:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x55555554, 0x6, 3f, x1, 2012,0)
+
+inst_521:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x2, 0x100, 3f, x1, 2016,0)
+
+inst_522:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0xb504, 0x4, 3f, x1, 2020,0)
+
+inst_523:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, -0xb504, 0xa, 1b, x1, 2024,0)
+
+inst_524:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x66666666, 0x400, 1b, x1, 2028,0)
+
+inst_525:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x33333333, 0x8, 3f, x1, 2032,0)
+
+inst_526:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x5, 0x0, 1b, x1, 2036,0)
+
+inst_527:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, -0x55555556, 0x6, 1b, x1, 2040,0)
+
+inst_528:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x55555555, 0x100, 3f, x1, 2044,0)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_529:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0xb504, 0x3, 0x8, 3f, x1, 0,0)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0xb505, 0x400, 1b, x1, 4,0)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, -0xb503, 0x6, 3f, x1, 8,0)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x66666667, 0x400, 3f, x1, 12,0)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x33333334, 0x100, 3f, x1, 16,0)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x6; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x6, 0x400, 1b, x1, 20,0)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, -0x55555555, 0x0, 3f, x1, 24,0)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x55555556, 0x20, 3f, x1, 28,0)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x4, 0x2, 1b, x1, 32,0)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0xb503, 0x2, 3f, x1, 36,0)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x0, 0x2, 1b, x1, 40,0)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x66666665, 0x20, 3f, x1, 44,0)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x33333332, 0x2, 3f, x1, 48,0)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x55555554, 0x6, 3f, x1, 52,0)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x2, 0x6, 1b, x1, 56,0)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0xb504, 0x2, 3f, x1, 60,0)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, -0xb504, 0x556, 1b, x1, 64,0)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x66666666, 0x20, 3f, x1, 68,0)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x33333333, 0x40, 3f, x1, 72,0)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x5, 0x2, 3f, x1, 76,0)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, -0x55555556, 0x400, 1b, x1, 80,0)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x55555555, 0x100, 3f, x1, 84,0)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:-0xb504; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0xb504, 0x3, 0x40, 3f, x1, 88,0)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0xb505, 0x10, 3f, x1, 92,0)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, -0xb503, 0x20, 3f, x1, 96,0)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x66666667, 0x2, 1b, x1, 100,0)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x33333334, 0x0, 3f, x1, 104,0)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x6, 0x10, 3f, x1, 108,0)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, -0x55555555, 0x4, 1b, x1, 112,0)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x55555556, 0x2, 3f, x1, 116,0)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x4, 0x10, 3f, x1, 120,0)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0xb503, 0x6, 3f, x1, 124,0)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x0, 0x80, 3f, x1, 128,0)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x66666665, 0x2, 1b, x1, 132,0)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x33333332, 0x40, 3f, x1, 136,0)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x55555554, 0x4, 1b, x1, 140,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x2, 0x2, 1b, x1, 144,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0xb504, 0x0, 1b, x1, 148,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, -0xb504, 0x20, 3f, x1, 152,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x66666666, 0x0, 3f, x1, 156,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x33333333, 0x200, 3f, x1, 160,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x5, 0x0, 3f, x1, 164,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, -0x55555556, 0x0, 1b, x1, 168,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x55555555, 0x20, 3f, x1, 172,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x66666666, 0x3, 0x6, 1b, x1, 176,0)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0xb505, 0x20, 3f, x1, 180,0)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, -0xb503, 0x6, 1b, x1, 184,0)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x66666667, 0x400, 1b, x1, 188,0)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x33333334, 0x0, 3f, x1, 192,0)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x6, 0x2, 3f, x1, 196,0)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, -0x55555555, 0x8, 3f, x1, 200,0)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x55555556, 0x80, 3f, x1, 204,0)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x200; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0x4, 0x200, 3f, x1, 208,0)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: bge, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x33333333, 0xb503, 0x8, 1b, x1, 212,0)
+
+inst_583:
+// rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val == -65537, rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x10; op2:x11; op1val:-0x10001; op2val:-0x8; immval:0x400; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x10001, -0x8, 0x400, 1b, x1, 216,0)
+
+inst_584:
+// rs2_val == -536870913, rs1_val == -32769, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: bge, op1:x10; op2:x11; op1val:-0x8001; op2val:-0x20000001; immval:0x20; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, -0x8001, -0x20000001, 0x20, 3f, x1, 220,0)
+
+inst_585:
+// rs2_val == -67108865, rs1_val == 256
+// opcode: bge, op1:x10; op2:x11; op1val:0x100; op2val:-0x4000001; immval:0x556; align:0
+TEST_BRANCH_OP(bge, x3, x10, x11, 0x100, -0x4000001, 0x556, 1b, x1, 224,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 57*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S
new file mode 100644
index 000000000..43bf2ec72
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S
@@ -0,0 +1,3721 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the bgeu instruction of the RISC-V E extension for the bgeu covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",bgeu)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 == rs2, rs1==x5, rs2==x5, rs1_val > 0 and rs2_val > 0, rs2_val == 4294967039, rs1_val == 3758096383, rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 
+// opcode: bgeu, op1:x5; op2:x5; op1val:0xdfffffff; op2val:0xdfffffff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x3, x5, x5, 0xdfffffff, 0xdfffffff, 0x400, 1b, x2, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x1, rs2==x10, rs2_val == 2147483647, rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 , rs1_val == 4261412863
+// opcode: bgeu, op1:x1; op2:x10; op1val:0xfdffffff; op2val:0x7fffffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x3, x1, x10, 0xfdffffff, 0x7fffffff, 0x4, 3f, x2, 4,0)
+
+inst_2:
+// rs1==x0, rs2==x9, rs2_val == 3221225471, 
+// opcode: bgeu, op1:x0; op2:x9; op1val:0x0; op2val:0xbfffffff; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x3, x0, x9, 0x0, 0xbfffffff, 0xa, 1b, x2, 8,0)
+
+inst_3:
+// rs1==x7, rs2==x11, rs2_val == 3758096383, rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 
+// opcode: bgeu, op1:x7; op2:x11; op1val:0x13; op2val:0xdfffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x3, x7, x11, 0x13, 0xdfffffff, 0x6, 3f, x2, 12,0)
+
+inst_4:
+// rs1==x6, rs2==x12, rs2_val == 4026531839, rs1_val == 2
+// opcode: bgeu, op1:x6; op2:x12; op1val:0x2; op2val:0xefffffff; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x3, x6, x12, 0x2, 0xefffffff, 0x8, 3f, x2, 16,0)
+
+inst_5:
+// rs1==x9, rs2==x13, rs2_val == 4160749567, rs1_val == 3221225471
+// opcode: bgeu, op1:x9; op2:x13; op1val:0xbfffffff; op2val:0xf7ffffff; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x3, x9, x13, 0xbfffffff, 0xf7ffffff, 0x10, 3f, x2, 20,0)
+
+inst_6:
+// rs1==x11, rs2==x7, rs2_val == 4227858431, 
+// opcode: bgeu, op1:x11; op2:x7; op1val:0xb505; op2val:0xfbffffff; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x3, x11, x7, 0xb505, 0xfbffffff, 0x2, 3f, x2, 24,0)
+
+inst_7:
+// rs1==x13, rs2==x6, rs2_val == 4261412863, rs1_val == 1
+// opcode: bgeu, op1:x13; op2:x6; op1val:0x1; op2val:0xfdffffff; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x3, x13, x6, 0x1, 0xfdffffff, 0x2, 3f, x2, 28,0)
+
+inst_8:
+// rs1==x12, rs2==x15, rs2_val == 4278190079, 
+// opcode: bgeu, op1:x12; op2:x15; op1val:0x66666666; op2val:0xfeffffff; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x3, x12, x15, 0x66666666, 0xfeffffff, 0x0, 1b, x2, 32,0)
+
+inst_9:
+// rs1==x10, rs2==x14, rs2_val == 4286578687, 
+// opcode: bgeu, op1:x10; op2:x14; op1val:0x33333333; op2val:0xff7fffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x3, x10, x14, 0x33333333, 0xff7fffff, 0x6, 3f, x2, 36,0)
+
+inst_10:
+// rs1==x3, rs2==x8, rs2_val == 4290772991, 
+// opcode: bgeu, op1:x3; op2:x8; op1val:0x12; op2val:0xffbfffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x3, x8, 0x12, 0xffbfffff, 0x4, 1b, x2, 40,0)
+RVTEST_SIGBASE( x5,signature_x5_0)
+
+inst_11:
+// rs1==x4, rs2==x2, rs2_val == 4292870143, 
+// opcode: bgeu, op1:x4; op2:x2; op1val:0x6; op2val:0xffdfffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x4, x2, 0x6, 0xffdfffff, 0x6, 1b, x5, 0,0)
+
+inst_12:
+// rs1==x15, rs2==x3, rs2_val == 4293918719, 
+// opcode: bgeu, op1:x15; op2:x3; op1val:0x5; op2val:0xffefffff; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x15, x3, 0x5, 0xffefffff, 0x2, 1b, x5, 4,0)
+
+inst_13:
+// rs1==x14, rs2==x1, rs2_val == 4294443007, rs1_val == 4293918719
+// opcode: bgeu, op1:x14; op2:x1; op1val:0xffefffff; op2val:0xfff7ffff; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x14, x1, 0xffefffff, 0xfff7ffff, 0x80, 3f, x5, 8,0)
+
+inst_14:
+// rs1==x8, rs2==x4, rs2_val == 4294705151, 
+// opcode: bgeu, op1:x8; op2:x4; op1val:0x3; op2val:0xfffbffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x8, x4, 0x3, 0xfffbffff, 0x4, 1b, x5, 12,0)
+
+inst_15:
+// rs1==x2, rs2==x0, rs2_val == 4294836223, rs1_val == 2147483647
+// opcode: bgeu, op1:x2; op2:x0; op1val:0x7fffffff; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x2, x0, 0x7fffffff, 0x0, 0x2, 1b, x5, 16,0)
+
+inst_16:
+// rs2_val == 4294901759, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xfffeffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xfffeffff, 0x4, 3f, x5, 20,0)
+
+inst_17:
+// rs2_val == 4294934527, rs1_val == 4
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xffff7fff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xffff7fff, 0x6, 3f, x5, 24,0)
+
+inst_18:
+// rs2_val == 4294950911, rs1_val == 4294443007
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfff7ffff; op2val:0xffffbfff; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfff7ffff, 0xffffbfff, 0x2, 1b, x5, 28,0)
+
+inst_19:
+// rs2_val == 4294959103, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xffffdfff; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xffffdfff, 0x20, 3f, x5, 32,0)
+
+inst_20:
+// rs2_val == 4294963199, rs1_val == 4286578687
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xff7fffff; op2val:0xffffefff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xff7fffff, 0xffffefff, 0x100, 3f, x5, 36,0)
+
+inst_21:
+// rs2_val == 4294965247, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xfffff7ff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xfffff7ff, 0x400, 1b, x5, 40,0)
+
+inst_22:
+// rs2_val == 4294966271, rs1_val == 268435456
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000000; op2val:0xfffffbff; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000000, 0xfffffbff, 0x8, 1b, x5, 44,0)
+
+inst_23:
+// rs2_val == 4294966783, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xfffffdff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xfffffdff, 0x4, 3f, x5, 48,0)
+
+inst_24:
+// rs2_val == 4294967167, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xffffff7f; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xffffff7f, 0x0, 3f, x5, 52,0)
+
+inst_25:
+// rs2_val == 4294967231, rs1_val == 4294967293
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffffd; op2val:0xffffffbf; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffffd, 0xffffffbf, 0x0, 3f, x5, 56,0)
+
+inst_26:
+// rs2_val == 4294967263, rs1_val == 16777216
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1000000; op2val:0xffffffdf; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1000000, 0xffffffdf, 0x100, 3f, x5, 60,0)
+
+inst_27:
+// rs2_val == 4294967279, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x11; op2val:0xffffffef; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x11, 0xffffffef, 0x80, 3f, x5, 64,0)
+
+inst_28:
+// rs2_val == 4294967287, rs1_val == 67108864
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4000000; op2val:0xfffffff7; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4000000, 0xfffffff7, 0xa, 1b, x5, 68,0)
+
+inst_29:
+// rs2_val == 4294967291, rs1_val == 32768
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x8000; op2val:0xfffffffb; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x8000, 0xfffffffb, 0xa, 1b, x5, 72,0)
+
+inst_30:
+// rs2_val == 4294967293, rs1_val == 524288
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x80000; op2val:0xfffffffd; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x80000, 0xfffffffd, 0x10, 3f, x5, 76,0)
+
+inst_31:
+// rs2_val == 4294967294, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xdfffffff; op2val:0xfffffffe; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xdfffffff, 0xfffffffe, 0x6, 1b, x5, 80,0)
+
+inst_32:
+// rs1_val == 4026531839, rs2_val == 1073741824
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xefffffff; op2val:0x40000000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xefffffff, 0x40000000, 0x2, 3f, x5, 84,0)
+
+inst_33:
+// rs1_val == 4160749567, rs2_val == 67108864
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xf7ffffff; op2val:0x4000000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xf7ffffff, 0x4000000, 0x2, 3f, x5, 88,0)
+
+inst_34:
+// rs1_val == 4227858431, rs2_val == 32768
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfbffffff; op2val:0x8000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfbffffff, 0x8000, 0x4, 3f, x5, 92,0)
+
+inst_35:
+// rs1_val == 4278190079, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfeffffff; op2val:0xc; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfeffffff, 0xc, 0x4, 3f, x5, 96,0)
+
+inst_36:
+// rs1_val == 4290772991, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffbfffff; op2val:0xffffffff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffbfffff, 0xffffffff, 0x556, 1b, x5, 100,0)
+
+inst_37:
+// rs1_val == 4292870143, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffdfffff; op2val:0x8000; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffdfffff, 0x8000, 0x10, 3f, x5, 104,0)
+
+inst_38:
+// rs1_val == 4294705151, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffbffff; op2val:0xfffffeff; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffbffff, 0xfffffeff, 0x0, 1b, x5, 108,0)
+
+inst_39:
+// rs1_val == 4294836223, rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffdffff; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffdffff, 0x5, 0x0, 1b, x5, 112,0)
+
+inst_40:
+// rs1_val == 4294901759, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffeffff; op2val:0xfffff7ff; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffeffff, 0xfffff7ff, 0x20, 3f, x5, 116,0)
+
+inst_41:
+// rs1_val == 4294934527, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff7fff; op2val:0xc; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff7fff, 0xc, 0xa, 1b, x5, 120,0)
+
+inst_42:
+// rs1_val == 4294950911, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffbfff; op2val:0xfffffffd; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffbfff, 0xfffffffd, 0x20, 3f, x5, 124,0)
+
+inst_43:
+// rs1_val == 4294959103, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffdfff; op2val:0xfeffffff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffdfff, 0xfeffffff, 0x100, 3f, x5, 128,0)
+
+inst_44:
+// rs1_val == 4294963199, rs2_val == 16777216
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffefff; op2val:0x1000000; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffefff, 0x1000000, 0x10, 3f, x5, 132,0)
+
+inst_45:
+// rs1_val == 4294965247, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffff7ff; op2val:0xfffffbff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffff7ff, 0xfffffbff, 0x400, 3f, x5, 136,0)
+
+inst_46:
+// rs1_val == 4294966271, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffbff; op2val:0xefffffff; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffbff, 0xefffffff, 0x80, 3f, x5, 140,0)
+
+inst_47:
+// rs1_val == 4294966783, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffdff; op2val:0x1000000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffdff, 0x1000000, 0x6, 1b, x5, 144,0)
+
+inst_48:
+// rs1_val == 4294967039, rs2_val == 268435456
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffeff; op2val:0x10000000; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffeff, 0x10000000, 0x0, 3f, x5, 148,0)
+
+inst_49:
+// rs1_val == 4294967167, rs2_val == 256
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffff7f; op2val:0x100; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffff7f, 0x100, 0x6, 3f, x5, 152,0)
+
+inst_50:
+// rs1_val == 4294967231, rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffffbf; op2val:0xffffffbf; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffffbf, 0xffffffbf, 0x100, 3f, x5, 156,0)
+
+inst_51:
+// rs1_val == 4294967263, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffffdf; op2val:0xffffffbf; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffffdf, 0xffffffbf, 0x6, 1b, x5, 160,0)
+
+inst_52:
+// rs1_val == 4294967279, rs2_val == 2048
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffffef; op2val:0x800; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffffef, 0x800, 0xa, 1b, x5, 164,0)
+
+inst_53:
+// rs1_val == 4294967287, rs2_val == 134217728
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffff7; op2val:0x8000000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffff7, 0x8000000, 0x2, 1b, x5, 168,0)
+
+inst_54:
+// rs1_val == 4294967291, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffffb; op2val:0xfffffeff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffffb, 0xfffffeff, 0x400, 1b, x5, 172,0)
+
+inst_55:
+// rs1_val == 4294967294, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffffffe; op2val:0xe; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffffffe, 0xe, 0x400, 3f, x5, 176,0)
+
+inst_56:
+// rs2_val == 2147483648, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff7fff; op2val:0x80000000; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff7fff, 0x80000000, 0x80, 3f, x5, 180,0)
+
+inst_57:
+// rs2_val == 536870912, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffff7f; op2val:0x20000000; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffff7f, 0x20000000, 0x556, 1b, x5, 184,0)
+
+inst_58:
+// rs2_val == 33554432, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffefff; op2val:0x2000000; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffefff, 0x2000000, 0x200, 3f, x5, 188,0)
+
+inst_59:
+// rs2_val == 8388608, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x800000; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x800000, 0x200, 3f, x5, 192,0)
+
+inst_60:
+// rs2_val == 4194304, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffff7ff; op2val:0x400000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffff7ff, 0x400000, 0x6, 3f, x5, 196,0)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x200000; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x200000, 0x8, 1b, x5, 200,0)
+
+inst_62:
+// rs2_val == 1048576, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x100000; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x100000, 0x0, 3f, x5, 204,0)
+
+inst_63:
+// rs2_val == 524288, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x7; op2val:0x80000; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x7, 0x80000, 0x10, 3f, x5, 208,0)
+
+inst_64:
+// rs2_val == 262144, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1000000; op2val:0x40000; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1000000, 0x40000, 0x0, 3f, x5, 212,0)
+
+inst_65:
+// rs2_val == 131072, rs1_val == 65536
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x20000; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x20000, 0x200, 3f, x5, 216,0)
+
+inst_66:
+// rs2_val == 65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfbffffff; op2val:0x10000; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfbffffff, 0x10000, 0x40, 3f, x5, 220,0)
+
+inst_67:
+// rs2_val == 16384, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xc; op2val:0x4000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xc, 0x4000, 0x2, 3f, x5, 224,0)
+
+inst_68:
+// rs2_val == 8192, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x2000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x2000, 0x6, 3f, x5, 228,0)
+
+inst_69:
+// rs2_val == 4096, rs1_val == 32
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x20; op2val:0x1000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x20, 0x1000, 0x2, 1b, x5, 232,0)
+
+inst_70:
+// rs2_val == 1024, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x400; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x400, 0x6, 1b, x5, 236,0)
+
+inst_71:
+// rs2_val == 512, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x200; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x200, 0x4, 3f, x5, 240,0)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x80; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x80, 0x100, 3f, x5, 244,0)
+
+inst_73:
+// rs2_val == 64, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x40; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x40, 0x8, 3f, x5, 248,0)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x20; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x20, 0x200, 3f, x5, 252,0)
+
+inst_75:
+// rs2_val == 16, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1000000; op2val:0x10; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1000000, 0x10, 0x6, 3f, x5, 256,0)
+
+inst_76:
+// rs2_val == 8, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffffdf; op2val:0x8; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffffdf, 0x8, 0x2, 1b, x5, 260,0)
+
+inst_77:
+// rs2_val == 4, rs1_val==65536 and rs2_val==4
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x4, 0x2, 1b, x5, 264,0)
+
+inst_78:
+// rs2_val == 2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffffff7f; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffffff7f, 0x2, 0x4, 3f, x5, 268,0)
+
+inst_79:
+// rs2_val == 1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfbffffff; op2val:0x1; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfbffffff, 0x1, 0x10, 3f, x5, 272,0)
+
+inst_80:
+// rs1_val == 2147483648, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x80000000; op2val:0xfffffff7; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x80000000, 0xfffffff7, 0x2, 1b, x5, 276,0)
+
+inst_81:
+// rs1_val == 1073741824, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x40000000; op2val:0xb; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x40000000, 0xb, 0x100, 3f, x5, 280,0)
+
+inst_82:
+// rs1_val == 536870912, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x20000000; op2val:0x800000; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x20000000, 0x800000, 0x8, 3f, x5, 284,0)
+
+inst_83:
+// rs1_val == 134217728, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x8000000; op2val:0xefffffff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x8000000, 0xefffffff, 0x100, 3f, x5, 288,0)
+
+inst_84:
+// rs1_val == 33554432, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2000000; op2val:0xb; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2000000, 0xb, 0x200, 3f, x5, 292,0)
+
+inst_85:
+// rs1_val == 8388608, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x800000; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x800000, 0x4, 0x8, 1b, x5, 296,0)
+
+inst_86:
+// rs1_val == 4194304, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x400000; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x400000, 0x1, 0x0, 3f, x5, 300,0)
+
+inst_87:
+// rs1_val == 2097152, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x200000; op2val:0x7fffffff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x200000, 0x7fffffff, 0x400, 1b, x5, 304,0)
+
+inst_88:
+// rs1_val == 1048576, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x100000; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x100000, 0x33333333, 0x2, 1b, x5, 308,0)
+
+inst_89:
+// rs1_val == 262144, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x40000; op2val:0x80; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x40000, 0x80, 0x8, 3f, x5, 312,0)
+
+inst_90:
+// rs1_val == 131072, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x20000; op2val:0x20000000; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x20000, 0x20000000, 0x20, 3f, x5, 316,0)
+
+inst_91:
+// rs1_val == 16384, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4000; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4000, 0x66666666, 0x6, 3f, x5, 320,0)
+
+inst_92:
+// rs1_val == 8192, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2000; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2000, 0x66666666, 0x2, 1b, x5, 324,0)
+
+inst_93:
+// rs1_val == 4096, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1000; op2val:0xfffffeff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1000, 0xfffffeff, 0x556, 1b, x5, 328,0)
+
+inst_94:
+// rs1_val == 2048, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x800; op2val:0xfffffffd; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x800, 0xfffffffd, 0x80, 3f, x5, 332,0)
+
+inst_95:
+// rs1_val == 1024, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x400; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x400, 0x0, 0x6, 3f, x5, 336,0)
+
+inst_96:
+// rs1_val == 512, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x200; op2val:0xefffffff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x200, 0xefffffff, 0x556, 1b, x5, 340,0)
+
+inst_97:
+// rs1_val == 256, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x100; op2val:0xb505; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x100, 0xb505, 0x200, 3f, x5, 344,0)
+
+inst_98:
+// rs1_val == 128, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x80; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x80, 0x0, 0x4, 3f, x5, 348,0)
+
+inst_99:
+// rs1_val == 64, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x40; op2val:0xffffefff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x40, 0xffffefff, 0x556, 1b, x5, 352,0)
+
+inst_100:
+// rs1_val == 16, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10; op2val:0xfffffeff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10, 0xfffffeff, 0x100, 3f, x5, 356,0)
+
+inst_101:
+// rs1_val == 8, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x8; op2val:0xffffefff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x8, 0xffffefff, 0x6, 3f, x5, 360,0)
+
+inst_102:
+// rs1_val==65536 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x10000, 0x0, 3f, x5, 364,0)
+
+inst_103:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x1; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x1, 0x80, 3f, x5, 368,0)
+
+inst_104:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xb505, 0x10, 3f, x5, 372,0)
+
+inst_105:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x66666667, 0x556, 1b, x5, 376,0)
+
+inst_106:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333334; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x33333334, 0x80, 3f, x5, 380,0)
+
+inst_107:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x6; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x6, 0x400, 1b, x5, 384,0)
+
+inst_108:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xaaaaaaab, 0x100, 3f, x5, 388,0)
+
+inst_109:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x55555556, 0x20, 3f, x5, 392,0)
+
+inst_110:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xfffe; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xfffe, 0x4, 3f, x5, 396,0)
+
+inst_111:
+// rs1_val==65536 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x0, 0x100, 3f, x5, 400,0)
+
+inst_112:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xb503, 0x8, 1b, x5, 404,0)
+
+inst_113:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x66666665, 0x400, 1b, x5, 408,0)
+
+inst_114:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x33333332, 0x8, 3f, x5, 412,0)
+
+inst_115:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaa9; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xaaaaaaa9, 0x200, 3f, x5, 416,0)
+
+inst_116:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x55555554, 0x8, 1b, x5, 420,0)
+
+inst_117:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x2, 0x40, 3f, x5, 424,0)
+
+inst_118:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xffff; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xffff, 0x80, 3f, x5, 428,0)
+
+inst_119:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xb504, 0x100, 3f, x5, 432,0)
+
+inst_120:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x66666666, 0x4, 3f, x5, 436,0)
+
+inst_121:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x33333333, 0x2, 3f, x5, 440,0)
+
+inst_122:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x5, 0x4, 1b, x5, 444,0)
+
+inst_123:
+// rs1_val==65536 and rs2_val==2863311530, rs2_val == 2863311530
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaaa; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0xaaaaaaaa, 0x2, 3f, x5, 448,0)
+
+inst_124:
+// rs1_val==65536 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x55555555, 0x20, 3f, x5, 452,0)
+
+inst_125:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x10000; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x10000, 0x3, 0x20, 3f, x5, 456,0)
+
+inst_126:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x10000, 0x4, 1b, x5, 460,0)
+
+inst_127:
+// rs1_val==1 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x1; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x1, 0x100, 3f, x5, 464,0)
+
+inst_128:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xb505, 0x80, 3f, x5, 468,0)
+
+inst_129:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x66666667, 0x2, 1b, x5, 472,0)
+
+inst_130:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x33333334, 0x4, 3f, x5, 476,0)
+
+inst_131:
+// rs1_val==1 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x6, 0xa, 1b, x5, 480,0)
+
+inst_132:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaab; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xaaaaaaab, 0x400, 3f, x5, 484,0)
+
+inst_133:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x55555556, 0x400, 3f, x5, 488,0)
+
+inst_134:
+// rs1_val==1 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x4, 0x80, 3f, x5, 492,0)
+
+inst_135:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xfffe; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xfffe, 0x400, 1b, x5, 496,0)
+
+inst_136:
+// rs1_val==1 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x0, 0x2, 3f, x5, 500,0)
+
+inst_137:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xb503, 0x8, 1b, x5, 504,0)
+
+inst_138:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x66666665, 0x556, 1b, x5, 508,0)
+
+inst_139:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x33333332, 0x40, 3f, x5, 512,0)
+
+inst_140:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaa9; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xaaaaaaa9, 0x400, 3f, x5, 516,0)
+
+inst_141:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x55555554, 0x40, 3f, x5, 520,0)
+
+inst_142:
+// rs1_val==1 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x2, 0x100, 3f, x5, 524,0)
+
+inst_143:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xffff; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xffff, 0x20, 3f, x5, 528,0)
+
+inst_144:
+// rs1_val==1 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xb504, 0x4, 3f, x5, 532,0)
+
+inst_145:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666666; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x66666666, 0x10, 3f, x5, 536,0)
+
+inst_146:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x33333333, 0x8, 1b, x5, 540,0)
+
+inst_147:
+// rs1_val==1 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x5, 0x8, 3f, x5, 544,0)
+
+inst_148:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaaa; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0xaaaaaaaa, 0x40, 3f, x5, 548,0)
+
+inst_149:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x55555555, 0x6, 1b, x5, 552,0)
+
+inst_150:
+// rs1_val==1 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x1; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x1, 0x3, 0x10, 3f, x5, 556,0)
+
+inst_151:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x10000; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x10000, 0x8, 3f, x5, 560,0)
+
+inst_152:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x1; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x1, 0x200, 3f, x5, 564,0)
+
+inst_153:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xb505, 0x400, 3f, x5, 568,0)
+
+inst_154:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x66666667, 0x556, 1b, x5, 572,0)
+
+inst_155:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x33333334, 0x10, 3f, x5, 576,0)
+
+inst_156:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x6, 0x20, 3f, x5, 580,0)
+
+inst_157:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xaaaaaaab, 0x4, 1b, x5, 584,0)
+
+inst_158:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x55555556, 0x6, 3f, x5, 588,0)
+
+inst_159:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x4, 0x4, 1b, x5, 592,0)
+
+inst_160:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xfffe; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xfffe, 0x556, 1b, x5, 596,0)
+
+inst_161:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x0, 0x6, 1b, x5, 600,0)
+
+inst_162:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xb503, 0xa, 1b, x5, 604,0)
+
+inst_163:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x66666665, 0x80, 3f, x5, 608,0)
+
+inst_164:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x33333332, 0x200, 3f, x5, 612,0)
+
+inst_165:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaa9; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xaaaaaaa9, 0x0, 3f, x5, 616,0)
+
+inst_166:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x55555554, 0x2, 1b, x5, 620,0)
+
+inst_167:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x2, 0x80, 3f, x5, 624,0)
+
+inst_168:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xffff, 0x6, 1b, x5, 628,0)
+
+inst_169:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xb504, 0x40, 3f, x5, 632,0)
+
+inst_170:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x66666666, 0x6, 1b, x5, 636,0)
+
+inst_171:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x33333333, 0xa, 1b, x5, 640,0)
+
+inst_172:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x5, 0x20, 3f, x5, 644,0)
+
+inst_173:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaaa; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0xaaaaaaaa, 0x20, 3f, x5, 648,0)
+
+inst_174:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x55555555, 0x6, 3f, x5, 652,0)
+
+inst_175:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb505, 0x3, 0x40, 3f, x5, 656,0)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x10000, 0x4, 3f, x5, 660,0)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x1; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x1, 0x200, 3f, x5, 664,0)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xb505, 0x400, 1b, x5, 668,0)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x66666667, 0x6, 3f, x5, 672,0)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x33333334, 0x400, 1b, x5, 676,0)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x6, 0x6, 3f, x5, 680,0)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaab; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xaaaaaaab, 0x400, 1b, x5, 684,0)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x55555556, 0x6, 3f, x5, 688,0)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x4, 0x8, 1b, x5, 692,0)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xfffe; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xfffe, 0x2, 3f, x5, 696,0)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x0, 0x6, 1b, x5, 700,0)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xb503, 0x80, 3f, x5, 704,0)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x66666665, 0x8, 1b, x5, 708,0)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x33333332, 0x8, 1b, x5, 712,0)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaa9; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xaaaaaaa9, 0x20, 3f, x5, 716,0)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x55555554, 0x200, 3f, x5, 720,0)
+
+inst_192:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x2, 0x4, 3f, x5, 724,0)
+
+inst_193:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xffff; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xffff, 0x10, 3f, x5, 728,0)
+
+inst_194:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xb504, 0x8, 1b, x5, 732,0)
+
+inst_195:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x66666666, 0x8, 1b, x5, 736,0)
+
+inst_196:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x33333333, 0x0, 3f, x5, 740,0)
+
+inst_197:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x5, 0x6, 3f, x5, 744,0)
+
+inst_198:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaaa; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0xaaaaaaaa, 0x556, 1b, x5, 748,0)
+
+inst_199:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x55555555, 0x80, 3f, x5, 752,0)
+
+inst_200:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666667, 0x3, 0x4, 3f, x5, 756,0)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x10000; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x10000, 0x8, 3f, x5, 760,0)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x1, 0x8, 3f, x5, 764,0)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xb505, 0x0, 3f, x5, 768,0)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x66666667, 0x6, 3f, x5, 772,0)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x33333334, 0x200, 3f, x5, 776,0)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x6, 0x4, 3f, x5, 780,0)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xaaaaaaab, 0x8, 3f, x5, 784,0)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x55555556, 0x10, 3f, x5, 788,0)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x4, 0x40, 3f, x5, 792,0)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xfffe; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xfffe, 0x10, 3f, x5, 796,0)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x0, 0x400, 1b, x5, 800,0)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xb503, 0x556, 1b, x5, 804,0)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x66666665, 0x6, 1b, x5, 808,0)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x33333332, 0x2, 3f, x5, 812,0)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaa9; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xaaaaaaa9, 0x8, 3f, x5, 816,0)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x55555554, 0x4, 3f, x5, 820,0)
+
+inst_217:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x2, 0x20, 3f, x5, 824,0)
+
+inst_218:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xffff; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xffff, 0x40, 3f, x5, 828,0)
+
+inst_219:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xb504, 0x10, 3f, x5, 832,0)
+
+inst_220:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x66666666, 0x4, 3f, x5, 836,0)
+
+inst_221:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x33333333, 0x400, 3f, x5, 840,0)
+
+inst_222:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x5, 0x0, 3f, x5, 844,0)
+
+inst_223:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaaa; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0xaaaaaaaa, 0x2, 3f, x5, 848,0)
+
+inst_224:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x55555555, 0x0, 1b, x5, 852,0)
+
+inst_225:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333334, 0x3, 0x2, 1b, x5, 856,0)
+
+inst_226:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x10000, 0x4, 3f, x5, 860,0)
+
+inst_227:
+// rs1_val==6 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x1; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x1, 0x20, 3f, x5, 864,0)
+
+inst_228:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xb505, 0x100, 3f, x5, 868,0)
+
+inst_229:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x66666667, 0x2, 3f, x5, 872,0)
+
+inst_230:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x33333334, 0x556, 1b, x5, 876,0)
+
+inst_231:
+// rs1_val==6 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x6, 0x4, 3f, x5, 880,0)
+
+inst_232:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaab; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xaaaaaaab, 0x20, 3f, x5, 884,0)
+
+inst_233:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x55555556, 0x4, 3f, x5, 888,0)
+
+inst_234:
+// rs1_val==6 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x4, 0x4, 1b, x5, 892,0)
+
+inst_235:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xfffe; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xfffe, 0x6, 1b, x5, 896,0)
+
+inst_236:
+// rs1_val==6 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x0, 0x556, 1b, x5, 900,0)
+
+inst_237:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xb503, 0x10, 3f, x5, 904,0)
+
+inst_238:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x66666665, 0x8, 3f, x5, 908,0)
+
+inst_239:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x33333332, 0x4, 1b, x5, 912,0)
+
+inst_240:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaa9; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xaaaaaaa9, 0x4, 1b, x5, 916,0)
+
+inst_241:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x55555554, 0x200, 3f, x5, 920,0)
+
+inst_242:
+// rs1_val==6 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x2, 0x4, 3f, x5, 924,0)
+
+inst_243:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xffff, 0x4, 1b, x5, 928,0)
+
+inst_244:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xb504, 0x80, 3f, x5, 932,0)
+
+inst_245:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x66666666, 0x6, 1b, x5, 936,0)
+
+inst_246:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x33333333, 0x2, 3f, x5, 940,0)
+
+inst_247:
+// rs1_val==6 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x5, 0x40, 3f, x5, 944,0)
+
+inst_248:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaaa; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0xaaaaaaaa, 0x80, 3f, x5, 948,0)
+
+inst_249:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x55555555, 0x556, 1b, x5, 952,0)
+
+inst_250:
+// rs1_val==6 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x6, 0x3, 0x6, 1b, x5, 956,0)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x10000, 0x400, 1b, x5, 960,0)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x1; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x1, 0xa, 1b, x5, 964,0)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xb505, 0x100, 3f, x5, 968,0)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666667; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x66666667, 0x100, 3f, x5, 972,0)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x33333334, 0x8, 1b, x5, 976,0)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x6, 0x2, 1b, x5, 980,0)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==2863311531, rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xaaaaaaab, 0x8, 1b, x5, 984,0)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x55555556, 0x8, 3f, x5, 988,0)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x4, 0x6, 3f, x5, 992,0)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xfffe; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xfffe, 0x6, 1b, x5, 996,0)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x0, 0x400, 1b, x5, 1000,0)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xb503, 0x8, 1b, x5, 1004,0)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x66666665, 0x2, 3f, x5, 1008,0)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x33333332, 0x0, 3f, x5, 1012,0)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaa9; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xaaaaaaa9, 0x8, 1b, x5, 1016,0)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x55555554, 0x40, 3f, x5, 1020,0)
+
+inst_267:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x2, 0x2, 1b, x5, 1024,0)
+
+inst_268:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xffff; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xffff, 0x200, 3f, x5, 1028,0)
+
+inst_269:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xb504, 0x8, 3f, x5, 1032,0)
+
+inst_270:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666666; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x66666666, 0x80, 3f, x5, 1036,0)
+
+inst_271:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x33333333, 0x6, 1b, x5, 1040,0)
+
+inst_272:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x5, 0x2, 3f, x5, 1044,0)
+
+inst_273:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaaa; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0xaaaaaaaa, 0xa, 1b, x5, 1048,0)
+
+inst_274:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x55555555, 0x40, 3f, x5, 1052,0)
+
+inst_275:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaab, 0x3, 0x6, 1b, x5, 1056,0)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x10000, 0x4, 1b, x5, 1060,0)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x1, 0x0, 1b, x5, 1064,0)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xb505, 0x8, 1b, x5, 1068,0)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x66666667, 0x4, 1b, x5, 1072,0)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x33333334, 0x20, 3f, x5, 1076,0)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x6, 0x6, 3f, x5, 1080,0)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaab; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xaaaaaaab, 0x400, 3f, x5, 1084,0)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x55555556, 0x20, 3f, x5, 1088,0)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x4, 0x4, 3f, x5, 1092,0)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xfffe; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xfffe, 0x8, 3f, x5, 1096,0)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x0, 0x400, 3f, x5, 1100,0)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xb503, 0x8, 3f, x5, 1104,0)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x66666665, 0x0, 1b, x5, 1108,0)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x33333332, 0x556, 1b, x5, 1112,0)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaa9; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xaaaaaaa9, 0x6, 3f, x5, 1116,0)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x55555554, 0x2, 3f, x5, 1120,0)
+
+inst_292:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x2, 0x20, 3f, x5, 1124,0)
+
+inst_293:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xffff; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xffff, 0x400, 3f, x5, 1128,0)
+
+inst_294:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xb504, 0x80, 3f, x5, 1132,0)
+
+inst_295:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x66666666, 0x80, 3f, x5, 1136,0)
+
+inst_296:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x33333333, 0x6, 1b, x5, 1140,0)
+
+inst_297:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x5, 0x80, 3f, x5, 1144,0)
+
+inst_298:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaaa; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0xaaaaaaaa, 0x8, 3f, x5, 1148,0)
+
+inst_299:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x55555555, 0x400, 3f, x5, 1152,0)
+
+inst_300:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555556, 0x3, 0x2, 1b, x5, 1156,0)
+
+inst_301:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x10000, 0x2, 1b, x5, 1160,0)
+
+inst_302:
+// rs1_val==4 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x1, 0x4, 1b, x5, 1164,0)
+
+inst_303:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xb505, 0x2, 3f, x5, 1168,0)
+
+inst_304:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x66666667, 0x6, 3f, x5, 1172,0)
+
+inst_305:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x33333334, 0x0, 1b, x5, 1176,0)
+
+inst_306:
+// rs1_val==4 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x6, 0x4, 1b, x5, 1180,0)
+
+inst_307:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xaaaaaaab, 0x4, 3f, x5, 1184,0)
+
+inst_308:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x55555556, 0x4, 3f, x5, 1188,0)
+
+inst_309:
+// rs1_val==4 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x4, 0x0, 1b, x5, 1192,0)
+
+inst_310:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xfffe, 0x200, 3f, x5, 1196,0)
+
+inst_311:
+// rs1_val==4 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x0, 0x2, 1b, x5, 1200,0)
+
+inst_312:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xb503, 0xa, 1b, x5, 1204,0)
+
+inst_313:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x66666665, 0x8, 3f, x5, 1208,0)
+
+inst_314:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x33333332, 0x400, 1b, x5, 1212,0)
+
+inst_315:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaa9; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xaaaaaaa9, 0x200, 3f, x5, 1216,0)
+
+inst_316:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x55555554, 0x100, 3f, x5, 1220,0)
+
+inst_317:
+// rs1_val==4 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x2, 0x2, 3f, x5, 1224,0)
+
+inst_318:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xffff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xffff, 0x100, 3f, x5, 1228,0)
+
+inst_319:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xb504, 0xa, 1b, x5, 1232,0)
+
+inst_320:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x66666666, 0x10, 3f, x5, 1236,0)
+
+inst_321:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x33333333, 0x80, 3f, x5, 1240,0)
+
+inst_322:
+// rs1_val==4 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x5, 0x2, 1b, x5, 1244,0)
+
+inst_323:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaaa; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0xaaaaaaaa, 0x200, 3f, x5, 1248,0)
+
+inst_324:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x55555555, 0x10, 3f, x5, 1252,0)
+
+inst_325:
+// rs1_val==4 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x4, 0x3, 0x20, 3f, x5, 1256,0)
+
+inst_326:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x10000, 0x0, 3f, x5, 1260,0)
+
+inst_327:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x1; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x1, 0x40, 3f, x5, 1264,0)
+
+inst_328:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xb505, 0x0, 3f, x5, 1268,0)
+
+inst_329:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x66666667, 0xa, 1b, x5, 1272,0)
+
+inst_330:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x33333334, 0x8, 3f, x5, 1276,0)
+
+inst_331:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x6, 0x20, 3f, x5, 1280,0)
+
+inst_332:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xaaaaaaab, 0x6, 1b, x5, 1284,0)
+
+inst_333:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x55555556, 0x10, 3f, x5, 1288,0)
+
+inst_334:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x4, 0x400, 3f, x5, 1292,0)
+
+inst_335:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xfffe; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xfffe, 0x556, 1b, x5, 1296,0)
+
+inst_336:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x0, 0x2, 3f, x5, 1300,0)
+
+inst_337:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xb503, 0x0, 1b, x5, 1304,0)
+
+inst_338:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x66666665, 0x8, 1b, x5, 1308,0)
+
+inst_339:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x33333332, 0x40, 3f, x5, 1312,0)
+
+inst_340:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaa9; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xaaaaaaa9, 0x2, 1b, x5, 1316,0)
+
+inst_341:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x55555554, 0x6, 1b, x5, 1320,0)
+
+inst_342:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x2, 0x2, 1b, x5, 1324,0)
+
+inst_343:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xffff; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xffff, 0xa, 1b, x5, 1328,0)
+
+inst_344:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xb504, 0x2, 3f, x5, 1332,0)
+
+inst_345:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x66666666, 0x200, 3f, x5, 1336,0)
+
+inst_346:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x33333333, 0x2, 1b, x5, 1340,0)
+
+inst_347:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x5, 0x400, 1b, x5, 1344,0)
+
+inst_348:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaaa; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0xaaaaaaaa, 0xa, 1b, x5, 1348,0)
+
+inst_349:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x55555555, 0x20, 3f, x5, 1352,0)
+
+inst_350:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xfffe, 0x3, 0x6, 1b, x5, 1356,0)
+
+inst_351:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x10000; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x10000, 0x10, 3f, x5, 1360,0)
+
+inst_352:
+// rs1_val==0 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x1, 0x6, 1b, x5, 1364,0)
+
+inst_353:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xb505, 0x6, 3f, x5, 1368,0)
+
+inst_354:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x66666667, 0x400, 1b, x5, 1372,0)
+
+inst_355:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x33333334, 0x8, 1b, x5, 1376,0)
+
+inst_356:
+// rs1_val==0 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x6, 0x80, 3f, x5, 1380,0)
+
+inst_357:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xaaaaaaab, 0x100, 3f, x5, 1384,0)
+
+inst_358:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x55555556, 0x0, 1b, x5, 1388,0)
+
+inst_359:
+// rs1_val==0 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x4, 0x4, 3f, x5, 1392,0)
+
+inst_360:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xfffe, 0x200, 3f, x5, 1396,0)
+
+inst_361:
+// rs1_val==0 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x0, 0x2, 1b, x5, 1400,0)
+
+inst_362:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xb503, 0x400, 1b, x5, 1404,0)
+
+inst_363:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x66666665, 0x80, 3f, x5, 1408,0)
+
+inst_364:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x33333332, 0x200, 3f, x5, 1412,0)
+
+inst_365:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaa9; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xaaaaaaa9, 0x6, 1b, x5, 1416,0)
+
+inst_366:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x55555554, 0xa, 1b, x5, 1420,0)
+
+inst_367:
+// rs1_val==0 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x2, 0x4, 1b, x5, 1424,0)
+
+inst_368:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xffff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xffff, 0x556, 1b, x5, 1428,0)
+
+inst_369:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xb504, 0x80, 3f, x5, 1432,0)
+
+inst_370:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x66666666, 0x2, 3f, x5, 1436,0)
+
+inst_371:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x33333333, 0x400, 3f, x5, 1440,0)
+
+inst_372:
+// rs1_val==0 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x5, 0x4, 1b, x5, 1444,0)
+
+inst_373:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaaa; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0xaaaaaaaa, 0xa, 1b, x5, 1448,0)
+
+inst_374:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x55555555, 0x0, 1b, x5, 1452,0)
+
+inst_375:
+// rs1_val==0 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x0, 0x3, 0x10, 3f, x5, 1456,0)
+
+inst_376:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x10000, 0x2, 1b, x5, 1460,0)
+
+inst_377:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x1; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x1, 0x2, 3f, x5, 1464,0)
+
+inst_378:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xb505, 0x0, 3f, x5, 1468,0)
+
+inst_379:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x66666667, 0x0, 3f, x5, 1472,0)
+
+inst_380:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x33333334, 0xa, 1b, x5, 1476,0)
+
+inst_381:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x6, 0x200, 3f, x5, 1480,0)
+
+inst_382:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xaaaaaaab, 0x4, 1b, x5, 1484,0)
+
+inst_383:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x55555556, 0x200, 3f, x5, 1488,0)
+
+inst_384:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x4, 0x8, 3f, x5, 1492,0)
+
+inst_385:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xfffe; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xfffe, 0x100, 3f, x5, 1496,0)
+
+inst_386:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x0, 0x4, 1b, x5, 1500,0)
+
+inst_387:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xb503, 0x4, 1b, x5, 1504,0)
+
+inst_388:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x66666665, 0x4, 1b, x5, 1508,0)
+
+inst_389:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x33333332, 0x2, 1b, x5, 1512,0)
+
+inst_390:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaa9; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xaaaaaaa9, 0x40, 3f, x5, 1516,0)
+
+inst_391:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x55555554, 0x400, 1b, x5, 1520,0)
+
+inst_392:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x2, 0x10, 3f, x5, 1524,0)
+
+inst_393:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xffff; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xffff, 0x4, 1b, x5, 1528,0)
+
+inst_394:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xb504, 0x10, 3f, x5, 1532,0)
+
+inst_395:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x66666666, 0x400, 3f, x5, 1536,0)
+
+inst_396:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x33333333, 0x20, 3f, x5, 1540,0)
+
+inst_397:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x5, 0xa, 1b, x5, 1544,0)
+
+inst_398:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaaa; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0xaaaaaaaa, 0x556, 1b, x5, 1548,0)
+
+inst_399:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x55555555, 0x0, 3f, x5, 1552,0)
+
+inst_400:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb503, 0x3, 0x40, 3f, x5, 1556,0)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x10000, 0x6, 1b, x5, 1560,0)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x1; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x1, 0xa, 1b, x5, 1564,0)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xb505, 0x0, 3f, x5, 1568,0)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x66666667, 0x6, 3f, x5, 1572,0)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x33333334, 0x4, 1b, x5, 1576,0)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x6, 0x0, 1b, x5, 1580,0)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xaaaaaaab, 0x8, 3f, x5, 1584,0)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x55555556, 0x200, 3f, x5, 1588,0)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x4, 0x6, 1b, x5, 1592,0)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xfffe, 0x200, 3f, x5, 1596,0)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x0, 0x400, 1b, x5, 1600,0)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xb503, 0x6, 3f, x5, 1604,0)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x66666665, 0x20, 3f, x5, 1608,0)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x33333332, 0x0, 3f, x5, 1612,0)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaa9; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xaaaaaaa9, 0x4, 1b, x5, 1616,0)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x55555554, 0x80, 3f, x5, 1620,0)
+
+inst_417:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x2, 0x40, 3f, x5, 1624,0)
+
+inst_418:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xffff, 0x6, 3f, x5, 1628,0)
+
+inst_419:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xb504, 0x80, 3f, x5, 1632,0)
+
+inst_420:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x66666666, 0x8, 1b, x5, 1636,0)
+
+inst_421:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x33333333, 0x10, 3f, x5, 1640,0)
+
+inst_422:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x5, 0x0, 1b, x5, 1644,0)
+
+inst_423:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaaa; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0xaaaaaaaa, 0x556, 1b, x5, 1648,0)
+
+inst_424:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x55555555, 0x200, 3f, x5, 1652,0)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666665, 0x3, 0x8, 1b, x5, 1656,0)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x10000; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x10000, 0x100, 3f, x5, 1660,0)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x1, 0x8, 1b, x5, 1664,0)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xb505, 0x2, 1b, x5, 1668,0)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x66666667, 0x400, 3f, x5, 1672,0)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x33333334, 0x10, 3f, x5, 1676,0)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x6, 0xa, 1b, x5, 1680,0)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xaaaaaaab, 0x100, 3f, x5, 1684,0)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x55555556, 0x4, 1b, x5, 1688,0)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x4, 0x100, 3f, x5, 1692,0)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xfffe; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xfffe, 0x2, 3f, x5, 1696,0)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x0, 0x80, 3f, x5, 1700,0)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xb503, 0x556, 1b, x5, 1704,0)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x66666665, 0x400, 1b, x5, 1708,0)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x33333332, 0x10, 3f, x5, 1712,0)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaa9; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xaaaaaaa9, 0x6, 1b, x5, 1716,0)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x55555554, 0x0, 1b, x5, 1720,0)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x2, 0x10, 3f, x5, 1724,0)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xffff, 0x6, 3f, x5, 1728,0)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xb504, 0x6, 1b, x5, 1732,0)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x66666666, 0x100, 3f, x5, 1736,0)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x33333333, 0x2, 1b, x5, 1740,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x5, 0x2, 1b, x5, 1744,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaaa; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0xaaaaaaaa, 0x80, 3f, x5, 1748,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x55555555, 0x80, 3f, x5, 1752,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333332, 0x3, 0x200, 3f, x5, 1756,0)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x10000; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x10000, 0x20, 3f, x5, 1760,0)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x1; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x1, 0x556, 1b, x5, 1764,0)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xb505, 0x40, 3f, x5, 1768,0)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x66666667, 0x40, 3f, x5, 1772,0)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x33333334, 0x400, 3f, x5, 1776,0)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x6, 0x6, 3f, x5, 1780,0)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaab; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xaaaaaaab, 0x80, 3f, x5, 1784,0)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x55555556, 0x4, 3f, x5, 1788,0)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x4, 0x6, 1b, x5, 1792,0)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xfffe, 0x200, 3f, x5, 1796,0)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x0, 0x4, 1b, x5, 1800,0)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xb503, 0x80, 3f, x5, 1804,0)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x66666665, 0x400, 3f, x5, 1808,0)
+
+inst_464:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x33333332, 0x4, 3f, x5, 1812,0)
+
+inst_465:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaa9; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0x0, 1b, x5, 1816,0)
+
+inst_466:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x55555554, 0x2, 1b, x5, 1820,0)
+
+inst_467:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x2, 0x6, 3f, x5, 1824,0)
+
+inst_468:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xffff; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xffff, 0x200, 3f, x5, 1828,0)
+
+inst_469:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xb504, 0x400, 1b, x5, 1832,0)
+
+inst_470:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x66666666, 0x100, 3f, x5, 1836,0)
+
+inst_471:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x33333333, 0x400, 1b, x5, 1840,0)
+
+inst_472:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x5, 0x2, 3f, x5, 1844,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x4, 0x10, 3f, x5, 1848,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xfffe; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xfffe, 0x556, 1b, x5, 1852,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x0, 0x200, 3f, x5, 1856,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xb503, 0x80, 3f, x5, 1860,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x66666665, 0x8, 1b, x5, 1864,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x33333332, 0x80, 3f, x5, 1868,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaa9; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xaaaaaaa9, 0x100, 3f, x5, 1872,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x55555554, 0x0, 1b, x5, 1876,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x2, 0x80, 3f, x5, 1880,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xffff; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xffff, 0x20, 3f, x5, 1884,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xb504, 0x556, 1b, x5, 1888,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x66666666, 0x6, 1b, x5, 1892,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x33333333, 0x556, 1b, x5, 1896,0)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x5, 0x20, 3f, x5, 1900,0)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaaa; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xaaaaaaaa, 0x20, 3f, x5, 1904,0)
+
+inst_488:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x55555555, 0x100, 3f, x5, 1908,0)
+
+inst_489:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x3, 0x556, 1b, x5, 1912,0)
+
+inst_490:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x10000, 0x4, 3f, x5, 1916,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x1; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x1, 0x40, 3f, x5, 1920,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xb505, 0x2, 3f, x5, 1924,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x66666667, 0x2, 1b, x5, 1928,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x33333334, 0x8, 3f, x5, 1932,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x6, 0x8, 1b, x5, 1936,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xaaaaaaab, 0x4, 1b, x5, 1940,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x55555556, 0x100, 3f, x5, 1944,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x4, 0x556, 1b, x5, 1948,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xfffe, 0x200, 3f, x5, 1952,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x0, 0x400, 3f, x5, 1956,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xb503, 0x0, 3f, x5, 1960,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x66666665, 0x4, 3f, x5, 1964,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x33333332, 0x20, 3f, x5, 1968,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaa9; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xaaaaaaa9, 0x0, 1b, x5, 1972,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x55555554, 0x200, 3f, x5, 1976,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x2, 0x400, 3f, x5, 1980,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xffff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xffff, 0x556, 1b, x5, 1984,0)
+
+inst_508:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xb504, 0x8, 3f, x5, 1988,0)
+
+inst_509:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x66666666, 0x40, 3f, x5, 1992,0)
+
+inst_510:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x33333333, 0xa, 1b, x5, 1996,0)
+
+inst_511:
+// rs1_val==2 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x5, 0x10, 3f, x5, 2000,0)
+
+inst_512:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaaa; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0xaaaaaaaa, 0x400, 1b, x5, 2004,0)
+
+inst_513:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x55555555, 0xa, 1b, x5, 2008,0)
+
+inst_514:
+// rs1_val==2 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x2, 0x3, 0x6, 3f, x5, 2012,0)
+
+inst_515:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x10000; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x10000, 0x556, 1b, x5, 2016,0)
+
+inst_516:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x1, 0x4, 1b, x5, 2020,0)
+
+inst_517:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xb505, 0x8, 3f, x5, 2024,0)
+
+inst_518:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x66666667, 0x4, 1b, x5, 2028,0)
+
+inst_519:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333334; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x33333334, 0x20, 3f, x5, 2032,0)
+
+inst_520:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x6, 0x4, 1b, x5, 2036,0)
+
+inst_521:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xaaaaaaab, 0x100, 3f, x5, 2040,0)
+
+inst_522:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x55555556, 0x20, 3f, x5, 2044,0)
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_523:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x4; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x4, 0x100, 3f, x5, 0,0)
+
+inst_524:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xfffe; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xfffe, 0x6, 1b, x5, 4,0)
+
+inst_525:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x0, 0x556, 1b, x5, 8,0)
+
+inst_526:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xb503, 0x100, 3f, x5, 12,0)
+
+inst_527:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x66666665, 0x2, 1b, x5, 16,0)
+
+inst_528:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x33333332, 0x100, 3f, x5, 20,0)
+
+inst_529:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaa9; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xaaaaaaa9, 0x200, 3f, x5, 24,0)
+
+inst_530:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555554; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x55555554, 0x20, 3f, x5, 28,0)
+
+inst_531:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x2, 0x6, 1b, x5, 32,0)
+
+inst_532:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xffff, 0x0, 1b, x5, 36,0)
+
+inst_533:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xb504, 0x200, 3f, x5, 40,0)
+
+inst_534:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x66666666, 0x0, 3f, x5, 44,0)
+
+inst_535:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x33333333, 0xa, 1b, x5, 48,0)
+
+inst_536:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x5, 0x80, 3f, x5, 52,0)
+
+inst_537:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaaa; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0xaaaaaaaa, 0x40, 3f, x5, 56,0)
+
+inst_538:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x55555555, 0x2, 3f, x5, 60,0)
+
+inst_539:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xffff; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xffff, 0x3, 0x8, 3f, x5, 64,0)
+
+inst_540:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x10000, 0x6, 1b, x5, 68,0)
+
+inst_541:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x1; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x1, 0x2, 1b, x5, 72,0)
+
+inst_542:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xb505, 0x40, 3f, x5, 76,0)
+
+inst_543:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x66666667, 0x8, 1b, x5, 80,0)
+
+inst_544:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x33333334, 0x400, 3f, x5, 84,0)
+
+inst_545:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x6, 0x2, 1b, x5, 88,0)
+
+inst_546:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaab; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xaaaaaaab, 0x556, 1b, x5, 92,0)
+
+inst_547:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x55555556, 0x0, 3f, x5, 96,0)
+
+inst_548:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x4, 0x8, 1b, x5, 100,0)
+
+inst_549:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xfffe; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xfffe, 0x80, 3f, x5, 104,0)
+
+inst_550:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x0, 0x2, 3f, x5, 108,0)
+
+inst_551:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xb503, 0xa, 1b, x5, 112,0)
+
+inst_552:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x66666665, 0x8, 3f, x5, 116,0)
+
+inst_553:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x33333332, 0x4, 1b, x5, 120,0)
+
+inst_554:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaa9; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xaaaaaaa9, 0x200, 3f, x5, 124,0)
+
+inst_555:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x55555554, 0x100, 3f, x5, 128,0)
+
+inst_556:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x2, 0x200, 3f, x5, 132,0)
+
+inst_557:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xffff; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xffff, 0x100, 3f, x5, 136,0)
+
+inst_558:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xb504, 0x400, 1b, x5, 140,0)
+
+inst_559:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x66666666, 0x0, 1b, x5, 144,0)
+
+inst_560:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x33333333, 0x200, 3f, x5, 148,0)
+
+inst_561:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x5, 0x556, 1b, x5, 152,0)
+
+inst_562:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaaa; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0xaaaaaaaa, 0x10, 3f, x5, 156,0)
+
+inst_563:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x55555555, 0x8, 3f, x5, 160,0)
+
+inst_564:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xb504, 0x3, 0x8, 3f, x5, 164,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x10000; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x10000, 0x10, 3f, x5, 168,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x1; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x1, 0x200, 3f, x5, 172,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xb505, 0x4, 1b, x5, 176,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x66666667, 0x6, 1b, x5, 180,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x33333334, 0x2, 1b, x5, 184,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x6, 0x8, 1b, x5, 188,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xaaaaaaab, 0x6, 3f, x5, 192,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x55555556, 0x4, 1b, x5, 196,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x4, 0x40, 3f, x5, 200,0)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xfffe, 0x200, 3f, x5, 204,0)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x0, 0x0, 1b, x5, 208,0)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xb503, 0x0, 1b, x5, 212,0)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x66666665, 0x100, 3f, x5, 216,0)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x33333332, 0x2, 3f, x5, 220,0)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaa9; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xaaaaaaa9, 0x10, 3f, x5, 224,0)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x55555554, 0x556, 1b, x5, 228,0)
+
+inst_581:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x2, 0x400, 1b, x5, 232,0)
+
+inst_582:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xffff; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xffff, 0x200, 3f, x5, 236,0)
+
+inst_583:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xb504, 0x2, 1b, x5, 240,0)
+
+inst_584:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x66666666, 0x200, 3f, x5, 244,0)
+
+inst_585:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x33333333, 0x10, 3f, x5, 248,0)
+
+inst_586:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x5, 0x400, 3f, x5, 252,0)
+
+inst_587:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0xaaaaaaaa, 0x4, 1b, x5, 256,0)
+
+inst_588:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x55555555, 0x2, 3f, x5, 260,0)
+
+inst_589:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x66666666, 0x3, 0x8, 1b, x5, 264,0)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x10000, 0x2, 1b, x5, 268,0)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x1, 0x0, 1b, x5, 272,0)
+
+inst_592:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xb505, 0x2, 3f, x5, 276,0)
+
+inst_593:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x66666667, 0x6, 3f, x5, 280,0)
+
+inst_594:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x33333334, 0x400, 1b, x5, 284,0)
+
+inst_595:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x6, 0x0, 3f, x5, 288,0)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaab; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xaaaaaaab, 0x10, 3f, x5, 292,0)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x55555556, 0x200, 3f, x5, 296,0)
+
+inst_598:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x4, 0x8, 1b, x5, 300,0)
+
+inst_599:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xfffe; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xfffe, 0xa, 1b, x5, 304,0)
+
+inst_600:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x0, 0x0, 1b, x5, 308,0)
+
+inst_601:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x3, 0x6, 1b, x5, 312,0)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xb503, 0x400, 1b, x5, 316,0)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x66666665, 0x100, 3f, x5, 320,0)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x33333332, 0x10, 3f, x5, 324,0)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaa9; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xaaaaaaa9, 0x100, 3f, x5, 328,0)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x55555554, 0x8, 1b, x5, 332,0)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x2, 0x80, 3f, x5, 336,0)
+
+inst_608:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xffff; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xffff, 0x556, 1b, x5, 340,0)
+
+inst_609:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xb504, 0x8, 1b, x5, 344,0)
+
+inst_610:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x66666666, 0x0, 3f, x5, 348,0)
+
+inst_611:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x33333333, 0x2, 1b, x5, 352,0)
+
+inst_612:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x5, 0x80, 3f, x5, 356,0)
+
+inst_613:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0xaaaaaaaa, 0x6, 1b, x5, 360,0)
+
+inst_614:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x55555555, 0x2, 3f, x5, 364,0)
+
+inst_615:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x33333333, 0x3, 0x0, 3f, x5, 368,0)
+
+inst_616:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x10000; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x10000, 0x100, 3f, x5, 372,0)
+
+inst_617:
+// rs1_val==5 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x1, 0x6, 3f, x5, 376,0)
+
+inst_618:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xb505, 0xa, 1b, x5, 380,0)
+
+inst_619:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x66666667, 0x400, 1b, x5, 384,0)
+
+inst_620:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x33333334, 0x8, 3f, x5, 388,0)
+
+inst_621:
+// rs1_val==5 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x6, 0x2, 1b, x5, 392,0)
+
+inst_622:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xaaaaaaab, 0x100, 3f, x5, 396,0)
+
+inst_623:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x55555556, 0x4, 3f, x5, 400,0)
+
+inst_624:
+// rs1_val==5 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x4, 0x0, 3f, x5, 404,0)
+
+inst_625:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xfffe; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xfffe, 0x400, 3f, x5, 408,0)
+
+inst_626:
+// rs1_val==5 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x0, 0x200, 3f, x5, 412,0)
+
+inst_627:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xb503, 0x556, 1b, x5, 416,0)
+
+inst_628:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x66666665, 0x6, 1b, x5, 420,0)
+
+inst_629:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x33333332, 0x556, 1b, x5, 424,0)
+
+inst_630:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaa9; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xaaaaaaa9, 0x6, 3f, x5, 428,0)
+
+inst_631:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x55555554, 0x556, 1b, x5, 432,0)
+
+inst_632:
+// rs1_val==5 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x2, 0x6, 3f, x5, 436,0)
+
+inst_633:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xffff; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xffff, 0xa, 1b, x5, 440,0)
+
+inst_634:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xb504, 0x556, 1b, x5, 444,0)
+
+inst_635:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x66666666, 0x2, 3f, x5, 448,0)
+
+inst_636:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x33333333, 0x6, 3f, x5, 452,0)
+
+inst_637:
+// rs1_val==5 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x5, 0x6, 1b, x5, 456,0)
+
+inst_638:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaaa; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0xaaaaaaaa, 0xa, 1b, x5, 460,0)
+
+inst_639:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x55555555, 0x0, 1b, x5, 464,0)
+
+inst_640:
+// rs1_val==5 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x5, 0x3, 0x0, 3f, x5, 468,0)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==65536, rs1_val == 2863311530
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x10000, 0x6, 1b, x5, 472,0)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x1; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x1, 0x556, 1b, x5, 476,0)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xb505, 0x10, 3f, x5, 480,0)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x66666667, 0x0, 1b, x5, 484,0)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x33333334, 0x4, 1b, x5, 488,0)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x6, 0x20, 3f, x5, 492,0)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaab; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xaaaaaaab, 0x0, 3f, x5, 496,0)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x55555556, 0x8, 3f, x5, 500,0)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x4, 0x80, 3f, x5, 504,0)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xfffe; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xfffe, 0x20, 3f, x5, 508,0)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x0, 0x6, 3f, x5, 512,0)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xb503, 0x400, 1b, x5, 516,0)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x66666665, 0x20, 3f, x5, 520,0)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x33333332, 0x0, 3f, x5, 524,0)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaa9; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xaaaaaaa9, 0x40, 3f, x5, 528,0)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x55555554, 0x40, 3f, x5, 532,0)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x2, 0x0, 1b, x5, 536,0)
+
+inst_658:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xffff; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xffff, 0x40, 3f, x5, 540,0)
+
+inst_659:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xb504, 0x0, 1b, x5, 544,0)
+
+inst_660:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x66666666, 0x400, 3f, x5, 548,0)
+
+inst_661:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333333; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x33333333, 0x100, 3f, x5, 552,0)
+
+inst_662:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x5, 0x100, 3f, x5, 556,0)
+
+inst_663:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0xaaaaaaaa, 0x6, 3f, x5, 560,0)
+
+inst_664:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x55555555, 0x400, 1b, x5, 564,0)
+
+inst_665:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaaa, 0x3, 0x20, 3f, x5, 568,0)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==65536, rs1_val == 1431655765
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x10000, 0x400, 3f, x5, 572,0)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x1, 0x8, 1b, x5, 576,0)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xb505, 0x10, 3f, x5, 580,0)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x66666667, 0x40, 3f, x5, 584,0)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x33333334, 0x6, 3f, x5, 588,0)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x6, 0x80, 3f, x5, 592,0)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xaaaaaaab, 0x8, 3f, x5, 596,0)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x55555556, 0x200, 3f, x5, 600,0)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x4, 0x556, 1b, x5, 604,0)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xfffe; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xfffe, 0x4, 3f, x5, 608,0)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x0, 0x200, 3f, x5, 612,0)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xb503, 0x8, 3f, x5, 616,0)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x66666665, 0xa, 1b, x5, 620,0)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x33333332, 0x4, 1b, x5, 624,0)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaa9; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xaaaaaaa9, 0x100, 3f, x5, 628,0)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x55555554, 0x100, 3f, x5, 632,0)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x2, 0x8, 1b, x5, 636,0)
+
+inst_683:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xffff, 0x0, 1b, x5, 640,0)
+
+inst_684:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xb504, 0x20, 3f, x5, 644,0)
+
+inst_685:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x66666666, 0x4, 1b, x5, 648,0)
+
+inst_686:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x33333333, 0x400, 1b, x5, 652,0)
+
+inst_687:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x5, 0xa, 1b, x5, 656,0)
+
+inst_688:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaaa; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0xaaaaaaaa, 0x8, 3f, x5, 660,0)
+
+inst_689:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x55555555, 0x0, 1b, x5, 664,0)
+
+inst_690:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555555, 0x3, 0x8, 3f, x5, 668,0)
+
+inst_691:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x10000, 0x400, 1b, x5, 672,0)
+
+inst_692:
+// rs1_val==3 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x1; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x1, 0x400, 1b, x5, 676,0)
+
+inst_693:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xb505, 0x8, 3f, x5, 680,0)
+
+inst_694:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x66666667, 0x0, 3f, x5, 684,0)
+
+inst_695:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x33333334, 0x8, 1b, x5, 688,0)
+
+inst_696:
+// rs1_val==3 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x6, 0x0, 3f, x5, 692,0)
+
+inst_697:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaab; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xaaaaaaab, 0x400, 3f, x5, 696,0)
+
+inst_698:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x55555556, 0x400, 3f, x5, 700,0)
+
+inst_699:
+// rs1_val==3 and rs2_val==4, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x4, 0x8, 1b, x5, 704,0)
+
+inst_700:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xfffe; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xfffe, 0x8, 3f, x5, 708,0)
+
+inst_701:
+// rs1_val==3 and rs2_val==0, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x0, 0xa, 1b, x5, 712,0)
+
+inst_702:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xb503, 0x40, 3f, x5, 716,0)
+
+inst_703:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x66666665, 0x200, 3f, x5, 720,0)
+
+inst_704:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x33333332, 0x200, 3f, x5, 724,0)
+
+inst_705:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaa9; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xaaaaaaa9, 0x4, 1b, x5, 728,0)
+
+inst_706:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x55555554, 0x2, 3f, x5, 732,0)
+
+inst_707:
+// rs1_val==3 and rs2_val==2, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x2, 0x400, 1b, x5, 736,0)
+
+inst_708:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xffff, 0x6, 3f, x5, 740,0)
+
+inst_709:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xb504, 0x2, 3f, x5, 744,0)
+
+inst_710:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x66666666, 0x8, 1b, x5, 748,0)
+
+inst_711:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x33333333, 0x2, 1b, x5, 752,0)
+
+inst_712:
+// rs1_val==3 and rs2_val==5, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x5, 0x4, 3f, x5, 756,0)
+
+inst_713:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaaa; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0xaaaaaaaa, 0x0, 1b, x5, 760,0)
+
+inst_714:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x55555555, 0x0, 3f, x5, 764,0)
+
+inst_715:
+// rs1_val==3 and rs2_val==3, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x3, 0x3, 0x200, 3f, x5, 768,0)
+
+inst_716:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaaa; immval:0x200; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0xaaaaaaaa, 0x200, 3f, x5, 772,0)
+
+inst_717:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0xaaaaaaa9, 0x55555555, 0x20, 3f, x5, 776,0)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x10000, 0x4, 1b, x5, 780,0)
+
+inst_719:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x1, 0x6, 3f, x5, 784,0)
+
+inst_720:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xb505, 0x2, 3f, x5, 788,0)
+
+inst_721:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x66666667, 0x4, 1b, x5, 792,0)
+
+inst_722:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x33333334, 0x2, 1b, x5, 796,0)
+
+inst_723:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x6, 0xa, 1b, x5, 800,0)
+
+inst_724:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0xaaaaaaab, 0x6, 1b, x5, 804,0)
+
+inst_725:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x55555554, 0x55555556, 0xa, 1b, x5, 808,0)
+
+inst_726:
+// rs2_val == 3221225471, 
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x11; op2val:0xbfffffff; immval:0xa; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x11, 0xbfffffff, 0xa, 1b, x5, 812,0)
+
+inst_727:
+// rs2_val == 4294836223, rs1_val == 2147483647
+// opcode: bgeu, op1:x10; op2:x11; op1val:0x7fffffff; op2val:0xfffdffff; immval:0x2; align:0
+TEST_BRANCH_OP(bgeu, x6, x10, x11, 0x7fffffff, 0xfffdffff, 0x2, 1b, x5, 816,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 11*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 205*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S
new file mode 100644
index 000000000..a23350a44
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S
@@ -0,0 +1,3011 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the blt instruction of the RISC-V E extension for the blt covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",blt)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 == rs2, rs1==x7, rs2==x7, rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val == -65537, rs2_val == -65, rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: blt, op1:x7; op2:x7; op1val:-0x10001; op2val:-0x10001; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x4, x7, x7, -0x10001, -0x10001, 0x80, 3f, x6, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x9, rs2==x15, rs2_val == 2147483647, rs1_val == 4, rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: blt, op1:x9; op2:x15; op1val:0x4; op2val:0x7fffffff; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x4, x9, x15, 0x4, 0x7fffffff, 0x0, 3f, x6, 4,0)
+
+inst_2:
+// rs1==x12, rs2==x3, rs2_val == -1073741825, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0
+// opcode: blt, op1:x12; op2:x3; op1val:0x4; op2val:-0x40000001; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x4, x12, x3, 0x4, -0x40000001, 0x400, 3f, x6, 8,0)
+
+inst_3:
+// rs1==x2, rs2==x5, rs2_val == -536870913, 
+// opcode: blt, op1:x2; op2:x5; op1val:0x0; op2val:-0x20000001; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x4, x2, x5, 0x0, -0x20000001, 0x6, 1b, x6, 12,0)
+
+inst_4:
+// rs1==x11, rs2==x0, rs2_val == -268435457, rs1_val == 1048576
+// opcode: blt, op1:x11; op2:x0; op1val:0x100000; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x4, x11, x0, 0x100000, 0x0, 0x200, 3f, x6, 16,0)
+
+inst_5:
+// rs1==x3, rs2==x13, rs2_val == -134217729, rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0, rs1_val == -9
+// opcode: blt, op1:x3; op2:x13; op1val:-0x9; op2val:-0x8000001; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x4, x3, x13, -0x9, -0x8000001, 0x4, 1b, x6, 20,0)
+
+inst_6:
+// rs1==x5, rs2==x12, rs2_val == -67108865, 
+// opcode: blt, op1:x5; op2:x12; op1val:-0x1; op2val:-0x4000001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x4, x5, x12, -0x1, -0x4000001, 0x2, 1b, x6, 24,0)
+
+inst_7:
+// rs1==x1, rs2==x14, rs2_val == -33554433, 
+// opcode: blt, op1:x1; op2:x14; op1val:-0x10001; op2val:-0x2000001; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x4, x1, x14, -0x10001, -0x2000001, 0x6, 1b, x6, 28,0)
+
+inst_8:
+// rs1==x13, rs2==x4, rs2_val == -16777217, rs1_val == 1024
+// opcode: blt, op1:x13; op2:x4; op1val:0x400; op2val:-0x1000001; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x5, x13, x4, 0x400, -0x1000001, 0x6, 3f, x6, 32,0)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_9:
+// rs1==x14, rs2==x8, rs2_val == -8388609, rs1_val == -2049
+// opcode: blt, op1:x14; op2:x8; op1val:-0x801; op2val:-0x800001; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x5, x14, x8, -0x801, -0x800001, 0x8, 3f, x3, 0,0)
+
+inst_10:
+// rs1==x8, rs2==x10, rs2_val == -4194305, 
+// opcode: blt, op1:x8; op2:x10; op1val:-0x1; op2val:-0x400001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x5, x8, x10, -0x1, -0x400001, 0x2, 1b, x3, 4,0)
+
+inst_11:
+// rs1==x0, rs2==x2, rs2_val == -2097153, 
+// opcode: blt, op1:x0; op2:x2; op1val:0x0; op2val:-0x200001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x5, x0, x2, 0x0, -0x200001, 0x2, 3f, x3, 8,0)
+
+inst_12:
+// rs1==x4, rs2==x1, rs2_val == -1048577, rs1_val == 67108864
+// opcode: blt, op1:x4; op2:x1; op1val:0x4000000; op2val:-0x100001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x5, x4, x1, 0x4000000, -0x100001, 0x2, 1b, x3, 12,0)
+
+inst_13:
+// rs1==x10, rs2==x6, rs2_val == -524289, rs1_val == -8388609
+// opcode: blt, op1:x10; op2:x6; op1val:-0x800001; op2val:-0x80001; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x5, x10, x6, -0x800001, -0x80001, 0x556, 1b, x3, 16,0)
+
+inst_14:
+// rs1==x15, rs2==x11, rs2_val == -262145, 
+// opcode: blt, op1:x15; op2:x11; op1val:-0xb503; op2val:-0x40001; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x5, x15, x11, -0xb503, -0x40001, 0x200, 3f, x3, 20,0)
+
+inst_15:
+// rs1==x6, rs2==x9, rs2_val == -131073, rs1_val == -1025
+// opcode: blt, op1:x6; op2:x9; op1val:-0x401; op2val:-0x20001; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x5, x6, x9, -0x401, -0x20001, 0x4, 3f, x3, 24,0)
+
+inst_16:
+// rs2_val == -65537, rs1_val == 2048
+// opcode: blt, op1:x10; op2:x11; op1val:0x800; op2val:-0x10001; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x800, -0x10001, 0x0, 3f, x3, 28,0)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:-0x8001; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, -0x8001, 0x0, 1b, x3, 32,0)
+
+inst_18:
+// rs2_val == -16385, rs1_val == -5
+// opcode: blt, op1:x10; op2:x11; op1val:-0x5; op2val:-0x4001; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x5, -0x4001, 0x40, 3f, x3, 36,0)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:-0x2001; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, -0x2001, 0x4, 1b, x3, 40,0)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x40000000; op2val:-0x1001; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x40000000, -0x1001, 0x80, 3f, x3, 44,0)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x801; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, -0x801, 0x6, 3f, x3, 48,0)
+
+inst_22:
+// rs2_val == -1025, rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0, rs1_val == -1048577
+// opcode: blt, op1:x10; op2:x11; op1val:-0x100001; op2val:-0x401; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x100001, -0x401, 0x8, 1b, x3, 52,0)
+
+inst_23:
+// rs2_val == -513, rs1_val == -67108865
+// opcode: blt, op1:x10; op2:x11; op1val:-0x4000001; op2val:-0x201; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x4000001, -0x201, 0x0, 1b, x3, 56,0)
+
+inst_24:
+// rs2_val == -257, rs1_val == -134217729
+// opcode: blt, op1:x10; op2:x11; op1val:-0x8000001; op2val:-0x101; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x8000001, -0x101, 0x6, 1b, x3, 60,0)
+
+inst_25:
+// rs2_val == -129, rs1_val == 32
+// opcode: blt, op1:x10; op2:x11; op1val:0x20; op2val:-0x81; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x20, -0x81, 0x0, 1b, x3, 64,0)
+
+inst_26:
+// rs2_val == -33, rs1_val == 2
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:-0x21; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, -0x21, 0x20, 3f, x3, 68,0)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x6; op2val:-0x11; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x6, -0x11, 0x100, 3f, x3, 72,0)
+
+inst_28:
+// rs2_val == -9, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x9; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, -0x9, 0x400, 3f, x3, 76,0)
+
+inst_29:
+// rs2_val == -5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:-0x5; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, -0x5, 0x6, 3f, x3, 80,0)
+
+inst_30:
+// rs2_val == -3, rs1_val == -268435457
+// opcode: blt, op1:x10; op2:x11; op1val:-0x10000001; op2val:-0x3; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x10000001, -0x3, 0x400, 3f, x3, 84,0)
+
+inst_31:
+// rs2_val == -2, rs1_val == -129
+// opcode: blt, op1:x10; op2:x11; op1val:-0x81; op2val:-0x2; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x81, -0x2, 0x400, 1b, x3, 88,0)
+
+inst_32:
+// rs1_val == 2147483647, rs2_val == 8
+// opcode: blt, op1:x10; op2:x11; op1val:0x7fffffff; op2val:0x8; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x7fffffff, 0x8, 0x80, 3f, x3, 92,0)
+
+inst_33:
+// rs1_val == -1073741825, rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0, rs2_val == 134217728
+// opcode: blt, op1:x10; op2:x11; op1val:-0x40000001; op2val:0x8000000; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x40000001, 0x8000000, 0x40, 3f, x3, 96,0)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x201; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x20000001, -0x201, 0x4, 3f, x3, 100,0)
+
+inst_35:
+// rs1_val == -33554433, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x2000001; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x2000001, -0x55555555, 0x4, 1b, x3, 104,0)
+
+inst_36:
+// rs1_val == -16777217, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x800001; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x1000001, -0x800001, 0x556, 1b, x3, 108,0)
+
+inst_37:
+// rs1_val == -4194305, rs2_val == 1048576
+// opcode: blt, op1:x10; op2:x11; op1val:-0x400001; op2val:0x100000; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x400001, 0x100000, 0x6, 3f, x3, 112,0)
+
+inst_38:
+// rs1_val == -2097153, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x200001; op2val:0x8000000; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x200001, 0x8000000, 0x0, 3f, x3, 116,0)
+
+inst_39:
+// rs1_val == -524289, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x80001; op2val:-0x200001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x80001, -0x200001, 0x2, 3f, x3, 120,0)
+
+inst_40:
+// rs1_val == -262145, rs2_val == 524288
+// opcode: blt, op1:x10; op2:x11; op1val:-0x40001; op2val:0x80000; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x40001, 0x80000, 0x2, 3f, x3, 124,0)
+
+inst_41:
+// rs1_val == -131073, rs2_val == 131072
+// opcode: blt, op1:x10; op2:x11; op1val:-0x20001; op2val:0x20000; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x20001, 0x20000, 0x400, 3f, x3, 128,0)
+
+inst_42:
+// rs1_val == -32769, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x8001; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x8001, -0xb503, 0x4, 1b, x3, 132,0)
+
+inst_43:
+// rs1_val == -16385, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x4001; op2val:-0x40001; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x4001, -0x40001, 0x2, 3f, x3, 136,0)
+
+inst_44:
+// rs1_val == -8193, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x2001; op2val:-0x40000001; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x2001, -0x40000001, 0x20, 3f, x3, 140,0)
+
+inst_45:
+// rs1_val == -4097, rs2_val == 256
+// opcode: blt, op1:x10; op2:x11; op1val:-0x1001; op2val:0x100; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x1001, 0x100, 0x4, 3f, x3, 144,0)
+
+inst_46:
+// rs1_val == -513, rs2_val == 1431655765
+// opcode: blt, op1:x10; op2:x11; op1val:-0x201; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x201, 0x55555555, 0x8, 1b, x3, 148,0)
+
+inst_47:
+// rs1_val == -257, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x101; op2val:-0x801; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x101, -0x801, 0x2, 3f, x3, 152,0)
+
+inst_48:
+// rs1_val == -65, rs2_val == 2
+// opcode: blt, op1:x10; op2:x11; op1val:-0x41; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x41, 0x2, 0x400, 1b, x3, 156,0)
+
+inst_49:
+// rs1_val == -33, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x21; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x21, 0x55555554, 0x80, 3f, x3, 160,0)
+
+inst_50:
+// rs1_val == -17, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x11; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x11, 0x66666667, 0x10, 3f, x3, 164,0)
+
+inst_51:
+// rs1_val == -3, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x3; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x3, 0x5, 0x100, 3f, x3, 168,0)
+
+inst_52:
+// rs1_val == -2, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x2; op2val:-0x2001; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x2, -0x2001, 0x0, 3f, x3, 172,0)
+
+inst_53:
+// rs2_val == -2147483648, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:-0x80000000; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, -0x80000000, 0x8, 1b, x3, 176,0)
+
+inst_54:
+// rs2_val == 1073741824, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x40000000; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x40000000, 0x2, 3f, x3, 180,0)
+
+inst_55:
+// rs2_val == 536870912, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x20000000; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x20000000, 0x2, 1b, x3, 184,0)
+
+inst_56:
+// rs2_val == 268435456, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x5; op2val:0x10000000; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x5, 0x10000000, 0x6, 3f, x3, 188,0)
+
+inst_57:
+// rs2_val == 67108864, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x200001; op2val:0x4000000; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x200001, 0x4000000, 0x400, 3f, x3, 192,0)
+
+inst_58:
+// rs2_val == 33554432, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x9; op2val:0x2000000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x9, 0x2000000, 0xa, 1b, x3, 196,0)
+
+inst_59:
+// rs2_val == 16777216, rs1_val == 2097152
+// opcode: blt, op1:x10; op2:x11; op1val:0x200000; op2val:0x1000000; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x200000, 0x1000000, 0x100, 3f, x3, 200,0)
+
+inst_60:
+// rs2_val == 8388608, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x3; op2val:0x800000; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x3, 0x800000, 0x100, 3f, x3, 204,0)
+
+inst_61:
+// rs2_val == 4194304, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x400000; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x400000, 0x20, 3f, x3, 208,0)
+
+inst_62:
+// rs2_val == 2097152, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x200000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x200000, 0xa, 1b, x3, 212,0)
+
+inst_63:
+// rs2_val == 262144, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x40000; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x40000, 0x100, 3f, x3, 216,0)
+
+inst_64:
+// rs2_val == 65536, rs1_val == 8192
+// opcode: blt, op1:x10; op2:x11; op1val:0x2000; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2000, 0x10000, 0x6, 3f, x3, 220,0)
+
+inst_65:
+// rs2_val == 32768, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x10000001; op2val:0x8000; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x10000001, 0x8000, 0x2, 3f, x3, 224,0)
+
+inst_66:
+// rs2_val == 16384, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4000; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x4000, 0x400, 3f, x3, 228,0)
+
+inst_67:
+// rs2_val == 8192, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x2000; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x2000, 0x10, 3f, x3, 232,0)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x81; op2val:0x1000; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x81, 0x1000, 0x6, 3f, x3, 236,0)
+
+inst_69:
+// rs2_val == 2048, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x800; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x800, 0x2, 3f, x3, 240,0)
+
+inst_70:
+// rs2_val == 1024, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x8000001; op2val:0x400; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x8000001, 0x400, 0x556, 1b, x3, 244,0)
+
+inst_71:
+// rs2_val == 512, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x200; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x200, 0x80, 3f, x3, 248,0)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x80; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x80, 0x40, 3f, x3, 252,0)
+
+inst_73:
+// rs2_val == 64, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x100001; op2val:0x40; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x100001, 0x40, 0x10, 3f, x3, 256,0)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3fffffff; op2val:0x20; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3fffffff, 0x20, 0x0, 1b, x3, 260,0)
+
+inst_75:
+// rs2_val == 16, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x3; op2val:0x10; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x3, 0x10, 0x100, 3f, x3, 264,0)
+
+inst_76:
+// rs2_val == 4, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x80001; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x80001, 0x4, 0x4, 1b, x3, 268,0)
+
+inst_77:
+// rs2_val == 1, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x200001; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x200001, 0x1, 0x4, 1b, x3, 272,0)
+
+inst_78:
+// rs1_val == -2147483648, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x80000000; op2val:-0x2; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x80000000, -0x2, 0x6, 1b, x3, 276,0)
+
+inst_79:
+// rs1_val == 1073741824, rs2_val == -1431655766
+// opcode: blt, op1:x10; op2:x11; op1val:0x40000000; op2val:-0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x40000000, -0x55555556, 0x20, 3f, x3, 280,0)
+
+inst_80:
+// rs1_val == 536870912, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x20000000; op2val:0x4000; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x20000000, 0x4000, 0x0, 1b, x3, 284,0)
+
+inst_81:
+// rs1_val == 268435456, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x10000000; op2val:-0x41; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x10000000, -0x41, 0xa, 1b, x3, 288,0)
+
+inst_82:
+// rs1_val == 134217728, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x8000000; op2val:0x8000; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x8000000, 0x8000, 0x0, 3f, x3, 292,0)
+
+inst_83:
+// rs1_val == 33554432, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2000000; op2val:0x8000000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2000000, 0x8000000, 0xa, 1b, x3, 296,0)
+
+inst_84:
+// rs1_val == 16777216, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x1000000; op2val:0x40000; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x1000000, 0x40000, 0x8, 3f, x3, 300,0)
+
+inst_85:
+// rs1_val == 8388608, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x800000; op2val:0x40000; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x800000, 0x40000, 0x8, 1b, x3, 304,0)
+
+inst_86:
+// rs1_val == 4194304, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x400000; op2val:-0x5; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x400000, -0x5, 0x556, 1b, x3, 308,0)
+
+inst_87:
+// rs1_val == 524288, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x80000; op2val:-0x80000000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x80000, -0x80000000, 0xa, 1b, x3, 312,0)
+
+inst_88:
+// rs1_val == 262144, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x40000; op2val:0x1; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x40000, 0x1, 0xa, 1b, x3, 316,0)
+
+inst_89:
+// rs1_val == 131072, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x20000; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x20000, 0x33333332, 0x2, 3f, x3, 320,0)
+
+inst_90:
+// rs1_val == 65536, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x10000; op2val:0x2000; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x10000, 0x2000, 0x100, 3f, x3, 324,0)
+
+inst_91:
+// rs1_val == 32768, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x8000; op2val:0x4000; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x8000, 0x4000, 0x40, 3f, x3, 328,0)
+
+inst_92:
+// rs1_val == 16384, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4000; op2val:-0x81; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4000, -0x81, 0x4, 3f, x3, 332,0)
+
+inst_93:
+// rs1_val == 4096, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x1000; op2val:0x2000000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x1000, 0x2000000, 0xa, 1b, x3, 336,0)
+
+inst_94:
+// rs1_val == 512, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x200; op2val:-0x201; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x200, -0x201, 0x4, 1b, x3, 340,0)
+
+inst_95:
+// rs1_val == 256, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x100; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x100, 0x6, 0x556, 1b, x3, 344,0)
+
+inst_96:
+// rs1_val == 128, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x80; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x80, -0xb503, 0x400, 1b, x3, 348,0)
+
+inst_97:
+// rs1_val == 64, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x40; op2val:0x10; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x40, 0x10, 0x20, 3f, x3, 352,0)
+
+inst_98:
+// rs1_val == 16, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x10; op2val:-0x4001; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x10, -0x4001, 0x200, 3f, x3, 356,0)
+
+inst_99:
+// rs1_val == 8, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x8; op2val:0x40000; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x8, 0x40000, 0x2, 3f, x3, 360,0)
+
+inst_100:
+// rs1_val == 1, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x1; op2val:0x2000000; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x1, 0x2000000, 0xa, 1b, x3, 364,0)
+
+inst_101:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0xb505, 0x0, 1b, x3, 368,0)
+
+inst_102:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, -0xb503, 0x200, 3f, x3, 372,0)
+
+inst_103:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x66666667, 0x8, 3f, x3, 376,0)
+
+inst_104:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x33333334, 0x200, 3f, x3, 380,0)
+
+inst_105:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x6, 0x6, 1b, x3, 384,0)
+
+inst_106:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, -0x55555555, 0x80, 3f, x3, 388,0)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x55555556, 0x0, 3f, x3, 392,0)
+
+inst_108:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x4, 0xa, 1b, x3, 396,0)
+
+inst_109:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0xb503, 0x0, 1b, x3, 400,0)
+
+inst_110:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x0, 0x4, 3f, x3, 404,0)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x66666665, 0x20, 3f, x3, 408,0)
+
+inst_112:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x33333332, 0x400, 1b, x3, 412,0)
+
+inst_113:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x55555554, 0x40, 3f, x3, 416,0)
+
+inst_114:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x2, 0x8, 3f, x3, 420,0)
+
+inst_115:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0xb504, 0x80, 3f, x3, 424,0)
+
+inst_116:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, -0xb504, 0x6, 1b, x3, 428,0)
+
+inst_117:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x66666666, 0x40, 3f, x3, 432,0)
+
+inst_118:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x33333333, 0x8, 1b, x3, 436,0)
+
+inst_119:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x5, 0x4, 1b, x3, 440,0)
+
+inst_120:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, -0x55555556, 0x2, 3f, x3, 444,0)
+
+inst_121:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x55555555, 0x6, 3f, x3, 448,0)
+
+inst_122:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb505, 0x3, 0x400, 1b, x3, 452,0)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0xb505, 0x20, 3f, x3, 456,0)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==-46339, rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, -0xb503, 0x4, 3f, x3, 460,0)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x66666667, 0x556, 1b, x3, 464,0)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x33333334, 0x8, 3f, x3, 468,0)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x6, 0x556, 1b, x3, 472,0)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, -0x55555555, 0x2, 1b, x3, 476,0)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x55555556, 0x4, 1b, x3, 480,0)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x4, 0x20, 3f, x3, 484,0)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0xb503, 0x80, 3f, x3, 488,0)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x0, 0x8, 1b, x3, 492,0)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x66666665, 0x20, 3f, x3, 496,0)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x33333332, 0x0, 3f, x3, 500,0)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x55555554, 0x200, 3f, x3, 504,0)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x2; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x2, 0xa, 1b, x3, 508,0)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0xb504, 0x2, 3f, x3, 512,0)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, -0xb504, 0x8, 1b, x3, 516,0)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x66666666, 0x400, 1b, x3, 520,0)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x33333333, 0xa, 1b, x3, 524,0)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x5, 0x0, 1b, x3, 528,0)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, -0x55555556, 0x100, 3f, x3, 532,0)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x55555555, 0x4, 1b, x3, 536,0)
+
+inst_144:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb503; op2val:0x3; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb503, 0x3, 0xa, 1b, x3, 540,0)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0xb505, 0x0, 3f, x3, 544,0)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, -0xb503, 0x8, 3f, x3, 548,0)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x66666667, 0x556, 1b, x3, 552,0)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x33333334, 0x0, 3f, x3, 556,0)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x6, 0xa, 1b, x3, 560,0)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, -0x55555555, 0x40, 3f, x3, 564,0)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x55555556, 0x0, 1b, x3, 568,0)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x4, 0x0, 3f, x3, 572,0)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0xb503, 0x4, 3f, x3, 576,0)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x0, 0x400, 3f, x3, 580,0)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x66666665, 0x4, 1b, x3, 584,0)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x33333332, 0x2, 1b, x3, 588,0)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x55555554, 0x40, 3f, x3, 592,0)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x2, 0x10, 3f, x3, 596,0)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0xb504, 0x400, 3f, x3, 600,0)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, -0xb504, 0x6, 1b, x3, 604,0)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x66666666, 0x100, 3f, x3, 608,0)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x33333333, 0x4, 3f, x3, 612,0)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x5, 0x6, 3f, x3, 616,0)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, -0x55555556, 0x80, 3f, x3, 620,0)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x55555555, 0x2, 1b, x3, 624,0)
+
+inst_166:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666667, 0x3, 0x0, 3f, x3, 628,0)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0xb505, 0x0, 1b, x3, 632,0)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, -0xb503, 0x4, 3f, x3, 636,0)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x66666667, 0x6, 3f, x3, 640,0)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x33333334, 0x20, 3f, x3, 644,0)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x6, 0x0, 1b, x3, 648,0)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, -0x55555555, 0x400, 3f, x3, 652,0)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x55555556, 0x6, 3f, x3, 656,0)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x4, 0x8, 1b, x3, 660,0)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0xb503, 0x2, 3f, x3, 664,0)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x0, 0x6, 3f, x3, 668,0)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x66666665, 0x0, 1b, x3, 672,0)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x33333332, 0x2, 1b, x3, 676,0)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x55555554, 0x6, 3f, x3, 680,0)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x2, 0x200, 3f, x3, 684,0)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0xb504, 0x4, 3f, x3, 688,0)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, -0xb504, 0x20, 3f, x3, 692,0)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x66666666, 0x2, 3f, x3, 696,0)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x33333333, 0x4, 1b, x3, 700,0)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x5, 0x6, 1b, x3, 704,0)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, -0x55555556, 0x4, 1b, x3, 708,0)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x55555555, 0x80, 3f, x3, 712,0)
+
+inst_188:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333334, 0x3, 0x40, 3f, x3, 716,0)
+
+inst_189:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0xb505, 0x556, 1b, x3, 720,0)
+
+inst_190:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, -0xb503, 0x80, 3f, x3, 724,0)
+
+inst_191:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x66666667, 0x2, 3f, x3, 728,0)
+
+inst_192:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x33333334, 0x400, 3f, x3, 732,0)
+
+inst_193:
+// rs1_val==6 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x6, 0x200, 3f, x3, 736,0)
+
+inst_194:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, -0x55555555, 0x0, 1b, x3, 740,0)
+
+inst_195:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x55555556, 0x40, 3f, x3, 744,0)
+
+inst_196:
+// rs1_val==6 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x4, 0x4, 3f, x3, 748,0)
+
+inst_197:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0xb503, 0x2, 3f, x3, 752,0)
+
+inst_198:
+// rs1_val==6 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x0, 0x6, 1b, x3, 756,0)
+
+inst_199:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x66666665, 0xa, 1b, x3, 760,0)
+
+inst_200:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x33333332, 0x200, 3f, x3, 764,0)
+
+inst_201:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x55555554, 0x20, 3f, x3, 768,0)
+
+inst_202:
+// rs1_val==6 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x2, 0x0, 3f, x3, 772,0)
+
+inst_203:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0xb504, 0x40, 3f, x3, 776,0)
+
+inst_204:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:-0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, -0xb504, 0x200, 3f, x3, 780,0)
+
+inst_205:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x66666666, 0x40, 3f, x3, 784,0)
+
+inst_206:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x33333333, 0xa, 1b, x3, 788,0)
+
+inst_207:
+// rs1_val==6 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x5, 0x200, 3f, x3, 792,0)
+
+inst_208:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, -0x55555556, 0x0, 3f, x3, 796,0)
+
+inst_209:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x55555555, 0x2, 1b, x3, 800,0)
+
+inst_210:
+// rs1_val==6 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x6, 0x3, 0x40, 3f, x3, 804,0)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0xb505, 0x2, 3f, x3, 808,0)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, -0xb503, 0x2, 1b, x3, 812,0)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x66666667, 0x6, 1b, x3, 816,0)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x33333334, 0x556, 1b, x3, 820,0)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x6, 0x10, 3f, x3, 824,0)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, -0x55555555, 0x20, 3f, x3, 828,0)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x55555556, 0x40, 3f, x3, 832,0)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x4, 0x8, 1b, x3, 836,0)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0xb503, 0x0, 1b, x3, 840,0)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x0, 0x0, 1b, x3, 844,0)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x66666665, 0x20, 3f, x3, 848,0)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x33333332, 0x556, 1b, x3, 852,0)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x55555554, 0x40, 3f, x3, 856,0)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x2, 0x400, 1b, x3, 860,0)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0xb504, 0x556, 1b, x3, 864,0)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, -0xb504, 0x10, 3f, x3, 868,0)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x66666666, 0x6, 3f, x3, 872,0)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x33333333, 0x400, 3f, x3, 876,0)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x5, 0x80, 3f, x3, 880,0)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, -0x55555556, 0x4, 3f, x3, 884,0)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x55555555, 0x20, 3f, x3, 888,0)
+
+inst_232:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555555, 0x3, 0x4, 1b, x3, 892,0)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0xb505, 0x80, 3f, x3, 896,0)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, -0xb503, 0x0, 3f, x3, 900,0)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x66666667, 0x10, 3f, x3, 904,0)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x33333334, 0x40, 3f, x3, 908,0)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x6, 0x556, 1b, x3, 912,0)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, -0x55555555, 0x10, 3f, x3, 916,0)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x55555556, 0x0, 1b, x3, 920,0)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x4, 0x6, 3f, x3, 924,0)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0xb503, 0x20, 3f, x3, 928,0)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x0, 0x556, 1b, x3, 932,0)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x66666665, 0x2, 3f, x3, 936,0)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x33333332, 0x0, 1b, x3, 940,0)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x55555554, 0x8, 3f, x3, 944,0)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x2, 0xa, 1b, x3, 948,0)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0xb504, 0x200, 3f, x3, 952,0)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, -0xb504, 0x40, 3f, x3, 956,0)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x66666666, 0x4, 3f, x3, 960,0)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x33333333, 0x4, 3f, x3, 964,0)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x5, 0x556, 1b, x3, 968,0)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, -0x55555556, 0x2, 3f, x3, 972,0)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x55555555, 0x100, 3f, x3, 976,0)
+
+inst_254:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555556, 0x3, 0x2, 3f, x3, 980,0)
+
+inst_255:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0xb505, 0x8, 1b, x3, 984,0)
+
+inst_256:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, -0xb503, 0x0, 1b, x3, 988,0)
+
+inst_257:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x66666667, 0x20, 3f, x3, 992,0)
+
+inst_258:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x33333334, 0x6, 1b, x3, 996,0)
+
+inst_259:
+// rs1_val==4 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x6, 0x2, 1b, x3, 1000,0)
+
+inst_260:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, -0x55555555, 0x100, 3f, x3, 1004,0)
+
+inst_261:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x55555556, 0x4, 3f, x3, 1008,0)
+
+inst_262:
+// rs1_val==4 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x4, 0x400, 1b, x3, 1012,0)
+
+inst_263:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0xb503, 0x0, 3f, x3, 1016,0)
+
+inst_264:
+// rs1_val==4 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x0, 0x2, 1b, x3, 1020,0)
+
+inst_265:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x66666665, 0x4, 3f, x3, 1024,0)
+
+inst_266:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x33333332, 0x100, 3f, x3, 1028,0)
+
+inst_267:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x55555554, 0x2, 1b, x3, 1032,0)
+
+inst_268:
+// rs1_val==4 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x2, 0x6, 1b, x3, 1036,0)
+
+inst_269:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0xb504, 0x20, 3f, x3, 1040,0)
+
+inst_270:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, -0xb504, 0x400, 1b, x3, 1044,0)
+
+inst_271:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x66666666, 0x10, 3f, x3, 1048,0)
+
+inst_272:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x33333333, 0x2, 3f, x3, 1052,0)
+
+inst_273:
+// rs1_val==4 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x5, 0x40, 3f, x3, 1056,0)
+
+inst_274:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, -0x55555556, 0x2, 3f, x3, 1060,0)
+
+inst_275:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x55555555, 0x8, 1b, x3, 1064,0)
+
+inst_276:
+// rs1_val==4 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x4, 0x3, 0x556, 1b, x3, 1068,0)
+
+inst_277:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0xb505, 0x2, 3f, x3, 1072,0)
+
+inst_278:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, -0xb503, 0x6, 3f, x3, 1076,0)
+
+inst_279:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x66666667, 0x400, 1b, x3, 1080,0)
+
+inst_280:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x33333334, 0x400, 3f, x3, 1084,0)
+
+inst_281:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x6, 0x100, 3f, x3, 1088,0)
+
+inst_282:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, -0x55555555, 0x20, 3f, x3, 1092,0)
+
+inst_283:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x55555556, 0x200, 3f, x3, 1096,0)
+
+inst_284:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x4, 0x100, 3f, x3, 1100,0)
+
+inst_285:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0xb503, 0x400, 3f, x3, 1104,0)
+
+inst_286:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x0, 0x200, 3f, x3, 1108,0)
+
+inst_287:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x66666665, 0x4, 3f, x3, 1112,0)
+
+inst_288:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x33333332, 0x4, 1b, x3, 1116,0)
+
+inst_289:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x55555554, 0x40, 3f, x3, 1120,0)
+
+inst_290:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x2, 0x80, 3f, x3, 1124,0)
+
+inst_291:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0xb504, 0x8, 3f, x3, 1128,0)
+
+inst_292:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, -0xb504, 0x10, 3f, x3, 1132,0)
+
+inst_293:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x66666666, 0x400, 3f, x3, 1136,0)
+
+inst_294:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x33333333, 0x200, 3f, x3, 1140,0)
+
+inst_295:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x5, 0x200, 3f, x3, 1144,0)
+
+inst_296:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, -0x55555556, 0x2, 1b, x3, 1148,0)
+
+inst_297:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x55555555, 0x400, 1b, x3, 1152,0)
+
+inst_298:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb503, 0x3, 0x2, 3f, x3, 1156,0)
+
+inst_299:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0xb505, 0x0, 3f, x3, 1160,0)
+
+inst_300:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, -0xb503, 0x4, 1b, x3, 1164,0)
+
+inst_301:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x66666667, 0x6, 1b, x3, 1168,0)
+
+inst_302:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x33333334, 0x80, 3f, x3, 1172,0)
+
+inst_303:
+// rs1_val==0 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x6, 0x0, 1b, x3, 1176,0)
+
+inst_304:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, -0x55555555, 0x0, 1b, x3, 1180,0)
+
+inst_305:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x55555556, 0x8, 1b, x3, 1184,0)
+
+inst_306:
+// rs1_val==0 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x4, 0x80, 3f, x3, 1188,0)
+
+inst_307:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0xb503, 0x8, 3f, x3, 1192,0)
+
+inst_308:
+// rs1_val==0 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x0, 0x4, 1b, x3, 1196,0)
+
+inst_309:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x66666665, 0x10, 3f, x3, 1200,0)
+
+inst_310:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x33333332, 0x0, 3f, x3, 1204,0)
+
+inst_311:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x55555554, 0x40, 3f, x3, 1208,0)
+
+inst_312:
+// rs1_val==0 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x2, 0x20, 3f, x3, 1212,0)
+
+inst_313:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0xb504, 0x100, 3f, x3, 1216,0)
+
+inst_314:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:-0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, -0xb504, 0x556, 1b, x3, 1220,0)
+
+inst_315:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x66666666, 0x8, 1b, x3, 1224,0)
+
+inst_316:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x33333333, 0x4, 3f, x3, 1228,0)
+
+inst_317:
+// rs1_val==0 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x5, 0x20, 3f, x3, 1232,0)
+
+inst_318:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, -0x55555556, 0x6, 3f, x3, 1236,0)
+
+inst_319:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x55555555, 0x4, 1b, x3, 1240,0)
+
+inst_320:
+// rs1_val==0 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x0, 0x3, 0x400, 3f, x3, 1244,0)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0xb505, 0x100, 3f, x3, 1248,0)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, -0xb503, 0x400, 1b, x3, 1252,0)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x66666667, 0x2, 3f, x3, 1256,0)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x33333334, 0x400, 3f, x3, 1260,0)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x6, 0x10, 3f, x3, 1264,0)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, -0x55555555, 0x4, 1b, x3, 1268,0)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x55555556, 0xa, 1b, x3, 1272,0)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x4, 0x4, 3f, x3, 1276,0)
+
+inst_329:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0xb503, 0x400, 1b, x3, 1280,0)
+
+inst_330:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x0, 0x2, 3f, x3, 1284,0)
+
+inst_331:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x66666665, 0x40, 3f, x3, 1288,0)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x0, 0x0, 3f, x3, 1292,0)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x66666665, 0x4, 1b, x3, 1296,0)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x33333332, 0x100, 3f, x3, 1300,0)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x55555554, 0x400, 3f, x3, 1304,0)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x2, 0x10, 3f, x3, 1308,0)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0xb504, 0x400, 1b, x3, 1312,0)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, -0xb504, 0x80, 3f, x3, 1316,0)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x66666666, 0x4, 3f, x3, 1320,0)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x33333333, 0xa, 1b, x3, 1324,0)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x5, 0x6, 1b, x3, 1328,0)
+
+inst_342:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, -0x55555556, 0x200, 3f, x3, 1332,0)
+
+inst_343:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x55555555, 0x2, 3f, x3, 1336,0)
+
+inst_344:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x3, 0x400, 3f, x3, 1340,0)
+
+inst_345:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0xb505, 0x4, 1b, x3, 1344,0)
+
+inst_346:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, -0xb503, 0x2, 1b, x3, 1348,0)
+
+inst_347:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x66666667, 0x4, 3f, x3, 1352,0)
+
+inst_348:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x33333334, 0x4, 1b, x3, 1356,0)
+
+inst_349:
+// rs1_val==5 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x6, 0x2, 1b, x3, 1360,0)
+
+inst_350:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, -0x55555555, 0x400, 3f, x3, 1364,0)
+
+inst_351:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x55555556, 0x6, 1b, x3, 1368,0)
+
+inst_352:
+// rs1_val==5 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x4, 0x6, 3f, x3, 1372,0)
+
+inst_353:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0xb503, 0x8, 3f, x3, 1376,0)
+
+inst_354:
+// rs1_val==5 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x0, 0x400, 3f, x3, 1380,0)
+
+inst_355:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x66666665, 0x400, 3f, x3, 1384,0)
+
+inst_356:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x33333332, 0x0, 3f, x3, 1388,0)
+
+inst_357:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x55555554, 0x2, 1b, x3, 1392,0)
+
+inst_358:
+// rs1_val==5 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x2, 0x20, 3f, x3, 1396,0)
+
+inst_359:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0xb504, 0x40, 3f, x3, 1400,0)
+
+inst_360:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:-0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, -0xb504, 0x4, 1b, x3, 1404,0)
+
+inst_361:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x66666666, 0x0, 3f, x3, 1408,0)
+
+inst_362:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x33333333, 0x556, 1b, x3, 1412,0)
+
+inst_363:
+// rs1_val==5 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x5, 0x200, 3f, x3, 1416,0)
+
+inst_364:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, -0x55555556, 0x400, 3f, x3, 1420,0)
+
+inst_365:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x55555555, 0x400, 1b, x3, 1424,0)
+
+inst_366:
+// rs1_val==5 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x5, 0x3, 0x4, 3f, x3, 1428,0)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0xb505, 0x0, 1b, x3, 1432,0)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, -0xb503, 0x8, 1b, x3, 1436,0)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x66666667, 0x6, 1b, x3, 1440,0)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x33333334, 0xa, 1b, x3, 1444,0)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x6, 0x4, 3f, x3, 1448,0)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, -0x55555555, 0x200, 3f, x3, 1452,0)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x55555556, 0x80, 3f, x3, 1456,0)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x4, 0x6, 1b, x3, 1460,0)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0xb503, 0x0, 1b, x3, 1464,0)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x0, 0xa, 1b, x3, 1468,0)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x66666665, 0x556, 1b, x3, 1472,0)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x33333332, 0x20, 3f, x3, 1476,0)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x55555554, 0x8, 1b, x3, 1480,0)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x2, 0x6, 3f, x3, 1484,0)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0xb504, 0x8, 1b, x3, 1488,0)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, -0xb504, 0x556, 1b, x3, 1492,0)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x66666666, 0x556, 1b, x3, 1496,0)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x33333333, 0x20, 3f, x3, 1500,0)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x5, 0x0, 3f, x3, 1504,0)
+
+inst_386:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, -0x55555556, 0x6, 3f, x3, 1508,0)
+
+inst_387:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x55555555, 0x2, 1b, x3, 1512,0)
+
+inst_388:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0x55555556, 0x3, 0xa, 1b, x3, 1516,0)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0xb505, 0x4, 3f, x3, 1520,0)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, -0xb503, 0x100, 3f, x3, 1524,0)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x66666667, 0x40, 3f, x3, 1528,0)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x33333334, 0x6, 3f, x3, 1532,0)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x6, 0x4, 1b, x3, 1536,0)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, -0x55555555, 0x4, 1b, x3, 1540,0)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x55555556, 0x8, 1b, x3, 1544,0)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x4, 0x10, 3f, x3, 1548,0)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0xb503, 0x400, 1b, x3, 1552,0)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x0, 0x556, 1b, x3, 1556,0)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x66666665, 0x80, 3f, x3, 1560,0)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x33333332, 0x10, 3f, x3, 1564,0)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x55555554, 0x200, 3f, x3, 1568,0)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x2, 0x0, 3f, x3, 1572,0)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0xb504, 0x10, 3f, x3, 1576,0)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, -0xb504, 0x8, 3f, x3, 1580,0)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x66666666, 0x200, 3f, x3, 1584,0)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x33333333, 0x400, 3f, x3, 1588,0)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x5, 0x8, 1b, x3, 1592,0)
+
+inst_408:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, -0x55555556, 0x200, 3f, x3, 1596,0)
+
+inst_409:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x55555555, 0x4, 3f, x3, 1600,0)
+
+inst_410:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555555, 0x3, 0x400, 3f, x3, 1604,0)
+
+inst_411:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0xb505, 0x6, 3f, x3, 1608,0)
+
+inst_412:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:-0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, -0xb503, 0xa, 1b, x3, 1612,0)
+
+inst_413:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x66666667, 0x20, 3f, x3, 1616,0)
+
+inst_414:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x33333334, 0x8, 1b, x3, 1620,0)
+
+inst_415:
+// rs1_val==3 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x6, 0x100, 3f, x3, 1624,0)
+
+inst_416:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, -0x55555555, 0x400, 1b, x3, 1628,0)
+
+inst_417:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x55555556, 0x10, 3f, x3, 1632,0)
+
+inst_418:
+// rs1_val==3 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x4, 0x8, 3f, x3, 1636,0)
+
+inst_419:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0xb503, 0x4, 3f, x3, 1640,0)
+
+inst_420:
+// rs1_val==3 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x0, 0x2, 1b, x3, 1644,0)
+
+inst_421:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x66666665, 0x400, 1b, x3, 1648,0)
+
+inst_422:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x33333332, 0x200, 3f, x3, 1652,0)
+
+inst_423:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x55555554, 0x0, 3f, x3, 1656,0)
+
+inst_424:
+// rs1_val==3 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x2, 0x200, 3f, x3, 1660,0)
+
+inst_425:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0xb504, 0x556, 1b, x3, 1664,0)
+
+inst_426:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:-0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, -0xb504, 0x40, 3f, x3, 1668,0)
+
+inst_427:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x66666666, 0x4, 1b, x3, 1672,0)
+
+inst_428:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x33333333, 0x0, 1b, x3, 1676,0)
+
+inst_429:
+// rs1_val==3 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x5, 0x4, 3f, x3, 1680,0)
+
+inst_430:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, -0x55555556, 0xa, 1b, x3, 1684,0)
+
+inst_431:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x55555555, 0x556, 1b, x3, 1688,0)
+
+inst_432:
+// rs1_val==3 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x3, 0x3, 0x6, 3f, x3, 1692,0)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x33333332, 0x0, 1b, x3, 1696,0)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x55555554, 0x8, 3f, x3, 1700,0)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x2, 0x8, 1b, x3, 1704,0)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0xb504, 0x20, 3f, x3, 1708,0)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, -0xb504, 0x6, 1b, x3, 1712,0)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x66666666, 0x400, 1b, x3, 1716,0)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x33333333, 0x8, 1b, x3, 1720,0)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x5, 0x8, 1b, x3, 1724,0)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, -0x55555556, 0x20, 3f, x3, 1728,0)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x55555555, 0x6, 1b, x3, 1732,0)
+
+inst_443:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666665, 0x3, 0x0, 3f, x3, 1736,0)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0xb505, 0x8, 1b, x3, 1740,0)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, -0xb503, 0x20, 3f, x3, 1744,0)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x66666667, 0x400, 1b, x3, 1748,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x33333334, 0x0, 1b, x3, 1752,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x6, 0xa, 1b, x3, 1756,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, -0x55555555, 0x80, 3f, x3, 1760,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x55555556, 0x100, 3f, x3, 1764,0)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x4, 0x4, 1b, x3, 1768,0)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0xb503, 0x0, 1b, x3, 1772,0)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x0, 0x8, 3f, x3, 1776,0)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x66666665, 0x400, 3f, x3, 1780,0)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x33333332, 0x8, 3f, x3, 1784,0)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x55555554, 0x8, 3f, x3, 1788,0)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x2, 0x4, 1b, x3, 1792,0)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0xb504, 0x2, 3f, x3, 1796,0)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, -0xb504, 0x10, 3f, x3, 1800,0)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x66666666, 0x200, 3f, x3, 1804,0)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x33333333, 0x6, 3f, x3, 1808,0)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x5, 0x400, 1b, x3, 1812,0)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, -0x55555556, 0xa, 1b, x3, 1816,0)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x55555555, 0x6, 3f, x3, 1820,0)
+
+inst_465:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333332, 0x3, 0x6, 1b, x3, 1824,0)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0xb505, 0x40, 3f, x3, 1828,0)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, -0xb503, 0x40, 3f, x3, 1832,0)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x66666667, 0x200, 3f, x3, 1836,0)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x33333334, 0x2, 1b, x3, 1840,0)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x6, 0x400, 1b, x3, 1844,0)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, -0x55555555, 0x400, 1b, x3, 1848,0)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x55555556, 0x40, 3f, x3, 1852,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x4, 0x0, 3f, x3, 1856,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0xb503, 0x0, 1b, x3, 1860,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x0, 0x10, 3f, x3, 1864,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x66666665, 0x20, 3f, x3, 1868,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x33333332, 0x40, 3f, x3, 1872,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x55555554, 0x400, 1b, x3, 1876,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x2, 0x200, 3f, x3, 1880,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0xb504, 0x2, 1b, x3, 1884,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, -0xb504, 0x0, 3f, x3, 1888,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x66666666, 0x4, 1b, x3, 1892,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x33333333, 0x8, 3f, x3, 1896,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x5, 0x100, 3f, x3, 1900,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, -0x55555556, 0x0, 1b, x3, 1904,0)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x55555555, 0x2, 1b, x3, 1908,0)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x55555554, 0x3, 0x20, 3f, x3, 1912,0)
+
+inst_488:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0xb505, 0x2, 3f, x3, 1916,0)
+
+inst_489:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, -0xb503, 0x2, 3f, x3, 1920,0)
+
+inst_490:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x66666667, 0x4, 1b, x3, 1924,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x33333334, 0x10, 3f, x3, 1928,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x6, 0xa, 1b, x3, 1932,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, -0x55555555, 0x4, 3f, x3, 1936,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x55555556, 0x2, 1b, x3, 1940,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x4, 0x8, 1b, x3, 1944,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0xb503, 0x4, 1b, x3, 1948,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x0, 0x6, 1b, x3, 1952,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x66666665, 0x40, 3f, x3, 1956,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x33333332, 0x400, 3f, x3, 1960,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x55555554, 0x40, 3f, x3, 1964,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x2, 0x2, 3f, x3, 1968,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0xb504, 0x4, 1b, x3, 1972,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, -0xb504, 0x8, 3f, x3, 1976,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x66666666, 0x200, 3f, x3, 1980,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x33333333, 0x0, 3f, x3, 1984,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x5, 0x8, 1b, x3, 1988,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, -0x55555556, 0x40, 3f, x3, 1992,0)
+
+inst_508:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x55555555, 0x2, 3f, x3, 1996,0)
+
+inst_509:
+// rs1_val==2 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x2, 0x3, 0x100, 3f, x3, 2000,0)
+
+inst_510:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0xb505, 0x4, 3f, x3, 2004,0)
+
+inst_511:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, -0xb503, 0x100, 3f, x3, 2008,0)
+
+inst_512:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x66666667, 0x8, 1b, x3, 2012,0)
+
+inst_513:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x33333334, 0x6, 1b, x3, 2016,0)
+
+inst_514:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x6, 0x2, 1b, x3, 2020,0)
+
+inst_515:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, -0x55555555, 0x6, 3f, x3, 2024,0)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x55555556, 0x8, 1b, x3, 2028,0)
+
+inst_517:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x4, 0x6, 1b, x3, 2032,0)
+
+inst_518:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0xb503, 0x6, 1b, x3, 2036,0)
+
+inst_519:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x0, 0x40, 3f, x3, 2040,0)
+
+inst_520:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x66666665, 0x4, 3f, x3, 2044,0)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_521:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x33333332, 0xa, 1b, x3, 0,0)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x55555554, 0x556, 1b, x3, 4,0)
+
+inst_523:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x2, 0x8, 1b, x3, 8,0)
+
+inst_524:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0xb504, 0xa, 1b, x3, 12,0)
+
+inst_525:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, -0xb504, 0x0, 1b, x3, 16,0)
+
+inst_526:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x66666666, 0x6, 1b, x3, 20,0)
+
+inst_527:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x33333333, 0xa, 1b, x3, 24,0)
+
+inst_528:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x5, 0x80, 3f, x3, 28,0)
+
+inst_529:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, -0x55555556, 0x80, 3f, x3, 32,0)
+
+inst_530:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x55555555, 0x6, 3f, x3, 36,0)
+
+inst_531:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0xb504, 0x3, 0x80, 3f, x3, 40,0)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0xb505, 0x0, 1b, x3, 44,0)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, -0xb503, 0x10, 3f, x3, 48,0)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x66666667, 0x8, 3f, x3, 52,0)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x33333334, 0xa, 1b, x3, 56,0)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x6; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x6, 0xa, 1b, x3, 60,0)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, -0x55555555, 0x0, 3f, x3, 64,0)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x55555556, 0x400, 3f, x3, 68,0)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x4; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x4, 0x80, 3f, x3, 72,0)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0xb503, 0x8, 3f, x3, 76,0)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x0, 0x0, 3f, x3, 80,0)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x66666665, 0x20, 3f, x3, 84,0)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x33333332, 0x400, 1b, x3, 88,0)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x55555554, 0x2, 3f, x3, 92,0)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x2, 0x100, 3f, x3, 96,0)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0xb504, 0x2, 1b, x3, 100,0)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, -0xb504, 0x200, 3f, x3, 104,0)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x66666666, 0x4, 3f, x3, 108,0)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x33333333, 0x556, 1b, x3, 112,0)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x5, 0x40, 3f, x3, 116,0)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, -0x55555556, 0x0, 1b, x3, 120,0)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x55555555, 0x10, 3f, x3, 124,0)
+
+inst_553:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:-0xb504; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, -0xb504, 0x3, 0x8, 1b, x3, 128,0)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0xb505, 0x20, 3f, x3, 132,0)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, -0xb503, 0xa, 1b, x3, 136,0)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x66666667, 0x400, 1b, x3, 140,0)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x33333334, 0x200, 3f, x3, 144,0)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x6, 0x0, 1b, x3, 148,0)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, -0x55555555, 0x40, 3f, x3, 152,0)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x55555556, 0x4, 1b, x3, 156,0)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x4, 0x400, 3f, x3, 160,0)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0xb503, 0x80, 3f, x3, 164,0)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x0, 0x20, 3f, x3, 168,0)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x66666665, 0x4, 1b, x3, 172,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x33333332, 0x10, 3f, x3, 176,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x55555554, 0x4, 1b, x3, 180,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x2, 0x2, 3f, x3, 184,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0xb504, 0x400, 1b, x3, 188,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, -0xb504, 0x400, 1b, x3, 192,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x66666666, 0x6, 3f, x3, 196,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x33333333, 0x8, 3f, x3, 200,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x5, 0x556, 1b, x3, 204,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, -0x55555556, 0x8, 1b, x3, 208,0)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x55555555, 0x0, 1b, x3, 212,0)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x66666666, 0x3, 0x8, 1b, x3, 216,0)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0xb505, 0x10, 3f, x3, 220,0)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, -0xb503, 0x80, 3f, x3, 224,0)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x66666667, 0x556, 1b, x3, 228,0)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x33333334, 0x2, 1b, x3, 232,0)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x6, 0x2, 1b, x3, 236,0)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, -0x55555555, 0x400, 1b, x3, 240,0)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x55555556, 0x6, 3f, x3, 244,0)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0x4, 0x20, 3f, x3, 248,0)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: blt, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x33333333, 0xb503, 0x80, 3f, x3, 252,0)
+
+inst_585:
+// rs2_val == -268435457, rs1_val == 1048576
+// opcode: blt, op1:x10; op2:x11; op1val:0x100000; op2val:-0x10000001; immval:0x200; align:0
+TEST_BRANCH_OP(blt, x1, x10, x11, 0x100000, -0x10000001, 0x200, 3f, x3, 256,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 65*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S
new file mode 100644
index 000000000..e6e5b69ac
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S
@@ -0,0 +1,3716 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the bltu instruction of the RISC-V E extension for the bltu covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",bltu)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 == rs2, rs1==x4, rs2==x4, rs1_val > 0 and rs2_val > 0, rs1_val == 3758096383, rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 , rs2_val == 512
+// opcode: bltu, op1:x4; op2:x4; op1val:0xdfffffff; op2val:0xdfffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x7, x4, x4, 0xdfffffff, 0xdfffffff, 0x6, 3f, x1, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x5, rs2==x6, rs2_val == 2147483647, rs1_val == 268435456, rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 
+// opcode: bltu, op1:x5; op2:x6; op1val:0x10000000; op2val:0x7fffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x7, x5, x6, 0x10000000, 0x7fffffff, 0x6, 3f, x1, 4,0)
+
+inst_2:
+// rs1==x15, rs2==x8, rs2_val == 3221225471, rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 
+// opcode: bltu, op1:x15; op2:x8; op1val:0xdfffffff; op2val:0xbfffffff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x7, x15, x8, 0xdfffffff, 0xbfffffff, 0x8, 1b, x1, 8,0)
+
+inst_3:
+// rs1==x13, rs2==x15, rs2_val == 3758096383, rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 
+// opcode: bltu, op1:x13; op2:x15; op1val:0x3; op2val:0xdfffffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x7, x13, x15, 0x3, 0xdfffffff, 0x0, 1b, x1, 12,0)
+
+inst_4:
+// rs1==x2, rs2==x14, rs2_val == 4026531839, rs1_val == 134217728
+// opcode: bltu, op1:x2; op2:x14; op1val:0x8000000; op2val:0xefffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x7, x2, x14, 0x8000000, 0xefffffff, 0x6, 1b, x1, 16,0)
+
+inst_5:
+// rs1==x9, rs2==x11, rs2_val == 4160749567, 
+// opcode: bltu, op1:x9; op2:x11; op1val:0x66666665; op2val:0xf7ffffff; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x7, x9, x11, 0x66666665, 0xf7ffffff, 0x4, 1b, x1, 20,0)
+
+inst_6:
+// rs1==x3, rs2==x2, rs2_val == 4227858431, 
+// opcode: bltu, op1:x3; op2:x2; op1val:0xffffffff; op2val:0xfbffffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x7, x3, x2, 0xffffffff, 0xfbffffff, 0x0, 1b, x1, 24,0)
+
+inst_7:
+// rs1==x7, rs2==x5, rs2_val == 4261412863, rs1_val == 2
+// opcode: bltu, op1:x7; op2:x5; op1val:0x2; op2val:0xfdffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x4, x7, x5, 0x2, 0xfdffffff, 0x6, 3f, x1, 28,0)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_8:
+// rs1==x6, rs2==x12, rs2_val == 4278190079, 
+// opcode: bltu, op1:x6; op2:x12; op1val:0x66666665; op2val:0xfeffffff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x4, x6, x12, 0x66666665, 0xfeffffff, 0x8, 3f, x2, 0,0)
+
+inst_9:
+// rs1==x1, rs2==x9, rs2_val == 4286578687, rs1_val == 4294967167
+// opcode: bltu, op1:x1; op2:x9; op1val:0xffffff7f; op2val:0xff7fffff; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x4, x1, x9, 0xffffff7f, 0xff7fffff, 0x4, 3f, x2, 4,0)
+
+inst_10:
+// rs1==x12, rs2==x10, rs2_val == 4290772991, rs1_val == 2147483648
+// opcode: bltu, op1:x12; op2:x10; op1val:0x80000000; op2val:0xffbfffff; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x4, x12, x10, 0x80000000, 0xffbfffff, 0x20, 3f, x2, 8,0)
+
+inst_11:
+// rs1==x14, rs2==x13, rs2_val == 4292870143, 
+// opcode: bltu, op1:x14; op2:x13; op1val:0x0; op2val:0xffdfffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x4, x14, x13, 0x0, 0xffdfffff, 0x0, 3f, x2, 12,0)
+
+inst_12:
+// rs1==x10, rs2==x7, rs2_val == 4293918719, 
+// opcode: bltu, op1:x10; op2:x7; op1val:0xffffff7f; op2val:0xffefffff; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x4, x10, x7, 0xffffff7f, 0xffefffff, 0x100, 3f, x2, 16,0)
+
+inst_13:
+// rs1==x0, rs2==x3, rs2_val == 4294443007, rs1_val == 4290772991
+// opcode: bltu, op1:x0; op2:x3; op1val:0x0; op2val:0xfff7ffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x4, x0, x3, 0x0, 0xfff7ffff, 0x6, 1b, x2, 20,0)
+
+inst_14:
+// rs1==x11, rs2==x0, rs2_val == 4294705151, 
+// opcode: bltu, op1:x11; op2:x0; op1val:0x9; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x4, x11, x0, 0x9, 0x0, 0x40, 3f, x2, 24,0)
+
+inst_15:
+// rs1==x8, rs2==x1, rs2_val == 4294836223, rs1_val == 4294836223
+// opcode: bltu, op1:x8; op2:x1; op1val:0xfffdffff; op2val:0xfffdffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x8, x1, 0xfffdffff, 0xfffdffff, 0x0, 3f, x2, 28,0)
+
+inst_16:
+// rs2_val == 4294901759, rs1_val == 2147483647
+// opcode: bltu, op1:x10; op2:x11; op1val:0x7fffffff; op2val:0xfffeffff; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x7fffffff, 0xfffeffff, 0x556, 1b, x2, 32,0)
+
+inst_17:
+// rs2_val == 4294934527, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xffff7fff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xffff7fff, 0x8, 3f, x2, 36,0)
+
+inst_18:
+// rs2_val == 4294950911, rs1_val == 4026531839
+// opcode: bltu, op1:x10; op2:x11; op1val:0xefffffff; op2val:0xffffbfff; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xefffffff, 0xffffbfff, 0x80, 3f, x2, 40,0)
+
+inst_19:
+// rs2_val == 4294959103, rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0, rs1_val == 4294959103
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffdfff; op2val:0xffffdfff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffdfff, 0xffffdfff, 0x8, 1b, x2, 44,0)
+
+inst_20:
+// rs2_val == 4294963199, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000000; op2val:0xffffefff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000000, 0xffffefff, 0x0, 1b, x2, 48,0)
+
+inst_21:
+// rs2_val == 4294965247, rs1_val == 8192
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2000; op2val:0xfffff7ff; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2000, 0xfffff7ff, 0xa, 1b, x2, 52,0)
+
+inst_22:
+// rs2_val == 4294966271, rs1_val == 1
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xfffffbff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xfffffbff, 0x8, 1b, x2, 56,0)
+
+inst_23:
+// rs2_val == 4294966783, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x12; op2val:0xfffffdff; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x12, 0xfffffdff, 0x10, 3f, x2, 60,0)
+
+inst_24:
+// rs2_val == 4294967039, rs1_val == 16
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10; op2val:0xfffffeff; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10, 0xfffffeff, 0x4, 3f, x2, 64,0)
+
+inst_25:
+// rs2_val == 4294967167, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xffffff7f; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xffffff7f, 0x40, 3f, x2, 68,0)
+
+inst_26:
+// rs2_val == 4294967231, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xffffffbf; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xffffffbf, 0x6, 1b, x2, 72,0)
+
+inst_27:
+// rs2_val == 4294967263, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xffffffdf; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xffffffdf, 0x8, 3f, x2, 76,0)
+
+inst_28:
+// rs2_val == 4294967279, rs1_val == 64
+// opcode: bltu, op1:x10; op2:x11; op1val:0x40; op2val:0xffffffef; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x40, 0xffffffef, 0x6, 3f, x2, 80,0)
+
+inst_29:
+// rs2_val == 4294967287, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xe; op2val:0xfffffff7; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xe, 0xfffffff7, 0x40, 3f, x2, 84,0)
+
+inst_30:
+// rs2_val == 4294967291, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xfffffffb; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xfffffffb, 0x2, 3f, x2, 88,0)
+
+inst_31:
+// rs2_val == 4294967293, rs1_val == 131072
+// opcode: bltu, op1:x10; op2:x11; op1val:0x20000; op2val:0xfffffffd; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x20000, 0xfffffffd, 0x80, 3f, x2, 92,0)
+
+inst_32:
+// rs2_val == 4294967294, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x7; op2val:0xfffffffe; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x7, 0xfffffffe, 0x2, 1b, x2, 96,0)
+
+inst_33:
+// rs1_val == 3221225471, rs2_val == 8192
+// opcode: bltu, op1:x10; op2:x11; op1val:0xbfffffff; op2val:0x2000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xbfffffff, 0x2000, 0x4, 3f, x2, 100,0)
+
+inst_34:
+// rs1_val == 4160749567, rs2_val == 67108864
+// opcode: bltu, op1:x10; op2:x11; op1val:0xf7ffffff; op2val:0x4000000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xf7ffffff, 0x4000000, 0x4, 1b, x2, 104,0)
+
+inst_35:
+// rs1_val == 4227858431, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfbffffff; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfbffffff, 0x55555556, 0x6, 1b, x2, 108,0)
+
+inst_36:
+// rs1_val == 4261412863, rs2_val == 1431655765
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfdffffff; op2val:0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfdffffff, 0x55555555, 0x40, 3f, x2, 112,0)
+
+inst_37:
+// rs1_val == 4278190079, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfeffffff; op2val:0xffff; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfeffffff, 0xffff, 0x8, 3f, x2, 116,0)
+
+inst_38:
+// rs1_val == 4286578687, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xff7fffff; op2val:0x200; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xff7fffff, 0x200, 0x4, 3f, x2, 120,0)
+
+inst_39:
+// rs1_val == 4292870143, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffdfffff; op2val:0x9; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffdfffff, 0x9, 0x2, 1b, x2, 124,0)
+
+inst_40:
+// rs1_val == 4293918719, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffefffff; op2val:0x7fffffff; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffefffff, 0x7fffffff, 0xa, 1b, x2, 128,0)
+
+inst_41:
+// rs1_val == 4294443007, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfff7ffff; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfff7ffff, 0x55555555, 0x0, 3f, x2, 132,0)
+
+inst_42:
+// rs1_val == 4294705151, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffbffff; op2val:0xfff7ffff; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffbffff, 0xfff7ffff, 0x40, 3f, x2, 136,0)
+
+inst_43:
+// rs1_val == 4294901759, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffeffff; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffeffff, 0x5, 0x4, 3f, x2, 140,0)
+
+inst_44:
+// rs1_val == 4294934527, rs2_val == 256
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff7fff; op2val:0x100; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff7fff, 0x100, 0x10, 3f, x2, 144,0)
+
+inst_45:
+// rs1_val == 4294950911, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffbfff; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffbfff, 0x33333334, 0x40, 3f, x2, 148,0)
+
+inst_46:
+// rs1_val == 4294963199, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffefff; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffefff, 0x55555556, 0x0, 1b, x2, 152,0)
+
+inst_47:
+// rs1_val == 4294965247, rs2_val == 8
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffff7ff; op2val:0x8; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffff7ff, 0x8, 0x556, 1b, x2, 156,0)
+
+inst_48:
+// rs1_val == 4294966271, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffbff; op2val:0xfffdffff; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffbff, 0xfffdffff, 0x100, 3f, x2, 160,0)
+
+inst_49:
+// rs1_val == 4294966783, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffdff; op2val:0x8; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffdff, 0x8, 0x4, 3f, x2, 164,0)
+
+inst_50:
+// rs1_val == 4294967039, rs2_val == 131072
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffeff; op2val:0x20000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffeff, 0x20000, 0x6, 3f, x2, 168,0)
+
+inst_51:
+// rs1_val == 4294967231, rs2_val == 64
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffffbf; op2val:0x40; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffffbf, 0x40, 0x0, 3f, x2, 172,0)
+
+inst_52:
+// rs1_val == 4294967263, rs2_val == 2863311530
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffffdf; op2val:0xaaaaaaaa; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffffdf, 0xaaaaaaaa, 0x100, 3f, x2, 176,0)
+
+inst_53:
+// rs1_val == 4294967279, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffffef; op2val:0x11; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffffef, 0x11, 0x556, 1b, x2, 180,0)
+
+inst_54:
+// rs1_val == 4294967287, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffff7; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffff7, 0x33333332, 0x0, 1b, x2, 184,0)
+
+inst_55:
+// rs1_val == 4294967291, rs2_val == 2
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffffb; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffffb, 0x2, 0x100, 3f, x2, 188,0)
+
+inst_56:
+// rs1_val == 4294967293, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffffd; op2val:0xfffe; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffffd, 0xfffe, 0x100, 3f, x2, 192,0)
+
+inst_57:
+// rs1_val == 4294967294, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffffffe; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffffffe, 0x66666667, 0x200, 3f, x2, 196,0)
+
+inst_58:
+// rs2_val == 2147483648, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffdfff; op2val:0x80000000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffdfff, 0x80000000, 0x6, 3f, x2, 200,0)
+
+inst_59:
+// rs2_val == 1073741824, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xbfffffff; op2val:0x40000000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xbfffffff, 0x40000000, 0x4, 3f, x2, 204,0)
+
+inst_60:
+// rs2_val == 536870912, rs1_val == 4
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x20000000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x20000000, 0x0, 3f, x2, 208,0)
+
+inst_61:
+// rs2_val == 268435456, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x20000; op2val:0x10000000; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x20000, 0x10000000, 0x80, 3f, x2, 212,0)
+
+inst_62:
+// rs2_val == 134217728, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x11; op2val:0x8000000; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x11, 0x8000000, 0x8, 1b, x2, 216,0)
+
+inst_63:
+// rs2_val == 33554432, rs1_val == 536870912
+// opcode: bltu, op1:x10; op2:x11; op1val:0x20000000; op2val:0x2000000; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x20000000, 0x2000000, 0x556, 1b, x2, 220,0)
+
+inst_64:
+// rs2_val == 16777216, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffdffff; op2val:0x1000000; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffdffff, 0x1000000, 0x400, 1b, x2, 224,0)
+
+inst_65:
+// rs2_val == 8388608, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfff7ffff; op2val:0x800000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfff7ffff, 0x800000, 0x0, 3f, x2, 228,0)
+
+inst_66:
+// rs2_val == 4194304, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xefffffff; op2val:0x400000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xefffffff, 0x400000, 0x4, 1b, x2, 232,0)
+
+inst_67:
+// rs2_val == 2097152, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x200000; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x200000, 0x20, 3f, x2, 236,0)
+
+inst_68:
+// rs2_val == 1048576, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x100000; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x100000, 0x556, 1b, x2, 240,0)
+
+inst_69:
+// rs2_val == 524288, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x80000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x80000, 0x6, 3f, x2, 244,0)
+
+inst_70:
+// rs2_val == 262144, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x7; op2val:0x40000; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x7, 0x40000, 0x80, 3f, x2, 248,0)
+
+inst_71:
+// rs2_val == 65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfff7ffff; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfff7ffff, 0x10000, 0x4, 1b, x2, 252,0)
+
+inst_72:
+// rs2_val == 32768, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffefffff; op2val:0x8000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffefffff, 0x8000, 0x4, 3f, x2, 256,0)
+
+inst_73:
+// rs2_val == 16384, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xf; op2val:0x4000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xf, 0x4000, 0x4, 1b, x2, 260,0)
+
+inst_74:
+// rs2_val == 4096, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffefff; op2val:0x1000; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffefff, 0x1000, 0x400, 1b, x2, 264,0)
+
+inst_75:
+// rs2_val == 2048, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x800; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x800, 0x20, 3f, x2, 268,0)
+
+inst_76:
+// rs2_val == 1024, rs1_val == 1431655765
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x400; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x400, 0x6, 1b, x2, 272,0)
+
+inst_77:
+// rs2_val == 128, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x80; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x80, 0x8, 3f, x2, 276,0)
+
+inst_78:
+// rs2_val == 32, rs1_val == 4194304
+// opcode: bltu, op1:x10; op2:x11; op1val:0x400000; op2val:0x20; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x400000, 0x20, 0x2, 3f, x2, 280,0)
+
+inst_79:
+// rs2_val == 16, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffbfffff; op2val:0x10; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffbfffff, 0x10, 0x4, 1b, x2, 284,0)
+
+inst_80:
+// rs2_val == 4, rs1_val == 67108864
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4000000; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4000000, 0x4, 0x556, 1b, x2, 288,0)
+
+inst_81:
+// rs2_val == 1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffffdfff; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffffdfff, 0x1, 0x0, 3f, x2, 292,0)
+
+inst_82:
+// rs1_val == 1073741824, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x40000000; op2val:0x2000000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x40000000, 0x2000000, 0x4, 1b, x2, 296,0)
+
+inst_83:
+// rs1_val == 33554432, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2000000; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2000000, 0xaaaaaaab, 0x6, 1b, x2, 300,0)
+
+inst_84:
+// rs1_val == 16777216, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1000000; op2val:0x40000000; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1000000, 0x40000000, 0x40, 3f, x2, 304,0)
+
+inst_85:
+// rs1_val == 8388608, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x800000; op2val:0x40000; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x800000, 0x40000, 0x40, 3f, x2, 308,0)
+
+inst_86:
+// rs1_val == 2097152, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x200000; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x200000, 0x55555556, 0xa, 1b, x2, 312,0)
+
+inst_87:
+// rs1_val == 1048576, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x100000; op2val:0x80000000; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x100000, 0x80000000, 0x10, 3f, x2, 316,0)
+
+inst_88:
+// rs1_val == 524288, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x80000; op2val:0xb; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x80000, 0xb, 0x40, 3f, x2, 320,0)
+
+inst_89:
+// rs1_val == 262144, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x40000; op2val:0x1; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x40000, 0x1, 0x400, 1b, x2, 324,0)
+
+inst_90:
+// rs1_val == 65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xfffff7ff; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xfffff7ff, 0x556, 1b, x2, 328,0)
+
+inst_91:
+// rs1_val == 32768, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x8000; op2val:0xfffffdff; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x8000, 0xfffffdff, 0x80, 3f, x2, 332,0)
+
+inst_92:
+// rs1_val == 16384, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4000; op2val:0xfffffffe; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4000, 0xfffffffe, 0x0, 3f, x2, 336,0)
+
+inst_93:
+// rs1_val == 4096, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1000; op2val:0xfffffffb; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1000, 0xfffffffb, 0x0, 3f, x2, 340,0)
+
+inst_94:
+// rs1_val == 2048, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x800; op2val:0x4000000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x800, 0x4000000, 0x6, 1b, x2, 344,0)
+
+inst_95:
+// rs1_val == 1024, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x400; op2val:0x13; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x400, 0x13, 0x0, 3f, x2, 348,0)
+
+inst_96:
+// rs1_val == 512, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x200; op2val:0x20; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x200, 0x20, 0x8, 3f, x2, 352,0)
+
+inst_97:
+// rs1_val == 256, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x100; op2val:0xfffff7ff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x100, 0xfffff7ff, 0x6, 3f, x2, 356,0)
+
+inst_98:
+// rs1_val == 128, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x80; op2val:0x7; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x80, 0x7, 0x10, 3f, x2, 360,0)
+
+inst_99:
+// rs1_val == 32, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x20; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x20, 0x10000, 0x400, 1b, x2, 364,0)
+
+inst_100:
+// rs1_val == 8, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x8; op2val:0x10000; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x8, 0x10000, 0x100, 3f, x2, 368,0)
+
+inst_101:
+// rs1_val==65536 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x10000, 0x2, 1b, x2, 372,0)
+
+inst_102:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x1, 0x6, 1b, x2, 376,0)
+
+inst_103:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xb505, 0x556, 1b, x2, 380,0)
+
+inst_104:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x66666667, 0x2, 1b, x2, 384,0)
+
+inst_105:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x33333334, 0x4, 3f, x2, 388,0)
+
+inst_106:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x6, 0x4, 3f, x2, 392,0)
+
+inst_107:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaab; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xaaaaaaab, 0x20, 3f, x2, 396,0)
+
+inst_108:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x55555556, 0x100, 3f, x2, 400,0)
+
+inst_109:
+// rs1_val==65536 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x4, 0x20, 3f, x2, 404,0)
+
+inst_110:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xfffe; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xfffe, 0x20, 3f, x2, 408,0)
+
+inst_111:
+// rs1_val==65536 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x0, 0x0, 1b, x2, 412,0)
+
+inst_112:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xb503, 0x0, 1b, x2, 416,0)
+
+inst_113:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x66666665, 0x2, 1b, x2, 420,0)
+
+inst_114:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x33333332, 0x556, 1b, x2, 424,0)
+
+inst_115:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaa9; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xaaaaaaa9, 0x400, 3f, x2, 428,0)
+
+inst_116:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x55555554, 0x80, 3f, x2, 432,0)
+
+inst_117:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x2; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x2, 0x556, 1b, x2, 436,0)
+
+inst_118:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xffff, 0x0, 3f, x2, 440,0)
+
+inst_119:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xb504, 0x10, 3f, x2, 444,0)
+
+inst_120:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x66666666, 0x400, 1b, x2, 448,0)
+
+inst_121:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x33333333, 0x2, 3f, x2, 452,0)
+
+inst_122:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x5, 0x400, 1b, x2, 456,0)
+
+inst_123:
+// rs1_val==65536 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0xaaaaaaaa; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0xaaaaaaaa, 0x0, 1b, x2, 460,0)
+
+inst_124:
+// rs1_val==65536 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x55555555, 0x2, 1b, x2, 464,0)
+
+inst_125:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x10000; op2val:0x3; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x10000, 0x3, 0x80, 3f, x2, 468,0)
+
+inst_126:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x10000, 0x6, 1b, x2, 472,0)
+
+inst_127:
+// rs1_val==1 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x1, 0x0, 1b, x2, 476,0)
+
+inst_128:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xb505, 0x2, 1b, x2, 480,0)
+
+inst_129:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x66666667, 0x200, 3f, x2, 484,0)
+
+inst_130:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x33333334, 0x4, 3f, x2, 488,0)
+
+inst_131:
+// rs1_val==1 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x6, 0x20, 3f, x2, 492,0)
+
+inst_132:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaab; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xaaaaaaab, 0x80, 3f, x2, 496,0)
+
+inst_133:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x55555556, 0x400, 3f, x2, 500,0)
+
+inst_134:
+// rs1_val==1 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x4, 0x4, 1b, x2, 504,0)
+
+inst_135:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xfffe; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xfffe, 0x40, 3f, x2, 508,0)
+
+inst_136:
+// rs1_val==1 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x0, 0x0, 3f, x2, 512,0)
+
+inst_137:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xb503, 0x10, 3f, x2, 516,0)
+
+inst_138:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x66666665, 0x400, 3f, x2, 520,0)
+
+inst_139:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x33333332, 0x8, 3f, x2, 524,0)
+
+inst_140:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaa9; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xaaaaaaa9, 0x10, 3f, x2, 528,0)
+
+inst_141:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x55555554, 0x4, 1b, x2, 532,0)
+
+inst_142:
+// rs1_val==1 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x2; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x2, 0x200, 3f, x2, 536,0)
+
+inst_143:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xffff; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xffff, 0x400, 3f, x2, 540,0)
+
+inst_144:
+// rs1_val==1 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xb504, 0x6, 1b, x2, 544,0)
+
+inst_145:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x66666666, 0x556, 1b, x2, 548,0)
+
+inst_146:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x33333333, 0x0, 1b, x2, 552,0)
+
+inst_147:
+// rs1_val==1 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x5, 0x200, 3f, x2, 556,0)
+
+inst_148:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0xaaaaaaaa; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0xaaaaaaaa, 0x8, 1b, x2, 560,0)
+
+inst_149:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x55555555, 0x556, 1b, x2, 564,0)
+
+inst_150:
+// rs1_val==1 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x1; op2val:0x3; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x1, 0x3, 0x80, 3f, x2, 568,0)
+
+inst_151:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x10000, 0x0, 3f, x2, 572,0)
+
+inst_152:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x1; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x1, 0x2, 3f, x2, 576,0)
+
+inst_153:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xb505, 0x4, 1b, x2, 580,0)
+
+inst_154:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x66666667, 0x6, 3f, x2, 584,0)
+
+inst_155:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x33333334, 0x100, 3f, x2, 588,0)
+
+inst_156:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x6, 0x80, 3f, x2, 592,0)
+
+inst_157:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaab; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xaaaaaaab, 0x100, 3f, x2, 596,0)
+
+inst_158:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x55555556, 0x556, 1b, x2, 600,0)
+
+inst_159:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x4, 0x8, 1b, x2, 604,0)
+
+inst_160:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xfffe; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xfffe, 0x8, 3f, x2, 608,0)
+
+inst_161:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x0, 0x0, 3f, x2, 612,0)
+
+inst_162:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xb503, 0x20, 3f, x2, 616,0)
+
+inst_163:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x66666665, 0x10, 3f, x2, 620,0)
+
+inst_164:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x33333332, 0x20, 3f, x2, 624,0)
+
+inst_165:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaa9; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xaaaaaaa9, 0xa, 1b, x2, 628,0)
+
+inst_166:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x55555554, 0x10, 3f, x2, 632,0)
+
+inst_167:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x2, 0x8, 1b, x2, 636,0)
+
+inst_168:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xffff, 0x6, 1b, x2, 640,0)
+
+inst_169:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xb504, 0x2, 1b, x2, 644,0)
+
+inst_170:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x66666666, 0x400, 3f, x2, 648,0)
+
+inst_171:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x33333333, 0x4, 3f, x2, 652,0)
+
+inst_172:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x5, 0x2, 3f, x2, 656,0)
+
+inst_173:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0xaaaaaaaa; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0xaaaaaaaa, 0x556, 1b, x2, 660,0)
+
+inst_174:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x55555555, 0x100, 3f, x2, 664,0)
+
+inst_175:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb505, 0x3, 0x6, 3f, x2, 668,0)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x10000; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x10000, 0x10, 3f, x2, 672,0)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x1, 0x4, 3f, x2, 676,0)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xb505, 0x556, 1b, x2, 680,0)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==1717986919, rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x66666667, 0x80, 3f, x2, 684,0)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x33333334, 0x0, 3f, x2, 688,0)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x6, 0x0, 3f, x2, 692,0)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xaaaaaaab, 0x6, 3f, x2, 696,0)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x55555556, 0x556, 1b, x2, 700,0)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x4, 0x4, 1b, x2, 704,0)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xfffe; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xfffe, 0x20, 3f, x2, 708,0)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x0, 0x0, 3f, x2, 712,0)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xb503, 0x6, 3f, x2, 716,0)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x66666665, 0x400, 1b, x2, 720,0)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x33333332, 0x556, 1b, x2, 724,0)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaa9; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xaaaaaaa9, 0x2, 1b, x2, 728,0)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x55555554, 0x0, 1b, x2, 732,0)
+
+inst_192:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x2, 0xa, 1b, x2, 736,0)
+
+inst_193:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xffff; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xffff, 0x40, 3f, x2, 740,0)
+
+inst_194:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xb504, 0x8, 3f, x2, 744,0)
+
+inst_195:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x66666666, 0x100, 3f, x2, 748,0)
+
+inst_196:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x33333333, 0x40, 3f, x2, 752,0)
+
+inst_197:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x5, 0x40, 3f, x2, 756,0)
+
+inst_198:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0xaaaaaaaa; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0xaaaaaaaa, 0x8, 3f, x2, 760,0)
+
+inst_199:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x55555555, 0x4, 1b, x2, 764,0)
+
+inst_200:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666667, 0x3, 0x8, 3f, x2, 768,0)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x10000, 0x2, 1b, x2, 772,0)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x1, 0x4, 3f, x2, 776,0)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xb505, 0x4, 1b, x2, 780,0)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x66666667, 0x10, 3f, x2, 784,0)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x33333334, 0x0, 1b, x2, 788,0)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x6, 0x6, 1b, x2, 792,0)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xaaaaaaab, 0x6, 1b, x2, 796,0)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x55555556, 0x4, 1b, x2, 800,0)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x4, 0x400, 3f, x2, 804,0)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xfffe; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xfffe, 0x4, 1b, x2, 808,0)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x0, 0x2, 1b, x2, 812,0)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xb503, 0x80, 3f, x2, 816,0)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x66666665, 0x20, 3f, x2, 820,0)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x33333332, 0xa, 1b, x2, 824,0)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaa9; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xaaaaaaa9, 0x4, 3f, x2, 828,0)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x55555554, 0x4, 1b, x2, 832,0)
+
+inst_217:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x2, 0x2, 1b, x2, 836,0)
+
+inst_218:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xffff, 0x0, 1b, x2, 840,0)
+
+inst_219:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xb504, 0x100, 3f, x2, 844,0)
+
+inst_220:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x66666666, 0x200, 3f, x2, 848,0)
+
+inst_221:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x33333333, 0x10, 3f, x2, 852,0)
+
+inst_222:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x5, 0x100, 3f, x2, 856,0)
+
+inst_223:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0xaaaaaaaa, 0x6, 1b, x2, 860,0)
+
+inst_224:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x55555555, 0x6, 3f, x2, 864,0)
+
+inst_225:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333334, 0x3, 0x400, 1b, x2, 868,0)
+
+inst_226:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x10000; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x10000, 0x40, 3f, x2, 872,0)
+
+inst_227:
+// rs1_val==6 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x1, 0x0, 3f, x2, 876,0)
+
+inst_228:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xb505, 0xa, 1b, x2, 880,0)
+
+inst_229:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x66666667, 0x4, 1b, x2, 884,0)
+
+inst_230:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x33333334, 0x10, 3f, x2, 888,0)
+
+inst_231:
+// rs1_val==6 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x6, 0x100, 3f, x2, 892,0)
+
+inst_232:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaab; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xaaaaaaab, 0x10, 3f, x2, 896,0)
+
+inst_233:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x55555556, 0x4, 1b, x2, 900,0)
+
+inst_234:
+// rs1_val==6 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x4, 0x6, 3f, x2, 904,0)
+
+inst_235:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xfffe; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xfffe, 0x2, 3f, x2, 908,0)
+
+inst_236:
+// rs1_val==6 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x0, 0x6, 3f, x2, 912,0)
+
+inst_237:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xb503, 0x8, 3f, x2, 916,0)
+
+inst_238:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x66666665, 0x4, 3f, x2, 920,0)
+
+inst_239:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x33333332, 0x10, 3f, x2, 924,0)
+
+inst_240:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaa9; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xaaaaaaa9, 0x400, 3f, x2, 928,0)
+
+inst_241:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x55555554, 0x0, 3f, x2, 932,0)
+
+inst_242:
+// rs1_val==6 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x2, 0x0, 3f, x2, 936,0)
+
+inst_243:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xffff; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xffff, 0x2, 1b, x2, 940,0)
+
+inst_244:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xb504, 0x10, 3f, x2, 944,0)
+
+inst_245:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x66666666, 0x0, 3f, x2, 948,0)
+
+inst_246:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x33333333, 0x8, 1b, x2, 952,0)
+
+inst_247:
+// rs1_val==6 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x5, 0x6, 1b, x2, 956,0)
+
+inst_248:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0xaaaaaaaa; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0xaaaaaaaa, 0x40, 3f, x2, 960,0)
+
+inst_249:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x55555555, 0x400, 3f, x2, 964,0)
+
+inst_250:
+// rs1_val==6 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x6, 0x3, 0x400, 3f, x2, 968,0)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x10000, 0x0, 3f, x2, 972,0)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x1; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x1, 0x0, 1b, x2, 976,0)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xb505, 0x8, 3f, x2, 980,0)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x66666667, 0x8, 3f, x2, 984,0)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x33333334, 0x8, 3f, x2, 988,0)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x6, 0x2, 1b, x2, 992,0)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xaaaaaaab, 0x8, 3f, x2, 996,0)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x55555556, 0xa, 1b, x2, 1000,0)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x4, 0x0, 1b, x2, 1004,0)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xfffe; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xfffe, 0x100, 3f, x2, 1008,0)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x0, 0x2, 3f, x2, 1012,0)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xb503, 0x6, 3f, x2, 1016,0)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x66666665, 0x556, 1b, x2, 1020,0)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x33333332, 0x4, 1b, x2, 1024,0)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaa9; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xaaaaaaa9, 0x6, 3f, x2, 1028,0)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x55555554, 0x8, 3f, x2, 1032,0)
+
+inst_267:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x2, 0x6, 3f, x2, 1036,0)
+
+inst_268:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xffff; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xffff, 0x100, 3f, x2, 1040,0)
+
+inst_269:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xb504, 0x0, 1b, x2, 1044,0)
+
+inst_270:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x66666666; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x66666666, 0x20, 3f, x2, 1048,0)
+
+inst_271:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x33333333, 0x4, 3f, x2, 1052,0)
+
+inst_272:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x5, 0x100, 3f, x2, 1056,0)
+
+inst_273:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0xaaaaaaaa; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0xaaaaaaaa, 0x2, 1b, x2, 1060,0)
+
+inst_274:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x55555555, 0x80, 3f, x2, 1064,0)
+
+inst_275:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaab; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaab, 0x3, 0x4, 3f, x2, 1068,0)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x10000, 0x4, 3f, x2, 1072,0)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x1; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x1, 0xa, 1b, x2, 1076,0)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xb505, 0x10, 3f, x2, 1080,0)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x66666667, 0x0, 1b, x2, 1084,0)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x33333334, 0x0, 3f, x2, 1088,0)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x6, 0x6, 1b, x2, 1092,0)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xaaaaaaab, 0x6, 1b, x2, 1096,0)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x55555556, 0x556, 1b, x2, 1100,0)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x4, 0x6, 3f, x2, 1104,0)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xfffe; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xfffe, 0x0, 1b, x2, 1108,0)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x0, 0x6, 1b, x2, 1112,0)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xb503, 0x8, 3f, x2, 1116,0)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x66666665, 0xa, 1b, x2, 1120,0)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x33333332, 0x20, 3f, x2, 1124,0)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaa9; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xaaaaaaa9, 0x8, 3f, x2, 1128,0)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x55555554, 0x6, 3f, x2, 1132,0)
+
+inst_292:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x2, 0x100, 3f, x2, 1136,0)
+
+inst_293:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xffff, 0x6, 1b, x2, 1140,0)
+
+inst_294:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xb504, 0x200, 3f, x2, 1144,0)
+
+inst_295:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x66666666, 0x0, 3f, x2, 1148,0)
+
+inst_296:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x33333333, 0x2, 1b, x2, 1152,0)
+
+inst_297:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x5, 0x4, 3f, x2, 1156,0)
+
+inst_298:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0xaaaaaaaa; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0xaaaaaaaa, 0x0, 3f, x2, 1160,0)
+
+inst_299:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x55555555, 0x8, 3f, x2, 1164,0)
+
+inst_300:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555556, 0x3, 0x0, 3f, x2, 1168,0)
+
+inst_301:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x10000; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x10000, 0x6, 1b, x2, 1172,0)
+
+inst_302:
+// rs1_val==4 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x1, 0x6, 1b, x2, 1176,0)
+
+inst_303:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xb505, 0x8, 3f, x2, 1180,0)
+
+inst_304:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x66666667, 0x0, 1b, x2, 1184,0)
+
+inst_305:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x33333334, 0x40, 3f, x2, 1188,0)
+
+inst_306:
+// rs1_val==4 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x6, 0x200, 3f, x2, 1192,0)
+
+inst_307:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaab; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xaaaaaaab, 0x400, 1b, x2, 1196,0)
+
+inst_308:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x55555556, 0x0, 1b, x2, 1200,0)
+
+inst_309:
+// rs1_val==4 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x4, 0x40, 3f, x2, 1204,0)
+
+inst_310:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xfffe; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xfffe, 0x6, 1b, x2, 1208,0)
+
+inst_311:
+// rs1_val==4 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x0, 0x8, 1b, x2, 1212,0)
+
+inst_312:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xb503, 0x8, 1b, x2, 1216,0)
+
+inst_313:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x66666665, 0x556, 1b, x2, 1220,0)
+
+inst_314:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x33333332, 0x8, 1b, x2, 1224,0)
+
+inst_315:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaa9; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xaaaaaaa9, 0x0, 1b, x2, 1228,0)
+
+inst_316:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x55555554, 0x6, 1b, x2, 1232,0)
+
+inst_317:
+// rs1_val==4 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x2, 0x100, 3f, x2, 1236,0)
+
+inst_318:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xffff, 0x6, 3f, x2, 1240,0)
+
+inst_319:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xb504, 0x400, 3f, x2, 1244,0)
+
+inst_320:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x66666666, 0x100, 3f, x2, 1248,0)
+
+inst_321:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x33333333, 0x8, 1b, x2, 1252,0)
+
+inst_322:
+// rs1_val==4 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x5, 0x10, 3f, x2, 1256,0)
+
+inst_323:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0xaaaaaaaa; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0xaaaaaaaa, 0x400, 1b, x2, 1260,0)
+
+inst_324:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x55555555, 0xa, 1b, x2, 1264,0)
+
+inst_325:
+// rs1_val==4 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x4, 0x3, 0x2, 3f, x2, 1268,0)
+
+inst_326:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x10000, 0x0, 3f, x2, 1272,0)
+
+inst_327:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x1, 0x6, 1b, x2, 1276,0)
+
+inst_328:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xb505, 0x2, 1b, x2, 1280,0)
+
+inst_329:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x66666667, 0x4, 1b, x2, 1284,0)
+
+inst_330:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x33333334, 0x8, 3f, x2, 1288,0)
+
+inst_331:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x6, 0x200, 3f, x2, 1292,0)
+
+inst_332:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xaaaaaaab, 0x6, 3f, x2, 1296,0)
+
+inst_333:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x55555556, 0x0, 3f, x2, 1300,0)
+
+inst_334:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x4, 0x8, 1b, x2, 1304,0)
+
+inst_335:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xfffe; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xfffe, 0x400, 3f, x2, 1308,0)
+
+inst_336:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x0; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x0, 0x80, 3f, x2, 1312,0)
+
+inst_337:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xb503, 0x40, 3f, x2, 1316,0)
+
+inst_338:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x66666665, 0x6, 3f, x2, 1320,0)
+
+inst_339:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x33333332, 0x100, 3f, x2, 1324,0)
+
+inst_340:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaa9; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xaaaaaaa9, 0xa, 1b, x2, 1328,0)
+
+inst_341:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x55555554, 0x0, 1b, x2, 1332,0)
+
+inst_342:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x2, 0x40, 3f, x2, 1336,0)
+
+inst_343:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xffff; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xffff, 0x6, 3f, x2, 1340,0)
+
+inst_344:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xb504, 0x6, 1b, x2, 1344,0)
+
+inst_345:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x66666666; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x66666666, 0x200, 3f, x2, 1348,0)
+
+inst_346:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x33333333, 0x6, 3f, x2, 1352,0)
+
+inst_347:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x5, 0x4, 3f, x2, 1356,0)
+
+inst_348:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0xaaaaaaaa; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0xaaaaaaaa, 0x8, 3f, x2, 1360,0)
+
+inst_349:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x55555555, 0x0, 3f, x2, 1364,0)
+
+inst_350:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xfffe; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xfffe, 0x3, 0x0, 1b, x2, 1368,0)
+
+inst_351:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x10000; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x10000, 0x8, 3f, x2, 1372,0)
+
+inst_352:
+// rs1_val==0 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x1; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x1, 0x100, 3f, x2, 1376,0)
+
+inst_353:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xb505, 0x40, 3f, x2, 1380,0)
+
+inst_354:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x66666667, 0x400, 3f, x2, 1384,0)
+
+inst_355:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x33333334, 0x10, 3f, x2, 1388,0)
+
+inst_356:
+// rs1_val==0 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x6, 0x20, 3f, x2, 1392,0)
+
+inst_357:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaab; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xaaaaaaab, 0x2, 3f, x2, 1396,0)
+
+inst_358:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x55555556, 0x8, 1b, x2, 1400,0)
+
+inst_359:
+// rs1_val==0 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x4, 0x400, 3f, x2, 1404,0)
+
+inst_360:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xfffe; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xfffe, 0x400, 3f, x2, 1408,0)
+
+inst_361:
+// rs1_val==0 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x0, 0x0, 3f, x2, 1412,0)
+
+inst_362:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xb503, 0x400, 3f, x2, 1416,0)
+
+inst_363:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x66666665, 0x20, 3f, x2, 1420,0)
+
+inst_364:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x33333332, 0x2, 1b, x2, 1424,0)
+
+inst_365:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaa9; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xaaaaaaa9, 0x80, 3f, x2, 1428,0)
+
+inst_366:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x55555554, 0xa, 1b, x2, 1432,0)
+
+inst_367:
+// rs1_val==0 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x2, 0x20, 3f, x2, 1436,0)
+
+inst_368:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xffff; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xffff, 0x2, 3f, x2, 1440,0)
+
+inst_369:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xb504, 0x8, 1b, x2, 1444,0)
+
+inst_370:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x66666666, 0x8, 1b, x2, 1448,0)
+
+inst_371:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x33333333, 0x400, 3f, x2, 1452,0)
+
+inst_372:
+// rs1_val==0 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x5, 0x8, 3f, x2, 1456,0)
+
+inst_373:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0xaaaaaaaa; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0xaaaaaaaa, 0x400, 1b, x2, 1460,0)
+
+inst_374:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x55555555, 0x2, 1b, x2, 1464,0)
+
+inst_375:
+// rs1_val==0 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x0, 0x3, 0x20, 3f, x2, 1468,0)
+
+inst_376:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x10000; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x10000, 0x200, 3f, x2, 1472,0)
+
+inst_377:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x1, 0x8, 3f, x2, 1476,0)
+
+inst_378:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xb505, 0x400, 3f, x2, 1480,0)
+
+inst_379:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x66666667, 0x20, 3f, x2, 1484,0)
+
+inst_380:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x33333334, 0x2, 1b, x2, 1488,0)
+
+inst_381:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x6, 0x20, 3f, x2, 1492,0)
+
+inst_382:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xaaaaaaab, 0x8, 3f, x2, 1496,0)
+
+inst_383:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x55555556, 0x400, 3f, x2, 1500,0)
+
+inst_384:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x4, 0x0, 1b, x2, 1504,0)
+
+inst_385:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xfffe; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xfffe, 0x556, 1b, x2, 1508,0)
+
+inst_386:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x0, 0x6, 3f, x2, 1512,0)
+
+inst_387:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xb503, 0x20, 3f, x2, 1516,0)
+
+inst_388:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x66666665, 0x400, 1b, x2, 1520,0)
+
+inst_389:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x33333332, 0x100, 3f, x2, 1524,0)
+
+inst_390:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaa9; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xaaaaaaa9, 0x400, 1b, x2, 1528,0)
+
+inst_391:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x55555554, 0x8, 1b, x2, 1532,0)
+
+inst_392:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x2, 0x6, 3f, x2, 1536,0)
+
+inst_393:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xffff; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xffff, 0x4, 1b, x2, 1540,0)
+
+inst_394:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xb504, 0x8, 3f, x2, 1544,0)
+
+inst_395:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x66666666, 0x8, 1b, x2, 1548,0)
+
+inst_396:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x33333333, 0x20, 3f, x2, 1552,0)
+
+inst_397:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x5, 0x8, 1b, x2, 1556,0)
+
+inst_398:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0xaaaaaaaa; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0xaaaaaaaa, 0x200, 3f, x2, 1560,0)
+
+inst_399:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x55555555, 0x80, 3f, x2, 1564,0)
+
+inst_400:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb503, 0x3, 0x4, 3f, x2, 1568,0)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x10000; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x10000, 0x10, 3f, x2, 1572,0)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x1, 0x8, 3f, x2, 1576,0)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xb505, 0x80, 3f, x2, 1580,0)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x66666667, 0x4, 3f, x2, 1584,0)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x33333334, 0x4, 1b, x2, 1588,0)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x6, 0x10, 3f, x2, 1592,0)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaab; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xaaaaaaab, 0x556, 1b, x2, 1596,0)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x55555556, 0x2, 3f, x2, 1600,0)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x4, 0x10, 3f, x2, 1604,0)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xfffe; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xfffe, 0x4, 1b, x2, 1608,0)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x0, 0x6, 1b, x2, 1612,0)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xb503, 0x10, 3f, x2, 1616,0)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x66666665, 0x40, 3f, x2, 1620,0)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x33333332, 0x8, 1b, x2, 1624,0)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaa9; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xaaaaaaa9, 0x0, 1b, x2, 1628,0)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x55555554, 0x80, 3f, x2, 1632,0)
+
+inst_417:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x2, 0x400, 3f, x2, 1636,0)
+
+inst_418:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xffff, 0x0, 3f, x2, 1640,0)
+
+inst_419:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xb504, 0x10, 3f, x2, 1644,0)
+
+inst_420:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x66666666, 0x6, 3f, x2, 1648,0)
+
+inst_421:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x33333333, 0x400, 3f, x2, 1652,0)
+
+inst_422:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x5, 0x6, 3f, x2, 1656,0)
+
+inst_423:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0xaaaaaaaa, 0x4, 3f, x2, 1660,0)
+
+inst_424:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x55555555, 0x400, 1b, x2, 1664,0)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666665, 0x3, 0x40, 3f, x2, 1668,0)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x10000; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x10000, 0x200, 3f, x2, 1672,0)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x1; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x1, 0x40, 3f, x2, 1676,0)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xb505, 0x40, 3f, x2, 1680,0)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x66666667, 0x80, 3f, x2, 1684,0)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x33333334, 0x4, 3f, x2, 1688,0)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x6, 0x4, 1b, x2, 1692,0)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaab; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xaaaaaaab, 0xa, 1b, x2, 1696,0)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x55555556, 0x10, 3f, x2, 1700,0)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x4, 0x2, 1b, x2, 1704,0)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xfffe; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xfffe, 0x100, 3f, x2, 1708,0)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x0, 0x556, 1b, x2, 1712,0)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xb503, 0x2, 1b, x2, 1716,0)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x66666665, 0x4, 1b, x2, 1720,0)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x33333332, 0x80, 3f, x2, 1724,0)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaa9; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xaaaaaaa9, 0x200, 3f, x2, 1728,0)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x55555554, 0x8, 3f, x2, 1732,0)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x2, 0x4, 3f, x2, 1736,0)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xffff; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xffff, 0x10, 3f, x2, 1740,0)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xb504, 0x4, 3f, x2, 1744,0)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x66666666, 0x4, 1b, x2, 1748,0)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x33333333, 0x8, 3f, x2, 1752,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x5, 0xa, 1b, x2, 1756,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0xaaaaaaaa, 0x4, 1b, x2, 1760,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x55555555, 0x100, 3f, x2, 1764,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333332, 0x3, 0x80, 3f, x2, 1768,0)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x10000; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x10000, 0x100, 3f, x2, 1772,0)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x1, 0x6, 3f, x2, 1776,0)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xb505, 0x2, 3f, x2, 1780,0)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x66666667, 0x4, 3f, x2, 1784,0)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x33333334, 0x4, 1b, x2, 1788,0)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x6, 0x200, 3f, x2, 1792,0)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaab; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xaaaaaaab, 0x8, 3f, x2, 1796,0)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x55555556, 0x556, 1b, x2, 1800,0)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x4, 0x8, 3f, x2, 1804,0)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xfffe; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xfffe, 0x4, 3f, x2, 1808,0)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x0, 0x40, 3f, x2, 1812,0)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xb503, 0x400, 1b, x2, 1816,0)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x66666665, 0x8, 1b, x2, 1820,0)
+
+inst_464:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x33333332, 0x0, 1b, x2, 1824,0)
+
+inst_465:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaa9; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xaaaaaaa9, 0x400, 1b, x2, 1828,0)
+
+inst_466:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x55555554, 0x2, 3f, x2, 1832,0)
+
+inst_467:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x2, 0x8, 1b, x2, 1836,0)
+
+inst_468:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xffff; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xffff, 0x10, 3f, x2, 1840,0)
+
+inst_469:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xb504, 0x8, 3f, x2, 1844,0)
+
+inst_470:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x66666666, 0x2, 1b, x2, 1848,0)
+
+inst_471:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x33333333, 0x80, 3f, x2, 1852,0)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x4, 0x4, 3f, x2, 1856,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xfffe; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xfffe, 0x556, 1b, x2, 1860,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x0, 0x40, 3f, x2, 1864,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xb503, 0x6, 1b, x2, 1868,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x66666665, 0x8, 3f, x2, 1872,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x33333332, 0x10, 3f, x2, 1876,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaa9; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xaaaaaaa9, 0x80, 3f, x2, 1880,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x55555554, 0x0, 1b, x2, 1884,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x2, 0x0, 3f, x2, 1888,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xffff; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xffff, 0x100, 3f, x2, 1892,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xb504, 0x0, 1b, x2, 1896,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x66666666, 0x8, 1b, x2, 1900,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x33333333, 0x6, 3f, x2, 1904,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x5, 0x4, 1b, x2, 1908,0)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaaa; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xaaaaaaaa, 0x400, 3f, x2, 1912,0)
+
+inst_487:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x55555555, 0x2, 1b, x2, 1916,0)
+
+inst_488:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x3, 0x20, 3f, x2, 1920,0)
+
+inst_489:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x10000, 0x2, 3f, x2, 1924,0)
+
+inst_490:
+// rs1_val==2 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x1; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x1, 0x6, 3f, x2, 1928,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xb505, 0x10, 3f, x2, 1932,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x66666667, 0x400, 3f, x2, 1936,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x33333334, 0x400, 1b, x2, 1940,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x6, 0x6, 3f, x2, 1944,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xaaaaaaab, 0x6, 3f, x2, 1948,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x55555556, 0x10, 3f, x2, 1952,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x4, 0x8, 3f, x2, 1956,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xfffe; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xfffe, 0x0, 3f, x2, 1960,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x0, 0x400, 1b, x2, 1964,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xb503, 0x0, 1b, x2, 1968,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x66666665, 0x4, 3f, x2, 1972,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x33333332, 0x400, 3f, x2, 1976,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaa9; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xaaaaaaa9, 0x2, 1b, x2, 1980,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x55555554, 0x2, 1b, x2, 1984,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x2, 0x4, 1b, x2, 1988,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xffff; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xffff, 0x80, 3f, x2, 1992,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xb504, 0x8, 3f, x2, 1996,0)
+
+inst_508:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x66666666, 0x40, 3f, x2, 2000,0)
+
+inst_509:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x33333333, 0x80, 3f, x2, 2004,0)
+
+inst_510:
+// rs1_val==2 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x5, 0x40, 3f, x2, 2008,0)
+
+inst_511:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0xaaaaaaaa; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0xaaaaaaaa, 0x200, 3f, x2, 2012,0)
+
+inst_512:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x55555555, 0x2, 3f, x2, 2016,0)
+
+inst_513:
+// rs1_val==2 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x2, 0x3, 0x0, 3f, x2, 2020,0)
+
+inst_514:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x10000, 0x400, 1b, x2, 2024,0)
+
+inst_515:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x1; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x1, 0x400, 1b, x2, 2028,0)
+
+inst_516:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xb505, 0x80, 3f, x2, 2032,0)
+
+inst_517:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666667; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x66666667, 0x556, 1b, x2, 2036,0)
+
+inst_518:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x33333334, 0x200, 3f, x2, 2040,0)
+
+inst_519:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x6, 0x4, 1b, x2, 2044,0)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_520:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaab; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xaaaaaaab, 0x20, 3f, x2, 0,0)
+
+inst_521:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x55555556, 0x100, 3f, x2, 4,0)
+
+inst_522:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x4, 0x6, 1b, x2, 8,0)
+
+inst_523:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xfffe; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xfffe, 0x6, 3f, x2, 12,0)
+
+inst_524:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x0, 0x40, 3f, x2, 16,0)
+
+inst_525:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xb503, 0x0, 3f, x2, 20,0)
+
+inst_526:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x66666665, 0x200, 3f, x2, 24,0)
+
+inst_527:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x33333332, 0x100, 3f, x2, 28,0)
+
+inst_528:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaa9; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xaaaaaaa9, 0xa, 1b, x2, 32,0)
+
+inst_529:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x55555554, 0x200, 3f, x2, 36,0)
+
+inst_530:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x2, 0x0, 3f, x2, 40,0)
+
+inst_531:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xffff; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xffff, 0x20, 3f, x2, 44,0)
+
+inst_532:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xb504, 0x8, 3f, x2, 48,0)
+
+inst_533:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x66666666, 0x0, 3f, x2, 52,0)
+
+inst_534:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x33333333; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x33333333, 0x40, 3f, x2, 56,0)
+
+inst_535:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x5, 0x2, 1b, x2, 60,0)
+
+inst_536:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0xaaaaaaaa, 0x4, 1b, x2, 64,0)
+
+inst_537:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x55555555, 0x0, 1b, x2, 68,0)
+
+inst_538:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xffff; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xffff, 0x3, 0x400, 3f, x2, 72,0)
+
+inst_539:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x10000; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x10000, 0x8, 1b, x2, 76,0)
+
+inst_540:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x1; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x1, 0x100, 3f, x2, 80,0)
+
+inst_541:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xb505, 0x8, 1b, x2, 84,0)
+
+inst_542:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x66666667, 0x2, 1b, x2, 88,0)
+
+inst_543:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x33333334, 0x6, 3f, x2, 92,0)
+
+inst_544:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x6, 0x6, 1b, x2, 96,0)
+
+inst_545:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaab; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xaaaaaaab, 0x80, 3f, x2, 100,0)
+
+inst_546:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x55555556, 0x0, 3f, x2, 104,0)
+
+inst_547:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x4, 0x400, 3f, x2, 108,0)
+
+inst_548:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xfffe; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xfffe, 0x8, 3f, x2, 112,0)
+
+inst_549:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x0, 0x400, 1b, x2, 116,0)
+
+inst_550:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xb503, 0x0, 1b, x2, 120,0)
+
+inst_551:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x66666665, 0xa, 1b, x2, 124,0)
+
+inst_552:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x33333332, 0x40, 3f, x2, 128,0)
+
+inst_553:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaa9; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xaaaaaaa9, 0x4, 1b, x2, 132,0)
+
+inst_554:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x55555554, 0x10, 3f, x2, 136,0)
+
+inst_555:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x2, 0x10, 3f, x2, 140,0)
+
+inst_556:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xffff; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xffff, 0x2, 1b, x2, 144,0)
+
+inst_557:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xb504, 0x2, 3f, x2, 148,0)
+
+inst_558:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x66666666, 0x400, 1b, x2, 152,0)
+
+inst_559:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x33333333, 0x4, 1b, x2, 156,0)
+
+inst_560:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x5, 0x6, 1b, x2, 160,0)
+
+inst_561:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0xaaaaaaaa; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0xaaaaaaaa, 0x10, 3f, x2, 164,0)
+
+inst_562:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x55555555, 0x8, 3f, x2, 168,0)
+
+inst_563:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xb504, 0x3, 0x0, 3f, x2, 172,0)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x10000; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x10000, 0x100, 3f, x2, 176,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x1; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x1, 0x80, 3f, x2, 180,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xb505, 0x0, 1b, x2, 184,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x66666667, 0x40, 3f, x2, 188,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x33333334, 0x6, 1b, x2, 192,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x6, 0x4, 1b, x2, 196,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xaaaaaaab, 0x4, 1b, x2, 200,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x55555556, 0x20, 3f, x2, 204,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x4, 0x10, 3f, x2, 208,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xfffe; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xfffe, 0x40, 3f, x2, 212,0)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x0, 0x10, 3f, x2, 216,0)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xb503, 0x40, 3f, x2, 220,0)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x66666665, 0x8, 1b, x2, 224,0)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x33333332, 0x40, 3f, x2, 228,0)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaa9; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xaaaaaaa9, 0x100, 3f, x2, 232,0)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x55555554, 0x10, 3f, x2, 236,0)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x2, 0x40, 3f, x2, 240,0)
+
+inst_581:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xffff; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xffff, 0x4, 1b, x2, 244,0)
+
+inst_582:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xb504, 0x80, 3f, x2, 248,0)
+
+inst_583:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x66666666, 0x4, 3f, x2, 252,0)
+
+inst_584:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x33333333, 0x2, 3f, x2, 256,0)
+
+inst_585:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x5, 0x0, 3f, x2, 260,0)
+
+inst_586:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0xaaaaaaaa, 0x6, 3f, x2, 264,0)
+
+inst_587:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x55555555, 0x20, 3f, x2, 268,0)
+
+inst_588:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x66666666, 0x3, 0x4, 3f, x2, 272,0)
+
+inst_589:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x10000; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x10000, 0x0, 1b, x2, 276,0)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x1; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x1, 0x2, 3f, x2, 280,0)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xb505, 0xa, 1b, x2, 284,0)
+
+inst_592:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x66666667, 0x40, 3f, x2, 288,0)
+
+inst_593:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x33333334, 0x400, 3f, x2, 292,0)
+
+inst_594:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x6, 0x6, 3f, x2, 296,0)
+
+inst_595:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaab; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xaaaaaaab, 0xa, 1b, x2, 300,0)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x55555556, 0x8, 3f, x2, 304,0)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x4, 0x10, 3f, x2, 308,0)
+
+inst_598:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xfffe; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xfffe, 0x200, 3f, x2, 312,0)
+
+inst_599:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x0, 0x20, 3f, x2, 316,0)
+
+inst_600:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x3, 0x2, 1b, x2, 320,0)
+
+inst_601:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xb503, 0x40, 3f, x2, 324,0)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x66666665, 0x6, 1b, x2, 328,0)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x33333332, 0x2, 1b, x2, 332,0)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaa9; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xaaaaaaa9, 0x2, 3f, x2, 336,0)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x55555554, 0x400, 1b, x2, 340,0)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x2, 0x80, 3f, x2, 344,0)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xffff; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xffff, 0x2, 3f, x2, 348,0)
+
+inst_608:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xb504, 0x8, 3f, x2, 352,0)
+
+inst_609:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x66666666, 0x0, 1b, x2, 356,0)
+
+inst_610:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x33333333, 0x100, 3f, x2, 360,0)
+
+inst_611:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x5, 0x4, 1b, x2, 364,0)
+
+inst_612:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0xaaaaaaaa; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0xaaaaaaaa, 0x80, 3f, x2, 368,0)
+
+inst_613:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x55555555, 0x4, 3f, x2, 372,0)
+
+inst_614:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x33333333, 0x3, 0x400, 1b, x2, 376,0)
+
+inst_615:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x10000; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x10000, 0x400, 1b, x2, 380,0)
+
+inst_616:
+// rs1_val==5 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x1, 0x8, 1b, x2, 384,0)
+
+inst_617:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xb505, 0x2, 1b, x2, 388,0)
+
+inst_618:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x66666667, 0x400, 1b, x2, 392,0)
+
+inst_619:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x33333334, 0x10, 3f, x2, 396,0)
+
+inst_620:
+// rs1_val==5 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x6, 0x40, 3f, x2, 400,0)
+
+inst_621:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaab; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xaaaaaaab, 0x6, 1b, x2, 404,0)
+
+inst_622:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x55555556, 0xa, 1b, x2, 408,0)
+
+inst_623:
+// rs1_val==5 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x4, 0x556, 1b, x2, 412,0)
+
+inst_624:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xfffe; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xfffe, 0x10, 3f, x2, 416,0)
+
+inst_625:
+// rs1_val==5 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x0, 0x0, 1b, x2, 420,0)
+
+inst_626:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xb503, 0x400, 3f, x2, 424,0)
+
+inst_627:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x66666665, 0x20, 3f, x2, 428,0)
+
+inst_628:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x33333332, 0x10, 3f, x2, 432,0)
+
+inst_629:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaa9; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xaaaaaaa9, 0x80, 3f, x2, 436,0)
+
+inst_630:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x55555554, 0x200, 3f, x2, 440,0)
+
+inst_631:
+// rs1_val==5 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x2, 0x100, 3f, x2, 444,0)
+
+inst_632:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xffff; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xffff, 0x0, 3f, x2, 448,0)
+
+inst_633:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xb504, 0x40, 3f, x2, 452,0)
+
+inst_634:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x66666666, 0xa, 1b, x2, 456,0)
+
+inst_635:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x33333333, 0x8, 3f, x2, 460,0)
+
+inst_636:
+// rs1_val==5 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x5, 0x0, 1b, x2, 464,0)
+
+inst_637:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0xaaaaaaaa, 0x4, 3f, x2, 468,0)
+
+inst_638:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x55555555, 0x80, 3f, x2, 472,0)
+
+inst_639:
+// rs1_val==5 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x5, 0x3, 0x0, 1b, x2, 476,0)
+
+inst_640:
+// rs1_val==2863311530 and rs2_val==65536, rs1_val == 2863311530
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x10000; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x10000, 0x20, 3f, x2, 480,0)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x1, 0x8, 3f, x2, 484,0)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xb505, 0x0, 1b, x2, 488,0)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x66666667, 0x2, 1b, x2, 492,0)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x33333334, 0x400, 1b, x2, 496,0)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x6; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x6, 0x200, 3f, x2, 500,0)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xaaaaaaab, 0x4, 3f, x2, 504,0)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x55555556, 0x556, 1b, x2, 508,0)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x4, 0x0, 1b, x2, 512,0)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xfffe; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xfffe, 0x40, 3f, x2, 516,0)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x0, 0x4, 3f, x2, 520,0)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xb503, 0x0, 3f, x2, 524,0)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x66666665, 0x200, 3f, x2, 528,0)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x33333332, 0x20, 3f, x2, 532,0)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaa9; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xaaaaaaa9, 0x2, 1b, x2, 536,0)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555554; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x55555554, 0x10, 3f, x2, 540,0)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x2, 0x2, 1b, x2, 544,0)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xffff; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xffff, 0x100, 3f, x2, 548,0)
+
+inst_658:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xb504, 0x200, 3f, x2, 552,0)
+
+inst_659:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x66666666; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x66666666, 0x10, 3f, x2, 556,0)
+
+inst_660:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x33333333, 0xa, 1b, x2, 560,0)
+
+inst_661:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x5, 0x200, 3f, x2, 564,0)
+
+inst_662:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0xaaaaaaaa; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0xaaaaaaaa, 0x4, 1b, x2, 568,0)
+
+inst_663:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x55555555, 0x4, 3f, x2, 572,0)
+
+inst_664:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaaa; op2val:0x3; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaaa, 0x3, 0x200, 3f, x2, 576,0)
+
+inst_665:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x10000; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x10000, 0x4, 1b, x2, 580,0)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x1, 0x4, 3f, x2, 584,0)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xb505, 0x2, 1b, x2, 588,0)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x66666667, 0xa, 1b, x2, 592,0)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x33333334, 0x8, 3f, x2, 596,0)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x6, 0x8, 3f, x2, 600,0)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xaaaaaaab, 0x4, 3f, x2, 604,0)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x55555556, 0x20, 3f, x2, 608,0)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x4, 0x6, 1b, x2, 612,0)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xfffe; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xfffe, 0x2, 3f, x2, 616,0)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x0, 0x20, 3f, x2, 620,0)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xb503, 0xa, 1b, x2, 624,0)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x66666665, 0x2, 3f, x2, 628,0)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x33333332, 0x2, 1b, x2, 632,0)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaa9; immval:0x20; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xaaaaaaa9, 0x20, 3f, x2, 636,0)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x55555554, 0xa, 1b, x2, 640,0)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x2, 0x0, 1b, x2, 644,0)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xffff; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xffff, 0x2, 3f, x2, 648,0)
+
+inst_683:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xb504, 0x2, 3f, x2, 652,0)
+
+inst_684:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x66666666, 0x40, 3f, x2, 656,0)
+
+inst_685:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x33333333, 0x2, 3f, x2, 660,0)
+
+inst_686:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x5, 0x100, 3f, x2, 664,0)
+
+inst_687:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0xaaaaaaaa; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0xaaaaaaaa, 0x556, 1b, x2, 668,0)
+
+inst_688:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x55555555, 0x400, 3f, x2, 672,0)
+
+inst_689:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555555, 0x3, 0x400, 1b, x2, 676,0)
+
+inst_690:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x10000, 0x2, 1b, x2, 680,0)
+
+inst_691:
+// rs1_val==3 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x1; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x1, 0x400, 3f, x2, 684,0)
+
+inst_692:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xb505, 0x10, 3f, x2, 688,0)
+
+inst_693:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x66666667, 0x0, 3f, x2, 692,0)
+
+inst_694:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x33333334, 0x4, 1b, x2, 696,0)
+
+inst_695:
+// rs1_val==3 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x6, 0x80, 3f, x2, 700,0)
+
+inst_696:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaab; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xaaaaaaab, 0x4, 1b, x2, 704,0)
+
+inst_697:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x55555556, 0x10, 3f, x2, 708,0)
+
+inst_698:
+// rs1_val==3 and rs2_val==4, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x4, 0x8, 1b, x2, 712,0)
+
+inst_699:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xfffe; immval:0xa; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xfffe, 0xa, 1b, x2, 716,0)
+
+inst_700:
+// rs1_val==3 and rs2_val==0, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x0, 0x400, 1b, x2, 720,0)
+
+inst_701:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xb503, 0x80, 3f, x2, 724,0)
+
+inst_702:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x66666665, 0x4, 1b, x2, 728,0)
+
+inst_703:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x33333332, 0x556, 1b, x2, 732,0)
+
+inst_704:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaa9; immval:0x10; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xaaaaaaa9, 0x10, 3f, x2, 736,0)
+
+inst_705:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x55555554, 0x400, 3f, x2, 740,0)
+
+inst_706:
+// rs1_val==3 and rs2_val==2, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x2, 0x4, 3f, x2, 744,0)
+
+inst_707:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xffff; immval:0x200; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xffff, 0x200, 3f, x2, 748,0)
+
+inst_708:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xb504, 0x40, 3f, x2, 752,0)
+
+inst_709:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x66666666, 0x8, 3f, x2, 756,0)
+
+inst_710:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x33333333, 0x80, 3f, x2, 760,0)
+
+inst_711:
+// rs1_val==3 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x5, 0x40, 3f, x2, 764,0)
+
+inst_712:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0xaaaaaaaa, 0x6, 3f, x2, 768,0)
+
+inst_713:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x55555555, 0x8, 1b, x2, 772,0)
+
+inst_714:
+// rs1_val==3 and rs2_val==3, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x3, 0x3, 0x4, 3f, x2, 776,0)
+
+inst_715:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x5, 0x8, 1b, x2, 780,0)
+
+inst_716:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0xaaaaaaaa; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0xaaaaaaaa, 0x6, 1b, x2, 784,0)
+
+inst_717:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0xaaaaaaa9; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0xaaaaaaa9, 0x55555555, 0x400, 3f, x2, 788,0)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x10000; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x10000, 0x2, 1b, x2, 792,0)
+
+inst_719:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x1; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x1, 0x556, 1b, x2, 796,0)
+
+inst_720:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xb505, 0x0, 1b, x2, 800,0)
+
+inst_721:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x100; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x66666667, 0x100, 3f, x2, 804,0)
+
+inst_722:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x33333334, 0x6, 3f, x2, 808,0)
+
+inst_723:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x6, 0x2, 1b, x2, 812,0)
+
+inst_724:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0xaaaaaaab; immval:0x556; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0xaaaaaaab, 0x556, 1b, x2, 816,0)
+
+inst_725:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x55555554, 0x55555556, 0x80, 3f, x2, 820,0)
+
+inst_726:
+// rs2_val == 4294705151, 
+// opcode: bltu, op1:x10; op2:x11; op1val:0x9; op2val:0xfffbffff; immval:0x40; align:0
+TEST_BRANCH_OP(bltu, x3, x10, x11, 0x9, 0xfffbffff, 0x40, 3f, x2, 824,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 207*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S
new file mode 100644
index 000000000..92ccd2b4f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S
@@ -0,0 +1,3011 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the bne instruction of the RISC-V E extension for the bne covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",bne)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 == rs2, rs1==x14, rs2==x14, rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0, rs2_val == -268435457, rs1_val == -33554433
+// opcode: bne, op1:x14; op2:x14; op1val:-0x2000001; op2val:-0x2000001; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x3, x14, x14, -0x2000001, -0x2000001, 0x8, 1b, x2, 0,0)
+
+inst_1:
+// rs1 != rs2, rs1==x9, rs2==x10, rs2_val == 2147483647, 
+// opcode: bne, op1:x9; op2:x10; op1val:0x9; op2val:0x7fffffff; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x3, x9, x10, 0x9, 0x7fffffff, 0x6, 1b, x2, 4,0)
+
+inst_2:
+// rs1==x12, rs2==x4, rs2_val == -1073741825, rs1_val == -257, rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x12; op2:x4; op1val:-0x101; op2val:-0x40000001; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x3, x12, x4, -0x101, -0x40000001, 0x10, 3f, x2, 8,0)
+
+inst_3:
+// rs1==x6, rs2==x5, rs2_val == -536870913, rs1_val == -2097153
+// opcode: bne, op1:x6; op2:x5; op1val:-0x200001; op2val:-0x20000001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x3, x6, x5, -0x200001, -0x20000001, 0x2, 1b, x2, 12,0)
+
+inst_4:
+// rs1==x13, rs2==x0, rs2_val == -134217729, rs1_val == -16777217
+// opcode: bne, op1:x13; op2:x0; op1val:-0x1000001; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x3, x13, x0, -0x1000001, 0x0, 0x6, 1b, x2, 16,0)
+
+inst_5:
+// rs1==x7, rs2==x8, rs2_val == -67108865, rs1_val == 64, rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x7; op2:x8; op1val:0x40; op2val:-0x4000001; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x3, x7, x8, 0x40, -0x4000001, 0x100, 3f, x2, 20,0)
+
+inst_6:
+// rs1==x1, rs2==x13, rs2_val == -33554433, rs1_val == 4194304
+// opcode: bne, op1:x1; op2:x13; op1val:0x400000; op2val:-0x2000001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x3, x1, x13, 0x400000, -0x2000001, 0x2, 1b, x2, 24,0)
+
+inst_7:
+// rs1==x5, rs2==x11, rs2_val == -16777217, rs1_val == 2147483647
+// opcode: bne, op1:x5; op2:x11; op1val:0x7fffffff; op2val:-0x1000001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x13, x5, x11, 0x7fffffff, -0x1000001, 0x2, 3f, x2, 28,0)
+RVTEST_SIGBASE( x5,signature_x5_0)
+
+inst_8:
+// rs1==x0, rs2==x1, rs2_val == -8388609, rs1_val == 8192
+// opcode: bne, op1:x0; op2:x1; op1val:0x0; op2val:-0x800001; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x13, x0, x1, 0x0, -0x800001, 0x4, 1b, x5, 0,0)
+
+inst_9:
+// rs1==x4, rs2==x9, rs2_val == -4194305, rs1_val == -16385
+// opcode: bne, op1:x4; op2:x9; op1val:-0x4001; op2val:-0x400001; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x13, x4, x9, -0x4001, -0x400001, 0x10, 3f, x5, 4,0)
+
+inst_10:
+// rs1==x11, rs2==x15, rs2_val == -2097153, rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0, rs1_val == -67108865
+// opcode: bne, op1:x11; op2:x15; op1val:-0x4000001; op2val:-0x200001; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x13, x11, x15, -0x4000001, -0x200001, 0x80, 3f, x5, 8,0)
+
+inst_11:
+// rs1==x15, rs2==x3, rs2_val == -1048577, 
+// opcode: bne, op1:x15; op2:x3; op1val:0x6; op2val:-0x100001; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x13, x15, x3, 0x6, -0x100001, 0x6, 1b, x5, 12,0)
+
+inst_12:
+// rs1==x10, rs2==x7, rs2_val == -524289, rs1_val == -4097
+// opcode: bne, op1:x10; op2:x7; op1val:-0x1001; op2val:-0x80001; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x13, x10, x7, -0x1001, -0x80001, 0x556, 1b, x5, 16,0)
+
+inst_13:
+// rs1==x3, rs2==x2, rs2_val == -262145, 
+// opcode: bne, op1:x3; op2:x2; op1val:0xb505; op2val:-0x40001; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x13, x3, x2, 0xb505, -0x40001, 0x0, 3f, x5, 20,0)
+
+inst_14:
+// rs1==x2, rs2==x12, rs2_val == -131073, 
+// opcode: bne, op1:x2; op2:x12; op1val:-0x6; op2val:-0x20001; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x13, x2, x12, -0x6, -0x20001, 0x100, 3f, x5, 24,0)
+
+inst_15:
+// rs1==x8, rs2==x6, rs2_val == -65537, 
+// opcode: bne, op1:x8; op2:x6; op1val:0x66666666; op2val:-0x10001; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x13, x8, x6, 0x66666666, -0x10001, 0x200, 3f, x5, 28,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_16:
+// rs2_val == -32769, rs1_val == -2147483648
+// opcode: bne, op1:x10; op2:x11; op1val:-0x80000000; op2val:-0x8001; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x80000000, -0x8001, 0x400, 3f, x1, 0,0)
+
+inst_17:
+// rs2_val == -16385, rs1_val == 32
+// opcode: bne, op1:x10; op2:x11; op1val:0x20; op2val:-0x4001; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x20, -0x4001, 0x6, 1b, x1, 4,0)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:-0x2001; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, -0x2001, 0x8, 3f, x1, 8,0)
+
+inst_19:
+// rs2_val == -4097, rs1_val == 2048
+// opcode: bne, op1:x10; op2:x11; op1val:0x800; op2val:-0x1001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x800, -0x1001, 0x2, 3f, x1, 12,0)
+
+inst_20:
+// rs2_val == -2049, rs1_val == -65537
+// opcode: bne, op1:x10; op2:x11; op1val:-0x10001; op2val:-0x801; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x10001, -0x801, 0x0, 3f, x1, 16,0)
+
+inst_21:
+// rs2_val == -1025, rs1_val == -262145
+// opcode: bne, op1:x10; op2:x11; op1val:-0x40001; op2val:-0x401; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x40001, -0x401, 0x0, 3f, x1, 20,0)
+
+inst_22:
+// rs2_val == -513, rs1_val == -268435457
+// opcode: bne, op1:x10; op2:x11; op1val:-0x10000001; op2val:-0x201; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x10000001, -0x201, 0x2, 3f, x1, 24,0)
+
+inst_23:
+// rs2_val == -257, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3fffffff; op2val:-0x101; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3fffffff, -0x101, 0x8, 3f, x1, 28,0)
+
+inst_24:
+// rs2_val == -129, rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x81; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0x81, 0x4, 1b, x1, 32,0)
+
+inst_25:
+// rs2_val == -65, rs1_val == -2049
+// opcode: bne, op1:x10; op2:x11; op1val:-0x801; op2val:-0x41; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x801, -0x41, 0x8, 3f, x1, 36,0)
+
+inst_26:
+// rs2_val == -33, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x40000000; op2val:-0x21; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x40000000, -0x21, 0x20, 3f, x1, 40,0)
+
+inst_27:
+// rs2_val == -17, rs1_val == -1073741825
+// opcode: bne, op1:x10; op2:x11; op1val:-0x40000001; op2val:-0x11; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x40000001, -0x11, 0x400, 3f, x1, 44,0)
+
+inst_28:
+// rs2_val == -9, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x9; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0x9, 0x100, 3f, x1, 48,0)
+
+inst_29:
+// rs2_val == -5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x1001; op2val:-0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x1001, -0x5, 0x4, 1b, x1, 52,0)
+
+inst_30:
+// rs2_val == -3, rs1_val == 134217728
+// opcode: bne, op1:x10; op2:x11; op1val:0x8000000; op2val:-0x3; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x8000000, -0x3, 0x556, 1b, x1, 56,0)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x101; op2val:-0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x101, -0x2, 0x2, 3f, x1, 60,0)
+
+inst_32:
+// rs1_val == -536870913, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x20000001; op2val:-0x1001; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x20000001, -0x1001, 0x80, 3f, x1, 64,0)
+
+inst_33:
+// rs1_val == -134217729, rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0, rs2_val == 2
+// opcode: bne, op1:x10; op2:x11; op1val:-0x8000001; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x8000001, 0x2, 0x0, 1b, x1, 68,0)
+
+inst_34:
+// rs1_val == -8388609, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x800001; op2val:-0x11; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x800001, -0x11, 0x200, 3f, x1, 72,0)
+
+inst_35:
+// rs1_val == -4194305, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x400001; op2val:-0x20000001; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x400001, -0x20000001, 0x40, 3f, x1, 76,0)
+
+inst_36:
+// rs1_val == -1048577, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x100001; op2val:-0x800001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x100001, -0x800001, 0x2, 1b, x1, 80,0)
+
+inst_37:
+// rs1_val == -524289, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x80001; op2val:-0x200001; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x80001, -0x200001, 0x10, 3f, x1, 84,0)
+
+inst_38:
+// rs1_val == -131073, rs2_val == 1024
+// opcode: bne, op1:x10; op2:x11; op1val:-0x20001; op2val:0x400; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x20001, 0x400, 0x10, 3f, x1, 88,0)
+
+inst_39:
+// rs1_val == -32769, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x8001; op2val:-0x80001; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x8001, -0x80001, 0x4, 3f, x1, 92,0)
+
+inst_40:
+// rs1_val == -8193, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x2001; op2val:-0x100001; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x2001, -0x100001, 0x2, 1b, x1, 96,0)
+
+inst_41:
+// rs1_val == -1025, rs2_val == -1431655766
+// opcode: bne, op1:x10; op2:x11; op1val:-0x401; op2val:-0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x401, -0x55555556, 0x556, 1b, x1, 100,0)
+
+inst_42:
+// rs1_val == -513, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x201; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x201, 0x6, 0x20, 3f, x1, 104,0)
+
+inst_43:
+// rs1_val == -129, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x81; op2val:-0x400001; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x81, -0x400001, 0x6, 1b, x1, 108,0)
+
+inst_44:
+// rs1_val == -65, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x41; op2val:-0x1001; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x41, -0x1001, 0x200, 3f, x1, 112,0)
+
+inst_45:
+// rs1_val == -33, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x21; op2val:-0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x21, -0x55555556, 0x80, 3f, x1, 116,0)
+
+inst_46:
+// rs1_val == -17, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x11; op2val:-0x101; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x11, -0x101, 0x6, 1b, x1, 120,0)
+
+inst_47:
+// rs1_val == -9, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x9; op2val:-0x40001; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x9, -0x40001, 0x400, 1b, x1, 124,0)
+
+inst_48:
+// rs1_val == -5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x5; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x5, 0x6, 0x80, 3f, x1, 128,0)
+
+inst_49:
+// rs1_val == -3, rs2_val == 1431655765
+// opcode: bne, op1:x10; op2:x11; op1val:-0x3; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x3, 0x55555555, 0xa, 1b, x1, 132,0)
+
+inst_50:
+// rs1_val == -2, rs2_val == 524288
+// opcode: bne, op1:x10; op2:x11; op1val:-0x2; op2val:0x80000; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x2, 0x80000, 0x4, 3f, x1, 136,0)
+
+inst_51:
+// rs2_val == -2147483648, rs1_val == -1431655766
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x80000000; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, -0x80000000, 0x2, 1b, x1, 140,0)
+
+inst_52:
+// rs2_val == 1073741824, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x8001; op2val:0x40000000; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x8001, 0x40000000, 0x80, 3f, x1, 144,0)
+
+inst_53:
+// rs2_val == 536870912, rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x20000000; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x20000000, 0x8, 1b, x1, 148,0)
+
+inst_54:
+// rs2_val == 268435456, rs1_val == 16384
+// opcode: bne, op1:x10; op2:x11; op1val:0x4000; op2val:0x10000000; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4000, 0x10000000, 0x2, 3f, x1, 152,0)
+
+inst_55:
+// rs2_val == 134217728, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x8000000; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x8000000, 0x2, 3f, x1, 156,0)
+
+inst_56:
+// rs2_val == 67108864, rs1_val == 8
+// opcode: bne, op1:x10; op2:x11; op1val:0x8; op2val:0x4000000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x8, 0x4000000, 0xa, 1b, x1, 160,0)
+
+inst_57:
+// rs2_val == 33554432, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2000000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x2000000, 0xa, 1b, x1, 164,0)
+
+inst_58:
+// rs2_val == 16777216, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x4000001; op2val:0x1000000; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x4000001, 0x1000000, 0x2, 1b, x1, 168,0)
+
+inst_59:
+// rs2_val == 8388608, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x20; op2val:0x800000; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x20, 0x800000, 0x8, 3f, x1, 172,0)
+
+inst_60:
+// rs2_val == 4194304, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x6; op2val:0x400000; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x6, 0x400000, 0x200, 3f, x1, 176,0)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x200000; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x200000, 0x20, 3f, x1, 180,0)
+
+inst_62:
+// rs2_val == 1048576, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x100000; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x100000, 0x0, 3f, x1, 184,0)
+
+inst_63:
+// rs2_val == 262144, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2000; op2val:0x40000; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2000, 0x40000, 0x80, 3f, x1, 188,0)
+
+inst_64:
+// rs2_val == 131072, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x9; op2val:0x20000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x9, 0x20000, 0xa, 1b, x1, 192,0)
+
+inst_65:
+// rs2_val == 65536, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x10000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x10000, 0xa, 1b, x1, 196,0)
+
+inst_66:
+// rs2_val == 32768, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x801; op2val:0x8000; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x801, 0x8000, 0x0, 1b, x1, 200,0)
+
+inst_67:
+// rs2_val == 16384, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3fffffff; op2val:0x4000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3fffffff, 0x4000, 0xa, 1b, x1, 204,0)
+
+inst_68:
+// rs2_val == 8192, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x2000001; op2val:0x2000; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x2000001, 0x2000, 0xa, 1b, x1, 208,0)
+
+inst_69:
+// rs2_val == 4096, rs1_val == 32768
+// opcode: bne, op1:x10; op2:x11; op1val:0x8000; op2val:0x1000; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x8000, 0x1000, 0x6, 3f, x1, 212,0)
+
+inst_70:
+// rs2_val == 2048, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x40; op2val:0x800; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x40, 0x800, 0x6, 3f, x1, 216,0)
+
+inst_71:
+// rs2_val == 512, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x200; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x200, 0x400, 1b, x1, 220,0)
+
+inst_72:
+// rs2_val == 256, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x100; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x100, 0x200, 3f, x1, 224,0)
+
+inst_73:
+// rs2_val == 128, rs1_val == 65536
+// opcode: bne, op1:x10; op2:x11; op1val:0x10000; op2val:0x80; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x10000, 0x80, 0x80, 3f, x1, 228,0)
+
+inst_74:
+// rs2_val == 64, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x9; op2val:0x40; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x9, 0x40, 0x8, 3f, x1, 232,0)
+
+inst_75:
+// rs2_val == 32, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x201; op2val:0x20; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x201, 0x20, 0x40, 3f, x1, 236,0)
+
+inst_76:
+// rs2_val == 16, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x2000001; op2val:0x10; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x2000001, 0x10, 0x400, 3f, x1, 240,0)
+
+inst_77:
+// rs2_val == 8, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x8; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x8, 0x80, 3f, x1, 244,0)
+
+inst_78:
+// rs2_val == 4, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x80000000; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x80000000, 0x4, 0x2, 1b, x1, 248,0)
+
+inst_79:
+// rs2_val == 1, rs1_val == 2
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x1; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x1, 0x4, 3f, x1, 252,0)
+
+inst_80:
+// rs1_val == 1073741824, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x40000000; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x40000000, 0x33333333, 0x2, 1b, x1, 256,0)
+
+inst_81:
+// rs1_val == 536870912, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x20000000; op2val:-0x9; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x20000000, -0x9, 0x4, 3f, x1, 260,0)
+
+inst_82:
+// rs1_val == 268435456, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x10000000; op2val:0x4; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x10000000, 0x4, 0x10, 3f, x1, 264,0)
+
+inst_83:
+// rs1_val == 67108864, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4000000; op2val:0x800000; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4000000, 0x800000, 0x200, 3f, x1, 268,0)
+
+inst_84:
+// rs1_val == 33554432, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2000000; op2val:0x3fffffff; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2000000, 0x3fffffff, 0x2, 3f, x1, 272,0)
+
+inst_85:
+// rs1_val == 16777216, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x1000000; op2val:-0x100001; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x1000000, -0x100001, 0x0, 3f, x1, 276,0)
+
+inst_86:
+// rs1_val == 8388608, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x800000; op2val:0x1000; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x800000, 0x1000, 0x8, 1b, x1, 280,0)
+
+inst_87:
+// rs1_val == 2097152, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x200000; op2val:-0x401; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x200000, -0x401, 0x200, 3f, x1, 284,0)
+
+inst_88:
+// rs1_val == 1048576, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x100000; op2val:-0x1; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x100000, -0x1, 0x8, 3f, x1, 288,0)
+
+inst_89:
+// rs1_val == 524288, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x80000; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x80000, 0x0, 0x2, 3f, x1, 292,0)
+
+inst_90:
+// rs1_val == 262144, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x40000; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x40000, 0x33333333, 0x0, 3f, x1, 296,0)
+
+inst_91:
+// rs1_val == 131072, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x20000; op2val:-0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x20000, -0x5, 0x100, 3f, x1, 300,0)
+
+inst_92:
+// rs1_val == 4096, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x1000; op2val:0x100000; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x1000, 0x100000, 0x20, 3f, x1, 304,0)
+
+inst_93:
+// rs1_val == 1024, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x400; op2val:0x80; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x400, 0x80, 0x400, 1b, x1, 308,0)
+
+inst_94:
+// rs1_val == 512, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x200; op2val:-0x9; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x200, -0x9, 0x0, 3f, x1, 312,0)
+
+inst_95:
+// rs1_val == 256, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x100; op2val:0x8000; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x100, 0x8000, 0x556, 1b, x1, 316,0)
+
+inst_96:
+// rs1_val == 128, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x80; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x80, 0x55555556, 0x20, 3f, x1, 320,0)
+
+inst_97:
+// rs1_val == 16, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x10; op2val:-0x81; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x10, -0x81, 0x4, 1b, x1, 324,0)
+
+inst_98:
+// rs1_val == 4, rs1_val==4 and rs2_val==0
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x0, 0x556, 1b, x1, 328,0)
+
+inst_99:
+// rs1_val == 1, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x1; op2val:-0x4000001; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x1, -0x4000001, 0x200, 3f, x1, 332,0)
+
+inst_100:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0xb505, 0xa, 1b, x1, 336,0)
+
+inst_101:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, -0xb503, 0x4, 1b, x1, 340,0)
+
+inst_102:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x66666667, 0x200, 3f, x1, 344,0)
+
+inst_103:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333334; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x33333334, 0x200, 3f, x1, 348,0)
+
+inst_104:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x6, 0x4, 3f, x1, 352,0)
+
+inst_105:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, -0x55555555, 0x2, 3f, x1, 356,0)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x55555556, 0x2, 3f, x1, 360,0)
+
+inst_107:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x4, 0x6, 3f, x1, 364,0)
+
+inst_108:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0xb503, 0x556, 1b, x1, 368,0)
+
+inst_109:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x0, 0x6, 1b, x1, 372,0)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x66666665, 0x6, 3f, x1, 376,0)
+
+inst_111:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x33333332, 0x400, 3f, x1, 380,0)
+
+inst_112:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555554; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x55555554, 0x40, 3f, x1, 384,0)
+
+inst_113:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x2, 0x20, 3f, x1, 388,0)
+
+inst_114:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0xb504, 0x200, 3f, x1, 392,0)
+
+inst_115:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, -0xb504, 0x6, 3f, x1, 396,0)
+
+inst_116:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x66666666, 0x100, 3f, x1, 400,0)
+
+inst_117:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x33333333, 0x10, 3f, x1, 404,0)
+
+inst_118:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x5, 0x2, 3f, x1, 408,0)
+
+inst_119:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, -0x55555556, 0x6, 1b, x1, 412,0)
+
+inst_120:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x55555555, 0xa, 1b, x1, 416,0)
+
+inst_121:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb505; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb505, 0x3, 0x6, 3f, x1, 420,0)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb505; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0xb505, 0x4, 1b, x1, 424,0)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==-46339, rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, -0xb503, 0x400, 3f, x1, 428,0)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666667; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x66666667, 0x100, 3f, x1, 432,0)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x33333334, 0x4, 3f, x1, 436,0)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x6, 0x10, 3f, x1, 440,0)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, -0x55555555, 0x556, 1b, x1, 444,0)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x55555556, 0x4, 1b, x1, 448,0)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x4, 0x400, 3f, x1, 452,0)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0xb503, 0x400, 3f, x1, 456,0)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x0, 0x4, 3f, x1, 460,0)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x66666665, 0x6, 1b, x1, 464,0)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x33333332, 0x6, 1b, x1, 468,0)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555554; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x55555554, 0x2, 1b, x1, 472,0)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x2, 0x400, 3f, x1, 476,0)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0xb504, 0x2, 1b, x1, 480,0)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, -0xb504, 0x400, 3f, x1, 484,0)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x66666666, 0x4, 1b, x1, 488,0)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x33333333, 0x2, 3f, x1, 492,0)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x5, 0x400, 3f, x1, 496,0)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, -0x55555556, 0x6, 1b, x1, 500,0)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x55555555, 0x20, 3f, x1, 504,0)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb503; op2val:0x3; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb503, 0x3, 0x556, 1b, x1, 508,0)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0xb505, 0x6, 3f, x1, 512,0)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, -0xb503, 0x6, 1b, x1, 516,0)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x66666667, 0x2, 1b, x1, 520,0)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x33333334, 0x0, 3f, x1, 524,0)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x6, 0x0, 3f, x1, 528,0)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, -0x55555555, 0x10, 3f, x1, 532,0)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x55555556, 0x8, 1b, x1, 536,0)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x4, 0x4, 3f, x1, 540,0)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0xb503, 0x4, 1b, x1, 544,0)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x0; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x0, 0x556, 1b, x1, 548,0)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x66666665, 0x2, 3f, x1, 552,0)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x33333332, 0x20, 3f, x1, 556,0)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555554; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x55555554, 0x8, 3f, x1, 560,0)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x2, 0x6, 3f, x1, 564,0)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0xb504, 0x20, 3f, x1, 568,0)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, -0xb504, 0x2, 1b, x1, 572,0)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x66666666, 0x100, 3f, x1, 576,0)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x33333333, 0x8, 3f, x1, 580,0)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x5; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x5, 0x400, 3f, x1, 584,0)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:-0x55555556; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, -0x55555556, 0x40, 3f, x1, 588,0)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x55555555, 0x4, 3f, x1, 592,0)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666667; op2val:0x3; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666667, 0x3, 0x2, 1b, x1, 596,0)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb505; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0xb505, 0x556, 1b, x1, 600,0)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb503; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, -0xb503, 0x100, 3f, x1, 604,0)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x66666667, 0x200, 3f, x1, 608,0)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x33333334, 0x100, 3f, x1, 612,0)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x6, 0x0, 1b, x1, 616,0)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, -0x55555555, 0x2, 3f, x1, 620,0)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x55555556, 0x8, 1b, x1, 624,0)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x4, 0x556, 1b, x1, 628,0)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0xb503, 0x40, 3f, x1, 632,0)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x0; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x0, 0x2, 1b, x1, 636,0)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666665; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x66666665, 0x40, 3f, x1, 640,0)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333332; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x33333332, 0x200, 3f, x1, 644,0)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555554; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x55555554, 0x6, 1b, x1, 648,0)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x2; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x2, 0x556, 1b, x1, 652,0)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0xb504, 0x2, 1b, x1, 656,0)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:-0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, -0xb504, 0x8, 3f, x1, 660,0)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x66666666, 0x0, 3f, x1, 664,0)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x33333333, 0x4, 3f, x1, 668,0)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x5; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x5, 0x6, 3f, x1, 672,0)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, -0x55555556, 0x200, 3f, x1, 676,0)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x55555555, 0x0, 3f, x1, 680,0)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333334; op2val:0x3; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333334, 0x3, 0x80, 3f, x1, 684,0)
+
+inst_188:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0xb505, 0x10, 3f, x1, 688,0)
+
+inst_189:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:-0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, -0xb503, 0x20, 3f, x1, 692,0)
+
+inst_190:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x66666667, 0x2, 3f, x1, 696,0)
+
+inst_191:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x33333334; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x33333334, 0x40, 3f, x1, 700,0)
+
+inst_192:
+// rs1_val==6 and rs2_val==6, rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x6, 0x4, 1b, x1, 704,0)
+
+inst_193:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, -0x55555555, 0x0, 1b, x1, 708,0)
+
+inst_194:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x55555556, 0x2, 1b, x1, 712,0)
+
+inst_195:
+// rs1_val==6 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x4; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x4, 0x20, 3f, x1, 716,0)
+
+inst_196:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0xb503, 0x400, 1b, x1, 720,0)
+
+inst_197:
+// rs1_val==6 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x0; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x0, 0xa, 1b, x1, 724,0)
+
+inst_198:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x66666665, 0x4, 1b, x1, 728,0)
+
+inst_199:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x33333332, 0x0, 3f, x1, 732,0)
+
+inst_200:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x55555554, 0x4, 1b, x1, 736,0)
+
+inst_201:
+// rs1_val==6 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x2, 0x80, 3f, x1, 740,0)
+
+inst_202:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0xb504, 0x4, 1b, x1, 744,0)
+
+inst_203:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, -0xb504, 0x6, 3f, x1, 748,0)
+
+inst_204:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x66666666, 0x2, 1b, x1, 752,0)
+
+inst_205:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x33333333, 0x8, 3f, x1, 756,0)
+
+inst_206:
+// rs1_val==6 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x5; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x5, 0x8, 3f, x1, 760,0)
+
+inst_207:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:-0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, -0x55555556, 0x80, 3f, x1, 764,0)
+
+inst_208:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x55555555, 0x556, 1b, x1, 768,0)
+
+inst_209:
+// rs1_val==6 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x6; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x6, 0x3, 0x6, 3f, x1, 772,0)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0xb505, 0x2, 3f, x1, 776,0)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb503; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, -0xb503, 0x40, 3f, x1, 780,0)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666667; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x66666667, 0xa, 1b, x1, 784,0)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x33333334, 0x400, 1b, x1, 788,0)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x6; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x6, 0x20, 3f, x1, 792,0)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555555; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, -0x55555555, 0x556, 1b, x1, 796,0)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x55555556, 0x0, 3f, x1, 800,0)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x4, 0x40, 3f, x1, 804,0)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb503; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0xb503, 0x556, 1b, x1, 808,0)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x0, 0x4, 3f, x1, 812,0)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666665; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x66666665, 0x80, 3f, x1, 816,0)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x33333332, 0x80, 3f, x1, 820,0)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x55555554, 0x0, 3f, x1, 824,0)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x2, 0x10, 3f, x1, 828,0)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0xb504, 0x8, 3f, x1, 832,0)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, -0xb504, 0x2, 3f, x1, 836,0)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x66666666; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x66666666, 0x20, 3f, x1, 840,0)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x33333333, 0x6, 1b, x1, 844,0)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x5, 0x2, 3f, x1, 848,0)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, -0x55555556, 0x8, 3f, x1, 852,0)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x55555555, 0x10, 3f, x1, 856,0)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555555; op2val:0x3; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555555, 0x3, 0x20, 3f, x1, 860,0)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0xb505, 0x10, 3f, x1, 864,0)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, -0xb503, 0x2, 1b, x1, 868,0)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x66666667, 0x0, 1b, x1, 872,0)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x33333334, 0x556, 1b, x1, 876,0)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x6, 0x556, 1b, x1, 880,0)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, -0x55555555, 0xa, 1b, x1, 884,0)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x55555556, 0x6, 3f, x1, 888,0)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x4, 0x40, 3f, x1, 892,0)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0xb503, 0x4, 1b, x1, 896,0)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x0, 0x400, 1b, x1, 900,0)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x66666665, 0x2, 3f, x1, 904,0)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x33333332, 0x8, 3f, x1, 908,0)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x55555554, 0x0, 1b, x1, 912,0)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x2, 0x8, 1b, x1, 916,0)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0xb504; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0xb504, 0x100, 3f, x1, 920,0)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, -0xb504, 0x10, 3f, x1, 924,0)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x66666666, 0x8, 1b, x1, 928,0)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x33333333; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x33333333, 0x20, 3f, x1, 932,0)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x5, 0x4, 3f, x1, 936,0)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:-0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, -0x55555556, 0x400, 3f, x1, 940,0)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x55555555; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x55555555, 0x6, 3f, x1, 944,0)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555556; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555556, 0x3, 0x400, 1b, x1, 948,0)
+
+inst_254:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0xb505, 0x2, 1b, x1, 952,0)
+
+inst_255:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, -0xb503, 0x0, 3f, x1, 956,0)
+
+inst_256:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x66666667; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x66666667, 0x2, 1b, x1, 960,0)
+
+inst_257:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x33333334, 0x0, 3f, x1, 964,0)
+
+inst_258:
+// rs1_val==4 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x6, 0x4, 3f, x1, 968,0)
+
+inst_259:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, -0x55555555, 0x0, 1b, x1, 972,0)
+
+inst_260:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x55555556, 0x0, 3f, x1, 976,0)
+
+inst_261:
+// rs1_val==4 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x4, 0x0, 3f, x1, 980,0)
+
+inst_262:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0xb503, 0x8, 3f, x1, 984,0)
+
+inst_263:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x66666665, 0x8, 1b, x1, 988,0)
+
+inst_264:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x33333332, 0x40, 3f, x1, 992,0)
+
+inst_265:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x55555554, 0x556, 1b, x1, 996,0)
+
+inst_266:
+// rs1_val==4 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x2, 0x8, 1b, x1, 1000,0)
+
+inst_267:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0xb504, 0x20, 3f, x1, 1004,0)
+
+inst_268:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:-0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, -0xb504, 0x80, 3f, x1, 1008,0)
+
+inst_269:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x66666666, 0x556, 1b, x1, 1012,0)
+
+inst_270:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x33333333, 0x4, 1b, x1, 1016,0)
+
+inst_271:
+// rs1_val==4 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x5, 0x100, 3f, x1, 1020,0)
+
+inst_272:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:-0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, -0x55555556, 0x20, 3f, x1, 1024,0)
+
+inst_273:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x55555555, 0x8, 3f, x1, 1028,0)
+
+inst_274:
+// rs1_val==4 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x4; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x4, 0x3, 0x10, 3f, x1, 1032,0)
+
+inst_275:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0xb505, 0x80, 3f, x1, 1036,0)
+
+inst_276:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, -0xb503, 0x8, 1b, x1, 1040,0)
+
+inst_277:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x66666667, 0x400, 3f, x1, 1044,0)
+
+inst_278:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x33333334, 0x2, 3f, x1, 1048,0)
+
+inst_279:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x6, 0x10, 3f, x1, 1052,0)
+
+inst_280:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555555; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, -0x55555555, 0x10, 3f, x1, 1056,0)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555556; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x55555556, 0x80, 3f, x1, 1060,0)
+
+inst_282:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x4, 0x400, 3f, x1, 1064,0)
+
+inst_283:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0xb503; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0xb503, 0xa, 1b, x1, 1068,0)
+
+inst_284:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x0, 0x40, 3f, x1, 1072,0)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x66666665, 0x6, 3f, x1, 1076,0)
+
+inst_286:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333332; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x33333332, 0x0, 3f, x1, 1080,0)
+
+inst_287:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x55555554, 0x556, 1b, x1, 1084,0)
+
+inst_288:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x2; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x2, 0x10, 3f, x1, 1088,0)
+
+inst_289:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0xb504; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0xb504, 0x20, 3f, x1, 1092,0)
+
+inst_290:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, -0xb504, 0x2, 1b, x1, 1096,0)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x66666666, 0x556, 1b, x1, 1100,0)
+
+inst_292:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x33333333, 0x4, 1b, x1, 1104,0)
+
+inst_293:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x5, 0x20, 3f, x1, 1108,0)
+
+inst_294:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, -0x55555556, 0x8, 3f, x1, 1112,0)
+
+inst_295:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x55555555, 0x2, 3f, x1, 1116,0)
+
+inst_296:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb503; op2val:0x3; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb503, 0x3, 0x0, 3f, x1, 1120,0)
+
+inst_297:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0xb505; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0xb505, 0x0, 3f, x1, 1124,0)
+
+inst_298:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:-0xb503; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, -0xb503, 0x80, 3f, x1, 1128,0)
+
+inst_299:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x66666667; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x66666667, 0x10, 3f, x1, 1132,0)
+
+inst_300:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x33333334; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x33333334, 0x80, 3f, x1, 1136,0)
+
+inst_301:
+// rs1_val==0 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x6, 0x4, 1b, x1, 1140,0)
+
+inst_302:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, -0x55555555, 0x0, 1b, x1, 1144,0)
+
+inst_303:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x55555556, 0x0, 3f, x1, 1148,0)
+
+inst_304:
+// rs1_val==0 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x4; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x4, 0x556, 1b, x1, 1152,0)
+
+inst_305:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0xb503, 0x400, 3f, x1, 1156,0)
+
+inst_306:
+// rs1_val==0 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x0, 0x8, 3f, x1, 1160,0)
+
+inst_307:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x66666665, 0x2, 1b, x1, 1164,0)
+
+inst_308:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x33333332; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x33333332, 0x400, 3f, x1, 1168,0)
+
+inst_309:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x55555554, 0x4, 3f, x1, 1172,0)
+
+inst_310:
+// rs1_val==0 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x2; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x2, 0x8, 3f, x1, 1176,0)
+
+inst_311:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0xb504, 0x2, 1b, x1, 1180,0)
+
+inst_312:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:-0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, -0xb504, 0x400, 1b, x1, 1184,0)
+
+inst_313:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x66666666, 0x8, 1b, x1, 1188,0)
+
+inst_314:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x33333333, 0x200, 3f, x1, 1192,0)
+
+inst_315:
+// rs1_val==0 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x5, 0x2, 3f, x1, 1196,0)
+
+inst_316:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:-0x55555556; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, -0x55555556, 0x556, 1b, x1, 1200,0)
+
+inst_317:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x55555555, 0x0, 1b, x1, 1204,0)
+
+inst_318:
+// rs1_val==0 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x0; op2val:0x3; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x0, 0x3, 0xa, 1b, x1, 1208,0)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0xb505, 0x2, 3f, x1, 1212,0)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, -0xb503, 0x20, 3f, x1, 1216,0)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x66666667, 0x400, 3f, x1, 1220,0)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x33333334, 0x4, 1b, x1, 1224,0)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x6; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x6, 0x4, 3f, x1, 1228,0)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, -0x55555555, 0x0, 3f, x1, 1232,0)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x55555556, 0x6, 3f, x1, 1236,0)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x4, 0x8, 3f, x1, 1240,0)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0xb503, 0x6, 3f, x1, 1244,0)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x0, 0x0, 3f, x1, 1248,0)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x0; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x0, 0x0, 3f, x1, 1252,0)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666665; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x66666665, 0x400, 3f, x1, 1256,0)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333332; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x33333332, 0x100, 3f, x1, 1260,0)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555554; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x55555554, 0xa, 1b, x1, 1264,0)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x2; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x2, 0x2, 3f, x1, 1268,0)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0xb504, 0x400, 1b, x1, 1272,0)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, -0xb504, 0x0, 1b, x1, 1276,0)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x66666666, 0x4, 3f, x1, 1280,0)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333333; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x33333333, 0xa, 1b, x1, 1284,0)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x5; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x5, 0x2, 1b, x1, 1288,0)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, -0x55555556, 0x4, 3f, x1, 1292,0)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x55555555, 0x4, 1b, x1, 1296,0)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x3, 0x4, 1b, x1, 1300,0)
+
+inst_342:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0xb505; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0xb505, 0x20, 3f, x1, 1304,0)
+
+inst_343:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, -0xb503, 0x400, 3f, x1, 1308,0)
+
+inst_344:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x66666667; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x66666667, 0x6, 1b, x1, 1312,0)
+
+inst_345:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x33333334, 0x100, 3f, x1, 1316,0)
+
+inst_346:
+// rs1_val==5 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x6, 0x80, 3f, x1, 1320,0)
+
+inst_347:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555555; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, -0x55555555, 0x8, 3f, x1, 1324,0)
+
+inst_348:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x55555556, 0x10, 3f, x1, 1328,0)
+
+inst_349:
+// rs1_val==5 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x4, 0x400, 1b, x1, 1332,0)
+
+inst_350:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0xb503, 0x8, 3f, x1, 1336,0)
+
+inst_351:
+// rs1_val==5 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x0; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x0, 0x8, 1b, x1, 1340,0)
+
+inst_352:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x66666665, 0x2, 1b, x1, 1344,0)
+
+inst_353:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x33333332, 0x6, 3f, x1, 1348,0)
+
+inst_354:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x55555554; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x55555554, 0x100, 3f, x1, 1352,0)
+
+inst_355:
+// rs1_val==5 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x2, 0x6, 3f, x1, 1356,0)
+
+inst_356:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0xb504, 0x2, 1b, x1, 1360,0)
+
+inst_357:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, -0xb504, 0x6, 1b, x1, 1364,0)
+
+inst_358:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x66666666; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x66666666, 0x556, 1b, x1, 1368,0)
+
+inst_359:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x33333333; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x33333333, 0x4, 1b, x1, 1372,0)
+
+inst_360:
+// rs1_val==5 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x5, 0x20, 3f, x1, 1376,0)
+
+inst_361:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, -0x55555556, 0x0, 3f, x1, 1380,0)
+
+inst_362:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x55555555, 0x4, 3f, x1, 1384,0)
+
+inst_363:
+// rs1_val==5 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x5; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x5, 0x3, 0x8, 1b, x1, 1388,0)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb505; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0xb505, 0x80, 3f, x1, 1392,0)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, -0xb503, 0x0, 3f, x1, 1396,0)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x66666667, 0x40, 3f, x1, 1400,0)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x33333334, 0x4, 1b, x1, 1404,0)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x6, 0x80, 3f, x1, 1408,0)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, -0x55555555, 0x20, 3f, x1, 1412,0)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x55555556, 0x400, 1b, x1, 1416,0)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x4, 0x6, 1b, x1, 1420,0)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0xb503, 0x400, 3f, x1, 1424,0)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x0, 0x4, 3f, x1, 1428,0)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x66666665, 0x2, 1b, x1, 1432,0)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x33333332, 0x2, 1b, x1, 1436,0)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x55555554, 0x200, 3f, x1, 1440,0)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x2, 0x400, 3f, x1, 1444,0)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0xb504, 0x556, 1b, x1, 1448,0)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0xb504; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, -0xb504, 0x0, 1b, x1, 1452,0)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x66666666, 0x6, 1b, x1, 1456,0)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x33333333, 0x2, 3f, x1, 1460,0)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x5, 0x4, 1b, x1, 1464,0)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:-0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, -0x55555556, 0x6, 1b, x1, 1468,0)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x55555555, 0x4, 3f, x1, 1472,0)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0x55555556; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x55555556, 0x3, 0x40, 3f, x1, 1476,0)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0xb505, 0x6, 1b, x1, 1480,0)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, -0xb503, 0x10, 3f, x1, 1484,0)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666667; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x66666667, 0x8, 3f, x1, 1488,0)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x33333334, 0x6, 3f, x1, 1492,0)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x6; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x6, 0x556, 1b, x1, 1496,0)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, -0x55555555, 0xa, 1b, x1, 1500,0)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555556; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x55555556, 0x20, 3f, x1, 1504,0)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x4; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x4, 0x0, 1b, x1, 1508,0)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0xb503, 0x10, 3f, x1, 1512,0)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x0, 0x4, 1b, x1, 1516,0)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x66666665, 0x20, 3f, x1, 1520,0)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333332; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x33333332, 0x2, 1b, x1, 1524,0)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x55555554, 0x400, 3f, x1, 1528,0)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x2; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x2, 0x4, 3f, x1, 1532,0)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0xb504, 0x400, 1b, x1, 1536,0)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, -0xb504, 0x6, 3f, x1, 1540,0)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x66666666; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x66666666, 0x4, 1b, x1, 1544,0)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x33333333, 0x400, 1b, x1, 1548,0)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x5, 0x200, 3f, x1, 1552,0)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:-0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, -0x55555556, 0x100, 3f, x1, 1556,0)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x55555555, 0xa, 1b, x1, 1560,0)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555555; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555555, 0x3, 0x8, 1b, x1, 1564,0)
+
+inst_408:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0xb505; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0xb505, 0x200, 3f, x1, 1568,0)
+
+inst_409:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:-0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, -0xb503, 0x4, 1b, x1, 1572,0)
+
+inst_410:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x66666667; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x66666667, 0x40, 3f, x1, 1576,0)
+
+inst_411:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x33333334; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x33333334, 0x2, 3f, x1, 1580,0)
+
+inst_412:
+// rs1_val==3 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x6, 0x0, 3f, x1, 1584,0)
+
+inst_413:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, -0x55555555, 0x4, 1b, x1, 1588,0)
+
+inst_414:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x55555556, 0x8, 3f, x1, 1592,0)
+
+inst_415:
+// rs1_val==3 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x4, 0x4, 1b, x1, 1596,0)
+
+inst_416:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0xb503, 0x0, 1b, x1, 1600,0)
+
+inst_417:
+// rs1_val==3 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x0, 0x200, 3f, x1, 1604,0)
+
+inst_418:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x66666665; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x66666665, 0x6, 3f, x1, 1608,0)
+
+inst_419:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x33333332; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x33333332, 0x4, 3f, x1, 1612,0)
+
+inst_420:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x55555554, 0x4, 1b, x1, 1616,0)
+
+inst_421:
+// rs1_val==3 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x2; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x2, 0x100, 3f, x1, 1620,0)
+
+inst_422:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0xb504, 0x400, 1b, x1, 1624,0)
+
+inst_423:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, -0xb504, 0x10, 3f, x1, 1628,0)
+
+inst_424:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x66666666, 0x6, 3f, x1, 1632,0)
+
+inst_425:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x33333333; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x33333333, 0x6, 3f, x1, 1636,0)
+
+inst_426:
+// rs1_val==3 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x5; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x5, 0x4, 1b, x1, 1640,0)
+
+inst_427:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:-0x55555556; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, -0x55555556, 0x8, 1b, x1, 1644,0)
+
+inst_428:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x55555555; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x55555555, 0x2, 1b, x1, 1648,0)
+
+inst_429:
+// rs1_val==3 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x3; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x3, 0x3, 0x400, 3f, x1, 1652,0)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666665; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x66666665, 0x200, 3f, x1, 1656,0)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x33333332, 0x6, 3f, x1, 1660,0)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555554; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x55555554, 0x556, 1b, x1, 1664,0)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x2; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x2, 0x6, 1b, x1, 1668,0)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0xb504; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0xb504, 0x8, 1b, x1, 1672,0)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:-0xb504; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, -0xb504, 0xa, 1b, x1, 1676,0)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x66666666; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x66666666, 0x100, 3f, x1, 1680,0)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x33333333; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x33333333, 0x2, 1b, x1, 1684,0)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x5, 0x20, 3f, x1, 1688,0)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:-0x55555556; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, -0x55555556, 0xa, 1b, x1, 1692,0)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x55555555, 0xa, 1b, x1, 1696,0)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666665; op2val:0x3; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666665, 0x3, 0x200, 3f, x1, 1700,0)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb505; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0xb505, 0xa, 1b, x1, 1704,0)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, -0xb503, 0x400, 3f, x1, 1708,0)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x66666667, 0x400, 3f, x1, 1712,0)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x33333334, 0x100, 3f, x1, 1716,0)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x6, 0x0, 1b, x1, 1720,0)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, -0x55555555, 0x40, 3f, x1, 1724,0)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x55555556, 0x4, 1b, x1, 1728,0)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x4; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x4, 0x2, 3f, x1, 1732,0)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0xb503, 0x20, 3f, x1, 1736,0)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x0; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x0, 0x4, 1b, x1, 1740,0)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666665; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x66666665, 0x20, 3f, x1, 1744,0)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333332; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x33333332, 0x20, 3f, x1, 1748,0)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x55555554, 0x0, 1b, x1, 1752,0)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x2; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x2, 0x400, 1b, x1, 1756,0)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0xb504, 0x2, 3f, x1, 1760,0)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:-0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, -0xb504, 0x6, 1b, x1, 1764,0)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x66666666; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x66666666, 0x2, 1b, x1, 1768,0)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x33333333; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x33333333, 0x400, 3f, x1, 1772,0)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x5; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x5, 0x200, 3f, x1, 1776,0)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, -0x55555556, 0x0, 3f, x1, 1780,0)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x55555555; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x55555555, 0x4, 3f, x1, 1784,0)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333332; op2val:0x3; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333332, 0x3, 0x400, 1b, x1, 1788,0)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb505; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0xb505, 0x8, 1b, x1, 1792,0)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, -0xb503, 0x8, 3f, x1, 1796,0)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x66666667, 0x400, 1b, x1, 1800,0)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333334; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x33333334, 0x100, 3f, x1, 1804,0)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x6; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x6, 0x10, 3f, x1, 1808,0)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555555; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, -0x55555555, 0x0, 3f, x1, 1812,0)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x55555556, 0x0, 1b, x1, 1816,0)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x4; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x4, 0x8, 1b, x1, 1820,0)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0xb503, 0x4, 3f, x1, 1824,0)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x0; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x0, 0x200, 3f, x1, 1828,0)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x66666665, 0x4, 1b, x1, 1832,0)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x33333332, 0x6, 1b, x1, 1836,0)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555554; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x55555554, 0x4, 3f, x1, 1840,0)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x2, 0x0, 1b, x1, 1844,0)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0xb504, 0x80, 3f, x1, 1848,0)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:-0xb504; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, -0xb504, 0x10, 3f, x1, 1852,0)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x66666666; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x66666666, 0x80, 3f, x1, 1856,0)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x33333333; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x33333333, 0x10, 3f, x1, 1860,0)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x5, 0xa, 1b, x1, 1864,0)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:-0x55555556; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, -0x55555556, 0x2, 1b, x1, 1868,0)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x55555555, 0x400, 1b, x1, 1872,0)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x55555554; op2val:0x3; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x55555554, 0x3, 0x10, 3f, x1, 1876,0)
+
+inst_486:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0xb505, 0x100, 3f, x1, 1880,0)
+
+inst_487:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, -0xb503, 0x400, 1b, x1, 1884,0)
+
+inst_488:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x66666667, 0x4, 1b, x1, 1888,0)
+
+inst_489:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x33333334; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x33333334, 0x6, 1b, x1, 1892,0)
+
+inst_490:
+// rs1_val==2 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x6, 0x2, 3f, x1, 1896,0)
+
+inst_491:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, -0x55555555, 0x400, 1b, x1, 1900,0)
+
+inst_492:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x55555556, 0x10, 3f, x1, 1904,0)
+
+inst_493:
+// rs1_val==2 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x4; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x4, 0x4, 3f, x1, 1908,0)
+
+inst_494:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0xb503, 0x10, 3f, x1, 1912,0)
+
+inst_495:
+// rs1_val==2 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x0; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x0, 0x40, 3f, x1, 1916,0)
+
+inst_496:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x66666665; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x66666665, 0x2, 1b, x1, 1920,0)
+
+inst_497:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x33333332; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x33333332, 0x40, 3f, x1, 1924,0)
+
+inst_498:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x55555554; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x55555554, 0x0, 3f, x1, 1928,0)
+
+inst_499:
+// rs1_val==2 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x2; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x2, 0x80, 3f, x1, 1932,0)
+
+inst_500:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0xb504; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0xb504, 0x4, 1b, x1, 1936,0)
+
+inst_501:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:-0xb504; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, -0xb504, 0x2, 1b, x1, 1940,0)
+
+inst_502:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x66666666, 0x0, 1b, x1, 1944,0)
+
+inst_503:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x33333333; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x33333333, 0x200, 3f, x1, 1948,0)
+
+inst_504:
+// rs1_val==2 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x5; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x5, 0x556, 1b, x1, 1952,0)
+
+inst_505:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:-0x55555556; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, -0x55555556, 0x200, 3f, x1, 1956,0)
+
+inst_506:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x55555555, 0xa, 1b, x1, 1960,0)
+
+inst_507:
+// rs1_val==2 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x2; op2val:0x3; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x2, 0x3, 0x6, 1b, x1, 1964,0)
+
+inst_508:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0xb505; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0xb505, 0x10, 3f, x1, 1968,0)
+
+inst_509:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb503; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, -0xb503, 0x10, 3f, x1, 1972,0)
+
+inst_510:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666667; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x66666667, 0x4, 3f, x1, 1976,0)
+
+inst_511:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333334; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x33333334, 0x556, 1b, x1, 1980,0)
+
+inst_512:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x6; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x6, 0x80, 3f, x1, 1984,0)
+
+inst_513:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555555; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, -0x55555555, 0x400, 3f, x1, 1988,0)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555556; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x55555556, 0x4, 1b, x1, 1992,0)
+
+inst_515:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x4; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x4, 0x40, 3f, x1, 1996,0)
+
+inst_516:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0xb503; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0xb503, 0x20, 3f, x1, 2000,0)
+
+inst_517:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x0; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x0, 0x400, 1b, x1, 2004,0)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666665; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x66666665, 0x4, 1b, x1, 2008,0)
+
+inst_519:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333332; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x33333332, 0x80, 3f, x1, 2012,0)
+
+inst_520:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x55555554, 0x400, 1b, x1, 2016,0)
+
+inst_521:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x2; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x2, 0xa, 1b, x1, 2020,0)
+
+inst_522:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0xb504; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0xb504, 0x200, 3f, x1, 2024,0)
+
+inst_523:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:-0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, -0xb504, 0x80, 3f, x1, 2028,0)
+
+inst_524:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x66666666; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x66666666, 0x0, 1b, x1, 2032,0)
+
+inst_525:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x33333333, 0x0, 1b, x1, 2036,0)
+
+inst_526:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x5; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x5, 0x20, 3f, x1, 2040,0)
+
+inst_527:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:-0x55555556; immval:0x10; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, -0x55555556, 0x10, 3f, x1, 2044,0)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_528:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x55555555, 0x20, 3f, x1, 0,0)
+
+inst_529:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0xb504; op2val:0x3; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0xb504, 0x3, 0x4, 3f, x1, 4,0)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb505; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0xb505, 0x6, 3f, x1, 8,0)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb503; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0xb503, 0x6, 1b, x1, 12,0)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666667; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x66666667, 0x400, 1b, x1, 16,0)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333334; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x33333334, 0x400, 3f, x1, 20,0)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x6, 0x2, 1b, x1, 24,0)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555555; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0x55555555, 0x20, 3f, x1, 28,0)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555556; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x55555556, 0x400, 1b, x1, 32,0)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x4; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x4, 0x6, 1b, x1, 36,0)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb503; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0xb503, 0x2, 3f, x1, 40,0)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x0; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x0, 0x100, 3f, x1, 44,0)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666665; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x66666665, 0x8, 1b, x1, 48,0)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333332; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x33333332, 0x6, 3f, x1, 52,0)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555554; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x55555554, 0x200, 3f, x1, 56,0)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x2; immval:0x20; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x2, 0x20, 3f, x1, 60,0)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0xb504; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0xb504, 0x400, 1b, x1, 64,0)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0xb504; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0xb504, 0x80, 3f, x1, 68,0)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x66666666; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x66666666, 0x8, 1b, x1, 72,0)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x33333333; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x33333333, 0x8, 3f, x1, 76,0)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x5; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x5, 0x100, 3f, x1, 80,0)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:-0x55555556; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, -0x55555556, 0x100, 3f, x1, 84,0)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x55555555; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x55555555, 0xa, 1b, x1, 88,0)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:-0xb504; op2val:0x3; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0xb504, 0x3, 0x40, 3f, x1, 92,0)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb505; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0xb505, 0x100, 3f, x1, 96,0)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb503; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, -0xb503, 0x400, 3f, x1, 100,0)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666667; immval:0x200; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x66666667, 0x200, 3f, x1, 104,0)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333334; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x33333334, 0x0, 3f, x1, 108,0)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x6; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x6, 0x0, 3f, x1, 112,0)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555555; immval:0x80; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, -0x55555555, 0x80, 3f, x1, 116,0)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x55555556, 0x6, 3f, x1, 120,0)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x4; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x4, 0x400, 1b, x1, 124,0)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb503; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0xb503, 0x8, 3f, x1, 128,0)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x0; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x0, 0x6, 1b, x1, 132,0)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666665; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x66666665, 0x100, 3f, x1, 136,0)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333332; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x33333332, 0x8, 3f, x1, 140,0)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555554; immval:0x400; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x55555554, 0x400, 3f, x1, 144,0)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x2; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x2, 0x0, 1b, x1, 148,0)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0xb504; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0xb504, 0x6, 1b, x1, 152,0)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:-0xb504; immval:0x556; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, -0xb504, 0x556, 1b, x1, 156,0)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x66666666; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x66666666, 0x6, 1b, x1, 160,0)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x33333333; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x33333333, 0x0, 3f, x1, 164,0)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x5; immval:0xa; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x5, 0xa, 1b, x1, 168,0)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:-0x55555556; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, -0x55555556, 0x0, 1b, x1, 172,0)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x55555555, 0x40, 3f, x1, 176,0)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x66666666; op2val:0x3; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x66666666, 0x3, 0x8, 1b, x1, 180,0)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb505; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0xb505, 0x2, 1b, x1, 184,0)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:-0xb503; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, -0xb503, 0x0, 1b, x1, 188,0)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x66666667; immval:0x0; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x66666667, 0x0, 1b, x1, 192,0)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x33333334; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x33333334, 0x4, 1b, x1, 196,0)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x6; immval:0x2; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x6, 0x2, 3f, x1, 200,0)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:-0x55555555; immval:0x40; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, -0x55555555, 0x40, 3f, x1, 204,0)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x55555556; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x55555556, 0x6, 3f, x1, 208,0)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0x4; immval:0x100; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0x4, 0x100, 3f, x1, 212,0)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: bne, op1:x10; op2:x11; op1val:0x33333333; op2val:0xb503; immval:0x4; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, 0x33333333, 0xb503, 0x4, 3f, x1, 216,0)
+
+inst_583:
+// rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0, rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0, rs2_val == -268435457, rs1_val == -33554433
+// opcode: bne, op1:x10; op2:x11; op1val:-0x2000001; op2val:-0x10000001; immval:0x8; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x2000001, -0x10000001, 0x8, 1b, x1, 220,0)
+
+inst_584:
+// rs2_val == -134217729, rs1_val == -16777217
+// opcode: bne, op1:x10; op2:x11; op1val:-0x1000001; op2val:-0x8000001; immval:0x6; align:0
+TEST_BRANCH_OP(bne, x2, x10, x11, -0x1000001, -0x8000001, 0x6, 1b, x1, 224,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 57*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S
new file mode 100644
index 000000000..2fd3e9e2b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S
@@ -0,0 +1,156 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jal)
+
+RVTEST_SIGBASE( x7,signature_x7_1)
+
+inst_0:
+// rd==x8, imm_val < 0, 
+// opcode: jal; dest:x8; immval:0x4; align:0
+TEST_JAL_OP(x2, x8, 0x4, 1b, x7, 0,0)
+
+inst_1:
+// rd==x14, imm_val == ((2**(18))), imm_val > 0
+// opcode: jal; dest:x14; immval:0x40000; align:0
+TEST_JAL_OP(x2, x14, 0x40000, 3f, x7, 4,0)
+
+inst_2:
+// rd==x9, imm_val == (-(2**(18))), 
+// opcode: jal; dest:x9; immval:0x40000; align:0
+TEST_JAL_OP(x2, x9, 0x40000, 1b, x7, 8,0)
+
+inst_3:
+// rd==x12, 
+// opcode: jal; dest:x12; immval:0x80000; align:0
+TEST_JAL_OP(x2, x12, 0x80000, 1b, x7, 12,0)
+
+inst_4:
+// rd==x0, 
+// opcode: jal; dest:x0; immval:0x80000; align:0
+TEST_JAL_OP(x2, x0, 0x80000, 1b, x7, 16,0)
+
+inst_5:
+// rd==x3, 
+// opcode: jal; dest:x3; immval:0x80000; align:0
+TEST_JAL_OP(x2, x3, 0x80000, 1b, x7, 20,0)
+
+inst_6:
+// rd==x4, 
+// opcode: jal; dest:x4; immval:0x80000; align:0
+TEST_JAL_OP(x2, x4, 0x80000, 1b, x7, 24,0)
+
+inst_7:
+// rd==x5, 
+// opcode: jal; dest:x5; immval:0x80000; align:0
+TEST_JAL_OP(x2, x5, 0x80000, 1b, x7, 28,0)
+
+inst_8:
+// rd==x13, 
+// opcode: jal; dest:x13; immval:0x80000; align:0
+TEST_JAL_OP(x2, x13, 0x80000, 1b, x7, 32,0)
+
+inst_9:
+// rd==x6, 
+// opcode: jal; dest:x6; immval:0x80000; align:0
+TEST_JAL_OP(x2, x6, 0x80000, 1b, x7, 36,0)
+
+inst_10:
+// rd==x15, 
+// opcode: jal; dest:x15; immval:0x80000; align:0
+TEST_JAL_OP(x2, x15, 0x80000, 1b, x7, 40,0)
+
+inst_11:
+// rd==x1, 
+// opcode: jal; dest:x1; immval:0x80000; align:0
+TEST_JAL_OP(x2, x1, 0x80000, 1b, x7, 44,0)
+
+inst_12:
+// rd==x2, 
+// opcode: jal; dest:x2; immval:0x80000; align:0
+TEST_JAL_OP(x3, x2, 0x80000, 1b, x7, 48,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_13:
+// rd==x7, 
+// opcode: jal; dest:x7; immval:0x80000; align:0
+TEST_JAL_OP(x3, x7, 0x80000, 1b, x1, 0,0)
+
+inst_14:
+// rd==x10, 
+// opcode: jal; dest:x10; immval:0x80000; align:0
+TEST_JAL_OP(x3, x10, 0x80000, 1b, x1, 4,0)
+
+inst_15:
+// rd==x11, 
+// opcode: jal; dest:x11; immval:0x80000; align:0
+TEST_JAL_OP(x3, x11, 0x80000, 1b, x1, 8,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x7_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_1:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 3*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S
new file mode 100644
index 000000000..c8ac34760
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S
@@ -0,0 +1,216 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the jalr instruction of the RISC-V E extension for the jalr covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",jalr)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x8, rd==x12, imm_val < 0, imm_val == -129
+// opcode: jalr; op1:x8; dest:x12; immval:-0x81; align:0 
+TEST_JALR_OP(x6, x12, x8, -0x81, x1, 0,0)
+
+inst_1:
+// rs1 == rd, rs1==x5, rd==x5, imm_val == 2047, imm_val > 0
+// opcode: jalr; op1:x5; dest:x5; immval:0x7ff; align:0 
+TEST_JALR_OP(x6, x5, x5, 0x7ff, x1, 4,0)
+
+inst_2:
+// rs1==x3, rd==x15, imm_val == -1025, 
+// opcode: jalr; op1:x3; dest:x15; immval:-0x401; align:0 
+TEST_JALR_OP(x6, x15, x3, -0x401, x1, 8,0)
+
+inst_3:
+// rs1==x2, rd==x3, imm_val == -513, 
+// opcode: jalr; op1:x2; dest:x3; immval:-0x201; align:0 
+TEST_JALR_OP(x6, x3, x2, -0x201, x1, 12,0)
+
+inst_4:
+// rs1==x4, rd==x9, imm_val == -257, 
+// opcode: jalr; op1:x4; dest:x9; immval:-0x101; align:0 
+TEST_JALR_OP(x6, x9, x4, -0x101, x1, 16,0)
+
+inst_5:
+// rs1==x9, rd==x7, imm_val == -65, 
+// opcode: jalr; op1:x9; dest:x7; immval:-0x41; align:0 
+TEST_JALR_OP(x6, x7, x9, -0x41, x1, 20,0)
+
+inst_6:
+// rs1==x10, rd==x13, imm_val == -33, 
+// opcode: jalr; op1:x10; dest:x13; immval:-0x21; align:0 
+TEST_JALR_OP(x6, x13, x10, -0x21, x1, 24,0)
+
+inst_7:
+// rs1==x14, rd==x0, imm_val == -17, 
+// opcode: jalr; op1:x14; dest:x0; immval:-0x11; align:0 
+TEST_JALR_OP(x5, x0, x14, -0x11, x1, 28,0)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_8:
+// rs1==x15, rd==x4, imm_val == -9, 
+// opcode: jalr; op1:x15; dest:x4; immval:-0x9; align:0 
+TEST_JALR_OP(x5, x4, x15, -0x9, x3, 0,0)
+
+inst_9:
+// rs1==x7, rd==x14, imm_val == -5, 
+// opcode: jalr; op1:x7; dest:x14; immval:-0x5; align:0 
+TEST_JALR_OP(x5, x14, x7, -0x5, x3, 4,0)
+
+inst_10:
+// rs1==x11, rd==x2, imm_val == -3, 
+// opcode: jalr; op1:x11; dest:x2; immval:-0x3; align:0 
+TEST_JALR_OP(x5, x2, x11, -0x3, x3, 8,0)
+
+inst_11:
+// rs1==x6, rd==x11, imm_val == -2, 
+// opcode: jalr; op1:x6; dest:x11; immval:-0x2; align:0 
+TEST_JALR_OP(x5, x11, x6, -0x2, x3, 12,0)
+
+inst_12:
+// rs1==x12, rd==x8, imm_val == -2048, 
+// opcode: jalr; op1:x12; dest:x8; immval:-0x800; align:0 
+TEST_JALR_OP(x5, x8, x12, -0x800, x3, 16,0)
+
+inst_13:
+// rs1==x13, rd==x1, imm_val == 1024, 
+// opcode: jalr; op1:x13; dest:x1; immval:0x400; align:0 
+TEST_JALR_OP(x5, x1, x13, 0x400, x3, 20,0)
+
+inst_14:
+// rs1==x1, rd==x10, imm_val == 512, 
+// opcode: jalr; op1:x1; dest:x10; immval:0x200; align:0 
+TEST_JALR_OP(x2, x10, x1, 0x200, x3, 24,0)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_15:
+// rd==x6, imm_val == 256, 
+// opcode: jalr; op1:x13; dest:x6; immval:0x100; align:0 
+TEST_JALR_OP(x2, x6, x13, 0x100, x1, 0,0)
+
+inst_16:
+// imm_val == 128, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x80; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x80, x1, 4,0)
+
+inst_17:
+// imm_val == 64, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x40; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x40, x1, 8,0)
+
+inst_18:
+// imm_val == 32, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x20; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x20, x1, 12,0)
+
+inst_19:
+// imm_val == 16, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x10; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x10, x1, 16,0)
+
+inst_20:
+// imm_val == 8, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x8; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x8, x1, 20,0)
+
+inst_21:
+// imm_val == 4, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x4; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x4, x1, 24,0)
+
+inst_22:
+// imm_val == 1, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x1; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x1, x1, 28,0)
+
+inst_23:
+// imm_val == -1366, 
+// opcode: jalr; op1:x10; dest:x11; immval:-0x556; align:0 
+TEST_JALR_OP(x2, x11, x10, -0x556, x1, 32,0)
+
+inst_24:
+// imm_val == 1365, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x555; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x555, x1, 36,0)
+
+inst_25:
+// imm_val == 2, 
+// opcode: jalr; op1:x10; dest:x11; immval:0x2; align:0 
+TEST_JALR_OP(x2, x11, x10, 0x2, x1, 40,0)
+
+inst_26:
+// imm_val == -17, 
+// opcode: jalr; op1:x10; dest:x11; immval:-0x11; align:0 
+TEST_JALR_OP(x2, x11, x10, -0x11, x1, 44,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S
new file mode 100644
index 000000000..d42f83ccd
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S
@@ -0,0 +1,166 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lb instruction of the RISC-V E extension for the lb-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lb-align)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x8, rd==x9, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
+// opcode:lb op1:x8; dest:x9; immval:-0x4; align:0
+TEST_LOAD(x1,x4,0,x8,x9,-0x4,0,lb,0)
+
+inst_1:
+// rs1 == rd, rs1==x15, rd==x15, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
+// opcode:lb op1:x15; dest:x15; immval:0x5; align:0
+TEST_LOAD(x1,x4,0,x15,x15,0x5,4,lb,0)
+
+inst_2:
+// rs1==x2, rd==x8, ea_align == 0 and (imm_val % 4) == 2, 
+// opcode:lb op1:x2; dest:x8; immval:0x2; align:0
+TEST_LOAD(x1,x4,0,x2,x8,0x2,8,lb,0)
+
+inst_3:
+// rs1==x11, rd==x7, ea_align == 0 and (imm_val % 4) == 3, 
+// opcode:lb op1:x11; dest:x7; immval:-0x101; align:0
+TEST_LOAD(x1,x4,0,x11,x7,-0x101,12,lb,0)
+
+inst_4:
+// rs1==x6, rd==x5, ea_align == 1 and (imm_val % 4) == 0, 
+// opcode:lb op1:x6; dest:x5; immval:0x4; align:1
+TEST_LOAD(x1,x4,0,x6,x5,0x4,16,lb,1)
+
+inst_5:
+// rs1==x12, rd==x10, ea_align == 1 and (imm_val % 4) == 1, 
+// opcode:lb op1:x12; dest:x10; immval:-0x3; align:1
+TEST_LOAD(x1,x4,0,x12,x10,-0x3,20,lb,1)
+
+inst_6:
+// rs1==x10, rd==x12, ea_align == 1 and (imm_val % 4) == 2, 
+// opcode:lb op1:x10; dest:x12; immval:-0x2; align:1
+TEST_LOAD(x1,x4,0,x10,x12,-0x2,24,lb,1)
+
+inst_7:
+// rs1==x9, rd==x6, ea_align == 1 and (imm_val % 4) == 3, 
+// opcode:lb op1:x9; dest:x6; immval:-0x401; align:1
+TEST_LOAD(x1,x4,0,x9,x6,-0x401,28,lb,1)
+
+inst_8:
+// rs1==x13, rd==x3, ea_align == 2 and (imm_val % 4) == 0, 
+// opcode:lb op1:x13; dest:x3; immval:0x40; align:2
+TEST_LOAD(x1,x4,0,x13,x3,0x40,32,lb,2)
+RVTEST_SIGBASE( x6,signature_x6_0)
+
+inst_9:
+// rs1==x4, rd==x1, ea_align == 2 and (imm_val % 4) == 1, 
+// opcode:lb op1:x4; dest:x1; immval:0x5; align:2
+TEST_LOAD(x6,x8,0,x4,x1,0x5,0,lb,2)
+
+inst_10:
+// rs1==x1, rd==x11, imm_val == 0, 
+// opcode:lb op1:x1; dest:x11; immval:0x0; align:0
+TEST_LOAD(x6,x8,0,x1,x11,0x0,4,lb,0)
+
+inst_11:
+// rs1==x3, rd==x14, ea_align == 2 and (imm_val % 4) == 2, 
+// opcode:lb op1:x3; dest:x14; immval:0x2; align:2
+TEST_LOAD(x6,x8,0,x3,x14,0x2,8,lb,2)
+
+inst_12:
+// rs1==x7, rd==x4, ea_align == 2 and (imm_val % 4) == 3, 
+// opcode:lb op1:x7; dest:x4; immval:-0x1; align:2
+TEST_LOAD(x6,x8,0,x7,x4,-0x1,12,lb,2)
+
+inst_13:
+// rs1==x14, rd==x0, ea_align == 3 and (imm_val % 4) == 0, 
+// opcode:lb op1:x14; dest:x0; immval:-0x8; align:3
+TEST_LOAD(x6,x8,0,x14,x0,-0x8,16,lb,3)
+
+inst_14:
+// rs1==x5, rd==x13, ea_align == 3 and (imm_val % 4) == 1, 
+// opcode:lb op1:x5; dest:x13; immval:-0x3; align:3
+TEST_LOAD(x6,x8,0,x5,x13,-0x3,20,lb,3)
+
+inst_15:
+// rd==x2, ea_align == 3 and (imm_val % 4) == 2, 
+// opcode:lb op1:x5; dest:x2; immval:-0x556; align:3
+TEST_LOAD(x6,x8,0,x5,x2,-0x556,24,lb,3)
+
+inst_16:
+// ea_align == 3 and (imm_val % 4) == 3, 
+// opcode:lb op1:x10; dest:x11; immval:-0x401; align:3
+TEST_LOAD(x6,x8,0,x10,x11,-0x401,28,lb,3)
+
+inst_17:
+// ea_align == 3 and (imm_val % 4) == 0, 
+// opcode:lb op1:x10; dest:x11; immval:-0x8; align:3
+TEST_LOAD(x6,x8,0,x10,x11,-0x8,32,lb,3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_0:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S
new file mode 100644
index 000000000..bc2c0527d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S
@@ -0,0 +1,166 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lbu instruction of the RISC-V E extension for the lbu-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lbu-align)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x14, rd==x0, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0
+// opcode:lbu op1:x14; dest:x0; immval:0x100; align:0
+TEST_LOAD(x1,x8,0,x14,x0,0x100,0,lbu,0)
+
+inst_1:
+// rs1 == rd, rs1==x13, rd==x13, ea_align == 0 and (imm_val % 4) == 1, imm_val < 0
+// opcode:lbu op1:x13; dest:x13; immval:-0x7; align:0
+TEST_LOAD(x1,x8,0,x13,x13,-0x7,4,lbu,0)
+
+inst_2:
+// rs1==x2, rd==x3, ea_align == 0 and (imm_val % 4) == 2, 
+// opcode:lbu op1:x2; dest:x3; immval:0x6; align:0
+TEST_LOAD(x1,x8,0,x2,x3,0x6,8,lbu,0)
+
+inst_3:
+// rs1==x5, rd==x11, ea_align == 0 and (imm_val % 4) == 3, 
+// opcode:lbu op1:x5; dest:x11; immval:-0x9; align:0
+TEST_LOAD(x1,x8,0,x5,x11,-0x9,12,lbu,0)
+
+inst_4:
+// rs1==x4, rd==x15, ea_align == 1 and (imm_val % 4) == 0, 
+// opcode:lbu op1:x4; dest:x15; immval:-0x4; align:1
+TEST_LOAD(x1,x8,0,x4,x15,-0x4,16,lbu,1)
+
+inst_5:
+// rs1==x6, rd==x9, ea_align == 1 and (imm_val % 4) == 1, 
+// opcode:lbu op1:x6; dest:x9; immval:0x1; align:1
+TEST_LOAD(x1,x8,0,x6,x9,0x1,20,lbu,1)
+
+inst_6:
+// rs1==x9, rd==x7, ea_align == 1 and (imm_val % 4) == 2, 
+// opcode:lbu op1:x9; dest:x7; immval:0x6; align:1
+TEST_LOAD(x1,x8,0,x9,x7,0x6,24,lbu,1)
+
+inst_7:
+// rs1==x10, rd==x8, ea_align == 1 and (imm_val % 4) == 3, 
+// opcode:lbu op1:x10; dest:x8; immval:-0x201; align:1
+TEST_LOAD(x1,x13,0,x10,x8,-0x201,28,lbu,1)
+RVTEST_SIGBASE( x9,signature_x9_0)
+
+inst_8:
+// rs1==x11, rd==x1, ea_align == 2 and (imm_val % 4) == 0, 
+// opcode:lbu op1:x11; dest:x1; immval:0x4; align:2
+TEST_LOAD(x9,x13,0,x11,x1,0x4,0,lbu,2)
+
+inst_9:
+// rs1==x3, rd==x4, ea_align == 2 and (imm_val % 4) == 1, 
+// opcode:lbu op1:x3; dest:x4; immval:-0x7; align:2
+TEST_LOAD(x9,x13,0,x3,x4,-0x7,4,lbu,2)
+
+inst_10:
+// rs1==x1, rd==x6, imm_val == 0, 
+// opcode:lbu op1:x1; dest:x6; immval:0x0; align:0
+TEST_LOAD(x9,x13,0,x1,x6,0x0,8,lbu,0)
+
+inst_11:
+// rs1==x8, rd==x10, ea_align == 2 and (imm_val % 4) == 2, 
+// opcode:lbu op1:x8; dest:x10; immval:-0x2; align:2
+TEST_LOAD(x9,x13,0,x8,x10,-0x2,12,lbu,2)
+
+inst_12:
+// rs1==x12, rd==x2, ea_align == 2 and (imm_val % 4) == 3, 
+// opcode:lbu op1:x12; dest:x2; immval:-0x401; align:2
+TEST_LOAD(x9,x13,0,x12,x2,-0x401,16,lbu,2)
+
+inst_13:
+// rs1==x7, rd==x5, ea_align == 3 and (imm_val % 4) == 0, 
+// opcode:lbu op1:x7; dest:x5; immval:0x4; align:3
+TEST_LOAD(x9,x13,0,x7,x5,0x4,20,lbu,3)
+
+inst_14:
+// rs1==x15, rd==x14, ea_align == 3 and (imm_val % 4) == 1, 
+// opcode:lbu op1:x15; dest:x14; immval:0x9; align:3
+TEST_LOAD(x9,x2,0,x15,x14,0x9,24,lbu,3)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_15:
+// rd==x12, ea_align == 3 and (imm_val % 4) == 2, 
+// opcode:lbu op1:x14; dest:x12; immval:-0x2; align:3
+TEST_LOAD(x1,x2,0,x14,x12,-0x2,0,lbu,3)
+
+inst_16:
+// ea_align == 3 and (imm_val % 4) == 3, 
+// opcode:lbu op1:x10; dest:x11; immval:-0x5; align:3
+TEST_LOAD(x1,x2,0,x10,x11,-0x5,4,lbu,3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x9_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 2*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S
new file mode 100644
index 000000000..e16cb695d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S
@@ -0,0 +1,156 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lh instruction of the RISC-V E extension for the lh-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lh-align)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x3, rd==x2, ea_align == 0 and (imm_val % 4) == 0, imm_val == 0
+// opcode:lh op1:x3; dest:x2; immval:0x0; align:0
+TEST_LOAD(x4,x5,0,x3,x2,0x0,0,lh,0)
+
+inst_1:
+// rs1 == rd, rs1==x15, rd==x15, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
+// opcode:lh op1:x15; dest:x15; immval:0x5; align:0
+TEST_LOAD(x4,x5,0,x15,x15,0x5,4,lh,0)
+
+inst_2:
+// rs1==x12, rd==x14, ea_align == 0 and (imm_val % 4) == 2, imm_val < 0
+// opcode:lh op1:x12; dest:x14; immval:-0x556; align:0
+TEST_LOAD(x4,x5,0,x12,x14,-0x556,8,lh,0)
+
+inst_3:
+// rs1==x14, rd==x8, ea_align == 0 and (imm_val % 4) == 3, 
+// opcode:lh op1:x14; dest:x8; immval:0x3ff; align:0
+TEST_LOAD(x4,x5,0,x14,x8,0x3ff,12,lh,0)
+
+inst_4:
+// rs1==x10, rd==x3, ea_align == 2 and (imm_val % 4) == 0, 
+// opcode:lh op1:x10; dest:x3; immval:-0x8; align:2
+TEST_LOAD(x4,x5,0,x10,x3,-0x8,16,lh,2)
+
+inst_5:
+// rs1==x6, rd==x1, ea_align == 2 and (imm_val % 4) == 1, 
+// opcode:lh op1:x6; dest:x1; immval:0x555; align:2
+TEST_LOAD(x4,x5,0,x6,x1,0x555,20,lh,2)
+
+inst_6:
+// rs1==x13, rd==x6, ea_align == 2 and (imm_val % 4) == 2, 
+// opcode:lh op1:x13; dest:x6; immval:-0x6; align:2
+TEST_LOAD(x4,x5,0,x13,x6,-0x6,24,lh,2)
+
+inst_7:
+// rs1==x1, rd==x9, ea_align == 2 and (imm_val % 4) == 3, 
+// opcode:lh op1:x1; dest:x9; immval:0x7ff; align:2
+TEST_LOAD(x4,x5,0,x1,x9,0x7ff,28,lh,2)
+
+inst_8:
+// rs1==x9, rd==x0, 
+// opcode:lh op1:x9; dest:x0; immval:-0x800; align:0
+TEST_LOAD(x4,x3,0,x9,x0,-0x800,32,lh,0)
+
+inst_9:
+// rs1==x5, rd==x12, 
+// opcode:lh op1:x5; dest:x12; immval:-0x800; align:0
+TEST_LOAD(x4,x3,0,x5,x12,-0x800,36,lh,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_10:
+// rs1==x8, rd==x11, 
+// opcode:lh op1:x8; dest:x11; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x8,x11,-0x800,0,lh,0)
+
+inst_11:
+// rs1==x11, rd==x4, 
+// opcode:lh op1:x11; dest:x4; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x11,x4,-0x800,4,lh,0)
+
+inst_12:
+// rs1==x2, rd==x7, 
+// opcode:lh op1:x2; dest:x7; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x2,x7,-0x800,8,lh,0)
+
+inst_13:
+// rs1==x4, rd==x10, 
+// opcode:lh op1:x4; dest:x10; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x4,x10,-0x800,12,lh,0)
+
+inst_14:
+// rs1==x7, rd==x5, 
+// opcode:lh op1:x7; dest:x5; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x7,x5,-0x800,16,lh,0)
+
+inst_15:
+// rd==x13, 
+// opcode:lh op1:x12; dest:x13; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x12,x13,-0x800,20,lh,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 10*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S
new file mode 100644
index 000000000..9e4427ca5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S
@@ -0,0 +1,161 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lhu instruction of the RISC-V E extension for the lhu-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lhu-align)
+
+RVTEST_SIGBASE( x7,signature_x7_1)
+
+inst_0:
+// rs1 != rd, rs1==x15, rd==x9, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
+// opcode:lhu op1:x15; dest:x9; immval:-0x4; align:0
+TEST_LOAD(x7,x1,0,x15,x9,-0x4,0,lhu,0)
+
+inst_1:
+// rs1 == rd, rs1==x3, rd==x3, ea_align == 0 and (imm_val % 4) == 1, imm_val > 0
+// opcode:lhu op1:x3; dest:x3; immval:0x5; align:0
+TEST_LOAD(x7,x1,0,x3,x3,0x5,4,lhu,0)
+
+inst_2:
+// rs1==x13, rd==x2, ea_align == 0 and (imm_val % 4) == 2, 
+// opcode:lhu op1:x13; dest:x2; immval:-0x556; align:0
+TEST_LOAD(x7,x1,0,x13,x2,-0x556,8,lhu,0)
+
+inst_3:
+// rs1==x4, rd==x11, ea_align == 0 and (imm_val % 4) == 3, 
+// opcode:lhu op1:x4; dest:x11; immval:-0x5; align:0
+TEST_LOAD(x7,x1,0,x4,x11,-0x5,12,lhu,0)
+
+inst_4:
+// rs1==x8, rd==x5, ea_align == 2 and (imm_val % 4) == 0, 
+// opcode:lhu op1:x8; dest:x5; immval:0x80; align:2
+TEST_LOAD(x7,x1,0,x8,x5,0x80,16,lhu,2)
+
+inst_5:
+// rs1==x6, rd==x10, imm_val == 0, 
+// opcode:lhu op1:x6; dest:x10; immval:0x0; align:0
+TEST_LOAD(x7,x1,0,x6,x10,0x0,20,lhu,0)
+
+inst_6:
+// rs1==x10, rd==x1, ea_align == 2 and (imm_val % 4) == 1, 
+// opcode:lhu op1:x10; dest:x1; immval:0x9; align:2
+TEST_LOAD(x7,x2,0,x10,x1,0x9,24,lhu,2)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_7:
+// rs1==x1, rd==x13, ea_align == 2 and (imm_val % 4) == 2, 
+// opcode:lhu op1:x1; dest:x13; immval:-0xa; align:2
+TEST_LOAD(x3,x2,0,x1,x13,-0xa,0,lhu,2)
+
+inst_8:
+// rs1==x14, rd==x4, ea_align == 2 and (imm_val % 4) == 3, 
+// opcode:lhu op1:x14; dest:x4; immval:-0x11; align:2
+TEST_LOAD(x3,x2,0,x14,x4,-0x11,4,lhu,2)
+
+inst_9:
+// rs1==x11, rd==x8, 
+// opcode:lhu op1:x11; dest:x8; immval:-0x800; align:0
+TEST_LOAD(x3,x2,0,x11,x8,-0x800,8,lhu,0)
+
+inst_10:
+// rs1==x5, rd==x12, 
+// opcode:lhu op1:x5; dest:x12; immval:-0x800; align:0
+TEST_LOAD(x3,x2,0,x5,x12,-0x800,12,lhu,0)
+
+inst_11:
+// rs1==x9, rd==x7, 
+// opcode:lhu op1:x9; dest:x7; immval:-0x800; align:0
+TEST_LOAD(x3,x2,0,x9,x7,-0x800,16,lhu,0)
+
+inst_12:
+// rs1==x12, rd==x15, 
+// opcode:lhu op1:x12; dest:x15; immval:-0x800; align:0
+TEST_LOAD(x3,x4,0,x12,x15,-0x800,20,lhu,0)
+
+inst_13:
+// rs1==x7, rd==x0, 
+// opcode:lhu op1:x7; dest:x0; immval:-0x800; align:0
+TEST_LOAD(x3,x4,0,x7,x0,-0x800,24,lhu,0)
+
+inst_14:
+// rs1==x2, rd==x14, 
+// opcode:lhu op1:x2; dest:x14; immval:-0x800; align:0
+TEST_LOAD(x3,x4,0,x2,x14,-0x800,28,lhu,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_15:
+// rd==x6, 
+// opcode:lhu op1:x14; dest:x6; immval:-0x800; align:0
+TEST_LOAD(x1,x4,0,x14,x6,-0x800,0,lhu,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x7_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 1*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S
new file mode 100644
index 000000000..f1257005f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S
@@ -0,0 +1,391 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lui instruction of the RISC-V E extension for the lui covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lui)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rd==x3, imm_val == ((2**20)-1), imm_val > 0
+// opcode: lui ; dest:x3; immval:0xfffff
+TEST_CASE(x5, x3, -0x1000, x4, 0, lui x3,0xfffff)
+
+inst_1:
+// rd==x2, imm_val == 524287, 
+// opcode: lui ; dest:x2; immval:0x7ffff
+TEST_CASE(x5, x2, 0x7ffff000, x4, 4, lui x2,0x7ffff)
+
+inst_2:
+// rd==x1, imm_val == 786431, 
+// opcode: lui ; dest:x1; immval:0xbffff
+TEST_CASE(x5, x1, -0x40001000, x4, 8, lui x1,0xbffff)
+
+inst_3:
+// rd==x8, imm_val == 917503, 
+// opcode: lui ; dest:x8; immval:0xdffff
+TEST_CASE(x5, x8, -0x20001000, x4, 12, lui x8,0xdffff)
+
+inst_4:
+// rd==x14, imm_val == 983039, 
+// opcode: lui ; dest:x14; immval:0xeffff
+TEST_CASE(x5, x14, -0x10001000, x4, 16, lui x14,0xeffff)
+
+inst_5:
+// rd==x7, imm_val == 1015807, 
+// opcode: lui ; dest:x7; immval:0xf7fff
+TEST_CASE(x5, x7, -0x8001000, x4, 20, lui x7,0xf7fff)
+
+inst_6:
+// rd==x13, imm_val == 1032191, 
+// opcode: lui ; dest:x13; immval:0xfbfff
+TEST_CASE(x5, x13, -0x4001000, x4, 24, lui x13,0xfbfff)
+
+inst_7:
+// rd==x12, imm_val == 1040383, 
+// opcode: lui ; dest:x12; immval:0xfdfff
+TEST_CASE(x5, x12, -0x2001000, x4, 28, lui x12,0xfdfff)
+
+inst_8:
+// rd==x15, imm_val == 1044479, 
+// opcode: lui ; dest:x15; immval:0xfefff
+TEST_CASE(x5, x15, -0x1001000, x4, 32, lui x15,0xfefff)
+
+inst_9:
+// rd==x10, imm_val == 1046527, 
+// opcode: lui ; dest:x10; immval:0xff7ff
+TEST_CASE(x5, x10, -0x801000, x4, 36, lui x10,0xff7ff)
+
+inst_10:
+// rd==x6, imm_val == 1047551, 
+// opcode: lui ; dest:x6; immval:0xffbff
+TEST_CASE(x5, x6, -0x401000, x4, 40, lui x6,0xffbff)
+
+inst_11:
+// rd==x9, imm_val == 1048063, 
+// opcode: lui ; dest:x9; immval:0xffdff
+TEST_CASE(x2, x9, -0x201000, x4, 44, lui x9,0xffdff)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_12:
+// rd==x4, imm_val == 1048319, 
+// opcode: lui ; dest:x4; immval:0xffeff
+TEST_CASE(x2, x4, -0x101000, x1, 0, lui x4,0xffeff)
+
+inst_13:
+// rd==x0, imm_val == 1048447, 
+// opcode: lui ; dest:x0; immval:0xfff7f
+TEST_CASE(x2, x0, 0, x1, 4, lui x0,0xfff7f)
+
+inst_14:
+// rd==x5, imm_val == 1048511, 
+// opcode: lui ; dest:x5; immval:0xfffbf
+TEST_CASE(x2, x5, -0x41000, x1, 8, lui x5,0xfffbf)
+
+inst_15:
+// rd==x11, imm_val == 1048543, 
+// opcode: lui ; dest:x11; immval:0xfffdf
+TEST_CASE(x2, x11, -0x21000, x1, 12, lui x11,0xfffdf)
+
+inst_16:
+// imm_val == 1048559, 
+// opcode: lui ; dest:x10; immval:0xfffef
+TEST_CASE(x2, x10, -0x11000, x1, 16, lui x10,0xfffef)
+
+inst_17:
+// imm_val == 1048567, 
+// opcode: lui ; dest:x10; immval:0xffff7
+TEST_CASE(x2, x10, -0x9000, x1, 20, lui x10,0xffff7)
+
+inst_18:
+// imm_val == 1048571, 
+// opcode: lui ; dest:x10; immval:0xffffb
+TEST_CASE(x2, x10, -0x5000, x1, 24, lui x10,0xffffb)
+
+inst_19:
+// imm_val == 1048573, 
+// opcode: lui ; dest:x10; immval:0xffffd
+TEST_CASE(x2, x10, -0x3000, x1, 28, lui x10,0xffffd)
+
+inst_20:
+// imm_val == 1048574, 
+// opcode: lui ; dest:x10; immval:0xffffe
+TEST_CASE(x2, x10, -0x2000, x1, 32, lui x10,0xffffe)
+
+inst_21:
+// imm_val == 524288, 
+// opcode: lui ; dest:x10; immval:0x80000
+TEST_CASE(x2, x10, -0x80000000, x1, 36, lui x10,0x80000)
+
+inst_22:
+// imm_val == 262144, 
+// opcode: lui ; dest:x10; immval:0x40000
+TEST_CASE(x2, x10, 0x40000000, x1, 40, lui x10,0x40000)
+
+inst_23:
+// imm_val == 131072, 
+// opcode: lui ; dest:x10; immval:0x20000
+TEST_CASE(x2, x10, 0x20000000, x1, 44, lui x10,0x20000)
+
+inst_24:
+// imm_val == 65536, 
+// opcode: lui ; dest:x10; immval:0x10000
+TEST_CASE(x2, x10, 0x10000000, x1, 48, lui x10,0x10000)
+
+inst_25:
+// imm_val == 32768, 
+// opcode: lui ; dest:x10; immval:0x8000
+TEST_CASE(x2, x10, 0x8000000, x1, 52, lui x10,0x8000)
+
+inst_26:
+// imm_val == 16384, 
+// opcode: lui ; dest:x10; immval:0x4000
+TEST_CASE(x2, x10, 0x4000000, x1, 56, lui x10,0x4000)
+
+inst_27:
+// imm_val == 8192, 
+// opcode: lui ; dest:x10; immval:0x2000
+TEST_CASE(x2, x10, 0x2000000, x1, 60, lui x10,0x2000)
+
+inst_28:
+// imm_val == 4096, 
+// opcode: lui ; dest:x10; immval:0x1000
+TEST_CASE(x2, x10, 0x1000000, x1, 64, lui x10,0x1000)
+
+inst_29:
+// imm_val == 2048, 
+// opcode: lui ; dest:x10; immval:0x800
+TEST_CASE(x2, x10, 0x800000, x1, 68, lui x10,0x800)
+
+inst_30:
+// imm_val == 1024, imm_val==1024
+// opcode: lui ; dest:x10; immval:0x400
+TEST_CASE(x2, x10, 0x400000, x1, 72, lui x10,0x400)
+
+inst_31:
+// imm_val == 512, 
+// opcode: lui ; dest:x10; immval:0x200
+TEST_CASE(x2, x10, 0x200000, x1, 76, lui x10,0x200)
+
+inst_32:
+// imm_val == 256, 
+// opcode: lui ; dest:x10; immval:0x100
+TEST_CASE(x2, x10, 0x100000, x1, 80, lui x10,0x100)
+
+inst_33:
+// imm_val == 128, 
+// opcode: lui ; dest:x10; immval:0x80
+TEST_CASE(x2, x10, 0x80000, x1, 84, lui x10,0x80)
+
+inst_34:
+// imm_val == 64, 
+// opcode: lui ; dest:x10; immval:0x40
+TEST_CASE(x2, x10, 0x40000, x1, 88, lui x10,0x40)
+
+inst_35:
+// imm_val == 32, 
+// opcode: lui ; dest:x10; immval:0x20
+TEST_CASE(x2, x10, 0x20000, x1, 92, lui x10,0x20)
+
+inst_36:
+// imm_val == 16, 
+// opcode: lui ; dest:x10; immval:0x10
+TEST_CASE(x2, x10, 0x10000, x1, 96, lui x10,0x10)
+
+inst_37:
+// imm_val==349525, imm_val == 349525
+// opcode: lui ; dest:x10; immval:0x55555
+TEST_CASE(x2, x10, 0x55555000, x1, 100, lui x10,0x55555)
+
+inst_38:
+// imm_val==3, 
+// opcode: lui ; dest:x10; immval:0x3
+TEST_CASE(x2, x10, 0x3000, x1, 104, lui x10,0x3)
+
+inst_39:
+// imm_val == 699050, imm_val==699050
+// opcode: lui ; dest:x10; immval:0xaaaaa
+TEST_CASE(x2, x10, -0x55556000, x1, 108, lui x10,0xaaaaa)
+
+inst_40:
+// imm_val == 0, imm_val==0
+// opcode: lui ; dest:x10; immval:0x0
+TEST_CASE(x2, x10, 0x0, x1, 112, lui x10,0x0)
+
+inst_41:
+// imm_val == 8, 
+// opcode: lui ; dest:x10; immval:0x8
+TEST_CASE(x2, x10, 0x8000, x1, 116, lui x10,0x8)
+
+inst_42:
+// imm_val == 4, imm_val==4
+// opcode: lui ; dest:x10; immval:0x4
+TEST_CASE(x2, x10, 0x4000, x1, 120, lui x10,0x4)
+
+inst_43:
+// imm_val == 2, imm_val==2
+// opcode: lui ; dest:x10; immval:0x2
+TEST_CASE(x2, x10, 0x2000, x1, 124, lui x10,0x2)
+
+inst_44:
+// imm_val == 1, imm_val==1
+// opcode: lui ; dest:x10; immval:0x1
+TEST_CASE(x2, x10, 0x1000, x1, 128, lui x10,0x1)
+
+inst_45:
+// imm_val==725, 
+// opcode: lui ; dest:x10; immval:0x2d5
+TEST_CASE(x2, x10, 0x2d5000, x1, 132, lui x10,0x2d5)
+
+inst_46:
+// imm_val==419431, 
+// opcode: lui ; dest:x10; immval:0x66667
+TEST_CASE(x2, x10, 0x66667000, x1, 136, lui x10,0x66667)
+
+inst_47:
+// imm_val==209716, 
+// opcode: lui ; dest:x10; immval:0x33334
+TEST_CASE(x2, x10, 0x33334000, x1, 140, lui x10,0x33334)
+
+inst_48:
+// imm_val==6, 
+// opcode: lui ; dest:x10; immval:0x6
+TEST_CASE(x2, x10, 0x6000, x1, 144, lui x10,0x6)
+
+inst_49:
+// imm_val==699051, 
+// opcode: lui ; dest:x10; immval:0xaaaab
+TEST_CASE(x2, x10, -0x55555000, x1, 148, lui x10,0xaaaab)
+
+inst_50:
+// imm_val==349526, 
+// opcode: lui ; dest:x10; immval:0x55556
+TEST_CASE(x2, x10, 0x55556000, x1, 152, lui x10,0x55556)
+
+inst_51:
+// imm_val==1022, 
+// opcode: lui ; dest:x10; immval:0x3fe
+TEST_CASE(x2, x10, 0x3fe000, x1, 156, lui x10,0x3fe)
+
+inst_52:
+// imm_val==723, 
+// opcode: lui ; dest:x10; immval:0x2d3
+TEST_CASE(x2, x10, 0x2d3000, x1, 160, lui x10,0x2d3)
+
+inst_53:
+// imm_val==419429, 
+// opcode: lui ; dest:x10; immval:0x66665
+TEST_CASE(x2, x10, 0x66665000, x1, 164, lui x10,0x66665)
+
+inst_54:
+// imm_val==209714, 
+// opcode: lui ; dest:x10; immval:0x33332
+TEST_CASE(x2, x10, 0x33332000, x1, 168, lui x10,0x33332)
+
+inst_55:
+// imm_val==699049, 
+// opcode: lui ; dest:x10; immval:0xaaaa9
+TEST_CASE(x2, x10, -0x55557000, x1, 172, lui x10,0xaaaa9)
+
+inst_56:
+// imm_val==349524, 
+// opcode: lui ; dest:x10; immval:0x55554
+TEST_CASE(x2, x10, 0x55554000, x1, 176, lui x10,0x55554)
+
+inst_57:
+// imm_val==1023, 
+// opcode: lui ; dest:x10; immval:0x3ff
+TEST_CASE(x2, x10, 0x3ff000, x1, 180, lui x10,0x3ff)
+
+inst_58:
+// imm_val==724, 
+// opcode: lui ; dest:x10; immval:0x2d4
+TEST_CASE(x2, x10, 0x2d4000, x1, 184, lui x10,0x2d4)
+
+inst_59:
+// imm_val==419430, 
+// opcode: lui ; dest:x10; immval:0x66666
+TEST_CASE(x2, x10, 0x66666000, x1, 188, lui x10,0x66666)
+
+inst_60:
+// imm_val==209715, 
+// opcode: lui ; dest:x10; immval:0x33333
+TEST_CASE(x2, x10, 0x33333000, x1, 192, lui x10,0x33333)
+
+inst_61:
+// imm_val==5, 
+// opcode: lui ; dest:x10; immval:0x5
+TEST_CASE(x2, x10, 0x5000, x1, 196, lui x10,0x5)
+
+inst_62:
+// imm_val == 1048447, 
+// opcode: lui ; dest:x10; immval:0xfff7f
+TEST_CASE(x2, x10, -0x81000, x1, 200, lui x10,0xfff7f)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 12*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 51*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S
new file mode 100644
index 000000000..e1f368a9b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S
@@ -0,0 +1,161 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the lw instruction of the RISC-V E extension for the lw-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",lw-align)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 != rd, rs1==x11, rd==x1, ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
+// opcode:lw op1:x11; dest:x1; immval:-0x400; align:0
+TEST_LOAD(x2,x6,0,x11,x1,-0x400,0,lw,0)
+
+inst_1:
+// rs1 == rd, rs1==x14, rd==x14, ea_align == 0 and (imm_val % 4) == 1, 
+// opcode:lw op1:x14; dest:x14; immval:-0x3; align:0
+TEST_LOAD(x2,x6,0,x14,x14,-0x3,4,lw,0)
+
+inst_2:
+// rs1==x4, rd==x8, ea_align == 0 and (imm_val % 4) == 2, 
+// opcode:lw op1:x4; dest:x8; immval:-0x556; align:0
+TEST_LOAD(x2,x6,0,x4,x8,-0x556,8,lw,0)
+
+inst_3:
+// rs1==x1, rd==x10, ea_align == 0 and (imm_val % 4) == 3, 
+// opcode:lw op1:x1; dest:x10; immval:-0x5; align:0
+TEST_LOAD(x2,x6,0,x1,x10,-0x5,12,lw,0)
+
+inst_4:
+// rs1==x12, rd==x15, imm_val == 0, 
+// opcode:lw op1:x12; dest:x15; immval:0x0; align:0
+TEST_LOAD(x2,x6,0,x12,x15,0x0,16,lw,0)
+
+inst_5:
+// rs1==x7, rd==x13, imm_val > 0, 
+// opcode:lw op1:x7; dest:x13; immval:0x20; align:0
+TEST_LOAD(x2,x6,0,x7,x13,0x20,20,lw,0)
+
+inst_6:
+// rs1==x5, rd==x3, 
+// opcode:lw op1:x5; dest:x3; immval:-0x800; align:0
+TEST_LOAD(x2,x6,0,x5,x3,-0x800,24,lw,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_7:
+// rs1==x8, rd==x0, 
+// opcode:lw op1:x8; dest:x0; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x8,x0,-0x800,0,lw,0)
+
+inst_8:
+// rs1==x3, rd==x12, 
+// opcode:lw op1:x3; dest:x12; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x3,x12,-0x800,4,lw,0)
+
+inst_9:
+// rs1==x13, rd==x4, 
+// opcode:lw op1:x13; dest:x4; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x13,x4,-0x800,8,lw,0)
+
+inst_10:
+// rs1==x15, rd==x7, 
+// opcode:lw op1:x15; dest:x7; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x15,x7,-0x800,12,lw,0)
+
+inst_11:
+// rs1==x9, rd==x5, 
+// opcode:lw op1:x9; dest:x5; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x9,x5,-0x800,16,lw,0)
+
+inst_12:
+// rs1==x6, rd==x9, 
+// opcode:lw op1:x6; dest:x9; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x6,x9,-0x800,20,lw,0)
+
+inst_13:
+// rs1==x10, rd==x2, 
+// opcode:lw op1:x10; dest:x2; immval:-0x800; align:0
+TEST_LOAD(x1,x11,0,x10,x2,-0x800,24,lw,0)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_14:
+// rs1==x2, rd==x6, 
+// opcode:lw op1:x2; dest:x6; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x2,x6,-0x800,0,lw,0)
+
+inst_15:
+// rd==x11, 
+// opcode:lw op1:x5; dest:x11; immval:-0x800; align:0
+TEST_LOAD(x1,x3,0,x5,x11,-0x800,4,lw,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 2*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S
new file mode 100644
index 000000000..193785007
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S
@@ -0,0 +1,3036 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the or instruction of the RISC-V E extension for the or covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",or)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x3, rd==x2, rs1_val != rs2_val, rs2_val == 536870912, rs1_val == -2097153, rs1_val < 0 and rs2_val > 0
+// opcode: or ; op1:x10; op2:x3; dest:x2; op1val:-0x200001;  op2val:0x20000000
+TEST_RR_OP(or, x2, x10, x3, 0xffdfffff, -0x200001, 0x20000000, x5, 0, x4)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x14, rs2==x10, rd==x14, rs2_val == 2147483647, rs1_val > 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: or ; op1:x14; op2:x10; dest:x14; op1val:0x5;  op2val:0x7fffffff
+TEST_RR_OP(or, x14, x14, x10, 0x7fffffff, 0x5, 0x7fffffff, x5, 4, x4)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x1, rs2==x6, rd==x6, rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0
+// opcode: or ; op1:x1; op2:x6; dest:x6; op1val:-0xb504;  op2val:-0x40000001
+TEST_RR_OP(or, x6, x1, x6, 0xffffffff, -0xb504, -0x40000001, x5, 8, x4)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x11, rs2==x11, rd==x9, rs2_val == -536870913, 
+// opcode: or ; op1:x11; op2:x11; dest:x9; op1val:-0x40000000;  op2val:-0x40000000
+TEST_RR_OP(or, x9, x11, x11, 0xc0000000, -0x40000000, -0x40000000, x5, 12, x4)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8, rs2_val == -268435457, rs1_val == 16384, rs1_val > 0 and rs2_val < 0
+// opcode: or ; op1:x8; op2:x8; dest:x8; op1val:0x4000;  op2val:0x4000
+TEST_RR_OP(or, x8, x8, x8, 0x4000, 0x4000, 0x4000, x5, 16, x4)
+
+inst_5:
+// rs1==x7, rs2==x9, rd==x12, rs2_val == -134217729, rs1_val == -8193
+// opcode: or ; op1:x7; op2:x9; dest:x12; op1val:-0x2001;  op2val:-0x8000001
+TEST_RR_OP(or, x12, x7, x9, 0xffffffff, -0x2001, -0x8000001, x5, 20, x4)
+
+inst_6:
+// rs1==x4, rs2==x1, rd==x15, rs2_val == -67108865, rs1_val == -3
+// opcode: or ; op1:x4; op2:x1; dest:x15; op1val:-0x3;  op2val:-0x4000001
+TEST_RR_OP(or, x15, x4, x1, 0xffffffff, -0x3, -0x4000001, x5, 24, x3)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_7:
+// rs1==x6, rs2==x13, rd==x10, rs2_val == -33554433, rs1_val == 1024
+// opcode: or ; op1:x6; op2:x13; dest:x10; op1val:0x400;  op2val:-0x2000001
+TEST_RR_OP(or, x10, x6, x13, 0xfdffffff, 0x400, -0x2000001, x4, 0, x3)
+
+inst_8:
+// rs1==x5, rs2==x14, rd==x0, rs2_val == -16777217, rs1_val == 0
+// opcode: or ; op1:x5; op2:x14; dest:x0; op1val:0x0;  op2val:-0x1000001
+TEST_RR_OP(or, x0, x5, x14, 0, 0x0, -0x1000001, x4, 4, x3)
+
+inst_9:
+// rs1==x9, rs2==x0, rd==x1, rs2_val == -8388609, 
+// opcode: or ; op1:x9; op2:x0; dest:x1; op1val:0x6;  op2val:0x0
+TEST_RR_OP(or, x1, x9, x0, 0x6, 0x6, 0x0, x4, 8, x3)
+
+inst_10:
+// rs1==x13, rs2==x5, rd==x11, rs2_val == -4194305, 
+// opcode: or ; op1:x13; op2:x5; dest:x11; op1val:0x6;  op2val:-0x400001
+TEST_RR_OP(or, x11, x13, x5, 0xffbfffff, 0x6, -0x400001, x4, 12, x3)
+
+inst_11:
+// rs1==x12, rs2==x2, rd==x5, rs2_val == -2097153, rs1_val == 134217728
+// opcode: or ; op1:x12; op2:x2; dest:x5; op1val:0x8000000;  op2val:-0x200001
+TEST_RR_OP(or, x5, x12, x2, 0xffdfffff, 0x8000000, -0x200001, x4, 16, x3)
+
+inst_12:
+// rs1==x3, rs2==x12, rd==x7, rs2_val == -1048577, 
+// opcode: or ; op1:x3; op2:x12; dest:x7; op1val:0xb504;  op2val:-0x100001
+TEST_RR_OP(or, x7, x3, x12, 0xffefffff, 0xb504, -0x100001, x4, 20, x6)
+RVTEST_SIGBASE( x5,signature_x5_2)
+
+inst_13:
+// rs1==x0, rs2==x15, rd==x13, rs2_val == -524289, rs1_val == -33
+// opcode: or ; op1:x0; op2:x15; dest:x13; op1val:0x0;  op2val:-0x80001
+TEST_RR_OP(or, x13, x0, x15, 0xfff7ffff, 0x0, -0x80001, x5, 0, x6)
+
+inst_14:
+// rs1==x15, rs2==x7, rd==x3, rs2_val == -262145, rs1_val == -1431655766
+// opcode: or ; op1:x15; op2:x7; dest:x3; op1val:-0x55555556;  op2val:-0x40001
+TEST_RR_OP(or, x3, x15, x7, 0xfffbffff, -0x55555556, -0x40001, x5, 4, x6)
+
+inst_15:
+// rs1==x2, rs2_val == -131073, 
+// opcode: or ; op1:x2; op2:x12; dest:x1; op1val:-0x55555555;  op2val:-0x20001
+TEST_RR_OP(or, x1, x2, x12, 0xffffffff, -0x55555555, -0x20001, x5, 8, x6)
+
+inst_16:
+// rs2==x4, rs2_val == -65537, 
+// opcode: or ; op1:x9; op2:x4; dest:x10; op1val:0x9;  op2val:-0x10001
+TEST_RR_OP(or, x10, x9, x4, 0xfffeffff, 0x9, -0x10001, x5, 12, x6)
+
+inst_17:
+// rd==x4, rs2_val == -32769, 
+// opcode: or ; op1:x3; op2:x8; dest:x4; op1val:-0xb504;  op2val:-0x8001
+TEST_RR_OP(or, x4, x3, x8, 0xffff7fff, -0xb504, -0x8001, x5, 16, x6)
+
+inst_18:
+// rs2_val == -16385, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1)
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x4001
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x7fffffff, -0x4001, x5, 20, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_19:
+// rs2_val == -8193, rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:-0x2001
+TEST_RR_OP(or, x12, x10, x11, 0xffffdfff, -0x80000000, -0x2001, x1, 0, x2)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x1001
+TEST_RR_OP(or, x12, x10, x11, 0xffffefff, 0x0, -0x1001, x1, 4, x2)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x801
+TEST_RR_OP(or, x12, x10, x11, 0xfffff7ff, 0x66666665, -0x801, x1, 8, x2)
+
+inst_22:
+// rs2_val == -1025, rs1_val == -513
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:-0x401
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x201, -0x401, x1, 12, x2)
+
+inst_23:
+// rs2_val == -513, rs1_val == 64
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x201
+TEST_RR_OP(or, x12, x10, x11, 0xfffffdff, 0x40, -0x201, x1, 16, x2)
+
+inst_24:
+// rs2_val == -257, rs1_val == 128
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:-0x101
+TEST_RR_OP(or, x12, x10, x11, 0xfffffeff, 0x80, -0x101, x1, 20, x2)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x81
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x200001, -0x81, x1, 24, x2)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x41
+TEST_RR_OP(or, x12, x10, x11, 0xffffffbf, -0x55555555, -0x41, x1, 28, x2)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x21
+TEST_RR_OP(or, x12, x10, x11, 0xffffffdf, 0x6, -0x21, x1, 32, x2)
+
+inst_28:
+// rs2_val == -17, rs1_val == -134217729
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x11
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x8000001, -0x11, x1, 36, x2)
+
+inst_29:
+// rs2_val == -9, rs1_val == -2
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0x9
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x2, -0x9, x1, 40, x2)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x8;  op2val:-0x5
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffb, -0x8, -0x5, x1, 44, x2)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x3
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x7fffffff, -0x3, x1, 48, x2)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x2
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, 0x6, -0x2, x1, 52, x2)
+
+inst_33:
+// rs1_val == -1073741825, rs2_val == 32
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x20
+TEST_RR_OP(or, x12, x10, x11, 0xbfffffff, -0x40000001, 0x20, x1, 56, x2)
+
+inst_34:
+// rs1_val == -536870913, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:-0x41
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x20000001, -0x41, x1, 60, x2)
+
+inst_35:
+// rs1_val == -268435457, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:-0x100001
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x10000001, -0x100001, x1, 64, x2)
+
+inst_36:
+// rs1_val == -67108865, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:-0x201
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x4000001, -0x201, x1, 68, x2)
+
+inst_37:
+// rs1_val == -33554433, rs2_val == 65536
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x10000
+TEST_RR_OP(or, x12, x10, x11, 0xfdffffff, -0x2000001, 0x10000, x1, 72, x2)
+
+inst_38:
+// rs1_val == -16777217, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:-0x801
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x1000001, -0x801, x1, 76, x2)
+
+inst_39:
+// rs1_val == -8388609, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0xff7fffff, -0x800001, 0x33333332, x1, 80, x2)
+
+inst_40:
+// rs1_val == -4194305, rs2_val == 1431655765
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x400001, 0x55555555, x1, 84, x2)
+
+inst_41:
+// rs1_val == -1048577, rs2_val == 1024
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x400
+TEST_RR_OP(or, x12, x10, x11, 0xffefffff, -0x100001, 0x400, x1, 88, x2)
+
+inst_42:
+// rs1_val == -524289, rs2_val == 524288
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0x80000
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x80001, 0x80000, x1, 92, x2)
+
+inst_43:
+// rs1_val == -262145, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x40001, 0x55555555, x1, 96, x2)
+
+inst_44:
+// rs1_val == -131073, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:-0x2001
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x20001, -0x2001, x1, 100, x2)
+
+inst_45:
+// rs1_val == -65537, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x400001
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x10001, -0x400001, x1, 104, x2)
+
+inst_46:
+// rs1_val == -32769, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xffff7fff, -0x8001, 0x5, x1, 108, x2)
+
+inst_47:
+// rs1_val == -16385, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x400
+TEST_RR_OP(or, x12, x10, x11, 0xffffbfff, -0x4001, 0x400, x1, 112, x2)
+
+inst_48:
+// rs1_val == -4097, rs2_val == 256
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x100
+TEST_RR_OP(or, x12, x10, x11, 0xffffefff, -0x1001, 0x100, x1, 116, x2)
+
+inst_49:
+// rs1_val == -2049, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0x6
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x801, -0x6, x1, 120, x2)
+
+inst_50:
+// rs1_val == -1025, rs2_val == 8
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x8
+TEST_RR_OP(or, x12, x10, x11, 0xfffffbff, -0x401, 0x8, x1, 124, x2)
+
+inst_51:
+// rs1_val == -257, rs2_val == 32768
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x8000
+TEST_RR_OP(or, x12, x10, x11, 0xfffffeff, -0x101, 0x8000, x1, 128, x2)
+
+inst_52:
+// rs1_val == -129, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:-0x1
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x81, -0x1, x1, 132, x2)
+
+inst_53:
+// rs1_val == -65, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x1
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x41, -0x1, x1, 136, x2)
+
+inst_54:
+// rs1_val == -17, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:-0x101
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x11, -0x101, x1, 140, x2)
+
+inst_55:
+// rs1_val == -9, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:-0x6
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x9, -0x6, x1, 144, x2)
+
+inst_56:
+// rs1_val == -5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x20000000
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffb, -0x5, 0x20000000, x1, 148, x2)
+
+inst_57:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x80000000
+TEST_RR_OP(or, x12, x10, x11, 0x80000005, 0x5, -0x80000000, x1, 152, x2)
+
+inst_58:
+// rs2_val == 1073741824, rs1_val == 32768
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x40000000
+TEST_RR_OP(or, x12, x10, x11, 0x40008000, 0x8000, 0x40000000, x1, 156, x2)
+
+inst_59:
+// rs2_val == 268435456, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x10000000
+TEST_RR_OP(or, x12, x10, x11, 0xfffff7ff, -0x801, 0x10000000, x1, 160, x2)
+
+inst_60:
+// rs2_val == 134217728, rs1_val == 8
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x8000000
+TEST_RR_OP(or, x12, x10, x11, 0x8000008, 0x8, 0x8000000, x1, 164, x2)
+
+inst_61:
+// rs2_val == 67108864, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4000000
+TEST_RR_OP(or, x12, x10, x11, 0xaeaaaaaa, -0x55555556, 0x4000000, x1, 168, x2)
+
+inst_62:
+// rs2_val == 33554432, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2000000
+TEST_RR_OP(or, x12, x10, x11, 0x200b504, 0xb504, 0x2000000, x1, 172, x2)
+
+inst_63:
+// rs2_val == 16777216, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x1000000
+TEST_RR_OP(or, x12, x10, x11, 0xffffdfff, -0x2001, 0x1000000, x1, 176, x2)
+
+inst_64:
+// rs2_val == 8388608, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x7;  op2val:0x800000
+TEST_RR_OP(or, x12, x10, x11, 0xfffffff9, -0x7, 0x800000, x1, 180, x2)
+
+inst_65:
+// rs2_val == 4194304, rs1_val == 16
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x400000
+TEST_RR_OP(or, x12, x10, x11, 0x400010, 0x10, 0x400000, x1, 184, x2)
+
+inst_66:
+// rs2_val == 2097152, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0x200000
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x200001, 0x200000, x1, 188, x2)
+
+inst_67:
+// rs2_val == 1048576, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x100000
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, 0x100000, x1, 192, x2)
+
+inst_68:
+// rs2_val == 262144, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x40000
+TEST_RR_OP(or, x12, x10, x11, 0x4b503, 0xb503, 0x40000, x1, 196, x2)
+
+inst_69:
+// rs2_val == 131072, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x20000
+TEST_RR_OP(or, x12, x10, x11, 0x20008, 0x8, 0x20000, x1, 200, x2)
+
+inst_70:
+// rs2_val == 16384, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x4000
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, -0x2, 0x4000, x1, 204, x2)
+
+inst_71:
+// rs2_val == 8192, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2000
+TEST_RR_OP(or, x12, x10, x11, 0x55557556, 0x55555556, 0x2000, x1, 208, x2)
+
+inst_72:
+// rs2_val == 4096, rs1_val == 2
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1000
+TEST_RR_OP(or, x12, x10, x11, 0x1002, 0x2, 0x1000, x1, 212, x2)
+
+inst_73:
+// rs2_val == 2048, rs1_val == 4
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x800
+TEST_RR_OP(or, x12, x10, x11, 0x804, 0x4, 0x800, x1, 216, x2)
+
+inst_74:
+// rs2_val == 512, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x200
+TEST_RR_OP(or, x12, x10, x11, 0x80000200, -0x80000000, 0x200, x1, 220, x2)
+
+inst_75:
+// rs2_val == 128, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3fffffff;  op2val:0x80
+TEST_RR_OP(or, x12, x10, x11, 0x3fffffff, 0x3fffffff, 0x80, x1, 224, x2)
+
+inst_76:
+// rs2_val == 64, rs1_val == 32
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x40
+TEST_RR_OP(or, x12, x10, x11, 0x60, 0x20, 0x40, x1, 228, x2)
+
+inst_77:
+// rs2_val == 16, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x10
+TEST_RR_OP(or, x12, x10, x11, 0xfffff7ff, -0x801, 0x10, x1, 232, x2)
+
+inst_78:
+// rs2_val == 4, rs1_val == 524288
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x80004, 0x80000, 0x4, x1, 236, x2)
+
+inst_79:
+// rs2_val == 2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xfffffdff, -0x201, 0x2, x1, 240, x2)
+
+inst_80:
+// rs2_val == 1, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(or, x12, x10, x11, 0x1, 0x0, 0x1, x1, 244, x2)
+
+inst_81:
+// rs1_val == 1073741824, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x81
+TEST_RR_OP(or, x12, x10, x11, 0xffffff7f, 0x40000000, -0x81, x1, 248, x2)
+
+inst_82:
+// rs1_val == 536870912, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x2000000
+TEST_RR_OP(or, x12, x10, x11, 0x22000000, 0x20000000, 0x2000000, x1, 252, x2)
+
+inst_83:
+// rs1_val == 268435456, rs2_val == 0
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x10000000, 0x10000000, 0x0, x1, 256, x2)
+
+inst_84:
+// rs1_val == 67108864, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x20000000
+TEST_RR_OP(or, x12, x10, x11, 0x24000000, 0x4000000, 0x20000000, x1, 260, x2)
+
+inst_85:
+// rs1_val == 33554432, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:-0x6
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffa, 0x2000000, -0x6, x1, 264, x2)
+
+inst_86:
+// rs1_val == 16777216, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x400000
+TEST_RR_OP(or, x12, x10, x11, 0x1400000, 0x1000000, 0x400000, x1, 268, x2)
+
+inst_87:
+// rs1_val == 8388608, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55d55555, 0x800000, 0x55555555, x1, 272, x2)
+
+inst_88:
+// rs1_val == 4194304, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:-0xa
+TEST_RR_OP(or, x12, x10, x11, 0xfffffff6, 0x400000, -0xa, x1, 276, x2)
+
+inst_89:
+// rs1_val == 2097152, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x200000, 0x33333334, x1, 280, x2)
+
+inst_90:
+// rs1_val == 1048576, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x80
+TEST_RR_OP(or, x12, x10, x11, 0x100080, 0x100000, 0x80, x1, 284, x2)
+
+inst_91:
+// rs1_val == 262144, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x10000
+TEST_RR_OP(or, x12, x10, x11, 0x50000, 0x40000, 0x10000, x1, 288, x2)
+
+inst_92:
+// rs1_val == 131072, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x1000
+TEST_RR_OP(or, x12, x10, x11, 0x21000, 0x20000, 0x1000, x1, 292, x2)
+
+inst_93:
+// rs1_val == 65536, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x10006, 0x10000, 0x6, x1, 296, x2)
+
+inst_94:
+// rs1_val == 8192, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x8
+TEST_RR_OP(or, x12, x10, x11, 0x2008, 0x2000, 0x8, x1, 300, x2)
+
+inst_95:
+// rs1_val == 4096, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:-0x3
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, 0x1000, -0x3, x1, 304, x2)
+
+inst_96:
+// rs1_val == 2048, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555d55, 0x800, 0x55555555, x1, 308, x2)
+
+inst_97:
+// rs1_val == 512, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x20
+TEST_RR_OP(or, x12, x10, x11, 0x220, 0x200, 0x20, x1, 312, x2)
+
+inst_98:
+// rs1_val == 256, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:-0x81
+TEST_RR_OP(or, x12, x10, x11, 0xffffff7f, 0x100, -0x81, x1, 316, x2)
+
+inst_99:
+// rs1_val == 1, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2000000
+TEST_RR_OP(or, x12, x10, x11, 0x2000001, 0x1, 0x2000000, x1, 320, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb505, 0xb505, x1, 324, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, 0xb505, -0xb503, x1, 328, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb505, 0x66666667, x1, 332, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x3333b735, 0xb505, 0x33333334, x1, 336, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb505, 0x6, x1, 340, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, 0xb505, -0x55555555, x1, 344, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0xb505, 0x55555556, x1, 348, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb505, 0x4, x1, 352, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb505, 0xb503, x1, 356, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb505, 0x0, x1, 360, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x6666f765, 0xb505, 0x66666665, x1, 364, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0xb505, 0x33333332, x1, 368, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0xb505, 0x55555554, x1, 372, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb505, 0x2, x1, 376, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb505, 0xb504, x1, 380, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, 0xb505, -0xb504, x1, 384, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb505, 0x66666666, x1, 388, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0xb505, 0x33333333, x1, 392, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb505, 0x5, x1, 396, x2)
+
+inst_119:
+// rs1_val==46341 and rs2_val==-1431655766, rs2_val == -1431655766
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, 0xb505, -0x55555556, x1, 400, x2)
+
+inst_120:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0xb505, 0x55555555, x1, 404, x2)
+
+inst_121:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb505, 0x3, x1, 408, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, -0xb503, 0xb505, x1, 412, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, -0xb503, x1, 416, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, -0xb503, 0x66666667, x1, 420, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfd, -0xb503, 0x33333334, x1, 424, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, -0xb503, 0x6, x1, 428, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0xb503, -0x55555555, x1, 432, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffff5fff, -0xb503, 0x55555556, x1, 436, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, 0x4, x1, 440, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0xb503, 0xb503, x1, 444, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 448, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efd, -0xb503, 0x66666665, x1, 452, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, -0xb503, 0x33333332, x1, 456, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, -0xb503, 0x55555554, x1, 460, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, -0xb503, 0x2, x1, 464, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, -0xb503, 0xb504, x1, 468, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, -0xb504, x1, 472, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, -0xb503, 0x66666666, x1, 476, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, -0xb503, 0x33333333, x1, 480, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb503, 0x5, x1, 484, x2)
+
+inst_141:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0xb503, -0x55555556, x1, 488, x2)
+
+inst_142:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, -0xb503, 0x55555555, x1, 492, x2)
+
+inst_143:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, -0xb503, 0x3, x1, 496, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666667, 0xb505, x1, 500, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, 0x66666667, -0xb503, x1, 504, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x66666667, x1, 508, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x33333334, x1, 512, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x6, x1, 516, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, 0x66666667, -0x55555555, x1, 520, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x55555556, x1, 524, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x4, x1, 528, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666667, 0xb503, x1, 532, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 536, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x66666665, x1, 540, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x33333332, x1, 544, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x55555554, x1, 548, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x2, x1, 552, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666667, 0xb504, x1, 556, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, 0x66666667, -0xb504, x1, 560, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x66666666, x1, 564, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x33333333, x1, 568, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x5, x1, 572, x2)
+
+inst_163:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, 0x66666667, -0x55555556, x1, 576, x2)
+
+inst_164:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666667, 0x55555555, x1, 580, x2)
+
+inst_165:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666667, 0x3, x1, 584, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x3333b735, 0x33333334, 0xb505, x1, 588, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfd, 0x33333334, -0xb503, x1, 592, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333334, 0x66666667, x1, 596, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x33333334, 0x33333334, x1, 600, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333334, 0x6, x1, 604, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbf, 0x33333334, -0x55555555, x1, 608, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x33333334, 0x55555556, x1, 612, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x33333334, 0x4, x1, 616, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0x33333334, 0xb503, x1, 620, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 624, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x33333334, 0x66666665, x1, 628, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333334, 0x33333332, x1, 632, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777774, 0x33333334, 0x55555554, x1, 636, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333334, 0x2, x1, 640, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x3333b734, 0x33333334, 0xb504, x1, 644, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfc, 0x33333334, -0xb504, x1, 648, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x33333334, 0x66666666, x1, 652, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333334, 0x33333333, x1, 656, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x33333335, 0x33333334, 0x5, x1, 660, x2)
+
+inst_185:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbe, 0x33333334, -0x55555556, x1, 664, x2)
+
+inst_186:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x33333334, 0x55555555, x1, 668, x2)
+
+inst_187:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333334, 0x3, x1, 672, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x6, 0xb505, x1, 676, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, 0x6, -0xb503, x1, 680, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x6, 0x66666667, x1, 684, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x6, 0x33333334, x1, 688, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x6, 0x6, x1, 692, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, 0x6, -0x55555555, x1, 696, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x6, 0x55555556, x1, 700, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x6, 0x4, x1, 704, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x6, 0xb503, x1, 708, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x6, 0x0, x1, 712, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x6, 0x66666665, x1, 716, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x6, 0x33333332, x1, 720, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x6, 0x55555554, x1, 724, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x6, 0x2, x1, 728, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb506, 0x6, 0xb504, x1, 732, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afe, 0x6, -0xb504, x1, 736, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x6, 0x66666666, x1, 740, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x6, 0x33333333, x1, 744, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x6, 0x5, x1, 748, x2)
+
+inst_207:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaae, 0x6, -0x55555556, x1, 752, x2)
+
+inst_208:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x6, 0x55555555, x1, 756, x2)
+
+inst_209:
+// rs1_val==6 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x6, 0x3, x1, 760, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, -0x55555555, 0xb505, x1, 764, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0x55555555, -0xb503, x1, 768, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666667, x1, 772, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbf, -0x55555555, 0x33333334, x1, 776, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, -0x55555555, 0x6, x1, 780, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555555, x1, 784, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x55555555, 0x55555556, x1, 788, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x1, 792, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfab, -0x55555555, 0xb503, x1, 796, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 800, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666665, x1, 804, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, -0x55555555, 0x33333332, x1, 808, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x1, 812, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x2, x1, 816, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, -0x55555555, 0xb504, x1, 820, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0x55555555, -0xb504, x1, 824, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, -0x55555555, 0x66666666, x1, 828, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, -0x55555555, 0x33333333, x1, 832, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, -0x55555555, 0x5, x1, 836, x2)
+
+inst_229:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555555, -0x55555556, x1, 840, x2)
+
+inst_230:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x55555555, 0x55555555, x1, 844, x2)
+
+inst_231:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x3, x1, 848, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0x55555556, 0xb505, x1, 852, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff5fff, 0x55555556, -0xb503, x1, 856, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555556, 0x66666667, x1, 860, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x55555556, 0x33333334, x1, 864, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x6, x1, 868, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x55555556, -0x55555555, x1, 872, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x55555556, x1, 876, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x4, x1, 880, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0x55555556, 0xb503, x1, 884, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 888, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555556, 0x66666665, x1, 892, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x55555556, 0x33333332, x1, 896, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x55555554, x1, 900, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555556, 0x2, x1, 904, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x5555f556, 0x55555556, 0xb504, x1, 908, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffe, 0x55555556, -0xb504, x1, 912, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x55555556, 0x66666666, x1, 916, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555556, 0x33333333, x1, 920, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555556, 0x5, x1, 924, x2)
+
+inst_251:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, 0x55555556, -0x55555556, x1, 928, x2)
+
+inst_252:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555556, 0x55555555, x1, 932, x2)
+
+inst_253:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555556, 0x3, x1, 936, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0x4, 0xb505, x1, 940, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, 0x4, -0xb503, x1, 944, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x4, 0x66666667, x1, 948, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x4, 0x33333334, x1, 952, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x4, 0x6, x1, 956, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x1, 960, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x4, 0x55555556, x1, 964, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x4, 0x4, 0x4, x1, 968, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x4, 0xb503, x1, 972, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x4, 0x4, 0x0, x1, 976, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x4, 0x66666665, x1, 980, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x4, 0x33333332, x1, 984, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555554, 0x4, 0x55555554, x1, 988, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x4, 0x2, x1, 992, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb504, 0x4, 0xb504, x1, 996, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afc, 0x4, -0xb504, x1, 1000, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x4, 0x66666666, x1, 1004, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x4, 0x33333333, x1, 1008, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x5, 0x4, 0x5, x1, 1012, x2)
+
+inst_273:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x1, 1016, x2)
+
+inst_274:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x4, 0x55555555, x1, 1020, x2)
+
+inst_275:
+// rs1_val==4 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x4, 0x3, x1, 1024, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb503, 0xb505, x1, 1028, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0xb503, -0xb503, x1, 1032, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb503, 0x66666667, x1, 1036, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0xb503, 0x33333334, x1, 1040, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb503, 0x6, x1, 1044, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfab, 0xb503, -0x55555555, x1, 1048, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0xb503, 0x55555556, x1, 1052, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb503, 0x4, x1, 1056, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0xb503, 0xb503, x1, 1060, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 1064, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb503, 0x66666665, x1, 1068, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x3333b733, 0xb503, 0x33333332, x1, 1072, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0xb503, 0x55555554, x1, 1076, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0xb503, 0x2, x1, 1080, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb503, 0xb504, x1, 1084, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0xb503, -0xb504, x1, 1088, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb503, 0x66666666, x1, 1092, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x3333b733, 0xb503, 0x33333333, x1, 1096, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb503, 0x5, x1, 1100, x2)
+
+inst_295:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfab, 0xb503, -0x55555556, x1, 1104, x2)
+
+inst_296:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0xb503, 0x55555555, x1, 1108, x2)
+
+inst_297:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0xb503, 0x3, x1, 1112, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0x0, 0xb505, x1, 1116, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, 0x0, -0xb503, x1, 1120, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x0, 0x66666667, x1, 1124, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333334, 0x0, 0x33333334, x1, 1128, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x0, 0x6, x1, 1132, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x1, 1136, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x0, 0x55555556, x1, 1140, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x4, 0x0, 0x4, x1, 1144, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0x0, 0xb503, x1, 1148, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1152, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x0, 0x66666665, x1, 1156, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333332, 0x0, 0x33333332, x1, 1160, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555554, 0x0, 0x55555554, x1, 1164, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x2, 0x0, 0x2, x1, 1168, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb504, 0x0, 0xb504, x1, 1172, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afc, 0x0, -0xb504, x1, 1176, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x0, 0x66666666, x1, 1180, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x0, 0x33333333, x1, 1184, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x5, 0x0, 0x5, x1, 1188, x2)
+
+inst_317:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x1, 1192, x2)
+
+inst_318:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x0, 0x55555555, x1, 1196, x2)
+
+inst_319:
+// rs1_val==0 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x3, 0x0, 0x3, x1, 1200, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x6666f765, 0x66666665, 0xb505, x1, 1204, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efd, 0x66666665, -0xb503, x1, 1208, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666665, 0x66666667, x1, 1212, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x66666665, 0x33333334, x1, 1216, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666665, 0x6, x1, 1220, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, 0x66666665, -0x55555555, x1, 1224, x2)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666665, 0x55555556, x1, 1228, x2)
+
+inst_327:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x66666665, 0x4, x1, 1232, x2)
+
+inst_328:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666665, 0xb503, x1, 1236, x2)
+
+inst_329:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1240, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1244, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x66666665, x1, 1248, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333333, 0x33333332, x1, 1252, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x55555554, x1, 1256, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333333, 0x2, x1, 1260, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0x33333333, 0xb504, x1, 1264, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, 0x33333333, -0xb504, x1, 1268, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x66666666, x1, 1272, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333333, 0x33333333, x1, 1276, x2)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333333, 0x5, x1, 1280, x2)
+
+inst_340:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, 0x33333333, -0x55555556, x1, 1284, x2)
+
+inst_341:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x55555555, x1, 1288, x2)
+
+inst_342:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333333, 0x3, x1, 1292, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0x5, 0xb505, x1, 1296, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, 0x5, -0xb503, x1, 1300, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x5, 0x66666667, x1, 1304, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333335, 0x5, 0x33333334, x1, 1308, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x5, 0x6, x1, 1312, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, 0x5, -0x55555555, x1, 1316, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x5, 0x55555556, x1, 1320, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x5, 0x5, 0x4, x1, 1324, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x5, 0xb503, x1, 1328, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x5, 0x5, 0x0, x1, 1332, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x5, 0x66666665, x1, 1336, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x5, 0x33333332, x1, 1340, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x5, 0x55555554, x1, 1344, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x5, 0x2, x1, 1348, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0x5, 0xb504, x1, 1352, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, 0x5, -0xb504, x1, 1356, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x5, 0x66666666, x1, 1360, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x5, 0x33333333, x1, 1364, x2)
+
+inst_361:
+// rs1_val==5 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x5, 0x5, 0x5, x1, 1368, x2)
+
+inst_362:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x1, 1372, x2)
+
+inst_363:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x5, 0x55555555, x1, 1376, x2)
+
+inst_364:
+// rs1_val==5 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x5, 0x3, x1, 1380, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, -0x55555556, 0xb505, x1, 1384, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0x55555556, -0xb503, x1, 1388, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, -0x55555556, 0x66666667, x1, 1392, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbe, -0x55555556, 0x33333334, x1, 1396, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaae, -0x55555556, 0x6, x1, 1400, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555556, -0x55555555, x1, 1404, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, -0x55555556, 0x55555556, x1, 1408, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x1, 1412, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfab, -0x55555556, 0xb503, x1, 1416, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1420, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, -0x55555556, 0x66666665, x1, 1424, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbba, -0x55555556, 0x33333332, x1, 1428, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x1, 1432, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaa, -0x55555556, 0x2, x1, 1436, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfae, -0x55555556, 0xb504, x1, 1440, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffffeafe, -0x55555556, -0xb504, x1, 1444, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeee, -0x55555556, 0x66666666, x1, 1448, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, -0x55555556, 0x33333333, x1, 1452, x2)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1456, x2)
+
+inst_384:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaa, -0x55555556, -0x55555556, x1, 1460, x2)
+
+inst_385:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x1, 1464, x2)
+
+inst_386:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, -0x55555556, 0x3, x1, 1468, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0x55555555, 0xb505, x1, 1472, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, 0x55555555, -0xb503, x1, 1476, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555555, 0x66666667, x1, 1480, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x55555555, 0x33333334, x1, 1484, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555555, 0x6, x1, 1488, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x55555555, -0x55555555, x1, 1492, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555555, 0x55555556, x1, 1496, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555555, 0x4, x1, 1500, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0x55555555, 0xb503, x1, 1504, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1508, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x55555555, 0x66666665, x1, 1512, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555555, 0x33333332, x1, 1516, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555555, 0x55555554, x1, 1520, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555555, 0x2, x1, 1524, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0x55555555, 0xb504, x1, 1528, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, 0x55555555, -0xb504, x1, 1532, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555555, 0x66666666, x1, 1536, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555555, 0x33333333, x1, 1540, x2)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555555, 0x5, x1, 1544, x2)
+
+inst_406:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x1, 1548, x2)
+
+inst_407:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555555, 0x55555555, x1, 1552, x2)
+
+inst_408:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555555, 0x3, x1, 1556, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x3, 0xb505, x1, 1560, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, 0x3, -0xb503, x1, 1564, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x3, 0x66666667, x1, 1568, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x3, 0x33333334, x1, 1572, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x3, 0x6, x1, 1576, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, 0x3, -0x55555555, x1, 1580, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x3, 0x55555556, x1, 1584, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x3, 0x4, x1, 1588, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0x3, 0xb503, x1, 1592, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x3, 0x3, 0x0, x1, 1596, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x3, 0x66666665, x1, 1600, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x3, 0x33333332, x1, 1604, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x3, 0x55555554, x1, 1608, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x3, 0x3, 0x2, x1, 1612, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x3, 0xb504, x1, 1616, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, 0x3, -0xb504, x1, 1620, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x3, 0x66666666, x1, 1624, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x3, 0x33333333, x1, 1628, x2)
+
+inst_427:
+// rs1_val==3 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x3, 0x5, x1, 1632, x2)
+
+inst_428:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, 0x3, -0x55555556, x1, 1636, x2)
+
+inst_429:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x3, 0x55555555, x1, 1640, x2)
+
+inst_430:
+// rs1_val==3 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x3, 0x3, 0x3, x1, 1644, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x66666665, 0x66666665, x1, 1648, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666665, 0x33333332, x1, 1652, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x66666665, 0x55555554, x1, 1656, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666665, 0x2, x1, 1660, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x6666f765, 0x66666665, 0xb504, x1, 1664, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efd, 0x66666665, -0xb504, x1, 1668, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666665, 0x66666666, x1, 1672, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666665, 0x33333333, x1, 1676, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x66666665, 0x66666665, 0x5, x1, 1680, x2)
+
+inst_440:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, 0x66666665, -0x55555556, x1, 1684, x2)
+
+inst_441:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x66666665, 0x55555555, x1, 1688, x2)
+
+inst_442:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666665, 0x3, x1, 1692, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0x33333332, 0xb505, x1, 1696, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, 0x33333332, -0xb503, x1, 1700, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333332, 0x66666667, x1, 1704, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333332, 0x33333334, x1, 1708, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333332, 0x6, x1, 1712, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, 0x33333332, -0x55555555, x1, 1716, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x33333332, 0x55555556, x1, 1720, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x33333332, 0x4, x1, 1724, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x3333b733, 0x33333332, 0xb503, x1, 1728, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1732, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333332, 0x66666665, x1, 1736, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333332, 0x33333332, 0x33333332, x1, 1740, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x33333332, 0x55555554, x1, 1744, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x33333332, 0x33333332, 0x2, x1, 1748, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x3333b736, 0x33333332, 0xb504, x1, 1752, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfe, 0x33333332, -0xb504, x1, 1756, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x33333332, 0x66666666, x1, 1760, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333332, 0x33333333, x1, 1764, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333332, 0x5, x1, 1768, x2)
+
+inst_462:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbba, 0x33333332, -0x55555556, x1, 1772, x2)
+
+inst_463:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333332, 0x55555555, x1, 1776, x2)
+
+inst_464:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x33333332, 0x3, x1, 1780, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0x55555554, 0xb505, x1, 1784, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, 0x55555554, -0xb503, x1, 1788, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555554, 0x66666667, x1, 1792, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777774, 0x55555554, 0x33333334, x1, 1796, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555554, 0x6, x1, 1800, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x1, 1804, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555554, 0x55555556, x1, 1808, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x55555554, 0x55555554, 0x4, x1, 1812, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x5555f557, 0x55555554, 0xb503, x1, 1816, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1820, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x77777775, 0x55555554, 0x66666665, x1, 1824, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x55555554, 0x33333332, x1, 1828, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555554, 0x55555554, 0x55555554, x1, 1832, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x55555554, 0x2, x1, 1836, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x5555f554, 0x55555554, 0xb504, x1, 1840, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffc, 0x55555554, -0xb504, x1, 1844, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x55555554, 0x66666666, x1, 1848, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x55555554, 0x33333333, x1, 1852, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555554, 0x5, x1, 1856, x2)
+
+inst_484:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x1, 1860, x2)
+
+inst_485:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555555, 0x55555554, 0x55555555, x1, 1864, x2)
+
+inst_486:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x55555554, 0x3, x1, 1868, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0x2, 0xb505, x1, 1872, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, 0x2, -0xb503, x1, 1876, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x2, 0x66666667, x1, 1880, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333336, 0x2, 0x33333334, x1, 1884, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x2, 0x6, x1, 1888, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaab, 0x2, -0x55555555, x1, 1892, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x2, 0x55555556, x1, 1896, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x6, 0x2, 0x4, x1, 1900, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb503, 0x2, 0xb503, x1, 1904, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x2, 0x2, 0x0, x1, 1908, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x2, 0x66666665, x1, 1912, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x33333332, 0x2, 0x33333332, x1, 1916, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x55555556, 0x2, 0x55555554, x1, 1920, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x2, 0x2, 0x2, x1, 1924, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb506, 0x2, 0xb504, x1, 1928, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afe, 0x2, -0xb504, x1, 1932, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x2, 0x66666666, x1, 1936, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x33333333, 0x2, 0x33333333, x1, 1940, x2)
+
+inst_505:
+// rs1_val==2 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x7, 0x2, 0x5, x1, 1944, x2)
+
+inst_506:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaaaaaa, 0x2, -0x55555556, x1, 1948, x2)
+
+inst_507:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x55555557, 0x2, 0x55555555, x1, 1952, x2)
+
+inst_508:
+// rs1_val==2 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x3, 0x2, 0x3, x1, 1956, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb504, 0xb505, x1, 1960, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, 0xb504, -0xb503, x1, 1964, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0xb504, 0x66666667, x1, 1968, x2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x3333b734, 0xb504, 0x33333334, x1, 1972, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xb506, 0xb504, 0x6, x1, 1976, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfaf, 0xb504, -0x55555555, x1, 1980, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x5555f556, 0xb504, 0x55555556, x1, 1984, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xb504, 0xb504, 0x4, x1, 1988, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb504, 0xb503, x1, 1992, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xb504, 0xb504, 0x0, x1, 1996, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x6666f765, 0xb504, 0x66666665, x1, 2000, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x3333b736, 0xb504, 0x33333332, x1, 2004, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x5555f554, 0xb504, 0x55555554, x1, 2008, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xb506, 0xb504, 0x2, x1, 2012, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xb504, 0xb504, 0xb504, x1, 2016, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffc, 0xb504, -0xb504, x1, 2020, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x6666f766, 0xb504, 0x66666666, x1, 2024, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0xb504, 0x33333333, x1, 2028, x2)
+
+inst_527:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xb505, 0xb504, 0x5, x1, 2032, x2)
+
+inst_528:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xaaaabfae, 0xb504, -0x55555556, x1, 2036, x2)
+
+inst_529:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x5555f555, 0xb504, 0x55555555, x1, 2040, x2)
+
+inst_530:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xb507, 0xb504, 0x3, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffd, -0xb504, 0xb505, x1, 0, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb504, -0xb503, x1, 4, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, -0xb504, 0x66666667, x1, 8, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfc, -0xb504, 0x33333334, x1, 12, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afe, -0xb504, 0x6, x1, 16, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffffeaff, -0xb504, -0x55555555, x1, 20, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffe, -0xb504, 0x55555556, x1, 24, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afc, -0xb504, 0x4, x1, 28, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 32, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 36, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efd, -0xb504, 0x66666665, x1, 40, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bfe, -0xb504, 0x33333332, x1, 44, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffc, -0xb504, 0x55555554, x1, 48, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afe, -0xb504, 0x2, x1, 52, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xfffffffc, -0xb504, 0xb504, x1, 56, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afc, -0xb504, -0xb504, x1, 60, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efe, -0xb504, 0x66666666, x1, 64, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, -0xb504, 0x33333333, x1, 68, x2)
+
+inst_549:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0xffff4afd, -0xb504, 0x5, x1, 72, x2)
+
+inst_550:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xffffeafe, -0xb504, -0x55555556, x1, 76, x2)
+
+inst_551:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xffff5ffd, -0xb504, 0x55555555, x1, 80, x2)
+
+inst_552:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0xffff4aff, -0xb504, 0x3, x1, 84, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666666, 0xb505, x1, 88, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff6eff, 0x66666666, -0xb503, x1, 92, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666666, 0x66666667, x1, 96, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x66666666, 0x33333334, x1, 100, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x66666666, 0x6, x1, 104, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeef, 0x66666666, -0x55555555, x1, 108, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x66666666, 0x55555556, x1, 112, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x66666666, 0x4, x1, 116, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x6666f767, 0x66666666, 0xb503, x1, 120, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 124, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666666, 0x66666665, x1, 128, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x66666666, 0x33333332, x1, 132, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(or, x12, x10, x11, 0x77777776, 0x66666666, 0x55555554, x1, 136, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x66666666, 0x2, x1, 140, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(or, x12, x10, x11, 0x6666f766, 0x66666666, 0xb504, x1, 144, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(or, x12, x10, x11, 0xffff6efe, 0x66666666, -0xb504, x1, 148, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(or, x12, x10, x11, 0x66666666, 0x66666666, 0x66666666, x1, 152, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666666, 0x33333333, x1, 156, x2)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666666, 0x5, x1, 160, x2)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0xeeeeeeee, 0x66666666, -0x55555556, x1, 164, x2)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x66666666, 0x55555555, x1, 168, x2)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(or, x12, x10, x11, 0x66666667, 0x66666666, 0x3, x1, 172, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(or, x12, x10, x11, 0x3333b737, 0x33333333, 0xb505, x1, 176, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(or, x12, x10, x11, 0xffff7bff, 0x33333333, -0xb503, x1, 180, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x66666667, x1, 184, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333333, 0x33333334, x1, 188, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333333, 0x6, x1, 192, x2)
+
+inst_580:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(or, x12, x10, x11, 0xbbbbbbbb, 0x33333333, -0x55555555, x1, 196, x2)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(or, x12, x10, x11, 0x77777777, 0x33333333, 0x55555556, x1, 200, x2)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(or, x12, x10, x11, 0x33333337, 0x33333333, 0x4, x1, 204, x2)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(or, x12, x10, x11, 0x3333b733, 0x33333333, 0xb503, x1, 208, x2)
+
+inst_584:
+// rs2_val == -536870913, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000;  op2val:-0x20000001
+TEST_RR_OP(or, x12, x10, x11, 0xdfffffff, -0x40000000, -0x20000001, x1, 212, x2)
+
+inst_585:
+// rs2_val == -268435457, rs1_val == 16384, rs1_val > 0 and rs2_val < 0
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x10000001
+TEST_RR_OP(or, x12, x10, x11, 0xefffffff, 0x4000, -0x10000001, x1, 216, x2)
+
+inst_586:
+// rs2_val == -16777217, rs1_val == 0
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x1000001
+TEST_RR_OP(or, x12, x10, x11, 0xfeffffff, 0x0, -0x1000001, x1, 220, x2)
+
+inst_587:
+// rs2_val == -8388609, 
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x800001
+TEST_RR_OP(or, x12, x10, x11, 0xff7fffff, 0x6, -0x800001, x1, 224, x2)
+
+inst_588:
+// rs2_val == -524289, rs1_val == -33
+// opcode: or ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x80001
+TEST_RR_OP(or, x12, x10, x11, 0xffffffff, -0x21, -0x80001, x1, 228, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_2:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 58*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S
new file mode 100644
index 000000000..3c8078862
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S
@@ -0,0 +1,2866 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the ori instruction of the RISC-V E extension for the ori covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",ori)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x12, rd==x9, imm_val == (-2**(12-1)), rs1_val > 0 and imm_val < 0, rs1_val != imm_val, imm_val == -2048, rs1_val == 2097152
+// opcode: ori ; op1:x12; dest:x9; op1val:0x200000;  immval:-0x800
+TEST_IMM_OP( ori, x9, x12, 0xfffff800, 0x200000, -0x800, x1, 0, x2)
+
+inst_1:
+// rs1 == rd, rs1==x0, rd==x0, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: ori ; op1:x0; dest:x0; op1val:0x0;  immval:0x3ff
+TEST_IMM_OP( ori, x0, x0, 0, 0x0, 0x3ff, x1, 4, x2)
+
+inst_2:
+// rs1==x6, rd==x7, rs1_val == -1073741825, rs1_val < 0 and imm_val > 0, imm_val == 1024
+// opcode: ori ; op1:x6; dest:x7; op1val:-0x40000001;  immval:0x400
+TEST_IMM_OP( ori, x7, x6, 0xbfffffff, -0x40000001, 0x400, x1, 8, x2)
+
+inst_3:
+// rs1==x9, rd==x3, rs1_val == -536870913, 
+// opcode: ori ; op1:x9; dest:x3; op1val:-0x20000001;  immval:0x2d
+TEST_IMM_OP( ori, x3, x9, 0xdfffffff, -0x20000001, 0x2d, x1, 12, x2)
+
+inst_4:
+// rs1==x5, rd==x14, rs1_val == -268435457, 
+// opcode: ori ; op1:x5; dest:x14; op1val:-0x10000001;  immval:0x666
+TEST_IMM_OP( ori, x14, x5, 0xefffffff, -0x10000001, 0x666, x1, 16, x2)
+
+inst_5:
+// rs1==x13, rd==x11, rs1_val == -134217729, imm_val == 2
+// opcode: ori ; op1:x13; dest:x11; op1val:-0x8000001;  immval:0x2
+TEST_IMM_OP( ori, x11, x13, 0xf7ffffff, -0x8000001, 0x2, x1, 20, x2)
+
+inst_6:
+// rs1==x3, rd==x5, rs1_val == -67108865, 
+// opcode: ori ; op1:x3; dest:x5; op1val:-0x4000001;  immval:0x2
+TEST_IMM_OP( ori, x5, x3, 0xfbffffff, -0x4000001, 0x2, x1, 24, x2)
+
+inst_7:
+// rs1==x11, rd==x12, rs1_val == -33554433, 
+// opcode: ori ; op1:x11; dest:x12; op1val:-0x2000001;  immval:0x3
+TEST_IMM_OP( ori, x12, x11, 0xfdffffff, -0x2000001, 0x3, x1, 28, x2)
+
+inst_8:
+// rs1==x10, rd==x15, rs1_val == -16777217, imm_val == 1
+// opcode: ori ; op1:x10; dest:x15; op1val:-0x1000001;  immval:0x1
+TEST_IMM_OP( ori, x15, x10, 0xfeffffff, -0x1000001, 0x1, x1, 32, x2)
+
+inst_9:
+// rs1==x4, rd==x13, rs1_val == -8388609, rs1_val < 0 and imm_val < 0
+// opcode: ori ; op1:x4; dest:x13; op1val:-0x800001;  immval:-0x555
+TEST_IMM_OP( ori, x13, x4, 0xffffffff, -0x800001, -0x555, x1, 36, x5)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_10:
+// rs1==x15, rd==x10, rs1_val == -4194305, imm_val == -3
+// opcode: ori ; op1:x15; dest:x10; op1val:-0x400001;  immval:-0x3
+TEST_IMM_OP( ori, x10, x15, 0xffffffff, -0x400001, -0x3, x3, 0, x5)
+
+inst_11:
+// rs1==x7, rd==x4, rs1_val == -2097153, imm_val == 1365
+// opcode: ori ; op1:x7; dest:x4; op1val:-0x200001;  immval:0x555
+TEST_IMM_OP( ori, x4, x7, 0xffdfffff, -0x200001, 0x555, x3, 4, x5)
+
+inst_12:
+// rs1==x2, rd==x6, rs1_val == -1048577, imm_val == -5
+// opcode: ori ; op1:x2; dest:x6; op1val:-0x100001;  immval:-0x5
+TEST_IMM_OP( ori, x6, x2, 0xffffffff, -0x100001, -0x5, x3, 8, x5)
+
+inst_13:
+// rs1==x8, rd==x1, rs1_val == -524289, 
+// opcode: ori ; op1:x8; dest:x1; op1val:-0x80001;  immval:-0x3
+TEST_IMM_OP( ori, x1, x8, 0xffffffff, -0x80001, -0x3, x3, 12, x5)
+
+inst_14:
+// rs1==x1, rd==x2, rs1_val == -262145, 
+// opcode: ori ; op1:x1; dest:x2; op1val:-0x40001;  immval:0x333
+TEST_IMM_OP( ori, x2, x1, 0xfffbffff, -0x40001, 0x333, x3, 16, x5)
+
+inst_15:
+// rs1==x14, rd==x8, rs1_val == -131073, 
+// opcode: ori ; op1:x14; dest:x8; op1val:-0x20001;  immval:0x332
+TEST_IMM_OP( ori, x8, x14, 0xfffdffff, -0x20001, 0x332, x3, 20, x5)
+
+inst_16:
+// rs1_val == -65537, imm_val == 4
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x10001;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xfffeffff, -0x10001, 0x4, x3, 24, x5)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xffff7fff, -0x8001, 0x555, x3, 28, x1)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xffffbfff, -0x4001, 0x666, x3, 32, x1)
+
+inst_19:
+// rs1_val == -8193, imm_val == -9
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x2001;  immval:-0x9
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x2001, -0x9, x3, 36, x1)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x1001, -0x2d, x3, 40, x1)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x801;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xfffff7ff, -0x801, 0x666, x3, 44, x1)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x401;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x401, -0x2c, x3, 48, x1)
+
+inst_23:
+// rs1_val == -513, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x201;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffdff, -0x201, 0x555, x3, 52, x1)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x101;  immval:-0x3
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x101, -0x3, x3, 56, x1)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x81;  immval:-0x9
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x81, -0x9, x3, 60, x1)
+
+inst_26:
+// rs1_val == -65, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x41;  immval:-0x4
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x41, -0x4, x3, 64, x1)
+
+inst_27:
+// rs1_val == -33, imm_val == -17
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x21;  immval:-0x11
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x21, -0x11, x3, 68, x1)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x11;  immval:-0x5
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x11, -0x5, x3, 72, x1)
+
+inst_29:
+// rs1_val == -9, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x9;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, -0x9, 0x4, x3, 76, x1)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x5;  immval:-0x7
+TEST_IMM_OP( ori, x11, x10, 0xfffffffb, -0x5, -0x7, x3, 80, x1)
+
+inst_31:
+// rs1_val == -3, imm_val == -65
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x3;  immval:-0x41
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x3, -0x41, x3, 84, x1)
+
+inst_32:
+// rs1_val == -2, imm_val == -129
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x2;  immval:-0x81
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x2, -0x81, x3, 88, x1)
+
+inst_33:
+// imm_val == 2047, imm_val == (2**(12-1)-1), rs1_val == 8192
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2000;  immval:0x7ff
+TEST_IMM_OP( ori, x11, x10, 0x27ff, 0x2000, 0x7ff, x3, 92, x1)
+
+inst_34:
+// imm_val == -1025, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x401
+TEST_IMM_OP( ori, x11, x10, 0xfffffbff, 0x6, -0x401, x3, 96, x1)
+
+inst_35:
+// imm_val == -513, rs1_val == 131072
+// opcode: ori ; op1:x10; dest:x11; op1val:0x20000;  immval:-0x201
+TEST_IMM_OP( ori, x11, x10, 0xfffffdff, 0x20000, -0x201, x3, 100, x1)
+
+inst_36:
+// imm_val == -257, rs1_val == 1431655765
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x101
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x55555555, -0x101, x3, 104, x1)
+
+inst_37:
+// imm_val == -33, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x21
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x55555555, -0x21, x3, 108, x1)
+
+inst_38:
+// imm_val == -2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x200001;  immval:-0x2
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x200001, -0x2, x3, 112, x1)
+
+inst_39:
+// rs1_val == -2147483648, imm_val == 0, rs1_val == (-2**(xlen-1))
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x80000000, -0x80000000, 0x0, x3, 116, x1)
+
+inst_40:
+// rs1_val == 1073741824, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x40000000;  immval:-0x2
+TEST_IMM_OP( ori, x11, x10, 0xfffffffe, 0x40000000, -0x2, x3, 120, x1)
+
+inst_41:
+// rs1_val == 536870912, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x20000555, 0x20000000, 0x555, x3, 124, x1)
+
+inst_42:
+// rs1_val == 268435456, imm_val == -1366
+// opcode: ori ; op1:x10; dest:x11; op1val:0x10000000;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaa, 0x10000000, -0x556, x3, 128, x1)
+
+inst_43:
+// rs1_val == 134217728, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x8000000;  immval:-0x1
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x8000000, -0x1, x3, 132, x1)
+
+inst_44:
+// rs1_val == 67108864, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x4000332, 0x4000000, 0x332, x3, 136, x1)
+
+inst_45:
+// rs1_val == 33554432, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x2000556, 0x2000000, 0x556, x3, 140, x1)
+
+inst_46:
+// rs1_val == 16777216, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x1000000;  immval:-0x401
+TEST_IMM_OP( ori, x11, x10, 0xfffffbff, 0x1000000, -0x401, x3, 144, x1)
+
+inst_47:
+// rs1_val == 8388608, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x800000;  immval:-0x101
+TEST_IMM_OP( ori, x11, x10, 0xfffffeff, 0x800000, -0x101, x3, 148, x1)
+
+inst_48:
+// rs1_val == 4194304, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x400000;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x400000, 0x400000, 0x0, x3, 152, x1)
+
+inst_49:
+// rs1_val == 1048576, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x100000;  immval:-0x21
+TEST_IMM_OP( ori, x11, x10, 0xffffffdf, 0x100000, -0x21, x3, 156, x1)
+
+inst_50:
+// rs1_val == 524288, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x80000;  immval:-0x401
+TEST_IMM_OP( ori, x11, x10, 0xfffffbff, 0x80000, -0x401, x3, 160, x1)
+
+inst_51:
+// rs1_val == 262144, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x40000;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x40556, 0x40000, 0x556, x3, 164, x1)
+
+inst_52:
+// rs1_val == 65536, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x10000;  immval:0x1
+TEST_IMM_OP( ori, x11, x10, 0x10001, 0x10000, 0x1, x3, 168, x1)
+
+inst_53:
+// rs1_val == 32768, imm_val == 512
+// opcode: ori ; op1:x10; dest:x11; op1val:0x8000;  immval:0x200
+TEST_IMM_OP( ori, x11, x10, 0x8200, 0x8000, 0x200, x3, 172, x1)
+
+inst_54:
+// rs1_val == 16384, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4000;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0x4000, -0x2c, x3, 176, x1)
+
+inst_55:
+// rs1_val == 4096, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x1000;  immval:-0x8
+TEST_IMM_OP( ori, x11, x10, 0xfffffff8, 0x1000, -0x8, x3, 180, x1)
+
+inst_56:
+// rs1_val == 2048, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x800;  immval:-0x8
+TEST_IMM_OP( ori, x11, x10, 0xfffffff8, 0x800, -0x8, x3, 184, x1)
+
+inst_57:
+// rs1_val == 1024, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x400;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd3, 0x400, -0x2d, x3, 188, x1)
+
+inst_58:
+// rs1_val == 512, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x200;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0x200, -0x2c, x3, 192, x1)
+
+inst_59:
+// rs1_val == 256, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x100;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x102, 0x100, 0x2, x3, 196, x1)
+
+inst_60:
+// rs1_val == 128, rs1_val == imm_val, imm_val == 128
+// opcode: ori ; op1:x10; dest:x11; op1val:0x80;  immval:0x80
+TEST_IMM_OP( ori, x11, x10, 0x80, 0x80, 0x80, x3, 200, x1)
+
+inst_61:
+// rs1_val == 64, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x40;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x46, 0x40, 0x6, x3, 204, x1)
+
+inst_62:
+// rs1_val == 32, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x20;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff4, 0x20, -0x2c, x3, 208, x1)
+
+inst_63:
+// rs1_val == 16, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x10;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x555, 0x10, 0x555, x3, 212, x1)
+
+inst_64:
+// rs1_val == 8, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x8;  immval:-0xa
+TEST_IMM_OP( ori, x11, x10, 0xfffffffe, 0x8, -0xa, x3, 216, x1)
+
+inst_65:
+// rs1_val == 4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x3ff
+TEST_IMM_OP( ori, x11, x10, 0x3ff, 0x4, 0x3ff, x3, 220, x1)
+
+inst_66:
+// rs1_val == 2, rs1_val==2 and imm_val==2
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x2, 0x2, 0x2, x3, 224, x1)
+
+inst_67:
+// rs1_val == 1, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x1;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x1, 0x1, 0x0, x3, 228, x1)
+
+inst_68:
+// imm_val == 256, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x100
+TEST_IMM_OP( ori, x11, x10, 0x20000100, 0x20000000, 0x100, x3, 232, x1)
+
+inst_69:
+// imm_val == 64, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x40
+TEST_IMM_OP( ori, x11, x10, 0x44, 0x4, 0x40, x3, 236, x1)
+
+inst_70:
+// imm_val == 32, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x20
+TEST_IMM_OP( ori, x11, x10, 0x33333334, 0x33333334, 0x20, x3, 240, x1)
+
+inst_71:
+// imm_val == 16, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x10
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x10, x3, 244, x1)
+
+inst_72:
+// imm_val == 8, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x8;  immval:0x8
+TEST_IMM_OP( ori, x11, x10, 0xfffffff8, -0x8, 0x8, x3, 248, x1)
+
+inst_73:
+// rs1_val==46341 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xb52f, 0xb505, 0x2e, x3, 252, x1)
+
+inst_74:
+// rs1_val==46341 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd5, 0xb505, -0x2c, x3, 256, x1)
+
+inst_75:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb505, 0x667, x3, 260, x1)
+
+inst_76:
+// rs1_val==46341 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xb735, 0xb505, 0x334, x3, 264, x1)
+
+inst_77:
+// rs1_val==46341 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb505, 0x6, x3, 268, x1)
+
+inst_78:
+// rs1_val==46341 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffaf, 0xb505, -0x555, x3, 272, x1)
+
+inst_79:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xb557, 0xb505, 0x556, x3, 276, x1)
+
+inst_80:
+// rs1_val==46341 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xb505, 0xb505, 0x4, x3, 280, x1)
+
+inst_81:
+// rs1_val==46341 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xb52d, 0xb505, 0x2c, x3, 284, x1)
+
+inst_82:
+// rs1_val==46341 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xb505, 0xb505, 0x0, x3, 288, x1)
+
+inst_83:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xb765, 0xb505, 0x665, x3, 292, x1)
+
+inst_84:
+// rs1_val==46341 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xb737, 0xb505, 0x332, x3, 296, x1)
+
+inst_85:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xb555, 0xb505, 0x554, x3, 300, x1)
+
+inst_86:
+// rs1_val==46341 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb505, 0x2, x3, 304, x1)
+
+inst_87:
+// rs1_val==46341 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xb52d, 0xb505, 0x2d, x3, 308, x1)
+
+inst_88:
+// rs1_val==46341 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0xb505, -0x2d, x3, 312, x1)
+
+inst_89:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb505, 0x666, x3, 316, x1)
+
+inst_90:
+// rs1_val==46341 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xb737, 0xb505, 0x333, x3, 320, x1)
+
+inst_91:
+// rs1_val==46341 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xb505, 0xb505, 0x5, x3, 324, x1)
+
+inst_92:
+// rs1_val==46341 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xffffffaf, 0xb505, -0x556, x3, 328, x1)
+
+inst_93:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xb555, 0xb505, 0x555, x3, 332, x1)
+
+inst_94:
+// rs1_val==46341 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb505, 0x3, x3, 336, x1)
+
+inst_95:
+// rs1_val==-46339 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xffff4aff, -0xb503, 0x2e, x3, 340, x1)
+
+inst_96:
+// rs1_val==-46339 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffffd, -0xb503, -0x2c, x3, 344, x1)
+
+inst_97:
+// rs1_val==-46339 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xffff4eff, -0xb503, 0x667, x3, 348, x1)
+
+inst_98:
+// rs1_val==-46339 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xffff4bfd, -0xb503, 0x334, x3, 352, x1)
+
+inst_99:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xffff4aff, -0xb503, 0x6, x3, 356, x1)
+
+inst_100:
+// rs1_val==-46339 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaff, -0xb503, -0x555, x3, 360, x1)
+
+inst_101:
+// rs1_val==-46339 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xffff4fff, -0xb503, 0x556, x3, 364, x1)
+
+inst_102:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb503, 0x4, x3, 368, x1)
+
+inst_103:
+// rs1_val==-46339 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb503, 0x2c, x3, 372, x1)
+
+inst_104:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb503, 0x0, x3, 376, x1)
+
+inst_105:
+// rs1_val==-46339 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xffff4efd, -0xb503, 0x665, x3, 380, x1)
+
+inst_106:
+// rs1_val==-46339 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xffff4bff, -0xb503, 0x332, x3, 384, x1)
+
+inst_107:
+// rs1_val==-46339 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xffff4ffd, -0xb503, 0x554, x3, 388, x1)
+
+inst_108:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xffff4aff, -0xb503, 0x2, x3, 392, x1)
+
+inst_109:
+// rs1_val==-46339 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb503, 0x2d, x3, 396, x1)
+
+inst_110:
+// rs1_val==-46339 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0xb503, -0x2d, x3, 400, x1)
+
+inst_111:
+// rs1_val==-46339 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xffff4eff, -0xb503, 0x666, x3, 404, x1)
+
+inst_112:
+// rs1_val==-46339 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xffff4bff, -0xb503, 0x333, x3, 408, x1)
+
+inst_113:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb503, 0x5, x3, 412, x1)
+
+inst_114:
+// rs1_val==-46339 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaff, -0xb503, -0x556, x3, 416, x1)
+
+inst_115:
+// rs1_val==-46339 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xffff4ffd, -0xb503, 0x555, x3, 420, x1)
+
+inst_116:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xffff4aff, -0xb503, 0x3, x3, 424, x1)
+
+inst_117:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x6666666f, 0x66666667, 0x2e, x3, 428, x1)
+
+inst_118:
+// rs1_val==1717986919 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x66666667, -0x2c, x3, 432, x1)
+
+inst_119:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x667, x3, 436, x1)
+
+inst_120:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x334, x3, 440, x1)
+
+inst_121:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x6, x3, 444, x1)
+
+inst_122:
+// rs1_val==1717986919 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffeef, 0x66666667, -0x555, x3, 448, x1)
+
+inst_123:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x556, x3, 452, x1)
+
+inst_124:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x4, x3, 456, x1)
+
+inst_125:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x6666666f, 0x66666667, 0x2c, x3, 460, x1)
+
+inst_126:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x0, x3, 464, x1)
+
+inst_127:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x665, x3, 468, x1)
+
+inst_128:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x332, x3, 472, x1)
+
+inst_129:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x554, x3, 476, x1)
+
+inst_130:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x2, x3, 480, x1)
+
+inst_131:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x6666666f, 0x66666667, 0x2d, x3, 484, x1)
+
+inst_132:
+// rs1_val==1717986919 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x66666667, -0x2d, x3, 488, x1)
+
+inst_133:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x666, x3, 492, x1)
+
+inst_134:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x333, x3, 496, x1)
+
+inst_135:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x5, x3, 500, x1)
+
+inst_136:
+// rs1_val==1717986919 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffeef, 0x66666667, -0x556, x3, 504, x1)
+
+inst_137:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666667, 0x555, x3, 508, x1)
+
+inst_138:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666667, 0x3, x3, 512, x1)
+
+inst_139:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x3333333e, 0x33333334, 0x2e, x3, 516, x1)
+
+inst_140:
+// rs1_val==858993460 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff4, 0x33333334, -0x2c, x3, 520, x1)
+
+inst_141:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333334, 0x667, x3, 524, x1)
+
+inst_142:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x33333334, 0x33333334, 0x334, x3, 528, x1)
+
+inst_143:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333334, 0x6, x3, 532, x1)
+
+inst_144:
+// rs1_val==858993460 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffbbf, 0x33333334, -0x555, x3, 536, x1)
+
+inst_145:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x33333776, 0x33333334, 0x556, x3, 540, x1)
+
+inst_146:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x33333334, 0x33333334, 0x4, x3, 544, x1)
+
+inst_147:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x3333333c, 0x33333334, 0x2c, x3, 548, x1)
+
+inst_148:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x33333334, 0x33333334, 0x0, x3, 552, x1)
+
+inst_149:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x33333775, 0x33333334, 0x665, x3, 556, x1)
+
+inst_150:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333334, 0x332, x3, 560, x1)
+
+inst_151:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x33333774, 0x33333334, 0x554, x3, 564, x1)
+
+inst_152:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333334, 0x2, x3, 568, x1)
+
+inst_153:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x3333333d, 0x33333334, 0x2d, x3, 572, x1)
+
+inst_154:
+// rs1_val==858993460 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x33333334, -0x2d, x3, 576, x1)
+
+inst_155:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x33333776, 0x33333334, 0x666, x3, 580, x1)
+
+inst_156:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333334, 0x333, x3, 584, x1)
+
+inst_157:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x33333335, 0x33333334, 0x5, x3, 588, x1)
+
+inst_158:
+// rs1_val==858993460 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffbbe, 0x33333334, -0x556, x3, 592, x1)
+
+inst_159:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x33333775, 0x33333334, 0x555, x3, 596, x1)
+
+inst_160:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333334, 0x3, x3, 600, x1)
+
+inst_161:
+// rs1_val==6 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x6, 0x2e, x3, 604, x1)
+
+inst_162:
+// rs1_val==6 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd6, 0x6, -0x2c, x3, 608, x1)
+
+inst_163:
+// rs1_val==6 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x6, 0x667, x3, 612, x1)
+
+inst_164:
+// rs1_val==6 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x336, 0x6, 0x334, x3, 616, x1)
+
+inst_165:
+// rs1_val==6 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x6, 0x6, x3, 620, x1)
+
+inst_166:
+// rs1_val==6 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaf, 0x6, -0x555, x3, 624, x1)
+
+inst_167:
+// rs1_val==6 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x6, 0x556, x3, 628, x1)
+
+inst_168:
+// rs1_val==6 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x6, 0x4, x3, 632, x1)
+
+inst_169:
+// rs1_val==6 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x6, 0x2c, x3, 636, x1)
+
+inst_170:
+// rs1_val==6 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x6, 0x0, x3, 640, x1)
+
+inst_171:
+// rs1_val==6 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x6, 0x665, x3, 644, x1)
+
+inst_172:
+// rs1_val==6 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x336, 0x6, 0x332, x3, 648, x1)
+
+inst_173:
+// rs1_val==6 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x6, 0x554, x3, 652, x1)
+
+inst_174:
+// rs1_val==6 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x6, 0x2, x3, 656, x1)
+
+inst_175:
+// rs1_val==6 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x6, 0x2d, x3, 660, x1)
+
+inst_176:
+// rs1_val==6 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x6, -0x2d, x3, 664, x1)
+
+inst_177:
+// rs1_val==6 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x666, 0x6, 0x666, x3, 668, x1)
+
+inst_178:
+// rs1_val==6 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x337, 0x6, 0x333, x3, 672, x1)
+
+inst_179:
+// rs1_val==6 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x6, 0x5, x3, 676, x1)
+
+inst_180:
+// rs1_val==6 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaae, 0x6, -0x556, x3, 680, x1)
+
+inst_181:
+// rs1_val==6 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x6, 0x555, x3, 684, x1)
+
+inst_182:
+// rs1_val==6 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x6, 0x3, x3, 688, x1)
+
+inst_183:
+// rs1_val==-1431655765 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x2e, x3, 692, x1)
+
+inst_184:
+// rs1_val==-1431655765 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0x55555555, -0x2c, x3, 696, x1)
+
+inst_185:
+// rs1_val==-1431655765 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeef, -0x55555555, 0x667, x3, 700, x1)
+
+inst_186:
+// rs1_val==-1431655765 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabbf, -0x55555555, 0x334, x3, 704, x1)
+
+inst_187:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x6, x3, 708, x1)
+
+inst_188:
+// rs1_val==-1431655765 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, -0x55555555, -0x555, x3, 712, x1)
+
+inst_189:
+// rs1_val==-1431655765 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xaaaaafff, -0x55555555, 0x556, x3, 716, x1)
+
+inst_190:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x4, x3, 720, x1)
+
+inst_191:
+// rs1_val==-1431655765 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x2c, x3, 724, x1)
+
+inst_192:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaab, -0x55555555, 0x0, x3, 728, x1)
+
+inst_193:
+// rs1_val==-1431655765 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeef, -0x55555555, 0x665, x3, 732, x1)
+
+inst_194:
+// rs1_val==-1431655765 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabbb, -0x55555555, 0x332, x3, 736, x1)
+
+inst_195:
+// rs1_val==-1431655765 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xaaaaafff, -0x55555555, 0x554, x3, 740, x1)
+
+inst_196:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaab, -0x55555555, 0x2, x3, 744, x1)
+
+inst_197:
+// rs1_val==-1431655765 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x2d, x3, 748, x1)
+
+inst_198:
+// rs1_val==-1431655765 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffffb, -0x55555555, -0x2d, x3, 752, x1)
+
+inst_199:
+// rs1_val==-1431655765 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeef, -0x55555555, 0x666, x3, 756, x1)
+
+inst_200:
+// rs1_val==-1431655765 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabbb, -0x55555555, 0x333, x3, 760, x1)
+
+inst_201:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x5, x3, 764, x1)
+
+inst_202:
+// rs1_val==-1431655765 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, -0x55555555, -0x556, x3, 768, x1)
+
+inst_203:
+// rs1_val==-1431655765 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xaaaaafff, -0x55555555, 0x555, x3, 772, x1)
+
+inst_204:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaab, -0x55555555, 0x3, x3, 776, x1)
+
+inst_205:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x5555557e, 0x55555556, 0x2e, x3, 780, x1)
+
+inst_206:
+// rs1_val==1431655766 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd6, 0x55555556, -0x2c, x3, 784, x1)
+
+inst_207:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555556, 0x667, x3, 788, x1)
+
+inst_208:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x55555776, 0x55555556, 0x334, x3, 792, x1)
+
+inst_209:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x6, x3, 796, x1)
+
+inst_210:
+// rs1_val==1431655766 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x55555556, -0x555, x3, 800, x1)
+
+inst_211:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x556, x3, 804, x1)
+
+inst_212:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x4, x3, 808, x1)
+
+inst_213:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x5555557e, 0x55555556, 0x2c, x3, 812, x1)
+
+inst_214:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x0, x3, 816, x1)
+
+inst_215:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555556, 0x665, x3, 820, x1)
+
+inst_216:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x55555776, 0x55555556, 0x332, x3, 824, x1)
+
+inst_217:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x554, x3, 828, x1)
+
+inst_218:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555556, 0x2, x3, 832, x1)
+
+inst_219:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x5555557f, 0x55555556, 0x2d, x3, 836, x1)
+
+inst_220:
+// rs1_val==1431655766 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x55555556, -0x2d, x3, 840, x1)
+
+inst_221:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x55555776, 0x55555556, 0x666, x3, 844, x1)
+
+inst_222:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555556, 0x333, x3, 848, x1)
+
+inst_223:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555556, 0x5, x3, 852, x1)
+
+inst_224:
+// rs1_val==1431655766 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffffe, 0x55555556, -0x556, x3, 856, x1)
+
+inst_225:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555556, 0x555, x3, 860, x1)
+
+inst_226:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555556, 0x3, x3, 864, x1)
+
+inst_227:
+// rs1_val==4 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x4, 0x2e, x3, 868, x1)
+
+inst_228:
+// rs1_val==4 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0x4, -0x2c, x3, 872, x1)
+
+inst_229:
+// rs1_val==4 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x4, 0x667, x3, 876, x1)
+
+inst_230:
+// rs1_val==4 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x334, 0x4, 0x334, x3, 880, x1)
+
+inst_231:
+// rs1_val==4 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x4, 0x6, x3, 884, x1)
+
+inst_232:
+// rs1_val==4 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaf, 0x4, -0x555, x3, 888, x1)
+
+inst_233:
+// rs1_val==4 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x4, 0x556, x3, 892, x1)
+
+inst_234:
+// rs1_val==4 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x4, 0x4, 0x4, x3, 896, x1)
+
+inst_235:
+// rs1_val==4 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2c, 0x4, 0x2c, x3, 900, x1)
+
+inst_236:
+// rs1_val==4 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x4, 0x4, 0x0, x3, 904, x1)
+
+inst_237:
+// rs1_val==4 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x665, 0x4, 0x665, x3, 908, x1)
+
+inst_238:
+// rs1_val==4 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x336, 0x4, 0x332, x3, 912, x1)
+
+inst_239:
+// rs1_val==4 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x554, 0x4, 0x554, x3, 916, x1)
+
+inst_240:
+// rs1_val==4 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x4, 0x2, x3, 920, x1)
+
+inst_241:
+// rs1_val==4 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2d, 0x4, 0x2d, x3, 924, x1)
+
+inst_242:
+// rs1_val==4 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x4, -0x2d, x3, 928, x1)
+
+inst_243:
+// rs1_val==4 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x666, 0x4, 0x666, x3, 932, x1)
+
+inst_244:
+// rs1_val==4 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x337, 0x4, 0x333, x3, 936, x1)
+
+inst_245:
+// rs1_val==4 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x5, 0x4, 0x5, x3, 940, x1)
+
+inst_246:
+// rs1_val==4 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaae, 0x4, -0x556, x3, 944, x1)
+
+inst_247:
+// rs1_val==4 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x555, 0x4, 0x555, x3, 948, x1)
+
+inst_248:
+// rs1_val==4 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x4, 0x3, x3, 952, x1)
+
+inst_249:
+// rs1_val==46339 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xb52f, 0xb503, 0x2e, x3, 956, x1)
+
+inst_250:
+// rs1_val==46339 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0xb503, -0x2c, x3, 960, x1)
+
+inst_251:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb503, 0x667, x3, 964, x1)
+
+inst_252:
+// rs1_val==46339 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xb737, 0xb503, 0x334, x3, 968, x1)
+
+inst_253:
+// rs1_val==46339 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb503, 0x6, x3, 972, x1)
+
+inst_254:
+// rs1_val==46339 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffab, 0xb503, -0x555, x3, 976, x1)
+
+inst_255:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xb557, 0xb503, 0x556, x3, 980, x1)
+
+inst_256:
+// rs1_val==46339 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb503, 0x4, x3, 984, x1)
+
+inst_257:
+// rs1_val==46339 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xb52f, 0xb503, 0x2c, x3, 988, x1)
+
+inst_258:
+// rs1_val==46339 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xb503, 0xb503, 0x0, x3, 992, x1)
+
+inst_259:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb503, 0x665, x3, 996, x1)
+
+inst_260:
+// rs1_val==46339 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xb733, 0xb503, 0x332, x3, 1000, x1)
+
+inst_261:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xb557, 0xb503, 0x554, x3, 1004, x1)
+
+inst_262:
+// rs1_val==46339 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xb503, 0xb503, 0x2, x3, 1008, x1)
+
+inst_263:
+// rs1_val==46339 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xb52f, 0xb503, 0x2d, x3, 1012, x1)
+
+inst_264:
+// rs1_val==46339 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd3, 0xb503, -0x2d, x3, 1016, x1)
+
+inst_265:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb503, 0x666, x3, 1020, x1)
+
+inst_266:
+// rs1_val==46339 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xb733, 0xb503, 0x333, x3, 1024, x1)
+
+inst_267:
+// rs1_val==46339 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb503, 0x5, x3, 1028, x1)
+
+inst_268:
+// rs1_val==46339 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xffffffab, 0xb503, -0x556, x3, 1032, x1)
+
+inst_269:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xb557, 0xb503, 0x555, x3, 1036, x1)
+
+inst_270:
+// rs1_val==46339 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xb503, 0xb503, 0x3, x3, 1040, x1)
+
+inst_271:
+// rs1_val==0 and imm_val==46, rs1_val == 0
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x0, 0x2e, x3, 1044, x1)
+
+inst_272:
+// rs1_val==0 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0x0, -0x2c, x3, 1048, x1)
+
+inst_273:
+// rs1_val==0 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x0, 0x667, x3, 1052, x1)
+
+inst_274:
+// rs1_val==0 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x334, 0x0, 0x334, x3, 1056, x1)
+
+inst_275:
+// rs1_val==0 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x0, 0x6, x3, 1060, x1)
+
+inst_276:
+// rs1_val==0 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, 0x0, -0x555, x3, 1064, x1)
+
+inst_277:
+// rs1_val==0 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x0, 0x556, x3, 1068, x1)
+
+inst_278:
+// rs1_val==0 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x4, 0x0, 0x4, x3, 1072, x1)
+
+inst_279:
+// rs1_val==0 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2c, 0x0, 0x2c, x3, 1076, x1)
+
+inst_280:
+// rs1_val==0 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x0, 0x0, 0x0, x3, 1080, x1)
+
+inst_281:
+// rs1_val==0 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x665, 0x0, 0x665, x3, 1084, x1)
+
+inst_282:
+// rs1_val==0 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x332, 0x0, 0x332, x3, 1088, x1)
+
+inst_283:
+// rs1_val==0 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x554, 0x0, 0x554, x3, 1092, x1)
+
+inst_284:
+// rs1_val==0 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x2, 0x0, 0x2, x3, 1096, x1)
+
+inst_285:
+// rs1_val==0 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2d, 0x0, 0x2d, x3, 1100, x1)
+
+inst_286:
+// rs1_val==0 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd3, 0x0, -0x2d, x3, 1104, x1)
+
+inst_287:
+// rs1_val==0 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x666, 0x0, 0x666, x3, 1108, x1)
+
+inst_288:
+// rs1_val==0 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x333, 0x0, 0x333, x3, 1112, x1)
+
+inst_289:
+// rs1_val==0 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x5, 0x0, 0x5, x3, 1116, x1)
+
+inst_290:
+// rs1_val==0 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaa, 0x0, -0x556, x3, 1120, x1)
+
+inst_291:
+// rs1_val==0 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x555, 0x0, 0x555, x3, 1124, x1)
+
+inst_292:
+// rs1_val==0 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x3, 0x0, 0x3, x3, 1128, x1)
+
+inst_293:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x6666666f, 0x66666665, 0x2e, x3, 1132, x1)
+
+inst_294:
+// rs1_val==1717986917 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff5, 0x66666665, -0x2c, x3, 1136, x1)
+
+inst_295:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666665, 0x667, x3, 1140, x1)
+
+inst_296:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x66666775, 0x66666665, 0x334, x3, 1144, x1)
+
+inst_297:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666665, 0x6, x3, 1148, x1)
+
+inst_298:
+// rs1_val==1717986917 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffeef, 0x66666665, -0x555, x3, 1152, x1)
+
+inst_299:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666665, 0x556, x3, 1156, x1)
+
+inst_300:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x66666665, 0x66666665, 0x4, x3, 1160, x1)
+
+inst_301:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x6666666d, 0x66666665, 0x2c, x3, 1164, x1)
+
+inst_302:
+// rs1_val==-1431655766 and imm_val==-1365, rs1_val == -1431655766
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, -0x55555556, -0x555, x3, 1168, x1)
+
+inst_303:
+// rs1_val==-1431655766 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaffe, -0x55555556, 0x556, x3, 1172, x1)
+
+inst_304:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaae, -0x55555556, 0x4, x3, 1176, x1)
+
+inst_305:
+// rs1_val==-1431655766 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaae, -0x55555556, 0x2c, x3, 1180, x1)
+
+inst_306:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaa, -0x55555556, 0x0, x3, 1184, x1)
+
+inst_307:
+// rs1_val==-1431655766 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeef, -0x55555556, 0x665, x3, 1188, x1)
+
+inst_308:
+// rs1_val==-1431655766 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabba, -0x55555556, 0x332, x3, 1192, x1)
+
+inst_309:
+// rs1_val==-1431655766 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaffe, -0x55555556, 0x554, x3, 1196, x1)
+
+inst_310:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaa, -0x55555556, 0x2, x3, 1200, x1)
+
+inst_311:
+// rs1_val==-1431655766 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555556, 0x2d, x3, 1204, x1)
+
+inst_312:
+// rs1_val==-1431655766 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffffb, -0x55555556, -0x2d, x3, 1208, x1)
+
+inst_313:
+// rs1_val==-1431655766 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeee, -0x55555556, 0x666, x3, 1212, x1)
+
+inst_314:
+// rs1_val==-1431655766 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabbb, -0x55555556, 0x333, x3, 1216, x1)
+
+inst_315:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaaf, -0x55555556, 0x5, x3, 1220, x1)
+
+inst_316:
+// rs1_val==-1431655766 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaa, -0x55555556, -0x556, x3, 1224, x1)
+
+inst_317:
+// rs1_val==-1431655766 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xaaaaafff, -0x55555556, 0x555, x3, 1228, x1)
+
+inst_318:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaab, -0x55555556, 0x3, x3, 1232, x1)
+
+inst_319:
+// rs1_val==1431655765 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x5555557f, 0x55555555, 0x2e, x3, 1236, x1)
+
+inst_320:
+// rs1_val==1431655765 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd5, 0x55555555, -0x2c, x3, 1240, x1)
+
+inst_321:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555555, 0x667, x3, 1244, x1)
+
+inst_322:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x55555775, 0x55555555, 0x334, x3, 1248, x1)
+
+inst_323:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555555, 0x6, x3, 1252, x1)
+
+inst_324:
+// rs1_val==1431655765 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x55555555, -0x555, x3, 1256, x1)
+
+inst_325:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555555, 0x556, x3, 1260, x1)
+
+inst_326:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555555, 0x4, x3, 1264, x1)
+
+inst_327:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x5555557d, 0x55555555, 0x2c, x3, 1268, x1)
+
+inst_328:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555555, 0x0, x3, 1272, x1)
+
+inst_329:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x55555775, 0x55555555, 0x665, x3, 1276, x1)
+
+inst_330:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555555, 0x332, x3, 1280, x1)
+
+inst_331:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555555, 0x554, x3, 1284, x1)
+
+inst_332:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555555, 0x2, x3, 1288, x1)
+
+inst_333:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x5555557d, 0x55555555, 0x2d, x3, 1292, x1)
+
+inst_334:
+// rs1_val==1431655765 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x55555555, -0x2d, x3, 1296, x1)
+
+inst_335:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555555, 0x666, x3, 1300, x1)
+
+inst_336:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555555, 0x333, x3, 1304, x1)
+
+inst_337:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555555, 0x5, x3, 1308, x1)
+
+inst_338:
+// rs1_val==1431655765 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x55555555, -0x556, x3, 1312, x1)
+
+inst_339:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555555, 0x555, x3, 1316, x1)
+
+inst_340:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555555, 0x3, x3, 1320, x1)
+
+inst_341:
+// rs1_val==3 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x3, 0x2e, x3, 1324, x1)
+
+inst_342:
+// rs1_val==3 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x3, -0x2c, x3, 1328, x1)
+
+inst_343:
+// rs1_val==3 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x3, 0x667, x3, 1332, x1)
+
+inst_344:
+// rs1_val==3 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x337, 0x3, 0x334, x3, 1336, x1)
+
+inst_345:
+// rs1_val==3 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x3, 0x6, x3, 1340, x1)
+
+inst_346:
+// rs1_val==3 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, 0x3, -0x555, x3, 1344, x1)
+
+inst_347:
+// rs1_val==3 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x3, 0x556, x3, 1348, x1)
+
+inst_348:
+// rs1_val==3 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x3, 0x4, x3, 1352, x1)
+
+inst_349:
+// rs1_val==3 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x3, 0x2c, x3, 1356, x1)
+
+inst_350:
+// rs1_val==3 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x3, 0x3, 0x0, x3, 1360, x1)
+
+inst_351:
+// rs1_val==3 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x3, 0x665, x3, 1364, x1)
+
+inst_352:
+// rs1_val==3 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x333, 0x3, 0x332, x3, 1368, x1)
+
+inst_353:
+// rs1_val==3 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x3, 0x554, x3, 1372, x1)
+
+inst_354:
+// rs1_val==3 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x3, 0x3, 0x2, x3, 1376, x1)
+
+inst_355:
+// rs1_val==3 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x3, 0x2d, x3, 1380, x1)
+
+inst_356:
+// rs1_val==3 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd3, 0x3, -0x2d, x3, 1384, x1)
+
+inst_357:
+// rs1_val==3 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x3, 0x666, x3, 1388, x1)
+
+inst_358:
+// rs1_val==3 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x333, 0x3, 0x333, x3, 1392, x1)
+
+inst_359:
+// rs1_val==3 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x3, 0x5, x3, 1396, x1)
+
+inst_360:
+// rs1_val==3 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, 0x3, -0x556, x3, 1400, x1)
+
+inst_361:
+// rs1_val==3 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x3, 0x555, x3, 1404, x1)
+
+inst_362:
+// rs1_val==3 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x3, 0x3, 0x3, x3, 1408, x1)
+
+inst_363:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x66666665, 0x66666665, 0x0, x3, 1412, x1)
+
+inst_364:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x66666665, 0x66666665, 0x665, x3, 1416, x1)
+
+inst_365:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666665, 0x332, x3, 1420, x1)
+
+inst_366:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x66666775, 0x66666665, 0x554, x3, 1424, x1)
+
+inst_367:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666665, 0x2, x3, 1428, x1)
+
+inst_368:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x6666666d, 0x66666665, 0x2d, x3, 1432, x1)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x66666665, -0x2d, x3, 1436, x1)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666665, 0x666, x3, 1440, x1)
+
+inst_371:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666665, 0x333, x3, 1444, x1)
+
+inst_372:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x66666665, 0x66666665, 0x5, x3, 1448, x1)
+
+inst_373:
+// rs1_val==1717986917 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffeef, 0x66666665, -0x556, x3, 1452, x1)
+
+inst_374:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x66666775, 0x66666665, 0x555, x3, 1456, x1)
+
+inst_375:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666665, 0x3, x3, 1460, x1)
+
+inst_376:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x3333333e, 0x33333332, 0x2e, x3, 1464, x1)
+
+inst_377:
+// rs1_val==858993458 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff6, 0x33333332, -0x2c, x3, 1468, x1)
+
+inst_378:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333332, 0x667, x3, 1472, x1)
+
+inst_379:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333332, 0x334, x3, 1476, x1)
+
+inst_380:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333332, 0x6, x3, 1480, x1)
+
+inst_381:
+// rs1_val==858993458 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffbbb, 0x33333332, -0x555, x3, 1484, x1)
+
+inst_382:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x33333776, 0x33333332, 0x556, x3, 1488, x1)
+
+inst_383:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x33333336, 0x33333332, 0x4, x3, 1492, x1)
+
+inst_384:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x3333333e, 0x33333332, 0x2c, x3, 1496, x1)
+
+inst_385:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x33333332, 0x33333332, 0x0, x3, 1500, x1)
+
+inst_386:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333332, 0x665, x3, 1504, x1)
+
+inst_387:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x33333332, 0x33333332, 0x332, x3, 1508, x1)
+
+inst_388:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x33333776, 0x33333332, 0x554, x3, 1512, x1)
+
+inst_389:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x33333332, 0x33333332, 0x2, x3, 1516, x1)
+
+inst_390:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x3333333f, 0x33333332, 0x2d, x3, 1520, x1)
+
+inst_391:
+// rs1_val==858993458 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff3, 0x33333332, -0x2d, x3, 1524, x1)
+
+inst_392:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x33333776, 0x33333332, 0x666, x3, 1528, x1)
+
+inst_393:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333332, 0x333, x3, 1532, x1)
+
+inst_394:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333332, 0x5, x3, 1536, x1)
+
+inst_395:
+// rs1_val==858993458 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffbba, 0x33333332, -0x556, x3, 1540, x1)
+
+inst_396:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333332, 0x555, x3, 1544, x1)
+
+inst_397:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333332, 0x3, x3, 1548, x1)
+
+inst_398:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x5555557e, 0x55555554, 0x2e, x3, 1552, x1)
+
+inst_399:
+// rs1_val==1431655764 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0x55555554, -0x2c, x3, 1556, x1)
+
+inst_400:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555554, 0x667, x3, 1560, x1)
+
+inst_401:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x55555774, 0x55555554, 0x334, x3, 1564, x1)
+
+inst_402:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555554, 0x6, x3, 1568, x1)
+
+inst_403:
+// rs1_val==1431655764 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, 0x55555554, -0x555, x3, 1572, x1)
+
+inst_404:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555554, 0x556, x3, 1576, x1)
+
+inst_405:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x55555554, 0x55555554, 0x4, x3, 1580, x1)
+
+inst_406:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x5555557c, 0x55555554, 0x2c, x3, 1584, x1)
+
+inst_407:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x55555554, 0x55555554, 0x0, x3, 1588, x1)
+
+inst_408:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x55555775, 0x55555554, 0x665, x3, 1592, x1)
+
+inst_409:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x55555776, 0x55555554, 0x332, x3, 1596, x1)
+
+inst_410:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x55555554, 0x55555554, 0x554, x3, 1600, x1)
+
+inst_411:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x55555556, 0x55555554, 0x2, x3, 1604, x1)
+
+inst_412:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x5555557d, 0x55555554, 0x2d, x3, 1608, x1)
+
+inst_413:
+// rs1_val==1431655764 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x55555554, -0x2d, x3, 1612, x1)
+
+inst_414:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x55555776, 0x55555554, 0x666, x3, 1616, x1)
+
+inst_415:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x55555777, 0x55555554, 0x333, x3, 1620, x1)
+
+inst_416:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555554, 0x5, x3, 1624, x1)
+
+inst_417:
+// rs1_val==1431655764 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffffe, 0x55555554, -0x556, x3, 1628, x1)
+
+inst_418:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x55555555, 0x55555554, 0x555, x3, 1632, x1)
+
+inst_419:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x55555557, 0x55555554, 0x3, x3, 1636, x1)
+
+inst_420:
+// rs1_val==2 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x2, 0x2e, x3, 1640, x1)
+
+inst_421:
+// rs1_val==2 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd6, 0x2, -0x2c, x3, 1644, x1)
+
+inst_422:
+// rs1_val==2 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x2, 0x667, x3, 1648, x1)
+
+inst_423:
+// rs1_val==2 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x336, 0x2, 0x334, x3, 1652, x1)
+
+inst_424:
+// rs1_val==2 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x2, 0x6, x3, 1656, x1)
+
+inst_425:
+// rs1_val==2 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaab, 0x2, -0x555, x3, 1660, x1)
+
+inst_426:
+// rs1_val==2 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x2, 0x556, x3, 1664, x1)
+
+inst_427:
+// rs1_val==2 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x6, 0x2, 0x4, x3, 1668, x1)
+
+inst_428:
+// rs1_val==2 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2e, 0x2, 0x2c, x3, 1672, x1)
+
+inst_429:
+// rs1_val==2 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x2, 0x2, 0x0, x3, 1676, x1)
+
+inst_430:
+// rs1_val==2 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x2, 0x665, x3, 1680, x1)
+
+inst_431:
+// rs1_val==2 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x332, 0x2, 0x332, x3, 1684, x1)
+
+inst_432:
+// rs1_val==2 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x556, 0x2, 0x554, x3, 1688, x1)
+
+inst_433:
+// rs1_val==2 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x2, 0x2d, x3, 1692, x1)
+
+inst_434:
+// rs1_val==2 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd3, 0x2, -0x2d, x3, 1696, x1)
+
+inst_435:
+// rs1_val==2 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x666, 0x2, 0x666, x3, 1700, x1)
+
+inst_436:
+// rs1_val==2 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x333, 0x2, 0x333, x3, 1704, x1)
+
+inst_437:
+// rs1_val==2 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x2, 0x5, x3, 1708, x1)
+
+inst_438:
+// rs1_val==2 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaa, 0x2, -0x556, x3, 1712, x1)
+
+inst_439:
+// rs1_val==2 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x2, 0x555, x3, 1716, x1)
+
+inst_440:
+// rs1_val==2 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x3, 0x2, 0x3, x3, 1720, x1)
+
+inst_441:
+// rs1_val==46340 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xb52e, 0xb504, 0x2e, x3, 1724, x1)
+
+inst_442:
+// rs1_val==46340 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd4, 0xb504, -0x2c, x3, 1728, x1)
+
+inst_443:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xb767, 0xb504, 0x667, x3, 1732, x1)
+
+inst_444:
+// rs1_val==46340 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xb734, 0xb504, 0x334, x3, 1736, x1)
+
+inst_445:
+// rs1_val==46340 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xb506, 0xb504, 0x6, x3, 1740, x1)
+
+inst_446:
+// rs1_val==46340 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xffffffaf, 0xb504, -0x555, x3, 1744, x1)
+
+inst_447:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xb556, 0xb504, 0x556, x3, 1748, x1)
+
+inst_448:
+// rs1_val==46340 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xb504, 0xb504, 0x4, x3, 1752, x1)
+
+inst_449:
+// rs1_val==46340 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xb52c, 0xb504, 0x2c, x3, 1756, x1)
+
+inst_450:
+// rs1_val==46340 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xb504, 0xb504, 0x0, x3, 1760, x1)
+
+inst_451:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xb765, 0xb504, 0x665, x3, 1764, x1)
+
+inst_452:
+// rs1_val==46340 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xb736, 0xb504, 0x332, x3, 1768, x1)
+
+inst_453:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xb554, 0xb504, 0x554, x3, 1772, x1)
+
+inst_454:
+// rs1_val==46340 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xb506, 0xb504, 0x2, x3, 1776, x1)
+
+inst_455:
+// rs1_val==46340 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xb52d, 0xb504, 0x2d, x3, 1780, x1)
+
+inst_456:
+// rs1_val==46340 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0xb504, -0x2d, x3, 1784, x1)
+
+inst_457:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xb766, 0xb504, 0x666, x3, 1788, x1)
+
+inst_458:
+// rs1_val==46340 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xb737, 0xb504, 0x333, x3, 1792, x1)
+
+inst_459:
+// rs1_val==46340 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xb505, 0xb504, 0x5, x3, 1796, x1)
+
+inst_460:
+// rs1_val==46340 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xffffffae, 0xb504, -0x556, x3, 1800, x1)
+
+inst_461:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xb555, 0xb504, 0x555, x3, 1804, x1)
+
+inst_462:
+// rs1_val==46340 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xb507, 0xb504, 0x3, x3, 1808, x1)
+
+inst_463:
+// rs1_val==-46340 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xffff4afe, -0xb504, 0x2e, x3, 1812, x1)
+
+inst_464:
+// rs1_val==-46340 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffffc, -0xb504, -0x2c, x3, 1816, x1)
+
+inst_465:
+// rs1_val==-46340 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xffff4eff, -0xb504, 0x667, x3, 1820, x1)
+
+inst_466:
+// rs1_val==-46340 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xffff4bfc, -0xb504, 0x334, x3, 1824, x1)
+
+inst_467:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xffff4afe, -0xb504, 0x6, x3, 1828, x1)
+
+inst_468:
+// rs1_val==-46340 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaff, -0xb504, -0x555, x3, 1832, x1)
+
+inst_469:
+// rs1_val==-46340 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0xffff4ffe, -0xb504, 0x556, x3, 1836, x1)
+
+inst_470:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0xffff4afc, -0xb504, 0x4, x3, 1840, x1)
+
+inst_471:
+// rs1_val==-46340 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffff4afc, -0xb504, 0x2c, x3, 1844, x1)
+
+inst_472:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0xffff4afc, -0xb504, 0x0, x3, 1848, x1)
+
+inst_473:
+// rs1_val==-46340 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0xffff4efd, -0xb504, 0x665, x3, 1852, x1)
+
+inst_474:
+// rs1_val==-46340 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0xffff4bfe, -0xb504, 0x332, x3, 1856, x1)
+
+inst_475:
+// rs1_val==-46340 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0xffff4ffc, -0xb504, 0x554, x3, 1860, x1)
+
+inst_476:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0xffff4afe, -0xb504, 0x2, x3, 1864, x1)
+
+inst_477:
+// rs1_val==-46340 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb504, 0x2d, x3, 1868, x1)
+
+inst_478:
+// rs1_val==-46340 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffff, -0xb504, -0x2d, x3, 1872, x1)
+
+inst_479:
+// rs1_val==-46340 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0xffff4efe, -0xb504, 0x666, x3, 1876, x1)
+
+inst_480:
+// rs1_val==-46340 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0xffff4bff, -0xb504, 0x333, x3, 1880, x1)
+
+inst_481:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0xffff4afd, -0xb504, 0x5, x3, 1884, x1)
+
+inst_482:
+// rs1_val==-46340 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffafe, -0xb504, -0x556, x3, 1888, x1)
+
+inst_483:
+// rs1_val==-46340 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0xffff4ffd, -0xb504, 0x555, x3, 1892, x1)
+
+inst_484:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0xffff4aff, -0xb504, 0x3, x3, 1896, x1)
+
+inst_485:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x6666666e, 0x66666666, 0x2e, x3, 1900, x1)
+
+inst_486:
+// rs1_val==1717986918 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff6, 0x66666666, -0x2c, x3, 1904, x1)
+
+inst_487:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666666, 0x667, x3, 1908, x1)
+
+inst_488:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x66666776, 0x66666666, 0x334, x3, 1912, x1)
+
+inst_489:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x66666666, 0x66666666, 0x6, x3, 1916, x1)
+
+inst_490:
+// rs1_val==1717986918 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffeef, 0x66666666, -0x555, x3, 1920, x1)
+
+inst_491:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x66666776, 0x66666666, 0x556, x3, 1924, x1)
+
+inst_492:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x66666666, 0x66666666, 0x4, x3, 1928, x1)
+
+inst_493:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x6666666e, 0x66666666, 0x2c, x3, 1932, x1)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x66666666, 0x66666666, 0x0, x3, 1936, x1)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666666, 0x665, x3, 1940, x1)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x66666776, 0x66666666, 0x332, x3, 1944, x1)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x66666776, 0x66666666, 0x554, x3, 1948, x1)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x66666666, 0x66666666, 0x2, x3, 1952, x1)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x6666666f, 0x66666666, 0x2d, x3, 1956, x1)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x66666666, -0x2d, x3, 1960, x1)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x66666666, 0x66666666, 0x666, x3, 1964, x1)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666666, 0x333, x3, 1968, x1)
+
+inst_503:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666666, 0x5, x3, 1972, x1)
+
+inst_504:
+// rs1_val==1717986918 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffeee, 0x66666666, -0x556, x3, 1976, x1)
+
+inst_505:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x66666777, 0x66666666, 0x555, x3, 1980, x1)
+
+inst_506:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x66666667, 0x66666666, 0x3, x3, 1984, x1)
+
+inst_507:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x3333333f, 0x33333333, 0x2e, x3, 1988, x1)
+
+inst_508:
+// rs1_val==858993459 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffff7, 0x33333333, -0x2c, x3, 1992, x1)
+
+inst_509:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x667, x3, 1996, x1)
+
+inst_510:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333333, 0x334, x3, 2000, x1)
+
+inst_511:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333333, 0x6, x3, 2004, x1)
+
+inst_512:
+// rs1_val==858993459 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffbbb, 0x33333333, -0x555, x3, 2008, x1)
+
+inst_513:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x556, x3, 2012, x1)
+
+inst_514:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333333, 0x4, x3, 2016, x1)
+
+inst_515:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x3333333f, 0x33333333, 0x2c, x3, 2020, x1)
+
+inst_516:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x0, x3, 2024, x1)
+
+inst_517:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x665, x3, 2028, x1)
+
+inst_518:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x332, x3, 2032, x1)
+
+inst_519:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x554, x3, 2036, x1)
+
+inst_520:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x2, x3, 2040, x1)
+
+inst_521:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x3333333f, 0x33333333, 0x2d, x3, 2044, x1)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_522:
+// rs1_val==858993459 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xfffffff3, 0x33333333, -0x2d, x3, 0, x1)
+
+inst_523:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x666, x3, 4, x1)
+
+inst_524:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x333, x3, 8, x1)
+
+inst_525:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x33333337, 0x33333333, 0x5, x3, 12, x1)
+
+inst_526:
+// rs1_val==858993459 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffbbb, 0x33333333, -0x556, x3, 16, x1)
+
+inst_527:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x33333777, 0x33333333, 0x555, x3, 20, x1)
+
+inst_528:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x33333333, 0x33333333, 0x3, x3, 24, x1)
+
+inst_529:
+// rs1_val==5 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0x2f, 0x5, 0x2e, x3, 28, x1)
+
+inst_530:
+// rs1_val==5 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xffffffd5, 0x5, -0x2c, x3, 32, x1)
+
+inst_531:
+// rs1_val==5 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x5, 0x667, x3, 36, x1)
+
+inst_532:
+// rs1_val==5 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0x335, 0x5, 0x334, x3, 40, x1)
+
+inst_533:
+// rs1_val==5 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x5, 0x6, x3, 44, x1)
+
+inst_534:
+// rs1_val==5 and imm_val==-1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x555
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaf, 0x5, -0x555, x3, 48, x1)
+
+inst_535:
+// rs1_val==5 and imm_val==1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( ori, x11, x10, 0x557, 0x5, 0x556, x3, 52, x1)
+
+inst_536:
+// rs1_val==5 and imm_val==4, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( ori, x11, x10, 0x5, 0x5, 0x4, x3, 56, x1)
+
+inst_537:
+// rs1_val==5 and imm_val==44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( ori, x11, x10, 0x2d, 0x5, 0x2c, x3, 60, x1)
+
+inst_538:
+// rs1_val==5 and imm_val==0, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( ori, x11, x10, 0x5, 0x5, 0x0, x3, 64, x1)
+
+inst_539:
+// rs1_val==5 and imm_val==1637, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( ori, x11, x10, 0x665, 0x5, 0x665, x3, 68, x1)
+
+inst_540:
+// rs1_val==5 and imm_val==818, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( ori, x11, x10, 0x337, 0x5, 0x332, x3, 72, x1)
+
+inst_541:
+// rs1_val==5 and imm_val==1364, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( ori, x11, x10, 0x555, 0x5, 0x554, x3, 76, x1)
+
+inst_542:
+// rs1_val==5 and imm_val==2, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x5, 0x2, x3, 80, x1)
+
+inst_543:
+// rs1_val==5 and imm_val==45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( ori, x11, x10, 0x2d, 0x5, 0x2d, x3, 84, x1)
+
+inst_544:
+// rs1_val==5 and imm_val==-45, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2d
+TEST_IMM_OP( ori, x11, x10, 0xffffffd7, 0x5, -0x2d, x3, 88, x1)
+
+inst_545:
+// rs1_val==5 and imm_val==1638, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( ori, x11, x10, 0x667, 0x5, 0x666, x3, 92, x1)
+
+inst_546:
+// rs1_val==5 and imm_val==819, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( ori, x11, x10, 0x337, 0x5, 0x333, x3, 96, x1)
+
+inst_547:
+// rs1_val==5 and imm_val==5, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( ori, x11, x10, 0x5, 0x5, 0x5, x3, 100, x1)
+
+inst_548:
+// rs1_val==5 and imm_val==-1366, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x556
+TEST_IMM_OP( ori, x11, x10, 0xfffffaaf, 0x5, -0x556, x3, 104, x1)
+
+inst_549:
+// rs1_val==5 and imm_val==1365, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( ori, x11, x10, 0x555, 0x5, 0x555, x3, 108, x1)
+
+inst_550:
+// rs1_val==5 and imm_val==3, 
+// opcode: ori ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( ori, x11, x10, 0x7, 0x5, 0x3, x3, 112, x1)
+
+inst_551:
+// rs1_val==-1431655766 and imm_val==46, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2e
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaae, -0x55555556, 0x2e, x3, 116, x1)
+
+inst_552:
+// rs1_val==-1431655766 and imm_val==-44, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2c
+TEST_IMM_OP( ori, x11, x10, 0xfffffffe, -0x55555556, -0x2c, x3, 120, x1)
+
+inst_553:
+// rs1_val==-1431655766 and imm_val==1639, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x667
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaeef, -0x55555556, 0x667, x3, 124, x1)
+
+inst_554:
+// rs1_val==-1431655766 and imm_val==820, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x334
+TEST_IMM_OP( ori, x11, x10, 0xaaaaabbe, -0x55555556, 0x334, x3, 128, x1)
+
+inst_555:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: ori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x6
+TEST_IMM_OP( ori, x11, x10, 0xaaaaaaae, -0x55555556, 0x6, x3, 132, x1)
+
+inst_556:
+// rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: ori ; op1:x10; dest:x11; op1val:0x7fffffff;  immval:0x3ff
+TEST_IMM_OP( ori, x11, x10, 0x7fffffff, 0x7fffffff, 0x3ff, x3, 136, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 10*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 35*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S
new file mode 100644
index 000000000..3eaf9072c
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S
@@ -0,0 +1,466 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sb instruction of the RISC-V E extension for the sb-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sb-align)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 != rs2, rs1==x4, rs2==x0, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0
+// opcode: sb; op1:x4; op2:x0; op2val:0x0; immval:0x8; align:0
+TEST_STORE(x3,x5,0,x4,x0,0x0,0x8,0,sb,0)
+
+inst_1:
+// rs1==x8, rs2==x11, rs2_val == 2147483647, imm_val < 0, ea_align == 0 and (imm_val % 4) == 3, rs2_val == (2**(xlen-1)-1)
+// opcode: sb; op1:x8; op2:x11; op2val:0x7fffffff; immval:-0x41; align:0
+TEST_STORE(x3,x5,0,x8,x11,0x7fffffff,-0x41,4,sb,0)
+
+inst_2:
+// rs1==x1, rs2==x15, rs2_val == -1073741825, 
+// opcode: sb; op1:x1; op2:x15; op2val:-0x40000001; immval:-0x11; align:0
+TEST_STORE(x3,x5,0,x1,x15,-0x40000001,-0x11,8,sb,0)
+
+inst_3:
+// rs1==x14, rs2==x2, rs2_val == -536870913, 
+// opcode: sb; op1:x14; op2:x2; op2val:-0x20000001; immval:-0x101; align:0
+TEST_STORE(x3,x5,0,x14,x2,-0x20000001,-0x101,12,sb,0)
+
+inst_4:
+// rs1==x15, rs2==x8, rs2_val == -268435457, ea_align == 0 and (imm_val % 4) == 1
+// opcode: sb; op1:x15; op2:x8; op2val:-0x10000001; immval:-0x3; align:0
+TEST_STORE(x3,x5,0,x15,x8,-0x10000001,-0x3,16,sb,0)
+
+inst_5:
+// rs1==x6, rs2==x7, rs2_val == -134217729, 
+// opcode: sb; op1:x6; op2:x7; op2val:-0x8000001; immval:-0x8; align:0
+TEST_STORE(x3,x5,0,x6,x7,-0x8000001,-0x8,20,sb,0)
+
+inst_6:
+// rs1==x2, rs2==x10, rs2_val == -67108865, 
+// opcode: sb; op1:x2; op2:x10; op2val:-0x4000001; immval:0x7ff; align:0
+TEST_STORE(x3,x5,0,x2,x10,-0x4000001,0x7ff,24,sb,0)
+
+inst_7:
+// rs1==x13, rs2==x6, rs2_val == -33554433, 
+// opcode: sb; op1:x13; op2:x6; op2val:-0x2000001; immval:0x555; align:0
+TEST_STORE(x3,x5,0,x13,x6,-0x2000001,0x555,28,sb,0)
+
+inst_8:
+// rs1==x7, rs2==x4, rs2_val == -16777217, 
+// opcode: sb; op1:x7; op2:x4; op2val:-0x1000001; immval:0x100; align:0
+TEST_STORE(x3,x2,0,x7,x4,-0x1000001,0x100,32,sb,0)
+
+inst_9:
+// rs1==x9, rs2==x1, rs2_val == -8388609, 
+// opcode: sb; op1:x9; op2:x1; op2val:-0x800001; immval:-0x3; align:0
+TEST_STORE(x3,x2,0,x9,x1,-0x800001,-0x3,36,sb,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_10:
+// rs1==x10, rs2==x12, rs2_val == -4194305, 
+// opcode: sb; op1:x10; op2:x12; op2val:-0x400001; immval:0x1; align:0
+TEST_STORE(x1,x2,0,x10,x12,-0x400001,0x1,0,sb,0)
+
+inst_11:
+// rs1==x3, rs2==x13, rs2_val == -2097153, 
+// opcode: sb; op1:x3; op2:x13; op2val:-0x200001; immval:0x80; align:0
+TEST_STORE(x1,x2,0,x3,x13,-0x200001,0x80,4,sb,0)
+
+inst_12:
+// rs1==x11, rs2==x5, rs2_val == -1048577, 
+// opcode: sb; op1:x11; op2:x5; op2val:-0x100001; immval:-0x401; align:0
+TEST_STORE(x1,x2,0,x11,x5,-0x100001,-0x401,8,sb,0)
+
+inst_13:
+// rs1==x5, rs2==x9, rs2_val == -524289, 
+// opcode: sb; op1:x5; op2:x9; op2val:-0x80001; immval:-0x800; align:0
+TEST_STORE(x1,x2,0,x5,x9,-0x80001,-0x800,12,sb,0)
+
+inst_14:
+// rs1==x12, rs2==x3, rs2_val == -262145, 
+// opcode: sb; op1:x12; op2:x3; op2val:-0x40001; immval:-0x9; align:0
+TEST_STORE(x1,x2,0,x12,x3,-0x40001,-0x9,16,sb,0)
+
+inst_15:
+// rs2==x14, rs2_val == -131073, 
+// opcode: sb; op1:x4; op2:x14; op2val:-0x20001; immval:0x8; align:0
+TEST_STORE(x1,x2,0,x4,x14,-0x20001,0x8,20,sb,0)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x10001; immval:-0x800; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x10001,-0x800,24,sb,0)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x8001; immval:0x9; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x8001,0x9,28,sb,0)
+
+inst_18:
+// rs2_val == -16385, ea_align == 0 and (imm_val % 4) == 2
+// opcode: sb; op1:x10; op2:x11; op2val:-0x4001; immval:-0x556; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x4001,-0x556,32,sb,0)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x2001; immval:0x7ff; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x2001,0x7ff,36,sb,0)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x1001; immval:0x7; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x1001,0x7,40,sb,0)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x801; immval:-0x800; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x801,-0x800,44,sb,0)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x401; immval:0x9; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x401,0x9,48,sb,0)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x201; immval:-0x3; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x201,-0x3,52,sb,0)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x101; immval:-0x41; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x101,-0x41,56,sb,0)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x81; immval:0x2; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x81,0x2,60,sb,0)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x41; immval:-0xa; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x41,-0xa,64,sb,0)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x21; immval:-0x41; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x21,-0x41,68,sb,0)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x11; immval:0x3; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x11,0x3,72,sb,0)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x9; immval:0x10; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x9,0x10,76,sb,0)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x5; immval:-0x7; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x5,-0x7,80,sb,0)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x3; immval:0x555; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x3,0x555,84,sb,0)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x2; immval:-0xa; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x2,-0xa,88,sb,0)
+
+inst_33:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: sb; op1:x10; op2:x11; op2val:-0x80000000; immval:-0x8; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x80000000,-0x8,92,sb,0)
+
+inst_34:
+// rs2_val == 1073741824, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x40000000; immval:-0x5; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x40000000,-0x5,96,sb,0)
+
+inst_35:
+// rs2_val == 536870912, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x20000000; immval:-0x41; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x20000000,-0x41,100,sb,0)
+
+inst_36:
+// rs2_val == 268435456, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x10000000; immval:-0xa; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x10000000,-0xa,104,sb,0)
+
+inst_37:
+// rs2_val == 134217728, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x8000000; immval:0x555; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x8000000,0x555,108,sb,0)
+
+inst_38:
+// rs2_val == 67108864, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x4000000; immval:-0x81; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x4000000,-0x81,112,sb,0)
+
+inst_39:
+// rs2_val == 33554432, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x2000000; immval:-0x400; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x2000000,-0x400,116,sb,0)
+
+inst_40:
+// rs2_val == 16777216, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x1000000; immval:-0x41; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x1000000,-0x41,120,sb,0)
+
+inst_41:
+// rs2_val == 8388608, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x800000; immval:-0x5; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x800000,-0x5,124,sb,0)
+
+inst_42:
+// rs2_val == 4194304, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x400000; immval:-0x9; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x400000,-0x9,128,sb,0)
+
+inst_43:
+// rs2_val == 2097152, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x200000; immval:0x7ff; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x200000,0x7ff,132,sb,0)
+
+inst_44:
+// rs2_val == 1048576, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x100000; immval:-0x41; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x100000,-0x41,136,sb,0)
+
+inst_45:
+// rs2_val == 524288, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x80000; immval:-0x3; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x80000,-0x3,140,sb,0)
+
+inst_46:
+// rs2_val == 262144, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x40000; immval:0x6; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x40000,0x6,144,sb,0)
+
+inst_47:
+// rs2_val == 131072, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x20000; immval:0x80; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x20000,0x80,148,sb,0)
+
+inst_48:
+// rs2_val == 65536, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x10000; immval:0x555; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x10000,0x555,152,sb,0)
+
+inst_49:
+// rs2_val == 32768, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x8000; immval:0x5; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x8000,0x5,156,sb,0)
+
+inst_50:
+// rs2_val == 1, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x1; immval:0x400; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x1,0x400,160,sb,0)
+
+inst_51:
+// rs2_val == -1431655766, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x6; align:0
+TEST_STORE(x1,x2,0,x10,x11,-0x55555556,-0x6,164,sb,0)
+
+inst_52:
+// rs2_val == 1431655765, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x55555555; immval:0x555; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x55555555,0x555,168,sb,0)
+
+inst_53:
+// ea_align == 1 and (imm_val % 4) == 0, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x5; immval:0x20; align:1
+TEST_STORE(x1,x2,0,x10,x11,-0x5,0x20,172,sb,1)
+
+inst_54:
+// ea_align == 1 and (imm_val % 4) == 1, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x101; immval:0x5; align:1
+TEST_STORE(x1,x2,0,x10,x11,-0x101,0x5,176,sb,1)
+
+inst_55:
+// ea_align == 1 and (imm_val % 4) == 2, rs2_val == 8
+// opcode: sb; op1:x10; op2:x11; op2val:0x8; immval:-0x2; align:1
+TEST_STORE(x1,x2,0,x10,x11,0x8,-0x2,180,sb,1)
+
+inst_56:
+// ea_align == 1 and (imm_val % 4) == 3, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x8; immval:-0x201; align:1
+TEST_STORE(x1,x2,0,x10,x11,-0x8,-0x201,184,sb,1)
+
+inst_57:
+// ea_align == 2 and (imm_val % 4) == 0, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x2000000; immval:-0x400; align:2
+TEST_STORE(x1,x2,0,x10,x11,0x2000000,-0x400,188,sb,2)
+
+inst_58:
+// ea_align == 2 and (imm_val % 4) == 1, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x41; immval:0x9; align:2
+TEST_STORE(x1,x2,0,x10,x11,-0x41,0x9,192,sb,2)
+
+inst_59:
+// ea_align == 2 and (imm_val % 4) == 2, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x8; immval:0x2; align:2
+TEST_STORE(x1,x2,0,x10,x11,-0x8,0x2,196,sb,2)
+
+inst_60:
+// ea_align == 2 and (imm_val % 4) == 3, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x9; immval:-0x5; align:2
+TEST_STORE(x1,x2,0,x10,x11,0x9,-0x5,200,sb,2)
+
+inst_61:
+// ea_align == 3 and (imm_val % 4) == 0, rs2_val == 16
+// opcode: sb; op1:x10; op2:x11; op2val:0x10; immval:0x400; align:3
+TEST_STORE(x1,x2,0,x10,x11,0x10,0x400,204,sb,3)
+
+inst_62:
+// ea_align == 3 and (imm_val % 4) == 1, 
+// opcode: sb; op1:x10; op2:x11; op2val:-0x200001; immval:0x555; align:3
+TEST_STORE(x1,x2,0,x10,x11,-0x200001,0x555,208,sb,3)
+
+inst_63:
+// ea_align == 3 and (imm_val % 4) == 2, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x10000000; immval:-0x556; align:3
+TEST_STORE(x1,x2,0,x10,x11,0x10000000,-0x556,212,sb,3)
+
+inst_64:
+// rs2_val == 64, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x40; immval:0x20; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x40,0x20,216,sb,0)
+
+inst_65:
+// ea_align == 3 and (imm_val % 4) == 3, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x8000; immval:0x3ff; align:3
+TEST_STORE(x1,x2,0,x10,x11,0x8000,0x3ff,220,sb,3)
+
+inst_66:
+// rs2_val == 16384, imm_val == 0
+// opcode: sb; op1:x10; op2:x11; op2val:0x4000; immval:0x0; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x4000,0x0,224,sb,0)
+
+inst_67:
+// rs2_val == 8192, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x2000; immval:0x40; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x2000,0x40,228,sb,0)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x1000; immval:0x9; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x1000,0x9,232,sb,0)
+
+inst_69:
+// rs2_val == 2048, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x800; immval:-0x556; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x800,-0x556,236,sb,0)
+
+inst_70:
+// rs2_val == 512, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x200; immval:0x5; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x200,0x5,240,sb,0)
+
+inst_71:
+// rs2_val == 1024, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x400; immval:-0x11; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x400,-0x11,244,sb,0)
+
+inst_72:
+// rs2_val == 0, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x0; immval:-0x11; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x0,-0x11,248,sb,0)
+
+inst_73:
+// rs2_val == 256, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x100; immval:0x80; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x100,0x80,252,sb,0)
+
+inst_74:
+// rs2_val == 128, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x80; immval:0x7; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x80,0x7,256,sb,0)
+
+inst_75:
+// rs2_val == 32, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x20; immval:0x200; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x20,0x200,260,sb,0)
+
+inst_76:
+// rs2_val == 4, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x4; immval:0x3; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x4,0x3,264,sb,0)
+
+inst_77:
+// rs2_val == 2, 
+// opcode: sb; op1:x10; op2:x11; op2val:0x2; immval:0x400; align:0
+TEST_STORE(x1,x2,0,x10,x11,0x2,0x400,268,sb,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 10*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 68*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S
new file mode 100644
index 000000000..86d7c2781
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S
@@ -0,0 +1,436 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sh instruction of the RISC-V E extension for the sh-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sh-align)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs1 != rs2, rs1==x6, rs2==x4, ea_align == 0 and (imm_val % 4) == 0, rs2_val == 1, imm_val > 0
+// opcode: sh; op1:x6; op2:x4; op2val:0x1; immval:0x4; align:0
+TEST_STORE(x8,x12,0,x6,x4,0x1,0x4,0,sh,0)
+
+inst_1:
+// rs1==x10, rs2==x5, rs2_val == 2147483647, imm_val == 0, rs2_val == (2**(xlen-1)-1)
+// opcode: sh; op1:x10; op2:x5; op2val:0x7fffffff; immval:0x0; align:0
+TEST_STORE(x8,x12,0,x10,x5,0x7fffffff,0x0,4,sh,0)
+
+inst_2:
+// rs1==x9, rs2==x10, rs2_val == -1073741825, ea_align == 0 and (imm_val % 4) == 2
+// opcode: sh; op1:x9; op2:x10; op2val:-0x40000001; immval:0x2; align:0
+TEST_STORE(x8,x12,0,x9,x10,-0x40000001,0x2,8,sh,0)
+
+inst_3:
+// rs1==x2, rs2==x11, rs2_val == -536870913, imm_val < 0
+// opcode: sh; op1:x2; op2:x11; op2val:-0x20000001; immval:-0x8; align:0
+TEST_STORE(x8,x12,0,x2,x11,-0x20000001,-0x8,12,sh,0)
+
+inst_4:
+// rs1==x13, rs2==x1, rs2_val == -268435457, 
+// opcode: sh; op1:x13; op2:x1; op2val:-0x10000001; immval:0x8; align:0
+TEST_STORE(x8,x12,0,x13,x1,-0x10000001,0x8,16,sh,0)
+
+inst_5:
+// rs1==x7, rs2==x3, rs2_val == -134217729, 
+// opcode: sh; op1:x7; op2:x3; op2val:-0x8000001; immval:0x80; align:0
+TEST_STORE(x8,x12,0,x7,x3,-0x8000001,0x80,20,sh,0)
+
+inst_6:
+// rs1==x3, rs2==x6, rs2_val == -67108865, 
+// opcode: sh; op1:x3; op2:x6; op2val:-0x4000001; immval:0x6; align:0
+TEST_STORE(x8,x9,0,x3,x6,-0x4000001,0x6,24,sh,0)
+
+inst_7:
+// rs1==x12, rs2==x2, rs2_val == -33554433, ea_align == 0 and (imm_val % 4) == 3
+// opcode: sh; op1:x12; op2:x2; op2val:-0x2000001; immval:0x7; align:0
+TEST_STORE(x8,x9,0,x12,x2,-0x2000001,0x7,28,sh,0)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_8:
+// rs1==x5, rs2==x13, rs2_val == -16777217, 
+// opcode: sh; op1:x5; op2:x13; op2val:-0x1000001; immval:-0x800; align:0
+TEST_STORE(x2,x9,0,x5,x13,-0x1000001,-0x800,0,sh,0)
+
+inst_9:
+// rs1==x1, rs2==x15, rs2_val == -8388609, 
+// opcode: sh; op1:x1; op2:x15; op2val:-0x800001; immval:0x3; align:0
+TEST_STORE(x2,x9,0,x1,x15,-0x800001,0x3,4,sh,0)
+
+inst_10:
+// rs1==x15, rs2==x7, rs2_val == -4194305, 
+// opcode: sh; op1:x15; op2:x7; op2val:-0x400001; immval:0x40; align:0
+TEST_STORE(x2,x9,0,x15,x7,-0x400001,0x40,8,sh,0)
+
+inst_11:
+// rs1==x14, rs2==x12, rs2_val == -2097153, ea_align == 0 and (imm_val % 4) == 1
+// opcode: sh; op1:x14; op2:x12; op2val:-0x200001; immval:0x5; align:0
+TEST_STORE(x2,x9,0,x14,x12,-0x200001,0x5,12,sh,0)
+
+inst_12:
+// rs1==x4, rs2==x14, rs2_val == -1048577, 
+// opcode: sh; op1:x4; op2:x14; op2val:-0x100001; immval:-0x41; align:0
+TEST_STORE(x2,x9,0,x4,x14,-0x100001,-0x41,16,sh,0)
+
+inst_13:
+// rs1==x11, rs2==x0, rs2_val == -524289, 
+// opcode: sh; op1:x11; op2:x0; op2val:0x0; immval:-0x5; align:0
+TEST_STORE(x2,x3,0,x11,x0,0x0,-0x5,20,sh,0)
+
+inst_14:
+// rs1==x8, rs2==x9, rs2_val == -262145, 
+// opcode: sh; op1:x8; op2:x9; op2val:-0x40001; immval:-0x400; align:0
+TEST_STORE(x2,x3,0,x8,x9,-0x40001,-0x400,24,sh,0)
+
+inst_15:
+// rs2==x8, rs2_val == -131073, 
+// opcode: sh; op1:x11; op2:x8; op2val:-0x20001; immval:0x20; align:0
+TEST_STORE(x2,x3,0,x11,x8,-0x20001,0x20,28,sh,0)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x10001; immval:-0x9; align:0
+TEST_STORE(x2,x3,0,x10,x11,-0x10001,-0x9,32,sh,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x8001; immval:-0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x8001,-0x9,0,sh,0)
+
+inst_18:
+// rs2_val == -16385, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x4001; immval:0x0; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x4001,0x0,4,sh,0)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x2001; immval:-0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x2001,-0x2,8,sh,0)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x1001; immval:0x10; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x1001,0x10,12,sh,0)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x801; immval:-0x556; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x801,-0x556,16,sh,0)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x401; immval:-0x8; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x401,-0x8,20,sh,0)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x201; immval:-0x800; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x201,-0x800,24,sh,0)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x101; immval:-0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x101,-0x2,28,sh,0)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x81; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x81,0x40,32,sh,0)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x41; immval:0x100; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x41,0x100,36,sh,0)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x21; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x21,-0x81,40,sh,0)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x11; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x11,-0x401,44,sh,0)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x9; immval:-0x800; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x9,-0x800,48,sh,0)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x5; immval:-0x800; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x5,-0x800,52,sh,0)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x3; immval:0x200; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x3,0x200,56,sh,0)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x2; immval:-0x21; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x2,-0x21,60,sh,0)
+
+inst_33:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: sh; op1:x10; op2:x11; op2val:-0x80000000; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x80000000,0x40,64,sh,0)
+
+inst_34:
+// rs2_val == 1073741824, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x40000000; immval:-0x101; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40000000,-0x101,68,sh,0)
+
+inst_35:
+// rs2_val == 536870912, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x20000000; immval:0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20000000,0x2,72,sh,0)
+
+inst_36:
+// rs2_val == 268435456, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x10000000; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10000000,-0x401,76,sh,0)
+
+inst_37:
+// rs2_val == 134217728, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x8000000; immval:-0xa; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8000000,-0xa,80,sh,0)
+
+inst_38:
+// rs2_val == 67108864, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x4000000; immval:0x200; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x4000000,0x200,84,sh,0)
+
+inst_39:
+// rs2_val == 33554432, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x2000000; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2000000,-0x81,88,sh,0)
+
+inst_40:
+// rs2_val == -1431655766, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x556; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x55555556,-0x556,92,sh,0)
+
+inst_41:
+// rs2_val == 1431655765, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x55555555; immval:-0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x55555555,-0x9,96,sh,0)
+
+inst_42:
+// ea_align == 2 and (imm_val % 4) == 0, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x1000001; immval:-0x400; align:2
+TEST_STORE(x1,x3,0,x10,x11,-0x1000001,-0x400,100,sh,2)
+
+inst_43:
+// ea_align == 2 and (imm_val % 4) == 1, rs2_val == 2048
+// opcode: sh; op1:x10; op2:x11; op2val:0x800; immval:-0x7; align:2
+TEST_STORE(x1,x3,0,x10,x11,0x800,-0x7,104,sh,2)
+
+inst_44:
+// ea_align == 2 and (imm_val % 4) == 2, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x3; immval:-0x556; align:2
+TEST_STORE(x1,x3,0,x10,x11,0x3,-0x556,108,sh,2)
+
+inst_45:
+// ea_align == 2 and (imm_val % 4) == 3, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x6; immval:-0x1; align:2
+TEST_STORE(x1,x3,0,x10,x11,-0x6,-0x1,112,sh,2)
+
+inst_46:
+// rs2_val == 0, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x0; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x0,-0x81,116,sh,0)
+
+inst_47:
+// rs2_val == 16777216, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x1000000; immval:-0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x1000000,-0x9,120,sh,0)
+
+inst_48:
+// rs2_val == 8388608, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x800000; immval:-0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x800000,-0x2,124,sh,0)
+
+inst_49:
+// rs2_val == 4194304, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x400000; immval:-0x11; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x400000,-0x11,128,sh,0)
+
+inst_50:
+// rs2_val == 2097152, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x200000; immval:0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x200000,0x9,132,sh,0)
+
+inst_51:
+// rs2_val == 1048576, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x100000; immval:0x4; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x100000,0x4,136,sh,0)
+
+inst_52:
+// rs2_val == 524288, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x80000; immval:-0x3; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x80000,-0x3,140,sh,0)
+
+inst_53:
+// rs2_val == 262144, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x40000; immval:0x100; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40000,0x100,144,sh,0)
+
+inst_54:
+// rs2_val == 131072, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x20000; immval:-0x201; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20000,-0x201,148,sh,0)
+
+inst_55:
+// rs2_val == 65536, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x10000; immval:-0x6; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10000,-0x6,152,sh,0)
+
+inst_56:
+// rs2_val == 32768, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x8000; immval:0x100; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8000,0x100,156,sh,0)
+
+inst_57:
+// rs2_val == 16384, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x4000; immval:-0x400; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x4000,-0x400,160,sh,0)
+
+inst_58:
+// rs2_val == 8192, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x2000; immval:-0x201; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2000,-0x201,164,sh,0)
+
+inst_59:
+// rs2_val == 4096, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x1000; immval:-0x3; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x1000,-0x3,168,sh,0)
+
+inst_60:
+// rs2_val == 1024, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x400; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x400,-0x81,172,sh,0)
+
+inst_61:
+// rs2_val == 512, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x200; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x200,0x40,176,sh,0)
+
+inst_62:
+// rs2_val == 256, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x100; immval:-0x800; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x100,-0x800,180,sh,0)
+
+inst_63:
+// rs2_val == 128, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x80; immval:-0x6; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x80,-0x6,184,sh,0)
+
+inst_64:
+// rs2_val == 64, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x40; immval:-0x11; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40,-0x11,188,sh,0)
+
+inst_65:
+// rs2_val == 32, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x20; immval:0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20,0x9,192,sh,0)
+
+inst_66:
+// rs2_val == 16, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x10; immval:-0x7; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10,-0x7,196,sh,0)
+
+inst_67:
+// rs2_val == 8, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x8; immval:-0x3; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8,-0x3,200,sh,0)
+
+inst_68:
+// rs2_val == 4, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x4; immval:-0x4; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x4,-0x4,204,sh,0)
+
+inst_69:
+// rs2_val == 2, 
+// opcode: sh; op1:x10; op2:x11; op2val:0x2; immval:0x400; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2,0x400,208,sh,0)
+
+inst_70:
+// rs2_val == -524289, 
+// opcode: sh; op1:x10; op2:x11; op2val:-0x80001; immval:-0x5; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x80001,-0x5,212,sh,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 54*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S
new file mode 100644
index 000000000..f219b7af4
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S
@@ -0,0 +1,521 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sll instruction of the RISC-V E extension for the sll covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sll)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x6, rs2==x13, rd==x1, rs1_val < 0 and rs2_val == 0, 
+// opcode: sll ; op1:x6; op2:x13; dest:x1; op1val:-0x40000000;  op2val:0x0
+TEST_RR_OP(sll, x1, x6, x13, 0xc0000000, -0x40000000, 0x0, x2, 0, x7)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x4, rs2==x1, rd==x4, rs2_val == 15, rs1_val == -17, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: sll ; op1:x4; op2:x1; dest:x4; op1val:-0x11;  op2val:0xf
+TEST_RR_OP(sll, x4, x4, x1, 0xfff78000, -0x11, 0xf, x2, 4, x7)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x9, rs2==x11, rd==x11, rs2_val == 23, rs1_val == -257
+// opcode: sll ; op1:x9; op2:x11; dest:x11; op1val:-0x101;  op2val:0x17
+TEST_RR_OP(sll, x11, x9, x11, 0x7f800000, -0x101, 0x17, x2, 8, x7)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x12, rs2==x12, rd==x9, rs2_val == 27, rs1_val==-46340
+// opcode: sll ; op1:x12; op2:x12; dest:x9; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(sll, x9, x12, x12, 0xc0000000, -0xb504, -0xb504, x2, 12, x7)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0, rs2_val == 29, rs1_val == 4, rs1_val==4, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: sll ; op1:x0; op2:x0; dest:x0; op1val:0x0;  op2val:0x0
+TEST_RR_OP(sll, x0, x0, x0, 0, 0x0, 0x0, x2, 16, x7)
+
+inst_5:
+// rs1==x5, rs2==x4, rd==x15, rs2_val == 30, rs1_val == -65
+// opcode: sll ; op1:x5; op2:x4; dest:x15; op1val:-0x41;  op2val:0x1e
+TEST_RR_OP(sll, x15, x5, x4, 0xc0000000, -0x41, 0x1e, x2, 20, x7)
+
+inst_6:
+// rs1==x1, rs2==x10, rd==x3, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
+// opcode: sll ; op1:x1; op2:x10; dest:x3; op1val:0x7fffffff;  op2val:0x9
+TEST_RR_OP(sll, x3, x1, x10, 0xfffffe00, 0x7fffffff, 0x9, x2, 24, x7)
+
+inst_7:
+// rs1==x8, rs2==x15, rd==x10, rs1_val == -1073741825, 
+// opcode: sll ; op1:x8; op2:x15; dest:x10; op1val:-0x40000001;  op2val:0x11
+TEST_RR_OP(sll, x10, x8, x15, 0xfffe0000, -0x40000001, 0x11, x2, 28, x4)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_8:
+// rs1==x13, rs2==x6, rd==x12, rs1_val == -536870913, rs2_val == 1
+// opcode: sll ; op1:x13; op2:x6; dest:x12; op1val:-0x20000001;  op2val:0x1
+TEST_RR_OP(sll, x12, x13, x6, 0xbffffffe, -0x20000001, 0x1, x1, 0, x4)
+
+inst_9:
+// rs1==x3, rs2==x9, rd==x5, rs1_val == -268435457, 
+// opcode: sll ; op1:x3; op2:x9; dest:x5; op1val:-0x10000001;  op2val:0xe
+TEST_RR_OP(sll, x5, x3, x9, 0xffffc000, -0x10000001, 0xe, x1, 4, x4)
+
+inst_10:
+// rs1==x7, rs2==x2, rd==x13, rs1_val == -134217729, 
+// opcode: sll ; op1:x7; op2:x2; dest:x13; op1val:-0x8000001;  op2val:0x1e
+TEST_RR_OP(sll, x13, x7, x2, 0xc0000000, -0x8000001, 0x1e, x1, 8, x4)
+
+inst_11:
+// rs1==x11, rs2==x7, rd==x8, rs1_val == -67108865, 
+// opcode: sll ; op1:x11; op2:x7; dest:x8; op1val:-0x4000001;  op2val:0x17
+TEST_RR_OP(sll, x8, x11, x7, 0xff800000, -0x4000001, 0x17, x1, 12, x4)
+
+inst_12:
+// rs1==x10, rs2==x14, rd==x7, rs1_val == -33554433, rs2_val == 8
+// opcode: sll ; op1:x10; op2:x14; dest:x7; op1val:-0x2000001;  op2val:0x8
+TEST_RR_OP(sll, x7, x10, x14, 0xffffff00, -0x2000001, 0x8, x1, 16, x4)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_13:
+// rs1==x14, rs2==x8, rd==x6, rs1_val == -16777217, 
+// opcode: sll ; op1:x14; op2:x8; dest:x6; op1val:-0x1000001;  op2val:0xd
+TEST_RR_OP(sll, x6, x14, x8, 0xffffe000, -0x1000001, 0xd, x1, 0, x4)
+
+inst_14:
+// rs1==x15, rs2==x3, rd==x2, rs1_val == -8388609, rs2_val == 21
+// opcode: sll ; op1:x15; op2:x3; dest:x2; op1val:-0x800001;  op2val:0x15
+TEST_RR_OP(sll, x2, x15, x3, 0xffe00000, -0x800001, 0x15, x1, 4, x4)
+
+inst_15:
+// rs1==x2, rs2==x5, rd==x14, rs1_val == -4194305, 
+// opcode: sll ; op1:x2; op2:x5; dest:x14; op1val:-0x400001;  op2val:0xb
+TEST_RR_OP(sll, x14, x2, x5, 0xfffff800, -0x400001, 0xb, x1, 8, x4)
+
+inst_16:
+// rs1_val == -2097153, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0xb
+TEST_RR_OP(sll, x12, x10, x11, 0xfffff800, -0x200001, 0xb, x1, 12, x4)
+
+inst_17:
+// rs1_val == -1048577, rs2_val == 2
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x2
+TEST_RR_OP(sll, x12, x10, x11, 0xffbffffc, -0x100001, 0x2, x1, 16, x2)
+
+inst_18:
+// rs1_val == -524289, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0x9
+TEST_RR_OP(sll, x12, x10, x11, 0xeffffe00, -0x80001, 0x9, x1, 20, x2)
+
+inst_19:
+// rs1_val == -262145, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0xf
+TEST_RR_OP(sll, x12, x10, x11, 0xffff8000, -0x40001, 0xf, x1, 24, x2)
+
+inst_20:
+// rs1_val == -131073, rs2_val == 10
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0xf7fffc00, -0x20001, 0xa, x1, 28, x2)
+
+inst_21:
+// rs1_val == -65537, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x2
+TEST_RR_OP(sll, x12, x10, x11, 0xfffbfffc, -0x10001, 0x2, x1, 32, x2)
+
+inst_22:
+// rs1_val == -32769, rs2_val == 4
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x4
+TEST_RR_OP(sll, x12, x10, x11, 0xfff7fff0, -0x8001, 0x4, x1, 36, x2)
+
+inst_23:
+// rs1_val == -16385, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x0
+TEST_RR_OP(sll, x12, x10, x11, 0xffffbfff, -0x4001, 0x0, x1, 40, x2)
+
+inst_24:
+// rs1_val == -8193, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0xd
+TEST_RR_OP(sll, x12, x10, x11, 0xfbffe000, -0x2001, 0xd, x1, 44, x2)
+
+inst_25:
+// rs1_val == -4097, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x1e
+TEST_RR_OP(sll, x12, x10, x11, 0xc0000000, -0x1001, 0x1e, x1, 48, x2)
+
+inst_26:
+// rs1_val == -2049, rs2_val == 16
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0xf7ff0000, -0x801, 0x10, x1, 52, x2)
+
+inst_27:
+// rs1_val == -1025, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x5
+TEST_RR_OP(sll, x12, x10, x11, 0xffff7fe0, -0x401, 0x5, x1, 56, x2)
+
+inst_28:
+// rs1_val == -513, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x5
+TEST_RR_OP(sll, x12, x10, x11, 0xffffbfe0, -0x201, 0x5, x1, 60, x2)
+
+inst_29:
+// rs1_val == -129, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0xff7f0000, -0x81, 0x10, x1, 64, x2)
+
+inst_30:
+// rs1_val == -33, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0xffdf0000, -0x21, 0x10, x1, 68, x2)
+
+inst_31:
+// rs1_val == -9, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0xfff70000, -0x9, 0x10, x1, 72, x2)
+
+inst_32:
+// rs1_val == -5, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0xf
+TEST_RR_OP(sll, x12, x10, x11, 0xfffd8000, -0x5, 0xf, x1, 76, x2)
+
+inst_33:
+// rs1_val == -3, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0x4
+TEST_RR_OP(sll, x12, x10, x11, 0xffffffd0, -0x3, 0x4, x1, 80, x2)
+
+inst_34:
+// rs1_val == -2, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x2
+TEST_RR_OP(sll, x12, x10, x11, 0xfffffff8, -0x2, 0x2, x1, 84, x2)
+
+inst_35:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x1f
+TEST_RR_OP(sll, x12, x10, x11, 0x0, -0x80000000, 0x1f, x1, 88, x2)
+
+inst_36:
+// rs1_val == 1073741824, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x17
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x40000000, 0x17, x1, 92, x2)
+
+inst_37:
+// rs1_val == 536870912, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0xb
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x20000000, 0xb, x1, 96, x2)
+
+inst_38:
+// rs1_val == 268435456, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x1
+TEST_RR_OP(sll, x12, x10, x11, 0x20000000, 0x10000000, 0x1, x1, 100, x2)
+
+inst_39:
+// rs1_val == 134217728, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x13
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x8000000, 0x13, x1, 104, x2)
+
+inst_40:
+// rs1_val == 67108864, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x5
+TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x4000000, 0x5, x1, 108, x2)
+
+inst_41:
+// rs1_val == 33554432, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x3
+TEST_RR_OP(sll, x12, x10, x11, 0x10000000, 0x2000000, 0x3, x1, 112, x2)
+
+inst_42:
+// rs1_val == 16777216, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x1000000, 0xa, x1, 116, x2)
+
+inst_43:
+// rs1_val == 8388608, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x4
+TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x800000, 0x4, x1, 120, x2)
+
+inst_44:
+// rs1_val == 4194304, rs1_val > 0 and rs2_val == 0
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x0
+TEST_RR_OP(sll, x12, x10, x11, 0x400000, 0x400000, 0x0, x1, 124, x2)
+
+inst_45:
+// rs1_val == 2097152, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x12
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x200000, 0x12, x1, 128, x2)
+
+inst_46:
+// rs1_val == 1048576, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x1f
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x100000, 0x1f, x1, 132, x2)
+
+inst_47:
+// rs1_val == 524288, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x7
+TEST_RR_OP(sll, x12, x10, x11, 0x4000000, 0x80000, 0x7, x1, 136, x2)
+
+inst_48:
+// rs1_val == 262144, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x1b
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x40000, 0x1b, x1, 140, x2)
+
+inst_49:
+// rs1_val == 131072, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x20000, 0x10, x1, 144, x2)
+
+inst_50:
+// rs1_val == 65536, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x11
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x10000, 0x11, x1, 148, x2)
+
+inst_51:
+// rs1_val == 32768, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0xc
+TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x8000, 0xc, x1, 152, x2)
+
+inst_52:
+// rs1_val == 16384, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x12
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x4000, 0x12, x1, 156, x2)
+
+inst_53:
+// rs1_val == 8192, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x8
+TEST_RR_OP(sll, x12, x10, x11, 0x200000, 0x2000, 0x8, x1, 160, x2)
+
+inst_54:
+// rs1_val == 4096, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x400000, 0x1000, 0xa, x1, 164, x2)
+
+inst_55:
+// rs1_val == 2048, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x200000, 0x800, 0xa, x1, 168, x2)
+
+inst_56:
+// rs1_val == 1024, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x11
+TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x400, 0x11, x1, 172, x2)
+
+inst_57:
+// rs1_val == 512, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x17
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x200, 0x17, x1, 176, x2)
+
+inst_58:
+// rs1_val == 256, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x7
+TEST_RR_OP(sll, x12, x10, x11, 0x8000, 0x100, 0x7, x1, 180, x2)
+
+inst_59:
+// rs1_val == 128, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x1f
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x80, 0x1f, x1, 184, x2)
+
+inst_60:
+// rs1_val == 64, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x10000, 0x40, 0xa, x1, 188, x2)
+
+inst_61:
+// rs1_val == 32, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x8000, 0x20, 0xa, x1, 192, x2)
+
+inst_62:
+// rs1_val == 16, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x17
+TEST_RR_OP(sll, x12, x10, x11, 0x8000000, 0x10, 0x17, x1, 196, x2)
+
+inst_63:
+// rs1_val == 8, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x1d
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x8, 0x1d, x1, 200, x2)
+
+inst_64:
+// rs1_val == 2, rs1_val==2
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1b
+TEST_RR_OP(sll, x12, x10, x11, 0x10000000, 0x2, 0x1b, x1, 204, x2)
+
+inst_65:
+// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1f
+TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x1, 0x1f, x1, 208, x2)
+
+inst_66:
+// rs1_val==46341, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x13
+TEST_RR_OP(sll, x12, x10, x11, 0xa8280000, 0xb505, 0x13, x1, 212, x2)
+
+inst_67:
+// rs1_val==-46339, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x8
+TEST_RR_OP(sll, x12, x10, x11, 0xff4afd00, -0xb503, 0x8, x1, 216, x2)
+
+inst_68:
+// rs1_val==1717986919, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(sll, x12, x10, x11, 0x9999999c, 0x66666667, 0x2, x1, 220, x2)
+
+inst_69:
+// rs1_val==858993460, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(sll, x12, x10, x11, 0x66666680, 0x33333334, 0x5, x1, 224, x2)
+
+inst_70:
+// rs1_val==6, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x11
+TEST_RR_OP(sll, x12, x10, x11, 0xc0000, 0x6, 0x11, x1, 228, x2)
+
+inst_71:
+// rs1_val==-1431655765, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x11
+TEST_RR_OP(sll, x12, x10, x11, 0x55560000, -0x55555555, 0x11, x1, 232, x2)
+
+inst_72:
+// rs1_val==1431655766, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x13
+TEST_RR_OP(sll, x12, x10, x11, 0xaab00000, 0x55555556, 0x13, x1, 236, x2)
+
+inst_73:
+// rs1_val==46339, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(sll, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 240, x2)
+
+inst_74:
+// rs1_val==3, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x11
+TEST_RR_OP(sll, x12, x10, x11, 0x60000, 0x3, 0x11, x1, 244, x2)
+
+inst_75:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x10
+TEST_RR_OP(sll, x12, x10, x11, 0xaaaa0000, -0x55555556, 0x10, x1, 248, x2)
+
+inst_76:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x12
+TEST_RR_OP(sll, x12, x10, x11, 0x55540000, 0x55555555, 0x12, x1, 252, x2)
+
+inst_77:
+// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xc
+TEST_RR_OP(sll, x12, x10, x11, 0x0, 0x0, 0xc, x1, 256, x2)
+
+inst_78:
+// rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(sll, x12, x10, x11, 0x8, 0x2, 0x2, x1, 260, x2)
+
+inst_79:
+// rs1_val==1717986917, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x8
+TEST_RR_OP(sll, x12, x10, x11, 0x66666500, 0x66666665, 0x8, x1, 264, x2)
+
+inst_80:
+// rs1_val==858993458, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xe
+TEST_RR_OP(sll, x12, x10, x11, 0xcccc8000, 0x33333332, 0xe, x1, 268, x2)
+
+inst_81:
+// rs1_val==1431655764, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(sll, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 272, x2)
+
+inst_82:
+// rs1_val==46340, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x12
+TEST_RR_OP(sll, x12, x10, x11, 0xd4100000, 0xb504, 0x12, x1, 276, x2)
+
+inst_83:
+// rs1_val==1717986918, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x15
+TEST_RR_OP(sll, x12, x10, x11, 0xccc00000, 0x66666666, 0x15, x1, 280, x2)
+
+inst_84:
+// rs1_val==858993459, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(sll, x12, x10, x11, 0xccccccc0, 0x33333333, 0x6, x1, 284, x2)
+
+inst_85:
+// rs1_val==5, 
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xa
+TEST_RR_OP(sll, x12, x10, x11, 0x1400, 0x5, 0xa, x1, 288, x2)
+
+inst_86:
+// rs2_val == 27, rs1_val==-46340
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x1b
+TEST_RR_OP(sll, x12, x10, x11, 0xe0000000, -0xb504, 0x1b, x1, 292, x2)
+
+inst_87:
+// rs2_val == 29, rs1_val == 4, rs1_val==4, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: sll ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1d
+TEST_RR_OP(sll, x12, x10, x11, 0x80000000, 0x4, 0x1d, x1, 296, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 5*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 75*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S
new file mode 100644
index 000000000..754c14a5d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S
@@ -0,0 +1,526 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the slli instruction of the RISC-V E extension for the slli covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",slli)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rs1 != rd, rs1==x2, rd==x10, rs1_val < 0 and imm_val == (xlen-1), rs1_val < 0 and imm_val > 0 and imm_val < xlen
+// opcode: slli ; op1:x2; dest:x10; op1val:-0x1;  immval:0x1f
+TEST_IMM_OP( slli, x10, x2, 0x80000000, -0x1, 0x1f, x5, 0, x12)
+
+inst_1:
+// rs1 == rd, rs1==x3, rd==x3, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, imm_val == 27, rs1_val > 0 and imm_val > 0 and imm_val < xlen
+// opcode: slli ; op1:x3; dest:x3; op1val:0x7fffffff;  immval:0x1b
+TEST_IMM_OP( slli, x3, x3, 0xf8000000, 0x7fffffff, 0x1b, x5, 4, x12)
+
+inst_2:
+// rs1==x9, rd==x14, rs1_val == -1073741825, 
+// opcode: slli ; op1:x9; dest:x14; op1val:-0x40000001;  immval:0x7
+TEST_IMM_OP( slli, x14, x9, 0xffffff80, -0x40000001, 0x7, x5, 8, x12)
+
+inst_3:
+// rs1==x7, rd==x8, rs1_val == -536870913, imm_val == 1
+// opcode: slli ; op1:x7; dest:x8; op1val:-0x20000001;  immval:0x1
+TEST_IMM_OP( slli, x8, x7, 0xbffffffe, -0x20000001, 0x1, x5, 12, x12)
+
+inst_4:
+// rs1==x4, rd==x6, rs1_val == -268435457, 
+// opcode: slli ; op1:x4; dest:x6; op1val:-0x10000001;  immval:0x12
+TEST_IMM_OP( slli, x6, x4, 0xfffc0000, -0x10000001, 0x12, x5, 16, x12)
+
+inst_5:
+// rs1==x11, rd==x7, rs1_val == -134217729, rs1_val < 0 and imm_val == 0
+// opcode: slli ; op1:x11; dest:x7; op1val:-0x8000001;  immval:0x0
+TEST_IMM_OP( slli, x7, x11, 0xf7ffffff, -0x8000001, 0x0, x5, 20, x12)
+
+inst_6:
+// rs1==x0, rd==x1, rs1_val == -67108865, 
+// opcode: slli ; op1:x0; dest:x1; op1val:0x0;  immval:0x7
+TEST_IMM_OP( slli, x1, x0, 0x0, 0x0, 0x7, x5, 24, x12)
+
+inst_7:
+// rs1==x1, rd==x11, rs1_val == -33554433, imm_val == 15
+// opcode: slli ; op1:x1; dest:x11; op1val:-0x2000001;  immval:0xf
+TEST_IMM_OP( slli, x11, x1, 0xffff8000, -0x2000001, 0xf, x5, 28, x3)
+
+inst_8:
+// rs1==x10, rd==x12, rs1_val == -16777217, 
+// opcode: slli ; op1:x10; dest:x12; op1val:-0x1000001;  immval:0x13
+TEST_IMM_OP( slli, x12, x10, 0xfff80000, -0x1000001, 0x13, x5, 32, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_9:
+// rs1==x13, rd==x9, rs1_val == -8388609, imm_val == 16
+// opcode: slli ; op1:x13; dest:x9; op1val:-0x800001;  immval:0x10
+TEST_IMM_OP( slli, x9, x13, 0xffff0000, -0x800001, 0x10, x1, 0, x3)
+
+inst_10:
+// rs1==x5, rd==x13, rs1_val == -4194305, 
+// opcode: slli ; op1:x5; dest:x13; op1val:-0x400001;  immval:0x1f
+TEST_IMM_OP( slli, x13, x5, 0x80000000, -0x400001, 0x1f, x1, 4, x3)
+
+inst_11:
+// rs1==x8, rd==x15, rs1_val == -2097153, 
+// opcode: slli ; op1:x8; dest:x15; op1val:-0x200001;  immval:0x1b
+TEST_IMM_OP( slli, x15, x8, 0xf8000000, -0x200001, 0x1b, x1, 8, x3)
+
+inst_12:
+// rs1==x15, rd==x4, rs1_val == -1048577, 
+// opcode: slli ; op1:x15; dest:x4; op1val:-0x100001;  immval:0xc
+TEST_IMM_OP( slli, x4, x15, 0xfffff000, -0x100001, 0xc, x1, 12, x3)
+
+inst_13:
+// rs1==x14, rd==x5, rs1_val == -524289, 
+// opcode: slli ; op1:x14; dest:x5; op1val:-0x80001;  immval:0x9
+TEST_IMM_OP( slli, x5, x14, 0xeffffe00, -0x80001, 0x9, x1, 16, x3)
+
+inst_14:
+// rs1==x6, rd==x2, rs1_val == -262145, 
+// opcode: slli ; op1:x6; dest:x2; op1val:-0x40001;  immval:0x0
+TEST_IMM_OP( slli, x2, x6, 0xfffbffff, -0x40001, 0x0, x1, 20, x3)
+
+inst_15:
+// rs1==x12, rd==x0, rs1_val == -131073, 
+// opcode: slli ; op1:x12; dest:x0; op1val:-0x20001;  immval:0x10
+TEST_IMM_OP( slli, x0, x12, 0, -0x20001, 0x10, x1, 24, x2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x10001;  immval:0xb
+TEST_IMM_OP( slli, x11, x10, 0xf7fff800, -0x10001, 0xb, x1, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x11
+TEST_IMM_OP( slli, x11, x10, 0xfffe0000, -0x8001, 0x11, x1, 0, x2)
+
+inst_18:
+// rs1_val == -16385, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x1b
+TEST_IMM_OP( slli, x11, x10, 0xf8000000, -0x4001, 0x1b, x1, 4, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x11
+TEST_IMM_OP( slli, x11, x10, 0xbffe0000, -0x2001, 0x11, x1, 8, x2)
+
+inst_20:
+// rs1_val == -4097, imm_val == 29
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x1001;  immval:0x1d
+TEST_IMM_OP( slli, x11, x10, 0xe0000000, -0x1001, 0x1d, x1, 12, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x801;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0xfdffc000, -0x801, 0xe, x1, 16, x2)
+
+inst_22:
+// rs1_val == -1025, imm_val == 23
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x401;  immval:0x17
+TEST_IMM_OP( slli, x11, x10, 0xff800000, -0x401, 0x17, x1, 20, x2)
+
+inst_23:
+// rs1_val == -513, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x201;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0xff7fc000, -0x201, 0xe, x1, 24, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x101;  immval:0x11
+TEST_IMM_OP( slli, x11, x10, 0xfdfe0000, -0x101, 0x11, x1, 28, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x81;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0xffdfc000, -0x81, 0xe, x1, 32, x2)
+
+inst_26:
+// rs1_val == -65, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x41;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0xffefc000, -0x41, 0xe, x1, 36, x2)
+
+inst_27:
+// rs1_val == -33, imm_val == 8
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x21;  immval:0x8
+TEST_IMM_OP( slli, x11, x10, 0xffffdf00, -0x21, 0x8, x1, 40, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x11;  immval:0x6
+TEST_IMM_OP( slli, x11, x10, 0xfffffbc0, -0x11, 0x6, x1, 44, x2)
+
+inst_29:
+// rs1_val == -9, imm_val == 4
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x9;  immval:0x4
+TEST_IMM_OP( slli, x11, x10, 0xffffff70, -0x9, 0x4, x1, 48, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x5;  immval:0x10
+TEST_IMM_OP( slli, x11, x10, 0xfffb0000, -0x5, 0x10, x1, 52, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x3;  immval:0x9
+TEST_IMM_OP( slli, x11, x10, 0xfffffa00, -0x3, 0x9, x1, 56, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x2;  immval:0x7
+TEST_IMM_OP( slli, x11, x10, 0xffffff00, -0x2, 0x7, x1, 60, x2)
+
+inst_33:
+// imm_val == 30, rs1_val == 0 and imm_val >= 0 and imm_val < xlen, rs1_val==0
+// opcode: slli ; op1:x10; dest:x11; op1val:0x0;  immval:0x1e
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x0, 0x1e, x1, 64, x2)
+
+inst_34:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x17
+TEST_IMM_OP( slli, x11, x10, 0x0, -0x80000000, 0x17, x1, 68, x2)
+
+inst_35:
+// rs1_val == 1073741824, imm_val == 21
+// opcode: slli ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x15
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x40000000, 0x15, x1, 72, x2)
+
+inst_36:
+// rs1_val == 536870912, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x10
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x20000000, 0x10, x1, 76, x2)
+
+inst_37:
+// rs1_val == 268435456, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x7
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x10000000, 0x7, x1, 80, x2)
+
+inst_38:
+// rs1_val == 134217728, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x8000000;  immval:0x1e
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x8000000, 0x1e, x1, 84, x2)
+
+inst_39:
+// rs1_val == 67108864, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x4000000;  immval:0xf
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x4000000, 0xf, x1, 88, x2)
+
+inst_40:
+// rs1_val == 33554432, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x1e
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x2000000, 0x1e, x1, 92, x2)
+
+inst_41:
+// rs1_val == 16777216, rs1_val > 0 and imm_val == (xlen-1)
+// opcode: slli ; op1:x10; dest:x11; op1val:0x1000000;  immval:0x1f
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x1000000, 0x1f, x1, 96, x2)
+
+inst_42:
+// rs1_val == 8388608, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x800000;  immval:0x15
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x800000, 0x15, x1, 100, x2)
+
+inst_43:
+// rs1_val == 4194304, rs1_val > 0 and imm_val == 0
+// opcode: slli ; op1:x10; dest:x11; op1val:0x400000;  immval:0x0
+TEST_IMM_OP( slli, x11, x10, 0x400000, 0x400000, 0x0, x1, 104, x2)
+
+inst_44:
+// rs1_val == 2097152, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x200000;  immval:0x6
+TEST_IMM_OP( slli, x11, x10, 0x8000000, 0x200000, 0x6, x1, 108, x2)
+
+inst_45:
+// rs1_val == 1048576, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x100000;  immval:0x11
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x100000, 0x11, x1, 112, x2)
+
+inst_46:
+// rs1_val == 524288, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x80000;  immval:0x1e
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x80000, 0x1e, x1, 116, x2)
+
+inst_47:
+// rs1_val == 262144, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x40000;  immval:0x13
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x40000, 0x13, x1, 120, x2)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x20000;  immval:0xf
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x20000, 0xf, x1, 124, x2)
+
+inst_49:
+// rs1_val == 65536, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x10000;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0x40000000, 0x10000, 0xe, x1, 128, x2)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x8000;  immval:0xc
+TEST_IMM_OP( slli, x11, x10, 0x8000000, 0x8000, 0xc, x1, 132, x2)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x4000;  immval:0x0
+TEST_IMM_OP( slli, x11, x10, 0x4000, 0x4000, 0x0, x1, 136, x2)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x2000;  immval:0x0
+TEST_IMM_OP( slli, x11, x10, 0x2000, 0x2000, 0x0, x1, 140, x2)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x1000;  immval:0x1
+TEST_IMM_OP( slli, x11, x10, 0x2000, 0x1000, 0x1, x1, 144, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x800;  immval:0x15
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x800, 0x15, x1, 148, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x400;  immval:0xc
+TEST_IMM_OP( slli, x11, x10, 0x400000, 0x400, 0xc, x1, 152, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x200;  immval:0x3
+TEST_IMM_OP( slli, x11, x10, 0x1000, 0x200, 0x3, x1, 156, x2)
+
+inst_57:
+// rs1_val == 256, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x100;  immval:0x15
+TEST_IMM_OP( slli, x11, x10, 0x20000000, 0x100, 0x15, x1, 160, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x80;  immval:0x1d
+TEST_IMM_OP( slli, x11, x10, 0x0, 0x80, 0x1d, x1, 164, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x40;  immval:0x6
+TEST_IMM_OP( slli, x11, x10, 0x1000, 0x40, 0x6, x1, 168, x2)
+
+inst_60:
+// rs1_val == 32, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x20;  immval:0xb
+TEST_IMM_OP( slli, x11, x10, 0x10000, 0x20, 0xb, x1, 172, x2)
+
+inst_61:
+// rs1_val == 16, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x10;  immval:0x0
+TEST_IMM_OP( slli, x11, x10, 0x10, 0x10, 0x0, x1, 176, x2)
+
+inst_62:
+// rs1_val == 8, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x8;  immval:0x13
+TEST_IMM_OP( slli, x11, x10, 0x400000, 0x8, 0x13, x1, 180, x2)
+
+inst_63:
+// rs1_val == 4, rs1_val==4, rs1_val == imm_val and imm_val > 0 and imm_val < xlen
+// opcode: slli ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( slli, x11, x10, 0x40, 0x4, 0x4, x1, 184, x2)
+
+inst_64:
+// rs1_val == 2, rs1_val==2
+// opcode: slli ; op1:x10; dest:x11; op1val:0x2;  immval:0xb
+TEST_IMM_OP( slli, x11, x10, 0x1000, 0x2, 0xb, x1, 188, x2)
+
+inst_65:
+// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen
+// opcode: slli ; op1:x10; dest:x11; op1val:0x1;  immval:0xe
+TEST_IMM_OP( slli, x11, x10, 0x4000, 0x1, 0xe, x1, 192, x2)
+
+inst_66:
+// imm_val == 2, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x81;  immval:0x2
+TEST_IMM_OP( slli, x11, x10, 0xfffffdfc, -0x81, 0x2, x1, 196, x2)
+
+inst_67:
+// rs1_val==46341, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0xb505;  immval:0xf
+TEST_IMM_OP( slli, x11, x10, 0x5a828000, 0xb505, 0xf, x1, 200, x2)
+
+inst_68:
+// rs1_val==-46339, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x17
+TEST_IMM_OP( slli, x11, x10, 0x7e800000, -0xb503, 0x17, x1, 204, x2)
+
+inst_69:
+// rs1_val==1717986919, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x1b
+TEST_IMM_OP( slli, x11, x10, 0x38000000, 0x66666667, 0x1b, x1, 208, x2)
+
+inst_70:
+// rs1_val==858993460, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x13
+TEST_IMM_OP( slli, x11, x10, 0x99a00000, 0x33333334, 0x13, x1, 212, x2)
+
+inst_71:
+// rs1_val==6, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x6;  immval:0xb
+TEST_IMM_OP( slli, x11, x10, 0x3000, 0x6, 0xb, x1, 216, x2)
+
+inst_72:
+// rs1_val==-1431655765, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x12
+TEST_IMM_OP( slli, x11, x10, 0xaaac0000, -0x55555555, 0x12, x1, 220, x2)
+
+inst_73:
+// rs1_val==1431655766, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x1e
+TEST_IMM_OP( slli, x11, x10, 0x80000000, 0x55555556, 0x1e, x1, 224, x2)
+
+inst_74:
+// rs1_val==3, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x3;  immval:0x12
+TEST_IMM_OP( slli, x11, x10, 0xc0000, 0x3, 0x12, x1, 228, x2)
+
+inst_75:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x10
+TEST_IMM_OP( slli, x11, x10, 0xaaaa0000, -0x55555556, 0x10, x1, 232, x2)
+
+inst_76:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: slli ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x7
+TEST_IMM_OP( slli, x11, x10, 0xaaaaaa80, 0x55555555, 0x7, x1, 236, x2)
+
+inst_77:
+// imm_val == 10, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x1001;  immval:0xa
+TEST_IMM_OP( slli, x11, x10, 0xffbffc00, -0x1001, 0xa, x1, 240, x2)
+
+inst_78:
+// rs1_val==46339, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( slli, x11, x10, 0x2d40c0, 0xb503, 0x6, x1, 244, x2)
+
+inst_79:
+// rs1_val==1717986917, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x66666665;  immval:0xd
+TEST_IMM_OP( slli, x11, x10, 0xcccca000, 0x66666665, 0xd, x1, 248, x2)
+
+inst_80:
+// rs1_val==858993458, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x1
+TEST_IMM_OP( slli, x11, x10, 0x66666664, 0x33333332, 0x1, x1, 252, x2)
+
+inst_81:
+// rs1_val==1431655764, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x1d
+TEST_IMM_OP( slli, x11, x10, 0x80000000, 0x55555554, 0x1d, x1, 256, x2)
+
+inst_82:
+// rs1_val==46340, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0xb504;  immval:0x11
+TEST_IMM_OP( slli, x11, x10, 0x6a080000, 0xb504, 0x11, x1, 260, x2)
+
+inst_83:
+// rs1_val==-46340, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x13
+TEST_IMM_OP( slli, x11, x10, 0x57e00000, -0xb504, 0x13, x1, 264, x2)
+
+inst_84:
+// rs1_val==1717986918, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x1d
+TEST_IMM_OP( slli, x11, x10, 0xc0000000, 0x66666666, 0x1d, x1, 268, x2)
+
+inst_85:
+// rs1_val==858993459, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x33333333;  immval:0xa
+TEST_IMM_OP( slli, x11, x10, 0xcccccc00, 0x33333333, 0xa, x1, 272, x2)
+
+inst_86:
+// rs1_val==5, 
+// opcode: slli ; op1:x10; dest:x11; op1val:0x5;  immval:0x1b
+TEST_IMM_OP( slli, x11, x10, 0x28000000, 0x5, 0x1b, x1, 276, x2)
+
+inst_87:
+// rs1_val == -67108865, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x4000001;  immval:0x7
+TEST_IMM_OP( slli, x11, x10, 0xffffff80, -0x4000001, 0x7, x1, 280, x2)
+
+inst_88:
+// rs1_val == -131073, 
+// opcode: slli ; op1:x10; dest:x11; op1val:-0x20001;  immval:0x10
+TEST_IMM_OP( slli, x11, x10, 0xffff0000, -0x20001, 0x10, x1, 284, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 72*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S
new file mode 100644
index 000000000..f7c57a553
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S
@@ -0,0 +1,2991 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the slt instruction of the RISC-V E extension for the slt covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",slt)
+
+RVTEST_SIGBASE( x12,signature_x12_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x5, rs2==x10, rd==x7, rs1_val != rs2_val, rs2_val == -65537, rs1_val == -129, rs1_val < 0 and rs2_val < 0
+// opcode: slt ; op1:x5; op2:x10; dest:x7; op1val:-0x81;  op2val:-0x10001
+TEST_RR_OP(slt, x7, x5, x10, 0x0, -0x81, -0x10001, x12, 0, x13)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x0, rs2==x6, rd==x0, rs2_val == 2147483647, rs1_val == -4194305, rs1_val < 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: slt ; op1:x0; op2:x6; dest:x0; op1val:0x0;  op2val:0x7fffffff
+TEST_RR_OP(slt, x0, x0, x6, 0, 0x0, 0x7fffffff, x12, 4, x13)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x9, rs2==x8, rd==x8, rs2_val == -1073741825, rs1_val > 0 and rs2_val < 0, rs1_val == 512
+// opcode: slt ; op1:x9; op2:x8; dest:x8; op1val:0x200;  op2val:-0x40000001
+TEST_RR_OP(slt, x8, x9, x8, 0x0, 0x200, -0x40000001, x12, 8, x13)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x4, rs2==x4, rd==x11, rs2_val == -536870913, rs1_val == -4097
+// opcode: slt ; op1:x4; op2:x4; dest:x11; op1val:-0x1001;  op2val:-0x1001
+TEST_RR_OP(slt, x11, x4, x4, 0x0, -0x1001, -0x1001, x12, 12, x13)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x3, rs2==x3, rd==x3, rs2_val == -268435457, 
+// opcode: slt ; op1:x3; op2:x3; dest:x3; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(slt, x3, x3, x3, 0x0, -0x55555555, -0x55555555, x12, 16, x13)
+
+inst_5:
+// rs1==x1, rs2==x0, rd==x4, rs2_val == -134217729, rs1_val == -65537
+// opcode: slt ; op1:x1; op2:x0; dest:x4; op1val:-0x10001;  op2val:0x0
+TEST_RR_OP(slt, x4, x1, x0, 0x1, -0x10001, 0x0, x12, 20, x13)
+
+inst_6:
+// rs1==x6, rs2==x2, rd==x5, rs2_val == -67108865, rs1_val == -33554433
+// opcode: slt ; op1:x6; op2:x2; dest:x5; op1val:-0x2000001;  op2val:-0x4000001
+TEST_RR_OP(slt, x5, x6, x2, 0x0, -0x2000001, -0x4000001, x12, 24, x13)
+
+inst_7:
+// rs1==x7, rs2==x11, rd==x13, rs2_val == -33554433, rs1_val == -2
+// opcode: slt ; op1:x7; op2:x11; dest:x13; op1val:-0x2;  op2val:-0x2000001
+TEST_RR_OP(slt, x13, x7, x11, 0x0, -0x2, -0x2000001, x12, 28, x1)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_8:
+// rs1==x15, rs2==x7, rd==x12, rs2_val == -16777217, rs1_val == 4096
+// opcode: slt ; op1:x15; op2:x7; dest:x12; op1val:0x1000;  op2val:-0x1000001
+TEST_RR_OP(slt, x12, x15, x7, 0x0, 0x1000, -0x1000001, x3, 0, x1)
+
+inst_9:
+// rs1==x13, rs2==x5, rd==x2, rs2_val == -8388609, rs1_val == -268435457
+// opcode: slt ; op1:x13; op2:x5; dest:x2; op1val:-0x10000001;  op2val:-0x800001
+TEST_RR_OP(slt, x2, x13, x5, 0x1, -0x10000001, -0x800001, x3, 4, x1)
+
+inst_10:
+// rs1==x2, rs2==x9, rd==x15, rs2_val == -4194305, rs1_val == -1431655766
+// opcode: slt ; op1:x2; op2:x9; dest:x15; op1val:-0x55555556;  op2val:-0x400001
+TEST_RR_OP(slt, x15, x2, x9, 0x1, -0x55555556, -0x400001, x3, 8, x1)
+
+inst_11:
+// rs1==x8, rs2==x15, rd==x14, rs2_val == -2097153, rs1_val == -513
+// opcode: slt ; op1:x8; op2:x15; dest:x14; op1val:-0x201;  op2val:-0x200001
+TEST_RR_OP(slt, x14, x8, x15, 0x0, -0x201, -0x200001, x3, 12, x1)
+
+inst_12:
+// rs1==x10, rs2==x13, rd==x9, rs2_val == -1048577, rs1_val == 524288
+// opcode: slt ; op1:x10; op2:x13; dest:x9; op1val:0x80000;  op2val:-0x100001
+TEST_RR_OP(slt, x9, x10, x13, 0x0, 0x80000, -0x100001, x3, 16, x1)
+
+inst_13:
+// rs1==x12, rs2==x14, rd==x6, rs2_val == -524289, rs1_val == 0
+// opcode: slt ; op1:x12; op2:x14; dest:x6; op1val:0x0;  op2val:-0x80001
+TEST_RR_OP(slt, x6, x12, x14, 0x0, 0x0, -0x80001, x3, 20, x4)
+
+inst_14:
+// rs1==x14, rs2==x1, rd==x10, rs2_val == -262145, rs1_val == -2049
+// opcode: slt ; op1:x14; op2:x1; dest:x10; op1val:-0x801;  op2val:-0x40001
+TEST_RR_OP(slt, x10, x14, x1, 0x0, -0x801, -0x40001, x3, 24, x4)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_15:
+// rs1==x11, rs2==x12, rd==x1, rs2_val == -131073, 
+// opcode: slt ; op1:x11; op2:x12; dest:x1; op1val:0x0;  op2val:-0x20001
+TEST_RR_OP(slt, x1, x11, x12, 0x0, 0x0, -0x20001, x2, 0, x4)
+
+inst_16:
+// rs2_val == -32769, rs1_val == 16384
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x8001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4000, -0x8001, x2, 4, x4)
+
+inst_17:
+// rs2_val == -16385, rs1_val == 1073741824
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x4001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x40000000, -0x4001, x2, 8, x4)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0x2001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x801, -0x2001, x2, 12, x4)
+
+inst_19:
+// rs2_val == -4097, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x1001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, -0x1001, x2, 16, x4)
+
+inst_20:
+// rs2_val == -2049, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x801
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, -0x801, x2, 20, x4)
+
+inst_21:
+// rs2_val == -1025, rs1_val == -16385
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x401
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x4001, -0x401, x2, 24, x4)
+
+inst_22:
+// rs2_val == -513, rs1_val == 8192
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x201
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2000, -0x201, x2, 28, x4)
+
+inst_23:
+// rs2_val == -257, rs1_val == -5
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:-0x101
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x5, -0x101, x2, 32, x4)
+
+inst_24:
+// rs2_val == -129, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x81
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, -0x81, x2, 36, x4)
+
+inst_25:
+// rs2_val == -65, rs1_val == -32769
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:-0x41
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x8001, -0x41, x2, 40, x4)
+
+inst_26:
+// rs2_val == -33, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:-0x21
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x10000001, -0x21, x2, 44, x4)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x11
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x40000000, -0x11, x2, 48, x4)
+
+inst_28:
+// rs2_val == -9, rs1_val == 536870912
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:-0x9
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x20000000, -0x9, x2, 52, x4)
+
+inst_29:
+// rs2_val == -5, rs1_val == 128
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:-0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x80, -0x5, x2, 56, x4)
+
+inst_30:
+// rs2_val == -3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x9, -0x3, x2, 60, x4)
+
+inst_31:
+// rs2_val == -2, rs1_val == -65
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x41, -0x2, x2, 64, x4)
+
+inst_32:
+// rs1_val == 2147483647, rs2_val == 16777216, rs1_val == (2**(xlen-1)-1), rs1_val > 0 and rs2_val > 0
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x1000000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x7fffffff, 0x1000000, x2, 68, x4)
+
+inst_33:
+// rs1_val == -1073741825, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:-0x8001
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x40000001, -0x8001, x2, 72, x4)
+
+inst_34:
+// rs1_val == -536870913, rs2_val == 128
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x80
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x20000001, 0x80, x2, 76, x4)
+
+inst_35:
+// rs1_val == -134217729, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x8000001, -0x3, x2, 80, x4)
+
+inst_36:
+// rs1_val == -67108865, rs2_val == 8192
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x2000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x4000001, 0x2000, x2, 84, x4)
+
+inst_37:
+// rs1_val == -16777217, rs2_val == 2048
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x800
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x1000001, 0x800, x2, 88, x4)
+
+inst_38:
+// rs1_val == -8388609, rs2_val == -1431655766
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x800001, -0x55555556, x2, 92, x4)
+
+inst_39:
+// rs1_val == -2097153, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x1000001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x200001, -0x1000001, x2, 96, x4)
+
+inst_40:
+// rs1_val == -1048577, rs1_val == rs2_val
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:-0x100001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x100001, -0x100001, x2, 100, x4)
+
+inst_41:
+// rs1_val == -524289, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x81
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x80001, -0x81, x2, 104, x4)
+
+inst_42:
+// rs1_val == -262145, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x40001, 0x66666665, x2, 108, x4)
+
+inst_43:
+// rs1_val == -131073, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x7fffffff
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x20001, 0x7fffffff, x2, 112, x4)
+
+inst_44:
+// rs1_val == -8193, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x2001, -0x4, x2, 116, x4)
+
+inst_45:
+// rs1_val == -1025, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:-0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x401, -0x2, x2, 120, x4)
+
+inst_46:
+// rs1_val == -257, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x101, 0x66666667, x2, 124, x4)
+
+inst_47:
+// rs1_val == -33, rs2_val == 512
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x200
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x21, 0x200, x2, 128, x4)
+
+inst_48:
+// rs1_val == -17, rs2_val == 4
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x11, 0x4, x2, 132, x4)
+
+inst_49:
+// rs1_val == -9, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:-0x20000001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x9, -0x20000001, x2, 136, x4)
+
+inst_50:
+// rs1_val == -3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:-0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x3, -0x6, x2, 140, x4)
+
+inst_51:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1)), rs1_val == 8
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x80000000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x8, -0x80000000, x2, 144, x4)
+
+inst_52:
+// rs2_val == 1073741824, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:0x40000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x8000001, 0x40000000, x2, 148, x4)
+
+inst_53:
+// rs2_val == 536870912, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x20000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x20000000, x2, 152, x4)
+
+inst_54:
+// rs2_val == 268435456, rs1_val == 65536
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x10000, 0x10000000, x2, 156, x4)
+
+inst_55:
+// rs2_val == 134217728, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x8000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x4000001, 0x8000000, x2, 160, x4)
+
+inst_56:
+// rs2_val == 67108864, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x4000000, x2, 164, x4)
+
+inst_57:
+// rs2_val == 33554432, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x2000000, x2, 168, x4)
+
+inst_58:
+// rs2_val == 8388608, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0x800000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x7, 0x800000, x2, 172, x4)
+
+inst_59:
+// rs2_val == 4194304, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x400000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x400000, x2, 176, x4)
+
+inst_60:
+// rs2_val == 2097152, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x200000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x80, 0x200000, x2, 180, x4)
+
+inst_61:
+// rs2_val == 1048576, rs1_val == 16
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x100000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x10, 0x100000, x2, 184, x4)
+
+inst_62:
+// rs2_val == 524288, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x80000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x80000, x2, 188, x4)
+
+inst_63:
+// rs2_val == 262144, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x40000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x5, 0x40000, x2, 192, x4)
+
+inst_64:
+// rs2_val == 131072, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x20000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x20000, x2, 196, x4)
+
+inst_65:
+// rs2_val == 65536, rs1_val == 2097152
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x10000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x200000, 0x10000, x2, 200, x4)
+
+inst_66:
+// rs2_val == 32768, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x8000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x10000, 0x8000, x2, 204, x4)
+
+inst_67:
+// rs2_val == 16384, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x4000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x20001, 0x4000, x2, 208, x4)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x1000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x11, 0x1000, x2, 212, x4)
+
+inst_69:
+// rs2_val == 1024, rs1_val == 32768
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x400
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x8000, 0x400, x2, 216, x4)
+
+inst_70:
+// rs2_val == 256, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3fffffff;  op2val:0x100
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3fffffff, 0x100, x2, 220, x4)
+
+inst_71:
+// rs2_val == 64, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x40
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x40, x2, 224, x4)
+
+inst_72:
+// rs2_val == 32, rs1_val == 262144
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x20
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x40000, 0x20, x2, 228, x4)
+
+inst_73:
+// rs2_val == 16, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x10, x2, 232, x4)
+
+inst_74:
+// rs2_val == 8, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x8
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x8, x2, 236, x4)
+
+inst_75:
+// rs2_val == 2, rs1_val==2 and rs2_val==2, rs1_val == 2
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, 0x2, x2, 240, x4)
+
+inst_76:
+// rs2_val == 1, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x1, x2, 244, x4)
+
+inst_77:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x80000000, 0x3, x2, 248, x4)
+
+inst_78:
+// rs1_val == 268435456, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:-0x100001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x10000000, -0x100001, x2, 252, x4)
+
+inst_79:
+// rs1_val == 134217728, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x8000000, -0xb504, x2, 256, x4)
+
+inst_80:
+// rs1_val == 67108864, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:-0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4000000, -0x3, x2, 260, x4)
+
+inst_81:
+// rs1_val == 33554432, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2000000, 0x66666667, x2, 264, x4)
+
+inst_82:
+// rs1_val == 16777216, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x200000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x1000000, 0x200000, x2, 268, x4)
+
+inst_83:
+// rs1_val == 8388608, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x8000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x800000, 0x8000000, x2, 272, x4)
+
+inst_84:
+// rs1_val == 4194304, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:-0x100001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x400000, -0x100001, x2, 276, x4)
+
+inst_85:
+// rs1_val == 1048576, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x100000, 0x6, x2, 280, x4)
+
+inst_86:
+// rs1_val == 131072, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x800
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x20000, 0x800, x2, 284, x4)
+
+inst_87:
+// rs1_val == 2048, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x800, 0x66666665, x2, 288, x4)
+
+inst_88:
+// rs1_val == 1024, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:-0x40000000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x400, -0x40000000, x2, 292, x4)
+
+inst_89:
+// rs1_val == 256, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x40000000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x100, 0x40000000, x2, 296, x4)
+
+inst_90:
+// rs1_val == 64, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x80000000
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x40, -0x80000000, x2, 300, x4)
+
+inst_91:
+// rs1_val == 32, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:-0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x20, -0x3, x2, 304, x4)
+
+inst_92:
+// rs1_val == 4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x7fffffff
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x7fffffff, x2, 308, x4)
+
+inst_93:
+// rs1_val == 1, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2000
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x1, 0x2000, x2, 312, x4)
+
+inst_94:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0xb505, x2, 316, x4)
+
+inst_95:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, -0xb503, x2, 320, x4)
+
+inst_96:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x66666667, x2, 324, x4)
+
+inst_97:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x33333334, x2, 328, x4)
+
+inst_98:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x6, x2, 332, x4)
+
+inst_99:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, -0x55555555, x2, 336, x4)
+
+inst_100:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x55555556, x2, 340, x4)
+
+inst_101:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x4, x2, 344, x4)
+
+inst_102:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0xb503, x2, 348, x4)
+
+inst_103:
+// rs1_val==46341 and rs2_val==0, rs2_val == 0
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x0, x2, 352, x4)
+
+inst_104:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x66666665, x2, 356, x4)
+
+inst_105:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x33333332, x2, 360, x4)
+
+inst_106:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x55555554, x2, 364, x4)
+
+inst_107:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x2, x2, 368, x4)
+
+inst_108:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0xb504, x2, 372, x4)
+
+inst_109:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, -0xb504, x2, 376, x4)
+
+inst_110:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x66666666, x2, 380, x4)
+
+inst_111:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x33333333, x2, 384, x4)
+
+inst_112:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x5, x2, 388, x4)
+
+inst_113:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, -0x55555556, x2, 392, x4)
+
+inst_114:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb505, 0x55555555, x2, 396, x4)
+
+inst_115:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb505, 0x3, x2, 400, x4)
+
+inst_116:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0xb505, x2, 404, x4)
+
+inst_117:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb503, -0xb503, x2, 408, x4)
+
+inst_118:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x66666667, x2, 412, x4)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x33333334, x2, 416, x4)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x6, x2, 420, x4)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb503, -0x55555555, x2, 424, x4)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x55555556, x2, 428, x4)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x4, x2, 432, x4)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0xb503, x2, 436, x4)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x0, x2, 440, x4)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x66666665, x2, 444, x4)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x33333332, x2, 448, x4)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x55555554, x2, 452, x4)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x2, x2, 456, x4)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0xb504, x2, 460, x4)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb503, -0xb504, x2, 464, x4)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x66666666, x2, 468, x4)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x33333333, x2, 472, x4)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x5, x2, 476, x4)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb503, -0x55555556, x2, 480, x4)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x55555555, x2, 484, x4)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb503, 0x3, x2, 488, x4)
+
+inst_138:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0xb505, x2, 492, x4)
+
+inst_139:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, -0xb503, x2, 496, x4)
+
+inst_140:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x2, 500, x4)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x33333334, x2, 504, x4)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x6, x2, 508, x4)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, -0x55555555, x2, 512, x4)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x55555556, x2, 516, x4)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x4, x2, 520, x4)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0xb503, x2, 524, x4)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x0, x2, 528, x4)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x66666665, x2, 532, x4)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x33333332, x2, 536, x4)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x55555554, x2, 540, x4)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x2, x2, 544, x4)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0xb504, x2, 548, x4)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, -0xb504, x2, 552, x4)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x66666666, x2, 556, x4)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x33333333, x2, 560, x4)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x5, x2, 564, x4)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, -0x55555556, x2, 568, x4)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x55555555, x2, 572, x4)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666667, 0x3, x2, 576, x4)
+
+inst_160:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0xb505, x2, 580, x4)
+
+inst_161:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, -0xb503, x2, 584, x4)
+
+inst_162:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x66666667, x2, 588, x4)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x2, 592, x4)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x6, x2, 596, x4)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, -0x55555555, x2, 600, x4)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x55555556, x2, 604, x4)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x4, x2, 608, x4)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0xb503, x2, 612, x4)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x0, x2, 616, x4)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x66666665, x2, 620, x4)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x33333332, x2, 624, x4)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x55555554, x2, 628, x4)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x2, x2, 632, x4)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0xb504, x2, 636, x4)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, -0xb504, x2, 640, x4)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x66666666, x2, 644, x4)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x33333333, x2, 648, x4)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x5, x2, 652, x4)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, -0x55555556, x2, 656, x4)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333334, 0x55555555, x2, 660, x4)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333334, 0x3, x2, 664, x4)
+
+inst_182:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0xb505, x2, 668, x4)
+
+inst_183:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, -0xb503, x2, 672, x4)
+
+inst_184:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x66666667, x2, 676, x4)
+
+inst_185:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x33333334, x2, 680, x4)
+
+inst_186:
+// rs1_val==6 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x6, x2, 684, x4)
+
+inst_187:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, -0x55555555, x2, 688, x4)
+
+inst_188:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x55555556, x2, 692, x4)
+
+inst_189:
+// rs1_val==6 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x4, x2, 696, x4)
+
+inst_190:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0xb503, x2, 700, x4)
+
+inst_191:
+// rs1_val==6 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x0, x2, 704, x4)
+
+inst_192:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x66666665, x2, 708, x4)
+
+inst_193:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x33333332, x2, 712, x4)
+
+inst_194:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x55555554, x2, 716, x4)
+
+inst_195:
+// rs1_val==6 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x2, x2, 720, x4)
+
+inst_196:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0xb504, x2, 724, x4)
+
+inst_197:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, -0xb504, x2, 728, x4)
+
+inst_198:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x66666666, x2, 732, x4)
+
+inst_199:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x33333333, x2, 736, x4)
+
+inst_200:
+// rs1_val==6 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x5, x2, 740, x4)
+
+inst_201:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, -0x55555556, x2, 744, x4)
+
+inst_202:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x6, 0x55555555, x2, 748, x4)
+
+inst_203:
+// rs1_val==6 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x6, 0x3, x2, 752, x4)
+
+inst_204:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0xb505, x2, 756, x4)
+
+inst_205:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, -0xb503, x2, 760, x4)
+
+inst_206:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x66666667, x2, 764, x4)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x33333334, x2, 768, x4)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x6, x2, 772, x4)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x55555555, -0x55555555, x2, 776, x4)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x55555556, x2, 780, x4)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x4, x2, 784, x4)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0xb503, x2, 788, x4)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x0, x2, 792, x4)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x66666665, x2, 796, x4)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x33333332, x2, 800, x4)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x55555554, x2, 804, x4)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x2, x2, 808, x4)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0xb504, x2, 812, x4)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, -0xb504, x2, 816, x4)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x66666666, x2, 820, x4)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x33333333, x2, 824, x4)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x5, x2, 828, x4)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x55555555, -0x55555556, x2, 832, x4)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x55555555, x2, 836, x4)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, 0x3, x2, 840, x4)
+
+inst_226:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0xb505, x2, 844, x4)
+
+inst_227:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, -0xb503, x2, 848, x4)
+
+inst_228:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555556, 0x66666667, x2, 852, x4)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x33333334, x2, 856, x4)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x6, x2, 860, x4)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, -0x55555555, x2, 864, x4)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x2, 868, x4)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x4, x2, 872, x4)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0xb503, x2, 876, x4)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x0, x2, 880, x4)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555556, 0x66666665, x2, 884, x4)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x33333332, x2, 888, x4)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x55555554, x2, 892, x4)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x2, x2, 896, x4)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0xb504, x2, 900, x4)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, -0xb504, x2, 904, x4)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555556, 0x66666666, x2, 908, x4)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x33333333, x2, 912, x4)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x5, x2, 916, x4)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, -0x55555556, x2, 920, x4)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x55555555, x2, 924, x4)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555556, 0x3, x2, 928, x4)
+
+inst_248:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0xb505, x2, 932, x4)
+
+inst_249:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, -0xb503, x2, 936, x4)
+
+inst_250:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x66666667, x2, 940, x4)
+
+inst_251:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x33333334, x2, 944, x4)
+
+inst_252:
+// rs1_val==4 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x6, x2, 948, x4)
+
+inst_253:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, -0x55555555, x2, 952, x4)
+
+inst_254:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x55555556, x2, 956, x4)
+
+inst_255:
+// rs1_val==4 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, 0x4, x2, 960, x4)
+
+inst_256:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0xb503, x2, 964, x4)
+
+inst_257:
+// rs1_val==4 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, 0x0, x2, 968, x4)
+
+inst_258:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x66666665, x2, 972, x4)
+
+inst_259:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x33333332, x2, 976, x4)
+
+inst_260:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x55555554, x2, 980, x4)
+
+inst_261:
+// rs1_val==4 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, 0x2, x2, 984, x4)
+
+inst_262:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0xb504, x2, 988, x4)
+
+inst_263:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, -0xb504, x2, 992, x4)
+
+inst_264:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x66666666, x2, 996, x4)
+
+inst_265:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x33333333, x2, 1000, x4)
+
+inst_266:
+// rs1_val==4 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x5, x2, 1004, x4)
+
+inst_267:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, -0x55555556, x2, 1008, x4)
+
+inst_268:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x4, 0x55555555, x2, 1012, x4)
+
+inst_269:
+// rs1_val==4 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x4, 0x3, x2, 1016, x4)
+
+inst_270:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0xb505, x2, 1020, x4)
+
+inst_271:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, -0xb503, x2, 1024, x4)
+
+inst_272:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x66666667, x2, 1028, x4)
+
+inst_273:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x33333334, x2, 1032, x4)
+
+inst_274:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x6, x2, 1036, x4)
+
+inst_275:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, -0x55555555, x2, 1040, x4)
+
+inst_276:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x55555556, x2, 1044, x4)
+
+inst_277:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x4, x2, 1048, x4)
+
+inst_278:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0xb503, x2, 1052, x4)
+
+inst_279:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x0, x2, 1056, x4)
+
+inst_280:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x66666665, x2, 1060, x4)
+
+inst_281:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x33333332, x2, 1064, x4)
+
+inst_282:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x55555554, x2, 1068, x4)
+
+inst_283:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x2, x2, 1072, x4)
+
+inst_284:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0xb504, x2, 1076, x4)
+
+inst_285:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, -0xb504, x2, 1080, x4)
+
+inst_286:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x66666666, x2, 1084, x4)
+
+inst_287:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x33333333, x2, 1088, x4)
+
+inst_288:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x5, x2, 1092, x4)
+
+inst_289:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, -0x55555556, x2, 1096, x4)
+
+inst_290:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb503, 0x55555555, x2, 1100, x4)
+
+inst_291:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb503, 0x3, x2, 1104, x4)
+
+inst_292:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0xb505, x2, 1108, x4)
+
+inst_293:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x0, -0xb503, x2, 1112, x4)
+
+inst_294:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x66666667, x2, 1116, x4)
+
+inst_295:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x33333334, x2, 1120, x4)
+
+inst_296:
+// rs1_val==0 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x6, x2, 1124, x4)
+
+inst_297:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x0, -0x55555555, x2, 1128, x4)
+
+inst_298:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x55555556, x2, 1132, x4)
+
+inst_299:
+// rs1_val==0 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x4, x2, 1136, x4)
+
+inst_300:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0xb503, x2, 1140, x4)
+
+inst_301:
+// rs1_val==0 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x0, 0x0, x2, 1144, x4)
+
+inst_302:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x66666665, x2, 1148, x4)
+
+inst_303:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x33333332, x2, 1152, x4)
+
+inst_304:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x55555554, x2, 1156, x4)
+
+inst_305:
+// rs1_val==0 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x2, x2, 1160, x4)
+
+inst_306:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0xb504, x2, 1164, x4)
+
+inst_307:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x0, -0xb504, x2, 1168, x4)
+
+inst_308:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x66666666, x2, 1172, x4)
+
+inst_309:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x33333333, x2, 1176, x4)
+
+inst_310:
+// rs1_val==0 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x5, x2, 1180, x4)
+
+inst_311:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x0, -0x55555556, x2, 1184, x4)
+
+inst_312:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x55555555, x2, 1188, x4)
+
+inst_313:
+// rs1_val==0 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x0, 0x3, x2, 1192, x4)
+
+inst_314:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0xb505, x2, 1196, x4)
+
+inst_315:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, -0xb503, x2, 1200, x4)
+
+inst_316:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x66666665, 0x66666667, x2, 1204, x4)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x33333334, x2, 1208, x4)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x6, x2, 1212, x4)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, -0x55555555, x2, 1216, x4)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x55555556, x2, 1220, x4)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x4, x2, 1224, x4)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0xb503, x2, 1228, x4)
+
+inst_323:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x0, x2, 1232, x4)
+
+inst_324:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x66666665, x2, 1236, x4)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x33333332, x2, 1240, x4)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x55555554, x2, 1244, x4)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x2, x2, 1248, x4)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0xb504, x2, 1252, x4)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, -0xb504, x2, 1256, x4)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x66666666, x2, 1260, x4)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x2, 1264, x4)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x5, x2, 1268, x4)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, -0x55555556, x2, 1272, x4)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x55555555, x2, 1276, x4)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x3, x2, 1280, x4)
+
+inst_336:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0xb505, x2, 1284, x4)
+
+inst_337:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, -0xb503, x2, 1288, x4)
+
+inst_338:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x66666667, x2, 1292, x4)
+
+inst_339:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x33333334, x2, 1296, x4)
+
+inst_340:
+// rs1_val==5 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x6, x2, 1300, x4)
+
+inst_341:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, -0x55555555, x2, 1304, x4)
+
+inst_342:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x55555556, x2, 1308, x4)
+
+inst_343:
+// rs1_val==5 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, 0x4, x2, 1312, x4)
+
+inst_344:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0xb503, x2, 1316, x4)
+
+inst_345:
+// rs1_val==5 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, 0x0, x2, 1320, x4)
+
+inst_346:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x66666665, x2, 1324, x4)
+
+inst_347:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x33333332, x2, 1328, x4)
+
+inst_348:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x55555554, x2, 1332, x4)
+
+inst_349:
+// rs1_val==5 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, 0x2, x2, 1336, x4)
+
+inst_350:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0xb504, x2, 1340, x4)
+
+inst_351:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, -0xb504, x2, 1344, x4)
+
+inst_352:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x66666666, x2, 1348, x4)
+
+inst_353:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x33333333, x2, 1352, x4)
+
+inst_354:
+// rs1_val==5 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, 0x5, x2, 1356, x4)
+
+inst_355:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, -0x55555556, x2, 1360, x4)
+
+inst_356:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x5, 0x55555555, x2, 1364, x4)
+
+inst_357:
+// rs1_val==5 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x5, 0x3, x2, 1368, x4)
+
+inst_358:
+// rs1_val==-1431655766 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0xb505, x2, 1372, x4)
+
+inst_359:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, -0xb503, x2, 1376, x4)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x66666667, x2, 1380, x4)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x33333334, x2, 1384, x4)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x6, x2, 1388, x4)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, -0x55555555, x2, 1392, x4)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x55555556, x2, 1396, x4)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x4, x2, 1400, x4)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0xb503, x2, 1404, x4)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x0, x2, 1408, x4)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x66666665, x2, 1412, x4)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x33333332, x2, 1416, x4)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x55555554, x2, 1420, x4)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x2, x2, 1424, x4)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0xb504, x2, 1428, x4)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, -0xb504, x2, 1432, x4)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x66666666, x2, 1436, x4)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x33333333, x2, 1440, x4)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x5, x2, 1444, x4)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x55555556, -0x55555556, x2, 1448, x4)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x55555555, x2, 1452, x4)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555556, 0x3, x2, 1456, x4)
+
+inst_380:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0xb505, x2, 1460, x4)
+
+inst_381:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, -0xb503, x2, 1464, x4)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555555, 0x66666667, x2, 1468, x4)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x33333334, x2, 1472, x4)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x6, x2, 1476, x4)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, -0x55555555, x2, 1480, x4)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555555, 0x55555556, x2, 1484, x4)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x4, x2, 1488, x4)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0xb503, x2, 1492, x4)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x0, x2, 1496, x4)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555555, 0x66666665, x2, 1500, x4)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x33333332, x2, 1504, x4)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x55555554, x2, 1508, x4)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x2, x2, 1512, x4)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0xb504, x2, 1516, x4)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, -0xb504, x2, 1520, x4)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555555, 0x66666666, x2, 1524, x4)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x33333333, x2, 1528, x4)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x5, x2, 1532, x4)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, -0x55555556, x2, 1536, x4)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x2, 1540, x4)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555555, 0x3, x2, 1544, x4)
+
+inst_402:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0xb505, x2, 1548, x4)
+
+inst_403:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, -0xb503, x2, 1552, x4)
+
+inst_404:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x66666667, x2, 1556, x4)
+
+inst_405:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x33333334, x2, 1560, x4)
+
+inst_406:
+// rs1_val==3 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x6, x2, 1564, x4)
+
+inst_407:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, -0x55555555, x2, 1568, x4)
+
+inst_408:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x55555556, x2, 1572, x4)
+
+inst_409:
+// rs1_val==3 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x4, x2, 1576, x4)
+
+inst_410:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0xb503, x2, 1580, x4)
+
+inst_411:
+// rs1_val==3 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, 0x0, x2, 1584, x4)
+
+inst_412:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x66666665, x2, 1588, x4)
+
+inst_413:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x33333332, x2, 1592, x4)
+
+inst_414:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x55555554, x2, 1596, x4)
+
+inst_415:
+// rs1_val==3 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, 0x2, x2, 1600, x4)
+
+inst_416:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0xb504, x2, 1604, x4)
+
+inst_417:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, -0xb504, x2, 1608, x4)
+
+inst_418:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x66666666, x2, 1612, x4)
+
+inst_419:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x33333333, x2, 1616, x4)
+
+inst_420:
+// rs1_val==3 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x5, x2, 1620, x4)
+
+inst_421:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, -0x55555556, x2, 1624, x4)
+
+inst_422:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x3, 0x55555555, x2, 1628, x4)
+
+inst_423:
+// rs1_val==3 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x3, 0x3, x2, 1632, x4)
+
+inst_424:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x0, x2, 1636, x4)
+
+inst_425:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x2, 1640, x4)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x33333332, x2, 1644, x4)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x55555554, x2, 1648, x4)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x2, x2, 1652, x4)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0xb504, x2, 1656, x4)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, -0xb504, x2, 1660, x4)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x66666665, 0x66666666, x2, 1664, x4)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x33333333, x2, 1668, x4)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x5, x2, 1672, x4)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, -0x55555556, x2, 1676, x4)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x55555555, x2, 1680, x4)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666665, 0x3, x2, 1684, x4)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0xb505, x2, 1688, x4)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, -0xb503, x2, 1692, x4)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x66666667, x2, 1696, x4)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x33333334, x2, 1700, x4)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x6, x2, 1704, x4)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, -0x55555555, x2, 1708, x4)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x55555556, x2, 1712, x4)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x4, x2, 1716, x4)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0xb503, x2, 1720, x4)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x0, x2, 1724, x4)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x66666665, x2, 1728, x4)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x2, 1732, x4)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x55555554, x2, 1736, x4)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x2, x2, 1740, x4)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0xb504, x2, 1744, x4)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, -0xb504, x2, 1748, x4)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x66666666, x2, 1752, x4)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x33333333, x2, 1756, x4)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x5, x2, 1760, x4)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, -0x55555556, x2, 1764, x4)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333332, 0x55555555, x2, 1768, x4)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333332, 0x3, x2, 1772, x4)
+
+inst_459:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0xb505, x2, 1776, x4)
+
+inst_460:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, -0xb503, x2, 1780, x4)
+
+inst_461:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555554, 0x66666667, x2, 1784, x4)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x33333334, x2, 1788, x4)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x6, x2, 1792, x4)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, -0x55555555, x2, 1796, x4)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555554, 0x55555556, x2, 1800, x4)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x4, x2, 1804, x4)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0xb503, x2, 1808, x4)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x0, x2, 1812, x4)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555554, 0x66666665, x2, 1816, x4)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x33333332, x2, 1820, x4)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x2, 1824, x4)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x2, x2, 1828, x4)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0xb504, x2, 1832, x4)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, -0xb504, x2, 1836, x4)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555554, 0x66666666, x2, 1840, x4)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x33333333, x2, 1844, x4)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x5, x2, 1848, x4)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, -0x55555556, x2, 1852, x4)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x55555554, 0x55555555, x2, 1856, x4)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x55555554, 0x3, x2, 1860, x4)
+
+inst_481:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0xb505, x2, 1864, x4)
+
+inst_482:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, -0xb503, x2, 1868, x4)
+
+inst_483:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x66666667, x2, 1872, x4)
+
+inst_484:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x33333334, x2, 1876, x4)
+
+inst_485:
+// rs1_val==2 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x6, x2, 1880, x4)
+
+inst_486:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, -0x55555555, x2, 1884, x4)
+
+inst_487:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x55555556, x2, 1888, x4)
+
+inst_488:
+// rs1_val==2 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x4, x2, 1892, x4)
+
+inst_489:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0xb503, x2, 1896, x4)
+
+inst_490:
+// rs1_val==2 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, 0x0, x2, 1900, x4)
+
+inst_491:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x66666665, x2, 1904, x4)
+
+inst_492:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x33333332, x2, 1908, x4)
+
+inst_493:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x55555554, x2, 1912, x4)
+
+inst_494:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0xb504, x2, 1916, x4)
+
+inst_495:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, -0xb504, x2, 1920, x4)
+
+inst_496:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x66666666, x2, 1924, x4)
+
+inst_497:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x33333333, x2, 1928, x4)
+
+inst_498:
+// rs1_val==2 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x5, x2, 1932, x4)
+
+inst_499:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x2, -0x55555556, x2, 1936, x4)
+
+inst_500:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x55555555, x2, 1940, x4)
+
+inst_501:
+// rs1_val==2 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x2, 0x3, x2, 1944, x4)
+
+inst_502:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0xb505, x2, 1948, x4)
+
+inst_503:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, -0xb503, x2, 1952, x4)
+
+inst_504:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x66666667, x2, 1956, x4)
+
+inst_505:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x33333334, x2, 1960, x4)
+
+inst_506:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x6, x2, 1964, x4)
+
+inst_507:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, -0x55555555, x2, 1968, x4)
+
+inst_508:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x55555556, x2, 1972, x4)
+
+inst_509:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x4, x2, 1976, x4)
+
+inst_510:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0xb503, x2, 1980, x4)
+
+inst_511:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x0, x2, 1984, x4)
+
+inst_512:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x66666665, x2, 1988, x4)
+
+inst_513:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x33333332, x2, 1992, x4)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x55555554, x2, 1996, x4)
+
+inst_515:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x2, x2, 2000, x4)
+
+inst_516:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0xb504, x2, 2004, x4)
+
+inst_517:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, -0xb504, x2, 2008, x4)
+
+inst_518:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x66666666, x2, 2012, x4)
+
+inst_519:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x33333333, x2, 2016, x4)
+
+inst_520:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x5, x2, 2020, x4)
+
+inst_521:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, -0x55555556, x2, 2024, x4)
+
+inst_522:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0xb504, 0x55555555, x2, 2028, x4)
+
+inst_523:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0xb504, 0x3, x2, 2032, x4)
+
+inst_524:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0xb505, x2, 2036, x4)
+
+inst_525:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, -0xb503, x2, 2040, x4)
+
+inst_526:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x66666667, x2, 2044, x4)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x33333334, x2, 0, x4)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x6, x2, 4, x4)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb504, -0x55555555, x2, 8, x4)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x55555556, x2, 12, x4)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x4, x2, 16, x4)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0xb503, x2, 20, x4)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x0, x2, 24, x4)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x66666665, x2, 28, x4)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x33333332, x2, 32, x4)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x55555554, x2, 36, x4)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x2, x2, 40, x4)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0xb504, x2, 44, x4)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb504, -0xb504, x2, 48, x4)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x66666666, x2, 52, x4)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x33333333, x2, 56, x4)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x5, x2, 60, x4)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0xb504, -0x55555556, x2, 64, x4)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x55555555, x2, 68, x4)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0xb504, 0x3, x2, 72, x4)
+
+inst_546:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0xb505, x2, 76, x4)
+
+inst_547:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, -0xb503, x2, 80, x4)
+
+inst_548:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x66666666, 0x66666667, x2, 84, x4)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x33333334, x2, 88, x4)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x6, x2, 92, x4)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, -0x55555555, x2, 96, x4)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x55555556, x2, 100, x4)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x4, x2, 104, x4)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0xb503, x2, 108, x4)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x0, x2, 112, x4)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x66666665, x2, 116, x4)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x33333332, x2, 120, x4)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x55555554, x2, 124, x4)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x2, x2, 128, x4)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0xb504, x2, 132, x4)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, -0xb504, x2, 136, x4)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x2, 140, x4)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x33333333, x2, 144, x4)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x5, x2, 148, x4)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, -0x55555556, x2, 152, x4)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x55555555, x2, 156, x4)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x66666666, 0x3, x2, 160, x4)
+
+inst_568:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0xb505, x2, 164, x4)
+
+inst_569:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, -0xb503, x2, 168, x4)
+
+inst_570:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x66666667, x2, 172, x4)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x33333334, x2, 176, x4)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x6, x2, 180, x4)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, -0x55555555, x2, 184, x4)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(slt, x12, x10, x11, 0x1, 0x33333333, 0x55555556, x2, 188, x4)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0x4, x2, 192, x4)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(slt, x12, x10, x11, 0x0, 0x33333333, 0xb503, x2, 196, x4)
+
+inst_577:
+// rs2_val == 2147483647, rs1_val == -4194305, rs1_val < 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x7fffffff
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x400001, 0x7fffffff, x2, 200, x4)
+
+inst_578:
+// rs2_val == -536870913, rs1_val == -4097
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:-0x20000001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x1001, -0x20000001, x2, 204, x4)
+
+inst_579:
+// rs2_val == -268435457, 
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x10000001
+TEST_RR_OP(slt, x12, x10, x11, 0x1, -0x55555555, -0x10000001, x2, 208, x4)
+
+inst_580:
+// rs2_val == -134217729, rs1_val == -65537
+// opcode: slt ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x8000001
+TEST_RR_OP(slt, x12, x10, x11, 0x0, -0x10001, -0x8000001, x2, 212, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x12_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x12_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 54*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S
new file mode 100644
index 000000000..c0a3feccd
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S
@@ -0,0 +1,2891 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the slti instruction of the RISC-V E extension for the slti covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",slti)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x3, rd==x11, imm_val == (-2**(12-1)), rs1_val > 0 and imm_val < 0, rs1_val != imm_val, rs1_val == 512, imm_val == -2048
+// opcode: slti ; op1:x3; dest:x11; op1val:0x200;  immval:-0x800
+TEST_IMM_OP( slti, x11, x3, 0x0, 0x200, -0x800, x4, 0, x8)
+
+inst_1:
+// rs1 == rd, rs1==x7, rd==x7, rs1_val == 2147483647, rs1_val > 0 and imm_val > 0, rs1_val == (2**(xlen-1)-1)
+// opcode: slti ; op1:x7; dest:x7; op1val:0x7fffffff;  immval:0x665
+TEST_IMM_OP( slti, x7, x7, 0x0, 0x7fffffff, 0x665, x4, 4, x8)
+
+inst_2:
+// rs1==x13, rd==x3, rs1_val == -1073741825, rs1_val < 0 and imm_val < 0
+// opcode: slti ; op1:x13; dest:x3; op1val:-0x40000001;  immval:-0x800
+TEST_IMM_OP( slti, x3, x13, 0x1, -0x40000001, -0x800, x4, 8, x8)
+
+inst_3:
+// rs1==x0, rd==x14, rs1_val == -536870913, 
+// opcode: slti ; op1:x0; dest:x14; op1val:0x0;  immval:-0x6
+TEST_IMM_OP( slti, x14, x0, 0x0, 0x0, -0x6, x4, 12, x8)
+
+inst_4:
+// rs1==x15, rd==x10, rs1_val == -268435457, imm_val == -513
+// opcode: slti ; op1:x15; dest:x10; op1val:-0x10000001;  immval:-0x201
+TEST_IMM_OP( slti, x10, x15, 0x1, -0x10000001, -0x201, x4, 16, x8)
+
+inst_5:
+// rs1==x6, rd==x5, rs1_val == -134217729, rs1_val < 0 and imm_val > 0, imm_val == 2
+// opcode: slti ; op1:x6; dest:x5; op1val:-0x8000001;  immval:0x2
+TEST_IMM_OP( slti, x5, x6, 0x1, -0x8000001, 0x2, x4, 20, x8)
+
+inst_6:
+// rs1==x12, rd==x13, rs1_val == -67108865, imm_val == 1024
+// opcode: slti ; op1:x12; dest:x13; op1val:-0x4000001;  immval:0x400
+TEST_IMM_OP( slti, x13, x12, 0x1, -0x4000001, 0x400, x4, 24, x8)
+
+inst_7:
+// rs1==x2, rd==x1, rs1_val == -33554433, 
+// opcode: slti ; op1:x2; dest:x1; op1val:-0x2000001;  immval:-0x6
+TEST_IMM_OP( slti, x1, x2, 0x1, -0x2000001, -0x6, x4, 28, x8)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_8:
+// rs1==x9, rd==x6, rs1_val == -16777217, 
+// opcode: slti ; op1:x9; dest:x6; op1val:-0x1000001;  immval:0x7
+TEST_IMM_OP( slti, x6, x9, 0x1, -0x1000001, 0x7, x3, 0, x7)
+
+inst_9:
+// rs1==x8, rd==x4, rs1_val == -8388609, imm_val == 512
+// opcode: slti ; op1:x8; dest:x4; op1val:-0x800001;  immval:0x200
+TEST_IMM_OP( slti, x4, x8, 0x1, -0x800001, 0x200, x3, 4, x7)
+
+inst_10:
+// rs1==x10, rd==x0, rs1_val == -4194305, 
+// opcode: slti ; op1:x10; dest:x0; op1val:-0x400001;  immval:0x2d
+TEST_IMM_OP( slti, x0, x10, 0, -0x400001, 0x2d, x3, 8, x7)
+
+inst_11:
+// rs1==x1, rd==x2, rs1_val == -2097153, 
+// opcode: slti ; op1:x1; dest:x2; op1val:-0x200001;  immval:0x665
+TEST_IMM_OP( slti, x2, x1, 0x1, -0x200001, 0x665, x3, 12, x7)
+
+inst_12:
+// rs1==x14, rd==x8, rs1_val == -1048577, imm_val == 4
+// opcode: slti ; op1:x14; dest:x8; op1val:-0x100001;  immval:0x4
+TEST_IMM_OP( slti, x8, x14, 0x1, -0x100001, 0x4, x3, 16, x7)
+
+inst_13:
+// rs1==x5, rd==x12, rs1_val == -524289, imm_val == -1366
+// opcode: slti ; op1:x5; dest:x12; op1val:-0x80001;  immval:-0x556
+TEST_IMM_OP( slti, x12, x5, 0x1, -0x80001, -0x556, x3, 20, x7)
+
+inst_14:
+// rs1==x4, rd==x9, rs1_val == -262145, imm_val == 1
+// opcode: slti ; op1:x4; dest:x9; op1val:-0x40001;  immval:0x1
+TEST_IMM_OP( slti, x9, x4, 0x1, -0x40001, 0x1, x3, 24, x7)
+
+inst_15:
+// rs1==x11, rd==x15, rs1_val == -131073, 
+// opcode: slti ; op1:x11; dest:x15; op1val:-0x20001;  immval:0x4
+TEST_IMM_OP( slti, x15, x11, 0x1, -0x20001, 0x4, x3, 28, x7)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_16:
+// rs1_val == -65537, imm_val == 32
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x10001;  immval:0x20
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x10001, 0x20, x1, 0, x2)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x8001, 0x554, x1, 4, x2)
+
+inst_18:
+// rs1_val == -16385, imm_val == -1025
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x4001;  immval:-0x401
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x4001, -0x401, x1, 8, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x2001, 0x2c, x1, 12, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x1001, -0x6, x1, 16, x2)
+
+inst_21:
+// rs1_val == -2049, imm_val == 0
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x801;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x801, 0x0, x1, 20, x2)
+
+inst_22:
+// rs1_val == -1025, rs1_val == imm_val
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x401;  immval:-0x401
+TEST_IMM_OP( slti, x11, x10, 0x0, -0x401, -0x401, x1, 24, x2)
+
+inst_23:
+// rs1_val == -513, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x201;  immval:-0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x201, -0x6, x1, 28, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x101;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x101, 0x3, x1, 32, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x81;  immval:0x200
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x81, 0x200, x1, 36, x2)
+
+inst_26:
+// rs1_val == -65, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x41;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x41, -0x2c, x1, 40, x2)
+
+inst_27:
+// rs1_val == -33, imm_val == 8
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x21;  immval:0x8
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x21, 0x8, x1, 44, x2)
+
+inst_28:
+// rs1_val == -17, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x11;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x11, 0x332, x1, 48, x2)
+
+inst_29:
+// rs1_val == -9, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x9;  immval:0x3ff
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x9, 0x3ff, x1, 52, x2)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x5;  immval:0x400
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x5, 0x400, x1, 56, x2)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x3;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x3, 0x2, x1, 60, x2)
+
+inst_32:
+// rs1_val == -2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x2;  immval:-0xa
+TEST_IMM_OP( slti, x11, x10, 0x0, -0x2, -0xa, x1, 64, x2)
+
+inst_33:
+// imm_val == 2047, imm_val == (2**(12-1)-1)
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x7ff
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x7ff, x1, 68, x2)
+
+inst_34:
+// imm_val == -257, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x400001;  immval:-0x101
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x400001, -0x101, x1, 72, x2)
+
+inst_35:
+// imm_val == -129, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x4;  immval:-0x81
+TEST_IMM_OP( slti, x11, x10, 0x0, -0x4, -0x81, x1, 76, x2)
+
+inst_36:
+// imm_val == -65, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x7fffffff;  immval:-0x41
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x7fffffff, -0x41, x1, 80, x2)
+
+inst_37:
+// imm_val == -33, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x7;  immval:-0x21
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x7, -0x21, x1, 84, x2)
+
+inst_38:
+// imm_val == -17, rs1_val == 32
+// opcode: slti ; op1:x10; dest:x11; op1val:0x20;  immval:-0x11
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x20, -0x11, x1, 88, x2)
+
+inst_39:
+// imm_val == -9, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x2000001;  immval:-0x9
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x2000001, -0x9, x1, 92, x2)
+
+inst_40:
+// imm_val == -5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x401;  immval:-0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x401, -0x5, x1, 96, x2)
+
+inst_41:
+// imm_val == -3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, -0x3, x1, 100, x2)
+
+inst_42:
+// imm_val == -2, rs1_val == 0
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, -0x2, x1, 104, x2)
+
+inst_43:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x80000000, 0x667, x1, 108, x2)
+
+inst_44:
+// rs1_val == 1073741824, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x9
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x40000000, 0x9, x1, 112, x2)
+
+inst_45:
+// rs1_val == 536870912, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x20000000;  immval:-0x8
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x20000000, -0x8, x1, 116, x2)
+
+inst_46:
+// rs1_val == 268435456, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x7
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x10000000, 0x7, x1, 120, x2)
+
+inst_47:
+// rs1_val == 134217728, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x8000000;  immval:-0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x8000000, -0x4, x1, 124, x2)
+
+inst_48:
+// rs1_val == 67108864, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4000000, 0x2e, x1, 128, x2)
+
+inst_49:
+// rs1_val == 33554432, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2000000, 0x556, x1, 132, x2)
+
+inst_50:
+// rs1_val == 16777216, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x1000000;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x1000000, -0x556, x1, 136, x2)
+
+inst_51:
+// rs1_val == 8388608, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x800000;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x800000, 0x4, x1, 140, x2)
+
+inst_52:
+// rs1_val == 4194304, imm_val == 1365
+// opcode: slti ; op1:x10; dest:x11; op1val:0x400000;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x400000, 0x555, x1, 144, x2)
+
+inst_53:
+// rs1_val == 2097152, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x200000;  immval:-0x400
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x200000, -0x400, x1, 148, x2)
+
+inst_54:
+// rs1_val == 1048576, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x100000;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x100000, 0x2c, x1, 152, x2)
+
+inst_55:
+// rs1_val == 524288, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x80000;  immval:-0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x80000, -0x4, x1, 156, x2)
+
+inst_56:
+// rs1_val == 262144, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x40000;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x40000, 0x2, x1, 160, x2)
+
+inst_57:
+// rs1_val == 131072, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x20000;  immval:0x400
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x20000, 0x400, x1, 164, x2)
+
+inst_58:
+// rs1_val == 65536, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x10000;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x10000, -0x2c, x1, 168, x2)
+
+inst_59:
+// rs1_val == 32768, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x8000;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x8000, 0x6, x1, 172, x2)
+
+inst_60:
+// rs1_val == 16384, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4000;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4000, 0x0, x1, 176, x2)
+
+inst_61:
+// rs1_val == 8192, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2000;  immval:0x200
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2000, 0x200, x1, 180, x2)
+
+inst_62:
+// rs1_val == 4096, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x1000;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x1000, 0x3, x1, 184, x2)
+
+inst_63:
+// rs1_val == 2048, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x800;  immval:-0x81
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x800, -0x81, x1, 188, x2)
+
+inst_64:
+// rs1_val == 1024, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x400;  immval:-0xa
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x400, -0xa, x1, 192, x2)
+
+inst_65:
+// rs1_val == 256, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x100;  immval:0x3ff
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x100, 0x3ff, x1, 196, x2)
+
+inst_66:
+// rs1_val == 128, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x80;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x80, 0x4, x1, 200, x2)
+
+inst_67:
+// rs1_val == 64, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x40;  immval:-0x400
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x40, -0x400, x1, 204, x2)
+
+inst_68:
+// rs1_val == 16, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x10;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x10, 0x2e, x1, 208, x2)
+
+inst_69:
+// rs1_val == 8, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x8;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x8, 0x3, x1, 212, x2)
+
+inst_70:
+// rs1_val == 4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:-0xa
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, -0xa, x1, 216, x2)
+
+inst_71:
+// rs1_val == 2, rs1_val==2 and imm_val==45
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x2d, x1, 220, x2)
+
+inst_72:
+// rs1_val == 1, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x1;  immval:-0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x1, -0x3, x1, 224, x2)
+
+inst_73:
+// imm_val == 256, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x100
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x100, x1, 228, x2)
+
+inst_74:
+// imm_val == 128, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x80
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x80, x1, 232, x2)
+
+inst_75:
+// imm_val == 64, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x40
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4000000, 0x40, x1, 236, x2)
+
+inst_76:
+// imm_val == 16, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x3;  immval:0x10
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x3, 0x10, x1, 240, x2)
+
+inst_77:
+// rs1_val==46341 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x2e, x1, 244, x2)
+
+inst_78:
+// rs1_val==46341 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, -0x2c, x1, 248, x2)
+
+inst_79:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x667, x1, 252, x2)
+
+inst_80:
+// rs1_val==46341 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x334, x1, 256, x2)
+
+inst_81:
+// rs1_val==46341 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x6, x1, 260, x2)
+
+inst_82:
+// rs1_val==46341 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, -0x555, x1, 264, x2)
+
+inst_83:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x556, x1, 268, x2)
+
+inst_84:
+// rs1_val==46341 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x4, x1, 272, x2)
+
+inst_85:
+// rs1_val==46341 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x2c, x1, 276, x2)
+
+inst_86:
+// rs1_val==46341 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x0, x1, 280, x2)
+
+inst_87:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x665, x1, 284, x2)
+
+inst_88:
+// rs1_val==46341 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x332, x1, 288, x2)
+
+inst_89:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x554, x1, 292, x2)
+
+inst_90:
+// rs1_val==46341 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x2, x1, 296, x2)
+
+inst_91:
+// rs1_val==46341 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x2d, x1, 300, x2)
+
+inst_92:
+// rs1_val==46341 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, -0x2d, x1, 304, x2)
+
+inst_93:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x666, x1, 308, x2)
+
+inst_94:
+// rs1_val==46341 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x333, x1, 312, x2)
+
+inst_95:
+// rs1_val==46341 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x5, x1, 316, x2)
+
+inst_96:
+// rs1_val==46341 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, -0x556, x1, 320, x2)
+
+inst_97:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x555, x1, 324, x2)
+
+inst_98:
+// rs1_val==46341 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb505, 0x3, x1, 328, x2)
+
+inst_99:
+// rs1_val==-46339 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x2e, x1, 332, x2)
+
+inst_100:
+// rs1_val==-46339 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, -0x2c, x1, 336, x2)
+
+inst_101:
+// rs1_val==-46339 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x667, x1, 340, x2)
+
+inst_102:
+// rs1_val==-46339 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x334, x1, 344, x2)
+
+inst_103:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x6, x1, 348, x2)
+
+inst_104:
+// rs1_val==-46339 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, -0x555, x1, 352, x2)
+
+inst_105:
+// rs1_val==-46339 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x556, x1, 356, x2)
+
+inst_106:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x4, x1, 360, x2)
+
+inst_107:
+// rs1_val==-46339 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x2c, x1, 364, x2)
+
+inst_108:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x0, x1, 368, x2)
+
+inst_109:
+// rs1_val==-46339 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x665, x1, 372, x2)
+
+inst_110:
+// rs1_val==-46339 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x332, x1, 376, x2)
+
+inst_111:
+// rs1_val==-46339 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x554, x1, 380, x2)
+
+inst_112:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x2, x1, 384, x2)
+
+inst_113:
+// rs1_val==-46339 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x2d, x1, 388, x2)
+
+inst_114:
+// rs1_val==-46339 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, -0x2d, x1, 392, x2)
+
+inst_115:
+// rs1_val==-46339 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x666, x1, 396, x2)
+
+inst_116:
+// rs1_val==-46339 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x333, x1, 400, x2)
+
+inst_117:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x5, x1, 404, x2)
+
+inst_118:
+// rs1_val==-46339 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, -0x556, x1, 408, x2)
+
+inst_119:
+// rs1_val==-46339 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x555, x1, 412, x2)
+
+inst_120:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb503, 0x3, x1, 416, x2)
+
+inst_121:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x2e, x1, 420, x2)
+
+inst_122:
+// rs1_val==1717986919 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, -0x2c, x1, 424, x2)
+
+inst_123:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x667, x1, 428, x2)
+
+inst_124:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x334, x1, 432, x2)
+
+inst_125:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x6, x1, 436, x2)
+
+inst_126:
+// rs1_val==1717986919 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, -0x555, x1, 440, x2)
+
+inst_127:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x556, x1, 444, x2)
+
+inst_128:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x4, x1, 448, x2)
+
+inst_129:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x2c, x1, 452, x2)
+
+inst_130:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x0, x1, 456, x2)
+
+inst_131:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x665, x1, 460, x2)
+
+inst_132:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x332, x1, 464, x2)
+
+inst_133:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x554, x1, 468, x2)
+
+inst_134:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x2, x1, 472, x2)
+
+inst_135:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x2d, x1, 476, x2)
+
+inst_136:
+// rs1_val==1717986919 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, -0x2d, x1, 480, x2)
+
+inst_137:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x666, x1, 484, x2)
+
+inst_138:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x333, x1, 488, x2)
+
+inst_139:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x5, x1, 492, x2)
+
+inst_140:
+// rs1_val==1717986919 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, -0x556, x1, 496, x2)
+
+inst_141:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x555, x1, 500, x2)
+
+inst_142:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666667, 0x3, x1, 504, x2)
+
+inst_143:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x2e, x1, 508, x2)
+
+inst_144:
+// rs1_val==858993460 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, -0x2c, x1, 512, x2)
+
+inst_145:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x667, x1, 516, x2)
+
+inst_146:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x334, x1, 520, x2)
+
+inst_147:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x6, x1, 524, x2)
+
+inst_148:
+// rs1_val==858993460 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, -0x555, x1, 528, x2)
+
+inst_149:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x556, x1, 532, x2)
+
+inst_150:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x4, x1, 536, x2)
+
+inst_151:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x2c, x1, 540, x2)
+
+inst_152:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x0, x1, 544, x2)
+
+inst_153:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x665, x1, 548, x2)
+
+inst_154:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x332, x1, 552, x2)
+
+inst_155:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x554, x1, 556, x2)
+
+inst_156:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x2, x1, 560, x2)
+
+inst_157:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x2d, x1, 564, x2)
+
+inst_158:
+// rs1_val==858993460 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, -0x2d, x1, 568, x2)
+
+inst_159:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x666, x1, 572, x2)
+
+inst_160:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x333, x1, 576, x2)
+
+inst_161:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x5, x1, 580, x2)
+
+inst_162:
+// rs1_val==858993460 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, -0x556, x1, 584, x2)
+
+inst_163:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x555, x1, 588, x2)
+
+inst_164:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333334, 0x3, x1, 592, x2)
+
+inst_165:
+// rs1_val==6 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x2e, x1, 596, x2)
+
+inst_166:
+// rs1_val==6 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, -0x2c, x1, 600, x2)
+
+inst_167:
+// rs1_val==6 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x667, x1, 604, x2)
+
+inst_168:
+// rs1_val==6 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x334, x1, 608, x2)
+
+inst_169:
+// rs1_val==6 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x6, x1, 612, x2)
+
+inst_170:
+// rs1_val==6 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, -0x555, x1, 616, x2)
+
+inst_171:
+// rs1_val==6 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x556, x1, 620, x2)
+
+inst_172:
+// rs1_val==6 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x4, x1, 624, x2)
+
+inst_173:
+// rs1_val==6 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x2c, x1, 628, x2)
+
+inst_174:
+// rs1_val==6 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x0, x1, 632, x2)
+
+inst_175:
+// rs1_val==6 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x665, x1, 636, x2)
+
+inst_176:
+// rs1_val==6 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x332, x1, 640, x2)
+
+inst_177:
+// rs1_val==6 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x554, x1, 644, x2)
+
+inst_178:
+// rs1_val==6 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x2, x1, 648, x2)
+
+inst_179:
+// rs1_val==6 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x2d, x1, 652, x2)
+
+inst_180:
+// rs1_val==6 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, -0x2d, x1, 656, x2)
+
+inst_181:
+// rs1_val==6 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x666, x1, 660, x2)
+
+inst_182:
+// rs1_val==6 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x333, x1, 664, x2)
+
+inst_183:
+// rs1_val==6 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x5, x1, 668, x2)
+
+inst_184:
+// rs1_val==6 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, -0x556, x1, 672, x2)
+
+inst_185:
+// rs1_val==6 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x6, 0x555, x1, 676, x2)
+
+inst_186:
+// rs1_val==6 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x6, 0x3, x1, 680, x2)
+
+inst_187:
+// rs1_val==-1431655765 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x2e, x1, 684, x2)
+
+inst_188:
+// rs1_val==-1431655765 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, -0x2c, x1, 688, x2)
+
+inst_189:
+// rs1_val==-1431655765 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x667, x1, 692, x2)
+
+inst_190:
+// rs1_val==-1431655765 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x334, x1, 696, x2)
+
+inst_191:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x6, x1, 700, x2)
+
+inst_192:
+// rs1_val==-1431655765 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, -0x555, x1, 704, x2)
+
+inst_193:
+// rs1_val==-1431655765 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x556, x1, 708, x2)
+
+inst_194:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x4, x1, 712, x2)
+
+inst_195:
+// rs1_val==-1431655765 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x2c, x1, 716, x2)
+
+inst_196:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x0, x1, 720, x2)
+
+inst_197:
+// rs1_val==-1431655765 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x665, x1, 724, x2)
+
+inst_198:
+// rs1_val==-1431655765 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x332, x1, 728, x2)
+
+inst_199:
+// rs1_val==-1431655765 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x554, x1, 732, x2)
+
+inst_200:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x2, x1, 736, x2)
+
+inst_201:
+// rs1_val==-1431655765 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x2d, x1, 740, x2)
+
+inst_202:
+// rs1_val==-1431655765 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, -0x2d, x1, 744, x2)
+
+inst_203:
+// rs1_val==-1431655765 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x666, x1, 748, x2)
+
+inst_204:
+// rs1_val==-1431655765 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x333, x1, 752, x2)
+
+inst_205:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x5, x1, 756, x2)
+
+inst_206:
+// rs1_val==-1431655765 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, -0x556, x1, 760, x2)
+
+inst_207:
+// rs1_val==-1431655765 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x555, x1, 764, x2)
+
+inst_208:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555555, 0x3, x1, 768, x2)
+
+inst_209:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x2e, x1, 772, x2)
+
+inst_210:
+// rs1_val==1431655766 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, -0x2c, x1, 776, x2)
+
+inst_211:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x667, x1, 780, x2)
+
+inst_212:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x334, x1, 784, x2)
+
+inst_213:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x6, x1, 788, x2)
+
+inst_214:
+// rs1_val==1431655766 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, -0x555, x1, 792, x2)
+
+inst_215:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x556, x1, 796, x2)
+
+inst_216:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x4, x1, 800, x2)
+
+inst_217:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x2c, x1, 804, x2)
+
+inst_218:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x0, x1, 808, x2)
+
+inst_219:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x665, x1, 812, x2)
+
+inst_220:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x332, x1, 816, x2)
+
+inst_221:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x554, x1, 820, x2)
+
+inst_222:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x2, x1, 824, x2)
+
+inst_223:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x2d, x1, 828, x2)
+
+inst_224:
+// rs1_val==1431655766 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, -0x2d, x1, 832, x2)
+
+inst_225:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x666, x1, 836, x2)
+
+inst_226:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x333, x1, 840, x2)
+
+inst_227:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x5, x1, 844, x2)
+
+inst_228:
+// rs1_val==1431655766 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, -0x556, x1, 848, x2)
+
+inst_229:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x555, x1, 852, x2)
+
+inst_230:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555556, 0x3, x1, 856, x2)
+
+inst_231:
+// rs1_val==4 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x2e, x1, 860, x2)
+
+inst_232:
+// rs1_val==4 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, -0x2c, x1, 864, x2)
+
+inst_233:
+// rs1_val==4 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x667, x1, 868, x2)
+
+inst_234:
+// rs1_val==4 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x334, x1, 872, x2)
+
+inst_235:
+// rs1_val==4 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x6, x1, 876, x2)
+
+inst_236:
+// rs1_val==4 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, -0x555, x1, 880, x2)
+
+inst_237:
+// rs1_val==4 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x556, x1, 884, x2)
+
+inst_238:
+// rs1_val==4 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, 0x4, x1, 888, x2)
+
+inst_239:
+// rs1_val==4 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x2c, x1, 892, x2)
+
+inst_240:
+// rs1_val==4 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, 0x0, x1, 896, x2)
+
+inst_241:
+// rs1_val==4 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x665, x1, 900, x2)
+
+inst_242:
+// rs1_val==4 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x332, x1, 904, x2)
+
+inst_243:
+// rs1_val==4 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x554, x1, 908, x2)
+
+inst_244:
+// rs1_val==4 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, 0x2, x1, 912, x2)
+
+inst_245:
+// rs1_val==4 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x2d, x1, 916, x2)
+
+inst_246:
+// rs1_val==4 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, -0x2d, x1, 920, x2)
+
+inst_247:
+// rs1_val==4 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x666, x1, 924, x2)
+
+inst_248:
+// rs1_val==4 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x333, x1, 928, x2)
+
+inst_249:
+// rs1_val==4 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x5, x1, 932, x2)
+
+inst_250:
+// rs1_val==4 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, -0x556, x1, 936, x2)
+
+inst_251:
+// rs1_val==4 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x4, 0x555, x1, 940, x2)
+
+inst_252:
+// rs1_val==4 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x4, 0x3, x1, 944, x2)
+
+inst_253:
+// rs1_val==46339 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x2e, x1, 948, x2)
+
+inst_254:
+// rs1_val==46339 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, -0x2c, x1, 952, x2)
+
+inst_255:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x667, x1, 956, x2)
+
+inst_256:
+// rs1_val==46339 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x334, x1, 960, x2)
+
+inst_257:
+// rs1_val==46339 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x6, x1, 964, x2)
+
+inst_258:
+// rs1_val==46339 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, -0x555, x1, 968, x2)
+
+inst_259:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x556, x1, 972, x2)
+
+inst_260:
+// rs1_val==46339 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x4, x1, 976, x2)
+
+inst_261:
+// rs1_val==46339 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x2c, x1, 980, x2)
+
+inst_262:
+// rs1_val==46339 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x0, x1, 984, x2)
+
+inst_263:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x665, x1, 988, x2)
+
+inst_264:
+// rs1_val==46339 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x332, x1, 992, x2)
+
+inst_265:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x554, x1, 996, x2)
+
+inst_266:
+// rs1_val==46339 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x2, x1, 1000, x2)
+
+inst_267:
+// rs1_val==46339 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x2d, x1, 1004, x2)
+
+inst_268:
+// rs1_val==46339 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, -0x2d, x1, 1008, x2)
+
+inst_269:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x666, x1, 1012, x2)
+
+inst_270:
+// rs1_val==46339 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x333, x1, 1016, x2)
+
+inst_271:
+// rs1_val==46339 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x5, x1, 1020, x2)
+
+inst_272:
+// rs1_val==46339 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, -0x556, x1, 1024, x2)
+
+inst_273:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x555, x1, 1028, x2)
+
+inst_274:
+// rs1_val==46339 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb503, 0x3, x1, 1032, x2)
+
+inst_275:
+// rs1_val==0 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x2e, x1, 1036, x2)
+
+inst_276:
+// rs1_val==0 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, -0x2c, x1, 1040, x2)
+
+inst_277:
+// rs1_val==0 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x667, x1, 1044, x2)
+
+inst_278:
+// rs1_val==0 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x334, x1, 1048, x2)
+
+inst_279:
+// rs1_val==0 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x6, x1, 1052, x2)
+
+inst_280:
+// rs1_val==0 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, -0x555, x1, 1056, x2)
+
+inst_281:
+// rs1_val==0 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x556, x1, 1060, x2)
+
+inst_282:
+// rs1_val==0 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x4, x1, 1064, x2)
+
+inst_283:
+// rs1_val==0 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x2c, x1, 1068, x2)
+
+inst_284:
+// rs1_val==0 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, 0x0, x1, 1072, x2)
+
+inst_285:
+// rs1_val==0 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x665, x1, 1076, x2)
+
+inst_286:
+// rs1_val==0 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x332, x1, 1080, x2)
+
+inst_287:
+// rs1_val==0 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x554, x1, 1084, x2)
+
+inst_288:
+// rs1_val==0 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x2, x1, 1088, x2)
+
+inst_289:
+// rs1_val==0 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x2d, x1, 1092, x2)
+
+inst_290:
+// rs1_val==0 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, -0x2d, x1, 1096, x2)
+
+inst_291:
+// rs1_val==0 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x666, x1, 1100, x2)
+
+inst_292:
+// rs1_val==0 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x333, x1, 1104, x2)
+
+inst_293:
+// rs1_val==0 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x5, x1, 1108, x2)
+
+inst_294:
+// rs1_val==0 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x0, -0x556, x1, 1112, x2)
+
+inst_295:
+// rs1_val==0 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x555, x1, 1116, x2)
+
+inst_296:
+// rs1_val==0 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x0, 0x3, x1, 1120, x2)
+
+inst_297:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x2e, x1, 1124, x2)
+
+inst_298:
+// rs1_val==1717986917 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, -0x2c, x1, 1128, x2)
+
+inst_299:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x667, x1, 1132, x2)
+
+inst_300:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x334, x1, 1136, x2)
+
+inst_301:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x6, x1, 1140, x2)
+
+inst_302:
+// rs1_val==1717986917 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, -0x555, x1, 1144, x2)
+
+inst_303:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x556, x1, 1148, x2)
+
+inst_304:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x4, x1, 1152, x2)
+
+inst_305:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x2c, x1, 1156, x2)
+
+inst_306:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x0, x1, 1160, x2)
+
+inst_307:
+// rs1_val==-1431655766 and imm_val==-1365, rs1_val == -1431655766
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, -0x555, x1, 1164, x2)
+
+inst_308:
+// rs1_val==-1431655766 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x556, x1, 1168, x2)
+
+inst_309:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x4, x1, 1172, x2)
+
+inst_310:
+// rs1_val==-1431655766 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x2c, x1, 1176, x2)
+
+inst_311:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x0, x1, 1180, x2)
+
+inst_312:
+// rs1_val==-1431655766 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x665, x1, 1184, x2)
+
+inst_313:
+// rs1_val==-1431655766 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x332, x1, 1188, x2)
+
+inst_314:
+// rs1_val==-1431655766 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x554, x1, 1192, x2)
+
+inst_315:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x2, x1, 1196, x2)
+
+inst_316:
+// rs1_val==-1431655766 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x2d, x1, 1200, x2)
+
+inst_317:
+// rs1_val==-1431655766 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, -0x2d, x1, 1204, x2)
+
+inst_318:
+// rs1_val==-1431655766 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x666, x1, 1208, x2)
+
+inst_319:
+// rs1_val==-1431655766 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x333, x1, 1212, x2)
+
+inst_320:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x5, x1, 1216, x2)
+
+inst_321:
+// rs1_val==-1431655766 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, -0x556, x1, 1220, x2)
+
+inst_322:
+// rs1_val==-1431655766 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x555, x1, 1224, x2)
+
+inst_323:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x3, x1, 1228, x2)
+
+inst_324:
+// rs1_val==1431655765 and imm_val==46, rs1_val == 1431655765
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x2e, x1, 1232, x2)
+
+inst_325:
+// rs1_val==1431655765 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, -0x2c, x1, 1236, x2)
+
+inst_326:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x667, x1, 1240, x2)
+
+inst_327:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x334, x1, 1244, x2)
+
+inst_328:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x6, x1, 1248, x2)
+
+inst_329:
+// rs1_val==1431655765 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, -0x555, x1, 1252, x2)
+
+inst_330:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x556, x1, 1256, x2)
+
+inst_331:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x4, x1, 1260, x2)
+
+inst_332:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x2c, x1, 1264, x2)
+
+inst_333:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x0, x1, 1268, x2)
+
+inst_334:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x665, x1, 1272, x2)
+
+inst_335:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x332, x1, 1276, x2)
+
+inst_336:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x554, x1, 1280, x2)
+
+inst_337:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x2, x1, 1284, x2)
+
+inst_338:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x2d, x1, 1288, x2)
+
+inst_339:
+// rs1_val==1431655765 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, -0x2d, x1, 1292, x2)
+
+inst_340:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x666, x1, 1296, x2)
+
+inst_341:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x333, x1, 1300, x2)
+
+inst_342:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x5, x1, 1304, x2)
+
+inst_343:
+// rs1_val==1431655765 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, -0x556, x1, 1308, x2)
+
+inst_344:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x555, x1, 1312, x2)
+
+inst_345:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555555, 0x3, x1, 1316, x2)
+
+inst_346:
+// rs1_val==3 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x2e, x1, 1320, x2)
+
+inst_347:
+// rs1_val==3 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, -0x2c, x1, 1324, x2)
+
+inst_348:
+// rs1_val==3 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x667, x1, 1328, x2)
+
+inst_349:
+// rs1_val==3 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x334, x1, 1332, x2)
+
+inst_350:
+// rs1_val==3 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x6, x1, 1336, x2)
+
+inst_351:
+// rs1_val==3 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, -0x555, x1, 1340, x2)
+
+inst_352:
+// rs1_val==3 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x556, x1, 1344, x2)
+
+inst_353:
+// rs1_val==3 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x4, x1, 1348, x2)
+
+inst_354:
+// rs1_val==3 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x2c, x1, 1352, x2)
+
+inst_355:
+// rs1_val==3 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, 0x0, x1, 1356, x2)
+
+inst_356:
+// rs1_val==3 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x665, x1, 1360, x2)
+
+inst_357:
+// rs1_val==3 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x332, x1, 1364, x2)
+
+inst_358:
+// rs1_val==3 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x554, x1, 1368, x2)
+
+inst_359:
+// rs1_val==3 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, 0x2, x1, 1372, x2)
+
+inst_360:
+// rs1_val==3 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x2d, x1, 1376, x2)
+
+inst_361:
+// rs1_val==3 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, -0x2d, x1, 1380, x2)
+
+inst_362:
+// rs1_val==3 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x666, x1, 1384, x2)
+
+inst_363:
+// rs1_val==3 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x333, x1, 1388, x2)
+
+inst_364:
+// rs1_val==3 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x5, x1, 1392, x2)
+
+inst_365:
+// rs1_val==3 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, -0x556, x1, 1396, x2)
+
+inst_366:
+// rs1_val==3 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x3, 0x555, x1, 1400, x2)
+
+inst_367:
+// rs1_val==3 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x3, 0x3, x1, 1404, x2)
+
+inst_368:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x665, x1, 1408, x2)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x332, x1, 1412, x2)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x554, x1, 1416, x2)
+
+inst_371:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x2, x1, 1420, x2)
+
+inst_372:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x2d, x1, 1424, x2)
+
+inst_373:
+// rs1_val==1717986917 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, -0x2d, x1, 1428, x2)
+
+inst_374:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x666, x1, 1432, x2)
+
+inst_375:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x333, x1, 1436, x2)
+
+inst_376:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x5, x1, 1440, x2)
+
+inst_377:
+// rs1_val==1717986917 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, -0x556, x1, 1444, x2)
+
+inst_378:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x555, x1, 1448, x2)
+
+inst_379:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666665, 0x3, x1, 1452, x2)
+
+inst_380:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x2e, x1, 1456, x2)
+
+inst_381:
+// rs1_val==858993458 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, -0x2c, x1, 1460, x2)
+
+inst_382:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x667, x1, 1464, x2)
+
+inst_383:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x334, x1, 1468, x2)
+
+inst_384:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x6, x1, 1472, x2)
+
+inst_385:
+// rs1_val==858993458 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, -0x555, x1, 1476, x2)
+
+inst_386:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x556, x1, 1480, x2)
+
+inst_387:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x4, x1, 1484, x2)
+
+inst_388:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x2c, x1, 1488, x2)
+
+inst_389:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x0, x1, 1492, x2)
+
+inst_390:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x665, x1, 1496, x2)
+
+inst_391:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x332, x1, 1500, x2)
+
+inst_392:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x554, x1, 1504, x2)
+
+inst_393:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x2, x1, 1508, x2)
+
+inst_394:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x2d, x1, 1512, x2)
+
+inst_395:
+// rs1_val==858993458 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, -0x2d, x1, 1516, x2)
+
+inst_396:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x666, x1, 1520, x2)
+
+inst_397:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x333, x1, 1524, x2)
+
+inst_398:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x5, x1, 1528, x2)
+
+inst_399:
+// rs1_val==858993458 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, -0x556, x1, 1532, x2)
+
+inst_400:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x555, x1, 1536, x2)
+
+inst_401:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333332, 0x3, x1, 1540, x2)
+
+inst_402:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x2e, x1, 1544, x2)
+
+inst_403:
+// rs1_val==1431655764 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, -0x2c, x1, 1548, x2)
+
+inst_404:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x667, x1, 1552, x2)
+
+inst_405:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x334, x1, 1556, x2)
+
+inst_406:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x6, x1, 1560, x2)
+
+inst_407:
+// rs1_val==1431655764 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, -0x555, x1, 1564, x2)
+
+inst_408:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x556, x1, 1568, x2)
+
+inst_409:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x4, x1, 1572, x2)
+
+inst_410:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x2c, x1, 1576, x2)
+
+inst_411:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x0, x1, 1580, x2)
+
+inst_412:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x665, x1, 1584, x2)
+
+inst_413:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x332, x1, 1588, x2)
+
+inst_414:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x554, x1, 1592, x2)
+
+inst_415:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x2, x1, 1596, x2)
+
+inst_416:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x2d, x1, 1600, x2)
+
+inst_417:
+// rs1_val==1431655764 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, -0x2d, x1, 1604, x2)
+
+inst_418:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x666, x1, 1608, x2)
+
+inst_419:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x333, x1, 1612, x2)
+
+inst_420:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x5, x1, 1616, x2)
+
+inst_421:
+// rs1_val==1431655764 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, -0x556, x1, 1620, x2)
+
+inst_422:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x555, x1, 1624, x2)
+
+inst_423:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x55555554, 0x3, x1, 1628, x2)
+
+inst_424:
+// rs1_val==2 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x2e, x1, 1632, x2)
+
+inst_425:
+// rs1_val==2 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, -0x2c, x1, 1636, x2)
+
+inst_426:
+// rs1_val==2 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x667, x1, 1640, x2)
+
+inst_427:
+// rs1_val==2 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x334, x1, 1644, x2)
+
+inst_428:
+// rs1_val==2 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x6, x1, 1648, x2)
+
+inst_429:
+// rs1_val==2 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, -0x555, x1, 1652, x2)
+
+inst_430:
+// rs1_val==2 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x556, x1, 1656, x2)
+
+inst_431:
+// rs1_val==2 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x4, x1, 1660, x2)
+
+inst_432:
+// rs1_val==2 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x2c, x1, 1664, x2)
+
+inst_433:
+// rs1_val==2 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, 0x0, x1, 1668, x2)
+
+inst_434:
+// rs1_val==2 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x665, x1, 1672, x2)
+
+inst_435:
+// rs1_val==2 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x332, x1, 1676, x2)
+
+inst_436:
+// rs1_val==2 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x554, x1, 1680, x2)
+
+inst_437:
+// rs1_val==2 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, 0x2, x1, 1684, x2)
+
+inst_438:
+// rs1_val==2 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, -0x2d, x1, 1688, x2)
+
+inst_439:
+// rs1_val==2 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x666, x1, 1692, x2)
+
+inst_440:
+// rs1_val==2 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x333, x1, 1696, x2)
+
+inst_441:
+// rs1_val==2 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x5, x1, 1700, x2)
+
+inst_442:
+// rs1_val==2 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x2, -0x556, x1, 1704, x2)
+
+inst_443:
+// rs1_val==2 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x555, x1, 1708, x2)
+
+inst_444:
+// rs1_val==2 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x2, 0x3, x1, 1712, x2)
+
+inst_445:
+// rs1_val==46340 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x2e, x1, 1716, x2)
+
+inst_446:
+// rs1_val==46340 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, -0x2c, x1, 1720, x2)
+
+inst_447:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x667, x1, 1724, x2)
+
+inst_448:
+// rs1_val==46340 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x334, x1, 1728, x2)
+
+inst_449:
+// rs1_val==46340 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x6, x1, 1732, x2)
+
+inst_450:
+// rs1_val==46340 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, -0x555, x1, 1736, x2)
+
+inst_451:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x556, x1, 1740, x2)
+
+inst_452:
+// rs1_val==46340 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x4, x1, 1744, x2)
+
+inst_453:
+// rs1_val==46340 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x2c, x1, 1748, x2)
+
+inst_454:
+// rs1_val==46340 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x0, x1, 1752, x2)
+
+inst_455:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x665, x1, 1756, x2)
+
+inst_456:
+// rs1_val==46340 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x332, x1, 1760, x2)
+
+inst_457:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x554, x1, 1764, x2)
+
+inst_458:
+// rs1_val==46340 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x2, x1, 1768, x2)
+
+inst_459:
+// rs1_val==46340 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x2d, x1, 1772, x2)
+
+inst_460:
+// rs1_val==46340 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, -0x2d, x1, 1776, x2)
+
+inst_461:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x666, x1, 1780, x2)
+
+inst_462:
+// rs1_val==46340 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x333, x1, 1784, x2)
+
+inst_463:
+// rs1_val==46340 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x5, x1, 1788, x2)
+
+inst_464:
+// rs1_val==46340 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, -0x556, x1, 1792, x2)
+
+inst_465:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x555, x1, 1796, x2)
+
+inst_466:
+// rs1_val==46340 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0xb504, 0x3, x1, 1800, x2)
+
+inst_467:
+// rs1_val==-46340 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x2e, x1, 1804, x2)
+
+inst_468:
+// rs1_val==-46340 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, -0x2c, x1, 1808, x2)
+
+inst_469:
+// rs1_val==-46340 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x667, x1, 1812, x2)
+
+inst_470:
+// rs1_val==-46340 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x334, x1, 1816, x2)
+
+inst_471:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x6, x1, 1820, x2)
+
+inst_472:
+// rs1_val==-46340 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, -0x555, x1, 1824, x2)
+
+inst_473:
+// rs1_val==-46340 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x556, x1, 1828, x2)
+
+inst_474:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x4, x1, 1832, x2)
+
+inst_475:
+// rs1_val==-46340 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x2c, x1, 1836, x2)
+
+inst_476:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x0, x1, 1840, x2)
+
+inst_477:
+// rs1_val==-46340 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x665, x1, 1844, x2)
+
+inst_478:
+// rs1_val==-46340 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x332, x1, 1848, x2)
+
+inst_479:
+// rs1_val==-46340 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x554, x1, 1852, x2)
+
+inst_480:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x2, x1, 1856, x2)
+
+inst_481:
+// rs1_val==-46340 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x2d, x1, 1860, x2)
+
+inst_482:
+// rs1_val==-46340 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, -0x2d, x1, 1864, x2)
+
+inst_483:
+// rs1_val==-46340 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x666, x1, 1868, x2)
+
+inst_484:
+// rs1_val==-46340 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x333, x1, 1872, x2)
+
+inst_485:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x5, x1, 1876, x2)
+
+inst_486:
+// rs1_val==-46340 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, -0x556, x1, 1880, x2)
+
+inst_487:
+// rs1_val==-46340 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x555, x1, 1884, x2)
+
+inst_488:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x1, -0xb504, 0x3, x1, 1888, x2)
+
+inst_489:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x2e, x1, 1892, x2)
+
+inst_490:
+// rs1_val==1717986918 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, -0x2c, x1, 1896, x2)
+
+inst_491:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x667, x1, 1900, x2)
+
+inst_492:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x334, x1, 1904, x2)
+
+inst_493:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x6, x1, 1908, x2)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, -0x555, x1, 1912, x2)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x556, x1, 1916, x2)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x4, x1, 1920, x2)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x2c, x1, 1924, x2)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x0, x1, 1928, x2)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x665, x1, 1932, x2)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x332, x1, 1936, x2)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x554, x1, 1940, x2)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x2, x1, 1944, x2)
+
+inst_503:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x2d, x1, 1948, x2)
+
+inst_504:
+// rs1_val==1717986918 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, -0x2d, x1, 1952, x2)
+
+inst_505:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x666, x1, 1956, x2)
+
+inst_506:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x333, x1, 1960, x2)
+
+inst_507:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x5, x1, 1964, x2)
+
+inst_508:
+// rs1_val==1717986918 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, -0x556, x1, 1968, x2)
+
+inst_509:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x555, x1, 1972, x2)
+
+inst_510:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x66666666, 0x3, x1, 1976, x2)
+
+inst_511:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x2e, x1, 1980, x2)
+
+inst_512:
+// rs1_val==858993459 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, -0x2c, x1, 1984, x2)
+
+inst_513:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x667, x1, 1988, x2)
+
+inst_514:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x334, x1, 1992, x2)
+
+inst_515:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x6, x1, 1996, x2)
+
+inst_516:
+// rs1_val==858993459 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, -0x555, x1, 2000, x2)
+
+inst_517:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x556, x1, 2004, x2)
+
+inst_518:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x4, x1, 2008, x2)
+
+inst_519:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x2c, x1, 2012, x2)
+
+inst_520:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x0, x1, 2016, x2)
+
+inst_521:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x665, x1, 2020, x2)
+
+inst_522:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x332, x1, 2024, x2)
+
+inst_523:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x554, x1, 2028, x2)
+
+inst_524:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x2, x1, 2032, x2)
+
+inst_525:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x2d, x1, 2036, x2)
+
+inst_526:
+// rs1_val==858993459 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, -0x2d, x1, 2040, x2)
+
+inst_527:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x666, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_528:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x333, x1, 0, x2)
+
+inst_529:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x5, x1, 4, x2)
+
+inst_530:
+// rs1_val==858993459 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, -0x556, x1, 8, x2)
+
+inst_531:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x555, x1, 12, x2)
+
+inst_532:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x33333333, 0x3, x1, 16, x2)
+
+inst_533:
+// rs1_val==5 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x2e, x1, 20, x2)
+
+inst_534:
+// rs1_val==5 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, -0x2c, x1, 24, x2)
+
+inst_535:
+// rs1_val==5 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x667, x1, 28, x2)
+
+inst_536:
+// rs1_val==5 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x334, x1, 32, x2)
+
+inst_537:
+// rs1_val==5 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x6, x1, 36, x2)
+
+inst_538:
+// rs1_val==5 and imm_val==-1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:-0x555
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, -0x555, x1, 40, x2)
+
+inst_539:
+// rs1_val==5 and imm_val==1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x556, x1, 44, x2)
+
+inst_540:
+// rs1_val==5 and imm_val==4, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, 0x4, x1, 48, x2)
+
+inst_541:
+// rs1_val==5 and imm_val==44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x2c, x1, 52, x2)
+
+inst_542:
+// rs1_val==5 and imm_val==0, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, 0x0, x1, 56, x2)
+
+inst_543:
+// rs1_val==5 and imm_val==1637, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x665, x1, 60, x2)
+
+inst_544:
+// rs1_val==5 and imm_val==818, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x332, x1, 64, x2)
+
+inst_545:
+// rs1_val==5 and imm_val==1364, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x554, x1, 68, x2)
+
+inst_546:
+// rs1_val==5 and imm_val==2, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, 0x2, x1, 72, x2)
+
+inst_547:
+// rs1_val==5 and imm_val==45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x2d, x1, 76, x2)
+
+inst_548:
+// rs1_val==5 and imm_val==-45, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2d
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, -0x2d, x1, 80, x2)
+
+inst_549:
+// rs1_val==5 and imm_val==1638, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x666, x1, 84, x2)
+
+inst_550:
+// rs1_val==5 and imm_val==819, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x333, x1, 88, x2)
+
+inst_551:
+// rs1_val==5 and imm_val==5, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, 0x5, x1, 92, x2)
+
+inst_552:
+// rs1_val==5 and imm_val==-1366, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:-0x556
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, -0x556, x1, 96, x2)
+
+inst_553:
+// rs1_val==5 and imm_val==1365, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( slti, x11, x10, 0x1, 0x5, 0x555, x1, 100, x2)
+
+inst_554:
+// rs1_val==5 and imm_val==3, 
+// opcode: slti ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( slti, x11, x10, 0x0, 0x5, 0x3, x1, 104, x2)
+
+inst_555:
+// rs1_val==-1431655766 and imm_val==46, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2e
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x2e, x1, 108, x2)
+
+inst_556:
+// rs1_val==-1431655766 and imm_val==-44, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2c
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, -0x2c, x1, 112, x2)
+
+inst_557:
+// rs1_val==-1431655766 and imm_val==1639, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x667
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x667, x1, 116, x2)
+
+inst_558:
+// rs1_val==-1431655766 and imm_val==820, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x334
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x334, x1, 120, x2)
+
+inst_559:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x55555556, 0x6, x1, 124, x2)
+
+inst_560:
+// rs1_val == -536870913, 
+// opcode: slti ; op1:x10; dest:x11; op1val:-0x20000001;  immval:-0x6
+TEST_IMM_OP( slti, x11, x10, 0x1, -0x20000001, -0x6, x1, 128, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 33*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S
new file mode 100644
index 000000000..79336c4f0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S
@@ -0,0 +1,3566 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sltiu instruction of the RISC-V E extension for the sltiu covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sltiu)
+
+RVTEST_SIGBASE( x14,signature_x14_1)
+
+inst_0:
+// rs1 != rd, rs1==x7, rd==x2, imm_val == (2**(12)-1), rs1_val != imm_val and rs1_val > 0 and imm_val > 0
+// opcode: sltiu ; op1:x7; dest:x2; op1val:0x9;  immval:0xfff
+TEST_IMM_OP( sltiu, x2, x7, 0x1, 0x9, 0xfff, x14, 0, x9)
+
+inst_1:
+// rs1 == rd, rs1==x3, rd==x3, rs1_val == 2147483647, imm_val == 3839
+// opcode: sltiu ; op1:x3; dest:x3; op1val:0x7fffffff;  immval:0xeff
+TEST_IMM_OP( sltiu, x3, x3, 0x1, 0x7fffffff, 0xeff, x14, 4, x9)
+
+inst_2:
+// rs1==x10, rd==x4, rs1_val == 3221225471, imm_val == 32
+// opcode: sltiu ; op1:x10; dest:x4; op1val:0xbfffffff;  immval:0x20
+TEST_IMM_OP( sltiu, x4, x10, 0x0, 0xbfffffff, 0x20, x14, 8, x9)
+
+inst_3:
+// rs1==x4, rd==x6, rs1_val == 3758096383, 
+// opcode: sltiu ; op1:x4; dest:x6; op1val:0xdfffffff;  immval:0x5
+TEST_IMM_OP( sltiu, x6, x4, 0x0, 0xdfffffff, 0x5, x14, 12, x9)
+
+inst_4:
+// rs1==x6, rd==x13, rs1_val == 4026531839, 
+// opcode: sltiu ; op1:x6; dest:x13; op1val:0xefffffff;  immval:0x667
+TEST_IMM_OP( sltiu, x13, x6, 0x0, 0xefffffff, 0x667, x14, 16, x9)
+
+inst_5:
+// rs1==x1, rd==x7, rs1_val == 4160749567, imm_val == 16
+// opcode: sltiu ; op1:x1; dest:x7; op1val:0xf7ffffff;  immval:0x10
+TEST_IMM_OP( sltiu, x7, x1, 0x0, 0xf7ffffff, 0x10, x14, 20, x9)
+
+inst_6:
+// rs1==x2, rd==x8, rs1_val == 4227858431, imm_val == 0
+// opcode: sltiu ; op1:x2; dest:x8; op1val:0xfbffffff;  immval:0x0
+TEST_IMM_OP( sltiu, x8, x2, 0x0, 0xfbffffff, 0x0, x14, 24, x9)
+
+inst_7:
+// rs1==x0, rd==x1, rs1_val == 4261412863, 
+// opcode: sltiu ; op1:x0; dest:x1; op1val:0x0;  immval:0xc
+TEST_IMM_OP( sltiu, x1, x0, 0x1, 0x0, 0xc, x14, 28, x9)
+
+inst_8:
+// rs1==x5, rd==x12, rs1_val == 4278190079, imm_val == 512
+// opcode: sltiu ; op1:x5; dest:x12; op1val:0xfeffffff;  immval:0x200
+TEST_IMM_OP( sltiu, x12, x5, 0x0, 0xfeffffff, 0x200, x14, 32, x9)
+
+inst_9:
+// rs1==x11, rd==x9, rs1_val == 4286578687, 
+// opcode: sltiu ; op1:x11; dest:x9; op1val:0xff7fffff;  immval:0xf
+TEST_IMM_OP( sltiu, x9, x11, 0x0, 0xff7fffff, 0xf, x14, 36, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_10:
+// rs1==x12, rd==x10, rs1_val == 4290772991, imm_val == 4093
+// opcode: sltiu ; op1:x12; dest:x10; op1val:0xffbfffff;  immval:0xffd
+TEST_IMM_OP( sltiu, x10, x12, 0x1, 0xffbfffff, 0xffd, x1, 0, x2)
+
+inst_11:
+// rs1==x9, rd==x14, rs1_val == 4292870143, 
+// opcode: sltiu ; op1:x9; dest:x14; op1val:0xffdfffff;  immval:0xaab
+TEST_IMM_OP( sltiu, x14, x9, 0x1, 0xffdfffff, 0xaab, x1, 4, x2)
+
+inst_12:
+// rs1==x14, rd==x15, rs1_val == 4293918719, 
+// opcode: sltiu ; op1:x14; dest:x15; op1val:0xffefffff;  immval:0x11
+TEST_IMM_OP( sltiu, x15, x14, 0x0, 0xffefffff, 0x11, x1, 8, x2)
+
+inst_13:
+// rs1==x15, rd==x0, rs1_val == 4294443007, 
+// opcode: sltiu ; op1:x15; dest:x0; op1val:0xfff7ffff;  immval:0xa
+TEST_IMM_OP( sltiu, x0, x15, 0, 0xfff7ffff, 0xa, x1, 12, x2)
+
+inst_14:
+// rs1==x13, rd==x11, rs1_val == 4294705151, 
+// opcode: sltiu ; op1:x13; dest:x11; op1val:0xfffbffff;  immval:0x13
+TEST_IMM_OP( sltiu, x11, x13, 0x0, 0xfffbffff, 0x13, x1, 16, x2)
+
+inst_15:
+// rs1==x8, rd==x5, rs1_val == 4294836223, 
+// opcode: sltiu ; op1:x8; dest:x5; op1val:0xfffdffff;  immval:0x0
+TEST_IMM_OP( sltiu, x5, x8, 0x0, 0xfffdffff, 0x0, x1, 20, x2)
+
+inst_16:
+// rs1_val == 4294901759, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffeffff;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffeffff, 0x3, x1, 24, x2)
+
+inst_17:
+// rs1_val == 4294934527, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff7fff;  immval:0xfff
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffff7fff, 0xfff, x1, 28, x2)
+
+inst_18:
+// rs1_val == 4294950911, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffbfff;  immval:0xf
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffbfff, 0xf, x1, 32, x2)
+
+inst_19:
+// rs1_val == 4294959103, imm_val == 4087
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffdfff;  immval:0xff7
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffffdfff, 0xff7, x1, 36, x2)
+
+inst_20:
+// rs1_val == 4294963199, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffefff;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffefff, 0x334, x1, 40, x2)
+
+inst_21:
+// rs1_val == 4294965247, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffff7ff;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffff7ff, 0x666, x1, 44, x2)
+
+inst_22:
+// rs1_val == 4294966271, imm_val == 3071
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffbff;  immval:0xbff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffbff, 0xbff, x1, 48, x2)
+
+inst_23:
+// rs1_val == 4294966783, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffdff;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffdff, 0x332, x1, 52, x2)
+
+inst_24:
+// rs1_val == 4294967039, imm_val == 3583
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffeff;  immval:0xdff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffeff, 0xdff, x1, 56, x2)
+
+inst_25:
+// rs1_val == 4294967167, imm_val == 4094
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffff7f;  immval:0xffe
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffffff7f, 0xffe, x1, 60, x2)
+
+inst_26:
+// rs1_val == 4294967231, imm_val == 128
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffffbf;  immval:0x80
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffffbf, 0x80, x1, 64, x2)
+
+inst_27:
+// rs1_val == 4294967263, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffffdf;  immval:0xc
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffffdf, 0xc, x1, 68, x2)
+
+inst_28:
+// rs1_val == 4294967279, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffffef;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffffef, 0xaab, x1, 72, x2)
+
+inst_29:
+// rs1_val == 4294967287, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffff7;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffff7, 0x554, x1, 76, x2)
+
+inst_30:
+// rs1_val == 4294967291, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffffb;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffffb, 0x667, x1, 80, x2)
+
+inst_31:
+// rs1_val == 4294967293, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffffd;  immval:0xdff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffffd, 0xdff, x1, 84, x2)
+
+inst_32:
+// rs1_val == 4294967294, imm_val == 4079
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffffe;  immval:0xfef
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffffe, 0xfef, x1, 88, x2)
+
+inst_33:
+// imm_val == 2047, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffffffe;  immval:0x7ff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffffffe, 0x7ff, x1, 92, x2)
+
+inst_34:
+// imm_val == 3967, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffffdf;  immval:0xf7f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffffdf, 0xf7f, x1, 96, x2)
+
+inst_35:
+// imm_val == 4031, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xfbf
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666667, 0xfbf, x1, 100, x2)
+
+inst_36:
+// imm_val == 4063, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffbffff;  immval:0xfdf
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xfffbffff, 0xfdf, x1, 104, x2)
+
+inst_37:
+// imm_val == 4091, rs1_val == 524288
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x80000;  immval:0xffb
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x80000, 0xffb, x1, 108, x2)
+
+inst_38:
+// rs1_val == 2147483648, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x80000000;  immval:0x200
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x80000000, 0x200, x1, 112, x2)
+
+inst_39:
+// rs1_val == 1073741824, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x7ff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x40000000, 0x7ff, x1, 116, x2)
+
+inst_40:
+// rs1_val == 536870912, imm_val == 2
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x20000000, 0x2, x1, 120, x2)
+
+inst_41:
+// rs1_val == 268435456, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000000, 0x3, x1, 124, x2)
+
+inst_42:
+// rs1_val == 134217728, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x8000000;  immval:0xeff
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x8000000, 0xeff, x1, 128, x2)
+
+inst_43:
+// rs1_val == 67108864, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4000000;  immval:0xe
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4000000, 0xe, x1, 132, x2)
+
+inst_44:
+// rs1_val == 33554432, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x2000000, 0x5, x1, 136, x2)
+
+inst_45:
+// rs1_val == 16777216, imm_val == 2048
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1000000;  immval:0x800
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1000000, 0x800, x1, 140, x2)
+
+inst_46:
+// rs1_val == 8388608, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x800000;  immval:0x7
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x800000, 0x7, x1, 144, x2)
+
+inst_47:
+// rs1_val == 4194304, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x400000;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x400000, 0xaab, x1, 148, x2)
+
+inst_48:
+// rs1_val == 2097152, imm_val == 1
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x200000;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x200000, 0x1, x1, 152, x2)
+
+inst_49:
+// rs1_val == 1048576, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x100000;  immval:0x7ff
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x100000, 0x7ff, x1, 156, x2)
+
+inst_50:
+// rs1_val == 262144, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x40000;  immval:0xff7
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x40000, 0xff7, x1, 160, x2)
+
+inst_51:
+// rs1_val == 131072, imm_val == 4
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x20000;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x20000, 0x4, x1, 164, x2)
+
+inst_52:
+// rs1_val == 65536, rs1_val==65536 and imm_val==3
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x3, x1, 168, x2)
+
+inst_53:
+// rs1_val == 32768, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x8000;  immval:0xffb
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x8000, 0xffb, x1, 172, x2)
+
+inst_54:
+// rs1_val == 16384, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4000;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4000, 0x2, x1, 176, x2)
+
+inst_55:
+// rs1_val == 8192, imm_val == 8
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2000;  immval:0x8
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x2000, 0x8, x1, 180, x2)
+
+inst_56:
+// rs1_val == 4096, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1000;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x1000, 0x2d, x1, 184, x2)
+
+inst_57:
+// rs1_val == 2048, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x800;  immval:0xfbf
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x800, 0xfbf, x1, 188, x2)
+
+inst_58:
+// rs1_val == 1024, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x400;  immval:0x20
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x400, 0x20, x1, 192, x2)
+
+inst_59:
+// rs1_val == 512, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x200;  immval:0x9
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x200, 0x9, x1, 196, x2)
+
+inst_60:
+// rs1_val == 256, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x100;  immval:0x7
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x100, 0x7, x1, 200, x2)
+
+inst_61:
+// rs1_val == 128, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x80;  immval:0x800
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x80, 0x800, x1, 204, x2)
+
+inst_62:
+// rs1_val == 64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x40;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x40, 0x3e, x1, 208, x2)
+
+inst_63:
+// rs1_val == 32, imm_val == 2730
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x20;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x20, 0xaaa, x1, 212, x2)
+
+inst_64:
+// rs1_val == 16, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10;  immval:0xfef
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x10, 0xfef, x1, 216, x2)
+
+inst_65:
+// rs1_val == 8, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x8;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x8, 0x0, x1, 220, x2)
+
+inst_66:
+// rs1_val == 4, rs1_val==4 and imm_val==4, rs1_val == imm_val and rs1_val > 0 and imm_val > 0
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4, 0x4, x1, 224, x2)
+
+inst_67:
+// rs1_val == 2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0xbff
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0xbff, x1, 228, x2)
+
+inst_68:
+// rs1_val == 1, rs1_val==1 and imm_val==1638
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x666, x1, 232, x2)
+
+inst_69:
+// imm_val == 1024, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x400
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x400, x1, 236, x2)
+
+inst_70:
+// imm_val == 256, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xdfffffff;  immval:0x100
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xdfffffff, 0x100, x1, 240, x2)
+
+inst_71:
+// imm_val == 64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x12;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x12, 0x40, x1, 244, x2)
+
+inst_72:
+// rs1_val==65536 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x40, x1, 248, x2)
+
+inst_73:
+// rs1_val==65536 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x1, x1, 252, x2)
+
+inst_74:
+// rs1_val==65536 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x2e, x1, 256, x2)
+
+inst_75:
+// rs1_val==65536 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x667, x1, 260, x2)
+
+inst_76:
+// rs1_val==65536 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x334, x1, 264, x2)
+
+inst_77:
+// rs1_val==65536 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x6, x1, 268, x2)
+
+inst_78:
+// rs1_val==65536 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x10000, 0xaab, x1, 272, x2)
+
+inst_79:
+// rs1_val==65536 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x556, x1, 276, x2)
+
+inst_80:
+// rs1_val==65536 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x4, x1, 280, x2)
+
+inst_81:
+// rs1_val==65536 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x3e, x1, 284, x2)
+
+inst_82:
+// rs1_val==65536 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x0, x1, 288, x2)
+
+inst_83:
+// rs1_val==65536 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x2c, x1, 292, x2)
+
+inst_84:
+// rs1_val==65536 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x665, x1, 296, x2)
+
+inst_85:
+// rs1_val==65536 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x332, x1, 300, x2)
+
+inst_86:
+// rs1_val==65536 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x10000, 0xaa9, x1, 304, x2)
+
+inst_87:
+// rs1_val==65536 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x554, x1, 308, x2)
+
+inst_88:
+// rs1_val==65536 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x2, x1, 312, x2)
+
+inst_89:
+// rs1_val==65536 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x3f, x1, 316, x2)
+
+inst_90:
+// rs1_val==65536 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x2d, x1, 320, x2)
+
+inst_91:
+// rs1_val==65536 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x666, x1, 324, x2)
+
+inst_92:
+// rs1_val==65536 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x333, x1, 328, x2)
+
+inst_93:
+// rs1_val==65536 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x5, x1, 332, x2)
+
+inst_94:
+// rs1_val==65536 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x10000, 0xaaa, x1, 336, x2)
+
+inst_95:
+// rs1_val==65536 and imm_val==1365, imm_val == 1365
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x10000;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x10000, 0x555, x1, 340, x2)
+
+inst_96:
+// rs1_val==1 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x40, x1, 344, x2)
+
+inst_97:
+// rs1_val==1 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x1, 0x1, x1, 348, x2)
+
+inst_98:
+// rs1_val==1 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x2e, x1, 352, x2)
+
+inst_99:
+// rs1_val==1 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x667, x1, 356, x2)
+
+inst_100:
+// rs1_val==1 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x334, x1, 360, x2)
+
+inst_101:
+// rs1_val==1 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x6, x1, 364, x2)
+
+inst_102:
+// rs1_val==1 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0xaab, x1, 368, x2)
+
+inst_103:
+// rs1_val==1 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x556, x1, 372, x2)
+
+inst_104:
+// rs1_val==1 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x4, x1, 376, x2)
+
+inst_105:
+// rs1_val==1 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x3e, x1, 380, x2)
+
+inst_106:
+// rs1_val==1 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x1, 0x0, x1, 384, x2)
+
+inst_107:
+// rs1_val==1 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x2c, x1, 388, x2)
+
+inst_108:
+// rs1_val==1 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x665, x1, 392, x2)
+
+inst_109:
+// rs1_val==1 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x332, x1, 396, x2)
+
+inst_110:
+// rs1_val==1 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0xaa9, x1, 400, x2)
+
+inst_111:
+// rs1_val==1 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x554, x1, 404, x2)
+
+inst_112:
+// rs1_val==1 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x2, x1, 408, x2)
+
+inst_113:
+// rs1_val==1 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x3f, x1, 412, x2)
+
+inst_114:
+// rs1_val==1 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x2d, x1, 416, x2)
+
+inst_115:
+// rs1_val==1 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x333, x1, 420, x2)
+
+inst_116:
+// rs1_val==1 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x5, x1, 424, x2)
+
+inst_117:
+// rs1_val==1 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0xaaa, x1, 428, x2)
+
+inst_118:
+// rs1_val==1 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x555, x1, 432, x2)
+
+inst_119:
+// rs1_val==1 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x1;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x1, 0x3, x1, 436, x2)
+
+inst_120:
+// rs1_val==46341 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x40, x1, 440, x2)
+
+inst_121:
+// rs1_val==46341 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x1, x1, 444, x2)
+
+inst_122:
+// rs1_val==46341 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x2e, x1, 448, x2)
+
+inst_123:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x667, x1, 452, x2)
+
+inst_124:
+// rs1_val==46341 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x334, x1, 456, x2)
+
+inst_125:
+// rs1_val==46341 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x6, x1, 460, x2)
+
+inst_126:
+// rs1_val==46341 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb505, 0xaab, x1, 464, x2)
+
+inst_127:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x556, x1, 468, x2)
+
+inst_128:
+// rs1_val==46341 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x4, x1, 472, x2)
+
+inst_129:
+// rs1_val==46341 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x3e, x1, 476, x2)
+
+inst_130:
+// rs1_val==46341 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x0, x1, 480, x2)
+
+inst_131:
+// rs1_val==46341 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x2c, x1, 484, x2)
+
+inst_132:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x665, x1, 488, x2)
+
+inst_133:
+// rs1_val==46341 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x332, x1, 492, x2)
+
+inst_134:
+// rs1_val==46341 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb505, 0xaa9, x1, 496, x2)
+
+inst_135:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x554, x1, 500, x2)
+
+inst_136:
+// rs1_val==46341 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x2, x1, 504, x2)
+
+inst_137:
+// rs1_val==46341 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x3f, x1, 508, x2)
+
+inst_138:
+// rs1_val==46341 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x2d, x1, 512, x2)
+
+inst_139:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x666, x1, 516, x2)
+
+inst_140:
+// rs1_val==46341 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x333, x1, 520, x2)
+
+inst_141:
+// rs1_val==46341 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x5, x1, 524, x2)
+
+inst_142:
+// rs1_val==46341 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb505, 0xaaa, x1, 528, x2)
+
+inst_143:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x555, x1, 532, x2)
+
+inst_144:
+// rs1_val==46341 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb505, 0x3, x1, 536, x2)
+
+inst_145:
+// rs1_val==1717986919 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x40, x1, 540, x2)
+
+inst_146:
+// rs1_val==1717986919 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x1, x1, 544, x2)
+
+inst_147:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x2e, x1, 548, x2)
+
+inst_148:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x667, x1, 552, x2)
+
+inst_149:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x334, x1, 556, x2)
+
+inst_150:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x6, x1, 560, x2)
+
+inst_151:
+// rs1_val==1717986919 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666667, 0xaab, x1, 564, x2)
+
+inst_152:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x556, x1, 568, x2)
+
+inst_153:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x4, x1, 572, x2)
+
+inst_154:
+// rs1_val==1717986919 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x3e, x1, 576, x2)
+
+inst_155:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x0, x1, 580, x2)
+
+inst_156:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x2c, x1, 584, x2)
+
+inst_157:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x665, x1, 588, x2)
+
+inst_158:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x332, x1, 592, x2)
+
+inst_159:
+// rs1_val==1717986919 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666667, 0xaa9, x1, 596, x2)
+
+inst_160:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x554, x1, 600, x2)
+
+inst_161:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x2, x1, 604, x2)
+
+inst_162:
+// rs1_val==1717986919 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x3f, x1, 608, x2)
+
+inst_163:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x2d, x1, 612, x2)
+
+inst_164:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x666, x1, 616, x2)
+
+inst_165:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x333, x1, 620, x2)
+
+inst_166:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x5, x1, 624, x2)
+
+inst_167:
+// rs1_val==1717986919 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666667, 0xaaa, x1, 628, x2)
+
+inst_168:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x555, x1, 632, x2)
+
+inst_169:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666667, 0x3, x1, 636, x2)
+
+inst_170:
+// rs1_val==858993460 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x40, x1, 640, x2)
+
+inst_171:
+// rs1_val==858993460 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x1, x1, 644, x2)
+
+inst_172:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x2e, x1, 648, x2)
+
+inst_173:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x667, x1, 652, x2)
+
+inst_174:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x334, x1, 656, x2)
+
+inst_175:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x6, x1, 660, x2)
+
+inst_176:
+// rs1_val==858993460 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333334, 0xaab, x1, 664, x2)
+
+inst_177:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x556, x1, 668, x2)
+
+inst_178:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x4, x1, 672, x2)
+
+inst_179:
+// rs1_val==858993460 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x3e, x1, 676, x2)
+
+inst_180:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x0, x1, 680, x2)
+
+inst_181:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x2c, x1, 684, x2)
+
+inst_182:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x665, x1, 688, x2)
+
+inst_183:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x332, x1, 692, x2)
+
+inst_184:
+// rs1_val==858993460 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333334, 0xaa9, x1, 696, x2)
+
+inst_185:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x554, x1, 700, x2)
+
+inst_186:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x2, x1, 704, x2)
+
+inst_187:
+// rs1_val==858993460 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x3f, x1, 708, x2)
+
+inst_188:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x2d, x1, 712, x2)
+
+inst_189:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x666, x1, 716, x2)
+
+inst_190:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x333, x1, 720, x2)
+
+inst_191:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x5, x1, 724, x2)
+
+inst_192:
+// rs1_val==858993460 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333334, 0xaaa, x1, 728, x2)
+
+inst_193:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x555, x1, 732, x2)
+
+inst_194:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333334, 0x3, x1, 736, x2)
+
+inst_195:
+// rs1_val==6 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x40, x1, 740, x2)
+
+inst_196:
+// rs1_val==6 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x1, x1, 744, x2)
+
+inst_197:
+// rs1_val==6 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x2e, x1, 748, x2)
+
+inst_198:
+// rs1_val==6 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x667, x1, 752, x2)
+
+inst_199:
+// rs1_val==6 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x334, x1, 756, x2)
+
+inst_200:
+// rs1_val==6 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x6, x1, 760, x2)
+
+inst_201:
+// rs1_val==6 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0xaab, x1, 764, x2)
+
+inst_202:
+// rs1_val==6 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x556, x1, 768, x2)
+
+inst_203:
+// rs1_val==6 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x4, x1, 772, x2)
+
+inst_204:
+// rs1_val==6 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x3e, x1, 776, x2)
+
+inst_205:
+// rs1_val==6 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x0, x1, 780, x2)
+
+inst_206:
+// rs1_val==6 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x2c, x1, 784, x2)
+
+inst_207:
+// rs1_val==6 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x665, x1, 788, x2)
+
+inst_208:
+// rs1_val==6 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x332, x1, 792, x2)
+
+inst_209:
+// rs1_val==6 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0xaa9, x1, 796, x2)
+
+inst_210:
+// rs1_val==6 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x554, x1, 800, x2)
+
+inst_211:
+// rs1_val==6 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x2, x1, 804, x2)
+
+inst_212:
+// rs1_val==6 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x3f, x1, 808, x2)
+
+inst_213:
+// rs1_val==6 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x2d, x1, 812, x2)
+
+inst_214:
+// rs1_val==6 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x666, x1, 816, x2)
+
+inst_215:
+// rs1_val==6 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x333, x1, 820, x2)
+
+inst_216:
+// rs1_val==6 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x5, x1, 824, x2)
+
+inst_217:
+// rs1_val==6 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0xaaa, x1, 828, x2)
+
+inst_218:
+// rs1_val==6 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x6, 0x555, x1, 832, x2)
+
+inst_219:
+// rs1_val==6 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x6, 0x3, x1, 836, x2)
+
+inst_220:
+// rs1_val==2863311531 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x40, x1, 840, x2)
+
+inst_221:
+// rs1_val==2863311531 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x1, x1, 844, x2)
+
+inst_222:
+// rs1_val==2863311531 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x2e, x1, 848, x2)
+
+inst_223:
+// rs1_val==2863311531 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x667, x1, 852, x2)
+
+inst_224:
+// rs1_val==2863311531 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x334, x1, 856, x2)
+
+inst_225:
+// rs1_val==2863311531 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x6, x1, 860, x2)
+
+inst_226:
+// rs1_val==2863311531 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaab, 0xaab, x1, 864, x2)
+
+inst_227:
+// rs1_val==2863311531 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x556, x1, 868, x2)
+
+inst_228:
+// rs1_val==2863311531 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x4, x1, 872, x2)
+
+inst_229:
+// rs1_val==2863311531 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x3e, x1, 876, x2)
+
+inst_230:
+// rs1_val==2863311531 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x0, x1, 880, x2)
+
+inst_231:
+// rs1_val==2863311531 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x2c, x1, 884, x2)
+
+inst_232:
+// rs1_val==2863311531 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x665, x1, 888, x2)
+
+inst_233:
+// rs1_val==2863311531 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x332, x1, 892, x2)
+
+inst_234:
+// rs1_val==2863311531 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaab, 0xaa9, x1, 896, x2)
+
+inst_235:
+// rs1_val==2863311531 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x554, x1, 900, x2)
+
+inst_236:
+// rs1_val==2863311531 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x2, x1, 904, x2)
+
+inst_237:
+// rs1_val==2863311531 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x3f, x1, 908, x2)
+
+inst_238:
+// rs1_val==2863311531 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x2d, x1, 912, x2)
+
+inst_239:
+// rs1_val==2863311531 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x666, x1, 916, x2)
+
+inst_240:
+// rs1_val==2863311531 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x333, x1, 920, x2)
+
+inst_241:
+// rs1_val==2863311531 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x5, x1, 924, x2)
+
+inst_242:
+// rs1_val==2863311531 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaab, 0xaaa, x1, 928, x2)
+
+inst_243:
+// rs1_val==2863311531 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x555, x1, 932, x2)
+
+inst_244:
+// rs1_val==2863311531 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaab;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaab, 0x3, x1, 936, x2)
+
+inst_245:
+// rs1_val==1431655766 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x40, x1, 940, x2)
+
+inst_246:
+// rs1_val==1431655766 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x1, x1, 944, x2)
+
+inst_247:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x2e, x1, 948, x2)
+
+inst_248:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x667, x1, 952, x2)
+
+inst_249:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x334, x1, 956, x2)
+
+inst_250:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x6, x1, 960, x2)
+
+inst_251:
+// rs1_val==1431655766 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555556, 0xaab, x1, 964, x2)
+
+inst_252:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x556, x1, 968, x2)
+
+inst_253:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x4, x1, 972, x2)
+
+inst_254:
+// rs1_val==1431655766 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x3e, x1, 976, x2)
+
+inst_255:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x0, x1, 980, x2)
+
+inst_256:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x2c, x1, 984, x2)
+
+inst_257:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x665, x1, 988, x2)
+
+inst_258:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x332, x1, 992, x2)
+
+inst_259:
+// rs1_val==1431655766 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555556, 0xaa9, x1, 996, x2)
+
+inst_260:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x554, x1, 1000, x2)
+
+inst_261:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x2, x1, 1004, x2)
+
+inst_262:
+// rs1_val==1431655766 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x3f, x1, 1008, x2)
+
+inst_263:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x2d, x1, 1012, x2)
+
+inst_264:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x666, x1, 1016, x2)
+
+inst_265:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x333, x1, 1020, x2)
+
+inst_266:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x5, x1, 1024, x2)
+
+inst_267:
+// rs1_val==1431655766 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555556, 0xaaa, x1, 1028, x2)
+
+inst_268:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x555, x1, 1032, x2)
+
+inst_269:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555556, 0x3, x1, 1036, x2)
+
+inst_270:
+// rs1_val==4 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x40, x1, 1040, x2)
+
+inst_271:
+// rs1_val==4 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4, 0x1, x1, 1044, x2)
+
+inst_272:
+// rs1_val==4 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x2e, x1, 1048, x2)
+
+inst_273:
+// rs1_val==4 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x667, x1, 1052, x2)
+
+inst_274:
+// rs1_val==4 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x334, x1, 1056, x2)
+
+inst_275:
+// rs1_val==4 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x6, x1, 1060, x2)
+
+inst_276:
+// rs1_val==4 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0xaab, x1, 1064, x2)
+
+inst_277:
+// rs1_val==4 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x556, x1, 1068, x2)
+
+inst_278:
+// rs1_val==4 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x3e, x1, 1072, x2)
+
+inst_279:
+// rs1_val==4 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4, 0x0, x1, 1076, x2)
+
+inst_280:
+// rs1_val==4 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x2c, x1, 1080, x2)
+
+inst_281:
+// rs1_val==4 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x665, x1, 1084, x2)
+
+inst_282:
+// rs1_val==4 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x332, x1, 1088, x2)
+
+inst_283:
+// rs1_val==4 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0xaa9, x1, 1092, x2)
+
+inst_284:
+// rs1_val==4 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x554, x1, 1096, x2)
+
+inst_285:
+// rs1_val==4 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4, 0x2, x1, 1100, x2)
+
+inst_286:
+// rs1_val==4 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x3f, x1, 1104, x2)
+
+inst_287:
+// rs1_val==4 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x2d, x1, 1108, x2)
+
+inst_288:
+// rs1_val==4 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x666, x1, 1112, x2)
+
+inst_289:
+// rs1_val==4 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x333, x1, 1116, x2)
+
+inst_290:
+// rs1_val==4 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x5, x1, 1120, x2)
+
+inst_291:
+// rs1_val==4 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0xaaa, x1, 1124, x2)
+
+inst_292:
+// rs1_val==4 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x4, 0x555, x1, 1128, x2)
+
+inst_293:
+// rs1_val==4 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x4, 0x3, x1, 1132, x2)
+
+inst_294:
+// rs1_val==65534 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x40, x1, 1136, x2)
+
+inst_295:
+// rs1_val==65534 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x1, x1, 1140, x2)
+
+inst_296:
+// rs1_val==65534 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x2e, x1, 1144, x2)
+
+inst_297:
+// rs1_val==65534 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x667, x1, 1148, x2)
+
+inst_298:
+// rs1_val==65534 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x334, x1, 1152, x2)
+
+inst_299:
+// rs1_val==65534 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x6, x1, 1156, x2)
+
+inst_300:
+// rs1_val==65534 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xfffe, 0xaab, x1, 1160, x2)
+
+inst_301:
+// rs1_val==65534 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x556, x1, 1164, x2)
+
+inst_302:
+// rs1_val==65534 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x4, x1, 1168, x2)
+
+inst_303:
+// rs1_val==65534 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x3e, x1, 1172, x2)
+
+inst_304:
+// rs1_val==65534 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x0, x1, 1176, x2)
+
+inst_305:
+// rs1_val==65534 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x2c, x1, 1180, x2)
+
+inst_306:
+// rs1_val==65534 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x665, x1, 1184, x2)
+
+inst_307:
+// rs1_val==65534 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x332, x1, 1188, x2)
+
+inst_308:
+// rs1_val==65534 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xfffe, 0xaa9, x1, 1192, x2)
+
+inst_309:
+// rs1_val==65534 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x554, x1, 1196, x2)
+
+inst_310:
+// rs1_val==65534 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x2, x1, 1200, x2)
+
+inst_311:
+// rs1_val==65534 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x3f, x1, 1204, x2)
+
+inst_312:
+// rs1_val==65534 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x2d, x1, 1208, x2)
+
+inst_313:
+// rs1_val==65534 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x666, x1, 1212, x2)
+
+inst_314:
+// rs1_val==65534 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x333, x1, 1216, x2)
+
+inst_315:
+// rs1_val==65534 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x5, x1, 1220, x2)
+
+inst_316:
+// rs1_val==65534 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xfffe, 0xaaa, x1, 1224, x2)
+
+inst_317:
+// rs1_val==65534 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x555, x1, 1228, x2)
+
+inst_318:
+// rs1_val==65534 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfffe;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfffe, 0x3, x1, 1232, x2)
+
+inst_319:
+// rs1_val==0 and imm_val==64, rs1_val == 0
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x40, x1, 1236, x2)
+
+inst_320:
+// rs1_val==0 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x1, x1, 1240, x2)
+
+inst_321:
+// rs1_val==0 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x2e, x1, 1244, x2)
+
+inst_322:
+// rs1_val==0 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x667, x1, 1248, x2)
+
+inst_323:
+// rs1_val==0 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x334, x1, 1252, x2)
+
+inst_324:
+// rs1_val==0 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x6, x1, 1256, x2)
+
+inst_325:
+// rs1_val==0 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0xaab, x1, 1260, x2)
+
+inst_326:
+// rs1_val==0 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x556, x1, 1264, x2)
+
+inst_327:
+// rs1_val==0 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x4, x1, 1268, x2)
+
+inst_328:
+// rs1_val==0 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x3e, x1, 1272, x2)
+
+inst_329:
+// rs1_val==0 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x0, 0x0, x1, 1276, x2)
+
+inst_330:
+// rs1_val==0 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x2c, x1, 1280, x2)
+
+inst_331:
+// rs1_val==0 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x665, x1, 1284, x2)
+
+inst_332:
+// rs1_val==0 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x332, x1, 1288, x2)
+
+inst_333:
+// rs1_val==0 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0xaa9, x1, 1292, x2)
+
+inst_334:
+// rs1_val==0 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x554, x1, 1296, x2)
+
+inst_335:
+// rs1_val==0 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x2, x1, 1300, x2)
+
+inst_336:
+// rs1_val==0 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x3f, x1, 1304, x2)
+
+inst_337:
+// rs1_val==0 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x2d, x1, 1308, x2)
+
+inst_338:
+// rs1_val==0 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x666, x1, 1312, x2)
+
+inst_339:
+// rs1_val==0 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x333, x1, 1316, x2)
+
+inst_340:
+// rs1_val==0 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x5, x1, 1320, x2)
+
+inst_341:
+// rs1_val==0 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0xaaa, x1, 1324, x2)
+
+inst_342:
+// rs1_val==0 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x555, x1, 1328, x2)
+
+inst_343:
+// rs1_val==0 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x0, 0x3, x1, 1332, x2)
+
+inst_344:
+// rs1_val==46339 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x40, x1, 1336, x2)
+
+inst_345:
+// rs1_val==46339 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x1, x1, 1340, x2)
+
+inst_346:
+// rs1_val==46339 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x2e, x1, 1344, x2)
+
+inst_347:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x667, x1, 1348, x2)
+
+inst_348:
+// rs1_val==46339 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x334, x1, 1352, x2)
+
+inst_349:
+// rs1_val==46339 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x6, x1, 1356, x2)
+
+inst_350:
+// rs1_val==46339 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb503, 0xaab, x1, 1360, x2)
+
+inst_351:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x556, x1, 1364, x2)
+
+inst_352:
+// rs1_val==46339 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x4, x1, 1368, x2)
+
+inst_353:
+// rs1_val==46339 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x3e, x1, 1372, x2)
+
+inst_354:
+// rs1_val==46339 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x0, x1, 1376, x2)
+
+inst_355:
+// rs1_val==46339 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x2c, x1, 1380, x2)
+
+inst_356:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x665, x1, 1384, x2)
+
+inst_357:
+// rs1_val==46339 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x332, x1, 1388, x2)
+
+inst_358:
+// rs1_val==46339 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb503, 0xaa9, x1, 1392, x2)
+
+inst_359:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x554, x1, 1396, x2)
+
+inst_360:
+// rs1_val==46339 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x2, x1, 1400, x2)
+
+inst_361:
+// rs1_val==46339 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x3f, x1, 1404, x2)
+
+inst_362:
+// rs1_val==46339 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x2d, x1, 1408, x2)
+
+inst_363:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x666, x1, 1412, x2)
+
+inst_364:
+// rs1_val==46339 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x333, x1, 1416, x2)
+
+inst_365:
+// rs1_val==46339 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x5, x1, 1420, x2)
+
+inst_366:
+// rs1_val==46339 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb503, 0xaaa, x1, 1424, x2)
+
+inst_367:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x555, x1, 1428, x2)
+
+inst_368:
+// rs1_val==46339 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb503, 0x3, x1, 1432, x2)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x40, x1, 1436, x2)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x1, x1, 1440, x2)
+
+inst_371:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x2e, x1, 1444, x2)
+
+inst_372:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x667, x1, 1448, x2)
+
+inst_373:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x334, x1, 1452, x2)
+
+inst_374:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x6, x1, 1456, x2)
+
+inst_375:
+// rs1_val==1717986917 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666665, 0xaab, x1, 1460, x2)
+
+inst_376:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x556, x1, 1464, x2)
+
+inst_377:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x4, x1, 1468, x2)
+
+inst_378:
+// rs1_val==1717986917 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x3e, x1, 1472, x2)
+
+inst_379:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x0, x1, 1476, x2)
+
+inst_380:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x2c, x1, 1480, x2)
+
+inst_381:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x665, x1, 1484, x2)
+
+inst_382:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x332, x1, 1488, x2)
+
+inst_383:
+// rs1_val==1717986917 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666665, 0xaa9, x1, 1492, x2)
+
+inst_384:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x554, x1, 1496, x2)
+
+inst_385:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x2, x1, 1500, x2)
+
+inst_386:
+// rs1_val==1717986917 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x3f, x1, 1504, x2)
+
+inst_387:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x2d, x1, 1508, x2)
+
+inst_388:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x666, x1, 1512, x2)
+
+inst_389:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x333, x1, 1516, x2)
+
+inst_390:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x5, x1, 1520, x2)
+
+inst_391:
+// rs1_val==1717986917 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666665, 0xaaa, x1, 1524, x2)
+
+inst_392:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x555, x1, 1528, x2)
+
+inst_393:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666665, 0x3, x1, 1532, x2)
+
+inst_394:
+// rs1_val==858993458 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x40, x1, 1536, x2)
+
+inst_395:
+// rs1_val==858993458 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x1, x1, 1540, x2)
+
+inst_396:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x2e, x1, 1544, x2)
+
+inst_397:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x667, x1, 1548, x2)
+
+inst_398:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x334, x1, 1552, x2)
+
+inst_399:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x6, x1, 1556, x2)
+
+inst_400:
+// rs1_val==858993458 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333332, 0xaab, x1, 1560, x2)
+
+inst_401:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x556, x1, 1564, x2)
+
+inst_402:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x4, x1, 1568, x2)
+
+inst_403:
+// rs1_val==858993458 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x3e, x1, 1572, x2)
+
+inst_404:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x0, x1, 1576, x2)
+
+inst_405:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x2c, x1, 1580, x2)
+
+inst_406:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x665, x1, 1584, x2)
+
+inst_407:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x332, x1, 1588, x2)
+
+inst_408:
+// rs1_val==858993458 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333332, 0xaa9, x1, 1592, x2)
+
+inst_409:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x554, x1, 1596, x2)
+
+inst_410:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x2, x1, 1600, x2)
+
+inst_411:
+// rs1_val==858993458 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x3f, x1, 1604, x2)
+
+inst_412:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x2d, x1, 1608, x2)
+
+inst_413:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x666, x1, 1612, x2)
+
+inst_414:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x333, x1, 1616, x2)
+
+inst_415:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x5, x1, 1620, x2)
+
+inst_416:
+// rs1_val==858993458 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333332, 0xaaa, x1, 1624, x2)
+
+inst_417:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x555, x1, 1628, x2)
+
+inst_418:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333332, 0x3, x1, 1632, x2)
+
+inst_419:
+// rs1_val==2863311529 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x40, x1, 1636, x2)
+
+inst_420:
+// rs1_val==2863311529 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x1, x1, 1640, x2)
+
+inst_421:
+// rs1_val==2863311529 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x2e, x1, 1644, x2)
+
+inst_422:
+// rs1_val==2863311529 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x667, x1, 1648, x2)
+
+inst_423:
+// rs1_val==2863311529 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x334, x1, 1652, x2)
+
+inst_424:
+// rs1_val==2863311529 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x6, x1, 1656, x2)
+
+inst_425:
+// rs1_val==2863311529 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaa9, 0xaab, x1, 1660, x2)
+
+inst_426:
+// rs1_val==2863311529 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x556, x1, 1664, x2)
+
+inst_427:
+// rs1_val==2863311529 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x4, x1, 1668, x2)
+
+inst_428:
+// rs1_val==2863311529 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x3e, x1, 1672, x2)
+
+inst_429:
+// rs1_val==2863311529 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x0, x1, 1676, x2)
+
+inst_430:
+// rs1_val==2863311529 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x2c, x1, 1680, x2)
+
+inst_431:
+// rs1_val==2863311529 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x665, x1, 1684, x2)
+
+inst_432:
+// rs1_val==2863311529 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x332, x1, 1688, x2)
+
+inst_433:
+// rs1_val==2863311529 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaa9, 0xaa9, x1, 1692, x2)
+
+inst_434:
+// rs1_val==2863311529 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x554, x1, 1696, x2)
+
+inst_435:
+// rs1_val==2863311529 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x2, x1, 1700, x2)
+
+inst_436:
+// rs1_val==2863311529 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x3f, x1, 1704, x2)
+
+inst_437:
+// rs1_val==2863311529 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x2d, x1, 1708, x2)
+
+inst_438:
+// rs1_val==2863311529 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x666, x1, 1712, x2)
+
+inst_439:
+// rs1_val==2863311529 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x333, x1, 1716, x2)
+
+inst_440:
+// rs1_val==2863311529 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x5, x1, 1720, x2)
+
+inst_441:
+// rs1_val==2863311529 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaa9, 0xaaa, x1, 1724, x2)
+
+inst_442:
+// rs1_val==2 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x555, x1, 1728, x2)
+
+inst_443:
+// rs1_val==2 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x3, x1, 1732, x2)
+
+inst_444:
+// rs1_val==65535 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x40, x1, 1736, x2)
+
+inst_445:
+// rs1_val==65535 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x1, x1, 1740, x2)
+
+inst_446:
+// rs1_val==65535 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x2e, x1, 1744, x2)
+
+inst_447:
+// rs1_val==65535 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x667, x1, 1748, x2)
+
+inst_448:
+// rs1_val==65535 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x334, x1, 1752, x2)
+
+inst_449:
+// rs1_val==65535 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x6, x1, 1756, x2)
+
+inst_450:
+// rs1_val==65535 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffff, 0xaab, x1, 1760, x2)
+
+inst_451:
+// rs1_val==65535 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x556, x1, 1764, x2)
+
+inst_452:
+// rs1_val==65535 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x4, x1, 1768, x2)
+
+inst_453:
+// rs1_val==65535 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x3e, x1, 1772, x2)
+
+inst_454:
+// rs1_val==65535 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x0, x1, 1776, x2)
+
+inst_455:
+// rs1_val==65535 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x2c, x1, 1780, x2)
+
+inst_456:
+// rs1_val==65535 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x665, x1, 1784, x2)
+
+inst_457:
+// rs1_val==65535 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x332, x1, 1788, x2)
+
+inst_458:
+// rs1_val==65535 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffff, 0xaa9, x1, 1792, x2)
+
+inst_459:
+// rs1_val==65535 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x554, x1, 1796, x2)
+
+inst_460:
+// rs1_val==65535 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x2, x1, 1800, x2)
+
+inst_461:
+// rs1_val==65535 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x3f, x1, 1804, x2)
+
+inst_462:
+// rs1_val==65535 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x2d, x1, 1808, x2)
+
+inst_463:
+// rs1_val==65535 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x666, x1, 1812, x2)
+
+inst_464:
+// rs1_val==65535 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x333, x1, 1816, x2)
+
+inst_465:
+// rs1_val==65535 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x5, x1, 1820, x2)
+
+inst_466:
+// rs1_val==65535 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xffff, 0xaaa, x1, 1824, x2)
+
+inst_467:
+// rs1_val==65535 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x555, x1, 1828, x2)
+
+inst_468:
+// rs1_val==65535 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffff;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffff, 0x3, x1, 1832, x2)
+
+inst_469:
+// rs1_val==46340 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x40, x1, 1836, x2)
+
+inst_470:
+// rs1_val==46340 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x1, x1, 1840, x2)
+
+inst_471:
+// rs1_val==46340 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x2e, x1, 1844, x2)
+
+inst_472:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x667, x1, 1848, x2)
+
+inst_473:
+// rs1_val==46340 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x334, x1, 1852, x2)
+
+inst_474:
+// rs1_val==46340 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x6, x1, 1856, x2)
+
+inst_475:
+// rs1_val==46340 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb504, 0xaab, x1, 1860, x2)
+
+inst_476:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x556, x1, 1864, x2)
+
+inst_477:
+// rs1_val==46340 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x4, x1, 1868, x2)
+
+inst_478:
+// rs1_val==46340 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x3e, x1, 1872, x2)
+
+inst_479:
+// rs1_val==46340 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x0, x1, 1876, x2)
+
+inst_480:
+// rs1_val==46340 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x2c, x1, 1880, x2)
+
+inst_481:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x665, x1, 1884, x2)
+
+inst_482:
+// rs1_val==46340 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x332, x1, 1888, x2)
+
+inst_483:
+// rs1_val==46340 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb504, 0xaa9, x1, 1892, x2)
+
+inst_484:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x554, x1, 1896, x2)
+
+inst_485:
+// rs1_val==46340 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x2, x1, 1900, x2)
+
+inst_486:
+// rs1_val==46340 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x3f, x1, 1904, x2)
+
+inst_487:
+// rs1_val==46340 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x2d, x1, 1908, x2)
+
+inst_488:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x666, x1, 1912, x2)
+
+inst_489:
+// rs1_val==46340 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x333, x1, 1916, x2)
+
+inst_490:
+// rs1_val==46340 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x5, x1, 1920, x2)
+
+inst_491:
+// rs1_val==46340 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xb504, 0xaaa, x1, 1924, x2)
+
+inst_492:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x555, x1, 1928, x2)
+
+inst_493:
+// rs1_val==46340 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xb504, 0x3, x1, 1932, x2)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x40, x1, 1936, x2)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x1, x1, 1940, x2)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x2e, x1, 1944, x2)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x667, x1, 1948, x2)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x334, x1, 1952, x2)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x6, x1, 1956, x2)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666666, 0xaab, x1, 1960, x2)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x556, x1, 1964, x2)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x4, x1, 1968, x2)
+
+inst_503:
+// rs1_val==1717986918 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x3e, x1, 1972, x2)
+
+inst_504:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x0, x1, 1976, x2)
+
+inst_505:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x2c, x1, 1980, x2)
+
+inst_506:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x665, x1, 1984, x2)
+
+inst_507:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x332, x1, 1988, x2)
+
+inst_508:
+// rs1_val==1717986918 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666666, 0xaa9, x1, 1992, x2)
+
+inst_509:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x554, x1, 1996, x2)
+
+inst_510:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x2, x1, 2000, x2)
+
+inst_511:
+// rs1_val==1717986918 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x3f, x1, 2004, x2)
+
+inst_512:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x2d, x1, 2008, x2)
+
+inst_513:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x666, x1, 2012, x2)
+
+inst_514:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x333, x1, 2016, x2)
+
+inst_515:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x5, x1, 2020, x2)
+
+inst_516:
+// rs1_val==1717986918 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x66666666, 0xaaa, x1, 2024, x2)
+
+inst_517:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x555, x1, 2028, x2)
+
+inst_518:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x66666666, 0x3, x1, 2032, x2)
+
+inst_519:
+// rs1_val==858993459 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x40, x1, 2036, x2)
+
+inst_520:
+// rs1_val==858993459 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x1, x1, 2040, x2)
+
+inst_521:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x2e, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_522:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x667, x1, 0, x2)
+
+inst_523:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x334, x1, 4, x2)
+
+inst_524:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x6, x1, 8, x2)
+
+inst_525:
+// rs1_val==858993459 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333333, 0xaab, x1, 12, x2)
+
+inst_526:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x556, x1, 16, x2)
+
+inst_527:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x4, x1, 20, x2)
+
+inst_528:
+// rs1_val==858993459 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x3e, x1, 24, x2)
+
+inst_529:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x0, x1, 28, x2)
+
+inst_530:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x2c, x1, 32, x2)
+
+inst_531:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x665, x1, 36, x2)
+
+inst_532:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x332, x1, 40, x2)
+
+inst_533:
+// rs1_val==858993459 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333333, 0xaa9, x1, 44, x2)
+
+inst_534:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x554, x1, 48, x2)
+
+inst_535:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x2, x1, 52, x2)
+
+inst_536:
+// rs1_val==858993459 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x3f, x1, 56, x2)
+
+inst_537:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x2d, x1, 60, x2)
+
+inst_538:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x666, x1, 64, x2)
+
+inst_539:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x333, x1, 68, x2)
+
+inst_540:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x5, x1, 72, x2)
+
+inst_541:
+// rs1_val==858993459 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x33333333, 0xaaa, x1, 76, x2)
+
+inst_542:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x555, x1, 80, x2)
+
+inst_543:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x33333333, 0x3, x1, 84, x2)
+
+inst_544:
+// rs1_val==5 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x40, x1, 88, x2)
+
+inst_545:
+// rs1_val==5 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x1, x1, 92, x2)
+
+inst_546:
+// rs1_val==5 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x2e, x1, 96, x2)
+
+inst_547:
+// rs1_val==5 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x667, x1, 100, x2)
+
+inst_548:
+// rs1_val==5 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x334, x1, 104, x2)
+
+inst_549:
+// rs1_val==5 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x6, x1, 108, x2)
+
+inst_550:
+// rs1_val==5 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0xaab, x1, 112, x2)
+
+inst_551:
+// rs1_val==5 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x556, x1, 116, x2)
+
+inst_552:
+// rs1_val==5 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x4, x1, 120, x2)
+
+inst_553:
+// rs1_val==5 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x3e, x1, 124, x2)
+
+inst_554:
+// rs1_val==5 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x0, x1, 128, x2)
+
+inst_555:
+// rs1_val==5 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x2c, x1, 132, x2)
+
+inst_556:
+// rs1_val==5 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x665, x1, 136, x2)
+
+inst_557:
+// rs1_val==5 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x332, x1, 140, x2)
+
+inst_558:
+// rs1_val==5 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0xaa9, x1, 144, x2)
+
+inst_559:
+// rs1_val==5 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x554, x1, 148, x2)
+
+inst_560:
+// rs1_val==5 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x2, x1, 152, x2)
+
+inst_561:
+// rs1_val==5 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x3f, x1, 156, x2)
+
+inst_562:
+// rs1_val==5 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x2d, x1, 160, x2)
+
+inst_563:
+// rs1_val==5 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x666, x1, 164, x2)
+
+inst_564:
+// rs1_val==5 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x333, x1, 168, x2)
+
+inst_565:
+// rs1_val==5 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x5, x1, 172, x2)
+
+inst_566:
+// rs1_val==5 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0xaaa, x1, 176, x2)
+
+inst_567:
+// rs1_val==5 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x5, 0x555, x1, 180, x2)
+
+inst_568:
+// rs1_val==5 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x5, 0x3, x1, 184, x2)
+
+inst_569:
+// rs1_val==2863311530 and imm_val==64, rs1_val == 2863311530
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x40, x1, 188, x2)
+
+inst_570:
+// rs1_val==2 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0xaa9, x1, 192, x2)
+
+inst_571:
+// rs1_val==2863311530 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x1, x1, 196, x2)
+
+inst_572:
+// rs1_val==2863311530 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x2e, x1, 200, x2)
+
+inst_573:
+// rs1_val==2863311530 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x667, x1, 204, x2)
+
+inst_574:
+// rs1_val==2863311530 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x334, x1, 208, x2)
+
+inst_575:
+// rs1_val==2863311530 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x6, x1, 212, x2)
+
+inst_576:
+// rs1_val==2863311530 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaaa, 0xaab, x1, 216, x2)
+
+inst_577:
+// rs1_val==2863311530 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x556, x1, 220, x2)
+
+inst_578:
+// rs1_val==2863311530 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x4, x1, 224, x2)
+
+inst_579:
+// rs1_val==2863311530 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x3e, x1, 228, x2)
+
+inst_580:
+// rs1_val==2863311530 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x0, x1, 232, x2)
+
+inst_581:
+// rs1_val==2863311530 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x2c, x1, 236, x2)
+
+inst_582:
+// rs1_val==2863311530 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x665, x1, 240, x2)
+
+inst_583:
+// rs1_val==2863311530 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x332, x1, 244, x2)
+
+inst_584:
+// rs1_val==2863311530 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaaa, 0xaa9, x1, 248, x2)
+
+inst_585:
+// rs1_val==2863311530 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x554, x1, 252, x2)
+
+inst_586:
+// rs1_val==2863311530 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x2, x1, 256, x2)
+
+inst_587:
+// rs1_val==2863311530 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x3f, x1, 260, x2)
+
+inst_588:
+// rs1_val==2863311530 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x2d, x1, 264, x2)
+
+inst_589:
+// rs1_val==2863311530 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x666, x1, 268, x2)
+
+inst_590:
+// rs1_val==2863311530 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x333, x1, 272, x2)
+
+inst_591:
+// rs1_val==2863311530 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x5, x1, 276, x2)
+
+inst_592:
+// rs1_val==2863311530 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0xaaaaaaaa, 0xaaa, x1, 280, x2)
+
+inst_593:
+// rs1_val==2863311530 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x555, x1, 284, x2)
+
+inst_594:
+// rs1_val==2863311530 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaaa;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaaa, 0x3, x1, 288, x2)
+
+inst_595:
+// rs1_val==1431655765 and imm_val==64, rs1_val == 1431655765
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x40, x1, 292, x2)
+
+inst_596:
+// rs1_val==1431655765 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x1, x1, 296, x2)
+
+inst_597:
+// rs1_val==1431655765 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x2e, x1, 300, x2)
+
+inst_598:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x667, x1, 304, x2)
+
+inst_599:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x334, x1, 308, x2)
+
+inst_600:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x6, x1, 312, x2)
+
+inst_601:
+// rs1_val==1431655765 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555555, 0xaab, x1, 316, x2)
+
+inst_602:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x556, x1, 320, x2)
+
+inst_603:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x4, x1, 324, x2)
+
+inst_604:
+// rs1_val==1431655765 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x3e, x1, 328, x2)
+
+inst_605:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x0, x1, 332, x2)
+
+inst_606:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x2c, x1, 336, x2)
+
+inst_607:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x665, x1, 340, x2)
+
+inst_608:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x332, x1, 344, x2)
+
+inst_609:
+// rs1_val==1431655765 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555555, 0xaa9, x1, 348, x2)
+
+inst_610:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x554, x1, 352, x2)
+
+inst_611:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x2, x1, 356, x2)
+
+inst_612:
+// rs1_val==1431655765 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x3f, x1, 360, x2)
+
+inst_613:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x2d, x1, 364, x2)
+
+inst_614:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x666, x1, 368, x2)
+
+inst_615:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x333, x1, 372, x2)
+
+inst_616:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x5, x1, 376, x2)
+
+inst_617:
+// rs1_val==1431655765 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555555, 0xaaa, x1, 380, x2)
+
+inst_618:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x555, x1, 384, x2)
+
+inst_619:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555555, 0x3, x1, 388, x2)
+
+inst_620:
+// rs1_val==3 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x40, x1, 392, x2)
+
+inst_621:
+// rs1_val==3 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x3, 0x1, x1, 396, x2)
+
+inst_622:
+// rs1_val==3 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x2e, x1, 400, x2)
+
+inst_623:
+// rs1_val==3 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x667, x1, 404, x2)
+
+inst_624:
+// rs1_val==3 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x334, x1, 408, x2)
+
+inst_625:
+// rs1_val==3 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x6, x1, 412, x2)
+
+inst_626:
+// rs1_val==3 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0xaab, x1, 416, x2)
+
+inst_627:
+// rs1_val==3 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x556, x1, 420, x2)
+
+inst_628:
+// rs1_val==3 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x4, x1, 424, x2)
+
+inst_629:
+// rs1_val==3 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x3e, x1, 428, x2)
+
+inst_630:
+// rs1_val==3 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x3, 0x0, x1, 432, x2)
+
+inst_631:
+// rs1_val==3 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x2c, x1, 436, x2)
+
+inst_632:
+// rs1_val==3 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x665, x1, 440, x2)
+
+inst_633:
+// rs1_val==3 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x332, x1, 444, x2)
+
+inst_634:
+// rs1_val==3 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0xaa9, x1, 448, x2)
+
+inst_635:
+// rs1_val==3 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x554, x1, 452, x2)
+
+inst_636:
+// rs1_val==3 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x3, 0x2, x1, 456, x2)
+
+inst_637:
+// rs1_val==3 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x3f, x1, 460, x2)
+
+inst_638:
+// rs1_val==3 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x2d, x1, 464, x2)
+
+inst_639:
+// rs1_val==3 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x666, x1, 468, x2)
+
+inst_640:
+// rs1_val==3 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x333, x1, 472, x2)
+
+inst_641:
+// rs1_val==3 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x5, x1, 476, x2)
+
+inst_642:
+// rs1_val==3 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0xaaa, x1, 480, x2)
+
+inst_643:
+// rs1_val==3 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x3, 0x555, x1, 484, x2)
+
+inst_644:
+// rs1_val==3 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x3, 0x3, x1, 488, x2)
+
+inst_645:
+// rs1_val==2863311529 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x555, x1, 492, x2)
+
+inst_646:
+// rs1_val==2863311529 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xaaaaaaa9;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xaaaaaaa9, 0x3, x1, 496, x2)
+
+inst_647:
+// rs1_val == (2**(xlen)-1), 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xffffffff;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xffffffff, 0x40, x1, 500, x2)
+
+inst_648:
+// rs1_val==1431655764 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x40, x1, 504, x2)
+
+inst_649:
+// rs1_val==1431655764 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x1, x1, 508, x2)
+
+inst_650:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x2e, x1, 512, x2)
+
+inst_651:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x667, x1, 516, x2)
+
+inst_652:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x334, x1, 520, x2)
+
+inst_653:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x6, x1, 524, x2)
+
+inst_654:
+// rs1_val==1431655764 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555554, 0xaab, x1, 528, x2)
+
+inst_655:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x556, x1, 532, x2)
+
+inst_656:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x4, x1, 536, x2)
+
+inst_657:
+// rs1_val==1431655764 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x3e, x1, 540, x2)
+
+inst_658:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x0, x1, 544, x2)
+
+inst_659:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x2c, x1, 548, x2)
+
+inst_660:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x665, x1, 552, x2)
+
+inst_661:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x332, x1, 556, x2)
+
+inst_662:
+// rs1_val==1431655764 and imm_val==2729, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0xaa9
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555554, 0xaa9, x1, 560, x2)
+
+inst_663:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x554, x1, 564, x2)
+
+inst_664:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x2, x1, 568, x2)
+
+inst_665:
+// rs1_val==1431655764 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x3f, x1, 572, x2)
+
+inst_666:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x2d, x1, 576, x2)
+
+inst_667:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x666, x1, 580, x2)
+
+inst_668:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x333, x1, 584, x2)
+
+inst_669:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x5, x1, 588, x2)
+
+inst_670:
+// rs1_val==1431655764 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x55555554, 0xaaa, x1, 592, x2)
+
+inst_671:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x555, x1, 596, x2)
+
+inst_672:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x55555554, 0x3, x1, 600, x2)
+
+inst_673:
+// rs1_val==2 and imm_val==64, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x40
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x40, x1, 604, x2)
+
+inst_674:
+// rs1_val==2 and imm_val==1, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x1
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x2, 0x1, x1, 608, x2)
+
+inst_675:
+// rs1_val==2 and imm_val==46, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x2e, x1, 612, x2)
+
+inst_676:
+// rs1_val==2 and imm_val==1639, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x667, x1, 616, x2)
+
+inst_677:
+// rs1_val==2 and imm_val==820, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x334, x1, 620, x2)
+
+inst_678:
+// rs1_val==2 and imm_val==6, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x6, x1, 624, x2)
+
+inst_679:
+// rs1_val==2 and imm_val==2731, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0xaab
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0xaab, x1, 628, x2)
+
+inst_680:
+// rs1_val==2 and imm_val==1366, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x556, x1, 632, x2)
+
+inst_681:
+// rs1_val==2 and imm_val==4, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x4, x1, 636, x2)
+
+inst_682:
+// rs1_val==2 and imm_val==62, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x3e
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x3e, x1, 640, x2)
+
+inst_683:
+// rs1_val==2 and imm_val==0, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x2, 0x0, x1, 644, x2)
+
+inst_684:
+// rs1_val==2 and imm_val==44, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x2c, x1, 648, x2)
+
+inst_685:
+// rs1_val==2 and imm_val==1637, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x665, x1, 652, x2)
+
+inst_686:
+// rs1_val==2 and imm_val==818, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x332, x1, 656, x2)
+
+inst_687:
+// rs1_val==2 and imm_val==1364, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x554, x1, 660, x2)
+
+inst_688:
+// rs1_val==2 and imm_val==2, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0x2, 0x2, x1, 664, x2)
+
+inst_689:
+// rs1_val==2 and imm_val==63, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x3f
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x3f, x1, 668, x2)
+
+inst_690:
+// rs1_val==2 and imm_val==45, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x2d, x1, 672, x2)
+
+inst_691:
+// rs1_val==2 and imm_val==1638, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x666, x1, 676, x2)
+
+inst_692:
+// rs1_val==2 and imm_val==819, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x333, x1, 680, x2)
+
+inst_693:
+// rs1_val==2 and imm_val==5, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0x5, x1, 684, x2)
+
+inst_694:
+// rs1_val==2 and imm_val==2730, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0x2;  immval:0xaaa
+TEST_IMM_OP( sltiu, x11, x10, 0x1, 0x2, 0xaaa, x1, 688, x2)
+
+inst_695:
+// rs1_val == 4261412863, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfdffffff;  immval:0xc
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfdffffff, 0xc, x1, 692, x2)
+
+inst_696:
+// rs1_val == 4294443007, 
+// opcode: sltiu ; op1:x10; dest:x11; op1val:0xfff7ffff;  immval:0xa
+TEST_IMM_OP( sltiu, x11, x10, 0x0, 0xfff7ffff, 0xa, x1, 696, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x14_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x14_1:
+    .fill 10*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 175*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S
new file mode 100644
index 000000000..b28398c3d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S
@@ -0,0 +1,3696 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sltu instruction of the RISC-V E extension for the sltu covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sltu)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x12, rs2==x2, rd==x7, rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0, rs1_val > 0 and rs2_val > 0, rs2_val == 16384
+// opcode: sltu ; op1:x12; op2:x2; dest:x7; op1val:0xaaaaaaab;  op2val:0x4000
+TEST_RR_OP(sltu, x7, x12, x2, 0x0, 0xaaaaaaab, 0x4000, x4, 0, x9)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x11, rs2==x7, rd==x11, rs2_val == 2147483647, rs1_val == 262144
+// opcode: sltu ; op1:x11; op2:x7; dest:x11; op1val:0x40000;  op2val:0x7fffffff
+TEST_RR_OP(sltu, x11, x11, x7, 0x1, 0x40000, 0x7fffffff, x4, 4, x9)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x6, rs2==x10, rd==x10, rs2_val == 3221225471, rs1_val == 131072
+// opcode: sltu ; op1:x6; op2:x10; dest:x10; op1val:0x20000;  op2val:0xbfffffff
+TEST_RR_OP(sltu, x10, x6, x10, 0x1, 0x20000, 0xbfffffff, x4, 8, x9)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x14, rs2==x14, rd==x3, rs2_val == 3758096383, rs1_val == 4261412863
+// opcode: sltu ; op1:x14; op2:x14; dest:x3; op1val:0xfdffffff;  op2val:0xfdffffff
+TEST_RR_OP(sltu, x3, x14, x14, 0x0, 0xfdffffff, 0xfdffffff, x4, 12, x9)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x5, rs2==x5, rd==x5, rs2_val == 4026531839, rs1_val == 0
+// opcode: sltu ; op1:x5; op2:x5; dest:x5; op1val:0x0;  op2val:0x0
+TEST_RR_OP(sltu, x5, x5, x5, 0x0, 0x0, 0x0, x4, 16, x9)
+
+inst_5:
+// rs1==x8, rs2==x1, rd==x0, rs2_val == 4160749567, 
+// opcode: sltu ; op1:x8; op2:x1; dest:x0; op1val:0x0;  op2val:0xf7ffffff
+TEST_RR_OP(sltu, x0, x8, x1, 0, 0x0, 0xf7ffffff, x4, 20, x9)
+
+inst_6:
+// rs1==x3, rs2==x9, rd==x13, rs2_val == 4227858431, 
+// opcode: sltu ; op1:x3; op2:x9; dest:x13; op1val:0x0;  op2val:0xfbffffff
+TEST_RR_OP(sltu, x13, x3, x9, 0x1, 0x0, 0xfbffffff, x4, 24, x7)
+RVTEST_SIGBASE( x5,signature_x5_0)
+
+inst_7:
+// rs1==x9, rs2==x3, rd==x2, rs2_val == 4261412863, rs1_val == 4294967167
+// opcode: sltu ; op1:x9; op2:x3; dest:x2; op1val:0xffffff7f;  op2val:0xfdffffff
+TEST_RR_OP(sltu, x2, x9, x3, 0x0, 0xffffff7f, 0xfdffffff, x5, 0, x7)
+
+inst_8:
+// rs1==x15, rs2==x13, rd==x6, rs2_val == 4278190079, rs1_val == 4294950911
+// opcode: sltu ; op1:x15; op2:x13; dest:x6; op1val:0xffffbfff;  op2val:0xfeffffff
+TEST_RR_OP(sltu, x6, x15, x13, 0x0, 0xffffbfff, 0xfeffffff, x5, 4, x7)
+
+inst_9:
+// rs1==x13, rs2==x0, rd==x12, rs2_val == 4286578687, rs1_val == 4026531839
+// opcode: sltu ; op1:x13; op2:x0; dest:x12; op1val:0xefffffff;  op2val:0x0
+TEST_RR_OP(sltu, x12, x13, x0, 0x0, 0xefffffff, 0x0, x5, 8, x7)
+
+inst_10:
+// rs1==x1, rs2==x11, rd==x14, rs2_val == 4290772991, rs1_val == 4294901759
+// opcode: sltu ; op1:x1; op2:x11; dest:x14; op1val:0xfffeffff;  op2val:0xffbfffff
+TEST_RR_OP(sltu, x14, x1, x11, 0x0, 0xfffeffff, 0xffbfffff, x5, 12, x7)
+
+inst_11:
+// rs1==x2, rs2==x8, rd==x4, rs2_val == 4292870143, rs1_val == 8
+// opcode: sltu ; op1:x2; op2:x8; dest:x4; op1val:0x8;  op2val:0xffdfffff
+TEST_RR_OP(sltu, x4, x2, x8, 0x1, 0x8, 0xffdfffff, x5, 16, x3)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_12:
+// rs1==x7, rs2==x4, rd==x8, rs2_val == 4293918719, rs1_val == 2863311530
+// opcode: sltu ; op1:x7; op2:x4; dest:x8; op1val:0xaaaaaaaa;  op2val:0xffefffff
+TEST_RR_OP(sltu, x8, x7, x4, 0x1, 0xaaaaaaaa, 0xffefffff, x2, 0, x3)
+
+inst_13:
+// rs1==x10, rs2==x12, rd==x15, rs2_val == 4294443007, 
+// opcode: sltu ; op1:x10; op2:x12; dest:x15; op1val:0xb504;  op2val:0xfff7ffff
+TEST_RR_OP(sltu, x15, x10, x12, 0x1, 0xb504, 0xfff7ffff, x2, 4, x3)
+
+inst_14:
+// rs1==x4, rs2==x15, rd==x9, rs2_val == 4294705151, rs1_val == 2048
+// opcode: sltu ; op1:x4; op2:x15; dest:x9; op1val:0x800;  op2val:0xfffbffff
+TEST_RR_OP(sltu, x9, x4, x15, 0x1, 0x800, 0xfffbffff, x2, 8, x3)
+
+inst_15:
+// rs1==x0, rs2==x6, rd==x1, rs2_val == 4294836223, 
+// opcode: sltu ; op1:x0; op2:x6; dest:x1; op1val:0x0;  op2val:0xfffdffff
+TEST_RR_OP(sltu, x1, x0, x6, 0x1, 0x0, 0xfffdffff, x2, 12, x3)
+
+inst_16:
+// rs2_val == 4294901759, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0xfffeffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xf, 0xfffeffff, x2, 16, x3)
+
+inst_17:
+// rs2_val == 4294934527, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0xffff7fff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xf, 0xffff7fff, x2, 20, x1)
+
+inst_18:
+// rs2_val == 4294950911, rs1_val == 1431655765
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffffbfff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0xffffbfff, x2, 24, x1)
+
+inst_19:
+// rs2_val == 4294959103, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xffffdfff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0xffffdfff, x2, 28, x1)
+
+inst_20:
+// rs2_val == 4294963199, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xffffefff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0xffffefff, x2, 32, x1)
+
+inst_21:
+// rs2_val == 4294965247, rs1_val == 4293918719
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffefffff;  op2val:0xfffff7ff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffefffff, 0xfffff7ff, x2, 36, x1)
+
+inst_22:
+// rs2_val == 4294966271, rs1_val == 524288
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0xfffffbff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x80000, 0xfffffbff, x2, 40, x1)
+
+inst_23:
+// rs2_val == 4294966783, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffffdff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0xfffffdff, x2, 44, x1)
+
+inst_24:
+// rs2_val == 4294967039, rs1_val == 4286578687
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xff7fffff;  op2val:0xfffffeff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xff7fffff, 0xfffffeff, x2, 48, x1)
+
+inst_25:
+// rs2_val == 4294967167, rs1_val == 4294966271
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffbff;  op2val:0xffffff7f
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffffbff, 0xffffff7f, x2, 52, x1)
+
+inst_26:
+// rs2_val == 4294967231, rs1_val == 64
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0xffffffbf
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x40, 0xffffffbf, x2, 56, x1)
+
+inst_27:
+// rs2_val == 4294967263, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0xffffffdf
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x800, 0xffffffdf, x2, 60, x1)
+
+inst_28:
+// rs2_val == 4294967279, rs1_val == 4294965247
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ff;  op2val:0xffffffef
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffff7ff, 0xffffffef, x2, 64, x1)
+
+inst_29:
+// rs2_val == 4294967287, rs1_val == 4194304
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xfffffff7
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x400000, 0xfffffff7, x2, 68, x1)
+
+inst_30:
+// rs2_val == 4294967291, rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0, rs1_val == 4294967291
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffb;  op2val:0xfffffffb
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffffb, 0xfffffffb, x2, 72, x1)
+
+inst_31:
+// rs2_val == 4294967293, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffffffd
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0xfffffffd, x2, 76, x1)
+
+inst_32:
+// rs2_val == 4294967294, rs1_val == 536870912
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0xfffffffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x20000000, 0xfffffffe, x2, 80, x1)
+
+inst_33:
+// rs1_val == 2147483647, rs2_val == 536870912
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x20000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x7fffffff, 0x20000000, x2, 84, x1)
+
+inst_34:
+// rs1_val == 3221225471, rs2_val == 0
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffff;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xbfffffff, 0x0, x2, 88, x1)
+
+inst_35:
+// rs1_val == 3758096383, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffff;  op2val:0x12
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xdfffffff, 0x12, x2, 92, x1)
+
+inst_36:
+// rs1_val == 4160749567, rs2_val == 2863311530
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xf7ffffff;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xf7ffffff, 0xaaaaaaaa, x2, 96, x1)
+
+inst_37:
+// rs1_val == 4227858431, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfbffffff;  op2val:0x20000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfbffffff, 0x20000000, x2, 100, x1)
+
+inst_38:
+// rs1_val == 4278190079, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfeffffff;  op2val:0xfffffdff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfeffffff, 0xfffffdff, x2, 104, x1)
+
+inst_39:
+// rs1_val == 4290772991, rs2_val == 65536
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffff;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffbfffff, 0x10000, x2, 108, x1)
+
+inst_40:
+// rs1_val == 4292870143, rs2_val == 2097152
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffdfffff;  op2val:0x200000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffdfffff, 0x200000, x2, 112, x1)
+
+inst_41:
+// rs1_val == 4294443007, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfff7ffff;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfff7ffff, 0x3, x2, 116, x1)
+
+inst_42:
+// rs1_val == 4294705151, rs2_val == 16
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffbffff;  op2val:0x10
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffbffff, 0x10, x2, 120, x1)
+
+inst_43:
+// rs1_val == 4294836223, rs2_val == 32768
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffff;  op2val:0x8000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffdffff, 0x8000, x2, 124, x1)
+
+inst_44:
+// rs1_val == 4294934527, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fff;  op2val:0xfffffffd
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff7fff, 0xfffffffd, x2, 128, x1)
+
+inst_45:
+// rs1_val == 4294959103, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0x8000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffdfff, 0x8000, x2, 132, x1)
+
+inst_46:
+// rs1_val == 4294963199, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffefff;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffefff, 0xaaaaaaa9, x2, 136, x1)
+
+inst_47:
+// rs1_val == 4294966783, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdff;  op2val:0xfffffffb
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffffdff, 0xfffffffb, x2, 140, x1)
+
+inst_48:
+// rs1_val == 4294967039, rs2_val == 4194304
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffeff;  op2val:0x400000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffeff, 0x400000, x2, 144, x1)
+
+inst_49:
+// rs1_val == 4294967231, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbf;  op2val:0xa
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffffbf, 0xa, x2, 148, x1)
+
+inst_50:
+// rs1_val == 4294967263, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdf;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffffdf, 0x5, x2, 152, x1)
+
+inst_51:
+// rs1_val == 4294967279, rs2_val == 2048
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffef;  op2val:0x800
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffffef, 0x800, x2, 156, x1)
+
+inst_52:
+// rs1_val == 4294967287, rs2_val == 33554432
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0x2000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffff7, 0x2000000, x2, 160, x1)
+
+inst_53:
+// rs1_val == 4294967293, rs2_val == 8388608
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffd;  op2val:0x800000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffffd, 0x800000, x2, 164, x1)
+
+inst_54:
+// rs1_val == 4294967294, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffe;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffffe, 0x6, x2, 168, x1)
+
+inst_55:
+// rs2_val == 2147483648, rs1_val == 2
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x80000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x80000000, x2, 172, x1)
+
+inst_56:
+// rs2_val == 1073741824, rs1_val == 4
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x40000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x40000000, x2, 176, x1)
+
+inst_57:
+// rs2_val == 268435456, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xd;  op2val:0x10000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xd, 0x10000000, x2, 180, x1)
+
+inst_58:
+// rs2_val == 134217728, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x8000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x8000000, x2, 184, x1)
+
+inst_59:
+// rs2_val == 67108864, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x4000000, x2, 188, x1)
+
+inst_60:
+// rs2_val == 16777216, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffe;  op2val:0x1000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffffe, 0x1000000, x2, 192, x1)
+
+inst_61:
+// rs2_val == 1048576, rs1_val == 16
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x100000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10, 0x100000, x2, 196, x1)
+
+inst_62:
+// rs2_val == 524288, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffdfffff;  op2val:0x80000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffdfffff, 0x80000, x2, 200, x1)
+
+inst_63:
+// rs2_val == 262144, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x40000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x40000, x2, 204, x1)
+
+inst_64:
+// rs2_val == 131072, rs1_val == 2097152
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x20000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x200000, 0x20000, x2, 208, x1)
+
+inst_65:
+// rs2_val == 8192, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffbffff;  op2val:0x2000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffbffff, 0x2000, x2, 212, x1)
+
+inst_66:
+// rs2_val == 4096, rs1_val == 268435456
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x1000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000000, 0x1000, x2, 216, x1)
+
+inst_67:
+// rs2_val == 1024, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x400
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x400, x2, 220, x1)
+
+inst_68:
+// rs2_val == 512, rs1_val == 1048576
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x200
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x100000, 0x200, x2, 224, x1)
+
+inst_69:
+// rs2_val == 256, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x100
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x100, x2, 228, x1)
+
+inst_70:
+// rs2_val == 128, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7;  op2val:0x80
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffffff7, 0x80, x2, 232, x1)
+
+inst_71:
+// rs2_val == 64, rs1_val == 2147483648
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x80000000;  op2val:0x40
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x80000000, 0x40, x2, 236, x1)
+
+inst_72:
+// rs2_val == 32, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfff;  op2val:0x20
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffdfff, 0x20, x2, 240, x1)
+
+inst_73:
+// rs2_val == 8, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x8
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000000, 0x8, x2, 244, x1)
+
+inst_74:
+// rs2_val == 4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x8, 0x4, x2, 248, x1)
+
+inst_75:
+// rs2_val == 2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xa;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xa, 0x2, x2, 252, x1)
+
+inst_76:
+// rs2_val == 1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xa;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xa, 0x1, x2, 256, x1)
+
+inst_77:
+// rs1_val == 1073741824, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x2000000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x40000000, 0x2000000, x2, 260, x1)
+
+inst_78:
+// rs1_val == 134217728, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x200
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x8000000, 0x200, x2, 264, x1)
+
+inst_79:
+// rs1_val == 67108864, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4000000, 0xfffe, x2, 268, x1)
+
+inst_80:
+// rs1_val == 33554432, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x2000000, 0x4, x2, 272, x1)
+
+inst_81:
+// rs1_val == 16777216, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1000000, 0x33333334, x2, 276, x1)
+
+inst_82:
+// rs1_val == 8388608, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x80000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x800000, 0x80000, x2, 280, x1)
+
+inst_83:
+// rs1_val == 65536, rs1_val==65536 and rs2_val==0
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x0, x2, 284, x1)
+
+inst_84:
+// rs1_val == 32768, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x8000, 0xaaaaaaa9, x2, 288, x1)
+
+inst_85:
+// rs1_val == 16384, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4000, 0x4, x2, 292, x1)
+
+inst_86:
+// rs1_val == 8192, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x20
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x2000, 0x20, x2, 296, x1)
+
+inst_87:
+// rs1_val == 4096, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0xfffffbff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1000, 0xfffffbff, x2, 300, x1)
+
+inst_88:
+// rs1_val == 1024, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0xbfffffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x400, 0xbfffffff, x2, 304, x1)
+
+inst_89:
+// rs1_val == 512, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x200, 0x10000, x2, 308, x1)
+
+inst_90:
+// rs1_val == 256, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0xf7ffffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x100, 0xf7ffffff, x2, 312, x1)
+
+inst_91:
+// rs1_val == 128, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x80, 0x10000, x2, 316, x1)
+
+inst_92:
+// rs1_val == 32, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0xefffffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x20, 0xefffffff, x2, 320, x1)
+
+inst_93:
+// rs1_val == 1, rs1_val==1 and rs2_val==46340
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xb504, x2, 324, x1)
+
+inst_94:
+// rs1_val==65536 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x10000, x2, 328, x1)
+
+inst_95:
+// rs1_val==65536 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x1, x2, 332, x1)
+
+inst_96:
+// rs1_val==65536 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0xb505, x2, 336, x1)
+
+inst_97:
+// rs1_val==65536 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x66666667, x2, 340, x1)
+
+inst_98:
+// rs1_val==65536 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x33333334, x2, 344, x1)
+
+inst_99:
+// rs1_val==65536 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x6, x2, 348, x1)
+
+inst_100:
+// rs1_val==65536 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0xaaaaaaab, x2, 352, x1)
+
+inst_101:
+// rs1_val==65536 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x55555556, x2, 356, x1)
+
+inst_102:
+// rs1_val==65536 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x4, x2, 360, x1)
+
+inst_103:
+// rs1_val==65536 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0xfffe, x2, 364, x1)
+
+inst_104:
+// rs1_val==65536 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0xb503, x2, 368, x1)
+
+inst_105:
+// rs1_val==65536 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x66666665, x2, 372, x1)
+
+inst_106:
+// rs1_val==65536 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x33333332, x2, 376, x1)
+
+inst_107:
+// rs1_val==65536 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0xaaaaaaa9, x2, 380, x1)
+
+inst_108:
+// rs1_val==65536 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x55555554, x2, 384, x1)
+
+inst_109:
+// rs1_val==65536 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x2, x2, 388, x1)
+
+inst_110:
+// rs1_val==65536 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0xffff, x2, 392, x1)
+
+inst_111:
+// rs1_val==65536 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0xb504, x2, 396, x1)
+
+inst_112:
+// rs1_val==65536 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x66666666, x2, 400, x1)
+
+inst_113:
+// rs1_val==65536 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x33333333, x2, 404, x1)
+
+inst_114:
+// rs1_val==65536 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x5, x2, 408, x1)
+
+inst_115:
+// rs1_val==65536 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0xaaaaaaaa, x2, 412, x1)
+
+inst_116:
+// rs1_val==65536 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x10000, 0x55555555, x2, 416, x1)
+
+inst_117:
+// rs1_val==65536 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x10000, 0x3, x2, 420, x1)
+
+inst_118:
+// rs1_val==1 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x10000, x2, 424, x1)
+
+inst_119:
+// rs1_val==1 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x1, 0x1, x2, 428, x1)
+
+inst_120:
+// rs1_val==1 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xb505, x2, 432, x1)
+
+inst_121:
+// rs1_val==1 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x66666667, x2, 436, x1)
+
+inst_122:
+// rs1_val==1 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x33333334, x2, 440, x1)
+
+inst_123:
+// rs1_val==1 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x6, x2, 444, x1)
+
+inst_124:
+// rs1_val==1 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaab, x2, 448, x1)
+
+inst_125:
+// rs1_val==1 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x55555556, x2, 452, x1)
+
+inst_126:
+// rs1_val==1 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x4, x2, 456, x1)
+
+inst_127:
+// rs1_val==1 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xfffe, x2, 460, x1)
+
+inst_128:
+// rs1_val==1 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x1, 0x0, x2, 464, x1)
+
+inst_129:
+// rs1_val==1 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xb503, x2, 468, x1)
+
+inst_130:
+// rs1_val==1 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x66666665, x2, 472, x1)
+
+inst_131:
+// rs1_val==1 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x33333332, x2, 476, x1)
+
+inst_132:
+// rs1_val==1 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaa9, x2, 480, x1)
+
+inst_133:
+// rs1_val==1 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x55555554, x2, 484, x1)
+
+inst_134:
+// rs1_val==1 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x2, x2, 488, x1)
+
+inst_135:
+// rs1_val==1 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xffff, x2, 492, x1)
+
+inst_136:
+// rs1_val==1 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x66666666, x2, 496, x1)
+
+inst_137:
+// rs1_val==1 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x33333333, x2, 500, x1)
+
+inst_138:
+// rs1_val==1 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x5, x2, 504, x1)
+
+inst_139:
+// rs1_val==1 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0xaaaaaaaa, x2, 508, x1)
+
+inst_140:
+// rs1_val==1 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x55555555, x2, 512, x1)
+
+inst_141:
+// rs1_val==1 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x1, 0x3, x2, 516, x1)
+
+inst_142:
+// rs1_val==46341 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x10000, x2, 520, x1)
+
+inst_143:
+// rs1_val==46341 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x1, x2, 524, x1)
+
+inst_144:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0xb505, x2, 528, x1)
+
+inst_145:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x66666667, x2, 532, x1)
+
+inst_146:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x33333334, x2, 536, x1)
+
+inst_147:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x6, x2, 540, x1)
+
+inst_148:
+// rs1_val==46341 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0xaaaaaaab, x2, 544, x1)
+
+inst_149:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x55555556, x2, 548, x1)
+
+inst_150:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x4, x2, 552, x1)
+
+inst_151:
+// rs1_val==46341 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0xfffe, x2, 556, x1)
+
+inst_152:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x0, x2, 560, x1)
+
+inst_153:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0xb503, x2, 564, x1)
+
+inst_154:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x66666665, x2, 568, x1)
+
+inst_155:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x33333332, x2, 572, x1)
+
+inst_156:
+// rs1_val==46341 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0xaaaaaaa9, x2, 576, x1)
+
+inst_157:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x55555554, x2, 580, x1)
+
+inst_158:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x2, x2, 584, x1)
+
+inst_159:
+// rs1_val==46341 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0xffff, x2, 588, x1)
+
+inst_160:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0xb504, x2, 592, x1)
+
+inst_161:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x66666666, x2, 596, x1)
+
+inst_162:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x33333333, x2, 600, x1)
+
+inst_163:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x5, x2, 604, x1)
+
+inst_164:
+// rs1_val==46341 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0xaaaaaaaa, x2, 608, x1)
+
+inst_165:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb505, 0x55555555, x2, 612, x1)
+
+inst_166:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb505, 0x3, x2, 616, x1)
+
+inst_167:
+// rs1_val==1717986919 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x10000, x2, 620, x1)
+
+inst_168:
+// rs1_val==1717986919 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x1, x2, 624, x1)
+
+inst_169:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0xb505, x2, 628, x1)
+
+inst_170:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x2, 632, x1)
+
+inst_171:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x33333334, x2, 636, x1)
+
+inst_172:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x6, x2, 640, x1)
+
+inst_173:
+// rs1_val==1717986919 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666667, 0xaaaaaaab, x2, 644, x1)
+
+inst_174:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x55555556, x2, 648, x1)
+
+inst_175:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x4, x2, 652, x1)
+
+inst_176:
+// rs1_val==1717986919 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0xfffe, x2, 656, x1)
+
+inst_177:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x0, x2, 660, x1)
+
+inst_178:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0xb503, x2, 664, x1)
+
+inst_179:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x66666665, x2, 668, x1)
+
+inst_180:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x33333332, x2, 672, x1)
+
+inst_181:
+// rs1_val==1717986919 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666667, 0xaaaaaaa9, x2, 676, x1)
+
+inst_182:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x55555554, x2, 680, x1)
+
+inst_183:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x2, x2, 684, x1)
+
+inst_184:
+// rs1_val==1717986919 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0xffff, x2, 688, x1)
+
+inst_185:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0xb504, x2, 692, x1)
+
+inst_186:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x66666666, x2, 696, x1)
+
+inst_187:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x33333333, x2, 700, x1)
+
+inst_188:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x5, x2, 704, x1)
+
+inst_189:
+// rs1_val==1717986919 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666667, 0xaaaaaaaa, x2, 708, x1)
+
+inst_190:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x55555555, x2, 712, x1)
+
+inst_191:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666667, 0x3, x2, 716, x1)
+
+inst_192:
+// rs1_val==858993460 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x10000, x2, 720, x1)
+
+inst_193:
+// rs1_val==858993460 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x1, x2, 724, x1)
+
+inst_194:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0xb505, x2, 728, x1)
+
+inst_195:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x66666667, x2, 732, x1)
+
+inst_196:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x2, 736, x1)
+
+inst_197:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x6, x2, 740, x1)
+
+inst_198:
+// rs1_val==858993460 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0xaaaaaaab, x2, 744, x1)
+
+inst_199:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x55555556, x2, 748, x1)
+
+inst_200:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x4, x2, 752, x1)
+
+inst_201:
+// rs1_val==858993460 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0xfffe, x2, 756, x1)
+
+inst_202:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x0, x2, 760, x1)
+
+inst_203:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0xb503, x2, 764, x1)
+
+inst_204:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x66666665, x2, 768, x1)
+
+inst_205:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x33333332, x2, 772, x1)
+
+inst_206:
+// rs1_val==858993460 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0xaaaaaaa9, x2, 776, x1)
+
+inst_207:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x55555554, x2, 780, x1)
+
+inst_208:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x2, x2, 784, x1)
+
+inst_209:
+// rs1_val==858993460 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0xffff, x2, 788, x1)
+
+inst_210:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0xb504, x2, 792, x1)
+
+inst_211:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x66666666, x2, 796, x1)
+
+inst_212:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x33333333, x2, 800, x1)
+
+inst_213:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x5, x2, 804, x1)
+
+inst_214:
+// rs1_val==858993460 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0xaaaaaaaa, x2, 808, x1)
+
+inst_215:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333334, 0x55555555, x2, 812, x1)
+
+inst_216:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333334, 0x3, x2, 816, x1)
+
+inst_217:
+// rs1_val==6 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x10000, x2, 820, x1)
+
+inst_218:
+// rs1_val==6 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x1, x2, 824, x1)
+
+inst_219:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xb505, x2, 828, x1)
+
+inst_220:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x66666667, x2, 832, x1)
+
+inst_221:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x33333334, x2, 836, x1)
+
+inst_222:
+// rs1_val==6 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x6, x2, 840, x1)
+
+inst_223:
+// rs1_val==6 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xaaaaaaab, x2, 844, x1)
+
+inst_224:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x55555556, x2, 848, x1)
+
+inst_225:
+// rs1_val==6 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x4, x2, 852, x1)
+
+inst_226:
+// rs1_val==6 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xfffe, x2, 856, x1)
+
+inst_227:
+// rs1_val==6 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x0, x2, 860, x1)
+
+inst_228:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xb503, x2, 864, x1)
+
+inst_229:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x66666665, x2, 868, x1)
+
+inst_230:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x33333332, x2, 872, x1)
+
+inst_231:
+// rs1_val==6 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xaaaaaaa9, x2, 876, x1)
+
+inst_232:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x55555554, x2, 880, x1)
+
+inst_233:
+// rs1_val==6 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x2, x2, 884, x1)
+
+inst_234:
+// rs1_val==6 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xffff, x2, 888, x1)
+
+inst_235:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xb504, x2, 892, x1)
+
+inst_236:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x66666666, x2, 896, x1)
+
+inst_237:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x33333333, x2, 900, x1)
+
+inst_238:
+// rs1_val==6 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x5, x2, 904, x1)
+
+inst_239:
+// rs1_val==6 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0xaaaaaaaa, x2, 908, x1)
+
+inst_240:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x6, 0x55555555, x2, 912, x1)
+
+inst_241:
+// rs1_val==6 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x6, 0x3, x2, 916, x1)
+
+inst_242:
+// rs1_val==2863311531 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x10000, x2, 920, x1)
+
+inst_243:
+// rs1_val==2863311531 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x1, x2, 924, x1)
+
+inst_244:
+// rs1_val==2863311531 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xb505, x2, 928, x1)
+
+inst_245:
+// rs1_val==2863311531 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x66666667, x2, 932, x1)
+
+inst_246:
+// rs1_val==2863311531 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x33333334, x2, 936, x1)
+
+inst_247:
+// rs1_val==2863311531 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x6, x2, 940, x1)
+
+inst_248:
+// rs1_val==2863311531 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xaaaaaaab, x2, 944, x1)
+
+inst_249:
+// rs1_val==2863311531 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x55555556, x2, 948, x1)
+
+inst_250:
+// rs1_val==2863311531 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x4, x2, 952, x1)
+
+inst_251:
+// rs1_val==2863311531 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xfffe, x2, 956, x1)
+
+inst_252:
+// rs1_val==2863311531 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x0, x2, 960, x1)
+
+inst_253:
+// rs1_val==2863311531 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xb503, x2, 964, x1)
+
+inst_254:
+// rs1_val==2863311531 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x66666665, x2, 968, x1)
+
+inst_255:
+// rs1_val==2863311531 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x33333332, x2, 972, x1)
+
+inst_256:
+// rs1_val==2863311531 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xaaaaaaa9, x2, 976, x1)
+
+inst_257:
+// rs1_val==2863311531 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x55555554, x2, 980, x1)
+
+inst_258:
+// rs1_val==2863311531 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x2, x2, 984, x1)
+
+inst_259:
+// rs1_val==2863311531 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xffff, x2, 988, x1)
+
+inst_260:
+// rs1_val==2863311531 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xb504, x2, 992, x1)
+
+inst_261:
+// rs1_val==2863311531 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x66666666, x2, 996, x1)
+
+inst_262:
+// rs1_val==2863311531 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x33333333, x2, 1000, x1)
+
+inst_263:
+// rs1_val==2863311531 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x5, x2, 1004, x1)
+
+inst_264:
+// rs1_val==2863311531 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0xaaaaaaaa, x2, 1008, x1)
+
+inst_265:
+// rs1_val==2863311531 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x55555555, x2, 1012, x1)
+
+inst_266:
+// rs1_val==2863311531 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaab;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaab, 0x3, x2, 1016, x1)
+
+inst_267:
+// rs1_val==1431655766 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x10000, x2, 1020, x1)
+
+inst_268:
+// rs1_val==1431655766 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x1, x2, 1024, x1)
+
+inst_269:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0xb505, x2, 1028, x1)
+
+inst_270:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0x66666667, x2, 1032, x1)
+
+inst_271:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x33333334, x2, 1036, x1)
+
+inst_272:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x6, x2, 1040, x1)
+
+inst_273:
+// rs1_val==1431655766 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0xaaaaaaab, x2, 1044, x1)
+
+inst_274:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x2, 1048, x1)
+
+inst_275:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x4, x2, 1052, x1)
+
+inst_276:
+// rs1_val==1431655766 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0xfffe, x2, 1056, x1)
+
+inst_277:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x0, x2, 1060, x1)
+
+inst_278:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0xb503, x2, 1064, x1)
+
+inst_279:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0x66666665, x2, 1068, x1)
+
+inst_280:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x33333332, x2, 1072, x1)
+
+inst_281:
+// rs1_val==1431655766 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0xaaaaaaa9, x2, 1076, x1)
+
+inst_282:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x55555554, x2, 1080, x1)
+
+inst_283:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x2, x2, 1084, x1)
+
+inst_284:
+// rs1_val==1431655766 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0xffff, x2, 1088, x1)
+
+inst_285:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0xb504, x2, 1092, x1)
+
+inst_286:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0x66666666, x2, 1096, x1)
+
+inst_287:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x33333333, x2, 1100, x1)
+
+inst_288:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x5, x2, 1104, x1)
+
+inst_289:
+// rs1_val==1431655766 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555556, 0xaaaaaaaa, x2, 1108, x1)
+
+inst_290:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x55555555, x2, 1112, x1)
+
+inst_291:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555556, 0x3, x2, 1116, x1)
+
+inst_292:
+// rs1_val==4 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x10000, x2, 1120, x1)
+
+inst_293:
+// rs1_val==4 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4, 0x1, x2, 1124, x1)
+
+inst_294:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xb505, x2, 1128, x1)
+
+inst_295:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x66666667, x2, 1132, x1)
+
+inst_296:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x33333334, x2, 1136, x1)
+
+inst_297:
+// rs1_val==4 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x6, x2, 1140, x1)
+
+inst_298:
+// rs1_val==4 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xaaaaaaab, x2, 1144, x1)
+
+inst_299:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x55555556, x2, 1148, x1)
+
+inst_300:
+// rs1_val==4 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4, 0x4, x2, 1152, x1)
+
+inst_301:
+// rs1_val==4 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xfffe, x2, 1156, x1)
+
+inst_302:
+// rs1_val==4 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4, 0x0, x2, 1160, x1)
+
+inst_303:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xb503, x2, 1164, x1)
+
+inst_304:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x66666665, x2, 1168, x1)
+
+inst_305:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x33333332, x2, 1172, x1)
+
+inst_306:
+// rs1_val==4 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xaaaaaaa9, x2, 1176, x1)
+
+inst_307:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x55555554, x2, 1180, x1)
+
+inst_308:
+// rs1_val==4 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4, 0x2, x2, 1184, x1)
+
+inst_309:
+// rs1_val==4 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xffff, x2, 1188, x1)
+
+inst_310:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xb504, x2, 1192, x1)
+
+inst_311:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x66666666, x2, 1196, x1)
+
+inst_312:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x33333333, x2, 1200, x1)
+
+inst_313:
+// rs1_val==4 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x5, x2, 1204, x1)
+
+inst_314:
+// rs1_val==4 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0xaaaaaaaa, x2, 1208, x1)
+
+inst_315:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x4, 0x55555555, x2, 1212, x1)
+
+inst_316:
+// rs1_val==4 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x4, 0x3, x2, 1216, x1)
+
+inst_317:
+// rs1_val==65534 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x10000, x2, 1220, x1)
+
+inst_318:
+// rs1_val==65534 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x1, x2, 1224, x1)
+
+inst_319:
+// rs1_val==65534 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0xb505, x2, 1228, x1)
+
+inst_320:
+// rs1_val==65534 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x66666667, x2, 1232, x1)
+
+inst_321:
+// rs1_val==65534 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x33333334, x2, 1236, x1)
+
+inst_322:
+// rs1_val==65534 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x6, x2, 1240, x1)
+
+inst_323:
+// rs1_val==65534 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0xaaaaaaab, x2, 1244, x1)
+
+inst_324:
+// rs1_val==65534 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x55555556, x2, 1248, x1)
+
+inst_325:
+// rs1_val==65534 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x4, x2, 1252, x1)
+
+inst_326:
+// rs1_val==65534 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0xfffe, x2, 1256, x1)
+
+inst_327:
+// rs1_val==65534 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x0, x2, 1260, x1)
+
+inst_328:
+// rs1_val==65534 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0xb503, x2, 1264, x1)
+
+inst_329:
+// rs1_val==65534 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x66666665, x2, 1268, x1)
+
+inst_330:
+// rs1_val==65534 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x33333332, x2, 1272, x1)
+
+inst_331:
+// rs1_val==65534 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0xaaaaaaa9, x2, 1276, x1)
+
+inst_332:
+// rs1_val==65534 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x55555554, x2, 1280, x1)
+
+inst_333:
+// rs1_val==65534 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x2, x2, 1284, x1)
+
+inst_334:
+// rs1_val==65534 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0xffff, x2, 1288, x1)
+
+inst_335:
+// rs1_val==65534 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0xb504, x2, 1292, x1)
+
+inst_336:
+// rs1_val==65534 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x66666666, x2, 1296, x1)
+
+inst_337:
+// rs1_val==65534 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x33333333, x2, 1300, x1)
+
+inst_338:
+// rs1_val==65534 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x5, x2, 1304, x1)
+
+inst_339:
+// rs1_val==65534 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0xaaaaaaaa, x2, 1308, x1)
+
+inst_340:
+// rs1_val==65534 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xfffe, 0x55555555, x2, 1312, x1)
+
+inst_341:
+// rs1_val==65534 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfffe;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfffe, 0x3, x2, 1316, x1)
+
+inst_342:
+// rs1_val==0 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x10000, x2, 1320, x1)
+
+inst_343:
+// rs1_val==0 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x1, x2, 1324, x1)
+
+inst_344:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xb505, x2, 1328, x1)
+
+inst_345:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x66666667, x2, 1332, x1)
+
+inst_346:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x33333334, x2, 1336, x1)
+
+inst_347:
+// rs1_val==0 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x6, x2, 1340, x1)
+
+inst_348:
+// rs1_val==0 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xaaaaaaab, x2, 1344, x1)
+
+inst_349:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x55555556, x2, 1348, x1)
+
+inst_350:
+// rs1_val==0 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x4, x2, 1352, x1)
+
+inst_351:
+// rs1_val==0 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xfffe, x2, 1356, x1)
+
+inst_352:
+// rs1_val==0 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x0, 0x0, x2, 1360, x1)
+
+inst_353:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xb503, x2, 1364, x1)
+
+inst_354:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x66666665, x2, 1368, x1)
+
+inst_355:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x33333332, x2, 1372, x1)
+
+inst_356:
+// rs1_val==0 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xaaaaaaa9, x2, 1376, x1)
+
+inst_357:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x55555554, x2, 1380, x1)
+
+inst_358:
+// rs1_val==0 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x2, x2, 1384, x1)
+
+inst_359:
+// rs1_val==0 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xffff, x2, 1388, x1)
+
+inst_360:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xb504, x2, 1392, x1)
+
+inst_361:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x66666666, x2, 1396, x1)
+
+inst_362:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x33333333, x2, 1400, x1)
+
+inst_363:
+// rs1_val==0 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x5, x2, 1404, x1)
+
+inst_364:
+// rs1_val==0 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0xaaaaaaaa, x2, 1408, x1)
+
+inst_365:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x55555555, x2, 1412, x1)
+
+inst_366:
+// rs1_val==0 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x0, 0x3, x2, 1416, x1)
+
+inst_367:
+// rs1_val==46339 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x10000, x2, 1420, x1)
+
+inst_368:
+// rs1_val==46339 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x1, x2, 1424, x1)
+
+inst_369:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xb505, x2, 1428, x1)
+
+inst_370:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x66666667, x2, 1432, x1)
+
+inst_371:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x33333334, x2, 1436, x1)
+
+inst_372:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x6, x2, 1440, x1)
+
+inst_373:
+// rs1_val==46339 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xaaaaaaab, x2, 1444, x1)
+
+inst_374:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x55555556, x2, 1448, x1)
+
+inst_375:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x4, x2, 1452, x1)
+
+inst_376:
+// rs1_val==46339 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xfffe, x2, 1456, x1)
+
+inst_377:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x0, x2, 1460, x1)
+
+inst_378:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0xb503, x2, 1464, x1)
+
+inst_379:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x66666665, x2, 1468, x1)
+
+inst_380:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x33333332, x2, 1472, x1)
+
+inst_381:
+// rs1_val==46339 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xaaaaaaa9, x2, 1476, x1)
+
+inst_382:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x55555554, x2, 1480, x1)
+
+inst_383:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x2, x2, 1484, x1)
+
+inst_384:
+// rs1_val==46339 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xffff, x2, 1488, x1)
+
+inst_385:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xb504, x2, 1492, x1)
+
+inst_386:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x66666666, x2, 1496, x1)
+
+inst_387:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x33333333, x2, 1500, x1)
+
+inst_388:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x5, x2, 1504, x1)
+
+inst_389:
+// rs1_val==46339 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0xaaaaaaaa, x2, 1508, x1)
+
+inst_390:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb503, 0x55555555, x2, 1512, x1)
+
+inst_391:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb503, 0x3, x2, 1516, x1)
+
+inst_392:
+// rs1_val==1717986917 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x10000, x2, 1520, x1)
+
+inst_393:
+// rs1_val==1717986917 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x1, x2, 1524, x1)
+
+inst_394:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0xb505, x2, 1528, x1)
+
+inst_395:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666665, 0x66666667, x2, 1532, x1)
+
+inst_396:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x33333334, x2, 1536, x1)
+
+inst_397:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x6, x2, 1540, x1)
+
+inst_398:
+// rs1_val==1717986917 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666665, 0xaaaaaaab, x2, 1544, x1)
+
+inst_399:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x55555556, x2, 1548, x1)
+
+inst_400:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x4, x2, 1552, x1)
+
+inst_401:
+// rs1_val==1717986917 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0xfffe, x2, 1556, x1)
+
+inst_402:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x0, x2, 1560, x1)
+
+inst_403:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0xb503, x2, 1564, x1)
+
+inst_404:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x2, 1568, x1)
+
+inst_405:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x33333332, x2, 1572, x1)
+
+inst_406:
+// rs1_val==1717986917 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666665, 0xaaaaaaa9, x2, 1576, x1)
+
+inst_407:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x55555554, x2, 1580, x1)
+
+inst_408:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x2, x2, 1584, x1)
+
+inst_409:
+// rs1_val==1717986917 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0xffff, x2, 1588, x1)
+
+inst_410:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0xb504, x2, 1592, x1)
+
+inst_411:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666665, 0x66666666, x2, 1596, x1)
+
+inst_412:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x33333333, x2, 1600, x1)
+
+inst_413:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x5, x2, 1604, x1)
+
+inst_414:
+// rs1_val==1717986917 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666665, 0xaaaaaaaa, x2, 1608, x1)
+
+inst_415:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x55555555, x2, 1612, x1)
+
+inst_416:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666665, 0x3, x2, 1616, x1)
+
+inst_417:
+// rs1_val==858993458 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x10000, x2, 1620, x1)
+
+inst_418:
+// rs1_val==858993458 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x1, x2, 1624, x1)
+
+inst_419:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0xb505, x2, 1628, x1)
+
+inst_420:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x66666667, x2, 1632, x1)
+
+inst_421:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x33333334, x2, 1636, x1)
+
+inst_422:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x6, x2, 1640, x1)
+
+inst_423:
+// rs1_val==858993458 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0xaaaaaaab, x2, 1644, x1)
+
+inst_424:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x55555556, x2, 1648, x1)
+
+inst_425:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x4, x2, 1652, x1)
+
+inst_426:
+// rs1_val==858993458 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0xfffe, x2, 1656, x1)
+
+inst_427:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x0, x2, 1660, x1)
+
+inst_428:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0xb503, x2, 1664, x1)
+
+inst_429:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x66666665, x2, 1668, x1)
+
+inst_430:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x2, 1672, x1)
+
+inst_431:
+// rs1_val==858993458 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0xaaaaaaa9, x2, 1676, x1)
+
+inst_432:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x55555554, x2, 1680, x1)
+
+inst_433:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x2, x2, 1684, x1)
+
+inst_434:
+// rs1_val==858993458 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0xffff, x2, 1688, x1)
+
+inst_435:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0xb504, x2, 1692, x1)
+
+inst_436:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x66666666, x2, 1696, x1)
+
+inst_437:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x33333333, x2, 1700, x1)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x5, x2, 1704, x1)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0xaaaaaaaa, x2, 1708, x1)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333332, 0x55555555, x2, 1712, x1)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333332, 0x3, x2, 1716, x1)
+
+inst_442:
+// rs1_val==2863311529 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x10000, x2, 1720, x1)
+
+inst_443:
+// rs1_val==2863311529 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x1, x2, 1724, x1)
+
+inst_444:
+// rs1_val==2863311529 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xb505, x2, 1728, x1)
+
+inst_445:
+// rs1_val==2863311529 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x66666667, x2, 1732, x1)
+
+inst_446:
+// rs1_val==2863311529 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x33333334, x2, 1736, x1)
+
+inst_447:
+// rs1_val==2863311529 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x6, x2, 1740, x1)
+
+inst_448:
+// rs1_val==2863311529 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0xaaaaaaab, x2, 1744, x1)
+
+inst_449:
+// rs1_val==2863311529 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x55555556, x2, 1748, x1)
+
+inst_450:
+// rs1_val==2863311529 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x4, x2, 1752, x1)
+
+inst_451:
+// rs1_val==2863311529 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xfffe, x2, 1756, x1)
+
+inst_452:
+// rs1_val==2863311529 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x0, x2, 1760, x1)
+
+inst_453:
+// rs1_val==2863311529 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xb503, x2, 1764, x1)
+
+inst_454:
+// rs1_val==2863311529 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x66666665, x2, 1768, x1)
+
+inst_455:
+// rs1_val==2863311529 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x33333332, x2, 1772, x1)
+
+inst_456:
+// rs1_val==2863311529 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xaaaaaaa9, x2, 1776, x1)
+
+inst_457:
+// rs1_val==2863311529 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x55555554, x2, 1780, x1)
+
+inst_458:
+// rs1_val==2863311529 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x2, x2, 1784, x1)
+
+inst_459:
+// rs1_val==2863311529 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xffff, x2, 1788, x1)
+
+inst_460:
+// rs1_val==2863311529 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0xb504, x2, 1792, x1)
+
+inst_461:
+// rs1_val==2863311529 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x66666666, x2, 1796, x1)
+
+inst_462:
+// rs1_val==2863311529 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x33333333, x2, 1800, x1)
+
+inst_463:
+// rs1_val==2863311529 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x5, x2, 1804, x1)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x4, x2, 1808, x1)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0xfffe, x2, 1812, x1)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x0, x2, 1816, x1)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0xb503, x2, 1820, x1)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0x66666665, x2, 1824, x1)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x33333332, x2, 1828, x1)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0xaaaaaaa9, x2, 1832, x1)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x2, 1836, x1)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x2, x2, 1840, x1)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0xffff, x2, 1844, x1)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0xb504, x2, 1848, x1)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0x66666666, x2, 1852, x1)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x33333333, x2, 1856, x1)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x5, x2, 1860, x1)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0xaaaaaaaa, x2, 1864, x1)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0x55555555, x2, 1868, x1)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x3, x2, 1872, x1)
+
+inst_481:
+// rs1_val==2 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x10000, x2, 1876, x1)
+
+inst_482:
+// rs1_val==2 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x2, 0x1, x2, 1880, x1)
+
+inst_483:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xb505, x2, 1884, x1)
+
+inst_484:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x66666667, x2, 1888, x1)
+
+inst_485:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x33333334, x2, 1892, x1)
+
+inst_486:
+// rs1_val==2 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x6, x2, 1896, x1)
+
+inst_487:
+// rs1_val==2 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaab, x2, 1900, x1)
+
+inst_488:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x55555556, x2, 1904, x1)
+
+inst_489:
+// rs1_val==2 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x4, x2, 1908, x1)
+
+inst_490:
+// rs1_val==2 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xfffe, x2, 1912, x1)
+
+inst_491:
+// rs1_val==2 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x2, 0x0, x2, 1916, x1)
+
+inst_492:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xb503, x2, 1920, x1)
+
+inst_493:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x66666665, x2, 1924, x1)
+
+inst_494:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x33333332, x2, 1928, x1)
+
+inst_495:
+// rs1_val==2 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaa9, x2, 1932, x1)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x55555554, x2, 1936, x1)
+
+inst_497:
+// rs1_val==2 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x2, 0x2, x2, 1940, x1)
+
+inst_498:
+// rs1_val==2 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xffff, x2, 1944, x1)
+
+inst_499:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xb504, x2, 1948, x1)
+
+inst_500:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x66666666, x2, 1952, x1)
+
+inst_501:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x33333333, x2, 1956, x1)
+
+inst_502:
+// rs1_val==2 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x5, x2, 1960, x1)
+
+inst_503:
+// rs1_val==2 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0xaaaaaaaa, x2, 1964, x1)
+
+inst_504:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x55555555, x2, 1968, x1)
+
+inst_505:
+// rs1_val==2 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x2, 0x3, x2, 1972, x1)
+
+inst_506:
+// rs1_val==65535 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x10000, x2, 1976, x1)
+
+inst_507:
+// rs1_val==65535 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x1, x2, 1980, x1)
+
+inst_508:
+// rs1_val==65535 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0xb505, x2, 1984, x1)
+
+inst_509:
+// rs1_val==65535 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x66666667, x2, 1988, x1)
+
+inst_510:
+// rs1_val==65535 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x33333334, x2, 1992, x1)
+
+inst_511:
+// rs1_val==65535 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x6, x2, 1996, x1)
+
+inst_512:
+// rs1_val==65535 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0xaaaaaaab, x2, 2000, x1)
+
+inst_513:
+// rs1_val==65535 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x55555556, x2, 2004, x1)
+
+inst_514:
+// rs1_val==65535 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x4, x2, 2008, x1)
+
+inst_515:
+// rs1_val==65535 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0xfffe, x2, 2012, x1)
+
+inst_516:
+// rs1_val==65535 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x0, x2, 2016, x1)
+
+inst_517:
+// rs1_val==65535 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0xb503, x2, 2020, x1)
+
+inst_518:
+// rs1_val==65535 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x66666665, x2, 2024, x1)
+
+inst_519:
+// rs1_val==65535 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x33333332, x2, 2028, x1)
+
+inst_520:
+// rs1_val==65535 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0xaaaaaaa9, x2, 2032, x1)
+
+inst_521:
+// rs1_val==65535 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x55555554, x2, 2036, x1)
+
+inst_522:
+// rs1_val==65535 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x2, x2, 2040, x1)
+
+inst_523:
+// rs1_val==65535 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0xffff, x2, 2044, x1)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_524:
+// rs1_val==65535 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0xb504, x2, 0, x1)
+
+inst_525:
+// rs1_val==65535 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x66666666, x2, 4, x1)
+
+inst_526:
+// rs1_val==65535 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x33333333, x2, 8, x1)
+
+inst_527:
+// rs1_val==65535 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x5, x2, 12, x1)
+
+inst_528:
+// rs1_val==65535 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0xaaaaaaaa, x2, 16, x1)
+
+inst_529:
+// rs1_val==65535 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xffff, 0x55555555, x2, 20, x1)
+
+inst_530:
+// rs1_val==65535 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffff;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffff, 0x3, x2, 24, x1)
+
+inst_531:
+// rs1_val==46340 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x10000, x2, 28, x1)
+
+inst_532:
+// rs1_val==46340 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x1, x2, 32, x1)
+
+inst_533:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xb505, x2, 36, x1)
+
+inst_534:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x66666667, x2, 40, x1)
+
+inst_535:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x33333334, x2, 44, x1)
+
+inst_536:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x6, x2, 48, x1)
+
+inst_537:
+// rs1_val==46340 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xaaaaaaab, x2, 52, x1)
+
+inst_538:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x55555556, x2, 56, x1)
+
+inst_539:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x4, x2, 60, x1)
+
+inst_540:
+// rs1_val==46340 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xfffe, x2, 64, x1)
+
+inst_541:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x0, x2, 68, x1)
+
+inst_542:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0xb503, x2, 72, x1)
+
+inst_543:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x66666665, x2, 76, x1)
+
+inst_544:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x33333332, x2, 80, x1)
+
+inst_545:
+// rs1_val==46340 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xaaaaaaa9, x2, 84, x1)
+
+inst_546:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x55555554, x2, 88, x1)
+
+inst_547:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x2, x2, 92, x1)
+
+inst_548:
+// rs1_val==46340 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xffff, x2, 96, x1)
+
+inst_549:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0xb504, x2, 100, x1)
+
+inst_550:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x66666666, x2, 104, x1)
+
+inst_551:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x33333333, x2, 108, x1)
+
+inst_552:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x5, x2, 112, x1)
+
+inst_553:
+// rs1_val==46340 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0xaaaaaaaa, x2, 116, x1)
+
+inst_554:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xb504, 0x55555555, x2, 120, x1)
+
+inst_555:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xb504, 0x3, x2, 124, x1)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x10000, x2, 128, x1)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x1, x2, 132, x1)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0xb505, x2, 136, x1)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666666, 0x66666667, x2, 140, x1)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x33333334, x2, 144, x1)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x6, x2, 148, x1)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666666, 0xaaaaaaab, x2, 152, x1)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x55555556, x2, 156, x1)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x4, x2, 160, x1)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0xfffe, x2, 164, x1)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x0, x2, 168, x1)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0xb503, x2, 172, x1)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x66666665, x2, 176, x1)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x33333332, x2, 180, x1)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666666, 0xaaaaaaa9, x2, 184, x1)
+
+inst_571:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x55555554, x2, 188, x1)
+
+inst_572:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x2, x2, 192, x1)
+
+inst_573:
+// rs1_val==1717986918 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0xffff, x2, 196, x1)
+
+inst_574:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0xb504, x2, 200, x1)
+
+inst_575:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x2, 204, x1)
+
+inst_576:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x33333333, x2, 208, x1)
+
+inst_577:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x5, x2, 212, x1)
+
+inst_578:
+// rs1_val==1717986918 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x66666666, 0xaaaaaaaa, x2, 216, x1)
+
+inst_579:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x55555555, x2, 220, x1)
+
+inst_580:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x66666666, 0x3, x2, 224, x1)
+
+inst_581:
+// rs1_val==858993459 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x10000, x2, 228, x1)
+
+inst_582:
+// rs1_val==858993459 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x1, x2, 232, x1)
+
+inst_583:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0xb505, x2, 236, x1)
+
+inst_584:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x66666667, x2, 240, x1)
+
+inst_585:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x33333334, x2, 244, x1)
+
+inst_586:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x6, x2, 248, x1)
+
+inst_587:
+// rs1_val==858993459 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0xaaaaaaab, x2, 252, x1)
+
+inst_588:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x55555556, x2, 256, x1)
+
+inst_589:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x4, x2, 260, x1)
+
+inst_590:
+// rs1_val==858993459 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0xfffe, x2, 264, x1)
+
+inst_591:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x0, x2, 268, x1)
+
+inst_592:
+// rs1_val==2863311529 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x3, x2, 272, x1)
+
+inst_593:
+// rs2_val == (2**(xlen)-1), 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0xffffffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xefffffff, 0xffffffff, x2, 276, x1)
+
+inst_594:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0xb503, x2, 280, x1)
+
+inst_595:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x66666665, x2, 284, x1)
+
+inst_596:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x33333332, x2, 288, x1)
+
+inst_597:
+// rs1_val==858993459 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0xaaaaaaa9, x2, 292, x1)
+
+inst_598:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x55555554, x2, 296, x1)
+
+inst_599:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x2, x2, 300, x1)
+
+inst_600:
+// rs1_val==858993459 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0xffff, x2, 304, x1)
+
+inst_601:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0xb504, x2, 308, x1)
+
+inst_602:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x66666666, x2, 312, x1)
+
+inst_603:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x2, 316, x1)
+
+inst_604:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x5, x2, 320, x1)
+
+inst_605:
+// rs1_val==858993459 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0xaaaaaaaa, x2, 324, x1)
+
+inst_606:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x33333333, 0x55555555, x2, 328, x1)
+
+inst_607:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x33333333, 0x3, x2, 332, x1)
+
+inst_608:
+// rs1_val==5 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x10000, x2, 336, x1)
+
+inst_609:
+// rs1_val==5 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x1, x2, 340, x1)
+
+inst_610:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xb505, x2, 344, x1)
+
+inst_611:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x66666667, x2, 348, x1)
+
+inst_612:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x33333334, x2, 352, x1)
+
+inst_613:
+// rs1_val==5 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x6, x2, 356, x1)
+
+inst_614:
+// rs1_val==5 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xaaaaaaab, x2, 360, x1)
+
+inst_615:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x55555556, x2, 364, x1)
+
+inst_616:
+// rs1_val==5 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x4, x2, 368, x1)
+
+inst_617:
+// rs1_val==5 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xfffe, x2, 372, x1)
+
+inst_618:
+// rs1_val==5 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x0, x2, 376, x1)
+
+inst_619:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xb503, x2, 380, x1)
+
+inst_620:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x66666665, x2, 384, x1)
+
+inst_621:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x33333332, x2, 388, x1)
+
+inst_622:
+// rs1_val==5 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xaaaaaaa9, x2, 392, x1)
+
+inst_623:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x55555554, x2, 396, x1)
+
+inst_624:
+// rs1_val==5 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x2, x2, 400, x1)
+
+inst_625:
+// rs1_val==5 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xffff, x2, 404, x1)
+
+inst_626:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xb504, x2, 408, x1)
+
+inst_627:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x66666666, x2, 412, x1)
+
+inst_628:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x33333333, x2, 416, x1)
+
+inst_629:
+// rs1_val==5 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x5, x2, 420, x1)
+
+inst_630:
+// rs1_val==5 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xaaaaaaaa, x2, 424, x1)
+
+inst_631:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0x55555555, x2, 428, x1)
+
+inst_632:
+// rs1_val==5 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x5, 0x3, x2, 432, x1)
+
+inst_633:
+// rs1_val==2863311530 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x10000, x2, 436, x1)
+
+inst_634:
+// rs1_val==2863311530 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x1, x2, 440, x1)
+
+inst_635:
+// rs1_val==2863311530 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xb505, x2, 444, x1)
+
+inst_636:
+// rs1_val==2863311530 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x66666667, x2, 448, x1)
+
+inst_637:
+// rs1_val==2863311530 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x33333334, x2, 452, x1)
+
+inst_638:
+// rs1_val==2863311530 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x6, x2, 456, x1)
+
+inst_639:
+// rs1_val==2863311530 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xaaaaaaaa, 0xaaaaaaab, x2, 460, x1)
+
+inst_640:
+// rs1_val==2863311530 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x55555556, x2, 464, x1)
+
+inst_641:
+// rs1_val==2863311530 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x4, x2, 468, x1)
+
+inst_642:
+// rs1_val==2863311530 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xfffe, x2, 472, x1)
+
+inst_643:
+// rs1_val==2863311530 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x0, x2, 476, x1)
+
+inst_644:
+// rs1_val==2863311530 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xb503, x2, 480, x1)
+
+inst_645:
+// rs1_val==2863311530 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x66666665, x2, 484, x1)
+
+inst_646:
+// rs1_val==2863311530 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x33333332, x2, 488, x1)
+
+inst_647:
+// rs1_val==2863311530 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xaaaaaaa9, x2, 492, x1)
+
+inst_648:
+// rs1_val==2863311530 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x55555554, x2, 496, x1)
+
+inst_649:
+// rs1_val==2863311530 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x2, x2, 500, x1)
+
+inst_650:
+// rs1_val==2863311530 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xffff, x2, 504, x1)
+
+inst_651:
+// rs1_val==2863311530 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xb504, x2, 508, x1)
+
+inst_652:
+// rs1_val==2863311530 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x66666666, x2, 512, x1)
+
+inst_653:
+// rs1_val==2863311530 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x33333333, x2, 516, x1)
+
+inst_654:
+// rs1_val==2863311530 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x5, x2, 520, x1)
+
+inst_655:
+// rs1_val==2863311530 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0xaaaaaaaa, x2, 524, x1)
+
+inst_656:
+// rs1_val==2863311530 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x55555555, x2, 528, x1)
+
+inst_657:
+// rs1_val==2863311530 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaaa;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaaa, 0x3, x2, 532, x1)
+
+inst_658:
+// rs1_val==1431655765 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x10000, x2, 536, x1)
+
+inst_659:
+// rs1_val==1431655765 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x1, x2, 540, x1)
+
+inst_660:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0xb505, x2, 544, x1)
+
+inst_661:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0x66666667, x2, 548, x1)
+
+inst_662:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x33333334, x2, 552, x1)
+
+inst_663:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x6, x2, 556, x1)
+
+inst_664:
+// rs1_val==1431655765 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0xaaaaaaab, x2, 560, x1)
+
+inst_665:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0x55555556, x2, 564, x1)
+
+inst_666:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x4, x2, 568, x1)
+
+inst_667:
+// rs1_val==1431655765 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0xfffe, x2, 572, x1)
+
+inst_668:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x0, x2, 576, x1)
+
+inst_669:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0xb503, x2, 580, x1)
+
+inst_670:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0x66666665, x2, 584, x1)
+
+inst_671:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x33333332, x2, 588, x1)
+
+inst_672:
+// rs1_val==1431655765 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0xaaaaaaa9, x2, 592, x1)
+
+inst_673:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x55555554, x2, 596, x1)
+
+inst_674:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x2, x2, 600, x1)
+
+inst_675:
+// rs1_val==1431655765 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0xffff, x2, 604, x1)
+
+inst_676:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0xb504, x2, 608, x1)
+
+inst_677:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0x66666666, x2, 612, x1)
+
+inst_678:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x33333333, x2, 616, x1)
+
+inst_679:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x5, x2, 620, x1)
+
+inst_680:
+// rs1_val==1431655765 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555555, 0xaaaaaaaa, x2, 624, x1)
+
+inst_681:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x2, 628, x1)
+
+inst_682:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555555, 0x3, x2, 632, x1)
+
+inst_683:
+// rs1_val==3 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x10000, x2, 636, x1)
+
+inst_684:
+// rs1_val==3 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x3, 0x1, x2, 640, x1)
+
+inst_685:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xb505, x2, 644, x1)
+
+inst_686:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x66666667, x2, 648, x1)
+
+inst_687:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x33333334, x2, 652, x1)
+
+inst_688:
+// rs1_val==3 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x6, x2, 656, x1)
+
+inst_689:
+// rs1_val==3 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaab, x2, 660, x1)
+
+inst_690:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x55555556, x2, 664, x1)
+
+inst_691:
+// rs1_val==3 and rs2_val==4, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x4, x2, 668, x1)
+
+inst_692:
+// rs1_val==3 and rs2_val==65534, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xfffe
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xfffe, x2, 672, x1)
+
+inst_693:
+// rs1_val==3 and rs2_val==0, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x3, 0x0, x2, 676, x1)
+
+inst_694:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xb503, x2, 680, x1)
+
+inst_695:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x66666665, x2, 684, x1)
+
+inst_696:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x33333332, x2, 688, x1)
+
+inst_697:
+// rs1_val==3 and rs2_val==2863311529, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaa9
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaa9, x2, 692, x1)
+
+inst_698:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x55555554, x2, 696, x1)
+
+inst_699:
+// rs1_val==3 and rs2_val==2, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x3, 0x2, x2, 700, x1)
+
+inst_700:
+// rs1_val==3 and rs2_val==65535, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xffff, x2, 704, x1)
+
+inst_701:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xb504, x2, 708, x1)
+
+inst_702:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x66666666, x2, 712, x1)
+
+inst_703:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x33333333, x2, 716, x1)
+
+inst_704:
+// rs1_val==3 and rs2_val==5, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x5, x2, 720, x1)
+
+inst_705:
+// rs1_val==3 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0xaaaaaaaa, x2, 724, x1)
+
+inst_706:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x3, 0x55555555, x2, 728, x1)
+
+inst_707:
+// rs1_val==3 and rs2_val==3, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x3, 0x3, x2, 732, x1)
+
+inst_708:
+// rs1_val==2863311529 and rs2_val==2863311530, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0xaaaaaaaa
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xaaaaaaa9, 0xaaaaaaaa, x2, 736, x1)
+
+inst_709:
+// rs1_val == (2**(xlen)-1), 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff;  op2val:0xfffffbff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xffffffff, 0xfffffbff, x2, 740, x1)
+
+inst_710:
+// rs1_val==2863311529 and rs2_val==1431655765, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xaaaaaaa9;  op2val:0x55555555
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xaaaaaaa9, 0x55555555, x2, 744, x1)
+
+inst_711:
+// rs1_val==1431655764 and rs2_val==65536, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x10000
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x10000, x2, 748, x1)
+
+inst_712:
+// rs1_val==1431655764 and rs2_val==1, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x1
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x1, x2, 752, x1)
+
+inst_713:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0xb505, x2, 756, x1)
+
+inst_714:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0x66666667, x2, 760, x1)
+
+inst_715:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x33333334, x2, 764, x1)
+
+inst_716:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0x55555554, 0x6, x2, 768, x1)
+
+inst_717:
+// rs1_val==1431655764 and rs2_val==2863311531, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xaaaaaaab
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0xaaaaaaab, x2, 772, x1)
+
+inst_718:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x55555554, 0x55555556, x2, 776, x1)
+
+inst_719:
+// rs2_val == 3758096383, rs1_val == 4261412863
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffff;  op2val:0xdfffffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x0, 0xfdffffff, 0xdfffffff, x2, 780, x1)
+
+inst_720:
+// rs2_val == 4286578687, rs1_val == 4026531839
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0xefffffff;  op2val:0xff7fffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0xefffffff, 0xff7fffff, x2, 784, x1)
+
+inst_721:
+// rs2_val == 4294836223, 
+// opcode: sltu ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffdffff
+TEST_RR_OP(sltu, x12, x10, x11, 0x1, 0x5, 0xfffdffff, x2, 788, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_0:
+    .fill 5*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 198*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S
new file mode 100644
index 000000000..7e3e8c253
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S
@@ -0,0 +1,531 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sra instruction of the RISC-V E extension for the sra covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sra)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x11, rs2==x9, rd==x12, rs1_val < 0 and rs2_val == 0, rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: sra ; op1:x11; op2:x9; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(sra, x12, x11, x9, -0x55555556, -0x55555556, 0x0, x3, 0, x5)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x8, rs2==x12, rd==x8, rs2_val == 15, rs1_val == -524289, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: sra ; op1:x8; op2:x12; dest:x8; op1val:-0x80001;  op2val:0xf
+TEST_RR_OP(sra, x8, x8, x12, -0x11, -0x80001, 0xf, x3, 4, x5)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x10, rs2==x2, rd==x2, rs2_val == 23, rs1_val==3, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: sra ; op1:x10; op2:x2; dest:x2; op1val:0x3;  op2val:0x17
+TEST_RR_OP(sra, x2, x10, x2, 0x0, 0x3, 0x17, x3, 8, x5)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x4, rs2_val == 27, 
+// opcode: sra ; op1:x6; op2:x6; dest:x4; op1val:-0x8;  op2val:-0x8
+TEST_RR_OP(sra, x4, x6, x6, -0x1, -0x8, -0x8, x3, 12, x5)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13, rs2_val == 29, rs1_val==-1431655765
+// opcode: sra ; op1:x13; op2:x13; dest:x13; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(sra, x13, x13, x13, -0xaaaab, -0x55555555, -0x55555555, x3, 16, x5)
+
+inst_5:
+// rs1==x0, rs2==x10, rd==x7, rs2_val == 30, rs1_val == 16384
+// opcode: sra ; op1:x0; op2:x10; dest:x7; op1val:0x0;  op2val:0x1e
+TEST_RR_OP(sra, x7, x0, x10, 0x0, 0x0, 0x1e, x3, 20, x5)
+
+inst_6:
+// rs1==x1, rs2==x15, rd==x14, rs1_val == 2147483647, rs2_val == 21, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
+// opcode: sra ; op1:x1; op2:x15; dest:x14; op1val:0x7fffffff;  op2val:0x15
+TEST_RR_OP(sra, x14, x1, x15, 0x3ff, 0x7fffffff, 0x15, x3, 24, x5)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_7:
+// rs1==x3, rs2==x7, rd==x5, rs1_val == -1073741825, rs2_val == 1
+// opcode: sra ; op1:x3; op2:x7; dest:x5; op1val:-0x40000001;  op2val:0x1
+TEST_RR_OP(sra, x5, x3, x7, -0x20000001, -0x40000001, 0x1, x4, 0, x6)
+
+inst_8:
+// rs1==x2, rs2==x8, rd==x15, rs1_val == -536870913, 
+// opcode: sra ; op1:x2; op2:x8; dest:x15; op1val:-0x20000001;  op2val:0x7
+TEST_RR_OP(sra, x15, x2, x8, -0x400001, -0x20000001, 0x7, x4, 4, x6)
+
+inst_9:
+// rs1==x7, rs2==x11, rd==x1, rs1_val == -268435457, 
+// opcode: sra ; op1:x7; op2:x11; dest:x1; op1val:-0x10000001;  op2val:0x9
+TEST_RR_OP(sra, x1, x7, x11, -0x80001, -0x10000001, 0x9, x4, 8, x6)
+
+inst_10:
+// rs1==x12, rs2==x0, rd==x9, rs1_val == -134217729, 
+// opcode: sra ; op1:x12; op2:x0; dest:x9; op1val:-0x8000001;  op2val:0x0
+TEST_RR_OP(sra, x9, x12, x0, -0x8000001, -0x8000001, 0x0, x4, 12, x6)
+
+inst_11:
+// rs1==x5, rs2==x14, rd==x10, rs1_val == -67108865, 
+// opcode: sra ; op1:x5; op2:x14; dest:x10; op1val:-0x4000001;  op2val:0x17
+TEST_RR_OP(sra, x10, x5, x14, -0x9, -0x4000001, 0x17, x4, 16, x6)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_12:
+// rs1==x4, rs2==x5, rd==x0, rs1_val == -33554433, 
+// opcode: sra ; op1:x4; op2:x5; dest:x0; op1val:-0x2000001;  op2val:0x9
+TEST_RR_OP(sra, x0, x4, x5, 0, -0x2000001, 0x9, x2, 0, x7)
+
+inst_13:
+// rs1==x15, rs2==x4, rd==x3, rs1_val == -16777217, 
+// opcode: sra ; op1:x15; op2:x4; dest:x3; op1val:-0x1000001;  op2val:0xe
+TEST_RR_OP(sra, x3, x15, x4, -0x401, -0x1000001, 0xe, x2, 4, x7)
+
+inst_14:
+// rs1==x9, rs2==x3, rd==x11, rs1_val == -8388609, 
+// opcode: sra ; op1:x9; op2:x3; dest:x11; op1val:-0x800001;  op2val:0x11
+TEST_RR_OP(sra, x11, x9, x3, -0x41, -0x800001, 0x11, x2, 8, x7)
+
+inst_15:
+// rs1==x14, rs2==x1, rd==x6, rs1_val == -4194305, 
+// opcode: sra ; op1:x14; op2:x1; dest:x6; op1val:-0x400001;  op2val:0x1b
+TEST_RR_OP(sra, x6, x14, x1, -0x1, -0x400001, 0x1b, x2, 12, x7)
+
+inst_16:
+// rs1_val == -2097153, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0xf
+TEST_RR_OP(sra, x12, x10, x11, -0x41, -0x200001, 0xf, x2, 16, x7)
+
+inst_17:
+// rs1_val == -1048577, rs2_val == 2
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x2
+TEST_RR_OP(sra, x12, x10, x11, -0x40001, -0x100001, 0x2, x2, 20, x1)
+
+inst_18:
+// rs1_val == -262145, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, -0x201, -0x40001, 0x9, x2, 24, x1)
+
+inst_19:
+// rs1_val == -131073, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x1e
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x20001, 0x1e, x2, 28, x1)
+
+inst_20:
+// rs1_val == -65537, rs2_val == 16
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x10
+TEST_RR_OP(sra, x12, x10, x11, -0x2, -0x10001, 0x10, x2, 32, x1)
+
+inst_21:
+// rs1_val == -32769, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x1b
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x8001, 0x1b, x2, 36, x1)
+
+inst_22:
+// rs1_val == -16385, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x2
+TEST_RR_OP(sra, x12, x10, x11, -0x1001, -0x4001, 0x2, x2, 40, x1)
+
+inst_23:
+// rs1_val == -8193, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x1e
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2001, 0x1e, x2, 44, x1)
+
+inst_24:
+// rs1_val == -4097, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0xf
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x1001, 0xf, x2, 48, x1)
+
+inst_25:
+// rs1_val == -2049, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x12
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x801, 0x12, x2, 52, x1)
+
+inst_26:
+// rs1_val == -1025, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x12
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x401, 0x12, x2, 56, x1)
+
+inst_27:
+// rs1_val == -513, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x1b
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x201, 0x1b, x2, 60, x1)
+
+inst_28:
+// rs1_val == -257, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x101, 0x9, x2, 64, x1)
+
+inst_29:
+// rs1_val == -129, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x6
+TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x81, 0x6, x2, 68, x1)
+
+inst_30:
+// rs1_val == -65, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0x1d
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x41, 0x1d, x2, 72, x1)
+
+inst_31:
+// rs1_val == -33, rs2_val == 8
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x8
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x21, 0x8, x2, 76, x1)
+
+inst_32:
+// rs1_val == -17, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0xe
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x11, 0xe, x2, 80, x1)
+
+inst_33:
+// rs1_val == -9, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x9, 0x9, x2, 84, x1)
+
+inst_34:
+// rs1_val == -5, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0xe
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x5, 0xe, x2, 88, x1)
+
+inst_35:
+// rs1_val == -3, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0x15
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x3, 0x15, x2, 92, x1)
+
+inst_36:
+// rs1_val == -2, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x10
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0x2, 0x10, x2, 96, x1)
+
+inst_37:
+// rs2_val == 4, rs1_val==2, rs1_val == 2
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2, 0x4, x2, 100, x1)
+
+inst_38:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x13
+TEST_RR_OP(sra, x12, x10, x11, -0x1000, -0x80000000, 0x13, x2, 104, x1)
+
+inst_39:
+// rs1_val == 1073741824, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x1b
+TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x40000000, 0x1b, x2, 108, x1)
+
+inst_40:
+// rs1_val == 536870912, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, 0x100000, 0x20000000, 0x9, x2, 112, x1)
+
+inst_41:
+// rs1_val == 268435456, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0xb
+TEST_RR_OP(sra, x12, x10, x11, 0x20000, 0x10000000, 0xb, x2, 116, x1)
+
+inst_42:
+// rs1_val == 134217728, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x17
+TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x8000000, 0x17, x2, 120, x1)
+
+inst_43:
+// rs1_val == 67108864, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xc
+TEST_RR_OP(sra, x12, x10, x11, 0x4000, 0x4000000, 0xc, x2, 124, x1)
+
+inst_44:
+// rs1_val == 33554432, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x11
+TEST_RR_OP(sra, x12, x10, x11, 0x100, 0x2000000, 0x11, x2, 128, x1)
+
+inst_45:
+// rs1_val == 16777216, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x11
+TEST_RR_OP(sra, x12, x10, x11, 0x80, 0x1000000, 0x11, x2, 132, x1)
+
+inst_46:
+// rs1_val == 8388608, rs1_val > 0 and rs2_val == 0
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x0
+TEST_RR_OP(sra, x12, x10, x11, 0x800000, 0x800000, 0x0, x2, 136, x1)
+
+inst_47:
+// rs1_val == 4194304, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xb
+TEST_RR_OP(sra, x12, x10, x11, 0x800, 0x400000, 0xb, x2, 140, x1)
+
+inst_48:
+// rs1_val == 2097152, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, 0x1000, 0x200000, 0x9, x2, 144, x1)
+
+inst_49:
+// rs1_val == 1048576, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x1
+TEST_RR_OP(sra, x12, x10, x11, 0x80000, 0x100000, 0x1, x2, 148, x1)
+
+inst_50:
+// rs1_val == 524288, rs2_val == 10
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0xa
+TEST_RR_OP(sra, x12, x10, x11, 0x200, 0x80000, 0xa, x2, 152, x1)
+
+inst_51:
+// rs1_val == 262144, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x1f
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x40000, 0x1f, x2, 156, x1)
+
+inst_52:
+// rs1_val == 131072, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0xb
+TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x20000, 0xb, x2, 160, x1)
+
+inst_53:
+// rs1_val == 65536, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0xa
+TEST_RR_OP(sra, x12, x10, x11, 0x40, 0x10000, 0xa, x2, 164, x1)
+
+inst_54:
+// rs1_val == 32768, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x10
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x8000, 0x10, x2, 168, x1)
+
+inst_55:
+// rs1_val == 8192, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0xf
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x2000, 0xf, x2, 172, x1)
+
+inst_56:
+// rs1_val == 4096, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x1d
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1000, 0x1d, x2, 176, x1)
+
+inst_57:
+// rs1_val == 2048, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x8
+TEST_RR_OP(sra, x12, x10, x11, 0x8, 0x800, 0x8, x2, 180, x1)
+
+inst_58:
+// rs1_val == 1024, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x5
+TEST_RR_OP(sra, x12, x10, x11, 0x20, 0x400, 0x5, x2, 184, x1)
+
+inst_59:
+// rs1_val == 512, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x1b
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x200, 0x1b, x2, 188, x1)
+
+inst_60:
+// rs1_val == 256, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0xd
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x100, 0xd, x2, 192, x1)
+
+inst_61:
+// rs1_val == 128, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x3
+TEST_RR_OP(sra, x12, x10, x11, 0x10, 0x80, 0x3, x2, 196, x1)
+
+inst_62:
+// rs1_val == 64, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x5
+TEST_RR_OP(sra, x12, x10, x11, 0x2, 0x40, 0x5, x2, 200, x1)
+
+inst_63:
+// rs1_val == 32, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x5
+TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x20, 0x5, x2, 204, x1)
+
+inst_64:
+// rs1_val == 16, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x8
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x10, 0x8, x2, 208, x1)
+
+inst_65:
+// rs1_val == 8, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x3
+TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x8, 0x3, x2, 212, x1)
+
+inst_66:
+// rs1_val == 4, rs1_val==4
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4, 0xb, x2, 216, x1)
+
+inst_67:
+// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x8
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x1, 0x8, x2, 220, x1)
+
+inst_68:
+// rs1_val==46341, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x1e
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0xb505, 0x1e, x2, 224, x1)
+
+inst_69:
+// rs1_val==-46339, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x8
+TEST_RR_OP(sra, x12, x10, x11, -0xb6, -0xb503, 0x8, x2, 228, x1)
+
+inst_70:
+// rs1_val==1717986919, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x10
+TEST_RR_OP(sra, x12, x10, x11, 0x6666, 0x66666667, 0x10, x2, 232, x1)
+
+inst_71:
+// rs1_val==858993460, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xa
+TEST_RR_OP(sra, x12, x10, x11, 0xccccc, 0x33333334, 0xa, x2, 236, x1)
+
+inst_72:
+// rs1_val==6, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x13
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x6, 0x13, x2, 240, x1)
+
+inst_73:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x15
+TEST_RR_OP(sra, x12, x10, x11, 0x2aa, 0x55555555, 0x15, x2, 244, x1)
+
+inst_74:
+// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xa
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x0, 0xa, x2, 248, x1)
+
+inst_75:
+// rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0x7
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x7, 0x7, x2, 252, x1)
+
+inst_76:
+// rs1_val==1431655766, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x13
+TEST_RR_OP(sra, x12, x10, x11, 0xaaa, 0x55555556, 0x13, x2, 256, x1)
+
+inst_77:
+// rs1_val==46339, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x7
+TEST_RR_OP(sra, x12, x10, x11, 0x16a, 0xb503, 0x7, x2, 260, x1)
+
+inst_78:
+// rs1_val==1717986917, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1b
+TEST_RR_OP(sra, x12, x10, x11, 0xc, 0x66666665, 0x1b, x2, 264, x1)
+
+inst_79:
+// rs1_val==858993458, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x15
+TEST_RR_OP(sra, x12, x10, x11, 0x199, 0x33333332, 0x15, x2, 268, x1)
+
+inst_80:
+// rs1_val==1431655764, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x7
+TEST_RR_OP(sra, x12, x10, x11, 0xaaaaaa, 0x55555554, 0x7, x2, 272, x1)
+
+inst_81:
+// rs1_val==46340, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xf
+TEST_RR_OP(sra, x12, x10, x11, 0x1, 0xb504, 0xf, x2, 276, x1)
+
+inst_82:
+// rs1_val==-46340, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x15
+TEST_RR_OP(sra, x12, x10, x11, -0x1, -0xb504, 0x15, x2, 280, x1)
+
+inst_83:
+// rs1_val==1717986918, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1e
+TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x66666666, 0x1e, x2, 284, x1)
+
+inst_84:
+// rs1_val==858993459, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1d
+TEST_RR_OP(sra, x12, x10, x11, 0x1, 0x33333333, 0x1d, x2, 288, x1)
+
+inst_85:
+// rs1_val==5, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x1d
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x5, 0x1d, x2, 292, x1)
+
+inst_86:
+// rs2_val == 29, rs1_val==-1431655765
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x1d
+TEST_RR_OP(sra, x12, x10, x11, -0x3, -0x55555555, 0x1d, x2, 296, x1)
+
+inst_87:
+// rs2_val == 30, rs1_val == 16384
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x1e
+TEST_RR_OP(sra, x12, x10, x11, 0x0, 0x4000, 0x1e, x2, 300, x1)
+
+inst_88:
+// rs1_val == -134217729, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:0xb
+TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x8000001, 0xb, x2, 304, x1)
+
+inst_89:
+// rs1_val == -33554433, 
+// opcode: sra ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x9
+TEST_RR_OP(sra, x12, x10, x11, -0x10001, -0x2000001, 0x9, x2, 308, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 5*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 78*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S
new file mode 100644
index 000000000..e87f2b740
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S
@@ -0,0 +1,516 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the srai instruction of the RISC-V E extension for the srai covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srai)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x0, rd==x2, rs1_val < 0 and imm_val == (xlen-1), rs1_val == -536870913, rs1_val < 0 and imm_val > 0 and imm_val < xlen
+// opcode: srai ; op1:x0; dest:x2; op1val:0x0;  immval:0x1f
+TEST_IMM_OP( srai, x2, x0, 0x0, 0x0, 0x1f, x1, 0, x5)
+
+inst_1:
+// rs1 == rd, rs1==x14, rd==x14, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val > 0 and imm_val < xlen
+// opcode: srai ; op1:x14; dest:x14; op1val:0x7fffffff;  immval:0xc
+TEST_IMM_OP( srai, x14, x14, 0x7ffff, 0x7fffffff, 0xc, x1, 4, x5)
+
+inst_2:
+// rs1==x3, rd==x11, rs1_val == -1073741825, 
+// opcode: srai ; op1:x3; dest:x11; op1val:-0x40000001;  immval:0x7
+TEST_IMM_OP( srai, x11, x3, -0x800001, -0x40000001, 0x7, x1, 8, x5)
+
+inst_3:
+// rs1==x15, rd==x4, rs1_val == -268435457, rs1_val < 0 and imm_val == 0
+// opcode: srai ; op1:x15; dest:x4; op1val:-0x10000001;  immval:0x0
+TEST_IMM_OP( srai, x4, x15, -0x10000001, -0x10000001, 0x0, x1, 12, x5)
+
+inst_4:
+// rs1==x7, rd==x10, rs1_val == -134217729, imm_val == 21
+// opcode: srai ; op1:x7; dest:x10; op1val:-0x8000001;  immval:0x15
+TEST_IMM_OP( srai, x10, x7, -0x41, -0x8000001, 0x15, x1, 16, x5)
+
+inst_5:
+// rs1==x8, rd==x6, rs1_val == -67108865, imm_val == 10
+// opcode: srai ; op1:x8; dest:x6; op1val:-0x4000001;  immval:0xa
+TEST_IMM_OP( srai, x6, x8, -0x10001, -0x4000001, 0xa, x1, 20, x5)
+
+inst_6:
+// rs1==x9, rd==x13, rs1_val == -33554433, imm_val == 2
+// opcode: srai ; op1:x9; dest:x13; op1val:-0x2000001;  immval:0x2
+TEST_IMM_OP( srai, x13, x9, -0x800001, -0x2000001, 0x2, x1, 24, x5)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_7:
+// rs1==x5, rd==x0, rs1_val == -16777217, 
+// opcode: srai ; op1:x5; dest:x0; op1val:-0x1000001;  immval:0x12
+TEST_IMM_OP( srai, x0, x5, 0, -0x1000001, 0x12, x3, 0, x6)
+
+inst_8:
+// rs1==x10, rd==x8, rs1_val == -8388609, imm_val == 30
+// opcode: srai ; op1:x10; dest:x8; op1val:-0x800001;  immval:0x1e
+TEST_IMM_OP( srai, x8, x10, -0x1, -0x800001, 0x1e, x3, 4, x6)
+
+inst_9:
+// rs1==x13, rd==x5, rs1_val == -4194305, 
+// opcode: srai ; op1:x13; dest:x5; op1val:-0x400001;  immval:0x9
+TEST_IMM_OP( srai, x5, x13, -0x2001, -0x400001, 0x9, x3, 8, x6)
+
+inst_10:
+// rs1==x4, rd==x12, rs1_val == -2097153, 
+// opcode: srai ; op1:x4; dest:x12; op1val:-0x200001;  immval:0x7
+TEST_IMM_OP( srai, x12, x4, -0x4001, -0x200001, 0x7, x3, 12, x6)
+
+inst_11:
+// rs1==x12, rd==x7, rs1_val == -1048577, 
+// opcode: srai ; op1:x12; dest:x7; op1val:-0x100001;  immval:0x7
+TEST_IMM_OP( srai, x7, x12, -0x2001, -0x100001, 0x7, x3, 16, x6)
+
+inst_12:
+// rs1==x2, rd==x15, rs1_val == -524289, 
+// opcode: srai ; op1:x2; dest:x15; op1val:-0x80001;  immval:0x7
+TEST_IMM_OP( srai, x15, x2, -0x1001, -0x80001, 0x7, x3, 20, x6)
+
+inst_13:
+// rs1==x1, rd==x9, rs1_val == -262145, imm_val == 8
+// opcode: srai ; op1:x1; dest:x9; op1val:-0x40001;  immval:0x8
+TEST_IMM_OP( srai, x9, x1, -0x401, -0x40001, 0x8, x3, 24, x6)
+
+inst_14:
+// rs1==x6, rd==x1, rs1_val == -131073, 
+// opcode: srai ; op1:x6; dest:x1; op1val:-0x20001;  immval:0x13
+TEST_IMM_OP( srai, x1, x6, -0x1, -0x20001, 0x13, x3, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_15:
+// rs1==x11, rd==x3, rs1_val == -65537, imm_val == 4
+// opcode: srai ; op1:x11; dest:x3; op1val:-0x10001;  immval:0x4
+TEST_IMM_OP( srai, x3, x11, -0x1001, -0x10001, 0x4, x1, 0, x2)
+
+inst_16:
+// rs1_val == -32769, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x7
+TEST_IMM_OP( srai, x11, x10, -0x101, -0x8001, 0x7, x1, 4, x2)
+
+inst_17:
+// rs1_val == -16385, imm_val == 16
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x10
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x4001, 0x10, x1, 8, x2)
+
+inst_18:
+// rs1_val == -8193, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x13
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x2001, 0x13, x1, 12, x2)
+
+inst_19:
+// rs1_val == -4097, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x1001;  immval:0x1e
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x1001, 0x1e, x1, 16, x2)
+
+inst_20:
+// rs1_val == -2049, imm_val == 15
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x801;  immval:0xf
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x801, 0xf, x1, 20, x2)
+
+inst_21:
+// rs1_val == -1025, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x401;  immval:0x11
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x401, 0x11, x1, 24, x2)
+
+inst_22:
+// rs1_val == -513, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x201;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x201, 0xb, x1, 28, x2)
+
+inst_23:
+// rs1_val == -257, imm_val == 1
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x101;  immval:0x1
+TEST_IMM_OP( srai, x11, x10, -0x81, -0x101, 0x1, x1, 32, x2)
+
+inst_24:
+// rs1_val == -129, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x81;  immval:0xc
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x81, 0xc, x1, 36, x2)
+
+inst_25:
+// rs1_val == -65, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x41;  immval:0x13
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x41, 0x13, x1, 40, x2)
+
+inst_26:
+// rs1_val == -33, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x21;  immval:0xd
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x21, 0xd, x1, 44, x2)
+
+inst_27:
+// rs1_val == -17, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x11;  immval:0x1e
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x11, 0x1e, x1, 48, x2)
+
+inst_28:
+// rs1_val == -9, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x9;  immval:0x12
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x9, 0x12, x1, 52, x2)
+
+inst_29:
+// rs1_val == -5, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x5;  immval:0xf
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x5, 0xf, x1, 56, x2)
+
+inst_30:
+// rs1_val == -3, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x3;  immval:0x9
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x3, 0x9, x1, 60, x2)
+
+inst_31:
+// rs1_val == -2, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x2;  immval:0x1f
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x2, 0x1f, x1, 64, x2)
+
+inst_32:
+// imm_val == 23, rs1_val == 4096
+// opcode: srai ; op1:x10; dest:x11; op1val:0x1000;  immval:0x17
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x1000, 0x17, x1, 68, x2)
+
+inst_33:
+// imm_val == 27, rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x1b
+TEST_IMM_OP( srai, x11, x10, -0xb, -0x55555556, 0x1b, x1, 72, x2)
+
+inst_34:
+// imm_val == 29, rs1_val == 0 and imm_val >= 0 and imm_val < xlen, rs1_val==0
+// opcode: srai ; op1:x10; dest:x11; op1val:0x0;  immval:0x1d
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x0, 0x1d, x1, 76, x2)
+
+inst_35:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0x2
+TEST_IMM_OP( srai, x11, x10, -0x20000000, -0x80000000, 0x2, x1, 80, x2)
+
+inst_36:
+// rs1_val == 1073741824, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x2
+TEST_IMM_OP( srai, x11, x10, 0x10000000, 0x40000000, 0x2, x1, 84, x2)
+
+inst_37:
+// rs1_val == 536870912, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x4
+TEST_IMM_OP( srai, x11, x10, 0x2000000, 0x20000000, 0x4, x1, 88, x2)
+
+inst_38:
+// rs1_val == 268435456, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x10000000;  immval:0xe
+TEST_IMM_OP( srai, x11, x10, 0x4000, 0x10000000, 0xe, x1, 92, x2)
+
+inst_39:
+// rs1_val == 134217728, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x8000000;  immval:0x15
+TEST_IMM_OP( srai, x11, x10, 0x40, 0x8000000, 0x15, x1, 96, x2)
+
+inst_40:
+// rs1_val == 67108864, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x4000000;  immval:0xc
+TEST_IMM_OP( srai, x11, x10, 0x4000, 0x4000000, 0xc, x1, 100, x2)
+
+inst_41:
+// rs1_val == 33554432, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x9
+TEST_IMM_OP( srai, x11, x10, 0x10000, 0x2000000, 0x9, x1, 104, x2)
+
+inst_42:
+// rs1_val == 16777216, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x1000000;  immval:0xe
+TEST_IMM_OP( srai, x11, x10, 0x400, 0x1000000, 0xe, x1, 108, x2)
+
+inst_43:
+// rs1_val == 8388608, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x800000;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, 0x1000, 0x800000, 0xb, x1, 112, x2)
+
+inst_44:
+// rs1_val == 4194304, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x400000;  immval:0x11
+TEST_IMM_OP( srai, x11, x10, 0x20, 0x400000, 0x11, x1, 116, x2)
+
+inst_45:
+// rs1_val == 2097152, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x200000;  immval:0x4
+TEST_IMM_OP( srai, x11, x10, 0x20000, 0x200000, 0x4, x1, 120, x2)
+
+inst_46:
+// rs1_val == 1048576, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x100000;  immval:0x1b
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x100000, 0x1b, x1, 124, x2)
+
+inst_47:
+// rs1_val == 524288, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x80000;  immval:0x17
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x80000, 0x17, x1, 128, x2)
+
+inst_48:
+// rs1_val == 262144, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x40000;  immval:0x11
+TEST_IMM_OP( srai, x11, x10, 0x2, 0x40000, 0x11, x1, 132, x2)
+
+inst_49:
+// rs1_val == 131072, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x20000;  immval:0x9
+TEST_IMM_OP( srai, x11, x10, 0x100, 0x20000, 0x9, x1, 136, x2)
+
+inst_50:
+// rs1_val == 65536, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x10000;  immval:0x10
+TEST_IMM_OP( srai, x11, x10, 0x1, 0x10000, 0x10, x1, 140, x2)
+
+inst_51:
+// rs1_val == 32768, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x8000;  immval:0xa
+TEST_IMM_OP( srai, x11, x10, 0x20, 0x8000, 0xa, x1, 144, x2)
+
+inst_52:
+// rs1_val == 16384, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x4000;  immval:0x12
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x4000, 0x12, x1, 148, x2)
+
+inst_53:
+// rs1_val == 8192, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x2000;  immval:0x5
+TEST_IMM_OP( srai, x11, x10, 0x100, 0x2000, 0x5, x1, 152, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x800;  immval:0x6
+TEST_IMM_OP( srai, x11, x10, 0x20, 0x800, 0x6, x1, 156, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x400;  immval:0x17
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x400, 0x17, x1, 160, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x200;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x200, 0xb, x1, 164, x2)
+
+inst_57:
+// rs1_val == 256, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x100;  immval:0x9
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x100, 0x9, x1, 168, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x80;  immval:0x2
+TEST_IMM_OP( srai, x11, x10, 0x20, 0x80, 0x2, x1, 172, x2)
+
+inst_59:
+// rs1_val == 64, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x40;  immval:0x11
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x40, 0x11, x1, 176, x2)
+
+inst_60:
+// rs1_val == 32, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x20;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x20, 0xb, x1, 180, x2)
+
+inst_61:
+// rs1_val == 16, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x10;  immval:0xd
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x10, 0xd, x1, 184, x2)
+
+inst_62:
+// rs1_val == 8, rs1_val > 0 and imm_val == (xlen-1)
+// opcode: srai ; op1:x10; dest:x11; op1val:0x8;  immval:0x1f
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x8, 0x1f, x1, 188, x2)
+
+inst_63:
+// rs1_val == 4, rs1_val==4
+// opcode: srai ; op1:x10; dest:x11; op1val:0x4;  immval:0x1f
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x4, 0x1f, x1, 192, x2)
+
+inst_64:
+// rs1_val == 2, rs1_val==2
+// opcode: srai ; op1:x10; dest:x11; op1val:0x2;  immval:0xc
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x2, 0xc, x1, 196, x2)
+
+inst_65:
+// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen
+// opcode: srai ; op1:x10; dest:x11; op1val:0x1;  immval:0x9
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x1, 0x9, x1, 200, x2)
+
+inst_66:
+// rs1_val==46341, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0xb505;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, 0x16, 0xb505, 0xb, x1, 204, x2)
+
+inst_67:
+// rs1_val==-46339, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0xb503;  immval:0xf
+TEST_IMM_OP( srai, x11, x10, -0x2, -0xb503, 0xf, x1, 208, x2)
+
+inst_68:
+// rs1_val==1717986919, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x8
+TEST_IMM_OP( srai, x11, x10, 0x666666, 0x66666667, 0x8, x1, 212, x2)
+
+inst_69:
+// rs1_val==858993460, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xc
+TEST_IMM_OP( srai, x11, x10, 0x33333, 0x33333334, 0xc, x1, 216, x2)
+
+inst_70:
+// rs1_val==6, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x6;  immval:0x17
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x6, 0x17, x1, 220, x2)
+
+inst_71:
+// rs1_val==-1431655765, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0xb
+TEST_IMM_OP( srai, x11, x10, -0xaaaab, -0x55555555, 0xb, x1, 224, x2)
+
+inst_72:
+// rs1_val==3, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x3;  immval:0x8
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x3, 0x8, x1, 228, x2)
+
+inst_73:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: srai ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x1e
+TEST_IMM_OP( srai, x11, x10, 0x1, 0x55555555, 0x1e, x1, 232, x2)
+
+inst_74:
+// rs1_val == imm_val and imm_val > 0 and imm_val < xlen, rs1_val==5
+// opcode: srai ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( srai, x11, x10, 0x0, 0x5, 0x5, x1, 236, x2)
+
+inst_75:
+// rs1_val > 0 and imm_val == 0, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( srai, x11, x10, 0x2, 0x2, 0x0, x1, 240, x2)
+
+inst_76:
+// rs1_val==1431655766, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( srai, x11, x10, 0x15555555, 0x55555556, 0x2, x1, 244, x2)
+
+inst_77:
+// rs1_val==46339, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0xb503;  immval:0x1
+TEST_IMM_OP( srai, x11, x10, 0x5a81, 0xb503, 0x1, x1, 248, x2)
+
+inst_78:
+// rs1_val==1717986917, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x10
+TEST_IMM_OP( srai, x11, x10, 0x6666, 0x66666665, 0x10, x1, 252, x2)
+
+inst_79:
+// rs1_val==858993458, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x12
+TEST_IMM_OP( srai, x11, x10, 0xccc, 0x33333332, 0x12, x1, 256, x2)
+
+inst_80:
+// rs1_val==1431655764, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x1b
+TEST_IMM_OP( srai, x11, x10, 0xa, 0x55555554, 0x1b, x1, 260, x2)
+
+inst_81:
+// rs1_val==46340, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0xb504;  immval:0x1e
+TEST_IMM_OP( srai, x11, x10, 0x0, 0xb504, 0x1e, x1, 264, x2)
+
+inst_82:
+// rs1_val==-46340, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x11
+TEST_IMM_OP( srai, x11, x10, -0x1, -0xb504, 0x11, x1, 268, x2)
+
+inst_83:
+// rs1_val==1717986918, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x66666666;  immval:0xe
+TEST_IMM_OP( srai, x11, x10, 0x19999, 0x66666666, 0xe, x1, 272, x2)
+
+inst_84:
+// rs1_val==858993459, 
+// opcode: srai ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x12
+TEST_IMM_OP( srai, x11, x10, 0xccc, 0x33333333, 0x12, x1, 276, x2)
+
+inst_85:
+// rs1_val < 0 and imm_val == (xlen-1), rs1_val == -536870913, rs1_val < 0 and imm_val > 0 and imm_val < xlen
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x20000001;  immval:0x1f
+TEST_IMM_OP( srai, x11, x10, -0x1, -0x20000001, 0x1f, x1, 280, x2)
+
+inst_86:
+// rs1_val == -16777217, 
+// opcode: srai ; op1:x10; dest:x11; op1val:-0x1000001;  immval:0x12
+TEST_IMM_OP( srai, x11, x10, -0x41, -0x1000001, 0x12, x1, 284, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 72*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S
new file mode 100644
index 000000000..80f27c5fd
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S
@@ -0,0 +1,526 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the srl instruction of the RISC-V E extension for the srl covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srl)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x4, rd==x7, rs1_val < 0 and rs2_val == 0, rs1_val == -9
+// opcode: srl ; op1:x10; op2:x4; dest:x7; op1val:-0x9;  op2val:0x0
+TEST_RR_OP(srl, x7, x10, x4, 0xfffffff7, -0x9, 0x0, x1, 0, x6)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x15, rs2==x0, rd==x15, rs2_val == 15, rs1_val < 0 and rs2_val > 0 and rs2_val < xlen
+// opcode: srl ; op1:x15; op2:x0; dest:x15; op1val:-0x6;  op2val:0x0
+TEST_RR_OP(srl, x15, x15, x0, 0xfffffffa, -0x6, 0x0, x1, 4, x6)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x2, rs2==x3, rd==x3, rs2_val == 23, rs1_val == -2049
+// opcode: srl ; op1:x2; op2:x3; dest:x3; op1val:-0x801;  op2val:0x17
+TEST_RR_OP(srl, x3, x2, x3, 0x1ff, -0x801, 0x17, x1, 8, x6)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x5, rs2==x5, rd==x12, rs2_val == 27, rs1_val == -1048577
+// opcode: srl ; op1:x5; op2:x5; dest:x12; op1val:-0x100001;  op2val:-0x100001
+TEST_RR_OP(srl, x12, x5, x5, 0x1, -0x100001, -0x100001, x1, 12, x6)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14, rs2_val == 29, rs1_val == -16777217
+// opcode: srl ; op1:x14; op2:x14; dest:x14; op1val:-0x1000001;  op2val:-0x1000001
+TEST_RR_OP(srl, x14, x14, x14, 0x1, -0x1000001, -0x1000001, x1, 16, x6)
+
+inst_5:
+// rs1==x12, rs2==x10, rd==x2, rs2_val == 30, rs1_val == -1073741825
+// opcode: srl ; op1:x12; op2:x10; dest:x2; op1val:-0x40000001;  op2val:0x1e
+TEST_RR_OP(srl, x2, x12, x10, 0x2, -0x40000001, 0x1e, x1, 20, x6)
+
+inst_6:
+// rs1==x11, rs2==x15, rd==x9, rs1_val == 2147483647, rs1_val > 0 and rs2_val > 0 and rs2_val < xlen, rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen
+// opcode: srl ; op1:x11; op2:x15; dest:x9; op1val:0x7fffffff;  op2val:0x1b
+TEST_RR_OP(srl, x9, x11, x15, 0xf, 0x7fffffff, 0x1b, x1, 24, x6)
+
+inst_7:
+// rs1==x4, rs2==x6, rd==x10, rs1_val == -536870913, 
+// opcode: srl ; op1:x4; op2:x6; dest:x10; op1val:-0x20000001;  op2val:0x13
+TEST_RR_OP(srl, x10, x4, x6, 0x1bff, -0x20000001, 0x13, x1, 28, x2)
+RVTEST_SIGBASE( x10,signature_x10_0)
+
+inst_8:
+// rs1==x0, rs2==x9, rd==x8, rs1_val == -268435457, 
+// opcode: srl ; op1:x0; op2:x9; dest:x8; op1val:0x0;  op2val:0xe
+TEST_RR_OP(srl, x8, x0, x9, 0x0, 0x0, 0xe, x10, 0, x2)
+
+inst_9:
+// rs1==x1, rs2==x7, rd==x11, rs1_val == -134217729, 
+// opcode: srl ; op1:x1; op2:x7; dest:x11; op1val:-0x8000001;  op2val:0x13
+TEST_RR_OP(srl, x11, x1, x7, 0x1eff, -0x8000001, 0x13, x10, 4, x2)
+
+inst_10:
+// rs1==x7, rs2==x12, rd==x5, rs1_val == -67108865, 
+// opcode: srl ; op1:x7; op2:x12; dest:x5; op1val:-0x4000001;  op2val:0x1b
+TEST_RR_OP(srl, x5, x7, x12, 0x1f, -0x4000001, 0x1b, x10, 8, x2)
+
+inst_11:
+// rs1==x6, rs2==x13, rd==x1, rs1_val == -33554433, 
+// opcode: srl ; op1:x6; op2:x13; dest:x1; op1val:-0x2000001;  op2val:0x6
+TEST_RR_OP(srl, x1, x6, x13, 0x3f7ffff, -0x2000001, 0x6, x10, 12, x2)
+
+inst_12:
+// rs1==x9, rs2==x8, rd==x4, rs1_val == -8388609, 
+// opcode: srl ; op1:x9; op2:x8; dest:x4; op1val:-0x800001;  op2val:0xe
+TEST_RR_OP(srl, x4, x9, x8, 0x3fdff, -0x800001, 0xe, x10, 16, x2)
+
+inst_13:
+// rs1==x3, rs2==x11, rd==x6, rs1_val == -4194305, rs2_val == 8
+// opcode: srl ; op1:x3; op2:x11; dest:x6; op1val:-0x400001;  op2val:0x8
+TEST_RR_OP(srl, x6, x3, x11, 0xffbfff, -0x400001, 0x8, x10, 20, x2)
+
+inst_14:
+// rs1==x13, rs2==x1, rd==x0, rs1_val == -2097153, rs2_val == 4
+// opcode: srl ; op1:x13; op2:x1; dest:x0; op1val:-0x200001;  op2val:0x4
+TEST_RR_OP(srl, x0, x13, x1, 0, -0x200001, 0x4, x10, 24, x3)
+
+inst_15:
+// rs1==x8, rs2==x2, rd==x13, rs1_val == -524289, 
+// opcode: srl ; op1:x8; op2:x2; dest:x13; op1val:-0x80001;  op2val:0x1d
+TEST_RR_OP(srl, x13, x8, x2, 0x7, -0x80001, 0x1d, x10, 28, x3)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_16:
+// rs1_val == -262145, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0x4
+TEST_RR_OP(srl, x12, x10, x11, 0xfffbfff, -0x40001, 0x4, x1, 0, x3)
+
+inst_17:
+// rs1_val == -131073, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x8
+TEST_RR_OP(srl, x12, x10, x11, 0xfffdff, -0x20001, 0x8, x1, 4, x3)
+
+inst_18:
+// rs1_val == -65537, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:0x1e
+TEST_RR_OP(srl, x12, x10, x11, 0x3, -0x10001, 0x1e, x1, 8, x3)
+
+inst_19:
+// rs1_val == -32769, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x1d
+TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x8001, 0x1d, x1, 12, x3)
+
+inst_20:
+// rs1_val == -16385, rs2_val == 10
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0xa
+TEST_RR_OP(srl, x12, x10, x11, 0x3fffef, -0x4001, 0xa, x1, 16, x3)
+
+inst_21:
+// rs1_val == -8193, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x3ffff, -0x2001, 0xe, x1, 20, x3)
+
+inst_22:
+// rs1_val == -4097, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x1f
+TEST_RR_OP(srl, x12, x10, x11, 0x1, -0x1001, 0x1f, x1, 24, x3)
+
+inst_23:
+// rs1_val == -1025, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x1e
+TEST_RR_OP(srl, x12, x10, x11, 0x3, -0x401, 0x1e, x1, 28, x3)
+
+inst_24:
+// rs1_val == -513, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x11
+TEST_RR_OP(srl, x12, x10, x11, 0x7fff, -0x201, 0x11, x1, 32, x3)
+
+inst_25:
+// rs1_val == -257, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x1d
+TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x101, 0x1d, x1, 36, x3)
+
+inst_26:
+// rs1_val == -129, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0xd
+TEST_RR_OP(srl, x12, x10, x11, 0x7ffff, -0x81, 0xd, x1, 40, x3)
+
+inst_27:
+// rs1_val == -65, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:0x9
+TEST_RR_OP(srl, x12, x10, x11, 0x7fffff, -0x41, 0x9, x1, 44, x3)
+
+inst_28:
+// rs1_val == -33, rs2_val == 21
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x15
+TEST_RR_OP(srl, x12, x10, x11, 0x7ff, -0x21, 0x15, x1, 48, x3)
+
+inst_29:
+// rs1_val == -17, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x3ffff, -0x11, 0xe, x1, 52, x3)
+
+inst_30:
+// rs1_val == -5, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x0
+TEST_RR_OP(srl, x12, x10, x11, 0xfffffffb, -0x5, 0x0, x1, 56, x3)
+
+inst_31:
+// rs1_val == -3, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0x1f
+TEST_RR_OP(srl, x12, x10, x11, 0x1, -0x3, 0x1f, x1, 60, x3)
+
+inst_32:
+// rs1_val == -2, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x5
+TEST_RR_OP(srl, x12, x10, x11, 0x7ffffff, -0x2, 0x5, x1, 64, x3)
+
+inst_33:
+// rs2_val == 16, rs1_val == 524288
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x10
+TEST_RR_OP(srl, x12, x10, x11, 0x8, 0x80000, 0x10, x1, 68, x3)
+
+inst_34:
+// rs2_val == 2, rs1_val==46341
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(srl, x12, x10, x11, 0x2d41, 0xb505, 0x2, x1, 72, x3)
+
+inst_35:
+// rs2_val == 1, rs1_val == 268435456
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x1
+TEST_RR_OP(srl, x12, x10, x11, 0x8000000, 0x10000000, 0x1, x1, 76, x3)
+
+inst_36:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x17
+TEST_RR_OP(srl, x12, x10, x11, 0x100, -0x80000000, 0x17, x1, 80, x3)
+
+inst_37:
+// rs1_val == 1073741824, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x6
+TEST_RR_OP(srl, x12, x10, x11, 0x1000000, 0x40000000, 0x6, x1, 84, x3)
+
+inst_38:
+// rs1_val == 536870912, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0xa
+TEST_RR_OP(srl, x12, x10, x11, 0x80000, 0x20000000, 0xa, x1, 88, x3)
+
+inst_39:
+// rs1_val == 134217728, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x11
+TEST_RR_OP(srl, x12, x10, x11, 0x400, 0x8000000, 0x11, x1, 92, x3)
+
+inst_40:
+// rs1_val == 67108864, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x1000, 0x4000000, 0xe, x1, 96, x3)
+
+inst_41:
+// rs1_val == 33554432, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x12
+TEST_RR_OP(srl, x12, x10, x11, 0x80, 0x2000000, 0x12, x1, 100, x3)
+
+inst_42:
+// rs1_val == 16777216, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0xa
+TEST_RR_OP(srl, x12, x10, x11, 0x4000, 0x1000000, 0xa, x1, 104, x3)
+
+inst_43:
+// rs1_val == 8388608, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0x13
+TEST_RR_OP(srl, x12, x10, x11, 0x10, 0x800000, 0x13, x1, 108, x3)
+
+inst_44:
+// rs1_val == 4194304, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0xb
+TEST_RR_OP(srl, x12, x10, x11, 0x800, 0x400000, 0xb, x1, 112, x3)
+
+inst_45:
+// rs1_val == 2097152, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x8
+TEST_RR_OP(srl, x12, x10, x11, 0x2000, 0x200000, 0x8, x1, 116, x3)
+
+inst_46:
+// rs1_val == 1048576, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x100000, 0xe, x1, 120, x3)
+
+inst_47:
+// rs1_val == 262144, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:0x11
+TEST_RR_OP(srl, x12, x10, x11, 0x2, 0x40000, 0x11, x1, 124, x3)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x8, 0x20000, 0xe, x1, 128, x3)
+
+inst_49:
+// rs1_val == 65536, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x13
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x10000, 0x13, x1, 132, x3)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0xf
+TEST_RR_OP(srl, x12, x10, x11, 0x1, 0x8000, 0xf, x1, 136, x3)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x1, 0x4000, 0xe, x1, 140, x3)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0x8
+TEST_RR_OP(srl, x12, x10, x11, 0x20, 0x2000, 0x8, x1, 144, x3)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x6
+TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x1000, 0x6, x1, 148, x3)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x1b
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x800, 0x1b, x1, 152, x3)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x13
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x400, 0x13, x1, 156, x3)
+
+inst_56:
+// rs1_val == 512, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x3
+TEST_RR_OP(srl, x12, x10, x11, 0x40, 0x200, 0x3, x1, 160, x3)
+
+inst_57:
+// rs1_val == 256, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x1e
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x100, 0x1e, x1, 164, x3)
+
+inst_58:
+// rs1_val == 128, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0xa
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x80, 0xa, x1, 168, x3)
+
+inst_59:
+// rs1_val == 64, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0x4
+TEST_RR_OP(srl, x12, x10, x11, 0x4, 0x40, 0x4, x1, 172, x3)
+
+inst_60:
+// rs1_val == 32, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0xd
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x20, 0xd, x1, 176, x3)
+
+inst_61:
+// rs1_val == 16, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x11
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x10, 0x11, x1, 180, x3)
+
+inst_62:
+// rs1_val == 8, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x12
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x8, 0x12, x1, 184, x3)
+
+inst_63:
+// rs1_val == 4, rs1_val==4
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x10
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x4, 0x10, x1, 188, x3)
+
+inst_64:
+// rs1_val == 2, rs1_val==2, rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x2, 0x2, x1, 192, x3)
+
+inst_65:
+// rs1_val == 1, rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x1f
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x1, 0x1f, x1, 196, x3)
+
+inst_66:
+// rs1_val==-46339, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(srl, x12, x10, x11, 0x3fffd2b, -0xb503, 0x6, x1, 200, x3)
+
+inst_67:
+// rs1_val==1717986919, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x19999, 0x66666667, 0xe, x1, 204, x3)
+
+inst_68:
+// rs1_val==858993460, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x9
+TEST_RR_OP(srl, x12, x10, x11, 0x199999, 0x33333334, 0x9, x1, 208, x3)
+
+inst_69:
+// rs1_val==6, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xd
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x6, 0xd, x1, 212, x3)
+
+inst_70:
+// rs1_val==-1431655765, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x2aaaa, -0x55555555, 0xe, x1, 216, x3)
+
+inst_71:
+// rs1_val==1431655766, rs1_val > 0 and rs2_val == 0
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(srl, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 220, x3)
+
+inst_72:
+// rs1_val==46339, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xd
+TEST_RR_OP(srl, x12, x10, x11, 0x5, 0xb503, 0xd, x1, 224, x3)
+
+inst_73:
+// rs1_val==3, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xf
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x3, 0xf, x1, 228, x3)
+
+inst_74:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(srl, x12, x10, x11, 0xaaaaaaa, -0x55555556, 0x4, x1, 232, x3)
+
+inst_75:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x7
+TEST_RR_OP(srl, x12, x10, x11, 0xaaaaaa, 0x55555555, 0x7, x1, 236, x3)
+
+inst_76:
+// rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen, rs1_val==0
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x0, 0x7, x1, 240, x3)
+
+inst_77:
+// rs1_val==1717986917, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x1b
+TEST_RR_OP(srl, x12, x10, x11, 0xc, 0x66666665, 0x1b, x1, 244, x3)
+
+inst_78:
+// rs1_val==858993458, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x11
+TEST_RR_OP(srl, x12, x10, x11, 0x1999, 0x33333332, 0x11, x1, 248, x3)
+
+inst_79:
+// rs1_val==1431655764, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x13
+TEST_RR_OP(srl, x12, x10, x11, 0xaaa, 0x55555554, 0x13, x1, 252, x3)
+
+inst_80:
+// rs1_val==46340, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x12
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0xb504, 0x12, x1, 256, x3)
+
+inst_81:
+// rs1_val==-46340, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(srl, x12, x10, x11, 0xffff4af, -0xb504, 0x4, x1, 260, x3)
+
+inst_82:
+// rs1_val==1717986918, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x1b
+TEST_RR_OP(srl, x12, x10, x11, 0xc, 0x66666666, 0x1b, x1, 264, x3)
+
+inst_83:
+// rs1_val==858993459, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x15
+TEST_RR_OP(srl, x12, x10, x11, 0x199, 0x33333333, 0x15, x1, 268, x3)
+
+inst_84:
+// rs1_val==5, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x10
+TEST_RR_OP(srl, x12, x10, x11, 0x0, 0x5, 0x10, x1, 272, x3)
+
+inst_85:
+// rs2_val == 27, rs1_val == -1048577
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x1b
+TEST_RR_OP(srl, x12, x10, x11, 0x1f, -0x100001, 0x1b, x1, 276, x3)
+
+inst_86:
+// rs2_val == 29, rs1_val == -16777217
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x1d
+TEST_RR_OP(srl, x12, x10, x11, 0x7, -0x1000001, 0x1d, x1, 280, x3)
+
+inst_87:
+// rs1_val == -268435457, 
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:0xe
+TEST_RR_OP(srl, x12, x10, x11, 0x3bfff, -0x10000001, 0xe, x1, 284, x3)
+
+inst_88:
+// rs1_val == -2097153, rs2_val == 4
+// opcode: srl ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0x4
+TEST_RR_OP(srl, x12, x10, x11, 0xffdffff, -0x200001, 0x4, x1, 288, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 73*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S
new file mode 100644
index 000000000..8ecc2f5dc
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S
@@ -0,0 +1,521 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the srli instruction of the RISC-V E extension for the srli covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",srli)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x4, rd==x5, rs1_val < 0 and imm_val == (xlen-1), rs1_val == -65, rs1_val < 0 and imm_val > 0 and imm_val < xlen
+// opcode: srli ; op1:x4; dest:x5; op1val:-0x41;  immval:0x1f
+TEST_IMM_OP( srli, x5, x4, 0x1, -0x41, 0x1f, x1, 0, x10)
+
+inst_1:
+// rs1 == rd, rs1==x9, rd==x9, rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val > 0 and imm_val < xlen, imm_val == 8
+// opcode: srli ; op1:x9; dest:x9; op1val:0x7fffffff;  immval:0x8
+TEST_IMM_OP( srli, x9, x9, 0x7fffff, 0x7fffffff, 0x8, x1, 4, x10)
+
+inst_2:
+// rs1==x0, rd==x6, rs1_val == -1073741825, imm_val == 23
+// opcode: srli ; op1:x0; dest:x6; op1val:0x0;  immval:0x17
+TEST_IMM_OP( srli, x6, x0, 0x0, 0x0, 0x17, x1, 8, x10)
+
+inst_3:
+// rs1==x12, rd==x4, rs1_val == -536870913, 
+// opcode: srli ; op1:x12; dest:x4; op1val:-0x20000001;  immval:0x6
+TEST_IMM_OP( srli, x4, x12, 0x37fffff, -0x20000001, 0x6, x1, 12, x10)
+
+inst_4:
+// rs1==x8, rd==x14, rs1_val == -268435457, imm_val == 10
+// opcode: srli ; op1:x8; dest:x14; op1val:-0x10000001;  immval:0xa
+TEST_IMM_OP( srli, x14, x8, 0x3bffff, -0x10000001, 0xa, x1, 16, x10)
+
+inst_5:
+// rs1==x7, rd==x3, rs1_val == -134217729, imm_val == 2
+// opcode: srli ; op1:x7; dest:x3; op1val:-0x8000001;  immval:0x2
+TEST_IMM_OP( srli, x3, x7, 0x3dffffff, -0x8000001, 0x2, x1, 20, x10)
+
+inst_6:
+// rs1==x6, rd==x2, rs1_val == -67108865, 
+// opcode: srli ; op1:x6; dest:x2; op1val:-0x4000001;  immval:0x12
+TEST_IMM_OP( srli, x2, x6, 0x3eff, -0x4000001, 0x12, x1, 24, x10)
+
+inst_7:
+// rs1==x11, rd==x15, rs1_val == -33554433, imm_val == 16
+// opcode: srli ; op1:x11; dest:x15; op1val:-0x2000001;  immval:0x10
+TEST_IMM_OP( srli, x15, x11, 0xfdff, -0x2000001, 0x10, x1, 28, x10)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_8:
+// rs1==x5, rd==x13, rs1_val == -16777217, imm_val == 1
+// opcode: srli ; op1:x5; dest:x13; op1val:-0x1000001;  immval:0x1
+TEST_IMM_OP( srli, x13, x5, 0x7f7fffff, -0x1000001, 0x1, x4, 0, x6)
+
+inst_9:
+// rs1==x15, rd==x11, rs1_val == -8388609, 
+// opcode: srli ; op1:x15; dest:x11; op1val:-0x800001;  immval:0x11
+TEST_IMM_OP( srli, x11, x15, 0x7fbf, -0x800001, 0x11, x4, 4, x6)
+
+inst_10:
+// rs1==x2, rd==x12, rs1_val == -4194305, imm_val == 15
+// opcode: srli ; op1:x2; dest:x12; op1val:-0x400001;  immval:0xf
+TEST_IMM_OP( srli, x12, x2, 0x1ff7f, -0x400001, 0xf, x4, 8, x6)
+
+inst_11:
+// rs1==x14, rd==x7, rs1_val == -2097153, 
+// opcode: srli ; op1:x14; dest:x7; op1val:-0x200001;  immval:0x7
+TEST_IMM_OP( srli, x7, x14, 0x1ffbfff, -0x200001, 0x7, x4, 12, x6)
+
+inst_12:
+// rs1==x13, rd==x0, rs1_val == -1048577, 
+// opcode: srli ; op1:x13; dest:x0; op1val:-0x100001;  immval:0xc
+TEST_IMM_OP( srli, x0, x13, 0, -0x100001, 0xc, x4, 16, x6)
+
+inst_13:
+// rs1==x3, rd==x10, rs1_val == -524289, imm_val == 21
+// opcode: srli ; op1:x3; dest:x10; op1val:-0x80001;  immval:0x15
+TEST_IMM_OP( srli, x10, x3, 0x7ff, -0x80001, 0x15, x4, 20, x6)
+
+inst_14:
+// rs1==x10, rd==x1, rs1_val == -262145, 
+// opcode: srli ; op1:x10; dest:x1; op1val:-0x40001;  immval:0x10
+TEST_IMM_OP( srli, x1, x10, 0xfffb, -0x40001, 0x10, x4, 24, x6)
+
+inst_15:
+// rs1==x1, rd==x8, rs1_val == -131073, 
+// opcode: srli ; op1:x1; dest:x8; op1val:-0x20001;  immval:0x11
+TEST_IMM_OP( srli, x8, x1, 0x7ffe, -0x20001, 0x11, x4, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_16:
+// rs1_val == -65537, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x10001;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0x1fffdf, -0x10001, 0xb, x1, 0, x2)
+
+inst_17:
+// rs1_val == -32769, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x12
+TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x8001, 0x12, x1, 4, x2)
+
+inst_18:
+// rs1_val == -16385, rs1_val < 0 and imm_val == 0
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x4001;  immval:0x0
+TEST_IMM_OP( srli, x11, x10, 0xffffbfff, -0x4001, 0x0, x1, 8, x2)
+
+inst_19:
+// rs1_val == -8193, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x2001;  immval:0x13
+TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x2001, 0x13, x1, 12, x2)
+
+inst_20:
+// rs1_val == -4097, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x1001;  immval:0xa
+TEST_IMM_OP( srli, x11, x10, 0x3ffffb, -0x1001, 0xa, x1, 16, x2)
+
+inst_21:
+// rs1_val == -2049, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x801;  immval:0x15
+TEST_IMM_OP( srli, x11, x10, 0x7ff, -0x801, 0x15, x1, 20, x2)
+
+inst_22:
+// rs1_val == -1025, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x401;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0x3ffffef, -0x401, 0x6, x1, 24, x2)
+
+inst_23:
+// rs1_val == -513, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x201;  immval:0x13
+TEST_IMM_OP( srli, x11, x10, 0x1fff, -0x201, 0x13, x1, 28, x2)
+
+inst_24:
+// rs1_val == -257, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x101;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0xfffffe, -0x101, 0x8, x1, 32, x2)
+
+inst_25:
+// rs1_val == -129, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x81;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0xffffff, -0x81, 0x8, x1, 36, x2)
+
+inst_26:
+// rs1_val == -33, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x21;  immval:0x2
+TEST_IMM_OP( srli, x11, x10, 0x3ffffff7, -0x21, 0x2, x1, 40, x2)
+
+inst_27:
+// rs1_val == -17, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x11;  immval:0x12
+TEST_IMM_OP( srli, x11, x10, 0x3fff, -0x11, 0x12, x1, 44, x2)
+
+inst_28:
+// rs1_val == -9, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x9;  immval:0x2
+TEST_IMM_OP( srli, x11, x10, 0x3ffffffd, -0x9, 0x2, x1, 48, x2)
+
+inst_29:
+// rs1_val == -5, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x5;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0x3ffffff, -0x5, 0x6, x1, 52, x2)
+
+inst_30:
+// rs1_val == -3, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x3;  immval:0xf
+TEST_IMM_OP( srli, x11, x10, 0x1ffff, -0x3, 0xf, x1, 56, x2)
+
+inst_31:
+// rs1_val == -2, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x2;  immval:0xc
+TEST_IMM_OP( srli, x11, x10, 0xfffff, -0x2, 0xc, x1, 60, x2)
+
+inst_32:
+// imm_val == 27, rs1_val == 262144
+// opcode: srli ; op1:x10; dest:x11; op1val:0x40000;  immval:0x1b
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x40000, 0x1b, x1, 64, x2)
+
+inst_33:
+// imm_val == 29, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000000;  immval:0x1d
+TEST_IMM_OP( srli, x11, x10, 0x6, -0x40000000, 0x1d, x1, 68, x2)
+
+inst_34:
+// imm_val == 30, rs1_val == 64
+// opcode: srli ; op1:x10; dest:x11; op1val:0x40;  immval:0x1e
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x40, 0x1e, x1, 72, x2)
+
+inst_35:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x80000000;  immval:0xa
+TEST_IMM_OP( srli, x11, x10, 0x200000, -0x80000000, 0xa, x1, 76, x2)
+
+inst_36:
+// rs1_val == 1073741824, rs1_val > 0 and imm_val == 0
+// opcode: srli ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x0
+TEST_IMM_OP( srli, x11, x10, 0x40000000, 0x40000000, 0x0, x1, 80, x2)
+
+inst_37:
+// rs1_val == 536870912, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x11
+TEST_IMM_OP( srli, x11, x10, 0x1000, 0x20000000, 0x11, x1, 84, x2)
+
+inst_38:
+// rs1_val == 268435456, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x11
+TEST_IMM_OP( srli, x11, x10, 0x800, 0x10000000, 0x11, x1, 88, x2)
+
+inst_39:
+// rs1_val == 134217728, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x8000000;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0x10000, 0x8000000, 0xb, x1, 92, x2)
+
+inst_40:
+// rs1_val == 67108864, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x1e
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x4000000, 0x1e, x1, 96, x2)
+
+inst_41:
+// rs1_val == 33554432, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x2000000;  immval:0x13
+TEST_IMM_OP( srli, x11, x10, 0x40, 0x2000000, 0x13, x1, 100, x2)
+
+inst_42:
+// rs1_val == 16777216, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x1000000;  immval:0xd
+TEST_IMM_OP( srli, x11, x10, 0x800, 0x1000000, 0xd, x1, 104, x2)
+
+inst_43:
+// rs1_val == 8388608, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x800000;  immval:0x7
+TEST_IMM_OP( srli, x11, x10, 0x10000, 0x800000, 0x7, x1, 108, x2)
+
+inst_44:
+// rs1_val == 4194304, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x400000;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0x10000, 0x400000, 0x6, x1, 112, x2)
+
+inst_45:
+// rs1_val == 2097152, imm_val == 4
+// opcode: srli ; op1:x10; dest:x11; op1val:0x200000;  immval:0x4
+TEST_IMM_OP( srli, x11, x10, 0x20000, 0x200000, 0x4, x1, 116, x2)
+
+inst_46:
+// rs1_val == 1048576, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x100000;  immval:0x9
+TEST_IMM_OP( srli, x11, x10, 0x800, 0x100000, 0x9, x1, 120, x2)
+
+inst_47:
+// rs1_val == 524288, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x80000;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0x100, 0x80000, 0xb, x1, 124, x2)
+
+inst_48:
+// rs1_val == 131072, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x20000;  immval:0x10
+TEST_IMM_OP( srli, x11, x10, 0x2, 0x20000, 0x10, x1, 128, x2)
+
+inst_49:
+// rs1_val == 65536, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x10000;  immval:0x0
+TEST_IMM_OP( srli, x11, x10, 0x10000, 0x10000, 0x0, x1, 132, x2)
+
+inst_50:
+// rs1_val == 32768, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x8000;  immval:0x10
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x8000, 0x10, x1, 136, x2)
+
+inst_51:
+// rs1_val == 16384, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x4000;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0x100, 0x4000, 0x6, x1, 140, x2)
+
+inst_52:
+// rs1_val == 8192, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x2000;  immval:0x4
+TEST_IMM_OP( srli, x11, x10, 0x200, 0x2000, 0x4, x1, 144, x2)
+
+inst_53:
+// rs1_val == 4096, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x1000;  immval:0xf
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x1000, 0xf, x1, 148, x2)
+
+inst_54:
+// rs1_val == 2048, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x800;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0x8, 0x800, 0x8, x1, 152, x2)
+
+inst_55:
+// rs1_val == 1024, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x400;  immval:0x12
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x400, 0x12, x1, 156, x2)
+
+inst_56:
+// rs1_val == 512, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x200;  immval:0xe
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x200, 0xe, x1, 160, x2)
+
+inst_57:
+// rs1_val == 256, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x100;  immval:0x13
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x100, 0x13, x1, 164, x2)
+
+inst_58:
+// rs1_val == 128, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x80;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x80, 0x8, x1, 168, x2)
+
+inst_59:
+// rs1_val == 32, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x20;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x20, 0xb, x1, 172, x2)
+
+inst_60:
+// rs1_val == 16, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x10;  immval:0x17
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x10, 0x17, x1, 176, x2)
+
+inst_61:
+// rs1_val == 8, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x8;  immval:0x1d
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x8, 0x1d, x1, 180, x2)
+
+inst_62:
+// rs1_val == 4, rs1_val==4
+// opcode: srli ; op1:x10; dest:x11; op1val:0x4;  immval:0x9
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x9, x1, 184, x2)
+
+inst_63:
+// rs1_val == 2, rs1_val==2
+// opcode: srli ; op1:x10; dest:x11; op1val:0x2;  immval:0x11
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x2, 0x11, x1, 188, x2)
+
+inst_64:
+// rs1_val == 1, rs1_val == 1 and imm_val >= 0 and imm_val < xlen, rs1_val > 0 and imm_val == (xlen-1)
+// opcode: srli ; op1:x10; dest:x11; op1val:0x1;  immval:0x1f
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x1, 0x1f, x1, 192, x2)
+
+inst_65:
+// rs1_val==46341, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0xb505;  immval:0xd
+TEST_IMM_OP( srli, x11, x10, 0x5, 0xb505, 0xd, x1, 196, x2)
+
+inst_66:
+// rs1_val==-46339, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x7
+TEST_IMM_OP( srli, x11, x10, 0x1fffe95, -0xb503, 0x7, x1, 200, x2)
+
+inst_67:
+// rs1_val==1717986919, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x66666667;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0xccccc, 0x66666667, 0xb, x1, 204, x2)
+
+inst_68:
+// rs1_val==858993460, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x33333334;  immval:0xe
+TEST_IMM_OP( srli, x11, x10, 0xcccc, 0x33333334, 0xe, x1, 208, x2)
+
+inst_69:
+// rs1_val==6, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x6;  immval:0xe
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x6, 0xe, x1, 212, x2)
+
+inst_70:
+// rs1_val==-1431655765, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x1
+TEST_IMM_OP( srli, x11, x10, 0x55555555, -0x55555555, 0x1, x1, 216, x2)
+
+inst_71:
+// rs1_val==1431655766, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x10
+TEST_IMM_OP( srli, x11, x10, 0x5555, 0x55555556, 0x10, x1, 220, x2)
+
+inst_72:
+// rs1_val==46339, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0xb503;  immval:0x15
+TEST_IMM_OP( srli, x11, x10, 0x0, 0xb503, 0x15, x1, 224, x2)
+
+inst_73:
+// rs1_val==0, rs1_val == 0 and imm_val >= 0 and imm_val < xlen
+// opcode: srli ; op1:x10; dest:x11; op1val:0x0;  immval:0x17
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x0, 0x17, x1, 228, x2)
+
+inst_74:
+// rs1_val==3, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x3;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x3, 0x8, x1, 232, x2)
+
+inst_75:
+// rs1_val == -1431655766, rs1_val==-1431655766
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( srli, x11, x10, 0x2aaaaaaa, -0x55555556, 0x2, x1, 236, x2)
+
+inst_76:
+// rs1_val == 1431655765, rs1_val==1431655765
+// opcode: srli ; op1:x10; dest:x11; op1val:0x55555555;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0xaaaaa, 0x55555555, 0xb, x1, 240, x2)
+
+inst_77:
+// rs1_val == imm_val and imm_val > 0 and imm_val < xlen, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x4, 0x4, x1, 244, x2)
+
+inst_78:
+// rs1_val==1717986917, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x15
+TEST_IMM_OP( srli, x11, x10, 0x333, 0x66666665, 0x15, x1, 248, x2)
+
+inst_79:
+// rs1_val==858993458, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0xcccccc, 0x33333332, 0x6, x1, 252, x2)
+
+inst_80:
+// rs1_val==1431655764, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( srli, x11, x10, 0x1555555, 0x55555554, 0x6, x1, 256, x2)
+
+inst_81:
+// rs1_val==46340, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0xb504;  immval:0x17
+TEST_IMM_OP( srli, x11, x10, 0x0, 0xb504, 0x17, x1, 260, x2)
+
+inst_82:
+// rs1_val==-46340, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x8
+TEST_IMM_OP( srli, x11, x10, 0xffff4a, -0xb504, 0x8, x1, 264, x2)
+
+inst_83:
+// rs1_val==1717986918, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x9
+TEST_IMM_OP( srli, x11, x10, 0x333333, 0x66666666, 0x9, x1, 268, x2)
+
+inst_84:
+// rs1_val==858993459, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x1e
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x33333333, 0x1e, x1, 272, x2)
+
+inst_85:
+// rs1_val==5, 
+// opcode: srli ; op1:x10; dest:x11; op1val:0x5;  immval:0xb
+TEST_IMM_OP( srli, x11, x10, 0x0, 0x5, 0xb, x1, 276, x2)
+
+inst_86:
+// rs1_val == -1073741825, imm_val == 23
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x40000001;  immval:0x17
+TEST_IMM_OP( srli, x11, x10, 0x17f, -0x40000001, 0x17, x1, 280, x2)
+
+inst_87:
+// rs1_val == -1048577, 
+// opcode: srli ; op1:x10; dest:x11; op1val:-0x100001;  immval:0xc
+TEST_IMM_OP( srli, x11, x10, 0xffeff, -0x100001, 0xc, x1, 284, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 72*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S
new file mode 100644
index 000000000..60ce1b737
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S
@@ -0,0 +1,3006 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sub instruction of the RISC-V E extension for the sub covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sub)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x14, rs2==x9, rd==x4, rs1_val != rs2_val, rs1_val > 0 and rs2_val > 0, rs2_val == 4194304, rs1_val == 33554432
+// opcode: sub ; op1:x14; op2:x9; dest:x4; op1val:0x2000000;  op2val:0x400000
+TEST_RR_OP(sub, x4, x14, x9, 0x1c00000, 0x2000000, 0x400000, x3, 0, x5)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x1, rs2==x0, rd==x1, rs2_val == 2147483647, rs1_val == -4194305, rs1_val < 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: sub ; op1:x1; op2:x0; dest:x1; op1val:-0x400001;  op2val:0x0
+TEST_RR_OP(sub, x1, x1, x0, 0xffbfffff, -0x400001, 0x0, x3, 4, x5)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x11, rs2==x6, rd==x6, rs2_val == -1073741825, rs1_val < 0 and rs2_val < 0
+// opcode: sub ; op1:x11; op2:x6; dest:x6; op1val:-0x6;  op2val:-0x40000001
+TEST_RR_OP(sub, x6, x11, x6, 0x3ffffffb, -0x6, -0x40000001, x3, 8, x5)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x12, rs2==x12, rd==x15, rs2_val == -536870913, rs1_val == -8388609
+// opcode: sub ; op1:x12; op2:x12; dest:x15; op1val:-0x800001;  op2val:-0x800001
+TEST_RR_OP(sub, x15, x12, x12, 0x0, -0x800001, -0x800001, x3, 12, x5)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x13, rs2==x13, rd==x13, rs2_val == -268435457, rs1_val == -33554433
+// opcode: sub ; op1:x13; op2:x13; dest:x13; op1val:-0x2000001;  op2val:-0x2000001
+TEST_RR_OP(sub, x13, x13, x13, 0x0, -0x2000001, -0x2000001, x3, 16, x5)
+
+inst_5:
+// rs1==x10, rs2==x1, rd==x12, rs2_val == -134217729, rs1_val == -5
+// opcode: sub ; op1:x10; op2:x1; dest:x12; op1val:-0x5;  op2val:-0x8000001
+TEST_RR_OP(sub, x12, x10, x1, 0x7fffffc, -0x5, -0x8000001, x3, 20, x5)
+
+inst_6:
+// rs1==x7, rs2==x2, rd==x8, rs2_val == -67108865, rs1_val == 0
+// opcode: sub ; op1:x7; op2:x2; dest:x8; op1val:0x0;  op2val:-0x4000001
+TEST_RR_OP(sub, x8, x7, x2, 0x4000001, 0x0, -0x4000001, x3, 24, x5)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_7:
+// rs1==x5, rs2==x11, rd==x9, rs2_val == -33554433, rs1_val == -1025
+// opcode: sub ; op1:x5; op2:x11; dest:x9; op1val:-0x401;  op2val:-0x2000001
+TEST_RR_OP(sub, x9, x5, x11, 0x1fffc00, -0x401, -0x2000001, x1, 0, x10)
+
+inst_8:
+// rs1==x8, rs2==x3, rd==x14, rs2_val == -16777217, rs1_val == 16, rs1_val > 0 and rs2_val < 0
+// opcode: sub ; op1:x8; op2:x3; dest:x14; op1val:0x10;  op2val:-0x1000001
+TEST_RR_OP(sub, x14, x8, x3, 0x1000011, 0x10, -0x1000001, x1, 4, x10)
+
+inst_9:
+// rs1==x4, rs2==x15, rd==x5, rs2_val == -8388609, rs1_val == 128
+// opcode: sub ; op1:x4; op2:x15; dest:x5; op1val:0x80;  op2val:-0x800001
+TEST_RR_OP(sub, x5, x4, x15, 0x800081, 0x80, -0x800001, x1, 8, x10)
+
+inst_10:
+// rs1==x15, rs2==x4, rd==x2, rs2_val == -4194305, rs1_val == 2
+// opcode: sub ; op1:x15; op2:x4; dest:x2; op1val:0x2;  op2val:-0x400001
+TEST_RR_OP(sub, x2, x15, x4, 0x400003, 0x2, -0x400001, x1, 12, x10)
+
+inst_11:
+// rs1==x2, rs2==x14, rd==x7, rs2_val == -2097153, rs1_val == 4
+// opcode: sub ; op1:x2; op2:x14; dest:x7; op1val:0x4;  op2val:-0x200001
+TEST_RR_OP(sub, x7, x2, x14, 0x200005, 0x4, -0x200001, x1, 16, x10)
+
+inst_12:
+// rs1==x6, rs2==x7, rd==x3, rs2_val == -1048577, rs1_val == -513
+// opcode: sub ; op1:x6; op2:x7; dest:x3; op1val:-0x201;  op2val:-0x100001
+TEST_RR_OP(sub, x3, x6, x7, 0xffe00, -0x201, -0x100001, x1, 20, x10)
+
+inst_13:
+// rs1==x3, rs2==x8, rd==x0, rs2_val == -524289, rs1_val == -2
+// opcode: sub ; op1:x3; op2:x8; dest:x0; op1val:-0x2;  op2val:-0x80001
+TEST_RR_OP(sub, x0, x3, x8, 0, -0x2, -0x80001, x1, 24, x2)
+
+inst_14:
+// rs1==x0, rs2==x10, rd==x11, rs2_val == -262145, rs1_val == rs2_val, rs1_val == -262145
+// opcode: sub ; op1:x0; op2:x10; dest:x11; op1val:0x0;  op2val:-0x40001
+TEST_RR_OP(sub, x11, x0, x10, 0x40001, 0x0, -0x40001, x1, 28, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_15:
+// rs1==x9, rs2==x5, rd==x10, rs2_val == -131073, rs1_val == -2097153
+// opcode: sub ; op1:x9; op2:x5; dest:x10; op1val:-0x200001;  op2val:-0x20001
+TEST_RR_OP(sub, x10, x9, x5, 0xffe20000, -0x200001, -0x20001, x1, 0, x2)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:-0x10001
+TEST_RR_OP(sub, x12, x10, x11, 0xfffc, -0x5, -0x10001, x1, 4, x2)
+
+inst_17:
+// rs2_val == -32769, rs1_val == 64
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x8001
+TEST_RR_OP(sub, x12, x10, x11, 0x8041, 0x40, -0x8001, x1, 8, x2)
+
+inst_18:
+// rs2_val == -16385, rs1_val == -268435457
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:-0x4001
+TEST_RR_OP(sub, x12, x10, x11, 0xf0004000, -0x10000001, -0x4001, x1, 12, x2)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x2001
+TEST_RR_OP(sub, x12, x10, x11, 0x33335333, 0x33333332, -0x2001, x1, 16, x2)
+
+inst_20:
+// rs2_val == -4097, rs1_val == 536870912
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:-0x1001
+TEST_RR_OP(sub, x12, x10, x11, 0x20001001, 0x20000000, -0x1001, x1, 20, x2)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x801
+TEST_RR_OP(sub, x12, x10, x11, 0xffc00800, -0x400001, -0x801, x1, 24, x2)
+
+inst_22:
+// rs2_val == -1025, rs1_val == 32
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:-0x401
+TEST_RR_OP(sub, x12, x10, x11, 0x421, 0x20, -0x401, x1, 28, x2)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:-0x201
+TEST_RR_OP(sub, x12, x10, x11, 0xfffc0200, -0x40001, -0x201, x1, 32, x2)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x101
+TEST_RR_OP(sub, x12, x10, x11, 0xffe00100, -0x200001, -0x101, x1, 36, x2)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x81
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b7e, -0xb503, -0x81, x1, 40, x2)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x41
+TEST_RR_OP(sub, x12, x10, x11, 0x55555597, 0x55555556, -0x41, x1, 44, x2)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x21
+TEST_RR_OP(sub, x12, x10, x11, 0x23, 0x2, -0x21, x1, 48, x2)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x11
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaabc, -0x55555555, -0x11, x1, 52, x2)
+
+inst_29:
+// rs2_val == -9, rs1_val == 65536
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:-0x9
+TEST_RR_OP(sub, x12, x10, x11, 0x10009, 0x10000, -0x9, x1, 56, x2)
+
+inst_30:
+// rs2_val == -5, rs1_val == 262144
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:-0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x40005, 0x40000, -0x5, x1, 60, x2)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xb508, 0xb505, -0x3, x1, 64, x2)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4aff, -0xb503, -0x2, x1, 68, x2)
+
+inst_33:
+// rs1_val == 2147483647, rs1_val == (2**(xlen-1)-1), rs2_val == -1431655766
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xd5555555, 0x7fffffff, -0x55555556, x1, 72, x2)
+
+inst_34:
+// rs1_val == -1073741825, rs2_val == 67108864
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:0x4000000
+TEST_RR_OP(sub, x12, x10, x11, 0xbbffffff, -0x40000001, 0x4000000, x1, 76, x2)
+
+inst_35:
+// rs1_val == -536870913, rs2_val == 536870912
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x20000000
+TEST_RR_OP(sub, x12, x10, x11, 0xbfffffff, -0x20000001, 0x20000000, x1, 80, x2)
+
+inst_36:
+// rs1_val == -134217729, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x8001
+TEST_RR_OP(sub, x12, x10, x11, 0xf8008000, -0x8000001, -0x8001, x1, 84, x2)
+
+inst_37:
+// rs1_val == -67108865, rs2_val == 0
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xfbffffff, -0x4000001, 0x0, x1, 88, x2)
+
+inst_38:
+// rs1_val == -16777217, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcbcccccb, -0x1000001, 0x33333334, x1, 92, x2)
+
+inst_39:
+// rs1_val == -1048577, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x100001;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xccbccccb, -0x100001, 0x33333334, x1, 96, x2)
+
+inst_40:
+// rs1_val == -524289, rs2_val == 8388608
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:0x800000
+TEST_RR_OP(sub, x12, x10, x11, 0xff77ffff, -0x80001, 0x800000, x1, 100, x2)
+
+inst_41:
+// rs1_val == -131073, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xfffdfff9, -0x20001, 0x6, x1, 104, x2)
+
+inst_42:
+// rs1_val == -65537, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x81
+TEST_RR_OP(sub, x12, x10, x11, 0xffff0080, -0x10001, -0x81, x1, 108, x2)
+
+inst_43:
+// rs1_val == -32769, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xfffecafc, -0x8001, 0xb503, x1, 112, x2)
+
+inst_44:
+// rs1_val == -16385, rs2_val == 8
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:0x8
+TEST_RR_OP(sub, x12, x10, x11, 0xffffbff7, -0x4001, 0x8, x1, 116, x2)
+
+inst_45:
+// rs1_val == -8193, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:-0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xffffe003, -0x2001, -0x4, x1, 120, x2)
+
+inst_46:
+// rs1_val == -4097, rs2_val == 262144
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:0x40000
+TEST_RR_OP(sub, x12, x10, x11, 0xfffbefff, -0x1001, 0x40000, x1, 124, x2)
+
+inst_47:
+// rs1_val == -2049, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:-0x20000001
+TEST_RR_OP(sub, x12, x10, x11, 0x1ffff800, -0x801, -0x20000001, x1, 128, x2)
+
+inst_48:
+// rs1_val == -257, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:-0x8000001
+TEST_RR_OP(sub, x12, x10, x11, 0x7ffff00, -0x101, -0x8000001, x1, 132, x2)
+
+inst_49:
+// rs1_val == -129, rs2_val == 2048
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x800
+TEST_RR_OP(sub, x12, x10, x11, 0xfffff77f, -0x81, 0x800, x1, 136, x2)
+
+inst_50:
+// rs1_val == -65, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x41;  op2val:-0x10001
+TEST_RR_OP(sub, x12, x10, x11, 0xffc0, -0x41, -0x10001, x1, 140, x2)
+
+inst_51:
+// rs1_val == -33, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:-0x80001
+TEST_RR_OP(sub, x12, x10, x11, 0x7ffe0, -0x21, -0x80001, x1, 144, x2)
+
+inst_52:
+// rs1_val == -17, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:-0x200001
+TEST_RR_OP(sub, x12, x10, x11, 0x1ffff0, -0x11, -0x200001, x1, 148, x2)
+
+inst_53:
+// rs1_val == -9, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:-0x8000001
+TEST_RR_OP(sub, x12, x10, x11, 0x7fffff8, -0x9, -0x8000001, x1, 152, x2)
+
+inst_54:
+// rs1_val == -3, rs2_val == 8192
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0x2000
+TEST_RR_OP(sub, x12, x10, x11, 0xffffdffd, -0x3, 0x2000, x1, 156, x2)
+
+inst_55:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x80000000
+TEST_RR_OP(sub, x12, x10, x11, 0x2aaaaaab, -0x55555555, -0x80000000, x1, 160, x2)
+
+inst_56:
+// rs2_val == 1073741824, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x40000000
+TEST_RR_OP(sub, x12, x10, x11, 0xbfff7fff, -0x8001, 0x40000000, x1, 164, x2)
+
+inst_57:
+// rs2_val == 268435456, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0x10000000
+TEST_RR_OP(sub, x12, x10, x11, 0xf2000000, 0x2000000, 0x10000000, x1, 168, x2)
+
+inst_58:
+// rs2_val == 134217728, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x8000000
+TEST_RR_OP(sub, x12, x10, x11, 0xa2aaaaab, -0x55555555, 0x8000000, x1, 172, x2)
+
+inst_59:
+// rs2_val == 33554432, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x2000000
+TEST_RR_OP(sub, x12, x10, x11, 0xfdffdfff, -0x2001, 0x2000000, x1, 176, x2)
+
+inst_60:
+// rs2_val == 16777216, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x1000000
+TEST_RR_OP(sub, x12, x10, x11, 0xfeffffef, -0x11, 0x1000000, x1, 180, x2)
+
+inst_61:
+// rs2_val == 2097152, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0x200000
+TEST_RR_OP(sub, x12, x10, x11, 0xffe00010, 0x10, 0x200000, x1, 184, x2)
+
+inst_62:
+// rs2_val == 1048576, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x100000
+TEST_RR_OP(sub, x12, x10, x11, 0x33233333, 0x33333333, 0x100000, x1, 188, x2)
+
+inst_63:
+// rs2_val == 524288, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:0x80000
+TEST_RR_OP(sub, x12, x10, x11, 0xfef7ffff, -0x1000001, 0x80000, x1, 192, x2)
+
+inst_64:
+// rs2_val == 131072, rs1_val == 524288
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:0x20000
+TEST_RR_OP(sub, x12, x10, x11, 0x60000, 0x80000, 0x20000, x1, 196, x2)
+
+inst_65:
+// rs2_val == 65536, rs1_val == 134217728
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x10000
+TEST_RR_OP(sub, x12, x10, x11, 0x7ff0000, 0x8000000, 0x10000, x1, 200, x2)
+
+inst_66:
+// rs2_val == 32768, rs1_val == 2097152
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:0x8000
+TEST_RR_OP(sub, x12, x10, x11, 0x1f8000, 0x200000, 0x8000, x1, 204, x2)
+
+inst_67:
+// rs2_val == 16384, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:0x4000
+TEST_RR_OP(sub, x12, x10, x11, 0xf7ffbfff, -0x8000001, 0x4000, x1, 208, x2)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x1000
+TEST_RR_OP(sub, x12, x10, x11, 0x1ffff000, 0x20000000, 0x1000, x1, 212, x2)
+
+inst_69:
+// rs2_val == 1024, rs1_val == 1073741824
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0x400
+TEST_RR_OP(sub, x12, x10, x11, 0x3ffffc00, 0x40000000, 0x400, x1, 216, x2)
+
+inst_70:
+// rs2_val == 512, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0x200
+TEST_RR_OP(sub, x12, x10, x11, 0xffff7dff, -0x8001, 0x200, x1, 220, x2)
+
+inst_71:
+// rs2_val == 256, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x100
+TEST_RR_OP(sub, x12, x10, x11, 0x55555454, 0x55555554, 0x100, x1, 224, x2)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x80
+TEST_RR_OP(sub, x12, x10, x11, 0x333332b3, 0x33333333, 0x80, x1, 228, x2)
+
+inst_73:
+// rs2_val == 64, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x40
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffc4, 0x4, 0x40, x1, 232, x2)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x20
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffbdf, -0x401, 0x20, x1, 236, x2)
+
+inst_75:
+// rs2_val == 16, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffff2, 0x2, 0x10, x1, 240, x2)
+
+inst_76:
+// rs2_val == 4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xffbffffb, -0x400001, 0x4, x1, 244, x2)
+
+inst_77:
+// rs2_val == 2, rs1_val==2 and rs2_val==2
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x2, 0x2, x1, 248, x2)
+
+inst_78:
+// rs2_val == 1, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x1
+TEST_RR_OP(sub, x12, x10, x11, 0x1fffffff, 0x20000000, 0x1, x1, 252, x2)
+
+inst_79:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:0x400
+TEST_RR_OP(sub, x12, x10, x11, 0x7ffffc00, -0x80000000, 0x400, x1, 256, x2)
+
+inst_80:
+// rs1_val == 268435456, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffe, 0x10000000, 0x2, x1, 260, x2)
+
+inst_81:
+// rs1_val == 67108864, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x4000000
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x4000000, 0x4000000, x1, 264, x2)
+
+inst_82:
+// rs1_val == 16777216, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:-0x40001
+TEST_RR_OP(sub, x12, x10, x11, 0x1040001, 0x1000000, -0x40001, x1, 268, x2)
+
+inst_83:
+// rs1_val == 8388608, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:-0x8000001
+TEST_RR_OP(sub, x12, x10, x11, 0x8800001, 0x800000, -0x8000001, x1, 272, x2)
+
+inst_84:
+// rs1_val == 4194304, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x99d9999a, 0x400000, 0x66666666, x1, 276, x2)
+
+inst_85:
+// rs1_val == 1048576, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:-0x80000000
+TEST_RR_OP(sub, x12, x10, x11, 0x80100000, 0x100000, -0x80000000, x1, 280, x2)
+
+inst_86:
+// rs1_val == 131072, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:-0x2000001
+TEST_RR_OP(sub, x12, x10, x11, 0x2020001, 0x20000, -0x2000001, x1, 284, x2)
+
+inst_87:
+// rs1_val == 32768, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x8000, 0x8000, 0x0, x1, 288, x2)
+
+inst_88:
+// rs1_val == 16384, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x3ffb, 0x4000, 0x5, x1, 292, x2)
+
+inst_89:
+// rs1_val == 8192, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff6afb, 0x2000, 0xb505, x1, 296, x2)
+
+inst_90:
+// rs1_val == 4096, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x80
+TEST_RR_OP(sub, x12, x10, x11, 0xf80, 0x1000, 0x80, x1, 300, x2)
+
+inst_91:
+// rs1_val == 2048, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:-0x80000000
+TEST_RR_OP(sub, x12, x10, x11, 0x80000800, 0x800, -0x80000000, x1, 304, x2)
+
+inst_92:
+// rs1_val == 1024, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:0x800000
+TEST_RR_OP(sub, x12, x10, x11, 0xff800400, 0x400, 0x800000, x1, 308, x2)
+
+inst_93:
+// rs1_val == 512, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x204, 0x200, -0x4, x1, 312, x2)
+
+inst_94:
+// rs1_val == 256, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x20000000
+TEST_RR_OP(sub, x12, x10, x11, 0xe0000100, 0x100, 0x20000000, x1, 316, x2)
+
+inst_95:
+// rs1_val == 8, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x4000
+TEST_RR_OP(sub, x12, x10, x11, 0xffffc008, 0x8, 0x4000, x1, 320, x2)
+
+inst_96:
+// rs1_val == 1, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x20001
+TEST_RR_OP(sub, x12, x10, x11, 0x20002, 0x1, -0x20001, x1, 324, x2)
+
+inst_97:
+// rs1_val==46341 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0xb505, 0xb505, x1, 328, x2)
+
+inst_98:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x16a08, 0xb505, -0xb503, x1, 332, x2)
+
+inst_99:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9e, 0xb505, 0x66666667, x1, 336, x2)
+
+inst_100:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d1, 0xb505, 0x33333334, x1, 340, x2)
+
+inst_101:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xb4ff, 0xb505, 0x6, x1, 344, x2)
+
+inst_102:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a5a, 0xb505, -0x55555555, x1, 348, x2)
+
+inst_103:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5faf, 0xb505, 0x55555556, x1, 352, x2)
+
+inst_104:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xb501, 0xb505, 0x4, x1, 356, x2)
+
+inst_105:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0xb505, 0xb503, x1, 360, x2)
+
+inst_106:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xb505, 0xb505, 0x0, x1, 364, x2)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4ea0, 0xb505, 0x66666665, x1, 368, x2)
+
+inst_108:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d3, 0xb505, 0x33333332, x1, 372, x2)
+
+inst_109:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fb1, 0xb505, 0x55555554, x1, 376, x2)
+
+inst_110:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xb503, 0xb505, 0x2, x1, 380, x2)
+
+inst_111:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0xb505, 0xb504, x1, 384, x2)
+
+inst_112:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x16a09, 0xb505, -0xb504, x1, 388, x2)
+
+inst_113:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9f, 0xb505, 0x66666666, x1, 392, x2)
+
+inst_114:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d2, 0xb505, 0x33333333, x1, 396, x2)
+
+inst_115:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xb500, 0xb505, 0x5, x1, 400, x2)
+
+inst_116:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a5b, 0xb505, -0x55555556, x1, 404, x2)
+
+inst_117:
+// rs1_val==46341 and rs2_val==1431655765, rs2_val == 1431655765
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fb0, 0xb505, 0x55555555, x1, 408, x2)
+
+inst_118:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xb502, 0xb505, 0x3, x1, 412, x2)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95f8, -0xb503, 0xb505, x1, 416, x2)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x0, -0xb503, -0xb503, x1, 420, x2)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e496, -0xb503, 0x66666667, x1, 424, x2)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17c9, -0xb503, 0x33333334, x1, 428, x2)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af7, -0xb503, 0x6, x1, 432, x2)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a052, -0xb503, -0x55555555, x1, 436, x2)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a7, -0xb503, 0x55555556, x1, 440, x2)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af9, -0xb503, 0x4, x1, 444, x2)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95fa, -0xb503, 0xb503, x1, 448, x2)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 452, x2)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e498, -0xb503, 0x66666665, x1, 456, x2)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17cb, -0xb503, 0x33333332, x1, 460, x2)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a9, -0xb503, 0x55555554, x1, 464, x2)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afb, -0xb503, 0x2, x1, 468, x2)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95f9, -0xb503, 0xb504, x1, 472, x2)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x1, -0xb503, -0xb504, x1, 476, x2)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e497, -0xb503, 0x66666666, x1, 480, x2)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17ca, -0xb503, 0x33333333, x1, 484, x2)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af8, -0xb503, 0x5, x1, 488, x2)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a053, -0xb503, -0x55555556, x1, 492, x2)
+
+inst_139:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a8, -0xb503, 0x55555555, x1, 496, x2)
+
+inst_140:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afa, -0xb503, 0x3, x1, 500, x2)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b162, 0x66666667, 0xb505, x1, 504, x2)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b6a, 0x66666667, -0xb503, x1, 508, x2)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x1, 512, x2)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x33333333, 0x66666667, 0x33333334, x1, 516, x2)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x66666661, 0x66666667, 0x6, x1, 520, x2)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbbc, 0x66666667, -0x55555555, x1, 524, x2)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x11111111, 0x66666667, 0x55555556, x1, 528, x2)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x66666663, 0x66666667, 0x4, x1, 532, x2)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b164, 0x66666667, 0xb503, x1, 536, x2)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 540, x2)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x66666667, 0x66666665, x1, 544, x2)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x33333335, 0x66666667, 0x33333332, x1, 548, x2)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x11111113, 0x66666667, 0x55555554, x1, 552, x2)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x66666665, 0x66666667, 0x2, x1, 556, x2)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b163, 0x66666667, 0xb504, x1, 560, x2)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b6b, 0x66666667, -0xb504, x1, 564, x2)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 568, x2)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x33333334, 0x66666667, 0x33333333, x1, 572, x2)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x66666662, 0x66666667, 0x5, x1, 576, x2)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbbd, 0x66666667, -0x55555556, x1, 580, x2)
+
+inst_161:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x11111112, 0x66666667, 0x55555555, x1, 584, x2)
+
+inst_162:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x66666664, 0x66666667, 0x3, x1, 588, x2)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2f, 0x33333334, 0xb505, x1, 592, x2)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e837, 0x33333334, -0xb503, x1, 596, x2)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccd, 0x33333334, 0x66666667, x1, 600, x2)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x1, 604, x2)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332e, 0x33333334, 0x6, x1, 608, x2)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x88888889, 0x33333334, -0x55555555, x1, 612, x2)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xddddddde, 0x33333334, 0x55555556, x1, 616, x2)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x33333330, 0x33333334, 0x4, x1, 620, x2)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e31, 0x33333334, 0xb503, x1, 624, x2)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 628, x2)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccf, 0x33333334, 0x66666665, x1, 632, x2)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x33333334, 0x33333332, x1, 636, x2)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddde0, 0x33333334, 0x55555554, x1, 640, x2)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x33333332, 0x33333334, 0x2, x1, 644, x2)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e30, 0x33333334, 0xb504, x1, 648, x2)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e838, 0x33333334, -0xb504, x1, 652, x2)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccce, 0x33333334, 0x66666666, x1, 656, x2)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x33333334, 0x33333333, x1, 660, x2)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332f, 0x33333334, 0x5, x1, 664, x2)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x8888888a, 0x33333334, -0x55555556, x1, 668, x2)
+
+inst_183:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddddf, 0x33333334, 0x55555555, x1, 672, x2)
+
+inst_184:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x33333331, 0x33333334, 0x3, x1, 676, x2)
+
+inst_185:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b01, 0x6, 0xb505, x1, 680, x2)
+
+inst_186:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb509, 0x6, -0xb503, x1, 684, x2)
+
+inst_187:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999f, 0x6, 0x66666667, x1, 688, x2)
+
+inst_188:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd2, 0x6, 0x33333334, x1, 692, x2)
+
+inst_189:
+// rs1_val==6 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x6, 0x6, x1, 696, x2)
+
+inst_190:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x5555555b, 0x6, -0x55555555, x1, 700, x2)
+
+inst_191:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab0, 0x6, 0x55555556, x1, 704, x2)
+
+inst_192:
+// rs1_val==6 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x6, 0x4, x1, 708, x2)
+
+inst_193:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b03, 0x6, 0xb503, x1, 712, x2)
+
+inst_194:
+// rs1_val==6 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x6, 0x6, 0x0, x1, 716, x2)
+
+inst_195:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x999999a1, 0x6, 0x66666665, x1, 720, x2)
+
+inst_196:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd4, 0x6, 0x33333332, x1, 724, x2)
+
+inst_197:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab2, 0x6, 0x55555554, x1, 728, x2)
+
+inst_198:
+// rs1_val==6 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x4, 0x6, 0x2, x1, 732, x2)
+
+inst_199:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b02, 0x6, 0xb504, x1, 736, x2)
+
+inst_200:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb50a, 0x6, -0xb504, x1, 740, x2)
+
+inst_201:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x999999a0, 0x6, 0x66666666, x1, 744, x2)
+
+inst_202:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd3, 0x6, 0x33333333, x1, 748, x2)
+
+inst_203:
+// rs1_val==6 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x6, 0x5, x1, 752, x2)
+
+inst_204:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x5555555c, 0x6, -0x55555556, x1, 756, x2)
+
+inst_205:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab1, 0x6, 0x55555555, x1, 760, x2)
+
+inst_206:
+// rs1_val==6 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x3, 0x6, 0x3, x1, 764, x2)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a6, -0x55555555, 0xb505, x1, 768, x2)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fae, -0x55555555, -0xb503, x1, 772, x2)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x44444444, -0x55555555, 0x66666667, x1, 776, x2)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x77777777, -0x55555555, 0x33333334, x1, 780, x2)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa5, -0x55555555, 0x6, x1, 784, x2)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x0, -0x55555555, -0x55555555, x1, 788, x2)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55555555, -0x55555555, 0x55555556, x1, 792, x2)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa7, -0x55555555, 0x4, x1, 796, x2)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a8, -0x55555555, 0xb503, x1, 800, x2)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 804, x2)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x44444446, -0x55555555, 0x66666665, x1, 808, x2)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x77777779, -0x55555555, 0x33333332, x1, 812, x2)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x55555557, -0x55555555, 0x55555554, x1, 816, x2)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa9, -0x55555555, 0x2, x1, 820, x2)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a7, -0x55555555, 0xb504, x1, 824, x2)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5faf, -0x55555555, -0xb504, x1, 828, x2)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x44444445, -0x55555555, 0x66666666, x1, 832, x2)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x77777778, -0x55555555, 0x33333333, x1, 836, x2)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa6, -0x55555555, 0x5, x1, 840, x2)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x1, -0x55555555, -0x55555556, x1, 844, x2)
+
+inst_227:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555556, -0x55555555, 0x55555555, x1, 848, x2)
+
+inst_228:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa8, -0x55555555, 0x3, x1, 852, x2)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a051, 0x55555556, 0xb505, x1, 856, x2)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a59, 0x55555556, -0xb503, x1, 860, x2)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeef, 0x55555556, 0x66666667, x1, 864, x2)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x22222222, 0x55555556, 0x33333334, x1, 868, x2)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x55555550, 0x55555556, 0x6, x1, 872, x2)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaab, 0x55555556, -0x55555555, x1, 876, x2)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x1, 880, x2)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x55555552, 0x55555556, 0x4, x1, 884, x2)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a053, 0x55555556, 0xb503, x1, 888, x2)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 892, x2)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeef1, 0x55555556, 0x66666665, x1, 896, x2)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x22222224, 0x55555556, 0x33333332, x1, 900, x2)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x55555556, 0x55555554, x1, 904, x2)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x55555554, 0x55555556, 0x2, x1, 908, x2)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a052, 0x55555556, 0xb504, x1, 912, x2)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a5a, 0x55555556, -0xb504, x1, 916, x2)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeef0, 0x55555556, 0x66666666, x1, 920, x2)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x22222223, 0x55555556, 0x33333333, x1, 924, x2)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x55555551, 0x55555556, 0x5, x1, 928, x2)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaac, 0x55555556, -0x55555556, x1, 932, x2)
+
+inst_249:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x55555556, 0x55555555, x1, 936, x2)
+
+inst_250:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x55555553, 0x55555556, 0x3, x1, 940, x2)
+
+inst_251:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4aff, 0x4, 0xb505, x1, 944, x2)
+
+inst_252:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb507, 0x4, -0xb503, x1, 948, x2)
+
+inst_253:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999d, 0x4, 0x66666667, x1, 952, x2)
+
+inst_254:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd0, 0x4, 0x33333334, x1, 956, x2)
+
+inst_255:
+// rs1_val==4 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x4, 0x6, x1, 960, x2)
+
+inst_256:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555559, 0x4, -0x55555555, x1, 964, x2)
+
+inst_257:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaae, 0x4, 0x55555556, x1, 968, x2)
+
+inst_258:
+// rs1_val==4 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x4, 0x4, x1, 972, x2)
+
+inst_259:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b01, 0x4, 0xb503, x1, 976, x2)
+
+inst_260:
+// rs1_val==4 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x4, 0x4, 0x0, x1, 980, x2)
+
+inst_261:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999f, 0x4, 0x66666665, x1, 984, x2)
+
+inst_262:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd2, 0x4, 0x33333332, x1, 988, x2)
+
+inst_263:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab0, 0x4, 0x55555554, x1, 992, x2)
+
+inst_264:
+// rs1_val==4 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x4, 0x2, x1, 996, x2)
+
+inst_265:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b00, 0x4, 0xb504, x1, 1000, x2)
+
+inst_266:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb508, 0x4, -0xb504, x1, 1004, x2)
+
+inst_267:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999e, 0x4, 0x66666666, x1, 1008, x2)
+
+inst_268:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd1, 0x4, 0x33333333, x1, 1012, x2)
+
+inst_269:
+// rs1_val==4 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x4, 0x5, x1, 1016, x2)
+
+inst_270:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x5555555a, 0x4, -0x55555556, x1, 1020, x2)
+
+inst_271:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaf, 0x4, 0x55555555, x1, 1024, x2)
+
+inst_272:
+// rs1_val==4 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x4, 0x3, x1, 1028, x2)
+
+inst_273:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0xb503, 0xb505, x1, 1032, x2)
+
+inst_274:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x16a06, 0xb503, -0xb503, x1, 1036, x2)
+
+inst_275:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9c, 0xb503, 0x66666667, x1, 1040, x2)
+
+inst_276:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81cf, 0xb503, 0x33333334, x1, 1044, x2)
+
+inst_277:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xb4fd, 0xb503, 0x6, x1, 1048, x2)
+
+inst_278:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a58, 0xb503, -0x55555555, x1, 1052, x2)
+
+inst_279:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fad, 0xb503, 0x55555556, x1, 1056, x2)
+
+inst_280:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xb4ff, 0xb503, 0x4, x1, 1060, x2)
+
+inst_281:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0xb503, 0xb503, x1, 1064, x2)
+
+inst_282:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 1068, x2)
+
+inst_283:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9e, 0xb503, 0x66666665, x1, 1072, x2)
+
+inst_284:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d1, 0xb503, 0x33333332, x1, 1076, x2)
+
+inst_285:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5faf, 0xb503, 0x55555554, x1, 1080, x2)
+
+inst_286:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xb501, 0xb503, 0x2, x1, 1084, x2)
+
+inst_287:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0xb503, 0xb504, x1, 1088, x2)
+
+inst_288:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x16a07, 0xb503, -0xb504, x1, 1092, x2)
+
+inst_289:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9d, 0xb503, 0x66666666, x1, 1096, x2)
+
+inst_290:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d0, 0xb503, 0x33333333, x1, 1100, x2)
+
+inst_291:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xb4fe, 0xb503, 0x5, x1, 1104, x2)
+
+inst_292:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a59, 0xb503, -0x55555556, x1, 1108, x2)
+
+inst_293:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fae, 0xb503, 0x55555555, x1, 1112, x2)
+
+inst_294:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xb500, 0xb503, 0x3, x1, 1116, x2)
+
+inst_295:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afb, 0x0, 0xb505, x1, 1120, x2)
+
+inst_296:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb503, 0x0, -0xb503, x1, 1124, x2)
+
+inst_297:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x99999999, 0x0, 0x66666667, x1, 1128, x2)
+
+inst_298:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccc, 0x0, 0x33333334, x1, 1132, x2)
+
+inst_299:
+// rs1_val==0 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffa, 0x0, 0x6, x1, 1136, x2)
+
+inst_300:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555555, 0x0, -0x55555555, x1, 1140, x2)
+
+inst_301:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaa, 0x0, 0x55555556, x1, 1144, x2)
+
+inst_302:
+// rs1_val==0 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffc, 0x0, 0x4, x1, 1148, x2)
+
+inst_303:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afd, 0x0, 0xb503, x1, 1152, x2)
+
+inst_304:
+// rs1_val==0 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1156, x2)
+
+inst_305:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999b, 0x0, 0x66666665, x1, 1160, x2)
+
+inst_306:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccce, 0x0, 0x33333332, x1, 1164, x2)
+
+inst_307:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaac, 0x0, 0x55555554, x1, 1168, x2)
+
+inst_308:
+// rs1_val==0 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x0, 0x2, x1, 1172, x2)
+
+inst_309:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afc, 0x0, 0xb504, x1, 1176, x2)
+
+inst_310:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb504, 0x0, -0xb504, x1, 1180, x2)
+
+inst_311:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999a, 0x0, 0x66666666, x1, 1184, x2)
+
+inst_312:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccd, 0x0, 0x33333333, x1, 1188, x2)
+
+inst_313:
+// rs1_val==0 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffb, 0x0, 0x5, x1, 1192, x2)
+
+inst_314:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55555556, 0x0, -0x55555556, x1, 1196, x2)
+
+inst_315:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaab, 0x0, 0x55555555, x1, 1200, x2)
+
+inst_316:
+// rs1_val==0 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffd, 0x0, 0x3, x1, 1204, x2)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b160, 0x66666665, 0xb505, x1, 1208, x2)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b68, 0x66666665, -0xb503, x1, 1212, x2)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x66666665, 0x66666667, x1, 1216, x2)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x33333331, 0x66666665, 0x33333334, x1, 1220, x2)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x6666665f, 0x66666665, 0x6, x1, 1224, x2)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbba, 0x66666665, -0x55555555, x1, 1228, x2)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x1111110f, 0x66666665, 0x55555556, x1, 1232, x2)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x66666661, 0x66666665, 0x4, x1, 1236, x2)
+
+inst_325:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b162, 0x66666665, 0xb503, x1, 1240, x2)
+
+inst_326:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1244, x2)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1248, x2)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccce, 0x33333333, 0x66666665, x1, 1252, x2)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 1256, x2)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddddf, 0x33333333, 0x55555554, x1, 1260, x2)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x33333331, 0x33333333, 0x2, x1, 1264, x2)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2f, 0x33333333, 0xb504, x1, 1268, x2)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e837, 0x33333333, -0xb504, x1, 1272, x2)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccd, 0x33333333, 0x66666666, x1, 1276, x2)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x1, 1280, x2)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332e, 0x33333333, 0x5, x1, 1284, x2)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x88888889, 0x33333333, -0x55555556, x1, 1288, x2)
+
+inst_338:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xddddddde, 0x33333333, 0x55555555, x1, 1292, x2)
+
+inst_339:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x33333330, 0x33333333, 0x3, x1, 1296, x2)
+
+inst_340:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b00, 0x5, 0xb505, x1, 1300, x2)
+
+inst_341:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb508, 0x5, -0xb503, x1, 1304, x2)
+
+inst_342:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999e, 0x5, 0x66666667, x1, 1308, x2)
+
+inst_343:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd1, 0x5, 0x33333334, x1, 1312, x2)
+
+inst_344:
+// rs1_val==5 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x5, 0x6, x1, 1316, x2)
+
+inst_345:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x5555555a, 0x5, -0x55555555, x1, 1320, x2)
+
+inst_346:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaf, 0x5, 0x55555556, x1, 1324, x2)
+
+inst_347:
+// rs1_val==5 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x5, 0x4, x1, 1328, x2)
+
+inst_348:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b02, 0x5, 0xb503, x1, 1332, x2)
+
+inst_349:
+// rs1_val==5 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x5, 0x5, 0x0, x1, 1336, x2)
+
+inst_350:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x999999a0, 0x5, 0x66666665, x1, 1340, x2)
+
+inst_351:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd3, 0x5, 0x33333332, x1, 1344, x2)
+
+inst_352:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab1, 0x5, 0x55555554, x1, 1348, x2)
+
+inst_353:
+// rs1_val==5 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x3, 0x5, 0x2, x1, 1352, x2)
+
+inst_354:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b01, 0x5, 0xb504, x1, 1356, x2)
+
+inst_355:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb509, 0x5, -0xb504, x1, 1360, x2)
+
+inst_356:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999f, 0x5, 0x66666666, x1, 1364, x2)
+
+inst_357:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd2, 0x5, 0x33333333, x1, 1368, x2)
+
+inst_358:
+// rs1_val==5 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x5, 0x5, x1, 1372, x2)
+
+inst_359:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x5555555b, 0x5, -0x55555556, x1, 1376, x2)
+
+inst_360:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaab0, 0x5, 0x55555555, x1, 1380, x2)
+
+inst_361:
+// rs1_val==5 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x5, 0x3, x1, 1384, x2)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a5, -0x55555556, 0xb505, x1, 1388, x2)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fad, -0x55555556, -0xb503, x1, 1392, x2)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x44444443, -0x55555556, 0x66666667, x1, 1396, x2)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x77777776, -0x55555556, 0x33333334, x1, 1400, x2)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa4, -0x55555556, 0x6, x1, 1404, x2)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, -0x55555556, -0x55555555, x1, 1408, x2)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55555554, -0x55555556, 0x55555556, x1, 1412, x2)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa6, -0x55555556, 0x4, x1, 1416, x2)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a7, -0x55555556, 0xb503, x1, 1420, x2)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1424, x2)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x44444445, -0x55555556, 0x66666665, x1, 1428, x2)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x77777778, -0x55555556, 0x33333332, x1, 1432, x2)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x55555556, -0x55555556, 0x55555554, x1, 1436, x2)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa8, -0x55555556, 0x2, x1, 1440, x2)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a6, -0x55555556, 0xb504, x1, 1444, x2)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fae, -0x55555556, -0xb504, x1, 1448, x2)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x44444444, -0x55555556, 0x66666666, x1, 1452, x2)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x77777777, -0x55555556, 0x33333333, x1, 1456, x2)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa5, -0x55555556, 0x5, x1, 1460, x2)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x0, -0x55555556, -0x55555556, x1, 1464, x2)
+
+inst_382:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555555, -0x55555556, 0x55555555, x1, 1468, x2)
+
+inst_383:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa7, -0x55555556, 0x3, x1, 1472, x2)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==46341, rs1_val == 1431655765
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a050, 0x55555555, 0xb505, x1, 1476, x2)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a58, 0x55555555, -0xb503, x1, 1480, x2)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeee, 0x55555555, 0x66666667, x1, 1484, x2)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x22222221, 0x55555555, 0x33333334, x1, 1488, x2)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x5555554f, 0x55555555, 0x6, x1, 1492, x2)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaa, 0x55555555, -0x55555555, x1, 1496, x2)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x55555555, 0x55555556, x1, 1500, x2)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x55555551, 0x55555555, 0x4, x1, 1504, x2)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a052, 0x55555555, 0xb503, x1, 1508, x2)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1512, x2)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeef0, 0x55555555, 0x66666665, x1, 1516, x2)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x22222223, 0x55555555, 0x33333332, x1, 1520, x2)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 1524, x2)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x55555553, 0x55555555, 0x2, x1, 1528, x2)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a051, 0x55555555, 0xb504, x1, 1532, x2)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a59, 0x55555555, -0xb504, x1, 1536, x2)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeef, 0x55555555, 0x66666666, x1, 1540, x2)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x22222222, 0x55555555, 0x33333333, x1, 1544, x2)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x55555550, 0x55555555, 0x5, x1, 1548, x2)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaab, 0x55555555, -0x55555556, x1, 1552, x2)
+
+inst_404:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x1, 1556, x2)
+
+inst_405:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x55555552, 0x55555555, 0x3, x1, 1560, x2)
+
+inst_406:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afe, 0x3, 0xb505, x1, 1564, x2)
+
+inst_407:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb506, 0x3, -0xb503, x1, 1568, x2)
+
+inst_408:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999c, 0x3, 0x66666667, x1, 1572, x2)
+
+inst_409:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccf, 0x3, 0x33333334, x1, 1576, x2)
+
+inst_410:
+// rs1_val==3 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffd, 0x3, 0x6, x1, 1580, x2)
+
+inst_411:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555558, 0x3, -0x55555555, x1, 1584, x2)
+
+inst_412:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaad, 0x3, 0x55555556, x1, 1588, x2)
+
+inst_413:
+// rs1_val==3 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x3, 0x4, x1, 1592, x2)
+
+inst_414:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4b00, 0x3, 0xb503, x1, 1596, x2)
+
+inst_415:
+// rs1_val==3 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x3, 0x3, 0x0, x1, 1600, x2)
+
+inst_416:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999e, 0x3, 0x66666665, x1, 1604, x2)
+
+inst_417:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd1, 0x3, 0x33333332, x1, 1608, x2)
+
+inst_418:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaf, 0x3, 0x55555554, x1, 1612, x2)
+
+inst_419:
+// rs1_val==3 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x3, 0x2, x1, 1616, x2)
+
+inst_420:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4aff, 0x3, 0xb504, x1, 1620, x2)
+
+inst_421:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb507, 0x3, -0xb504, x1, 1624, x2)
+
+inst_422:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999d, 0x3, 0x66666666, x1, 1628, x2)
+
+inst_423:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd0, 0x3, 0x33333333, x1, 1632, x2)
+
+inst_424:
+// rs1_val==3 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x3, 0x5, x1, 1636, x2)
+
+inst_425:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55555559, 0x3, -0x55555556, x1, 1640, x2)
+
+inst_426:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaae, 0x3, 0x55555555, x1, 1644, x2)
+
+inst_427:
+// rs1_val==3 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x3, 0x3, x1, 1648, x2)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x1, 1652, x2)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x33333333, 0x66666665, 0x33333332, x1, 1656, x2)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x11111111, 0x66666665, 0x55555554, x1, 1660, x2)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x66666663, 0x66666665, 0x2, x1, 1664, x2)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b161, 0x66666665, 0xb504, x1, 1668, x2)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b69, 0x66666665, -0xb504, x1, 1672, x2)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x66666665, 0x66666666, x1, 1676, x2)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x33333332, 0x66666665, 0x33333333, x1, 1680, x2)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x66666660, 0x66666665, 0x5, x1, 1684, x2)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbbb, 0x66666665, -0x55555556, x1, 1688, x2)
+
+inst_438:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x11111110, 0x66666665, 0x55555555, x1, 1692, x2)
+
+inst_439:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x66666662, 0x66666665, 0x3, x1, 1696, x2)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2d, 0x33333332, 0xb505, x1, 1700, x2)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e835, 0x33333332, -0xb503, x1, 1704, x2)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccb, 0x33333332, 0x66666667, x1, 1708, x2)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x33333332, 0x33333334, x1, 1712, x2)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332c, 0x33333332, 0x6, x1, 1716, x2)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x88888887, 0x33333332, -0x55555555, x1, 1720, x2)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddddc, 0x33333332, 0x55555556, x1, 1724, x2)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332e, 0x33333332, 0x4, x1, 1728, x2)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2f, 0x33333332, 0xb503, x1, 1732, x2)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1736, x2)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccd, 0x33333332, 0x66666665, x1, 1740, x2)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x1, 1744, x2)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xddddddde, 0x33333332, 0x55555554, x1, 1748, x2)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x33333330, 0x33333332, 0x2, x1, 1752, x2)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2e, 0x33333332, 0xb504, x1, 1756, x2)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e836, 0x33333332, -0xb504, x1, 1760, x2)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccc, 0x33333332, 0x66666666, x1, 1764, x2)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x33333332, 0x33333333, x1, 1768, x2)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332d, 0x33333332, 0x5, x1, 1772, x2)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x88888888, 0x33333332, -0x55555556, x1, 1776, x2)
+
+inst_460:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddddd, 0x33333332, 0x55555555, x1, 1780, x2)
+
+inst_461:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332f, 0x33333332, 0x3, x1, 1784, x2)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a04f, 0x55555554, 0xb505, x1, 1788, x2)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a57, 0x55555554, -0xb503, x1, 1792, x2)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeed, 0x55555554, 0x66666667, x1, 1796, x2)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x22222220, 0x55555554, 0x33333334, x1, 1800, x2)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x5555554e, 0x55555554, 0x6, x1, 1804, x2)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaa9, 0x55555554, -0x55555555, x1, 1808, x2)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x55555554, 0x55555556, x1, 1812, x2)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x55555550, 0x55555554, 0x4, x1, 1816, x2)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a051, 0x55555554, 0xb503, x1, 1820, x2)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1824, x2)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeef, 0x55555554, 0x66666665, x1, 1828, x2)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x22222222, 0x55555554, 0x33333332, x1, 1832, x2)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x1, 1836, x2)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x55555552, 0x55555554, 0x2, x1, 1840, x2)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a050, 0x55555554, 0xb504, x1, 1844, x2)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a58, 0x55555554, -0xb504, x1, 1848, x2)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0xeeeeeeee, 0x55555554, 0x66666666, x1, 1852, x2)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x22222221, 0x55555554, 0x33333333, x1, 1856, x2)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x5555554f, 0x55555554, 0x5, x1, 1860, x2)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaaa, 0x55555554, -0x55555556, x1, 1864, x2)
+
+inst_482:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x55555554, 0x55555555, x1, 1868, x2)
+
+inst_483:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x55555551, 0x55555554, 0x3, x1, 1872, x2)
+
+inst_484:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afd, 0x2, 0xb505, x1, 1876, x2)
+
+inst_485:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xb505, 0x2, -0xb503, x1, 1880, x2)
+
+inst_486:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999b, 0x2, 0x66666667, x1, 1884, x2)
+
+inst_487:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccce, 0x2, 0x33333334, x1, 1888, x2)
+
+inst_488:
+// rs1_val==2 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffc, 0x2, 0x6, x1, 1892, x2)
+
+inst_489:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55555557, 0x2, -0x55555555, x1, 1896, x2)
+
+inst_490:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaac, 0x2, 0x55555556, x1, 1900, x2)
+
+inst_491:
+// rs1_val==2 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffe, 0x2, 0x4, x1, 1904, x2)
+
+inst_492:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4aff, 0x2, 0xb503, x1, 1908, x2)
+
+inst_493:
+// rs1_val==2 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x2, 0x2, 0x0, x1, 1912, x2)
+
+inst_494:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999d, 0x2, 0x66666665, x1, 1916, x2)
+
+inst_495:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xccccccd0, 0x2, 0x33333332, x1, 1920, x2)
+
+inst_496:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaae, 0x2, 0x55555554, x1, 1924, x2)
+
+inst_497:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afe, 0x2, 0xb504, x1, 1928, x2)
+
+inst_498:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xb506, 0x2, -0xb504, x1, 1932, x2)
+
+inst_499:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9999999c, 0x2, 0x66666666, x1, 1936, x2)
+
+inst_500:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccf, 0x2, 0x33333333, x1, 1940, x2)
+
+inst_501:
+// rs1_val==2 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xfffffffd, 0x2, 0x5, x1, 1944, x2)
+
+inst_502:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55555558, 0x2, -0x55555556, x1, 1948, x2)
+
+inst_503:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaaaaaad, 0x2, 0x55555555, x1, 1952, x2)
+
+inst_504:
+// rs1_val==2 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x2, 0x3, x1, 1956, x2)
+
+inst_505:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0xb504, 0xb505, x1, 1960, x2)
+
+inst_506:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x16a07, 0xb504, -0xb503, x1, 1964, x2)
+
+inst_507:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9d, 0xb504, 0x66666667, x1, 1968, x2)
+
+inst_508:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d0, 0xb504, 0x33333334, x1, 1972, x2)
+
+inst_509:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xb4fe, 0xb504, 0x6, x1, 1976, x2)
+
+inst_510:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a59, 0xb504, -0x55555555, x1, 1980, x2)
+
+inst_511:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fae, 0xb504, 0x55555556, x1, 1984, x2)
+
+inst_512:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xb500, 0xb504, 0x4, x1, 1988, x2)
+
+inst_513:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0xb504, 0xb503, x1, 1992, x2)
+
+inst_514:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xb504, 0xb504, 0x0, x1, 1996, x2)
+
+inst_515:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9f, 0xb504, 0x66666665, x1, 2000, x2)
+
+inst_516:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d2, 0xb504, 0x33333332, x1, 2004, x2)
+
+inst_517:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5fb0, 0xb504, 0x55555554, x1, 2008, x2)
+
+inst_518:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xb502, 0xb504, 0x2, x1, 2012, x2)
+
+inst_519:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0xb504, 0xb504, x1, 2016, x2)
+
+inst_520:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x16a08, 0xb504, -0xb504, x1, 2020, x2)
+
+inst_521:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x999a4e9e, 0xb504, 0x66666666, x1, 2024, x2)
+
+inst_522:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccd81d1, 0xb504, 0x33333333, x1, 2028, x2)
+
+inst_523:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xb4ff, 0xb504, 0x5, x1, 2032, x2)
+
+inst_524:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x55560a5a, 0xb504, -0x55555556, x1, 2036, x2)
+
+inst_525:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaab5faf, 0xb504, 0x55555555, x1, 2040, x2)
+
+inst_526:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xb501, 0xb504, 0x3, x1, 2044, x2)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95f7, -0xb504, 0xb505, x1, 0, x2)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, -0xb504, -0xb503, x1, 4, x2)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e495, -0xb504, 0x66666667, x1, 8, x2)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17c8, -0xb504, 0x33333334, x1, 12, x2)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af6, -0xb504, 0x6, x1, 16, x2)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a051, -0xb504, -0x55555555, x1, 20, x2)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a6, -0xb504, 0x55555556, x1, 24, x2)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af8, -0xb504, 0x4, x1, 28, x2)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95f9, -0xb504, 0xb503, x1, 32, x2)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 36, x2)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e497, -0xb504, 0x66666665, x1, 40, x2)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17ca, -0xb504, 0x33333332, x1, 44, x2)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a8, -0xb504, 0x55555554, x1, 48, x2)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4afa, -0xb504, 0x2, x1, 52, x2)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0xfffe95f8, -0xb504, 0xb504, x1, 56, x2)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x0, -0xb504, -0xb504, x1, 60, x2)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x9998e496, -0xb504, 0x66666666, x1, 64, x2)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0xcccc17c9, -0xb504, 0x33333333, x1, 68, x2)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af7, -0xb504, 0x5, x1, 72, x2)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x5554a052, -0xb504, -0x55555556, x1, 76, x2)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xaaa9f5a7, -0xb504, 0x55555555, x1, 80, x2)
+
+inst_548:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0xffff4af9, -0xb504, 0x3, x1, 84, x2)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b161, 0x66666666, 0xb505, x1, 88, x2)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b69, 0x66666666, -0xb503, x1, 92, x2)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x66666666, 0x66666667, x1, 96, x2)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0x33333332, 0x66666666, 0x33333334, x1, 100, x2)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x66666660, 0x66666666, 0x6, x1, 104, x2)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbbb, 0x66666666, -0x55555555, x1, 108, x2)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0x11111110, 0x66666666, 0x55555556, x1, 112, x2)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x66666662, 0x66666666, 0x4, x1, 116, x2)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b163, 0x66666666, 0xb503, x1, 120, x2)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(sub, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 124, x2)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(sub, x12, x10, x11, 0x1, 0x66666666, 0x66666665, x1, 128, x2)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(sub, x12, x10, x11, 0x33333334, 0x66666666, 0x33333332, x1, 132, x2)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(sub, x12, x10, x11, 0x11111112, 0x66666666, 0x55555554, x1, 136, x2)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(sub, x12, x10, x11, 0x66666664, 0x66666666, 0x2, x1, 140, x2)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x6665b162, 0x66666666, 0xb504, x1, 144, x2)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(sub, x12, x10, x11, 0x66671b6a, 0x66666666, -0xb504, x1, 148, x2)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(sub, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x1, 152, x2)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(sub, x12, x10, x11, 0x33333333, 0x66666666, 0x33333333, x1, 156, x2)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(sub, x12, x10, x11, 0x66666661, 0x66666666, 0x5, x1, 160, x2)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xbbbbbbbc, 0x66666666, -0x55555556, x1, 164, x2)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x11111111, 0x66666666, 0x55555555, x1, 168, x2)
+
+inst_570:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(sub, x12, x10, x11, 0x66666663, 0x66666666, 0x3, x1, 172, x2)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e2e, 0x33333333, 0xb505, x1, 176, x2)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x3333e836, 0x33333333, -0xb503, x1, 180, x2)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(sub, x12, x10, x11, 0xcccccccc, 0x33333333, 0x66666667, x1, 184, x2)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(sub, x12, x10, x11, 0xffffffff, 0x33333333, 0x33333334, x1, 188, x2)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332d, 0x33333333, 0x6, x1, 192, x2)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(sub, x12, x10, x11, 0x88888888, 0x33333333, -0x55555555, x1, 196, x2)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(sub, x12, x10, x11, 0xdddddddd, 0x33333333, 0x55555556, x1, 200, x2)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(sub, x12, x10, x11, 0x3333332f, 0x33333333, 0x4, x1, 204, x2)
+
+inst_579:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(sub, x12, x10, x11, 0x33327e30, 0x33333333, 0xb503, x1, 208, x2)
+
+inst_580:
+// rs2_val == 2147483647, rs1_val == -4194305, rs1_val < 0 and rs2_val > 0, rs2_val == (2**(xlen-1)-1)
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:0x7fffffff
+TEST_RR_OP(sub, x12, x10, x11, 0x7fc00000, -0x400001, 0x7fffffff, x1, 212, x2)
+
+inst_581:
+// rs2_val == -536870913, rs1_val == -8388609
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:-0x20000001
+TEST_RR_OP(sub, x12, x10, x11, 0x1f800000, -0x800001, -0x20000001, x1, 216, x2)
+
+inst_582:
+// rs2_val == -268435457, rs1_val == -33554433
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:-0x10000001
+TEST_RR_OP(sub, x12, x10, x11, 0xe000000, -0x2000001, -0x10000001, x1, 220, x2)
+
+inst_583:
+// rs2_val == -524289, rs1_val == -2
+// opcode: sub ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0x80001
+TEST_RR_OP(sub, x12, x10, x11, 0x7ffff, -0x2, -0x80001, x1, 224, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 57*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S
new file mode 100644
index 000000000..71dd41b89
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S
@@ -0,0 +1,416 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sw instruction of the RISC-V E extension for the sw-align covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",sw-align)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 != rs2, rs1==x13, rs2==x1, ea_align == 0 and (imm_val % 4) == 0, imm_val > 0, rs2_val == 67108864
+// opcode: sw; op1:x13; op2:x1; op2val:0x4000000; immval:0x4; align:0
+TEST_STORE(x2,x9,0,x13,x1,0x4000000,0x4,0,sw,0)
+
+inst_1:
+// rs1==x7, rs2==x6, rs2_val == 2147483647, rs2_val == (2**(xlen-1)-1)
+// opcode: sw; op1:x7; op2:x6; op2val:0x7fffffff; immval:0x20; align:0
+TEST_STORE(x2,x9,0,x7,x6,0x7fffffff,0x20,4,sw,0)
+
+inst_2:
+// rs1==x5, rs2==x0, rs2_val == -1073741825, imm_val < 0
+// opcode: sw; op1:x5; op2:x0; op2val:0x0; immval:-0x4; align:0
+TEST_STORE(x2,x9,0,x5,x0,0x0,-0x4,8,sw,0)
+
+inst_3:
+// rs1==x4, rs2==x5, rs2_val == -536870913, ea_align == 0 and (imm_val % 4) == 3
+// opcode: sw; op1:x4; op2:x5; op2val:-0x20000001; immval:-0x11; align:0
+TEST_STORE(x2,x9,0,x4,x5,-0x20000001,-0x11,12,sw,0)
+
+inst_4:
+// rs1==x12, rs2==x3, rs2_val == -268435457, 
+// opcode: sw; op1:x12; op2:x3; op2val:-0x10000001; immval:-0x101; align:0
+TEST_STORE(x2,x9,0,x12,x3,-0x10000001,-0x101,16,sw,0)
+
+inst_5:
+// rs1==x8, rs2==x10, rs2_val == -134217729, 
+// opcode: sw; op1:x8; op2:x10; op2val:-0x8000001; immval:-0x1; align:0
+TEST_STORE(x2,x9,0,x8,x10,-0x8000001,-0x1,20,sw,0)
+
+inst_6:
+// rs1==x1, rs2==x8, rs2_val == -67108865, 
+// opcode: sw; op1:x1; op2:x8; op2val:-0x4000001; immval:-0x401; align:0
+TEST_STORE(x2,x9,0,x1,x8,-0x4000001,-0x401,24,sw,0)
+
+inst_7:
+// rs1==x6, rs2==x15, rs2_val == -33554433, 
+// opcode: sw; op1:x6; op2:x15; op2val:-0x2000001; immval:0x40; align:0
+TEST_STORE(x2,x9,0,x6,x15,-0x2000001,0x40,28,sw,0)
+
+inst_8:
+// rs1==x11, rs2==x14, rs2_val == -16777217, ea_align == 0 and (imm_val % 4) == 1
+// opcode: sw; op1:x11; op2:x14; op2val:-0x1000001; immval:0x555; align:0
+TEST_STORE(x2,x5,0,x11,x14,-0x1000001,0x555,32,sw,0)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_9:
+// rs1==x15, rs2==x7, rs2_val == -8388609, 
+// opcode: sw; op1:x15; op2:x7; op2val:-0x800001; immval:-0x201; align:0
+TEST_STORE(x1,x5,0,x15,x7,-0x800001,-0x201,0,sw,0)
+
+inst_10:
+// rs1==x3, rs2==x12, rs2_val == -4194305, 
+// opcode: sw; op1:x3; op2:x12; op2val:-0x400001; immval:-0x8; align:0
+TEST_STORE(x1,x5,0,x3,x12,-0x400001,-0x8,4,sw,0)
+
+inst_11:
+// rs1==x14, rs2==x9, rs2_val == -2097153, 
+// opcode: sw; op1:x14; op2:x9; op2val:-0x200001; immval:-0x800; align:0
+TEST_STORE(x1,x5,0,x14,x9,-0x200001,-0x800,8,sw,0)
+
+inst_12:
+// rs1==x9, rs2==x13, rs2_val == -1048577, 
+// opcode: sw; op1:x9; op2:x13; op2val:-0x100001; immval:0x9; align:0
+TEST_STORE(x1,x5,0,x9,x13,-0x100001,0x9,12,sw,0)
+
+inst_13:
+// rs1==x10, rs2==x4, rs2_val == -524289, 
+// opcode: sw; op1:x10; op2:x4; op2val:-0x80001; immval:0x7; align:0
+TEST_STORE(x1,x5,0,x10,x4,-0x80001,0x7,16,sw,0)
+
+inst_14:
+// rs1==x2, rs2==x11, rs2_val == -262145, ea_align == 0 and (imm_val % 4) == 2
+// opcode: sw; op1:x2; op2:x11; op2val:-0x40001; immval:0x6; align:0
+TEST_STORE(x1,x3,0,x2,x11,-0x40001,0x6,20,sw,0)
+
+inst_15:
+// rs2==x2, rs2_val == -131073, 
+// opcode: sw; op1:x9; op2:x2; op2val:-0x20001; immval:0x20; align:0
+TEST_STORE(x1,x3,0,x9,x2,-0x20001,0x20,24,sw,0)
+
+inst_16:
+// rs2_val == -65537, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x10001; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x10001,-0x81,28,sw,0)
+
+inst_17:
+// rs2_val == -32769, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x8001; immval:-0x11; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x8001,-0x11,32,sw,0)
+
+inst_18:
+// rs2_val == -16385, imm_val == 0
+// opcode: sw; op1:x10; op2:x11; op2val:-0x4001; immval:0x0; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x4001,0x0,36,sw,0)
+
+inst_19:
+// rs2_val == -8193, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x2001; immval:0x3ff; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x2001,0x3ff,40,sw,0)
+
+inst_20:
+// rs2_val == -4097, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x1001; immval:0x200; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x1001,0x200,44,sw,0)
+
+inst_21:
+// rs2_val == -2049, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x801; immval:0x4; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x801,0x4,48,sw,0)
+
+inst_22:
+// rs2_val == -1025, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x401; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x401,-0x401,52,sw,0)
+
+inst_23:
+// rs2_val == -513, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x201; immval:0x3ff; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x201,0x3ff,56,sw,0)
+
+inst_24:
+// rs2_val == -257, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x101; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x101,-0x81,60,sw,0)
+
+inst_25:
+// rs2_val == -129, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x81; immval:0x1; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x81,0x1,64,sw,0)
+
+inst_26:
+// rs2_val == -65, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x41; immval:-0xa; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x41,-0xa,68,sw,0)
+
+inst_27:
+// rs2_val == -33, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x21; immval:0x3; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x21,0x3,72,sw,0)
+
+inst_28:
+// rs2_val == -17, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x11; immval:0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x11,0x2,76,sw,0)
+
+inst_29:
+// rs2_val == -9, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x9; immval:-0xa; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x9,-0xa,80,sw,0)
+
+inst_30:
+// rs2_val == -5, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x5; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x5,0x40,84,sw,0)
+
+inst_31:
+// rs2_val == -3, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x3; immval:0x1; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x3,0x1,88,sw,0)
+
+inst_32:
+// rs2_val == -2, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x2; immval:-0x201; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x2,-0x201,92,sw,0)
+
+inst_33:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: sw; op1:x10; op2:x11; op2val:-0x80000000; immval:0x20; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x80000000,0x20,96,sw,0)
+
+inst_34:
+// rs2_val == 1073741824, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x40000000; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40000000,-0x401,100,sw,0)
+
+inst_35:
+// rs2_val == 536870912, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x20000000; immval:-0x8; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20000000,-0x8,104,sw,0)
+
+inst_36:
+// rs2_val == 1, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x1; immval:-0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x1,-0x2,108,sw,0)
+
+inst_37:
+// rs2_val == -1431655766, 
+// opcode: sw; op1:x10; op2:x11; op2val:-0x55555556; immval:-0x556; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x55555556,-0x556,112,sw,0)
+
+inst_38:
+// rs2_val == 1431655765, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x55555555; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x55555555,0x40,116,sw,0)
+
+inst_39:
+// rs2_val == 0, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x0; immval:-0xa; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x0,-0xa,120,sw,0)
+
+inst_40:
+// rs2_val == 268435456, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x10000000; immval:-0x4; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10000000,-0x4,124,sw,0)
+
+inst_41:
+// rs2_val == 134217728, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x8000000; immval:0x7ff; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8000000,0x7ff,128,sw,0)
+
+inst_42:
+// rs2_val == 33554432, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x2000000; immval:0x555; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2000000,0x555,132,sw,0)
+
+inst_43:
+// rs2_val == 16777216, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x1000000; immval:0x1; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x1000000,0x1,136,sw,0)
+
+inst_44:
+// rs2_val == 8388608, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x800000; immval:-0x5; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x800000,-0x5,140,sw,0)
+
+inst_45:
+// rs2_val == 4194304, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x400000; immval:0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x400000,0x2,144,sw,0)
+
+inst_46:
+// rs2_val == 2097152, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x200000; immval:-0x1; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x200000,-0x1,148,sw,0)
+
+inst_47:
+// rs2_val == 1048576, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x100000; immval:-0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x100000,-0x9,152,sw,0)
+
+inst_48:
+// rs2_val == 524288, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x80000; immval:0x400; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x80000,0x400,156,sw,0)
+
+inst_49:
+// rs2_val == 262144, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x40000; immval:0x555; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40000,0x555,160,sw,0)
+
+inst_50:
+// rs2_val == 131072, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x20000; immval:-0x8; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20000,-0x8,164,sw,0)
+
+inst_51:
+// rs2_val == 65536, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x10000; immval:-0x2; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10000,-0x2,168,sw,0)
+
+inst_52:
+// rs2_val == 32768, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x8000; immval:-0xa; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8000,-0xa,172,sw,0)
+
+inst_53:
+// rs2_val == 16384, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x4000; immval:-0x1; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x4000,-0x1,176,sw,0)
+
+inst_54:
+// rs2_val == 8192, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x2000; immval:-0x201; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2000,-0x201,180,sw,0)
+
+inst_55:
+// rs2_val == 4096, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x1000; immval:0x7; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x1000,0x7,184,sw,0)
+
+inst_56:
+// rs2_val == 2048, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x800; immval:-0x81; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x800,-0x81,188,sw,0)
+
+inst_57:
+// rs2_val == 1024, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x400; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x400,-0x401,192,sw,0)
+
+inst_58:
+// rs2_val == 512, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x200; immval:0x7; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x200,0x7,196,sw,0)
+
+inst_59:
+// rs2_val == 256, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x100; immval:-0x101; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x100,-0x101,200,sw,0)
+
+inst_60:
+// rs2_val == 128, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x80; immval:-0x21; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x80,-0x21,204,sw,0)
+
+inst_61:
+// rs2_val == 64, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x40; immval:0x40; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x40,0x40,208,sw,0)
+
+inst_62:
+// rs2_val == 32, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x20; immval:0x9; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x20,0x9,212,sw,0)
+
+inst_63:
+// rs2_val == 16, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x10; immval:0x10; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x10,0x10,216,sw,0)
+
+inst_64:
+// rs2_val == 8, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x8; immval:0x400; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x8,0x400,220,sw,0)
+
+inst_65:
+// rs2_val == 4, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x4; immval:-0x401; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x4,-0x401,224,sw,0)
+
+inst_66:
+// rs2_val == 2, 
+// opcode: sw; op1:x10; op2:x11; op2val:0x2; immval:-0x400; align:0
+TEST_STORE(x1,x3,0,x10,x11,0x2,-0x400,228,sw,0)
+
+inst_67:
+// rs2_val == -1073741825, imm_val < 0
+// opcode: sw; op1:x10; op2:x11; op2val:-0x40000001; immval:-0x4; align:0
+TEST_STORE(x1,x3,0,x10,x11,-0x40000001,-0x4,232,sw,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 9*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 59*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S
new file mode 100644
index 000000000..41fa0ac9d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S
@@ -0,0 +1,3001 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the xor instruction of the RISC-V E extension for the xor covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",xor)
+
+RVTEST_SIGBASE( x7,signature_x7_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x5, rs2==x14, rd==x1, rs1_val != rs2_val, rs2_val == -1048577, rs1_val > 0 and rs2_val < 0, rs1_val == 131072
+// opcode: xor ; op1:x5; op2:x14; dest:x1; op1val:0x20000;  op2val:-0x100001
+TEST_RR_OP(xor, x1, x5, x14, 0xffedffff, 0x20000, -0x100001, x7, 0, x10)
+
+inst_1:
+// rs1 == rd != rs2, rs1==x3, rs2==x15, rd==x3, rs2_val == 2147483647, rs1_val < 0 and rs2_val > 0, rs1_val == -1048577, rs2_val == (2**(xlen-1)-1)
+// opcode: xor ; op1:x3; op2:x15; dest:x3; op1val:-0x100001;  op2val:0x7fffffff
+TEST_RR_OP(xor, x3, x3, x15, 0x80100000, -0x100001, 0x7fffffff, x7, 4, x10)
+
+inst_2:
+// rs2 == rd != rs1, rs1==x4, rs2==x0, rd==x0, rs2_val == -1073741825, rs1_val == 1024
+// opcode: xor ; op1:x4; op2:x0; dest:x0; op1val:0x400;  op2val:0x0
+TEST_RR_OP(xor, x0, x4, x0, 0, 0x400, 0x0, x7, 8, x10)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x6, rs2_val == -536870913, rs1_val == 8192
+// opcode: xor ; op1:x8; op2:x8; dest:x6; op1val:0x2000;  op2val:0x2000
+TEST_RR_OP(xor, x6, x8, x8, 0x0, 0x2000, 0x2000, x7, 12, x10)
+
+inst_4:
+// rs1 == rs2 == rd, rs1==x12, rs2==x12, rd==x12, rs2_val == -268435457, rs1_val == 1
+// opcode: xor ; op1:x12; op2:x12; dest:x12; op1val:0x1;  op2val:0x1
+TEST_RR_OP(xor, x12, x12, x12, 0x0, 0x1, 0x1, x7, 16, x10)
+
+inst_5:
+// rs1==x1, rs2==x4, rd==x15, rs2_val == -134217729, 
+// opcode: xor ; op1:x1; op2:x4; dest:x15; op1val:0x66666667;  op2val:-0x8000001
+TEST_RR_OP(xor, x15, x1, x4, 0x91999998, 0x66666667, -0x8000001, x7, 20, x10)
+
+inst_6:
+// rs1==x9, rs2==x1, rd==x14, rs2_val == -67108865, rs1_val < 0 and rs2_val < 0, rs1_val == -65
+// opcode: xor ; op1:x9; op2:x1; dest:x14; op1val:-0x41;  op2val:-0x4000001
+TEST_RR_OP(xor, x14, x9, x1, 0x4000040, -0x41, -0x4000001, x7, 24, x10)
+
+inst_7:
+// rs1==x15, rs2==x13, rd==x2, rs2_val == -33554433, rs1_val == 32768
+// opcode: xor ; op1:x15; op2:x13; dest:x2; op1val:0x8000;  op2val:-0x2000001
+TEST_RR_OP(xor, x2, x15, x13, 0xfdff7fff, 0x8000, -0x2000001, x7, 28, x10)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_8:
+// rs1==x10, rs2==x9, rd==x11, rs2_val == -16777217, 
+// opcode: xor ; op1:x10; op2:x9; dest:x11; op1val:0xb503;  op2val:-0x1000001
+TEST_RR_OP(xor, x11, x10, x9, 0xfeff4afc, 0xb503, -0x1000001, x1, 0, x2)
+
+inst_9:
+// rs1==x7, rs2==x5, rd==x10, rs2_val == -8388609, rs1_val == -17
+// opcode: xor ; op1:x7; op2:x5; dest:x10; op1val:-0x11;  op2val:-0x800001
+TEST_RR_OP(xor, x10, x7, x5, 0x800010, -0x11, -0x800001, x1, 4, x2)
+
+inst_10:
+// rs1==x6, rs2==x7, rd==x8, rs2_val == -4194305, rs1_val == 262144
+// opcode: xor ; op1:x6; op2:x7; dest:x8; op1val:0x40000;  op2val:-0x400001
+TEST_RR_OP(xor, x8, x6, x7, 0xffbbffff, 0x40000, -0x400001, x1, 8, x2)
+
+inst_11:
+// rs1==x13, rs2==x11, rd==x4, rs2_val == -2097153, rs1_val == 2097152
+// opcode: xor ; op1:x13; op2:x11; dest:x4; op1val:0x200000;  op2val:-0x200001
+TEST_RR_OP(xor, x4, x13, x11, 0xffffffff, 0x200000, -0x200001, x1, 12, x2)
+
+inst_12:
+// rs1==x14, rs2==x6, rd==x9, rs2_val == -524289, rs1_val == 524288
+// opcode: xor ; op1:x14; op2:x6; dest:x9; op1val:0x80000;  op2val:-0x80001
+TEST_RR_OP(xor, x9, x14, x6, 0xffffffff, 0x80000, -0x80001, x1, 16, x2)
+
+inst_13:
+// rs1==x0, rs2==x3, rd==x7, rs2_val == -262145, rs1_val == -65537
+// opcode: xor ; op1:x0; op2:x3; dest:x7; op1val:0x0;  op2val:-0x40001
+TEST_RR_OP(xor, x7, x0, x3, 0xfffbffff, 0x0, -0x40001, x1, 20, x2)
+
+inst_14:
+// rs1==x11, rs2==x10, rd==x5, rs2_val == -131073, 
+// opcode: xor ; op1:x11; op2:x10; dest:x5; op1val:-0x8;  op2val:-0x20001
+TEST_RR_OP(xor, x5, x11, x10, 0x20007, -0x8, -0x20001, x1, 24, x3)
+
+inst_15:
+// rs1==x2, rs2_val == -65537, rs1_val == 2
+// opcode: xor ; op1:x2; op2:x9; dest:x14; op1val:0x2;  op2val:-0x10001
+TEST_RR_OP(xor, x14, x2, x9, 0xfffefffd, 0x2, -0x10001, x1, 28, x3)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_16:
+// rs2==x2, rs2_val == -32769, rs1_val == -262145
+// opcode: xor ; op1:x10; op2:x2; dest:x14; op1val:-0x40001;  op2val:-0x8001
+TEST_RR_OP(xor, x14, x10, x2, 0x48000, -0x40001, -0x8001, x1, 0, x3)
+
+inst_17:
+// rd==x13, rs2_val == -16385, 
+// opcode: xor ; op1:x7; op2:x11; dest:x13; op1val:0x2;  op2val:-0x4001
+TEST_RR_OP(xor, x13, x7, x11, 0xffffbffd, 0x2, -0x4001, x1, 4, x3)
+
+inst_18:
+// rs2_val == -8193, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x2001
+TEST_RR_OP(xor, x12, x10, x11, 0xffffdffa, 0x5, -0x2001, x1, 8, x3)
+
+inst_19:
+// rs2_val == -4097, rs1_val == -67108865
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x4000001;  op2val:-0x1001
+TEST_RR_OP(xor, x12, x10, x11, 0x4001000, -0x4000001, -0x1001, x1, 12, x3)
+
+inst_20:
+// rs2_val == -2049, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x801
+TEST_RR_OP(xor, x12, x10, x11, 0xfffff7fd, 0x2, -0x801, x1, 16, x3)
+
+inst_21:
+// rs2_val == -1025, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x401
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffbfd, 0x2, -0x401, x1, 20, x3)
+
+inst_22:
+// rs2_val == -513, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x201
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffdfc, 0x3, -0x201, x1, 24, x3)
+
+inst_23:
+// rs2_val == -257, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:-0x101
+TEST_RR_OP(xor, x12, x10, x11, 0xffff7eff, 0x8000, -0x101, x1, 28, x3)
+
+inst_24:
+// rs2_val == -129, rs1_val == -1073741825
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x40000001;  op2val:-0x81
+TEST_RR_OP(xor, x12, x10, x11, 0x40000080, -0x40000001, -0x81, x1, 32, x3)
+
+inst_25:
+// rs2_val == -65, rs1_val == -134217729
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x8000001;  op2val:-0x41
+TEST_RR_OP(xor, x12, x10, x11, 0x8000040, -0x8000001, -0x41, x1, 36, x3)
+
+inst_26:
+// rs2_val == -33, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:-0x21
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffd8, 0x7, -0x21, x1, 40, x3)
+
+inst_27:
+// rs2_val == -17, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x11
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffec, 0x3, -0x11, x1, 44, x3)
+
+inst_28:
+// rs2_val == -9, rs1_val == 0
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x9
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff7, 0x0, -0x9, x1, 48, x3)
+
+inst_29:
+// rs2_val == -5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x6;  op2val:-0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x1, -0x6, -0x5, x1, 52, x3)
+
+inst_30:
+// rs2_val == -3, rs1_val == 1431655765
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa8, 0x55555555, -0x3, x1, 56, x3)
+
+inst_31:
+// rs2_val == -2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, 0x0, -0x2, x1, 60, x3)
+
+inst_32:
+// rs1_val == 2147483647, rs1_val > 0 and rs2_val > 0, rs1_val == (2**(xlen-1)-1), rs2_val == 1431655765
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffff;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x2aaaaaaa, 0x7fffffff, 0x55555555, x1, 64, x3)
+
+inst_33:
+// rs1_val == -536870913, rs2_val == 2097152
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x20000001;  op2val:0x200000
+TEST_RR_OP(xor, x12, x10, x11, 0xdfdfffff, -0x20000001, 0x200000, x1, 68, x3)
+
+inst_34:
+// rs1_val == -268435457, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x10000001;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x1000b503, -0x10000001, -0xb504, x1, 72, x3)
+
+inst_35:
+// rs1_val == -33554433, rs2_val == 2
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xfdfffffd, -0x2000001, 0x2, x1, 76, x3)
+
+inst_36:
+// rs1_val == -16777217, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x1000001;  op2val:-0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x1000005, -0x1000001, -0x6, x1, 80, x3)
+
+inst_37:
+// rs1_val == -8388609, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x800001;  op2val:-0x21
+TEST_RR_OP(xor, x12, x10, x11, 0x800020, -0x800001, -0x21, x1, 84, x3)
+
+inst_38:
+// rs1_val == -4194305, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x400001;  op2val:-0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x400002, -0x400001, -0x3, x1, 88, x3)
+
+inst_39:
+// rs1_val == -2097153, rs2_val == -1431655766
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55755555, -0x200001, -0x55555556, x1, 92, x3)
+
+inst_40:
+// rs1_val == -524289, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x80001;  op2val:-0x40000000
+TEST_RR_OP(xor, x12, x10, x11, 0x3ff7ffff, -0x80001, -0x40000000, x1, 96, x3)
+
+inst_41:
+// rs1_val == -131073, rs2_val == 1048576
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x20001;  op2val:0x100000
+TEST_RR_OP(xor, x12, x10, x11, 0xffedffff, -0x20001, 0x100000, x1, 100, x3)
+
+inst_42:
+// rs1_val == -32769, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x8001;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffffcafb, -0x8001, 0xb504, x1, 104, x3)
+
+inst_43:
+// rs1_val == -16385, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x4001;  op2val:-0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x4005, -0x4001, -0x6, x1, 108, x3)
+
+inst_44:
+// rs1_val == -8193, rs2_val == 1024
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x2001;  op2val:0x400
+TEST_RR_OP(xor, x12, x10, x11, 0xffffdbff, -0x2001, 0x400, x1, 112, x3)
+
+inst_45:
+// rs1_val == -4097, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x1001;  op2val:-0x1000001
+TEST_RR_OP(xor, x12, x10, x11, 0x1001000, -0x1001, -0x1000001, x1, 116, x3)
+
+inst_46:
+// rs1_val == -2049, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x801;  op2val:0x9
+TEST_RR_OP(xor, x12, x10, x11, 0xfffff7f6, -0x801, 0x9, x1, 120, x3)
+
+inst_47:
+// rs1_val == -1025, rs2_val == 16777216
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x401;  op2val:0x1000000
+TEST_RR_OP(xor, x12, x10, x11, 0xfefffbff, -0x401, 0x1000000, x1, 124, x3)
+
+inst_48:
+// rs1_val == -513, rs2_val == 67108864
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x4000000
+TEST_RR_OP(xor, x12, x10, x11, 0xfbfffdff, -0x201, 0x4000000, x1, 128, x3)
+
+inst_49:
+// rs1_val == -257, rs2_val == 268435456
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x101;  op2val:0x10000000
+TEST_RR_OP(xor, x12, x10, x11, 0xeffffeff, -0x101, 0x10000000, x1, 132, x3)
+
+inst_50:
+// rs1_val == -129, rs2_val == 131072
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x20000
+TEST_RR_OP(xor, x12, x10, x11, 0xfffdff7f, -0x81, 0x20000, x1, 136, x3)
+
+inst_51:
+// rs1_val == -33, rs2_val == 0
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffdf, -0x21, 0x0, x1, 140, x3)
+
+inst_52:
+// rs1_val == -9, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0xccccccc4, -0x9, 0x33333333, x1, 144, x3)
+
+inst_53:
+// rs1_val == -5, rs2_val == 536870912
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0x20000000
+TEST_RR_OP(xor, x12, x10, x11, 0xdffffffb, -0x5, 0x20000000, x1, 148, x3)
+
+inst_54:
+// rs1_val == -3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x3;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afe, -0x3, 0xb503, x1, 152, x3)
+
+inst_55:
+// rs1_val == -2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:-0x400001
+TEST_RR_OP(xor, x12, x10, x11, 0x400001, -0x2, -0x400001, x1, 156, x3)
+
+inst_56:
+// rs2_val == -2147483648, rs2_val == (-2**(xlen-1))
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x9;  op2val:-0x80000000
+TEST_RR_OP(xor, x12, x10, x11, 0x80000009, 0x9, -0x80000000, x1, 160, x3)
+
+inst_57:
+// rs2_val == 1073741824, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x40000000;  op2val:0x40000000
+TEST_RR_OP(xor, x12, x10, x11, 0x80000000, -0x40000000, 0x40000000, x1, 164, x3)
+
+inst_58:
+// rs2_val == 134217728, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0x8000000
+TEST_RR_OP(xor, x12, x10, x11, 0x8000007, 0x7, 0x8000000, x1, 168, x3)
+
+inst_59:
+// rs2_val == 33554432, rs1_val == 4
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2000000
+TEST_RR_OP(xor, x12, x10, x11, 0x2000004, 0x4, 0x2000000, x1, 172, x3)
+
+inst_60:
+// rs2_val == 8388608, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x800000
+TEST_RR_OP(xor, x12, x10, x11, 0x33b33333, 0x33333333, 0x800000, x1, 176, x3)
+
+inst_61:
+// rs2_val == 4194304, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x2000001;  op2val:0x400000
+TEST_RR_OP(xor, x12, x10, x11, 0xfdbfffff, -0x2000001, 0x400000, x1, 180, x3)
+
+inst_62:
+// rs2_val == 524288, rs1_val == 256
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x80000
+TEST_RR_OP(xor, x12, x10, x11, 0x80100, 0x100, 0x80000, x1, 184, x3)
+
+inst_63:
+// rs2_val == 262144, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x40000
+TEST_RR_OP(xor, x12, x10, x11, 0x33373333, 0x33333333, 0x40000, x1, 188, x3)
+
+inst_64:
+// rs2_val == 65536, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x1;  op2val:0x10000
+TEST_RR_OP(xor, x12, x10, x11, 0xfffeffff, -0x1, 0x10000, x1, 192, x3)
+
+inst_65:
+// rs2_val == 32768, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x8000
+TEST_RR_OP(xor, x12, x10, x11, 0xffffcafc, -0xb504, 0x8000, x1, 196, x3)
+
+inst_66:
+// rs2_val == 16384, rs1_val == 32
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x4000
+TEST_RR_OP(xor, x12, x10, x11, 0x4020, 0x20, 0x4000, x1, 200, x3)
+
+inst_67:
+// rs2_val == 8192, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:0x2000
+TEST_RR_OP(xor, x12, x10, x11, 0xffffdff6, -0xa, 0x2000, x1, 204, x3)
+
+inst_68:
+// rs2_val == 4096, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x1000
+TEST_RR_OP(xor, x12, x10, x11, 0x33332333, 0x33333333, 0x1000, x1, 208, x3)
+
+inst_69:
+// rs2_val == 2048, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x800
+TEST_RR_OP(xor, x12, x10, x11, 0x33333b34, 0x33333334, 0x800, x1, 212, x3)
+
+inst_70:
+// rs2_val == 512, rs1_val == 2048
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x200
+TEST_RR_OP(xor, x12, x10, x11, 0xa00, 0x800, 0x200, x1, 216, x3)
+
+inst_71:
+// rs2_val == 256, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x100
+TEST_RR_OP(xor, x12, x10, x11, 0x100, 0x0, 0x100, x1, 220, x3)
+
+inst_72:
+// rs2_val == 128, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x20000;  op2val:0x80
+TEST_RR_OP(xor, x12, x10, x11, 0x20080, 0x20000, 0x80, x1, 224, x3)
+
+inst_73:
+// rs2_val == 64, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x40
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaeb, -0x55555555, 0x40, x1, 228, x3)
+
+inst_74:
+// rs2_val == 32, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x20
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffcf, -0x11, 0x20, x1, 232, x3)
+
+inst_75:
+// rs2_val == 16, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0x10
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffdef, -0x201, 0x10, x1, 236, x3)
+
+inst_76:
+// rs2_val == 8, rs1_val == 16777216
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:0x8
+TEST_RR_OP(xor, x12, x10, x11, 0x1000008, 0x1000000, 0x8, x1, 240, x3)
+
+inst_77:
+// rs2_val == 4, rs1_val == 134217728
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x8000004, 0x8000000, 0x4, x1, 244, x3)
+
+inst_78:
+// rs2_val == 1, rs1_val == 4194304
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x1
+TEST_RR_OP(xor, x12, x10, x11, 0x400001, 0x400000, 0x1, x1, 248, x3)
+
+inst_79:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x7fff4afd, -0x80000000, -0xb503, x1, 252, x3)
+
+inst_80:
+// rs1_val == 1073741824, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:-0x10000001
+TEST_RR_OP(xor, x12, x10, x11, 0xafffffff, 0x40000000, -0x10000001, x1, 256, x3)
+
+inst_81:
+// rs1_val == 536870912, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:-0x21
+TEST_RR_OP(xor, x12, x10, x11, 0xdfffffdf, 0x20000000, -0x21, x1, 260, x3)
+
+inst_82:
+// rs1_val == 268435456, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x20000
+TEST_RR_OP(xor, x12, x10, x11, 0x10020000, 0x10000000, 0x20000, x1, 264, x3)
+
+inst_83:
+// rs1_val == 67108864, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x4000000, 0x4000000, 0x0, x1, 268, x3)
+
+inst_84:
+// rs1_val == 33554432, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:-0x801
+TEST_RR_OP(xor, x12, x10, x11, 0xfdfff7ff, 0x2000000, -0x801, x1, 272, x3)
+
+inst_85:
+// rs1_val == 8388608, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x80b503, 0x800000, 0xb503, x1, 276, x3)
+
+inst_86:
+// rs1_val == 1048576, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x100003, 0x100000, 0x3, x1, 280, x3)
+
+inst_87:
+// rs1_val == 65536, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66676667, 0x10000, 0x66666667, x1, 284, x3)
+
+inst_88:
+// rs1_val == 16384, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:-0x1001
+TEST_RR_OP(xor, x12, x10, x11, 0xffffafff, 0x4000, -0x1001, x1, 288, x3)
+
+inst_89:
+// rs1_val == 4096, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55554555, 0x1000, 0x55555555, x1, 292, x3)
+
+inst_90:
+// rs1_val == 512, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:0x8000000
+TEST_RR_OP(xor, x12, x10, x11, 0x8000200, 0x200, 0x8000000, x1, 296, x3)
+
+inst_91:
+// rs1_val == 128, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x86, 0x80, 0x6, x1, 300, x3)
+
+inst_92:
+// rs1_val == 64, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:-0x401
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffbbf, 0x40, -0x401, x1, 304, x3)
+
+inst_93:
+// rs1_val == 16, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:-0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffeb, 0x10, -0x5, x1, 308, x3)
+
+inst_94:
+// rs1_val == 8, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:-0x11
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffe7, 0x8, -0x11, x1, 312, x3)
+
+inst_95:
+// rs1_val==46341 and rs2_val==46341, rs1_val == rs2_val
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0xb505, 0xb505, x1, 316, x3)
+
+inst_96:
+// rs1_val==46341 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff8, 0xb505, -0xb503, x1, 320, x3)
+
+inst_97:
+// rs1_val==46341 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d362, 0xb505, 0x66666667, x1, 324, x3)
+
+inst_98:
+// rs1_val==46341 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33338631, 0xb505, 0x33333334, x1, 328, x3)
+
+inst_99:
+// rs1_val==46341 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xb503, 0xb505, 0x6, x1, 332, x3)
+
+inst_100:
+// rs1_val==46341 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fae, 0xb505, -0x55555555, x1, 336, x3)
+
+inst_101:
+// rs1_val==46341 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e053, 0xb505, 0x55555556, x1, 340, x3)
+
+inst_102:
+// rs1_val==46341 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0xb505, 0x4, x1, 344, x3)
+
+inst_103:
+// rs1_val==46341 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0xb505, 0xb503, x1, 348, x3)
+
+inst_104:
+// rs1_val==46341 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xb505, 0xb505, 0x0, x1, 352, x3)
+
+inst_105:
+// rs1_val==46341 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d360, 0xb505, 0x66666665, x1, 356, x3)
+
+inst_106:
+// rs1_val==46341 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0xb505, 0x33333332, x1, 360, x3)
+
+inst_107:
+// rs1_val==46341 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e051, 0xb505, 0x55555554, x1, 364, x3)
+
+inst_108:
+// rs1_val==46341 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0xb505, 0x2, x1, 368, x3)
+
+inst_109:
+// rs1_val==46341 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0xb505, 0xb504, x1, 372, x3)
+
+inst_110:
+// rs1_val==46341 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff9, 0xb505, -0xb504, x1, 376, x3)
+
+inst_111:
+// rs1_val==46341 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d363, 0xb505, 0x66666666, x1, 380, x3)
+
+inst_112:
+// rs1_val==46341 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33338636, 0xb505, 0x33333333, x1, 384, x3)
+
+inst_113:
+// rs1_val==46341 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0xb505, 0x5, x1, 388, x3)
+
+inst_114:
+// rs1_val==46341 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faf, 0xb505, -0x55555556, x1, 392, x3)
+
+inst_115:
+// rs1_val==46341 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e050, 0xb505, 0x55555555, x1, 396, x3)
+
+inst_116:
+// rs1_val==46341 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb505;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0xb505, 0x3, x1, 400, x3)
+
+inst_117:
+// rs1_val==-46339 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff8, -0xb503, 0xb505, x1, 404, x3)
+
+inst_118:
+// rs1_val==-46339 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x0, -0xb503, -0xb503, x1, 408, x3)
+
+inst_119:
+// rs1_val==-46339 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9a, -0xb503, 0x66666667, x1, 412, x3)
+
+inst_120:
+// rs1_val==-46339 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79c9, -0xb503, 0x33333334, x1, 416, x3)
+
+inst_121:
+// rs1_val==-46339 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afb, -0xb503, 0x6, x1, 420, x3)
+
+inst_122:
+// rs1_val==-46339 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, -0xb503, -0x55555555, x1, 424, x3)
+
+inst_123:
+// rs1_val==-46339 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fab, -0xb503, 0x55555556, x1, 428, x3)
+
+inst_124:
+// rs1_val==-46339 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af9, -0xb503, 0x4, x1, 432, x3)
+
+inst_125:
+// rs1_val==-46339 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, -0xb503, 0xb503, x1, 436, x3)
+
+inst_126:
+// rs1_val==-46339 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afd, -0xb503, 0x0, x1, 440, x3)
+
+inst_127:
+// rs1_val==-46339 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c98, -0xb503, 0x66666665, x1, 444, x3)
+
+inst_128:
+// rs1_val==-46339 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79cf, -0xb503, 0x33333332, x1, 448, x3)
+
+inst_129:
+// rs1_val==-46339 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, -0xb503, 0x55555554, x1, 452, x3)
+
+inst_130:
+// rs1_val==-46339 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4aff, -0xb503, 0x2, x1, 456, x3)
+
+inst_131:
+// rs1_val==-46339 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff9, -0xb503, 0xb504, x1, 460, x3)
+
+inst_132:
+// rs1_val==-46339 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x1, -0xb503, -0xb504, x1, 464, x3)
+
+inst_133:
+// rs1_val==-46339 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9b, -0xb503, 0x66666666, x1, 468, x3)
+
+inst_134:
+// rs1_val==-46339 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79ce, -0xb503, 0x33333333, x1, 472, x3)
+
+inst_135:
+// rs1_val==-46339 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af8, -0xb503, 0x5, x1, 476, x3)
+
+inst_136:
+// rs1_val==-46339 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, -0xb503, -0x55555556, x1, 480, x3)
+
+inst_137:
+// rs1_val==-46339 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, -0xb503, 0x55555555, x1, 484, x3)
+
+inst_138:
+// rs1_val==-46339 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb503;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afe, -0xb503, 0x3, x1, 488, x3)
+
+inst_139:
+// rs1_val==1717986919 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d362, 0x66666667, 0xb505, x1, 492, x3)
+
+inst_140:
+// rs1_val==1717986919 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9a, 0x66666667, -0xb503, x1, 496, x3)
+
+inst_141:
+// rs1_val==1717986919 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x66666667, 0x66666667, x1, 500, x3)
+
+inst_142:
+// rs1_val==1717986919 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x66666667, 0x33333334, x1, 504, x3)
+
+inst_143:
+// rs1_val==1717986919 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x66666667, 0x6, x1, 508, x3)
+
+inst_144:
+// rs1_val==1717986919 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccc, 0x66666667, -0x55555555, x1, 512, x3)
+
+inst_145:
+// rs1_val==1717986919 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x66666667, 0x55555556, x1, 516, x3)
+
+inst_146:
+// rs1_val==1717986919 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x66666667, 0x4, x1, 520, x3)
+
+inst_147:
+// rs1_val==1717986919 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d364, 0x66666667, 0xb503, x1, 524, x3)
+
+inst_148:
+// rs1_val==1717986919 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x66666667, 0x0, x1, 528, x3)
+
+inst_149:
+// rs1_val==1717986919 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x66666667, 0x66666665, x1, 532, x3)
+
+inst_150:
+// rs1_val==1717986919 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x66666667, 0x33333332, x1, 536, x3)
+
+inst_151:
+// rs1_val==1717986919 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x66666667, 0x55555554, x1, 540, x3)
+
+inst_152:
+// rs1_val==1717986919 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x66666667, 0x2, x1, 544, x3)
+
+inst_153:
+// rs1_val==1717986919 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d363, 0x66666667, 0xb504, x1, 548, x3)
+
+inst_154:
+// rs1_val==1717986919 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9b, 0x66666667, -0xb504, x1, 552, x3)
+
+inst_155:
+// rs1_val==1717986919 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x66666667, 0x66666666, x1, 556, x3)
+
+inst_156:
+// rs1_val==1717986919 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x66666667, 0x33333333, x1, 560, x3)
+
+inst_157:
+// rs1_val==1717986919 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x66666667, 0x5, x1, 564, x3)
+
+inst_158:
+// rs1_val==1717986919 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccd, 0x66666667, -0x55555556, x1, 568, x3)
+
+inst_159:
+// rs1_val==1717986919 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x66666667, 0x55555555, x1, 572, x3)
+
+inst_160:
+// rs1_val==1717986919 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666667;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x66666667, 0x3, x1, 576, x3)
+
+inst_161:
+// rs1_val==858993460 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x33338631, 0x33333334, 0xb505, x1, 580, x3)
+
+inst_162:
+// rs1_val==858993460 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79c9, 0x33333334, -0xb503, x1, 584, x3)
+
+inst_163:
+// rs1_val==858993460 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x33333334, 0x66666667, x1, 588, x3)
+
+inst_164:
+// rs1_val==858993460 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x33333334, 0x33333334, x1, 592, x3)
+
+inst_165:
+// rs1_val==858993460 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x33333334, 0x6, x1, 596, x3)
+
+inst_166:
+// rs1_val==858993460 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x9999999f, 0x33333334, -0x55555555, x1, 600, x3)
+
+inst_167:
+// rs1_val==858993460 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x33333334, 0x55555556, x1, 604, x3)
+
+inst_168:
+// rs1_val==858993460 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x33333334, 0x4, x1, 608, x3)
+
+inst_169:
+// rs1_val==858993460 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0x33333334, 0xb503, x1, 612, x3)
+
+inst_170:
+// rs1_val==858993460 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x33333334, 0x33333334, 0x0, x1, 616, x3)
+
+inst_171:
+// rs1_val==858993460 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x33333334, 0x66666665, x1, 620, x3)
+
+inst_172:
+// rs1_val==858993460 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x33333334, 0x33333332, x1, 624, x3)
+
+inst_173:
+// rs1_val==858993460 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x33333334, 0x55555554, x1, 628, x3)
+
+inst_174:
+// rs1_val==858993460 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x33333334, 0x2, x1, 632, x3)
+
+inst_175:
+// rs1_val==858993460 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x33338630, 0x33333334, 0xb504, x1, 636, x3)
+
+inst_176:
+// rs1_val==858993460 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79c8, 0x33333334, -0xb504, x1, 640, x3)
+
+inst_177:
+// rs1_val==858993460 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x33333334, 0x66666666, x1, 644, x3)
+
+inst_178:
+// rs1_val==858993460 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x33333334, 0x33333333, x1, 648, x3)
+
+inst_179:
+// rs1_val==858993460 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x33333334, 0x5, x1, 652, x3)
+
+inst_180:
+// rs1_val==858993460 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x9999999e, 0x33333334, -0x55555556, x1, 656, x3)
+
+inst_181:
+// rs1_val==858993460 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x33333334, 0x55555555, x1, 660, x3)
+
+inst_182:
+// rs1_val==858993460 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333334;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x33333334, 0x3, x1, 664, x3)
+
+inst_183:
+// rs1_val==6 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb503, 0x6, 0xb505, x1, 668, x3)
+
+inst_184:
+// rs1_val==6 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afb, 0x6, -0xb503, x1, 672, x3)
+
+inst_185:
+// rs1_val==6 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x6, 0x66666667, x1, 676, x3)
+
+inst_186:
+// rs1_val==6 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x6, 0x33333334, x1, 680, x3)
+
+inst_187:
+// rs1_val==6 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x6, 0x6, x1, 684, x3)
+
+inst_188:
+// rs1_val==6 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaad, 0x6, -0x55555555, x1, 688, x3)
+
+inst_189:
+// rs1_val==6 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x6, 0x55555556, x1, 692, x3)
+
+inst_190:
+// rs1_val==6 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x6, 0x4, x1, 696, x3)
+
+inst_191:
+// rs1_val==6 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb505, 0x6, 0xb503, x1, 700, x3)
+
+inst_192:
+// rs1_val==6 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x6, 0x0, x1, 704, x3)
+
+inst_193:
+// rs1_val==6 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x6, 0x66666665, x1, 708, x3)
+
+inst_194:
+// rs1_val==6 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333334, 0x6, 0x33333332, x1, 712, x3)
+
+inst_195:
+// rs1_val==6 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x6, 0x55555554, x1, 716, x3)
+
+inst_196:
+// rs1_val==6 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x4, 0x6, 0x2, x1, 720, x3)
+
+inst_197:
+// rs1_val==6 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb502, 0x6, 0xb504, x1, 724, x3)
+
+inst_198:
+// rs1_val==6 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afa, 0x6, -0xb504, x1, 728, x3)
+
+inst_199:
+// rs1_val==6 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x6, 0x66666666, x1, 732, x3)
+
+inst_200:
+// rs1_val==6 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333335, 0x6, 0x33333333, x1, 736, x3)
+
+inst_201:
+// rs1_val==6 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x6, 0x5, x1, 740, x3)
+
+inst_202:
+// rs1_val==6 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaac, 0x6, -0x55555556, x1, 744, x3)
+
+inst_203:
+// rs1_val==6 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x6, 0x55555555, x1, 748, x3)
+
+inst_204:
+// rs1_val==6 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x5, 0x6, 0x3, x1, 752, x3)
+
+inst_205:
+// rs1_val==-1431655765 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fae, -0x55555555, 0xb505, x1, 756, x3)
+
+inst_206:
+// rs1_val==-1431655765 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, -0x55555555, -0xb503, x1, 760, x3)
+
+inst_207:
+// rs1_val==-1431655765 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccc, -0x55555555, 0x66666667, x1, 764, x3)
+
+inst_208:
+// rs1_val==-1431655765 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x9999999f, -0x55555555, 0x33333334, x1, 768, x3)
+
+inst_209:
+// rs1_val==-1431655765 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaad, -0x55555555, 0x6, x1, 772, x3)
+
+inst_210:
+// rs1_val==-1431655765 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x0, -0x55555555, -0x55555555, x1, 776, x3)
+
+inst_211:
+// rs1_val==-1431655765 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffd, -0x55555555, 0x55555556, x1, 780, x3)
+
+inst_212:
+// rs1_val==-1431655765 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaf, -0x55555555, 0x4, x1, 784, x3)
+
+inst_213:
+// rs1_val==-1431655765 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, -0x55555555, 0xb503, x1, 788, x3)
+
+inst_214:
+// rs1_val==-1431655765 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaab, -0x55555555, 0x0, x1, 792, x3)
+
+inst_215:
+// rs1_val==-1431655765 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0xccccccce, -0x55555555, 0x66666665, x1, 796, x3)
+
+inst_216:
+// rs1_val==-1431655765 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x99999999, -0x55555555, 0x33333332, x1, 800, x3)
+
+inst_217:
+// rs1_val==-1431655765 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, -0x55555555, 0x55555554, x1, 804, x3)
+
+inst_218:
+// rs1_val==-1431655765 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa9, -0x55555555, 0x2, x1, 808, x3)
+
+inst_219:
+// rs1_val==-1431655765 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faf, -0x55555555, 0xb504, x1, 812, x3)
+
+inst_220:
+// rs1_val==-1431655765 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, -0x55555555, -0xb504, x1, 816, x3)
+
+inst_221:
+// rs1_val==-1431655765 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccd, -0x55555555, 0x66666666, x1, 820, x3)
+
+inst_222:
+// rs1_val==-1431655765 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x99999998, -0x55555555, 0x33333333, x1, 824, x3)
+
+inst_223:
+// rs1_val==-1431655765 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaae, -0x55555555, 0x5, x1, 828, x3)
+
+inst_224:
+// rs1_val==-1431655765 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x1, -0x55555555, -0x55555556, x1, 832, x3)
+
+inst_225:
+// rs1_val==-1431655765 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, -0x55555555, 0x55555555, x1, 836, x3)
+
+inst_226:
+// rs1_val==-1431655765 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555555;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa8, -0x55555555, 0x3, x1, 840, x3)
+
+inst_227:
+// rs1_val==1431655766 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e053, 0x55555556, 0xb505, x1, 844, x3)
+
+inst_228:
+// rs1_val==1431655766 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fab, 0x55555556, -0xb503, x1, 848, x3)
+
+inst_229:
+// rs1_val==1431655766 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x55555556, 0x66666667, x1, 852, x3)
+
+inst_230:
+// rs1_val==1431655766 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x55555556, 0x33333334, x1, 856, x3)
+
+inst_231:
+// rs1_val==1431655766 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x55555556, 0x6, x1, 860, x3)
+
+inst_232:
+// rs1_val==1431655766 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffd, 0x55555556, -0x55555555, x1, 864, x3)
+
+inst_233:
+// rs1_val==1431655766 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x55555556, 0x55555556, x1, 868, x3)
+
+inst_234:
+// rs1_val==1431655766 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x55555556, 0x4, x1, 872, x3)
+
+inst_235:
+// rs1_val==1431655766 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e055, 0x55555556, 0xb503, x1, 876, x3)
+
+inst_236:
+// rs1_val==1431655766 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x55555556, 0x0, x1, 880, x3)
+
+inst_237:
+// rs1_val==1431655766 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x55555556, 0x66666665, x1, 884, x3)
+
+inst_238:
+// rs1_val==1431655766 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x55555556, 0x33333332, x1, 888, x3)
+
+inst_239:
+// rs1_val==1431655766 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x55555556, 0x55555554, x1, 892, x3)
+
+inst_240:
+// rs1_val==1431655766 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x55555556, 0x2, x1, 896, x3)
+
+inst_241:
+// rs1_val==1431655766 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e052, 0x55555556, 0xb504, x1, 900, x3)
+
+inst_242:
+// rs1_val==1431655766 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faa, 0x55555556, -0xb504, x1, 904, x3)
+
+inst_243:
+// rs1_val==1431655766 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x55555556, 0x66666666, x1, 908, x3)
+
+inst_244:
+// rs1_val==1431655766 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x55555556, 0x33333333, x1, 912, x3)
+
+inst_245:
+// rs1_val==1431655766 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x55555556, 0x5, x1, 916, x3)
+
+inst_246:
+// rs1_val==1431655766 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffc, 0x55555556, -0x55555556, x1, 920, x3)
+
+inst_247:
+// rs1_val==1431655766 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x55555556, 0x55555555, x1, 924, x3)
+
+inst_248:
+// rs1_val==1431655766 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555556;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x55555556, 0x3, x1, 928, x3)
+
+inst_249:
+// rs1_val==4 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0x4, 0xb505, x1, 932, x3)
+
+inst_250:
+// rs1_val==4 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af9, 0x4, -0xb503, x1, 936, x3)
+
+inst_251:
+// rs1_val==4 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x4, 0x66666667, x1, 940, x3)
+
+inst_252:
+// rs1_val==4 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x4, 0x33333334, x1, 944, x3)
+
+inst_253:
+// rs1_val==4 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x4, 0x6, x1, 948, x3)
+
+inst_254:
+// rs1_val==4 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaf, 0x4, -0x55555555, x1, 952, x3)
+
+inst_255:
+// rs1_val==4 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x4, 0x55555556, x1, 956, x3)
+
+inst_256:
+// rs1_val==4 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x4, 0x4, x1, 960, x3)
+
+inst_257:
+// rs1_val==4 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0x4, 0xb503, x1, 964, x3)
+
+inst_258:
+// rs1_val==4 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x4, 0x4, 0x0, x1, 968, x3)
+
+inst_259:
+// rs1_val==4 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x4, 0x66666665, x1, 972, x3)
+
+inst_260:
+// rs1_val==4 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x4, 0x33333332, x1, 976, x3)
+
+inst_261:
+// rs1_val==4 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x4, 0x55555554, x1, 980, x3)
+
+inst_262:
+// rs1_val==4 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x4, 0x2, x1, 984, x3)
+
+inst_263:
+// rs1_val==4 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0x4, 0xb504, x1, 988, x3)
+
+inst_264:
+// rs1_val==4 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af8, 0x4, -0xb504, x1, 992, x3)
+
+inst_265:
+// rs1_val==4 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x4, 0x66666666, x1, 996, x3)
+
+inst_266:
+// rs1_val==4 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x4, 0x33333333, x1, 1000, x3)
+
+inst_267:
+// rs1_val==4 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x4, 0x5, x1, 1004, x3)
+
+inst_268:
+// rs1_val==4 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaae, 0x4, -0x55555556, x1, 1008, x3)
+
+inst_269:
+// rs1_val==4 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x4, 0x55555555, x1, 1012, x3)
+
+inst_270:
+// rs1_val==4 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x4, 0x3, x1, 1016, x3)
+
+inst_271:
+// rs1_val==46339 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0xb503, 0xb505, x1, 1020, x3)
+
+inst_272:
+// rs1_val==46339 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, 0xb503, -0xb503, x1, 1024, x3)
+
+inst_273:
+// rs1_val==46339 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d364, 0xb503, 0x66666667, x1, 1028, x3)
+
+inst_274:
+// rs1_val==46339 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0xb503, 0x33333334, x1, 1032, x3)
+
+inst_275:
+// rs1_val==46339 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xb505, 0xb503, 0x6, x1, 1036, x3)
+
+inst_276:
+// rs1_val==46339 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, 0xb503, -0x55555555, x1, 1040, x3)
+
+inst_277:
+// rs1_val==46339 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e055, 0xb503, 0x55555556, x1, 1044, x3)
+
+inst_278:
+// rs1_val==46339 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0xb503, 0x4, x1, 1048, x3)
+
+inst_279:
+// rs1_val==46339 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0xb503, 0xb503, x1, 1052, x3)
+
+inst_280:
+// rs1_val==46339 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xb503, 0xb503, 0x0, x1, 1056, x3)
+
+inst_281:
+// rs1_val==46339 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d366, 0xb503, 0x66666665, x1, 1060, x3)
+
+inst_282:
+// rs1_val==46339 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33338631, 0xb503, 0x33333332, x1, 1064, x3)
+
+inst_283:
+// rs1_val==46339 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, 0xb503, 0x55555554, x1, 1068, x3)
+
+inst_284:
+// rs1_val==46339 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0xb503, 0x2, x1, 1072, x3)
+
+inst_285:
+// rs1_val==46339 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0xb503, 0xb504, x1, 1076, x3)
+
+inst_286:
+// rs1_val==46339 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, 0xb503, -0xb504, x1, 1080, x3)
+
+inst_287:
+// rs1_val==46339 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d365, 0xb503, 0x66666666, x1, 1084, x3)
+
+inst_288:
+// rs1_val==46339 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33338630, 0xb503, 0x33333333, x1, 1088, x3)
+
+inst_289:
+// rs1_val==46339 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0xb503, 0x5, x1, 1092, x3)
+
+inst_290:
+// rs1_val==46339 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, 0xb503, -0x55555556, x1, 1096, x3)
+
+inst_291:
+// rs1_val==46339 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, 0xb503, 0x55555555, x1, 1100, x3)
+
+inst_292:
+// rs1_val==46339 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb503;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0xb503, 0x3, x1, 1104, x3)
+
+inst_293:
+// rs1_val==0 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb505, 0x0, 0xb505, x1, 1108, x3)
+
+inst_294:
+// rs1_val==0 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afd, 0x0, -0xb503, x1, 1112, x3)
+
+inst_295:
+// rs1_val==0 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x0, 0x66666667, x1, 1116, x3)
+
+inst_296:
+// rs1_val==0 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333334, 0x0, 0x33333334, x1, 1120, x3)
+
+inst_297:
+// rs1_val==0 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x0, 0x6, x1, 1124, x3)
+
+inst_298:
+// rs1_val==0 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaab, 0x0, -0x55555555, x1, 1128, x3)
+
+inst_299:
+// rs1_val==0 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x0, 0x55555556, x1, 1132, x3)
+
+inst_300:
+// rs1_val==0 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x4, 0x0, 0x4, x1, 1136, x3)
+
+inst_301:
+// rs1_val==0 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb503, 0x0, 0xb503, x1, 1140, x3)
+
+inst_302:
+// rs1_val==0 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x0, 0x0, x1, 1144, x3)
+
+inst_303:
+// rs1_val==0 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x0, 0x66666665, x1, 1148, x3)
+
+inst_304:
+// rs1_val==0 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x0, 0x33333332, x1, 1152, x3)
+
+inst_305:
+// rs1_val==0 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x0, 0x55555554, x1, 1156, x3)
+
+inst_306:
+// rs1_val==0 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x0, 0x2, x1, 1160, x3)
+
+inst_307:
+// rs1_val==0 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb504, 0x0, 0xb504, x1, 1164, x3)
+
+inst_308:
+// rs1_val==0 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afc, 0x0, -0xb504, x1, 1168, x3)
+
+inst_309:
+// rs1_val==0 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x0, 0x66666666, x1, 1172, x3)
+
+inst_310:
+// rs1_val==0 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x0, 0x33333333, x1, 1176, x3)
+
+inst_311:
+// rs1_val==0 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x5, 0x0, 0x5, x1, 1180, x3)
+
+inst_312:
+// rs1_val==0 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaa, 0x0, -0x55555556, x1, 1184, x3)
+
+inst_313:
+// rs1_val==0 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x0, 0x55555555, x1, 1188, x3)
+
+inst_314:
+// rs1_val==0 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x0, 0x3, x1, 1192, x3)
+
+inst_315:
+// rs1_val==1717986917 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d360, 0x66666665, 0xb505, x1, 1196, x3)
+
+inst_316:
+// rs1_val==1717986917 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c98, 0x66666665, -0xb503, x1, 1200, x3)
+
+inst_317:
+// rs1_val==1717986917 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x66666665, 0x66666667, x1, 1204, x3)
+
+inst_318:
+// rs1_val==1717986917 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x66666665, 0x33333334, x1, 1208, x3)
+
+inst_319:
+// rs1_val==1717986917 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x66666665, 0x6, x1, 1212, x3)
+
+inst_320:
+// rs1_val==1717986917 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xccccccce, 0x66666665, -0x55555555, x1, 1216, x3)
+
+inst_321:
+// rs1_val==1717986917 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x66666665, 0x55555556, x1, 1220, x3)
+
+inst_322:
+// rs1_val==1717986917 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x66666665, 0x4, x1, 1224, x3)
+
+inst_323:
+// rs1_val==1717986917 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d366, 0x66666665, 0xb503, x1, 1228, x3)
+
+inst_324:
+// rs1_val==1717986917 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x66666665, 0x0, x1, 1232, x3)
+
+inst_325:
+// rs1_val==858993459 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x33333333, 0x0, x1, 1236, x3)
+
+inst_326:
+// rs1_val==858993459 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x33333333, 0x66666665, x1, 1240, x3)
+
+inst_327:
+// rs1_val==858993459 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x33333333, 0x33333332, x1, 1244, x3)
+
+inst_328:
+// rs1_val==858993459 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x33333333, 0x55555554, x1, 1248, x3)
+
+inst_329:
+// rs1_val==858993459 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x33333333, 0x2, x1, 1252, x3)
+
+inst_330:
+// rs1_val==858993459 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0x33333333, 0xb504, x1, 1256, x3)
+
+inst_331:
+// rs1_val==858993459 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79cf, 0x33333333, -0xb504, x1, 1260, x3)
+
+inst_332:
+// rs1_val==858993459 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x33333333, 0x66666666, x1, 1264, x3)
+
+inst_333:
+// rs1_val==858993459 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x33333333, 0x33333333, x1, 1268, x3)
+
+inst_334:
+// rs1_val==858993459 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x33333333, 0x5, x1, 1272, x3)
+
+inst_335:
+// rs1_val==858993459 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x99999999, 0x33333333, -0x55555556, x1, 1276, x3)
+
+inst_336:
+// rs1_val==858993459 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x33333333, 0x55555555, x1, 1280, x3)
+
+inst_337:
+// rs1_val==858993459 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x33333333, 0x3, x1, 1284, x3)
+
+inst_338:
+// rs1_val==5 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0x5, 0xb505, x1, 1288, x3)
+
+inst_339:
+// rs1_val==5 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af8, 0x5, -0xb503, x1, 1292, x3)
+
+inst_340:
+// rs1_val==5 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x5, 0x66666667, x1, 1296, x3)
+
+inst_341:
+// rs1_val==5 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x5, 0x33333334, x1, 1300, x3)
+
+inst_342:
+// rs1_val==5 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x5, 0x6, x1, 1304, x3)
+
+inst_343:
+// rs1_val==5 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaae, 0x5, -0x55555555, x1, 1308, x3)
+
+inst_344:
+// rs1_val==5 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x5, 0x55555556, x1, 1312, x3)
+
+inst_345:
+// rs1_val==5 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x5, 0x4, x1, 1316, x3)
+
+inst_346:
+// rs1_val==5 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0x5, 0xb503, x1, 1320, x3)
+
+inst_347:
+// rs1_val==5 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x5, 0x5, 0x0, x1, 1324, x3)
+
+inst_348:
+// rs1_val==5 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x5, 0x66666665, x1, 1328, x3)
+
+inst_349:
+// rs1_val==5 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x5, 0x33333332, x1, 1332, x3)
+
+inst_350:
+// rs1_val==5 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x5, 0x55555554, x1, 1336, x3)
+
+inst_351:
+// rs1_val==5 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x5, 0x2, x1, 1340, x3)
+
+inst_352:
+// rs1_val==5 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0x5, 0xb504, x1, 1344, x3)
+
+inst_353:
+// rs1_val==5 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af9, 0x5, -0xb504, x1, 1348, x3)
+
+inst_354:
+// rs1_val==5 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x5, 0x66666666, x1, 1352, x3)
+
+inst_355:
+// rs1_val==5 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x5, 0x33333333, x1, 1356, x3)
+
+inst_356:
+// rs1_val==5 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x5, 0x5, x1, 1360, x3)
+
+inst_357:
+// rs1_val==5 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaf, 0x5, -0x55555556, x1, 1364, x3)
+
+inst_358:
+// rs1_val==5 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x5, 0x55555555, x1, 1368, x3)
+
+inst_359:
+// rs1_val==5 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x5, 0x3, x1, 1372, x3)
+
+inst_360:
+// rs1_val==-1431655766 and rs2_val==46341, rs1_val == -1431655766
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faf, -0x55555556, 0xb505, x1, 1376, x3)
+
+inst_361:
+// rs1_val==-1431655766 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, -0x55555556, -0xb503, x1, 1380, x3)
+
+inst_362:
+// rs1_val==-1431655766 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccd, -0x55555556, 0x66666667, x1, 1384, x3)
+
+inst_363:
+// rs1_val==-1431655766 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x9999999e, -0x55555556, 0x33333334, x1, 1388, x3)
+
+inst_364:
+// rs1_val==-1431655766 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaac, -0x55555556, 0x6, x1, 1392, x3)
+
+inst_365:
+// rs1_val==-1431655766 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x1, -0x55555556, -0x55555555, x1, 1396, x3)
+
+inst_366:
+// rs1_val==-1431655766 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffc, -0x55555556, 0x55555556, x1, 1400, x3)
+
+inst_367:
+// rs1_val==-1431655766 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaae, -0x55555556, 0x4, x1, 1404, x3)
+
+inst_368:
+// rs1_val==-1431655766 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, -0x55555556, 0xb503, x1, 1408, x3)
+
+inst_369:
+// rs1_val==-1431655766 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaa, -0x55555556, 0x0, x1, 1412, x3)
+
+inst_370:
+// rs1_val==-1431655766 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccf, -0x55555556, 0x66666665, x1, 1416, x3)
+
+inst_371:
+// rs1_val==-1431655766 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x99999998, -0x55555556, 0x33333332, x1, 1420, x3)
+
+inst_372:
+// rs1_val==-1431655766 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, -0x55555556, 0x55555554, x1, 1424, x3)
+
+inst_373:
+// rs1_val==-1431655766 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa8, -0x55555556, 0x2, x1, 1428, x3)
+
+inst_374:
+// rs1_val==-1431655766 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fae, -0x55555556, 0xb504, x1, 1432, x3)
+
+inst_375:
+// rs1_val==-1431655766 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, -0x55555556, -0xb504, x1, 1436, x3)
+
+inst_376:
+// rs1_val==-1431655766 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccc, -0x55555556, 0x66666666, x1, 1440, x3)
+
+inst_377:
+// rs1_val==-1431655766 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x99999999, -0x55555556, 0x33333333, x1, 1444, x3)
+
+inst_378:
+// rs1_val==-1431655766 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaaf, -0x55555556, 0x5, x1, 1448, x3)
+
+inst_379:
+// rs1_val==-1431655766 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x0, -0x55555556, -0x55555556, x1, 1452, x3)
+
+inst_380:
+// rs1_val==-1431655766 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, -0x55555556, 0x55555555, x1, 1456, x3)
+
+inst_381:
+// rs1_val==-1431655766 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x55555556;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa9, -0x55555556, 0x3, x1, 1460, x3)
+
+inst_382:
+// rs1_val==1431655765 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e050, 0x55555555, 0xb505, x1, 1464, x3)
+
+inst_383:
+// rs1_val==1431655765 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, 0x55555555, -0xb503, x1, 1468, x3)
+
+inst_384:
+// rs1_val==1431655765 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x55555555, 0x66666667, x1, 1472, x3)
+
+inst_385:
+// rs1_val==1431655765 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x66666661, 0x55555555, 0x33333334, x1, 1476, x3)
+
+inst_386:
+// rs1_val==1431655765 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x55555553, 0x55555555, 0x6, x1, 1480, x3)
+
+inst_387:
+// rs1_val==1431655765 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, 0x55555555, -0x55555555, x1, 1484, x3)
+
+inst_388:
+// rs1_val==1431655765 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x55555555, 0x55555556, x1, 1488, x3)
+
+inst_389:
+// rs1_val==1431655765 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x55555555, 0x4, x1, 1492, x3)
+
+inst_390:
+// rs1_val==1431655765 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, 0x55555555, 0xb503, x1, 1496, x3)
+
+inst_391:
+// rs1_val==1431655765 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x55555555, 0x0, x1, 1500, x3)
+
+inst_392:
+// rs1_val==1431655765 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x55555555, 0x66666665, x1, 1504, x3)
+
+inst_393:
+// rs1_val==1431655765 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x55555555, 0x33333332, x1, 1508, x3)
+
+inst_394:
+// rs1_val==1431655765 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x55555555, 0x55555554, x1, 1512, x3)
+
+inst_395:
+// rs1_val==1431655765 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x55555555, 0x2, x1, 1516, x3)
+
+inst_396:
+// rs1_val==1431655765 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e051, 0x55555555, 0xb504, x1, 1520, x3)
+
+inst_397:
+// rs1_val==1431655765 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, 0x55555555, -0xb504, x1, 1524, x3)
+
+inst_398:
+// rs1_val==1431655765 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x55555555, 0x66666666, x1, 1528, x3)
+
+inst_399:
+// rs1_val==1431655765 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x55555555, 0x33333333, x1, 1532, x3)
+
+inst_400:
+// rs1_val==1431655765 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x55555555, 0x5, x1, 1536, x3)
+
+inst_401:
+// rs1_val==1431655765 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, 0x55555555, -0x55555556, x1, 1540, x3)
+
+inst_402:
+// rs1_val==1431655765 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x55555555, 0x55555555, x1, 1544, x3)
+
+inst_403:
+// rs1_val==1431655765 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555555;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x55555555, 0x3, x1, 1548, x3)
+
+inst_404:
+// rs1_val==3 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0x3, 0xb505, x1, 1552, x3)
+
+inst_405:
+// rs1_val==3 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afe, 0x3, -0xb503, x1, 1556, x3)
+
+inst_406:
+// rs1_val==3 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x3, 0x66666667, x1, 1560, x3)
+
+inst_407:
+// rs1_val==3 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x3, 0x33333334, x1, 1564, x3)
+
+inst_408:
+// rs1_val==3 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x5, 0x3, 0x6, x1, 1568, x3)
+
+inst_409:
+// rs1_val==3 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa8, 0x3, -0x55555555, x1, 1572, x3)
+
+inst_410:
+// rs1_val==3 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x3, 0x55555556, x1, 1576, x3)
+
+inst_411:
+// rs1_val==3 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x3, 0x4, x1, 1580, x3)
+
+inst_412:
+// rs1_val==3 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0x3, 0xb503, x1, 1584, x3)
+
+inst_413:
+// rs1_val==3 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x3, 0x0, x1, 1588, x3)
+
+inst_414:
+// rs1_val==3 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x3, 0x66666665, x1, 1592, x3)
+
+inst_415:
+// rs1_val==3 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x3, 0x33333332, x1, 1596, x3)
+
+inst_416:
+// rs1_val==3 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x3, 0x55555554, x1, 1600, x3)
+
+inst_417:
+// rs1_val==3 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x3, 0x2, x1, 1604, x3)
+
+inst_418:
+// rs1_val==3 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0x3, 0xb504, x1, 1608, x3)
+
+inst_419:
+// rs1_val==3 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4aff, 0x3, -0xb504, x1, 1612, x3)
+
+inst_420:
+// rs1_val==3 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x3, 0x66666666, x1, 1616, x3)
+
+inst_421:
+// rs1_val==3 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x3, 0x33333333, x1, 1620, x3)
+
+inst_422:
+// rs1_val==3 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x3, 0x5, x1, 1624, x3)
+
+inst_423:
+// rs1_val==3 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa9, 0x3, -0x55555556, x1, 1628, x3)
+
+inst_424:
+// rs1_val==3 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x3, 0x55555555, x1, 1632, x3)
+
+inst_425:
+// rs1_val==3 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x3;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x3, 0x3, x1, 1636, x3)
+
+inst_426:
+// rs1_val==1717986917 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x66666665, 0x66666665, x1, 1640, x3)
+
+inst_427:
+// rs1_val==1717986917 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x66666665, 0x33333332, x1, 1644, x3)
+
+inst_428:
+// rs1_val==1717986917 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x66666665, 0x55555554, x1, 1648, x3)
+
+inst_429:
+// rs1_val==1717986917 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x66666665, 0x2, x1, 1652, x3)
+
+inst_430:
+// rs1_val==1717986917 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d361, 0x66666665, 0xb504, x1, 1656, x3)
+
+inst_431:
+// rs1_val==1717986917 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c99, 0x66666665, -0xb504, x1, 1660, x3)
+
+inst_432:
+// rs1_val==1717986917 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x66666665, 0x66666666, x1, 1664, x3)
+
+inst_433:
+// rs1_val==1717986917 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x66666665, 0x33333333, x1, 1668, x3)
+
+inst_434:
+// rs1_val==1717986917 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x66666665, 0x5, x1, 1672, x3)
+
+inst_435:
+// rs1_val==1717986917 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccf, 0x66666665, -0x55555556, x1, 1676, x3)
+
+inst_436:
+// rs1_val==1717986917 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x66666665, 0x55555555, x1, 1680, x3)
+
+inst_437:
+// rs1_val==1717986917 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666665;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x66666665, 0x3, x1, 1684, x3)
+
+inst_438:
+// rs1_val==858993458 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0x33333332, 0xb505, x1, 1688, x3)
+
+inst_439:
+// rs1_val==858993458 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79cf, 0x33333332, -0xb503, x1, 1692, x3)
+
+inst_440:
+// rs1_val==858993458 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x33333332, 0x66666667, x1, 1696, x3)
+
+inst_441:
+// rs1_val==858993458 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x33333332, 0x33333334, x1, 1700, x3)
+
+inst_442:
+// rs1_val==858993458 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x33333334, 0x33333332, 0x6, x1, 1704, x3)
+
+inst_443:
+// rs1_val==858993458 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x99999999, 0x33333332, -0x55555555, x1, 1708, x3)
+
+inst_444:
+// rs1_val==858993458 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x33333332, 0x55555556, x1, 1712, x3)
+
+inst_445:
+// rs1_val==858993458 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x33333332, 0x4, x1, 1716, x3)
+
+inst_446:
+// rs1_val==858993458 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x33338631, 0x33333332, 0xb503, x1, 1720, x3)
+
+inst_447:
+// rs1_val==858993458 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x33333332, 0x0, x1, 1724, x3)
+
+inst_448:
+// rs1_val==858993458 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x33333332, 0x66666665, x1, 1728, x3)
+
+inst_449:
+// rs1_val==858993458 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x33333332, 0x33333332, x1, 1732, x3)
+
+inst_450:
+// rs1_val==858993458 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x33333332, 0x55555554, x1, 1736, x3)
+
+inst_451:
+// rs1_val==858993458 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x33333332, 0x2, x1, 1740, x3)
+
+inst_452:
+// rs1_val==858993458 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x33338636, 0x33333332, 0xb504, x1, 1744, x3)
+
+inst_453:
+// rs1_val==858993458 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79ce, 0x33333332, -0xb504, x1, 1748, x3)
+
+inst_454:
+// rs1_val==858993458 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x33333332, 0x66666666, x1, 1752, x3)
+
+inst_455:
+// rs1_val==858993458 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x33333332, 0x33333333, x1, 1756, x3)
+
+inst_456:
+// rs1_val==858993458 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x33333332, 0x5, x1, 1760, x3)
+
+inst_457:
+// rs1_val==858993458 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x99999998, 0x33333332, -0x55555556, x1, 1764, x3)
+
+inst_458:
+// rs1_val==858993458 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x33333332, 0x55555555, x1, 1768, x3)
+
+inst_459:
+// rs1_val==858993458 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333332;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x33333332, 0x3, x1, 1772, x3)
+
+inst_460:
+// rs1_val==1431655764 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e051, 0x55555554, 0xb505, x1, 1776, x3)
+
+inst_461:
+// rs1_val==1431655764 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, 0x55555554, -0xb503, x1, 1780, x3)
+
+inst_462:
+// rs1_val==1431655764 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x55555554, 0x66666667, x1, 1784, x3)
+
+inst_463:
+// rs1_val==1431655764 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x55555554, 0x33333334, x1, 1788, x3)
+
+inst_464:
+// rs1_val==1431655764 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x55555554, 0x6, x1, 1792, x3)
+
+inst_465:
+// rs1_val==1431655764 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, 0x55555554, -0x55555555, x1, 1796, x3)
+
+inst_466:
+// rs1_val==1431655764 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x55555554, 0x55555556, x1, 1800, x3)
+
+inst_467:
+// rs1_val==1431655764 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x55555550, 0x55555554, 0x4, x1, 1804, x3)
+
+inst_468:
+// rs1_val==1431655764 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, 0x55555554, 0xb503, x1, 1808, x3)
+
+inst_469:
+// rs1_val==1431655764 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x55555554, 0x0, x1, 1812, x3)
+
+inst_470:
+// rs1_val==1431655764 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x55555554, 0x66666665, x1, 1816, x3)
+
+inst_471:
+// rs1_val==1431655764 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x55555554, 0x33333332, x1, 1820, x3)
+
+inst_472:
+// rs1_val==1431655764 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x55555554, 0x55555554, x1, 1824, x3)
+
+inst_473:
+// rs1_val==1431655764 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x55555554, 0x2, x1, 1828, x3)
+
+inst_474:
+// rs1_val==1431655764 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e050, 0x55555554, 0xb504, x1, 1832, x3)
+
+inst_475:
+// rs1_val==1431655764 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, 0x55555554, -0xb504, x1, 1836, x3)
+
+inst_476:
+// rs1_val==1431655764 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x55555554, 0x66666666, x1, 1840, x3)
+
+inst_477:
+// rs1_val==1431655764 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x55555554, 0x33333333, x1, 1844, x3)
+
+inst_478:
+// rs1_val==1431655764 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x55555551, 0x55555554, 0x5, x1, 1848, x3)
+
+inst_479:
+// rs1_val==1431655764 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffffe, 0x55555554, -0x55555556, x1, 1852, x3)
+
+inst_480:
+// rs1_val==1431655764 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x55555554, 0x55555555, x1, 1856, x3)
+
+inst_481:
+// rs1_val==1431655764 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x55555554;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x55555554, 0x3, x1, 1860, x3)
+
+inst_482:
+// rs1_val==2 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0x2, 0xb505, x1, 1864, x3)
+
+inst_483:
+// rs1_val==2 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4aff, 0x2, -0xb503, x1, 1868, x3)
+
+inst_484:
+// rs1_val==2 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x2, 0x66666667, x1, 1872, x3)
+
+inst_485:
+// rs1_val==2 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33333336, 0x2, 0x33333334, x1, 1876, x3)
+
+inst_486:
+// rs1_val==2 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x4, 0x2, 0x6, x1, 1880, x3)
+
+inst_487:
+// rs1_val==2 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa9, 0x2, -0x55555555, x1, 1884, x3)
+
+inst_488:
+// rs1_val==2 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x2, 0x55555556, x1, 1888, x3)
+
+inst_489:
+// rs1_val==2 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x6, 0x2, 0x4, x1, 1892, x3)
+
+inst_490:
+// rs1_val==2 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0x2, 0xb503, x1, 1896, x3)
+
+inst_491:
+// rs1_val==2 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x2, 0x2, 0x0, x1, 1900, x3)
+
+inst_492:
+// rs1_val==2 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x66666667, 0x2, 0x66666665, x1, 1904, x3)
+
+inst_493:
+// rs1_val==2 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x2, 0x33333332, x1, 1908, x3)
+
+inst_494:
+// rs1_val==2 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x55555556, 0x2, 0x55555554, x1, 1912, x3)
+
+inst_495:
+// rs1_val==2 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x2, 0x2, x1, 1916, x3)
+
+inst_496:
+// rs1_val==2 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0x2, 0xb504, x1, 1920, x3)
+
+inst_497:
+// rs1_val==2 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afe, 0x2, -0xb504, x1, 1924, x3)
+
+inst_498:
+// rs1_val==2 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x2, 0x66666666, x1, 1928, x3)
+
+inst_499:
+// rs1_val==2 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33333331, 0x2, 0x33333333, x1, 1932, x3)
+
+inst_500:
+// rs1_val==2 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x2, 0x5, x1, 1936, x3)
+
+inst_501:
+// rs1_val==2 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaaaaa8, 0x2, -0x55555556, x1, 1940, x3)
+
+inst_502:
+// rs1_val==2 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x55555557, 0x2, 0x55555555, x1, 1944, x3)
+
+inst_503:
+// rs1_val==2 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x2, 0x3, x1, 1948, x3)
+
+inst_504:
+// rs1_val==46340 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0xb504, 0xb505, x1, 1952, x3)
+
+inst_505:
+// rs1_val==46340 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff9, 0xb504, -0xb503, x1, 1956, x3)
+
+inst_506:
+// rs1_val==46340 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d363, 0xb504, 0x66666667, x1, 1960, x3)
+
+inst_507:
+// rs1_val==46340 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x33338630, 0xb504, 0x33333334, x1, 1964, x3)
+
+inst_508:
+// rs1_val==46340 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xb502, 0xb504, 0x6, x1, 1968, x3)
+
+inst_509:
+// rs1_val==46340 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faf, 0xb504, -0x55555555, x1, 1972, x3)
+
+inst_510:
+// rs1_val==46340 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e052, 0xb504, 0x55555556, x1, 1976, x3)
+
+inst_511:
+// rs1_val==46340 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xb500, 0xb504, 0x4, x1, 1980, x3)
+
+inst_512:
+// rs1_val==46340 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0xb504, 0xb503, x1, 1984, x3)
+
+inst_513:
+// rs1_val==46340 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xb504, 0xb504, 0x0, x1, 1988, x3)
+
+inst_514:
+// rs1_val==46340 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d361, 0xb504, 0x66666665, x1, 1992, x3)
+
+inst_515:
+// rs1_val==46340 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x33338636, 0xb504, 0x33333332, x1, 1996, x3)
+
+inst_516:
+// rs1_val==46340 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e050, 0xb504, 0x55555554, x1, 2000, x3)
+
+inst_517:
+// rs1_val==46340 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xb506, 0xb504, 0x2, x1, 2004, x3)
+
+inst_518:
+// rs1_val==46340 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0xb504, 0xb504, x1, 2008, x3)
+
+inst_519:
+// rs1_val==46340 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff8, 0xb504, -0xb504, x1, 2012, x3)
+
+inst_520:
+// rs1_val==46340 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d362, 0xb504, 0x66666666, x1, 2016, x3)
+
+inst_521:
+// rs1_val==46340 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x33338637, 0xb504, 0x33333333, x1, 2020, x3)
+
+inst_522:
+// rs1_val==46340 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xb501, 0xb504, 0x5, x1, 2024, x3)
+
+inst_523:
+// rs1_val==46340 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fae, 0xb504, -0x55555556, x1, 2028, x3)
+
+inst_524:
+// rs1_val==46340 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e051, 0xb504, 0x55555555, x1, 2032, x3)
+
+inst_525:
+// rs1_val==46340 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0xb504;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xb507, 0xb504, 0x3, x1, 2036, x3)
+
+inst_526:
+// rs1_val==-46340 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff9, -0xb504, 0xb505, x1, 2040, x3)
+
+inst_527:
+// rs1_val==-46340 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x1, -0xb504, -0xb503, x1, 2044, x3)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_528:
+// rs1_val==-46340 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9b, -0xb504, 0x66666667, x1, 0, x3)
+
+inst_529:
+// rs1_val==-46340 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79c8, -0xb504, 0x33333334, x1, 4, x3)
+
+inst_530:
+// rs1_val==-46340 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afa, -0xb504, 0x6, x1, 8, x3)
+
+inst_531:
+// rs1_val==-46340 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e057, -0xb504, -0x55555555, x1, 12, x3)
+
+inst_532:
+// rs1_val==-46340 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1faa, -0xb504, 0x55555556, x1, 16, x3)
+
+inst_533:
+// rs1_val==-46340 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af8, -0xb504, 0x4, x1, 20, x3)
+
+inst_534:
+// rs1_val==-46340 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xffffffff, -0xb504, 0xb503, x1, 24, x3)
+
+inst_535:
+// rs1_val==-46340 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afc, -0xb504, 0x0, x1, 28, x3)
+
+inst_536:
+// rs1_val==-46340 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c99, -0xb504, 0x66666665, x1, 32, x3)
+
+inst_537:
+// rs1_val==-46340 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79ce, -0xb504, 0x33333332, x1, 36, x3)
+
+inst_538:
+// rs1_val==-46340 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa8, -0xb504, 0x55555554, x1, 40, x3)
+
+inst_539:
+// rs1_val==-46340 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4afe, -0xb504, 0x2, x1, 44, x3)
+
+inst_540:
+// rs1_val==-46340 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0xfffffff8, -0xb504, 0xb504, x1, 48, x3)
+
+inst_541:
+// rs1_val==-46340 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x0, -0xb504, -0xb504, x1, 52, x3)
+
+inst_542:
+// rs1_val==-46340 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9a, -0xb504, 0x66666666, x1, 56, x3)
+
+inst_543:
+// rs1_val==-46340 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79cf, -0xb504, 0x33333333, x1, 60, x3)
+
+inst_544:
+// rs1_val==-46340 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4af9, -0xb504, 0x5, x1, 64, x3)
+
+inst_545:
+// rs1_val==-46340 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x5555e056, -0xb504, -0x55555556, x1, 68, x3)
+
+inst_546:
+// rs1_val==-46340 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xaaaa1fa9, -0xb504, 0x55555555, x1, 72, x3)
+
+inst_547:
+// rs1_val==-46340 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0xb504;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0xffff4aff, -0xb504, 0x3, x1, 76, x3)
+
+inst_548:
+// rs1_val==1717986918 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d363, 0x66666666, 0xb505, x1, 80, x3)
+
+inst_549:
+// rs1_val==1717986918 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9b, 0x66666666, -0xb503, x1, 84, x3)
+
+inst_550:
+// rs1_val==1717986918 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x1, 0x66666666, 0x66666667, x1, 88, x3)
+
+inst_551:
+// rs1_val==1717986918 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x55555552, 0x66666666, 0x33333334, x1, 92, x3)
+
+inst_552:
+// rs1_val==1717986918 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x66666660, 0x66666666, 0x6, x1, 96, x3)
+
+inst_553:
+// rs1_val==1717986918 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccd, 0x66666666, -0x55555555, x1, 100, x3)
+
+inst_554:
+// rs1_val==1717986918 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x33333330, 0x66666666, 0x55555556, x1, 104, x3)
+
+inst_555:
+// rs1_val==1717986918 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x66666662, 0x66666666, 0x4, x1, 108, x3)
+
+inst_556:
+// rs1_val==1717986918 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d365, 0x66666666, 0xb503, x1, 112, x3)
+
+inst_557:
+// rs1_val==1717986918 and rs2_val==0, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x0
+TEST_RR_OP(xor, x12, x10, x11, 0x66666666, 0x66666666, 0x0, x1, 116, x3)
+
+inst_558:
+// rs1_val==1717986918 and rs2_val==1717986917, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666665
+TEST_RR_OP(xor, x12, x10, x11, 0x3, 0x66666666, 0x66666665, x1, 120, x3)
+
+inst_559:
+// rs1_val==1717986918 and rs2_val==858993458, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333332
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x66666666, 0x33333332, x1, 124, x3)
+
+inst_560:
+// rs1_val==1717986918 and rs2_val==1431655764, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555554
+TEST_RR_OP(xor, x12, x10, x11, 0x33333332, 0x66666666, 0x55555554, x1, 128, x3)
+
+inst_561:
+// rs1_val==1717986918 and rs2_val==2, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x2
+TEST_RR_OP(xor, x12, x10, x11, 0x66666664, 0x66666666, 0x2, x1, 132, x3)
+
+inst_562:
+// rs1_val==1717986918 and rs2_val==46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x6666d362, 0x66666666, 0xb504, x1, 136, x3)
+
+inst_563:
+// rs1_val==1717986918 and rs2_val==-46340, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0xb504
+TEST_RR_OP(xor, x12, x10, x11, 0x99992c9a, 0x66666666, -0xb504, x1, 140, x3)
+
+inst_564:
+// rs1_val==1717986918 and rs2_val==1717986918, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x66666666
+TEST_RR_OP(xor, x12, x10, x11, 0x0, 0x66666666, 0x66666666, x1, 144, x3)
+
+inst_565:
+// rs1_val==1717986918 and rs2_val==858993459, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x33333333
+TEST_RR_OP(xor, x12, x10, x11, 0x55555555, 0x66666666, 0x33333333, x1, 148, x3)
+
+inst_566:
+// rs1_val==1717986918 and rs2_val==5, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x5
+TEST_RR_OP(xor, x12, x10, x11, 0x66666663, 0x66666666, 0x5, x1, 152, x3)
+
+inst_567:
+// rs1_val==1717986918 and rs2_val==-1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:-0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0xcccccccc, 0x66666666, -0x55555556, x1, 156, x3)
+
+inst_568:
+// rs1_val==1717986918 and rs2_val==1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x33333333, 0x66666666, 0x55555555, x1, 160, x3)
+
+inst_569:
+// rs1_val==1717986918 and rs2_val==3, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x66666666;  op2val:0x3
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x66666666, 0x3, x1, 164, x3)
+
+inst_570:
+// rs1_val==858993459 and rs2_val==46341, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb505
+TEST_RR_OP(xor, x12, x10, x11, 0x33338636, 0x33333333, 0xb505, x1, 168, x3)
+
+inst_571:
+// rs1_val==858993459 and rs2_val==-46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0xcccc79ce, 0x33333333, -0xb503, x1, 172, x3)
+
+inst_572:
+// rs1_val==858993459 and rs2_val==1717986919, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x66666667
+TEST_RR_OP(xor, x12, x10, x11, 0x55555554, 0x33333333, 0x66666667, x1, 176, x3)
+
+inst_573:
+// rs1_val==858993459 and rs2_val==858993460, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x33333334
+TEST_RR_OP(xor, x12, x10, x11, 0x7, 0x33333333, 0x33333334, x1, 180, x3)
+
+inst_574:
+// rs1_val==858993459 and rs2_val==6, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x6
+TEST_RR_OP(xor, x12, x10, x11, 0x33333335, 0x33333333, 0x6, x1, 184, x3)
+
+inst_575:
+// rs1_val==858993459 and rs2_val==-1431655765, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:-0x55555555
+TEST_RR_OP(xor, x12, x10, x11, 0x99999998, 0x33333333, -0x55555555, x1, 188, x3)
+
+inst_576:
+// rs1_val==858993459 and rs2_val==1431655766, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x55555556
+TEST_RR_OP(xor, x12, x10, x11, 0x66666665, 0x33333333, 0x55555556, x1, 192, x3)
+
+inst_577:
+// rs1_val==858993459 and rs2_val==4, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0x4
+TEST_RR_OP(xor, x12, x10, x11, 0x33333337, 0x33333333, 0x4, x1, 196, x3)
+
+inst_578:
+// rs1_val==858993459 and rs2_val==46339, 
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x33333333;  op2val:0xb503
+TEST_RR_OP(xor, x12, x10, x11, 0x33338630, 0x33333333, 0xb503, x1, 200, x3)
+
+inst_579:
+// rs2_val == -1073741825, rs1_val == 1024
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:-0x40000001
+TEST_RR_OP(xor, x12, x10, x11, 0xbffffbff, 0x400, -0x40000001, x1, 204, x3)
+
+inst_580:
+// rs2_val == -536870913, rs1_val == 8192
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x20000001
+TEST_RR_OP(xor, x12, x10, x11, 0xdfffdfff, 0x2000, -0x20000001, x1, 208, x3)
+
+inst_581:
+// rs2_val == -268435457, rs1_val == 1
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:-0x10000001
+TEST_RR_OP(xor, x12, x10, x11, 0xeffffffe, 0x1, -0x10000001, x1, 212, x3)
+
+inst_582:
+// rs2_val == -262145, rs1_val == -65537
+// opcode: xor ; op1:x10; op2:x11; dest:x12; op1val:-0x10001;  op2val:-0x40001
+TEST_RR_OP(xor, x12, x10, x11, 0x50000, -0x10001, -0x40001, x1, 216, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x7_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 55*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S
new file mode 100644
index 000000000..cc3f509f7
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S
@@ -0,0 +1,2881 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Mon Aug  2 08:58:53 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/bilalsakhawat/riscv-ctg/sample_cgfs/rv32e.cgf \
+//                  --base-isa rv32e \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the xori instruction of the RISC-V E extension for the xori covergroup.
+// 
+#define RVTEST_E
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32E")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",xori)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 != rd, rs1==x12, rd==x13, imm_val == (-2**(12-1)), rs1_val != imm_val, rs1_val < 0 and imm_val < 0, imm_val == -2048, rs1_val == -131073
+// opcode: xori ; op1:x12; dest:x13; op1val:-0x20001;  immval:-0x800
+TEST_IMM_OP( xori, x13, x12, 0x207ff, -0x20001, -0x800, x1, 0, x2)
+
+inst_1:
+// rs1 == rd, rs1==x10, rd==x10, rs1_val == 2147483647, rs1_val > 0 and imm_val < 0, rs1_val == (2**(xlen-1)-1), imm_val == -1366
+// opcode: xori ; op1:x10; dest:x10; op1val:0x7fffffff;  immval:-0x556
+TEST_IMM_OP( xori, x10, x10, 0x80000555, 0x7fffffff, -0x556, x1, 4, x2)
+
+inst_2:
+// rs1==x8, rd==x4, rs1_val == -1073741825, imm_val == -257
+// opcode: xori ; op1:x8; dest:x4; op1val:-0x40000001;  immval:-0x101
+TEST_IMM_OP( xori, x4, x8, 0x40000100, -0x40000001, -0x101, x1, 8, x2)
+
+inst_3:
+// rs1==x6, rd==x7, rs1_val == -536870913, rs1_val < 0 and imm_val > 0, imm_val == 2
+// opcode: xori ; op1:x6; dest:x7; op1val:-0x20000001;  immval:0x2
+TEST_IMM_OP( xori, x7, x6, 0xdffffffd, -0x20000001, 0x2, x1, 12, x2)
+
+inst_4:
+// rs1==x9, rd==x14, rs1_val == -268435457, 
+// opcode: xori ; op1:x9; dest:x14; op1val:-0x10000001;  immval:0x6
+TEST_IMM_OP( xori, x14, x9, 0xeffffff9, -0x10000001, 0x6, x1, 16, x2)
+
+inst_5:
+// rs1==x7, rd==x3, rs1_val == -134217729, 
+// opcode: xori ; op1:x7; dest:x3; op1val:-0x8000001;  immval:-0x2c
+TEST_IMM_OP( xori, x3, x7, 0x800002b, -0x8000001, -0x2c, x1, 20, x2)
+
+inst_6:
+// rs1==x11, rd==x15, rs1_val == -67108865, imm_val == 16
+// opcode: xori ; op1:x11; dest:x15; op1val:-0x4000001;  immval:0x10
+TEST_IMM_OP( xori, x15, x11, 0xfbffffef, -0x4000001, 0x10, x1, 24, x2)
+RVTEST_SIGBASE( x6,signature_x6_0)
+
+inst_7:
+// rs1==x13, rd==x1, rs1_val == -33554433, 
+// opcode: xori ; op1:x13; dest:x1; op1val:-0x2000001;  immval:0x333
+TEST_IMM_OP( xori, x1, x13, 0xfdfffccc, -0x2000001, 0x333, x6, 0, x7)
+
+inst_8:
+// rs1==x15, rd==x11, rs1_val == -16777217, 
+// opcode: xori ; op1:x15; dest:x11; op1val:-0x1000001;  immval:0x5
+TEST_IMM_OP( xori, x11, x15, 0xfefffffa, -0x1000001, 0x5, x6, 4, x7)
+
+inst_9:
+// rs1==x4, rd==x8, rs1_val == -8388609, imm_val == -65
+// opcode: xori ; op1:x4; dest:x8; op1val:-0x800001;  immval:-0x41
+TEST_IMM_OP( xori, x8, x4, 0x800040, -0x800001, -0x41, x6, 8, x7)
+
+inst_10:
+// rs1==x14, rd==x9, rs1_val == -4194305, 
+// opcode: xori ; op1:x14; dest:x9; op1val:-0x400001;  immval:0x7
+TEST_IMM_OP( xori, x9, x14, 0xffbffff8, -0x400001, 0x7, x6, 12, x7)
+
+inst_11:
+// rs1==x1, rd==x2, rs1_val == -2097153, 
+// opcode: xori ; op1:x1; dest:x2; op1val:-0x200001;  immval:-0xa
+TEST_IMM_OP( xori, x2, x1, 0x200009, -0x200001, -0xa, x6, 16, x7)
+
+inst_12:
+// rs1==x3, rd==x5, rs1_val == -1048577, 
+// opcode: xori ; op1:x3; dest:x5; op1val:-0x100001;  immval:0x665
+TEST_IMM_OP( xori, x5, x3, 0xffeff99a, -0x100001, 0x665, x6, 20, x7)
+
+inst_13:
+// rs1==x5, rd==x12, rs1_val == -524289, 
+// opcode: xori ; op1:x5; dest:x12; op1val:-0x80001;  immval:-0x4
+TEST_IMM_OP( xori, x12, x5, 0x80003, -0x80001, -0x4, x6, 24, x4)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_14:
+// rs1==x2, rd==x6, rs1_val == -262145, 
+// opcode: xori ; op1:x2; dest:x6; op1val:-0x40001;  immval:0x2e
+TEST_IMM_OP( xori, x6, x2, 0xfffbffd1, -0x40001, 0x2e, x3, 0, x4)
+
+inst_15:
+// rs1==x0, rs1_val == -65537, imm_val == 512
+// opcode: xori ; op1:x0; dest:x1; op1val:0x0;  immval:0x200
+TEST_IMM_OP( xori, x1, x0, 0x200, 0x0, 0x200, x3, 4, x4)
+
+inst_16:
+// rd==x0, rs1_val == -32769, imm_val == 0
+// opcode: xori ; op1:x12; dest:x0; op1val:-0x8001;  immval:0x0
+TEST_IMM_OP( xori, x0, x12, 0, -0x8001, 0x0, x3, 8, x4)
+
+inst_17:
+// rs1_val == -16385, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x4001;  immval:-0x1
+TEST_IMM_OP( xori, x11, x10, 0x4000, -0x4001, -0x1, x3, 12, x4)
+
+inst_18:
+// rs1_val == -8193, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x2001;  immval:-0x4
+TEST_IMM_OP( xori, x11, x10, 0x2003, -0x2001, -0x4, x3, 16, x4)
+
+inst_19:
+// rs1_val == -4097, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x1001;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xffffefd1, -0x1001, 0x2e, x3, 20, x4)
+
+inst_20:
+// rs1_val == -2049, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x801;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xfffff2ab, -0x801, 0x554, x3, 24, x4)
+
+inst_21:
+// rs1_val == -1025, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x401;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xfffffbf9, -0x401, 0x6, x3, 28, x4)
+
+inst_22:
+// rs1_val == -513, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x201;  immval:-0x6
+TEST_IMM_OP( xori, x11, x10, 0x205, -0x201, -0x6, x3, 32, x4)
+
+inst_23:
+// rs1_val == -257, rs1_val == imm_val
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x101;  immval:-0x101
+TEST_IMM_OP( xori, x11, x10, 0x0, -0x101, -0x101, x3, 36, x4)
+
+inst_24:
+// rs1_val == -129, imm_val == -1025
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x81;  immval:-0x401
+TEST_IMM_OP( xori, x11, x10, 0x480, -0x81, -0x401, x3, 40, x4)
+
+inst_25:
+// rs1_val == -65, imm_val == 1
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x41;  immval:0x1
+TEST_IMM_OP( xori, x11, x10, 0xffffffbe, -0x41, 0x1, x3, 44, x4)
+
+inst_26:
+// rs1_val == -33, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x21;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xffffffdc, -0x21, 0x3, x3, 48, x4)
+
+inst_27:
+// rs1_val == -17, imm_val == -3
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x11;  immval:-0x3
+TEST_IMM_OP( xori, x11, x10, 0x12, -0x11, -0x3, x3, 52, x4)
+
+inst_28:
+// rs1_val == -9, imm_val == 1365
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x9;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaa2, -0x9, 0x555, x3, 56, x4)
+
+inst_29:
+// rs1_val == -5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x5;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xfffffaaf, -0x5, 0x554, x3, 60, x4)
+
+inst_30:
+// rs1_val == -3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x3;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaab, -0x3, 0x556, x3, 64, x4)
+
+inst_31:
+// rs1_val == -2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x2;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd2, -0x2, 0x2c, x3, 68, x4)
+
+inst_32:
+// imm_val == 2047, imm_val == (2**(12-1)-1), rs1_val > 0 and imm_val > 0
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x7ff
+TEST_IMM_OP( xori, x11, x10, 0x66666199, 0x66666666, 0x7ff, x3, 72, x4)
+
+inst_33:
+// imm_val == -513, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x1001;  immval:-0x201
+TEST_IMM_OP( xori, x11, x10, 0x1200, -0x1001, -0x201, x3, 76, x4)
+
+inst_34:
+// imm_val == -129, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x20001;  immval:-0x81
+TEST_IMM_OP( xori, x11, x10, 0x20080, -0x20001, -0x81, x3, 80, x4)
+
+inst_35:
+// imm_val == -33, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x100001;  immval:-0x21
+TEST_IMM_OP( xori, x11, x10, 0x100020, -0x100001, -0x21, x3, 84, x4)
+
+inst_36:
+// imm_val == -17, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x2;  immval:-0x11
+TEST_IMM_OP( xori, x11, x10, 0x11, -0x2, -0x11, x3, 88, x4)
+
+inst_37:
+// imm_val == -9, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x100001;  immval:-0x9
+TEST_IMM_OP( xori, x11, x10, 0x100008, -0x100001, -0x9, x3, 92, x4)
+
+inst_38:
+// imm_val == -5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x2001;  immval:-0x5
+TEST_IMM_OP( xori, x11, x10, 0x2004, -0x2001, -0x5, x3, 96, x4)
+
+inst_39:
+// imm_val == -2, rs1_val == 262144
+// opcode: xori ; op1:x10; dest:x11; op1val:0x40000;  immval:-0x2
+TEST_IMM_OP( xori, x11, x10, 0xfffbfffe, 0x40000, -0x2, x3, 100, x4)
+
+inst_40:
+// rs1_val == -2147483648, rs1_val == (-2**(xlen-1))
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x80000000;  immval:-0x8
+TEST_IMM_OP( xori, x11, x10, 0x7ffffff8, -0x80000000, -0x8, x3, 104, x4)
+
+inst_41:
+// rs1_val == 1073741824, imm_val == 64
+// opcode: xori ; op1:x10; dest:x11; op1val:0x40000000;  immval:0x40
+TEST_IMM_OP( xori, x11, x10, 0x40000040, 0x40000000, 0x40, x3, 108, x4)
+
+inst_42:
+// rs1_val == 536870912, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x20000000;  immval:0x1
+TEST_IMM_OP( xori, x11, x10, 0x20000001, 0x20000000, 0x1, x3, 112, x4)
+
+inst_43:
+// rs1_val == 268435456, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x10000000;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x10000006, 0x10000000, 0x6, x3, 116, x4)
+
+inst_44:
+// rs1_val == 134217728, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x8000000;  immval:0x3ff
+TEST_IMM_OP( xori, x11, x10, 0x80003ff, 0x8000000, 0x3ff, x3, 120, x4)
+
+inst_45:
+// rs1_val == 67108864, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4000000;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x4000005, 0x4000000, 0x5, x3, 124, x4)
+
+inst_46:
+// rs1_val == 33554432, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2000000;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xfdffffd3, 0x2000000, -0x2d, x3, 128, x4)
+
+inst_47:
+// rs1_val == 16777216, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x1000000;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x1000003, 0x1000000, 0x3, x3, 132, x4)
+
+inst_48:
+// rs1_val == 8388608, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x800000;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x80002e, 0x800000, 0x2e, x3, 136, x4)
+
+inst_49:
+// rs1_val == 4194304, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x400000;  immval:-0x3
+TEST_IMM_OP( xori, x11, x10, 0xffbffffd, 0x400000, -0x3, x3, 140, x4)
+
+inst_50:
+// rs1_val == 2097152, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x200000;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffdfffd4, 0x200000, -0x2c, x3, 144, x4)
+
+inst_51:
+// rs1_val == 1048576, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x100000;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x100554, 0x100000, 0x554, x3, 148, x4)
+
+inst_52:
+// rs1_val == 524288, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x80000;  immval:-0x201
+TEST_IMM_OP( xori, x11, x10, 0xfff7fdff, 0x80000, -0x201, x3, 152, x4)
+
+inst_53:
+// rs1_val == 131072, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x20000;  immval:-0x2
+TEST_IMM_OP( xori, x11, x10, 0xfffdfffe, 0x20000, -0x2, x3, 156, x4)
+
+inst_54:
+// rs1_val == 65536, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x10000;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x10003, 0x10000, 0x3, x3, 160, x4)
+
+inst_55:
+// rs1_val == 32768, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x8000;  immval:0x7ff
+TEST_IMM_OP( xori, x11, x10, 0x87ff, 0x8000, 0x7ff, x3, 164, x4)
+
+inst_56:
+// rs1_val == 16384, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4000;  immval:-0x41
+TEST_IMM_OP( xori, x11, x10, 0xffffbfbf, 0x4000, -0x41, x3, 168, x4)
+
+inst_57:
+// rs1_val == 8192, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2000;  immval:0x7
+TEST_IMM_OP( xori, x11, x10, 0x2007, 0x2000, 0x7, x3, 172, x4)
+
+inst_58:
+// rs1_val == 4096, imm_val == 4
+// opcode: xori ; op1:x10; dest:x11; op1val:0x1000;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x1004, 0x1000, 0x4, x3, 176, x4)
+
+inst_59:
+// rs1_val == 2048, imm_val == 1024
+// opcode: xori ; op1:x10; dest:x11; op1val:0x800;  immval:0x400
+TEST_IMM_OP( xori, x11, x10, 0xc00, 0x800, 0x400, x3, 180, x4)
+
+inst_60:
+// rs1_val == 1024, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x400;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x267, 0x400, 0x667, x3, 184, x4)
+
+inst_61:
+// rs1_val == 512, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x200;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x204, 0x200, 0x4, x3, 188, x4)
+
+inst_62:
+// rs1_val == 256, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x100;  immval:-0x8
+TEST_IMM_OP( xori, x11, x10, 0xfffffef8, 0x100, -0x8, x3, 192, x4)
+
+inst_63:
+// rs1_val == 128, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x80;  immval:-0x2
+TEST_IMM_OP( xori, x11, x10, 0xffffff7e, 0x80, -0x2, x3, 196, x4)
+
+inst_64:
+// rs1_val == 64, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x40;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x40, 0x40, 0x0, x3, 200, x4)
+
+inst_65:
+// rs1_val == 32, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x20;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x20, 0x20, 0x0, x3, 204, x4)
+
+inst_66:
+// rs1_val == 16, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x10;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x15, 0x10, 0x5, x3, 208, x4)
+
+inst_67:
+// rs1_val == 8, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x8;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xb, 0x8, 0x3, x3, 212, x4)
+
+inst_68:
+// rs1_val == 4, rs1_val==4 and imm_val==-45
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd7, 0x4, -0x2d, x3, 216, x4)
+
+inst_69:
+// rs1_val == 2, rs1_val==2 and imm_val==1364
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x556, 0x2, 0x554, x3, 220, x4)
+
+inst_70:
+// rs1_val == 1, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x1;  immval:-0x11
+TEST_IMM_OP( xori, x11, x10, 0xffffffee, 0x1, -0x11, x3, 224, x4)
+
+inst_71:
+// imm_val == 256, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3fffffff;  immval:0x100
+TEST_IMM_OP( xori, x11, x10, 0x3ffffeff, 0x3fffffff, 0x100, x3, 228, x4)
+
+inst_72:
+// imm_val == 128, rs1_val == -1431655766
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x80
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa2a, -0x55555556, 0x80, x3, 232, x4)
+
+inst_73:
+// imm_val == 32, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x1;  immval:0x20
+TEST_IMM_OP( xori, x11, x10, 0x21, 0x1, 0x20, x3, 236, x4)
+
+inst_74:
+// imm_val == 8, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x7;  immval:0x8
+TEST_IMM_OP( xori, x11, x10, 0xfffffff1, -0x7, 0x8, x3, 240, x4)
+
+inst_75:
+// rs1_val==46341 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xb52b, 0xb505, 0x2e, x3, 244, x4)
+
+inst_76:
+// rs1_val==46341 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad1, 0xb505, -0x2c, x3, 248, x4)
+
+inst_77:
+// rs1_val==46341 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xb362, 0xb505, 0x667, x3, 252, x4)
+
+inst_78:
+// rs1_val==46341 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xb631, 0xb505, 0x334, x3, 256, x4)
+
+inst_79:
+// rs1_val==46341 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xb503, 0xb505, 0x6, x3, 260, x4)
+
+inst_80:
+// rs1_val==46341 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xffff4fae, 0xb505, -0x555, x3, 264, x4)
+
+inst_81:
+// rs1_val==46341 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xb053, 0xb505, 0x556, x3, 268, x4)
+
+inst_82:
+// rs1_val==46341 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xb501, 0xb505, 0x4, x3, 272, x4)
+
+inst_83:
+// rs1_val==46341 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xb529, 0xb505, 0x2c, x3, 276, x4)
+
+inst_84:
+// rs1_val==46341 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xb505, 0xb505, 0x0, x3, 280, x4)
+
+inst_85:
+// rs1_val==46341 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xb360, 0xb505, 0x665, x3, 284, x4)
+
+inst_86:
+// rs1_val==46341 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xb637, 0xb505, 0x332, x3, 288, x4)
+
+inst_87:
+// rs1_val==46341 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xb051, 0xb505, 0x554, x3, 292, x4)
+
+inst_88:
+// rs1_val==46341 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xb507, 0xb505, 0x2, x3, 296, x4)
+
+inst_89:
+// rs1_val==46341 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xb528, 0xb505, 0x2d, x3, 300, x4)
+
+inst_90:
+// rs1_val==46341 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad6, 0xb505, -0x2d, x3, 304, x4)
+
+inst_91:
+// rs1_val==46341 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xb363, 0xb505, 0x666, x3, 308, x4)
+
+inst_92:
+// rs1_val==46341 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xb636, 0xb505, 0x333, x3, 312, x4)
+
+inst_93:
+// rs1_val==46341 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xb500, 0xb505, 0x5, x3, 316, x4)
+
+inst_94:
+// rs1_val==46341 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xffff4faf, 0xb505, -0x556, x3, 320, x4)
+
+inst_95:
+// rs1_val==46341 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xb050, 0xb505, 0x555, x3, 324, x4)
+
+inst_96:
+// rs1_val==46341 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb505;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xb506, 0xb505, 0x3, x3, 328, x4)
+
+inst_97:
+// rs1_val==-46339 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad3, -0xb503, 0x2e, x3, 332, x4)
+
+inst_98:
+// rs1_val==-46339 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xb529, -0xb503, -0x2c, x3, 336, x4)
+
+inst_99:
+// rs1_val==-46339 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xffff4c9a, -0xb503, 0x667, x3, 340, x4)
+
+inst_100:
+// rs1_val==-46339 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xffff49c9, -0xb503, 0x334, x3, 344, x4)
+
+inst_101:
+// rs1_val==-46339 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xffff4afb, -0xb503, 0x6, x3, 348, x4)
+
+inst_102:
+// rs1_val==-46339 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xb056, -0xb503, -0x555, x3, 352, x4)
+
+inst_103:
+// rs1_val==-46339 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xffff4fab, -0xb503, 0x556, x3, 356, x4)
+
+inst_104:
+// rs1_val==-46339 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xffff4af9, -0xb503, 0x4, x3, 360, x4)
+
+inst_105:
+// rs1_val==-46339 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad1, -0xb503, 0x2c, x3, 364, x4)
+
+inst_106:
+// rs1_val==-46339 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xffff4afd, -0xb503, 0x0, x3, 368, x4)
+
+inst_107:
+// rs1_val==-46339 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xffff4c98, -0xb503, 0x665, x3, 372, x4)
+
+inst_108:
+// rs1_val==-46339 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xffff49cf, -0xb503, 0x332, x3, 376, x4)
+
+inst_109:
+// rs1_val==-46339 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa9, -0xb503, 0x554, x3, 380, x4)
+
+inst_110:
+// rs1_val==-46339 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xffff4aff, -0xb503, 0x2, x3, 384, x4)
+
+inst_111:
+// rs1_val==-46339 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad0, -0xb503, 0x2d, x3, 388, x4)
+
+inst_112:
+// rs1_val==-46339 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xb52e, -0xb503, -0x2d, x3, 392, x4)
+
+inst_113:
+// rs1_val==-46339 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xffff4c9b, -0xb503, 0x666, x3, 396, x4)
+
+inst_114:
+// rs1_val==-46339 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xffff49ce, -0xb503, 0x333, x3, 400, x4)
+
+inst_115:
+// rs1_val==-46339 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xffff4af8, -0xb503, 0x5, x3, 404, x4)
+
+inst_116:
+// rs1_val==-46339 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xb057, -0xb503, -0x556, x3, 408, x4)
+
+inst_117:
+// rs1_val==-46339 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa8, -0xb503, 0x555, x3, 412, x4)
+
+inst_118:
+// rs1_val==-46339 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb503;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xffff4afe, -0xb503, 0x3, x3, 416, x4)
+
+inst_119:
+// rs1_val==1717986919 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x66666649, 0x66666667, 0x2e, x3, 420, x4)
+
+inst_120:
+// rs1_val==1717986919 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0x999999b3, 0x66666667, -0x2c, x3, 424, x4)
+
+inst_121:
+// rs1_val==1717986919 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x66666000, 0x66666667, 0x667, x3, 428, x4)
+
+inst_122:
+// rs1_val==1717986919 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x66666553, 0x66666667, 0x334, x3, 432, x4)
+
+inst_123:
+// rs1_val==1717986919 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x66666661, 0x66666667, 0x6, x3, 436, x4)
+
+inst_124:
+// rs1_val==1717986919 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0x99999ccc, 0x66666667, -0x555, x3, 440, x4)
+
+inst_125:
+// rs1_val==1717986919 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x66666331, 0x66666667, 0x556, x3, 444, x4)
+
+inst_126:
+// rs1_val==1717986919 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x66666663, 0x66666667, 0x4, x3, 448, x4)
+
+inst_127:
+// rs1_val==1717986919 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x6666664b, 0x66666667, 0x2c, x3, 452, x4)
+
+inst_128:
+// rs1_val==1717986919 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x66666667, 0x66666667, 0x0, x3, 456, x4)
+
+inst_129:
+// rs1_val==1717986919 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x66666002, 0x66666667, 0x665, x3, 460, x4)
+
+inst_130:
+// rs1_val==1717986919 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x66666555, 0x66666667, 0x332, x3, 464, x4)
+
+inst_131:
+// rs1_val==1717986919 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x66666333, 0x66666667, 0x554, x3, 468, x4)
+
+inst_132:
+// rs1_val==1717986919 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x66666665, 0x66666667, 0x2, x3, 472, x4)
+
+inst_133:
+// rs1_val==1717986919 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x6666664a, 0x66666667, 0x2d, x3, 476, x4)
+
+inst_134:
+// rs1_val==1717986919 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0x999999b4, 0x66666667, -0x2d, x3, 480, x4)
+
+inst_135:
+// rs1_val==1717986919 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x66666001, 0x66666667, 0x666, x3, 484, x4)
+
+inst_136:
+// rs1_val==1717986919 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x66666554, 0x66666667, 0x333, x3, 488, x4)
+
+inst_137:
+// rs1_val==1717986919 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x66666662, 0x66666667, 0x5, x3, 492, x4)
+
+inst_138:
+// rs1_val==1717986919 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0x99999ccd, 0x66666667, -0x556, x3, 496, x4)
+
+inst_139:
+// rs1_val==1717986919 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x66666332, 0x66666667, 0x555, x3, 500, x4)
+
+inst_140:
+// rs1_val==1717986919 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666667;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x66666664, 0x66666667, 0x3, x3, 504, x4)
+
+inst_141:
+// rs1_val==858993460 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x3333331a, 0x33333334, 0x2e, x3, 508, x4)
+
+inst_142:
+// rs1_val==858993460 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xcccccce0, 0x33333334, -0x2c, x3, 512, x4)
+
+inst_143:
+// rs1_val==858993460 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x33333553, 0x33333334, 0x667, x3, 516, x4)
+
+inst_144:
+// rs1_val==858993460 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x33333000, 0x33333334, 0x334, x3, 520, x4)
+
+inst_145:
+// rs1_val==858993460 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x33333332, 0x33333334, 0x6, x3, 524, x4)
+
+inst_146:
+// rs1_val==858993460 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xccccc99f, 0x33333334, -0x555, x3, 528, x4)
+
+inst_147:
+// rs1_val==858993460 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x33333662, 0x33333334, 0x556, x3, 532, x4)
+
+inst_148:
+// rs1_val==858993460 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x33333330, 0x33333334, 0x4, x3, 536, x4)
+
+inst_149:
+// rs1_val==858993460 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x33333318, 0x33333334, 0x2c, x3, 540, x4)
+
+inst_150:
+// rs1_val==858993460 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x33333334, 0x33333334, 0x0, x3, 544, x4)
+
+inst_151:
+// rs1_val==858993460 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x33333551, 0x33333334, 0x665, x3, 548, x4)
+
+inst_152:
+// rs1_val==858993460 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x33333006, 0x33333334, 0x332, x3, 552, x4)
+
+inst_153:
+// rs1_val==858993460 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x33333660, 0x33333334, 0x554, x3, 556, x4)
+
+inst_154:
+// rs1_val==858993460 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x33333336, 0x33333334, 0x2, x3, 560, x4)
+
+inst_155:
+// rs1_val==858993460 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x33333319, 0x33333334, 0x2d, x3, 564, x4)
+
+inst_156:
+// rs1_val==858993460 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xcccccce7, 0x33333334, -0x2d, x3, 568, x4)
+
+inst_157:
+// rs1_val==858993460 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x33333552, 0x33333334, 0x666, x3, 572, x4)
+
+inst_158:
+// rs1_val==858993460 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x33333007, 0x33333334, 0x333, x3, 576, x4)
+
+inst_159:
+// rs1_val==858993460 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x33333331, 0x33333334, 0x5, x3, 580, x4)
+
+inst_160:
+// rs1_val==858993460 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xccccc99e, 0x33333334, -0x556, x3, 584, x4)
+
+inst_161:
+// rs1_val==858993460 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x33333661, 0x33333334, 0x555, x3, 588, x4)
+
+inst_162:
+// rs1_val==858993460 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333334;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x33333337, 0x33333334, 0x3, x3, 592, x4)
+
+inst_163:
+// rs1_val==6 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x28, 0x6, 0x2e, x3, 596, x4)
+
+inst_164:
+// rs1_val==6 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd2, 0x6, -0x2c, x3, 600, x4)
+
+inst_165:
+// rs1_val==6 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x661, 0x6, 0x667, x3, 604, x4)
+
+inst_166:
+// rs1_val==6 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x332, 0x6, 0x334, x3, 608, x4)
+
+inst_167:
+// rs1_val==6 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x6, 0x6, x3, 612, x4)
+
+inst_168:
+// rs1_val==6 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaad, 0x6, -0x555, x3, 616, x4)
+
+inst_169:
+// rs1_val==6 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x550, 0x6, 0x556, x3, 620, x4)
+
+inst_170:
+// rs1_val==6 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x2, 0x6, 0x4, x3, 624, x4)
+
+inst_171:
+// rs1_val==6 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x2a, 0x6, 0x2c, x3, 628, x4)
+
+inst_172:
+// rs1_val==6 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x6, 0x0, x3, 632, x4)
+
+inst_173:
+// rs1_val==6 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x663, 0x6, 0x665, x3, 636, x4)
+
+inst_174:
+// rs1_val==6 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x334, 0x6, 0x332, x3, 640, x4)
+
+inst_175:
+// rs1_val==6 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x552, 0x6, 0x554, x3, 644, x4)
+
+inst_176:
+// rs1_val==6 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x4, 0x6, 0x2, x3, 648, x4)
+
+inst_177:
+// rs1_val==6 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x2b, 0x6, 0x2d, x3, 652, x4)
+
+inst_178:
+// rs1_val==6 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd5, 0x6, -0x2d, x3, 656, x4)
+
+inst_179:
+// rs1_val==6 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x660, 0x6, 0x666, x3, 660, x4)
+
+inst_180:
+// rs1_val==6 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x335, 0x6, 0x333, x3, 664, x4)
+
+inst_181:
+// rs1_val==6 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x3, 0x6, 0x5, x3, 668, x4)
+
+inst_182:
+// rs1_val==6 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaac, 0x6, -0x556, x3, 672, x4)
+
+inst_183:
+// rs1_val==6 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x553, 0x6, 0x555, x3, 676, x4)
+
+inst_184:
+// rs1_val==6 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x6;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x5, 0x6, 0x3, x3, 680, x4)
+
+inst_185:
+// rs1_val==-1431655765 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa85, -0x55555555, 0x2e, x3, 684, x4)
+
+inst_186:
+// rs1_val==-1431655765 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0x5555557f, -0x55555555, -0x2c, x3, 688, x4)
+
+inst_187:
+// rs1_val==-1431655765 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaccc, -0x55555555, 0x667, x3, 692, x4)
+
+inst_188:
+// rs1_val==-1431655765 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa99f, -0x55555555, 0x334, x3, 696, x4)
+
+inst_189:
+// rs1_val==-1431655765 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaad, -0x55555555, 0x6, x3, 700, x4)
+
+inst_190:
+// rs1_val==-1431655765 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0x55555000, -0x55555555, -0x555, x3, 704, x4)
+
+inst_191:
+// rs1_val==-1431655765 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffd, -0x55555555, 0x556, x3, 708, x4)
+
+inst_192:
+// rs1_val==-1431655765 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaaf, -0x55555555, 0x4, x3, 712, x4)
+
+inst_193:
+// rs1_val==-1431655765 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa87, -0x55555555, 0x2c, x3, 716, x4)
+
+inst_194:
+// rs1_val==-1431655765 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaab, -0x55555555, 0x0, x3, 720, x4)
+
+inst_195:
+// rs1_val==-1431655765 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xaaaaacce, -0x55555555, 0x665, x3, 724, x4)
+
+inst_196:
+// rs1_val==-1431655765 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa999, -0x55555555, 0x332, x3, 728, x4)
+
+inst_197:
+// rs1_val==-1431655765 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xaaaaafff, -0x55555555, 0x554, x3, 732, x4)
+
+inst_198:
+// rs1_val==-1431655765 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaa9, -0x55555555, 0x2, x3, 736, x4)
+
+inst_199:
+// rs1_val==-1431655765 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa86, -0x55555555, 0x2d, x3, 740, x4)
+
+inst_200:
+// rs1_val==-1431655765 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0x55555578, -0x55555555, -0x2d, x3, 744, x4)
+
+inst_201:
+// rs1_val==-1431655765 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaccd, -0x55555555, 0x666, x3, 748, x4)
+
+inst_202:
+// rs1_val==-1431655765 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa998, -0x55555555, 0x333, x3, 752, x4)
+
+inst_203:
+// rs1_val==-1431655765 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaae, -0x55555555, 0x5, x3, 756, x4)
+
+inst_204:
+// rs1_val==-1431655765 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0x55555001, -0x55555555, -0x556, x3, 760, x4)
+
+inst_205:
+// rs1_val==-1431655765 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffe, -0x55555555, 0x555, x3, 764, x4)
+
+inst_206:
+// rs1_val==-1431655765 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555555;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaa8, -0x55555555, 0x3, x3, 768, x4)
+
+inst_207:
+// rs1_val==1431655766 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x55555578, 0x55555556, 0x2e, x3, 772, x4)
+
+inst_208:
+// rs1_val==1431655766 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa82, 0x55555556, -0x2c, x3, 776, x4)
+
+inst_209:
+// rs1_val==1431655766 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x55555331, 0x55555556, 0x667, x3, 780, x4)
+
+inst_210:
+// rs1_val==1431655766 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x55555662, 0x55555556, 0x334, x3, 784, x4)
+
+inst_211:
+// rs1_val==1431655766 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x55555550, 0x55555556, 0x6, x3, 788, x4)
+
+inst_212:
+// rs1_val==1431655766 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffd, 0x55555556, -0x555, x3, 792, x4)
+
+inst_213:
+// rs1_val==1431655766 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x55555000, 0x55555556, 0x556, x3, 796, x4)
+
+inst_214:
+// rs1_val==1431655766 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x55555552, 0x55555556, 0x4, x3, 800, x4)
+
+inst_215:
+// rs1_val==1431655766 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x5555557a, 0x55555556, 0x2c, x3, 804, x4)
+
+inst_216:
+// rs1_val==1431655766 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x55555556, 0x55555556, 0x0, x3, 808, x4)
+
+inst_217:
+// rs1_val==1431655766 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x55555333, 0x55555556, 0x665, x3, 812, x4)
+
+inst_218:
+// rs1_val==1431655766 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x55555664, 0x55555556, 0x332, x3, 816, x4)
+
+inst_219:
+// rs1_val==1431655766 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x55555002, 0x55555556, 0x554, x3, 820, x4)
+
+inst_220:
+// rs1_val==1431655766 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x55555554, 0x55555556, 0x2, x3, 824, x4)
+
+inst_221:
+// rs1_val==1431655766 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x5555557b, 0x55555556, 0x2d, x3, 828, x4)
+
+inst_222:
+// rs1_val==1431655766 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa85, 0x55555556, -0x2d, x3, 832, x4)
+
+inst_223:
+// rs1_val==1431655766 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x55555330, 0x55555556, 0x666, x3, 836, x4)
+
+inst_224:
+// rs1_val==1431655766 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x55555665, 0x55555556, 0x333, x3, 840, x4)
+
+inst_225:
+// rs1_val==1431655766 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x55555553, 0x55555556, 0x5, x3, 844, x4)
+
+inst_226:
+// rs1_val==1431655766 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffc, 0x55555556, -0x556, x3, 848, x4)
+
+inst_227:
+// rs1_val==1431655766 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x55555003, 0x55555556, 0x555, x3, 852, x4)
+
+inst_228:
+// rs1_val==1431655766 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555556;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x55555555, 0x55555556, 0x3, x3, 856, x4)
+
+inst_229:
+// rs1_val==4 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x2a, 0x4, 0x2e, x3, 860, x4)
+
+inst_230:
+// rs1_val==4 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd0, 0x4, -0x2c, x3, 864, x4)
+
+inst_231:
+// rs1_val==4 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x663, 0x4, 0x667, x3, 868, x4)
+
+inst_232:
+// rs1_val==4 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x330, 0x4, 0x334, x3, 872, x4)
+
+inst_233:
+// rs1_val==4 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x2, 0x4, 0x6, x3, 876, x4)
+
+inst_234:
+// rs1_val==4 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaaf, 0x4, -0x555, x3, 880, x4)
+
+inst_235:
+// rs1_val==4 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x552, 0x4, 0x556, x3, 884, x4)
+
+inst_236:
+// rs1_val==4 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x4, 0x4, x3, 888, x4)
+
+inst_237:
+// rs1_val==4 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x28, 0x4, 0x2c, x3, 892, x4)
+
+inst_238:
+// rs1_val==4 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x4, 0x4, 0x0, x3, 896, x4)
+
+inst_239:
+// rs1_val==4 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x661, 0x4, 0x665, x3, 900, x4)
+
+inst_240:
+// rs1_val==4 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x336, 0x4, 0x332, x3, 904, x4)
+
+inst_241:
+// rs1_val==4 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x550, 0x4, 0x554, x3, 908, x4)
+
+inst_242:
+// rs1_val==4 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x4, 0x2, x3, 912, x4)
+
+inst_243:
+// rs1_val==4 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x29, 0x4, 0x2d, x3, 916, x4)
+
+inst_244:
+// rs1_val==4 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x662, 0x4, 0x666, x3, 920, x4)
+
+inst_245:
+// rs1_val==4 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x337, 0x4, 0x333, x3, 924, x4)
+
+inst_246:
+// rs1_val==4 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x1, 0x4, 0x5, x3, 928, x4)
+
+inst_247:
+// rs1_val==4 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaae, 0x4, -0x556, x3, 932, x4)
+
+inst_248:
+// rs1_val==4 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x551, 0x4, 0x555, x3, 936, x4)
+
+inst_249:
+// rs1_val==4 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x4;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x7, 0x4, 0x3, x3, 940, x4)
+
+inst_250:
+// rs1_val==46339 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xb52d, 0xb503, 0x2e, x3, 944, x4)
+
+inst_251:
+// rs1_val==46339 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad7, 0xb503, -0x2c, x3, 948, x4)
+
+inst_252:
+// rs1_val==46339 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xb364, 0xb503, 0x667, x3, 952, x4)
+
+inst_253:
+// rs1_val==46339 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xb637, 0xb503, 0x334, x3, 956, x4)
+
+inst_254:
+// rs1_val==46339 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xb505, 0xb503, 0x6, x3, 960, x4)
+
+inst_255:
+// rs1_val==46339 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa8, 0xb503, -0x555, x3, 964, x4)
+
+inst_256:
+// rs1_val==46339 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xb055, 0xb503, 0x556, x3, 968, x4)
+
+inst_257:
+// rs1_val==46339 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xb507, 0xb503, 0x4, x3, 972, x4)
+
+inst_258:
+// rs1_val==46339 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xb52f, 0xb503, 0x2c, x3, 976, x4)
+
+inst_259:
+// rs1_val==46339 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xb503, 0xb503, 0x0, x3, 980, x4)
+
+inst_260:
+// rs1_val==46339 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xb366, 0xb503, 0x665, x3, 984, x4)
+
+inst_261:
+// rs1_val==46339 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xb631, 0xb503, 0x332, x3, 988, x4)
+
+inst_262:
+// rs1_val==46339 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xb057, 0xb503, 0x554, x3, 992, x4)
+
+inst_263:
+// rs1_val==46339 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xb501, 0xb503, 0x2, x3, 996, x4)
+
+inst_264:
+// rs1_val==46339 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xb52e, 0xb503, 0x2d, x3, 1000, x4)
+
+inst_265:
+// rs1_val==46339 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad0, 0xb503, -0x2d, x3, 1004, x4)
+
+inst_266:
+// rs1_val==46339 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xb365, 0xb503, 0x666, x3, 1008, x4)
+
+inst_267:
+// rs1_val==46339 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xb630, 0xb503, 0x333, x3, 1012, x4)
+
+inst_268:
+// rs1_val==46339 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xb506, 0xb503, 0x5, x3, 1016, x4)
+
+inst_269:
+// rs1_val==46339 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa9, 0xb503, -0x556, x3, 1020, x4)
+
+inst_270:
+// rs1_val==46339 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xb056, 0xb503, 0x555, x3, 1024, x4)
+
+inst_271:
+// rs1_val==46339 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb503;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xb500, 0xb503, 0x3, x3, 1028, x4)
+
+inst_272:
+// rs1_val==0 and imm_val==46, rs1_val == 0
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x2e, 0x0, 0x2e, x3, 1032, x4)
+
+inst_273:
+// rs1_val==0 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd4, 0x0, -0x2c, x3, 1036, x4)
+
+inst_274:
+// rs1_val==0 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x667, 0x0, 0x667, x3, 1040, x4)
+
+inst_275:
+// rs1_val==0 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x334, 0x0, 0x334, x3, 1044, x4)
+
+inst_276:
+// rs1_val==0 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x0, 0x6, x3, 1048, x4)
+
+inst_277:
+// rs1_val==0 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaab, 0x0, -0x555, x3, 1052, x4)
+
+inst_278:
+// rs1_val==0 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x556, 0x0, 0x556, x3, 1056, x4)
+
+inst_279:
+// rs1_val==0 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x4, 0x0, 0x4, x3, 1060, x4)
+
+inst_280:
+// rs1_val==0 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x2c, 0x0, 0x2c, x3, 1064, x4)
+
+inst_281:
+// rs1_val==0 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x0, 0x0, x3, 1068, x4)
+
+inst_282:
+// rs1_val==0 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x665, 0x0, 0x665, x3, 1072, x4)
+
+inst_283:
+// rs1_val==0 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x332, 0x0, 0x332, x3, 1076, x4)
+
+inst_284:
+// rs1_val==0 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x554, 0x0, 0x554, x3, 1080, x4)
+
+inst_285:
+// rs1_val==0 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x2, 0x0, 0x2, x3, 1084, x4)
+
+inst_286:
+// rs1_val==0 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x2d, 0x0, 0x2d, x3, 1088, x4)
+
+inst_287:
+// rs1_val==0 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd3, 0x0, -0x2d, x3, 1092, x4)
+
+inst_288:
+// rs1_val==0 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x666, 0x0, 0x666, x3, 1096, x4)
+
+inst_289:
+// rs1_val==0 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x333, 0x0, 0x333, x3, 1100, x4)
+
+inst_290:
+// rs1_val==0 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x5, 0x0, 0x5, x3, 1104, x4)
+
+inst_291:
+// rs1_val==0 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaaa, 0x0, -0x556, x3, 1108, x4)
+
+inst_292:
+// rs1_val==0 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x555, 0x0, 0x555, x3, 1112, x4)
+
+inst_293:
+// rs1_val==0 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x0;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x3, 0x0, 0x3, x3, 1116, x4)
+
+inst_294:
+// rs1_val==1717986917 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x6666664b, 0x66666665, 0x2e, x3, 1120, x4)
+
+inst_295:
+// rs1_val==1717986917 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0x999999b1, 0x66666665, -0x2c, x3, 1124, x4)
+
+inst_296:
+// rs1_val==1717986917 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x66666002, 0x66666665, 0x667, x3, 1128, x4)
+
+inst_297:
+// rs1_val==1717986917 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x66666551, 0x66666665, 0x334, x3, 1132, x4)
+
+inst_298:
+// rs1_val==1717986917 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x66666663, 0x66666665, 0x6, x3, 1136, x4)
+
+inst_299:
+// rs1_val==1717986917 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0x99999cce, 0x66666665, -0x555, x3, 1140, x4)
+
+inst_300:
+// rs1_val==1717986917 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x66666333, 0x66666665, 0x556, x3, 1144, x4)
+
+inst_301:
+// rs1_val==1717986917 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x66666661, 0x66666665, 0x4, x3, 1148, x4)
+
+inst_302:
+// rs1_val==1717986917 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x66666649, 0x66666665, 0x2c, x3, 1152, x4)
+
+inst_303:
+// rs1_val==-1431655766 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0x55555001, -0x55555556, -0x555, x3, 1156, x4)
+
+inst_304:
+// rs1_val==-1431655766 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffc, -0x55555556, 0x556, x3, 1160, x4)
+
+inst_305:
+// rs1_val==-1431655766 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaae, -0x55555556, 0x4, x3, 1164, x4)
+
+inst_306:
+// rs1_val==-1431655766 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa86, -0x55555556, 0x2c, x3, 1168, x4)
+
+inst_307:
+// rs1_val==-1431655766 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaaa, -0x55555556, 0x0, x3, 1172, x4)
+
+inst_308:
+// rs1_val==-1431655766 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaccf, -0x55555556, 0x665, x3, 1176, x4)
+
+inst_309:
+// rs1_val==-1431655766 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa998, -0x55555556, 0x332, x3, 1180, x4)
+
+inst_310:
+// rs1_val==-1431655766 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffe, -0x55555556, 0x554, x3, 1184, x4)
+
+inst_311:
+// rs1_val==-1431655766 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaa8, -0x55555556, 0x2, x3, 1188, x4)
+
+inst_312:
+// rs1_val==-1431655766 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa87, -0x55555556, 0x2d, x3, 1192, x4)
+
+inst_313:
+// rs1_val==-1431655766 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0x55555579, -0x55555556, -0x2d, x3, 1196, x4)
+
+inst_314:
+// rs1_val==-1431655766 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaccc, -0x55555556, 0x666, x3, 1200, x4)
+
+inst_315:
+// rs1_val==-1431655766 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa999, -0x55555556, 0x333, x3, 1204, x4)
+
+inst_316:
+// rs1_val==-1431655766 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaaf, -0x55555556, 0x5, x3, 1208, x4)
+
+inst_317:
+// rs1_val==-1431655766 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0x55555000, -0x55555556, -0x556, x3, 1212, x4)
+
+inst_318:
+// rs1_val==-1431655766 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xaaaaafff, -0x55555556, 0x555, x3, 1216, x4)
+
+inst_319:
+// rs1_val==-1431655766 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaa9, -0x55555556, 0x3, x3, 1220, x4)
+
+inst_320:
+// rs1_val==1431655765 and imm_val==46, rs1_val == 1431655765
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x5555557b, 0x55555555, 0x2e, x3, 1224, x4)
+
+inst_321:
+// rs1_val==1431655765 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa81, 0x55555555, -0x2c, x3, 1228, x4)
+
+inst_322:
+// rs1_val==1431655765 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x55555332, 0x55555555, 0x667, x3, 1232, x4)
+
+inst_323:
+// rs1_val==1431655765 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x55555661, 0x55555555, 0x334, x3, 1236, x4)
+
+inst_324:
+// rs1_val==1431655765 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x55555553, 0x55555555, 0x6, x3, 1240, x4)
+
+inst_325:
+// rs1_val==1431655765 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffe, 0x55555555, -0x555, x3, 1244, x4)
+
+inst_326:
+// rs1_val==1431655765 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x55555003, 0x55555555, 0x556, x3, 1248, x4)
+
+inst_327:
+// rs1_val==1431655765 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x55555551, 0x55555555, 0x4, x3, 1252, x4)
+
+inst_328:
+// rs1_val==1431655765 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x55555579, 0x55555555, 0x2c, x3, 1256, x4)
+
+inst_329:
+// rs1_val==1431655765 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x55555555, 0x55555555, 0x0, x3, 1260, x4)
+
+inst_330:
+// rs1_val==1431655765 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x55555330, 0x55555555, 0x665, x3, 1264, x4)
+
+inst_331:
+// rs1_val==1431655765 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x55555667, 0x55555555, 0x332, x3, 1268, x4)
+
+inst_332:
+// rs1_val==1431655765 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x55555001, 0x55555555, 0x554, x3, 1272, x4)
+
+inst_333:
+// rs1_val==1431655765 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x55555557, 0x55555555, 0x2, x3, 1276, x4)
+
+inst_334:
+// rs1_val==1431655765 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x55555578, 0x55555555, 0x2d, x3, 1280, x4)
+
+inst_335:
+// rs1_val==1431655765 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa86, 0x55555555, -0x2d, x3, 1284, x4)
+
+inst_336:
+// rs1_val==1431655765 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x55555333, 0x55555555, 0x666, x3, 1288, x4)
+
+inst_337:
+// rs1_val==1431655765 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x55555666, 0x55555555, 0x333, x3, 1292, x4)
+
+inst_338:
+// rs1_val==1431655765 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x55555550, 0x55555555, 0x5, x3, 1296, x4)
+
+inst_339:
+// rs1_val==1431655765 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xaaaaafff, 0x55555555, -0x556, x3, 1300, x4)
+
+inst_340:
+// rs1_val==1431655765 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x55555000, 0x55555555, 0x555, x3, 1304, x4)
+
+inst_341:
+// rs1_val==1431655765 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555555;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x55555556, 0x55555555, 0x3, x3, 1308, x4)
+
+inst_342:
+// rs1_val==3 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x2d, 0x3, 0x2e, x3, 1312, x4)
+
+inst_343:
+// rs1_val==3 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd7, 0x3, -0x2c, x3, 1316, x4)
+
+inst_344:
+// rs1_val==3 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x664, 0x3, 0x667, x3, 1320, x4)
+
+inst_345:
+// rs1_val==3 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x337, 0x3, 0x334, x3, 1324, x4)
+
+inst_346:
+// rs1_val==3 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x5, 0x3, 0x6, x3, 1328, x4)
+
+inst_347:
+// rs1_val==3 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaa8, 0x3, -0x555, x3, 1332, x4)
+
+inst_348:
+// rs1_val==3 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x555, 0x3, 0x556, x3, 1336, x4)
+
+inst_349:
+// rs1_val==3 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x7, 0x3, 0x4, x3, 1340, x4)
+
+inst_350:
+// rs1_val==3 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x2f, 0x3, 0x2c, x3, 1344, x4)
+
+inst_351:
+// rs1_val==3 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x3, 0x3, 0x0, x3, 1348, x4)
+
+inst_352:
+// rs1_val==3 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x666, 0x3, 0x665, x3, 1352, x4)
+
+inst_353:
+// rs1_val==3 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x331, 0x3, 0x332, x3, 1356, x4)
+
+inst_354:
+// rs1_val==3 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x557, 0x3, 0x554, x3, 1360, x4)
+
+inst_355:
+// rs1_val==3 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x1, 0x3, 0x2, x3, 1364, x4)
+
+inst_356:
+// rs1_val==3 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x2e, 0x3, 0x2d, x3, 1368, x4)
+
+inst_357:
+// rs1_val==3 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd0, 0x3, -0x2d, x3, 1372, x4)
+
+inst_358:
+// rs1_val==3 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x665, 0x3, 0x666, x3, 1376, x4)
+
+inst_359:
+// rs1_val==3 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x330, 0x3, 0x333, x3, 1380, x4)
+
+inst_360:
+// rs1_val==3 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x3, 0x5, x3, 1384, x4)
+
+inst_361:
+// rs1_val==3 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaa9, 0x3, -0x556, x3, 1388, x4)
+
+inst_362:
+// rs1_val==3 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x556, 0x3, 0x555, x3, 1392, x4)
+
+inst_363:
+// rs1_val==3 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x3;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x3, 0x3, x3, 1396, x4)
+
+inst_364:
+// rs1_val==1717986917 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x66666665, 0x66666665, 0x0, x3, 1400, x4)
+
+inst_365:
+// rs1_val==1717986917 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x66666000, 0x66666665, 0x665, x3, 1404, x4)
+
+inst_366:
+// rs1_val==1717986917 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x66666557, 0x66666665, 0x332, x3, 1408, x4)
+
+inst_367:
+// rs1_val==1717986917 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x66666331, 0x66666665, 0x554, x3, 1412, x4)
+
+inst_368:
+// rs1_val==1717986917 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x66666667, 0x66666665, 0x2, x3, 1416, x4)
+
+inst_369:
+// rs1_val==1717986917 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x66666648, 0x66666665, 0x2d, x3, 1420, x4)
+
+inst_370:
+// rs1_val==1717986917 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0x999999b6, 0x66666665, -0x2d, x3, 1424, x4)
+
+inst_371:
+// rs1_val==1717986917 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x66666003, 0x66666665, 0x666, x3, 1428, x4)
+
+inst_372:
+// rs1_val==1717986917 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x66666556, 0x66666665, 0x333, x3, 1432, x4)
+
+inst_373:
+// rs1_val==1717986917 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x66666660, 0x66666665, 0x5, x3, 1436, x4)
+
+inst_374:
+// rs1_val==1717986917 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0x99999ccf, 0x66666665, -0x556, x3, 1440, x4)
+
+inst_375:
+// rs1_val==1717986917 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x66666330, 0x66666665, 0x555, x3, 1444, x4)
+
+inst_376:
+// rs1_val==1717986917 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666665;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x66666666, 0x66666665, 0x3, x3, 1448, x4)
+
+inst_377:
+// rs1_val==858993458 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x3333331c, 0x33333332, 0x2e, x3, 1452, x4)
+
+inst_378:
+// rs1_val==858993458 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xcccccce6, 0x33333332, -0x2c, x3, 1456, x4)
+
+inst_379:
+// rs1_val==858993458 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x33333555, 0x33333332, 0x667, x3, 1460, x4)
+
+inst_380:
+// rs1_val==858993458 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x33333006, 0x33333332, 0x334, x3, 1464, x4)
+
+inst_381:
+// rs1_val==858993458 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x33333334, 0x33333332, 0x6, x3, 1468, x4)
+
+inst_382:
+// rs1_val==858993458 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xccccc999, 0x33333332, -0x555, x3, 1472, x4)
+
+inst_383:
+// rs1_val==858993458 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x33333664, 0x33333332, 0x556, x3, 1476, x4)
+
+inst_384:
+// rs1_val==858993458 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x33333336, 0x33333332, 0x4, x3, 1480, x4)
+
+inst_385:
+// rs1_val==858993458 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x3333331e, 0x33333332, 0x2c, x3, 1484, x4)
+
+inst_386:
+// rs1_val==858993458 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x33333332, 0x33333332, 0x0, x3, 1488, x4)
+
+inst_387:
+// rs1_val==858993458 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x33333557, 0x33333332, 0x665, x3, 1492, x4)
+
+inst_388:
+// rs1_val==858993458 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x33333000, 0x33333332, 0x332, x3, 1496, x4)
+
+inst_389:
+// rs1_val==858993458 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x33333666, 0x33333332, 0x554, x3, 1500, x4)
+
+inst_390:
+// rs1_val==858993458 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x33333330, 0x33333332, 0x2, x3, 1504, x4)
+
+inst_391:
+// rs1_val==858993458 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x3333331f, 0x33333332, 0x2d, x3, 1508, x4)
+
+inst_392:
+// rs1_val==858993458 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xcccccce1, 0x33333332, -0x2d, x3, 1512, x4)
+
+inst_393:
+// rs1_val==858993458 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x33333554, 0x33333332, 0x666, x3, 1516, x4)
+
+inst_394:
+// rs1_val==858993458 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x33333001, 0x33333332, 0x333, x3, 1520, x4)
+
+inst_395:
+// rs1_val==858993458 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x33333337, 0x33333332, 0x5, x3, 1524, x4)
+
+inst_396:
+// rs1_val==858993458 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xccccc998, 0x33333332, -0x556, x3, 1528, x4)
+
+inst_397:
+// rs1_val==858993458 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x33333667, 0x33333332, 0x555, x3, 1532, x4)
+
+inst_398:
+// rs1_val==858993458 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333332;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x33333331, 0x33333332, 0x3, x3, 1536, x4)
+
+inst_399:
+// rs1_val==1431655764 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x5555557a, 0x55555554, 0x2e, x3, 1540, x4)
+
+inst_400:
+// rs1_val==1431655764 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa80, 0x55555554, -0x2c, x3, 1544, x4)
+
+inst_401:
+// rs1_val==1431655764 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x55555333, 0x55555554, 0x667, x3, 1548, x4)
+
+inst_402:
+// rs1_val==1431655764 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x55555660, 0x55555554, 0x334, x3, 1552, x4)
+
+inst_403:
+// rs1_val==1431655764 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x55555552, 0x55555554, 0x6, x3, 1556, x4)
+
+inst_404:
+// rs1_val==1431655764 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xaaaaafff, 0x55555554, -0x555, x3, 1560, x4)
+
+inst_405:
+// rs1_val==1431655764 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x55555002, 0x55555554, 0x556, x3, 1564, x4)
+
+inst_406:
+// rs1_val==1431655764 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x55555550, 0x55555554, 0x4, x3, 1568, x4)
+
+inst_407:
+// rs1_val==1431655764 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x55555578, 0x55555554, 0x2c, x3, 1572, x4)
+
+inst_408:
+// rs1_val==1431655764 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x55555554, 0x55555554, 0x0, x3, 1576, x4)
+
+inst_409:
+// rs1_val==1431655764 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x55555331, 0x55555554, 0x665, x3, 1580, x4)
+
+inst_410:
+// rs1_val==1431655764 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x55555666, 0x55555554, 0x332, x3, 1584, x4)
+
+inst_411:
+// rs1_val==1431655764 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x55555000, 0x55555554, 0x554, x3, 1588, x4)
+
+inst_412:
+// rs1_val==1431655764 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x55555556, 0x55555554, 0x2, x3, 1592, x4)
+
+inst_413:
+// rs1_val==1431655764 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x55555579, 0x55555554, 0x2d, x3, 1596, x4)
+
+inst_414:
+// rs1_val==1431655764 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa87, 0x55555554, -0x2d, x3, 1600, x4)
+
+inst_415:
+// rs1_val==1431655764 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x55555332, 0x55555554, 0x666, x3, 1604, x4)
+
+inst_416:
+// rs1_val==1431655764 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x55555667, 0x55555554, 0x333, x3, 1608, x4)
+
+inst_417:
+// rs1_val==1431655764 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x55555551, 0x55555554, 0x5, x3, 1612, x4)
+
+inst_418:
+// rs1_val==1431655764 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaffe, 0x55555554, -0x556, x3, 1616, x4)
+
+inst_419:
+// rs1_val==1431655764 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x55555001, 0x55555554, 0x555, x3, 1620, x4)
+
+inst_420:
+// rs1_val==1431655764 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x55555554;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x55555557, 0x55555554, 0x3, x3, 1624, x4)
+
+inst_421:
+// rs1_val==2 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x2c, 0x2, 0x2e, x3, 1628, x4)
+
+inst_422:
+// rs1_val==2 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd6, 0x2, -0x2c, x3, 1632, x4)
+
+inst_423:
+// rs1_val==2 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x665, 0x2, 0x667, x3, 1636, x4)
+
+inst_424:
+// rs1_val==2 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x336, 0x2, 0x334, x3, 1640, x4)
+
+inst_425:
+// rs1_val==2 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x4, 0x2, 0x6, x3, 1644, x4)
+
+inst_426:
+// rs1_val==2 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaa9, 0x2, -0x555, x3, 1648, x4)
+
+inst_427:
+// rs1_val==2 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x554, 0x2, 0x556, x3, 1652, x4)
+
+inst_428:
+// rs1_val==2 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x2, 0x4, x3, 1656, x4)
+
+inst_429:
+// rs1_val==2 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x2e, 0x2, 0x2c, x3, 1660, x4)
+
+inst_430:
+// rs1_val==2 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x2, 0x2, 0x0, x3, 1664, x4)
+
+inst_431:
+// rs1_val==2 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x667, 0x2, 0x665, x3, 1668, x4)
+
+inst_432:
+// rs1_val==2 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x330, 0x2, 0x332, x3, 1672, x4)
+
+inst_433:
+// rs1_val==2 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x2, 0x2, x3, 1676, x4)
+
+inst_434:
+// rs1_val==2 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x2f, 0x2, 0x2d, x3, 1680, x4)
+
+inst_435:
+// rs1_val==2 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd1, 0x2, -0x2d, x3, 1684, x4)
+
+inst_436:
+// rs1_val==2 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x664, 0x2, 0x666, x3, 1688, x4)
+
+inst_437:
+// rs1_val==2 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x331, 0x2, 0x333, x3, 1692, x4)
+
+inst_438:
+// rs1_val==2 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x7, 0x2, 0x5, x3, 1696, x4)
+
+inst_439:
+// rs1_val==2 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaa8, 0x2, -0x556, x3, 1700, x4)
+
+inst_440:
+// rs1_val==2 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x557, 0x2, 0x555, x3, 1704, x4)
+
+inst_441:
+// rs1_val==2 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x2;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x1, 0x2, 0x3, x3, 1708, x4)
+
+inst_442:
+// rs1_val==46340 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xb52a, 0xb504, 0x2e, x3, 1712, x4)
+
+inst_443:
+// rs1_val==46340 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad0, 0xb504, -0x2c, x3, 1716, x4)
+
+inst_444:
+// rs1_val==46340 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xb363, 0xb504, 0x667, x3, 1720, x4)
+
+inst_445:
+// rs1_val==46340 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xb630, 0xb504, 0x334, x3, 1724, x4)
+
+inst_446:
+// rs1_val==46340 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xb502, 0xb504, 0x6, x3, 1728, x4)
+
+inst_447:
+// rs1_val==46340 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xffff4faf, 0xb504, -0x555, x3, 1732, x4)
+
+inst_448:
+// rs1_val==46340 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xb052, 0xb504, 0x556, x3, 1736, x4)
+
+inst_449:
+// rs1_val==46340 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xb500, 0xb504, 0x4, x3, 1740, x4)
+
+inst_450:
+// rs1_val==46340 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xb528, 0xb504, 0x2c, x3, 1744, x4)
+
+inst_451:
+// rs1_val==46340 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xb504, 0xb504, 0x0, x3, 1748, x4)
+
+inst_452:
+// rs1_val==46340 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xb361, 0xb504, 0x665, x3, 1752, x4)
+
+inst_453:
+// rs1_val==46340 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xb636, 0xb504, 0x332, x3, 1756, x4)
+
+inst_454:
+// rs1_val==46340 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xb050, 0xb504, 0x554, x3, 1760, x4)
+
+inst_455:
+// rs1_val==46340 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xb506, 0xb504, 0x2, x3, 1764, x4)
+
+inst_456:
+// rs1_val==46340 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xb529, 0xb504, 0x2d, x3, 1768, x4)
+
+inst_457:
+// rs1_val==46340 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad7, 0xb504, -0x2d, x3, 1772, x4)
+
+inst_458:
+// rs1_val==46340 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xb362, 0xb504, 0x666, x3, 1776, x4)
+
+inst_459:
+// rs1_val==46340 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xb637, 0xb504, 0x333, x3, 1780, x4)
+
+inst_460:
+// rs1_val==46340 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xb501, 0xb504, 0x5, x3, 1784, x4)
+
+inst_461:
+// rs1_val==46340 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xffff4fae, 0xb504, -0x556, x3, 1788, x4)
+
+inst_462:
+// rs1_val==46340 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xb051, 0xb504, 0x555, x3, 1792, x4)
+
+inst_463:
+// rs1_val==46340 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0xb504;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xb507, 0xb504, 0x3, x3, 1796, x4)
+
+inst_464:
+// rs1_val==-46340 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad2, -0xb504, 0x2e, x3, 1800, x4)
+
+inst_465:
+// rs1_val==-46340 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xb528, -0xb504, -0x2c, x3, 1804, x4)
+
+inst_466:
+// rs1_val==-46340 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xffff4c9b, -0xb504, 0x667, x3, 1808, x4)
+
+inst_467:
+// rs1_val==-46340 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xffff49c8, -0xb504, 0x334, x3, 1812, x4)
+
+inst_468:
+// rs1_val==-46340 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xffff4afa, -0xb504, 0x6, x3, 1816, x4)
+
+inst_469:
+// rs1_val==-46340 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xb057, -0xb504, -0x555, x3, 1820, x4)
+
+inst_470:
+// rs1_val==-46340 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0xffff4faa, -0xb504, 0x556, x3, 1824, x4)
+
+inst_471:
+// rs1_val==-46340 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0xffff4af8, -0xb504, 0x4, x3, 1828, x4)
+
+inst_472:
+// rs1_val==-46340 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad0, -0xb504, 0x2c, x3, 1832, x4)
+
+inst_473:
+// rs1_val==-46340 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xffff4afc, -0xb504, 0x0, x3, 1836, x4)
+
+inst_474:
+// rs1_val==-46340 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0xffff4c99, -0xb504, 0x665, x3, 1840, x4)
+
+inst_475:
+// rs1_val==-46340 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0xffff49ce, -0xb504, 0x332, x3, 1844, x4)
+
+inst_476:
+// rs1_val==-46340 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa8, -0xb504, 0x554, x3, 1848, x4)
+
+inst_477:
+// rs1_val==-46340 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0xffff4afe, -0xb504, 0x2, x3, 1852, x4)
+
+inst_478:
+// rs1_val==-46340 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffff4ad1, -0xb504, 0x2d, x3, 1856, x4)
+
+inst_479:
+// rs1_val==-46340 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xb52f, -0xb504, -0x2d, x3, 1860, x4)
+
+inst_480:
+// rs1_val==-46340 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0xffff4c9a, -0xb504, 0x666, x3, 1864, x4)
+
+inst_481:
+// rs1_val==-46340 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0xffff49cf, -0xb504, 0x333, x3, 1868, x4)
+
+inst_482:
+// rs1_val==-46340 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0xffff4af9, -0xb504, 0x5, x3, 1872, x4)
+
+inst_483:
+// rs1_val==-46340 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xb056, -0xb504, -0x556, x3, 1876, x4)
+
+inst_484:
+// rs1_val==-46340 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0xffff4fa9, -0xb504, 0x555, x3, 1880, x4)
+
+inst_485:
+// rs1_val==-46340 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0xb504;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0xffff4aff, -0xb504, 0x3, x3, 1884, x4)
+
+inst_486:
+// rs1_val==1717986918 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x66666648, 0x66666666, 0x2e, x3, 1888, x4)
+
+inst_487:
+// rs1_val==1717986918 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0x999999b2, 0x66666666, -0x2c, x3, 1892, x4)
+
+inst_488:
+// rs1_val==1717986918 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x66666001, 0x66666666, 0x667, x3, 1896, x4)
+
+inst_489:
+// rs1_val==1717986918 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x66666552, 0x66666666, 0x334, x3, 1900, x4)
+
+inst_490:
+// rs1_val==1717986918 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x66666660, 0x66666666, 0x6, x3, 1904, x4)
+
+inst_491:
+// rs1_val==1717986918 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0x99999ccd, 0x66666666, -0x555, x3, 1908, x4)
+
+inst_492:
+// rs1_val==1717986918 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x66666330, 0x66666666, 0x556, x3, 1912, x4)
+
+inst_493:
+// rs1_val==1717986918 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x66666662, 0x66666666, 0x4, x3, 1916, x4)
+
+inst_494:
+// rs1_val==1717986918 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x6666664a, 0x66666666, 0x2c, x3, 1920, x4)
+
+inst_495:
+// rs1_val==1717986918 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x66666666, 0x66666666, 0x0, x3, 1924, x4)
+
+inst_496:
+// rs1_val==1717986918 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x66666003, 0x66666666, 0x665, x3, 1928, x4)
+
+inst_497:
+// rs1_val==1717986918 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x66666554, 0x66666666, 0x332, x3, 1932, x4)
+
+inst_498:
+// rs1_val==1717986918 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x66666332, 0x66666666, 0x554, x3, 1936, x4)
+
+inst_499:
+// rs1_val==1717986918 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x66666664, 0x66666666, 0x2, x3, 1940, x4)
+
+inst_500:
+// rs1_val==1717986918 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x6666664b, 0x66666666, 0x2d, x3, 1944, x4)
+
+inst_501:
+// rs1_val==1717986918 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0x999999b5, 0x66666666, -0x2d, x3, 1948, x4)
+
+inst_502:
+// rs1_val==1717986918 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x66666000, 0x66666666, 0x666, x3, 1952, x4)
+
+inst_503:
+// rs1_val==1717986918 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x66666555, 0x66666666, 0x333, x3, 1956, x4)
+
+inst_504:
+// rs1_val==1717986918 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x66666663, 0x66666666, 0x5, x3, 1960, x4)
+
+inst_505:
+// rs1_val==1717986918 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0x99999ccc, 0x66666666, -0x556, x3, 1964, x4)
+
+inst_506:
+// rs1_val==1717986918 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x66666333, 0x66666666, 0x555, x3, 1968, x4)
+
+inst_507:
+// rs1_val==1717986918 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x66666666;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x66666665, 0x66666666, 0x3, x3, 1972, x4)
+
+inst_508:
+// rs1_val==858993459 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x3333331d, 0x33333333, 0x2e, x3, 1976, x4)
+
+inst_509:
+// rs1_val==858993459 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xcccccce7, 0x33333333, -0x2c, x3, 1980, x4)
+
+inst_510:
+// rs1_val==858993459 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x33333554, 0x33333333, 0x667, x3, 1984, x4)
+
+inst_511:
+// rs1_val==858993459 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x33333007, 0x33333333, 0x334, x3, 1988, x4)
+
+inst_512:
+// rs1_val==858993459 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x33333335, 0x33333333, 0x6, x3, 1992, x4)
+
+inst_513:
+// rs1_val==858993459 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xccccc998, 0x33333333, -0x555, x3, 1996, x4)
+
+inst_514:
+// rs1_val==858993459 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x33333665, 0x33333333, 0x556, x3, 2000, x4)
+
+inst_515:
+// rs1_val==858993459 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x33333337, 0x33333333, 0x4, x3, 2004, x4)
+
+inst_516:
+// rs1_val==858993459 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x3333331f, 0x33333333, 0x2c, x3, 2008, x4)
+
+inst_517:
+// rs1_val==858993459 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x33333333, 0x33333333, 0x0, x3, 2012, x4)
+
+inst_518:
+// rs1_val==858993459 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x33333556, 0x33333333, 0x665, x3, 2016, x4)
+
+inst_519:
+// rs1_val==858993459 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x33333001, 0x33333333, 0x332, x3, 2020, x4)
+
+inst_520:
+// rs1_val==858993459 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x33333667, 0x33333333, 0x554, x3, 2024, x4)
+
+inst_521:
+// rs1_val==858993459 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x33333331, 0x33333333, 0x2, x3, 2028, x4)
+
+inst_522:
+// rs1_val==858993459 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x3333331e, 0x33333333, 0x2d, x3, 2032, x4)
+
+inst_523:
+// rs1_val==858993459 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xcccccce0, 0x33333333, -0x2d, x3, 2036, x4)
+
+inst_524:
+// rs1_val==858993459 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x33333555, 0x33333333, 0x666, x3, 2040, x4)
+
+inst_525:
+// rs1_val==858993459 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x33333000, 0x33333333, 0x333, x3, 2044, x4)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_526:
+// rs1_val==858993459 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x33333336, 0x33333333, 0x5, x3, 0, x4)
+
+inst_527:
+// rs1_val==858993459 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xccccc999, 0x33333333, -0x556, x3, 4, x4)
+
+inst_528:
+// rs1_val==858993459 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x33333666, 0x33333333, 0x555, x3, 8, x4)
+
+inst_529:
+// rs1_val==858993459 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x33333333;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x33333330, 0x33333333, 0x3, x3, 12, x4)
+
+inst_530:
+// rs1_val==5 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0x2b, 0x5, 0x2e, x3, 16, x4)
+
+inst_531:
+// rs1_val==5 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0xffffffd1, 0x5, -0x2c, x3, 20, x4)
+
+inst_532:
+// rs1_val==5 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0x662, 0x5, 0x667, x3, 24, x4)
+
+inst_533:
+// rs1_val==5 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0x331, 0x5, 0x334, x3, 28, x4)
+
+inst_534:
+// rs1_val==5 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0x3, 0x5, 0x6, x3, 32, x4)
+
+inst_535:
+// rs1_val==5 and imm_val==-1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x555
+TEST_IMM_OP( xori, x11, x10, 0xfffffaae, 0x5, -0x555, x3, 36, x4)
+
+inst_536:
+// rs1_val==5 and imm_val==1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x556
+TEST_IMM_OP( xori, x11, x10, 0x553, 0x5, 0x556, x3, 40, x4)
+
+inst_537:
+// rs1_val==5 and imm_val==4, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x4
+TEST_IMM_OP( xori, x11, x10, 0x1, 0x5, 0x4, x3, 44, x4)
+
+inst_538:
+// rs1_val==5 and imm_val==44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2c
+TEST_IMM_OP( xori, x11, x10, 0x29, 0x5, 0x2c, x3, 48, x4)
+
+inst_539:
+// rs1_val==5 and imm_val==0, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0x5, 0x5, 0x0, x3, 52, x4)
+
+inst_540:
+// rs1_val==5 and imm_val==1637, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x665
+TEST_IMM_OP( xori, x11, x10, 0x660, 0x5, 0x665, x3, 56, x4)
+
+inst_541:
+// rs1_val==5 and imm_val==818, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x332
+TEST_IMM_OP( xori, x11, x10, 0x337, 0x5, 0x332, x3, 60, x4)
+
+inst_542:
+// rs1_val==5 and imm_val==1364, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x554
+TEST_IMM_OP( xori, x11, x10, 0x551, 0x5, 0x554, x3, 64, x4)
+
+inst_543:
+// rs1_val==5 and imm_val==2, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2
+TEST_IMM_OP( xori, x11, x10, 0x7, 0x5, 0x2, x3, 68, x4)
+
+inst_544:
+// rs1_val==5 and imm_val==45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x2d
+TEST_IMM_OP( xori, x11, x10, 0x28, 0x5, 0x2d, x3, 72, x4)
+
+inst_545:
+// rs1_val==5 and imm_val==-45, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x2d
+TEST_IMM_OP( xori, x11, x10, 0xffffffd6, 0x5, -0x2d, x3, 76, x4)
+
+inst_546:
+// rs1_val==5 and imm_val==1638, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x666
+TEST_IMM_OP( xori, x11, x10, 0x663, 0x5, 0x666, x3, 80, x4)
+
+inst_547:
+// rs1_val==5 and imm_val==819, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x333
+TEST_IMM_OP( xori, x11, x10, 0x336, 0x5, 0x333, x3, 84, x4)
+
+inst_548:
+// rs1_val==5 and imm_val==5, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x5
+TEST_IMM_OP( xori, x11, x10, 0x0, 0x5, 0x5, x3, 88, x4)
+
+inst_549:
+// rs1_val==5 and imm_val==-1366, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:-0x556
+TEST_IMM_OP( xori, x11, x10, 0xfffffaaf, 0x5, -0x556, x3, 92, x4)
+
+inst_550:
+// rs1_val==5 and imm_val==1365, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x555
+TEST_IMM_OP( xori, x11, x10, 0x550, 0x5, 0x555, x3, 96, x4)
+
+inst_551:
+// rs1_val==5 and imm_val==3, 
+// opcode: xori ; op1:x10; dest:x11; op1val:0x5;  immval:0x3
+TEST_IMM_OP( xori, x11, x10, 0x6, 0x5, 0x3, x3, 100, x4)
+
+inst_552:
+// rs1_val==-1431655766 and imm_val==46, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x2e
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaa84, -0x55555556, 0x2e, x3, 104, x4)
+
+inst_553:
+// rs1_val==-1431655766 and imm_val==-44, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:-0x2c
+TEST_IMM_OP( xori, x11, x10, 0x5555557e, -0x55555556, -0x2c, x3, 108, x4)
+
+inst_554:
+// rs1_val==-1431655766 and imm_val==1639, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x667
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaccd, -0x55555556, 0x667, x3, 112, x4)
+
+inst_555:
+// rs1_val==-1431655766 and imm_val==820, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x334
+TEST_IMM_OP( xori, x11, x10, 0xaaaaa99e, -0x55555556, 0x334, x3, 116, x4)
+
+inst_556:
+// rs1_val==-1431655766 and imm_val==6, 
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x55555556;  immval:0x6
+TEST_IMM_OP( xori, x11, x10, 0xaaaaaaac, -0x55555556, 0x6, x3, 120, x4)
+
+inst_557:
+// rs1_val == -65537, imm_val == 512
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x10001;  immval:0x200
+TEST_IMM_OP( xori, x11, x10, 0xfffefdff, -0x10001, 0x200, x3, 124, x4)
+
+inst_558:
+// rs1_val == -32769, imm_val == 0
+// opcode: xori ; op1:x10; dest:x11; op1val:-0x8001;  immval:0x0
+TEST_IMM_OP( xori, x11, x10, 0xffff7fff, -0x8001, 0x0, x3, 128, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_0:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 512*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 33*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
new file mode 100644
index 000000000..9b6561514
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
@@ -0,0 +1,138 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.906970//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
+
+# Testcase 0:  rs1:x28(0x00000000), rs2:x13(0x00000000), result rd:x25(0x00000000)
+li x28, MASK_XLEN(0x00000000)
+li x13, MASK_XLEN(0x00000000)
+ADD x25, x28, x13
+sw x25, 0(x6)
+
+# Testcase 1:  rs1:x29(0x00000000), rs2:x14(0x00000001), result rd:x2(0x00000001)
+li x29, MASK_XLEN(0x00000000)
+li x14, MASK_XLEN(0x00000001)
+ADD x2, x29, x14
+sw x2, 4(x6)
+
+# Testcase 2:  rs1:x9(0x00000000), rs2:x31(0xffffffff), result rd:x17(0xffffffff)
+li x9, MASK_XLEN(0x00000000)
+li x31, MASK_XLEN(0xffffffff)
+ADD x17, x9, x31
+sw x17, 8(x6)
+
+# Testcase 3:  rs1:x16(0x00000001), rs2:x13(0x00000000), result rd:x30(0x00000001)
+li x16, MASK_XLEN(0x00000001)
+li x13, MASK_XLEN(0x00000000)
+ADD x30, x16, x13
+sw x30, 12(x6)
+
+# Testcase 4:  rs1:x26(0x00000001), rs2:x27(0x00000001), result rd:x10(0x00000002)
+li x26, MASK_XLEN(0x00000001)
+li x27, MASK_XLEN(0x00000001)
+ADD x10, x26, x27
+sw x10, 16(x6)
+
+# Testcase 5:  rs1:x31(0x00000001), rs2:x16(0xffffffff), result rd:x12(0x00000000)
+li x31, MASK_XLEN(0x00000001)
+li x16, MASK_XLEN(0xffffffff)
+ADD x12, x31, x16
+sw x12, 20(x6)
+
+# Testcase 6:  rs1:x19(0xffffffff), rs2:x29(0x00000000), result rd:x30(0xffffffff)
+li x19, MASK_XLEN(0xffffffff)
+li x29, MASK_XLEN(0x00000000)
+ADD x30, x19, x29
+sw x30, 24(x6)
+
+# Testcase 7:  rs1:x7(0xffffffff), rs2:x17(0x00000001), result rd:x5(0x00000000)
+li x7, MASK_XLEN(0xffffffff)
+li x17, MASK_XLEN(0x00000001)
+ADD x5, x7, x17
+sw x5, 28(x6)
+
+# Testcase 8:  rs1:x10(0xffffffff), rs2:x5(0xffffffff), result rd:x25(0xfffffffe)
+li x10, MASK_XLEN(0xffffffff)
+li x5, MASK_XLEN(0xffffffff)
+ADD x25, x10, x5
+sw x25, 32(x6)
+
+# Testcase 9:  rs1:x26(0x1846d424), rs2:x9(0x9e4d6e3c), result rd:x30(0xb6944260)
+li x26, MASK_XLEN(0x1846d424)
+li x9, MASK_XLEN(0x9e4d6e3c)
+ADD x30, x26, x9
+sw x30, 36(x6)
+
+# Testcase 10:  rs1:x23(0x88561712), rs2:x26(0xfb97d435), result rd:x20(0x83edeb47)
+li x23, MASK_XLEN(0x88561712)
+li x26, MASK_XLEN(0xfb97d435)
+ADD x20, x23, x26
+sw x20, 40(x6)
+
+# Testcase 11:  rs1:x10(0xe6f4590b), rs2:x4(0x259f4329), result rd:x24(0x0c939c34)
+li x10, MASK_XLEN(0xe6f4590b)
+li x4, MASK_XLEN(0x259f4329)
+ADD x24, x10, x4
+sw x24, 44(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
new file mode 100644
index 000000000..10e5bc509
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.909889//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
+
+# Testcase 0:  rs1:x11(0x00000000), rs2:x8(0x00000000), result rd:x24(0x00000000)
+li x11, MASK_XLEN(0x00000000)
+li x8, MASK_XLEN(0x00000000)
+SLT x24, x11, x8
+sw x24, 0(x6)
+
+# Testcase 1:  rs1:x11(0x00000000), rs2:x23(0x00000001), result rd:x28(0x00000001)
+li x11, MASK_XLEN(0x00000000)
+li x23, MASK_XLEN(0x00000001)
+SLT x28, x11, x23
+sw x28, 4(x6)
+
+# Testcase 2:  rs1:x3(0x00000000), rs2:x7(0xffffffff), result rd:x30(0x00000000)
+li x3, MASK_XLEN(0x00000000)
+li x7, MASK_XLEN(0xffffffff)
+SLT x30, x3, x7
+sw x30, 8(x6)
+
+# Testcase 3:  rs1:x19(0x00000001), rs2:x8(0x00000000), result rd:x8(0x00000000)
+li x19, MASK_XLEN(0x00000001)
+li x8, MASK_XLEN(0x00000000)
+SLT x8, x19, x8
+sw x8, 12(x6)
+
+# Testcase 4:  rs1:x26(0x00000001), rs2:x31(0x00000001), result rd:x5(0x00000000)
+li x26, MASK_XLEN(0x00000001)
+li x31, MASK_XLEN(0x00000001)
+SLT x5, x26, x31
+sw x5, 16(x6)
+
+# Testcase 5:  rs1:x26(0x00000001), rs2:x18(0xffffffff), result rd:x15(0x00000000)
+li x26, MASK_XLEN(0x00000001)
+li x18, MASK_XLEN(0xffffffff)
+SLT x15, x26, x18
+sw x15, 20(x6)
+
+# Testcase 6:  rs1:x29(0xffffffff), rs2:x17(0x00000000), result rd:x30(0x00000001)
+li x29, MASK_XLEN(0xffffffff)
+li x17, MASK_XLEN(0x00000000)
+SLT x30, x29, x17
+sw x30, 24(x6)
+
+# Testcase 7:  rs1:x16(0xffffffff), rs2:x4(0x00000001), result rd:x10(0x00000001)
+li x16, MASK_XLEN(0xffffffff)
+li x4, MASK_XLEN(0x00000001)
+SLT x10, x16, x4
+sw x10, 28(x6)
+
+# Testcase 8:  rs1:x18(0xffffffff), rs2:x10(0xffffffff), result rd:x23(0x00000000)
+li x18, MASK_XLEN(0xffffffff)
+li x10, MASK_XLEN(0xffffffff)
+SLT x23, x18, x10
+sw x23, 32(x6)
+
+# Testcase 9:  rs1:x11(0x1ff39849), rs2:x27(0x8c25166a), result rd:x30(0x00000000)
+li x11, MASK_XLEN(0x1ff39849)
+li x27, MASK_XLEN(0x8c25166a)
+SLT x30, x11, x27
+sw x30, 36(x6)
+
+# Testcase 10:  rs1:x31(0x8a5006c1), rs2:x26(0x3405095c), result rd:x20(0x00000001)
+li x31, MASK_XLEN(0x8a5006c1)
+li x26, MASK_XLEN(0x3405095c)
+SLT x20, x31, x26
+sw x20, 40(x6)
+
+# Testcase 11:  rs1:x10(0x8c1745a7), rs2:x15(0x966e1277), result rd:x3(0x00000001)
+li x10, MASK_XLEN(0x8c1745a7)
+li x15, MASK_XLEN(0x966e1277)
+SLT x3, x10, x15
+sw x3, 44(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
new file mode 100644
index 000000000..aa080daf9
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.911056//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
+
+# Testcase 0:  rs1:x20(0x00000000), rs2:x26(0x00000000), result rd:x13(0x00000000)
+li x20, MASK_XLEN(0x00000000)
+li x26, MASK_XLEN(0x00000000)
+SLTU x13, x20, x26
+sw x13, 0(x6)
+
+# Testcase 1:  rs1:x11(0x00000000), rs2:x19(0x00000001), result rd:x8(0x00000001)
+li x11, MASK_XLEN(0x00000000)
+li x19, MASK_XLEN(0x00000001)
+SLTU x8, x11, x19
+sw x8, 4(x6)
+
+# Testcase 2:  rs1:x20(0x00000000), rs2:x22(0xffffffff), result rd:x9(0x00000001)
+li x20, MASK_XLEN(0x00000000)
+li x22, MASK_XLEN(0xffffffff)
+SLTU x9, x20, x22
+sw x9, 8(x6)
+
+# Testcase 3:  rs1:x16(0x00000001), rs2:x3(0x00000000), result rd:x3(0x00000000)
+li x16, MASK_XLEN(0x00000001)
+li x3, MASK_XLEN(0x00000000)
+SLTU x3, x16, x3
+sw x3, 12(x6)
+
+# Testcase 4:  rs1:x22(0x00000001), rs2:x25(0x00000001), result rd:x5(0x00000000)
+li x22, MASK_XLEN(0x00000001)
+li x25, MASK_XLEN(0x00000001)
+SLTU x5, x22, x25
+sw x5, 16(x6)
+
+# Testcase 5:  rs1:x29(0x00000001), rs2:x5(0xffffffff), result rd:x30(0x00000001)
+li x29, MASK_XLEN(0x00000001)
+li x5, MASK_XLEN(0xffffffff)
+SLTU x30, x29, x5
+sw x30, 20(x6)
+
+# Testcase 6:  rs1:x2(0xffffffff), rs2:x27(0x00000000), result rd:x3(0x00000000)
+li x2, MASK_XLEN(0xffffffff)
+li x27, MASK_XLEN(0x00000000)
+SLTU x3, x2, x27
+sw x3, 24(x6)
+
+# Testcase 7:  rs1:x29(0xffffffff), rs2:x23(0x00000001), result rd:x30(0x00000000)
+li x29, MASK_XLEN(0xffffffff)
+li x23, MASK_XLEN(0x00000001)
+SLTU x30, x29, x23
+sw x30, 28(x6)
+
+# Testcase 8:  rs1:x27(0xffffffff), rs2:x18(0xffffffff), result rd:x22(0x00000000)
+li x27, MASK_XLEN(0xffffffff)
+li x18, MASK_XLEN(0xffffffff)
+SLTU x22, x27, x18
+sw x22, 32(x6)
+
+# Testcase 9:  rs1:x23(0x642bfa42), rs2:x17(0xd67e55fd), result rd:x9(0x00000001)
+li x23, MASK_XLEN(0x642bfa42)
+li x17, MASK_XLEN(0xd67e55fd)
+SLTU x9, x23, x17
+sw x9, 36(x6)
+
+# Testcase 10:  rs1:x8(0x85940927), rs2:x28(0xcfc6e625), result rd:x7(0x00000001)
+li x8, MASK_XLEN(0x85940927)
+li x28, MASK_XLEN(0xcfc6e625)
+SLTU x7, x8, x28
+sw x7, 40(x6)
+
+# Testcase 11:  rs1:x19(0xe5214606), rs2:x27(0xadf20806), result rd:x31(0x00000000)
+li x19, MASK_XLEN(0xe5214606)
+li x27, MASK_XLEN(0xadf20806)
+SLTU x31, x19, x27
+sw x31, 44(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
new file mode 100644
index 000000000..b7f5fa299
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.908718//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+# Testcase 0:  rs1:x3(0x00000000), rs2:x29(0x00000000), result rd:x28(0x00000000)
+li x3, MASK_XLEN(0x00000000)
+li x29, MASK_XLEN(0x00000000)
+SUB x28, x3, x29
+sw x28, 0(x6)
+
+# Testcase 1:  rs1:x22(0x00000000), rs2:x11(0x00000001), result rd:x16(0xffffffff)
+li x22, MASK_XLEN(0x00000000)
+li x11, MASK_XLEN(0x00000001)
+SUB x16, x22, x11
+sw x16, 4(x6)
+
+# Testcase 2:  rs1:x18(0x00000000), rs2:x4(0xffffffff), result rd:x12(0x00000001)
+li x18, MASK_XLEN(0x00000000)
+li x4, MASK_XLEN(0xffffffff)
+SUB x12, x18, x4
+sw x12, 8(x6)
+
+# Testcase 3:  rs1:x14(0x00000001), rs2:x11(0x00000000), result rd:x20(0x00000001)
+li x14, MASK_XLEN(0x00000001)
+li x11, MASK_XLEN(0x00000000)
+SUB x20, x14, x11
+sw x20, 12(x6)
+
+# Testcase 4:  rs1:x21(0x00000001), rs2:x30(0x00000001), result rd:x7(0x00000000)
+li x21, MASK_XLEN(0x00000001)
+li x30, MASK_XLEN(0x00000001)
+SUB x7, x21, x30
+sw x7, 16(x6)
+
+# Testcase 5:  rs1:x31(0x00000001), rs2:x18(0xffffffff), result rd:x16(0x00000002)
+li x31, MASK_XLEN(0x00000001)
+li x18, MASK_XLEN(0xffffffff)
+SUB x16, x31, x18
+sw x16, 20(x6)
+
+# Testcase 6:  rs1:x15(0xffffffff), rs2:x28(0x00000000), result rd:x17(0xffffffff)
+li x15, MASK_XLEN(0xffffffff)
+li x28, MASK_XLEN(0x00000000)
+SUB x17, x15, x28
+sw x17, 24(x6)
+
+# Testcase 7:  rs1:x9(0xffffffff), rs2:x2(0x00000001), result rd:x26(0xfffffffe)
+li x9, MASK_XLEN(0xffffffff)
+li x2, MASK_XLEN(0x00000001)
+SUB x26, x9, x2
+sw x26, 28(x6)
+
+# Testcase 8:  rs1:x30(0xffffffff), rs2:x18(0xffffffff), result rd:x30(0x00000000)
+li x30, MASK_XLEN(0xffffffff)
+li x18, MASK_XLEN(0xffffffff)
+SUB x30, x30, x18
+sw x30, 32(x6)
+
+# Testcase 9:  rs1:x24(0x03983ca8), rs2:x27(0x17e0aa3c), result rd:x13(0xebb7926c)
+li x24, MASK_XLEN(0x03983ca8)
+li x27, MASK_XLEN(0x17e0aa3c)
+SUB x13, x24, x27
+sw x13, 36(x6)
+
+# Testcase 10:  rs1:x26(0xb5d32b16), rs2:x22(0xd3290a4c), result rd:x21(0xe2aa20ca)
+li x26, MASK_XLEN(0xb5d32b16)
+li x22, MASK_XLEN(0xd3290a4c)
+SUB x21, x26, x22
+sw x21, 40(x6)
+
+# Testcase 11:  rs1:x16(0x004ae545), rs2:x27(0x9ca5499d), result rd:x28(0x63a59ba8)
+li x16, MASK_XLEN(0x004ae545)
+li x27, MASK_XLEN(0x9ca5499d)
+SUB x28, x16, x27
+sw x28, 44(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
new file mode 100644
index 000000000..ea658637d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.913218//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
+
+# Testcase 0:  rs1:x14(0x00000000), rs2:x19(0x00000000), result rd:x9(0x00000000)
+li x14, MASK_XLEN(0x00000000)
+li x19, MASK_XLEN(0x00000000)
+XOR x9, x14, x19
+sw x9, 0(x6)
+
+# Testcase 1:  rs1:x15(0x00000000), rs2:x16(0x00000001), result rd:x22(0x00000001)
+li x15, MASK_XLEN(0x00000000)
+li x16, MASK_XLEN(0x00000001)
+XOR x22, x15, x16
+sw x22, 4(x6)
+
+# Testcase 2:  rs1:x21(0x00000000), rs2:x23(0xffffffff), result rd:x30(0xffffffff)
+li x21, MASK_XLEN(0x00000000)
+li x23, MASK_XLEN(0xffffffff)
+XOR x30, x21, x23
+sw x30, 8(x6)
+
+# Testcase 3:  rs1:x26(0x00000001), rs2:x12(0x00000000), result rd:x3(0x00000001)
+li x26, MASK_XLEN(0x00000001)
+li x12, MASK_XLEN(0x00000000)
+XOR x3, x26, x12
+sw x3, 12(x6)
+
+# Testcase 4:  rs1:x11(0x00000001), rs2:x20(0x00000001), result rd:x4(0x00000000)
+li x11, MASK_XLEN(0x00000001)
+li x20, MASK_XLEN(0x00000001)
+XOR x4, x11, x20
+sw x4, 16(x6)
+
+# Testcase 5:  rs1:x16(0x00000001), rs2:x19(0xffffffff), result rd:x21(0xfffffffe)
+li x16, MASK_XLEN(0x00000001)
+li x19, MASK_XLEN(0xffffffff)
+XOR x21, x16, x19
+sw x21, 20(x6)
+
+# Testcase 6:  rs1:x11(0xffffffff), rs2:x28(0x00000000), result rd:x7(0xffffffff)
+li x11, MASK_XLEN(0xffffffff)
+li x28, MASK_XLEN(0x00000000)
+XOR x7, x11, x28
+sw x7, 24(x6)
+
+# Testcase 7:  rs1:x8(0xffffffff), rs2:x1(0x00000001), result rd:x24(0xfffffffe)
+li x8, MASK_XLEN(0xffffffff)
+li x1, MASK_XLEN(0x00000001)
+XOR x24, x8, x1
+sw x24, 28(x6)
+
+# Testcase 8:  rs1:x9(0xffffffff), rs2:x4(0xffffffff), result rd:x23(0x00000000)
+li x9, MASK_XLEN(0xffffffff)
+li x4, MASK_XLEN(0xffffffff)
+XOR x23, x9, x4
+sw x23, 32(x6)
+
+# Testcase 9:  rs1:x14(0x38701a14), rs2:x27(0x5f3f5638), result rd:x2(0x674f4c2c)
+li x14, MASK_XLEN(0x38701a14)
+li x27, MASK_XLEN(0x5f3f5638)
+XOR x2, x14, x27
+sw x2, 36(x6)
+
+# Testcase 10:  rs1:x5(0x19c16a0d), rs2:x28(0xc87a7463), result rd:x23(0xd1bb1e6e)
+li x5, MASK_XLEN(0x19c16a0d)
+li x28, MASK_XLEN(0xc87a7463)
+XOR x23, x5, x28
+sw x23, 40(x6)
+
+# Testcase 11:  rs1:x27(0x38018b47), rs2:x19(0x0b9475b1), result rd:x21(0x3395fef6)
+li x27, MASK_XLEN(0x38018b47)
+li x19, MASK_XLEN(0x0b9475b1)
+XOR x21, x27, x19
+sw x21, 44(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefile
new file mode 100644
index 000000000..b810d28c0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefile
@@ -0,0 +1,4 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32ib -mabi=ilp32 -DXLEN=$(XLEN)))
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefrag
new file mode 100644
index 000000000..31462ca2f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/K_unratified/Makefrag
@@ -0,0 +1,31 @@
+# RISC-V Compliance Test RV32K Makefrag
+#
+#
+# Copyright (c) 2021 Imperas Software Ltd., www.imperas.com
+# Copyright (c) 2021 Indian Institute of Technology Madras
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied.
+#
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#
+
+#
+# Description: Makefrag for RV32K compliance tests
+
+rv32k_sc_tests = \
+
+rv32k_tests = $(addsuffix .elf, $(rv32k_sc_tests))
+
+target_tests += $(rv32k_tests)
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile
new file mode 100644
index 000000000..17df4991f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32im -mabi=ilp32 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag
new file mode 100644
index 000000000..1426cad31
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/M/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV32IM Makefrag
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32IM architectural tests
+
+rv32im_sc_tests = \
+
+rv32im_tests = $(addsuffix .elf, $(rv32im_sc_tests))
+
+target_tests += $(rv32im_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefile
new file mode 100644
index 000000000..74d788175
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefrag
new file mode 100644
index 000000000..79d1bd169
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/Makefrag
@@ -0,0 +1,34 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile
new file mode 100644
index 000000000..0c60cf417
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile
@@ -0,0 +1,5 @@
+include ../../Makefile.include
+
+RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
+
+$(eval $(call compile_template,-march=rv32iaf -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
new file mode 100644
index 000000000..23806cf67
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
@@ -0,0 +1,64 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+    WALLY-mmu-sv32 \
+    WALLY-pmp \
+    WALLY-csr-permission-s-01 \
+    WALLY-csr-permission-u-01 \
+    WALLY-minfo-01 \
+    WALLY-misa-01 \
+    WALLY-amo \
+    WALLY-lrsc \
+    WALLY-status-mie-01 \
+    WALLY-trap-sret-01 \
+
+
+target_tests_nosim = \
+    WALLY-pma \
+    WALLY-mtvec-01 \
+    WALLY-stvec-01 \
+    WALLY-mie-01 \
+    WALLY-sie-01 \
+    WALLY-trap-01 \
+    WALLY-trap-s-01 \
+    WALLY-trap-u-01 \
+    WALLY-wfi-01 \
+    WALLY-status-fp-enabled-01 \
+    WALLY-status-sie-01 \
+    WALLY-status-tw-01 \
+    WALLY-gpio-01 \
+    WALLY-clint-01 \
+    WALLY-plic-01 \
+    WALLY-uart-01 \
+
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output
new file mode 100644
index 000000000..6d2c17395
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-amo-01.reference_output
@@ -0,0 +1,20 @@
+fffffffe
+00000001
+fffffffb
+fffffffd
+ffffffef
+000007ef
+ffffffbf
+ffffffff
+fffffeff
+fffffd7e
+fffffeff
+000007ff
+ffffefff
+ffffefff
+ffffefff
+ffffefff
+fffeffff
+000007fa
+ffffffff
+ffffffff
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output
deleted file mode 100644
index faf3bf658..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cbom-01.reference_output
+++ /dev/null
@@ -1,428 +0,0 @@
-deadbeef # begin_signature
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef  # destination 1
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-00000000  # destination 2
-00000001
-00000002
-00000003
-00000004
-00000005
-00000006
-00000007
-00000008
-00000009
-0000000a
-0000000b
-0000000c
-0000000d
-0000000e
-0000000f
-00000010
-00000011
-00000012
-00000013
-00000014
-00000015
-00000016
-00000017
-00000018
-00000019
-0000001a
-0000001b
-0000001c
-0000001d
-0000001e
-0000001f
-00000020
-00000021
-00000022
-00000023
-00000024
-00000025
-00000026
-00000027
-00000028
-00000029
-0000002a
-0000002b
-0000002c
-0000002d
-0000002e
-0000002f
-00000030
-00000031
-00000032
-00000033
-00000034
-00000035
-00000036
-00000037
-00000038
-00000039
-0000003a
-0000003b
-0000003c
-0000003d
-0000003e
-0000003f
-00000040
-00000041
-00000042
-00000043
-00000044
-00000045
-00000046
-00000047
-00000048
-00000049
-0000004a
-0000004b
-0000004c
-0000004d
-0000004e
-0000004f
-00000050
-00000051
-00000052
-00000053
-00000054
-00000055
-00000056
-00000057
-00000058
-00000059
-0000005a
-0000005b
-0000005c
-0000005d
-0000005e
-0000005f
-00000060
-00000061
-00000062
-00000063
-00000064
-00000065
-00000066
-00000067
-00000068
-00000069
-0000006a
-0000006b
-0000006c
-0000006d
-0000006e
-0000006f
-00000070
-00000071
-00000072
-00000073
-00000074
-00000075
-00000076
-00000077
-00000078
-00000079
-0000007a
-0000007b
-0000007c
-0000007d
-0000007e
-0000007f
-00000000  # destination 3
-00000001
-00000002
-00000003
-00000004
-00000005
-00000006
-00000007
-00000008
-00000009
-0000000a
-0000000b
-0000000c
-0000000d
-0000000e
-0000000f
-00000010
-00000011
-00000012
-00000013
-00000014
-00000015
-00000016
-00000017
-00000018
-00000019
-0000001a
-0000001b
-0000001c
-0000001d
-0000001e
-0000001f
-00000020
-00000021
-00000022
-00000023
-00000024
-00000025
-00000026
-00000027
-00000028
-00000029
-0000002a
-0000002b
-0000002c
-0000002d
-0000002e
-0000002f
-00000030
-00000031
-00000032
-00000033
-00000034
-00000035
-00000036
-00000037
-00000038
-00000039
-0000003a
-0000003b
-0000003c
-0000003d
-0000003e
-0000003f
-00000040
-00000041
-00000042
-00000043
-00000044
-00000045
-00000046
-00000047
-00000048
-00000049
-0000004a
-0000004b
-0000004c
-0000004d
-0000004e
-0000004f
-00000050
-00000051
-00000052
-00000053
-00000054
-00000055
-00000056
-00000057
-00000058
-00000059
-0000005a
-0000005b
-0000005c
-0000005d
-0000005e
-0000005f
-00000060
-00000061
-00000062
-00000063
-00000064
-00000065
-00000066
-00000067
-00000068
-00000069
-0000006a
-0000006b
-0000006c
-0000006d
-0000006e
-0000006f
-00000070
-00000071
-00000072
-00000073
-00000074
-00000075
-00000076
-00000077
-00000078
-00000079
-0000007a
-0000007b
-0000007c
-0000007d
-0000007e
-0000007f
-ffffffff  # signature  The test writes -1 for correct answers and the a positive integer for incorrect copies.
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-0bad0bad # controls
-0bad0bad  
-0bad0bad
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cboz-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cboz-01.reference_output
deleted file mode 100644
index ef91aa32f..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-cboz-01.reference_output
+++ /dev/null
@@ -1,188 +0,0 @@
-deadbeef # begin_signature
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-00000000  # destination 1
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000  # destination 2
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff  # signature  The test writes -1 for correct answers and the a positive integer for incorrect copies.
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-0bad0bad
-0bad0bad
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
index 71ecd9fd2..4327e2c31 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
@@ -1,13 +1,4 @@
 0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
-00000002 # S mode write to mstatush with illegal instruction
-00000002 # S mode read from mstatush with illegal instruction
-00000bad
-00000002 # S mode write to menvcfgh with illegal instruction
-00000002 # S mode read from menvcfgh with illegal instruction
-00000bad
-00000002 # S mode write to mseccfgh with illegal instruction
-00000002 # S mode read from mseccfgh with illegal instruction
-00000bad
 00000002 # S mode write to pmpcfg1 with illegal instruction
 00000002 # S mode read from pmpcfg1 with illegal instruction
 00000bad
@@ -119,15 +110,9 @@
 00000002 # S mode write to mhartid with illegal instruction
 00000002 # S mode read from mhartid with illegal instruction
 00000bad
-00000002 # S mode write to mconfigptr with illegal instruction
-00000002 # S mode read from mconfigptr with illegal instruction
-00000bad
 00000002 # S mode write to mstatus with illegal instruction
 00000002 # S mode read from mstatus with illegal instruction
 00000bad
-00000002 # S mode write to mstatush with illegal instruction
-00000002 # S mode read from mstatush with illegal instruction
-00000bad
 00000002 # S mode write to misa with illegal instruction
 00000002 # S mode read from misa with illegal instruction
 00000bad
@@ -161,15 +146,6 @@
 00000002 # S mode write to mip with illegal instruction
 00000002 # S mode read from mip with illegal instruction
 00000bad
-00000002 # S mode write to menvcfg with illegal instruction
-00000002 # S mode read from menvcfg with illegal instruction
-00000bad
-00000002 # S mode write to menvcfgh with illegal instruction
-00000002 # S mode read from menvcfgh with illegal instruction
-00000bad
-00000002 # S mode write to mseccfg with illegal instruction
-00000002 # S mode read from mseccfg with illegal instruction
-00000bad
 00000002 # S mode write to pmpcfg0 with illegal instruction
 00000002 # S mode read from pmpcfg0 with illegal instruction
 00000bad
@@ -408,3 +384,641 @@
 00000002 # S mode read from mhpmevent31 with illegal instruction
 00000bad
 00000009 # ecall from terminating tess from S mode
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
index 36d8f368b..8069d08a9 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
@@ -41,15 +41,9 @@
 00000002 # U mode write to mhartid with illegal instruction
 00000002 # U mode read from mhartid with illegal instruction
 00000bad
-00000002 # S mode write to mconfigptr with illegal instruction
-00000002 # S mode read from mconfigptr with illegal instruction
-00000bad
 00000002 # U mode write to mstatus with illegal instruction
 00000002 # U mode read from mstatus with illegal instruction
 00000bad
-00000002 # U mode write to mstatush with illegal instruction
-00000002 # U mode read from mstatush with illegal instruction
-00000bad
 00000002 # U mode write to misa with illegal instruction
 00000002 # U mode read from misa with illegal instruction
 00000bad
@@ -83,18 +77,6 @@
 00000002 # U mode write to mip with illegal instruction
 00000002 # U mode read from mip with illegal instruction
 00000bad
-00000002 # S mode write to menvcfg with illegal instruction
-00000002 # S mode read from menvcfg with illegal instruction
-00000bad
-00000002 # S mode write to menvcfgh with illegal instruction
-00000002 # S mode read from menvcfgh with illegal instruction
-00000bad
-00000002 # S mode write to mseccfg with illegal instruction
-00000002 # S mode read from mseccfg with illegal instruction
-00000bad
-00000002 # S mode write to senvcfg with illegal instruction
-00000002 # S mode read from senvcfg with illegal instruction
-00000bad
 00000002 # U mode write to pmpcfg0 with illegal instruction
 00000002 # U mode read from pmpcfg0 with illegal instruction
 00000bad
@@ -333,3 +315,710 @@
 00000002 # U mode read from mhpmevent31 with illegal instruction
 00000bad
 00000008 # ecall from terminating tests in U mode
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output
new file mode 100644
index 000000000..c40c4a22b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-lrsc-01.reference_output
@@ -0,0 +1,8 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mie-01.reference_output
index 9ce9022a8..2a2edbd91 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mie-01.reference_output
@@ -2,3 +2,1023 @@
 0000000b # mcause for ecall from terminating tests in M mode
 00000000 # mtval of ecall (*** defined to be zero for now)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output
index fe96ed79e..55904acab 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output
@@ -6,7 +6,1019 @@
 00000011 # confirm read-only permissions of mimpid
 00000002 # write to read-only CSR failed with illegal instruction
 00000011 # confirm read-only permissions of mhartid
-00000002 # write to read-only CSR failed with illegal instruction
-00000011 # confirm read-only permissions of mconfigptr
 0000000b # ecall from terminating tests in M mode
-
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output
index eaaa5bbff..63f51669e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-misa-01.reference_output
@@ -1,2 +1,1024 @@
 00000111 # Test 5.3.2.2: successful read of nonzero misa
 0000000b # ecall from terminating tests in machine mode
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output
index eaab3127f..3c828a4e2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output
@@ -41,11 +41,984 @@ beef0110
 00000bad
 0000000f
 beef0bb0
-beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
+beef0077 # Test 12.3.1.4.1: successful read back of saved value with new memory mapping
+00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode
 00000000 # previous value of mprv before being set
 beef0099 # Read success from translated address when mprv=1, mpp=S and priv mode = m
-0000000b # Test 11.3.1.5.2: ecall from going to S mode from m mode
+0000000b # Test 12.3.1.5.2: ecall from going to S mode from m mode
 00000009 # ecall from going straight back to m mode to access mstatus
 00000000 # previous zeroed out value of mprv
 0000000b # ecall from terminating tests in m mode
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
deleted file mode 100644
index 1f6ccbd2c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output
+++ /dev/null
@@ -1,54 +0,0 @@
-0000000b
-beef0055
-beef0033
-beef0077
-beef0099
-beef0440
-11100393
-00008067
-beef0055
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-0000000d
-00000bad
-0000000f
-0000000d
-00000bad
-0000000d
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-00000111
-00000009
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-00000bad
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-00000bad
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-0000000c
-00000bad
-0000000d
-00000bad
-0000000d
-00000bad
-beef0440
-beef0110
-0000000f
-0000000c
-00000bad
-0000000f # Test 11.3.1.3.6(a) page fault on write when A = 0
-0000000d # Test 11.3.1.3.6(a) page fault on read when A = 0
-00000bad
-0000000f # Test 11.3.1.3.7(a) page fault on write when D = 0
-12345678 # Test 11.3.1.3.7(a) successful read when D = 0
-00000009 # call from going to m mode from s mode
-0000000b # ecall from going to S mode from m mode
-beef0770 # Test 11.3.1.3.6: check successful read/write when A=0 and MENVCFG.ADUE=1
-beef0aa0 # Test 11.3.1.3.7: check successful read/write when D=0 and MENVCFG.ADUE=1
-beef0077 # Test 11.3.1.4.1: successful read back of saved value with new memory mapping
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
-00000000 # previous value of mprv before being set
-beef0099 # Read success from translated address when mprv=1, mpp=S and priv mode = m
-0000000b # Test 11.3.1.5.2: ecall from going to S mode from m mode
-00000009 # ecall from going straight back to m mode to access mstatus
-00000000 # previous zeroed out value of mprv
-0000000b # ecall from terminating tests in m mode
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
index f44fd3f89..8c4f8f6bf 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
@@ -5,3 +5,1020 @@
 0000000b # mcause from M mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
index 8102cd075..25745a989 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
@@ -1,20 +1,20 @@
-01BEEF00 # Test 1 interrupt 0
-8000000B # MEIP
-00000000 # mcausehigh
-0000000A # claim ID
-00000004 # IIR
-00000061 # LSR
-00000061 # LSR after reading LSR
-00000068 # RBR
-00000060 # LSR after erading RBR too
-00000001 # SCR
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 #null
-01BEEF01 # Test 1 interrupt 1
+01BEEF00
+8000000B
+00000000
+0000000A
+00000004
+00000061
+00000061
+00000068
+00000060
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+01BEEF01
 8000000B
 00000000
 00000003
@@ -30,7 +30,7 @@ FFFFFFFF
 FFF7FFFF
 00000000
 00000000
-01BEEF02 # Test 1 interrupt 2
+01BEEF02
 8000000B
 00000000
 00000003
@@ -46,7 +46,7 @@ FFFFFFFF
 FFFFFFFE
 00000000
 00000000
-01BEEF03 # Test 1 interrupt 3
+01BEEF03
 8000000B
 00000000
 0000000A
@@ -62,7 +62,7 @@ FFFFFFFE
 00000000
 00000000
 00000000
-02BEEF04 # Test 2 interrupt 4
+02BEEF04
 8000000B
 00000000
 00000003
@@ -78,7 +78,7 @@ FFFFFFFF
 FFFF0F0F
 00000000
 00000000
-02BEEF05 # Test 2 interrupt 5
+02BEEF05
 8000000B
 00000000
 00000003
@@ -94,7 +94,7 @@ FFFFFFFF
 CFCFFFFF
 00000000
 00000000
-02BEEF06 # Test 2 interrupt 6
+02BEEF06
 8000000B
 00000000
 00000003
@@ -110,7 +110,7 @@ CFFFFFFF
 CFFFFFFF
 00000000
 00000000
-02BEEF07 # Test 2 interrupt 7
+02BEEF07
 8000000B
 00000000
 00000003
@@ -126,7 +126,7 @@ FFFFFFFF
 F0FFFFFF
 00000000
 00000000
-02BEEF08 # Test 2 interrupt 8
+02BEEF08
 8000000B
 00000000
 00000003
@@ -142,7 +142,7 @@ FFFFFFFF
 FF0000FF
 00000000
 00000000
-02BEEF09 # Test 2 interrupt 9
+02BEEF09
 8000000B
 00000000
 00000003
@@ -158,7 +158,7 @@ FF0000FF
 CC0000CC
 00000000
 00000000
-02BEEF0A # Test 2 interrupt 10
+02BEEF0A
 8000000B
 00000000
 00000003
@@ -174,7 +174,7 @@ CCFFFFCC
 CCFFFFCC
 00000000
 00000000
-02BEEF0B Test 2 interrupt 11
+02BEEF0B
 8000000B
 00000000
 00000003
@@ -190,7 +190,7 @@ FFFFFFFF
 FF3333FF
 00000000
 00000000
-02BEEF0C # Test 2 interrupt 12
+02BEEF0C
 8000000B
 00000000
 00000003
@@ -206,7 +206,7 @@ FF3333FF
 FF3333FF
 00000000
 00000000
-02BEEF0D # Test 2 interrupt 13
+02BEEF0D
 8000000B
 00000000
 00000003
@@ -222,7 +222,7 @@ FFFFFFFF
 33FF3333
 00000000
 00000000
-02BEEF0E # Test 2 interrupt 14
+02BEEF0E
 8000000B
 00000000
 00000003
@@ -238,7 +238,7 @@ CCCCCCCC
 33333333
 00000000
 00000000
-02BEEF0F # Test 2 interrupt 15
+02BEEF0F
 8000000B
 00000000
 00000003
@@ -254,7 +254,7 @@ FFFFEE00
 FFFFEE00
 00000000
 00000000
-02BEEF10 # Test 2 interrupt 16
+02BEEF10 # Something here is failing
 8000000B
 00000000
 00000003
@@ -270,7 +270,7 @@ FFFFFFFF
 FFFFFF00
 00000000
 00000000
-02BEEF11 # Test 2 interrupt 17
+02BEEF11 # this might be wrong
 8000000B
 00000000
 00000003 
@@ -286,7 +286,7 @@ FFFFFFCC # low ip
 FFFFFFCC # serviced low ip
 00000000
 00000000
-03BEEF12 # test 3 interrupt 18
+03BEEF12
 8000000B
 00000000
 0000000A
@@ -302,7 +302,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF13 # Test 3 interrupt 19
+03BEEF13
 8000000B
 00000000
 0000000A
@@ -318,7 +318,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF14 # Test 3 interrupt 20
+03BEEF14
 8000000B
 00000000
 0000000A
@@ -334,7 +334,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF15 # Test 3 interrupt 21
+03BEEF15
 8000000B
 00000000
 0000000A
@@ -350,7 +350,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF16 # Test 3 interrupt 22
+03BEEF16
 8000000B
 00000000
 0000000A
@@ -366,7 +366,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF17 # Test 3 interrupt 23
+03BEEF17
 8000000B
 00000000
 0000000A
@@ -382,7 +382,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF18 # Test 3 interrupt 24
+03BEEF18
 8000000B
 00000000
 0000000A
@@ -398,7 +398,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF19 # Test 3 interrupt 25
+03BEEF19
 8000000B
 00000000
 0000000A
@@ -414,7 +414,7 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
-03BEEF1A # Test 3 interrupt 26
+03BEEF1A
 8000000B
 00000000
 0000000A
@@ -430,3 +430,67 @@ FFFFFFCC # serviced low ip
 00000000
 00000000
 00000000
+04BEEF1B
+80000009
+00000000
+0000000A
+00000004
+00000061
+00000061
+00000065
+00000060
+00000001
+000000ff
+00000000
+00000000
+00000000
+00000000
+00000000
+04BEEF1C
+80000009
+00000000
+00000003
+00080000
+00080000
+00080000
+00000000
+00000000 # is it this one that's failing?
+00000000
+00080000 # failing
+00080000
+FFFFFFFF
+FFF7FFFF
+00000000
+00000000
+04BEEF1D
+80000009
+00000000
+00000003
+00000001
+00000001
+00000001
+00000000
+00080000
+00000000
+00080001
+00000001
+FFFFFFFF
+FFFFFFFE
+00000000
+00000000
+04BEEF1E # this might also be wrong
+80000009
+00000000
+0000000A
+00000004
+00000061
+00000061
+0000006e
+00000060
+00000001
+000000ff
+00000000
+00000000
+00000000
+00000000
+00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-s-01.reference_output
deleted file mode 100644
index bd53e97f5..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-s-01.reference_output
+++ /dev/null
@@ -1,496 +0,0 @@
-01BEEF00 # Test 1 interrupt 0
-8000000B # MEIP
-00000000 # mcausehigh
-0000000A # claim ID
-00000004 # IIR
-00000061 # LSR
-00000061 # LSR after reading LSR
-00000068 # RBR
-00000060 # LSR after erading RBR too
-00000001 # SCR
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 # null
-00000000 #null
-01BEEF01 # Test 1 interrupt 1
-8000000B
-00000000
-00000003
-00080000
-00080000
-00080000
-00000000
-00000000
-00000000
-00080000
-00080000
-FFFFFFFF
-FFF7FFFF
-00000000
-00000000
-01BEEF02 # Test 1 interrupt 2
-8000000B
-00000000
-00000003
-00000001
-00000001
-00000001
-00000000
-00080000
-00000000
-00080001
-00000001
-FFFFFFFF
-FFFFFFFE
-00000000
-00000000
-01BEEF03 # Test 1 interrupt 3
-8000000B
-00000000
-0000000A
-00000004
-00000061
-00000061
-00000065
-00000060
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-02BEEF04 # Test 2 interrupt 4
-8000000B
-00000000
-00000003
-0000F0F0
-3030F0F0
-0000F0F0
-00000000
-00000001
-00000000
-0000F0F1
-0000F0F0
-FFFFFFFF
-FFFF0F0F
-00000000
-00000000
-02BEEF05 # Test 2 interrupt 5
-8000000B
-00000000
-00000003
-30300000
-3030F0F0
-30300000
-00000000
-0000F0F0
-00000000
-3030F0F0
-30300000
-FFFFFFFF
-CFCFFFFF
-00000000
-00000000
-02BEEF06 # Test 2 interrupt 6
-8000000B
-00000000
-00000003
-30000000
-3030F0F0
-00000000
-00000000
-00300000
-00000000
-30300000
-30000000
-CFFFFFFF
-CFFFFFFF
-00000000
-00000000
-02BEEF07 # Test 2 interrupt 7
-8000000B
-00000000
-00000003
-0F000000
-0F0F0F0F
-0F000000
-00000000
-30000000
-00000000
-3F000000
-0F000000
-FFFFFFFF
-F0FFFFFF
-00000000
-00000000
-02BEEF08 # Test 2 interrupt 8
-8000000B
-00000000
-00000003
-00FFFF00
-00FFFF00
-00FFFF00
-00000000
-00000000
-00000000
-00FFFF00
-00FFFF00
-FFFFFFFF
-FF0000FF
-00000000
-00000000
-02BEEF09 # Test 2 interrupt 9
-8000000B
-00000000
-00000003
-33FFFF33
-33FFFF33
-33000033
-00000000
-00000000
-00000000
-33FFFF33
-33FFFF33
-FF0000FF
-CC0000CC
-00000000
-00000000
-02BEEF0A # Test 2 interrupt 10
-8000000B
-00000000
-00000003
-33000033
-33000033
-00000000
-00000000
-00FFFF00
-00000000
-33FFFF33
-33000033
-CCFFFFCC
-CCFFFFCC
-00000000
-00000000
-02BEEF0B Test 2 interrupt 11
-8000000B
-00000000
-00000003
-00CCCC00
-00CCCC00
-00CCCC00
-00000000
-33000033
-00000000
-33CCCC33
-00CCCC00
-FFFFFFFF
-FF3333FF
-00000000
-00000000
-02BEEF0C # Test 2 interrupt 12
-8000000B
-00000000
-00000003
-00CCCC00
-00CCCC00
-00000000
-00000000
-00000000
-00000000
-00CCCC00
-00CCCC00
-FF3333FF
-FF3333FF
-00000000
-00000000
-02BEEF0D # Test 2 interrupt 13
-8000000B
-00000000
-00000003
-CC00CCCC
-CCCCCCCC
-CC00CCCC
-00000000
-00CCCC00
-00000000
-CC00CCCC
-CC00CCCC
-FFFFFFFF
-33FF3333
-00000000
-00000000
-02BEEF0E # Test 2 interrupt 14
-8000000B
-00000000
-00000003
-CCCCCCCC
-CCCCCCCC
-00CC0000
-00000000
-00000000
-00000000
-CCCCCCCC
-CCCCCCCC
-33FF3333
-33333333
-00000000
-00000000
-02BEEF0F # Test 2 interrupt 15
-8000000B
-00000000
-00000003
-000011FF
-FF1111FF
-33333333
-00000000
-FFFFEE00
-00000000
-FFFFFFFF
-000011FF
-FFFFEE00
-FFFFEE00
-00000000
-00000000
-02BEEF10 # Test 2 interrupt 16
-8000000B
-00000000
-00000003
-000000FF
-00000000
-000000FF
-00000000
-00000000
-00000000
-000000FF
-000000FF
-FFFFFFFF
-FFFFFF00
-00000000
-00000000
-02BEEF11 # Test 2 interrupt 17
-8000000B
-00000000
-00000003 
-00000033 # input
-00000000 # output
-00000000 # rise ip
-00000000 # serviced rise ip
-000000CC # fall ip
-00000000 
-000000FF # high ip
-00000033 # why is this 0x33?
-FFFFFFCC # low ip
-FFFFFFCC # serviced low ip
-00000000
-00000000
-03BEEF12 # test 3 interrupt 18
-8000000B
-00000000
-0000000A
-00000002
-00000061
-00000061
-0000006C
-00000060
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF13 # Test 3 interrupt 19
-8000000B
-00000000
-0000000A
-00000002
-00000021
-00000021
-0000006C
-00000020
-00000001
-00000002
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF14 # Test 3 interrupt 20
-8000000B
-00000000
-0000000A
-00000004
-00000061
-00000061
-0000006F
-00000060
-00000001
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF15 # Test 3 interrupt 21
-8000000B
-00000000
-0000000A
-00000004
-00000061
-00000061
-00000020
-00000060
-00000001
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF16 # Test 3 interrupt 22
-8000000B
-00000000
-0000000A
-00000004
-00000061
-00000061
-00000074
-00000060
-00000001
-00000020
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF17 # Test 3 interrupt 23
-8000000B
-00000000
-0000000A
-00000002
-00000020
-00000020
-00000074
-00000020
-00000001
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF18 # Test 3 interrupt 24
-8000000B
-00000000
-0000000A
-00000002
-00000020
-00000020
-00000074
-00000020
-00000001
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF19 # Test 3 interrupt 25
-8000000B
-00000000
-0000000A
-00000004
-00000061
-00000061
-00000065
-00000060
-00000001
-00000003
-00000000
-00000000
-00000000
-00000000
-00000000
-03BEEF1A # Test 3 interrupt 26
-8000000B
-00000000
-0000000A
-00000006
-00000063
-00000061
-00000047
-00000060
-00000001
-000000FF
-00000000
-00000000
-00000000
-00000000
-00000000
-04BEEF1B # Test 4 interrupt 27
-80000009
-00000000
-0000000A
-00000004
-00000061
-00000061
-00000065
-00000060
-00000001
-000000ff
-00000000
-00000000
-00000000
-00000000
-00000000
-04BEEF1C # Test 4 interrupt 28
-80000009
-00000000
-00000003
-00080000
-00080000
-00080000
-00000000
-00000000
-00000000
-00080000
-00080000
-FFFFFFFF
-FFF7FFFF
-00000000
-00000000
-04BEEF1D # Test 4 interrupt 29
-80000009
-00000000
-00000003
-00000001
-00000001
-00000001
-00000000
-00080000
-00000000
-00080001
-00000001
-FFFFFFFF
-FFFFFFFE
-00000000
-00000000
-04BEEF1E # Test 4 interrupt 30
-80000009
-00000000
-0000000A
-00000004
-00000061
-00000061
-0000006e
-00000060
-00000001
-000000ff
-00000000
-00000000
-00000000
-00000000
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output
index e4f256e77..15626485b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output
@@ -61,3 +61,964 @@ beef00c1
 00000001
 00000bad
 0000000b
+deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output
index 0ad3d40c9..b929d6ff3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output
@@ -27,3 +27,998 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output
index 53a480fec..f0468cead 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output
@@ -1,3 +1,3 @@
 0000000b # Test *** Number: Ecall from going from M mode to S mode
-00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address
+00000002 # illegal instruction from truining on virtual memory with invalid satp address
 00000009 # ecall from ending tests in S mode.
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sie-01.reference_output
index f995e1cae..27199c350 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sie-01.reference_output
@@ -5,3 +5,1020 @@
 00000009 # mcause for ecall from terminating tests in S mode
 00000000 # mtval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output
deleted file mode 100644
index e19f75391..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output
+++ /dev/null
@@ -1,306 +0,0 @@
-00000003    # reset tests sck_div
-
-00000000    # sck_mode
-
-00000000    # cs_id
-
-0000000F    # cs_def
-
-00000000    # cs_mode
-
-00010001    # delay 0
-
-00000001    # delay 1
-
-00080000    # fmt
-
-00000000    # tx_data
-
-00000000    # tx_mark
-
-00000000    # rx_mark
-
-00000000    # ie reset
-
-00000000    # ip reset
-
-00000000    # fifo watermark and edge case tests
-
-00000001
-
-00000003
-
-00000003
-
-00000074    # spi_burst_send
-
-00000063    # spi_burst_send
-
-00000052    # spi_burst_send
-
-00000041    # spi_burst_send
-
-000000A1    # spi_burst_send
-
-00000003
-
-000000B2    # spi_burst_send
-
-00000001
-
-000000C3    # spi_burst_send
-
-000000D4    # spi_burst_send
-
-00000003
-
-000000A4    # tx_data write test
-
-00000001
-
-000000B4    # tx_data write test
-
-000000A5    # spi_burst_send    
-
-000000B5    # spi_burst_send
-
-000000C5    # spi_burst_send
-
-000000D5    # spi_burst_send
-
-000000A7    # spi_burst_send
-
-000000B7    # spi_burst_send
-
-000000C7    # spi_burst_send
-
-00000002
-
-000000D7    # spi_burst_send
-
-00000000
-
-00000011 #basic read write
-
-000000FF    # first test sck_div
-
-000000AE    # min sck_div first spi_burst_send
-
-000000AD
-
-000000AC
-
-000000AB
-
-000000AE
-
-000000AD
-
-000000AC
-
-000000AB
-
-000000AE
-
-000000AD
-
-000000AC
-
-000000AB
-
-000000AE
-
-000000AD
-
-000000AC
-
-000000AB
-
-000000A0
-
-0000000B
-
-000000F3
-
-00000079
-
-00000000
-
-000000C0
-
-00000011
-
-00000020 #delay registers
-
-00000032
-
-00000048
-
-000000AF
-
-00000050
-
-0000006B
-
-00000011
-
-00000015
-
-00000010
-
-00000010
-
-00000010
-
-00000010
-
-00000010
-
-00000010
-
-00000011
-
-00000011
-
-00000011
-
-00000011
-
-00000011
-
-00000011
-
-00000011 #delay1
-
-00000022
-
-00000033
-
-00000044
-
-0000007B
-
-00000021
-
-00000032
-
-00000043
-
-00000054
-
-00000066
-
-00000077
-
-00000088
-
-00000099
-
-00000066
-
-00000077
-
-00000088
-
-00000099
-
-00000065
-
-00000076
-
-00000087
-
-00000098
-
-00000048
-
-000000DD
-
-000000CC
-
-000000BB
-
-000000AA
-
-000000DE
-
-000000CD
-
-000000BC
-
-000000AB
-
-000000CE hold mode deassert
-
-000000F0 #fmt register
-
-00000000
-
-00000080
-
-00000000
-
-00000080
-
-000000A8
-
-000000F8
-
-00000048
-
-00000070
-
-00000000 
-
-00000008
-
-00000003
-
-00000017
-
-0000000F
-
-0000001F
-
-00000001 #watermark interrupts
-
-00000000 #read mip
-
-00000000 #read tx ip
-
-00000022 #clear 1 frame from rx fifo
-
-00000000 # read recieve ip
-
-00000002 #read recieve ip
-
-00000000 #read mip
-
-00000033 #clear frame
-
-00000000 # read receive ip
-
-00000044 #clear frame
-
-00000055 #clear frame
-
-00000001 #read tx ip
-
-00000800 #read mip
-
-00000022 #clear frame
-
-00000000 #read rx ip
-
-00000000 #read mip 94
-
-00000002 #read rx ip
-
-00000800 #read mip
-
-00000033 #clear frame
-
-00000000 #read rx wm
-
-00000000 #read mip 99
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
index 9af6a9b2c..fa09f6706 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
@@ -4,3 +4,1021 @@
 80006000 # read SD = 1, FS = 11
 00000002 # mcause from attempting fmv with status.FS cleared
 0000000b # mcause from M mode ecall from test termination
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output
index ef904a667..cf0b9854f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-mie-01.reference_output
@@ -6,3 +6,1019 @@
 0000000b # mcause for ecall from terminating tests in M mode 
 00000000 # mtval of ecall (*** defined to be zero for now) 
 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output
index c621e5747..e6297f1e6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output
@@ -10,3 +10,1015 @@
 00000009 # mcause for ecall from terminating tests in S mode
 00000000 # mtval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tvm-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tvm-01.reference_output
index 8633602f4..ade880c7e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tvm-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tvm-01.reference_output
@@ -3,3 +3,1022 @@
 00000002 # mcause for illegal satp read instruction due to status.tvm bit being set.
 00000002 # mcause for illegal sfence.vma instruction due to status.tvm bit being set.
 00000009 # mcause from S mode ecall from test termination
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output
index e1fe0b5c3..f41585309 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output
@@ -7,3 +7,1018 @@
 00000009 # mcause from S mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
index 123bf3622..fd53d0392 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
@@ -18,3 +18,1007 @@
 00000008 # mcause from U mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
index e00557a76..2877f4a8e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,23 +1,21 @@
-FFFFFFFF # stimecmp readback
-80000000 # menvcfg readback
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
 00000000 # mtval of faulting instruction address (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000002 # mcause from an Illegal instruction
-FFFFFFFF # mtval of faulting instruction (0x11111111)
+00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-80000168 # mtval of breakpoint instruction adress
+8000015c # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000171 # mtval of misaligned address
+80000165 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-80000189 # mtval of address with misaligned store instr
+8000017d # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)
@@ -55,25 +53,25 @@ FFFFFFFF # mtval of faulting instruction (0x11111111)
 8000000b # mcause value from m ext interrupt
 00000000 # mtval for mext interrupt (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
 00000000 # mtval of faulting instruction address (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000002 # mcause from an Illegal instruction
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-80000168 # mtval of breakpoint instruction adress
+8000015c # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000171 # mtval of misaligned address
+80000165 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-80000189 # mtval of address with misaligned store instr
+8000017d # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)
@@ -96,3 +94,931 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 0000000b # mcause from M mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
index bb64ad870..089aeba9d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
@@ -6,19 +6,19 @@
 00000000 # stval of faulting instruction address (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000002 # scause from an Illegal instruction
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -29,6 +29,10 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000008 # scause from U mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
+0007ec01 # value to indicate successful vectoring on s soft interrupt 
+80000001 # scause value from s soft interrupt
+00000000 # stval for ssoft interrupt (0x0)
+00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 0007ec03 # value to indicate successful vectoring on m soft interrupt 
 80000003 # scause value from m soft interrupt
 00000000 # stval for msoft interrupt (0x0)
@@ -48,7 +52,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000009 # scause from S mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 0000000b # scause from M mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
@@ -57,19 +61,19 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000 # stval of faulting instruction address (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000002 # scause from an Illegal instruction
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -91,3 +95,930 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000009 # scause from S mode ecall from test termination
 00000000 # stval of ecall (*** defined to be zero for now)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
index 2d1377a75..f5d842bf5 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output
@@ -7,3 +7,1018 @@
 00000009 # mcause from S mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
index 56ec350cc..22699f42f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
@@ -6,19 +6,19 @@
 00000000 # stval of faulting instruction address (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000002 # scause from an Illegal instruction
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -45,7 +45,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000008 # scause from U mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 0000000b # scause from M mode ecall 
 00000000 # stval of ecall (*** defined to be zero for now)
@@ -54,19 +54,19 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000 # stval of faulting instruction address (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000002 # scause from an Illegal instruction
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -81,3 +81,944 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000008 # scause from U mode ecall from test termination
 00000000 # stval of ecall (*** defined to be zero for now)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-wfi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-wfi-01.reference_output
index 43c4115f4..5ff5cca4c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-wfi-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-wfi-01.reference_output
@@ -7,3 +7,1018 @@
 0000000b # mcause from M mode ecall from test termination
 00000000 # mtval of ecall (*** defined to be zero for now)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
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+deadbeef
+deadbeef
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+deadbeef
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 838f886ec..07813da16 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -55,12 +55,6 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
-    // set up PMP so user and supervisor mode can access full address space
-    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
-    li t0, 0xFFFFFFFF   
-    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
-
-
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses
@@ -89,7 +83,7 @@ cause_instr_access:
     ret
 
 cause_illegal_instr:
-    .word 0xFFFFFFFF // 32 bit ones is an illegal instruction
+    .word 0x00000000 // 32 bit zero is an illegal instruction
     ret
 
 cause_breakpnt:
@@ -117,7 +111,7 @@ cause_store_acc:
     ret
 
 cause_ecall:
-    // ASSUMES you have already gone to the mode you need to call this from.
+    // *** ASSUMES you have already gone to the mode you need to call this from.
     ecall
     ret
 
@@ -131,31 +125,20 @@ cause_m_time_interrupt:
     lw t2, 0(t5)         // low word of MTIME
     lw t6, 4(t5)         // high word of MTIME
     add t3, t2, t3       // add desired offset to the current time
-    bgtu t3, t2, nowrap_m  // check new time exceeds current time (no wraparound)
+    bgtu t3, t2, nowrap  // check new time exceeds current time (no wraparound)
     addi t6, t6, 1       // if wrap, increment most significant word
-nowrap_m:
     sw t6,4(t4)          // store into most significant word of MTIMECMP
+nowrap:
     sw t3, 0(t4)         // store into least significant word of MTIMECMP
-time_loop_m:
+time_loop:
     addi a3, a3, -1
-    bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
+    bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
     ret
 
 cause_s_time_interrupt:
-    li t3, 0x30          // Desired offset from the present time
-    mv a3, t3            // copy value in to know to stop waiting for interrupt after this many cycles
-    la t5, 0x0200BFF8    // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
-    lw t2, 0(t5)         // low word of MTIME
-    lw t6, 4(t5)         // high word of MTIME
-    add t3, t2, t3       // add desired offset to the current time
-    bgtu t3, t2, nowrap_s  // check new time exceeds current time (no wraparound)
-    addi t6, t6, 1       // if wrap, increment most significant word
-nowrap_s:
-    csrw stimecmp, t3         // store into STIMECMP
-    csrw stimecmph, t6     // store into STIMECMPH
-time_loop_s:
-    addi a3, a3, -1
-    bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
+    li t3, 0x20
+    csrs mip, t3 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
+    nop // added extra nops in so the csrs can get through the pipeline before returning.
     ret
 
 cause_m_soft_interrupt:
@@ -280,7 +263,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sw t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
- 
+
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
@@ -319,7 +302,7 @@ end_trap_triggers:
 .align 6
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
-    // ASSUMES that a cause value of 0 for an interrupt is unimplemented
+    // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
     j s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
@@ -337,7 +320,7 @@ trap_handler_\MODE\():
 
 trap_unvectored_\MODE\():
     csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
-    // NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
+    // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
 
 trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
     // save registers on stack before using
@@ -562,12 +545,8 @@ soft_interrupt_\MODE\():
 time_interrupt_\MODE\():
     la t0, 0x02004000    // MTIMECMP register in CLINT
     li t2, 0xFFFFFFFF
-    sw t2, 0(t0) // reset interrupt by setting mtimecmp to max
-    //sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max
-    csrw stimecmp, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH.
-    csrw stimecmph, t2
-
-
+    sw t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+    
     li t0, 0x20
     csrc \MODE\()ip, t0
     lw ra, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
@@ -707,7 +686,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 .endm
 
 .macro READ32 ADDR
-    // Attempt read at ADDR. Write the value read out to the output. Consider adding specific test for reading a non known value
+    // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value
     // Success outputs:
     //      value read out from ADDR
     // Fault outputs:
@@ -751,6 +730,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 //      0x9: test called from S mode
 //      0xB: test called from M mode
 // they generally do not fault or cause issues as long as these modes are enabled 
+// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
 
 .macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 2 // determine trap handler behavior (go to machine mode)
@@ -806,7 +786,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     //      value read back out from CSR after writing
     // Fault outputs:
     //      The previous CSR value before write attempt
-    //      Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
+    //      *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
     li t5, 0xbad // load bad value to be overwritten by csrr
     li t4, \VAL
     csrw \CSR\(), t4
@@ -864,7 +844,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 
     .equ PLIC_INTPRI_GPIO, 0x0C00000C       # GPIO is interrupt 3
     .equ PLIC_INTPRI_UART, 0x0C000028       # UART is interrupt 10
-    .equ PLIC_INTPRI_SPI,  0x0C000018       # SPI in interrupt 6
     .equ PLIC_INTPENDING0, 0x0C001000       # intPending0 register
     .equ PLIC_INTEN00,     0x0C002000       # interrupt enables for context 0 (machine mode) sources 31:1
     .equ PLIC_INTEN10,     0x0C002080       # interrupt enables for context 1 (supervisor mode) sources 31:1
@@ -877,7 +856,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     .4byte PLIC_THRESH1, 7, write32_test    # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts
     .4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority
     .4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority
-    .4byte PLIC_INTPRI_SPI, 7, write32_test # Set UART to high priority
     .4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode
     .4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode
 .endm
@@ -1029,12 +1007,6 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
     sw t3, 0(t2)
     sw t4, -4(sp)
     addi sp, sp, -4
-    li t2, 0x0C000018 // SPI priority
-    li t3, 7
-    lw t4, 0(t2)
-    sw t3, 0(t2)
-    sw t4, -4(sp)
-    addi sp, sp, -4
     li t2, 0x0C002000
     li t3, 0x0C200004
     li t4, 0xFFF
@@ -1045,14 +1017,11 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
     sw t6, 0(t2) // restore saved enable status
     li t2, 0x0C00000C // GPIO priority
     li t3, 0x0C000028 // UART priority
-    li t6, 0x0C000018 // SPI priority
-    lw a4, 8(sp) // load stored GPIO prioroty
-    lw t4, 4(sp) // load stored UART priority
-    lw t5, 0(sp) // load stored SPI priority
-    addi sp, sp, 12 // restore stack pointer
-    sw a4, 0(t2)
-    sw t4, 0(t3)
-    sw t5, 0(t6)
+    lw t4, 4(sp) // load stored GPIO and UART priority
+    lw t5, 0(sp)
+    addi sp, sp, 8 // restore stack pointer
+    sw t4, 0(t2)
+    sw t5, 0(t3)
     j test_loop
 
 claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
@@ -1099,36 +1068,33 @@ uart_save_iir_status:
     j test_loop
 
 uart_data_wait:
-    li t2, 0x10000002
-    lbu t3, 0(t2) // save IIR before reading LSR might clear it
-    // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing.
-    li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
-    beq t3, t2, uart_rxfifo_timout
-    li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending.
-    beq t3, t2, uart_txempty_intr
-    li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang
-    lb t4, 0(t2) // read LSR
-    li t2, 0x61
-    bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready
+    li t2, 0x10000005 // LSR
+    li t3, 0x10000002 // IIR
+    li a4, 0x61
+uart_read_LSR_IIR:
+    lbu t4, 0(t3) // save IIR before reading LSR might clear it
+    //  check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this.
+    li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
+    beq t4, t5, uart_rxfifo_timout
+    lb t5, 0(t2) // read LSR
+    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
+    bne a4, t6, uart_read_LSR_IIR
     j uart_data_ready
 uart_rxfifo_timout:
-    li t2, 0x10000000 // read from the fifo to clear the rx timeout error
-    lb t5, 0(t2)
-    sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
-    j uart_data_wait
-uart_txempty_intr:
-    li t2, 0x10000002
-    lb t5, 0(t2) // Read IIR to clear this bit in LSR
-    j uart_data_wait
+    li t4, 0x10000000 // read from the fifo to clear the rx timeout error
+    lb t5, 0(t4)
+    sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
+    //read the fifo until empty
+    j uart_read_LSR_IIR
+
 
 uart_data_ready:
-    li t2, 0x10000002
-    lbu t3, 0(t2) // re read IIR
-    andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature
     li t2, 0
     sw t2, 0(t1) // clear entry deadbeef from memory
-    sb t3, 1(t1) // IIR
-    sb t4, 0(t1) // LSR
+    lbu t4, 0(t3) // re read IIR
+    andi t5, t5, 0x9F // mask THRE and TEMT from signature
+    sb t4, 1(t1) // IIR
+    sb t5, 0(t1) // LSR
     addi t1, t1, 4
     addi a6, a6, 4
     j test_loop
@@ -1138,34 +1104,6 @@ uart_clearmodemintr:
     lb t2, 0(t2)
     j test_loop
 
-spi_data_wait:
-    li t2, 0x10040054
-    sw t4, 0(t2) // set rx watermark level 
-    li t2, 0x10040074
-    lw t3, 0(t2) //read ip (interrupt pending register)
-    slli t3, t3, 28
-    srli t3, t3, 28
-    li t2, 0x00000002
-    bge t3, t2, spi_data_ready //branch to done if transmission complete
-    j spi_data_wait //else check again
-
-spi_data_ready:
-    li t2, 0x10040070
-    li t3, 0x00000000
-    sw t3, 0(t2) //disable rx watermark interrupt
-    j test_loop
-
-spi_burst_send: //function for loading multiple frames at once to test delays without returning to test loop
-    mv t2, t4
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    j test_loop
-
 goto_s_mode:
     // return to address in t3, 
     li a0, 3 // Trap handler behavior (go to supervisor mode)
@@ -1362,18 +1300,6 @@ write_mideleg:
     csrw mideleg, t4
     j test_loop
 
-write_menvcfg:
-    // writes the value in t4 to the menvcfg register
-    // Doesn't log anything
-    csrw menvcfg, t4
-    j test_loop
-
-write_menvcfgh:
-    // writes the value in t4 to the menvcfgh register
-    // Doesn't log anything
-    csrw menvcfgh, t4
-    j test_loop
-
 executable_test:
     // Execute the code at the address in t3, returning the value in t2.
     // Assumes the code modifies t2, to become the value stored in t4 for this test.  
@@ -1427,9 +1353,6 @@ RVMODEL_DATA_BEGIN
 test_1_res:
     .fill 1024, 4, 0xdeadbeef
 
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
 
 #ifdef rvtest_mtrap_routine
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S
new file mode 100644
index 000000000..8a1906585
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo-01.S
@@ -0,0 +1,175 @@
+///////////////////////////////////////////
+// WALLY-AMO.S
+//
+// Tests Atomic AMO instructions
+//
+// David_Harris@hmc.edu 11 March 2021
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Adapted from Imperas RISCV-TEST_SUITE
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV32IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo)
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+
+    # ---------------------------------------------------------------------------------------------
+    # address for test results
+    la x6, wally_signature
+    la x31, test_data
+
+    # Testcase 0:  amoswap.w
+    li x7, 1
+    amoswap.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be fffffffe (sign extended from test data)
+    sw x9, 4(x6)        # should be 00000001 (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 1:  amoadd.w
+    li x7, 2
+    amoadd.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be fffffffb (sign extended from test data)
+    sw x9, 4(x6)        # should be fffffffd (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 2:  amoand.w
+    li x7, 0x7ff
+    amoand.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be ffffffef (sign extended from test data)
+    sw x9, 4(x6)        # should be 000007ef (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 3:  amoor.w
+    li x7, 0x44
+    amoor.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be ffffffbf (sign extended from test data)
+    sw x9, 4(x6)        # should be ffffffff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 4:  amoxor.w
+    li x7, 0x381
+    amoxor.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be fffffeff (sign extended from test data)
+    sw x9, 4(x6)        # should be fffffd7e (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 5:  amomax.w
+    li x7, 0x7ff
+    amomax.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be fffffeff (sign extended from test data)
+    sw x9, 4(x6)        # should be 000007ff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 6:  amomin.w
+    li x7, 0x7fd
+    amomin.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be ffffefff (sign extended from test data)
+    sw x9, 4(x6)        # should be ffffefff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 7:  amomaxu.w
+    li x7, 0x7fb
+    amomaxu.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be ffffefff (sign extended from test data)
+    sw x9, 4(x6)        # should be ffffefff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+
+    # Testcase 8:  amominu.w
+    li x7, 0x7fa
+    amominu.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sw x8, 0(x6)        # should be fffeffff (sign extended from test data)
+    sw x9, 4(x6)        # should be 000007fa (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 8
+    # ---------------------------------------------------------------------------------------------
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+	.align 8
+test_data:
+	.dword 0xfffffffdfffffffe
+	.dword 0xfffffff7fffffffb
+	.dword 0xffffffdfffffffef
+	.dword 0xffffff7fffffffbf
+	.dword 0xfffffdfffffffeff
+	.dword 0xfffff7fffffffeff
+	.dword 0x0fffdfffffffefff
+	.dword 0xffff7fffffffefff
+	.dword 0x3ffdfffffffeffff
+	.dword 0xfff7fffffffbffff
+	.dword 0xffdfffffffefffff
+	.dword 0xff7fffffffbfffff
+	.dword 0xfdfffffffeffffff
+	.dword 0xf7fffffffeffffff
+	.dword 0xdfffffffefffffff
+	.dword 0x7fffffffefffffff
+	.dword 0x00000001ffffffff
+	.dword 0x0000000400000002
+	.dword 0x0000001000000008
+	.dword 0x0000004000000020
+	.dword 0x0000010000000080
+	.dword 0x0000040000000200
+	.dword 0x0000100000000800
+	.dword 0x0000400000002000
+	.dword 0x0000000100008000
+	.dword 0x0004000000000002
+	.dword 0x0000001000080000
+	.dword 0x0040000000000020
+	.dword 0x0000010000800000
+	.dword 0x0400000000000200
+	.dword 0x0000100008000000
+	.dword 0x4000000000002000
+	.dword 0x0000000080000000
+
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+#endif
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+# signature output
+wally_signature:
+.fill 20, 4, -1
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
deleted file mode 100644
index f3e3846f3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cbom-01.S
+++ /dev/null
@@ -1,475 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-cache-management-tests 
-// invalidate, clean, and flush
-//
-// Author: Rose Thompson <rose@rosethompson.net>
-//
-// Created 18 August 2023
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline
-#          granularity blocks of memory.  Invalidate: Clears valid and dirty bits
-#          and does not write back.  Clean: Writes back dirty cacheline if needed
-#          and clears dirty bit.  Does NOT clear valid bit.  Flush:  Cleans and then
-#          Invalidates.  These operations apply to all caches in the memory system.
-#          The tests are divided into three parts one for the data cache
-#          and checks to verify the uncached regions of memory cause exceptions.
-# -----------
-# Copyright (c) 2020. RISC-V International. All rights reserved.
-# SPDX-License-Identifier: BSD-3-Clause
-# -----------
-#
-# This assembly file tests the cbo.inval, cbo.clean, and cbo.flush instructions of the RISC-V Zicbom extension.
-# 
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32I_Zicbom")
-# Test code region
-.section .text.init
-.globl rvtest_entry_point
-	
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.inval)
-
-RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
-	
-CBOMTest:
-        # *** TODO
-        # first need to discover the length of the cacheline.
-        # for now assume it is 64 bytes
-
-        #addi sp, sp, -16
-        #sd s0, 0(sp)
-        #sd ra, 8(sp)
-
-	la s0, signature
-
-        ################################################################################
-        # INVALIDATE  D$
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Invalidate the second region
-        # 4. Verify the second region has the original invalid data
-        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
-        # but the next should have the copied data.
-
-        # step 1
-CBOMTest_inval_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcpy4
-
-        # step 2
-CBOMTest_inval_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 3
-CBOMTest_inval_step3: 
-        la a1, Destination1
-        cbo.inval (a1)
-        # step 4  (should be Invalid)
-        la a0, DeadBeafData1
-        la a1, Destination1
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-        # step 4 next line (should still be valid)
-CBOMTest_inval_step4: 
-        la a0, SourceData+64
-        la a1, Destination1+64
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-        # step 3 (Invalidate all remaining lines)
-CBOMTest_inval_step3_all: 
-        la a1, Destination1+64
-        cbo.inval (a1)
-        cbo.inval (a1)          # verify invalidating an already non present line does not cause an issue.
-        la a1, Destination1+128
-        cbo.inval (a1)
-        la a1, Destination1+192
-        cbo.inval (a1)
-        la a1, Destination1+256
-        cbo.inval (a1)
-        la a1, Destination1+320
-        cbo.inval (a1)
-        la a1, Destination1+384
-        cbo.inval (a1)
-        la a1, Destination1+448
-        cbo.inval (a1)
-	
-        # step 4 All should be invalid
-CBOMTest_inval_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-        ################################################################################
-        # Clean D$
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Invalidate the second region
-        # 4. Verify the second region has the original invalid data
-        # 5. Repeat step 1
-        # 6. Clean cachelines
-        # 7. Verify the second region has the same data
-        # 8. Invalidate the second region
-        # 9. Verify again but this time it should contain the same data
-        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
-        # but the next should have the copied data.
-        
-        # step 1
-CBOMTest_clean_step1: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 128
-        jal ra, memcpy4
-
-        # step 2
-CBOMTest_clean_step2:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 3
-CBOMTest_clean_step3:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-        la a1, Destination2+128
-        cbo.inval (a1)
-        la a1, Destination2+192
-        cbo.inval (a1)
-        la a1, Destination2+256
-        cbo.inval (a1)
-        la a1, Destination2+320
-        cbo.inval (a1)
-        la a1, Destination2+384
-        cbo.inval (a1)
-        la a1, Destination2+448
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-
-        # step 4 All should be invalid
-CBOMTest_clean_step4:
-        la a0, DeadBeafData1
-        la a1, Destination2
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-        
-        # step 5
-CBOMTest_clean_step5:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 128
-        jal ra, memcpy4
-
-        # step 6  only clean 1 line
-CBOMTest_clean_step6:
-        la a1, Destination2
-        cbo.clean (a1)
-	
-        # step 7  only check that 1 line
-CBOMTest_clean_step7:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 8  invalidate that 1 line and the next
-CBOMTest_clean_step8:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-	
-        # step 9  that 1 line should contain the valid data
-CBOMTest_clean_step9_line1:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 9 the next should contain the invalid data
-CBOMTest_clean_step9_line2:
-        la a0, DeadBeafData1
-        la a1, Destination2+64
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 5 # now recopy the one we just corrupted
-CBOMTest_clean_step5_recopy_line2:
-        la a0, SourceData+64
-        la a1, Destination2+64
-        li a2, 16
-        jal ra, memcpy4
-
-        # step 6 # clean the remaining
-CBOMTest_clean_step6_clean_all:
-        la a1, Destination2+64
-        cbo.clean (a1)
-        la a1, Destination2+128
-        cbo.clean (a1)
-        la a1, Destination2+192
-        cbo.clean (a1)
-        la a1, Destination2+256
-        cbo.clean (a1)
-        la a1, Destination2+320
-        cbo.clean (a1)
-        la a1, Destination2+384
-        cbo.clean (a1)
-        la a1, Destination2+448
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-	
-        # step 8 # invalidate all remaining
-CBOMTest_clean_step7_invalidate_all:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-        la a1, Destination2+128
-        cbo.inval (a1)
-        la a1, Destination2+192
-        cbo.inval (a1)
-        la a1, Destination2+256
-        cbo.inval (a1)
-        la a1, Destination2+320
-        cbo.inval (a1)
-        la a1, Destination2+384
-        cbo.inval (a1)
-        la a1, Destination2+448
-        cbo.inval (a1)
-	
-        # step 9 # check all
-CBOMTest_clean_step9_check_all:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        ################################################################################
-        # Flush D$ line
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. For flush there is no way to create a negative control. We will flush 1 cache line
-        # 4. Verify whole region
-        # 5. Flush the remaining lines
-        # 6. Verify whole region
-
-        # step 1
-CBOMTest_flush_step1: 
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 128
-        jal ra, memcpy4
-
-        # step 2 All should be valid
-CBOMTest_flush_step2_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 3 # flush 1 line
-CBOMTest_flush_step3:
-        la a1, Destination3
-        cbo.flush (a1)
-
-        # step 4 
-CBOMTest_flush_step4_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 5
-CBOMTest_flush_step5_flush_all:
-        la a1, Destination3
-        cbo.flush (a1)
-        la a1, Destination3+64
-        cbo.flush (a1)
-        la a1, Destination3+128
-        cbo.flush (a1)
-        la a1, Destination3+192
-        cbo.flush (a1)
-        la a1, Destination3+256
-        cbo.flush (a1)
-        la a1, Destination3+320
-        cbo.flush (a1)
-        la a1, Destination3+384
-        cbo.flush (a1)
-        la a1, Destination3+448
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-	
-        # step 6
-CBOMTest_flush_step6_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-        
-
-        #lw s0, 0(sp)
-        #lw ra, 8(sp)
-        #addi sp, sp, 16
-        #ret
-RVMODEL_HALT
-
-	
-.type memcpy4, @function
-memcpy4:        
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 4 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcpy4_loop:   
-        lw t3, 0(t0)
-        sw t3, 0(t1)
-        addi t0, t0, 4
-        addi t1, t1, 4
-        addi t2, t2, 1
-        blt t2, a2, memcpy4_loop
-        ret
-
-.type memcmp4, @function
-# returns which index mismatch, -1 if none
-memcmp4:
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 4 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp4_loop:
-        lw t3, 0(t0)
-        lw t4, 0(t1)
-        bne t3, t4, memcmp4_ne
-        addi t0, t0, 4
-        addi t1, t1, 4
-        addi t2, t2, 1
-        blt t2, a2, memcmp4_loop
-        li a0, -1
-        ret
-memcmp4_ne:
-        mv a0, t2
-        ret
-
-RVTEST_CODE_END
-        
-
-RVTEST_DATA_BEGIN
-# Input data section.
-#.data
-.align 7
-
-DeadBeafData1:
-        .fill 128, 4, 0xdeadbeef
-SourceData:
-        .int 0, 1, 2, 3, 4, 5, 6, 7
-        .int 8, 9, 10, 11, 12, 13, 14, 15
-        .int 16, 17, 18, 19, 20, 21, 22, 23
-        .int 24, 25, 26, 27, 28, 29, 30, 31
-        .int 32, 33, 34, 35, 36, 37, 38, 39
-        .int 40, 41, 42, 43, 44, 45, 46, 47
-        .int 48, 49, 50, 51, 52, 53, 54, 55
-        .int 56, 57, 58, 59, 60, 61, 62, 63
-        .int 64, 65, 66, 67, 68, 69, 70, 71
-        .int 72, 73, 74, 75, 76, 77, 78, 79
-        .int 80, 81, 82, 83, 84, 85, 86, 87
-        .int 88, 89, 90, 91, 92, 93, 94, 95
-        .int 96, 97, 98, 99, 100, 101, 102, 103
-        .int 104, 105, 106, 107, 108, 109, 110, 111
-        .int 112, 113, 114, 115, 116, 117, 118, 119
-        .int 120, 121, 122, 123, 124, 125, 126, 127
-
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-        .fill 28, 4, 0xdeadbeef   # this is annoying, but RVMODEL_DATA_END and BEGIN insert
-        # 4 bytes.  This needs to be aligned to a cacheline
-
-        .align 6
-Destination1:
-        .fill 128, 4, 0xdeadbeef
-Destination2:   
-        .fill 128, 4, 0xdeadbeef
-Destination3:
-        .fill 128, 4, 0xdeadbeef
-signature:
-        .fill 16, 4, 0x0bad0bad
-	
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-RVMODEL_DATA_END
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
deleted file mode 100644
index 2df8c246f..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-cboz-01.S
+++ /dev/null
@@ -1,379 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-cache-management-tests 
-// invalidate, clean, and flush
-//
-// Author: Rose Thompson <rose@rosethompson.net>
-//
-// Created 22 August 2023
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-# Purpose: Tests the Zicboz cache instruction which all operate on cacheline
-#          granularity blocks of memory.  The instruction cbo.zero allocates a cacheline
-#          and writes 0 to each byte.  A dirty cacheline is overwritten, any data in main
-#          memory is over written.        
-# -----------
-# Copyright (c) 2020. RISC-V International. All rights reserved.
-# SPDX-License-Identifier: BSD-3-Clause
-# -----------
-#
-# This assembly file tests the cbo.zero instruction of the RISC-V Zicboz extension.
-# 
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32I_Zicboz_Zicbom")
-# Test code region
-.section .text.init
-.globl rvtest_entry_point
-	
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
-
-RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
-	
-CBOZTest:
-        # *** TODO
-        # first need to discover the length of the cacheline.
-        # for now assume it is 64 bytes
-
-        #addi sp, sp, -16
-        #sd s0, 0(sp)
-        #sd ra, 8(sp)
-
-	la s0, signature
-
-        ################################################################################
-        # Zero cache line hit overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Zero that region of memory
-        # 4. Verify the second region is all zero.
-
-        # step 1
-CBOZTest_zero_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcpy4
-
-        # step 2
-CBOZTest_zero_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 3
-CBOZTest_zero_step3: 
-        la a1, Destination1
-        cbo.zero (a1)
-        la a1, Destination1+64
-        cbo.zero (a1)
-        la a1, Destination1+128
-        cbo.zero (a1)
-        la a1, Destination1+192
-        cbo.zero (a1)
-        la a1, Destination1+256
-        cbo.zero (a1)
-        la a1, Destination1+320
-        cbo.zero (a1)
-        la a1, Destination1+384
-        cbo.zero (a1)
-        la a1, Destination1+448
-        cbo.zero (a1)
-
-CBOZTest_zero_step4:    
-        # step 4  (should be zero)
-        la a0, ZeroData
-        la a1, Destination1
-        li a2, 128
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-        ################################################################################
-        # Verify cbo.zero miss overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Flush that one line
-        # 4. Zero that one line
-        # 5. Verify the second region is zero
-
-        # step 1
-CBOZTest_miss_zero_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 16
-        jal ra, memcpy4
-
-        # step 2
-CBOZTest_miss_zero_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 3
-CBOZTest_miss_zero_step3: 
-        la a1, Destination1
-        cbo.flush (a1)
-        cbo.zero (a1)
-
-CBOZTest_miss_zero_step4:    
-        # step 4  (should be Invalid)
-        la a0, ZeroData
-        la a1, Destination1
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-	
-        ################################################################################
-        # Verify cbo.zero miss with eviction overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
-        # 2. Repeate 1 four times at 4KiB intervals
-        # 2. Then verify the second region has the same data
-        # 4. Zero each line
-        # 5. Verify the second region is zero
-
-        # step 1
-CBOZTest_eviction_zero_step1_0: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 16
-        jal ra, memcpy4
-
-CBOZTest_eviction_zero_step2_4096: 
-        la a0, SourceData+8
-        la a1, Destination2+4096
-        li a2, 16
-        jal ra, memcpy4
-
-CBOZTest_eviction_zero_step2_8192: 
-        la a0, SourceData+16
-        la a1, Destination2+8192
-        li a2, 16
-        jal ra, memcpy4
-
-CBOZTest_eviction_zero_step2_12288: 
-        la a0, SourceData+24
-        la a1, Destination2+12288
-        li a2, 16
-        jal ra, memcpy4
-
-CBOZTest_eviction_zero_step2_16384: 
-        la a0, SourceData+32
-        la a1, Destination2+16384
-        li a2, 16
-        jal ra, memcpy4
-
-        # step 3
-CBOZTest_eviction_zero_step3_0: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-CBOZTest_eviction_zero_step3_4096: 
-        la a0, SourceData+8
-        la a1, Destination2+4096
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-CBOZTest_eviction_zero_step3_8192: 
-        la a0, SourceData+16
-        la a1, Destination2+8192
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-        
-CBOZTest_eviction_zero_step3_12288: 
-        la a0, SourceData+24
-        la a1, Destination2+12288
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-        
-CBOZTest_eviction_zero_step3_16384: 
-        la a0, SourceData+32
-        la a1, Destination2+16384
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)     # should be -1
-        addi s0, s0, 4
-
-        # step 4
-CBOZTest_eviction_zero_step4: 
-        la a1, Destination2
-        cbo.zero (a1)
-        la a1, Destination2+4096
-        cbo.zero (a1)
-        la a1, Destination2+8192
-        cbo.zero (a1)
-        la a1, Destination2+12288
-        cbo.zero (a1)
-        la a1, Destination2+16384
-        cbo.zero (a1)
-
-CBOZTest_eviction_zero_step5_0:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-CBOZTest_eviction_zero_step5_4096:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+4096
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-        
-CBOZTest_eviction_zero_step5_8192:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+8192
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-
-CBOZTest_eviction_zero_step5_12288:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+12288
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-        
-CBOZTest_eviction_zero_step5_16384:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+16384
-        li a2, 16
-        jal ra, memcmp4
-        sw a0, 0(s0)    # should be -1
-        addi s0, s0, 4
-	
-
-        #ld s0, 0(sp)
-        #ld ra, 8(sp)
-        #addi sp, sp, 16
-        #ret
-RVMODEL_HALT
-
-	
-.type memcpy4, @function
-memcpy4:        
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 4 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcpy4_loop:   
-        lw t3, 0(t0)
-        sw t3, 0(t1)
-        addi t0, t0, 4
-        addi t1, t1, 4
-        addi t2, t2, 1
-        blt t2, a2, memcpy4_loop
-        ret
-
-.type memcmp4, @function
-# returns which index mismatch, -1 if none
-memcmp4:
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 4 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp4_loop:
-        lw t3, 0(t0)
-        lw t4, 0(t1)
-        bne t3, t4, memcmp4_ne
-        addi t0, t0, 4
-        addi t1, t1, 4
-        addi t2, t2, 1
-        blt t2, a2, memcmp4_loop
-        li a0, -1
-        ret
-memcmp4_ne:
-        mv a0, t2
-        ret
-
-RVTEST_CODE_END
-        
-
-RVTEST_DATA_BEGIN
-# Input data section.
-#.data
-.align 7
-
-ZeroData:
-        .fill 128, 4, 0x0
-SourceData:
-        .int 0, 1, 2, 3, 4, 5, 6, 7
-        .int 8, 9, 10, 11, 12, 13, 14, 15
-        .int 16, 17, 18, 19, 20, 21, 22, 23
-        .int 24, 25, 26, 27, 28, 29, 30, 31
-        .int 32, 33, 34, 35, 36, 37, 38, 39
-        .int 40, 41, 42, 43, 44, 45, 46, 47
-        .int 48, 49, 50, 51, 52, 53, 54, 55
-        .int 56, 57, 58, 59, 60, 61, 62, 63
-        .int 64, 65, 66, 67, 68, 69, 70, 71
-        .int 72, 73, 74, 75, 76, 77, 78, 79
-        .int 80, 81, 82, 83, 84, 85, 86, 87
-        .int 88, 89, 90, 91, 92, 93, 94, 95
-        .int 96, 97, 98, 99, 100, 101, 102, 103
-        .int 104, 105, 106, 107, 108, 109, 110, 111
-        .int 112, 113, 114, 115, 116, 117, 118, 119
-        .int 120, 121, 122, 123, 124, 125, 126, 127
-
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-        .fill 28, 4, 0xdeadbeef   # this is annoying, but RVMODEL_DATA_END and BEGIN insert
-        # 4 bytes.  This needs to be aligned to a cacheline
-
-        .align 6
-Destination1:
-        .fill 128, 4, 0xdeadbeef
-Destination2:   
-        .fill 16, 4, 0xdeadbeef
-signature:
-        .fill 16, 4, 0x0bad0bad
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-RVMODEL_DATA_END
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
index b0ad29128..7aac05823 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
index a222a37a5..a43531cc7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s)
 
 INIT_TESTS
 
@@ -32,15 +32,18 @@ TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
 
+# *** several of these appear not to be implemented in the assembler? 
+# I get "assembler messages: error: unkown CSR" with many of them.
+
 GOTO_S_MODE 0x0, 0x0
 
 # Attempt to write 0x111 to each of these CSRs and read the value back
 # should result in an illegal instruction for the write and read, respectively
 
 # High-bit versions storing the upper 32 bits of some CSRs for RV32
-WRITE_READ_CSR mstatush 0x111
-WRITE_READ_CSR menvcfgh 0x111
-WRITE_READ_CSR mseccfgh 0x111
+# WRITE_READ_CSR mstatush 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR menvcfgh 0x111
+# WRITE_READ_CSR mseccfgh 0x111
 WRITE_READ_CSR pmpcfg1 0x111
 WRITE_READ_CSR pmpcfg3 0x111
 WRITE_READ_CSR mcycleh 0x111
@@ -80,11 +83,10 @@ WRITE_READ_CSR mvendorid, 0x111
 WRITE_READ_CSR marchid, 0x111
 WRITE_READ_CSR mimpid, 0x111
 WRITE_READ_CSR mhartid, 0x111
-WRITE_READ_CSR mconfigptr, 0x111
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
 WRITE_READ_CSR mstatus, 0x111
-WRITE_READ_CSR mstatush, 0x111
 WRITE_READ_CSR misa, 0x111
 WRITE_READ_CSR medeleg, 0x111
 WRITE_READ_CSR mideleg, 0x111
@@ -98,11 +100,12 @@ WRITE_READ_CSR mepc, 0x111
 WRITE_READ_CSR mcause, 0x111
 WRITE_READ_CSR mtval, 0x111
 WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-WRITE_READ_CSR menvcfg, 0x111
-WRITE_READ_CSR menvcfgh, 0x111
-WRITE_READ_CSR mseccfg, 0x111
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
 WRITE_READ_CSR pmpcfg0, 0x111
@@ -192,4 +195,4 @@ WRITE_READ_CSR mhpmevent31, 0x111
 
 END_TESTS
 
-TEST_STACK_AND_DATA
+TEST_STACK_AND_DATA
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
index 0835c8c1b..ace47a806 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u)
 
 INIT_TESTS
 
@@ -61,11 +61,10 @@ WRITE_READ_CSR mvendorid, 0xAAA
 WRITE_READ_CSR marchid, 0xAAA
 WRITE_READ_CSR mimpid, 0xAAA
 WRITE_READ_CSR mhartid, 0xAAA
-WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
+# WRITE_READ_CSR mconfigptr, 0xAAA # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
 WRITE_READ_CSR mstatus, 0xAAA
-WRITE_READ_CSR mstatush, 0xAAA
 WRITE_READ_CSR misa, 0xAAA
 WRITE_READ_CSR medeleg, 0xAAA
 WRITE_READ_CSR mideleg, 0xAAA
@@ -79,12 +78,12 @@ WRITE_READ_CSR mepc, 0xAAA
 WRITE_READ_CSR mcause, 0xAAA
 WRITE_READ_CSR mtval, 0xAAA
 WRITE_READ_CSR mip, 0xAAA
+# WRITE_READ_CSR mtinst, 0xAAA # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0xAAA
 
 # Machine Configuration
-WRITE_READ_CSR menvcfg, 0xAAA
-WRITE_READ_CSR menvcfgh, 0xAAA 
-WRITE_READ_CSR senvcfg, 0xAAA 
-WRITE_READ_CSR mseccfg, 0xAAA
+# WRITE_READ_CSR menvcfg, 0xAAA # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0xAAA
 
 # Machine Memory Protection
 WRITE_READ_CSR pmpcfg0, 0xAAA
@@ -174,4 +173,4 @@ WRITE_READ_CSR mhpmevent31, 0xAAA
 
 END_TESTS
 
-TEST_STACK_AND_DATA
+TEST_STACK_AND_DATA
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
index 01097e03f..c13dde253 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",endianness)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
index 94021491d..21ff79d10 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S
index 4b4968be9..2ea73ed35 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc-01.S
@@ -113,7 +113,4 @@ RVMODEL_DATA_BEGIN
 # signature output
 wally_signature:
 .fill 6, 4, -1
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
index bbb9fca5c..6c91f64fc 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
index a6107b4f4..3a4626b64 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",minfo)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
 
 INIT_TESTS
 
@@ -35,7 +35,7 @@ CSR_R_ACCESS mvendorid
 CSR_R_ACCESS marchid 
 CSR_R_ACCESS mimpid 
 CSR_R_ACCESS mhartid 
-CSR_R_ACCESS mconfigptr 
+# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
index b5d8f271a..888011ba6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",misa)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
index d18fbd76e..3bdd03ad2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 //
-// WALLY-MMU-SV32
+// WALLY-MMU
 //
 // Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
 //
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mmu)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",mmu)
 
 INIT_TESTS
 
@@ -52,9 +52,9 @@ test_cases:
 # 
 # ---------------------------------------------------------------------------------------------
 
-# =========== test 11.3.1.1 Page Table Translation ===========
+# =========== test 12.3.1.1 Page Table Translation ===========
 
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
+# test 12.3.1.1.1 write page tables / entries to phyiscal memory
 # sv32 Page table (See Figure 12.12***):
 # Level 1 page table, situated at 0x8000D000
 .4byte 0x8000D000, 0x20004C01, write32_test  # points to level 0 page table A
@@ -78,19 +78,19 @@ test_cases:
 .4byte 0x8000F000, 0x200000CF, write32_test # Vaddr 0x0 Paddr 0x80000000: aligned megapage
 .4byte 0x8000F800, 0x200000CF, write32_test # Vaddr 0x80000000 Paddr 0x80000000: aligned megapage (program and data memory)
 
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
+# test 12.3.1.1.2 write values to Paddrs in each page
+# each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments.
 # when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
-.4byte 0x800AAAA8, 0xBEEF0055, write32_test # 11.3.1.1.4 megapage
-.4byte 0x800FFAC0, 0xBEEF0033, write32_test # 11.3.1.3.2 
-.4byte 0x800E3130, 0xBEEF0077, write32_test # 11.3.1.3.2
-.4byte 0x808017E0, 0xBEEF0099, write32_test # 11.3.1.1.4 kilopage
-.4byte 0x80805EA0, 0xBEEF0440, write32_test # 11.3.1.3.3
-.4byte 0x80803AA0, 0xBEEF0BB0, write32_test # 11.3.1.3.7
+.4byte 0x800AAAA8, 0xBEEF0055, write32_test # 12.3.1.1.4 megapage
+.4byte 0x800FFAC0, 0xBEEF0033, write32_test # 12.3.1.3.2 
+.4byte 0x800E3130, 0xBEEF0077, write32_test # 12.3.1.3.2
+.4byte 0x808017E0, 0xBEEF0099, write32_test # 12.3.1.1.4 kilopage
+.4byte 0x80805EA0, 0xBEEF0440, write32_test # 12.3.1.3.3
+.4byte 0x80803AA0, 0xBEEF0BB0, write32_test # 12.3.1.3.7
 .4byte 0x8000FFA0, 0x11100393, write32_test # write executable code for "li x7, 0x111; ret" to executable region.
-.4byte 0x8000FFA4, 0x00008067, write32_test # Used for 11.3.1.3.1, 11.3.1.3.2
+.4byte 0x8000FFA4, 0x00008067, write32_test # Used for 12.3.1.3.1, 12.3.1.3.2
 
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
+# test 12.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
 .4byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation.
 .4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
 .4byte 0x800AAAA8, 0xBEEF0055, read32_test
@@ -102,38 +102,38 @@ test_cases:
 .4byte 0x8000FFA0, 0x11100393, read32_test
 .4byte 0x8000FFA4, 0x00008067, read32_test
 
-# test 11.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
+# test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
 .4byte 0x8000D, 0x0, goto_sv32 # satp.MODE = sv32, Nothing written to output
 .4byte 0x4AAAA8, 0xBEEF0055, read32_test    # megapage at Vaddr 0x400000, Paddr 0x80000000
 .4byte 0xBFF7E0, 0xBEEF0099, read32_test    # kilopage at Vaddr 0xBFF000, Paddr 0x80201000
 
-# =========== test 11.3.1.2 page fault tests ===========
+# =========== test 12.3.1.2 page fault tests ===========
 
-# test 11.3.1.2.1 load page fault if upper bits of Vaddr are not the same
+# test 12.3.1.2.1 load page fault if upper bits of Vaddr are not the same
 # Not tested in rv32/sv32
 
-# test 11.3.1.2.2 load page fault when reading an address where the valid flag is zero
+# test 12.3.1.2.2 load page fault when reading an address where the valid flag is zero
 .4byte 0x6000, 0x0, read32_test
 
-# test 11.3.1.2.3 store page fault if PTE has W and ~R flags set
+# test 12.3.1.2.3 store page fault if PTE has W and ~R flags set
 .4byte 0x2000, 0x0, write32_test
 
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
+# test 12.3.1.2.4 Fault if last level PTE is a pointer
 .4byte 0x0200, 0x0, read32_test
 
-# test 11.3.1.2.5 load page fault on misaligned pages
+# test 12.3.1.2.5 load page fault on misaligned pages
 .4byte 0xC00000, 0x0, read32_test   # misaligned megapage
 
-# =========== test 11.3.1.3 PTE Protection flags ===========
+# =========== test 12.3.1.3 PTE Protection flags ===========
 
-# test 11.3.1.3.1 User flag == 0
-# *** reads on pages with U=0 already tested in 11.3.1.1.4
+# test 12.3.1.3.1 User flag == 0
+# *** reads on pages with U=0 already tested in 12.3.1.1.4
 .4byte 0x40FFA0, 0x111, executable_test           # fetch success when U=0, priv=S
 .4byte 0x80400000, 0x1, goto_u_mode             # go to U mode, return to VPN 0x80400000 where PTE.U = 1. 0x9 written to output
 .4byte 0xBFFC80, 0xBEEF0550, read32_test    # load page fault when U=0, priv=U
 .4byte 0x40FFA0, 0xbad, executable_test           # instr page fault when U=0, priv=U
 
-# test 11.3.1.3.2 User flag == 1
+# test 12.3.1.3.2 User flag == 1
 .4byte 0x804FFAC0, 0xBEEF0033, read32_test  # read success when U=1, priv=U
 .4byte 0x80000000, 0x1, goto_s_mode             # go back to S mode, return to VPN 0x80000000 where PTE.U = 0. 0x8 written to output
 .4byte 0x0, 0x3, write_mxr_sum                # set sstatus.[MXR, SUM] = 11
@@ -142,61 +142,58 @@ test_cases:
 .4byte 0x0, 0x2, write_mxr_sum                # set sstatus.[MXR, SUM] = 10.
 .4byte 0x804FFAC0, 0xBEEF0033, read32_test  # load page fault when U-1, priv=S, sstatus.SUM=0
 
-# test 11.3.1.3.3 Read flag
-# *** reads on pages with R=1 already tested in 11.3.1.1.4
+# test 12.3.1.3.3 Read flag
+# *** reads on pages with R=1 already tested in 12.3.1.1.4
 .4byte 0x0, 0x1, write_mxr_sum            # set sstatus.[MXR, SUM] = 01.
 .4byte 0x5EA0, 0xBEEF0440, read32_test  # load page fault when R=0, sstatus.MXR=0
 .4byte 0x0, 0x3, write_mxr_sum            # set sstatus.[MXR, SUM] = 11.
 .4byte 0x5EA0, 0xBEEF0440, read32_test  # read success when R=0, MXR=1, X=1
 
-# test 11.3.1.3.4 Write flag
+# test 12.3.1.3.4 Write flag
 .4byte 0xBFF290, 0xBEEF0110, write32_test    # write success when W=1
 .4byte 0xBFF290, 0xBEEF0110, read32_test    # check write success by reading
 .4byte 0x5B78, 0xBEEF0CC0, write32_test      # store page fault when W=0
 
-# test 11.3.1.3.5 eXecute flag
-# *** fetches on pages with X = 1 already tested in 11.3.1.3.1
+# test 12.3.1.3.5 eXecute flag
+# *** fetches on pages with X = 1 already tested in 12.3.1.3.1
 .4byte 0xBFFDE0, 0xbad, executable_test             # instr page fault when X=0 
 
-# In the following two tests, SVADU is not supported, so the software handles the A/D bits
-# Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits
-
-# test 11.3.1.3.6 Accessed flag == 0
+# test 12.3.1.3.6 Accessed flag == 0
 .4byte 0x3020, 0xBEEF0770, write32_test # store page fault when A=0
 .4byte 0x3808, 0xBEEF0990, read32_test # load page fault when A=0
 
-# test 11.3.1.3.7 Dirty flag == 0
+# test 12.3.1.3.7 Dirty flag == 0
 .4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0
 .4byte 0x4AA0, 0xBEEF0BB0, read32_test # read success when D=0
 
-# =========== test 11.3.1.4 SATP Register ===========
+# =========== test 12.3.1.4 SATP Register ===========
 
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
+# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
 // *** .4byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write32_test # write identical value to global PTE to make sure it's still in the TLB
 .4byte 0x8000F, 0x11, goto_sv32 # go to SV39 on a second, very minimal page table
 .4byte 0xE3130, 0xBEEF0077, read32_test # Read success of old written value from a new page table mapping 
 
-# test 11.3.1.4.2 Test Global mapping
+# test 12.3.1.4.2 Test Global mapping
 // ***.4byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read32_test # read success of global PTE undefined in current mapping.
 
 
-# =========== test 11.3.1.5 STATUS Registers ===========
+# =========== test 12.3.1.5 STATUS Registers ===========
 
-# test 11.3.1.5.1 mstatus.mprv translation
+# test 12.3.1.5.1 mstatus.mprv translation
 # *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
 .4byte 0x8000D, 0x0, goto_sv32 // go back to old, extensive page table
 .4byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
 .4byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
 .4byte 0xBFF7E0, 0xBEEF0099, read32_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
 
-# test 11.3.1.5.2 mstatus.mprv clearing
+# test 12.3.1.5.2 mstatus.mprv clearing
 # mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
 .4byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
 .4byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
 .4byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
 
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
+# test 12.3.1.5.3 sstatus.mxr read
+# this bitfield already tested in 12.3.1.3.3
 
 # terminate tests
 .4byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
deleted file mode 100644
index f4c30a8e6..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
+++ /dev/null
@@ -1,217 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-MMU-SV32
-//
-// Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
-//
-// Created 2021-06-15
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "WALLY-TEST-LIB-32.h" 
-
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu)
-
-INIT_TESTS
-
-TRAP_HANDLER m
-
-j run_test_loop // begin test loop/table tests instead of executing inline code.
-
-INIT_TEST_TABLE
-
-TEST_STACK_AND_DATA
-
-.align 2
-test_cases:
-# ---------------------------------------------------------------------------------------------
-# Test Contents
-#
-#   Here is where the actual tests are held, or rather, what the actual tests do.
-#   each entry consists of 3 values that will be read in as follows:
-#   
-#   '.4byte [x28 Value], [x29 Value], [x30 value]'
-#                     or
-#   '.4byte [address], [value], [test type]'
-#
-#   The encoding for x30 test type values can be found in the test handler in the framework file
-# 
-# ---------------------------------------------------------------------------------------------
-
-# =========== test 11.3.1.1 Page Table Translation ===========
-
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
-# sv32 Page table (See Figure 12.12***):
-# Level 1 page table, situated at 0x8000D000
-.4byte 0x8000D000, 0x20004C01, write32_test  # points to level 0 page table A
-.4byte 0x8000D004, 0x200000CB, write32_test  # Vaddr 0x400000 Paddr 0x80000000: aligned megapage, W=0, used for execute tests
-.4byte 0x8000D008, 0x20005401, write32_test  # points to level 0 page table B 
-.4byte 0x8000D00C, 0x000800C7, write32_test  # Vaddr 0xC00000: misaligned megapage
-.4byte 0x8000D800, 0x200000CF, write32_test  # Vaddr 0x80000000 Paddr 0x80000000: aligned megapage (program and data memory)
-.4byte 0x8000D804, 0x200000DF, write32_test  # Vaddr 0x80400000 Paddr 0x80000000: aligned megapage, U=1 (aliased with program and data memory)
-# Level 0 page table A
-.4byte 0x80013000, 0x20007001, write32_test  # Vaddr 0x0000: bad PTE points to level -1 table
-.4byte 0x80013004, 0x202000DF, write32_test  # Vaddr 0x1000 Paddr 0x80800000: aligned kilopage, U=1
-.4byte 0x80013008, 0x202010D5, write32_test  # Vaddr 0x2000: pad PTE has W but not R
-.4byte 0x8001300C, 0x20200817, write32_test  # Vaddr 0x3000: A=0, should cause read fault
-.4byte 0x80013010, 0x20200C57, write32_test  # Vaddr 0x4000: D=0, should cause write fault
-.4byte 0x80013014, 0x202014C9, write32_test  # Vaddr 0x5000 Paddr 80805000: aligned kilopage, W=R=0
-.4byte 0x80013018, 0x0, write32_test         # Vaddr 0x6000: invalid page
-# Level 0 page table B
-.4byte 0x80015FFC, 0x202004C7, write32_test  # Vaddr 0xBFF000 Paddr 0x80801000: aligned kilopage with X=0, U=0
-
-# second page table to check context switches with satp
-.4byte 0x8000F000, 0x200000CF, write32_test # Vaddr 0x0 Paddr 0x80000000: aligned megapage
-.4byte 0x8000F800, 0x200000CF, write32_test # Vaddr 0x80000000 Paddr 0x80000000: aligned megapage (program and data memory)
-
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
-# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
-.4byte 0x800AAAA8, 0xBEEF0055, write32_test # 11.3.1.1.4 megapage
-.4byte 0x800FFAC0, 0xBEEF0033, write32_test # 11.3.1.3.2 
-.4byte 0x800E3130, 0xBEEF0077, write32_test # 11.3.1.3.2
-.4byte 0x808017E0, 0xBEEF0099, write32_test # 11.3.1.1.4 kilopage
-.4byte 0x80805EA0, 0xBEEF0440, write32_test # 11.3.1.3.3
-.4byte 0x8000FFA0, 0x11100393, write32_test # write executable code for "li x7, 0x111; ret" to executable region.
-.4byte 0x8000FFA4, 0x00008067, write32_test # Used for 11.3.1.3.1, 11.3.1.3.2
-.4byte 0x80803658, 0x12345678, write32_test # initialize memory for 11.3.1.3.7(a)
-
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
-.4byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation.
-.4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-.4byte 0x800AAAA8, 0xBEEF0055, read32_test
-.4byte 0x800FFAC0, 0xBEEF0033, read32_test
-.4byte 0x800E3130, 0xBEEF0077, read32_test
-.4byte 0x808017E0, 0xBEEF0099, read32_test
-.4byte 0x80805EA0, 0xBEEF0440, read32_test
-.4byte 0x8000FFA0, 0x11100393, read32_test
-.4byte 0x8000FFA4, 0x00008067, read32_test
-
-# test 11.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
-.4byte 0x8000D, 0x0, goto_sv32 # satp.MODE = sv32, Nothing written to output
-.4byte 0x4AAAA8, 0xBEEF0055, read32_test    # megapage at Vaddr 0x400000, Paddr 0x80000000
-.4byte 0xBFF7E0, 0xBEEF0099, read32_test    # kilopage at Vaddr 0xBFF000, Paddr 0x80201000
-
-# =========== test 11.3.1.2 page fault tests ===========
-
-# test 11.3.1.2.1 load page fault if upper bits of Vaddr are not the same
-# Not tested in rv32/sv32
-
-# test 11.3.1.2.2 load page fault when reading an address where the valid flag is zero
-.4byte 0x6000, 0x0, read32_test
-
-# test 11.3.1.2.3 store page fault if PTE has W and ~R flags set
-.4byte 0x2000, 0x0, write32_test
-
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
-.4byte 0x0200, 0x0, read32_test
-
-# test 11.3.1.2.5 load page fault on misaligned pages
-.4byte 0xC00000, 0x0, read32_test   # misaligned megapage
-
-# =========== test 11.3.1.3 PTE Protection flags ===========
-
-# test 11.3.1.3.1 User flag == 0
-# *** reads on pages with U=0 already tested in 11.3.1.1.4
-.4byte 0x40FFA0, 0x111, executable_test           # fetch success when U=0, priv=S
-.4byte 0x80400000, 0x1, goto_u_mode             # go to U mode, return to VPN 0x80400000 where PTE.U = 1. 0x9 written to output
-.4byte 0xBFFC80, 0xBEEF0550, read32_test    # load page fault when U=0, priv=U
-.4byte 0x40FFA0, 0xbad, executable_test           # instr page fault when U=0, priv=U
-
-# test 11.3.1.3.2 User flag == 1
-.4byte 0x804FFAC0, 0xBEEF0033, read32_test  # read success when U=1, priv=U
-.4byte 0x80000000, 0x1, goto_s_mode             # go back to S mode, return to VPN 0x80000000 where PTE.U = 0. 0x8 written to output
-.4byte 0x0, 0x3, write_mxr_sum                # set sstatus.[MXR, SUM] = 11
-.4byte 0x804E3130, 0xBEEF0077, read32_test  # read success when U=1, priv=S, sstatus.SUM=1
-.4byte 0x8040FFA0, 0xbad, executable_test           # instr page fault when U=1, priv=S (with any sstatus.SUM)
-.4byte 0x0, 0x2, write_mxr_sum                # set sstatus.[MXR, SUM] = 10.
-.4byte 0x804FFAC0, 0xBEEF0033, read32_test  # load page fault when U-1, priv=S, sstatus.SUM=0
-
-# test 11.3.1.3.3 Read flag
-# *** reads on pages with R=1 already tested in 11.3.1.1.4
-.4byte 0x0, 0x1, write_mxr_sum            # set sstatus.[MXR, SUM] = 01.
-.4byte 0x5EA0, 0xBEEF0440, read32_test  # load page fault when R=0, sstatus.MXR=0
-.4byte 0x0, 0x3, write_mxr_sum            # set sstatus.[MXR, SUM] = 11.
-.4byte 0x5EA0, 0xBEEF0440, read32_test  # read success when R=0, MXR=1, X=1
-
-# test 11.3.1.3.4 Write flag
-.4byte 0xBFF290, 0xBEEF0110, write32_test    # write success when W=1
-.4byte 0xBFF290, 0xBEEF0110, read32_test    # check write success by reading
-.4byte 0x5B78, 0xBEEF0CC0, write32_test      # store page fault when W=0
-
-# test 11.3.1.3.5 eXecute flag
-# *** fetches on pages with X = 1 already tested in 11.3.1.3.1
-.4byte 0xBFFDE0, 0xbad, executable_test             # instr page fault when X=0 
-
-# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
-# Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
-
-# test 11.3.1.3.6(a) Accessed flag == 0
-.4byte 0x3020, 0xBEEF0770, write32_test     # store page fault when A=0
-.4byte 0x3020, 0xBEEF0770, read32_test  # load page fault when A=0
-
-# test 11.3.1.3.7(a) Dirty flag == 0
-.4byte 0x4658, 0xBEEF0AA0, write32_test # store page fault when D=0
-.4byte 0x4658, 0xDEADBEEF, read32_test  # read success when D=0; default DEADBEEF value wasn't changed
-
-# Now set ADUE bit
-.4byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
-.4byte 0x0, 0x20000000, write_menvcfgh  # set menvcfg.ADUE = 1
-.4byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-
-# Since SVADU is 1, there are no faults when A/D=0
-
-# test 11.3.1.3.6(b) Accessed flag == 0
-.4byte 0x3020, 0xBEEF0770, write32_test # Write success when A=0 and SVADU is enabled
-.4byte 0x3020, 0xBEEF0770, read32_test # Read success when A=0 and SVADU is enabled
-
-# test 11.3.1.3.7(b) Dirty flag == 0
-.4byte 0x4658, 0xBEEF0AA0, write32_test # write successs when D=0 and SVADU is enabled
-.4byte 0x4658, 0xBEEF0AA0, read32_test # read success when D=0
-
-# =========== test 11.3.1.4 SATP Register ===========
-
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
-// *** .4byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write32_test # write identical value to global PTE to make sure it's still in the TLB
-.4byte 0x8000F, 0x11, goto_sv32 # go to SV39 on a second, very minimal page table
-.4byte 0xE3130, 0xBEEF0077, read32_test # Read success of old written value from a new page table mapping 
-
-# test 11.3.1.4.2 Test Global mapping
-// ***.4byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read32_test # read success of global PTE undefined in current mapping.
-
-
-# =========== test 11.3.1.5 STATUS Registers ===========
-
-# test 11.3.1.5.1 mstatus.mprv translation
-# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
-.4byte 0x8000D, 0x0, goto_sv32 // go back to old, extensive page table
-.4byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
-.4byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
-.4byte 0xBFF7E0, 0xBEEF0099, read32_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
-
-# test 11.3.1.5.2 mstatus.mprv clearing
-# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
-.4byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
-.4byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
-.4byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
-
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
-
-# terminate tests
-.4byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
index 4c2f3dcc8..e2865be3e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mtvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
index 856b41b23..febab70ef 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 // WALLY-PERIPH.S
-// 32 bit version
+// 64 bit version
 //
 // Ben Bracker (bbracker@hmc.edu)
 //
@@ -23,7 +23,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
+// this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); 
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
 
 .section .text.init
@@ -224,6 +225,9 @@ main_code: #####
     # load address of trap handler
     la t0, trap_handler
     csrrw x0, mtvec, t0
+    # delegate all external interrupts to machine mode
+    li t0, 0xD00
+    csrrc x0, mideleg, t0
     # set MIE
     li t0, 0x8
     csrrs x0, mstatus, t0
@@ -799,9 +803,96 @@ Intr03BEEF1A:
     1: bne t1,a0,1b
     li a0, 0
 
-    # PLIC Context 1 not in periph because it is unavailable without S mode in rv32imc
-    # See WALLY-periph-S for a version that does test PLIC context 1
+    ####################################################
+    ##### Test 4 - Signs of Life on PLIC Context 1 #####
+    ####################################################
+    li a1, 0x04beef00 # group ID 
+    # clear MEIE (good to turn off while configuring peripherals)
+    li t0, 0x800
+    csrrc x0, mie, t0
+    # ========== Configure PLIC ==========
+    # priority threshold = 0
+    li t0, 0xC200000
+    li t1, 0
+    sw t1, 0(t0)
+    # source 3 (GPIO) priority = 6
+    li t0, 0xC000000
+    li t1, 6
+    sw t1, 0x0C(t0)
+    # source 0xA (UART) priority = 7
+    li t1, 7
+    sw t1, 0x28(t0)
+    # disable sources 3,0xA on context 0
+    li t0, 0x0C002000
+    li t1, 0 
+    sw t1, 0(t0)
+    # enable sources 3,0xA on context 1
+    li t0, 0x0C002080
+    li t1, 0b10000001000  
+    sw t1, 0(t0)
+    # ========== Configure UART ==========
+    # MCR: Loop = 1
+    li t0, 0x10000000
+    li t1, 0b10000
+    sb t1, 4(t0)
+    # LCR: Use 8 data bits plus odd parity bit
+    li t1, 0b00001011
+    sb t1, 3(t0)
+    # IER: Enable Received Data Available Interrupt
+    li t1, 0x01
+    sb t1, 1(t0)
+    # ========== Configure GPIO ==========
+    # raise all input_en
+    li t0, 0x10060000
+    li t1, 0xFFFFFFFF
+    sw t1, 0x04(t0)
+    # raise all output_en
+    sw t1, 0x08(t0)
+    # raise all rise_en
+    sw t1, 0x18(t0)
+    # ========== Execute Test ==========
+    # set MEIE and SEIE
+    li t0, 0xA00
+    csrrs x0, mie, t0
+Intr04BEEF1B:
+    # UART TX 'e'
+    li t0, 0x10000000
+    li t1, 'e'
+    sb t1, 0(t0)
+    # wait to finish
+    li t1, 0b00010000
+    1: bne t1,a0,1b
+    li a0, 0
+Intr04BEEF1C:
+    # GPIO raise pin 19
+    li t0, 0x10060000
+    li t1, 0x00080000
+    sw t1, 0x0C(t0)
+    # wait to finish
+    li t1, 0b00001000
+    1: bne t1,a0,1b
+    li a0, 0
+    # Now let's go bonkers and trigger both!
+Intr04BEEF1D:
+    # TX 'n'
+    li t0, 0x10000000
+    li t1, 'n'
+    sb t1, 0(t0)
+Intr04BEEF1E:
+    # GPIO lower pin 19 raise pin 0
+    li t0, 0x10060000
+    li t1, 0x00000001
+    sw t1, 0x0C(t0)
+    # wait to finish
+    li t1, 0b00011000
+    1: bne t1,a0,1b
+    li a0, 0
+    # ---------------------------------------------------------------------------------------------
 
+//terminate_test:
+//    li a0, 2 // Trap handler behavior (go to machine mode)
+//    ecall //  writes mcause to the output.
+//    csrw mtvec, x4  // restore original trap handler to halt program
 
 RVTEST_CODE_END
 RVMODEL_HALT
@@ -826,7 +917,4 @@ RVMODEL_DATA_BEGIN
 # signature output
 wally_signature:
 .fill 0x200, 8, 0x00000000
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S
deleted file mode 100644
index d87c1a5f4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-s-01.S
+++ /dev/null
@@ -1,922 +0,0 @@
-///////////////////////////////////////////
-// WALLY-PERIPH-S.S
-// 32 bit version including SEIP tests that require supervisor mode
-//
-// Ben Bracker (bbracker@hmc.edu)
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-// Adapted from Imperas RISCV-TEST_SUITE
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-    # ---------------------------------------------------------------------------------------------
-    j main_code
-# 64 byte alignment for vectored traps to align with xtev
-.align 6
-###################
-###################
-trap_handler: #####
-###################
-###################
-    # save registers
-    addi sp, sp, 0x28
-    sw t0, 0x00(sp)
-    sw t1, 0x08(sp)
-    sw t2, 0x10(sp)
-    sw t3, 0x18(sp)
-    sw t4, 0x20(sp)
-
-    # ===================================
-    # ===== Signature Output Format =====
-    # ===================================
-    #
-    # Base address = <wally_signature>+0x40*<intr_num>
-    # Use sigout-translator.py for help with this!
-    #
-    # <offset>: <contents>
-    # 0x00: test ID = 0x<group_num>BEEF<intr_num>
-    # 0x04: mcause (low)  = 0x8000000B (MEIP) or 0x80000009 (SEIP)
-    # 0x08: mcause (high) = 0x00000000
-    # ----- If GPIO -----
-    # 0x0C: claim ID = 3
-    # 0x10: input_val 
-    # 0x14: output_val 
-    # 0x18: incoming rise_ip 
-    # 0x1C: serviced rise_ip = 0
-    # 0x20: incoming fall_ip 
-    # 0x24: serviced fall_ip = 0
-    # 0x28: incoming high_ip 
-    # 0x2C: serviced high_ip = 0
-    # 0x30: incoming low_ip 
-    # 0x34: serviced low_ip  = 0
-    # ----- If UART -----
-    # 0x0C: claim ID = 0xA
-    # 0x10: IIR
-    # 0x14: LSR
-    # 0x18: LSR (after reading LSR)
-    # 0x1C: RBR
-    # 0x20: LSR (after reading RBR too)
-    # 0x24: IIR (after reading everything else)
-    # 0x28: SCR
-
-    # 0x00: test ID = 0x<group_num>BEEF<intr_num>
-    la t0, wally_signature 
-    sub t0, s0, t0 # sigout offset
-    srli t0, t0, 6 # intr_num 
-    add t0, t0, a1
-    sw t0, 0x00(s0)
-
-    # 0x04: mcause (low)  = 0x0000000B (MEIP) or 0x00000009 (SEIP)
-    # 0x08: mcause (high) = 0x80000000
-    csrrc t0, mcause, x0
-    andi t1, t0, 0x7FF
-    sw t0, 0x04(s0)
-    //srli t0,t0,32
-    sw x0, 0x08(s0)
-    # MEIP or SEIP?
-    #     MEIP is on context 0   
-    li t4, 0x0C200004
-    li t0, 0xB 
-    beq t1, t0, meip
-    #     SEIP is on context 1   
-    li t4, 0x0C201004
-    meip:
-
-    # 0x0C: claim ID
-    #    3: GPIO
-    #    A: UART
-    mv t0, t4
-    lw t1, 0(t0)
-    sw t1, 0x0C(s0)
-    li t2, 0xA
-    beq t1, t2, uart_handler
-    li t2, 3
-    bne t1, t2, trap_handler_end
-
-    gpio_handler:
-        # 0x10: input_val 
-        li t0, 0x10060000
-        lw t1, 0x00(t0)
-        sw t1, 0x10(s0)
-        # 0x14: output_val 
-        lw t1, 0x0C(t0)
-        sw t1, 0x14(s0)
-        # 0x18: incoming rise_ip 
-        lw t1, 0x1C(t0)
-        sw t1, 0x18(s0)
-        # 0x1C: serviced rise_ip = 0
-        sw t1, 0x1C(t0)
-        lw t1, 0x1C(t0)
-        sw t1, 0x1C(s0)
-        # 0x20: incoming fall_ip 
-        lw t1, 0x24(t0)
-        sw t1, 0x20(s0)
-        # 0x24: serviced fall_ip = 0
-        sw t1, 0x24(t0)
-        lw t1, 0x24(t0)
-        sw t1, 0x24(s0)
-        # 0x28: incoming high_ip 
-        lw t1, 0x2C(t0)
-        sw t1, 0x28(s0)
-        # 0x2C: serviced high_ip = 0
-        sw t1, 0x2C(t0)
-        lw t1, 0x2C(t0)
-        sw t1, 0x2C(s0)
-        # 0x30: incoming low_ip 
-        lw t1, 0x34(t0)
-        sw t1, 0x30(s0)
-        # 0x34: serviced low_ip  = 0
-        sw t1, 0x34(t0)
-        lw t1, 0x34(t0)
-        sw t1, 0x34(s0)
-        # disable high_ie and low_ie so interrupt 
-        # is not taken again immediately
-        li t1, 0
-        sw t1, 0x28(t0)
-        sw t1, 0x30(t0)
-        # signal to main code that gpio was serviced
-        ori a0, a0, 0b00001000
-        # signal to plic that gpio was serviced
-        mv t0, t4
-        li t1, 3
-        sw t1, 0(t0)
-        j trap_handler_end
-
-    uart_handler:
-        # 0x10: IIR
-        li t0, 0x10000000
-        lbu t1, 2(t0)
-        sw t1, 0x10(s0)
-        # 0x14: LSR
-        lbu t1, 5(t0)
-        sw t1, 0x14(s0)
-        # 0x18: LSR (after reading LSR)
-        lbu t1, 5(t0)
-        sw t1, 0x18(s0)
-        # 0x1C: RBR
-        lbu t1, 0(t0)
-        sw t1, 0x1C(s0)
-        # 0x20: LSR (after reading RBR)
-        lbu t1, 5(t0)
-        sw t1, 0x20(s0)
-        # 0x24: IIR (after reading everything else)
-        lbu t1, 2(t0)
-        sw t1, 0x24(s0)
-        # 0x28: SCR
-        lbu t1, 7(t0)
-        sw t1, 0x28(s0)
-        # signal to main code that uart was serviced
-        ori a0, a0, 0b00010000
-        # signal to plic that uart was serviced
-        mv t0, t4
-        li t1, 0xA
-        sw t1, 0(t0)
-    
-    trap_handler_end:
-    # increment signature pointer
-    addi s0,s0,0x40
-    # restore vars
-    lw t0, 0x00(sp)
-    lw t1, 0x08(sp)
-    lw t2, 0x10(sp)
-    lw t3, 0x18(sp)
-    lw t4, 0x20(sp)
-    addi sp, sp, SEXT_IMM(-0x28)
-    mret
-
-################
-################
-main_code: #####
-################
-################
-
-    ##########################
-    ##### Initialization #####
-    ##########################
-    # ========== Global Vars ==========
-    la s0, wally_signature # signature output base adr 
-    la sp, stack           # stack pointer
-    li a0, 0               # interrupt complete flag
-    # ========== Configure Privileged Unit ==========
-    # load address of trap handler
-    la t0, trap_handler
-    csrrw x0, mtvec, t0
-    # delegate all external interrupts to machine mode
-    li t0, 0xD00
-    csrrc x0, mideleg, t0
-    # set MIE
-    li t0, 0x8
-    csrrs x0, mstatus, t0
-
-    ##################################
-    ##### Test 1 - Signs of Life #####
-    ##################################
-    li a1, 0x01beef00 # group ID 
-    # clear MEIE (good to turn off while configuring peripherals)
-    li t0, 0x800
-    csrrc x0, mie, t0
-    # ========== Configure PLIC ==========
-    # priority threshold = 0
-    li t0, 0xC200000
-    li t1, 0
-    sw t1, 0(t0)
-    # source 3 (GPIO) priority = 6
-    li t0, 0xC000000
-    li t1, 6
-    sw t1, 0x0C(t0)
-    # source 0xA (UART) priority = 7
-    li t1, 7
-    sw t1, 0x28(t0)
-    # enable sources 3,0xA
-    li t0, 0x0C002000
-    li t1, 0b10000001000 
-    sw t1, 0(t0)
-    # ========== Configure UART ==========
-    # MCR: Loop = 1
-    li t0, 0x10000000
-    li t1, 0b10000
-    sb t1, 4(t0)
-    # LCR: Use 8 data bits plus odd parity bit
-    li t1, 0b00001011
-    sb t1, 3(t0)
-    # IER: Enable Received Data Available Interrupt
-    li t1, 0x01
-    sb t1, 1(t0)
-    # ========== Configure GPIO ==========
-    # raise all input_en
-    li t0, 0x10060000
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # raise all output_en
-    sw t1, 0x08(t0)
-    # raise all rise_en
-    sw t1, 0x18(t0)
-    # ========== Execute Test ==========
-    # set MEIE
-    li t0, 0x800
-    csrrs x0, mie, t0
-Intr01BEEF00:
-    # UART TX 'h'
-    li t0, 0x10000000
-    li t1, 'h'
-    sb t1, 0(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr01BEEF01:
-    # GPIO raise pin 19
-    li t0, 0x10060000
-    li t1, 0x00080000
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # Now let's go bonkers and trigger both!
-Intr01BEEF02:
-    # TX 'e'
-    li t0, 0x10000000
-    li t1, 'e'
-    sb t1, 0(t0)
-Intr01BEEF03:
-    # GPIO lower pin 19 raise pin 0
-    li t0, 0x10060000
-    li t1, 0x00000001
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00011000
-    1: bne t1,a0,1b
-    li a0, 0
-    
-    ##################################
-    ##### Test 2 - GPIO Testing  #####
-    ##################################
-    li a1, 0x02beef00 # group ID 
-    # clear MEIE
-    li t0, 0x800
-    csrrc x0, mie, t0
-    # ========== Configure PLIC ==========
-    # priority threshold = 0
-    li t0, 0xC200000
-    li t1, 0
-    sw t1, 0(t0)
-    # source 3 (GPIO) priority = 1
-    li t0, 0xC000000
-    li t1, 1
-    sw t1, 0x0C(t0)
-    # enable source 3
-    li t0, 0x0C002000
-    li t1, 0b1000 
-    sw t1, 0(t0)
-    # ========== Input Enables ==========
-    # Note that this inherits
-    # a bit of state from the previous test.
-    # Namely output_val = 0x00000001
-    #
-    # enable some inputs
-    li t0, 0x10060000
-    li t1, 0x0000FFFF
-    sw t1, 0x04(t0)
-    # enable all outputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x08(t0)
-    # enable all rising edge interrupts
-    sw t1, 0x18(t0)
-    # set MEIE
-    li t1, 0x800
-    csrrs x0, mie, t1
-    # raise some input-disabled pins
-    # interrupt should not happen
-    li t1, 0xF0F00001
-    sw t1, 0x0C(t0)
-Intr02BEEF04:
-    # change some input-enabled pins
-    # interrupt should happen
-    li t1, 0x3030F0F0
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr02BEEF05:
-    # enable some different inputs
-    # this itself will cause some rise interrupts
-    li t1, 0xFFFF0000
-    sw t1, 0x04(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Output Enables ==========
-    # enable all fall interrupts
-    li t1, 0xFFFFFFFF
-    sw t1, 0x20(t0)
-Intr02BEEF06:
-    # disable some outputs
-    # should affect input value but not output val register itself
-    # this itself will cause some fall interrupts
-    li t1, 0xFF0000FF
-    sw t1, 0x08(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # change pins whose inputs and/or outputs are disabled
-    # should not cause any rise or fall interrupts
-    li t1, 0x300F0F0F
-    sw t1, 0x0C(t0)
-Intr02BEEF07:
-    # change pins whose inputs and outputs are enabled
-    li t1, 0x0F0F0F0F
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Clear GPIO State ==========
-    # (I've gotten a little annoyed with tests depending
-    # upon the results of previous tests).
-    # disable all interrupts
-    sw x0, 0x18(t0)
-    sw x0, 0x20(t0)
-    sw x0, 0x28(t0)
-    sw x0, 0x30(t0)
-    # enable all inputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # enable all outputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x08(t0)
-    # set initial output state
-    sw x0, 0x0C(t0)
-    # clear all pending interrupts
-    li t1, 0xFFFFFFFF
-    sw t1, 0x1C(t0)
-    sw t1, 0x24(t0)
-    sw t1, 0x2C(t0)
-    sw t1, 0x34(t0)
-    # ========== Rise Interrupt Enables ==========
-    # enable some rising edge interrupts
-    li t1, 0x0000FFFF
-    sw t1, 0x18(t0)
-Intr02BEEF08:
-    # raise some pins
-    li t1, 0x00FFFF00
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr02BEEF09:
-    # raise pins whose rise IEs are disabled
-    # should not cause an interrupt
-    li t1, 0x33FFFF00
-    sw t1, 0x0C(t0)
-    # raise pins whose rise IEs are enabled
-    li t1, 0x33FFFF33
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # =========== Fall Interrupts ===========
-    # (admittedly these are already used elsewhere)
-    # disable all rising edge interrupts
-    li t1, 0
-    sw t1, 0x18(t0)
-    # enable some falling edge interrupts
-    li t1, 0x0000FFFF
-    sw t1, 0x20(t0)
-Intr02BEEF0A:
-    # lower some pins
-    li t1, 0x33000033
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # lower pins whose fall IEs are disabled
-    # and raise a bunch of other pins
-    # should not cause an interrupt
-    li t1, 0x00CCCC33
-    sw t1, 0x0C(t0)
-Intr02BEEF0B:
-    # lower pins whose fall IEs are enabled
-    li t1, 0x00CCCC00
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # =========== High Interrupts ===========
-    # disable all falling edge interrupts
-    li t1, 0
-    sw t1, 0x20(t0)
-    # enable some high_ie's for low pins
-    # should not cause an interrupt
-    li t1, 0xFF0000FF
-    sw t1, 0x28(t0)
-Intr02BEEF0C:
-    # enable some high_ie's for high pins
-    li t1, 0x0000FFFF
-    sw t1, 0x28(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # lower all pins
-    li t1, 0
-    sw t1, 0x0C(t0)
-    # lower any existing high_ip's
-    li t1, 0xFFFFFFFF
-    sw t1, 0x2C(t0)
-    # re-enable some high_ie's
-    li t1, 0xFFFF0000
-    sw t1, 0x28(t0)
-    # raise some pins whose high_ie's are disabled
-    li t1, 0x0000CCCC
-    sw t1, 0x0C(t0)
-    # disable some inputs
-    li t1, 0xFF00FFFF
-    sw t1, 0x04(t0)
-    # raise some pins whose inputs are disabled
-    li t1, 0x00CCCCCC
-    sw t1, 0x0C(t0)
-Intr02BEEF0D:
-    # raise some pins whose high_ie's and inputs are enabled
-    li t1, 0xCCCCCCCC
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # =========== Low Interrupts ===========
-    # disable all high interrupts
-    li t1, 0
-    sw t1, 0x28(t0)
-    # enable all inputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # enable some low_ie's for high pins
-    # should not cause an interrupt
-    li t1, 0xCC0000CC
-    sw t1, 0x30(t0)
-Intr02BEEF0E:
-    # enable some low_ie's for low pins
-    li t1, 0xCCCCFFFF
-    sw t1, 0x30(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # raise all pins
-    li t1, 0xFFFFFFFF
-    sw t1, 0x0C(t0)
-    # lower any existing low_ip's
-    #   actually takes a little time for vals
-    #   to propagate through synchronizer
-    #   so this extra load is a nop effectively
-    li t1, 0xFFFFFFFF
-    sw t1, 0x34(t0)
-    # re-enable some low_ie's
-    li t1, 0xFF0000FF
-    sw t1, 0x30(t0)
-    # lower some pins whose low_ie's are disabled
-    li t1, 0xFF1111FF
-    sw t1, 0x0C(t0)
-Intr02BEEF0F:
-    # disable some inputs of pins whose low_ie's are enabled
-    li t1, 0x0000FFFF
-    sw t1, 0x04(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Clear GPIO State ==========
-    # disable all interrupts
-    sw x0, 0x18(t0)
-    sw x0, 0x20(t0)
-    sw x0, 0x28(t0)
-    sw x0, 0x30(t0)
-    # enable all inputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # enable all outputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x08(t0)
-    # set initial output state
-    sw x0, 0x0C(t0)
-    # clear all pending interrupts
-    li t1, 0xFFFFFFFF
-    sw t1, 0x1C(t0)
-    sw t1, 0x24(t0)
-    sw t1, 0x2C(t0)
-    sw t1, 0x34(t0)
-    # ========== Output XOR Test ==========
-    # enable some inputs
-    li t1, 0x0000FFFF
-    sw t1, 0x04(t0)
-    # enable some outputs
-    li t1, 0xFF0000FF
-    sw t1, 0x08(t0)
-    # enable all rising and falling edge interrupts
-    li t1, 0xFFFFFFFF
-    sw t1, 0x18(t0)
-    sw t1, 0x20(t0)
-Intr02BEEF10:
-    # XOR all outputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x40(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr02BEEF11:
-    # XOR some outputs
-    li t1, 0x33333333
-    sw t1, 0x40(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Clear GPIO State ==========
-    # disable all interrupts
-    sw x0, 0x18(t0)
-    sw x0, 0x20(t0)
-    sw x0, 0x28(t0)
-    sw x0, 0x30(t0)
-    # enable all inputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # enable all outputs
-    li t1, 0xFFFFFFFF
-    sw t1, 0x08(t0)
-    # set initial output state
-    sw x0, 0x0C(t0)
-    # clear XOR
-    li t1, 0x00000000
-    sw t1, 0x40(t0)
-    # clear all pending interrupts
-    li t1, 0xFFFFFFFF
-    sw t1, 0x1C(t0)
-    sw t1, 0x24(t0)
-    sw t1, 0x2C(t0)
-    sw t1, 0x34(t0)
-   
-    ##################################
-    ##### Test 3 - UART Testing  #####
-    ##################################
-    li a1, 0x03beef00 # group ID 
-    # clear MEIE
-    li t0, 0x800
-    csrrc x0, mie, t0
-    # ========== Configure PLIC ==========
-    # priority threshold = 0
-    li t0, 0xC200000
-    li t1, 0
-    sw t1, 0(t0)
-    # source 0xA (UART) priority = 1
-    li t0, 0xC000000
-    li t1, 1
-    sw t1, 0x28(t0)
-    # enable source 0xA
-    li t0, 0x0C002000
-    li t1, 0b10000000000 
-    sw t1, 0(t0)
-    # ========== Transmitter Holding Register Empty Interrupt (THRE) ==========
-    # MCR: Loop = 1
-    li t0, 0x10000000
-    li t1, 0b00010000
-    sb t1, 4(t0)
-    # LCR: Use 8 data bits plus odd parity bit
-    li t1, 0b00001011
-    sb t1, 3(t0)
-    # IER: Disable all interrupts for now
-    li t1, 0x0
-    sb t1, 1(t0)
-    # set MEIE
-    li t1, 0x800
-    csrrs x0, mie, t1
-    # THR: TX 'l'
-    li t1, 'l'
-    sb t1, 0(t0)
-    # wait directly on UART for completion
-    li t1, 0b01100001
-    1: lb t2, 5(t0)
-    bne t1, t2, 1b
-Intr03BEEF12:
-    # IER: enable THR empty intr (ETBEI)
-    li t1, 0b00000010
-    sb t1, 1(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # IER: disable THR empty intr (ETBEI)
-    sb x0, 1(t0)
-    # THR: TX 'l'
-    li t1, 'l'
-    sb t1, 0(t0)
-    # THR: TX 'o'
-    li t1, 'o'
-    sb t1, 0(t0)
-Intr03BEEF13:
-    # IER: enable THR empty intr (ETBEI)
-    li t1, 0b00000010
-    sb t1, 1(t0)
-    # This will take a few cycles before UART finishes TX'ing
-    # If we see SCR modifications in output, it means UART probably
-    # did wait until empty THR before triggering the interrupt.
-    sb t1, 7(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ==========
-    # Clear SCR
-    sb x0, 7(t0)
-Intr03BEEF14:
-    # IER: enable RBR ready intr ERBFI
-    li t1, 0x1
-    sb t1, 1(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr03BEEF15:
-    # THR: TX ' '
-    li t1, 0x20
-    sb t1, 0(t0)
-    # This will take a few cycles before UART finishes RX'ing
-    # If we see SCR modifications in output, it means UART probably
-    # did wait until received data available before triggering the interrupt.
-    li t1, 3
-    sb t1, 7(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr03BEEF16:
-    # THR: TX 't'
-    li t1, 't'
-    sb t1, 0(t0)
-    # Same shenanigans as before, only now we also confirm
-    # that you can read the RBR before new data is available
-    # without messing up the receive interrupt.
-    lb t1, 0(t0) 
-    sb t1, 7(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # MCR: Loop = 0
-    li t1, 0b00000000
-    sb t1, 4(t0)
-    # Clear SCR
-    sb x0, 7(t0)
-    # THR: TX 'h'
-    #   should TX but not not trigger interrupt
-    li t1, 'h'
-    sb t1, 0(t0)
-    # wait directly on UART for completion
-    li t1, 0b01100000
-    1: lb t2, 5(t0)
-    bne t1, t2, 1b
-    # Can use THRE test from before to verify we are transmitting
-    # THR: TX 'e'
-    li t1, 'e'
-    sb t1, 0(t0)
-    # THR: TX 'r'
-    li t1, 'r'
-    sb t1, 0(t0)
-Intr03BEEF17:
-    # IER: enable THR empty intr (ETBEI) and RBR ready intr (ERBFI)
-    li t1, 0b00000011
-    sb t1, 1(t0)
-    sb t1, 7(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # manually wait until transmitter finishes before enabling loop mode
-    li t1, 0b01100000
-    1: lb t2, 5(t0)
-    bne t1, t2, 1b
-    # MCR: Loop = 1
-    li t1, 0b00010000
-    sb t1, 4(t0)
-Intr03BEEF18:
-Intr03BEEF19:
-    # THR: TX 'e'
-    li t1, 'e'
-    sb t1, 0(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # wait to finish again
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ========== Receiver Line Status Intr (ELSI) & Overrun Error (OE) ==========
-    # IER: Enable Receiver Line Status Intr (ELSI)
-    li t1, 0b00000100
-    sb t1, 1(t0)
-    li t1, 0xFF
-    sb t1, 7(t0)
-    # We can't cause all kinds of interesting errors, but at least we can
-    # cause an overrun error by transmitting twice without reading.
-Intr03BEEF1A:
-    # THR: TX '\n'
-    li t1, 0xD
-    sb t1, 0(t0)
-    # THR: TX 'G'
-    li t1, 'G'
-    sb t1, 0(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-
-    ####################################################
-    ##### Test 4 - Signs of Life on PLIC Context 1 #####
-    ####################################################
-    li a1, 0x04beef00 # group ID 
-    # clear MEIE (good to turn off while configuring peripherals)
-    li t0, 0x800
-    csrrc x0, mie, t0
-    # ========== Configure PLIC ==========
-    # priority threshold = 0
-    li t0, 0xC200000
-    li t1, 0
-    sw t1, 0(t0)
-    # source 3 (GPIO) priority = 6
-    li t0, 0xC000000
-    li t1, 6
-    sw t1, 0x0C(t0)
-    # source 0xA (UART) priority = 7
-    li t1, 7
-    sw t1, 0x28(t0)
-    # disable sources 3,0xA on context 0
-    li t0, 0x0C002000
-    li t1, 0 
-    sw t1, 0(t0)
-    # enable sources 3,0xA on context 1
-    li t0, 0x0C002080
-    li t1, 0b10000001000  
-    sw t1, 0(t0)
-    # ========== Configure UART ==========
-    # MCR: Loop = 1
-    li t0, 0x10000000
-    li t1, 0b10000
-    sb t1, 4(t0)
-    # LCR: Use 8 data bits plus odd parity bit
-    li t1, 0b00001011
-    sb t1, 3(t0)
-    # IER: Enable Received Data Available Interrupt
-    li t1, 0x01
-    sb t1, 1(t0)
-    # ========== Configure GPIO ==========
-    # raise all input_en
-    li t0, 0x10060000
-    li t1, 0xFFFFFFFF
-    sw t1, 0x04(t0)
-    # raise all output_en
-    sw t1, 0x08(t0)
-    # raise all rise_en
-    sw t1, 0x18(t0)
-    # ========== Execute Test ==========
-    # set MEIE and SEIE
-    li t0, 0xA00
-    csrrs x0, mie, t0
-Intr04BEEF1B:
-    # UART TX 'e'
-    li t0, 0x10000000
-    li t1, 'e'
-    sb t1, 0(t0)
-    # wait to finish
-    li t1, 0b00010000
-    1: bne t1,a0,1b
-    li a0, 0
-Intr04BEEF1C:
-    # GPIO raise pin 19
-    li t0, 0x10060000
-    li t1, 0x00080000
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00001000
-    1: bne t1,a0,1b
-    li a0, 0
-    # Now let's go bonkers and trigger both!
-Intr04BEEF1D:
-    # TX 'n'
-    li t0, 0x10000000
-    li t1, 'n'
-    sb t1, 0(t0)
-Intr04BEEF1E:
-    # GPIO lower pin 19 raise pin 0
-    li t0, 0x10060000
-    li t1, 0x00000001
-    sw t1, 0x0C(t0)
-    # wait to finish
-    li t1, 0b00011000
-    1: bne t1,a0,1b
-    li a0, 0
-    # ---------------------------------------------------------------------------------------------
-
-//terminate_test:
-//    li a0, 2 // Trap handler behavior (go to machine mode)
-//    ecall //  writes mcause to the output.
-//    csrw mtvec, x4  // restore original trap handler to halt program
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-# stack memory (size 16 words)
-.align 3
-stack:
-.fill 16, 8, 0xdeadbeef
-#ifdef rvtest_mtrap_routine
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-#endif
-
-#ifdef rvtest_gpr_save
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-#endif
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-# signature output
-wally_signature:
-.fill 0x200, 8, 0x00000000
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
index 038b9ce00..414fb44b3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
index f48771c5e..a6ed546a8 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
index 2c58b0db8..3000ddcde 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
@@ -36,7 +36,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
@@ -66,7 +66,7 @@ test_cases:
 # ---------------------------------------------------------------------------------------------
 
 # =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
-# Tests memory load, store, and execute permissions
+# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
 
 # | Region | Base Address | Read widths | R   | W   | X   | Cacheable | Idempotent | Atomic |
 # | ROM    | 0x1000       | Any         | YES | NO  | YES | YES       | NO         | NO     |
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
index 4daddb3fb..0f93d4086 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
index 246d6e96d..dd412abe7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-satp-invalid-01.S
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
index d4d6c4f35..64c0567cb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S
deleted file mode 100644
index 19b70829c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S
+++ /dev/null
@@ -1,687 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-spi
-//
-// Author: David_Harris@hmc.edu and Naiche Whyte-Aguayo 
-//
-// Created 2023-02-01
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "WALLY-TEST-LIB-32.h" 
-
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",spi)
-
-INIT_TESTS
-
-TRAP_HANDLER m
-
-j run_test_loop // begin test loop/table tests instead of executing inline code.
-
-INIT_TEST_TABLE
-
-END_TESTS
-
-TEST_STACK_AND_DATA
-
-.align 2
-test_cases:
-# ---------------------------------------------------------------------------------------------
-# Test Contents
-#
-#   Here is where the actual tests are held, or rather, what the actual tests do.
-#   each entry consists of 3 values that will be read in as follows:
-#   
-#   '.4byte [x28 Value], [x29 Value], [x30 value]'
-#                     or
-#   '.4byte [address], [value], [test type]'
-#
-#   The encoding for x30 test type values can be found in the test handler in the framework file
-# ---------------------------------------------------------------------------------------------
-
-.equ SPI, 0x10040000
-.equ sck_div, (SPI+0x00)
-.equ sck_mode, (SPI+0x04)
-.equ cs_id, (SPI+0x10)
-.equ cs_def, (SPI+0x14)
-.equ cs_mode, (SPI+0x18)
-.equ delay0, (SPI+0x28)
-.equ delay1, (SPI+0x2C)
-.equ fmt, (SPI+0x40)
-.equ tx_data, (SPI+0x48)
-.equ rx_data, (SPI+0x4C)
-.equ tx_mark, (SPI+0x50)
-.equ rx_mark, (SPI+0x54)
-.equ ie, (SPI+0x70)
-.equ ip, (SPI+0x74)
-
-# =========== Verify all registers reset to correct values ===========
-
-.4byte sck_div, 0x00000003, read32_test     # sck_div reset to 0x3
-.4byte sck_mode, 0x00000000, read32_test    # sck_mode reset to 0x0
-.4byte cs_id, 0x00000000, read32_test       # cs_id reset to 0x0
-.4byte cs_def, 0x0000000F, read32_test      # cs_def reset to 0x1
-.4byte cs_mode, 0x00000000, read32_test     # cs_mode reset to 0x0
-.4byte delay0, 0x00010001, read32_test      # delay0 reset to [31:24] 0x0, [23:16] 0x1, [15:8] 0x0, [7:0] 0x1
-.4byte delay1, 0x00000001, read32_test      # delay1 reset to 0x1
-.4byte fmt, 0x00080000, read32_test         # fmt reset to [31:20] 0x0, [19:16] 0x8, [15:0] 0x0 for non-flash enabled SPI controllers
-.4byte tx_data, 0x00000000, read32_test     # tx_data [30:0] reset to 0x0, [31] read only
-.4byte tx_mark, 0x00000000, read32_test     # tx_mark reset to 0x0 for non-flash enabled controllers
-.4byte rx_mark, 0x00000000, read32_test     # rx_mark reset to 0x0
-.4byte ie, 0x00000000, read32_test          # ie reset to 0x0
-.4byte ip, 0x00000000, read32_test          # ip reset to 0x0
-
-#test watermark interrupts at beginning where fifo read/write pointers are known b/c reset
-# txwmp raised when # of entries in txfifo < txmark, rxwm raised when # of entries in rxfifo > rxmark
-
-.4byte ip, 0x00000000, read32_test          # txfifo entries not < 0, rxfifo entries not > 0;
-.4byte tx_mark, 0x00000004, write32_test    # set tx_mark to 4
-.4byte rx_mark, 0x00000003, write32_test    # set rx_mark to 3
-.4byte ip, 0x00000001, read32_test          # tx entries < 4, rx entries ! > 3
-.4byte tx_data, 0x41526374, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte ip, 0x00000003, read32_test          # tx entries < 4, rx entries > 3, visual inspection should see tx TransmitFIFOReadIncrement
-
-# txfifo wptr now at 0011, rxfifo wptr at 0000
-
-.4byte rx_mark, 0x00000007, write32_test    # set rx_mark to 7
-.4byte tx_data, 0xD4C3B2A1, spi_burst_send
-.4byte 0x0, 0x00000007, spi_data_wait       # rxfifo full, txfifo wptr at 1000, rxfifo wptr at 0000
-.4byte ip, 0x00000003, read32_test        
-.4byte rx_data, 0x00000074, read32_test
-.4byte rx_data, 0x00000063, read32_test     # clear 2 entries, txfifo wptr at 1000, rxfifo wptr at 0010
-
-
-.4byte tx_data, 0x000000A4, write32_test
-.4byte tx_data, 0x000000B4, write32_test    # tx 1010, rx 0010
-.4byte 0x0, 0x00000007, spi_data_wait       # 8 tx 1010, rx 0010
-.4byte rx_mark, 0x00000004, write32_test
-.4byte rx_data, 0x00000052, read32_test     # 7 rx 0011
-.4byte rx_data, 0x00000041, read32_test     # 6 rx 0100
-.4byte rx_data, 0x000000A1, read32_test     # 5 rx 0101
-.4byte ip, 0x00000003, read32_test          # 5 things in rx fifo
-.4byte rx_data, 0x000000B2, read32_test     # 4 tx 1010, rx 0110
-.4byte ip, 0x00000001, read32_test          # 4 entries in rxfifo, not strictly greater than 4
-
-.4byte rx_mark, 0x00000007, write32_test
-.4byte tx_data, 0xD5C5B5A5, spi_burst_send  # 8 tx1110, rx 0110
-.4byte 0x0, 0x00000007, spi_data_wait       
-
-.4byte rx_mark, 0x00000005, write32_test
-.4byte rx_data, 0x000000C3, read32_test     # tx 1110, rx 0111
-.4byte rx_data, 0x000000D4, read32_test     # tx 1110, rx 1000
-.4byte ip, 0x00000003, read32_test          # 6 entries
-.4byte rx_data, 0x000000A4, read32_test     # tx 1110, rx 1001
-.4byte ip, 0x00000001, read32_test          # 5 entries
-.4byte rx_data, 0x000000B4, read32_test     # tx 1110, rx 1010
-.4byte rx_data, 0x000000A5, read32_test     # tx 1110, rx 1011
-
-.4byte rx_mark, 0x00000006, write32_test
-.4byte tx_data, 0xD7C7B7A7, spi_burst_send
-.4byte 0x0, 0x00000006, spi_data_wait       # tx 0010, rx 1011
-.4byte tx_mark, 0x00000000, write32_test
-.4byte rx_mark, 0x00000000, write32_test
-.4byte rx_data, 0x000000B5, read32_test     # tx 0010, rx 1100
-.4byte rx_data, 0x000000C5, read32_test     # tx 0010, rx 1101
-.4byte rx_data, 0x000000D5, read32_test     # tx 0010, rx 1110
-.4byte rx_data, 0x000000A7, read32_test     # tx 0010, rx 1111
-.4byte rx_data, 0x000000B7, read32_test     # tx 0010, rx 0000
-.4byte rx_data, 0x000000C7, read32_test     # tx 0010, rx 0001
-.4byte ip, 0x00000002, read32_test
-.4byte rx_data, 0x000000D7, read32_test     # tx 0010, rx 1010
-.4byte ip, 0x00000000, read32_test
-.4byte tx_mark, 0x00000000, write32_test
-.4byte rx_mark, 0x00000000, write32_test    # reset watermark registers
-
-# =========== Basic read-write ===========
-
-.4byte tx_data, 0x000000011, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# =========== Different cs_mode, sck_mode, cs_def, sck_div ===========
-
-# Test sck_div
-
-.4byte sck_div, 0x00000101, write32_test    # set sck_div to 0x101
-.4byte tx_data, 0x000000FF, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000FF, read32_test     # read rx_data
-
-# Test min sck_div
-
-.4byte sck_div, 0x000000000, write32_test   #set sck_div to 0
-.4byte tx_data, 0xABACADAE, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x000000AE, read32_test
-.4byte rx_data, 0x000000AD, read32_test
-.4byte rx_data, 0x000000AC, read32_test
-.4byte rx_data, 0x000000AB, read32_test
-
-# min sck_div, sckmode 01
-
-.4byte sck_mode, 0x00000001, write32_test
-.4byte tx_data, 0xABACADAE, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x000000AE, read32_test
-.4byte rx_data, 0x000000AD, read32_test
-.4byte rx_data, 0x000000AC, read32_test
-.4byte rx_data, 0x000000AB, read32_test
-
-#min sck_div, sckmode 10
-.4byte sck_mode, 0x00000002, write32_test
-.4byte tx_data, 0xABACADAE, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x000000AE, read32_test
-.4byte rx_data, 0x000000AD, read32_test
-.4byte rx_data, 0x000000AC, read32_test
-.4byte rx_data, 0x000000AB, read32_test
-
-#min sck_div, sckmode 11
-.4byte sck_mode, 0x00000003, write32_test
-.4byte tx_data, 0xABACADAE, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x000000AE, read32_test
-.4byte rx_data, 0x000000AD, read32_test
-.4byte rx_data, 0x000000AC, read32_test
-.4byte rx_data, 0x000000AB, read32_test
-
-
-# Test phase
-
-.4byte sck_div, 0x00000003, write32_test    # reset sck_div to 0x03 so only sck_mode is different
-.4byte sck_mode, 0x00000001, write32_test   # change phase to falling edge
-.4byte tx_data, 0x000000A0, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000A0, read32_test     # read rx_data
-
-# Test polarity 
-
-.4byte sck_mode, 0x00000000, write32_test   # reset sck phase to rising edge
-.4byte sck_mode, 0x00000002, write32_test   # set sck polarity active low
-.4byte tx_data, 0x0000000B, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x0000000B, read32_test     # read rx_data
-
-# Test phase polarity
-.4byte sck_mode, 0x00000003, write32_test   # set sck mode to 11
-.4byte tx_data, 0x000000F3, write32_test    # place f3 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       # wait for transmission to end
-.4byte rx_data, 0x000000F3, read32_test     # read rx_data
-
-# Test chip select polarity
-
-.4byte sck_mode, 0x00000000, write32_test   # reset sck polarity to active high
-.4byte cs_def, 0x0000000E, write32_test     # set cs[0] to inactive low
-.4byte tx_data, 0x00000079, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000079, read32_test     # read rx_data
-
-# Test chip id 
-
-.4byte cs_def, 0x0000000F, write32_test     # reset all cs to active low
-.4byte cs_id, 0x00000001, write32_test      # select cs[1] 
-.4byte tx_data, 0x00000000, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test cs hold mode
-
-.4byte cs_id, 0x00000000, write32_test      # select cs[0] 
-.4byte cs_mode, 0x00000002, write32_test    # set cs_mode to HOLD
-.4byte tx_data, 0x000000C0, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000C0, read32_test     # read rx_data
-
-# Test cs OFF mode
-
-.4byte cs_mode, 0x00000003, write32_test    # set cs_mode to OFF
-.4byte tx_data, 0x00000011, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# =========== Test delay0 register ===========
-
-# Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay)
-
-.4byte cs_mode, 0x00000000, write32_test    # reset cs_mode to auto, all cs and sck mode settings should be defualt
-.4byte delay0, 0x00010000, write32_test     # set cs-sck delay to 0
-.4byte tx_data, 0x00000020, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000020, read32_test     # read rx_data
-
-# Test cs-sck delay of 0 with sck phase 1 (no delay)
-
-.4byte sck_mode, 0x00000001, write32_test   # set sck_mode[0] to 1 (sck phase = 1)
-.4byte tx_data, 0x00000032, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000032, read32_test     # read rx_data
-
-# Test arbitrary cs-sck delay (sck phase 1)
-
-.4byte delay0, 0x00010005, write32_test     # set cs-sck delay to 5 cycles
-.4byte tx_data, 0x00000048, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000048, read32_test     # read rx_data
-
-# Test arbitrary cs-sck delay (sck phase 0)
-
-.4byte sck_mode, 0x00000000, write32_test   # set sck phase to 0
-.4byte delay0, 0x00010005, write32_test     # set cs-sck delay to AF cycles
-.4byte tx_data, 0x000000AF, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000AF, read32_test     # read rx_data
-
-
-# Test sck-cs delay of 0 with sck phase = 0 (no delay)
-
-.4byte delay0, 0x00000001, write32_test     # set cs-sck delay to 0
-.4byte tx_data, 0x00000050, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000050, read32_test     # read rx_data
-
-# Test sck-cs delay of 0 with sck phase 1 (implicit half cycle delay)
-
-.4byte sck_mode, 0x00000001, write32_test   # set sck_mode[0] to 1 (sck phase = 1)
-.4byte tx_data, 0x0000006B, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x0000006B, read32_test     # read rx_data
-
-# Test arbitrary sck-cs delay (sck phase 1)
-
-.4byte delay0, 0x00050001, write32_test     # set cs-sck delay to A5 cycles
-.4byte tx_data, 0x00000011, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# Test arbitrary sck-cs delay (sck phase 0)
-
-.4byte sck_mode, 0x00000000, write32_test   # set sck phase to 0
-.4byte delay0, 0x00050001, write32_test     # set cs-sck delay to 5 cycles
-.4byte tx_data, 0x00000015, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000015, read32_test     # read rx_data
-
-# SCKCS Delay of 0, SCKMODE 10
-.4byte sck_mode, 0x00000002, write32_test    #set sckmode to 10
-.4byte delay0, 0x00000001, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Arbitrary SCKCS delay, SCKMODE 10
-.4byte delay0, 0x00050001, write32_test    # set sckcs delay to 5
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Long SCKCS delay, SCKMODE 10
-.4byte delay0, 0x00A50001, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# CSSCK Delay 0, SCKMODE 10
-.4byte delay0, 0x00010000, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Arbitrary CSSCK delay, SCKMODE 10
-.4byte delay0, 0x00010005, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Long CSSCK delay, SCKMODE 10
-.4byte delay0, 0x000100A5, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-
-
-# SCKCS Delay of 0, SCKMODE 11
-.4byte sck_mode, 0x00000003, write32_test
-.4byte delay0, 0x00000001, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Arbitrary SCKCS delay, SCKMODE 11
-.4byte delay0, 0x00050001, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Long SCKCS delay, SCKMODE 11
-.4byte delay0, 0x00A50001, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# CSSCK Delay 0, SCKMODE 11
-.4byte delay0, 0x00010000, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Arbitrary CSSCK delay, SCKMODE 11
-.4byte delay0, 0x00010005, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Long CSSCK delay, SCKMODE 11
-.4byte delay0, 0x000100A5, write32_test    # set sckcs delay to 0
-.4byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.4byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# =========== Test delay1 register ===========
-
-# Test inter cs delay 
-
-.4byte sck_mode, 0x00000000, write32_test   #reset sck_mode
-.4byte delay0, 0x00010001, write32_test     # reset delay0 register
-.4byte delay1, 0x00000005, write32_test     # set inter_cs delay to 5
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x44332211, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000011, read32_test
-.4byte rx_data, 0x00000022, read32_test
-.4byte rx_data, 0x00000033, read32_test
-.4byte rx_data, 0x00000044, read32_test     
-
-#test long inter_cs delay
-
-.4byte delay1, 0x000000A5, write32_test
-.4byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x0000007B, write32_test
-.4byte 0x0, 0x00000000, spi_data_wait
-.4byte rx_data, 0x0000007B, read32_test
-
-
-# Test inter_cs delay set to 0
-
-.4byte delay1, 0x00000000, write32_test     # set inter_cs delay to 5
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x54433221, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000021, read32_test
-.4byte rx_data, 0x00000032, read32_test
-.4byte rx_data, 0x00000043, read32_test
-.4byte rx_data, 0x00000054, read32_test
-
-
-# Test inter_xfr delay of 0 (maybe change behavior to half-period instead of period)
-
-.4byte delay1, 0x00000001, write32_test     # reset inter_cs delay to 1
-.4byte cs_mode, 0x00000002, write32_test    # set cs_mode to HOLD 
-.4byte tx_data, 0x99887766, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000066, read32_test
-.4byte rx_data, 0x00000077, read32_test
-.4byte rx_data, 0x00000088, read32_test
-.4byte rx_data, 0x00000099, read32_test
-
-# Test inter_xfr delay 0 with phase = 1
-.4byte sck_mode, 0x00000001, write32_test
-.4byte tx_data, 0x99887766, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x00000066, read32_test
-.4byte rx_data, 0x00000077, read32_test
-.4byte rx_data, 0x00000088, read32_test
-.4byte rx_data, 0x00000099, read32_test
-
-
-# Test arbitrary inter_xfr delay
-
-.4byte delay1, 0x00050001, write32_test     # set inter_xfr delay to 5
-.4byte sck_mode, 0x00000001, write32_test
-.4byte tx_data, 0x98877665, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000065, read32_test
-.4byte rx_data, 0x00000076, read32_test
-.4byte rx_data, 0x00000087, read32_test
-.4byte rx_data, 0x00000098, read32_test
-
-# test long inter_xfr delay
-.4byte delay1, 0x00A50001, write32_test
-.4byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x00000048, write32_test
-.4byte 0x0, 0x00000000, spi_data_wait
-.4byte rx_data, 0x00000048, read32_test
-
-# Test cs-sck delay with cs_mode = HOLD
-
-.4byte delay1, 0x00000001, write32_test     # set inter_xfr delay to 0
-.4byte delay0, 0x00010005, write32_test     # set cs-sck delay to 5 (should have no effect because cs is never inactive)
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0xAABBCCDD, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000DD, read32_test     # read rx_data
-.4byte rx_data, 0x000000CC, read32_test
-.4byte rx_data, 0x000000BB, read32_test
-.4byte rx_data, 0x000000AA, read32_test
-
-# Test sck-cs delay cs_mode = HOLD
-
-.4byte delay0, 0x00000501, write32_test     # set sck-cs delay to 5 (should have no effect because cs is never inactive)
-.4byte tx_data, 0xABBCCDDE, spi_burst_send   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000DE, read32_test     # read rx_data
-.4byte rx_data, 0x000000CD, read32_test
-.4byte rx_data, 0x000000BC, read32_test
-.4byte rx_data, 0x000000AB, read32_test
-
-# Test hold mode deassert conditions
-
-.4byte delay1, 0x00000001, write32_test     # reset delay1 register
-.4byte delay0, 0x00010001, write32_test     # reset delay0 register
-.4byte cs_mode, 0x00000002, write32_test    # set cs_mode to hold
-.4byte tx_data, 0x000000CE, write32_test    # place data into tx_data
-.4byte cs_id, 0x00000001, write32_test      #change selected cs pin. should deassert cs[0] in hold mode
-.4byte cs_def, 0x0000000D, write32_test     # change selected cs pins def value. should deassert cs[1]
-.4byte cs_mode, 0x00000000, write32_test    # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
-.4byte cs_def, 0x0000000F, write32_test     # reset cs_def
-.4byte cs_id, 0x00000000, write32_test      # reset cs_id
-.4byte rx_data, 0x000000CE, read32_test     # clear rx_fifo
-
-# =========== Test frame format (fmt) register ===========
-
-# Test frame length of 4
-
-.4byte delay1, 0x00000001, write32_test     # reset delay1 register
-.4byte delay0, 0x00010001, write32_test     # reset delay0 register
-.4byte sck_mode, 0x00000000, write32_test   #reset sckmode register
-.4byte cs_mode, 0x00000000, write32_test    # set cs_mode to AUTO 
-.4byte fmt, 0x00040000, write32_test        # set frame length to 4
-.4byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x000000F0, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000F0, read32_test     # read rx_data
-
-# Test frame length of 0
-
-#.4byte fmt, 0x00000000, write32_test        # set frame length to 4
-#.4byte tx_data, 0x00000077, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x0101, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x00000077, read32_test     # read rx_data
-
-# test frame length 1 burst
-.4byte fmt, 0x00010000, write32_test
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x80008000, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x00000000, read32_test
-.4byte rx_data, 0x00000080, read32_test
-.4byte rx_data, 0x00000000, read32_test
-.4byte rx_data, 0x00000080, read32_test
-
-
-# Test big endian with frame length = 5
-
-.4byte fmt, 0x00050000, write32_test        # set frame length to 5, big endian
-.4byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x000000A8, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x000000A8, read32_test     # read rx_data
-
-# Test big endian burst with frame length = 5
-
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x03774FFF, spi_burst_send 
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x000000F8, read32_test 
-.4byte rx_data, 0x00000048, read32_test
-.4byte rx_data, 0x00000070, read32_test
-.4byte rx_data, 0x00000000, read32_test
-
-
-
-
-# Test little endian with frame length = 5
-
-.4byte fmt, 0x00050004, write32_test        # set frame length to 5, little-endian
-.4byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0x000000A8, write32_test   # place 8'h11 into tx_data
-.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.4byte rx_data, 0x00000008, read32_test     # read rx_data -> 08
-
-#test little endian burst with frame length = 5
-
-.4byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.4byte tx_data, 0xFF4F7703, spi_burst_send
-.4byte 0x0, 0x00000003, spi_data_wait
-.4byte rx_data, 0x00000003, read32_test     #03
-.4byte rx_data, 0x00000017, read32_test     #17
-.4byte rx_data, 0x0000000F, read32_test     #0F
-.4byte rx_data, 0x0000001F, read32_test     #1F
-
-# Test dual SPI protocol, frame length = 8, big endian
-
-#.4byte fmt, 0x00080001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x000000C8, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test dual SPI protocol, frame length = 4
-
-#.4byte fmt, 0x00040001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x000000A2, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x000000A0, read32_test     # read rx_data
-
-# Test dual SPI protocol, frame length = 5
-
-#.4byte fmt, 0x00050001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x00000075, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x00000074, read32_test     # read rx_data
-
-# Test dual SPI protocol burst, frame length = 5
-#.4byte tx_data, 0x30733FFF, spi_burst_send
-#.4byte 0x0, 0x00000003, spi_data_wait
-#.4byte rx_data, 0x000000FC, read32_test
-#.4byte rx_data, 0x0000003C, read32_test
-#.4byte rx_data, 0x00000070, read32_test
-#.4byte rx_data, 0x00000030, read32_test 
-
-# Test quad SPI protocol, frame length = 5
-
-#.4byte fmt, 0x00050002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x0000003F, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x0000003F, read32_test     # read rx_data
-
-# Test quad SPI protocol, frame length = 4
-
-#.4byte fmt, 0x00040002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x0000000F, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test quad SPI protocol, frame length = 8
-
-#.4byte fmt, 0x00080002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.4byte tx_data, 0x000000F0, write32_test   # place 8'h11 into tx_data
-#.4byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.4byte rx_data, 0x000000F0, read32_test     # read rx_data
-
-
-# =========== Test watermark interrupts ===========
-
-# Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
-
-SETUP_PLIC
-.4byte fmt, 0x00080000, write32_test        # reset format register
-.4byte delay1, 0x0000001, write32_test      # reset delay1 register
-.4byte cs_mode, 0x00000000, write32_test    # reset cs_mode
-.4byte tx_mark, 0x00000001, write32_test    # set transmit watermark to 1 (any entry turns mark off)
-.4byte sck_div, 0x00000100, write32_test    # lower SPI clock rate so read32_tests trigger at correct times
-#.4byte ie, 0x00000000, write32_test         # enable transmit interrupt
-.4byte ip, 0x00000001, read32_test          # tx watermark interupt should be pending
-.4byte 0x0, 0x00000000, readmip_test
-.4byte tx_data, 0x55443322, spi_burst_send    # place 4 entries in transmit fifo
-.4byte ip, 0x00000000, read32_test          # tx watermark interupt should be off 125
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-
-# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
-
-.4byte tx_mark, 0x00000000, write32_test      # set tx_mark to 0
-.4byte rx_data, 0x00000022, read32_test       # clear one entry from rx FIFO
-.4byte rx_mark, 0x00000003, write32_test      # set recieve watermark to 3
-#.4byte ie, 0x0000002, write32_test          # enable receive interrupts
-.4byte ip, 0x00000000, read32_test          # rx interrupts should be low (rx FIFO has 3 entries)
-.4byte rx_mark, 0x00000002, write32_test    # set recieve watermark to 2
-.4byte ip, 0x00000002, read32_test          # recieve interrupt should be high
-.4byte 0x0, 0x00000000, readmip_test
-.4byte rx_data, 0x00000033, read32_test     # clear one more entry from recieve FIFO (2 entries)
-.4byte ip, 0x00000000, read32_test          # receive interrupt should be low
-.4byte rx_data, 0x00000044, read32_test
-.4byte rx_data, 0x00000055, read32_test     # clear rx fifo
-
-
-.4byte tx_mark, 0x00000001, write32_test    # set transmit watermark to 0
-.4byte ie, 0x00000001, write32_test         # enable transmit interrupt
-.4byte ip, 0x00000001, read32_test          # tx watermark interupt should be pending
-.4byte 0x0, 0x00000800, readmip_test
-.4byte ie, 0x00000000, write32_test      # disable tx intr
-.4byte tx_data, 0x55443322, spi_burst_send    # place 4 entries in transmit fifo
-.4byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-
-# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
-
-.4byte tx_mark, 0x00000000, write32_test
-.4byte 0x0, 0x00000000, claim_m_plic_interrupts
-.4byte rx_data, 0x00000022, read32_test       # clear one entry from rx FIFO
-.4byte rx_mark, 0x00000003, write32_test      # set recieve watermark to 3
-.4byte ie, 0x0000002, write32_test          # enable receive interrupts
-.4byte ip, 0x00000000, read32_test          # rx interrupts should be low (rx FIFO has 3 entries)
-.4byte 0x0, 0x00000000, readmip_test
-.4byte rx_mark, 0x00000002, write32_test    # set recieve watermark to 2
-.4byte ip, 0x00000002, read32_test          # recieve interrupt should be high
-.4byte 0x0, 0x00000800, readmip_test
-.4byte rx_data, 0x00000033, read32_test     # clear one more entry from recieve FIFO (2 entries)
-.4byte 0x0, 0x00000000, claim_m_plic_interrupts
-.4byte ip, 0x00000000, read32_test          # receive interrupt should be low
-.4byte 0x0, 0x00000000, readmip_test
-
-
-
-.4byte 0x0, 0x0, terminate_test
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
index 67e11bc31..7c1d609af 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32IAF_Zicsr")
+RVTEST_ISA("RV32IAF")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
 
 INIT_TESTS
@@ -77,4 +77,4 @@ fmv.s ft0, ft0 // should be an illegal instruction with fs set to 00
 
 END_TESTS
 
-TEST_STACK_AND_DATA
+TEST_STACK_AND_DATA
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
index 20f74d660..1fc792a98 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-mie)
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-mie)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
index 60e9c5c8b..81e230273 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
index 224420cb3..aa8be422c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tvm-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tvm)
 
 INIT_TESTS
@@ -42,4 +42,4 @@ sfence.vma x0, x0 // attempt to call sfence should cause illegal instruction wit
 
 END_TESTS
 
-TEST_STACK_AND_DATA
+TEST_STACK_AND_DATA
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
index faa2598f3..15155fb76 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tw)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
index f666c421e..e42ffb6dc 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",stvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
index 2b5daf264..9385e3547 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Sstc_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -34,9 +34,8 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
-WRITE_READ_CSR menvcfgh, 0x80000000 // Enable menvcfg.STCE
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
 // test 5.3.1.4 Basic trap tests 
 
 // instr address misaligned instructions are excluded from this test since they are impossible to cause when compressed instructions are enabled.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
index d779f74fa..4b1e2afa4 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def NO_SAIL=True;",trap-s)
 
 INIT_TESTS
@@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall
 GOTO_S_MODE // Causes U mode ecall
 
 
-// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
-//jal cause_s_soft_interrupt 
+// some interrupts excluded becaus writing MIP is illegal from S mode
+jal cause_s_soft_interrupt 
 jal cause_m_soft_interrupt
 jal cause_m_time_interrupt
 li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
-// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
+// since interrupts are not always enabled,
 jal cause_s_ext_interrupt_GPIO
 li a3, 0x40
 jal cause_m_ext_interrupt
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
index c4041c972..e0f81a2c0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
index 98da8180e..df812db64 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
index 101154923..deba11c29 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
index 2ed238e23..9e19ff202 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr_Zifencei")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
 
 .equ UART, 0x10000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
index 65f564a1e..720d83956 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
 
 INIT_TESTS
@@ -36,20 +36,20 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
 
 // Code copied from test library to cause m time interrupt, with time loop replaced with wfi.
 
-/* Note: the following line might cause problems in the future. If more than 0x100 cycles are needed before the wfi 
+/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi 
  instruction begins, then the program might fall into a loop and run forever*/
-    li x28, 0x100          // Desired offset from the present time
-    mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
-    la x29, 0x02004000    // MTIMECMP register in CLINT
-    la x30, 0x0200BFF8    // MTIME register in CLINT
-    lw x7, 0(x30)         // low word of MTIME
-    lw x31, 4(x30)         // high word of MTIME
-    add x28, x7, x28       // add desired offset to the current time
-    bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-    addi x31, x31, 1       // if wrap, increment most significant word
+li x28, 0x50          // Desired offset from the present time
+mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
+la x29, 0x02004000    // MTIMECMP register in CLINT
+la x30, 0x0200BFF8    // MTIME register in CLINT
+lw x7, 0(x30)         // low word of MTIME
+lw x31, 4(x30)         // high word of MTIME
+add x28, x7, x28       // add desired offset to the current time
+bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+addi x31, x31, 1       // if wrap, increment most significant word
+sw x31,4(x29)          // store into most significant word of MTIMECMP
 
 nowrap:
-    sw x31,4(x29)          // store into most significant word of MTIMECMP
     sw x28, 0(x29)         // store into least significant word of MTIMECMP
 
 auipc ra, 0x0
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/.gitgnore b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/.gitgnore
new file mode 100644
index 000000000..618bc413b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/.gitgnore
@@ -0,0 +1,6 @@
+I/src/env
+M/src/env
+C/src/env
+privilege/src/env
+Zicsr/src/env
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile
new file mode 100644
index 000000000..38d7cba9d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64ic -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag
new file mode 100644
index 000000000..d7032fc71
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/C/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV64I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64I architectural tests
+
+rv64i_sc_tests = \
+ 
+
+rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
+
+target_tests += $(rv64i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile
new file mode 100644
index 000000000..a474441d6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64id -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag
new file mode 100644
index 000000000..261a9a852
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV64IM Makefrag
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64IM architectural tests
+
+rv64im_sc_tests = \
+ 
+rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests))
+
+target_tests += $(rv64im_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/.gitignore b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/.gitignore
new file mode 100644
index 000000000..e69de29bb
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile
new file mode 100644
index 000000000..18dc245c8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag
new file mode 100644
index 000000000..5758ecc33
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/Makefrag
@@ -0,0 +1,40 @@
+# RISC-V Architecture Test RV64I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64I architectural tests
+
+rv64i_sc_tests = \
+	WALLY-ADD \
+    WALLY-SUB \
+    WALLY-SLT \
+	WALLY-SLTU \
+	WALLY-XOR 
+
+
+rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
+
+target_tests += $(rv64i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output
new file mode 100644
index 000000000..7e1ab4344
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-ADD.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000000
+00000001
+00000000
+ffffffff
+ffffffff
+00000001
+00000000
+00000002
+00000000
+00000000
+00000000
+ffffffff
+ffffffff
+00000000
+00000000
+fffffffe
+ffffffff
+393cb5d1
+72ca6f49
+7b12609b
+245889d8
+7f42ac28
+af17a2d3
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output
new file mode 100644
index 000000000..5958e1ed6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLT.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000000
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+00000000
+00000001
+00000000
+00000000
+00000000
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output
new file mode 100644
index 000000000..476470e4a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SLTU.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000000
+00000001
+00000000
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000001
+00000000
+00000000
+00000000
+00000001
+00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output
new file mode 100644
index 000000000..cc7461347
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-SUB.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000000
+ffffffff
+ffffffff
+00000001
+00000000
+00000001
+00000000
+00000000
+00000000
+00000002
+00000000
+ffffffff
+ffffffff
+fffffffe
+ffffffff
+00000000
+00000000
+0f7dc13a
+f51130ed
+bb2485d0
+9633d6e4
+4557352f
+60fe4e94
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output
new file mode 100644
index 000000000..477289586
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/references/WALLY-XOR.reference_output
@@ -0,0 +1,24 @@
+00000000
+00000000
+00000001
+00000000
+ffffffff
+ffffffff
+00000001
+00000000
+00000000
+00000000
+fffffffe
+ffffffff
+ffffffff
+ffffffff
+fffffffe
+ffffffff
+00000000
+00000000
+e6f91511
+a770a807
+87ea008b
+3afeadc9
+3e7f1ce8
+a43d2571
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
new file mode 100644
index 000000000..ed51aca50
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.914370//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
+
+# Testcase 0:  rs1:x20(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x3(0x0000000000000000)
+li x20, MASK_XLEN(0x0000000000000000)
+li x22, MASK_XLEN(0x0000000000000000)
+ADD x3, x20, x22
+sd x3, 0(x6)
+
+# Testcase 1:  rs1:x1(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x21(0x0000000000000001)
+li x1, MASK_XLEN(0x0000000000000000)
+li x4, MASK_XLEN(0x0000000000000001)
+ADD x21, x1, x4
+sd x21, 8(x6)
+
+# Testcase 2:  rs1:x7(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x27(0xffffffffffffffff)
+li x7, MASK_XLEN(0x0000000000000000)
+li x20, MASK_XLEN(0xffffffffffffffff)
+ADD x27, x7, x20
+sd x27, 16(x6)
+
+# Testcase 3:  rs1:x19(0x0000000000000001), rs2:x4(0x0000000000000000), result rd:x13(0x0000000000000001)
+li x19, MASK_XLEN(0x0000000000000001)
+li x4, MASK_XLEN(0x0000000000000000)
+ADD x13, x19, x4
+sd x13, 24(x6)
+
+# Testcase 4:  rs1:x3(0x0000000000000001), rs2:x12(0x0000000000000001), result rd:x27(0x0000000000000002)
+li x3, MASK_XLEN(0x0000000000000001)
+li x12, MASK_XLEN(0x0000000000000001)
+ADD x27, x3, x12
+sd x27, 32(x6)
+
+# Testcase 5:  rs1:x4(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x20(0x0000000000000000)
+li x4, MASK_XLEN(0x0000000000000001)
+li x2, MASK_XLEN(0xffffffffffffffff)
+ADD x20, x4, x2
+sd x20, 40(x6)
+
+# Testcase 6:  rs1:x1(0xffffffffffffffff), rs2:x7(0x0000000000000000), result rd:x31(0xffffffffffffffff)
+li x1, MASK_XLEN(0xffffffffffffffff)
+li x7, MASK_XLEN(0x0000000000000000)
+ADD x31, x1, x7
+sd x31, 48(x6)
+
+# Testcase 7:  rs1:x16(0xffffffffffffffff), rs2:x7(0x0000000000000001), result rd:x24(0x0000000000000000)
+li x16, MASK_XLEN(0xffffffffffffffff)
+li x7, MASK_XLEN(0x0000000000000001)
+ADD x24, x16, x7
+sd x24, 56(x6)
+
+# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x2(0xffffffffffffffff), result rd:x30(0xfffffffffffffffe)
+li x26, MASK_XLEN(0xffffffffffffffff)
+li x2, MASK_XLEN(0xffffffffffffffff)
+ADD x30, x26, x2
+sd x30, 64(x6)
+
+# Testcase 9:  rs1:x20(0x05d51433ade9b2b4), rs2:x4(0x6cf55b158b53031d), result rd:x27(0x72ca6f49393cb5d1)
+li x20, MASK_XLEN(0x05d51433ade9b2b4)
+li x4, MASK_XLEN(0x6cf55b158b53031d)
+ADD x27, x20, x4
+sd x27, 72(x6)
+
+# Testcase 10:  rs1:x21(0x11ebcd49428a1c22), rs2:x10(0x126cbc8f38884479), result rd:x12(0x245889d87b12609b)
+li x21, MASK_XLEN(0x11ebcd49428a1c22)
+li x10, MASK_XLEN(0x126cbc8f38884479)
+ADD x12, x21, x10
+sd x12, 80(x6)
+
+# Testcase 11:  rs1:x15(0x2e2950656fa231e9), rs2:x2(0x80ee526e0fa07a3f), result rd:x20(0xaf17a2d37f42ac28)
+li x15, MASK_XLEN(0x2e2950656fa231e9)
+li x2, MASK_XLEN(0x80ee526e0fa07a3f)
+ADD x20, x15, x2
+sd x20, 88(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
new file mode 100644
index 000000000..134bfe2aa
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.916813//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
+
+# Testcase 0:  rs1:x18(0x0000000000000000), rs2:x9(0x0000000000000000), result rd:x5(0x0000000000000000)
+li x18, MASK_XLEN(0x0000000000000000)
+li x9, MASK_XLEN(0x0000000000000000)
+SLT x5, x18, x9
+sd x5, 0(x6)
+
+# Testcase 1:  rs1:x8(0x0000000000000000), rs2:x25(0x0000000000000001), result rd:x31(0x0000000000000001)
+li x8, MASK_XLEN(0x0000000000000000)
+li x25, MASK_XLEN(0x0000000000000001)
+SLT x31, x8, x25
+sd x31, 8(x6)
+
+# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x12(0xffffffffffffffff), result rd:x20(0x0000000000000000)
+li x16, MASK_XLEN(0x0000000000000000)
+li x12, MASK_XLEN(0xffffffffffffffff)
+SLT x20, x16, x12
+sd x20, 16(x6)
+
+# Testcase 3:  rs1:x10(0x0000000000000001), rs2:x22(0x0000000000000000), result rd:x12(0x0000000000000000)
+li x10, MASK_XLEN(0x0000000000000001)
+li x22, MASK_XLEN(0x0000000000000000)
+SLT x12, x10, x22
+sd x12, 24(x6)
+
+# Testcase 4:  rs1:x19(0x0000000000000001), rs2:x31(0x0000000000000001), result rd:x29(0x0000000000000000)
+li x19, MASK_XLEN(0x0000000000000001)
+li x31, MASK_XLEN(0x0000000000000001)
+SLT x29, x19, x31
+sd x29, 32(x6)
+
+# Testcase 5:  rs1:x21(0x0000000000000001), rs2:x28(0xffffffffffffffff), result rd:x20(0x0000000000000000)
+li x21, MASK_XLEN(0x0000000000000001)
+li x28, MASK_XLEN(0xffffffffffffffff)
+SLT x20, x21, x28
+sd x20, 40(x6)
+
+# Testcase 6:  rs1:x5(0xffffffffffffffff), rs2:x23(0x0000000000000000), result rd:x10(0x0000000000000001)
+li x5, MASK_XLEN(0xffffffffffffffff)
+li x23, MASK_XLEN(0x0000000000000000)
+SLT x10, x5, x23
+sd x10, 48(x6)
+
+# Testcase 7:  rs1:x13(0xffffffffffffffff), rs2:x24(0x0000000000000001), result rd:x14(0x0000000000000001)
+li x13, MASK_XLEN(0xffffffffffffffff)
+li x24, MASK_XLEN(0x0000000000000001)
+SLT x14, x13, x24
+sd x14, 56(x6)
+
+# Testcase 8:  rs1:x27(0xffffffffffffffff), rs2:x21(0xffffffffffffffff), result rd:x3(0x0000000000000000)
+li x27, MASK_XLEN(0xffffffffffffffff)
+li x21, MASK_XLEN(0xffffffffffffffff)
+SLT x3, x27, x21
+sd x3, 64(x6)
+
+# Testcase 9:  rs1:x8(0x983631890063e42f), rs2:x21(0xb2d650af313b32b7), result rd:x15(0x0000000000000001)
+li x8, MASK_XLEN(0x983631890063e42f)
+li x21, MASK_XLEN(0xb2d650af313b32b7)
+SLT x15, x8, x21
+sd x15, 72(x6)
+
+# Testcase 10:  rs1:x19(0xb5d97ef760ef1471), rs2:x28(0xac7c8803e01bbf50), result rd:x14(0x0000000000000000)
+li x19, MASK_XLEN(0xb5d97ef760ef1471)
+li x28, MASK_XLEN(0xac7c8803e01bbf50)
+SLT x14, x19, x28
+sd x14, 80(x6)
+
+# Testcase 11:  rs1:x19(0x66faf98908135d58), rs2:x14(0xb3ab1b2cdf26f517), result rd:x25(0x0000000000000000)
+li x19, MASK_XLEN(0x66faf98908135d58)
+li x14, MASK_XLEN(0xb3ab1b2cdf26f517)
+SLT x25, x19, x14
+sd x25, 88(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
new file mode 100644
index 000000000..d3671a1e5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.917963//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
+
+# Testcase 0:  rs1:x22(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x2(0x0000000000000000)
+li x22, MASK_XLEN(0x0000000000000000)
+li x23, MASK_XLEN(0x0000000000000000)
+SLTU x2, x22, x23
+sd x2, 0(x6)
+
+# Testcase 1:  rs1:x15(0x0000000000000000), rs2:x17(0x0000000000000001), result rd:x29(0x0000000000000001)
+li x15, MASK_XLEN(0x0000000000000000)
+li x17, MASK_XLEN(0x0000000000000001)
+SLTU x29, x15, x17
+sd x29, 8(x6)
+
+# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x30(0xffffffffffffffff), result rd:x18(0x0000000000000001)
+li x16, MASK_XLEN(0x0000000000000000)
+li x30, MASK_XLEN(0xffffffffffffffff)
+SLTU x18, x16, x30
+sd x18, 16(x6)
+
+# Testcase 3:  rs1:x20(0x0000000000000001), rs2:x25(0x0000000000000000), result rd:x1(0x0000000000000000)
+li x20, MASK_XLEN(0x0000000000000001)
+li x25, MASK_XLEN(0x0000000000000000)
+SLTU x1, x20, x25
+sd x1, 24(x6)
+
+# Testcase 4:  rs1:x29(0x0000000000000001), rs2:x2(0x0000000000000001), result rd:x16(0x0000000000000000)
+li x29, MASK_XLEN(0x0000000000000001)
+li x2, MASK_XLEN(0x0000000000000001)
+SLTU x16, x29, x2
+sd x16, 32(x6)
+
+# Testcase 5:  rs1:x11(0x0000000000000001), rs2:x10(0xffffffffffffffff), result rd:x27(0x0000000000000001)
+li x11, MASK_XLEN(0x0000000000000001)
+li x10, MASK_XLEN(0xffffffffffffffff)
+SLTU x27, x11, x10
+sd x27, 40(x6)
+
+# Testcase 6:  rs1:x15(0xffffffffffffffff), rs2:x2(0x0000000000000000), result rd:x26(0x0000000000000000)
+li x15, MASK_XLEN(0xffffffffffffffff)
+li x2, MASK_XLEN(0x0000000000000000)
+SLTU x26, x15, x2
+sd x26, 48(x6)
+
+# Testcase 7:  rs1:x27(0xffffffffffffffff), rs2:x29(0x0000000000000001), result rd:x26(0x0000000000000000)
+li x27, MASK_XLEN(0xffffffffffffffff)
+li x29, MASK_XLEN(0x0000000000000001)
+SLTU x26, x27, x29
+sd x26, 56(x6)
+
+# Testcase 8:  rs1:x14(0xffffffffffffffff), rs2:x7(0xffffffffffffffff), result rd:x18(0x0000000000000000)
+li x14, MASK_XLEN(0xffffffffffffffff)
+li x7, MASK_XLEN(0xffffffffffffffff)
+SLTU x18, x14, x7
+sd x18, 64(x6)
+
+# Testcase 9:  rs1:x3(0xf689a4a5ffda0336), rs2:x27(0xfa83ada4a2121ac5), result rd:x24(0x0000000000000001)
+li x3, MASK_XLEN(0xf689a4a5ffda0336)
+li x27, MASK_XLEN(0xfa83ada4a2121ac5)
+SLTU x24, x3, x27
+sd x24, 72(x6)
+
+# Testcase 10:  rs1:x31(0xfca055362169df82), rs2:x22(0x66dd779403c54c71), result rd:x14(0x0000000000000000)
+li x31, MASK_XLEN(0xfca055362169df82)
+li x22, MASK_XLEN(0x66dd779403c54c71)
+SLTU x14, x31, x22
+sd x14, 80(x6)
+
+# Testcase 11:  rs1:x23(0x00de59f550f0fc2b), rs2:x25(0x03a8987936a98d74), result rd:x1(0x0000000000000001)
+li x23, MASK_XLEN(0x00de59f550f0fc2b)
+li x25, MASK_XLEN(0x03a8987936a98d74)
+SLTU x1, x23, x25
+sd x1, 88(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
new file mode 100644
index 000000000..bd71d8ba0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.915580//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
+
+# Testcase 0:  rs1:x4(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x13(0x0000000000000000)
+li x4, MASK_XLEN(0x0000000000000000)
+li x23, MASK_XLEN(0x0000000000000000)
+SUB x13, x4, x23
+sd x13, 0(x6)
+
+# Testcase 1:  rs1:x7(0x0000000000000000), rs2:x9(0x0000000000000001), result rd:x12(0xffffffffffffffff)
+li x7, MASK_XLEN(0x0000000000000000)
+li x9, MASK_XLEN(0x0000000000000001)
+SUB x12, x7, x9
+sd x12, 8(x6)
+
+# Testcase 2:  rs1:x29(0x0000000000000000), rs2:x24(0xffffffffffffffff), result rd:x16(0x0000000000000001)
+li x29, MASK_XLEN(0x0000000000000000)
+li x24, MASK_XLEN(0xffffffffffffffff)
+SUB x16, x29, x24
+sd x16, 16(x6)
+
+# Testcase 3:  rs1:x27(0x0000000000000001), rs2:x29(0x0000000000000000), result rd:x30(0x0000000000000001)
+li x27, MASK_XLEN(0x0000000000000001)
+li x29, MASK_XLEN(0x0000000000000000)
+SUB x30, x27, x29
+sd x30, 24(x6)
+
+# Testcase 4:  rs1:x22(0x0000000000000001), rs2:x7(0x0000000000000001), result rd:x31(0x0000000000000000)
+li x22, MASK_XLEN(0x0000000000000001)
+li x7, MASK_XLEN(0x0000000000000001)
+SUB x31, x22, x7
+sd x31, 32(x6)
+
+# Testcase 5:  rs1:x25(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x26(0x0000000000000002)
+li x25, MASK_XLEN(0x0000000000000001)
+li x2, MASK_XLEN(0xffffffffffffffff)
+SUB x26, x25, x2
+sd x26, 40(x6)
+
+# Testcase 6:  rs1:x9(0xffffffffffffffff), rs2:x4(0x0000000000000000), result rd:x20(0xffffffffffffffff)
+li x9, MASK_XLEN(0xffffffffffffffff)
+li x4, MASK_XLEN(0x0000000000000000)
+SUB x20, x9, x4
+sd x20, 48(x6)
+
+# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x22(0xfffffffffffffffe)
+li x30, MASK_XLEN(0xffffffffffffffff)
+li x15, MASK_XLEN(0x0000000000000001)
+SUB x22, x30, x15
+sd x22, 56(x6)
+
+# Testcase 8:  rs1:x22(0xffffffffffffffff), rs2:x14(0xffffffffffffffff), result rd:x29(0x0000000000000000)
+li x22, MASK_XLEN(0xffffffffffffffff)
+li x14, MASK_XLEN(0xffffffffffffffff)
+SUB x29, x22, x14
+sd x29, 64(x6)
+
+# Testcase 9:  rs1:x10(0xdff3334b91b15f5d), rs2:x21(0xeae2025e82339e23), result rd:x12(0xf51130ed0f7dc13a)
+li x10, MASK_XLEN(0xdff3334b91b15f5d)
+li x21, MASK_XLEN(0xeae2025e82339e23)
+SUB x12, x10, x21
+sd x12, 72(x6)
+
+# Testcase 10:  rs1:x5(0xd670f668637e0edc), rs2:x18(0x403d1f83a859890c), result rd:x23(0x9633d6e4bb2485d0)
+li x5, MASK_XLEN(0xd670f668637e0edc)
+li x18, MASK_XLEN(0x403d1f83a859890c)
+SUB x23, x5, x18
+sd x23, 80(x6)
+
+# Testcase 11:  rs1:x11(0x753c7c99032f06ca), rs2:x24(0x143e2e04bdd7d19b), result rd:x2(0x60fe4e944557352f)
+li x11, MASK_XLEN(0x753c7c99032f06ca)
+li x24, MASK_XLEN(0x143e2e04bdd7d19b)
+SUB x2, x11, x24
+sd x2, 88(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
new file mode 100644
index 000000000..b91ba798f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
@@ -0,0 +1,139 @@
+///////////////////////////////////////////
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
+// David_Harris@hmc.edu & Katherine Parry
+// Created 2022-06-17 22:58:09.919138//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+RVTEST_SIGBASE( x6, wally_signature)
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
+
+# Testcase 0:  rs1:x27(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x17(0x0000000000000000)
+li x27, MASK_XLEN(0x0000000000000000)
+li x22, MASK_XLEN(0x0000000000000000)
+XOR x17, x27, x22
+sd x17, 0(x6)
+
+# Testcase 1:  rs1:x20(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x7(0x0000000000000001)
+li x20, MASK_XLEN(0x0000000000000000)
+li x4, MASK_XLEN(0x0000000000000001)
+XOR x7, x20, x4
+sd x7, 8(x6)
+
+# Testcase 2:  rs1:x4(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x21(0xffffffffffffffff)
+li x4, MASK_XLEN(0x0000000000000000)
+li x20, MASK_XLEN(0xffffffffffffffff)
+XOR x21, x4, x20
+sd x21, 16(x6)
+
+# Testcase 3:  rs1:x7(0x0000000000000001), rs2:x28(0x0000000000000000), result rd:x10(0x0000000000000001)
+li x7, MASK_XLEN(0x0000000000000001)
+li x28, MASK_XLEN(0x0000000000000000)
+XOR x10, x7, x28
+sd x10, 24(x6)
+
+# Testcase 4:  rs1:x4(0x0000000000000001), rs2:x16(0x0000000000000001), result rd:x28(0x0000000000000000)
+li x4, MASK_XLEN(0x0000000000000001)
+li x16, MASK_XLEN(0x0000000000000001)
+XOR x28, x4, x16
+sd x28, 32(x6)
+
+# Testcase 5:  rs1:x30(0x0000000000000001), rs2:x13(0xffffffffffffffff), result rd:x21(0xfffffffffffffffe)
+li x30, MASK_XLEN(0x0000000000000001)
+li x13, MASK_XLEN(0xffffffffffffffff)
+XOR x21, x30, x13
+sd x21, 40(x6)
+
+# Testcase 6:  rs1:x3(0xffffffffffffffff), rs2:x1(0x0000000000000000), result rd:x9(0xffffffffffffffff)
+li x3, MASK_XLEN(0xffffffffffffffff)
+li x1, MASK_XLEN(0x0000000000000000)
+XOR x9, x3, x1
+sd x9, 48(x6)
+
+# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x26(0xfffffffffffffffe)
+li x30, MASK_XLEN(0xffffffffffffffff)
+li x15, MASK_XLEN(0x0000000000000001)
+XOR x26, x30, x15
+sd x26, 56(x6)
+
+# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x4(0xffffffffffffffff), result rd:x28(0x0000000000000000)
+li x26, MASK_XLEN(0xffffffffffffffff)
+li x4, MASK_XLEN(0xffffffffffffffff)
+XOR x28, x26, x4
+sd x28, 64(x6)
+
+# Testcase 9:  rs1:x27(0x2227d96d41a93f90), rs2:x21(0x8557716aa7502a81), result rd:x21(0xa770a807e6f91511)
+li x27, MASK_XLEN(0x2227d96d41a93f90)
+li x21, MASK_XLEN(0x8557716aa7502a81)
+XOR x21, x27, x21
+sd x21, 72(x6)
+
+# Testcase 10:  rs1:x9(0x1d77ce4058d87776), rs2:x28(0x27896389df3277fd), result rd:x1(0x3afeadc987ea008b)
+li x9, MASK_XLEN(0x1d77ce4058d87776)
+li x28, MASK_XLEN(0x27896389df3277fd)
+XOR x1, x9, x28
+sd x1, 80(x6)
+
+# Testcase 11:  rs1:x9(0x0a68e88e0ad40415), rs2:x18(0xae55cdff34ab18fd), result rd:x11(0xa43d25713e7f1ce8)
+li x9, MASK_XLEN(0x0a68e88e0ad40415)
+li x18, MASK_XLEN(0xae55cdff34ab18fd)
+XOR x11, x9, x18
+sd x11, 88(x6)
+
+.EQU NUMTESTS,12
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0x98765432
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+wally_signature:
+    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
+// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
+// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefile
new file mode 100644
index 000000000..6db6b8483
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefile
@@ -0,0 +1,4 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64ib -mabi=lp64 -DXLEN=$(XLEN)))
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefrag
new file mode 100644
index 000000000..250a9b506
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/Makefrag
@@ -0,0 +1,31 @@
+# RISC-V Compliance Test RV64K Makefrag
+#
+#
+# Copyright (c) 2021 Imperas Software Ltd., www.imperas.com
+# Copyright (c) 2021 Indian Institute of Technology Madras
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+# either express or implied.
+#
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#
+
+#
+# Description: Makefrag for RV64K compliance tests
+
+rv64k_sc_tests = \
+
+rv64k_tests = $(addsuffix .elf, $(rv64k_sc_tests))
+
+target_tests += $(rv64k_tests)
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S
new file mode 100644
index 000000000..1b573f563
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-01.S
@@ -0,0 +1,364 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64ds instruction of the RISC-V  extension for the aes64ds covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64ds)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64ds)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnd.*);def TEST_CASE_1=True;",aes64ds)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x23, rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64ds ; op1:x6; op2:x6; dest:x23; op1val:0x706050403020100;  op2val:0x706050403020100
+TEST_RR_OP(aes64ds, x23, x6, x6, 0x0000000000000000, 0x706050403020100, 0x706050403020100, x1, 0, x5)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64ds ; op1:x8; op2:x8; dest:x8; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(aes64ds, x8, x8, x8, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x1, 8, x5)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x31, rs2==x7, rd==x17, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: aes64ds ; op1:x31; op2:x7; dest:x17; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(aes64ds, x17, x31, x7, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x1, 16, x5)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x25, rs2==x2, rd==x25, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: aes64ds ; op1:x25; op2:x2; dest:x25; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(aes64ds, x25, x25, x2, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x1, 24, x5)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x20, rs2==x4, rd==x4, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64ds ; op1:x20; op2:x4; dest:x4; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64ds, x4, x20, x4, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x1, 32, x5)
+
+inst_5:
+// rs1==x29, rs2==x24, rd==x27, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: aes64ds ; op1:x29; op2:x24; dest:x27; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(aes64ds, x27, x29, x24, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x1, 40, x5)
+
+inst_6:
+// rs1==x30, rs2==x15, rd==x11, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64ds ; op1:x30; op2:x15; dest:x11; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64ds, x11, x30, x15, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x1, 48, x5)
+
+inst_7:
+// rs1==x4, rs2==x26, rd==x16, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64ds ; op1:x4; op2:x26; dest:x16; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64ds, x16, x4, x26, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x1, 56, x5)
+
+inst_8:
+// rs1==x9, rs2==x14, rd==x3, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: aes64ds ; op1:x9; op2:x14; dest:x3; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(aes64ds, x3, x9, x14, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x1, 64, x5)
+
+inst_9:
+// rs1==x19, rs2==x12, rd==x15, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: aes64ds ; op1:x19; op2:x12; dest:x15; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(aes64ds, x15, x19, x12, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x1, 72, x5)
+
+inst_10:
+// rs1==x26, rs2==x17, rd==x21, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64ds ; op1:x26; op2:x17; dest:x21; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64ds, x21, x26, x17, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x1, 80, x5)
+
+inst_11:
+// rs1==x16, rs2==x13, rd==x19, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64ds ; op1:x16; op2:x13; dest:x19; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64ds, x19, x16, x13, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x1, 88, x5)
+
+inst_12:
+// rs1==x3, rs2==x22, rd==x26, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: aes64ds ; op1:x3; op2:x22; dest:x26; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(aes64ds, x26, x3, x22, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x1, 96, x5)
+
+inst_13:
+// rs1==x2, rs2==x3, rd==x18, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64ds ; op1:x2; op2:x3; dest:x18; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(aes64ds, x18, x2, x3, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x1, 104, x5)
+
+inst_14:
+// rs1==x27, rs2==x11, rd==x30, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: aes64ds ; op1:x27; op2:x11; dest:x30; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(aes64ds, x30, x27, x11, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x1, 112, x3)
+
+inst_15:
+// rs1==x13, rs2==x29, rd==x12, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: aes64ds ; op1:x13; op2:x29; dest:x12; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(aes64ds, x12, x13, x29, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x1, 120, x3)
+
+inst_16:
+// rs1==x23, rs2==x20, rd==x24, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: aes64ds ; op1:x23; op2:x20; dest:x24; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(aes64ds, x24, x23, x20, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x1, 128, x3)
+
+inst_17:
+// rs1==x17, rs2==x28, rd==x2, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: aes64ds ; op1:x17; op2:x28; dest:x2; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(aes64ds, x2, x17, x28, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x1, 136, x3)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_18:
+// rs1==x21, rs2==x5, rd==x20, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: aes64ds ; op1:x21; op2:x5; dest:x20; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(aes64ds, x20, x21, x5, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x2, 0, x3)
+
+inst_19:
+// rs1==x24, rs2==x31, rd==x28, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: aes64ds ; op1:x24; op2:x31; dest:x28; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(aes64ds, x28, x24, x31, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x2, 8, x3)
+
+inst_20:
+// rs1==x7, rs2==x19, rd==x9, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64ds ; op1:x7; op2:x19; dest:x9; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(aes64ds, x9, x7, x19, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x2, 16, x3)
+
+inst_21:
+// rs1==x1, rs2==x23, rd==x29, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0xf7f6f5f4f3f2f1f0 
+// opcode: aes64ds ; op1:x1; op2:x23; dest:x29; op1val:0xfffefdfcfbfaf9f8;  op2val:0xf7f6f5f4f3f2f1f0
+TEST_RR_OP(aes64ds, x29, x1, x23, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0xf7f6f5f4f3f2f1f0, x2, 24, x3)
+
+inst_22:
+// rs1==x10, rs2==x9, rd==x31, rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfffefdfcfbfaf9f8 
+// opcode: aes64ds ; op1:x10; op2:x9; dest:x31; op1val:0xf7f6f5f4f3f2f1f0;  op2val:0xfffefdfcfbfaf9f8
+TEST_RR_OP(aes64ds, x31, x10, x9, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfffefdfcfbfaf9f8, x2, 32, x3)
+
+inst_23:
+// rs1==x12, rs2==x1, rd==x6, rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xe7e6e5e4e3e2e1e0 
+// opcode: aes64ds ; op1:x12; op2:x1; dest:x6; op1val:0xefeeedecebeae9e8;  op2val:0xe7e6e5e4e3e2e1e0
+TEST_RR_OP(aes64ds, x6, x12, x1, 0x0000000000000000, 0xefeeedecebeae9e8, 0xe7e6e5e4e3e2e1e0, x2, 40, x3)
+
+inst_24:
+// rs1==x11, rs2==x18, rd==x0, rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xefeeedecebeae9e8 
+// opcode: aes64ds ; op1:x11; op2:x18; dest:x0; op1val:0xe7e6e5e4e3e2e1e0;  op2val:0xefeeedecebeae9e8
+TEST_RR_OP(aes64ds, x0, x11, x18, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xefeeedecebeae9e8, x2, 48, x3)
+
+inst_25:
+// rs1==x0, rs2==x21, rd==x1, rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64ds ; op1:x0; op2:x21; dest:x1; op1val:0x0;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64ds, x1, x0, x21, 0x0000000000000000, 0x0, 0xd7d6d5d4d3d2d1d0, x2, 56, x3)
+
+inst_26:
+// rs1==x28, rs2==x27, rd==x22, rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdfdedddcdbdad9d8 
+// opcode: aes64ds ; op1:x28; op2:x27; dest:x22; op1val:0xd7d6d5d4d3d2d1d0;  op2val:0xdfdedddcdbdad9d8
+TEST_RR_OP(aes64ds, x22, x28, x27, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdfdedddcdbdad9d8, x2, 64, x3)
+
+inst_27:
+// rs1==x15, rs2==x10, rd==x13, rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xc7c6c5c4c3c2c1c0 
+// opcode: aes64ds ; op1:x15; op2:x10; dest:x13; op1val:0xcfcecdcccbcac9c8;  op2val:0xc7c6c5c4c3c2c1c0
+TEST_RR_OP(aes64ds, x13, x15, x10, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xc7c6c5c4c3c2c1c0, x2, 72, x3)
+
+inst_28:
+// rs1==x14, rs2==x16, rd==x10, rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcfcecdcccbcac9c8 
+// opcode: aes64ds ; op1:x14; op2:x16; dest:x10; op1val:0xc7c6c5c4c3c2c1c0;  op2val:0xcfcecdcccbcac9c8
+TEST_RR_OP(aes64ds, x10, x14, x16, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcfcecdcccbcac9c8, x2, 80, x3)
+
+inst_29:
+// rs1==x5, rs2==x30, rd==x7, rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xb7b6b5b4b3b2b1b0 
+// opcode: aes64ds ; op1:x5; op2:x30; dest:x7; op1val:0xbfbebdbcbbbab9b8;  op2val:0xb7b6b5b4b3b2b1b0
+TEST_RR_OP(aes64ds, x7, x5, x30, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xb7b6b5b4b3b2b1b0, x2, 88, x3)
+
+inst_30:
+// rs1==x22, rs2==x0, rd==x5, rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbfbebdbcbbbab9b8 
+// opcode: aes64ds ; op1:x22; op2:x0; dest:x5; op1val:0xb7b6b5b4b3b2b1b0;  op2val:0x0
+TEST_RR_OP(aes64ds, x5, x22, x0, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0x0, x2, 96, x3)
+
+inst_31:
+// rs1==x18, rs2==x25, rd==x14, rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xa7a6a5a4a3a2a1a0 
+// opcode: aes64ds ; op1:x18; op2:x25; dest:x14; op1val:0xafaeadacabaaa9a8;  op2val:0xa7a6a5a4a3a2a1a0
+TEST_RR_OP(aes64ds, x14, x18, x25, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xa7a6a5a4a3a2a1a0, x2, 104, x3)
+
+inst_32:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xafaeadacabaaa9a8 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0xa7a6a5a4a3a2a1a0;  op2val:0xafaeadacabaaa9a8
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xafaeadacabaaa9a8, x2, 112, x3)
+
+inst_33:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0x9796959493929190 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x9f9e9d9c9b9a9998;  op2val:0x9796959493929190
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0x9796959493929190, x2, 120, x3)
+
+inst_34:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9f9e9d9c9b9a9998 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x9796959493929190;  op2val:0x9f9e9d9c9b9a9998
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x9796959493929190, 0x9f9e9d9c9b9a9998, x2, 128, x3)
+
+inst_35:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x8786858483828180 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x8f8e8d8c8b8a8988;  op2val:0x8786858483828180
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x8786858483828180, x2, 136, x3)
+
+inst_36:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8f8e8d8c8b8a8988 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x8786858483828180;  op2val:0x8f8e8d8c8b8a8988
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x8786858483828180, 0x8f8e8d8c8b8a8988, x2, 144, x3)
+
+inst_37:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x7776757473727170 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x7f7e7d7c7b7a7978;  op2val:0x7776757473727170
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x7776757473727170, x2, 152, x3)
+
+inst_38:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7f7e7d7c7b7a7978 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x7776757473727170;  op2val:0x7f7e7d7c7b7a7978
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x7776757473727170, 0x7f7e7d7c7b7a7978, x2, 160, x3)
+
+inst_39:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x6766656463626160 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x6f6e6d6c6b6a6968;  op2val:0x6766656463626160
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x6766656463626160, x2, 168, x3)
+
+inst_40:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6f6e6d6c6b6a6968 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x6766656463626160;  op2val:0x6f6e6d6c6b6a6968
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x6766656463626160, 0x6f6e6d6c6b6a6968, x2, 176, x3)
+
+inst_41:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x5756555453525150 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x5f5e5d5c5b5a5958;  op2val:0x5756555453525150
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x5756555453525150, x2, 184, x3)
+
+inst_42:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5f5e5d5c5b5a5958 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x5756555453525150;  op2val:0x5f5e5d5c5b5a5958
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x5756555453525150, 0x5f5e5d5c5b5a5958, x2, 192, x3)
+
+inst_43:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x4746454443424140 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x4f4e4d4c4b4a4948;  op2val:0x4746454443424140
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x4746454443424140, x2, 200, x3)
+
+inst_44:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4f4e4d4c4b4a4948 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x4746454443424140;  op2val:0x4f4e4d4c4b4a4948
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x4746454443424140, 0x4f4e4d4c4b4a4948, x2, 208, x3)
+
+inst_45:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x3736353433323130 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x3f3e3d3c3b3a3938;  op2val:0x3736353433323130
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x3736353433323130, x2, 216, x3)
+
+inst_46:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3f3e3d3c3b3a3938 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x3736353433323130;  op2val:0x3f3e3d3c3b3a3938
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x3736353433323130, 0x3f3e3d3c3b3a3938, x2, 224, x3)
+
+inst_47:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x2726252423222120 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x2f2e2d2c2b2a2928;  op2val:0x2726252423222120
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x2726252423222120, x2, 232, x3)
+
+inst_48:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2f2e2d2c2b2a2928 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x2726252423222120;  op2val:0x2f2e2d2c2b2a2928
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x2726252423222120, 0x2f2e2d2c2b2a2928, x2, 240, x3)
+
+inst_49:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x1716151413121110 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x1f1e1d1c1b1a1918;  op2val:0x1716151413121110
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x1716151413121110, x2, 248, x3)
+
+inst_50:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1f1e1d1c1b1a1918 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x1716151413121110;  op2val:0x1f1e1d1c1b1a1918
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x1716151413121110, 0x1f1e1d1c1b1a1918, x2, 256, x3)
+
+inst_51:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x0706050403020100 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0xf0e0d0c0b0a0908;  op2val:0x706050403020100
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x706050403020100, x2, 264, x3)
+
+inst_52:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x706050403020100;  op2val:0xf0e0d0c0b0a0908
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x706050403020100, 0xf0e0d0c0b0a0908, x2, 272, x3)
+
+inst_53:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x2, 280, x3)
+
+inst_54:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xefeeedecebeae9e8 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0xe7e6e5e4e3e2e1e0;  op2val:0xefeeedecebeae9e8
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xefeeedecebeae9e8, x2, 288, x3)
+
+inst_55:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0xdfdedddcdbdad9d8;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xd7d6d5d4d3d2d1d0, x2, 296, x3)
+
+inst_56:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbfbebdbcbbbab9b8 
+// opcode: aes64ds ; op1:x10; op2:x11; dest:x12; op1val:0xb7b6b5b4b3b2b1b0;  op2val:0xbfbebdbcbbbab9b8
+TEST_RR_OP(aes64ds, x12, x10, x11, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbfbebdbcbbbab9b8, x2, 304, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 39*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S
new file mode 100644
index 000000000..652fdcad2
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ds-rwp1.S
@@ -0,0 +1,389 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64ds)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64ds)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// 1st Instruction => rs1 = x1; rs2 = x2 | 2nd Instruction => rs1 = x2; rs2 = x1 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x1; op2:x2; dest1:x3; dest2:x4; dest3:x5; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x1, x1, x2;
+aes64ds x3, x1, x2;
+aes64ds x4, x2, x1;
+xor x5, x4, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x4,8);
+RVTEST_SIGUPD(x31,x5,16);
+
+inst_1:
+// 1st Instruction => rs1 = x2; rs2 = x3 | 2nd Instruction => rs1 = x3; rs2 = x2 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x2; op2:x3; dest1:x4; dest2:x5; dest3:x6; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x2, x2, x3;
+aes64ds x4, x2, x3;
+aes64ds x5, x3, x2;
+xor x6, x5, x3;
+RVTEST_SIGUPD(x31,x4,24);
+RVTEST_SIGUPD(x31,x5,32);
+RVTEST_SIGUPD(x31,x6,40);
+
+inst_2:
+// 1st Instruction => rs1 = x3; rs2 = x4 | 2nd Instruction => rs1 = x4; rs2 = x3 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x3; op2:x4; dest1:x5; dest2:x6; dest3:x7; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x3, x3, x4;
+aes64ds x5, x3, x4;
+aes64ds x6, x4, x3;
+xor x7, x6, x4;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+RVTEST_SIGUPD(x31,x7,64);
+
+inst_3:
+// 1st Instruction => rs1 = x4; rs2 = x5 | 2nd Instruction => rs1 = x5; rs2 = x4 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x4; op2:x5; dest1:x6; dest2:x7; dest3:x8; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x4, x4, x5;
+aes64ds x6, x4, x5;
+aes64ds x7, x5, x4;
+xor x8, x7, x5;
+RVTEST_SIGUPD(x31,x6,72);
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_4:
+// 1st Instruction => rs1 = x5; rs2 = x6 | 2nd Instruction => rs1 = x6; rs2 = x5 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x5; op2:x6; dest1:x7; dest2:x8; dest3:x9; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x5, x5, x6;
+aes64ds x7, x5, x6;
+aes64ds x8, x6, x5;
+xor x9, x8, x6;
+RVTEST_SIGUPD(x31,x7,96);
+RVTEST_SIGUPD(x31,x8,104);
+RVTEST_SIGUPD(x31,x9,112);
+
+inst_5:
+// 1st Instruction => rs1 = x6; rs2 = x7 | 2nd Instruction => rs1 = x7; rs2 = x6 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x6; op2:x7; dest1:x8; dest2:x9; dest3:x10; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x6, x6, x7;
+aes64ds x8, x6, x7;
+aes64ds x9, x7, x6;
+xor x10, x9, x7;
+RVTEST_SIGUPD(x31,x8,120);
+RVTEST_SIGUPD(x31,x9,128);
+RVTEST_SIGUPD(x31,x10,136);
+
+inst_6:
+// 1st Instruction => rs1 = x7; rs2 = x8 | 2nd Instruction => rs1 = x8; rs2 = x7 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x7; op2:x8; dest1:x9; dest2:x10; dest3:x11; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x7, x7, x8;
+aes64ds x9, x7, x8;
+aes64ds x10, x8, x7;
+xor x11, x10, x8;
+RVTEST_SIGUPD(x31,x9,144);
+RVTEST_SIGUPD(x31,x10,152);
+RVTEST_SIGUPD(x31,x11,160);
+
+inst_7:
+// 1st Instruction => rs1 = x8; rs2 = x9 | 2nd Instruction => rs1 = x9; rs2 = x8 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x8; op2:x9; dest1:x10; dest2:x11; dest3:x12; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x8, x8, x9;
+aes64ds x10, x8, x9;
+aes64ds x11, x9, x8;
+xor x12, x11, x9;
+RVTEST_SIGUPD(x31,x10,168);
+RVTEST_SIGUPD(x31,x11,176);
+RVTEST_SIGUPD(x31,x12,184);
+
+inst_8:
+// 1st Instruction => rs1 = x9; rs2 = x10 | 2nd Instruction => rs1 = x10; rs2 = x9 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x9; op2:x10; dest1:x11; dest2:x12; dest3:x13; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x9, x9, x10;
+aes64ds x11, x9, x10;
+aes64ds x12, x10, x9;
+xor x13, x12, x10;
+RVTEST_SIGUPD(x31,x11,192);
+RVTEST_SIGUPD(x31,x12,200);
+RVTEST_SIGUPD(x31,x13,208);
+
+inst_9:
+// 1st Instruction => rs1 = x10; rs2 = x11 | 2nd Instruction => rs1 = x11; rs2 = x10 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x10; op2:x11; dest1:x12; dest2:x13; dest3:x14; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x10, x10, x11;
+aes64ds x12, x10, x11;
+aes64ds x13, x11, x10;
+xor x14, x13, x11;
+RVTEST_SIGUPD(x31,x12,216);
+RVTEST_SIGUPD(x31,x13,224);
+RVTEST_SIGUPD(x31,x14,232);
+
+inst_10:
+// 1st Instruction => rs1 = x11; rs2 = x12 | 2nd Instruction => rs1 = x12; rs2 = x11 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x11; op2:x12; dest1:x13; dest2:x14; dest3:x15; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x11, x11, x12;
+aes64ds x13, x11, x12;
+aes64ds x14, x12, x11;
+xor x15, x14, x12;
+RVTEST_SIGUPD(x31,x13,240);
+RVTEST_SIGUPD(x31,x14,248);
+RVTEST_SIGUPD(x31,x15,256);
+
+inst_11:
+// 1st Instruction => rs1 = x12; rs2 = x13 | 2nd Instruction => rs1 = x13; rs2 = x12 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x12; op2:x13; dest1:x14; dest2:x15; dest3:x16; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x12, x12, x13;
+aes64ds x14, x12, x13;
+aes64ds x15, x13, x12;
+xor x16, x15, x13;
+RVTEST_SIGUPD(x31,x14,264);
+RVTEST_SIGUPD(x31,x15,272);
+RVTEST_SIGUPD(x31,x16,280);
+
+inst_12:
+// 1st Instruction => rs1 = x13; rs2 = x14 | 2nd Instruction => rs1 = x14; rs2 = x13 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x13; op2:x14; dest1:x15; dest2:x16; dest3:x17; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x13, x13, x14;
+aes64ds x15, x13, x14;
+aes64ds x16, x14, x13;
+xor x17, x16, x14;
+RVTEST_SIGUPD(x31,x15,288);
+RVTEST_SIGUPD(x31,x16,296);
+RVTEST_SIGUPD(x31,x17,304);
+
+inst_13:
+// 1st Instruction => rs1 = x14; rs2 = x15 | 2nd Instruction => rs1 = x15; rs2 = x14 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x14; op2:x15; dest1:x16; dest2:x17; dest3:x18; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x14, x14, x15;
+aes64ds x16, x14, x15;
+aes64ds x17, x15, x14;
+xor x18, x17, x15;
+RVTEST_SIGUPD(x31,x16,312);
+RVTEST_SIGUPD(x31,x17,320);
+RVTEST_SIGUPD(x31,x18,328);
+
+inst_14:
+// 1st Instruction => rs1 = x15; rs2 = x16 | 2nd Instruction => rs1 = x16; rs2 = x15 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x15; op2:x16; dest1:x17; dest2:x18; dest3:x19; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x15, x15, x16;
+aes64ds x17, x15, x16;
+aes64ds x18, x16, x15;
+xor x19, x18, x16;
+RVTEST_SIGUPD(x31,x17,336);
+RVTEST_SIGUPD(x31,x18,344);
+RVTEST_SIGUPD(x31,x19,352);
+
+inst_15:
+// 1st Instruction => rs1 = x16; rs2 = x17 | 2nd Instruction => rs1 = x17; rs2 = x16 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x16; op2:x17; dest1:x18; dest2:x19; dest3:x20; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x16, x16, x17;
+aes64ds x18, x16, x17;
+aes64ds x19, x17, x16;
+xor x20, x19, x17;
+RVTEST_SIGUPD(x31,x18,360);
+RVTEST_SIGUPD(x31,x19,368);
+RVTEST_SIGUPD(x31,x20,376);
+
+inst_16:
+// 1st Instruction => rs1 = x17; rs2 = x18 | 2nd Instruction => rs1 = x18; rs2 = x17 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x17; op2:x18; dest1:x19; dest2:x20; dest3:x21; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x17, x17, x18;
+aes64ds x19, x17, x18;
+aes64ds x20, x18, x17;
+xor x21, x20, x18;
+RVTEST_SIGUPD(x31,x19,384);
+RVTEST_SIGUPD(x31,x20,392);
+RVTEST_SIGUPD(x31,x21,400);
+
+inst_17:
+// 1st Instruction => rs1 = x18; rs2 = x19 | 2nd Instruction => rs1 = x19; rs2 = x18 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x18; op2:x19; dest1:x20; dest2:x21; dest3:x22; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x18, x18, x19;
+aes64ds x20, x18, x19;
+aes64ds x21, x19, x18;
+xor x22, x21, x19;
+RVTEST_SIGUPD(x31,x20,408);
+RVTEST_SIGUPD(x31,x21,416);
+RVTEST_SIGUPD(x31,x22,424);
+
+inst_18:
+// 1st Instruction => rs1 = x19; rs2 = x20 | 2nd Instruction => rs1 = x20; rs2 = x19 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x19; op2:x20; dest1:x21; dest2:x22; dest3:x23; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x19, x19, x20;
+aes64ds x21, x19, x20;
+aes64ds x22, x20, x19;
+xor x23, x22, x20;
+RVTEST_SIGUPD(x31,x21,432);
+RVTEST_SIGUPD(x31,x22,440);
+RVTEST_SIGUPD(x31,x23,448);
+
+inst_19:
+// 1st Instruction => rs1 = x20; rs2 = x21 | 2nd Instruction => rs1 = x21; rs2 = x20 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x20; op2:x21; dest1:x22; dest2:x23; dest3:x24; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x20, x20, x21;
+aes64ds x22, x20, x21;
+aes64ds x23, x21, x20;
+xor x24, x23, x21;
+RVTEST_SIGUPD(x31,x22,456);
+RVTEST_SIGUPD(x31,x23,464);
+RVTEST_SIGUPD(x31,x24,472);
+
+inst_20:
+// 1st Instruction => rs1 = x21; rs2 = x22 | 2nd Instruction => rs1 = x22; rs2 = x21 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x21; op2:x22; dest1:x23; dest2:x24; dest3:x25; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x21, x21, x22;
+aes64ds x23, x21, x22;
+aes64ds x24, x22, x21;
+xor x25, x24, x22;
+RVTEST_SIGUPD(x31,x23,480);
+RVTEST_SIGUPD(x31,x24,488);
+RVTEST_SIGUPD(x31,x25,496);
+
+inst_21:
+// 1st Instruction => rs1 = x22; rs2 = x23 | 2nd Instruction => rs1 = x23; rs2 = x22 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x22; op2:x23; dest1:x24; dest2:x25; dest3:x26; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x22, x22, x23;
+aes64ds x24, x22, x23;
+aes64ds x25, x23, x22;
+xor x26, x25, x23;
+RVTEST_SIGUPD(x31,x24,504);
+RVTEST_SIGUPD(x31,x25,512);
+RVTEST_SIGUPD(x31,x26,520);
+
+inst_22:
+// 1st Instruction => rs1 = x23; rs2 = x24 | 2nd Instruction => rs1 = x24; rs2 = x23 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x23; op2:x24; dest1:x25; dest2:x26; dest3:x27; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x23, x23, x24;
+aes64ds x25, x23, x24;
+aes64ds x26, x24, x23;
+xor x27, x26, x24;
+RVTEST_SIGUPD(x31,x25,528);
+RVTEST_SIGUPD(x31,x26,536);
+RVTEST_SIGUPD(x31,x27,544);
+
+inst_23:
+// 1st Instruction => rs1 = x24; rs2 = x25 | 2nd Instruction => rs1 = x25; rs2 = x24 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x24; op2:x25; dest1:x26; dest2:x27; dest3:x28; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x24, x24, x25;
+aes64ds x26, x24, x25;
+aes64ds x27, x25, x24;
+xor x28, x27, x25;
+RVTEST_SIGUPD(x31,x26,552);
+RVTEST_SIGUPD(x31,x27,560);
+RVTEST_SIGUPD(x31,x28,568);
+
+inst_24:
+// 1st Instruction => rs1 = x25; rs2 = x26 | 2nd Instruction => rs1 = x26; rs2 = x25 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x25; op2:x26; dest1:x27; dest2:x28; dest3:x29; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x25, x25, x26;
+aes64ds x27, x25, x26;
+aes64ds x28, x26, x25;
+xor x29, x28, x26;
+RVTEST_SIGUPD(x31,x27,576);
+RVTEST_SIGUPD(x31,x28,584);
+RVTEST_SIGUPD(x31,x29,592);
+
+inst_25:
+// 1st Instruction => rs1 = x26; rs2 = x27 | 2nd Instruction => rs1 = x27; rs2 = x26 | Result of xor goes into aes64ds & vice versa
+// opcode: aes64ds; op1:x26; op2:x27; dest1:x28; dest2:x29; dest3:x30; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x26, x26, x27;
+aes64ds x28, x26, x27;
+aes64ds x29, x27, x26;
+xor x30, x29, x27;
+RVTEST_SIGUPD(x31,x28,600);
+RVTEST_SIGUPD(x31,x29,608);
+RVTEST_SIGUPD(x31,x30,616);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 78*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S
new file mode 100644
index 000000000..d01a79487
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-01.S
@@ -0,0 +1,364 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64dsm instruction of the RISC-V  extension for the aes64dsm covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64dsm)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64dsm)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnd.*);def TEST_CASE_1=True;",aes64dsm)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x5, rs2==x5, rd==x11, rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64dsm ; op1:x5; op2:x5; dest:x11; op1val:0x706050403020100;  op2val:0x706050403020100
+TEST_RR_OP(aes64dsm, x11, x5, x5, 0x0000000000000000, 0x706050403020100, 0x706050403020100, x3, 0, x1)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x9, rs2==x9, rd==x9, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64dsm ; op1:x9; op2:x9; dest:x9; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(aes64dsm, x9, x9, x9, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x3, 8, x1)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x20, rs2==x11, rd==x15, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: aes64dsm ; op1:x20; op2:x11; dest:x15; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(aes64dsm, x15, x20, x11, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x3, 16, x1)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x7, rs2==x15, rd==x7, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: aes64dsm ; op1:x7; op2:x15; dest:x7; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(aes64dsm, x7, x7, x15, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x3, 24, x1)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x2, rs2==x21, rd==x21, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64dsm ; op1:x2; op2:x21; dest:x21; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64dsm, x21, x2, x21, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x3, 32, x1)
+
+inst_5:
+// rs1==x4, rs2==x31, rd==x5, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: aes64dsm ; op1:x4; op2:x31; dest:x5; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(aes64dsm, x5, x4, x31, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x3, 40, x1)
+
+inst_6:
+// rs1==x0, rs2==x13, rd==x23, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64dsm ; op1:x0; op2:x13; dest:x23; op1val:0x0;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64dsm, x23, x0, x13, 0x0000000000000000, 0x0, 0x1aa1beebefb902cb, x3, 48, x1)
+
+inst_7:
+// rs1==x21, rs2==x20, rd==x31, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64dsm ; op1:x21; op2:x20; dest:x31; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64dsm, x31, x21, x20, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x3, 56, x1)
+
+inst_8:
+// rs1==x27, rs2==x24, rd==x22, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: aes64dsm ; op1:x27; op2:x24; dest:x22; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(aes64dsm, x22, x27, x24, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x3, 64, x1)
+
+inst_9:
+// rs1==x19, rs2==x26, rd==x12, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: aes64dsm ; op1:x19; op2:x26; dest:x12; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(aes64dsm, x12, x19, x26, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x3, 72, x1)
+
+inst_10:
+// rs1==x24, rs2==x27, rd==x13, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64dsm ; op1:x24; op2:x27; dest:x13; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64dsm, x13, x24, x27, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x3, 80, x1)
+
+inst_11:
+// rs1==x13, rs2==x17, rd==x0, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64dsm ; op1:x13; op2:x17; dest:x0; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64dsm, x0, x13, x17, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x3, 88, x1)
+
+inst_12:
+// rs1==x28, rs2==x10, rd==x30, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: aes64dsm ; op1:x28; op2:x10; dest:x30; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(aes64dsm, x30, x28, x10, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x3, 96, x1)
+
+inst_13:
+// rs1==x14, rs2==x6, rd==x25, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64dsm ; op1:x14; op2:x6; dest:x25; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(aes64dsm, x25, x14, x6, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x3, 104, x1)
+
+inst_14:
+// rs1==x18, rs2==x2, rd==x24, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: aes64dsm ; op1:x18; op2:x2; dest:x24; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(aes64dsm, x24, x18, x2, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x3, 112, x1)
+
+inst_15:
+// rs1==x10, rs2==x29, rd==x2, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: aes64dsm ; op1:x10; op2:x29; dest:x2; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(aes64dsm, x2, x10, x29, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x3, 120, x1)
+
+inst_16:
+// rs1==x15, rs2==x19, rd==x4, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: aes64dsm ; op1:x15; op2:x19; dest:x4; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(aes64dsm, x4, x15, x19, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x3, 128, x5)
+
+inst_17:
+// rs1==x12, rs2==x18, rd==x6, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: aes64dsm ; op1:x12; op2:x18; dest:x6; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(aes64dsm, x6, x12, x18, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x3, 136, x5)
+
+inst_18:
+// rs1==x1, rs2==x8, rd==x20, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: aes64dsm ; op1:x1; op2:x8; dest:x20; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(aes64dsm, x20, x1, x8, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x3, 144, x5)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_19:
+// rs1==x11, rs2==x22, rd==x3, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: aes64dsm ; op1:x11; op2:x22; dest:x3; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(aes64dsm, x3, x11, x22, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x2, 0, x5)
+
+inst_20:
+// rs1==x17, rs2==x28, rd==x1, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64dsm ; op1:x17; op2:x28; dest:x1; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(aes64dsm, x1, x17, x28, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x2, 8, x5)
+
+inst_21:
+// rs1==x23, rs2==x12, rd==x29, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0xf7f6f5f4f3f2f1f0 
+// opcode: aes64dsm ; op1:x23; op2:x12; dest:x29; op1val:0xfffefdfcfbfaf9f8;  op2val:0xf7f6f5f4f3f2f1f0
+TEST_RR_OP(aes64dsm, x29, x23, x12, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0xf7f6f5f4f3f2f1f0, x2, 16, x5)
+
+inst_22:
+// rs1==x22, rs2==x30, rd==x16, rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfffefdfcfbfaf9f8 
+// opcode: aes64dsm ; op1:x22; op2:x30; dest:x16; op1val:0xf7f6f5f4f3f2f1f0;  op2val:0xfffefdfcfbfaf9f8
+TEST_RR_OP(aes64dsm, x16, x22, x30, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfffefdfcfbfaf9f8, x2, 24, x5)
+
+inst_23:
+// rs1==x6, rs2==x16, rd==x26, rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xe7e6e5e4e3e2e1e0 
+// opcode: aes64dsm ; op1:x6; op2:x16; dest:x26; op1val:0xefeeedecebeae9e8;  op2val:0xe7e6e5e4e3e2e1e0
+TEST_RR_OP(aes64dsm, x26, x6, x16, 0x0000000000000000, 0xefeeedecebeae9e8, 0xe7e6e5e4e3e2e1e0, x2, 32, x5)
+
+inst_24:
+// rs1==x25, rs2==x7, rd==x19, rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xefeeedecebeae9e8 
+// opcode: aes64dsm ; op1:x25; op2:x7; dest:x19; op1val:0xe7e6e5e4e3e2e1e0;  op2val:0xefeeedecebeae9e8
+TEST_RR_OP(aes64dsm, x19, x25, x7, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xefeeedecebeae9e8, x2, 40, x5)
+
+inst_25:
+// rs1==x29, rs2==x4, rd==x28, rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64dsm ; op1:x29; op2:x4; dest:x28; op1val:0xdfdedddcdbdad9d8;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64dsm, x28, x29, x4, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xd7d6d5d4d3d2d1d0, x2, 48, x5)
+
+inst_26:
+// rs1==x26, rs2==x23, rd==x17, rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdfdedddcdbdad9d8 
+// opcode: aes64dsm ; op1:x26; op2:x23; dest:x17; op1val:0xd7d6d5d4d3d2d1d0;  op2val:0xdfdedddcdbdad9d8
+TEST_RR_OP(aes64dsm, x17, x26, x23, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdfdedddcdbdad9d8, x2, 56, x5)
+
+inst_27:
+// rs1==x30, rs2==x3, rd==x8, rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xc7c6c5c4c3c2c1c0 
+// opcode: aes64dsm ; op1:x30; op2:x3; dest:x8; op1val:0xcfcecdcccbcac9c8;  op2val:0xc7c6c5c4c3c2c1c0
+TEST_RR_OP(aes64dsm, x8, x30, x3, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xc7c6c5c4c3c2c1c0, x2, 64, x5)
+
+inst_28:
+// rs1==x8, rs2==x25, rd==x27, rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcfcecdcccbcac9c8 
+// opcode: aes64dsm ; op1:x8; op2:x25; dest:x27; op1val:0xc7c6c5c4c3c2c1c0;  op2val:0xcfcecdcccbcac9c8
+TEST_RR_OP(aes64dsm, x27, x8, x25, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcfcecdcccbcac9c8, x2, 72, x5)
+
+inst_29:
+// rs1==x31, rs2==x0, rd==x18, rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xb7b6b5b4b3b2b1b0 
+// opcode: aes64dsm ; op1:x31; op2:x0; dest:x18; op1val:0xbfbebdbcbbbab9b8;  op2val:0x0
+TEST_RR_OP(aes64dsm, x18, x31, x0, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0x0, x2, 80, x5)
+
+inst_30:
+// rs1==x16, rs2==x14, rd==x10, rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbfbebdbcbbbab9b8 
+// opcode: aes64dsm ; op1:x16; op2:x14; dest:x10; op1val:0xb7b6b5b4b3b2b1b0;  op2val:0xbfbebdbcbbbab9b8
+TEST_RR_OP(aes64dsm, x10, x16, x14, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbfbebdbcbbbab9b8, x2, 88, x5)
+
+inst_31:
+// rs1==x3, rs2==x1, rd==x14, rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xa7a6a5a4a3a2a1a0 
+// opcode: aes64dsm ; op1:x3; op2:x1; dest:x14; op1val:0xafaeadacabaaa9a8;  op2val:0xa7a6a5a4a3a2a1a0
+TEST_RR_OP(aes64dsm, x14, x3, x1, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xa7a6a5a4a3a2a1a0, x2, 96, x5)
+
+inst_32:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xafaeadacabaaa9a8 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0xa7a6a5a4a3a2a1a0;  op2val:0xafaeadacabaaa9a8
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xafaeadacabaaa9a8, x2, 104, x5)
+
+inst_33:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0x9796959493929190 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x9f9e9d9c9b9a9998;  op2val:0x9796959493929190
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0x9796959493929190, x2, 112, x5)
+
+inst_34:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9f9e9d9c9b9a9998 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x9796959493929190;  op2val:0x9f9e9d9c9b9a9998
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x9796959493929190, 0x9f9e9d9c9b9a9998, x2, 120, x5)
+
+inst_35:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x8786858483828180 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x8f8e8d8c8b8a8988;  op2val:0x8786858483828180
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x8786858483828180, x2, 128, x5)
+
+inst_36:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8f8e8d8c8b8a8988 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x8786858483828180;  op2val:0x8f8e8d8c8b8a8988
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x8786858483828180, 0x8f8e8d8c8b8a8988, x2, 136, x5)
+
+inst_37:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x7776757473727170 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x7f7e7d7c7b7a7978;  op2val:0x7776757473727170
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x7776757473727170, x2, 144, x5)
+
+inst_38:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7f7e7d7c7b7a7978 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x7776757473727170;  op2val:0x7f7e7d7c7b7a7978
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x7776757473727170, 0x7f7e7d7c7b7a7978, x2, 152, x5)
+
+inst_39:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x6766656463626160 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x6f6e6d6c6b6a6968;  op2val:0x6766656463626160
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x6766656463626160, x2, 160, x5)
+
+inst_40:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6f6e6d6c6b6a6968 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x6766656463626160;  op2val:0x6f6e6d6c6b6a6968
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x6766656463626160, 0x6f6e6d6c6b6a6968, x2, 168, x5)
+
+inst_41:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x5756555453525150 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x5f5e5d5c5b5a5958;  op2val:0x5756555453525150
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x5756555453525150, x2, 176, x5)
+
+inst_42:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5f5e5d5c5b5a5958 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x5756555453525150;  op2val:0x5f5e5d5c5b5a5958
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x5756555453525150, 0x5f5e5d5c5b5a5958, x2, 184, x5)
+
+inst_43:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x4746454443424140 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x4f4e4d4c4b4a4948;  op2val:0x4746454443424140
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x4746454443424140, x2, 192, x5)
+
+inst_44:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4f4e4d4c4b4a4948 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x4746454443424140;  op2val:0x4f4e4d4c4b4a4948
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x4746454443424140, 0x4f4e4d4c4b4a4948, x2, 200, x5)
+
+inst_45:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x3736353433323130 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x3f3e3d3c3b3a3938;  op2val:0x3736353433323130
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x3736353433323130, x2, 208, x5)
+
+inst_46:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3f3e3d3c3b3a3938 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x3736353433323130;  op2val:0x3f3e3d3c3b3a3938
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x3736353433323130, 0x3f3e3d3c3b3a3938, x2, 216, x5)
+
+inst_47:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x2726252423222120 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x2f2e2d2c2b2a2928;  op2val:0x2726252423222120
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x2726252423222120, x2, 224, x5)
+
+inst_48:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2f2e2d2c2b2a2928 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x2726252423222120;  op2val:0x2f2e2d2c2b2a2928
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x2726252423222120, 0x2f2e2d2c2b2a2928, x2, 232, x5)
+
+inst_49:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x1716151413121110 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x1f1e1d1c1b1a1918;  op2val:0x1716151413121110
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x1716151413121110, x2, 240, x5)
+
+inst_50:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1f1e1d1c1b1a1918 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x1716151413121110;  op2val:0x1f1e1d1c1b1a1918
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x1716151413121110, 0x1f1e1d1c1b1a1918, x2, 248, x5)
+
+inst_51:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x0706050403020100 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0xf0e0d0c0b0a0908;  op2val:0x706050403020100
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x706050403020100, x2, 256, x5)
+
+inst_52:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x706050403020100;  op2val:0xf0e0d0c0b0a0908
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x706050403020100, 0xf0e0d0c0b0a0908, x2, 264, x5)
+
+inst_53:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x2, 272, x5)
+
+inst_54:
+// rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x2, 280, x5)
+
+inst_55:
+// rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x2, 288, x5)
+
+inst_56:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xb7b6b5b4b3b2b1b0 
+// opcode: aes64dsm ; op1:x10; op2:x11; dest:x12; op1val:0xbfbebdbcbbbab9b8;  op2val:0xb7b6b5b4b3b2b1b0
+TEST_RR_OP(aes64dsm, x12, x10, x11, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xb7b6b5b4b3b2b1b0, x2, 296, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 38*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S
new file mode 100644
index 000000000..9895fdffb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64dsm-rwp1.S
@@ -0,0 +1,389 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64dsm)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64dsm)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// 1st Instruction => rs1 = x1; rs2 = x2 | 2nd Instruction => rs1 = x2; rs2 = x1 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x1; op2:x2; dest1:x3; dest2:x4; dest3:x5; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x1, x1, x2;
+aes64dsm x3, x1, x2;
+aes64dsm x4, x2, x1;
+xor x5, x4, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x4,8);
+RVTEST_SIGUPD(x31,x5,16);
+
+inst_1:
+// 1st Instruction => rs1 = x2; rs2 = x3 | 2nd Instruction => rs1 = x3; rs2 = x2 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x2; op2:x3; dest1:x4; dest2:x5; dest3:x6; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x2, x2, x3;
+aes64dsm x4, x2, x3;
+aes64dsm x5, x3, x2;
+xor x6, x5, x3;
+RVTEST_SIGUPD(x31,x4,24);
+RVTEST_SIGUPD(x31,x5,32);
+RVTEST_SIGUPD(x31,x6,40);
+
+inst_2:
+// 1st Instruction => rs1 = x3; rs2 = x4 | 2nd Instruction => rs1 = x4; rs2 = x3 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x3; op2:x4; dest1:x5; dest2:x6; dest3:x7; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x3, x3, x4;
+aes64dsm x5, x3, x4;
+aes64dsm x6, x4, x3;
+xor x7, x6, x4;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+RVTEST_SIGUPD(x31,x7,64);
+
+inst_3:
+// 1st Instruction => rs1 = x4; rs2 = x5 | 2nd Instruction => rs1 = x5; rs2 = x4 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x4; op2:x5; dest1:x6; dest2:x7; dest3:x8; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x4, x4, x5;
+aes64dsm x6, x4, x5;
+aes64dsm x7, x5, x4;
+xor x8, x7, x5;
+RVTEST_SIGUPD(x31,x6,72);
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_4:
+// 1st Instruction => rs1 = x5; rs2 = x6 | 2nd Instruction => rs1 = x6; rs2 = x5 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x5; op2:x6; dest1:x7; dest2:x8; dest3:x9; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x5, x5, x6;
+aes64dsm x7, x5, x6;
+aes64dsm x8, x6, x5;
+xor x9, x8, x6;
+RVTEST_SIGUPD(x31,x7,96);
+RVTEST_SIGUPD(x31,x8,104);
+RVTEST_SIGUPD(x31,x9,112);
+
+inst_5:
+// 1st Instruction => rs1 = x6; rs2 = x7 | 2nd Instruction => rs1 = x7; rs2 = x6 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x6; op2:x7; dest1:x8; dest2:x9; dest3:x10; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x6, x6, x7;
+aes64dsm x8, x6, x7;
+aes64dsm x9, x7, x6;
+xor x10, x9, x7;
+RVTEST_SIGUPD(x31,x8,120);
+RVTEST_SIGUPD(x31,x9,128);
+RVTEST_SIGUPD(x31,x10,136);
+
+inst_6:
+// 1st Instruction => rs1 = x7; rs2 = x8 | 2nd Instruction => rs1 = x8; rs2 = x7 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x7; op2:x8; dest1:x9; dest2:x10; dest3:x11; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x7, x7, x8;
+aes64dsm x9, x7, x8;
+aes64dsm x10, x8, x7;
+xor x11, x10, x8;
+RVTEST_SIGUPD(x31,x9,144);
+RVTEST_SIGUPD(x31,x10,152);
+RVTEST_SIGUPD(x31,x11,160);
+
+inst_7:
+// 1st Instruction => rs1 = x8; rs2 = x9 | 2nd Instruction => rs1 = x9; rs2 = x8 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x8; op2:x9; dest1:x10; dest2:x11; dest3:x12; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x8, x8, x9;
+aes64dsm x10, x8, x9;
+aes64dsm x11, x9, x8;
+xor x12, x11, x9;
+RVTEST_SIGUPD(x31,x10,168);
+RVTEST_SIGUPD(x31,x11,176);
+RVTEST_SIGUPD(x31,x12,184);
+
+inst_8:
+// 1st Instruction => rs1 = x9; rs2 = x10 | 2nd Instruction => rs1 = x10; rs2 = x9 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x9; op2:x10; dest1:x11; dest2:x12; dest3:x13; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x9, x9, x10;
+aes64dsm x11, x9, x10;
+aes64dsm x12, x10, x9;
+xor x13, x12, x10;
+RVTEST_SIGUPD(x31,x11,192);
+RVTEST_SIGUPD(x31,x12,200);
+RVTEST_SIGUPD(x31,x13,208);
+
+inst_9:
+// 1st Instruction => rs1 = x10; rs2 = x11 | 2nd Instruction => rs1 = x11; rs2 = x10 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x10; op2:x11; dest1:x12; dest2:x13; dest3:x14; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x10, x10, x11;
+aes64dsm x12, x10, x11;
+aes64dsm x13, x11, x10;
+xor x14, x13, x11;
+RVTEST_SIGUPD(x31,x12,216);
+RVTEST_SIGUPD(x31,x13,224);
+RVTEST_SIGUPD(x31,x14,232);
+
+inst_10:
+// 1st Instruction => rs1 = x11; rs2 = x12 | 2nd Instruction => rs1 = x12; rs2 = x11 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x11; op2:x12; dest1:x13; dest2:x14; dest3:x15; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x11, x11, x12;
+aes64dsm x13, x11, x12;
+aes64dsm x14, x12, x11;
+xor x15, x14, x12;
+RVTEST_SIGUPD(x31,x13,240);
+RVTEST_SIGUPD(x31,x14,248);
+RVTEST_SIGUPD(x31,x15,256);
+
+inst_11:
+// 1st Instruction => rs1 = x12; rs2 = x13 | 2nd Instruction => rs1 = x13; rs2 = x12 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x12; op2:x13; dest1:x14; dest2:x15; dest3:x16; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x12, x12, x13;
+aes64dsm x14, x12, x13;
+aes64dsm x15, x13, x12;
+xor x16, x15, x13;
+RVTEST_SIGUPD(x31,x14,264);
+RVTEST_SIGUPD(x31,x15,272);
+RVTEST_SIGUPD(x31,x16,280);
+
+inst_12:
+// 1st Instruction => rs1 = x13; rs2 = x14 | 2nd Instruction => rs1 = x14; rs2 = x13 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x13; op2:x14; dest1:x15; dest2:x16; dest3:x17; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x13, x13, x14;
+aes64dsm x15, x13, x14;
+aes64dsm x16, x14, x13;
+xor x17, x16, x14;
+RVTEST_SIGUPD(x31,x15,288);
+RVTEST_SIGUPD(x31,x16,296);
+RVTEST_SIGUPD(x31,x17,304);
+
+inst_13:
+// 1st Instruction => rs1 = x14; rs2 = x15 | 2nd Instruction => rs1 = x15; rs2 = x14 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x14; op2:x15; dest1:x16; dest2:x17; dest3:x18; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x14, x14, x15;
+aes64dsm x16, x14, x15;
+aes64dsm x17, x15, x14;
+xor x18, x17, x15;
+RVTEST_SIGUPD(x31,x16,312);
+RVTEST_SIGUPD(x31,x17,320);
+RVTEST_SIGUPD(x31,x18,328);
+
+inst_14:
+// 1st Instruction => rs1 = x15; rs2 = x16 | 2nd Instruction => rs1 = x16; rs2 = x15 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x15; op2:x16; dest1:x17; dest2:x18; dest3:x19; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x15, x15, x16;
+aes64dsm x17, x15, x16;
+aes64dsm x18, x16, x15;
+xor x19, x18, x16;
+RVTEST_SIGUPD(x31,x17,336);
+RVTEST_SIGUPD(x31,x18,344);
+RVTEST_SIGUPD(x31,x19,352);
+
+inst_15:
+// 1st Instruction => rs1 = x16; rs2 = x17 | 2nd Instruction => rs1 = x17; rs2 = x16 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x16; op2:x17; dest1:x18; dest2:x19; dest3:x20; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x16, x16, x17;
+aes64dsm x18, x16, x17;
+aes64dsm x19, x17, x16;
+xor x20, x19, x17;
+RVTEST_SIGUPD(x31,x18,360);
+RVTEST_SIGUPD(x31,x19,368);
+RVTEST_SIGUPD(x31,x20,376);
+
+inst_16:
+// 1st Instruction => rs1 = x17; rs2 = x18 | 2nd Instruction => rs1 = x18; rs2 = x17 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x17; op2:x18; dest1:x19; dest2:x20; dest3:x21; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x17, x17, x18;
+aes64dsm x19, x17, x18;
+aes64dsm x20, x18, x17;
+xor x21, x20, x18;
+RVTEST_SIGUPD(x31,x19,384);
+RVTEST_SIGUPD(x31,x20,392);
+RVTEST_SIGUPD(x31,x21,400);
+
+inst_17:
+// 1st Instruction => rs1 = x18; rs2 = x19 | 2nd Instruction => rs1 = x19; rs2 = x18 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x18; op2:x19; dest1:x20; dest2:x21; dest3:x22; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x18, x18, x19;
+aes64dsm x20, x18, x19;
+aes64dsm x21, x19, x18;
+xor x22, x21, x19;
+RVTEST_SIGUPD(x31,x20,408);
+RVTEST_SIGUPD(x31,x21,416);
+RVTEST_SIGUPD(x31,x22,424);
+
+inst_18:
+// 1st Instruction => rs1 = x19; rs2 = x20 | 2nd Instruction => rs1 = x20; rs2 = x19 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x19; op2:x20; dest1:x21; dest2:x22; dest3:x23; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x19, x19, x20;
+aes64dsm x21, x19, x20;
+aes64dsm x22, x20, x19;
+xor x23, x22, x20;
+RVTEST_SIGUPD(x31,x21,432);
+RVTEST_SIGUPD(x31,x22,440);
+RVTEST_SIGUPD(x31,x23,448);
+
+inst_19:
+// 1st Instruction => rs1 = x20; rs2 = x21 | 2nd Instruction => rs1 = x21; rs2 = x20 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x20; op2:x21; dest1:x22; dest2:x23; dest3:x24; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x20, x20, x21;
+aes64dsm x22, x20, x21;
+aes64dsm x23, x21, x20;
+xor x24, x23, x21;
+RVTEST_SIGUPD(x31,x22,456);
+RVTEST_SIGUPD(x31,x23,464);
+RVTEST_SIGUPD(x31,x24,472);
+
+inst_20:
+// 1st Instruction => rs1 = x21; rs2 = x22 | 2nd Instruction => rs1 = x22; rs2 = x21 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x21; op2:x22; dest1:x23; dest2:x24; dest3:x25; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x21, x21, x22;
+aes64dsm x23, x21, x22;
+aes64dsm x24, x22, x21;
+xor x25, x24, x22;
+RVTEST_SIGUPD(x31,x23,480);
+RVTEST_SIGUPD(x31,x24,488);
+RVTEST_SIGUPD(x31,x25,496);
+
+inst_21:
+// 1st Instruction => rs1 = x22; rs2 = x23 | 2nd Instruction => rs1 = x23; rs2 = x22 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x22; op2:x23; dest1:x24; dest2:x25; dest3:x26; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x22, x22, x23;
+aes64dsm x24, x22, x23;
+aes64dsm x25, x23, x22;
+xor x26, x25, x23;
+RVTEST_SIGUPD(x31,x24,504);
+RVTEST_SIGUPD(x31,x25,512);
+RVTEST_SIGUPD(x31,x26,520);
+
+inst_22:
+// 1st Instruction => rs1 = x23; rs2 = x24 | 2nd Instruction => rs1 = x24; rs2 = x23 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x23; op2:x24; dest1:x25; dest2:x26; dest3:x27; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x23, x23, x24;
+aes64dsm x25, x23, x24;
+aes64dsm x26, x24, x23;
+xor x27, x26, x24;
+RVTEST_SIGUPD(x31,x25,528);
+RVTEST_SIGUPD(x31,x26,536);
+RVTEST_SIGUPD(x31,x27,544);
+
+inst_23:
+// 1st Instruction => rs1 = x24; rs2 = x25 | 2nd Instruction => rs1 = x25; rs2 = x24 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x24; op2:x25; dest1:x26; dest2:x27; dest3:x28; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x24, x24, x25;
+aes64dsm x26, x24, x25;
+aes64dsm x27, x25, x24;
+xor x28, x27, x25;
+RVTEST_SIGUPD(x31,x26,552);
+RVTEST_SIGUPD(x31,x27,560);
+RVTEST_SIGUPD(x31,x28,568);
+
+inst_24:
+// 1st Instruction => rs1 = x25; rs2 = x26 | 2nd Instruction => rs1 = x26; rs2 = x25 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x25; op2:x26; dest1:x27; dest2:x28; dest3:x29; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x25, x25, x26;
+aes64dsm x27, x25, x26;
+aes64dsm x28, x26, x25;
+xor x29, x28, x26;
+RVTEST_SIGUPD(x31,x27,576);
+RVTEST_SIGUPD(x31,x28,584);
+RVTEST_SIGUPD(x31,x29,592);
+
+inst_25:
+// 1st Instruction => rs1 = x26; rs2 = x27 | 2nd Instruction => rs1 = x27; rs2 = x26 | Result of xor goes into aes64dsm & vice versa
+// opcode: aes64dsm; op1:x26; op2:x27; dest1:x28; dest2:x29; dest3:x30; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x26, x26, x27;
+aes64dsm x28, x26, x27;
+aes64dsm x29, x27, x26;
+xor x30, x29, x27;
+RVTEST_SIGUPD(x31,x28,600);
+RVTEST_SIGUPD(x31,x29,608);
+RVTEST_SIGUPD(x31,x30,616);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 78*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S
new file mode 100644
index 000000000..e870378f8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-01.S
@@ -0,0 +1,364 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64es instruction of the RISC-V  extension for the aes64es covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64es)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64es)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKne.*);def TEST_CASE_1=True;",aes64es)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x7, rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64es ; op1:x8; op2:x8; dest:x7; op1val:0x706050403020100;  op2val:0x706050403020100
+TEST_RR_OP(aes64es, x7, x8, x8, 0x0000000000000000, 0x706050403020100, 0x706050403020100, x6, 0, x2)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x19, rs2==x19, rd==x19, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64es ; op1:x19; op2:x19; dest:x19; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(aes64es, x19, x19, x19, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x6, 8, x2)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x20, rd==x26, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: aes64es ; op1:x10; op2:x20; dest:x26; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(aes64es, x26, x10, x20, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x6, 16, x2)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x13, rs2==x7, rd==x13, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: aes64es ; op1:x13; op2:x7; dest:x13; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(aes64es, x13, x13, x7, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x6, 24, x2)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x29, rs2==x14, rd==x14, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64es ; op1:x29; op2:x14; dest:x14; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64es, x14, x29, x14, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x6, 32, x2)
+
+inst_5:
+// rs1==x15, rs2==x22, rd==x1, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: aes64es ; op1:x15; op2:x22; dest:x1; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(aes64es, x1, x15, x22, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x6, 40, x2)
+
+inst_6:
+// rs1==x30, rs2==x13, rd==x21, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64es ; op1:x30; op2:x13; dest:x21; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64es, x21, x30, x13, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x6, 48, x2)
+
+inst_7:
+// rs1==x11, rs2==x9, rd==x20, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64es ; op1:x11; op2:x9; dest:x20; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64es, x20, x11, x9, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x6, 56, x2)
+
+inst_8:
+// rs1==x20, rs2==x12, rd==x17, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: aes64es ; op1:x20; op2:x12; dest:x17; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(aes64es, x17, x20, x12, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x6, 64, x2)
+
+inst_9:
+// rs1==x31, rs2==x29, rd==x8, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: aes64es ; op1:x31; op2:x29; dest:x8; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(aes64es, x8, x31, x29, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x6, 72, x2)
+
+inst_10:
+// rs1==x0, rs2==x15, rd==x23, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64es ; op1:x0; op2:x15; dest:x23; op1val:0x0;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64es, x23, x0, x15, 0x0000000000000000, 0x0, 0x53a66ed1dc80d916, x6, 80, x2)
+
+inst_11:
+// rs1==x9, rs2==x16, rd==x12, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64es ; op1:x9; op2:x16; dest:x12; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64es, x12, x9, x16, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x6, 88, x2)
+
+inst_12:
+// rs1==x17, rs2==x28, rd==x5, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: aes64es ; op1:x17; op2:x28; dest:x5; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(aes64es, x5, x17, x28, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x6, 96, x2)
+
+inst_13:
+// rs1==x18, rs2==x1, rd==x4, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64es ; op1:x18; op2:x1; dest:x4; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(aes64es, x4, x18, x1, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x6, 104, x2)
+
+inst_14:
+// rs1==x25, rs2==x4, rd==x31, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: aes64es ; op1:x25; op2:x4; dest:x31; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(aes64es, x31, x25, x4, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x6, 112, x2)
+
+inst_15:
+// rs1==x7, rs2==x17, rd==x10, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: aes64es ; op1:x7; op2:x17; dest:x10; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(aes64es, x10, x7, x17, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x6, 120, x2)
+
+inst_16:
+// rs1==x28, rs2==x23, rd==x9, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: aes64es ; op1:x28; op2:x23; dest:x9; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(aes64es, x9, x28, x23, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x6, 128, x2)
+
+inst_17:
+// rs1==x23, rs2==x3, rd==x28, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: aes64es ; op1:x23; op2:x3; dest:x28; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(aes64es, x28, x23, x3, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x6, 136, x2)
+
+inst_18:
+// rs1==x12, rs2==x18, rd==x2, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: aes64es ; op1:x12; op2:x18; dest:x2; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(aes64es, x2, x12, x18, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x6, 144, x8)
+RVTEST_SIGBASE( x7,signature_x7_0)
+
+inst_19:
+// rs1==x26, rs2==x10, rd==x29, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: aes64es ; op1:x26; op2:x10; dest:x29; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(aes64es, x29, x26, x10, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x7, 0, x8)
+
+inst_20:
+// rs1==x24, rs2==x27, rd==x22, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64es ; op1:x24; op2:x27; dest:x22; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(aes64es, x22, x24, x27, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x7, 8, x8)
+
+inst_21:
+// rs1==x27, rs2==x31, rd==x3, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0xf7f6f5f4f3f2f1f0 
+// opcode: aes64es ; op1:x27; op2:x31; dest:x3; op1val:0xfffefdfcfbfaf9f8;  op2val:0xf7f6f5f4f3f2f1f0
+TEST_RR_OP(aes64es, x3, x27, x31, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0xf7f6f5f4f3f2f1f0, x7, 16, x8)
+
+inst_22:
+// rs1==x1, rs2==x2, rd==x24, rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfffefdfcfbfaf9f8 
+// opcode: aes64es ; op1:x1; op2:x2; dest:x24; op1val:0xf7f6f5f4f3f2f1f0;  op2val:0xfffefdfcfbfaf9f8
+TEST_RR_OP(aes64es, x24, x1, x2, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfffefdfcfbfaf9f8, x7, 24, x8)
+
+inst_23:
+// rs1==x22, rs2==x26, rd==x16, rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xe7e6e5e4e3e2e1e0 
+// opcode: aes64es ; op1:x22; op2:x26; dest:x16; op1val:0xefeeedecebeae9e8;  op2val:0xe7e6e5e4e3e2e1e0
+TEST_RR_OP(aes64es, x16, x22, x26, 0x0000000000000000, 0xefeeedecebeae9e8, 0xe7e6e5e4e3e2e1e0, x7, 32, x8)
+
+inst_24:
+// rs1==x3, rs2==x21, rd==x15, rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xefeeedecebeae9e8 
+// opcode: aes64es ; op1:x3; op2:x21; dest:x15; op1val:0xe7e6e5e4e3e2e1e0;  op2val:0xefeeedecebeae9e8
+TEST_RR_OP(aes64es, x15, x3, x21, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xefeeedecebeae9e8, x7, 40, x8)
+
+inst_25:
+// rs1==x14, rs2==x6, rd==x0, rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64es ; op1:x14; op2:x6; dest:x0; op1val:0xdfdedddcdbdad9d8;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64es, x0, x14, x6, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xd7d6d5d4d3d2d1d0, x7, 48, x8)
+
+inst_26:
+// rs1==x5, rs2==x24, rd==x6, rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdfdedddcdbdad9d8 
+// opcode: aes64es ; op1:x5; op2:x24; dest:x6; op1val:0xd7d6d5d4d3d2d1d0;  op2val:0xdfdedddcdbdad9d8
+TEST_RR_OP(aes64es, x6, x5, x24, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdfdedddcdbdad9d8, x7, 56, x8)
+
+inst_27:
+// rs1==x16, rs2==x0, rd==x18, rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xc7c6c5c4c3c2c1c0 
+// opcode: aes64es ; op1:x16; op2:x0; dest:x18; op1val:0xcfcecdcccbcac9c8;  op2val:0x0
+TEST_RR_OP(aes64es, x18, x16, x0, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0x0, x7, 64, x8)
+
+inst_28:
+// rs1==x2, rs2==x25, rd==x30, rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcfcecdcccbcac9c8 
+// opcode: aes64es ; op1:x2; op2:x25; dest:x30; op1val:0xc7c6c5c4c3c2c1c0;  op2val:0xcfcecdcccbcac9c8
+TEST_RR_OP(aes64es, x30, x2, x25, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcfcecdcccbcac9c8, x7, 72, x8)
+
+inst_29:
+// rs1==x4, rs2==x30, rd==x11, rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xb7b6b5b4b3b2b1b0 
+// opcode: aes64es ; op1:x4; op2:x30; dest:x11; op1val:0xbfbebdbcbbbab9b8;  op2val:0xb7b6b5b4b3b2b1b0
+TEST_RR_OP(aes64es, x11, x4, x30, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xb7b6b5b4b3b2b1b0, x7, 80, x8)
+
+inst_30:
+// rs1==x6, rs2==x11, rd==x25, rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbfbebdbcbbbab9b8 
+// opcode: aes64es ; op1:x6; op2:x11; dest:x25; op1val:0xb7b6b5b4b3b2b1b0;  op2val:0xbfbebdbcbbbab9b8
+TEST_RR_OP(aes64es, x25, x6, x11, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbfbebdbcbbbab9b8, x7, 88, x8)
+
+inst_31:
+// rs1==x21, rs2==x5, rd==x27, rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xa7a6a5a4a3a2a1a0 
+// opcode: aes64es ; op1:x21; op2:x5; dest:x27; op1val:0xafaeadacabaaa9a8;  op2val:0xa7a6a5a4a3a2a1a0
+TEST_RR_OP(aes64es, x27, x21, x5, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xa7a6a5a4a3a2a1a0, x7, 96, x8)
+
+inst_32:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xafaeadacabaaa9a8 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0xa7a6a5a4a3a2a1a0;  op2val:0xafaeadacabaaa9a8
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xafaeadacabaaa9a8, x7, 104, x8)
+
+inst_33:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0x9796959493929190 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x9f9e9d9c9b9a9998;  op2val:0x9796959493929190
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0x9796959493929190, x7, 112, x8)
+
+inst_34:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9f9e9d9c9b9a9998 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x9796959493929190;  op2val:0x9f9e9d9c9b9a9998
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x9796959493929190, 0x9f9e9d9c9b9a9998, x7, 120, x8)
+
+inst_35:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x8786858483828180 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x8f8e8d8c8b8a8988;  op2val:0x8786858483828180
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x8786858483828180, x7, 128, x8)
+
+inst_36:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8f8e8d8c8b8a8988 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x8786858483828180;  op2val:0x8f8e8d8c8b8a8988
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x8786858483828180, 0x8f8e8d8c8b8a8988, x7, 136, x8)
+
+inst_37:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x7776757473727170 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x7f7e7d7c7b7a7978;  op2val:0x7776757473727170
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x7776757473727170, x7, 144, x8)
+
+inst_38:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7f7e7d7c7b7a7978 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x7776757473727170;  op2val:0x7f7e7d7c7b7a7978
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x7776757473727170, 0x7f7e7d7c7b7a7978, x7, 152, x8)
+
+inst_39:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x6766656463626160 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x6f6e6d6c6b6a6968;  op2val:0x6766656463626160
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x6766656463626160, x7, 160, x8)
+
+inst_40:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6f6e6d6c6b6a6968 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x6766656463626160;  op2val:0x6f6e6d6c6b6a6968
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x6766656463626160, 0x6f6e6d6c6b6a6968, x7, 168, x8)
+
+inst_41:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x5756555453525150 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x5f5e5d5c5b5a5958;  op2val:0x5756555453525150
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x5756555453525150, x7, 176, x8)
+
+inst_42:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5f5e5d5c5b5a5958 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x5756555453525150;  op2val:0x5f5e5d5c5b5a5958
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x5756555453525150, 0x5f5e5d5c5b5a5958, x7, 184, x8)
+
+inst_43:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x4746454443424140 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x4f4e4d4c4b4a4948;  op2val:0x4746454443424140
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x4746454443424140, x7, 192, x8)
+
+inst_44:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4f4e4d4c4b4a4948 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x4746454443424140;  op2val:0x4f4e4d4c4b4a4948
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x4746454443424140, 0x4f4e4d4c4b4a4948, x7, 200, x8)
+
+inst_45:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x3736353433323130 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x3f3e3d3c3b3a3938;  op2val:0x3736353433323130
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x3736353433323130, x7, 208, x8)
+
+inst_46:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3f3e3d3c3b3a3938 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x3736353433323130;  op2val:0x3f3e3d3c3b3a3938
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x3736353433323130, 0x3f3e3d3c3b3a3938, x7, 216, x8)
+
+inst_47:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x2726252423222120 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x2f2e2d2c2b2a2928;  op2val:0x2726252423222120
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x2726252423222120, x7, 224, x8)
+
+inst_48:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2f2e2d2c2b2a2928 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x2726252423222120;  op2val:0x2f2e2d2c2b2a2928
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x2726252423222120, 0x2f2e2d2c2b2a2928, x7, 232, x8)
+
+inst_49:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x1716151413121110 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x1f1e1d1c1b1a1918;  op2val:0x1716151413121110
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x1716151413121110, x7, 240, x8)
+
+inst_50:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1f1e1d1c1b1a1918 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x1716151413121110;  op2val:0x1f1e1d1c1b1a1918
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x1716151413121110, 0x1f1e1d1c1b1a1918, x7, 248, x8)
+
+inst_51:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x0706050403020100 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0xf0e0d0c0b0a0908;  op2val:0x706050403020100
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x706050403020100, x7, 256, x8)
+
+inst_52:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x706050403020100;  op2val:0xf0e0d0c0b0a0908
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x706050403020100, 0xf0e0d0c0b0a0908, x7, 264, x8)
+
+inst_53:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x7, 272, x8)
+
+inst_54:
+// rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x7, 280, x8)
+
+inst_55:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0xdfdedddcdbdad9d8;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xd7d6d5d4d3d2d1d0, x7, 288, x8)
+
+inst_56:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xc7c6c5c4c3c2c1c0 
+// opcode: aes64es ; op1:x10; op2:x11; dest:x12; op1val:0xcfcecdcccbcac9c8;  op2val:0xc7c6c5c4c3c2c1c0
+TEST_RR_OP(aes64es, x12, x10, x11, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xc7c6c5c4c3c2c1c0, x7, 296, x8)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_0:
+    .fill 38*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S
new file mode 100644
index 000000000..135f6a5e5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64es-rwp1.S
@@ -0,0 +1,389 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64es)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64es)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// 1st Instruction => rs1 = x1; rs2 = x2 | 2nd Instruction => rs1 = x2; rs2 = x1 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x1; op2:x2; dest1:x3; dest2:x4; dest3:x5; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x1, x1, x2;
+aes64es x3, x1, x2;
+aes64es x4, x2, x1;
+xor x5, x4, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x4,8);
+RVTEST_SIGUPD(x31,x5,16);
+
+inst_1:
+// 1st Instruction => rs1 = x2; rs2 = x3 | 2nd Instruction => rs1 = x3; rs2 = x2 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x2; op2:x3; dest1:x4; dest2:x5; dest3:x6; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x2, x2, x3;
+aes64es x4, x2, x3;
+aes64es x5, x3, x2;
+xor x6, x5, x3;
+RVTEST_SIGUPD(x31,x4,24);
+RVTEST_SIGUPD(x31,x5,32);
+RVTEST_SIGUPD(x31,x6,40);
+
+inst_2:
+// 1st Instruction => rs1 = x3; rs2 = x4 | 2nd Instruction => rs1 = x4; rs2 = x3 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x3; op2:x4; dest1:x5; dest2:x6; dest3:x7; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x3, x3, x4;
+aes64es x5, x3, x4;
+aes64es x6, x4, x3;
+xor x7, x6, x4;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+RVTEST_SIGUPD(x31,x7,64);
+
+inst_3:
+// 1st Instruction => rs1 = x4; rs2 = x5 | 2nd Instruction => rs1 = x5; rs2 = x4 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x4; op2:x5; dest1:x6; dest2:x7; dest3:x8; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x4, x4, x5;
+aes64es x6, x4, x5;
+aes64es x7, x5, x4;
+xor x8, x7, x5;
+RVTEST_SIGUPD(x31,x6,72);
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_4:
+// 1st Instruction => rs1 = x5; rs2 = x6 | 2nd Instruction => rs1 = x6; rs2 = x5 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x5; op2:x6; dest1:x7; dest2:x8; dest3:x9; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x5, x5, x6;
+aes64es x7, x5, x6;
+aes64es x8, x6, x5;
+xor x9, x8, x6;
+RVTEST_SIGUPD(x31,x7,96);
+RVTEST_SIGUPD(x31,x8,104);
+RVTEST_SIGUPD(x31,x9,112);
+
+inst_5:
+// 1st Instruction => rs1 = x6; rs2 = x7 | 2nd Instruction => rs1 = x7; rs2 = x6 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x6; op2:x7; dest1:x8; dest2:x9; dest3:x10; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x6, x6, x7;
+aes64es x8, x6, x7;
+aes64es x9, x7, x6;
+xor x10, x9, x7;
+RVTEST_SIGUPD(x31,x8,120);
+RVTEST_SIGUPD(x31,x9,128);
+RVTEST_SIGUPD(x31,x10,136);
+
+inst_6:
+// 1st Instruction => rs1 = x7; rs2 = x8 | 2nd Instruction => rs1 = x8; rs2 = x7 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x7; op2:x8; dest1:x9; dest2:x10; dest3:x11; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x7, x7, x8;
+aes64es x9, x7, x8;
+aes64es x10, x8, x7;
+xor x11, x10, x8;
+RVTEST_SIGUPD(x31,x9,144);
+RVTEST_SIGUPD(x31,x10,152);
+RVTEST_SIGUPD(x31,x11,160);
+
+inst_7:
+// 1st Instruction => rs1 = x8; rs2 = x9 | 2nd Instruction => rs1 = x9; rs2 = x8 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x8; op2:x9; dest1:x10; dest2:x11; dest3:x12; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x8, x8, x9;
+aes64es x10, x8, x9;
+aes64es x11, x9, x8;
+xor x12, x11, x9;
+RVTEST_SIGUPD(x31,x10,168);
+RVTEST_SIGUPD(x31,x11,176);
+RVTEST_SIGUPD(x31,x12,184);
+
+inst_8:
+// 1st Instruction => rs1 = x9; rs2 = x10 | 2nd Instruction => rs1 = x10; rs2 = x9 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x9; op2:x10; dest1:x11; dest2:x12; dest3:x13; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x9, x9, x10;
+aes64es x11, x9, x10;
+aes64es x12, x10, x9;
+xor x13, x12, x10;
+RVTEST_SIGUPD(x31,x11,192);
+RVTEST_SIGUPD(x31,x12,200);
+RVTEST_SIGUPD(x31,x13,208);
+
+inst_9:
+// 1st Instruction => rs1 = x10; rs2 = x11 | 2nd Instruction => rs1 = x11; rs2 = x10 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x10; op2:x11; dest1:x12; dest2:x13; dest3:x14; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x10, x10, x11;
+aes64es x12, x10, x11;
+aes64es x13, x11, x10;
+xor x14, x13, x11;
+RVTEST_SIGUPD(x31,x12,216);
+RVTEST_SIGUPD(x31,x13,224);
+RVTEST_SIGUPD(x31,x14,232);
+
+inst_10:
+// 1st Instruction => rs1 = x11; rs2 = x12 | 2nd Instruction => rs1 = x12; rs2 = x11 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x11; op2:x12; dest1:x13; dest2:x14; dest3:x15; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x11, x11, x12;
+aes64es x13, x11, x12;
+aes64es x14, x12, x11;
+xor x15, x14, x12;
+RVTEST_SIGUPD(x31,x13,240);
+RVTEST_SIGUPD(x31,x14,248);
+RVTEST_SIGUPD(x31,x15,256);
+
+inst_11:
+// 1st Instruction => rs1 = x12; rs2 = x13 | 2nd Instruction => rs1 = x13; rs2 = x12 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x12; op2:x13; dest1:x14; dest2:x15; dest3:x16; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x12, x12, x13;
+aes64es x14, x12, x13;
+aes64es x15, x13, x12;
+xor x16, x15, x13;
+RVTEST_SIGUPD(x31,x14,264);
+RVTEST_SIGUPD(x31,x15,272);
+RVTEST_SIGUPD(x31,x16,280);
+
+inst_12:
+// 1st Instruction => rs1 = x13; rs2 = x14 | 2nd Instruction => rs1 = x14; rs2 = x13 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x13; op2:x14; dest1:x15; dest2:x16; dest3:x17; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x13, x13, x14;
+aes64es x15, x13, x14;
+aes64es x16, x14, x13;
+xor x17, x16, x14;
+RVTEST_SIGUPD(x31,x15,288);
+RVTEST_SIGUPD(x31,x16,296);
+RVTEST_SIGUPD(x31,x17,304);
+
+inst_13:
+// 1st Instruction => rs1 = x14; rs2 = x15 | 2nd Instruction => rs1 = x15; rs2 = x14 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x14; op2:x15; dest1:x16; dest2:x17; dest3:x18; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x14, x14, x15;
+aes64es x16, x14, x15;
+aes64es x17, x15, x14;
+xor x18, x17, x15;
+RVTEST_SIGUPD(x31,x16,312);
+RVTEST_SIGUPD(x31,x17,320);
+RVTEST_SIGUPD(x31,x18,328);
+
+inst_14:
+// 1st Instruction => rs1 = x15; rs2 = x16 | 2nd Instruction => rs1 = x16; rs2 = x15 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x15; op2:x16; dest1:x17; dest2:x18; dest3:x19; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x15, x15, x16;
+aes64es x17, x15, x16;
+aes64es x18, x16, x15;
+xor x19, x18, x16;
+RVTEST_SIGUPD(x31,x17,336);
+RVTEST_SIGUPD(x31,x18,344);
+RVTEST_SIGUPD(x31,x19,352);
+
+inst_15:
+// 1st Instruction => rs1 = x16; rs2 = x17 | 2nd Instruction => rs1 = x17; rs2 = x16 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x16; op2:x17; dest1:x18; dest2:x19; dest3:x20; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x16, x16, x17;
+aes64es x18, x16, x17;
+aes64es x19, x17, x16;
+xor x20, x19, x17;
+RVTEST_SIGUPD(x31,x18,360);
+RVTEST_SIGUPD(x31,x19,368);
+RVTEST_SIGUPD(x31,x20,376);
+
+inst_16:
+// 1st Instruction => rs1 = x17; rs2 = x18 | 2nd Instruction => rs1 = x18; rs2 = x17 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x17; op2:x18; dest1:x19; dest2:x20; dest3:x21; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x17, x17, x18;
+aes64es x19, x17, x18;
+aes64es x20, x18, x17;
+xor x21, x20, x18;
+RVTEST_SIGUPD(x31,x19,384);
+RVTEST_SIGUPD(x31,x20,392);
+RVTEST_SIGUPD(x31,x21,400);
+
+inst_17:
+// 1st Instruction => rs1 = x18; rs2 = x19 | 2nd Instruction => rs1 = x19; rs2 = x18 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x18; op2:x19; dest1:x20; dest2:x21; dest3:x22; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x18, x18, x19;
+aes64es x20, x18, x19;
+aes64es x21, x19, x18;
+xor x22, x21, x19;
+RVTEST_SIGUPD(x31,x20,408);
+RVTEST_SIGUPD(x31,x21,416);
+RVTEST_SIGUPD(x31,x22,424);
+
+inst_18:
+// 1st Instruction => rs1 = x19; rs2 = x20 | 2nd Instruction => rs1 = x20; rs2 = x19 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x19; op2:x20; dest1:x21; dest2:x22; dest3:x23; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x19, x19, x20;
+aes64es x21, x19, x20;
+aes64es x22, x20, x19;
+xor x23, x22, x20;
+RVTEST_SIGUPD(x31,x21,432);
+RVTEST_SIGUPD(x31,x22,440);
+RVTEST_SIGUPD(x31,x23,448);
+
+inst_19:
+// 1st Instruction => rs1 = x20; rs2 = x21 | 2nd Instruction => rs1 = x21; rs2 = x20 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x20; op2:x21; dest1:x22; dest2:x23; dest3:x24; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x20, x20, x21;
+aes64es x22, x20, x21;
+aes64es x23, x21, x20;
+xor x24, x23, x21;
+RVTEST_SIGUPD(x31,x22,456);
+RVTEST_SIGUPD(x31,x23,464);
+RVTEST_SIGUPD(x31,x24,472);
+
+inst_20:
+// 1st Instruction => rs1 = x21; rs2 = x22 | 2nd Instruction => rs1 = x22; rs2 = x21 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x21; op2:x22; dest1:x23; dest2:x24; dest3:x25; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x21, x21, x22;
+aes64es x23, x21, x22;
+aes64es x24, x22, x21;
+xor x25, x24, x22;
+RVTEST_SIGUPD(x31,x23,480);
+RVTEST_SIGUPD(x31,x24,488);
+RVTEST_SIGUPD(x31,x25,496);
+
+inst_21:
+// 1st Instruction => rs1 = x22; rs2 = x23 | 2nd Instruction => rs1 = x23; rs2 = x22 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x22; op2:x23; dest1:x24; dest2:x25; dest3:x26; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x22, x22, x23;
+aes64es x24, x22, x23;
+aes64es x25, x23, x22;
+xor x26, x25, x23;
+RVTEST_SIGUPD(x31,x24,504);
+RVTEST_SIGUPD(x31,x25,512);
+RVTEST_SIGUPD(x31,x26,520);
+
+inst_22:
+// 1st Instruction => rs1 = x23; rs2 = x24 | 2nd Instruction => rs1 = x24; rs2 = x23 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x23; op2:x24; dest1:x25; dest2:x26; dest3:x27; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x23, x23, x24;
+aes64es x25, x23, x24;
+aes64es x26, x24, x23;
+xor x27, x26, x24;
+RVTEST_SIGUPD(x31,x25,528);
+RVTEST_SIGUPD(x31,x26,536);
+RVTEST_SIGUPD(x31,x27,544);
+
+inst_23:
+// 1st Instruction => rs1 = x24; rs2 = x25 | 2nd Instruction => rs1 = x25; rs2 = x24 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x24; op2:x25; dest1:x26; dest2:x27; dest3:x28; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x24, x24, x25;
+aes64es x26, x24, x25;
+aes64es x27, x25, x24;
+xor x28, x27, x25;
+RVTEST_SIGUPD(x31,x26,552);
+RVTEST_SIGUPD(x31,x27,560);
+RVTEST_SIGUPD(x31,x28,568);
+
+inst_24:
+// 1st Instruction => rs1 = x25; rs2 = x26 | 2nd Instruction => rs1 = x26; rs2 = x25 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x25; op2:x26; dest1:x27; dest2:x28; dest3:x29; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x25, x25, x26;
+aes64es x27, x25, x26;
+aes64es x28, x26, x25;
+xor x29, x28, x26;
+RVTEST_SIGUPD(x31,x27,576);
+RVTEST_SIGUPD(x31,x28,584);
+RVTEST_SIGUPD(x31,x29,592);
+
+inst_25:
+// 1st Instruction => rs1 = x26; rs2 = x27 | 2nd Instruction => rs1 = x27; rs2 = x26 | Result of xor goes into aes64es & vice versa
+// opcode: aes64es; op1:x26; op2:x27; dest1:x28; dest2:x29; dest3:x30; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x26, x26, x27;
+aes64es x28, x26, x27;
+aes64es x29, x27, x26;
+xor x30, x29, x27;
+RVTEST_SIGUPD(x31,x28,600);
+RVTEST_SIGUPD(x31,x29,608);
+RVTEST_SIGUPD(x31,x30,616);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 78*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S
new file mode 100644
index 000000000..b623390e8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-01.S
@@ -0,0 +1,364 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64esm instruction of the RISC-V  extension for the aes64esm covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64esm)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64esm)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKne.*);def TEST_CASE_1=True;",aes64esm)
+
+RVTEST_SIGBASE( x10,signature_x10_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x18, rs2==x18, rd==x29, rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64esm ; op1:x18; op2:x18; dest:x29; op1val:0x706050403020100;  op2val:0x706050403020100
+TEST_RR_OP(aes64esm, x29, x18, x18, 0x0000000000000000, 0x706050403020100, 0x706050403020100, x10, 0, x4)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x9, rs2==x9, rd==x9, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64esm ; op1:x9; op2:x9; dest:x9; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(aes64esm, x9, x9, x9, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x10, 8, x4)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x21, rs2==x19, rd==x7, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: aes64esm ; op1:x21; op2:x19; dest:x7; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(aes64esm, x7, x21, x19, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x10, 16, x4)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x22, rs2==x7, rd==x22, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: aes64esm ; op1:x22; op2:x7; dest:x22; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(aes64esm, x22, x22, x7, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x10, 24, x4)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x0, rs2==x26, rd==x26, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64esm ; op1:x0; op2:x26; dest:x26; op1val:0x0;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64esm, x26, x0, x26, 0x0000000000000000, 0x0, 0x1826a804284fe16c, x10, 32, x4)
+
+inst_5:
+// rs1==x12, rs2==x11, rd==x24, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: aes64esm ; op1:x12; op2:x11; dest:x24; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(aes64esm, x24, x12, x11, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x10, 40, x4)
+
+inst_6:
+// rs1==x23, rs2==x3, rd==x6, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64esm ; op1:x23; op2:x3; dest:x6; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64esm, x6, x23, x3, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x10, 48, x4)
+
+inst_7:
+// rs1==x3, rs2==x14, rd==x0, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64esm ; op1:x3; op2:x14; dest:x0; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64esm, x0, x3, x14, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x10, 56, x4)
+
+inst_8:
+// rs1==x11, rs2==x20, rd==x1, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: aes64esm ; op1:x11; op2:x20; dest:x1; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(aes64esm, x1, x11, x20, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x10, 64, x4)
+
+inst_9:
+// rs1==x5, rs2==x30, rd==x23, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: aes64esm ; op1:x5; op2:x30; dest:x23; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(aes64esm, x23, x5, x30, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x10, 72, x4)
+
+inst_10:
+// rs1==x19, rs2==x12, rd==x27, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64esm ; op1:x19; op2:x12; dest:x27; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64esm, x27, x19, x12, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x10, 80, x4)
+
+inst_11:
+// rs1==x29, rs2==x21, rd==x19, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64esm ; op1:x29; op2:x21; dest:x19; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64esm, x19, x29, x21, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x10, 88, x4)
+
+inst_12:
+// rs1==x24, rs2==x27, rd==x21, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: aes64esm ; op1:x24; op2:x27; dest:x21; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(aes64esm, x21, x24, x27, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x10, 96, x4)
+
+inst_13:
+// rs1==x8, rs2==x2, rd==x20, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64esm ; op1:x8; op2:x2; dest:x20; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(aes64esm, x20, x8, x2, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x10, 104, x4)
+
+inst_14:
+// rs1==x14, rs2==x1, rd==x15, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: aes64esm ; op1:x14; op2:x1; dest:x15; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(aes64esm, x15, x14, x1, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x10, 112, x4)
+
+inst_15:
+// rs1==x25, rs2==x6, rd==x8, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: aes64esm ; op1:x25; op2:x6; dest:x8; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(aes64esm, x8, x25, x6, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x10, 120, x4)
+
+inst_16:
+// rs1==x6, rs2==x22, rd==x28, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: aes64esm ; op1:x6; op2:x22; dest:x28; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(aes64esm, x28, x6, x22, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x10, 128, x4)
+
+inst_17:
+// rs1==x31, rs2==x17, rd==x14, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: aes64esm ; op1:x31; op2:x17; dest:x14; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(aes64esm, x14, x31, x17, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x10, 136, x4)
+
+inst_18:
+// rs1==x15, rs2==x8, rd==x4, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: aes64esm ; op1:x15; op2:x8; dest:x4; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(aes64esm, x4, x15, x8, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x10, 144, x9)
+RVTEST_SIGBASE( x6,signature_x6_0)
+
+inst_19:
+// rs1==x30, rs2==x13, rd==x12, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: aes64esm ; op1:x30; op2:x13; dest:x12; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(aes64esm, x12, x30, x13, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x6, 0, x9)
+
+inst_20:
+// rs1==x1, rs2==x23, rd==x18, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64esm ; op1:x1; op2:x23; dest:x18; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(aes64esm, x18, x1, x23, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x6, 8, x9)
+
+inst_21:
+// rs1==x10, rs2==x28, rd==x31, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0xf7f6f5f4f3f2f1f0 
+// opcode: aes64esm ; op1:x10; op2:x28; dest:x31; op1val:0xfffefdfcfbfaf9f8;  op2val:0xf7f6f5f4f3f2f1f0
+TEST_RR_OP(aes64esm, x31, x10, x28, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0xf7f6f5f4f3f2f1f0, x6, 16, x9)
+
+inst_22:
+// rs1==x4, rs2==x0, rd==x30, rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfffefdfcfbfaf9f8 
+// opcode: aes64esm ; op1:x4; op2:x0; dest:x30; op1val:0xf7f6f5f4f3f2f1f0;  op2val:0x0
+TEST_RR_OP(aes64esm, x30, x4, x0, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0x0, x6, 24, x9)
+
+inst_23:
+// rs1==x2, rs2==x5, rd==x3, rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xe7e6e5e4e3e2e1e0 
+// opcode: aes64esm ; op1:x2; op2:x5; dest:x3; op1val:0xefeeedecebeae9e8;  op2val:0xe7e6e5e4e3e2e1e0
+TEST_RR_OP(aes64esm, x3, x2, x5, 0x0000000000000000, 0xefeeedecebeae9e8, 0xe7e6e5e4e3e2e1e0, x6, 32, x9)
+
+inst_24:
+// rs1==x16, rs2==x15, rd==x5, rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xefeeedecebeae9e8 
+// opcode: aes64esm ; op1:x16; op2:x15; dest:x5; op1val:0xe7e6e5e4e3e2e1e0;  op2val:0xefeeedecebeae9e8
+TEST_RR_OP(aes64esm, x5, x16, x15, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xefeeedecebeae9e8, x6, 40, x9)
+
+inst_25:
+// rs1==x20, rs2==x31, rd==x25, rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xd7d6d5d4d3d2d1d0 
+// opcode: aes64esm ; op1:x20; op2:x31; dest:x25; op1val:0xdfdedddcdbdad9d8;  op2val:0xd7d6d5d4d3d2d1d0
+TEST_RR_OP(aes64esm, x25, x20, x31, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xd7d6d5d4d3d2d1d0, x6, 48, x9)
+
+inst_26:
+// rs1==x7, rs2==x25, rd==x13, rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdfdedddcdbdad9d8 
+// opcode: aes64esm ; op1:x7; op2:x25; dest:x13; op1val:0xd7d6d5d4d3d2d1d0;  op2val:0xdfdedddcdbdad9d8
+TEST_RR_OP(aes64esm, x13, x7, x25, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdfdedddcdbdad9d8, x6, 56, x9)
+
+inst_27:
+// rs1==x13, rs2==x4, rd==x2, rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xc7c6c5c4c3c2c1c0 
+// opcode: aes64esm ; op1:x13; op2:x4; dest:x2; op1val:0xcfcecdcccbcac9c8;  op2val:0xc7c6c5c4c3c2c1c0
+TEST_RR_OP(aes64esm, x2, x13, x4, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xc7c6c5c4c3c2c1c0, x6, 64, x9)
+
+inst_28:
+// rs1==x28, rs2==x10, rd==x11, rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcfcecdcccbcac9c8 
+// opcode: aes64esm ; op1:x28; op2:x10; dest:x11; op1val:0xc7c6c5c4c3c2c1c0;  op2val:0xcfcecdcccbcac9c8
+TEST_RR_OP(aes64esm, x11, x28, x10, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcfcecdcccbcac9c8, x6, 72, x9)
+
+inst_29:
+// rs1==x17, rs2==x29, rd==x10, rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xb7b6b5b4b3b2b1b0 
+// opcode: aes64esm ; op1:x17; op2:x29; dest:x10; op1val:0xbfbebdbcbbbab9b8;  op2val:0xb7b6b5b4b3b2b1b0
+TEST_RR_OP(aes64esm, x10, x17, x29, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xb7b6b5b4b3b2b1b0, x6, 80, x9)
+
+inst_30:
+// rs1==x27, rs2==x24, rd==x17, rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbfbebdbcbbbab9b8 
+// opcode: aes64esm ; op1:x27; op2:x24; dest:x17; op1val:0xb7b6b5b4b3b2b1b0;  op2val:0xbfbebdbcbbbab9b8
+TEST_RR_OP(aes64esm, x17, x27, x24, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbfbebdbcbbbab9b8, x6, 88, x9)
+
+inst_31:
+// rs1==x26, rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xa7a6a5a4a3a2a1a0 
+// opcode: aes64esm ; op1:x26; op2:x17; dest:x2; op1val:0xafaeadacabaaa9a8;  op2val:0xa7a6a5a4a3a2a1a0
+TEST_RR_OP(aes64esm, x2, x26, x17, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xa7a6a5a4a3a2a1a0, x6, 96, x9)
+
+inst_32:
+// rs2==x16, rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xafaeadacabaaa9a8 
+// opcode: aes64esm ; op1:x23; op2:x16; dest:x11; op1val:0xa7a6a5a4a3a2a1a0;  op2val:0xafaeadacabaaa9a8
+TEST_RR_OP(aes64esm, x11, x23, x16, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xafaeadacabaaa9a8, x6, 104, x9)
+
+inst_33:
+// rd==x16, rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0x9796959493929190 
+// opcode: aes64esm ; op1:x25; op2:x19; dest:x16; op1val:0x9f9e9d9c9b9a9998;  op2val:0x9796959493929190
+TEST_RR_OP(aes64esm, x16, x25, x19, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0x9796959493929190, x6, 112, x9)
+
+inst_34:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9f9e9d9c9b9a9998 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x9796959493929190;  op2val:0x9f9e9d9c9b9a9998
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x9796959493929190, 0x9f9e9d9c9b9a9998, x6, 120, x9)
+
+inst_35:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x8786858483828180 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x8f8e8d8c8b8a8988;  op2val:0x8786858483828180
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x8786858483828180, x6, 128, x9)
+
+inst_36:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8f8e8d8c8b8a8988 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x8786858483828180;  op2val:0x8f8e8d8c8b8a8988
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x8786858483828180, 0x8f8e8d8c8b8a8988, x6, 136, x9)
+
+inst_37:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x7776757473727170 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x7f7e7d7c7b7a7978;  op2val:0x7776757473727170
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x7776757473727170, x6, 144, x9)
+
+inst_38:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7f7e7d7c7b7a7978 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x7776757473727170;  op2val:0x7f7e7d7c7b7a7978
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x7776757473727170, 0x7f7e7d7c7b7a7978, x6, 152, x9)
+
+inst_39:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x6766656463626160 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x6f6e6d6c6b6a6968;  op2val:0x6766656463626160
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x6766656463626160, x6, 160, x9)
+
+inst_40:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6f6e6d6c6b6a6968 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x6766656463626160;  op2val:0x6f6e6d6c6b6a6968
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x6766656463626160, 0x6f6e6d6c6b6a6968, x6, 168, x9)
+
+inst_41:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x5756555453525150 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x5f5e5d5c5b5a5958;  op2val:0x5756555453525150
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x5756555453525150, x6, 176, x9)
+
+inst_42:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5f5e5d5c5b5a5958 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x5756555453525150;  op2val:0x5f5e5d5c5b5a5958
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x5756555453525150, 0x5f5e5d5c5b5a5958, x6, 184, x9)
+
+inst_43:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x4746454443424140 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x4f4e4d4c4b4a4948;  op2val:0x4746454443424140
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x4746454443424140, x6, 192, x9)
+
+inst_44:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4f4e4d4c4b4a4948 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x4746454443424140;  op2val:0x4f4e4d4c4b4a4948
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x4746454443424140, 0x4f4e4d4c4b4a4948, x6, 200, x9)
+
+inst_45:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x3736353433323130 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x3f3e3d3c3b3a3938;  op2val:0x3736353433323130
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x3736353433323130, x6, 208, x9)
+
+inst_46:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3f3e3d3c3b3a3938 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x3736353433323130;  op2val:0x3f3e3d3c3b3a3938
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x3736353433323130, 0x3f3e3d3c3b3a3938, x6, 216, x9)
+
+inst_47:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x2726252423222120 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x2f2e2d2c2b2a2928;  op2val:0x2726252423222120
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x2726252423222120, x6, 224, x9)
+
+inst_48:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2f2e2d2c2b2a2928 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x2726252423222120;  op2val:0x2f2e2d2c2b2a2928
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x2726252423222120, 0x2f2e2d2c2b2a2928, x6, 232, x9)
+
+inst_49:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x1716151413121110 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x1f1e1d1c1b1a1918;  op2val:0x1716151413121110
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x1716151413121110, x6, 240, x9)
+
+inst_50:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1f1e1d1c1b1a1918 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x1716151413121110;  op2val:0x1f1e1d1c1b1a1918
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x1716151413121110, 0x1f1e1d1c1b1a1918, x6, 248, x9)
+
+inst_51:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x0706050403020100 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0xf0e0d0c0b0a0908;  op2val:0x706050403020100
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x706050403020100, x6, 256, x9)
+
+inst_52:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0f0e0d0c0b0a0908 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x706050403020100;  op2val:0xf0e0d0c0b0a0908
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x706050403020100, 0xf0e0d0c0b0a0908, x6, 264, x9)
+
+inst_53:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x6, 272, x9)
+
+inst_54:
+// rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x6, 280, x9)
+
+inst_55:
+// rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x6, 288, x9)
+
+inst_56:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfffefdfcfbfaf9f8 
+// opcode: aes64esm ; op1:x10; op2:x11; dest:x12; op1val:0xf7f6f5f4f3f2f1f0;  op2val:0xfffefdfcfbfaf9f8
+TEST_RR_OP(aes64esm, x12, x10, x11, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfffefdfcfbfaf9f8, x6, 296, x9)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x10_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_0:
+    .fill 38*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S
new file mode 100644
index 000000000..1f01ceffc
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64esm-rwp1.S
@@ -0,0 +1,389 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64esm)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64esm)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// 1st Instruction => rs1 = x1; rs2 = x2 | 2nd Instruction => rs1 = x2; rs2 = x1 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x1; op2:x2; dest1:x3; dest2:x4; dest3:x5; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x1, x1, x2;
+aes64esm x3, x1, x2;
+aes64esm x4, x2, x1;
+xor x5, x4, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x4,8);
+RVTEST_SIGUPD(x31,x5,16);
+
+inst_1:
+// 1st Instruction => rs1 = x2; rs2 = x3 | 2nd Instruction => rs1 = x3; rs2 = x2 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x2; op2:x3; dest1:x4; dest2:x5; dest3:x6; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x2, x2, x3;
+aes64esm x4, x2, x3;
+aes64esm x5, x3, x2;
+xor x6, x5, x3;
+RVTEST_SIGUPD(x31,x4,24);
+RVTEST_SIGUPD(x31,x5,32);
+RVTEST_SIGUPD(x31,x6,40);
+
+inst_2:
+// 1st Instruction => rs1 = x3; rs2 = x4 | 2nd Instruction => rs1 = x4; rs2 = x3 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x3; op2:x4; dest1:x5; dest2:x6; dest3:x7; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x3, x3, x4;
+aes64esm x5, x3, x4;
+aes64esm x6, x4, x3;
+xor x7, x6, x4;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+RVTEST_SIGUPD(x31,x7,64);
+
+inst_3:
+// 1st Instruction => rs1 = x4; rs2 = x5 | 2nd Instruction => rs1 = x5; rs2 = x4 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x4; op2:x5; dest1:x6; dest2:x7; dest3:x8; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x4, x4, x5;
+aes64esm x6, x4, x5;
+aes64esm x7, x5, x4;
+xor x8, x7, x5;
+RVTEST_SIGUPD(x31,x6,72);
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_4:
+// 1st Instruction => rs1 = x5; rs2 = x6 | 2nd Instruction => rs1 = x6; rs2 = x5 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x5; op2:x6; dest1:x7; dest2:x8; dest3:x9; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x5, x5, x6;
+aes64esm x7, x5, x6;
+aes64esm x8, x6, x5;
+xor x9, x8, x6;
+RVTEST_SIGUPD(x31,x7,96);
+RVTEST_SIGUPD(x31,x8,104);
+RVTEST_SIGUPD(x31,x9,112);
+
+inst_5:
+// 1st Instruction => rs1 = x6; rs2 = x7 | 2nd Instruction => rs1 = x7; rs2 = x6 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x6; op2:x7; dest1:x8; dest2:x9; dest3:x10; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x6, x6, x7;
+aes64esm x8, x6, x7;
+aes64esm x9, x7, x6;
+xor x10, x9, x7;
+RVTEST_SIGUPD(x31,x8,120);
+RVTEST_SIGUPD(x31,x9,128);
+RVTEST_SIGUPD(x31,x10,136);
+
+inst_6:
+// 1st Instruction => rs1 = x7; rs2 = x8 | 2nd Instruction => rs1 = x8; rs2 = x7 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x7; op2:x8; dest1:x9; dest2:x10; dest3:x11; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x7, x7, x8;
+aes64esm x9, x7, x8;
+aes64esm x10, x8, x7;
+xor x11, x10, x8;
+RVTEST_SIGUPD(x31,x9,144);
+RVTEST_SIGUPD(x31,x10,152);
+RVTEST_SIGUPD(x31,x11,160);
+
+inst_7:
+// 1st Instruction => rs1 = x8; rs2 = x9 | 2nd Instruction => rs1 = x9; rs2 = x8 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x8; op2:x9; dest1:x10; dest2:x11; dest3:x12; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x8, x8, x9;
+aes64esm x10, x8, x9;
+aes64esm x11, x9, x8;
+xor x12, x11, x9;
+RVTEST_SIGUPD(x31,x10,168);
+RVTEST_SIGUPD(x31,x11,176);
+RVTEST_SIGUPD(x31,x12,184);
+
+inst_8:
+// 1st Instruction => rs1 = x9; rs2 = x10 | 2nd Instruction => rs1 = x10; rs2 = x9 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x9; op2:x10; dest1:x11; dest2:x12; dest3:x13; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x9, x9, x10;
+aes64esm x11, x9, x10;
+aes64esm x12, x10, x9;
+xor x13, x12, x10;
+RVTEST_SIGUPD(x31,x11,192);
+RVTEST_SIGUPD(x31,x12,200);
+RVTEST_SIGUPD(x31,x13,208);
+
+inst_9:
+// 1st Instruction => rs1 = x10; rs2 = x11 | 2nd Instruction => rs1 = x11; rs2 = x10 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x10; op2:x11; dest1:x12; dest2:x13; dest3:x14; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x10, x10, x11;
+aes64esm x12, x10, x11;
+aes64esm x13, x11, x10;
+xor x14, x13, x11;
+RVTEST_SIGUPD(x31,x12,216);
+RVTEST_SIGUPD(x31,x13,224);
+RVTEST_SIGUPD(x31,x14,232);
+
+inst_10:
+// 1st Instruction => rs1 = x11; rs2 = x12 | 2nd Instruction => rs1 = x12; rs2 = x11 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x11; op2:x12; dest1:x13; dest2:x14; dest3:x15; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x11, x11, x12;
+aes64esm x13, x11, x12;
+aes64esm x14, x12, x11;
+xor x15, x14, x12;
+RVTEST_SIGUPD(x31,x13,240);
+RVTEST_SIGUPD(x31,x14,248);
+RVTEST_SIGUPD(x31,x15,256);
+
+inst_11:
+// 1st Instruction => rs1 = x12; rs2 = x13 | 2nd Instruction => rs1 = x13; rs2 = x12 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x12; op2:x13; dest1:x14; dest2:x15; dest3:x16; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x12, x12, x13;
+aes64esm x14, x12, x13;
+aes64esm x15, x13, x12;
+xor x16, x15, x13;
+RVTEST_SIGUPD(x31,x14,264);
+RVTEST_SIGUPD(x31,x15,272);
+RVTEST_SIGUPD(x31,x16,280);
+
+inst_12:
+// 1st Instruction => rs1 = x13; rs2 = x14 | 2nd Instruction => rs1 = x14; rs2 = x13 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x13; op2:x14; dest1:x15; dest2:x16; dest3:x17; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x13, x13, x14;
+aes64esm x15, x13, x14;
+aes64esm x16, x14, x13;
+xor x17, x16, x14;
+RVTEST_SIGUPD(x31,x15,288);
+RVTEST_SIGUPD(x31,x16,296);
+RVTEST_SIGUPD(x31,x17,304);
+
+inst_13:
+// 1st Instruction => rs1 = x14; rs2 = x15 | 2nd Instruction => rs1 = x15; rs2 = x14 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x14; op2:x15; dest1:x16; dest2:x17; dest3:x18; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x14, x14, x15;
+aes64esm x16, x14, x15;
+aes64esm x17, x15, x14;
+xor x18, x17, x15;
+RVTEST_SIGUPD(x31,x16,312);
+RVTEST_SIGUPD(x31,x17,320);
+RVTEST_SIGUPD(x31,x18,328);
+
+inst_14:
+// 1st Instruction => rs1 = x15; rs2 = x16 | 2nd Instruction => rs1 = x16; rs2 = x15 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x15; op2:x16; dest1:x17; dest2:x18; dest3:x19; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x15, x15, x16;
+aes64esm x17, x15, x16;
+aes64esm x18, x16, x15;
+xor x19, x18, x16;
+RVTEST_SIGUPD(x31,x17,336);
+RVTEST_SIGUPD(x31,x18,344);
+RVTEST_SIGUPD(x31,x19,352);
+
+inst_15:
+// 1st Instruction => rs1 = x16; rs2 = x17 | 2nd Instruction => rs1 = x17; rs2 = x16 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x16; op2:x17; dest1:x18; dest2:x19; dest3:x20; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x16, x16, x17;
+aes64esm x18, x16, x17;
+aes64esm x19, x17, x16;
+xor x20, x19, x17;
+RVTEST_SIGUPD(x31,x18,360);
+RVTEST_SIGUPD(x31,x19,368);
+RVTEST_SIGUPD(x31,x20,376);
+
+inst_16:
+// 1st Instruction => rs1 = x17; rs2 = x18 | 2nd Instruction => rs1 = x18; rs2 = x17 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x17; op2:x18; dest1:x19; dest2:x20; dest3:x21; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x17, x17, x18;
+aes64esm x19, x17, x18;
+aes64esm x20, x18, x17;
+xor x21, x20, x18;
+RVTEST_SIGUPD(x31,x19,384);
+RVTEST_SIGUPD(x31,x20,392);
+RVTEST_SIGUPD(x31,x21,400);
+
+inst_17:
+// 1st Instruction => rs1 = x18; rs2 = x19 | 2nd Instruction => rs1 = x19; rs2 = x18 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x18; op2:x19; dest1:x20; dest2:x21; dest3:x22; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x18, x18, x19;
+aes64esm x20, x18, x19;
+aes64esm x21, x19, x18;
+xor x22, x21, x19;
+RVTEST_SIGUPD(x31,x20,408);
+RVTEST_SIGUPD(x31,x21,416);
+RVTEST_SIGUPD(x31,x22,424);
+
+inst_18:
+// 1st Instruction => rs1 = x19; rs2 = x20 | 2nd Instruction => rs1 = x20; rs2 = x19 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x19; op2:x20; dest1:x21; dest2:x22; dest3:x23; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x19, x19, x20;
+aes64esm x21, x19, x20;
+aes64esm x22, x20, x19;
+xor x23, x22, x20;
+RVTEST_SIGUPD(x31,x21,432);
+RVTEST_SIGUPD(x31,x22,440);
+RVTEST_SIGUPD(x31,x23,448);
+
+inst_19:
+// 1st Instruction => rs1 = x20; rs2 = x21 | 2nd Instruction => rs1 = x21; rs2 = x20 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x20; op2:x21; dest1:x22; dest2:x23; dest3:x24; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x20, x20, x21;
+aes64esm x22, x20, x21;
+aes64esm x23, x21, x20;
+xor x24, x23, x21;
+RVTEST_SIGUPD(x31,x22,456);
+RVTEST_SIGUPD(x31,x23,464);
+RVTEST_SIGUPD(x31,x24,472);
+
+inst_20:
+// 1st Instruction => rs1 = x21; rs2 = x22 | 2nd Instruction => rs1 = x22; rs2 = x21 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x21; op2:x22; dest1:x23; dest2:x24; dest3:x25; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x21, x21, x22;
+aes64esm x23, x21, x22;
+aes64esm x24, x22, x21;
+xor x25, x24, x22;
+RVTEST_SIGUPD(x31,x23,480);
+RVTEST_SIGUPD(x31,x24,488);
+RVTEST_SIGUPD(x31,x25,496);
+
+inst_21:
+// 1st Instruction => rs1 = x22; rs2 = x23 | 2nd Instruction => rs1 = x23; rs2 = x22 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x22; op2:x23; dest1:x24; dest2:x25; dest3:x26; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x22, x22, x23;
+aes64esm x24, x22, x23;
+aes64esm x25, x23, x22;
+xor x26, x25, x23;
+RVTEST_SIGUPD(x31,x24,504);
+RVTEST_SIGUPD(x31,x25,512);
+RVTEST_SIGUPD(x31,x26,520);
+
+inst_22:
+// 1st Instruction => rs1 = x23; rs2 = x24 | 2nd Instruction => rs1 = x24; rs2 = x23 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x23; op2:x24; dest1:x25; dest2:x26; dest3:x27; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x23, x23, x24;
+aes64esm x25, x23, x24;
+aes64esm x26, x24, x23;
+xor x27, x26, x24;
+RVTEST_SIGUPD(x31,x25,528);
+RVTEST_SIGUPD(x31,x26,536);
+RVTEST_SIGUPD(x31,x27,544);
+
+inst_23:
+// 1st Instruction => rs1 = x24; rs2 = x25 | 2nd Instruction => rs1 = x25; rs2 = x24 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x24; op2:x25; dest1:x26; dest2:x27; dest3:x28; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x24, x24, x25;
+aes64esm x26, x24, x25;
+aes64esm x27, x25, x24;
+xor x28, x27, x25;
+RVTEST_SIGUPD(x31,x26,552);
+RVTEST_SIGUPD(x31,x27,560);
+RVTEST_SIGUPD(x31,x28,568);
+
+inst_24:
+// 1st Instruction => rs1 = x25; rs2 = x26 | 2nd Instruction => rs1 = x26; rs2 = x25 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x25; op2:x26; dest1:x27; dest2:x28; dest3:x29; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x25, x25, x26;
+aes64esm x27, x25, x26;
+aes64esm x28, x26, x25;
+xor x29, x28, x26;
+RVTEST_SIGUPD(x31,x27,576);
+RVTEST_SIGUPD(x31,x28,584);
+RVTEST_SIGUPD(x31,x29,592);
+
+inst_25:
+// 1st Instruction => rs1 = x26; rs2 = x27 | 2nd Instruction => rs1 = x27; rs2 = x26 | Result of xor goes into aes64esm & vice versa
+// opcode: aes64esm; op1:x26; op2:x27; dest1:x28; dest2:x29; dest3:x30; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x26, x26, x27;
+aes64esm x28, x26, x27;
+aes64esm x29, x27, x26;
+xor x30, x29, x27;
+RVTEST_SIGUPD(x31,x28,600);
+RVTEST_SIGUPD(x31,x29,608);
+RVTEST_SIGUPD(x31,x30,616);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 78*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S
new file mode 100644
index 000000000..f926ced17
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64im instruction of the RISC-V  extension for the aes64im covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnd.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 != rd, rs1==x26, rd==x0, rs1_val == 0x75a3adb3254a9493 
+// opcode: aes64im ; op1:x26; dest:x0; op1val:0x75a3adb3254a9493;
+li x26, 0x75a3adb3254a9493
+aes64im x0, x26
+sw x0, 0(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x0, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x28, rd==x28, rs1_val == 9223372036854775807, 
+// opcode: aes64im ; op1:x28; dest:x28; op1val:0x7fffffffffffffff;
+li x28, 0x7fffffffffffffff
+aes64im x28, x28
+sw x28, 8(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x28, 0x0000000000000000)
+
+inst_2:
+// rs1==x14, rd==x1, rs1_val == 13835058055282163711, 
+// opcode: aes64im ; op1:x14; dest:x1; op1val:0xbfffffffffffffff;
+li x14, 0xbfffffffffffffff
+aes64im x1, x14
+sw x1, 16(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x1, 0x0000000000000000)
+
+inst_3:
+// rs1==x30, rd==x23, rs1_val == 16140901064495857663, 
+// opcode: aes64im ; op1:x30; dest:x23; op1val:0xdfffffffffffffff;
+li x30, 0xdfffffffffffffff
+aes64im x23, x30
+sw x23, 24(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x23, 0x0000000000000000)
+
+inst_4:
+// rs1==x4, rd==x27, rs1_val == 17293822569102704639, 
+// opcode: aes64im ; op1:x4; dest:x27; op1val:0xefffffffffffffff;
+li x4, 0xefffffffffffffff
+aes64im x27, x4
+sw x27, 32(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x27, 0x0000000000000000)
+
+inst_5:
+// rs1==x29, rd==x15, rs1_val == 17870283321406128127, 
+// opcode: aes64im ; op1:x29; dest:x15; op1val:0xf7ffffffffffffff;
+li x29, 0xf7ffffffffffffff
+aes64im x15, x29
+sw x15, 40(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x15, 0x0000000000000000)
+
+inst_6:
+// rs1==x9, rd==x22, rs1_val == 18158513697557839871, 
+// opcode: aes64im ; op1:x9; dest:x22; op1val:0xfbffffffffffffff;
+li x9, 0xfbffffffffffffff
+aes64im x22, x9
+sw x22, 48(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x22, 0x0000000000000000)
+
+inst_7:
+// rs1==x2, rd==x24, rs1_val == 18302628885633695743, 
+// opcode: aes64im ; op1:x2; dest:x24; op1val:0xfdffffffffffffff;
+li x2, 0xfdffffffffffffff
+aes64im x24, x2
+sw x24, 56(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x24, 0x0000000000000000)
+
+inst_8:
+// rs1==x8, rd==x6, rs1_val == 18374686479671623679, 
+// opcode: aes64im ; op1:x8; dest:x6; op1val:0xfeffffffffffffff;
+li x8, 0xfeffffffffffffff
+aes64im x6, x8
+sw x6, 64(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x6, 0x0000000000000000)
+
+inst_9:
+// rs1==x1, rd==x17, rs1_val == 18410715276690587647, 
+// opcode: aes64im ; op1:x1; dest:x17; op1val:0xff7fffffffffffff;
+li x1, 0xff7fffffffffffff
+aes64im x17, x1
+sw x17, 72(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x17, 0x0000000000000000)
+
+inst_10:
+// rs1==x11, rd==x30, rs1_val == 18428729675200069631, 
+// opcode: aes64im ; op1:x11; dest:x30; op1val:0xffbfffffffffffff;
+li x11, 0xffbfffffffffffff
+aes64im x30, x11
+sw x30, 80(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x30, 0x0000000000000000)
+
+inst_11:
+// rs1==x10, rd==x16, rs1_val == 18437736874454810623, 
+// opcode: aes64im ; op1:x10; dest:x16; op1val:0xffdfffffffffffff;
+li x10, 0xffdfffffffffffff
+aes64im x16, x10
+sw x16, 88(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x16, 0x0000000000000000)
+
+inst_12:
+// rs1==x15, rd==x8, rs1_val == 18442240474082181119, 
+// opcode: aes64im ; op1:x15; dest:x8; op1val:0xffefffffffffffff;
+li x15, 0xffefffffffffffff
+aes64im x8, x15
+sw x8, 96(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x8, 0x0000000000000000)
+
+inst_13:
+// rs1==x0, rd==x14, rs1_val == 18444492273895866367, 
+// opcode: aes64im ; op1:x0; dest:x14; op1val:0x0;
+li x0, 0x0
+aes64im x14, x0
+sw x14, 104(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x14, 0x0000000000000000)
+
+inst_14:
+// rs1==x19, rd==x18, rs1_val == 18445618173802708991, 
+// opcode: aes64im ; op1:x19; dest:x18; op1val:0xfffbffffffffffff;
+li x19, 0xfffbffffffffffff
+aes64im x18, x19
+sw x18, 112(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x18, 0x0000000000000000)
+
+inst_15:
+// rs1==x16, rd==x13, rs1_val == 18446181123756130303, 
+// opcode: aes64im ; op1:x16; dest:x13; op1val:0xfffdffffffffffff;
+li x16, 0xfffdffffffffffff
+aes64im x13, x16
+sw x13, 120(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x13, 0x0000000000000000)
+
+inst_16:
+// rs1==x17, rd==x20, rs1_val == 18446462598732840959, 
+// opcode: aes64im ; op1:x17; dest:x20; op1val:0xfffeffffffffffff;
+li x17, 0xfffeffffffffffff
+aes64im x20, x17
+sw x20, 128(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x20, 0x0000000000000000)
+
+inst_17:
+// rs1==x23, rd==x29, rs1_val == 18446603336221196287, 
+// opcode: aes64im ; op1:x23; dest:x29; op1val:0xffff7fffffffffff;
+li x23, 0xffff7fffffffffff
+aes64im x29, x23
+sw x29, 136(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x29, 0x0000000000000000)
+
+inst_18:
+// rs1==x12, rd==x2, rs1_val == 18446673704965373951, 
+// opcode: aes64im ; op1:x12; dest:x2; op1val:0xffffbfffffffffff;
+li x12, 0xffffbfffffffffff
+aes64im x2, x12
+sw x2, 144(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x2, 0x0000000000000000)
+
+inst_19:
+// rs1==x25, rd==x5, rs1_val == 18446708889337462783, 
+// opcode: aes64im ; op1:x25; dest:x5; op1val:0xffffdfffffffffff;
+li x25, 0xffffdfffffffffff
+aes64im x5, x25
+sw x5, 152(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x7, x5, 0x0000000000000000)
+
+inst_20:
+// rs1==x22, rd==x12, rs1_val == 18446726481523507199, 
+// opcode: aes64im ; op1:x22; dest:x12; op1val:0xffffefffffffffff;
+li x22, 0xffffefffffffffff
+aes64im x12, x22
+sw x12, 160(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x12, 0x0000000000000000)
+
+inst_21:
+// rs1==x5, rd==x4, rs1_val == 18446735277616529407, 
+// opcode: aes64im ; op1:x5; dest:x4; op1val:0xfffff7ffffffffff;
+li x5, 0xfffff7ffffffffff
+aes64im x4, x5
+sw x4, 168(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x4, 0x0000000000000000)
+
+inst_22:
+// rs1==x27, rd==x21, rs1_val == 18446739675663040511, 
+// opcode: aes64im ; op1:x27; dest:x21; op1val:0xfffffbffffffffff;
+li x27, 0xfffffbffffffffff
+aes64im x21, x27
+sw x21, 176(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_23:
+// rs1==x24, rd==x19, rs1_val == 18446741874686296063, 
+// opcode: aes64im ; op1:x24; dest:x19; op1val:0xfffffdffffffffff;
+li x24, 0xfffffdffffffffff
+aes64im x19, x24
+sw x19, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x19, 0x0000000000000000)
+
+inst_24:
+// rs1==x7, rd==x3, rs1_val == 18446742974197923839, 
+// opcode: aes64im ; op1:x7; dest:x3; op1val:0xfffffeffffffffff;
+li x7, 0xfffffeffffffffff
+aes64im x3, x7
+sw x3, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x3, 0x0000000000000000)
+
+inst_25:
+// rs1==x6, rd==x25, rs1_val == 18446743523953737727, 
+// opcode: aes64im ; op1:x6; dest:x25; op1val:0xffffff7fffffffff;
+li x6, 0xffffff7fffffffff
+aes64im x25, x6
+sw x25, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x25, 0x0000000000000000)
+
+inst_26:
+// rs1==x18, rd==x26, rs1_val == 18446743798831644671, 
+// opcode: aes64im ; op1:x18; dest:x26; op1val:0xffffffbfffffffff;
+li x18, 0xffffffbfffffffff
+aes64im x26, x18
+sw x26, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x26, 0x0000000000000000)
+
+inst_27:
+// rs1==x20, rd==x11, rs1_val == 18446743936270598143, 
+// opcode: aes64im ; op1:x20; dest:x11; op1val:0xffffffdfffffffff;
+li x20, 0xffffffdfffffffff
+aes64im x11, x20
+sw x11, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_28:
+// rs1==x3, rd==x10, rs1_val == 18446744004990074879, 
+// opcode: aes64im ; op1:x3; dest:x10; op1val:0xffffffefffffffff;
+li x3, 0xffffffefffffffff
+aes64im x10, x3
+sw x10, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x10, 0x0000000000000000)
+
+inst_29:
+// rs1==x21, rd==x7, rs1_val == 18446744039349813247, 
+// opcode: aes64im ; op1:x21; dest:x7; op1val:0xfffffff7ffffffff;
+li x21, 0xfffffff7ffffffff
+aes64im x7, x21
+sw x7, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x7, 0x0000000000000000)
+
+inst_30:
+// rs1==x31, rd==x9, rs1_val == 18446744056529682431, 
+// opcode: aes64im ; op1:x31; dest:x9; op1val:0xfffffffbffffffff;
+li x31, 0xfffffffbffffffff
+aes64im x9, x31
+sw x9, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x9, 0x0000000000000000)
+
+inst_31:
+// rs1==x13, rd==x31, rs1_val == 18446744065119617023, 
+// opcode: aes64im ; op1:x13; dest:x31; op1val:0xfffffffdffffffff;
+li x13, 0xfffffffdffffffff
+aes64im x31, x13
+sw x31, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+aes64im x11, x10
+sw x11, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+aes64im x11, x10
+sw x11, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+aes64im x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+aes64im x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+aes64im x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+aes64im x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+aes64im x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+aes64im x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+aes64im x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+aes64im x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+aes64im x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+aes64im x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+aes64im x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+aes64im x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+aes64im x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+aes64im x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+aes64im x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+aes64im x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+aes64im x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+aes64im x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+aes64im x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+aes64im x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+aes64im x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+aes64im x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+aes64im x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+aes64im x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+aes64im x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+aes64im x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+aes64im x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+aes64im x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+aes64im x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+aes64im x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+aes64im x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+aes64im x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+aes64im x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+aes64im x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+aes64im x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+aes64im x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+aes64im x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+aes64im x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+aes64im x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+aes64im x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+aes64im x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+aes64im x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+aes64im x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+aes64im x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+aes64im x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+aes64im x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+aes64im x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+aes64im x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+aes64im x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+aes64im x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+aes64im x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+aes64im x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+aes64im x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+aes64im x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+aes64im x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+aes64im x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+aes64im x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+aes64im x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+aes64im x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+aes64im x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+aes64im x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+aes64im x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+aes64im x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+aes64im x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+aes64im x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+aes64im x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+aes64im x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+aes64im x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+aes64im x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+aes64im x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+aes64im x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+aes64im x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+aes64im x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+aes64im x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+aes64im x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+aes64im x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+aes64im x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+aes64im x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+aes64im x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+aes64im x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+aes64im x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+aes64im x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+aes64im x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+aes64im x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+aes64im x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+aes64im x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+aes64im x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+aes64im x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+aes64im x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+aes64im x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+aes64im x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+aes64im x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+aes64im x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+aes64im x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+aes64im x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+aes64im x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+aes64im x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+aes64im x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+aes64im x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+aes64im x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+aes64im x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+aes64im x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+aes64im x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+aes64im x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+aes64im x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+aes64im x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+aes64im x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+aes64im x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+aes64im x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+aes64im x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+aes64im x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+aes64im x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+aes64im x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+aes64im x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 0x75a3adb3254a9493 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0x75a3adb3254a9493;
+li x10, 0x75a3adb3254a9493
+aes64im x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18444492273895866367, 
+// opcode: aes64im ; op1:x10; dest:x11; op1val:0xfff7ffffffffffff;
+li x10, 0xfff7ffffffffffff
+aes64im x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 23*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 127*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S
new file mode 100644
index 000000000..d827a5915
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+aes64im x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+aes64im x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+aes64im x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+aes64im x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+aes64im x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+aes64im x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+aes64im x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+aes64im x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+aes64im x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+aes64im x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+aes64im x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+aes64im x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+aes64im x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+aes64im x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+aes64im x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+aes64im x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+aes64im x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+aes64im x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+aes64im x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+aes64im x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+aes64im x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+aes64im x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+aes64im x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+aes64im x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+aes64im x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+aes64im x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+aes64im x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+aes64im x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+aes64im x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+aes64im x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+aes64im x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+aes64im x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+aes64im x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+aes64im x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+aes64im x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+aes64im x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+aes64im x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+aes64im x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+aes64im x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+aes64im x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+aes64im x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+aes64im x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+aes64im x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+aes64im x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+aes64im x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+aes64im x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+aes64im x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+aes64im x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+aes64im x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+aes64im x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+aes64im x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+aes64im x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+aes64im x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+aes64im x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+aes64im x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+aes64im x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+aes64im x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+aes64im x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+aes64im x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+aes64im x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+aes64im x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+aes64im x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+aes64im x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+aes64im x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+aes64im x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+aes64im x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+aes64im x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+aes64im x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+aes64im x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+aes64im x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+aes64im x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+aes64im x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+aes64im x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+aes64im x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+aes64im x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+aes64im x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+aes64im x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+aes64im x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into aes64im & the result back into xor
+// opcode: aes64im; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+aes64im x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into aes64im & the result back into not
+// opcode: aes64im; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+aes64im x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into aes64im & the result back into add
+// opcode: aes64im; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+aes64im x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S
new file mode 100644
index 000000000..281316aa8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64im-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64im)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+aes64im x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+aes64im x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+aes64im x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+aes64im x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+aes64im x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+aes64im x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+aes64im x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+aes64im x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+aes64im x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+aes64im x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+aes64im x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+aes64im x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+aes64im x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+aes64im x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+aes64im x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+aes64im x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+aes64im x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+aes64im x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+aes64im x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+aes64im x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+aes64im x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+aes64im x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+aes64im x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+aes64im x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+aes64im x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+aes64im x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+aes64im x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: aes64im; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+aes64im x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S
new file mode 100644
index 000000000..193161514
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks1i-01.S
@@ -0,0 +1,509 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Thu Aug 12 11:00:04 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64ks1i instruction of the RISC-V K extension for the aes64ks1i covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64ks1i)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64ks1i)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKne.*);def TEST_CASE_1=True;",aes64ks1i)
+
+RVTEST_SIGBASE( x14,signature_x14_1)
+
+inst_0:
+// rs1 != rd, rs1==x7, rd==x8, rs1_val == 0x0706050403020100 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x7; dest:x8; op1val:0x706050403020100;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x8, x7, 0x0000000000000000, 0x706050403020100, 0xa, x14, 0, x15)
+
+inst_1:
+// rs1 == rd, rs1==x19, rd==x19, rs1_val == 0x71fad878b369e102 and imm_val == 0x0 
+// opcode: aes64ks1i ; op1:x19; dest:x19; op1val:0x71fad878b369e102;  immval:0x0
+TEST_IMM_OP( aes64ks1i, x19, x19, 0x0000000000000000, 0x71fad878b369e102, 0x0, x14, 8, x15)
+
+inst_2:
+// rs1==x12, rd==x10, rs1_val == 0xa4b7f979a8e45869 and imm_val == 0x0 
+// opcode: aes64ks1i ; op1:x12; dest:x10; op1val:0xa4b7f979a8e45869;  immval:0x0
+TEST_IMM_OP( aes64ks1i, x10, x12, 0x0000000000000000, 0xa4b7f979a8e45869, 0x0, x14, 16, x15)
+
+inst_3:
+// rs1==x8, rd==x6, rs1_val == 0x0b3fd605358a9235 and imm_val == 0x1 
+// opcode: aes64ks1i ; op1:x8; dest:x6; op1val:0xb3fd605358a9235;  immval:0x1
+TEST_IMM_OP( aes64ks1i, x6, x8, 0x0000000000000000, 0xb3fd605358a9235, 0x1, x14, 24, x15)
+
+inst_4:
+// rs1==x30, rd==x28, rs1_val == 0xb0873a0f0334fcca and imm_val == 0x7 
+// opcode: aes64ks1i ; op1:x30; dest:x28; op1val:0xb0873a0f0334fcca;  immval:0x7
+TEST_IMM_OP( aes64ks1i, x28, x30, 0x0000000000000000, 0xb0873a0f0334fcca, 0x7, x14, 32, x15)
+
+inst_5:
+// rs1==x16, rd==x13, rs1_val == 0x5b730cad91766f62 and imm_val == 0x7 
+// opcode: aes64ks1i ; op1:x16; dest:x13; op1val:0x5b730cad91766f62;  immval:0x7
+TEST_IMM_OP( aes64ks1i, x13, x16, 0x0000000000000000, 0x5b730cad91766f62, 0x7, x14, 40, x15)
+
+inst_6:
+// rs1==x9, rd==x7, rs1_val == 0xb7c1fc5f1efa1095 and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x9; dest:x7; op1val:0xb7c1fc5f1efa1095;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x7, x9, 0x0000000000000000, 0xb7c1fc5f1efa1095, 0x3, x14, 48, x15)
+
+inst_7:
+// rs1==x17, rd==x5, rs1_val == 0x25ae27ee4113ee60 and imm_val == 0x5 
+// opcode: aes64ks1i ; op1:x17; dest:x5; op1val:0x25ae27ee4113ee60;  immval:0x5
+TEST_IMM_OP( aes64ks1i, x5, x17, 0x0000000000000000, 0x25ae27ee4113ee60, 0x5, x14, 56, x15)
+
+inst_8:
+// rs1==x4, rd==x21, rs1_val == 0xe3f4fca319f046a5 and imm_val == 0x6 
+// opcode: aes64ks1i ; op1:x4; dest:x21; op1val:0xe3f4fca319f046a5;  immval:0x6
+TEST_IMM_OP( aes64ks1i, x21, x4, 0x0000000000000000, 0xe3f4fca319f046a5, 0x6, x14, 64, x15)
+
+inst_9:
+// rs1==x2, rd==x20, rs1_val == 0xff9a1b805ced7e2e and imm_val == 0x6 
+// opcode: aes64ks1i ; op1:x2; dest:x20; op1val:0xff9a1b805ced7e2e;  immval:0x6
+TEST_IMM_OP( aes64ks1i, x20, x2, 0x0000000000000000, 0xff9a1b805ced7e2e, 0x6, x14, 72, x15)
+
+inst_10:
+// rs1==x0, rd==x1, rs1_val == 0x9722c9a6b0942992 and imm_val == 0x5 
+// opcode: aes64ks1i ; op1:x0; dest:x1; op1val:0x0;  immval:0x5
+TEST_IMM_OP( aes64ks1i, x1, x0, 0x0000000000000000, 0x0, 0x5, x14, 80, x15)
+
+inst_11:
+// rs1==x1, rd==x2, rs1_val == 0x9bedfe390d6ddd9d and imm_val == 0x4 
+// opcode: aes64ks1i ; op1:x1; dest:x2; op1val:0x9bedfe390d6ddd9d;  immval:0x4
+TEST_IMM_OP( aes64ks1i, x2, x1, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0x4, x14, 88, x15)
+
+inst_12:
+// rs1==x13, rd==x27, rs1_val == 0xd75739f82ac177c6 and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x13; dest:x27; op1val:0xd75739f82ac177c6;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x27, x13, 0x0000000000000000, 0xd75739f82ac177c6, 0x3, x14, 96, x15)
+
+inst_13:
+// rs1==x23, rd==x22, rs1_val == 0x90efb625d9fbcdb5 and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x23; dest:x22; op1val:0x90efb625d9fbcdb5;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x22, x23, 0x0000000000000000, 0x90efb625d9fbcdb5, 0x3, x14, 104, x15)
+
+inst_14:
+// rs1==x21, rd==x18, rs1_val == 0x60067d39d169a3f8 and imm_val == 0x1 
+// opcode: aes64ks1i ; op1:x21; dest:x18; op1val:0x60067d39d169a3f8;  immval:0x1
+TEST_IMM_OP( aes64ks1i, x18, x21, 0x0000000000000000, 0x60067d39d169a3f8, 0x1, x14, 112, x15)
+
+inst_15:
+// rs1==x18, rd==x24, rs1_val == 0xd5b9fe5cf69bdcf3 and imm_val == 0x6 
+// opcode: aes64ks1i ; op1:x18; dest:x24; op1val:0xd5b9fe5cf69bdcf3;  immval:0x6
+TEST_IMM_OP( aes64ks1i, x24, x18, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0x6, x14, 120, x15)
+
+inst_16:
+// rs1==x3, rd==x29, rs1_val == 0x58d548aae4921bf7 and imm_val == 0x6 
+// opcode: aes64ks1i ; op1:x3; dest:x29; op1val:0x58d548aae4921bf7;  immval:0x6
+TEST_IMM_OP( aes64ks1i, x29, x3, 0x0000000000000000, 0x58d548aae4921bf7, 0x6, x14, 128, x15)
+
+inst_17:
+// rs1==x26, rd==x17, rs1_val == 0x2daf9ac7f5faf207 and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x26; dest:x17; op1val:0x2daf9ac7f5faf207;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x17, x26, 0x0000000000000000, 0x2daf9ac7f5faf207, 0x3, x14, 136, x15)
+
+inst_18:
+// rs1==x6, rd==x11, rs1_val == 0x3acdf61655d98c6e and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x6; dest:x11; op1val:0x3acdf61655d98c6e;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x11, x6, 0x0000000000000000, 0x3acdf61655d98c6e, 0x3, x14, 144, x15)
+
+inst_19:
+// rs1==x24, rd==x16, rs1_val == 0x436f40f274b8de87 and imm_val == 0x3 
+// opcode: aes64ks1i ; op1:x24; dest:x16; op1val:0x436f40f274b8de87;  immval:0x3
+TEST_IMM_OP( aes64ks1i, x16, x24, 0x0000000000000000, 0x436f40f274b8de87, 0x3, x14, 152, x2)
+
+inst_20:
+// rs1==x10, rd==x31, rs1_val == 0x75a3adb3254a9493 and imm_val == 0x2 
+// opcode: aes64ks1i ; op1:x10; dest:x31; op1val:0x75a3adb3254a9493;  immval:0x2
+TEST_IMM_OP( aes64ks1i, x31, x10, 0x0000000000000000, 0x75a3adb3254a9493, 0x2, x14, 160, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_21:
+// rs1==x25, rd==x14, rs1_val == 0x03020100fffefdfc and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x25; dest:x14; op1val:0x3020100fffefdfc;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x14, x25, 0x0000000000000000, 0x3020100fffefdfc, 0xa, x1, 0, x2)
+
+inst_22:
+// rs1==x11, rd==x4, rs1_val == 0xfffefdfcfbfaf9f8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x11; dest:x4; op1val:0xfffefdfcfbfaf9f8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x4, x11, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0xa, x1, 8, x2)
+
+inst_23:
+// rs1==x27, rd==x23, rs1_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x27; dest:x23; op1val:0xfbfaf9f8f7f6f5f4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x23, x27, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xa, x1, 16, x2)
+
+inst_24:
+// rs1==x20, rd==x30, rs1_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x20; dest:x30; op1val:0xf7f6f5f4f3f2f1f0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x30, x20, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xa, x1, 24, x2)
+
+inst_25:
+// rs1==x29, rd==x9, rs1_val == 0xf3f2f1f0efeeedec and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x29; dest:x9; op1val:0xf3f2f1f0efeeedec;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x9, x29, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xa, x1, 32, x2)
+
+inst_26:
+// rs1==x28, rd==x3, rs1_val == 0xefeeedecebeae9e8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x28; dest:x3; op1val:0xefeeedecebeae9e8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x3, x28, 0x0000000000000000, 0xefeeedecebeae9e8, 0xa, x1, 40, x2)
+
+inst_27:
+// rs1==x31, rd==x15, rs1_val == 0xebeae9e8e7e6e5e4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x31; dest:x15; op1val:0xebeae9e8e7e6e5e4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x15, x31, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xa, x1, 48, x2)
+
+inst_28:
+// rs1==x5, rd==x25, rs1_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x5; dest:x25; op1val:0xe7e6e5e4e3e2e1e0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x25, x5, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xa, x1, 56, x2)
+
+inst_29:
+// rs1==x15, rd==x0, rs1_val == 0xe3e2e1e0dfdedddc and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x15; dest:x0; op1val:0xe3e2e1e0dfdedddc;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x0, x15, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xa, x1, 64, x2)
+
+inst_30:
+// rs1==x14, rd==x26, rs1_val == 0xdfdedddcdbdad9d8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x14; dest:x26; op1val:0xdfdedddcdbdad9d8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x26, x14, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xa, x1, 72, x2)
+
+inst_31:
+// rs1==x22, rd==x12, rs1_val == 0xdbdad9d8d7d6d5d4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x22; dest:x12; op1val:0xdbdad9d8d7d6d5d4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x12, x22, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xa, x1, 80, x2)
+
+inst_32:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xd7d6d5d4d3d2d1d0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xa, x1, 88, x2)
+
+inst_33:
+// rs1_val == 0xd3d2d1d0cfcecdcc and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xd3d2d1d0cfcecdcc;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xa, x1, 96, x2)
+
+inst_34:
+// rs1_val == 0xcfcecdcccbcac9c8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xcfcecdcccbcac9c8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xa, x1, 104, x2)
+
+inst_35:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xcbcac9c8c7c6c5c4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xa, x1, 112, x2)
+
+inst_36:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xc7c6c5c4c3c2c1c0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xa, x1, 120, x2)
+
+inst_37:
+// rs1_val == 0xc3c2c1c0bfbebdbc and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xc3c2c1c0bfbebdbc;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xa, x1, 128, x2)
+
+inst_38:
+// rs1_val == 0xbfbebdbcbbbab9b8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xbfbebdbcbbbab9b8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xa, x1, 136, x2)
+
+inst_39:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xbbbab9b8b7b6b5b4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xa, x1, 144, x2)
+
+inst_40:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xb7b6b5b4b3b2b1b0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xa, x1, 152, x2)
+
+inst_41:
+// rs1_val == 0xb3b2b1b0afaeadac and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xb3b2b1b0afaeadac;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xa, x1, 160, x2)
+
+inst_42:
+// rs1_val == 0xafaeadacabaaa9a8 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xafaeadacabaaa9a8;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xa, x1, 168, x2)
+
+inst_43:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xabaaa9a8a7a6a5a4;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa, x1, 176, x2)
+
+inst_44:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xa7a6a5a4a3a2a1a0;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xa, x1, 184, x2)
+
+inst_45:
+// rs1_val == 0xa3a2a1a09f9e9d9c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xa3a2a1a09f9e9d9c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0xa, x1, 192, x2)
+
+inst_46:
+// rs1_val == 0x9f9e9d9c9b9a9998 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x9f9e9d9c9b9a9998;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa, x1, 200, x2)
+
+inst_47:
+// rs1_val == 0x9b9a999897969594 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x9b9a999897969594;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x9b9a999897969594, 0xa, x1, 208, x2)
+
+inst_48:
+// rs1_val == 0x9796959493929190 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x9796959493929190;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x9796959493929190, 0xa, x1, 216, x2)
+
+inst_49:
+// rs1_val == 0x939291908f8e8d8c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x939291908f8e8d8c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x939291908f8e8d8c, 0xa, x1, 224, x2)
+
+inst_50:
+// rs1_val == 0x8f8e8d8c8b8a8988 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x8f8e8d8c8b8a8988;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0xa, x1, 232, x2)
+
+inst_51:
+// rs1_val == 0x8b8a898887868584 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x8b8a898887868584;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x8b8a898887868584, 0xa, x1, 240, x2)
+
+inst_52:
+// rs1_val == 0x8786858483828180 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x8786858483828180;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x8786858483828180, 0xa, x1, 248, x2)
+
+inst_53:
+// rs1_val == 0x838281807f7e7d7c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x838281807f7e7d7c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x838281807f7e7d7c, 0xa, x1, 256, x2)
+
+inst_54:
+// rs1_val == 0x7f7e7d7c7b7a7978 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x7f7e7d7c7b7a7978;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0xa, x1, 264, x2)
+
+inst_55:
+// rs1_val == 0x7b7a797877767574 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x7b7a797877767574;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x7b7a797877767574, 0xa, x1, 272, x2)
+
+inst_56:
+// rs1_val == 0x7776757473727170 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x7776757473727170;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x7776757473727170, 0xa, x1, 280, x2)
+
+inst_57:
+// rs1_val == 0x737271706f6e6d6c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x737271706f6e6d6c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x737271706f6e6d6c, 0xa, x1, 288, x2)
+
+inst_58:
+// rs1_val == 0x6f6e6d6c6b6a6968 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x6f6e6d6c6b6a6968;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0xa, x1, 296, x2)
+
+inst_59:
+// rs1_val == 0x6b6a696867666564 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x6b6a696867666564;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x6b6a696867666564, 0xa, x1, 304, x2)
+
+inst_60:
+// rs1_val == 0x6766656463626160 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x6766656463626160;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x6766656463626160, 0xa, x1, 312, x2)
+
+inst_61:
+// rs1_val == 0x636261605f5e5d5c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x636261605f5e5d5c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x636261605f5e5d5c, 0xa, x1, 320, x2)
+
+inst_62:
+// rs1_val == 0x5f5e5d5c5b5a5958 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x5f5e5d5c5b5a5958;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0xa, x1, 328, x2)
+
+inst_63:
+// rs1_val == 0x5b5a595857565554 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x5b5a595857565554;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x5b5a595857565554, 0xa, x1, 336, x2)
+
+inst_64:
+// rs1_val == 0x5756555453525150 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x5756555453525150;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x5756555453525150, 0xa, x1, 344, x2)
+
+inst_65:
+// rs1_val == 0x535251504f4e4d4c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x535251504f4e4d4c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x535251504f4e4d4c, 0xa, x1, 352, x2)
+
+inst_66:
+// rs1_val == 0x4f4e4d4c4b4a4948 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x4f4e4d4c4b4a4948;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0xa, x1, 360, x2)
+
+inst_67:
+// rs1_val == 0x4b4a494847464544 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x4b4a494847464544;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x4b4a494847464544, 0xa, x1, 368, x2)
+
+inst_68:
+// rs1_val == 0x4746454443424140 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x4746454443424140;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x4746454443424140, 0xa, x1, 376, x2)
+
+inst_69:
+// rs1_val == 0x434241403f3e3d3c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x434241403f3e3d3c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x434241403f3e3d3c, 0xa, x1, 384, x2)
+
+inst_70:
+// rs1_val == 0x3f3e3d3c3b3a3938 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x3f3e3d3c3b3a3938;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0xa, x1, 392, x2)
+
+inst_71:
+// rs1_val == 0x3b3a393837363534 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x3b3a393837363534;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x3b3a393837363534, 0xa, x1, 400, x2)
+
+inst_72:
+// rs1_val == 0x3736353433323130 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x3736353433323130;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x3736353433323130, 0xa, x1, 408, x2)
+
+inst_73:
+// rs1_val == 0x333231302f2e2d2c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x333231302f2e2d2c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x333231302f2e2d2c, 0xa, x1, 416, x2)
+
+inst_74:
+// rs1_val == 0x2f2e2d2c2b2a2928 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x2f2e2d2c2b2a2928;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0xa, x1, 424, x2)
+
+inst_75:
+// rs1_val == 0x2b2a292827262524 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x2b2a292827262524;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x2b2a292827262524, 0xa, x1, 432, x2)
+
+inst_76:
+// rs1_val == 0x2726252423222120 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x2726252423222120;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x2726252423222120, 0xa, x1, 440, x2)
+
+inst_77:
+// rs1_val == 0x232221201f1e1d1c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x232221201f1e1d1c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x232221201f1e1d1c, 0xa, x1, 448, x2)
+
+inst_78:
+// rs1_val == 0x1f1e1d1c1b1a1918 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x1f1e1d1c1b1a1918;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0xa, x1, 456, x2)
+
+inst_79:
+// rs1_val == 0x1b1a191817161514 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x1b1a191817161514;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x1b1a191817161514, 0xa, x1, 464, x2)
+
+inst_80:
+// rs1_val == 0x1716151413121110 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x1716151413121110;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x1716151413121110, 0xa, x1, 472, x2)
+
+inst_81:
+// rs1_val == 0x131211100f0e0d0c and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x131211100f0e0d0c;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x131211100f0e0d0c, 0xa, x1, 480, x2)
+
+inst_82:
+// rs1_val == 0x0f0e0d0c0b0a0908 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xf0e0d0c0b0a0908;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0xa, x1, 488, x2)
+
+inst_83:
+// rs1_val == 0x0b0a090807060504 and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xb0a090807060504;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xb0a090807060504, 0xa, x1, 496, x2)
+
+inst_84:
+// rs1_val == 0x9722c9a6b0942992 and imm_val == 0x5 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0x9722c9a6b0942992;  immval:0x5
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0x9722c9a6b0942992, 0x5, x1, 504, x2)
+
+inst_85:
+// rs1_val == 0xe3e2e1e0dfdedddc and imm_val == 0xA 
+// opcode: aes64ks1i ; op1:x10; dest:x11; op1val:0xe3e2e1e0dfdedddc;  immval:0xa
+TEST_IMM_OP( aes64ks1i, x11, x10, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xa, x1, 512, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x14_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x14_1:
+    .fill 21*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 65*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S
new file mode 100644
index 000000000..3f40ce4aa
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/aes64ks2-01.S
@@ -0,0 +1,1184 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the aes64ks2 instruction of the RISC-V  extension for the aes64ks2 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",aes64ks2)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",aes64ks2)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKne.*);def TEST_CASE_1=True;",aes64ks2)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x8, rs2==x8, rd==x13, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64ks2 ; op1:x8; op2:x8; dest:x13; op1val:0x75a3adb3254a9493;  op2val:0x75a3adb3254a9493
+TEST_RR_OP(aes64ks2, x13, x8, x8, 0x0000000000000000, 0x75a3adb3254a9493, 0x75a3adb3254a9493, x2, 0, x11)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x28, rs2==x28, rd==x28, rs2_val == 9223372036854775807, 
+// opcode: aes64ks2 ; op1:x28; op2:x28; dest:x28; op1val:0xd;  op2val:0xd
+TEST_RR_OP(aes64ks2, x28, x28, x28, 0x0000000000000000, 0xd, 0xd, x2, 8, x11)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x4, rs2==x0, rd==x24, rs2_val == 13835058055282163711, 
+// opcode: aes64ks2 ; op1:x4; op2:x0; dest:x24; op1val:-0x5;  op2val:0x0
+TEST_RR_OP(aes64ks2, x24, x4, x0, 0x0000000000000000, -0x5, 0x0, x2, 16, x11)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x6, rs2==x22, rd==x6, rs2_val == 16140901064495857663, rs1_val == 281474976710656
+// opcode: aes64ks2 ; op1:x6; op2:x22; dest:x6; op1val:0x1000000000000;  op2val:0xdfffffffffffffff
+TEST_RR_OP(aes64ks2, x6, x6, x22, 0x0000000000000000, 0x1000000000000, 0xdfffffffffffffff, x2, 24, x11)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x10, rs2==x9, rd==x9, rs2_val == 17293822569102704639, rs1_val == 16384
+// opcode: aes64ks2 ; op1:x10; op2:x9; dest:x9; op1val:0x4000;  op2val:0xefffffffffffffff
+TEST_RR_OP(aes64ks2, x9, x10, x9, 0x0000000000000000, 0x4000, 0xefffffffffffffff, x2, 32, x11)
+
+inst_5:
+// rs1==x1, rs2==x7, rd==x20, rs2_val == 17870283321406128127, rs1_val == 131072
+// opcode: aes64ks2 ; op1:x1; op2:x7; dest:x20; op1val:0x20000;  op2val:0xf7ffffffffffffff
+TEST_RR_OP(aes64ks2, x20, x1, x7, 0x0000000000000000, 0x20000, 0xf7ffffffffffffff, x2, 40, x11)
+
+inst_6:
+// rs1==x17, rs2==x23, rd==x7, rs2_val == 18158513697557839871, rs1_val == 70368744177664
+// opcode: aes64ks2 ; op1:x17; op2:x23; dest:x7; op1val:0x400000000000;  op2val:0xfbffffffffffffff
+TEST_RR_OP(aes64ks2, x7, x17, x23, 0x0000000000000000, 0x400000000000, 0xfbffffffffffffff, x2, 48, x11)
+
+inst_7:
+// rs1==x18, rs2==x13, rd==x14, rs2_val == 18302628885633695743, 
+// opcode: aes64ks2 ; op1:x18; op2:x13; dest:x14; op1val:-0x4000000000000000;  op2val:0xfdffffffffffffff
+TEST_RR_OP(aes64ks2, x14, x18, x13, 0x0000000000000000, -0x4000000000000000, 0xfdffffffffffffff, x2, 56, x11)
+
+inst_8:
+// rs1==x12, rs2==x27, rd==x16, rs2_val == 18374686479671623679, rs1_val == 18446744069414584319
+// opcode: aes64ks2 ; op1:x12; op2:x27; dest:x16; op1val:0xfffffffeffffffff;  op2val:0xfeffffffffffffff
+TEST_RR_OP(aes64ks2, x16, x12, x27, 0x0000000000000000, 0xfffffffeffffffff, 0xfeffffffffffffff, x2, 64, x11)
+
+inst_9:
+// rs1==x30, rs2==x17, rd==x31, rs2_val == 18410715276690587647, 
+// opcode: aes64ks2 ; op1:x30; op2:x17; dest:x31; op1val:-0x200000001;  op2val:0xff7fffffffffffff
+TEST_RR_OP(aes64ks2, x31, x30, x17, 0x0000000000000000, -0x200000001, 0xff7fffffffffffff, x2, 72, x11)
+
+inst_10:
+// rs1==x22, rs2==x4, rd==x3, rs2_val == 18428729675200069631, rs1_val == 4611686018427387904
+// opcode: aes64ks2 ; op1:x22; op2:x4; dest:x3; op1val:0x4000000000000000;  op2val:0xffbfffffffffffff
+TEST_RR_OP(aes64ks2, x3, x22, x4, 0x0000000000000000, 0x4000000000000000, 0xffbfffffffffffff, x2, 80, x11)
+
+inst_11:
+// rs1==x9, rs2==x15, rd==x5, rs2_val == 18437736874454810623, 
+// opcode: aes64ks2 ; op1:x9; op2:x15; dest:x5; op1val:-0x7;  op2val:0xffdfffffffffffff
+TEST_RR_OP(aes64ks2, x5, x9, x15, 0x0000000000000000, -0x7, 0xffdfffffffffffff, x2, 88, x11)
+
+inst_12:
+// rs1==x27, rs2==x18, rd==x29, rs2_val == 18442240474082181119, rs1_val == 18446744073709551487
+// opcode: aes64ks2 ; op1:x27; op2:x18; dest:x29; op1val:0xffffffffffffff7f;  op2val:0xffefffffffffffff
+TEST_RR_OP(aes64ks2, x29, x27, x18, 0x0000000000000000, 0xffffffffffffff7f, 0xffefffffffffffff, x2, 96, x11)
+
+inst_13:
+// rs1==x24, rs2==x12, rd==x17, rs2_val == 18444492273895866367, 
+// opcode: aes64ks2 ; op1:x24; op2:x12; dest:x17; op1val:-0x20000000001;  op2val:0xfff7ffffffffffff
+TEST_RR_OP(aes64ks2, x17, x24, x12, 0x0000000000000000, -0x20000000001, 0xfff7ffffffffffff, x2, 104, x11)
+
+inst_14:
+// rs1==x21, rs2==x26, rd==x10, rs2_val == 18445618173802708991, rs1_val == 18014398509481984
+// opcode: aes64ks2 ; op1:x21; op2:x26; dest:x10; op1val:0x40000000000000;  op2val:0xfffbffffffffffff
+TEST_RR_OP(aes64ks2, x10, x21, x26, 0x0000000000000000, 0x40000000000000, 0xfffbffffffffffff, x2, 112, x11)
+
+inst_15:
+// rs1==x0, rs2==x1, rd==x12, rs2_val == 18446181123756130303, 
+// opcode: aes64ks2 ; op1:x0; op2:x1; dest:x12; op1val:0x0;  op2val:0xfffdffffffffffff
+TEST_RR_OP(aes64ks2, x12, x0, x1, 0x0000000000000000, 0x0, 0xfffdffffffffffff, x2, 120, x8)
+
+inst_16:
+// rs1==x15, rs2==x19, rd==x25, rs2_val == 18446462598732840959, rs1_val == 18446744073709551614
+// opcode: aes64ks2 ; op1:x15; op2:x19; dest:x25; op1val:0xfffffffffffffffe;  op2val:0xfffeffffffffffff
+TEST_RR_OP(aes64ks2, x25, x15, x19, 0x0000000000000000, 0xfffffffffffffffe, 0xfffeffffffffffff, x2, 128, x8)
+RVTEST_SIGBASE( x9,signature_x9_0)
+
+inst_17:
+// rs1==x13, rs2==x6, rd==x1, rs2_val == 18446603336221196287, 
+// opcode: aes64ks2 ; op1:x13; op2:x6; dest:x1; op1val:-0x40001;  op2val:0xffff7fffffffffff
+TEST_RR_OP(aes64ks2, x1, x13, x6, 0x0000000000000000, -0x40001, 0xffff7fffffffffff, x9, 0, x8)
+
+inst_18:
+// rs1==x7, rs2==x2, rd==x30, rs2_val == 18446673704965373951, 
+// opcode: aes64ks2 ; op1:x7; op2:x2; dest:x30; op1val:0x400000000000;  op2val:0xffffbfffffffffff
+TEST_RR_OP(aes64ks2, x30, x7, x2, 0x0000000000000000, 0x400000000000, 0xffffbfffffffffff, x9, 8, x8)
+
+inst_19:
+// rs1==x29, rs2==x5, rd==x2, rs2_val == 18446708889337462783, rs1_val == 16
+// opcode: aes64ks2 ; op1:x29; op2:x5; dest:x2; op1val:0x10;  op2val:0xffffdfffffffffff
+TEST_RR_OP(aes64ks2, x2, x29, x5, 0x0000000000000000, 0x10, 0xffffdfffffffffff, x9, 16, x8)
+
+inst_20:
+// rs1==x25, rs2==x20, rd==x19, rs2_val == 18446726481523507199, 
+// opcode: aes64ks2 ; op1:x25; op2:x20; dest:x19; op1val:-0x40001;  op2val:0xffffefffffffffff
+TEST_RR_OP(aes64ks2, x19, x25, x20, 0x0000000000000000, -0x40001, 0xffffefffffffffff, x9, 24, x8)
+
+inst_21:
+// rs1==x26, rs2==x14, rd==x4, rs2_val == 18446735277616529407, 
+// opcode: aes64ks2 ; op1:x26; op2:x14; dest:x4; op1val:0x400000000000;  op2val:0xfffff7ffffffffff
+TEST_RR_OP(aes64ks2, x4, x26, x14, 0x0000000000000000, 0x400000000000, 0xfffff7ffffffffff, x9, 32, x8)
+
+inst_22:
+// rs1==x19, rs2==x24, rd==x23, rs2_val == 18446739675663040511, 
+// opcode: aes64ks2 ; op1:x19; op2:x24; dest:x23; op1val:-0x1000000000001;  op2val:0xfffffbffffffffff
+TEST_RR_OP(aes64ks2, x23, x19, x24, 0x0000000000000000, -0x1000000000001, 0xfffffbffffffffff, x9, 40, x8)
+
+inst_23:
+// rs1==x3, rs2==x16, rd==x15, rs2_val == 18446741874686296063, rs1_val == 18158513697557839871
+// opcode: aes64ks2 ; op1:x3; op2:x16; dest:x15; op1val:0xfbffffffffffffff;  op2val:0xfffffdffffffffff
+TEST_RR_OP(aes64ks2, x15, x3, x16, 0x0000000000000000, 0xfbffffffffffffff, 0xfffffdffffffffff, x9, 48, x8)
+
+inst_24:
+// rs1==x31, rs2==x11, rd==x21, rs2_val == 18446742974197923839, rs1_val == 18446744073707454463
+// opcode: aes64ks2 ; op1:x31; op2:x11; dest:x21; op1val:0xffffffffffdfffff;  op2val:0xfffffeffffffffff
+TEST_RR_OP(aes64ks2, x21, x31, x11, 0x0000000000000000, 0xffffffffffdfffff, 0xfffffeffffffffff, x9, 56, x8)
+
+inst_25:
+// rs1==x14, rs2==x21, rd==x27, rs2_val == 18446743523953737727, 
+// opcode: aes64ks2 ; op1:x14; op2:x21; dest:x27; op1val:0x4000000000000000;  op2val:0xffffff7fffffffff
+TEST_RR_OP(aes64ks2, x27, x14, x21, 0x0000000000000000, 0x4000000000000000, 0xffffff7fffffffff, x9, 64, x8)
+
+inst_26:
+// rs1==x5, rs2==x30, rd==x18, rs2_val == 18446743798831644671, rs1_val == 8
+// opcode: aes64ks2 ; op1:x5; op2:x30; dest:x18; op1val:0x8;  op2val:0xffffffbfffffffff
+TEST_RR_OP(aes64ks2, x18, x5, x30, 0x0000000000000000, 0x8, 0xffffffbfffffffff, x9, 72, x8)
+
+inst_27:
+// rs1==x2, rs2==x29, rd==x11, rs2_val == 18446743936270598143, 
+// opcode: aes64ks2 ; op1:x2; op2:x29; dest:x11; op1val:-0x800000000000001;  op2val:0xffffffdfffffffff
+TEST_RR_OP(aes64ks2, x11, x2, x29, 0x0000000000000000, -0x800000000000001, 0xffffffdfffffffff, x9, 80, x8)
+
+inst_28:
+// rs1==x20, rs2==x10, rd==x0, rs2_val == 18446744004990074879, 
+// opcode: aes64ks2 ; op1:x20; op2:x10; dest:x0; op1val:-0xa;  op2val:0xffffffefffffffff
+TEST_RR_OP(aes64ks2, x0, x20, x10, 0x0000000000000000, -0xa, 0xffffffefffffffff, x9, 88, x8)
+
+inst_29:
+// rs1==x16, rs2==x25, rd==x26, rs2_val == 18446744039349813247, rs1_val == 2251799813685248
+// opcode: aes64ks2 ; op1:x16; op2:x25; dest:x26; op1val:0x8000000000000;  op2val:0xfffffff7ffffffff
+TEST_RR_OP(aes64ks2, x26, x16, x25, 0x0000000000000000, 0x8000000000000, 0xfffffff7ffffffff, x9, 96, x8)
+
+inst_30:
+// rs1==x23, rs2==x3, rd==x22, rs2_val == 18446744056529682431, rs1_val == 35184372088832
+// opcode: aes64ks2 ; op1:x23; op2:x3; dest:x22; op1val:0x200000000000;  op2val:0xfffffffbffffffff
+TEST_RR_OP(aes64ks2, x22, x23, x3, 0x0000000000000000, 0x200000000000, 0xfffffffbffffffff, x9, 104, x8)
+
+inst_31:
+// rs1==x11, rs2==x31, rd==x8, rs2_val == 18446744065119617023, rs1_val == 72057594037927936
+// opcode: aes64ks2 ; op1:x11; op2:x31; dest:x8; op1val:0x100000000000000;  op2val:0xfffffffdffffffff
+TEST_RR_OP(aes64ks2, x8, x11, x31, 0x0000000000000000, 0x100000000000000, 0xfffffffdffffffff, x9, 112, x2)
+
+inst_32:
+// rs2_val == 18446744069414584319, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0xfffffffeffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0xfffffffeffffffff, x9, 120, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_33:
+// rs2_val == 18446744071562067967, rs1_val == 34359738368
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800000000;  op2val:0xffffffff7fffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800000000, 0xffffffff7fffffff, x1, 0, x2)
+
+inst_34:
+// rs2_val == 18446744072635809791, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x40001;  op2val:0xffffffffbfffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x40001, 0xffffffffbfffffff, x1, 8, x2)
+
+inst_35:
+// rs2_val == 18446744073172680703, rs1_val == 18446744073709543423
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffdfff;  op2val:0xffffffffdfffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffdfff, 0xffffffffdfffffff, x1, 16, x2)
+
+inst_36:
+// rs2_val == 18446744073441116159, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x8000000001;  op2val:0xffffffffefffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x8000000001, 0xffffffffefffffff, x1, 24, x2)
+
+inst_37:
+// rs2_val == 18446744073575333887, rs1_val == 18446744056529682431
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbffffffff;  op2val:0xfffffffff7ffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffbffffffff, 0xfffffffff7ffffff, x1, 32, x2)
+
+inst_38:
+// rs2_val == 18446744073642442751, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000000001;  op2val:0xfffffffffbffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x80000000000001, 0xfffffffffbffffff, x1, 40, x2)
+
+inst_39:
+// rs2_val == 18446744073675997183, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x6;  op2val:0xfffffffffdffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x6, 0xfffffffffdffffff, x1, 48, x2)
+
+inst_40:
+// rs2_val == 18446744073692774399, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x200000000000001;  op2val:0xfffffffffeffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x200000000000001, 0xfffffffffeffffff, x1, 56, x2)
+
+inst_41:
+// rs2_val == 18446744073701163007, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800000000;  op2val:0xffffffffff7fffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800000000, 0xffffffffff7fffff, x1, 64, x2)
+
+inst_42:
+// rs2_val == 18446744073705357311, rs1_val == 33554432
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2000000;  op2val:0xffffffffffbfffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2000000, 0xffffffffffbfffff, x1, 72, x2)
+
+inst_43:
+// rs2_val == 18446744073707454463, rs1_val == 18446741874686296063
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdffffffffff;  op2val:0xffffffffffdfffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffdffffffffff, 0xffffffffffdfffff, x1, 80, x2)
+
+inst_44:
+// rs2_val == 18446744073708503039, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000;  op2val:0xffffffffffefffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000000000, 0xffffffffffefffff, x1, 88, x2)
+
+inst_45:
+// rs2_val == 18446744073709027327, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x1;  op2val:0xfffffffffff7ffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x1, 0xfffffffffff7ffff, x1, 96, x2)
+
+inst_46:
+// rs2_val == 18446744073709289471, rs1_val == 18446603336221196287
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffff7fffffffffff;  op2val:0xfffffffffffbffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffff7fffffffffff, 0xfffffffffffbffff, x1, 104, x2)
+
+inst_47:
+// rs2_val == 18446744073709420543, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x80000001;  op2val:0xfffffffffffdffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x80000001, 0xfffffffffffdffff, x1, 112, x2)
+
+inst_48:
+// rs2_val == 18446744073709486079, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0xfffffffffffeffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x5, 0xfffffffffffeffff, x1, 120, x2)
+
+inst_49:
+// rs2_val == 18446744073709518847, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xc;  op2val:0xffffffffffff7fff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xc, 0xffffffffffff7fff, x1, 128, x2)
+
+inst_50:
+// rs2_val == 18446744073709535231, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x10;  op2val:0xffffffffffffbfff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x10, 0xffffffffffffbfff, x1, 136, x2)
+
+inst_51:
+// rs2_val == 18446744073709543423, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0xffffffffffffdfff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x201, 0xffffffffffffdfff, x1, 144, x2)
+
+inst_52:
+// rs2_val == 18446744073709547519, rs1_val == 128
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x80;  op2val:0xffffffffffffefff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x80, 0xffffffffffffefff, x1, 152, x2)
+
+inst_53:
+// rs2_val == 18446744073709549567, rs1_val == 4398046511104
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x40000000000;  op2val:0xfffffffffffff7ff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x40000000000, 0xfffffffffffff7ff, x1, 160, x2)
+
+inst_54:
+// rs2_val == 18446744073709550591, rs1_val == 144115188075855872
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000000;  op2val:0xfffffffffffffbff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x200000000000000, 0xfffffffffffffbff, x1, 168, x2)
+
+inst_55:
+// rs2_val == 18446744073709551103, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x200001;  op2val:0xfffffffffffffdff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x200001, 0xfffffffffffffdff, x1, 176, x2)
+
+inst_56:
+// rs2_val == 18446744073709551359, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xfffffffffffffeff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000, 0xfffffffffffffeff, x1, 184, x2)
+
+inst_57:
+// rs2_val == 18446744073709551487, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x201;  op2val:0xffffffffffffff7f
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x201, 0xffffffffffffff7f, x1, 192, x2)
+
+inst_58:
+// rs2_val == 18446744073709551551, rs1_val == 18437736874454810623
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffdfffffffffffff;  op2val:0xffffffffffffffbf
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffdfffffffffffff, 0xffffffffffffffbf, x1, 200, x2)
+
+inst_59:
+// rs2_val == 18446744073709551583, rs1_val == 1073741824
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x40000000;  op2val:0xffffffffffffffdf
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x40000000, 0xffffffffffffffdf, x1, 208, x2)
+
+inst_60:
+// rs2_val == 18446744073709551599, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x2000000000000001;  op2val:0xffffffffffffffef
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x2000000000000001, 0xffffffffffffffef, x1, 216, x2)
+
+inst_61:
+// rs2_val == 18446744073709551607, rs1_val == 1
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0xfffffffffffffff7
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1, 0xfffffffffffffff7, x1, 224, x2)
+
+inst_62:
+// rs2_val == 18446744073709551611, rs1_val == 1152921504606846976
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000000000;  op2val:0xfffffffffffffffb
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1000000000000000, 0xfffffffffffffffb, x1, 232, x2)
+
+inst_63:
+// rs2_val == 18446744073709551613, rs1_val == 18446744065119617023
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffdffffffff;  op2val:0xfffffffffffffffd
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffdffffffff, 0xfffffffffffffffd, x1, 240, x2)
+
+inst_64:
+// rs2_val == 18446744073709551614, rs1_val == 1125899906842624
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000;  op2val:0xfffffffffffffffe
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000000000000, 0xfffffffffffffffe, x1, 248, x2)
+
+inst_65:
+// rs1_val == 9223372036854775807, rs2_val == 17179869184
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x400000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x400000000, x1, 256, x2)
+
+inst_66:
+// rs1_val == 13835058055282163711, rs2_val == 2305843009213693952
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x2000000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x2000000000000000, x1, 264, x2)
+
+inst_67:
+// rs1_val == 16140901064495857663, rs2_val == 137438953472
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0x2000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0x2000000000, x1, 272, x2)
+
+inst_68:
+// rs1_val == 17293822569102704639, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xefffffffffffffff;  op2val:-0x2
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xefffffffffffffff, -0x2, x1, 280, x2)
+
+inst_69:
+// rs1_val == 17870283321406128127, rs2_val == 32
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xf7ffffffffffffff;  op2val:0x20
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xf7ffffffffffffff, 0x20, x1, 288, x2)
+
+inst_70:
+// rs1_val == 18302628885633695743, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfdffffffffffffff;  op2val:-0x40000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfdffffffffffffff, -0x40000000001, x1, 296, x2)
+
+inst_71:
+// rs1_val == 18374686479671623679, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfeffffffffffffff;  op2val:0xfffffffeffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfeffffffffffffff, 0xfffffffeffffffff, x1, 304, x2)
+
+inst_72:
+// rs1_val == 18410715276690587647, rs2_val == 70368744177664
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xff7fffffffffffff;  op2val:0x400000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xff7fffffffffffff, 0x400000000000, x1, 312, x2)
+
+inst_73:
+// rs1_val == 18428729675200069631, rs2_val == 8192
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffffffffffff;  op2val:0x2000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffbfffffffffffff, 0x2000, x1, 320, x2)
+
+inst_74:
+// rs1_val == 18442240474082181119, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffefffffffffffff;  op2val:0x9
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffefffffffffffff, 0x9, x1, 328, x2)
+
+inst_75:
+// rs1_val == 18444492273895866367, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfff7ffffffffffff;  op2val:-0x1000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfff7ffffffffffff, -0x1000001, x1, 336, x2)
+
+inst_76:
+// rs1_val == 18445618173802708991, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffbffffffffffff;  op2val:-0x100000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffbffffffffffff, -0x100000001, x1, 344, x2)
+
+inst_77:
+// rs1_val == 18446181123756130303, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffdffffffffffff;  op2val:0xffffffffffff7fff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffdffffffffffff, 0xffffffffffff7fff, x1, 352, x2)
+
+inst_78:
+// rs1_val == 18446462598732840959, rs2_val == 4503599627370496
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffeffffffffffff;  op2val:0x10000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffeffffffffffff, 0x10000000000000, x1, 360, x2)
+
+inst_79:
+// rs1_val == 18446673704965373951, rs2_val == 2
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfffffffffff;  op2val:0x2
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffbfffffffffff, 0x2, x1, 368, x2)
+
+inst_80:
+// rs1_val == 18446708889337462783, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfffffffffff;  op2val:0xfffffdffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffdfffffffffff, 0xfffffdffffffffff, x1, 376, x2)
+
+inst_81:
+// rs1_val == 18446726481523507199, rs2_val == 144115188075855872
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffefffffffffff;  op2val:0x200000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffefffffffffff, 0x200000000000000, x1, 384, x2)
+
+inst_82:
+// rs1_val == 18446735277616529407, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffff7ffffffffff;  op2val:0xfffffffff7ffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffff7ffffffffff, 0xfffffffff7ffffff, x1, 392, x2)
+
+inst_83:
+// rs1_val == 18446739675663040511, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffbffffffffff;  op2val:-0x100001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffbffffffffff, -0x100001, x1, 400, x2)
+
+inst_84:
+// rs1_val == 18446742974197923839, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffeffffffffff;  op2val:0xefffffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffeffffffffff, 0xefffffffffffffff, x1, 408, x2)
+
+inst_85:
+// rs1_val == 18446743523953737727, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffff7fffffffff;  op2val:-0x4000000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffff7fffffffff, -0x4000000000000000, x1, 416, x2)
+
+inst_86:
+// rs1_val == 18446743798831644671, rs2_val == 64
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffbfffffffff;  op2val:0x40
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffbfffffffff, 0x40, x1, 424, x2)
+
+inst_87:
+// rs1_val == 18446743936270598143, rs2_val == 18014398509481984
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdfffffffff;  op2val:0x40000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffdfffffffff, 0x40000000000000, x1, 432, x2)
+
+inst_88:
+// rs1_val == 18446744004990074879, rs2_val == 131072
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffefffffffff;  op2val:0x20000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffefffffffff, 0x20000, x1, 440, x2)
+
+inst_89:
+// rs1_val == 18446744039349813247, rs2_val == 2251799813685248
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7ffffffff;  op2val:0x8000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffff7ffffffff, 0x8000000000000, x1, 448, x2)
+
+inst_90:
+// rs1_val == 18446744071562067967, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff7fffffff;  op2val:0x6
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffff7fffffff, 0x6, x1, 456, x2)
+
+inst_91:
+// rs1_val == 18446744072635809791, rs2_val == 1099511627776
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffbfffffff;  op2val:0x10000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffbfffffff, 0x10000000000, x1, 464, x2)
+
+inst_92:
+// rs1_val == 18446744073172680703, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffdfffffff;  op2val:-0x1000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffdfffffff, -0x1000001, x1, 472, x2)
+
+inst_93:
+// rs1_val == 18446744073441116159, rs2_val == 268435456
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffefffffff;  op2val:0x10000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffefffffff, 0x10000000, x1, 480, x2)
+
+inst_94:
+// rs1_val == 18446744073575333887, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff7ffffff;  op2val:0x3
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffff7ffffff, 0x3, x1, 488, x2)
+
+inst_95:
+// rs1_val == 18446744073642442751, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffbffffff;  op2val:-0x40000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffbffffff, -0x40000000001, x1, 496, x2)
+
+inst_96:
+// rs1_val == 18446744073675997183, rs2_val == 1
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffdffffff;  op2val:0x1
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffdffffff, 0x1, x1, 504, x2)
+
+inst_97:
+// rs1_val == 18446744073692774399, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffeffffff;  op2val:-0x100000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffeffffff, -0x100000001, x1, 512, x2)
+
+inst_98:
+// rs1_val == 18446744073701163007, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7fffff;  op2val:0xfffffffffffffffd
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffff7fffff, 0xfffffffffffffffd, x1, 520, x2)
+
+inst_99:
+// rs1_val == 18446744073705357311, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffbfffff;  op2val:0x7fffffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffbfffff, 0x7fffffffffffffff, x1, 528, x2)
+
+inst_100:
+// rs1_val == 18446744073708503039, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffefffff;  op2val:0x12
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffefffff, 0x12, x1, 536, x2)
+
+inst_101:
+// rs1_val == 18446744073709027327, rs2_val == 140737488355328
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff7ffff;  op2val:0x800000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffff7ffff, 0x800000000000, x1, 544, x2)
+
+inst_102:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x1, 552, x2)
+
+inst_103:
+// rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x1, 560, x2)
+
+inst_104:
+// rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x1, 568, x2)
+
+inst_105:
+// rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x1, 576, x2)
+
+inst_106:
+// rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x1, 584, x2)
+
+inst_107:
+// rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x1, 592, x2)
+
+inst_108:
+// rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x1, 600, x2)
+
+inst_109:
+// rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x1, 608, x2)
+
+inst_110:
+// rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x1, 616, x2)
+
+inst_111:
+// rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x1, 624, x2)
+
+inst_112:
+// rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x1, 632, x2)
+
+inst_113:
+// rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x1, 640, x2)
+
+inst_114:
+// rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x1, 648, x2)
+
+inst_115:
+// rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x1, 656, x2)
+
+inst_116:
+// rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x1, 664, x2)
+
+inst_117:
+// rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x1, 672, x2)
+
+inst_118:
+// rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x1, 680, x2)
+
+inst_119:
+// rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x1, 688, x2)
+
+inst_120:
+// rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x1, 696, x2)
+
+inst_121:
+// rs1_val == 18446744073709289471, rs2_val == 72057594037927936
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbffff;  op2val:0x100000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbffff, 0x100000000000000, x1, 704, x2)
+
+inst_122:
+// rs1_val == 18446744073709420543, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffdffff;  op2val:-0x40000000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffdffff, -0x40000000000001, x1, 712, x2)
+
+inst_123:
+// rs1_val == 18446744073709486079, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffeffff;  op2val:-0x10000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffeffff, -0x10000000001, x1, 720, x2)
+
+inst_124:
+// rs1_val == 18446744073709518847, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff7fff;  op2val:-0x9
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffff7fff, -0x9, x1, 728, x2)
+
+inst_125:
+// rs1_val == 18446744073709535231, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffbfff;  op2val:0xfffffffffdffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffbfff, 0xfffffffffdffffff, x1, 736, x2)
+
+inst_126:
+// rs1_val == 18446744073709547519, rs2_val == 1152921504606846976
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffefff;  op2val:0x1000000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffefff, 0x1000000000000000, x1, 744, x2)
+
+inst_127:
+// rs1_val == 18446744073709549567, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff7ff;  op2val:0x5555555555555555
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff7ff, 0x5555555555555555, x1, 752, x2)
+
+inst_128:
+// rs1_val == 18446744073709550591, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffbff;  op2val:0xfffffffdffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffbff, 0xfffffffdffffffff, x1, 760, x2)
+
+inst_129:
+// rs1_val == 18446744073709551103, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffdff;  op2val:0x100000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffdff, 0x100000000000000, x1, 768, x2)
+
+inst_130:
+// rs1_val == 18446744073709551359, rs2_val == 4194304
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffeff;  op2val:0x400000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffeff, 0x400000, x1, 776, x2)
+
+inst_131:
+// rs1_val == 18446744073709551551, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffbf;  op2val:-0x2000000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffbf, -0x2000000000001, x1, 784, x2)
+
+inst_132:
+// rs1_val == 18446744073709551583, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffdf;  op2val:0x2
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffdf, 0x2, x1, 792, x2)
+
+inst_133:
+// rs1_val == 18446744073709551599, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffef;  op2val:0x2000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffef, 0x2000000000, x1, 800, x2)
+
+inst_134:
+// rs1_val == 18446744073709551607, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff7;  op2val:0x40000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff7, 0x40000000000000, x1, 808, x2)
+
+inst_135:
+// rs1_val == 18446744073709551611, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0x400000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0x400000000000, x1, 816, x2)
+
+inst_136:
+// rs1_val == 18446744073709551613, rs2_val == 2097152
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffd;  op2val:0x200000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffd, 0x200000, x1, 824, x2)
+
+inst_137:
+// rs2_val == 9223372036854775808, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffdfffffffff;  op2val:0x8000000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffdfffffffff, 0x8000000000000000, x1, 832, x2)
+
+inst_138:
+// rs2_val == 4611686018427387904, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x5555555555555555;  op2val:0x4000000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x5555555555555555, 0x4000000000000000, x1, 840, x2)
+
+inst_139:
+// rs2_val == 576460752303423488, rs1_val == 576460752303423488
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000000;  op2val:0x800000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800000000000000, 0x800000000000000, x1, 848, x2)
+
+inst_140:
+// rs2_val == 288230376151711744, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xd;  op2val:0x400000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xd, 0x400000000000000, x1, 856, x2)
+
+inst_141:
+// rs2_val == 36028797018963968, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffbfffffffffffff;  op2val:0x80000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffbfffffffffffff, 0x80000000000000, x1, 864, x2)
+
+inst_142:
+// rs2_val == 9007199254740992, rs1_val == 9007199254740992
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000;  op2val:0x20000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x20000000000000, 0x20000000000000, x1, 872, x2)
+
+inst_143:
+// rs2_val == 1125899906842624, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000;  op2val:0x4000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000000000, 0x4000000000000, x1, 880, x2)
+
+inst_144:
+// rs2_val == 562949953421312, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffdffffff;  op2val:0x2000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffdffffff, 0x2000000000000, x1, 888, x2)
+
+inst_145:
+// rs2_val == 281474976710656, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x81;  op2val:0x1000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x81, 0x1000000000000, x1, 896, x2)
+
+inst_146:
+// rs2_val == 35184372088832, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x80000000001;  op2val:0x200000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x80000000001, 0x200000000000, x1, 904, x2)
+
+inst_147:
+// rs2_val == 17592186044416, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000000;  op2val:0x100000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x20000000000000, 0x100000000000, x1, 912, x2)
+
+inst_148:
+// rs2_val == 8796093022208, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff7fffffff;  op2val:0x80000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffff7fffffff, 0x80000000000, x1, 920, x2)
+
+inst_149:
+// rs2_val == 4398046511104, rs1_val == 2305843009213693952
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0x40000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0x40000000000, x1, 928, x2)
+
+inst_150:
+// rs2_val == 2199023255552, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffbfffffff;  op2val:0x20000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffffffbfffffff, 0x20000000000, x1, 936, x2)
+
+inst_151:
+// rs2_val == 549755813888, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8;  op2val:0x8000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8, 0x8000000000, x1, 944, x2)
+
+inst_152:
+// rs2_val == 274877906944, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000;  op2val:0x4000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x400000000000, 0x4000000000, x1, 952, x2)
+
+inst_153:
+// rs2_val == 68719476736, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x1000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x11, 0x1000000000, x1, 960, x2)
+
+inst_154:
+// rs2_val == 34359738368, rs1_val == 1048576
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x800000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x100000, 0x800000000, x1, 968, x2)
+
+inst_155:
+// rs2_val == 8589934592, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x200000000000;  op2val:0x200000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x200000000000, 0x200000000, x1, 976, x2)
+
+inst_156:
+// rs2_val == 4294967296, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x100000;  op2val:0x100000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x100000, 0x100000000, x1, 984, x2)
+
+inst_157:
+// rs2_val == 2147483648, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffd;  op2val:0x80000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffd, 0x80000000, x1, 992, x2)
+
+inst_158:
+// rs2_val == 1073741824, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x5;  op2val:0x40000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x5, 0x40000000, x1, 1000, x2)
+
+inst_159:
+// rs2_val == 536870912, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff7ffffffff;  op2val:0x20000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffff7ffffffff, 0x20000000, x1, 1008, x2)
+
+inst_160:
+// rs2_val == 134217728, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x8000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x0, 0x8000000, x1, 1016, x2)
+
+inst_161:
+// rs2_val == 67108864, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x4000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x4000000, x1, 1024, x2)
+
+inst_162:
+// rs2_val == 33554432, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffdffffffffff;  op2val:0x2000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffdffffffffff, 0x2000000, x1, 1032, x2)
+
+inst_163:
+// rs2_val == 16777216, rs1_val == 65536
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x10000;  op2val:0x1000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x10000, 0x1000000, x1, 1040, x2)
+
+inst_164:
+// rs2_val == 8388608, rs1_val == 9223372036854775808
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0x800000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0x800000, x1, 1048, x2)
+
+inst_165:
+// rs2_val == 1048576, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x9;  op2val:0x100000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x9, 0x100000, x1, 1056, x2)
+
+inst_166:
+// rs2_val == 524288, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeffffffff;  op2val:0x80000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffeffffffff, 0x80000, x1, 1064, x2)
+
+inst_167:
+// rs2_val == 262144, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffdfffffffffff;  op2val:0x40000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffdfffffffffff, 0x40000, x1, 1072, x2)
+
+inst_168:
+// rs2_val == 65536, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffdff;  op2val:0x10000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffdff, 0x10000, x1, 1080, x2)
+
+inst_169:
+// rs2_val == 32768, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x8;  op2val:0x8000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x8, 0x8000, x1, 1088, x2)
+
+inst_170:
+// rs2_val == 16384, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xffffbfffffffffff;  op2val:0x4000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xffffbfffffffffff, 0x4000, x1, 1096, x2)
+
+inst_171:
+// rs2_val == 4096, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbffffffff;  op2val:0x1000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0xfffffffbffffffff, 0x1000, x1, 1104, x2)
+
+inst_172:
+// rs2_val == 2048, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x2;  op2val:0x800
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x2, 0x800, x1, 1112, x2)
+
+inst_173:
+// rs2_val == 1024, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x11;  op2val:0x400
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x11, 0x400, x1, 1120, x2)
+
+inst_174:
+// rs2_val == 512, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x5555555555555556;  op2val:0x200
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x5555555555555556, 0x200, x1, 1128, x2)
+
+inst_175:
+// rs2_val == 256, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x20000000001;  op2val:0x100
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x20000000001, 0x100, x1, 1136, x2)
+
+inst_176:
+// rs2_val == 128, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x21;  op2val:0x80
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x21, 0x80, x1, 1144, x2)
+
+inst_177:
+// rs2_val == 16, rs1_val == 268435456
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x10000000;  op2val:0x10
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x10000000, 0x10, x1, 1152, x2)
+
+inst_178:
+// rs2_val == 8, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0x8
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0x8, x1, 1160, x2)
+
+inst_179:
+// rs2_val == 4, rs1_val == 68719476736
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1000000000;  op2val:0x4
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1000000000, 0x4, x1, 1168, x2)
+
+inst_180:
+// rs1_val == 288230376151711744, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x400000000000000;  op2val:0xffffffbfffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x400000000000000, 0xffffffbfffffffff, x1, 1176, x2)
+
+inst_181:
+// rs1_val == 36028797018963968, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000000;  op2val:0x80000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x80000000000000, 0x80000000, x1, 1184, x2)
+
+inst_182:
+// rs1_val == 4503599627370496, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000000;  op2val:-0x40000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x10000000000000, -0x40000001, x1, 1192, x2)
+
+inst_183:
+// rs1_val == 562949953421312, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000;  op2val:-0x80000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2000000000000, -0x80000000001, x1, 1200, x2)
+
+inst_184:
+// rs1_val == 140737488355328, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800000000000;  op2val:-0xa
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800000000000, -0xa, x1, 1208, x2)
+
+inst_185:
+// rs1_val == 17592186044416, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x100000000000;  op2val:0x5555555555555555
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x100000000000, 0x5555555555555555, x1, 1216, x2)
+
+inst_186:
+// rs1_val == 8796093022208, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x80000000000;  op2val:0xe
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x80000000000, 0xe, x1, 1224, x2)
+
+inst_187:
+// rs1_val == 2199023255552, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x20000000000;  op2val:0x4
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x20000000000, 0x4, x1, 1232, x2)
+
+inst_188:
+// rs1_val == 1099511627776, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x10000000000;  op2val:0xdfffffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x10000000000, 0xdfffffffffffffff, x1, 1240, x2)
+
+inst_189:
+// rs1_val == 549755813888, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000;  op2val:-0x6
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000000, -0x6, x1, 1248, x2)
+
+inst_190:
+// rs1_val == 274877906944, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000;  op2val:-0xa
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000000000, -0xa, x1, 1256, x2)
+
+inst_191:
+// rs1_val == 137438953472, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000;  op2val:0x0
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2000000000, 0x0, x1, 1264, x2)
+
+inst_192:
+// rs1_val == 17179869184, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x400000000;  op2val:0x400000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x400000000, 0x400000, x1, 1272, x2)
+
+inst_193:
+// rs1_val == 8589934592, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x200000000;  op2val:0x800
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x200000000, 0x800, x1, 1280, x2)
+
+inst_194:
+// rs1_val == 4294967296, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x100000000;  op2val:0x10
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x100000000, 0x10, x1, 1288, x2)
+
+inst_195:
+// rs1_val == 2147483648, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x80000000;  op2val:-0x11
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x80000000, -0x11, x1, 1296, x2)
+
+inst_196:
+// rs1_val == 536870912, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x20000000;  op2val:0x80000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x20000000, 0x80000000000, x1, 1304, x2)
+
+inst_197:
+// rs1_val == 134217728, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000000;  op2val:0xfffffffffff7ffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000000, 0xfffffffffff7ffff, x1, 1312, x2)
+
+inst_198:
+// rs1_val == 67108864, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000000;  op2val:0xa
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000000, 0xa, x1, 1320, x2)
+
+inst_199:
+// rs1_val == 16777216, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1000000;  op2val:-0x100000000000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1000000, -0x100000000000001, x1, 1328, x2)
+
+inst_200:
+// rs1_val == 8388608, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800000;  op2val:0xfffbffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800000, 0xfffbffffffffffff, x1, 1336, x2)
+
+inst_201:
+// rs1_val == 4194304, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x400000;  op2val:0x20
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x400000, 0x20, x1, 1344, x2)
+
+inst_202:
+// rs1_val == 2097152, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x200000;  op2val:-0x81
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x200000, -0x81, x1, 1352, x2)
+
+inst_203:
+// rs1_val == 524288, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x80000;  op2val:-0x2000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x80000, -0x2000001, x1, 1360, x2)
+
+inst_204:
+// rs1_val == 262144, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x40000;  op2val:-0x11
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x40000, -0x11, x1, 1368, x2)
+
+inst_205:
+// rs1_val == 32768, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x8000;  op2val:0xfffffffbffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x8000, 0xfffffffbffffffff, x1, 1376, x2)
+
+inst_206:
+// rs1_val == 8192, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2000;  op2val:-0x801
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2000, -0x801, x1, 1384, x2)
+
+inst_207:
+// rs1_val == 4096, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x1000;  op2val:0x4000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x1000, 0x4000000, x1, 1392, x2)
+
+inst_208:
+// rs1_val == 2048, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x800;  op2val:0x5
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x800, 0x5, x1, 1400, x2)
+
+inst_209:
+// rs1_val == 1024, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x400;  op2val:-0x400001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x400, -0x400001, x1, 1408, x2)
+
+inst_210:
+// rs1_val == 512, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x200;  op2val:-0x1
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x200, -0x1, x1, 1416, x2)
+
+inst_211:
+// rs1_val == 256, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x100;  op2val:0x100000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x100, 0x100000000, x1, 1424, x2)
+
+inst_212:
+// rs1_val == 64, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x40;  op2val:0xfffffffffffffeff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x40, 0xfffffffffffffeff, x1, 1432, x2)
+
+inst_213:
+// rs1_val == 32, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x20;  op2val:0x40000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x20, 0x40000000, x1, 1440, x2)
+
+inst_214:
+// rs1_val == 4, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4;  op2val:-0x40000001
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4, -0x40000001, x1, 1448, x2)
+
+inst_215:
+// rs1_val == 2, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x10000000000000
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x2, 0x10000000000000, x1, 1456, x2)
+
+inst_216:
+// rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x1, 1464, x2)
+
+inst_217:
+// rs2_val == 13835058055282163711, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0x5;  op2val:0xbfffffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0x5, 0xbfffffffffffffff, x1, 1472, x2)
+
+inst_218:
+// rs2_val == 18446181123756130303, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:0x4000;  op2val:0xfffdffffffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, 0x4000, 0xfffdffffffffffff, x1, 1480, x2)
+
+inst_219:
+// rs2_val == 18446744004990074879, 
+// opcode: aes64ks2 ; op1:x10; op2:x11; dest:x12; op1val:-0xa;  op2val:0xffffffefffffffff
+TEST_RR_OP(aes64ks2, x12, x10, x11, 0x0000000000000000, -0xa, 0xffffffefffffffff, x1, 1488, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+
+signature_x9_0:
+    .fill 16*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 187*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S
new file mode 100644
index 000000000..daf30b85d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/andn-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the andn instruction of the RISC-V  extension for the andn covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",andn)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",andn)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",andn)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",andn)
+
+RVTEST_SIGBASE( x16,signature_x16_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x14, rs2==x14, rd==x1, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: andn ; op1:x14; op2:x14; dest:x1; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(andn, x1, x14, x14, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x16, 0, x12)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x2, rs2==x2, rd==x2, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: andn ; op1:x2; op2:x2; dest:x2; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(andn, x2, x2, x2, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x16, 8, x12)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x5, rs2==x3, rd==x26, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: andn ; op1:x5; op2:x3; dest:x26; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(andn, x26, x5, x3, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x16, 16, x12)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x0, rs2==x23, rd==x0, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: andn ; op1:x0; op2:x23; dest:x0; op1val:0x0;  op2val:0x4000000000000000
+TEST_RR_OP(andn, x0, x0, x23, 0x0000000000000000, 0x0, 0x4000000000000000, x16, 24, x12)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x29, rs2==x17, rd==x17, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: andn ; op1:x29; op2:x17; dest:x17; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(andn, x17, x29, x17, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x16, 32, x12)
+
+inst_5:
+// rs1==x13, rs2==x5, rd==x15, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: andn ; op1:x13; op2:x5; dest:x15; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(andn, x15, x13, x5, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x16, 40, x12)
+
+inst_6:
+// rs1==x6, rs2==x18, rd==x7, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: andn ; op1:x6; op2:x18; dest:x7; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(andn, x7, x6, x18, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x16, 48, x12)
+
+inst_7:
+// rs1==x18, rs2==x1, rd==x24, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: andn ; op1:x18; op2:x1; dest:x24; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(andn, x24, x18, x1, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x16, 56, x12)
+
+inst_8:
+// rs1==x24, rs2==x6, rd==x13, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: andn ; op1:x24; op2:x6; dest:x13; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(andn, x13, x24, x6, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x16, 64, x12)
+
+inst_9:
+// rs1==x21, rs2==x13, rd==x28, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: andn ; op1:x21; op2:x13; dest:x28; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(andn, x28, x21, x13, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x16, 72, x12)
+
+inst_10:
+// rs1==x11, rs2==x7, rd==x25, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: andn ; op1:x11; op2:x7; dest:x25; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(andn, x25, x11, x7, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x16, 80, x12)
+
+inst_11:
+// rs1==x3, rs2==x28, rd==x10, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: andn ; op1:x3; op2:x28; dest:x10; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(andn, x10, x3, x28, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x16, 88, x12)
+
+inst_12:
+// rs1==x10, rs2==x25, rd==x20, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: andn ; op1:x10; op2:x25; dest:x20; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(andn, x20, x10, x25, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x16, 96, x12)
+
+inst_13:
+// rs1==x30, rs2==x26, rd==x9, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: andn ; op1:x30; op2:x26; dest:x9; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(andn, x9, x30, x26, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x16, 104, x12)
+
+inst_14:
+// rs1==x19, rs2==x8, rd==x4, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: andn ; op1:x19; op2:x8; dest:x4; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(andn, x4, x19, x8, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x16, 112, x12)
+
+inst_15:
+// rs1==x9, rs2==x29, rd==x31, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: andn ; op1:x9; op2:x29; dest:x31; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(andn, x31, x9, x29, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x16, 120, x12)
+
+inst_16:
+// rs1==x25, rs2==x19, rd==x12, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: andn ; op1:x25; op2:x19; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(andn, x12, x25, x19, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x16, 128, x1)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_17:
+// rs1==x31, rs2==x9, rd==x19, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: andn ; op1:x31; op2:x9; dest:x19; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(andn, x19, x31, x9, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x2, 0, x1)
+
+inst_18:
+// rs1==x27, rs2==x24, rd==x29, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: andn ; op1:x27; op2:x24; dest:x29; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(andn, x29, x27, x24, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x2, 8, x1)
+
+inst_19:
+// rs1==x28, rs2==x20, rd==x30, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: andn ; op1:x28; op2:x20; dest:x30; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(andn, x30, x28, x20, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x2, 16, x1)
+
+inst_20:
+// rs1==x17, rs2==x10, rd==x3, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: andn ; op1:x17; op2:x10; dest:x3; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(andn, x3, x17, x10, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x2, 24, x1)
+
+inst_21:
+// rs1==x16, rs2==x11, rd==x23, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: andn ; op1:x16; op2:x11; dest:x23; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(andn, x23, x16, x11, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x2, 32, x1)
+
+inst_22:
+// rs1==x20, rs2==x12, rd==x14, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: andn ; op1:x20; op2:x12; dest:x14; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(andn, x14, x20, x12, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x2, 40, x1)
+
+inst_23:
+// rs1==x26, rs2==x21, rd==x27, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: andn ; op1:x26; op2:x21; dest:x27; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(andn, x27, x26, x21, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x2, 48, x1)
+
+inst_24:
+// rs1==x23, rs2==x16, rd==x6, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: andn ; op1:x23; op2:x16; dest:x6; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(andn, x6, x23, x16, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x2, 56, x1)
+
+inst_25:
+// rs1==x7, rs2==x15, rd==x18, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: andn ; op1:x7; op2:x15; dest:x18; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(andn, x18, x7, x15, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x2, 64, x1)
+
+inst_26:
+// rs1==x4, rs2==x31, rd==x21, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: andn ; op1:x4; op2:x31; dest:x21; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(andn, x21, x4, x31, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x2, 72, x1)
+
+inst_27:
+// rs1==x8, rs2==x22, rd==x16, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: andn ; op1:x8; op2:x22; dest:x16; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(andn, x16, x8, x22, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x2, 80, x1)
+
+inst_28:
+// rs1==x12, rs2==x30, rd==x11, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: andn ; op1:x12; op2:x30; dest:x11; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(andn, x11, x12, x30, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x2, 88, x3)
+
+inst_29:
+// rs1==x1, rs2==x4, rd==x5, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: andn ; op1:x1; op2:x4; dest:x5; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(andn, x5, x1, x4, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x2, 96, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_30:
+// rs1==x15, rs2==x0, rd==x22, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: andn ; op1:x15; op2:x0; dest:x22; op1val:0xb6de8bcfd96429c9;  op2val:0x0
+TEST_RR_OP(andn, x22, x15, x0, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x0, x1, 0, x3)
+
+inst_31:
+// rs1==x22, rs2==x27, rd==x8, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: andn ; op1:x22; op2:x27; dest:x8; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(andn, x8, x22, x27, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x1, 8, x3)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x1, 16, x3)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 24, x3)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 32, x3)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 40, x3)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 48, x3)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 56, x3)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 64, x3)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 72, x3)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 80, x3)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 88, x3)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 96, x3)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 104, x3)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 112, x3)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 120, x3)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 128, x3)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 136, x3)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 144, x3)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 152, x3)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 160, x3)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 168, x3)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 176, x3)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 184, x3)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 192, x3)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 200, x3)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 208, x3)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 216, x3)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 224, x3)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 232, x3)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 240, x3)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 248, x3)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 256, x3)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 264, x3)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 272, x3)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 280, x3)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 288, x3)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 296, x3)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 304, x3)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 312, x3)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 320, x3)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 328, x3)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 336, x3)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 344, x3)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 352, x3)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 360, x3)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 368, x3)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 376, x3)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 384, x3)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 392, x3)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 400, x3)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 408, x3)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 416, x3)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 424, x3)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 432, x3)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 440, x3)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 448, x3)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 456, x3)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 464, x3)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 472, x3)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 480, x3)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 488, x3)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 496, x3)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 504, x3)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 512, x3)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 520, x3)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 528, x3)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 536, x3)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 544, x3)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 552, x3)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 560, x3)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 568, x3)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 576, x3)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 584, x3)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 592, x3)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 600, x3)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 608, x3)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 616, x3)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 624, x3)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 632, x3)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 640, x3)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 648, x3)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 656, x3)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 664, x3)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 672, x3)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 680, x3)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 688, x3)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 696, x3)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 704, x3)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 712, x3)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 720, x3)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 728, x3)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 736, x3)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 744, x3)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 752, x3)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 760, x3)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 768, x3)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 776, x3)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 784, x3)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 792, x3)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 800, x3)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 808, x3)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 816, x3)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 824, x3)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 832, x3)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 840, x3)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 848, x3)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 856, x3)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 864, x3)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 872, x3)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 880, x3)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 888, x3)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 896, x3)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 904, x3)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 912, x3)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 920, x3)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 928, x3)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 936, x3)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 944, x3)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 952, x3)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 960, x3)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 968, x3)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 976, x3)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 984, x3)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 992, x3)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 1000, x3)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 1008, x3)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 1016, x3)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1024, x3)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1032, x3)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1040, x3)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1048, x3)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1056, x3)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1064, x3)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1072, x3)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1080, x3)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1088, x3)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1096, x3)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1104, x3)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1112, x3)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1120, x3)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1128, x3)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1136, x3)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1144, x3)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1152, x3)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1160, x3)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1168, x3)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1176, x3)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1184, x3)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1192, x3)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1200, x3)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1208, x3)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1216, x3)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1224, x3)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1232, x3)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1240, x3)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1248, x3)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1256, x3)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1264, x3)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1272, x3)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1280, x3)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1288, x3)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1296, x3)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1304, x3)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1312, x3)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1320, x3)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1328, x3)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1336, x3)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1344, x3)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1352, x3)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1360, x3)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1368, x3)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1376, x3)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1384, x3)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1392, x3)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1400, x3)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1408, x3)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1416, x3)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1424, x3)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1432, x3)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1440, x3)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1448, x3)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1456, x3)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1464, x3)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1472, x3)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1480, x3)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1488, x3)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1496, x3)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1504, x3)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1512, x3)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1520, x3)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1528, x3)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1536, x3)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1544, x3)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1552, x3)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1560, x3)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1568, x3)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1576, x3)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1584, x3)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1592, x3)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1600, x3)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1608, x3)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1616, x3)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1624, x3)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1632, x3)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1640, x3)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1648, x3)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1656, x3)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1664, x3)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1672, x3)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1680, x3)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1688, x3)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1696, x3)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1704, x3)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1712, x3)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1720, x3)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1728, x3)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1736, x3)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1744, x3)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1752, x3)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1760, x3)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1768, x3)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1776, x3)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1784, x3)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1792, x3)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1800, x3)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1808, x3)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1816, x3)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1824, x3)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1832, x3)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1840, x3)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1848, x3)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1856, x3)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1864, x3)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1872, x3)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1880, x3)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1888, x3)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1896, x3)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 1904, x3)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 1912, x3)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 1920, x3)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 1928, x3)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 1936, x3)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 1944, x3)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 1952, x3)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 1960, x3)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 1968, x3)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 1976, x3)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 1984, x3)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 1992, x3)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 2000, x3)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 2008, x3)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 2016, x3)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 2024, x3)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 2032, x3)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 2040, x3)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 0, x3)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 8, x3)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 16, x3)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 24, x3)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 32, x3)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 40, x3)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 48, x3)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 56, x3)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 64, x3)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 72, x3)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 80, x3)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 88, x3)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 96, x3)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 104, x3)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 112, x3)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 120, x3)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 128, x3)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 136, x3)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 144, x3)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 152, x3)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 160, x3)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 168, x3)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 176, x3)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 184, x3)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 192, x3)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 200, x3)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 208, x3)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 216, x3)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 224, x3)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 232, x3)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 240, x3)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 248, x3)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 256, x3)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 264, x3)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 272, x3)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 280, x3)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 288, x3)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 296, x3)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 304, x3)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 312, x3)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 320, x3)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 328, x3)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 336, x3)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 344, x3)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 352, x3)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 360, x3)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 368, x3)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 376, x3)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 384, x3)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 392, x3)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 400, x3)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 408, x3)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 416, x3)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 424, x3)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 432, x3)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 440, x3)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 448, x3)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 456, x3)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 464, x3)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 472, x3)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 480, x3)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 488, x3)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 496, x3)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 504, x3)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 512, x3)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 520, x3)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 528, x3)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 536, x3)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 544, x3)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 552, x3)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 560, x3)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 568, x3)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 576, x3)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 584, x3)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 592, x3)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 600, x3)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 608, x3)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 616, x3)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 624, x3)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 632, x3)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 640, x3)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 648, x3)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 656, x3)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 664, x3)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 672, x3)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 680, x3)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 688, x3)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 696, x3)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 704, x3)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 712, x3)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 720, x3)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 728, x3)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 736, x3)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 744, x3)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 752, x3)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 760, x3)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 768, x3)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 776, x3)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 784, x3)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 792, x3)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 800, x3)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 808, x3)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 816, x3)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 824, x3)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 832, x3)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 840, x3)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 848, x3)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 856, x3)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 864, x3)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 872, x3)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 880, x3)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 888, x3)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 896, x3)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 904, x3)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 912, x3)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 920, x3)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 928, x3)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 936, x3)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 944, x3)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 952, x3)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 960, x3)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 968, x3)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 976, x3)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 984, x3)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 992, x3)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 1000, x3)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 1008, x3)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 1016, x3)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1024, x3)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1032, x3)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1040, x3)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1048, x3)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1056, x3)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1064, x3)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1072, x3)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1080, x3)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1088, x3)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1096, x3)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1104, x3)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1112, x3)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1120, x3)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1128, x3)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1136, x3)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1144, x3)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1152, x3)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1160, x3)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1168, x3)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1176, x3)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1184, x3)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1192, x3)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1200, x3)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1208, x3)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1216, x3)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1224, x3)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1232, x3)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1240, x3)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1248, x3)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1256, x3)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1264, x3)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1272, x3)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1280, x3)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1288, x3)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1296, x3)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1304, x3)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1312, x3)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1320, x3)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1328, x3)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1336, x3)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1344, x3)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1352, x3)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1360, x3)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1368, x3)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1376, x3)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1384, x3)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1392, x3)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1400, x3)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1408, x3)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1416, x3)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1424, x3)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1432, x3)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1440, x3)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1448, x3)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1456, x3)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1464, x3)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1472, x3)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1480, x3)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1488, x3)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1496, x3)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1504, x3)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1512, x3)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1520, x3)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1528, x3)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1536, x3)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1544, x3)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1552, x3)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1560, x3)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1568, x3)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1576, x3)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1584, x3)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1592, x3)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1600, x3)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1608, x3)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1616, x3)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1624, x3)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1632, x3)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1640, x3)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1648, x3)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1656, x3)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1664, x3)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1672, x3)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1680, x3)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1688, x3)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1696, x3)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1704, x3)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1712, x3)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1720, x3)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1728, x3)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1736, x3)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1744, x3)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1752, x3)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1760, x3)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1768, x3)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1776, x3)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1784, x3)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1792, x3)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1800, x3)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1808, x3)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1816, x3)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1824, x3)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1832, x3)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1840, x3)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1848, x3)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1856, x3)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1864, x3)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1872, x3)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1880, x3)
+
+inst_522:
+// rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x1, 1888, x3)
+
+inst_523:
+// rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: andn ; op1:x10; op2:x11; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(andn, x12, x10, x11, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 1896, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x16_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x16_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 13*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 238*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S
new file mode 100644
index 000000000..e46e5636f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmul-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the clmul instruction of the RISC-V  extension for the clmul covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",clmul)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",clmul)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",clmul)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",clmul)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x16, rs2==x16, rd==x17, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: clmul ; op1:x16; op2:x16; dest:x17; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmul, x17, x16, x16, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x1, 0, x12)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x29, rs2==x29, rd==x29, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: clmul ; op1:x29; op2:x29; dest:x29; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(clmul, x29, x29, x29, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x1, 8, x12)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x6, rs2==x10, rd==x21, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: clmul ; op1:x6; op2:x10; dest:x21; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(clmul, x21, x6, x10, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x1, 16, x12)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x9, rs2==x8, rd==x9, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: clmul ; op1:x9; op2:x8; dest:x9; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(clmul, x9, x9, x8, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x1, 24, x12)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x30, rs2==x20, rd==x20, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: clmul ; op1:x30; op2:x20; dest:x20; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(clmul, x20, x30, x20, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x1, 32, x12)
+
+inst_5:
+// rs1==x27, rs2==x23, rd==x3, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: clmul ; op1:x27; op2:x23; dest:x3; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(clmul, x3, x27, x23, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x1, 40, x12)
+
+inst_6:
+// rs1==x26, rs2==x28, rd==x13, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: clmul ; op1:x26; op2:x28; dest:x13; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(clmul, x13, x26, x28, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x1, 48, x12)
+
+inst_7:
+// rs1==x2, rs2==x19, rd==x30, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: clmul ; op1:x2; op2:x19; dest:x30; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(clmul, x30, x2, x19, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x1, 56, x12)
+
+inst_8:
+// rs1==x15, rs2==x6, rd==x18, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: clmul ; op1:x15; op2:x6; dest:x18; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(clmul, x18, x15, x6, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x1, 64, x12)
+
+inst_9:
+// rs1==x5, rs2==x18, rd==x24, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: clmul ; op1:x5; op2:x18; dest:x24; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(clmul, x24, x5, x18, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x1, 72, x12)
+
+inst_10:
+// rs1==x20, rs2==x27, rd==x5, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: clmul ; op1:x20; op2:x27; dest:x5; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(clmul, x5, x20, x27, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x1, 80, x12)
+
+inst_11:
+// rs1==x18, rs2==x15, rd==x4, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: clmul ; op1:x18; op2:x15; dest:x4; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(clmul, x4, x18, x15, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x1, 88, x12)
+
+inst_12:
+// rs1==x8, rs2==x4, rd==x28, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: clmul ; op1:x8; op2:x4; dest:x28; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(clmul, x28, x8, x4, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x1, 96, x12)
+
+inst_13:
+// rs1==x24, rs2==x11, rd==x23, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: clmul ; op1:x24; op2:x11; dest:x23; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(clmul, x23, x24, x11, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x1, 104, x12)
+
+inst_14:
+// rs1==x28, rs2==x30, rd==x8, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: clmul ; op1:x28; op2:x30; dest:x8; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(clmul, x8, x28, x30, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x1, 112, x12)
+
+inst_15:
+// rs1==x22, rs2==x3, rd==x31, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: clmul ; op1:x22; op2:x3; dest:x31; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(clmul, x31, x22, x3, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x1, 120, x12)
+
+inst_16:
+// rs1==x10, rs2==x31, rd==x26, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: clmul ; op1:x10; op2:x31; dest:x26; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(clmul, x26, x10, x31, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x1, 128, x12)
+
+inst_17:
+// rs1==x7, rs2==x24, rd==x19, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: clmul ; op1:x7; op2:x24; dest:x19; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(clmul, x19, x7, x24, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x1, 136, x12)
+
+inst_18:
+// rs1==x0, rs2==x2, rd==x14, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: clmul ; op1:x0; op2:x2; dest:x14; op1val:0x0;  op2val:0x3b0b800000000000
+TEST_RR_OP(clmul, x14, x0, x2, 0x0000000000000000, 0x0, 0x3b0b800000000000, x1, 144, x18)
+RVTEST_SIGBASE( x8,signature_x8_0)
+
+inst_19:
+// rs1==x11, rs2==x21, rd==x7, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: clmul ; op1:x11; op2:x21; dest:x7; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(clmul, x7, x11, x21, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x8, 0, x18)
+
+inst_20:
+// rs1==x14, rs2==x22, rd==x2, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: clmul ; op1:x14; op2:x22; dest:x2; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(clmul, x2, x14, x22, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x8, 8, x18)
+
+inst_21:
+// rs1==x23, rs2==x5, rd==x11, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: clmul ; op1:x23; op2:x5; dest:x11; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(clmul, x11, x23, x5, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x8, 16, x18)
+
+inst_22:
+// rs1==x3, rs2==x26, rd==x22, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: clmul ; op1:x3; op2:x26; dest:x22; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(clmul, x22, x3, x26, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x8, 24, x18)
+
+inst_23:
+// rs1==x1, rs2==x17, rd==x25, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: clmul ; op1:x1; op2:x17; dest:x25; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(clmul, x25, x1, x17, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x8, 32, x18)
+
+inst_24:
+// rs1==x13, rs2==x9, rd==x0, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: clmul ; op1:x13; op2:x9; dest:x0; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(clmul, x0, x13, x9, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x8, 40, x18)
+
+inst_25:
+// rs1==x19, rs2==x0, rd==x1, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: clmul ; op1:x19; op2:x0; dest:x1; op1val:0x2466b4600d42ea01;  op2val:0x0
+TEST_RR_OP(clmul, x1, x19, x0, 0x0000000000000000, 0x2466b4600d42ea01, 0x0, x8, 48, x18)
+
+inst_26:
+// rs1==x31, rs2==x25, rd==x12, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: clmul ; op1:x31; op2:x25; dest:x12; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(clmul, x12, x31, x25, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x8, 56, x18)
+
+inst_27:
+// rs1==x21, rs2==x1, rd==x15, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: clmul ; op1:x21; op2:x1; dest:x15; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(clmul, x15, x21, x1, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x8, 64, x18)
+
+inst_28:
+// rs1==x17, rs2==x7, rd==x10, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: clmul ; op1:x17; op2:x7; dest:x10; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(clmul, x10, x17, x7, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x8, 72, x18)
+
+inst_29:
+// rs1==x25, rs2==x12, rd==x6, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: clmul ; op1:x25; op2:x12; dest:x6; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(clmul, x6, x25, x12, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x8, 80, x18)
+
+inst_30:
+// rs1==x4, rs2==x14, rd==x27, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: clmul ; op1:x4; op2:x14; dest:x27; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(clmul, x27, x4, x14, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x8, 88, x18)
+
+inst_31:
+// rs1==x12, rs2==x13, rd==x16, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: clmul ; op1:x12; op2:x13; dest:x16; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(clmul, x16, x12, x13, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x8, 96, x18)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x8, 104, x18)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x8, 112, x18)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x8, 120, x18)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x8, 128, x18)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x8, 136, x18)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x8, 144, x18)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x8, 152, x18)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x8, 160, x18)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x8, 168, x18)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x8, 176, x18)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x8, 184, x18)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x8, 192, x18)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x8, 200, x18)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x8, 208, x18)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x8, 216, x18)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x8, 224, x18)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x8, 232, x18)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x8, 240, x18)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x8, 248, x18)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x8, 256, x18)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x8, 264, x18)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x8, 272, x18)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x8, 280, x18)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x8, 288, x18)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x8, 296, x18)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x8, 304, x18)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x8, 312, x18)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x8, 320, x18)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x8, 328, x18)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x8, 336, x18)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x8, 344, x18)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x8, 352, x18)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x8, 360, x18)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x8, 368, x18)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x8, 376, x18)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x8, 384, x18)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x8, 392, x18)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x8, 400, x18)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x8, 408, x18)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x8, 416, x18)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x8, 424, x18)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x8, 432, x18)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x8, 440, x18)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x8, 448, x18)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x8, 456, x18)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x8, 464, x18)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x8, 472, x18)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x8, 480, x18)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x8, 488, x18)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x8, 496, x18)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x8, 504, x18)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x8, 512, x18)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x8, 520, x18)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x8, 528, x18)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x8, 536, x18)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x8, 544, x18)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x8, 552, x18)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x8, 560, x18)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x8, 568, x18)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x8, 576, x18)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x8, 584, x18)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x8, 592, x18)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x8, 600, x18)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x8, 608, x18)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x8, 616, x18)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x8, 624, x18)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x8, 632, x18)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x8, 640, x18)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x8, 648, x18)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x8, 656, x18)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x8, 664, x18)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x8, 672, x18)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x8, 680, x18)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x8, 688, x18)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x8, 696, x18)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x8, 704, x18)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x8, 712, x18)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x8, 720, x18)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x8, 728, x18)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x8, 736, x18)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x8, 744, x18)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x8, 752, x18)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x8, 760, x18)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x8, 768, x18)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x8, 776, x18)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x8, 784, x18)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x8, 792, x18)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x8, 800, x18)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x8, 808, x18)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x8, 816, x18)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x8, 824, x18)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x8, 832, x18)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x8, 840, x18)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x8, 848, x18)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x8, 856, x18)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x8, 864, x18)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x8, 872, x18)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x8, 880, x18)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x8, 888, x18)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x8, 896, x18)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x8, 904, x18)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x8, 912, x18)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x8, 920, x18)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x8, 928, x18)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x8, 936, x18)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x8, 944, x18)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x8, 952, x18)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x8, 960, x18)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x8, 968, x18)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x8, 976, x18)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x8, 984, x18)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x8, 992, x18)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x8, 1000, x18)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x8, 1008, x18)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x8, 1016, x18)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x8, 1024, x18)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x8, 1032, x18)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x8, 1040, x18)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x8, 1048, x18)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x8, 1056, x18)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x8, 1064, x18)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x8, 1072, x18)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x8, 1080, x18)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x8, 1088, x18)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x8, 1096, x18)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x8, 1104, x18)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x8, 1112, x18)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x8, 1120, x18)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x8, 1128, x18)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x8, 1136, x18)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x8, 1144, x18)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x8, 1152, x18)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x8, 1160, x18)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x8, 1168, x18)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x8, 1176, x18)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x8, 1184, x18)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x8, 1192, x18)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x8, 1200, x18)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x8, 1208, x18)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x8, 1216, x18)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x8, 1224, x18)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x8, 1232, x18)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x8, 1240, x18)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x8, 1248, x18)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x8, 1256, x18)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x8, 1264, x18)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x8, 1272, x18)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x8, 1280, x18)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x8, 1288, x18)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x8, 1296, x18)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x8, 1304, x18)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x8, 1312, x18)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x8, 1320, x18)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x8, 1328, x18)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x8, 1336, x18)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x8, 1344, x18)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x8, 1352, x18)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x8, 1360, x18)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x8, 1368, x18)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x8, 1376, x18)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x8, 1384, x18)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x8, 1392, x18)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x8, 1400, x18)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x8, 1408, x18)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x8, 1416, x18)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x8, 1424, x18)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x8, 1432, x18)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x8, 1440, x18)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x8, 1448, x18)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x8, 1456, x18)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x8, 1464, x18)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x8, 1472, x18)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x8, 1480, x18)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x8, 1488, x18)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x8, 1496, x18)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x8, 1504, x18)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x8, 1512, x18)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x8, 1520, x18)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x8, 1528, x18)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x8, 1536, x18)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x8, 1544, x18)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x8, 1552, x18)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x8, 1560, x18)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x8, 1568, x18)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x8, 1576, x18)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x8, 1584, x18)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x8, 1592, x18)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x8, 1600, x18)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x8, 1608, x18)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x8, 1616, x18)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x8, 1624, x18)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x8, 1632, x18)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x8, 1640, x18)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x8, 1648, x18)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x8, 1656, x18)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x8, 1664, x18)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x8, 1672, x18)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x8, 1680, x18)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x8, 1688, x18)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x8, 1696, x18)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x8, 1704, x18)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x8, 1712, x18)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x8, 1720, x18)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x8, 1728, x18)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x8, 1736, x18)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x8, 1744, x18)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x8, 1752, x18)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x8, 1760, x18)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x8, 1768, x18)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x8, 1776, x18)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x8, 1784, x18)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x8, 1792, x18)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x8, 1800, x18)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x8, 1808, x18)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x8, 1816, x18)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x8, 1824, x18)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x8, 1832, x18)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x8, 1840, x18)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x8, 1848, x18)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x8, 1856, x18)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x8, 1864, x18)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x8, 1872, x18)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x8, 1880, x18)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x8, 1888, x18)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x8, 1896, x18)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x8, 1904, x18)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x8, 1912, x18)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x8, 1920, x18)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x8, 1928, x18)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x8, 1936, x18)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x8, 1944, x18)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x8, 1952, x18)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x8, 1960, x18)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x8, 1968, x18)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x8, 1976, x18)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x8, 1984, x18)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x8, 1992, x18)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x8, 2000, x18)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x8, 2008, x18)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x8, 2016, x18)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x8, 2024, x18)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x8, 2032, x18)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x8, 2040, x18)
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x8, 0, x18)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x8, 8, x18)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x8, 16, x18)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x8, 24, x18)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x8, 32, x18)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x8, 40, x18)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x8, 48, x18)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x8, 56, x18)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x8, 64, x18)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x8, 72, x18)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x8, 80, x18)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x8, 88, x18)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x8, 96, x18)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x8, 104, x18)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x8, 112, x18)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x8, 120, x18)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x8, 128, x18)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x8, 136, x18)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x8, 144, x18)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x8, 152, x18)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x8, 160, x18)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x8, 168, x18)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x8, 176, x18)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x8, 184, x18)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x8, 192, x18)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x8, 200, x18)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x8, 208, x18)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x8, 216, x18)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x8, 224, x18)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x8, 232, x18)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x8, 240, x18)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x8, 248, x18)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x8, 256, x18)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x8, 264, x18)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x8, 272, x18)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x8, 280, x18)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x8, 288, x18)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x8, 296, x18)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x8, 304, x18)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x8, 312, x18)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x8, 320, x18)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x8, 328, x18)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x8, 336, x18)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x8, 344, x18)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x8, 352, x18)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x8, 360, x18)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x8, 368, x18)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x8, 376, x18)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x8, 384, x18)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x8, 392, x18)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x8, 400, x18)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x8, 408, x18)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x8, 416, x18)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x8, 424, x18)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x8, 432, x18)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x8, 440, x18)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x8, 448, x18)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x8, 456, x18)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x8, 464, x18)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x8, 472, x18)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x8, 480, x18)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x8, 488, x18)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x8, 496, x18)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x8, 504, x18)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x8, 512, x18)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x8, 520, x18)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x8, 528, x18)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x8, 536, x18)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x8, 544, x18)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x8, 552, x18)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x8, 560, x18)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x8, 568, x18)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x8, 576, x18)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x8, 584, x18)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x8, 592, x18)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x8, 600, x18)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x8, 608, x18)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x8, 616, x18)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x8, 624, x18)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x8, 632, x18)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x8, 640, x18)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x8, 648, x18)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x8, 656, x18)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x8, 664, x18)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x8, 672, x18)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x8, 680, x18)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x8, 688, x18)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x8, 696, x18)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x8, 704, x18)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x8, 712, x18)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x8, 720, x18)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x8, 728, x18)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x8, 736, x18)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x8, 744, x18)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x8, 752, x18)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x8, 760, x18)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x8, 768, x18)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x8, 776, x18)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x8, 784, x18)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x8, 792, x18)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x8, 800, x18)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x8, 808, x18)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x8, 816, x18)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x8, 824, x18)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x8, 832, x18)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x8, 840, x18)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x8, 848, x18)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x8, 856, x18)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x8, 864, x18)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x8, 872, x18)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x8, 880, x18)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x8, 888, x18)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x8, 896, x18)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x8, 904, x18)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x8, 912, x18)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x8, 920, x18)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x8, 928, x18)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x8, 936, x18)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x8, 944, x18)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x8, 952, x18)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x8, 960, x18)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x8, 968, x18)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x8, 976, x18)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x8, 984, x18)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x8, 992, x18)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x8, 1000, x18)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x8, 1008, x18)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x8, 1016, x18)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x8, 1024, x18)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x8, 1032, x18)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x8, 1040, x18)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x8, 1048, x18)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x8, 1056, x18)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x8, 1064, x18)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x8, 1072, x18)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x8, 1080, x18)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x8, 1088, x18)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x8, 1096, x18)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x8, 1104, x18)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x8, 1112, x18)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x8, 1120, x18)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x8, 1128, x18)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x8, 1136, x18)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x8, 1144, x18)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x8, 1152, x18)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x8, 1160, x18)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x8, 1168, x18)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x8, 1176, x18)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x8, 1184, x18)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x8, 1192, x18)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x8, 1200, x18)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x8, 1208, x18)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x8, 1216, x18)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x8, 1224, x18)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x8, 1232, x18)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x8, 1240, x18)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x8, 1248, x18)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x8, 1256, x18)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x8, 1264, x18)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x8, 1272, x18)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x8, 1280, x18)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x8, 1288, x18)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x8, 1296, x18)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x8, 1304, x18)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x8, 1312, x18)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x8, 1320, x18)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x8, 1328, x18)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x8, 1336, x18)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x8, 1344, x18)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x8, 1352, x18)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x8, 1360, x18)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x8, 1368, x18)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x8, 1376, x18)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x8, 1384, x18)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x8, 1392, x18)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x8, 1400, x18)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x8, 1408, x18)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x8, 1416, x18)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x8, 1424, x18)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x8, 1432, x18)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x8, 1440, x18)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x8, 1448, x18)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x8, 1456, x18)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x8, 1464, x18)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x8, 1472, x18)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x8, 1480, x18)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x8, 1488, x18)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x8, 1496, x18)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x8, 1504, x18)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x8, 1512, x18)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x8, 1520, x18)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x8, 1528, x18)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x8, 1536, x18)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x8, 1544, x18)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x8, 1552, x18)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x8, 1560, x18)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x8, 1568, x18)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x8, 1576, x18)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x8, 1584, x18)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x8, 1592, x18)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x8, 1600, x18)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x8, 1608, x18)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x8, 1616, x18)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x8, 1624, x18)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x8, 1632, x18)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x8, 1640, x18)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x8, 1648, x18)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x8, 1656, x18)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x8, 1664, x18)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x8, 1672, x18)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x8, 1680, x18)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x8, 1688, x18)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x8, 1696, x18)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x8, 1704, x18)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x8, 1712, x18)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x8, 1720, x18)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x8, 1728, x18)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x8, 1736, x18)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x8, 1744, x18)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x8, 1752, x18)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x8, 1760, x18)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x8, 1768, x18)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x8, 1776, x18)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x8, 1784, x18)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x8, 1792, x18)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x8, 1800, x18)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x8, 1808, x18)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x8, 1816, x18)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x8, 1824, x18)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x8, 1832, x18)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x8, 1840, x18)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x8, 1848, x18)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x8, 1856, x18)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x8, 1864, x18)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x8, 1872, x18)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x8, 1880, x18)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x8, 1888, x18)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x8, 1896, x18)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x8, 1904, x18)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x8, 1912, x18)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x8, 1920, x18)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x8, 1928, x18)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x8, 1936, x18)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x8, 1944, x18)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x8, 1952, x18)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x8, 1960, x18)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x8, 1968, x18)
+
+inst_522:
+// rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x8, 1976, x18)
+
+inst_523:
+// rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x8, 1984, x18)
+
+inst_524:
+// rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: clmul ; op1:x10; op2:x11; dest:x12; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(clmul, x12, x10, x11, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x8, 1992, x18)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 250*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S
new file mode 100644
index 000000000..aac8a1997
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/clmulh-01.S
@@ -0,0 +1,2716 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the clmulh instruction of the RISC-V  extension for the clmulh covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",clmulh)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",clmulh)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",clmulh)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",clmulh)
+
+RVTEST_SIGBASE( x18,signature_x18_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x14, rs2==x14, rd==x1, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: clmulh ; op1:x14; op2:x14; dest:x1; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmulh, x1, x14, x14, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x18, 0, x3)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x24, rs2==x24, rd==x24, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: clmulh ; op1:x24; op2:x24; dest:x24; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(clmulh, x24, x24, x24, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x18, 8, x3)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x4, rs2==x0, rd==x12, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: clmulh ; op1:x4; op2:x0; dest:x12; op1val:0x6f061d6dc38671b6;  op2val:0x0
+TEST_RR_OP(clmulh, x12, x4, x0, 0x0000000000000000, 0x6f061d6dc38671b6, 0x0, x18, 16, x3)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x8, rs2==x17, rd==x8, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: clmulh ; op1:x8; op2:x17; dest:x8; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(clmulh, x8, x8, x17, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x18, 24, x3)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x0, rs2==x25, rd==x25, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: clmulh ; op1:x0; op2:x25; dest:x25; op1val:0x0;  op2val:0xa000000000000000
+TEST_RR_OP(clmulh, x25, x0, x25, 0x0000000000000000, 0x0, 0xa000000000000000, x18, 32, x3)
+
+inst_5:
+// rs1==x11, rs2==x9, rd==x21, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: clmulh ; op1:x11; op2:x9; dest:x21; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(clmulh, x21, x11, x9, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x18, 40, x3)
+
+inst_6:
+// rs1==x5, rs2==x29, rd==x7, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: clmulh ; op1:x5; op2:x29; dest:x7; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(clmulh, x7, x5, x29, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x18, 48, x3)
+
+inst_7:
+// rs1==x13, rs2==x30, rd==x20, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: clmulh ; op1:x13; op2:x30; dest:x20; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(clmulh, x20, x13, x30, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x18, 56, x3)
+
+inst_8:
+// rs1==x21, rs2==x15, rd==x31, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: clmulh ; op1:x21; op2:x15; dest:x31; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(clmulh, x31, x21, x15, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x18, 64, x3)
+
+inst_9:
+// rs1==x6, rs2==x26, rd==x16, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: clmulh ; op1:x6; op2:x26; dest:x16; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(clmulh, x16, x6, x26, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x18, 72, x3)
+
+inst_10:
+// rs1==x10, rs2==x2, rd==x30, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: clmulh ; op1:x10; op2:x2; dest:x30; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(clmulh, x30, x10, x2, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x18, 80, x3)
+
+inst_11:
+// rs1==x1, rs2==x12, rd==x17, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: clmulh ; op1:x1; op2:x12; dest:x17; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(clmulh, x17, x1, x12, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x18, 88, x3)
+
+inst_12:
+// rs1==x15, rs2==x27, rd==x26, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: clmulh ; op1:x15; op2:x27; dest:x26; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(clmulh, x26, x15, x27, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x18, 96, x3)
+
+inst_13:
+// rs1==x28, rs2==x16, rd==x22, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: clmulh ; op1:x28; op2:x16; dest:x22; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(clmulh, x22, x28, x16, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x18, 104, x3)
+
+inst_14:
+// rs1==x26, rs2==x21, rd==x10, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: clmulh ; op1:x26; op2:x21; dest:x10; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(clmulh, x10, x26, x21, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x18, 112, x14)
+
+inst_15:
+// rs1==x7, rs2==x28, rd==x9, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: clmulh ; op1:x7; op2:x28; dest:x9; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(clmulh, x9, x7, x28, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x18, 120, x14)
+
+inst_16:
+// rs1==x12, rs2==x20, rd==x3, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: clmulh ; op1:x12; op2:x20; dest:x3; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(clmulh, x3, x12, x20, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x18, 128, x14)
+RVTEST_SIGBASE( x21,signature_x21_0)
+
+inst_17:
+// rs1==x23, rs2==x18, rd==x19, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: clmulh ; op1:x23; op2:x18; dest:x19; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(clmulh, x19, x23, x18, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x21, 0, x14)
+
+inst_18:
+// rs1==x22, rs2==x8, rd==x13, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: clmulh ; op1:x22; op2:x8; dest:x13; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(clmulh, x13, x22, x8, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x21, 8, x14)
+
+inst_19:
+// rs1==x19, rs2==x5, rd==x6, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: clmulh ; op1:x19; op2:x5; dest:x6; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(clmulh, x6, x19, x5, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x21, 16, x14)
+
+inst_20:
+// rs1==x18, rs2==x11, rd==x15, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: clmulh ; op1:x18; op2:x11; dest:x15; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(clmulh, x15, x18, x11, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x21, 24, x14)
+
+inst_21:
+// rs1==x3, rs2==x6, rd==x23, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: clmulh ; op1:x3; op2:x6; dest:x23; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(clmulh, x23, x3, x6, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x21, 32, x14)
+
+inst_22:
+// rs1==x29, rs2==x22, rd==x2, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: clmulh ; op1:x29; op2:x22; dest:x2; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(clmulh, x2, x29, x22, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x21, 40, x14)
+
+inst_23:
+// rs1==x16, rs2==x19, rd==x4, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: clmulh ; op1:x16; op2:x19; dest:x4; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(clmulh, x4, x16, x19, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x21, 48, x14)
+
+inst_24:
+// rs1==x20, rs2==x31, rd==x27, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: clmulh ; op1:x20; op2:x31; dest:x27; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(clmulh, x27, x20, x31, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x21, 56, x14)
+
+inst_25:
+// rs1==x25, rs2==x7, rd==x5, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: clmulh ; op1:x25; op2:x7; dest:x5; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(clmulh, x5, x25, x7, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x21, 64, x14)
+
+inst_26:
+// rs1==x30, rs2==x1, rd==x18, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: clmulh ; op1:x30; op2:x1; dest:x18; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(clmulh, x18, x30, x1, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x21, 72, x14)
+
+inst_27:
+// rs1==x9, rs2==x13, rd==x14, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: clmulh ; op1:x9; op2:x13; dest:x14; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(clmulh, x14, x9, x13, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x21, 80, x5)
+
+inst_28:
+// rs1==x17, rs2==x4, rd==x11, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: clmulh ; op1:x17; op2:x4; dest:x11; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(clmulh, x11, x17, x4, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x21, 88, x5)
+
+inst_29:
+// rs1==x2, rs2==x23, rd==x28, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: clmulh ; op1:x2; op2:x23; dest:x28; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(clmulh, x28, x2, x23, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x21, 96, x5)
+
+inst_30:
+// rs1==x27, rs2==x10, rd==x0, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: clmulh ; op1:x27; op2:x10; dest:x0; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(clmulh, x0, x27, x10, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x21, 104, x5)
+
+inst_31:
+// rs1==x31, rs2==x3, rd==x29, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: clmulh ; op1:x31; op2:x3; dest:x29; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(clmulh, x29, x31, x3, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x21, 112, x5)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x21, 120, x5)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 0, x5)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 8, x5)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 16, x5)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 24, x5)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 32, x5)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 40, x5)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 48, x5)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 56, x5)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 64, x5)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 72, x5)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 80, x5)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 88, x5)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 96, x5)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 104, x5)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 112, x5)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 120, x5)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 128, x5)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 136, x5)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 144, x5)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 152, x5)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 160, x5)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 168, x5)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 176, x5)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 184, x5)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 192, x5)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 200, x5)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 208, x5)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 216, x5)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 224, x5)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 232, x5)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 240, x5)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 248, x5)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 256, x5)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 264, x5)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 272, x5)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 280, x5)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 288, x5)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 296, x5)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 304, x5)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 312, x5)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 320, x5)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 328, x5)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 336, x5)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 344, x5)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 352, x5)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 360, x5)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 368, x5)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 376, x5)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 384, x5)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 392, x5)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 400, x5)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 408, x5)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 416, x5)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 424, x5)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 432, x5)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 440, x5)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 448, x5)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 456, x5)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 464, x5)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 472, x5)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 480, x5)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 488, x5)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 496, x5)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 504, x5)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 512, x5)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 520, x5)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 528, x5)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 536, x5)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 544, x5)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 552, x5)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 560, x5)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 568, x5)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 576, x5)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 584, x5)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 592, x5)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 600, x5)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 608, x5)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 616, x5)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 624, x5)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 632, x5)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 640, x5)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 648, x5)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 656, x5)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 664, x5)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 672, x5)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 680, x5)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 688, x5)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 696, x5)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 704, x5)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 712, x5)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 720, x5)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 728, x5)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 736, x5)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 744, x5)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 752, x5)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 760, x5)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 768, x5)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 776, x5)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 784, x5)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 792, x5)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 800, x5)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 808, x5)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 816, x5)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 824, x5)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 832, x5)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 840, x5)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 848, x5)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 856, x5)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 864, x5)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 872, x5)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 880, x5)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 888, x5)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 896, x5)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 904, x5)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 912, x5)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 920, x5)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 928, x5)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 936, x5)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 944, x5)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 952, x5)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 960, x5)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 968, x5)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 976, x5)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 984, x5)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 992, x5)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1000, x5)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1008, x5)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1016, x5)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1024, x5)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1032, x5)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1040, x5)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1048, x5)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1056, x5)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1064, x5)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1072, x5)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1080, x5)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1088, x5)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1096, x5)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1104, x5)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1112, x5)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1120, x5)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1128, x5)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1136, x5)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1144, x5)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1152, x5)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1160, x5)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1168, x5)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1176, x5)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1184, x5)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1192, x5)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1200, x5)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1208, x5)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1216, x5)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1224, x5)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1232, x5)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1240, x5)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1248, x5)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1256, x5)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1264, x5)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1272, x5)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1280, x5)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1288, x5)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1296, x5)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1304, x5)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1312, x5)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1320, x5)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1328, x5)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1336, x5)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1344, x5)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1352, x5)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1360, x5)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1368, x5)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1376, x5)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1384, x5)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1392, x5)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1400, x5)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1408, x5)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1416, x5)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1424, x5)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1432, x5)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1440, x5)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1448, x5)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1456, x5)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1464, x5)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1472, x5)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1480, x5)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1488, x5)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1496, x5)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1504, x5)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1512, x5)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1520, x5)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1528, x5)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1536, x5)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1544, x5)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1552, x5)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1560, x5)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1568, x5)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1576, x5)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1584, x5)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1592, x5)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1600, x5)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1608, x5)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1616, x5)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1624, x5)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1632, x5)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1640, x5)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1648, x5)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1656, x5)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1664, x5)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1672, x5)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1680, x5)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1688, x5)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1696, x5)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1704, x5)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1712, x5)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1720, x5)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1728, x5)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1736, x5)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1744, x5)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1752, x5)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1760, x5)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1768, x5)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1776, x5)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1784, x5)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1792, x5)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1800, x5)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1808, x5)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1816, x5)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1824, x5)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1832, x5)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1840, x5)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1848, x5)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1856, x5)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1864, x5)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1872, x5)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 1880, x5)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 1888, x5)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 1896, x5)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 1904, x5)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 1912, x5)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 1920, x5)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 1928, x5)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 1936, x5)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 1944, x5)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 1952, x5)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 1960, x5)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 1968, x5)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 1976, x5)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 1984, x5)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 1992, x5)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 2000, x5)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 2008, x5)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 2016, x5)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 2024, x5)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 2032, x5)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 2040, x5)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 0, x5)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 8, x5)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 16, x5)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 24, x5)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 32, x5)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 40, x5)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 48, x5)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 56, x5)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 64, x5)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 72, x5)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 80, x5)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 88, x5)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 96, x5)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 104, x5)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 112, x5)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 120, x5)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 128, x5)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 136, x5)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 144, x5)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 152, x5)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 160, x5)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 168, x5)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 176, x5)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 184, x5)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 192, x5)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 200, x5)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 208, x5)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 216, x5)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 224, x5)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 232, x5)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 240, x5)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 248, x5)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 256, x5)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 264, x5)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 272, x5)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 280, x5)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 288, x5)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 296, x5)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 304, x5)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 312, x5)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 320, x5)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 328, x5)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 336, x5)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 344, x5)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 352, x5)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 360, x5)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 368, x5)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 376, x5)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 384, x5)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 392, x5)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 400, x5)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 408, x5)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 416, x5)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 424, x5)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 432, x5)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 440, x5)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 448, x5)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 456, x5)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 464, x5)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 472, x5)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 480, x5)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 488, x5)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 496, x5)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 504, x5)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 512, x5)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 520, x5)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 528, x5)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 536, x5)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 544, x5)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 552, x5)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 560, x5)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 568, x5)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 576, x5)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 584, x5)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 592, x5)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 600, x5)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 608, x5)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 616, x5)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 624, x5)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 632, x5)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 640, x5)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 648, x5)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 656, x5)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 664, x5)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 672, x5)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 680, x5)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 688, x5)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 696, x5)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 704, x5)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 712, x5)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 720, x5)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 728, x5)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 736, x5)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 744, x5)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 752, x5)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 760, x5)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 768, x5)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 776, x5)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 784, x5)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 792, x5)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 800, x5)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 808, x5)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 816, x5)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 824, x5)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 832, x5)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 840, x5)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 848, x5)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 856, x5)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 864, x5)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 872, x5)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 880, x5)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 888, x5)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 896, x5)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 904, x5)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 912, x5)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 920, x5)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 928, x5)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 936, x5)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 944, x5)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 952, x5)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 960, x5)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 968, x5)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 976, x5)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 984, x5)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 992, x5)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1000, x5)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1008, x5)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1016, x5)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1024, x5)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1032, x5)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1040, x5)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1048, x5)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1056, x5)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1064, x5)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1072, x5)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1080, x5)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1088, x5)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1096, x5)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1104, x5)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1112, x5)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1120, x5)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1128, x5)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1136, x5)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1144, x5)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1152, x5)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1160, x5)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1168, x5)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1176, x5)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1184, x5)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1192, x5)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1200, x5)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1208, x5)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1216, x5)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1224, x5)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1232, x5)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1240, x5)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1248, x5)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1256, x5)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1264, x5)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1272, x5)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1280, x5)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1288, x5)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1296, x5)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1304, x5)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1312, x5)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1320, x5)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1328, x5)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1336, x5)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1344, x5)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1352, x5)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1360, x5)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1368, x5)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1376, x5)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1384, x5)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1392, x5)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1400, x5)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1408, x5)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1416, x5)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1424, x5)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1432, x5)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1440, x5)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1448, x5)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1456, x5)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1464, x5)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1472, x5)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1480, x5)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1488, x5)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1496, x5)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1504, x5)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1512, x5)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1520, x5)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1528, x5)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1536, x5)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1544, x5)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1552, x5)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1560, x5)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1568, x5)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1576, x5)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1584, x5)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1592, x5)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1600, x5)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1608, x5)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1616, x5)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1624, x5)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1632, x5)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1640, x5)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1648, x5)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1656, x5)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1664, x5)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1672, x5)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1680, x5)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1688, x5)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1696, x5)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1704, x5)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1712, x5)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1720, x5)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1728, x5)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1736, x5)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1744, x5)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1752, x5)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1760, x5)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1768, x5)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1776, x5)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1784, x5)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1792, x5)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1800, x5)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1808, x5)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1816, x5)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1824, x5)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1832, x5)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1840, x5)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1848, x5)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1856, x5)
+
+inst_522:
+// rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x1, 1864, x5)
+
+inst_523:
+// rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x1, 1872, x5)
+
+inst_524:
+// rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: clmulh ; op1:x10; op2:x11; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(clmulh, x12, x10, x11, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 1880, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x18_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x18_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+
+signature_x21_0:
+    .fill 16*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 236*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S
new file mode 100644
index 000000000..2c76117d3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/orn-01.S
@@ -0,0 +1,2716 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the orn instruction of the RISC-V  extension for the orn covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",orn)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",orn)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",orn)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",orn)
+
+RVTEST_SIGBASE( x10,signature_x10_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x11, rs2==x11, rd==x16, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: orn ; op1:x11; op2:x11; dest:x16; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(orn, x16, x11, x11, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x10, 0, x23)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x8, rs2==x8, rd==x8, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: orn ; op1:x8; op2:x8; dest:x8; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(orn, x8, x8, x8, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x10, 8, x23)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x27, rs2==x21, rd==x15, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: orn ; op1:x27; op2:x21; dest:x15; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(orn, x15, x27, x21, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x10, 16, x23)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x6, rs2==x31, rd==x6, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: orn ; op1:x6; op2:x31; dest:x6; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(orn, x6, x6, x31, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x10, 24, x23)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x5, rs2==x14, rd==x14, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: orn ; op1:x5; op2:x14; dest:x14; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(orn, x14, x5, x14, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x10, 32, x23)
+
+inst_5:
+// rs1==x20, rs2==x1, rd==x26, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: orn ; op1:x20; op2:x1; dest:x26; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(orn, x26, x20, x1, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x10, 40, x23)
+
+inst_6:
+// rs1==x2, rs2==x7, rd==x9, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: orn ; op1:x2; op2:x7; dest:x9; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(orn, x9, x2, x7, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x10, 48, x23)
+
+inst_7:
+// rs1==x9, rs2==x3, rd==x17, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: orn ; op1:x9; op2:x3; dest:x17; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(orn, x17, x9, x3, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x10, 56, x23)
+
+inst_8:
+// rs1==x4, rs2==x27, rd==x30, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: orn ; op1:x4; op2:x27; dest:x30; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(orn, x30, x4, x27, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x10, 64, x23)
+
+inst_9:
+// rs1==x24, rs2==x0, rd==x22, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: orn ; op1:x24; op2:x0; dest:x22; op1val:0xde81bcad0b815ef0;  op2val:0x0
+TEST_RR_OP(orn, x22, x24, x0, 0x0000000000000000, 0xde81bcad0b815ef0, 0x0, x10, 72, x23)
+
+inst_10:
+// rs1==x31, rs2==x30, rd==x19, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: orn ; op1:x31; op2:x30; dest:x19; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(orn, x19, x31, x30, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x10, 80, x23)
+
+inst_11:
+// rs1==x15, rs2==x12, rd==x20, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: orn ; op1:x15; op2:x12; dest:x20; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(orn, x20, x15, x12, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x10, 88, x23)
+
+inst_12:
+// rs1==x19, rs2==x13, rd==x31, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: orn ; op1:x19; op2:x13; dest:x31; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(orn, x31, x19, x13, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x10, 96, x23)
+
+inst_13:
+// rs1==x14, rs2==x24, rd==x28, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: orn ; op1:x14; op2:x24; dest:x28; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(orn, x28, x14, x24, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x10, 104, x23)
+
+inst_14:
+// rs1==x29, rs2==x18, rd==x0, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: orn ; op1:x29; op2:x18; dest:x0; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(orn, x0, x29, x18, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x10, 112, x23)
+RVTEST_SIGBASE( x8,signature_x8_0)
+
+inst_15:
+// rs1==x23, rs2==x4, rd==x11, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: orn ; op1:x23; op2:x4; dest:x11; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(orn, x11, x23, x4, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x8, 0, x14)
+
+inst_16:
+// rs1==x22, rs2==x25, rd==x10, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: orn ; op1:x22; op2:x25; dest:x10; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(orn, x10, x22, x25, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x8, 8, x14)
+
+inst_17:
+// rs1==x26, rs2==x28, rd==x18, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: orn ; op1:x26; op2:x28; dest:x18; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(orn, x18, x26, x28, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x8, 16, x14)
+
+inst_18:
+// rs1==x30, rs2==x26, rd==x3, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: orn ; op1:x30; op2:x26; dest:x3; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(orn, x3, x30, x26, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x8, 24, x14)
+
+inst_19:
+// rs1==x17, rs2==x9, rd==x2, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: orn ; op1:x17; op2:x9; dest:x2; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(orn, x2, x17, x9, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x8, 32, x14)
+
+inst_20:
+// rs1==x10, rs2==x17, rd==x4, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: orn ; op1:x10; op2:x17; dest:x4; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(orn, x4, x10, x17, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x8, 40, x14)
+
+inst_21:
+// rs1==x12, rs2==x19, rd==x23, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: orn ; op1:x12; op2:x19; dest:x23; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(orn, x23, x12, x19, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x8, 48, x14)
+
+inst_22:
+// rs1==x18, rs2==x23, rd==x13, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: orn ; op1:x18; op2:x23; dest:x13; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(orn, x13, x18, x23, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x8, 56, x14)
+
+inst_23:
+// rs1==x3, rs2==x6, rd==x5, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: orn ; op1:x3; op2:x6; dest:x5; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(orn, x5, x3, x6, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x8, 64, x14)
+
+inst_24:
+// rs1==x0, rs2==x5, rd==x24, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: orn ; op1:x0; op2:x5; dest:x24; op1val:0x0;  op2val:0xf37b4e0000000000
+TEST_RR_OP(orn, x24, x0, x5, 0x0000000000000000, 0x0, 0xf37b4e0000000000, x8, 72, x14)
+
+inst_25:
+// rs1==x1, rs2==x20, rd==x12, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: orn ; op1:x1; op2:x20; dest:x12; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(orn, x12, x1, x20, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x8, 80, x14)
+
+inst_26:
+// rs1==x16, rs2==x22, rd==x1, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: orn ; op1:x16; op2:x22; dest:x1; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(orn, x1, x16, x22, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x8, 88, x14)
+
+inst_27:
+// rs1==x7, rs2==x16, rd==x21, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: orn ; op1:x7; op2:x16; dest:x21; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(orn, x21, x7, x16, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x8, 96, x14)
+
+inst_28:
+// rs1==x21, rs2==x2, rd==x27, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: orn ; op1:x21; op2:x2; dest:x27; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(orn, x27, x21, x2, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x8, 104, x14)
+
+inst_29:
+// rs1==x13, rs2==x29, rd==x7, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: orn ; op1:x13; op2:x29; dest:x7; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(orn, x7, x13, x29, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x8, 112, x14)
+
+inst_30:
+// rs1==x25, rs2==x15, rd==x29, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: orn ; op1:x25; op2:x15; dest:x29; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(orn, x29, x25, x15, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x8, 120, x2)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_31:
+// rs1==x28, rs2==x10, rd==x25, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: orn ; op1:x28; op2:x10; dest:x25; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(orn, x25, x28, x10, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x1, 0, x2)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x1, 8, x2)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 16, x2)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 24, x2)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 32, x2)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 40, x2)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 48, x2)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 56, x2)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 64, x2)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 72, x2)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 80, x2)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 88, x2)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 96, x2)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 104, x2)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 112, x2)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 120, x2)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 128, x2)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 136, x2)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 144, x2)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 152, x2)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 160, x2)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 168, x2)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 176, x2)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 184, x2)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 192, x2)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 200, x2)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 208, x2)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 216, x2)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 224, x2)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 232, x2)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 240, x2)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 248, x2)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 256, x2)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 264, x2)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 272, x2)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 280, x2)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 288, x2)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 296, x2)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 304, x2)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 312, x2)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 320, x2)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 328, x2)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 336, x2)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 344, x2)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 352, x2)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 360, x2)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 368, x2)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 376, x2)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 384, x2)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 392, x2)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 400, x2)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 408, x2)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 416, x2)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 424, x2)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 432, x2)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 440, x2)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 448, x2)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 456, x2)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 464, x2)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 472, x2)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 480, x2)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 488, x2)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 496, x2)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 504, x2)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 512, x2)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 520, x2)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 528, x2)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 536, x2)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 544, x2)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 552, x2)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 560, x2)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 568, x2)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 576, x2)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 584, x2)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 592, x2)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 600, x2)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 608, x2)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 616, x2)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 624, x2)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 632, x2)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 640, x2)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 648, x2)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 656, x2)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 664, x2)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 672, x2)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 680, x2)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 688, x2)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 696, x2)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 704, x2)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 712, x2)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 720, x2)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 728, x2)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 736, x2)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 744, x2)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 752, x2)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 760, x2)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 768, x2)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 776, x2)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 784, x2)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 792, x2)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 800, x2)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 808, x2)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 816, x2)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 824, x2)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 832, x2)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 840, x2)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 848, x2)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 856, x2)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 864, x2)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 872, x2)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 880, x2)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 888, x2)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 896, x2)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 904, x2)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 912, x2)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 920, x2)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 928, x2)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 936, x2)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 944, x2)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 952, x2)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 960, x2)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 968, x2)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 976, x2)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 984, x2)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 992, x2)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 1000, x2)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 1008, x2)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1016, x2)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1024, x2)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1032, x2)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1040, x2)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1048, x2)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1056, x2)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1064, x2)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1072, x2)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1080, x2)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1088, x2)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1096, x2)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1104, x2)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1112, x2)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1120, x2)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1128, x2)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1136, x2)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1144, x2)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1152, x2)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1160, x2)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1168, x2)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1176, x2)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1184, x2)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1192, x2)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1200, x2)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1208, x2)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1216, x2)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1224, x2)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1232, x2)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1240, x2)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1248, x2)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1256, x2)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1264, x2)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1272, x2)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1280, x2)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1288, x2)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1296, x2)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1304, x2)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1312, x2)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1320, x2)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1328, x2)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1336, x2)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1344, x2)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1352, x2)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1360, x2)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1368, x2)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1376, x2)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1384, x2)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1392, x2)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1400, x2)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1408, x2)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1416, x2)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1424, x2)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1432, x2)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1440, x2)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1448, x2)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1456, x2)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1464, x2)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1472, x2)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1480, x2)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1488, x2)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1496, x2)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1504, x2)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1512, x2)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1520, x2)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1528, x2)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1536, x2)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1544, x2)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1552, x2)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1560, x2)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1568, x2)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1576, x2)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1584, x2)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1592, x2)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1600, x2)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1608, x2)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1616, x2)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1624, x2)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1632, x2)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1640, x2)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1648, x2)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1656, x2)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1664, x2)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1672, x2)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1680, x2)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1688, x2)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1696, x2)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1704, x2)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1712, x2)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1720, x2)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1728, x2)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1736, x2)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1744, x2)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1752, x2)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1760, x2)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1768, x2)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1776, x2)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1784, x2)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1792, x2)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1800, x2)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1808, x2)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1816, x2)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1824, x2)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1832, x2)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1840, x2)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1848, x2)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1856, x2)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1864, x2)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1872, x2)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1880, x2)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1888, x2)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 1896, x2)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 1904, x2)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 1912, x2)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 1920, x2)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 1928, x2)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 1936, x2)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 1944, x2)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 1952, x2)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 1960, x2)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 1968, x2)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 1976, x2)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 1984, x2)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 1992, x2)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 2000, x2)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 2008, x2)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 2016, x2)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 2024, x2)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 2032, x2)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 2040, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 0, x2)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 8, x2)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 16, x2)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 24, x2)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 32, x2)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 40, x2)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 48, x2)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 56, x2)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 64, x2)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 72, x2)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 80, x2)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 88, x2)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 96, x2)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 104, x2)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 112, x2)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 120, x2)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 128, x2)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 136, x2)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 144, x2)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 152, x2)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 160, x2)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 168, x2)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 176, x2)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 184, x2)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 192, x2)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 200, x2)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 208, x2)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 216, x2)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 224, x2)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 232, x2)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 240, x2)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 248, x2)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 256, x2)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 264, x2)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 272, x2)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 280, x2)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 288, x2)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 296, x2)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 304, x2)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 312, x2)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 320, x2)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 328, x2)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 336, x2)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 344, x2)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 352, x2)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 360, x2)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 368, x2)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 376, x2)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 384, x2)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 392, x2)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 400, x2)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 408, x2)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 416, x2)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 424, x2)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 432, x2)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 440, x2)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 448, x2)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 456, x2)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 464, x2)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 472, x2)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 480, x2)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 488, x2)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 496, x2)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 504, x2)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 512, x2)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 520, x2)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 528, x2)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 536, x2)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 544, x2)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 552, x2)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 560, x2)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 568, x2)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 576, x2)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 584, x2)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 592, x2)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 600, x2)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 608, x2)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 616, x2)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 624, x2)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 632, x2)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 640, x2)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 648, x2)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 656, x2)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 664, x2)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 672, x2)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 680, x2)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 688, x2)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 696, x2)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 704, x2)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 712, x2)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 720, x2)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 728, x2)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 736, x2)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 744, x2)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 752, x2)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 760, x2)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 768, x2)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 776, x2)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 784, x2)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 792, x2)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 800, x2)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 808, x2)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 816, x2)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 824, x2)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 832, x2)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 840, x2)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 848, x2)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 856, x2)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 864, x2)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 872, x2)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 880, x2)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 888, x2)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 896, x2)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 904, x2)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 912, x2)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 920, x2)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 928, x2)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 936, x2)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 944, x2)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 952, x2)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 960, x2)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 968, x2)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 976, x2)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 984, x2)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 992, x2)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 1000, x2)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 1008, x2)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1016, x2)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1024, x2)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1032, x2)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1040, x2)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1048, x2)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1056, x2)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1064, x2)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1072, x2)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1080, x2)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1088, x2)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1096, x2)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1104, x2)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1112, x2)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1120, x2)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1128, x2)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1136, x2)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1144, x2)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1152, x2)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1160, x2)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1168, x2)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1176, x2)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1184, x2)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1192, x2)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1200, x2)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1208, x2)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1216, x2)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1224, x2)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1232, x2)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1240, x2)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1248, x2)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1256, x2)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1264, x2)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1272, x2)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1280, x2)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1288, x2)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1296, x2)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1304, x2)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1312, x2)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1320, x2)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1328, x2)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1336, x2)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1344, x2)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1352, x2)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1360, x2)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1368, x2)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1376, x2)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1384, x2)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1392, x2)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1400, x2)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1408, x2)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1416, x2)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1424, x2)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1432, x2)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1440, x2)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1448, x2)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1456, x2)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1464, x2)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1472, x2)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1480, x2)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1488, x2)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1496, x2)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1504, x2)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1512, x2)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1520, x2)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1528, x2)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1536, x2)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1544, x2)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1552, x2)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1560, x2)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1568, x2)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1576, x2)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1584, x2)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1592, x2)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1600, x2)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1608, x2)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1616, x2)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1624, x2)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1632, x2)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1640, x2)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1648, x2)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1656, x2)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1664, x2)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1672, x2)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1680, x2)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1688, x2)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1696, x2)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1704, x2)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1712, x2)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1720, x2)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1728, x2)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1736, x2)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1744, x2)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1752, x2)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1760, x2)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1768, x2)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1776, x2)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1784, x2)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1792, x2)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1800, x2)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1808, x2)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1816, x2)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1824, x2)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1832, x2)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1840, x2)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1848, x2)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1856, x2)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1864, x2)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1872, x2)
+
+inst_522:
+// rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x1, 1880, x2)
+
+inst_523:
+// rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x1, 1888, x2)
+
+inst_524:
+// rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: orn ; op1:x10; op2:x11; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(orn, x12, x10, x11, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x1, 1896, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x10_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x10_1:
+    .fill 15*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_0:
+    .fill 16*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 238*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S
new file mode 100644
index 000000000..65270346f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/pack-01.S
@@ -0,0 +1,2706 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the pack instruction of the RISC-V  extension for the pack covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",pack)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",pack)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",pack)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",pack)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x23, rs2==x23, rd==x0, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: pack ; op1:x23; op2:x23; dest:x0; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(pack, x0, x23, x23, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x8, 0, x15)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x18, rs2==x18, rd==x18, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: pack ; op1:x18; op2:x18; dest:x18; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(pack, x18, x18, x18, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x8, 8, x15)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x5, rs2==x30, rd==x17, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: pack ; op1:x5; op2:x30; dest:x17; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(pack, x17, x5, x30, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x8, 16, x15)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x7, rs2==x24, rd==x7, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: pack ; op1:x7; op2:x24; dest:x7; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(pack, x7, x7, x24, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x8, 24, x15)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x12, rs2==x13, rd==x13, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: pack ; op1:x12; op2:x13; dest:x13; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(pack, x13, x12, x13, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x8, 32, x15)
+
+inst_5:
+// rs1==x21, rs2==x12, rd==x16, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: pack ; op1:x21; op2:x12; dest:x16; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(pack, x16, x21, x12, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x8, 40, x15)
+
+inst_6:
+// rs1==x17, rs2==x14, rd==x1, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: pack ; op1:x17; op2:x14; dest:x1; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(pack, x1, x17, x14, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x8, 48, x15)
+
+inst_7:
+// rs1==x27, rs2==x21, rd==x28, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: pack ; op1:x27; op2:x21; dest:x28; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(pack, x28, x27, x21, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x8, 56, x15)
+
+inst_8:
+// rs1==x22, rs2==x19, rd==x11, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: pack ; op1:x22; op2:x19; dest:x11; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(pack, x11, x22, x19, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x8, 64, x15)
+
+inst_9:
+// rs1==x3, rs2==x29, rd==x30, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: pack ; op1:x3; op2:x29; dest:x30; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(pack, x30, x3, x29, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x8, 72, x15)
+
+inst_10:
+// rs1==x11, rs2==x1, rd==x25, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: pack ; op1:x11; op2:x1; dest:x25; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(pack, x25, x11, x1, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x8, 80, x15)
+
+inst_11:
+// rs1==x2, rs2==x27, rd==x9, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: pack ; op1:x2; op2:x27; dest:x9; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(pack, x9, x2, x27, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x8, 88, x15)
+
+inst_12:
+// rs1==x13, rs2==x28, rd==x14, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: pack ; op1:x13; op2:x28; dest:x14; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(pack, x14, x13, x28, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x8, 96, x15)
+
+inst_13:
+// rs1==x29, rs2==x9, rd==x20, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: pack ; op1:x29; op2:x9; dest:x20; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(pack, x20, x29, x9, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x8, 104, x15)
+
+inst_14:
+// rs1==x24, rs2==x7, rd==x6, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: pack ; op1:x24; op2:x7; dest:x6; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(pack, x6, x24, x7, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x8, 112, x15)
+
+inst_15:
+// rs1==x6, rs2==x11, rd==x29, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: pack ; op1:x6; op2:x11; dest:x29; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(pack, x29, x6, x11, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x8, 120, x15)
+
+inst_16:
+// rs1==x10, rs2==x4, rd==x12, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: pack ; op1:x10; op2:x4; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(pack, x12, x10, x4, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x8, 128, x15)
+
+inst_17:
+// rs1==x1, rs2==x17, rd==x26, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: pack ; op1:x1; op2:x17; dest:x26; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(pack, x26, x1, x17, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x8, 136, x7)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_18:
+// rs1==x16, rs2==x22, rd==x27, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: pack ; op1:x16; op2:x22; dest:x27; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(pack, x27, x16, x22, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x1, 0, x7)
+
+inst_19:
+// rs1==x0, rs2==x10, rd==x31, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: pack ; op1:x0; op2:x10; dest:x31; op1val:0x0;  op2val:0x3da8400000000000
+TEST_RR_OP(pack, x31, x0, x10, 0x0000000000000000, 0x0, 0x3da8400000000000, x1, 8, x7)
+
+inst_20:
+// rs1==x30, rs2==x8, rd==x2, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: pack ; op1:x30; op2:x8; dest:x2; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(pack, x2, x30, x8, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x1, 16, x7)
+
+inst_21:
+// rs1==x26, rs2==x25, rd==x24, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: pack ; op1:x26; op2:x25; dest:x24; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(pack, x24, x26, x25, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x1, 24, x7)
+
+inst_22:
+// rs1==x25, rs2==x2, rd==x3, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: pack ; op1:x25; op2:x2; dest:x3; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(pack, x3, x25, x2, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x1, 32, x7)
+
+inst_23:
+// rs1==x4, rs2==x16, rd==x19, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: pack ; op1:x4; op2:x16; dest:x19; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(pack, x19, x4, x16, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x1, 40, x7)
+
+inst_24:
+// rs1==x20, rs2==x26, rd==x23, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: pack ; op1:x20; op2:x26; dest:x23; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(pack, x23, x20, x26, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x1, 48, x7)
+
+inst_25:
+// rs1==x28, rs2==x20, rd==x4, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: pack ; op1:x28; op2:x20; dest:x4; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(pack, x4, x28, x20, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x1, 56, x7)
+
+inst_26:
+// rs1==x31, rs2==x0, rd==x21, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: pack ; op1:x31; op2:x0; dest:x21; op1val:0x4256f18f2de4eb20;  op2val:0x0
+TEST_RR_OP(pack, x21, x31, x0, 0x0000000000000000, 0x4256f18f2de4eb20, 0x0, x1, 64, x7)
+
+inst_27:
+// rs1==x14, rs2==x5, rd==x8, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: pack ; op1:x14; op2:x5; dest:x8; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(pack, x8, x14, x5, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x1, 72, x7)
+
+inst_28:
+// rs1==x9, rs2==x15, rd==x22, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: pack ; op1:x9; op2:x15; dest:x22; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(pack, x22, x9, x15, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x1, 80, x7)
+
+inst_29:
+// rs1==x19, rs2==x6, rd==x5, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: pack ; op1:x19; op2:x6; dest:x5; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(pack, x5, x19, x6, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x1, 88, x7)
+
+inst_30:
+// rs1==x8, rs2==x3, rd==x10, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: pack ; op1:x8; op2:x3; dest:x10; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(pack, x10, x8, x3, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 96, x7)
+
+inst_31:
+// rs1==x15, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: pack ; op1:x15; op2:x18; dest:x24; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(pack, x24, x15, x18, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x1, 104, x7)
+
+inst_32:
+// rs2==x31, rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: pack ; op1:x14; op2:x31; dest:x4; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(pack, x4, x14, x31, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x1, 112, x7)
+
+inst_33:
+// rd==x15, rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: pack ; op1:x16; op2:x8; dest:x15; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(pack, x15, x16, x8, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 120, x7)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 128, x7)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 136, x2)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 144, x2)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 152, x2)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 160, x2)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 168, x2)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 176, x2)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 184, x2)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 192, x2)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 200, x2)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 208, x2)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 216, x2)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 224, x2)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 232, x2)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 240, x2)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 248, x2)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 256, x2)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 264, x2)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 272, x2)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 280, x2)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 288, x2)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 296, x2)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 304, x2)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 312, x2)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 320, x2)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 328, x2)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 336, x2)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 344, x2)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 352, x2)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 360, x2)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 368, x2)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 376, x2)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 384, x2)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 392, x2)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 400, x2)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 408, x2)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 416, x2)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 424, x2)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 432, x2)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 440, x2)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 448, x2)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 456, x2)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 464, x2)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 472, x2)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 480, x2)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 488, x2)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 496, x2)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 504, x2)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 512, x2)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 520, x2)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 528, x2)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 536, x2)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 544, x2)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 552, x2)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 560, x2)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 568, x2)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 576, x2)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 584, x2)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 592, x2)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 600, x2)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 608, x2)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 616, x2)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 624, x2)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 632, x2)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 640, x2)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 648, x2)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 656, x2)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 664, x2)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 672, x2)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 680, x2)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 688, x2)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 696, x2)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 704, x2)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 712, x2)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 720, x2)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 728, x2)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 736, x2)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 744, x2)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 752, x2)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 760, x2)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 768, x2)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 776, x2)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 784, x2)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 792, x2)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 800, x2)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 808, x2)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 816, x2)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 824, x2)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 832, x2)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 840, x2)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 848, x2)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 856, x2)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 864, x2)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 872, x2)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 880, x2)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 888, x2)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 896, x2)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 904, x2)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 912, x2)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 920, x2)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 928, x2)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 936, x2)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 944, x2)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 952, x2)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 960, x2)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 968, x2)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 976, x2)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 984, x2)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 992, x2)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 1000, x2)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 1008, x2)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 1016, x2)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 1024, x2)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 1032, x2)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 1040, x2)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 1048, x2)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 1056, x2)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 1064, x2)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 1072, x2)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 1080, x2)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 1088, x2)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 1096, x2)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 1104, x2)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 1112, x2)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1120, x2)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1128, x2)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1136, x2)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1144, x2)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1152, x2)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1160, x2)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1168, x2)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1176, x2)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1184, x2)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1192, x2)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1200, x2)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1208, x2)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1216, x2)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1224, x2)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1232, x2)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1240, x2)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1248, x2)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1256, x2)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1264, x2)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1272, x2)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1280, x2)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1288, x2)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1296, x2)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1304, x2)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1312, x2)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1320, x2)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1328, x2)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1336, x2)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1344, x2)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1352, x2)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1360, x2)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1368, x2)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1376, x2)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1384, x2)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1392, x2)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1400, x2)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1408, x2)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1416, x2)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1424, x2)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1432, x2)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1440, x2)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1448, x2)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1456, x2)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1464, x2)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1472, x2)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1480, x2)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1488, x2)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1496, x2)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1504, x2)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1512, x2)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1520, x2)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1528, x2)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1536, x2)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1544, x2)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1552, x2)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1560, x2)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1568, x2)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1576, x2)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1584, x2)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1592, x2)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1600, x2)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1608, x2)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1616, x2)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1624, x2)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1632, x2)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1640, x2)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1648, x2)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1656, x2)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1664, x2)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1672, x2)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1680, x2)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1688, x2)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1696, x2)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1704, x2)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1712, x2)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1720, x2)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1728, x2)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1736, x2)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1744, x2)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1752, x2)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1760, x2)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1768, x2)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1776, x2)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1784, x2)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1792, x2)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1800, x2)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1808, x2)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1816, x2)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1824, x2)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1832, x2)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1840, x2)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1848, x2)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1856, x2)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1864, x2)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1872, x2)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1880, x2)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1888, x2)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1896, x2)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1904, x2)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1912, x2)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1920, x2)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1928, x2)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1936, x2)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1944, x2)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1952, x2)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1960, x2)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1968, x2)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1976, x2)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1984, x2)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1992, x2)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 2000, x2)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 2008, x2)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 2016, x2)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 2024, x2)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 2032, x2)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 2040, x2)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 0, x2)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 8, x2)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 16, x2)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 24, x2)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 32, x2)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 40, x2)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 48, x2)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 56, x2)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 64, x2)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 72, x2)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 80, x2)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 88, x2)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 96, x2)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 104, x2)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 112, x2)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 120, x2)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 128, x2)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 136, x2)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 144, x2)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 152, x2)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 160, x2)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 168, x2)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 176, x2)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 184, x2)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 192, x2)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 200, x2)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 208, x2)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 216, x2)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 224, x2)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 232, x2)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 240, x2)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 248, x2)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 256, x2)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 264, x2)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 272, x2)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 280, x2)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 288, x2)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 296, x2)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 304, x2)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 312, x2)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 320, x2)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 328, x2)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 336, x2)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 344, x2)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 352, x2)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 360, x2)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 368, x2)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 376, x2)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 384, x2)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 392, x2)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 400, x2)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 408, x2)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 416, x2)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 424, x2)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 432, x2)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 440, x2)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 448, x2)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 456, x2)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 464, x2)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 472, x2)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 480, x2)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 488, x2)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 496, x2)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 504, x2)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 512, x2)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 520, x2)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 528, x2)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 536, x2)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 544, x2)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 552, x2)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 560, x2)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 568, x2)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 576, x2)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 584, x2)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 592, x2)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 600, x2)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 608, x2)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 616, x2)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 624, x2)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 632, x2)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 640, x2)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 648, x2)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 656, x2)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 664, x2)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 672, x2)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 680, x2)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 688, x2)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 696, x2)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 704, x2)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 712, x2)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 720, x2)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 728, x2)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 736, x2)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 744, x2)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 752, x2)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 760, x2)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 768, x2)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 776, x2)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 784, x2)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 792, x2)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 800, x2)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 808, x2)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 816, x2)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 824, x2)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 832, x2)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 840, x2)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 848, x2)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 856, x2)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 864, x2)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 872, x2)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 880, x2)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 888, x2)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 896, x2)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 904, x2)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 912, x2)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 920, x2)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 928, x2)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 936, x2)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 944, x2)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 952, x2)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 960, x2)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 968, x2)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 976, x2)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 984, x2)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 992, x2)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 1000, x2)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 1008, x2)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 1016, x2)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 1024, x2)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 1032, x2)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 1040, x2)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 1048, x2)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 1056, x2)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 1064, x2)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 1072, x2)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 1080, x2)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 1088, x2)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 1096, x2)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 1104, x2)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 1112, x2)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1120, x2)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1128, x2)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1136, x2)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1144, x2)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1152, x2)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1160, x2)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1168, x2)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1176, x2)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1184, x2)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1192, x2)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1200, x2)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1208, x2)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1216, x2)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1224, x2)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1232, x2)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1240, x2)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1248, x2)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1256, x2)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1264, x2)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1272, x2)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1280, x2)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1288, x2)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1296, x2)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1304, x2)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1312, x2)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1320, x2)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1328, x2)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1336, x2)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1344, x2)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1352, x2)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1360, x2)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1368, x2)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1376, x2)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1384, x2)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1392, x2)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1400, x2)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1408, x2)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1416, x2)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1424, x2)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1432, x2)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1440, x2)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1448, x2)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1456, x2)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1464, x2)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1472, x2)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1480, x2)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1488, x2)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1496, x2)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1504, x2)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1512, x2)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1520, x2)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1528, x2)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1536, x2)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1544, x2)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1552, x2)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1560, x2)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1568, x2)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1576, x2)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1584, x2)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1592, x2)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1600, x2)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1608, x2)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1616, x2)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1624, x2)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1632, x2)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1640, x2)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1648, x2)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1656, x2)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1664, x2)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1672, x2)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1680, x2)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1688, x2)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1696, x2)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1704, x2)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1712, x2)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1720, x2)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1728, x2)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1736, x2)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1744, x2)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1752, x2)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1760, x2)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1768, x2)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1776, x2)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1784, x2)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1792, x2)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1800, x2)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1808, x2)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1816, x2)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1824, x2)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1832, x2)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1840, x2)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1848, x2)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1856, x2)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1864, x2)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1872, x2)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1880, x2)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1888, x2)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1896, x2)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1904, x2)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1912, x2)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1920, x2)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1928, x2)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1936, x2)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1944, x2)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1952, x2)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1960, x2)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1968, x2)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1976, x2)
+
+inst_522:
+// rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x1, 1984, x2)
+
+inst_523:
+// rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: pack ; op1:x10; op2:x11; dest:x12; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(pack, x12, x10, x11, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x1, 1992, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 250*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S
new file mode 100644
index 000000000..f25688408
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packh-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the packh instruction of the RISC-V  extension for the packh covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",packh)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",packh)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",packh)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",packh)
+
+RVTEST_SIGBASE( x16,signature_x16_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x6, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packh ; op1:x29; op2:x29; dest:x6; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(packh, x6, x29, x29, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x16, 0, x15)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x18, rs2==x18, rd==x18, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packh ; op1:x18; op2:x18; dest:x18; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(packh, x18, x18, x18, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x16, 8, x15)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x20, rs2==x26, rd==x5, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: packh ; op1:x20; op2:x26; dest:x5; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(packh, x5, x20, x26, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x16, 16, x15)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x17, rs2==x24, rd==x17, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: packh ; op1:x17; op2:x24; dest:x17; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(packh, x17, x17, x24, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x16, 24, x15)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x12, rs2==x2, rd==x2, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: packh ; op1:x12; op2:x2; dest:x2; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(packh, x2, x12, x2, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x16, 32, x15)
+
+inst_5:
+// rs1==x30, rs2==x7, rd==x3, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: packh ; op1:x30; op2:x7; dest:x3; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(packh, x3, x30, x7, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x16, 40, x15)
+
+inst_6:
+// rs1==x7, rs2==x28, rd==x22, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: packh ; op1:x7; op2:x28; dest:x22; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(packh, x22, x7, x28, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x16, 48, x15)
+
+inst_7:
+// rs1==x8, rs2==x1, rd==x14, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: packh ; op1:x8; op2:x1; dest:x14; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(packh, x14, x8, x1, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x16, 56, x15)
+
+inst_8:
+// rs1==x3, rs2==x10, rd==x12, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: packh ; op1:x3; op2:x10; dest:x12; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(packh, x12, x3, x10, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x16, 64, x15)
+
+inst_9:
+// rs1==x5, rs2==x6, rd==x20, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: packh ; op1:x5; op2:x6; dest:x20; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(packh, x20, x5, x6, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x16, 72, x15)
+
+inst_10:
+// rs1==x11, rs2==x22, rd==x29, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: packh ; op1:x11; op2:x22; dest:x29; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(packh, x29, x11, x22, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x16, 80, x15)
+
+inst_11:
+// rs1==x24, rs2==x0, rd==x27, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packh ; op1:x24; op2:x0; dest:x27; op1val:0xfd8bf41246e4abd8;  op2val:0x0
+TEST_RR_OP(packh, x27, x24, x0, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x0, x16, 88, x15)
+
+inst_12:
+// rs1==x13, rs2==x23, rd==x4, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: packh ; op1:x13; op2:x23; dest:x4; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(packh, x4, x13, x23, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x16, 96, x15)
+
+inst_13:
+// rs1==x22, rs2==x3, rd==x0, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: packh ; op1:x22; op2:x3; dest:x0; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(packh, x0, x22, x3, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x16, 104, x15)
+
+inst_14:
+// rs1==x9, rs2==x5, rd==x24, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: packh ; op1:x9; op2:x5; dest:x24; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(packh, x24, x9, x5, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x16, 112, x15)
+
+inst_15:
+// rs1==x19, rs2==x30, rd==x13, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: packh ; op1:x19; op2:x30; dest:x13; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(packh, x13, x19, x30, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x16, 120, x15)
+
+inst_16:
+// rs1==x1, rs2==x20, rd==x7, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: packh ; op1:x1; op2:x20; dest:x7; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(packh, x7, x1, x20, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x16, 128, x15)
+
+inst_17:
+// rs1==x10, rs2==x9, rd==x21, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: packh ; op1:x10; op2:x9; dest:x21; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(packh, x21, x10, x9, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x16, 136, x15)
+
+inst_18:
+// rs1==x26, rs2==x8, rd==x1, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: packh ; op1:x26; op2:x8; dest:x1; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(packh, x1, x26, x8, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x16, 144, x3)
+
+inst_19:
+// rs1==x21, rs2==x13, rd==x11, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: packh ; op1:x21; op2:x13; dest:x11; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(packh, x11, x21, x13, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x16, 152, x3)
+
+inst_20:
+// rs1==x2, rs2==x4, rd==x30, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: packh ; op1:x2; op2:x4; dest:x30; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(packh, x30, x2, x4, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x16, 160, x3)
+
+inst_21:
+// rs1==x4, rs2==x17, rd==x8, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: packh ; op1:x4; op2:x17; dest:x8; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(packh, x8, x4, x17, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x16, 168, x3)
+
+inst_22:
+// rs1==x14, rs2==x15, rd==x9, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: packh ; op1:x14; op2:x15; dest:x9; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(packh, x9, x14, x15, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x16, 176, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_23:
+// rs1==x16, rs2==x11, rd==x28, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: packh ; op1:x16; op2:x11; dest:x28; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(packh, x28, x16, x11, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x1, 0, x3)
+
+inst_24:
+// rs1==x28, rs2==x31, rd==x23, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: packh ; op1:x28; op2:x31; dest:x23; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(packh, x23, x28, x31, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x1, 8, x3)
+
+inst_25:
+// rs1==x6, rs2==x19, rd==x31, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: packh ; op1:x6; op2:x19; dest:x31; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(packh, x31, x6, x19, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x1, 16, x3)
+
+inst_26:
+// rs1==x25, rs2==x16, rd==x15, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: packh ; op1:x25; op2:x16; dest:x15; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(packh, x15, x25, x16, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x1, 24, x3)
+
+inst_27:
+// rs1==x0, rs2==x21, rd==x25, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: packh ; op1:x0; op2:x21; dest:x25; op1val:0x0;  op2val:0xfa56aa4000000000
+TEST_RR_OP(packh, x25, x0, x21, 0x0000000000000000, 0x0, 0xfa56aa4000000000, x1, 32, x3)
+
+inst_28:
+// rs1==x27, rs2==x14, rd==x10, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: packh ; op1:x27; op2:x14; dest:x10; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(packh, x10, x27, x14, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x1, 40, x3)
+
+inst_29:
+// rs1==x23, rs2==x27, rd==x19, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: packh ; op1:x23; op2:x27; dest:x19; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(packh, x19, x23, x27, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x1, 48, x3)
+
+inst_30:
+// rs1==x31, rs2==x25, rd==x16, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: packh ; op1:x31; op2:x25; dest:x16; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(packh, x16, x31, x25, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 56, x3)
+
+inst_31:
+// rs1==x15, rs2==x12, rd==x26, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: packh ; op1:x15; op2:x12; dest:x26; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(packh, x26, x15, x12, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x1, 64, x3)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x1, 72, x3)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 80, x3)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 88, x3)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 96, x3)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 104, x3)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 112, x3)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 120, x3)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 128, x3)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 136, x3)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 144, x3)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 152, x3)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 160, x3)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 168, x3)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 176, x3)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 184, x3)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 192, x3)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 200, x3)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 208, x3)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 216, x3)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 224, x3)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 232, x3)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 240, x3)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 248, x3)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 256, x3)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 264, x3)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 272, x3)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 280, x3)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 288, x3)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 296, x3)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 304, x3)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 312, x3)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 320, x3)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 328, x3)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 336, x3)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 344, x3)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 352, x3)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 360, x3)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 368, x3)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 376, x3)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 384, x3)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 392, x3)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 400, x3)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 408, x3)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 416, x3)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 424, x3)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 432, x3)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 440, x3)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 448, x3)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 456, x3)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 464, x3)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 472, x3)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 480, x3)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 488, x3)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 496, x3)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 504, x3)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 512, x3)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 520, x3)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 528, x3)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 536, x3)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 544, x3)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 552, x3)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 560, x3)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 568, x3)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 576, x3)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 584, x3)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 592, x3)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 600, x3)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 608, x3)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 616, x3)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 624, x3)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 632, x3)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 640, x3)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 648, x3)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 656, x3)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 664, x3)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 672, x3)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 680, x3)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 688, x3)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 696, x3)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 704, x3)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 712, x3)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 720, x3)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 728, x3)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 736, x3)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 744, x3)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 752, x3)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 760, x3)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 768, x3)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 776, x3)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 784, x3)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 792, x3)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 800, x3)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 808, x3)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 816, x3)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 824, x3)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 832, x3)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 840, x3)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 848, x3)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 856, x3)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 864, x3)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 872, x3)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 880, x3)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 888, x3)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 896, x3)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 904, x3)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 912, x3)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 920, x3)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 928, x3)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 936, x3)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 944, x3)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 952, x3)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 960, x3)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 968, x3)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 976, x3)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 984, x3)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 992, x3)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 1000, x3)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 1008, x3)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 1016, x3)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 1024, x3)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 1032, x3)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 1040, x3)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 1048, x3)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 1056, x3)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 1064, x3)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 1072, x3)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1080, x3)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1088, x3)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1096, x3)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1104, x3)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1112, x3)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1120, x3)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1128, x3)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1136, x3)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1144, x3)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1152, x3)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1160, x3)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1168, x3)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1176, x3)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1184, x3)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1192, x3)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1200, x3)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1208, x3)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1216, x3)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1224, x3)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1232, x3)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1240, x3)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1248, x3)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1256, x3)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1264, x3)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1272, x3)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1280, x3)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1288, x3)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1296, x3)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1304, x3)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1312, x3)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1320, x3)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1328, x3)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1336, x3)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1344, x3)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1352, x3)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1360, x3)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1368, x3)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1376, x3)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1384, x3)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1392, x3)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1400, x3)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1408, x3)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1416, x3)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1424, x3)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1432, x3)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1440, x3)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1448, x3)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1456, x3)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1464, x3)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1472, x3)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1480, x3)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1488, x3)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1496, x3)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1504, x3)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1512, x3)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1520, x3)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1528, x3)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1536, x3)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1544, x3)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1552, x3)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1560, x3)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1568, x3)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1576, x3)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1584, x3)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1592, x3)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1600, x3)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1608, x3)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1616, x3)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1624, x3)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1632, x3)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1640, x3)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1648, x3)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1656, x3)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1664, x3)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1672, x3)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1680, x3)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1688, x3)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1696, x3)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1704, x3)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1712, x3)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1720, x3)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1728, x3)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1736, x3)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1744, x3)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1752, x3)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1760, x3)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1768, x3)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1776, x3)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1784, x3)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1792, x3)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1800, x3)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1808, x3)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1816, x3)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1824, x3)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1832, x3)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1840, x3)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1848, x3)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1856, x3)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1864, x3)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1872, x3)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1880, x3)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1888, x3)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1896, x3)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1904, x3)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1912, x3)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1920, x3)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1928, x3)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1936, x3)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1944, x3)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1952, x3)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 1960, x3)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 1968, x3)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 1976, x3)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 1984, x3)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 1992, x3)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 2000, x3)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 2008, x3)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 2016, x3)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 2024, x3)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 2032, x3)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 2040, x3)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 0, x3)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 8, x3)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 16, x3)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 24, x3)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 32, x3)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 40, x3)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 48, x3)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 56, x3)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 64, x3)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 72, x3)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 80, x3)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 88, x3)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 96, x3)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 104, x3)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 112, x3)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 120, x3)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 128, x3)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 136, x3)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 144, x3)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 152, x3)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 160, x3)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 168, x3)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 176, x3)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 184, x3)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 192, x3)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 200, x3)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 208, x3)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 216, x3)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 224, x3)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 232, x3)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 240, x3)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 248, x3)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 256, x3)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 264, x3)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 272, x3)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 280, x3)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 288, x3)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 296, x3)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 304, x3)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 312, x3)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 320, x3)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 328, x3)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 336, x3)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 344, x3)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 352, x3)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 360, x3)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 368, x3)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 376, x3)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 384, x3)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 392, x3)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 400, x3)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 408, x3)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 416, x3)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 424, x3)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 432, x3)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 440, x3)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 448, x3)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 456, x3)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 464, x3)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 472, x3)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 480, x3)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 488, x3)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 496, x3)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 504, x3)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 512, x3)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 520, x3)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 528, x3)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 536, x3)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 544, x3)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 552, x3)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 560, x3)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 568, x3)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 576, x3)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 584, x3)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 592, x3)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 600, x3)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 608, x3)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 616, x3)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 624, x3)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 632, x3)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 640, x3)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 648, x3)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 656, x3)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 664, x3)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 672, x3)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 680, x3)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 688, x3)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 696, x3)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 704, x3)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 712, x3)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 720, x3)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 728, x3)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 736, x3)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 744, x3)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 752, x3)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 760, x3)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 768, x3)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 776, x3)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 784, x3)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 792, x3)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 800, x3)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 808, x3)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 816, x3)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 824, x3)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 832, x3)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 840, x3)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 848, x3)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 856, x3)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 864, x3)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 872, x3)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 880, x3)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 888, x3)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 896, x3)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 904, x3)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 912, x3)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 920, x3)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 928, x3)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 936, x3)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 944, x3)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 952, x3)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 960, x3)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 968, x3)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 976, x3)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 984, x3)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 992, x3)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 1000, x3)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 1008, x3)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 1016, x3)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 1024, x3)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 1032, x3)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 1040, x3)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 1048, x3)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 1056, x3)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 1064, x3)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 1072, x3)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1080, x3)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1088, x3)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1096, x3)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1104, x3)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1112, x3)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1120, x3)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1128, x3)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1136, x3)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1144, x3)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1152, x3)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1160, x3)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1168, x3)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1176, x3)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1184, x3)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1192, x3)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1200, x3)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1208, x3)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1216, x3)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1224, x3)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1232, x3)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1240, x3)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1248, x3)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1256, x3)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1264, x3)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1272, x3)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1280, x3)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1288, x3)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1296, x3)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1304, x3)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1312, x3)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1320, x3)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1328, x3)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1336, x3)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1344, x3)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1352, x3)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1360, x3)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1368, x3)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1376, x3)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1384, x3)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1392, x3)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1400, x3)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1408, x3)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1416, x3)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1424, x3)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1432, x3)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1440, x3)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1448, x3)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1456, x3)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1464, x3)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1472, x3)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1480, x3)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1488, x3)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1496, x3)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1504, x3)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1512, x3)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1520, x3)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1528, x3)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1536, x3)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1544, x3)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1552, x3)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1560, x3)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1568, x3)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1576, x3)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1584, x3)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1592, x3)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1600, x3)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1608, x3)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1616, x3)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1624, x3)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1632, x3)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1640, x3)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1648, x3)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1656, x3)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1664, x3)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1672, x3)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1680, x3)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1688, x3)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1696, x3)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1704, x3)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1712, x3)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1720, x3)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1728, x3)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1736, x3)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1744, x3)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1752, x3)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1760, x3)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1768, x3)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1776, x3)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1784, x3)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1792, x3)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1800, x3)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1808, x3)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1816, x3)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1824, x3)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1832, x3)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1840, x3)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1848, x3)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1856, x3)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1864, x3)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1872, x3)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1880, x3)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1888, x3)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1896, x3)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1904, x3)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1912, x3)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1920, x3)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1928, x3)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1936, x3)
+
+inst_522:
+// rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x1, 1944, x3)
+
+inst_523:
+// rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x1, 1952, x3)
+
+inst_524:
+// rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: packh ; op1:x10; op2:x11; dest:x12; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(packh, x12, x10, x11, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x1, 1960, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x16_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x16_1:
+    .fill 23*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 246*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S
new file mode 100644
index 000000000..6e96f15cd
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packu-01.S
@@ -0,0 +1,2696 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the packu instruction of the RISC-V  extension for the packu covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",packu)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",packu)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",packu)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",packu)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x6, rs2==x6, rd==x8, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packu ; op1:x6; op2:x6; dest:x8; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(packu, x8, x6, x6, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x4, 0, x5)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x0, rs2==x0, rd==x0, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packu ; op1:x0; op2:x0; dest:x0; op1val:0x0;  op2val:0x0
+TEST_RR_OP(packu, x0, x0, x0, 0x0000000000000000, 0x0, 0x0, x4, 8, x5)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x3, rs2==x12, rd==x22, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: packu ; op1:x3; op2:x12; dest:x22; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(packu, x22, x3, x12, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x4, 16, x5)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x24, rs2==x16, rd==x24, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: packu ; op1:x24; op2:x16; dest:x24; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(packu, x24, x24, x16, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x4, 24, x5)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x20, rs2==x2, rd==x2, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: packu ; op1:x20; op2:x2; dest:x2; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(packu, x2, x20, x2, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x4, 32, x5)
+
+inst_5:
+// rs1==x13, rs2==x11, rd==x16, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: packu ; op1:x13; op2:x11; dest:x16; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(packu, x16, x13, x11, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x4, 40, x5)
+
+inst_6:
+// rs1==x9, rs2==x7, rd==x27, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: packu ; op1:x9; op2:x7; dest:x27; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(packu, x27, x9, x7, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x4, 48, x5)
+
+inst_7:
+// rs1==x19, rs2==x26, rd==x18, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: packu ; op1:x19; op2:x26; dest:x18; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(packu, x18, x19, x26, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x4, 56, x5)
+
+inst_8:
+// rs1==x14, rs2==x20, rd==x15, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: packu ; op1:x14; op2:x20; dest:x15; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(packu, x15, x14, x20, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x4, 64, x5)
+
+inst_9:
+// rs1==x28, rs2==x25, rd==x11, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: packu ; op1:x28; op2:x25; dest:x11; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(packu, x11, x28, x25, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x4, 72, x5)
+
+inst_10:
+// rs1==x2, rs2==x14, rd==x29, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: packu ; op1:x2; op2:x14; dest:x29; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(packu, x29, x2, x14, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x4, 80, x5)
+
+inst_11:
+// rs1==x31, rs2==x9, rd==x14, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packu ; op1:x31; op2:x9; dest:x14; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(packu, x14, x31, x9, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x4, 88, x5)
+
+inst_12:
+// rs1==x16, rs2==x19, rd==x3, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: packu ; op1:x16; op2:x19; dest:x3; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(packu, x3, x16, x19, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x4, 96, x5)
+
+inst_13:
+// rs1==x27, rs2==x15, rd==x13, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: packu ; op1:x27; op2:x15; dest:x13; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(packu, x13, x27, x15, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x4, 104, x5)
+
+inst_14:
+// rs1==x11, rs2==x22, rd==x28, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: packu ; op1:x11; op2:x22; dest:x28; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(packu, x28, x11, x22, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x4, 112, x5)
+
+inst_15:
+// rs1==x21, rs2==x29, rd==x10, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: packu ; op1:x21; op2:x29; dest:x10; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(packu, x10, x21, x29, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x4, 120, x5)
+
+inst_16:
+// rs1==x15, rs2==x17, rd==x1, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: packu ; op1:x15; op2:x17; dest:x1; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(packu, x1, x15, x17, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x4, 128, x5)
+
+inst_17:
+// rs1==x1, rs2==x23, rd==x5, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: packu ; op1:x1; op2:x23; dest:x5; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(packu, x5, x1, x23, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x4, 136, x14)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_18:
+// rs1==x22, rs2==x24, rd==x12, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: packu ; op1:x22; op2:x24; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(packu, x12, x22, x24, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x2, 0, x14)
+
+inst_19:
+// rs1==x18, rs2==x1, rd==x25, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: packu ; op1:x18; op2:x1; dest:x25; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(packu, x25, x18, x1, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x2, 8, x14)
+
+inst_20:
+// rs1==x7, rs2==x21, rd==x17, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: packu ; op1:x7; op2:x21; dest:x17; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(packu, x17, x7, x21, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x2, 16, x14)
+
+inst_21:
+// rs1==x26, rs2==x8, rd==x30, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: packu ; op1:x26; op2:x8; dest:x30; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(packu, x30, x26, x8, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x2, 24, x14)
+
+inst_22:
+// rs1==x17, rs2==x27, rd==x31, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: packu ; op1:x17; op2:x27; dest:x31; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(packu, x31, x17, x27, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x2, 32, x14)
+
+inst_23:
+// rs1==x23, rs2==x4, rd==x6, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: packu ; op1:x23; op2:x4; dest:x6; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(packu, x6, x23, x4, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x2, 40, x14)
+
+inst_24:
+// rs1==x29, rs2==x10, rd==x19, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: packu ; op1:x29; op2:x10; dest:x19; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(packu, x19, x29, x10, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x2, 48, x14)
+
+inst_25:
+// rs1==x4, rs2==x13, rd==x26, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: packu ; op1:x4; op2:x13; dest:x26; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(packu, x26, x4, x13, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x2, 56, x14)
+
+inst_26:
+// rs1==x10, rs2==x3, rd==x23, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: packu ; op1:x10; op2:x3; dest:x23; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(packu, x23, x10, x3, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x2, 64, x14)
+
+inst_27:
+// rs1==x8, rs2==x31, rd==x7, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: packu ; op1:x8; op2:x31; dest:x7; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(packu, x7, x8, x31, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x2, 72, x14)
+
+inst_28:
+// rs1==x12, rs2==x30, rd==x9, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: packu ; op1:x12; op2:x30; dest:x9; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(packu, x9, x12, x30, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x2, 80, x14)
+
+inst_29:
+// rs1==x30, rs2==x18, rd==x20, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: packu ; op1:x30; op2:x18; dest:x20; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(packu, x20, x30, x18, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x2, 88, x14)
+
+inst_30:
+// rs1==x25, rs2==x5, rd==x21, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: packu ; op1:x25; op2:x5; dest:x21; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(packu, x21, x25, x5, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x2, 96, x14)
+
+inst_31:
+// rs1==x5, rs2==x28, rd==x4, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: packu ; op1:x5; op2:x28; dest:x4; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(packu, x4, x5, x28, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x2, 104, x14)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x2, 112, x14)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x2, 120, x1)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x2, 128, x1)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x2, 136, x1)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x2, 144, x1)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x2, 152, x1)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x2, 160, x1)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x2, 168, x1)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x2, 176, x1)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x2, 184, x1)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x2, 192, x1)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x2, 200, x1)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x2, 208, x1)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x2, 216, x1)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x2, 224, x1)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x2, 232, x1)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x2, 240, x1)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x2, 248, x1)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x2, 256, x1)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x2, 264, x1)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x2, 272, x1)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x2, 280, x1)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x2, 288, x1)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x2, 296, x1)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x2, 304, x1)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x2, 312, x1)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x2, 320, x1)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x2, 328, x1)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x2, 336, x1)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x2, 344, x1)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x2, 352, x1)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x2, 360, x1)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x2, 368, x1)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x2, 376, x1)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x2, 384, x1)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x2, 392, x1)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x2, 400, x1)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x2, 408, x1)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x2, 416, x1)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x2, 424, x1)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x2, 432, x1)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x2, 440, x1)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x2, 448, x1)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x2, 456, x1)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x2, 464, x1)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x2, 472, x1)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x2, 480, x1)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x2, 488, x1)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x2, 496, x1)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x2, 504, x1)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x2, 512, x1)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x2, 520, x1)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x2, 528, x1)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x2, 536, x1)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x2, 544, x1)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x2, 552, x1)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x2, 560, x1)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x2, 568, x1)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x2, 576, x1)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x2, 584, x1)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x2, 592, x1)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x2, 600, x1)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x2, 608, x1)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x2, 616, x1)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x2, 624, x1)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x2, 632, x1)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x2, 640, x1)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x2, 648, x1)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x2, 656, x1)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x2, 664, x1)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x2, 672, x1)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x2, 680, x1)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x2, 688, x1)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x2, 696, x1)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x2, 704, x1)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x2, 712, x1)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x2, 720, x1)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x2, 728, x1)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x2, 736, x1)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x2, 744, x1)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x2, 752, x1)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x2, 760, x1)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x2, 768, x1)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x2, 776, x1)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x2, 784, x1)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x2, 792, x1)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x2, 800, x1)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x2, 808, x1)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x2, 816, x1)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x2, 824, x1)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x2, 832, x1)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x2, 840, x1)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x2, 848, x1)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x2, 856, x1)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x2, 864, x1)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x2, 872, x1)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x2, 880, x1)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x2, 888, x1)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x2, 896, x1)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x2, 904, x1)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x2, 912, x1)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x2, 920, x1)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x2, 928, x1)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x2, 936, x1)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x2, 944, x1)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x2, 952, x1)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x2, 960, x1)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x2, 968, x1)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x2, 976, x1)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x2, 984, x1)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x2, 992, x1)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x2, 1000, x1)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x2, 1008, x1)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x2, 1016, x1)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x2, 1024, x1)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x2, 1032, x1)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x2, 1040, x1)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x2, 1048, x1)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x2, 1056, x1)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x2, 1064, x1)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x2, 1072, x1)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x2, 1080, x1)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x2, 1088, x1)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x2, 1096, x1)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x2, 1104, x1)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x2, 1112, x1)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x2, 1120, x1)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x2, 1128, x1)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x2, 1136, x1)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x2, 1144, x1)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x2, 1152, x1)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x2, 1160, x1)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x2, 1168, x1)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x2, 1176, x1)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x2, 1184, x1)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x2, 1192, x1)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x2, 1200, x1)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x2, 1208, x1)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x2, 1216, x1)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x2, 1224, x1)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x2, 1232, x1)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x2, 1240, x1)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x2, 1248, x1)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x2, 1256, x1)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x2, 1264, x1)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x2, 1272, x1)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x2, 1280, x1)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x2, 1288, x1)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x2, 1296, x1)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x2, 1304, x1)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x2, 1312, x1)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x2, 1320, x1)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x2, 1328, x1)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x2, 1336, x1)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x2, 1344, x1)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x2, 1352, x1)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x2, 1360, x1)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x2, 1368, x1)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x2, 1376, x1)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x2, 1384, x1)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x2, 1392, x1)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x2, 1400, x1)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x2, 1408, x1)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x2, 1416, x1)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x2, 1424, x1)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x2, 1432, x1)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x2, 1440, x1)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x2, 1448, x1)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x2, 1456, x1)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x2, 1464, x1)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x2, 1472, x1)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x2, 1480, x1)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x2, 1488, x1)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x2, 1496, x1)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x2, 1504, x1)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x2, 1512, x1)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x2, 1520, x1)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x2, 1528, x1)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x2, 1536, x1)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x2, 1544, x1)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x2, 1552, x1)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x2, 1560, x1)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x2, 1568, x1)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x2, 1576, x1)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x2, 1584, x1)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x2, 1592, x1)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x2, 1600, x1)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x2, 1608, x1)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x2, 1616, x1)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x2, 1624, x1)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x2, 1632, x1)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x2, 1640, x1)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x2, 1648, x1)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x2, 1656, x1)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x2, 1664, x1)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x2, 1672, x1)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x2, 1680, x1)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x2, 1688, x1)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x2, 1696, x1)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x2, 1704, x1)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x2, 1712, x1)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x2, 1720, x1)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x2, 1728, x1)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x2, 1736, x1)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x2, 1744, x1)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x2, 1752, x1)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x2, 1760, x1)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x2, 1768, x1)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x2, 1776, x1)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x2, 1784, x1)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x2, 1792, x1)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x2, 1800, x1)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x2, 1808, x1)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x2, 1816, x1)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x2, 1824, x1)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x2, 1832, x1)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x2, 1840, x1)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x2, 1848, x1)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x2, 1856, x1)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x2, 1864, x1)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x2, 1872, x1)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x2, 1880, x1)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x2, 1888, x1)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x2, 1896, x1)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x2, 1904, x1)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x2, 1912, x1)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x2, 1920, x1)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x2, 1928, x1)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x2, 1936, x1)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x2, 1944, x1)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x2, 1952, x1)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x2, 1960, x1)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x2, 1968, x1)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x2, 1976, x1)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x2, 1984, x1)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x2, 1992, x1)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x2, 2000, x1)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x2, 2008, x1)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x2, 2016, x1)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x2, 2024, x1)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x2, 2032, x1)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x2, 2040, x1)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x2, 0, x1)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x2, 8, x1)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x2, 16, x1)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x2, 24, x1)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x2, 32, x1)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x2, 40, x1)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x2, 48, x1)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x2, 56, x1)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x2, 64, x1)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x2, 72, x1)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x2, 80, x1)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x2, 88, x1)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x2, 96, x1)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x2, 104, x1)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x2, 112, x1)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x2, 120, x1)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x2, 128, x1)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x2, 136, x1)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x2, 144, x1)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x2, 152, x1)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x2, 160, x1)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x2, 168, x1)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x2, 176, x1)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x2, 184, x1)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x2, 192, x1)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x2, 200, x1)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x2, 208, x1)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x2, 216, x1)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x2, 224, x1)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x2, 232, x1)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x2, 240, x1)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x2, 248, x1)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x2, 256, x1)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x2, 264, x1)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x2, 272, x1)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x2, 280, x1)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x2, 288, x1)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x2, 296, x1)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x2, 304, x1)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x2, 312, x1)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x2, 320, x1)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x2, 328, x1)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x2, 336, x1)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x2, 344, x1)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x2, 352, x1)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x2, 360, x1)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x2, 368, x1)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x2, 376, x1)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x2, 384, x1)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x2, 392, x1)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x2, 400, x1)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x2, 408, x1)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x2, 416, x1)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x2, 424, x1)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x2, 432, x1)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x2, 440, x1)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x2, 448, x1)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x2, 456, x1)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x2, 464, x1)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x2, 472, x1)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x2, 480, x1)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x2, 488, x1)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x2, 496, x1)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x2, 504, x1)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x2, 512, x1)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x2, 520, x1)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x2, 528, x1)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x2, 536, x1)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x2, 544, x1)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x2, 552, x1)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x2, 560, x1)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x2, 568, x1)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x2, 576, x1)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x2, 584, x1)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x2, 592, x1)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x2, 600, x1)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x2, 608, x1)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x2, 616, x1)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x2, 624, x1)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x2, 632, x1)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x2, 640, x1)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x2, 648, x1)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x2, 656, x1)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x2, 664, x1)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x2, 672, x1)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x2, 680, x1)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x2, 688, x1)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x2, 696, x1)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x2, 704, x1)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x2, 712, x1)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x2, 720, x1)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x2, 728, x1)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x2, 736, x1)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x2, 744, x1)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x2, 752, x1)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x2, 760, x1)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x2, 768, x1)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x2, 776, x1)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x2, 784, x1)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x2, 792, x1)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x2, 800, x1)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x2, 808, x1)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x2, 816, x1)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x2, 824, x1)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x2, 832, x1)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x2, 840, x1)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x2, 848, x1)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x2, 856, x1)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x2, 864, x1)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x2, 872, x1)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x2, 880, x1)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x2, 888, x1)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x2, 896, x1)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x2, 904, x1)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x2, 912, x1)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x2, 920, x1)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x2, 928, x1)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x2, 936, x1)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x2, 944, x1)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x2, 952, x1)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x2, 960, x1)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x2, 968, x1)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x2, 976, x1)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x2, 984, x1)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x2, 992, x1)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x2, 1000, x1)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x2, 1008, x1)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x2, 1016, x1)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x2, 1024, x1)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x2, 1032, x1)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x2, 1040, x1)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x2, 1048, x1)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x2, 1056, x1)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x2, 1064, x1)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x2, 1072, x1)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x2, 1080, x1)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x2, 1088, x1)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x2, 1096, x1)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x2, 1104, x1)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x2, 1112, x1)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x2, 1120, x1)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x2, 1128, x1)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x2, 1136, x1)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x2, 1144, x1)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x2, 1152, x1)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x2, 1160, x1)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x2, 1168, x1)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x2, 1176, x1)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x2, 1184, x1)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x2, 1192, x1)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x2, 1200, x1)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x2, 1208, x1)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x2, 1216, x1)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x2, 1224, x1)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x2, 1232, x1)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x2, 1240, x1)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x2, 1248, x1)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x2, 1256, x1)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x2, 1264, x1)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x2, 1272, x1)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x2, 1280, x1)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x2, 1288, x1)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x2, 1296, x1)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x2, 1304, x1)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x2, 1312, x1)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x2, 1320, x1)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x2, 1328, x1)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x2, 1336, x1)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x2, 1344, x1)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x2, 1352, x1)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x2, 1360, x1)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x2, 1368, x1)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x2, 1376, x1)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x2, 1384, x1)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x2, 1392, x1)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x2, 1400, x1)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x2, 1408, x1)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x2, 1416, x1)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x2, 1424, x1)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x2, 1432, x1)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x2, 1440, x1)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x2, 1448, x1)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x2, 1456, x1)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x2, 1464, x1)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x2, 1472, x1)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x2, 1480, x1)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x2, 1488, x1)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x2, 1496, x1)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x2, 1504, x1)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x2, 1512, x1)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x2, 1520, x1)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x2, 1528, x1)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x2, 1536, x1)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x2, 1544, x1)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x2, 1552, x1)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x2, 1560, x1)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x2, 1568, x1)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x2, 1576, x1)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x2, 1584, x1)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x2, 1592, x1)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x2, 1600, x1)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x2, 1608, x1)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x2, 1616, x1)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x2, 1624, x1)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x2, 1632, x1)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x2, 1640, x1)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x2, 1648, x1)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x2, 1656, x1)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x2, 1664, x1)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x2, 1672, x1)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x2, 1680, x1)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x2, 1688, x1)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x2, 1696, x1)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x2, 1704, x1)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x2, 1712, x1)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x2, 1720, x1)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x2, 1728, x1)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x2, 1736, x1)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x2, 1744, x1)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x2, 1752, x1)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x2, 1760, x1)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x2, 1768, x1)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x2, 1776, x1)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x2, 1784, x1)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x2, 1792, x1)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x2, 1800, x1)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x2, 1808, x1)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x2, 1816, x1)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x2, 1824, x1)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x2, 1832, x1)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x2, 1840, x1)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x2, 1848, x1)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x2, 1856, x1)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x2, 1864, x1)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x2, 1872, x1)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x2, 1880, x1)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x2, 1888, x1)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x2, 1896, x1)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x2, 1904, x1)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x2, 1912, x1)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x2, 1920, x1)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x2, 1928, x1)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x2, 1936, x1)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x2, 1944, x1)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x2, 1952, x1)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x2, 1960, x1)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x2, 1968, x1)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packu ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(packu, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x2, 1976, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 248*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S
new file mode 100644
index 000000000..84bc2ca74
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packuw-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the packuw instruction of the RISC-V  extension for the packuw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",packuw)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",packuw)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",packuw)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",packuw)
+
+RVTEST_SIGBASE( x12,signature_x12_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x9, rs2==x9, rd==x27, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packuw ; op1:x9; op2:x9; dest:x27; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(packuw, x27, x9, x9, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x12, 0, x16)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x25, rs2==x25, rd==x25, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packuw ; op1:x25; op2:x25; dest:x25; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(packuw, x25, x25, x25, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x12, 8, x16)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x27, rd==x13, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: packuw ; op1:x10; op2:x27; dest:x13; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(packuw, x13, x10, x27, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x12, 16, x16)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x30, rs2==x3, rd==x30, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: packuw ; op1:x30; op2:x3; dest:x30; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(packuw, x30, x30, x3, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x12, 24, x16)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x27, rs2==x2, rd==x2, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: packuw ; op1:x27; op2:x2; dest:x2; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(packuw, x2, x27, x2, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x12, 32, x16)
+
+inst_5:
+// rs1==x5, rs2==x0, rd==x9, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: packuw ; op1:x5; op2:x0; dest:x9; op1val:0xd50bd94a392e6fa3;  op2val:0x0
+TEST_RR_OP(packuw, x9, x5, x0, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x0, x12, 40, x16)
+
+inst_6:
+// rs1==x3, rs2==x4, rd==x1, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: packuw ; op1:x3; op2:x4; dest:x1; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(packuw, x1, x3, x4, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x12, 48, x16)
+
+inst_7:
+// rs1==x1, rs2==x18, rd==x10, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: packuw ; op1:x1; op2:x18; dest:x10; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(packuw, x10, x1, x18, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x12, 56, x16)
+
+inst_8:
+// rs1==x24, rs2==x7, rd==x17, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: packuw ; op1:x24; op2:x7; dest:x17; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(packuw, x17, x24, x7, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x12, 64, x16)
+
+inst_9:
+// rs1==x13, rs2==x26, rd==x31, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: packuw ; op1:x13; op2:x26; dest:x31; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(packuw, x31, x13, x26, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x12, 72, x16)
+
+inst_10:
+// rs1==x14, rs2==x1, rd==x7, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: packuw ; op1:x14; op2:x1; dest:x7; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(packuw, x7, x14, x1, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x12, 80, x16)
+
+inst_11:
+// rs1==x31, rs2==x30, rd==x29, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packuw ; op1:x31; op2:x30; dest:x29; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(packuw, x29, x31, x30, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x12, 88, x16)
+
+inst_12:
+// rs1==x29, rs2==x17, rd==x20, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: packuw ; op1:x29; op2:x17; dest:x20; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(packuw, x20, x29, x17, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x12, 96, x16)
+
+inst_13:
+// rs1==x11, rs2==x5, rd==x14, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: packuw ; op1:x11; op2:x5; dest:x14; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(packuw, x14, x11, x5, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x12, 104, x16)
+
+inst_14:
+// rs1==x26, rs2==x8, rd==x5, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: packuw ; op1:x26; op2:x8; dest:x5; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(packuw, x5, x26, x8, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x12, 112, x16)
+
+inst_15:
+// rs1==x28, rs2==x13, rd==x23, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: packuw ; op1:x28; op2:x13; dest:x23; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(packuw, x23, x28, x13, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x12, 120, x16)
+
+inst_16:
+// rs1==x15, rs2==x21, rd==x6, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: packuw ; op1:x15; op2:x21; dest:x6; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(packuw, x6, x15, x21, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x12, 128, x16)
+
+inst_17:
+// rs1==x16, rs2==x10, rd==x8, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: packuw ; op1:x16; op2:x10; dest:x8; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(packuw, x8, x16, x10, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x12, 136, x5)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_18:
+// rs1==x4, rs2==x31, rd==x3, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: packuw ; op1:x4; op2:x31; dest:x3; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(packuw, x3, x4, x31, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x1, 0, x5)
+
+inst_19:
+// rs1==x2, rs2==x29, rd==x22, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: packuw ; op1:x2; op2:x29; dest:x22; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(packuw, x22, x2, x29, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x1, 8, x5)
+
+inst_20:
+// rs1==x7, rs2==x15, rd==x16, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: packuw ; op1:x7; op2:x15; dest:x16; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(packuw, x16, x7, x15, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x1, 16, x5)
+
+inst_21:
+// rs1==x17, rs2==x19, rd==x24, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: packuw ; op1:x17; op2:x19; dest:x24; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(packuw, x24, x17, x19, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x1, 24, x5)
+
+inst_22:
+// rs1==x21, rs2==x20, rd==x28, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: packuw ; op1:x21; op2:x20; dest:x28; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(packuw, x28, x21, x20, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x1, 32, x5)
+
+inst_23:
+// rs1==x8, rs2==x11, rd==x19, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: packuw ; op1:x8; op2:x11; dest:x19; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(packuw, x19, x8, x11, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x1, 40, x5)
+
+inst_24:
+// rs1==x6, rs2==x16, rd==x26, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: packuw ; op1:x6; op2:x16; dest:x26; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(packuw, x26, x6, x16, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x1, 48, x5)
+
+inst_25:
+// rs1==x22, rs2==x6, rd==x12, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: packuw ; op1:x22; op2:x6; dest:x12; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(packuw, x12, x22, x6, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x1, 56, x5)
+
+inst_26:
+// rs1==x23, rs2==x22, rd==x11, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: packuw ; op1:x23; op2:x22; dest:x11; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(packuw, x11, x23, x22, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x1, 64, x5)
+
+inst_27:
+// rs1==x18, rs2==x12, rd==x21, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: packuw ; op1:x18; op2:x12; dest:x21; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(packuw, x21, x18, x12, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x1, 72, x5)
+
+inst_28:
+// rs1==x0, rs2==x24, rd==x15, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: packuw ; op1:x0; op2:x24; dest:x15; op1val:0x0;  op2val:0x60c9f22000000000
+TEST_RR_OP(packuw, x15, x0, x24, 0x0000000000000000, 0x0, 0x60c9f22000000000, x1, 80, x5)
+
+inst_29:
+// rs1==x19, rs2==x23, rd==x4, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: packuw ; op1:x19; op2:x23; dest:x4; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(packuw, x4, x19, x23, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x1, 88, x5)
+
+inst_30:
+// rs1==x12, rs2==x14, rd==x0, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: packuw ; op1:x12; op2:x14; dest:x0; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(packuw, x0, x12, x14, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 96, x5)
+
+inst_31:
+// rs1==x20, rs2==x28, rd==x18, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: packuw ; op1:x20; op2:x28; dest:x18; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(packuw, x18, x20, x28, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x1, 104, x5)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x1, 112, x5)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 120, x5)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 128, x5)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 136, x5)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 144, x5)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 152, x5)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 160, x5)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 168, x5)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 176, x5)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 184, x5)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 192, x5)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 200, x5)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 208, x5)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 216, x5)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 224, x5)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 232, x5)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 240, x5)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 248, x5)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 256, x5)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 264, x5)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 272, x5)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 280, x5)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 288, x5)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 296, x5)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 304, x5)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 312, x5)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 320, x5)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 328, x5)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 336, x5)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 344, x5)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 352, x5)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 360, x5)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 368, x5)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 376, x5)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 384, x5)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 392, x5)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 400, x5)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 408, x5)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 416, x5)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 424, x5)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 432, x5)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 440, x5)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 448, x5)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 456, x5)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 464, x5)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 472, x5)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 480, x5)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 488, x5)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 496, x5)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 504, x5)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 512, x5)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 520, x5)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 528, x5)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 536, x5)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 544, x5)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 552, x5)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 560, x5)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 568, x5)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 576, x5)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 584, x5)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 592, x5)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 600, x5)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 608, x5)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 616, x5)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 624, x5)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 632, x5)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 640, x5)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 648, x5)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 656, x5)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 664, x5)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 672, x5)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 680, x5)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 688, x5)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 696, x5)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 704, x5)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 712, x5)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 720, x5)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 728, x5)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 736, x5)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 744, x5)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 752, x5)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 760, x5)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 768, x5)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 776, x5)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 784, x5)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 792, x5)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 800, x5)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 808, x5)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 816, x5)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 824, x5)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 832, x5)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 840, x5)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 848, x5)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 856, x5)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 864, x5)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 872, x5)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 880, x5)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 888, x5)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 896, x5)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 904, x5)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 912, x5)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 920, x5)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 928, x5)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 936, x5)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 944, x5)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 952, x5)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 960, x5)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 968, x5)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 976, x5)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 984, x5)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 992, x5)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 1000, x5)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 1008, x5)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 1016, x5)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 1024, x5)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 1032, x5)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 1040, x5)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 1048, x5)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 1056, x5)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 1064, x5)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 1072, x5)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 1080, x5)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 1088, x5)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 1096, x5)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 1104, x5)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 1112, x5)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1120, x5)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1128, x5)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1136, x5)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1144, x5)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1152, x5)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1160, x5)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1168, x5)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1176, x5)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1184, x5)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1192, x5)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1200, x5)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1208, x5)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1216, x5)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1224, x5)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1232, x5)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1240, x5)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1248, x5)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1256, x5)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1264, x5)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1272, x5)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1280, x5)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1288, x5)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1296, x5)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1304, x5)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1312, x5)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1320, x5)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1328, x5)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1336, x5)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1344, x5)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1352, x5)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1360, x5)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1368, x5)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1376, x5)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1384, x5)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1392, x5)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1400, x5)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1408, x5)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1416, x5)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1424, x5)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1432, x5)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1440, x5)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1448, x5)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1456, x5)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1464, x5)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1472, x5)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1480, x5)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1488, x5)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1496, x5)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1504, x5)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1512, x5)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1520, x5)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1528, x5)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1536, x5)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1544, x5)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1552, x5)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1560, x5)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1568, x5)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1576, x5)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1584, x5)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1592, x5)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1600, x5)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1608, x5)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1616, x5)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1624, x5)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1632, x5)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1640, x5)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1648, x5)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1656, x5)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1664, x5)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1672, x5)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1680, x5)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1688, x5)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1696, x5)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1704, x5)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1712, x5)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1720, x5)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1728, x5)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1736, x5)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1744, x5)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1752, x5)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1760, x5)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1768, x5)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1776, x5)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1784, x5)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1792, x5)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1800, x5)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1808, x5)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1816, x5)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1824, x5)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1832, x5)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1840, x5)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1848, x5)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1856, x5)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1864, x5)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1872, x5)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1880, x5)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1888, x5)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1896, x5)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1904, x5)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1912, x5)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1920, x5)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1928, x5)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1936, x5)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1944, x5)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1952, x5)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1960, x5)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1968, x5)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1976, x5)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1984, x5)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1992, x5)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 2000, x5)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 2008, x5)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 2016, x5)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 2024, x5)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 2032, x5)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 2040, x5)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 0, x5)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 8, x5)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 16, x5)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 24, x5)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 32, x5)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 40, x5)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 48, x5)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 56, x5)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 64, x5)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 72, x5)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 80, x5)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 88, x5)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 96, x5)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 104, x5)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 112, x5)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 120, x5)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 128, x5)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 136, x5)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 144, x5)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 152, x5)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 160, x5)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 168, x5)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 176, x5)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 184, x5)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 192, x5)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 200, x5)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 208, x5)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 216, x5)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 224, x5)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 232, x5)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 240, x5)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 248, x5)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 256, x5)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 264, x5)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 272, x5)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 280, x5)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 288, x5)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 296, x5)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 304, x5)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 312, x5)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 320, x5)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 328, x5)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 336, x5)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 344, x5)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 352, x5)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 360, x5)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 368, x5)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 376, x5)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 384, x5)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 392, x5)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 400, x5)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 408, x5)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 416, x5)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 424, x5)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 432, x5)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 440, x5)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 448, x5)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 456, x5)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 464, x5)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 472, x5)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 480, x5)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 488, x5)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 496, x5)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 504, x5)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 512, x5)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 520, x5)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 528, x5)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 536, x5)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 544, x5)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 552, x5)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 560, x5)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 568, x5)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 576, x5)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 584, x5)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 592, x5)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 600, x5)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 608, x5)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 616, x5)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 624, x5)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 632, x5)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 640, x5)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 648, x5)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 656, x5)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 664, x5)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 672, x5)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 680, x5)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 688, x5)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 696, x5)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 704, x5)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 712, x5)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 720, x5)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 728, x5)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 736, x5)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 744, x5)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 752, x5)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 760, x5)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 768, x5)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 776, x5)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 784, x5)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 792, x5)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 800, x5)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 808, x5)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 816, x5)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 824, x5)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 832, x5)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 840, x5)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 848, x5)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 856, x5)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 864, x5)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 872, x5)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 880, x5)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 888, x5)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 896, x5)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 904, x5)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 912, x5)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 920, x5)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 928, x5)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 936, x5)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 944, x5)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 952, x5)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 960, x5)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 968, x5)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 976, x5)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 984, x5)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 992, x5)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 1000, x5)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 1008, x5)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 1016, x5)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 1024, x5)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 1032, x5)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 1040, x5)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 1048, x5)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 1056, x5)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 1064, x5)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 1072, x5)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 1080, x5)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 1088, x5)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 1096, x5)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 1104, x5)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 1112, x5)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1120, x5)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1128, x5)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1136, x5)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1144, x5)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1152, x5)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1160, x5)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1168, x5)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1176, x5)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1184, x5)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1192, x5)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1200, x5)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1208, x5)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1216, x5)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1224, x5)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1232, x5)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1240, x5)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1248, x5)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1256, x5)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1264, x5)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1272, x5)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1280, x5)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1288, x5)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1296, x5)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1304, x5)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1312, x5)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1320, x5)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1328, x5)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1336, x5)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1344, x5)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1352, x5)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1360, x5)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1368, x5)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1376, x5)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1384, x5)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1392, x5)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1400, x5)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1408, x5)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1416, x5)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1424, x5)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1432, x5)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1440, x5)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1448, x5)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1456, x5)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1464, x5)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1472, x5)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1480, x5)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1488, x5)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1496, x5)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1504, x5)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1512, x5)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1520, x5)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1528, x5)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1536, x5)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1544, x5)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1552, x5)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1560, x5)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1568, x5)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1576, x5)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1584, x5)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1592, x5)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1600, x5)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1608, x5)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1616, x5)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1624, x5)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1632, x5)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1640, x5)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1648, x5)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1656, x5)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1664, x5)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1672, x5)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1680, x5)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1688, x5)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1696, x5)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1704, x5)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1712, x5)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1720, x5)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1728, x5)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1736, x5)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1744, x5)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1752, x5)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1760, x5)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1768, x5)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1776, x5)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1784, x5)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1792, x5)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1800, x5)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1808, x5)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1816, x5)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1824, x5)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1832, x5)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1840, x5)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1848, x5)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1856, x5)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1864, x5)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1872, x5)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1880, x5)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1888, x5)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1896, x5)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1904, x5)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1912, x5)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1920, x5)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1928, x5)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1936, x5)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1944, x5)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1952, x5)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1960, x5)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1968, x5)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1976, x5)
+
+inst_522:
+// rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x1, 1984, x5)
+
+inst_523:
+// rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x1, 1992, x5)
+
+inst_524:
+// rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: packuw ; op1:x10; op2:x11; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(packuw, x12, x10, x11, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x1, 2000, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x12_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x12_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 251*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S
new file mode 100644
index 000000000..842dead52
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/packw-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the packw instruction of the RISC-V  extension for the packw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",packw)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",packw)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",packw)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",packw)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x1, rs2==x1, rd==x12, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packw ; op1:x1; op2:x1; dest:x12; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(packw, x12, x1, x1, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x8, 0, x21)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x19, rs2==x19, rd==x19, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packw ; op1:x19; op2:x19; dest:x19; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(packw, x19, x19, x19, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x8, 8, x21)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x31, rs2==x9, rd==x0, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: packw ; op1:x31; op2:x9; dest:x0; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(packw, x0, x31, x9, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x8, 16, x21)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x5, rs2==x25, rd==x5, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: packw ; op1:x5; op2:x25; dest:x5; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(packw, x5, x5, x25, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x8, 24, x21)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x29, rs2==x23, rd==x23, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: packw ; op1:x29; op2:x23; dest:x23; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(packw, x23, x29, x23, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x8, 32, x21)
+
+inst_5:
+// rs1==x28, rs2==x2, rd==x20, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: packw ; op1:x28; op2:x2; dest:x20; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(packw, x20, x28, x2, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x8, 40, x21)
+
+inst_6:
+// rs1==x3, rs2==x16, rd==x9, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: packw ; op1:x3; op2:x16; dest:x9; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(packw, x9, x3, x16, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x8, 48, x21)
+
+inst_7:
+// rs1==x12, rs2==x11, rd==x15, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: packw ; op1:x12; op2:x11; dest:x15; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(packw, x15, x12, x11, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x8, 56, x21)
+
+inst_8:
+// rs1==x22, rs2==x18, rd==x29, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: packw ; op1:x22; op2:x18; dest:x29; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(packw, x29, x22, x18, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x8, 64, x21)
+
+inst_9:
+// rs1==x4, rs2==x15, rd==x22, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: packw ; op1:x4; op2:x15; dest:x22; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(packw, x22, x4, x15, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x8, 72, x21)
+
+inst_10:
+// rs1==x7, rs2==x4, rd==x18, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: packw ; op1:x7; op2:x4; dest:x18; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(packw, x18, x7, x4, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x8, 80, x21)
+
+inst_11:
+// rs1==x2, rs2==x0, rd==x24, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packw ; op1:x2; op2:x0; dest:x24; op1val:0xfd8bf41246e4abd8;  op2val:0x0
+TEST_RR_OP(packw, x24, x2, x0, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x0, x8, 88, x21)
+
+inst_12:
+// rs1==x24, rs2==x5, rd==x30, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: packw ; op1:x24; op2:x5; dest:x30; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(packw, x30, x24, x5, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x8, 96, x21)
+
+inst_13:
+// rs1==x13, rs2==x24, rd==x17, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: packw ; op1:x13; op2:x24; dest:x17; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(packw, x17, x13, x24, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x8, 104, x21)
+
+inst_14:
+// rs1==x11, rs2==x7, rd==x4, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: packw ; op1:x11; op2:x7; dest:x4; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(packw, x4, x11, x7, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x8, 112, x21)
+
+inst_15:
+// rs1==x14, rs2==x6, rd==x10, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: packw ; op1:x14; op2:x6; dest:x10; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(packw, x10, x14, x6, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x8, 120, x21)
+
+inst_16:
+// rs1==x10, rs2==x30, rd==x26, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: packw ; op1:x10; op2:x30; dest:x26; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(packw, x26, x10, x30, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x8, 128, x5)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_17:
+// rs1==x26, rs2==x20, rd==x13, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: packw ; op1:x26; op2:x20; dest:x13; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(packw, x13, x26, x20, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x4, 0, x5)
+
+inst_18:
+// rs1==x0, rs2==x26, rd==x7, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: packw ; op1:x0; op2:x26; dest:x7; op1val:0x0;  op2val:0x3b0b800000000000
+TEST_RR_OP(packw, x7, x0, x26, 0x0000000000000000, 0x0, 0x3b0b800000000000, x4, 8, x5)
+
+inst_19:
+// rs1==x16, rs2==x31, rd==x8, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: packw ; op1:x16; op2:x31; dest:x8; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(packw, x8, x16, x31, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x4, 16, x5)
+
+inst_20:
+// rs1==x18, rs2==x27, rd==x31, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: packw ; op1:x18; op2:x27; dest:x31; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(packw, x31, x18, x27, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x4, 24, x5)
+
+inst_21:
+// rs1==x23, rs2==x12, rd==x11, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: packw ; op1:x23; op2:x12; dest:x11; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(packw, x11, x23, x12, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x4, 32, x5)
+
+inst_22:
+// rs1==x6, rs2==x10, rd==x16, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: packw ; op1:x6; op2:x10; dest:x16; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(packw, x16, x6, x10, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x4, 40, x5)
+
+inst_23:
+// rs1==x8, rs2==x13, rd==x25, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: packw ; op1:x8; op2:x13; dest:x25; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(packw, x25, x8, x13, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x4, 48, x5)
+
+inst_24:
+// rs1==x15, rs2==x17, rd==x21, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: packw ; op1:x15; op2:x17; dest:x21; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(packw, x21, x15, x17, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x4, 56, x5)
+
+inst_25:
+// rs1==x17, rs2==x14, rd==x3, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: packw ; op1:x17; op2:x14; dest:x3; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(packw, x3, x17, x14, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x4, 64, x5)
+
+inst_26:
+// rs1==x25, rs2==x22, rd==x6, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: packw ; op1:x25; op2:x22; dest:x6; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(packw, x6, x25, x22, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x4, 72, x5)
+
+inst_27:
+// rs1==x20, rs2==x8, rd==x1, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: packw ; op1:x20; op2:x8; dest:x1; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(packw, x1, x20, x8, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x4, 80, x5)
+
+inst_28:
+// rs1==x21, rs2==x28, rd==x27, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: packw ; op1:x21; op2:x28; dest:x27; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(packw, x27, x21, x28, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x4, 88, x5)
+
+inst_29:
+// rs1==x27, rs2==x3, rd==x2, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: packw ; op1:x27; op2:x3; dest:x2; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(packw, x2, x27, x3, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x4, 96, x5)
+
+inst_30:
+// rs1==x30, rs2==x29, rd==x28, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: packw ; op1:x30; op2:x29; dest:x28; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(packw, x28, x30, x29, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x4, 104, x5)
+
+inst_31:
+// rs1==x9, rs2==x21, rd==x14, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: packw ; op1:x9; op2:x21; dest:x14; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(packw, x14, x9, x21, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x4, 112, x5)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x4, 120, x1)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x4, 128, x1)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x4, 136, x1)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x4, 144, x1)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x4, 152, x1)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x4, 160, x1)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x4, 168, x1)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x4, 176, x1)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x4, 184, x1)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x4, 192, x1)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x4, 200, x1)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x4, 208, x1)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x4, 216, x1)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x4, 224, x1)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x4, 232, x1)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x4, 240, x1)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x4, 248, x1)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x4, 256, x1)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x4, 264, x1)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x4, 272, x1)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x4, 280, x1)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x4, 288, x1)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x4, 296, x1)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x4, 304, x1)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x4, 312, x1)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x4, 320, x1)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x4, 328, x1)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x4, 336, x1)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x4, 344, x1)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x4, 352, x1)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x4, 360, x1)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x4, 368, x1)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x4, 376, x1)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x4, 384, x1)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x4, 392, x1)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x4, 400, x1)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x4, 408, x1)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x4, 416, x1)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x4, 424, x1)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x4, 432, x1)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x4, 440, x1)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x4, 448, x1)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x4, 456, x1)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x4, 464, x1)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x4, 472, x1)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x4, 480, x1)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x4, 488, x1)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x4, 496, x1)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x4, 504, x1)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x4, 512, x1)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x4, 520, x1)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x4, 528, x1)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x4, 536, x1)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x4, 544, x1)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x4, 552, x1)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x4, 560, x1)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x4, 568, x1)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x4, 576, x1)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x4, 584, x1)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x4, 592, x1)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x4, 600, x1)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x4, 608, x1)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x4, 616, x1)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x4, 624, x1)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x4, 632, x1)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x4, 640, x1)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x4, 648, x1)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x4, 656, x1)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x4, 664, x1)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x4, 672, x1)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x4, 680, x1)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x4, 688, x1)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x4, 696, x1)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x4, 704, x1)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x4, 712, x1)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x4, 720, x1)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x4, 728, x1)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x4, 736, x1)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x4, 744, x1)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x4, 752, x1)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x4, 760, x1)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x4, 768, x1)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x4, 776, x1)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x4, 784, x1)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x4, 792, x1)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x4, 800, x1)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x4, 808, x1)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x4, 816, x1)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x4, 824, x1)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x4, 832, x1)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x4, 840, x1)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x4, 848, x1)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x4, 856, x1)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x4, 864, x1)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x4, 872, x1)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x4, 880, x1)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x4, 888, x1)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x4, 896, x1)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x4, 904, x1)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x4, 912, x1)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x4, 920, x1)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x4, 928, x1)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x4, 936, x1)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x4, 944, x1)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x4, 952, x1)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x4, 960, x1)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x4, 968, x1)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x4, 976, x1)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x4, 984, x1)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x4, 992, x1)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x4, 1000, x1)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x4, 1008, x1)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x4, 1016, x1)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x4, 1024, x1)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x4, 1032, x1)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x4, 1040, x1)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x4, 1048, x1)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x4, 1056, x1)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x4, 1064, x1)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x4, 1072, x1)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x4, 1080, x1)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x4, 1088, x1)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x4, 1096, x1)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x4, 1104, x1)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x4, 1112, x1)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x4, 1120, x1)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x4, 1128, x1)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x4, 1136, x1)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x4, 1144, x1)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x4, 1152, x1)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x4, 1160, x1)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x4, 1168, x1)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x4, 1176, x1)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x4, 1184, x1)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x4, 1192, x1)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x4, 1200, x1)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x4, 1208, x1)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x4, 1216, x1)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x4, 1224, x1)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x4, 1232, x1)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x4, 1240, x1)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x4, 1248, x1)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x4, 1256, x1)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x4, 1264, x1)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x4, 1272, x1)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x4, 1280, x1)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x4, 1288, x1)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x4, 1296, x1)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x4, 1304, x1)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x4, 1312, x1)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x4, 1320, x1)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x4, 1328, x1)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x4, 1336, x1)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x4, 1344, x1)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x4, 1352, x1)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x4, 1360, x1)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x4, 1368, x1)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x4, 1376, x1)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x4, 1384, x1)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x4, 1392, x1)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x4, 1400, x1)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x4, 1408, x1)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x4, 1416, x1)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x4, 1424, x1)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x4, 1432, x1)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x4, 1440, x1)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x4, 1448, x1)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x4, 1456, x1)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x4, 1464, x1)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x4, 1472, x1)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x4, 1480, x1)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x4, 1488, x1)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x4, 1496, x1)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x4, 1504, x1)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x4, 1512, x1)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x4, 1520, x1)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x4, 1528, x1)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x4, 1536, x1)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x4, 1544, x1)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x4, 1552, x1)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x4, 1560, x1)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x4, 1568, x1)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x4, 1576, x1)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x4, 1584, x1)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x4, 1592, x1)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x4, 1600, x1)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x4, 1608, x1)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x4, 1616, x1)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x4, 1624, x1)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x4, 1632, x1)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x4, 1640, x1)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x4, 1648, x1)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x4, 1656, x1)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x4, 1664, x1)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x4, 1672, x1)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x4, 1680, x1)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x4, 1688, x1)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x4, 1696, x1)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x4, 1704, x1)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x4, 1712, x1)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x4, 1720, x1)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x4, 1728, x1)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x4, 1736, x1)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x4, 1744, x1)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x4, 1752, x1)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x4, 1760, x1)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x4, 1768, x1)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x4, 1776, x1)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x4, 1784, x1)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x4, 1792, x1)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x4, 1800, x1)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x4, 1808, x1)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x4, 1816, x1)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x4, 1824, x1)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x4, 1832, x1)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x4, 1840, x1)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x4, 1848, x1)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x4, 1856, x1)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x4, 1864, x1)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x4, 1872, x1)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x4, 1880, x1)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x4, 1888, x1)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x4, 1896, x1)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x4, 1904, x1)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x4, 1912, x1)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x4, 1920, x1)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x4, 1928, x1)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x4, 1936, x1)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x4, 1944, x1)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x4, 1952, x1)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x4, 1960, x1)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x4, 1968, x1)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x4, 1976, x1)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x4, 1984, x1)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x4, 1992, x1)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x4, 2000, x1)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x4, 2008, x1)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x4, 2016, x1)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x4, 2024, x1)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x4, 2032, x1)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x4, 2040, x1)
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x4, 0, x1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x4, 8, x1)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x4, 16, x1)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x4, 24, x1)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x4, 32, x1)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x4, 40, x1)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x4, 48, x1)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x4, 56, x1)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x4, 64, x1)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x4, 72, x1)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x4, 80, x1)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x4, 88, x1)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x4, 96, x1)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x4, 104, x1)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x4, 112, x1)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x4, 120, x1)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x4, 128, x1)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x4, 136, x1)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x4, 144, x1)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x4, 152, x1)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x4, 160, x1)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x4, 168, x1)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x4, 176, x1)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x4, 184, x1)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x4, 192, x1)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x4, 200, x1)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x4, 208, x1)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x4, 216, x1)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x4, 224, x1)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x4, 232, x1)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x4, 240, x1)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x4, 248, x1)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x4, 256, x1)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x4, 264, x1)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x4, 272, x1)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x4, 280, x1)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x4, 288, x1)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x4, 296, x1)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x4, 304, x1)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x4, 312, x1)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x4, 320, x1)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x4, 328, x1)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x4, 336, x1)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x4, 344, x1)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x4, 352, x1)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x4, 360, x1)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x4, 368, x1)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x4, 376, x1)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x4, 384, x1)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x4, 392, x1)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x4, 400, x1)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x4, 408, x1)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x4, 416, x1)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x4, 424, x1)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x4, 432, x1)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x4, 440, x1)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x4, 448, x1)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x4, 456, x1)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x4, 464, x1)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x4, 472, x1)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x4, 480, x1)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x4, 488, x1)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x4, 496, x1)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x4, 504, x1)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x4, 512, x1)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x4, 520, x1)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x4, 528, x1)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x4, 536, x1)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x4, 544, x1)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x4, 552, x1)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x4, 560, x1)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x4, 568, x1)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x4, 576, x1)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x4, 584, x1)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x4, 592, x1)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x4, 600, x1)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x4, 608, x1)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x4, 616, x1)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x4, 624, x1)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x4, 632, x1)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x4, 640, x1)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x4, 648, x1)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x4, 656, x1)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x4, 664, x1)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x4, 672, x1)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x4, 680, x1)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x4, 688, x1)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x4, 696, x1)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x4, 704, x1)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x4, 712, x1)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x4, 720, x1)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x4, 728, x1)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x4, 736, x1)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x4, 744, x1)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x4, 752, x1)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x4, 760, x1)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x4, 768, x1)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x4, 776, x1)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x4, 784, x1)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x4, 792, x1)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x4, 800, x1)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x4, 808, x1)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x4, 816, x1)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x4, 824, x1)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x4, 832, x1)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x4, 840, x1)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x4, 848, x1)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x4, 856, x1)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x4, 864, x1)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x4, 872, x1)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x4, 880, x1)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x4, 888, x1)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x4, 896, x1)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x4, 904, x1)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x4, 912, x1)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x4, 920, x1)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x4, 928, x1)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x4, 936, x1)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x4, 944, x1)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x4, 952, x1)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x4, 960, x1)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x4, 968, x1)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x4, 976, x1)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x4, 984, x1)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x4, 992, x1)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x4, 1000, x1)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x4, 1008, x1)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x4, 1016, x1)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x4, 1024, x1)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x4, 1032, x1)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x4, 1040, x1)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x4, 1048, x1)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x4, 1056, x1)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x4, 1064, x1)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x4, 1072, x1)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x4, 1080, x1)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x4, 1088, x1)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x4, 1096, x1)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x4, 1104, x1)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x4, 1112, x1)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x4, 1120, x1)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x4, 1128, x1)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x4, 1136, x1)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x4, 1144, x1)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x4, 1152, x1)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x4, 1160, x1)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x4, 1168, x1)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x4, 1176, x1)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x4, 1184, x1)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x4, 1192, x1)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x4, 1200, x1)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x4, 1208, x1)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x4, 1216, x1)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x4, 1224, x1)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x4, 1232, x1)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x4, 1240, x1)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x4, 1248, x1)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x4, 1256, x1)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x4, 1264, x1)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x4, 1272, x1)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x4, 1280, x1)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x4, 1288, x1)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x4, 1296, x1)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x4, 1304, x1)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x4, 1312, x1)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x4, 1320, x1)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x4, 1328, x1)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x4, 1336, x1)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x4, 1344, x1)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x4, 1352, x1)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x4, 1360, x1)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x4, 1368, x1)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x4, 1376, x1)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x4, 1384, x1)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x4, 1392, x1)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x4, 1400, x1)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x4, 1408, x1)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x4, 1416, x1)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x4, 1424, x1)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x4, 1432, x1)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x4, 1440, x1)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x4, 1448, x1)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x4, 1456, x1)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x4, 1464, x1)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x4, 1472, x1)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x4, 1480, x1)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x4, 1488, x1)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x4, 1496, x1)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x4, 1504, x1)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x4, 1512, x1)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x4, 1520, x1)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x4, 1528, x1)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x4, 1536, x1)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x4, 1544, x1)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x4, 1552, x1)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x4, 1560, x1)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x4, 1568, x1)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x4, 1576, x1)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x4, 1584, x1)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x4, 1592, x1)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x4, 1600, x1)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x4, 1608, x1)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x4, 1616, x1)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x4, 1624, x1)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x4, 1632, x1)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x4, 1640, x1)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x4, 1648, x1)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x4, 1656, x1)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x4, 1664, x1)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x4, 1672, x1)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x4, 1680, x1)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x4, 1688, x1)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x4, 1696, x1)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x4, 1704, x1)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x4, 1712, x1)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x4, 1720, x1)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x4, 1728, x1)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x4, 1736, x1)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x4, 1744, x1)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x4, 1752, x1)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x4, 1760, x1)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x4, 1768, x1)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x4, 1776, x1)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x4, 1784, x1)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x4, 1792, x1)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x4, 1800, x1)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x4, 1808, x1)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x4, 1816, x1)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x4, 1824, x1)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x4, 1832, x1)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x4, 1840, x1)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x4, 1848, x1)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x4, 1856, x1)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x4, 1864, x1)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x4, 1872, x1)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x4, 1880, x1)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x4, 1888, x1)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x4, 1896, x1)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x4, 1904, x1)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x4, 1912, x1)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x4, 1920, x1)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x4, 1928, x1)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x4, 1936, x1)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x4, 1944, x1)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x4, 1952, x1)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x4, 1960, x1)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x4, 1968, x1)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x4, 1976, x1)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x4, 1984, x1)
+
+inst_522:
+// rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x4, 1992, x1)
+
+inst_523:
+// rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x4, 2000, x1)
+
+inst_524:
+// rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: packw ; op1:x10; op2:x11; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(packw, x12, x10, x11, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x4, 2008, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 252*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S
new file mode 100644
index 000000000..ed52f53dc
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev.b-01.S
@@ -0,0 +1,2161 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the grevi instruction of the RISC-V  extension for the rev.b covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rev.b)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",rev.b)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",rev.b)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",rev.b)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 != rd, rs1==x13, rd==x1, rs1_val == 0xFFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x13; dest:x1; op1val:0xffffffffffffffff;
+li x13, 0xffffffffffffffff
+grevi x1, x13, 7
+sw x1, 0(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x1, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x20, rd==x20, rs1_val == 0x0000000000000000 
+// opcode: grevi ; op1:x20; dest:x20; op1val:0x0;
+li x20, 0x0
+grevi x20, x20, 7
+sw x20, 8(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x20, 0x0000000000000000)
+
+inst_2:
+// rs1==x28, rd==x7, rs1_val == 0x8000000000000000 
+// opcode: grevi ; op1:x28; dest:x7; op1val:0x8000000000000000;
+li x28, 0x8000000000000000
+grevi x7, x28, 7
+sw x7, 16(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x7, 0x0000000000000000)
+
+inst_3:
+// rs1==x0, rd==x10, rs1_val == 0xC000000000000000 
+// opcode: grevi ; op1:x0; dest:x10; op1val:0x0;
+li x0, 0x0
+grevi x10, x0, 7
+sw x10, 24(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x10, 0x0000000000000000)
+
+inst_4:
+// rs1==x2, rd==x26, rs1_val == 0xA000000000000000 
+// opcode: grevi ; op1:x2; dest:x26; op1val:0xa000000000000000;
+li x2, 0xa000000000000000
+grevi x26, x2, 7
+sw x26, 32(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x26, 0x0000000000000000)
+
+inst_5:
+// rs1==x17, rd==x9, rs1_val == 0x9000000000000000 
+// opcode: grevi ; op1:x17; dest:x9; op1val:0x9000000000000000;
+li x17, 0x9000000000000000
+grevi x9, x17, 7
+sw x9, 40(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x9, 0x0000000000000000)
+
+inst_6:
+// rs1==x7, rd==x11, rs1_val == 0x0800000000000000 
+// opcode: grevi ; op1:x7; dest:x11; op1val:0x800000000000000;
+li x7, 0x800000000000000
+grevi x11, x7, 7
+sw x11, 48(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x11, 0x0000000000000000)
+
+inst_7:
+// rs1==x5, rd==x2, rs1_val == 0x2C00000000000000 
+// opcode: grevi ; op1:x5; dest:x2; op1val:0x2c00000000000000;
+li x5, 0x2c00000000000000
+grevi x2, x5, 7
+sw x2, 56(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x2, 0x0000000000000000)
+
+inst_8:
+// rs1==x9, rd==x23, rs1_val == 0x9600000000000000 
+// opcode: grevi ; op1:x9; dest:x23; op1val:0x9600000000000000;
+li x9, 0x9600000000000000
+grevi x23, x9, 7
+sw x23, 64(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x23, 0x0000000000000000)
+
+inst_9:
+// rs1==x31, rd==x8, rs1_val == 0x0100000000000000 
+// opcode: grevi ; op1:x31; dest:x8; op1val:0x100000000000000;
+li x31, 0x100000000000000
+grevi x8, x31, 7
+sw x8, 72(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x8, 0x0000000000000000)
+
+inst_10:
+// rs1==x11, rd==x30, rs1_val == 0x9480000000000000 
+// opcode: grevi ; op1:x11; dest:x30; op1val:0x9480000000000000;
+li x11, 0x9480000000000000
+grevi x30, x11, 7
+sw x30, 80(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x30, 0x0000000000000000)
+
+inst_11:
+// rs1==x15, rd==x24, rs1_val == 0xB5C0000000000000 
+// opcode: grevi ; op1:x15; dest:x24; op1val:0xb5c0000000000000;
+li x15, 0xb5c0000000000000
+grevi x24, x15, 7
+sw x24, 88(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x24, 0x0000000000000000)
+
+inst_12:
+// rs1==x24, rd==x0, rs1_val == 0x07A0000000000000 
+// opcode: grevi ; op1:x24; dest:x0; op1val:0x7a0000000000000;
+li x24, 0x7a0000000000000
+grevi x0, x24, 7
+sw x0, 96(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x0, 0x0000000000000000)
+
+inst_13:
+// rs1==x16, rd==x15, rs1_val == 0x77B0000000000000 
+// opcode: grevi ; op1:x16; dest:x15; op1val:0x77b0000000000000;
+li x16, 0x77b0000000000000
+grevi x15, x16, 7
+sw x15, 104(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x15, 0x0000000000000000)
+
+inst_14:
+// rs1==x26, rd==x19, rs1_val == 0xF128000000000000 
+// opcode: grevi ; op1:x26; dest:x19; op1val:0xf128000000000000;
+li x26, 0xf128000000000000
+grevi x19, x26, 7
+sw x19, 112(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x19, 0x0000000000000000)
+
+inst_15:
+// rs1==x18, rd==x13, rs1_val == 0xC0E4000000000000 
+// opcode: grevi ; op1:x18; dest:x13; op1val:0xc0e4000000000000;
+li x18, 0xc0e4000000000000
+grevi x13, x18, 7
+sw x13, 120(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x13, 0x0000000000000000)
+
+inst_16:
+// rs1==x4, rd==x16, rs1_val == 0xDC52000000000000 
+// opcode: grevi ; op1:x4; dest:x16; op1val:0xdc52000000000000;
+li x4, 0xdc52000000000000
+grevi x16, x4, 7
+sw x16, 128(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x16, 0x0000000000000000)
+
+inst_17:
+// rs1==x29, rd==x3, rs1_val == 0x0B3D000000000000 
+// opcode: grevi ; op1:x29; dest:x3; op1val:0xb3d000000000000;
+li x29, 0xb3d000000000000
+grevi x3, x29, 7
+sw x3, 136(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x3, 0x0000000000000000)
+
+inst_18:
+// rs1==x14, rd==x22, rs1_val == 0xB154800000000000 
+// opcode: grevi ; op1:x14; dest:x22; op1val:0xb154800000000000;
+li x14, 0xb154800000000000
+grevi x22, x14, 7
+sw x22, 144(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x22, 0x0000000000000000)
+
+inst_19:
+// rs1==x1, rd==x4, rs1_val == 0x2609C00000000000 
+// opcode: grevi ; op1:x1; dest:x4; op1val:0x2609c00000000000;
+li x1, 0x2609c00000000000
+grevi x4, x1, 7
+sw x4, 152(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x4, 0x0000000000000000)
+
+inst_20:
+// rs1==x19, rd==x14, rs1_val == 0xCF5BE00000000000 
+// opcode: grevi ; op1:x19; dest:x14; op1val:0xcf5be00000000000;
+li x19, 0xcf5be00000000000
+grevi x14, x19, 7
+sw x14, 160(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x14, 0x0000000000000000)
+
+inst_21:
+// rs1==x10, rd==x12, rs1_val == 0x3ED0700000000000 
+// opcode: grevi ; op1:x10; dest:x12; op1val:0x3ed0700000000000;
+li x10, 0x3ed0700000000000
+grevi x12, x10, 7
+sw x12, 168(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x21, x12, 0x0000000000000000)
+
+inst_22:
+// rs1==x22, rd==x31, rs1_val == 0x6BDED80000000000 
+// opcode: grevi ; op1:x22; dest:x31; op1val:0x6bded80000000000;
+li x22, 0x6bded80000000000
+grevi x31, x22, 7
+sw x31, 176(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000000000000)
+
+inst_23:
+// rs1==x3, rd==x29, rs1_val == 0x4637640000000000 
+// opcode: grevi ; op1:x3; dest:x29; op1val:0x4637640000000000;
+li x3, 0x4637640000000000
+grevi x29, x3, 7
+sw x29, 184(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x29, 0x0000000000000000)
+
+inst_24:
+// rs1==x8, rd==x21, rs1_val == 0x7239560000000000 
+// opcode: grevi ; op1:x8; dest:x21; op1val:0x7239560000000000;
+li x8, 0x7239560000000000
+grevi x21, x8, 7
+sw x21, 192(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_25:
+// rs1==x21, rd==x6, rs1_val == 0x8864C10000000000 
+// opcode: grevi ; op1:x21; dest:x6; op1val:0x8864c10000000000;
+li x21, 0x8864c10000000000
+grevi x6, x21, 7
+sw x6, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x6, 0x0000000000000000)
+
+inst_26:
+// rs1==x30, rd==x27, rs1_val == 0x68C7D88000000000 
+// opcode: grevi ; op1:x30; dest:x27; op1val:0x68c7d88000000000;
+li x30, 0x68c7d88000000000
+grevi x27, x30, 7
+sw x27, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x27, 0x0000000000000000)
+
+inst_27:
+// rs1==x6, rd==x18, rs1_val == 0xF52BF0C000000000 
+// opcode: grevi ; op1:x6; dest:x18; op1val:0xf52bf0c000000000;
+li x6, 0xf52bf0c000000000
+grevi x18, x6, 7
+sw x18, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x18, 0x0000000000000000)
+
+inst_28:
+// rs1==x23, rd==x17, rs1_val == 0xA4AFB46000000000 
+// opcode: grevi ; op1:x23; dest:x17; op1val:0xa4afb46000000000;
+li x23, 0xa4afb46000000000
+grevi x17, x23, 7
+sw x17, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x17, 0x0000000000000000)
+
+inst_29:
+// rs1==x27, rd==x5, rs1_val == 0x263BEA5000000000 
+// opcode: grevi ; op1:x27; dest:x5; op1val:0x263bea5000000000;
+li x27, 0x263bea5000000000
+grevi x5, x27, 7
+sw x5, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x5, 0x0000000000000000)
+
+inst_30:
+// rs1==x12, rd==x28, rs1_val == 0x4EE5BCE800000000 
+// opcode: grevi ; op1:x12; dest:x28; op1val:0x4ee5bce800000000;
+li x12, 0x4ee5bce800000000
+grevi x28, x12, 7
+sw x28, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x28, 0x0000000000000000)
+
+inst_31:
+// rs1==x25, rs1_val == 0x7C5DE60C00000000 
+// opcode: grevi ; op1:x25; dest:x23; op1val:0x7c5de60c00000000;
+li x25, 0x7c5de60c00000000
+grevi x23, x25, 7
+sw x23, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x23, 0x0000000000000000)
+
+inst_32:
+// rd==x25, rs1_val == 0xA005556A00000000 
+// opcode: grevi ; op1:x21; dest:x25; op1val:0xa005556a00000000;
+li x21, 0xa005556a00000000
+grevi x25, x21, 7
+sw x25, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x25, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 0x2293EA2900000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2293ea2900000000;
+li x10, 0x2293ea2900000000
+grevi x11, x10, 7
+sw x11, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 0x362BA25E80000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x362ba25e80000000;
+li x10, 0x362ba25e80000000
+grevi x11, x10, 7
+sw x11, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 0x4733A71E40000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4733a71e40000000;
+li x10, 0x4733a71e40000000
+grevi x11, x10, 7
+sw x11, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 0x1E4B791A20000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e4b791a20000000;
+li x10, 0x1e4b791a20000000
+grevi x11, x10, 7
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 0x5FCB4D02D0000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5fcb4d02d0000000;
+li x10, 0x5fcb4d02d0000000
+grevi x11, x10, 7
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 0x98BA52AA88000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98ba52aa88000000;
+li x10, 0x98ba52aa88000000
+grevi x11, x10, 7
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 0xEE0923E014000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee0923e014000000;
+li x10, 0xee0923e014000000
+grevi x11, x10, 7
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 0x4BD47F4A3A000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bd47f4a3a000000;
+li x10, 0x4bd47f4a3a000000
+grevi x11, x10, 7
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 0xB30F8F95F1000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb30f8f95f1000000;
+li x10, 0xb30f8f95f1000000
+grevi x11, x10, 7
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 0x398261A02E800000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x398261a02e800000;
+li x10, 0x398261a02e800000
+grevi x11, x10, 7
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 0x0AF5E9EFD7C00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf5e9efd7c00000;
+li x10, 0xaf5e9efd7c00000
+grevi x11, x10, 7
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 0x4BCCF299A5E00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bccf299a5e00000;
+li x10, 0x4bccf299a5e00000
+grevi x11, x10, 7
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 0xAFF56459AFF00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff56459aff00000;
+li x10, 0xaff56459aff00000
+grevi x11, x10, 7
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 0xE07D7EDD48F80000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe07d7edd48f80000;
+li x10, 0xe07d7edd48f80000
+grevi x11, x10, 7
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 0x26604C6677840000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x26604c6677840000;
+li x10, 0x26604c6677840000
+grevi x11, x10, 7
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 0x5F67A33C644A0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f67a33c644a0000;
+li x10, 0x5f67a33c644a0000
+grevi x11, x10, 7
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 0xCC710F0F1C6B0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcc710f0f1c6b0000;
+li x10, 0xcc710f0f1c6b0000
+grevi x11, x10, 7
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 0x86BA73F6EC348000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x86ba73f6ec348000;
+li x10, 0x86ba73f6ec348000
+grevi x11, x10, 7
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 0x51EACA62967E4000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x51eaca62967e4000;
+li x10, 0x51eaca62967e4000
+grevi x11, x10, 7
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 0xD52F0E14EDC96000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd52f0e14edc96000;
+li x10, 0xd52f0e14edc96000
+grevi x11, x10, 7
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 0x0DBD625329043000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbd625329043000;
+li x10, 0xdbd625329043000
+grevi x11, x10, 7
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 0x6DCF0D4A62B5D800 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6dcf0d4a62b5d800;
+li x10, 0x6dcf0d4a62b5d800
+grevi x11, x10, 7
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 0xB4B31E3B962C1C00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb4b31e3b962c1c00;
+li x10, 0xb4b31e3b962c1c00
+grevi x11, x10, 7
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 0x8DCD6133F22D6600 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8dcd6133f22d6600;
+li x10, 0x8dcd6133f22d6600
+grevi x11, x10, 7
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 0x45AF1CB0CAAE1D00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x45af1cb0caae1d00;
+li x10, 0x45af1cb0caae1d00
+grevi x11, x10, 7
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 0xE86EB367B97C2C80 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe86eb367b97c2c80;
+li x10, 0xe86eb367b97c2c80
+grevi x11, x10, 7
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 0x2D9BE3118A013740 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2d9be3118a013740;
+li x10, 0x2d9be3118a013740
+grevi x11, x10, 7
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 0x70F53C4BFDFD2260 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70f53c4bfdfd2260;
+li x10, 0x70f53c4bfdfd2260
+grevi x11, x10, 7
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 0xF22A27B02C7BFF30 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf22a27b02c7bff30;
+li x10, 0xf22a27b02c7bff30
+grevi x11, x10, 7
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 0x0D99CFF9240BA738 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd99cff9240ba738;
+li x10, 0xd99cff9240ba738
+grevi x11, x10, 7
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 0x662E236EAA6781EC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x662e236eaa6781ec;
+li x10, 0x662e236eaa6781ec
+grevi x11, x10, 7
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 0x0EEA3A9950A03C5A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xeea3a9950a03c5a;
+li x10, 0xeea3a9950a03c5a
+grevi x11, x10, 7
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 0x44DCDA6A797D76DF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x44dcda6a797d76df;
+li x10, 0x44dcda6a797d76df
+grevi x11, x10, 7
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 0x39935C590B0FB71C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39935c590b0fb71c;
+li x10, 0x39935c590b0fb71c
+grevi x11, x10, 7
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 0xDE14BFF2EED7A249 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xde14bff2eed7a249;
+li x10, 0xde14bff2eed7a249
+grevi x11, x10, 7
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 0x6C9FEE24B808A67B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c9fee24b808a67b;
+li x10, 0x6c9fee24b808a67b
+grevi x11, x10, 7
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 0x008EEF6A63C2A497 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8eef6a63c2a497;
+li x10, 0x8eef6a63c2a497
+grevi x11, x10, 7
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 0x76B1FD3DF423752F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x76b1fd3df423752f;
+li x10, 0x76b1fd3df423752f
+grevi x11, x10, 7
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 0xA10BC6CCA6B7201F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa10bc6cca6b7201f;
+li x10, 0xa10bc6cca6b7201f
+grevi x11, x10, 7
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 0x6E2D704512C233BF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6e2d704512c233bf;
+li x10, 0x6e2d704512c233bf
+grevi x11, x10, 7
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 0x218FDC135DCF017F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x218fdc135dcf017f;
+li x10, 0x218fdc135dcf017f
+grevi x11, x10, 7
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 0xB3988B5231C8B6FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb3988b5231c8b6ff;
+li x10, 0xb3988b5231c8b6ff
+grevi x11, x10, 7
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 0xE2F99B2A3C5569FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe2f99b2a3c5569ff;
+li x10, 0xe2f99b2a3c5569ff
+grevi x11, x10, 7
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 0x90BB34803C4643FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x90bb34803c4643ff;
+li x10, 0x90bb34803c4643ff
+grevi x11, x10, 7
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 0x8CCE89147DA8D7FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cce89147da8d7ff;
+li x10, 0x8cce89147da8d7ff
+grevi x11, x10, 7
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 0x93C38B33217ACFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x93c38b33217acfff;
+li x10, 0x93c38b33217acfff
+grevi x11, x10, 7
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 0xE3A707D665505FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe3a707d665505fff;
+li x10, 0xe3a707d665505fff
+grevi x11, x10, 7
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 0x47B7097B9B01BFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x47b7097b9b01bfff;
+li x10, 0x47b7097b9b01bfff
+grevi x11, x10, 7
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 0x4302DA54759F7FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4302da54759f7fff;
+li x10, 0x4302da54759f7fff
+grevi x11, x10, 7
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 0x5F013C8240D8FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f013c8240d8ffff;
+li x10, 0x5f013c8240d8ffff
+grevi x11, x10, 7
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 0x5B33199985CDFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b33199985cdffff;
+li x10, 0x5b33199985cdffff
+grevi x11, x10, 7
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 0x2DEDF12233DBFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2dedf12233dbffff;
+li x10, 0x2dedf12233dbffff
+grevi x11, x10, 7
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 0x4B1634E12D37FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4b1634e12d37ffff;
+li x10, 0x4b1634e12d37ffff
+grevi x11, x10, 7
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0x8935B826718FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8935b826718fffff;
+li x10, 0x8935b826718fffff
+grevi x11, x10, 7
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0xBA9C678AAD5FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xba9c678aad5fffff;
+li x10, 0xba9c678aad5fffff
+grevi x11, x10, 7
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0x70BCB8E322BFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70bcb8e322bfffff;
+li x10, 0x70bcb8e322bfffff
+grevi x11, x10, 7
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0xFCB627AFBF7FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfcb627afbf7fffff;
+li x10, 0xfcb627afbf7fffff
+grevi x11, x10, 7
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0x9C76DF528CFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x9c76df528cffffff;
+li x10, 0x9c76df528cffffff
+grevi x11, x10, 7
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0x72C8DD98B1FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x72c8dd98b1ffffff;
+li x10, 0x72c8dd98b1ffffff
+grevi x11, x10, 7
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x434CBF26FBFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x434cbf26fbffffff;
+li x10, 0x434cbf26fbffffff
+grevi x11, x10, 7
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0xA23FB787C7FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa23fb787c7ffffff;
+li x10, 0xa23fb787c7ffffff
+grevi x11, x10, 7
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x983CA1BECFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x983ca1becfffffff;
+li x10, 0x983ca1becfffffff
+grevi x11, x10, 7
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0x589218431FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x589218431fffffff;
+li x10, 0x589218431fffffff
+grevi x11, x10, 7
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xA7BE99AE3FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7be99ae3fffffff;
+li x10, 0xa7be99ae3fffffff
+grevi x11, x10, 7
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xA37E37287FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa37e37287fffffff;
+li x10, 0xa37e37287fffffff
+grevi x11, x10, 7
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xE37D3738FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe37d3738ffffffff;
+li x10, 0xe37d3738ffffffff
+grevi x11, x10, 7
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xABB4DA1DFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xabb4da1dffffffff;
+li x10, 0xabb4da1dffffffff
+grevi x11, x10, 7
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0xFB3E7193FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfb3e7193ffffffff;
+li x10, 0xfb3e7193ffffffff
+grevi x11, x10, 7
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0x8CB950A7FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cb950a7ffffffff;
+li x10, 0x8cb950a7ffffffff
+grevi x11, x10, 7
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0xE5F31BEFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe5f31befffffffff;
+li x10, 0xe5f31befffffffff
+grevi x11, x10, 7
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x3BE93F9FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3be93f9fffffffff;
+li x10, 0x3be93f9fffffffff
+grevi x11, x10, 7
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0x5B1196BFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b1196bfffffffff;
+li x10, 0x5b1196bfffffffff
+grevi x11, x10, 7
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 0xE084097FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe084097fffffffff;
+li x10, 0xe084097fffffffff
+grevi x11, x10, 7
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 0x23B6BCFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23b6bcffffffffff;
+li x10, 0x23b6bcffffffffff
+grevi x11, x10, 7
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 0x6FCFD5FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6fcfd5ffffffffff;
+li x10, 0x6fcfd5ffffffffff
+grevi x11, x10, 7
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 0x73790BFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x73790bffffffffff;
+li x10, 0x73790bffffffffff
+grevi x11, x10, 7
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 0x432FF7FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x432ff7ffffffffff;
+li x10, 0x432ff7ffffffffff
+grevi x11, x10, 7
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 0xE36B0FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe36b0fffffffffff;
+li x10, 0xe36b0fffffffffff
+grevi x11, x10, 7
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 0xCB4ADFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcb4adfffffffffff;
+li x10, 0xcb4adfffffffffff
+grevi x11, x10, 7
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 0x15BF3FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15bf3fffffffffff;
+li x10, 0x15bf3fffffffffff
+grevi x11, x10, 7
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 0xD59A7FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd59a7fffffffffff;
+li x10, 0xd59a7fffffffffff
+grevi x11, x10, 7
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 0xFE32FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfe32ffffffffffff;
+li x10, 0xfe32ffffffffffff
+grevi x11, x10, 7
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 0xFF7DFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff7dffffffffffff;
+li x10, 0xff7dffffffffffff
+grevi x11, x10, 7
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 0xAF23FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf23ffffffffffff;
+li x10, 0xaf23ffffffffffff
+grevi x11, x10, 7
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 0x2057FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2057ffffffffffff;
+li x10, 0x2057ffffffffffff
+grevi x11, x10, 7
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 0x07AFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7afffffffffffff;
+li x10, 0x7afffffffffffff
+grevi x11, x10, 7
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 0xBE9FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbe9fffffffffffff;
+li x10, 0xbe9fffffffffffff
+grevi x11, x10, 7
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 0xD8BFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd8bfffffffffffff;
+li x10, 0xd8bfffffffffffff
+grevi x11, x10, 7
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 0x127FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x127fffffffffffff;
+li x10, 0x127fffffffffffff
+grevi x11, x10, 7
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 0x2EFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2effffffffffffff;
+li x10, 0x2effffffffffffff
+grevi x11, x10, 7
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 0xA5FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa5ffffffffffffff;
+li x10, 0xa5ffffffffffffff
+grevi x11, x10, 7
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 0xDBFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbffffffffffffff;
+li x10, 0xdbffffffffffffff
+grevi x11, x10, 7
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 0xA7FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7ffffffffffffff;
+li x10, 0xa7ffffffffffffff
+grevi x11, x10, 7
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 0xAFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xafffffffffffffff;
+li x10, 0xafffffffffffffff
+grevi x11, x10, 7
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 0xDFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdfffffffffffffff;
+li x10, 0xdfffffffffffffff
+grevi x11, x10, 7
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 0xBFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbfffffffffffffff;
+li x10, 0xbfffffffffffffff
+grevi x11, x10, 7
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 0x7FFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7fffffffffffffff;
+li x10, 0x7fffffffffffffff
+grevi x11, x10, 7
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 0xA274EA181E34B3F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa274ea181e34b3f2;
+li x10, 0xa274ea181e34b3f2
+grevi x11, x10, 7
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 0x6C3FBF4DC20EF165 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c3fbf4dc20ef165;
+li x10, 0x6c3fbf4dc20ef165
+grevi x11, x10, 7
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 0x28F918D8F6CDB2F9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x28f918d8f6cdb2f9;
+li x10, 0x28f918d8f6cdb2f9
+grevi x11, x10, 7
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 0x13E0D681552454F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13e0d681552454f2;
+li x10, 0x13e0d681552454f2
+grevi x11, x10, 7
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 0x0FAB6F3E164F1514 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfab6f3e164f1514;
+li x10, 0xfab6f3e164f1514
+grevi x11, x10, 7
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 0x063E9BED45100359 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63e9bed45100359;
+li x10, 0x63e9bed45100359
+grevi x11, x10, 7
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 0x02C6D8F2C74C7CD0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2c6d8f2c74c7cd0;
+li x10, 0x2c6d8f2c74c7cd0
+grevi x11, x10, 7
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 0x01D03FDDA123F502 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d03fdda123f502;
+li x10, 0x1d03fdda123f502
+grevi x11, x10, 7
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 0x00F5380E12B2A415 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf5380e12b2a415;
+li x10, 0xf5380e12b2a415
+grevi x11, x10, 7
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 0x0077730F65BD9ACC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x77730f65bd9acc;
+li x10, 0x77730f65bd9acc
+grevi x11, x10, 7
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 0x003A6A1DFAF8CDAA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3a6a1dfaf8cdaa;
+li x10, 0x3a6a1dfaf8cdaa
+grevi x11, x10, 7
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 0x001E5B4578511609 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e5b4578511609;
+li x10, 0x1e5b4578511609
+grevi x11, x10, 7
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 0x000D0372E90794E0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd0372e90794e0;
+li x10, 0xd0372e90794e0
+grevi x11, x10, 7
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 0x0006A24135B00A55 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6a24135b00a55;
+li x10, 0x6a24135b00a55
+grevi x11, x10, 7
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 0x00020BDF0023B683 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x20bdf0023b683;
+li x10, 0x20bdf0023b683
+grevi x11, x10, 7
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 0x000170EED8E94B16 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x170eed8e94b16;
+li x10, 0x170eed8e94b16
+grevi x11, x10, 7
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 0x0000EF05F542441E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xef05f542441e;
+li x10, 0xef05f542441e
+grevi x11, x10, 7
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 0x00004AAA62F28D1B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4aaa62f28d1b;
+li x10, 0x4aaa62f28d1b
+grevi x11, x10, 7
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 0x00003CB3D8B9B45D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3cb3d8b9b45d;
+li x10, 0x3cb3d8b9b45d
+grevi x11, x10, 7
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 0x00001BE466809A12 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1be466809a12;
+li x10, 0x1be466809a12
+grevi x11, x10, 7
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_150:
+// rs1_val == 0x0000092EC42B7171 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x92ec42b7171;
+li x10, 0x92ec42b7171
+grevi x11, x10, 7
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_151:
+// rs1_val == 0x0000074F11FA2AC1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x74f11fa2ac1;
+li x10, 0x74f11fa2ac1
+grevi x11, x10, 7
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_152:
+// rs1_val == 0x0000025A49FE85B1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x25a49fe85b1;
+li x10, 0x25a49fe85b1
+grevi x11, x10, 7
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_153:
+// rs1_val == 0x0000017A3ACB6267 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a3acb6267;
+li x10, 0x17a3acb6267
+grevi x11, x10, 7
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_154:
+// rs1_val == 0x000000C250B601FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc250b601fd;
+li x10, 0xc250b601fd
+grevi x11, x10, 7
+sw x11, 1032(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_155:
+// rs1_val == 0x00000067B53302FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x67b53302fd;
+li x10, 0x67b53302fd
+grevi x11, x10, 7
+sw x11, 1040(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_156:
+// rs1_val == 0x0000002AD7185DDB 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2ad7185ddb;
+li x10, 0x2ad7185ddb
+grevi x11, x10, 7
+sw x11, 1048(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_157:
+// rs1_val == 0x0000001FFEE5A5B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1ffee5a5b3;
+li x10, 0x1ffee5a5b3
+grevi x11, x10, 7
+sw x11, 1056(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_158:
+// rs1_val == 0x0000000AFF66658A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff66658a;
+li x10, 0xaff66658a
+grevi x11, x10, 7
+sw x11, 1064(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_159:
+// rs1_val == 0x000000064735AF1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x64735af1d;
+li x10, 0x64735af1d
+grevi x11, x10, 7
+sw x11, 1072(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_160:
+// rs1_val == 0x0000000275139238 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x275139238;
+li x10, 0x275139238
+grevi x11, x10, 7
+sw x11, 1080(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_161:
+// rs1_val == 0x00000001A9964AF0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1a9964af0;
+li x10, 0x1a9964af0
+grevi x11, x10, 7
+sw x11, 1088(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_162:
+// rs1_val == 0x00000000FFF1222A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff1222a;
+li x10, 0xfff1222a
+grevi x11, x10, 7
+sw x11, 1096(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_163:
+// rs1_val == 0x0000000063EA284E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63ea284e;
+li x10, 0x63ea284e
+grevi x11, x10, 7
+sw x11, 1104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_164:
+// rs1_val == 0x0000000024E55161 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x24e55161;
+li x10, 0x24e55161
+grevi x11, x10, 7
+sw x11, 1112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_165:
+// rs1_val == 0x0000000017A94DEE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a94dee;
+li x10, 0x17a94dee
+grevi x11, x10, 7
+sw x11, 1120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_166:
+// rs1_val == 0x0000000008C6A5B9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8c6a5b9;
+li x10, 0x8c6a5b9
+grevi x11, x10, 7
+sw x11, 1128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_167:
+// rs1_val == 0x0000000006C468AF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c468af;
+li x10, 0x6c468af
+grevi x11, x10, 7
+sw x11, 1136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_168:
+// rs1_val == 0x0000000003B37E15 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3b37e15;
+li x10, 0x3b37e15
+grevi x11, x10, 7
+sw x11, 1144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_169:
+// rs1_val == 0x0000000001EFFA39 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1effa39;
+li x10, 0x1effa39
+grevi x11, x10, 7
+sw x11, 1152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_170:
+// rs1_val == 0x0000000000B17D0C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb17d0c;
+li x10, 0xb17d0c
+grevi x11, x10, 7
+sw x11, 1160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_171:
+// rs1_val == 0x00000000007EBDD4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7ebdd4;
+li x10, 0x7ebdd4
+grevi x11, x10, 7
+sw x11, 1168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_172:
+// rs1_val == 0x000000000023FEB7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23feb7;
+li x10, 0x23feb7
+grevi x11, x10, 7
+sw x11, 1176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_173:
+// rs1_val == 0x0000000000171685 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x171685;
+li x10, 0x171685
+grevi x11, x10, 7
+sw x11, 1184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_174:
+// rs1_val == 0x0000000000098868 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98868;
+li x10, 0x98868
+grevi x11, x10, 7
+sw x11, 1192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_175:
+// rs1_val == 0x000000000005847F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5847f;
+li x10, 0x5847f
+grevi x11, x10, 7
+sw x11, 1200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_176:
+// rs1_val == 0x0000000000037797 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x37797;
+li x10, 0x37797
+grevi x11, x10, 7
+sw x11, 1208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_177:
+// rs1_val == 0x0000000000015DB9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15db9;
+li x10, 0x15db9
+grevi x11, x10, 7
+sw x11, 1216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_178:
+// rs1_val == 0x0000000000008735 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8735;
+li x10, 0x8735
+grevi x11, x10, 7
+sw x11, 1224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_179:
+// rs1_val == 0x0000000000006B68 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6b68;
+li x10, 0x6b68
+grevi x11, x10, 7
+sw x11, 1232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_180:
+// rs1_val == 0x0000000000002F28 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2f28;
+li x10, 0x2f28
+grevi x11, x10, 7
+sw x11, 1240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_181:
+// rs1_val == 0x0000000000001D40 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d40;
+li x10, 0x1d40
+grevi x11, x10, 7
+sw x11, 1248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_182:
+// rs1_val == 0x0000000000000F26 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf26;
+li x10, 0xf26
+grevi x11, x10, 7
+sw x11, 1256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_183:
+// rs1_val == 0x0000000000000482 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x482;
+li x10, 0x482
+grevi x11, x10, 7
+sw x11, 1264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_184:
+// rs1_val == 0x0000000000000394 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x394;
+li x10, 0x394
+grevi x11, x10, 7
+sw x11, 1272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_185:
+// rs1_val == 0x0000000000000154 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x154;
+li x10, 0x154
+grevi x11, x10, 7
+sw x11, 1280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_186:
+// rs1_val == 0x00000000000000FA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfa;
+li x10, 0xfa
+grevi x11, x10, 7
+sw x11, 1288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_187:
+// rs1_val == 0x0000000000000043 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x43;
+li x10, 0x43
+grevi x11, x10, 7
+sw x11, 1296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_188:
+// rs1_val == 0x0000000000000039 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39;
+li x10, 0x39
+grevi x11, x10, 7
+sw x11, 1304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_189:
+// rs1_val == 0x0000000000000013 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13;
+li x10, 0x13
+grevi x11, x10, 7
+sw x11, 1312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_190:
+// rs1_val == 0x000000000000000E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe;
+li x10, 0xe
+grevi x11, x10, 7
+sw x11, 1320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_191:
+// rs1_val == 0x0000000000000006 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6;
+li x10, 0x6
+grevi x11, x10, 7
+sw x11, 1328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_192:
+// rs1_val == 0x0000000000000002 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+grevi x11, x10, 7
+sw x11, 1336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_193:
+// rs1_val == 0x0000000000000001 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+grevi x11, x10, 7
+sw x11, 1344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_194:
+// rs1_val == 0x5D68F2012DAF94C2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5d68f2012daf94c2;
+li x10, 0x5d68f2012daf94c2
+grevi x11, x10, 7
+sw x11, 1352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_195:
+// rs1_val == 0x85986ADB9E044707 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x85986adb9e044707;
+li x10, 0x85986adb9e044707
+grevi x11, x10, 7
+sw x11, 1360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_196:
+// rs1_val == 0xC4BD48204652F62E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc4bd48204652f62e;
+li x10, 0xc4bd48204652f62e
+grevi x11, x10, 7
+sw x11, 1368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_197:
+// rs1_val == 0xEE4839A13ED7E667 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee4839a13ed7e667;
+li x10, 0xee4839a13ed7e667
+grevi x11, x10, 7
+sw x11, 1376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_198:
+// rs1_val == 0xF213516D6A013381 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf213516d6a013381;
+li x10, 0xf213516d6a013381
+grevi x11, x10, 7
+sw x11, 1384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_199:
+// rs1_val == 0xF871CFDE6EE84271 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf871cfde6ee84271;
+li x10, 0xf871cfde6ee84271
+grevi x11, x10, 7
+sw x11, 1392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_200:
+// rs1_val == 0xFD432A19F29C11AE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfd432a19f29c11ae;
+li x10, 0xfd432a19f29c11ae
+grevi x11, x10, 7
+sw x11, 1400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_201:
+// rs1_val == 0xFEE0888FCEB506F7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfee0888fceb506f7;
+li x10, 0xfee0888fceb506f7
+grevi x11, x10, 7
+sw x11, 1408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_202:
+// rs1_val == 0xFF605EE62A96D06B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff605ee62a96d06b;
+li x10, 0xff605ee62a96d06b
+grevi x11, x10, 7
+sw x11, 1416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_203:
+// rs1_val == 0xFF89799918BB28EA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff89799918bb28ea;
+li x10, 0xff89799918bb28ea
+grevi x11, x10, 7
+sw x11, 1424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_204:
+// rs1_val == 0xFFCC6148C6880008 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffcc6148c6880008;
+li x10, 0xffcc6148c6880008
+grevi x11, x10, 7
+sw x11, 1432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_205:
+// rs1_val == 0xFFEB5EA11CE80B13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffeb5ea11ce80b13;
+li x10, 0xffeb5ea11ce80b13
+grevi x11, x10, 7
+sw x11, 1440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_206:
+// rs1_val == 0xFFF039F699EF1858 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff039f699ef1858;
+li x10, 0xfff039f699ef1858
+grevi x11, x10, 7
+sw x11, 1448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_207:
+// rs1_val == 0xFFFBEA615FC9EBA5 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffbea615fc9eba5;
+li x10, 0xfffbea615fc9eba5
+grevi x11, x10, 7
+sw x11, 1456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_208:
+// rs1_val == 0xFFFC8D619136580C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffc8d619136580c;
+li x10, 0xfffc8d619136580c
+grevi x11, x10, 7
+sw x11, 1464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_209:
+// rs1_val == 0xFFFE46462651F638 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffe46462651f638;
+li x10, 0xfffe46462651f638
+grevi x11, x10, 7
+sw x11, 1472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_210:
+// rs1_val == 0xFFFF1C79DAE98555 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff1c79dae98555;
+li x10, 0xffff1c79dae98555
+grevi x11, x10, 7
+sw x11, 1480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_211:
+// rs1_val == 0xFFFF8E6F889263CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff8e6f889263cf;
+li x10, 0xffff8e6f889263cf
+grevi x11, x10, 7
+sw x11, 1488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_212:
+// rs1_val == 0xFFFFDEE2A86B8A6F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffdee2a86b8a6f;
+li x10, 0xffffdee2a86b8a6f
+grevi x11, x10, 7
+sw x11, 1496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_213:
+// rs1_val == 0xFFFFE2AFD167533B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffe2afd167533b;
+li x10, 0xffffe2afd167533b
+grevi x11, x10, 7
+sw x11, 1504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_214:
+// rs1_val == 0xFFFFF1A07F216823 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff1a07f216823;
+li x10, 0xfffff1a07f216823
+grevi x11, x10, 7
+sw x11, 1512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_215:
+// rs1_val == 0xFFFFF9090973E89D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff9090973e89d;
+li x10, 0xfffff9090973e89d
+grevi x11, x10, 7
+sw x11, 1520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_216:
+// rs1_val == 0xFFFFFC3769B1DCC0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffc3769b1dcc0;
+li x10, 0xfffffc3769b1dcc0
+grevi x11, x10, 7
+sw x11, 1528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_217:
+// rs1_val == 0xFFFFFEB8396BA83B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffeb8396ba83b;
+li x10, 0xfffffeb8396ba83b
+grevi x11, x10, 7
+sw x11, 1536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_218:
+// rs1_val == 0xFFFFFF4F280B11FE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff4f280b11fe;
+li x10, 0xffffff4f280b11fe
+grevi x11, x10, 7
+sw x11, 1544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_219:
+// rs1_val == 0xFFFFFF85D814D576 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff85d814d576;
+li x10, 0xffffff85d814d576
+grevi x11, x10, 7
+sw x11, 1552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_220:
+// rs1_val == 0xFFFFFFCC95A4D258 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffcc95a4d258;
+li x10, 0xffffffcc95a4d258
+grevi x11, x10, 7
+sw x11, 1560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_221:
+// rs1_val == 0xFFFFFFE610A37559 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffe610a37559;
+li x10, 0xffffffe610a37559
+grevi x11, x10, 7
+sw x11, 1568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_222:
+// rs1_val == 0xFFFFFFF66F9FB998 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffff66f9fb998;
+li x10, 0xfffffff66f9fb998
+grevi x11, x10, 7
+sw x11, 1576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_223:
+// rs1_val == 0xFFFFFFFB8C8A18B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffb8c8a18b3;
+li x10, 0xfffffffb8c8a18b3
+grevi x11, x10, 7
+sw x11, 1584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_224:
+// rs1_val == 0xFFFFFFFC507A2561 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffc507a2561;
+li x10, 0xfffffffc507a2561
+grevi x11, x10, 7
+sw x11, 1592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_225:
+// rs1_val == 0xFFFFFFFEE5F0307F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffee5f0307f;
+li x10, 0xfffffffee5f0307f
+grevi x11, x10, 7
+sw x11, 1600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_226:
+// rs1_val == 0xFFFFFFFF5DBBB7CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff5dbbb7cf;
+li x10, 0xffffffff5dbbb7cf
+grevi x11, x10, 7
+sw x11, 1608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_227:
+// rs1_val == 0xFFFFFFFF8D884510 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff8d884510;
+li x10, 0xffffffff8d884510
+grevi x11, x10, 7
+sw x11, 1616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_228:
+// rs1_val == 0xFFFFFFFFD0E58651 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffd0e58651;
+li x10, 0xffffffffd0e58651
+grevi x11, x10, 7
+sw x11, 1624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_229:
+// rs1_val == 0xFFFFFFFFE24C0602 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffe24c0602;
+li x10, 0xffffffffe24c0602
+grevi x11, x10, 7
+sw x11, 1632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_230:
+// rs1_val == 0xFFFFFFFFF109C208 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffff109c208;
+li x10, 0xfffffffff109c208
+grevi x11, x10, 7
+sw x11, 1640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_231:
+// rs1_val == 0xFFFFFFFFFB54AA23 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffb54aa23;
+li x10, 0xfffffffffb54aa23
+grevi x11, x10, 7
+sw x11, 1648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_232:
+// rs1_val == 0xFFFFFFFFFD02FC91 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffd02fc91;
+li x10, 0xfffffffffd02fc91
+grevi x11, x10, 7
+sw x11, 1656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_233:
+// rs1_val == 0xFFFFFFFFFE29D2A0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffe29d2a0;
+li x10, 0xfffffffffe29d2a0
+grevi x11, x10, 7
+sw x11, 1664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_234:
+// rs1_val == 0xFFFFFFFFFF7F6F5E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff7f6f5e;
+li x10, 0xffffffffff7f6f5e
+grevi x11, x10, 7
+sw x11, 1672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_235:
+// rs1_val == 0xFFFFFFFFFF9104D1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff9104d1;
+li x10, 0xffffffffff9104d1
+grevi x11, x10, 7
+sw x11, 1680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_236:
+// rs1_val == 0xFFFFFFFFFFCADB0B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffcadb0b;
+li x10, 0xffffffffffcadb0b
+grevi x11, x10, 7
+sw x11, 1688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_237:
+// rs1_val == 0xFFFFFFFFFFEEC2B4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffeec2b4;
+li x10, 0xffffffffffeec2b4
+grevi x11, x10, 7
+sw x11, 1696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_238:
+// rs1_val == 0xFFFFFFFFFFF49E5F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffff49e5f;
+li x10, 0xfffffffffff49e5f
+grevi x11, x10, 7
+sw x11, 1704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_239:
+// rs1_val == 0xFFFFFFFFFFFAE2EE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffae2ee;
+li x10, 0xfffffffffffae2ee
+grevi x11, x10, 7
+sw x11, 1712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_240:
+// rs1_val == 0xFFFFFFFFFFFC7F0E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffc7f0e;
+li x10, 0xfffffffffffc7f0e
+grevi x11, x10, 7
+sw x11, 1720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_241:
+// rs1_val == 0xFFFFFFFFFFFE3410 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffe3410;
+li x10, 0xfffffffffffe3410
+grevi x11, x10, 7
+sw x11, 1728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_242:
+// rs1_val == 0xFFFFFFFFFFFF6E0A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffff6e0a;
+li x10, 0xffffffffffff6e0a
+grevi x11, x10, 7
+sw x11, 1736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_243:
+// rs1_val == 0xFFFFFFFFFFFFB32A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffb32a;
+li x10, 0xffffffffffffb32a
+grevi x11, x10, 7
+sw x11, 1744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_244:
+// rs1_val == 0xFFFFFFFFFFFFC384 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffc384;
+li x10, 0xffffffffffffc384
+grevi x11, x10, 7
+sw x11, 1752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_245:
+// rs1_val == 0xFFFFFFFFFFFFEC1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffec1d;
+li x10, 0xffffffffffffec1d
+grevi x11, x10, 7
+sw x11, 1760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_246:
+// rs1_val == 0xFFFFFFFFFFFFF3F0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffff3f0;
+li x10, 0xfffffffffffff3f0
+grevi x11, x10, 7
+sw x11, 1768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_247:
+// rs1_val == 0xFFFFFFFFFFFFFB13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffb13;
+li x10, 0xfffffffffffffb13
+grevi x11, x10, 7
+sw x11, 1776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_248:
+// rs1_val == 0xFFFFFFFFFFFFFC31 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffc31;
+li x10, 0xfffffffffffffc31
+grevi x11, x10, 7
+sw x11, 1784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_249:
+// rs1_val == 0xFFFFFFFFFFFFFE44 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffe44;
+li x10, 0xfffffffffffffe44
+grevi x11, x10, 7
+sw x11, 1792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_250:
+// rs1_val == 0xFFFFFFFFFFFFFF58 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffff58;
+li x10, 0xffffffffffffff58
+grevi x11, x10, 7
+sw x11, 1800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_251:
+// rs1_val == 0xFFFFFFFFFFFFFFB0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffb0;
+li x10, 0xffffffffffffffb0
+grevi x11, x10, 7
+sw x11, 1808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_252:
+// rs1_val == 0xFFFFFFFFFFFFFFC6 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffc6;
+li x10, 0xffffffffffffffc6
+grevi x11, x10, 7
+sw x11, 1816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_253:
+// rs1_val == 0xFFFFFFFFFFFFFFE8 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffe8;
+li x10, 0xffffffffffffffe8
+grevi x11, x10, 7
+sw x11, 1824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_254:
+// rs1_val == 0xFFFFFFFFFFFFFFF2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff2;
+li x10, 0xfffffffffffffff2
+grevi x11, x10, 7
+sw x11, 1832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_255:
+// rs1_val == 0xFFFFFFFFFFFFFFF9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff9;
+li x10, 0xfffffffffffffff9
+grevi x11, x10, 7
+sw x11, 1840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_256:
+// rs1_val == 0xFFFFFFFFFFFFFFFD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+grevi x11, x10, 7
+sw x11, 1848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_257:
+// rs1_val == 0xFFFFFFFFFFFFFFFE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+grevi x11, x10, 7
+sw x11, 1856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_258:
+// rs1_val == 0xC000000000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc000000000000000;
+li x10, 0xc000000000000000
+grevi x11, x10, 7
+sw x11, 1864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_259:
+// rs1_val == 0x07A0000000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7a0000000000000;
+li x10, 0x7a0000000000000
+grevi x11, x10, 7
+sw x11, 1872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 25*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 235*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S
new file mode 100644
index 000000000..1a0dcaf50
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8-01.S
@@ -0,0 +1,2161 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the grevi instruction of the RISC-V  extension for the rev8 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rev8)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",rev8)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",rev8)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",rev8)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x17, rd==x3, rs1_val == 0xFFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x17; dest:x3; op1val:0xffffffffffffffff;
+li x17, 0xffffffffffffffff
+grevi x3, x17, 7
+sw x3, 0(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x3, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x28, rd==x28, rs1_val == 0x0000000000000000 
+// opcode: grevi ; op1:x28; dest:x28; op1val:0x0;
+li x28, 0x0
+grevi x28, x28, 7
+sw x28, 8(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x28, 0x0000000000000000)
+
+inst_2:
+// rs1==x2, rd==x27, rs1_val == 0x8000000000000000 
+// opcode: grevi ; op1:x2; dest:x27; op1val:0x8000000000000000;
+li x2, 0x8000000000000000
+grevi x27, x2, 7
+sw x27, 16(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x27, 0x0000000000000000)
+
+inst_3:
+// rs1==x22, rd==x18, rs1_val == 0xC000000000000000 
+// opcode: grevi ; op1:x22; dest:x18; op1val:0xc000000000000000;
+li x22, 0xc000000000000000
+grevi x18, x22, 7
+sw x18, 24(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x18, 0x0000000000000000)
+
+inst_4:
+// rs1==x0, rd==x16, rs1_val == 0xA000000000000000 
+// opcode: grevi ; op1:x0; dest:x16; op1val:0x0;
+li x0, 0x0
+grevi x16, x0, 7
+sw x16, 32(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x16, 0x0000000000000000)
+
+inst_5:
+// rs1==x30, rd==x19, rs1_val == 0x9000000000000000 
+// opcode: grevi ; op1:x30; dest:x19; op1val:0x9000000000000000;
+li x30, 0x9000000000000000
+grevi x19, x30, 7
+sw x19, 40(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x19, 0x0000000000000000)
+
+inst_6:
+// rs1==x11, rd==x29, rs1_val == 0x0800000000000000 
+// opcode: grevi ; op1:x11; dest:x29; op1val:0x800000000000000;
+li x11, 0x800000000000000
+grevi x29, x11, 7
+sw x29, 48(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x29, 0x0000000000000000)
+
+inst_7:
+// rs1==x9, rd==x11, rs1_val == 0x2C00000000000000 
+// opcode: grevi ; op1:x9; dest:x11; op1val:0x2c00000000000000;
+li x9, 0x2c00000000000000
+grevi x11, x9, 7
+sw x11, 56(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x11, 0x0000000000000000)
+
+inst_8:
+// rs1==x26, rd==x5, rs1_val == 0x9600000000000000 
+// opcode: grevi ; op1:x26; dest:x5; op1val:0x9600000000000000;
+li x26, 0x9600000000000000
+grevi x5, x26, 7
+sw x5, 64(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x5, 0x0000000000000000)
+
+inst_9:
+// rs1==x21, rd==x6, rs1_val == 0x0100000000000000 
+// opcode: grevi ; op1:x21; dest:x6; op1val:0x100000000000000;
+li x21, 0x100000000000000
+grevi x6, x21, 7
+sw x6, 72(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x6, 0x0000000000000000)
+
+inst_10:
+// rs1==x29, rd==x7, rs1_val == 0x9480000000000000 
+// opcode: grevi ; op1:x29; dest:x7; op1val:0x9480000000000000;
+li x29, 0x9480000000000000
+grevi x7, x29, 7
+sw x7, 80(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x7, 0x0000000000000000)
+
+inst_11:
+// rs1==x12, rd==x21, rs1_val == 0xB5C0000000000000 
+// opcode: grevi ; op1:x12; dest:x21; op1val:0xb5c0000000000000;
+li x12, 0xb5c0000000000000
+grevi x21, x12, 7
+sw x21, 88(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x21, 0x0000000000000000)
+
+inst_12:
+// rs1==x1, rd==x24, rs1_val == 0x07A0000000000000 
+// opcode: grevi ; op1:x1; dest:x24; op1val:0x7a0000000000000;
+li x1, 0x7a0000000000000
+grevi x24, x1, 7
+sw x24, 96(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x24, 0x0000000000000000)
+
+inst_13:
+// rs1==x6, rd==x30, rs1_val == 0x77B0000000000000 
+// opcode: grevi ; op1:x6; dest:x30; op1val:0x77b0000000000000;
+li x6, 0x77b0000000000000
+grevi x30, x6, 7
+sw x30, 104(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x30, 0x0000000000000000)
+
+inst_14:
+// rs1==x14, rd==x31, rs1_val == 0xF128000000000000 
+// opcode: grevi ; op1:x14; dest:x31; op1val:0xf128000000000000;
+li x14, 0xf128000000000000
+grevi x31, x14, 7
+sw x31, 112(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x31, 0x0000000000000000)
+
+inst_15:
+// rs1==x27, rd==x1, rs1_val == 0xC0E4000000000000 
+// opcode: grevi ; op1:x27; dest:x1; op1val:0xc0e4000000000000;
+li x27, 0xc0e4000000000000
+grevi x1, x27, 7
+sw x1, 120(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x1, 0x0000000000000000)
+
+inst_16:
+// rs1==x20, rd==x26, rs1_val == 0xDC52000000000000 
+// opcode: grevi ; op1:x20; dest:x26; op1val:0xdc52000000000000;
+li x20, 0xdc52000000000000
+grevi x26, x20, 7
+sw x26, 128(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x26, 0x0000000000000000)
+
+inst_17:
+// rs1==x7, rd==x9, rs1_val == 0x0B3D000000000000 
+// opcode: grevi ; op1:x7; dest:x9; op1val:0xb3d000000000000;
+li x7, 0xb3d000000000000
+grevi x9, x7, 7
+sw x9, 136(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x9, 0x0000000000000000)
+
+inst_18:
+// rs1==x25, rd==x15, rs1_val == 0xB154800000000000 
+// opcode: grevi ; op1:x25; dest:x15; op1val:0xb154800000000000;
+li x25, 0xb154800000000000
+grevi x15, x25, 7
+sw x15, 144(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x15, 0x0000000000000000)
+
+inst_19:
+// rs1==x8, rd==x10, rs1_val == 0x2609C00000000000 
+// opcode: grevi ; op1:x8; dest:x10; op1val:0x2609c00000000000;
+li x8, 0x2609c00000000000
+grevi x10, x8, 7
+sw x10, 152(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x10, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_20:
+// rs1==x24, rd==x23, rs1_val == 0xCF5BE00000000000 
+// opcode: grevi ; op1:x24; dest:x23; op1val:0xcf5be00000000000;
+li x24, 0xcf5be00000000000
+grevi x23, x24, 7
+sw x23, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x23, 0x0000000000000000)
+
+inst_21:
+// rs1==x10, rd==x4, rs1_val == 0x3ED0700000000000 
+// opcode: grevi ; op1:x10; dest:x4; op1val:0x3ed0700000000000;
+li x10, 0x3ed0700000000000
+grevi x4, x10, 7
+sw x4, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x4, 0x0000000000000000)
+
+inst_22:
+// rs1==x31, rd==x14, rs1_val == 0x6BDED80000000000 
+// opcode: grevi ; op1:x31; dest:x14; op1val:0x6bded80000000000;
+li x31, 0x6bded80000000000
+grevi x14, x31, 7
+sw x14, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x14, 0x0000000000000000)
+
+inst_23:
+// rs1==x18, rd==x12, rs1_val == 0x4637640000000000 
+// opcode: grevi ; op1:x18; dest:x12; op1val:0x4637640000000000;
+li x18, 0x4637640000000000
+grevi x12, x18, 7
+sw x12, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x12, 0x0000000000000000)
+
+inst_24:
+// rs1==x15, rd==x25, rs1_val == 0x7239560000000000 
+// opcode: grevi ; op1:x15; dest:x25; op1val:0x7239560000000000;
+li x15, 0x7239560000000000
+grevi x25, x15, 7
+sw x25, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x25, 0x0000000000000000)
+
+inst_25:
+// rs1==x23, rd==x0, rs1_val == 0x8864C10000000000 
+// opcode: grevi ; op1:x23; dest:x0; op1val:0x8864c10000000000;
+li x23, 0x8864c10000000000
+grevi x0, x23, 7
+sw x0, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x0, 0x0000000000000000)
+
+inst_26:
+// rs1==x16, rd==x17, rs1_val == 0x68C7D88000000000 
+// opcode: grevi ; op1:x16; dest:x17; op1val:0x68c7d88000000000;
+li x16, 0x68c7d88000000000
+grevi x17, x16, 7
+sw x17, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x17, 0x0000000000000000)
+
+inst_27:
+// rs1==x19, rd==x2, rs1_val == 0xF52BF0C000000000 
+// opcode: grevi ; op1:x19; dest:x2; op1val:0xf52bf0c000000000;
+li x19, 0xf52bf0c000000000
+grevi x2, x19, 7
+sw x2, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x2, 0x0000000000000000)
+
+inst_28:
+// rs1==x4, rd==x8, rs1_val == 0xA4AFB46000000000 
+// opcode: grevi ; op1:x4; dest:x8; op1val:0xa4afb46000000000;
+li x4, 0xa4afb46000000000
+grevi x8, x4, 7
+sw x8, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x8, 0x0000000000000000)
+
+inst_29:
+// rs1==x3, rd==x13, rs1_val == 0x263BEA5000000000 
+// opcode: grevi ; op1:x3; dest:x13; op1val:0x263bea5000000000;
+li x3, 0x263bea5000000000
+grevi x13, x3, 7
+sw x13, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x13, 0x0000000000000000)
+
+inst_30:
+// rs1==x13, rd==x20, rs1_val == 0x4EE5BCE800000000 
+// opcode: grevi ; op1:x13; dest:x20; op1val:0x4ee5bce800000000;
+li x13, 0x4ee5bce800000000
+grevi x20, x13, 7
+sw x20, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x20, 0x0000000000000000)
+
+inst_31:
+// rs1==x5, rd==x22, rs1_val == 0x7C5DE60C00000000 
+// opcode: grevi ; op1:x5; dest:x22; op1val:0x7c5de60c00000000;
+li x5, 0x7c5de60c00000000
+grevi x22, x5, 7
+sw x22, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x22, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 0xA005556A00000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa005556a00000000;
+li x10, 0xa005556a00000000
+grevi x11, x10, 7
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 0x2293EA2900000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2293ea2900000000;
+li x10, 0x2293ea2900000000
+grevi x11, x10, 7
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 0x362BA25E80000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x362ba25e80000000;
+li x10, 0x362ba25e80000000
+grevi x11, x10, 7
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 0x4733A71E40000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4733a71e40000000;
+li x10, 0x4733a71e40000000
+grevi x11, x10, 7
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 0x1E4B791A20000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e4b791a20000000;
+li x10, 0x1e4b791a20000000
+grevi x11, x10, 7
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 0x5FCB4D02D0000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5fcb4d02d0000000;
+li x10, 0x5fcb4d02d0000000
+grevi x11, x10, 7
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 0x98BA52AA88000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98ba52aa88000000;
+li x10, 0x98ba52aa88000000
+grevi x11, x10, 7
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 0xEE0923E014000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee0923e014000000;
+li x10, 0xee0923e014000000
+grevi x11, x10, 7
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 0x4BD47F4A3A000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bd47f4a3a000000;
+li x10, 0x4bd47f4a3a000000
+grevi x11, x10, 7
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 0xB30F8F95F1000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb30f8f95f1000000;
+li x10, 0xb30f8f95f1000000
+grevi x11, x10, 7
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 0x398261A02E800000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x398261a02e800000;
+li x10, 0x398261a02e800000
+grevi x11, x10, 7
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 0x0AF5E9EFD7C00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf5e9efd7c00000;
+li x10, 0xaf5e9efd7c00000
+grevi x11, x10, 7
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 0x4BCCF299A5E00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bccf299a5e00000;
+li x10, 0x4bccf299a5e00000
+grevi x11, x10, 7
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 0xAFF56459AFF00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff56459aff00000;
+li x10, 0xaff56459aff00000
+grevi x11, x10, 7
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 0xE07D7EDD48F80000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe07d7edd48f80000;
+li x10, 0xe07d7edd48f80000
+grevi x11, x10, 7
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 0x26604C6677840000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x26604c6677840000;
+li x10, 0x26604c6677840000
+grevi x11, x10, 7
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 0x5F67A33C644A0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f67a33c644a0000;
+li x10, 0x5f67a33c644a0000
+grevi x11, x10, 7
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 0xCC710F0F1C6B0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcc710f0f1c6b0000;
+li x10, 0xcc710f0f1c6b0000
+grevi x11, x10, 7
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 0x86BA73F6EC348000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x86ba73f6ec348000;
+li x10, 0x86ba73f6ec348000
+grevi x11, x10, 7
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 0x51EACA62967E4000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x51eaca62967e4000;
+li x10, 0x51eaca62967e4000
+grevi x11, x10, 7
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 0xD52F0E14EDC96000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd52f0e14edc96000;
+li x10, 0xd52f0e14edc96000
+grevi x11, x10, 7
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 0x0DBD625329043000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbd625329043000;
+li x10, 0xdbd625329043000
+grevi x11, x10, 7
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 0x6DCF0D4A62B5D800 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6dcf0d4a62b5d800;
+li x10, 0x6dcf0d4a62b5d800
+grevi x11, x10, 7
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 0xB4B31E3B962C1C00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb4b31e3b962c1c00;
+li x10, 0xb4b31e3b962c1c00
+grevi x11, x10, 7
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 0x8DCD6133F22D6600 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8dcd6133f22d6600;
+li x10, 0x8dcd6133f22d6600
+grevi x11, x10, 7
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 0x45AF1CB0CAAE1D00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x45af1cb0caae1d00;
+li x10, 0x45af1cb0caae1d00
+grevi x11, x10, 7
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 0xE86EB367B97C2C80 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe86eb367b97c2c80;
+li x10, 0xe86eb367b97c2c80
+grevi x11, x10, 7
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 0x2D9BE3118A013740 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2d9be3118a013740;
+li x10, 0x2d9be3118a013740
+grevi x11, x10, 7
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 0x70F53C4BFDFD2260 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70f53c4bfdfd2260;
+li x10, 0x70f53c4bfdfd2260
+grevi x11, x10, 7
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 0xF22A27B02C7BFF30 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf22a27b02c7bff30;
+li x10, 0xf22a27b02c7bff30
+grevi x11, x10, 7
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 0x0D99CFF9240BA738 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd99cff9240ba738;
+li x10, 0xd99cff9240ba738
+grevi x11, x10, 7
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 0x662E236EAA6781EC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x662e236eaa6781ec;
+li x10, 0x662e236eaa6781ec
+grevi x11, x10, 7
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 0x0EEA3A9950A03C5A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xeea3a9950a03c5a;
+li x10, 0xeea3a9950a03c5a
+grevi x11, x10, 7
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 0x44DCDA6A797D76DF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x44dcda6a797d76df;
+li x10, 0x44dcda6a797d76df
+grevi x11, x10, 7
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 0x39935C590B0FB71C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39935c590b0fb71c;
+li x10, 0x39935c590b0fb71c
+grevi x11, x10, 7
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 0xDE14BFF2EED7A249 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xde14bff2eed7a249;
+li x10, 0xde14bff2eed7a249
+grevi x11, x10, 7
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 0x6C9FEE24B808A67B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c9fee24b808a67b;
+li x10, 0x6c9fee24b808a67b
+grevi x11, x10, 7
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 0x008EEF6A63C2A497 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8eef6a63c2a497;
+li x10, 0x8eef6a63c2a497
+grevi x11, x10, 7
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 0x76B1FD3DF423752F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x76b1fd3df423752f;
+li x10, 0x76b1fd3df423752f
+grevi x11, x10, 7
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 0xA10BC6CCA6B7201F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa10bc6cca6b7201f;
+li x10, 0xa10bc6cca6b7201f
+grevi x11, x10, 7
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 0x6E2D704512C233BF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6e2d704512c233bf;
+li x10, 0x6e2d704512c233bf
+grevi x11, x10, 7
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 0x218FDC135DCF017F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x218fdc135dcf017f;
+li x10, 0x218fdc135dcf017f
+grevi x11, x10, 7
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 0xB3988B5231C8B6FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb3988b5231c8b6ff;
+li x10, 0xb3988b5231c8b6ff
+grevi x11, x10, 7
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 0xE2F99B2A3C5569FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe2f99b2a3c5569ff;
+li x10, 0xe2f99b2a3c5569ff
+grevi x11, x10, 7
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 0x90BB34803C4643FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x90bb34803c4643ff;
+li x10, 0x90bb34803c4643ff
+grevi x11, x10, 7
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 0x8CCE89147DA8D7FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cce89147da8d7ff;
+li x10, 0x8cce89147da8d7ff
+grevi x11, x10, 7
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 0x93C38B33217ACFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x93c38b33217acfff;
+li x10, 0x93c38b33217acfff
+grevi x11, x10, 7
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 0xE3A707D665505FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe3a707d665505fff;
+li x10, 0xe3a707d665505fff
+grevi x11, x10, 7
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 0x47B7097B9B01BFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x47b7097b9b01bfff;
+li x10, 0x47b7097b9b01bfff
+grevi x11, x10, 7
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 0x4302DA54759F7FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4302da54759f7fff;
+li x10, 0x4302da54759f7fff
+grevi x11, x10, 7
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 0x5F013C8240D8FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f013c8240d8ffff;
+li x10, 0x5f013c8240d8ffff
+grevi x11, x10, 7
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 0x5B33199985CDFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b33199985cdffff;
+li x10, 0x5b33199985cdffff
+grevi x11, x10, 7
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 0x2DEDF12233DBFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2dedf12233dbffff;
+li x10, 0x2dedf12233dbffff
+grevi x11, x10, 7
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 0x4B1634E12D37FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4b1634e12d37ffff;
+li x10, 0x4b1634e12d37ffff
+grevi x11, x10, 7
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0x8935B826718FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8935b826718fffff;
+li x10, 0x8935b826718fffff
+grevi x11, x10, 7
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0xBA9C678AAD5FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xba9c678aad5fffff;
+li x10, 0xba9c678aad5fffff
+grevi x11, x10, 7
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0x70BCB8E322BFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70bcb8e322bfffff;
+li x10, 0x70bcb8e322bfffff
+grevi x11, x10, 7
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0xFCB627AFBF7FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfcb627afbf7fffff;
+li x10, 0xfcb627afbf7fffff
+grevi x11, x10, 7
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0x9C76DF528CFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x9c76df528cffffff;
+li x10, 0x9c76df528cffffff
+grevi x11, x10, 7
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0x72C8DD98B1FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x72c8dd98b1ffffff;
+li x10, 0x72c8dd98b1ffffff
+grevi x11, x10, 7
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x434CBF26FBFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x434cbf26fbffffff;
+li x10, 0x434cbf26fbffffff
+grevi x11, x10, 7
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0xA23FB787C7FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa23fb787c7ffffff;
+li x10, 0xa23fb787c7ffffff
+grevi x11, x10, 7
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x983CA1BECFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x983ca1becfffffff;
+li x10, 0x983ca1becfffffff
+grevi x11, x10, 7
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0x589218431FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x589218431fffffff;
+li x10, 0x589218431fffffff
+grevi x11, x10, 7
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xA7BE99AE3FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7be99ae3fffffff;
+li x10, 0xa7be99ae3fffffff
+grevi x11, x10, 7
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xA37E37287FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa37e37287fffffff;
+li x10, 0xa37e37287fffffff
+grevi x11, x10, 7
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xE37D3738FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe37d3738ffffffff;
+li x10, 0xe37d3738ffffffff
+grevi x11, x10, 7
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xABB4DA1DFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xabb4da1dffffffff;
+li x10, 0xabb4da1dffffffff
+grevi x11, x10, 7
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0xFB3E7193FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfb3e7193ffffffff;
+li x10, 0xfb3e7193ffffffff
+grevi x11, x10, 7
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0x8CB950A7FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cb950a7ffffffff;
+li x10, 0x8cb950a7ffffffff
+grevi x11, x10, 7
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0xE5F31BEFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe5f31befffffffff;
+li x10, 0xe5f31befffffffff
+grevi x11, x10, 7
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x3BE93F9FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3be93f9fffffffff;
+li x10, 0x3be93f9fffffffff
+grevi x11, x10, 7
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0x5B1196BFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b1196bfffffffff;
+li x10, 0x5b1196bfffffffff
+grevi x11, x10, 7
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 0xE084097FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe084097fffffffff;
+li x10, 0xe084097fffffffff
+grevi x11, x10, 7
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 0x23B6BCFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23b6bcffffffffff;
+li x10, 0x23b6bcffffffffff
+grevi x11, x10, 7
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 0x6FCFD5FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6fcfd5ffffffffff;
+li x10, 0x6fcfd5ffffffffff
+grevi x11, x10, 7
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 0x73790BFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x73790bffffffffff;
+li x10, 0x73790bffffffffff
+grevi x11, x10, 7
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 0x432FF7FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x432ff7ffffffffff;
+li x10, 0x432ff7ffffffffff
+grevi x11, x10, 7
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 0xE36B0FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe36b0fffffffffff;
+li x10, 0xe36b0fffffffffff
+grevi x11, x10, 7
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 0xCB4ADFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcb4adfffffffffff;
+li x10, 0xcb4adfffffffffff
+grevi x11, x10, 7
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 0x15BF3FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15bf3fffffffffff;
+li x10, 0x15bf3fffffffffff
+grevi x11, x10, 7
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 0xD59A7FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd59a7fffffffffff;
+li x10, 0xd59a7fffffffffff
+grevi x11, x10, 7
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 0xFE32FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfe32ffffffffffff;
+li x10, 0xfe32ffffffffffff
+grevi x11, x10, 7
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 0xFF7DFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff7dffffffffffff;
+li x10, 0xff7dffffffffffff
+grevi x11, x10, 7
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 0xAF23FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf23ffffffffffff;
+li x10, 0xaf23ffffffffffff
+grevi x11, x10, 7
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 0x2057FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2057ffffffffffff;
+li x10, 0x2057ffffffffffff
+grevi x11, x10, 7
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 0x07AFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7afffffffffffff;
+li x10, 0x7afffffffffffff
+grevi x11, x10, 7
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 0xBE9FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbe9fffffffffffff;
+li x10, 0xbe9fffffffffffff
+grevi x11, x10, 7
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 0xD8BFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd8bfffffffffffff;
+li x10, 0xd8bfffffffffffff
+grevi x11, x10, 7
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 0x127FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x127fffffffffffff;
+li x10, 0x127fffffffffffff
+grevi x11, x10, 7
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 0x2EFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2effffffffffffff;
+li x10, 0x2effffffffffffff
+grevi x11, x10, 7
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 0xA5FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa5ffffffffffffff;
+li x10, 0xa5ffffffffffffff
+grevi x11, x10, 7
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 0xDBFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbffffffffffffff;
+li x10, 0xdbffffffffffffff
+grevi x11, x10, 7
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 0xA7FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7ffffffffffffff;
+li x10, 0xa7ffffffffffffff
+grevi x11, x10, 7
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 0xAFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xafffffffffffffff;
+li x10, 0xafffffffffffffff
+grevi x11, x10, 7
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 0xDFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdfffffffffffffff;
+li x10, 0xdfffffffffffffff
+grevi x11, x10, 7
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 0xBFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbfffffffffffffff;
+li x10, 0xbfffffffffffffff
+grevi x11, x10, 7
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 0x7FFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7fffffffffffffff;
+li x10, 0x7fffffffffffffff
+grevi x11, x10, 7
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 0xA274EA181E34B3F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa274ea181e34b3f2;
+li x10, 0xa274ea181e34b3f2
+grevi x11, x10, 7
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 0x6C3FBF4DC20EF165 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c3fbf4dc20ef165;
+li x10, 0x6c3fbf4dc20ef165
+grevi x11, x10, 7
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 0x28F918D8F6CDB2F9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x28f918d8f6cdb2f9;
+li x10, 0x28f918d8f6cdb2f9
+grevi x11, x10, 7
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 0x13E0D681552454F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13e0d681552454f2;
+li x10, 0x13e0d681552454f2
+grevi x11, x10, 7
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 0x0FAB6F3E164F1514 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfab6f3e164f1514;
+li x10, 0xfab6f3e164f1514
+grevi x11, x10, 7
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 0x063E9BED45100359 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63e9bed45100359;
+li x10, 0x63e9bed45100359
+grevi x11, x10, 7
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 0x02C6D8F2C74C7CD0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2c6d8f2c74c7cd0;
+li x10, 0x2c6d8f2c74c7cd0
+grevi x11, x10, 7
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 0x01D03FDDA123F502 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d03fdda123f502;
+li x10, 0x1d03fdda123f502
+grevi x11, x10, 7
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 0x00F5380E12B2A415 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf5380e12b2a415;
+li x10, 0xf5380e12b2a415
+grevi x11, x10, 7
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 0x0077730F65BD9ACC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x77730f65bd9acc;
+li x10, 0x77730f65bd9acc
+grevi x11, x10, 7
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 0x003A6A1DFAF8CDAA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3a6a1dfaf8cdaa;
+li x10, 0x3a6a1dfaf8cdaa
+grevi x11, x10, 7
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 0x001E5B4578511609 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e5b4578511609;
+li x10, 0x1e5b4578511609
+grevi x11, x10, 7
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 0x000D0372E90794E0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd0372e90794e0;
+li x10, 0xd0372e90794e0
+grevi x11, x10, 7
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 0x0006A24135B00A55 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6a24135b00a55;
+li x10, 0x6a24135b00a55
+grevi x11, x10, 7
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 0x00020BDF0023B683 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x20bdf0023b683;
+li x10, 0x20bdf0023b683
+grevi x11, x10, 7
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 0x000170EED8E94B16 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x170eed8e94b16;
+li x10, 0x170eed8e94b16
+grevi x11, x10, 7
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 0x0000EF05F542441E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xef05f542441e;
+li x10, 0xef05f542441e
+grevi x11, x10, 7
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 0x00004AAA62F28D1B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4aaa62f28d1b;
+li x10, 0x4aaa62f28d1b
+grevi x11, x10, 7
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 0x00003CB3D8B9B45D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3cb3d8b9b45d;
+li x10, 0x3cb3d8b9b45d
+grevi x11, x10, 7
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 0x00001BE466809A12 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1be466809a12;
+li x10, 0x1be466809a12
+grevi x11, x10, 7
+sw x11, 1032(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_150:
+// rs1_val == 0x0000092EC42B7171 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x92ec42b7171;
+li x10, 0x92ec42b7171
+grevi x11, x10, 7
+sw x11, 1040(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_151:
+// rs1_val == 0x0000074F11FA2AC1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x74f11fa2ac1;
+li x10, 0x74f11fa2ac1
+grevi x11, x10, 7
+sw x11, 1048(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_152:
+// rs1_val == 0x0000025A49FE85B1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x25a49fe85b1;
+li x10, 0x25a49fe85b1
+grevi x11, x10, 7
+sw x11, 1056(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_153:
+// rs1_val == 0x0000017A3ACB6267 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a3acb6267;
+li x10, 0x17a3acb6267
+grevi x11, x10, 7
+sw x11, 1064(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_154:
+// rs1_val == 0x000000C250B601FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc250b601fd;
+li x10, 0xc250b601fd
+grevi x11, x10, 7
+sw x11, 1072(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_155:
+// rs1_val == 0x00000067B53302FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x67b53302fd;
+li x10, 0x67b53302fd
+grevi x11, x10, 7
+sw x11, 1080(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_156:
+// rs1_val == 0x0000002AD7185DDB 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2ad7185ddb;
+li x10, 0x2ad7185ddb
+grevi x11, x10, 7
+sw x11, 1088(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_157:
+// rs1_val == 0x0000001FFEE5A5B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1ffee5a5b3;
+li x10, 0x1ffee5a5b3
+grevi x11, x10, 7
+sw x11, 1096(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_158:
+// rs1_val == 0x0000000AFF66658A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff66658a;
+li x10, 0xaff66658a
+grevi x11, x10, 7
+sw x11, 1104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_159:
+// rs1_val == 0x000000064735AF1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x64735af1d;
+li x10, 0x64735af1d
+grevi x11, x10, 7
+sw x11, 1112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_160:
+// rs1_val == 0x0000000275139238 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x275139238;
+li x10, 0x275139238
+grevi x11, x10, 7
+sw x11, 1120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_161:
+// rs1_val == 0x00000001A9964AF0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1a9964af0;
+li x10, 0x1a9964af0
+grevi x11, x10, 7
+sw x11, 1128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_162:
+// rs1_val == 0x00000000FFF1222A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff1222a;
+li x10, 0xfff1222a
+grevi x11, x10, 7
+sw x11, 1136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_163:
+// rs1_val == 0x0000000063EA284E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63ea284e;
+li x10, 0x63ea284e
+grevi x11, x10, 7
+sw x11, 1144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_164:
+// rs1_val == 0x0000000024E55161 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x24e55161;
+li x10, 0x24e55161
+grevi x11, x10, 7
+sw x11, 1152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_165:
+// rs1_val == 0x0000000017A94DEE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a94dee;
+li x10, 0x17a94dee
+grevi x11, x10, 7
+sw x11, 1160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_166:
+// rs1_val == 0x0000000008C6A5B9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8c6a5b9;
+li x10, 0x8c6a5b9
+grevi x11, x10, 7
+sw x11, 1168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_167:
+// rs1_val == 0x0000000006C468AF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c468af;
+li x10, 0x6c468af
+grevi x11, x10, 7
+sw x11, 1176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_168:
+// rs1_val == 0x0000000003B37E15 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3b37e15;
+li x10, 0x3b37e15
+grevi x11, x10, 7
+sw x11, 1184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_169:
+// rs1_val == 0x0000000001EFFA39 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1effa39;
+li x10, 0x1effa39
+grevi x11, x10, 7
+sw x11, 1192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_170:
+// rs1_val == 0x0000000000B17D0C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb17d0c;
+li x10, 0xb17d0c
+grevi x11, x10, 7
+sw x11, 1200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_171:
+// rs1_val == 0x00000000007EBDD4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7ebdd4;
+li x10, 0x7ebdd4
+grevi x11, x10, 7
+sw x11, 1208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_172:
+// rs1_val == 0x000000000023FEB7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23feb7;
+li x10, 0x23feb7
+grevi x11, x10, 7
+sw x11, 1216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_173:
+// rs1_val == 0x0000000000171685 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x171685;
+li x10, 0x171685
+grevi x11, x10, 7
+sw x11, 1224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_174:
+// rs1_val == 0x0000000000098868 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98868;
+li x10, 0x98868
+grevi x11, x10, 7
+sw x11, 1232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_175:
+// rs1_val == 0x000000000005847F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5847f;
+li x10, 0x5847f
+grevi x11, x10, 7
+sw x11, 1240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_176:
+// rs1_val == 0x0000000000037797 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x37797;
+li x10, 0x37797
+grevi x11, x10, 7
+sw x11, 1248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_177:
+// rs1_val == 0x0000000000015DB9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15db9;
+li x10, 0x15db9
+grevi x11, x10, 7
+sw x11, 1256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_178:
+// rs1_val == 0x0000000000008735 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8735;
+li x10, 0x8735
+grevi x11, x10, 7
+sw x11, 1264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_179:
+// rs1_val == 0x0000000000006B68 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6b68;
+li x10, 0x6b68
+grevi x11, x10, 7
+sw x11, 1272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_180:
+// rs1_val == 0x0000000000002F28 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2f28;
+li x10, 0x2f28
+grevi x11, x10, 7
+sw x11, 1280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_181:
+// rs1_val == 0x0000000000001D40 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d40;
+li x10, 0x1d40
+grevi x11, x10, 7
+sw x11, 1288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_182:
+// rs1_val == 0x0000000000000F26 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf26;
+li x10, 0xf26
+grevi x11, x10, 7
+sw x11, 1296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_183:
+// rs1_val == 0x0000000000000482 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x482;
+li x10, 0x482
+grevi x11, x10, 7
+sw x11, 1304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_184:
+// rs1_val == 0x0000000000000394 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x394;
+li x10, 0x394
+grevi x11, x10, 7
+sw x11, 1312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_185:
+// rs1_val == 0x0000000000000154 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x154;
+li x10, 0x154
+grevi x11, x10, 7
+sw x11, 1320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_186:
+// rs1_val == 0x00000000000000FA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfa;
+li x10, 0xfa
+grevi x11, x10, 7
+sw x11, 1328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_187:
+// rs1_val == 0x0000000000000043 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x43;
+li x10, 0x43
+grevi x11, x10, 7
+sw x11, 1336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_188:
+// rs1_val == 0x0000000000000039 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39;
+li x10, 0x39
+grevi x11, x10, 7
+sw x11, 1344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_189:
+// rs1_val == 0x0000000000000013 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13;
+li x10, 0x13
+grevi x11, x10, 7
+sw x11, 1352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_190:
+// rs1_val == 0x000000000000000E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe;
+li x10, 0xe
+grevi x11, x10, 7
+sw x11, 1360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_191:
+// rs1_val == 0x0000000000000006 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6;
+li x10, 0x6
+grevi x11, x10, 7
+sw x11, 1368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_192:
+// rs1_val == 0x0000000000000002 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+grevi x11, x10, 7
+sw x11, 1376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_193:
+// rs1_val == 0x0000000000000001 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+grevi x11, x10, 7
+sw x11, 1384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_194:
+// rs1_val == 0x5D68F2012DAF94C2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5d68f2012daf94c2;
+li x10, 0x5d68f2012daf94c2
+grevi x11, x10, 7
+sw x11, 1392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_195:
+// rs1_val == 0x85986ADB9E044707 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x85986adb9e044707;
+li x10, 0x85986adb9e044707
+grevi x11, x10, 7
+sw x11, 1400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_196:
+// rs1_val == 0xC4BD48204652F62E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc4bd48204652f62e;
+li x10, 0xc4bd48204652f62e
+grevi x11, x10, 7
+sw x11, 1408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_197:
+// rs1_val == 0xEE4839A13ED7E667 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee4839a13ed7e667;
+li x10, 0xee4839a13ed7e667
+grevi x11, x10, 7
+sw x11, 1416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_198:
+// rs1_val == 0xF213516D6A013381 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf213516d6a013381;
+li x10, 0xf213516d6a013381
+grevi x11, x10, 7
+sw x11, 1424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_199:
+// rs1_val == 0xF871CFDE6EE84271 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf871cfde6ee84271;
+li x10, 0xf871cfde6ee84271
+grevi x11, x10, 7
+sw x11, 1432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_200:
+// rs1_val == 0xFD432A19F29C11AE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfd432a19f29c11ae;
+li x10, 0xfd432a19f29c11ae
+grevi x11, x10, 7
+sw x11, 1440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_201:
+// rs1_val == 0xFEE0888FCEB506F7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfee0888fceb506f7;
+li x10, 0xfee0888fceb506f7
+grevi x11, x10, 7
+sw x11, 1448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_202:
+// rs1_val == 0xFF605EE62A96D06B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff605ee62a96d06b;
+li x10, 0xff605ee62a96d06b
+grevi x11, x10, 7
+sw x11, 1456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_203:
+// rs1_val == 0xFF89799918BB28EA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff89799918bb28ea;
+li x10, 0xff89799918bb28ea
+grevi x11, x10, 7
+sw x11, 1464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_204:
+// rs1_val == 0xFFCC6148C6880008 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffcc6148c6880008;
+li x10, 0xffcc6148c6880008
+grevi x11, x10, 7
+sw x11, 1472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_205:
+// rs1_val == 0xFFEB5EA11CE80B13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffeb5ea11ce80b13;
+li x10, 0xffeb5ea11ce80b13
+grevi x11, x10, 7
+sw x11, 1480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_206:
+// rs1_val == 0xFFF039F699EF1858 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff039f699ef1858;
+li x10, 0xfff039f699ef1858
+grevi x11, x10, 7
+sw x11, 1488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_207:
+// rs1_val == 0xFFFBEA615FC9EBA5 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffbea615fc9eba5;
+li x10, 0xfffbea615fc9eba5
+grevi x11, x10, 7
+sw x11, 1496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_208:
+// rs1_val == 0xFFFC8D619136580C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffc8d619136580c;
+li x10, 0xfffc8d619136580c
+grevi x11, x10, 7
+sw x11, 1504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_209:
+// rs1_val == 0xFFFE46462651F638 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffe46462651f638;
+li x10, 0xfffe46462651f638
+grevi x11, x10, 7
+sw x11, 1512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_210:
+// rs1_val == 0xFFFF1C79DAE98555 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff1c79dae98555;
+li x10, 0xffff1c79dae98555
+grevi x11, x10, 7
+sw x11, 1520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_211:
+// rs1_val == 0xFFFF8E6F889263CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff8e6f889263cf;
+li x10, 0xffff8e6f889263cf
+grevi x11, x10, 7
+sw x11, 1528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_212:
+// rs1_val == 0xFFFFDEE2A86B8A6F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffdee2a86b8a6f;
+li x10, 0xffffdee2a86b8a6f
+grevi x11, x10, 7
+sw x11, 1536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_213:
+// rs1_val == 0xFFFFE2AFD167533B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffe2afd167533b;
+li x10, 0xffffe2afd167533b
+grevi x11, x10, 7
+sw x11, 1544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_214:
+// rs1_val == 0xFFFFF1A07F216823 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff1a07f216823;
+li x10, 0xfffff1a07f216823
+grevi x11, x10, 7
+sw x11, 1552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_215:
+// rs1_val == 0xFFFFF9090973E89D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff9090973e89d;
+li x10, 0xfffff9090973e89d
+grevi x11, x10, 7
+sw x11, 1560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_216:
+// rs1_val == 0xFFFFFC3769B1DCC0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffc3769b1dcc0;
+li x10, 0xfffffc3769b1dcc0
+grevi x11, x10, 7
+sw x11, 1568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_217:
+// rs1_val == 0xFFFFFEB8396BA83B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffeb8396ba83b;
+li x10, 0xfffffeb8396ba83b
+grevi x11, x10, 7
+sw x11, 1576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_218:
+// rs1_val == 0xFFFFFF4F280B11FE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff4f280b11fe;
+li x10, 0xffffff4f280b11fe
+grevi x11, x10, 7
+sw x11, 1584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_219:
+// rs1_val == 0xFFFFFF85D814D576 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff85d814d576;
+li x10, 0xffffff85d814d576
+grevi x11, x10, 7
+sw x11, 1592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_220:
+// rs1_val == 0xFFFFFFCC95A4D258 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffcc95a4d258;
+li x10, 0xffffffcc95a4d258
+grevi x11, x10, 7
+sw x11, 1600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_221:
+// rs1_val == 0xFFFFFFE610A37559 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffe610a37559;
+li x10, 0xffffffe610a37559
+grevi x11, x10, 7
+sw x11, 1608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_222:
+// rs1_val == 0xFFFFFFF66F9FB998 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffff66f9fb998;
+li x10, 0xfffffff66f9fb998
+grevi x11, x10, 7
+sw x11, 1616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_223:
+// rs1_val == 0xFFFFFFFB8C8A18B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffb8c8a18b3;
+li x10, 0xfffffffb8c8a18b3
+grevi x11, x10, 7
+sw x11, 1624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_224:
+// rs1_val == 0xFFFFFFFC507A2561 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffc507a2561;
+li x10, 0xfffffffc507a2561
+grevi x11, x10, 7
+sw x11, 1632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_225:
+// rs1_val == 0xFFFFFFFEE5F0307F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffee5f0307f;
+li x10, 0xfffffffee5f0307f
+grevi x11, x10, 7
+sw x11, 1640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_226:
+// rs1_val == 0xFFFFFFFF5DBBB7CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff5dbbb7cf;
+li x10, 0xffffffff5dbbb7cf
+grevi x11, x10, 7
+sw x11, 1648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_227:
+// rs1_val == 0xFFFFFFFF8D884510 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff8d884510;
+li x10, 0xffffffff8d884510
+grevi x11, x10, 7
+sw x11, 1656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_228:
+// rs1_val == 0xFFFFFFFFD0E58651 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffd0e58651;
+li x10, 0xffffffffd0e58651
+grevi x11, x10, 7
+sw x11, 1664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_229:
+// rs1_val == 0xFFFFFFFFE24C0602 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffe24c0602;
+li x10, 0xffffffffe24c0602
+grevi x11, x10, 7
+sw x11, 1672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_230:
+// rs1_val == 0xFFFFFFFFF109C208 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffff109c208;
+li x10, 0xfffffffff109c208
+grevi x11, x10, 7
+sw x11, 1680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_231:
+// rs1_val == 0xFFFFFFFFFB54AA23 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffb54aa23;
+li x10, 0xfffffffffb54aa23
+grevi x11, x10, 7
+sw x11, 1688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_232:
+// rs1_val == 0xFFFFFFFFFD02FC91 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffd02fc91;
+li x10, 0xfffffffffd02fc91
+grevi x11, x10, 7
+sw x11, 1696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_233:
+// rs1_val == 0xFFFFFFFFFE29D2A0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffe29d2a0;
+li x10, 0xfffffffffe29d2a0
+grevi x11, x10, 7
+sw x11, 1704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_234:
+// rs1_val == 0xFFFFFFFFFF7F6F5E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff7f6f5e;
+li x10, 0xffffffffff7f6f5e
+grevi x11, x10, 7
+sw x11, 1712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_235:
+// rs1_val == 0xFFFFFFFFFF9104D1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff9104d1;
+li x10, 0xffffffffff9104d1
+grevi x11, x10, 7
+sw x11, 1720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_236:
+// rs1_val == 0xFFFFFFFFFFCADB0B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffcadb0b;
+li x10, 0xffffffffffcadb0b
+grevi x11, x10, 7
+sw x11, 1728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_237:
+// rs1_val == 0xFFFFFFFFFFEEC2B4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffeec2b4;
+li x10, 0xffffffffffeec2b4
+grevi x11, x10, 7
+sw x11, 1736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_238:
+// rs1_val == 0xFFFFFFFFFFF49E5F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffff49e5f;
+li x10, 0xfffffffffff49e5f
+grevi x11, x10, 7
+sw x11, 1744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_239:
+// rs1_val == 0xFFFFFFFFFFFAE2EE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffae2ee;
+li x10, 0xfffffffffffae2ee
+grevi x11, x10, 7
+sw x11, 1752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_240:
+// rs1_val == 0xFFFFFFFFFFFC7F0E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffc7f0e;
+li x10, 0xfffffffffffc7f0e
+grevi x11, x10, 7
+sw x11, 1760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_241:
+// rs1_val == 0xFFFFFFFFFFFE3410 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffe3410;
+li x10, 0xfffffffffffe3410
+grevi x11, x10, 7
+sw x11, 1768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_242:
+// rs1_val == 0xFFFFFFFFFFFF6E0A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffff6e0a;
+li x10, 0xffffffffffff6e0a
+grevi x11, x10, 7
+sw x11, 1776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_243:
+// rs1_val == 0xFFFFFFFFFFFFB32A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffb32a;
+li x10, 0xffffffffffffb32a
+grevi x11, x10, 7
+sw x11, 1784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_244:
+// rs1_val == 0xFFFFFFFFFFFFC384 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffc384;
+li x10, 0xffffffffffffc384
+grevi x11, x10, 7
+sw x11, 1792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_245:
+// rs1_val == 0xFFFFFFFFFFFFEC1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffec1d;
+li x10, 0xffffffffffffec1d
+grevi x11, x10, 7
+sw x11, 1800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_246:
+// rs1_val == 0xFFFFFFFFFFFFF3F0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffff3f0;
+li x10, 0xfffffffffffff3f0
+grevi x11, x10, 7
+sw x11, 1808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_247:
+// rs1_val == 0xFFFFFFFFFFFFFB13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffb13;
+li x10, 0xfffffffffffffb13
+grevi x11, x10, 7
+sw x11, 1816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_248:
+// rs1_val == 0xFFFFFFFFFFFFFC31 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffc31;
+li x10, 0xfffffffffffffc31
+grevi x11, x10, 7
+sw x11, 1824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_249:
+// rs1_val == 0xFFFFFFFFFFFFFE44 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffe44;
+li x10, 0xfffffffffffffe44
+grevi x11, x10, 7
+sw x11, 1832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_250:
+// rs1_val == 0xFFFFFFFFFFFFFF58 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffff58;
+li x10, 0xffffffffffffff58
+grevi x11, x10, 7
+sw x11, 1840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_251:
+// rs1_val == 0xFFFFFFFFFFFFFFB0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffb0;
+li x10, 0xffffffffffffffb0
+grevi x11, x10, 7
+sw x11, 1848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_252:
+// rs1_val == 0xFFFFFFFFFFFFFFC6 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffc6;
+li x10, 0xffffffffffffffc6
+grevi x11, x10, 7
+sw x11, 1856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_253:
+// rs1_val == 0xFFFFFFFFFFFFFFE8 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffe8;
+li x10, 0xffffffffffffffe8
+grevi x11, x10, 7
+sw x11, 1864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_254:
+// rs1_val == 0xFFFFFFFFFFFFFFF2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff2;
+li x10, 0xfffffffffffffff2
+grevi x11, x10, 7
+sw x11, 1872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_255:
+// rs1_val == 0xFFFFFFFFFFFFFFF9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff9;
+li x10, 0xfffffffffffffff9
+grevi x11, x10, 7
+sw x11, 1880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_256:
+// rs1_val == 0xFFFFFFFFFFFFFFFD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+grevi x11, x10, 7
+sw x11, 1888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_257:
+// rs1_val == 0xFFFFFFFFFFFFFFFE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+grevi x11, x10, 7
+sw x11, 1896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_258:
+// rs1_val == 0xA000000000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa000000000000000;
+li x10, 0xa000000000000000
+grevi x11, x10, 7
+sw x11, 1904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+
+inst_259:
+// rs1_val == 0x8864C10000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8864c10000000000;
+li x10, 0x8864c10000000000
+grevi x11, x10, 7
+sw x11, 1912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x6, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 20*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 240*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S
new file mode 100644
index 000000000..b9e5d6ab1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rev8.w-01.S
@@ -0,0 +1,2161 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the grevi instruction of the RISC-V  extension for the rev8.w covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rev8.w)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",rev8.w)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",rev8.w)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",rev8.w)
+
+RVTEST_SIGBASE( x15,signature_x15_1)
+
+inst_0:
+// rs1 != rd, rs1==x27, rd==x28, rs1_val == 0xFFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x27; dest:x28; op1val:0xffffffffffffffff;
+li x27, 0xffffffffffffffff
+grevi x28, x27, 7
+sw x28, 0(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x28, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x22, rd==x22, rs1_val == 0x0000000000000000 
+// opcode: grevi ; op1:x22; dest:x22; op1val:0x0;
+li x22, 0x0
+grevi x22, x22, 7
+sw x22, 8(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x22, 0x0000000000000000)
+
+inst_2:
+// rs1==x1, rd==x7, rs1_val == 0x8000000000000000 
+// opcode: grevi ; op1:x1; dest:x7; op1val:0x8000000000000000;
+li x1, 0x8000000000000000
+grevi x7, x1, 7
+sw x7, 16(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x7, 0x0000000000000000)
+
+inst_3:
+// rs1==x24, rd==x17, rs1_val == 0xC000000000000000 
+// opcode: grevi ; op1:x24; dest:x17; op1val:0xc000000000000000;
+li x24, 0xc000000000000000
+grevi x17, x24, 7
+sw x17, 24(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x17, 0x0000000000000000)
+
+inst_4:
+// rs1==x18, rd==x1, rs1_val == 0xA000000000000000 
+// opcode: grevi ; op1:x18; dest:x1; op1val:0xa000000000000000;
+li x18, 0xa000000000000000
+grevi x1, x18, 7
+sw x1, 32(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x1, 0x0000000000000000)
+
+inst_5:
+// rs1==x10, rd==x12, rs1_val == 0x9000000000000000 
+// opcode: grevi ; op1:x10; dest:x12; op1val:0x9000000000000000;
+li x10, 0x9000000000000000
+grevi x12, x10, 7
+sw x12, 40(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x12, 0x0000000000000000)
+
+inst_6:
+// rs1==x29, rd==x2, rs1_val == 0x0800000000000000 
+// opcode: grevi ; op1:x29; dest:x2; op1val:0x800000000000000;
+li x29, 0x800000000000000
+grevi x2, x29, 7
+sw x2, 48(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x2, 0x0000000000000000)
+
+inst_7:
+// rs1==x14, rd==x3, rs1_val == 0x2C00000000000000 
+// opcode: grevi ; op1:x14; dest:x3; op1val:0x2c00000000000000;
+li x14, 0x2c00000000000000
+grevi x3, x14, 7
+sw x3, 56(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x3, 0x0000000000000000)
+
+inst_8:
+// rs1==x5, rd==x24, rs1_val == 0x9600000000000000 
+// opcode: grevi ; op1:x5; dest:x24; op1val:0x9600000000000000;
+li x5, 0x9600000000000000
+grevi x24, x5, 7
+sw x24, 64(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x24, 0x0000000000000000)
+
+inst_9:
+// rs1==x2, rd==x30, rs1_val == 0x0100000000000000 
+// opcode: grevi ; op1:x2; dest:x30; op1val:0x100000000000000;
+li x2, 0x100000000000000
+grevi x30, x2, 7
+sw x30, 72(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x30, 0x0000000000000000)
+
+inst_10:
+// rs1==x0, rd==x6, rs1_val == 0x9480000000000000 
+// opcode: grevi ; op1:x0; dest:x6; op1val:0x0;
+li x0, 0x0
+grevi x6, x0, 7
+sw x6, 80(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x6, 0x0000000000000000)
+
+inst_11:
+// rs1==x7, rd==x18, rs1_val == 0xB5C0000000000000 
+// opcode: grevi ; op1:x7; dest:x18; op1val:0xb5c0000000000000;
+li x7, 0xb5c0000000000000
+grevi x18, x7, 7
+sw x18, 88(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x18, 0x0000000000000000)
+
+inst_12:
+// rs1==x30, rd==x5, rs1_val == 0x07A0000000000000 
+// opcode: grevi ; op1:x30; dest:x5; op1val:0x7a0000000000000;
+li x30, 0x7a0000000000000
+grevi x5, x30, 7
+sw x5, 96(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x5, 0x0000000000000000)
+
+inst_13:
+// rs1==x28, rd==x0, rs1_val == 0x77B0000000000000 
+// opcode: grevi ; op1:x28; dest:x0; op1val:0x77b0000000000000;
+li x28, 0x77b0000000000000
+grevi x0, x28, 7
+sw x0, 104(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x0, 0x0000000000000000)
+
+inst_14:
+// rs1==x20, rd==x19, rs1_val == 0xF128000000000000 
+// opcode: grevi ; op1:x20; dest:x19; op1val:0xf128000000000000;
+li x20, 0xf128000000000000
+grevi x19, x20, 7
+sw x19, 112(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x19, 0x0000000000000000)
+
+inst_15:
+// rs1==x31, rd==x13, rs1_val == 0xC0E4000000000000 
+// opcode: grevi ; op1:x31; dest:x13; op1val:0xc0e4000000000000;
+li x31, 0xc0e4000000000000
+grevi x13, x31, 7
+sw x13, 120(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x13, 0x0000000000000000)
+
+inst_16:
+// rs1==x4, rd==x25, rs1_val == 0xDC52000000000000 
+// opcode: grevi ; op1:x4; dest:x25; op1val:0xdc52000000000000;
+li x4, 0xdc52000000000000
+grevi x25, x4, 7
+sw x25, 128(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x25, 0x0000000000000000)
+
+inst_17:
+// rs1==x13, rd==x8, rs1_val == 0x0B3D000000000000 
+// opcode: grevi ; op1:x13; dest:x8; op1val:0xb3d000000000000;
+li x13, 0xb3d000000000000
+grevi x8, x13, 7
+sw x8, 136(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x8, 0x0000000000000000)
+
+inst_18:
+// rs1==x3, rd==x31, rs1_val == 0xB154800000000000 
+// opcode: grevi ; op1:x3; dest:x31; op1val:0xb154800000000000;
+li x3, 0xb154800000000000
+grevi x31, x3, 7
+sw x31, 144(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x31, 0x0000000000000000)
+
+inst_19:
+// rs1==x17, rd==x10, rs1_val == 0x2609C00000000000 
+// opcode: grevi ; op1:x17; dest:x10; op1val:0x2609c00000000000;
+li x17, 0x2609c00000000000
+grevi x10, x17, 7
+sw x10, 152(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x10, 0x0000000000000000)
+
+inst_20:
+// rs1==x9, rd==x27, rs1_val == 0xCF5BE00000000000 
+// opcode: grevi ; op1:x9; dest:x27; op1val:0xcf5be00000000000;
+li x9, 0xcf5be00000000000
+grevi x27, x9, 7
+sw x27, 160(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x27, 0x0000000000000000)
+
+inst_21:
+// rs1==x6, rd==x26, rs1_val == 0x3ED0700000000000 
+// opcode: grevi ; op1:x6; dest:x26; op1val:0x3ed0700000000000;
+li x6, 0x3ed0700000000000
+grevi x26, x6, 7
+sw x26, 168(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x26, 0x0000000000000000)
+
+inst_22:
+// rs1==x11, rd==x21, rs1_val == 0x6BDED80000000000 
+// opcode: grevi ; op1:x11; dest:x21; op1val:0x6bded80000000000;
+li x11, 0x6bded80000000000
+grevi x21, x11, 7
+sw x21, 176(x15)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x21, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_23:
+// rs1==x12, rd==x9, rs1_val == 0x4637640000000000 
+// opcode: grevi ; op1:x12; dest:x9; op1val:0x4637640000000000;
+li x12, 0x4637640000000000
+grevi x9, x12, 7
+sw x9, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x9, 0x0000000000000000)
+
+inst_24:
+// rs1==x26, rd==x23, rs1_val == 0x7239560000000000 
+// opcode: grevi ; op1:x26; dest:x23; op1val:0x7239560000000000;
+li x26, 0x7239560000000000
+grevi x23, x26, 7
+sw x23, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x23, 0x0000000000000000)
+
+inst_25:
+// rs1==x23, rd==x16, rs1_val == 0x8864C10000000000 
+// opcode: grevi ; op1:x23; dest:x16; op1val:0x8864c10000000000;
+li x23, 0x8864c10000000000
+grevi x16, x23, 7
+sw x16, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x16, 0x0000000000000000)
+
+inst_26:
+// rs1==x16, rd==x11, rs1_val == 0x68C7D88000000000 
+// opcode: grevi ; op1:x16; dest:x11; op1val:0x68c7d88000000000;
+li x16, 0x68c7d88000000000
+grevi x11, x16, 7
+sw x11, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_27:
+// rs1==x8, rd==x4, rs1_val == 0xF52BF0C000000000 
+// opcode: grevi ; op1:x8; dest:x4; op1val:0xf52bf0c000000000;
+li x8, 0xf52bf0c000000000
+grevi x4, x8, 7
+sw x4, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x4, 0x0000000000000000)
+
+inst_28:
+// rs1==x21, rd==x20, rs1_val == 0xA4AFB46000000000 
+// opcode: grevi ; op1:x21; dest:x20; op1val:0xa4afb46000000000;
+li x21, 0xa4afb46000000000
+grevi x20, x21, 7
+sw x20, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x20, 0x0000000000000000)
+
+inst_29:
+// rs1==x19, rd==x15, rs1_val == 0x263BEA5000000000 
+// opcode: grevi ; op1:x19; dest:x15; op1val:0x263bea5000000000;
+li x19, 0x263bea5000000000
+grevi x15, x19, 7
+sw x15, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x15, 0x0000000000000000)
+
+inst_30:
+// rs1==x25, rd==x29, rs1_val == 0x4EE5BCE800000000 
+// opcode: grevi ; op1:x25; dest:x29; op1val:0x4ee5bce800000000;
+li x25, 0x4ee5bce800000000
+grevi x29, x25, 7
+sw x29, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x29, 0x0000000000000000)
+
+inst_31:
+// rs1==x15, rd==x14, rs1_val == 0x7C5DE60C00000000 
+// opcode: grevi ; op1:x15; dest:x14; op1val:0x7c5de60c00000000;
+li x15, 0x7c5de60c00000000
+grevi x14, x15, 7
+sw x14, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x14, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 0xA005556A00000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa005556a00000000;
+li x10, 0xa005556a00000000
+grevi x11, x10, 7
+sw x11, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 0x2293EA2900000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2293ea2900000000;
+li x10, 0x2293ea2900000000
+grevi x11, x10, 7
+sw x11, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 0x362BA25E80000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x362ba25e80000000;
+li x10, 0x362ba25e80000000
+grevi x11, x10, 7
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 0x4733A71E40000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4733a71e40000000;
+li x10, 0x4733a71e40000000
+grevi x11, x10, 7
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 0x1E4B791A20000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e4b791a20000000;
+li x10, 0x1e4b791a20000000
+grevi x11, x10, 7
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 0x5FCB4D02D0000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5fcb4d02d0000000;
+li x10, 0x5fcb4d02d0000000
+grevi x11, x10, 7
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 0x98BA52AA88000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98ba52aa88000000;
+li x10, 0x98ba52aa88000000
+grevi x11, x10, 7
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 0xEE0923E014000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee0923e014000000;
+li x10, 0xee0923e014000000
+grevi x11, x10, 7
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 0x4BD47F4A3A000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bd47f4a3a000000;
+li x10, 0x4bd47f4a3a000000
+grevi x11, x10, 7
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 0xB30F8F95F1000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb30f8f95f1000000;
+li x10, 0xb30f8f95f1000000
+grevi x11, x10, 7
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 0x398261A02E800000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x398261a02e800000;
+li x10, 0x398261a02e800000
+grevi x11, x10, 7
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 0x0AF5E9EFD7C00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf5e9efd7c00000;
+li x10, 0xaf5e9efd7c00000
+grevi x11, x10, 7
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 0x4BCCF299A5E00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4bccf299a5e00000;
+li x10, 0x4bccf299a5e00000
+grevi x11, x10, 7
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 0xAFF56459AFF00000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff56459aff00000;
+li x10, 0xaff56459aff00000
+grevi x11, x10, 7
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 0xE07D7EDD48F80000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe07d7edd48f80000;
+li x10, 0xe07d7edd48f80000
+grevi x11, x10, 7
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 0x26604C6677840000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x26604c6677840000;
+li x10, 0x26604c6677840000
+grevi x11, x10, 7
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 0x5F67A33C644A0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f67a33c644a0000;
+li x10, 0x5f67a33c644a0000
+grevi x11, x10, 7
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 0xCC710F0F1C6B0000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcc710f0f1c6b0000;
+li x10, 0xcc710f0f1c6b0000
+grevi x11, x10, 7
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 0x86BA73F6EC348000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x86ba73f6ec348000;
+li x10, 0x86ba73f6ec348000
+grevi x11, x10, 7
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 0x51EACA62967E4000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x51eaca62967e4000;
+li x10, 0x51eaca62967e4000
+grevi x11, x10, 7
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 0xD52F0E14EDC96000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd52f0e14edc96000;
+li x10, 0xd52f0e14edc96000
+grevi x11, x10, 7
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 0x0DBD625329043000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbd625329043000;
+li x10, 0xdbd625329043000
+grevi x11, x10, 7
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 0x6DCF0D4A62B5D800 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6dcf0d4a62b5d800;
+li x10, 0x6dcf0d4a62b5d800
+grevi x11, x10, 7
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 0xB4B31E3B962C1C00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb4b31e3b962c1c00;
+li x10, 0xb4b31e3b962c1c00
+grevi x11, x10, 7
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 0x8DCD6133F22D6600 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8dcd6133f22d6600;
+li x10, 0x8dcd6133f22d6600
+grevi x11, x10, 7
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 0x45AF1CB0CAAE1D00 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x45af1cb0caae1d00;
+li x10, 0x45af1cb0caae1d00
+grevi x11, x10, 7
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 0xE86EB367B97C2C80 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe86eb367b97c2c80;
+li x10, 0xe86eb367b97c2c80
+grevi x11, x10, 7
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 0x2D9BE3118A013740 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2d9be3118a013740;
+li x10, 0x2d9be3118a013740
+grevi x11, x10, 7
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 0x70F53C4BFDFD2260 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70f53c4bfdfd2260;
+li x10, 0x70f53c4bfdfd2260
+grevi x11, x10, 7
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 0xF22A27B02C7BFF30 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf22a27b02c7bff30;
+li x10, 0xf22a27b02c7bff30
+grevi x11, x10, 7
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 0x0D99CFF9240BA738 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd99cff9240ba738;
+li x10, 0xd99cff9240ba738
+grevi x11, x10, 7
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 0x662E236EAA6781EC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x662e236eaa6781ec;
+li x10, 0x662e236eaa6781ec
+grevi x11, x10, 7
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 0x0EEA3A9950A03C5A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xeea3a9950a03c5a;
+li x10, 0xeea3a9950a03c5a
+grevi x11, x10, 7
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 0x44DCDA6A797D76DF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x44dcda6a797d76df;
+li x10, 0x44dcda6a797d76df
+grevi x11, x10, 7
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 0x39935C590B0FB71C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39935c590b0fb71c;
+li x10, 0x39935c590b0fb71c
+grevi x11, x10, 7
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 0xDE14BFF2EED7A249 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xde14bff2eed7a249;
+li x10, 0xde14bff2eed7a249
+grevi x11, x10, 7
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 0x6C9FEE24B808A67B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c9fee24b808a67b;
+li x10, 0x6c9fee24b808a67b
+grevi x11, x10, 7
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 0x008EEF6A63C2A497 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8eef6a63c2a497;
+li x10, 0x8eef6a63c2a497
+grevi x11, x10, 7
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 0x76B1FD3DF423752F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x76b1fd3df423752f;
+li x10, 0x76b1fd3df423752f
+grevi x11, x10, 7
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 0xA10BC6CCA6B7201F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa10bc6cca6b7201f;
+li x10, 0xa10bc6cca6b7201f
+grevi x11, x10, 7
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 0x6E2D704512C233BF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6e2d704512c233bf;
+li x10, 0x6e2d704512c233bf
+grevi x11, x10, 7
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 0x218FDC135DCF017F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x218fdc135dcf017f;
+li x10, 0x218fdc135dcf017f
+grevi x11, x10, 7
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 0xB3988B5231C8B6FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb3988b5231c8b6ff;
+li x10, 0xb3988b5231c8b6ff
+grevi x11, x10, 7
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 0xE2F99B2A3C5569FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe2f99b2a3c5569ff;
+li x10, 0xe2f99b2a3c5569ff
+grevi x11, x10, 7
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 0x90BB34803C4643FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x90bb34803c4643ff;
+li x10, 0x90bb34803c4643ff
+grevi x11, x10, 7
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 0x8CCE89147DA8D7FF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cce89147da8d7ff;
+li x10, 0x8cce89147da8d7ff
+grevi x11, x10, 7
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 0x93C38B33217ACFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x93c38b33217acfff;
+li x10, 0x93c38b33217acfff
+grevi x11, x10, 7
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 0xE3A707D665505FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe3a707d665505fff;
+li x10, 0xe3a707d665505fff
+grevi x11, x10, 7
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 0x47B7097B9B01BFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x47b7097b9b01bfff;
+li x10, 0x47b7097b9b01bfff
+grevi x11, x10, 7
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 0x4302DA54759F7FFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4302da54759f7fff;
+li x10, 0x4302da54759f7fff
+grevi x11, x10, 7
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 0x5F013C8240D8FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5f013c8240d8ffff;
+li x10, 0x5f013c8240d8ffff
+grevi x11, x10, 7
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 0x5B33199985CDFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b33199985cdffff;
+li x10, 0x5b33199985cdffff
+grevi x11, x10, 7
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 0x2DEDF12233DBFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2dedf12233dbffff;
+li x10, 0x2dedf12233dbffff
+grevi x11, x10, 7
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 0x4B1634E12D37FFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4b1634e12d37ffff;
+li x10, 0x4b1634e12d37ffff
+grevi x11, x10, 7
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0x8935B826718FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8935b826718fffff;
+li x10, 0x8935b826718fffff
+grevi x11, x10, 7
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0xBA9C678AAD5FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xba9c678aad5fffff;
+li x10, 0xba9c678aad5fffff
+grevi x11, x10, 7
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0x70BCB8E322BFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x70bcb8e322bfffff;
+li x10, 0x70bcb8e322bfffff
+grevi x11, x10, 7
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0xFCB627AFBF7FFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfcb627afbf7fffff;
+li x10, 0xfcb627afbf7fffff
+grevi x11, x10, 7
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0x9C76DF528CFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x9c76df528cffffff;
+li x10, 0x9c76df528cffffff
+grevi x11, x10, 7
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0x72C8DD98B1FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x72c8dd98b1ffffff;
+li x10, 0x72c8dd98b1ffffff
+grevi x11, x10, 7
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x434CBF26FBFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x434cbf26fbffffff;
+li x10, 0x434cbf26fbffffff
+grevi x11, x10, 7
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0xA23FB787C7FFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa23fb787c7ffffff;
+li x10, 0xa23fb787c7ffffff
+grevi x11, x10, 7
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x983CA1BECFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x983ca1becfffffff;
+li x10, 0x983ca1becfffffff
+grevi x11, x10, 7
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0x589218431FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x589218431fffffff;
+li x10, 0x589218431fffffff
+grevi x11, x10, 7
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xA7BE99AE3FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7be99ae3fffffff;
+li x10, 0xa7be99ae3fffffff
+grevi x11, x10, 7
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xA37E37287FFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa37e37287fffffff;
+li x10, 0xa37e37287fffffff
+grevi x11, x10, 7
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xE37D3738FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe37d3738ffffffff;
+li x10, 0xe37d3738ffffffff
+grevi x11, x10, 7
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xABB4DA1DFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xabb4da1dffffffff;
+li x10, 0xabb4da1dffffffff
+grevi x11, x10, 7
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0xFB3E7193FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfb3e7193ffffffff;
+li x10, 0xfb3e7193ffffffff
+grevi x11, x10, 7
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0x8CB950A7FFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8cb950a7ffffffff;
+li x10, 0x8cb950a7ffffffff
+grevi x11, x10, 7
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0xE5F31BEFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe5f31befffffffff;
+li x10, 0xe5f31befffffffff
+grevi x11, x10, 7
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x3BE93F9FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3be93f9fffffffff;
+li x10, 0x3be93f9fffffffff
+grevi x11, x10, 7
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0x5B1196BFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5b1196bfffffffff;
+li x10, 0x5b1196bfffffffff
+grevi x11, x10, 7
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 0xE084097FFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe084097fffffffff;
+li x10, 0xe084097fffffffff
+grevi x11, x10, 7
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 0x23B6BCFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23b6bcffffffffff;
+li x10, 0x23b6bcffffffffff
+grevi x11, x10, 7
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 0x6FCFD5FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6fcfd5ffffffffff;
+li x10, 0x6fcfd5ffffffffff
+grevi x11, x10, 7
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 0x73790BFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x73790bffffffffff;
+li x10, 0x73790bffffffffff
+grevi x11, x10, 7
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 0x432FF7FFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x432ff7ffffffffff;
+li x10, 0x432ff7ffffffffff
+grevi x11, x10, 7
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 0xE36B0FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe36b0fffffffffff;
+li x10, 0xe36b0fffffffffff
+grevi x11, x10, 7
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 0xCB4ADFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xcb4adfffffffffff;
+li x10, 0xcb4adfffffffffff
+grevi x11, x10, 7
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 0x15BF3FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15bf3fffffffffff;
+li x10, 0x15bf3fffffffffff
+grevi x11, x10, 7
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 0xD59A7FFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd59a7fffffffffff;
+li x10, 0xd59a7fffffffffff
+grevi x11, x10, 7
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 0xFE32FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfe32ffffffffffff;
+li x10, 0xfe32ffffffffffff
+grevi x11, x10, 7
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 0xFF7DFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff7dffffffffffff;
+li x10, 0xff7dffffffffffff
+grevi x11, x10, 7
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 0xAF23FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaf23ffffffffffff;
+li x10, 0xaf23ffffffffffff
+grevi x11, x10, 7
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 0x2057FFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2057ffffffffffff;
+li x10, 0x2057ffffffffffff
+grevi x11, x10, 7
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 0x07AFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7afffffffffffff;
+li x10, 0x7afffffffffffff
+grevi x11, x10, 7
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 0xBE9FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbe9fffffffffffff;
+li x10, 0xbe9fffffffffffff
+grevi x11, x10, 7
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 0xD8BFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd8bfffffffffffff;
+li x10, 0xd8bfffffffffffff
+grevi x11, x10, 7
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 0x127FFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x127fffffffffffff;
+li x10, 0x127fffffffffffff
+grevi x11, x10, 7
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 0x2EFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2effffffffffffff;
+li x10, 0x2effffffffffffff
+grevi x11, x10, 7
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 0xA5FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa5ffffffffffffff;
+li x10, 0xa5ffffffffffffff
+grevi x11, x10, 7
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 0xDBFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdbffffffffffffff;
+li x10, 0xdbffffffffffffff
+grevi x11, x10, 7
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 0xA7FFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa7ffffffffffffff;
+li x10, 0xa7ffffffffffffff
+grevi x11, x10, 7
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 0xAFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xafffffffffffffff;
+li x10, 0xafffffffffffffff
+grevi x11, x10, 7
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 0xDFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xdfffffffffffffff;
+li x10, 0xdfffffffffffffff
+grevi x11, x10, 7
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 0xBFFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xbfffffffffffffff;
+li x10, 0xbfffffffffffffff
+grevi x11, x10, 7
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 0x7FFFFFFFFFFFFFFF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7fffffffffffffff;
+li x10, 0x7fffffffffffffff
+grevi x11, x10, 7
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 0xA274EA181E34B3F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xa274ea181e34b3f2;
+li x10, 0xa274ea181e34b3f2
+grevi x11, x10, 7
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 0x6C3FBF4DC20EF165 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c3fbf4dc20ef165;
+li x10, 0x6c3fbf4dc20ef165
+grevi x11, x10, 7
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 0x28F918D8F6CDB2F9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x28f918d8f6cdb2f9;
+li x10, 0x28f918d8f6cdb2f9
+grevi x11, x10, 7
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 0x13E0D681552454F2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13e0d681552454f2;
+li x10, 0x13e0d681552454f2
+grevi x11, x10, 7
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 0x0FAB6F3E164F1514 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfab6f3e164f1514;
+li x10, 0xfab6f3e164f1514
+grevi x11, x10, 7
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 0x063E9BED45100359 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63e9bed45100359;
+li x10, 0x63e9bed45100359
+grevi x11, x10, 7
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 0x02C6D8F2C74C7CD0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2c6d8f2c74c7cd0;
+li x10, 0x2c6d8f2c74c7cd0
+grevi x11, x10, 7
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 0x01D03FDDA123F502 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d03fdda123f502;
+li x10, 0x1d03fdda123f502
+grevi x11, x10, 7
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 0x00F5380E12B2A415 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf5380e12b2a415;
+li x10, 0xf5380e12b2a415
+grevi x11, x10, 7
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 0x0077730F65BD9ACC 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x77730f65bd9acc;
+li x10, 0x77730f65bd9acc
+grevi x11, x10, 7
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 0x003A6A1DFAF8CDAA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3a6a1dfaf8cdaa;
+li x10, 0x3a6a1dfaf8cdaa
+grevi x11, x10, 7
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 0x001E5B4578511609 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1e5b4578511609;
+li x10, 0x1e5b4578511609
+grevi x11, x10, 7
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 0x000D0372E90794E0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xd0372e90794e0;
+li x10, 0xd0372e90794e0
+grevi x11, x10, 7
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 0x0006A24135B00A55 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6a24135b00a55;
+li x10, 0x6a24135b00a55
+grevi x11, x10, 7
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 0x00020BDF0023B683 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x20bdf0023b683;
+li x10, 0x20bdf0023b683
+grevi x11, x10, 7
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 0x000170EED8E94B16 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x170eed8e94b16;
+li x10, 0x170eed8e94b16
+grevi x11, x10, 7
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 0x0000EF05F542441E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xef05f542441e;
+li x10, 0xef05f542441e
+grevi x11, x10, 7
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 0x00004AAA62F28D1B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x4aaa62f28d1b;
+li x10, 0x4aaa62f28d1b
+grevi x11, x10, 7
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 0x00003CB3D8B9B45D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3cb3d8b9b45d;
+li x10, 0x3cb3d8b9b45d
+grevi x11, x10, 7
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 0x00001BE466809A12 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1be466809a12;
+li x10, 0x1be466809a12
+grevi x11, x10, 7
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_150:
+// rs1_val == 0x0000092EC42B7171 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x92ec42b7171;
+li x10, 0x92ec42b7171
+grevi x11, x10, 7
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_151:
+// rs1_val == 0x0000074F11FA2AC1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x74f11fa2ac1;
+li x10, 0x74f11fa2ac1
+grevi x11, x10, 7
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_152:
+// rs1_val == 0x0000025A49FE85B1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x25a49fe85b1;
+li x10, 0x25a49fe85b1
+grevi x11, x10, 7
+sw x11, 1032(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_153:
+// rs1_val == 0x0000017A3ACB6267 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a3acb6267;
+li x10, 0x17a3acb6267
+grevi x11, x10, 7
+sw x11, 1040(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_154:
+// rs1_val == 0x000000C250B601FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc250b601fd;
+li x10, 0xc250b601fd
+grevi x11, x10, 7
+sw x11, 1048(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_155:
+// rs1_val == 0x00000067B53302FD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x67b53302fd;
+li x10, 0x67b53302fd
+grevi x11, x10, 7
+sw x11, 1056(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_156:
+// rs1_val == 0x0000002AD7185DDB 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2ad7185ddb;
+li x10, 0x2ad7185ddb
+grevi x11, x10, 7
+sw x11, 1064(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_157:
+// rs1_val == 0x0000001FFEE5A5B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1ffee5a5b3;
+li x10, 0x1ffee5a5b3
+grevi x11, x10, 7
+sw x11, 1072(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_158:
+// rs1_val == 0x0000000AFF66658A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xaff66658a;
+li x10, 0xaff66658a
+grevi x11, x10, 7
+sw x11, 1080(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_159:
+// rs1_val == 0x000000064735AF1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x64735af1d;
+li x10, 0x64735af1d
+grevi x11, x10, 7
+sw x11, 1088(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_160:
+// rs1_val == 0x0000000275139238 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x275139238;
+li x10, 0x275139238
+grevi x11, x10, 7
+sw x11, 1096(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_161:
+// rs1_val == 0x00000001A9964AF0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1a9964af0;
+li x10, 0x1a9964af0
+grevi x11, x10, 7
+sw x11, 1104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_162:
+// rs1_val == 0x00000000FFF1222A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff1222a;
+li x10, 0xfff1222a
+grevi x11, x10, 7
+sw x11, 1112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_163:
+// rs1_val == 0x0000000063EA284E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x63ea284e;
+li x10, 0x63ea284e
+grevi x11, x10, 7
+sw x11, 1120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_164:
+// rs1_val == 0x0000000024E55161 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x24e55161;
+li x10, 0x24e55161
+grevi x11, x10, 7
+sw x11, 1128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_165:
+// rs1_val == 0x0000000017A94DEE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x17a94dee;
+li x10, 0x17a94dee
+grevi x11, x10, 7
+sw x11, 1136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_166:
+// rs1_val == 0x0000000008C6A5B9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8c6a5b9;
+li x10, 0x8c6a5b9
+grevi x11, x10, 7
+sw x11, 1144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_167:
+// rs1_val == 0x0000000006C468AF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6c468af;
+li x10, 0x6c468af
+grevi x11, x10, 7
+sw x11, 1152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_168:
+// rs1_val == 0x0000000003B37E15 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x3b37e15;
+li x10, 0x3b37e15
+grevi x11, x10, 7
+sw x11, 1160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_169:
+// rs1_val == 0x0000000001EFFA39 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1effa39;
+li x10, 0x1effa39
+grevi x11, x10, 7
+sw x11, 1168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_170:
+// rs1_val == 0x0000000000B17D0C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xb17d0c;
+li x10, 0xb17d0c
+grevi x11, x10, 7
+sw x11, 1176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_171:
+// rs1_val == 0x00000000007EBDD4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x7ebdd4;
+li x10, 0x7ebdd4
+grevi x11, x10, 7
+sw x11, 1184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_172:
+// rs1_val == 0x000000000023FEB7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x23feb7;
+li x10, 0x23feb7
+grevi x11, x10, 7
+sw x11, 1192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_173:
+// rs1_val == 0x0000000000171685 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x171685;
+li x10, 0x171685
+grevi x11, x10, 7
+sw x11, 1200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_174:
+// rs1_val == 0x0000000000098868 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x98868;
+li x10, 0x98868
+grevi x11, x10, 7
+sw x11, 1208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_175:
+// rs1_val == 0x000000000005847F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5847f;
+li x10, 0x5847f
+grevi x11, x10, 7
+sw x11, 1216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_176:
+// rs1_val == 0x0000000000037797 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x37797;
+li x10, 0x37797
+grevi x11, x10, 7
+sw x11, 1224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_177:
+// rs1_val == 0x0000000000015DB9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x15db9;
+li x10, 0x15db9
+grevi x11, x10, 7
+sw x11, 1232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_178:
+// rs1_val == 0x0000000000008735 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x8735;
+li x10, 0x8735
+grevi x11, x10, 7
+sw x11, 1240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_179:
+// rs1_val == 0x0000000000006B68 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6b68;
+li x10, 0x6b68
+grevi x11, x10, 7
+sw x11, 1248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_180:
+// rs1_val == 0x0000000000002F28 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2f28;
+li x10, 0x2f28
+grevi x11, x10, 7
+sw x11, 1256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_181:
+// rs1_val == 0x0000000000001D40 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1d40;
+li x10, 0x1d40
+grevi x11, x10, 7
+sw x11, 1264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_182:
+// rs1_val == 0x0000000000000F26 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf26;
+li x10, 0xf26
+grevi x11, x10, 7
+sw x11, 1272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_183:
+// rs1_val == 0x0000000000000482 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x482;
+li x10, 0x482
+grevi x11, x10, 7
+sw x11, 1280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_184:
+// rs1_val == 0x0000000000000394 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x394;
+li x10, 0x394
+grevi x11, x10, 7
+sw x11, 1288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_185:
+// rs1_val == 0x0000000000000154 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x154;
+li x10, 0x154
+grevi x11, x10, 7
+sw x11, 1296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_186:
+// rs1_val == 0x00000000000000FA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfa;
+li x10, 0xfa
+grevi x11, x10, 7
+sw x11, 1304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_187:
+// rs1_val == 0x0000000000000043 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x43;
+li x10, 0x43
+grevi x11, x10, 7
+sw x11, 1312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_188:
+// rs1_val == 0x0000000000000039 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x39;
+li x10, 0x39
+grevi x11, x10, 7
+sw x11, 1320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_189:
+// rs1_val == 0x0000000000000013 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x13;
+li x10, 0x13
+grevi x11, x10, 7
+sw x11, 1328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_190:
+// rs1_val == 0x000000000000000E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xe;
+li x10, 0xe
+grevi x11, x10, 7
+sw x11, 1336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_191:
+// rs1_val == 0x0000000000000006 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x6;
+li x10, 0x6
+grevi x11, x10, 7
+sw x11, 1344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_192:
+// rs1_val == 0x0000000000000002 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+grevi x11, x10, 7
+sw x11, 1352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_193:
+// rs1_val == 0x0000000000000001 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+grevi x11, x10, 7
+sw x11, 1360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_194:
+// rs1_val == 0x5D68F2012DAF94C2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x5d68f2012daf94c2;
+li x10, 0x5d68f2012daf94c2
+grevi x11, x10, 7
+sw x11, 1368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_195:
+// rs1_val == 0x85986ADB9E044707 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x85986adb9e044707;
+li x10, 0x85986adb9e044707
+grevi x11, x10, 7
+sw x11, 1376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_196:
+// rs1_val == 0xC4BD48204652F62E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xc4bd48204652f62e;
+li x10, 0xc4bd48204652f62e
+grevi x11, x10, 7
+sw x11, 1384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_197:
+// rs1_val == 0xEE4839A13ED7E667 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xee4839a13ed7e667;
+li x10, 0xee4839a13ed7e667
+grevi x11, x10, 7
+sw x11, 1392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_198:
+// rs1_val == 0xF213516D6A013381 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf213516d6a013381;
+li x10, 0xf213516d6a013381
+grevi x11, x10, 7
+sw x11, 1400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_199:
+// rs1_val == 0xF871CFDE6EE84271 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xf871cfde6ee84271;
+li x10, 0xf871cfde6ee84271
+grevi x11, x10, 7
+sw x11, 1408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_200:
+// rs1_val == 0xFD432A19F29C11AE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfd432a19f29c11ae;
+li x10, 0xfd432a19f29c11ae
+grevi x11, x10, 7
+sw x11, 1416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_201:
+// rs1_val == 0xFEE0888FCEB506F7 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfee0888fceb506f7;
+li x10, 0xfee0888fceb506f7
+grevi x11, x10, 7
+sw x11, 1424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_202:
+// rs1_val == 0xFF605EE62A96D06B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff605ee62a96d06b;
+li x10, 0xff605ee62a96d06b
+grevi x11, x10, 7
+sw x11, 1432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_203:
+// rs1_val == 0xFF89799918BB28EA 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xff89799918bb28ea;
+li x10, 0xff89799918bb28ea
+grevi x11, x10, 7
+sw x11, 1440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_204:
+// rs1_val == 0xFFCC6148C6880008 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffcc6148c6880008;
+li x10, 0xffcc6148c6880008
+grevi x11, x10, 7
+sw x11, 1448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_205:
+// rs1_val == 0xFFEB5EA11CE80B13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffeb5ea11ce80b13;
+li x10, 0xffeb5ea11ce80b13
+grevi x11, x10, 7
+sw x11, 1456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_206:
+// rs1_val == 0xFFF039F699EF1858 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfff039f699ef1858;
+li x10, 0xfff039f699ef1858
+grevi x11, x10, 7
+sw x11, 1464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_207:
+// rs1_val == 0xFFFBEA615FC9EBA5 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffbea615fc9eba5;
+li x10, 0xfffbea615fc9eba5
+grevi x11, x10, 7
+sw x11, 1472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_208:
+// rs1_val == 0xFFFC8D619136580C 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffc8d619136580c;
+li x10, 0xfffc8d619136580c
+grevi x11, x10, 7
+sw x11, 1480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_209:
+// rs1_val == 0xFFFE46462651F638 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffe46462651f638;
+li x10, 0xfffe46462651f638
+grevi x11, x10, 7
+sw x11, 1488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_210:
+// rs1_val == 0xFFFF1C79DAE98555 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff1c79dae98555;
+li x10, 0xffff1c79dae98555
+grevi x11, x10, 7
+sw x11, 1496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_211:
+// rs1_val == 0xFFFF8E6F889263CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffff8e6f889263cf;
+li x10, 0xffff8e6f889263cf
+grevi x11, x10, 7
+sw x11, 1504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_212:
+// rs1_val == 0xFFFFDEE2A86B8A6F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffdee2a86b8a6f;
+li x10, 0xffffdee2a86b8a6f
+grevi x11, x10, 7
+sw x11, 1512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_213:
+// rs1_val == 0xFFFFE2AFD167533B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffe2afd167533b;
+li x10, 0xffffe2afd167533b
+grevi x11, x10, 7
+sw x11, 1520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_214:
+// rs1_val == 0xFFFFF1A07F216823 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff1a07f216823;
+li x10, 0xfffff1a07f216823
+grevi x11, x10, 7
+sw x11, 1528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_215:
+// rs1_val == 0xFFFFF9090973E89D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffff9090973e89d;
+li x10, 0xfffff9090973e89d
+grevi x11, x10, 7
+sw x11, 1536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_216:
+// rs1_val == 0xFFFFFC3769B1DCC0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffc3769b1dcc0;
+li x10, 0xfffffc3769b1dcc0
+grevi x11, x10, 7
+sw x11, 1544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_217:
+// rs1_val == 0xFFFFFEB8396BA83B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffeb8396ba83b;
+li x10, 0xfffffeb8396ba83b
+grevi x11, x10, 7
+sw x11, 1552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_218:
+// rs1_val == 0xFFFFFF4F280B11FE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff4f280b11fe;
+li x10, 0xffffff4f280b11fe
+grevi x11, x10, 7
+sw x11, 1560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_219:
+// rs1_val == 0xFFFFFF85D814D576 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffff85d814d576;
+li x10, 0xffffff85d814d576
+grevi x11, x10, 7
+sw x11, 1568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_220:
+// rs1_val == 0xFFFFFFCC95A4D258 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffcc95a4d258;
+li x10, 0xffffffcc95a4d258
+grevi x11, x10, 7
+sw x11, 1576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_221:
+// rs1_val == 0xFFFFFFE610A37559 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffe610a37559;
+li x10, 0xffffffe610a37559
+grevi x11, x10, 7
+sw x11, 1584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_222:
+// rs1_val == 0xFFFFFFF66F9FB998 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffff66f9fb998;
+li x10, 0xfffffff66f9fb998
+grevi x11, x10, 7
+sw x11, 1592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_223:
+// rs1_val == 0xFFFFFFFB8C8A18B3 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffb8c8a18b3;
+li x10, 0xfffffffb8c8a18b3
+grevi x11, x10, 7
+sw x11, 1600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_224:
+// rs1_val == 0xFFFFFFFC507A2561 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffc507a2561;
+li x10, 0xfffffffc507a2561
+grevi x11, x10, 7
+sw x11, 1608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_225:
+// rs1_val == 0xFFFFFFFEE5F0307F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffee5f0307f;
+li x10, 0xfffffffee5f0307f
+grevi x11, x10, 7
+sw x11, 1616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_226:
+// rs1_val == 0xFFFFFFFF5DBBB7CF 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff5dbbb7cf;
+li x10, 0xffffffff5dbbb7cf
+grevi x11, x10, 7
+sw x11, 1624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_227:
+// rs1_val == 0xFFFFFFFF8D884510 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffff8d884510;
+li x10, 0xffffffff8d884510
+grevi x11, x10, 7
+sw x11, 1632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_228:
+// rs1_val == 0xFFFFFFFFD0E58651 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffd0e58651;
+li x10, 0xffffffffd0e58651
+grevi x11, x10, 7
+sw x11, 1640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_229:
+// rs1_val == 0xFFFFFFFFE24C0602 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffe24c0602;
+li x10, 0xffffffffe24c0602
+grevi x11, x10, 7
+sw x11, 1648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_230:
+// rs1_val == 0xFFFFFFFFF109C208 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffff109c208;
+li x10, 0xfffffffff109c208
+grevi x11, x10, 7
+sw x11, 1656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_231:
+// rs1_val == 0xFFFFFFFFFB54AA23 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffb54aa23;
+li x10, 0xfffffffffb54aa23
+grevi x11, x10, 7
+sw x11, 1664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_232:
+// rs1_val == 0xFFFFFFFFFD02FC91 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffd02fc91;
+li x10, 0xfffffffffd02fc91
+grevi x11, x10, 7
+sw x11, 1672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_233:
+// rs1_val == 0xFFFFFFFFFE29D2A0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffe29d2a0;
+li x10, 0xfffffffffe29d2a0
+grevi x11, x10, 7
+sw x11, 1680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_234:
+// rs1_val == 0xFFFFFFFFFF7F6F5E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff7f6f5e;
+li x10, 0xffffffffff7f6f5e
+grevi x11, x10, 7
+sw x11, 1688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_235:
+// rs1_val == 0xFFFFFFFFFF9104D1 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffff9104d1;
+li x10, 0xffffffffff9104d1
+grevi x11, x10, 7
+sw x11, 1696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_236:
+// rs1_val == 0xFFFFFFFFFFCADB0B 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffcadb0b;
+li x10, 0xffffffffffcadb0b
+grevi x11, x10, 7
+sw x11, 1704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_237:
+// rs1_val == 0xFFFFFFFFFFEEC2B4 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffeec2b4;
+li x10, 0xffffffffffeec2b4
+grevi x11, x10, 7
+sw x11, 1712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_238:
+// rs1_val == 0xFFFFFFFFFFF49E5F 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffff49e5f;
+li x10, 0xfffffffffff49e5f
+grevi x11, x10, 7
+sw x11, 1720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_239:
+// rs1_val == 0xFFFFFFFFFFFAE2EE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffae2ee;
+li x10, 0xfffffffffffae2ee
+grevi x11, x10, 7
+sw x11, 1728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_240:
+// rs1_val == 0xFFFFFFFFFFFC7F0E 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffc7f0e;
+li x10, 0xfffffffffffc7f0e
+grevi x11, x10, 7
+sw x11, 1736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_241:
+// rs1_val == 0xFFFFFFFFFFFE3410 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffe3410;
+li x10, 0xfffffffffffe3410
+grevi x11, x10, 7
+sw x11, 1744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_242:
+// rs1_val == 0xFFFFFFFFFFFF6E0A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffff6e0a;
+li x10, 0xffffffffffff6e0a
+grevi x11, x10, 7
+sw x11, 1752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_243:
+// rs1_val == 0xFFFFFFFFFFFFB32A 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffb32a;
+li x10, 0xffffffffffffb32a
+grevi x11, x10, 7
+sw x11, 1760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_244:
+// rs1_val == 0xFFFFFFFFFFFFC384 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffc384;
+li x10, 0xffffffffffffc384
+grevi x11, x10, 7
+sw x11, 1768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_245:
+// rs1_val == 0xFFFFFFFFFFFFEC1D 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffec1d;
+li x10, 0xffffffffffffec1d
+grevi x11, x10, 7
+sw x11, 1776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_246:
+// rs1_val == 0xFFFFFFFFFFFFF3F0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffff3f0;
+li x10, 0xfffffffffffff3f0
+grevi x11, x10, 7
+sw x11, 1784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_247:
+// rs1_val == 0xFFFFFFFFFFFFFB13 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffb13;
+li x10, 0xfffffffffffffb13
+grevi x11, x10, 7
+sw x11, 1792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_248:
+// rs1_val == 0xFFFFFFFFFFFFFC31 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffc31;
+li x10, 0xfffffffffffffc31
+grevi x11, x10, 7
+sw x11, 1800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_249:
+// rs1_val == 0xFFFFFFFFFFFFFE44 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffe44;
+li x10, 0xfffffffffffffe44
+grevi x11, x10, 7
+sw x11, 1808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_250:
+// rs1_val == 0xFFFFFFFFFFFFFF58 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffff58;
+li x10, 0xffffffffffffff58
+grevi x11, x10, 7
+sw x11, 1816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_251:
+// rs1_val == 0xFFFFFFFFFFFFFFB0 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffb0;
+li x10, 0xffffffffffffffb0
+grevi x11, x10, 7
+sw x11, 1824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_252:
+// rs1_val == 0xFFFFFFFFFFFFFFC6 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffc6;
+li x10, 0xffffffffffffffc6
+grevi x11, x10, 7
+sw x11, 1832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_253:
+// rs1_val == 0xFFFFFFFFFFFFFFE8 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xffffffffffffffe8;
+li x10, 0xffffffffffffffe8
+grevi x11, x10, 7
+sw x11, 1840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_254:
+// rs1_val == 0xFFFFFFFFFFFFFFF2 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff2;
+li x10, 0xfffffffffffffff2
+grevi x11, x10, 7
+sw x11, 1848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_255:
+// rs1_val == 0xFFFFFFFFFFFFFFF9 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffff9;
+li x10, 0xfffffffffffffff9
+grevi x11, x10, 7
+sw x11, 1856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_256:
+// rs1_val == 0xFFFFFFFFFFFFFFFD 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+grevi x11, x10, 7
+sw x11, 1864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_257:
+// rs1_val == 0xFFFFFFFFFFFFFFFE 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+grevi x11, x10, 7
+sw x11, 1872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_258:
+// rs1_val == 0x9480000000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x9480000000000000;
+li x10, 0x9480000000000000
+grevi x11, x10, 7
+sw x11, 1880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_259:
+// rs1_val == 0x77B0000000000000 
+// opcode: grevi ; op1:x10; dest:x11; op1val:0x77b0000000000000;
+li x10, 0x77b0000000000000
+grevi x11, x10, 7
+sw x11, 1888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x15_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x15_1:
+    .fill 23*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 237*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S
new file mode 100644
index 000000000..945868cea
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rol-01.S
@@ -0,0 +1,2716 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the rol instruction of the RISC-V  extension for the rol covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rol)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",rol)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",rol)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",rol)
+
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x27, rs2==x27, rd==x18, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rol ; op1:x27; op2:x27; dest:x18; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(rol, x18, x27, x27, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x1, 0, x5)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x10, rs2==x10, rd==x10, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rol ; op1:x10; op2:x10; dest:x10; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(rol, x10, x10, x10, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x1, 8, x5)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x7, rs2==x11, rd==x29, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: rol ; op1:x7; op2:x11; dest:x29; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(rol, x29, x7, x11, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x1, 16, x5)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x3, rs2==x29, rd==x3, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: rol ; op1:x3; op2:x29; dest:x3; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(rol, x3, x3, x29, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x1, 24, x5)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x11, rs2==x12, rd==x12, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: rol ; op1:x11; op2:x12; dest:x12; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(rol, x12, x11, x12, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x1, 32, x5)
+
+inst_5:
+// rs1==x13, rs2==x22, rd==x20, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: rol ; op1:x13; op2:x22; dest:x20; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(rol, x20, x13, x22, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x1, 40, x5)
+
+inst_6:
+// rs1==x21, rs2==x19, rd==x9, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: rol ; op1:x21; op2:x19; dest:x9; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(rol, x9, x21, x19, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x1, 48, x5)
+
+inst_7:
+// rs1==x29, rs2==x0, rd==x23, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: rol ; op1:x29; op2:x0; dest:x23; op1val:0x2405b307cec7313a;  op2val:0x0
+TEST_RR_OP(rol, x23, x29, x0, 0x0000000000000000, 0x2405b307cec7313a, 0x0, x1, 56, x5)
+
+inst_8:
+// rs1==x0, rs2==x23, rd==x28, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: rol ; op1:x0; op2:x23; dest:x28; op1val:0x0;  op2val:0x8200000000000000
+TEST_RR_OP(rol, x28, x0, x23, 0x0000000000000000, 0x0, 0x8200000000000000, x1, 64, x5)
+
+inst_9:
+// rs1==x15, rs2==x20, rd==x25, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: rol ; op1:x15; op2:x20; dest:x25; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(rol, x25, x15, x20, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x1, 72, x5)
+
+inst_10:
+// rs1==x30, rs2==x9, rd==x11, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: rol ; op1:x30; op2:x9; dest:x11; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(rol, x11, x30, x9, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x1, 80, x5)
+
+inst_11:
+// rs1==x16, rs2==x31, rd==x7, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: rol ; op1:x16; op2:x31; dest:x7; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(rol, x7, x16, x31, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x1, 88, x5)
+
+inst_12:
+// rs1==x6, rs2==x30, rd==x27, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: rol ; op1:x6; op2:x30; dest:x27; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(rol, x27, x6, x30, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x1, 96, x5)
+
+inst_13:
+// rs1==x24, rs2==x2, rd==x26, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: rol ; op1:x24; op2:x2; dest:x26; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(rol, x26, x24, x2, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x1, 104, x5)
+
+inst_14:
+// rs1==x28, rs2==x4, rd==x6, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: rol ; op1:x28; op2:x4; dest:x6; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(rol, x6, x28, x4, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x1, 112, x5)
+
+inst_15:
+// rs1==x22, rs2==x18, rd==x2, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: rol ; op1:x22; op2:x18; dest:x2; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(rol, x2, x22, x18, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x1, 120, x5)
+
+inst_16:
+// rs1==x17, rs2==x13, rd==x4, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: rol ; op1:x17; op2:x13; dest:x4; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(rol, x4, x17, x13, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x1, 128, x5)
+
+inst_17:
+// rs1==x20, rs2==x14, rd==x17, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: rol ; op1:x20; op2:x14; dest:x17; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(rol, x17, x20, x14, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x1, 136, x27)
+RVTEST_SIGBASE( x20,signature_x20_0)
+
+inst_18:
+// rs1==x2, rs2==x21, rd==x24, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: rol ; op1:x2; op2:x21; dest:x24; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(rol, x24, x2, x21, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x20, 0, x27)
+
+inst_19:
+// rs1==x23, rs2==x17, rd==x5, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: rol ; op1:x23; op2:x17; dest:x5; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(rol, x5, x23, x17, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x20, 8, x27)
+
+inst_20:
+// rs1==x14, rs2==x3, rd==x16, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: rol ; op1:x14; op2:x3; dest:x16; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(rol, x16, x14, x3, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x20, 16, x27)
+
+inst_21:
+// rs1==x25, rs2==x24, rd==x15, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: rol ; op1:x25; op2:x24; dest:x15; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(rol, x15, x25, x24, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x20, 24, x27)
+
+inst_22:
+// rs1==x1, rs2==x25, rd==x22, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: rol ; op1:x1; op2:x25; dest:x22; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(rol, x22, x1, x25, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x20, 32, x27)
+
+inst_23:
+// rs1==x4, rs2==x16, rd==x30, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: rol ; op1:x4; op2:x16; dest:x30; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(rol, x30, x4, x16, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x20, 40, x27)
+
+inst_24:
+// rs1==x31, rs2==x8, rd==x0, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: rol ; op1:x31; op2:x8; dest:x0; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(rol, x0, x31, x8, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x20, 48, x27)
+
+inst_25:
+// rs1==x12, rs2==x15, rd==x19, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: rol ; op1:x12; op2:x15; dest:x19; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(rol, x19, x12, x15, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x20, 56, x27)
+
+inst_26:
+// rs1==x18, rs2==x5, rd==x8, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: rol ; op1:x18; op2:x5; dest:x8; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(rol, x8, x18, x5, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x20, 64, x27)
+
+inst_27:
+// rs1==x8, rs2==x26, rd==x14, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: rol ; op1:x8; op2:x26; dest:x14; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(rol, x14, x8, x26, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x20, 72, x27)
+
+inst_28:
+// rs1==x19, rs2==x6, rd==x13, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: rol ; op1:x19; op2:x6; dest:x13; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(rol, x13, x19, x6, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x20, 80, x27)
+
+inst_29:
+// rs1==x9, rs2==x7, rd==x1, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: rol ; op1:x9; op2:x7; dest:x1; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(rol, x1, x9, x7, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x20, 88, x27)
+
+inst_30:
+// rs1==x26, rs2==x28, rd==x31, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: rol ; op1:x26; op2:x28; dest:x31; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(rol, x31, x26, x28, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x20, 96, x27)
+
+inst_31:
+// rs1==x5, rs2==x1, rd==x21, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: rol ; op1:x5; op2:x1; dest:x21; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(rol, x21, x5, x1, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x20, 104, x27)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x20, 112, x27)
+RVTEST_SIGBASE( x1,signature_x1_2)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x1, 0, x2)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x1, 8, x2)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x1, 16, x2)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x1, 24, x2)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x1, 32, x2)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x1, 40, x2)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x1, 48, x2)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x1, 56, x2)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x1, 64, x2)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x1, 72, x2)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x1, 80, x2)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x1, 88, x2)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x1, 96, x2)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x1, 104, x2)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x1, 112, x2)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x1, 120, x2)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x1, 128, x2)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x1, 136, x2)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x1, 144, x2)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x1, 152, x2)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x1, 160, x2)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x1, 168, x2)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x1, 176, x2)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x1, 184, x2)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x1, 192, x2)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x1, 200, x2)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x1, 208, x2)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x1, 216, x2)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x1, 224, x2)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x1, 232, x2)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x1, 240, x2)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x1, 248, x2)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x1, 256, x2)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x1, 264, x2)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x1, 272, x2)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x1, 280, x2)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x1, 288, x2)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x1, 296, x2)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x1, 304, x2)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x1, 312, x2)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x1, 320, x2)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x1, 328, x2)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x1, 336, x2)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x1, 344, x2)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x1, 352, x2)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x1, 360, x2)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x1, 368, x2)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x1, 376, x2)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x1, 384, x2)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x1, 392, x2)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x1, 400, x2)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x1, 408, x2)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x1, 416, x2)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x1, 424, x2)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x1, 432, x2)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x1, 440, x2)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x1, 448, x2)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x1, 456, x2)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x1, 464, x2)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x1, 472, x2)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x1, 480, x2)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x1, 488, x2)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x1, 496, x2)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x1, 504, x2)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x1, 512, x2)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x1, 520, x2)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x1, 528, x2)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x1, 536, x2)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x1, 544, x2)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x1, 552, x2)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x1, 560, x2)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x1, 568, x2)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x1, 576, x2)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x1, 584, x2)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x1, 592, x2)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x1, 600, x2)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x1, 608, x2)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x1, 616, x2)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x1, 624, x2)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x1, 632, x2)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x1, 640, x2)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x1, 648, x2)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x1, 656, x2)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x1, 664, x2)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x1, 672, x2)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x1, 680, x2)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x1, 688, x2)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x1, 696, x2)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x1, 704, x2)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x1, 712, x2)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x1, 720, x2)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x1, 728, x2)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x1, 736, x2)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x1, 744, x2)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x1, 752, x2)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x1, 760, x2)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x1, 768, x2)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x1, 776, x2)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x1, 784, x2)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x1, 792, x2)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x1, 800, x2)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x1, 808, x2)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x1, 816, x2)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x1, 824, x2)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x1, 832, x2)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x1, 840, x2)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x1, 848, x2)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x1, 856, x2)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x1, 864, x2)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x1, 872, x2)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x1, 880, x2)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x1, 888, x2)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x1, 896, x2)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x1, 904, x2)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x1, 912, x2)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x1, 920, x2)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x1, 928, x2)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x1, 936, x2)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x1, 944, x2)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x1, 952, x2)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x1, 960, x2)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x1, 968, x2)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x1, 976, x2)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x1, 984, x2)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x1, 992, x2)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x1, 1000, x2)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x1, 1008, x2)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x1, 1016, x2)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x1, 1024, x2)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x1, 1032, x2)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x1, 1040, x2)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x1, 1048, x2)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x1, 1056, x2)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x1, 1064, x2)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x1, 1072, x2)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x1, 1080, x2)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x1, 1088, x2)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x1, 1096, x2)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x1, 1104, x2)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x1, 1112, x2)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x1, 1120, x2)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x1, 1128, x2)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x1, 1136, x2)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x1, 1144, x2)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x1, 1152, x2)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x1, 1160, x2)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x1, 1168, x2)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x1, 1176, x2)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x1, 1184, x2)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x1, 1192, x2)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x1, 1200, x2)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x1, 1208, x2)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x1, 1216, x2)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x1, 1224, x2)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x1, 1232, x2)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x1, 1240, x2)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x1, 1248, x2)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x1, 1256, x2)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x1, 1264, x2)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x1, 1272, x2)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x1, 1280, x2)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x1, 1288, x2)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x1, 1296, x2)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x1, 1304, x2)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x1, 1312, x2)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x1, 1320, x2)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x1, 1328, x2)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x1, 1336, x2)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x1, 1344, x2)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x1, 1352, x2)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x1, 1360, x2)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x1, 1368, x2)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x1, 1376, x2)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x1, 1384, x2)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x1, 1392, x2)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x1, 1400, x2)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x1, 1408, x2)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x1, 1416, x2)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x1, 1424, x2)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x1, 1432, x2)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x1, 1440, x2)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x1, 1448, x2)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x1, 1456, x2)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x1, 1464, x2)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x1, 1472, x2)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x1, 1480, x2)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x1, 1488, x2)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x1, 1496, x2)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x1, 1504, x2)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x1, 1512, x2)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x1, 1520, x2)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x1, 1528, x2)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x1, 1536, x2)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x1, 1544, x2)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x1, 1552, x2)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x1, 1560, x2)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x1, 1568, x2)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x1, 1576, x2)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x1, 1584, x2)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x1, 1592, x2)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x1, 1600, x2)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x1, 1608, x2)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x1, 1616, x2)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x1, 1624, x2)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x1, 1632, x2)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x1, 1640, x2)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x1, 1648, x2)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x1, 1656, x2)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x1, 1664, x2)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x1, 1672, x2)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x1, 1680, x2)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x1, 1688, x2)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x1, 1696, x2)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x1, 1704, x2)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x1, 1712, x2)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x1, 1720, x2)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x1, 1728, x2)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x1, 1736, x2)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x1, 1744, x2)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x1, 1752, x2)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x1, 1760, x2)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x1, 1768, x2)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x1, 1776, x2)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x1, 1784, x2)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x1, 1792, x2)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x1, 1800, x2)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x1, 1808, x2)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x1, 1816, x2)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x1, 1824, x2)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x1, 1832, x2)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x1, 1840, x2)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x1, 1848, x2)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x1, 1856, x2)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x1, 1864, x2)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x1, 1872, x2)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x1, 1880, x2)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x1, 1888, x2)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x1, 1896, x2)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x1, 1904, x2)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x1, 1912, x2)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x1, 1920, x2)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x1, 1928, x2)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x1, 1936, x2)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x1, 1944, x2)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x1, 1952, x2)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x1, 1960, x2)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x1, 1968, x2)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x1, 1976, x2)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x1, 1984, x2)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x1, 1992, x2)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x1, 2000, x2)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x1, 2008, x2)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x1, 2016, x2)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x1, 2024, x2)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x1, 2032, x2)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x1, 2040, x2)
+RVTEST_SIGBASE( x1,signature_x1_3)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x1, 0, x2)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x1, 8, x2)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x1, 16, x2)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x1, 24, x2)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x1, 32, x2)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x1, 40, x2)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x1, 48, x2)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x1, 56, x2)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x1, 64, x2)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x1, 72, x2)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x1, 80, x2)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x1, 88, x2)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x1, 96, x2)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x1, 104, x2)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x1, 112, x2)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x1, 120, x2)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x1, 128, x2)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x1, 136, x2)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x1, 144, x2)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x1, 152, x2)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x1, 160, x2)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x1, 168, x2)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x1, 176, x2)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x1, 184, x2)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x1, 192, x2)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x1, 200, x2)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x1, 208, x2)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x1, 216, x2)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x1, 224, x2)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x1, 232, x2)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x1, 240, x2)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x1, 248, x2)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x1, 256, x2)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x1, 264, x2)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x1, 272, x2)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x1, 280, x2)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x1, 288, x2)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x1, 296, x2)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x1, 304, x2)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x1, 312, x2)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x1, 320, x2)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x1, 328, x2)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x1, 336, x2)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x1, 344, x2)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x1, 352, x2)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x1, 360, x2)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x1, 368, x2)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x1, 376, x2)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x1, 384, x2)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x1, 392, x2)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x1, 400, x2)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x1, 408, x2)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x1, 416, x2)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x1, 424, x2)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x1, 432, x2)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x1, 440, x2)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x1, 448, x2)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x1, 456, x2)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x1, 464, x2)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x1, 472, x2)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x1, 480, x2)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x1, 488, x2)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x1, 496, x2)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x1, 504, x2)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x1, 512, x2)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x1, 520, x2)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x1, 528, x2)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x1, 536, x2)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x1, 544, x2)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x1, 552, x2)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x1, 560, x2)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x1, 568, x2)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x1, 576, x2)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x1, 584, x2)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x1, 592, x2)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x1, 600, x2)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x1, 608, x2)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x1, 616, x2)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x1, 624, x2)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x1, 632, x2)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x1, 640, x2)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x1, 648, x2)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x1, 656, x2)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x1, 664, x2)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x1, 672, x2)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x1, 680, x2)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x1, 688, x2)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x1, 696, x2)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x1, 704, x2)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x1, 712, x2)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x1, 720, x2)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x1, 728, x2)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x1, 736, x2)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x1, 744, x2)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x1, 752, x2)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x1, 760, x2)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x1, 768, x2)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x1, 776, x2)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x1, 784, x2)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x1, 792, x2)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x1, 800, x2)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x1, 808, x2)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x1, 816, x2)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x1, 824, x2)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x1, 832, x2)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x1, 840, x2)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x1, 848, x2)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x1, 856, x2)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x1, 864, x2)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x1, 872, x2)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x1, 880, x2)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x1, 888, x2)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x1, 896, x2)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x1, 904, x2)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x1, 912, x2)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x1, 920, x2)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x1, 928, x2)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x1, 936, x2)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x1, 944, x2)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x1, 952, x2)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x1, 960, x2)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x1, 968, x2)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x1, 976, x2)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x1, 984, x2)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x1, 992, x2)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x1, 1000, x2)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x1, 1008, x2)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x1, 1016, x2)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x1, 1024, x2)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x1, 1032, x2)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x1, 1040, x2)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x1, 1048, x2)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x1, 1056, x2)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x1, 1064, x2)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x1, 1072, x2)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x1, 1080, x2)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x1, 1088, x2)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x1, 1096, x2)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x1, 1104, x2)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x1, 1112, x2)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x1, 1120, x2)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x1, 1128, x2)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x1, 1136, x2)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x1, 1144, x2)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x1, 1152, x2)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x1, 1160, x2)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x1, 1168, x2)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x1, 1176, x2)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x1, 1184, x2)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x1, 1192, x2)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x1, 1200, x2)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x1, 1208, x2)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x1, 1216, x2)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x1, 1224, x2)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x1, 1232, x2)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x1, 1240, x2)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x1, 1248, x2)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x1, 1256, x2)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x1, 1264, x2)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x1, 1272, x2)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x1, 1280, x2)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x1, 1288, x2)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x1, 1296, x2)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x1, 1304, x2)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x1, 1312, x2)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x1, 1320, x2)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x1, 1328, x2)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x1, 1336, x2)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x1, 1344, x2)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x1, 1352, x2)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x1, 1360, x2)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x1, 1368, x2)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x1, 1376, x2)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x1, 1384, x2)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x1, 1392, x2)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x1, 1400, x2)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x1, 1408, x2)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x1, 1416, x2)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x1, 1424, x2)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x1, 1432, x2)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x1, 1440, x2)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x1, 1448, x2)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x1, 1456, x2)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x1, 1464, x2)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x1, 1472, x2)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x1, 1480, x2)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x1, 1488, x2)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x1, 1496, x2)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x1, 1504, x2)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x1, 1512, x2)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x1, 1520, x2)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x1, 1528, x2)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x1, 1536, x2)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x1, 1544, x2)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x1, 1552, x2)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x1, 1560, x2)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x1, 1568, x2)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x1, 1576, x2)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x1, 1584, x2)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x1, 1592, x2)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x1, 1600, x2)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x1, 1608, x2)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x1, 1616, x2)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x1, 1624, x2)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x1, 1632, x2)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x1, 1640, x2)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x1, 1648, x2)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x1, 1656, x2)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x1, 1664, x2)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x1, 1672, x2)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x1, 1680, x2)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x1, 1688, x2)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x1, 1696, x2)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x1, 1704, x2)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x1, 1712, x2)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x1, 1720, x2)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x1, 1728, x2)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x1, 1736, x2)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x1, 1744, x2)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x1, 1752, x2)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x1, 1760, x2)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x1, 1768, x2)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x1, 1776, x2)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x1, 1784, x2)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x1, 1792, x2)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x1, 1800, x2)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x1, 1808, x2)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x1, 1816, x2)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x1, 1824, x2)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x1, 1832, x2)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x1, 1840, x2)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x1, 1848, x2)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x1, 1856, x2)
+
+inst_522:
+// rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x1, 1864, x2)
+
+inst_523:
+// rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x1, 1872, x2)
+
+inst_524:
+// rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: rol ; op1:x10; op2:x11; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(rol, x12, x10, x11, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x1, 1880, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x1_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x20_0:
+    .fill 15*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_3:
+    .fill 236*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S
new file mode 100644
index 000000000..f34961f3b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rolw-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the rolw instruction of the RISC-V  extension for the rolw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rolw)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",rolw)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",rolw)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",rolw)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x31, rs2==x31, rd==x27, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rolw ; op1:x31; op2:x31; dest:x27; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(rolw, x27, x31, x31, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x6, 0, x2)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x25, rs2==x25, rd==x25, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rolw ; op1:x25; op2:x25; dest:x25; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(rolw, x25, x25, x25, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x6, 8, x2)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x17, rs2==x3, rd==x9, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: rolw ; op1:x17; op2:x3; dest:x9; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(rolw, x9, x17, x3, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x6, 16, x2)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x19, rs2==x16, rd==x19, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: rolw ; op1:x19; op2:x16; dest:x19; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(rolw, x19, x19, x16, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x6, 24, x2)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x30, rs2==x18, rd==x18, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: rolw ; op1:x30; op2:x18; dest:x18; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(rolw, x18, x30, x18, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x6, 32, x2)
+
+inst_5:
+// rs1==x14, rs2==x7, rd==x16, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: rolw ; op1:x14; op2:x7; dest:x16; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(rolw, x16, x14, x7, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x6, 40, x2)
+
+inst_6:
+// rs1==x29, rs2==x21, rd==x4, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: rolw ; op1:x29; op2:x21; dest:x4; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(rolw, x4, x29, x21, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x6, 48, x2)
+
+inst_7:
+// rs1==x5, rs2==x26, rd==x14, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: rolw ; op1:x5; op2:x26; dest:x14; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(rolw, x14, x5, x26, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x6, 56, x2)
+
+inst_8:
+// rs1==x8, rs2==x20, rd==x5, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: rolw ; op1:x8; op2:x20; dest:x5; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(rolw, x5, x8, x20, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x6, 64, x2)
+
+inst_9:
+// rs1==x12, rs2==x11, rd==x30, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: rolw ; op1:x12; op2:x11; dest:x30; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(rolw, x30, x12, x11, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x6, 72, x2)
+
+inst_10:
+// rs1==x22, rs2==x28, rd==x21, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: rolw ; op1:x22; op2:x28; dest:x21; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(rolw, x21, x22, x28, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x6, 80, x2)
+
+inst_11:
+// rs1==x0, rs2==x9, rd==x3, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: rolw ; op1:x0; op2:x9; dest:x3; op1val:0x0;  op2val:0x1940000000000000
+TEST_RR_OP(rolw, x3, x0, x9, 0x0000000000000000, 0x0, 0x1940000000000000, x6, 88, x2)
+
+inst_12:
+// rs1==x3, rs2==x30, rd==x13, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: rolw ; op1:x3; op2:x30; dest:x13; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(rolw, x13, x3, x30, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x6, 96, x2)
+
+inst_13:
+// rs1==x15, rs2==x29, rd==x17, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: rolw ; op1:x15; op2:x29; dest:x17; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(rolw, x17, x15, x29, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x6, 104, x2)
+
+inst_14:
+// rs1==x7, rs2==x19, rd==x10, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: rolw ; op1:x7; op2:x19; dest:x10; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(rolw, x10, x7, x19, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x6, 112, x2)
+
+inst_15:
+// rs1==x27, rs2==x10, rd==x7, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: rolw ; op1:x27; op2:x10; dest:x7; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(rolw, x7, x27, x10, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x6, 120, x2)
+
+inst_16:
+// rs1==x9, rs2==x1, rd==x12, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: rolw ; op1:x9; op2:x1; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(rolw, x12, x9, x1, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x6, 128, x2)
+
+inst_17:
+// rs1==x21, rs2==x12, rd==x2, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: rolw ; op1:x21; op2:x12; dest:x2; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(rolw, x2, x21, x12, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x6, 136, x7)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_18:
+// rs1==x11, rs2==x0, rd==x1, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: rolw ; op1:x11; op2:x0; dest:x1; op1val:0x718e177de812dd49;  op2val:0x0
+TEST_RR_OP(rolw, x1, x11, x0, 0x0000000000000000, 0x718e177de812dd49, 0x0, x3, 0, x7)
+
+inst_19:
+// rs1==x26, rs2==x2, rd==x15, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: rolw ; op1:x26; op2:x2; dest:x15; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(rolw, x15, x26, x2, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x3, 8, x7)
+
+inst_20:
+// rs1==x13, rs2==x6, rd==x22, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: rolw ; op1:x13; op2:x6; dest:x22; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(rolw, x22, x13, x6, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x3, 16, x7)
+
+inst_21:
+// rs1==x28, rs2==x14, rd==x29, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: rolw ; op1:x28; op2:x14; dest:x29; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(rolw, x29, x28, x14, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x3, 24, x7)
+
+inst_22:
+// rs1==x2, rs2==x24, rd==x20, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: rolw ; op1:x2; op2:x24; dest:x20; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(rolw, x20, x2, x24, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x3, 32, x7)
+
+inst_23:
+// rs1==x20, rs2==x4, rd==x0, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: rolw ; op1:x20; op2:x4; dest:x0; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(rolw, x0, x20, x4, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x3, 40, x7)
+
+inst_24:
+// rs1==x4, rs2==x5, rd==x23, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: rolw ; op1:x4; op2:x5; dest:x23; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(rolw, x23, x4, x5, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x3, 48, x7)
+
+inst_25:
+// rs1==x23, rs2==x13, rd==x31, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: rolw ; op1:x23; op2:x13; dest:x31; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(rolw, x31, x23, x13, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x3, 56, x7)
+
+inst_26:
+// rs1==x24, rs2==x8, rd==x11, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: rolw ; op1:x24; op2:x8; dest:x11; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(rolw, x11, x24, x8, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x3, 64, x7)
+
+inst_27:
+// rs1==x18, rs2==x17, rd==x24, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: rolw ; op1:x18; op2:x17; dest:x24; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(rolw, x24, x18, x17, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x3, 72, x7)
+
+inst_28:
+// rs1==x10, rs2==x15, rd==x26, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: rolw ; op1:x10; op2:x15; dest:x26; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(rolw, x26, x10, x15, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x3, 80, x7)
+
+inst_29:
+// rs1==x6, rs2==x22, rd==x8, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: rolw ; op1:x6; op2:x22; dest:x8; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(rolw, x8, x6, x22, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x3, 88, x7)
+
+inst_30:
+// rs1==x16, rs2==x27, rd==x28, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: rolw ; op1:x16; op2:x27; dest:x28; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(rolw, x28, x16, x27, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x3, 96, x7)
+
+inst_31:
+// rs1==x1, rs2==x23, rd==x6, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: rolw ; op1:x1; op2:x23; dest:x6; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(rolw, x6, x1, x23, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x3, 104, x7)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x3, 112, x7)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x3, 120, x7)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x3, 128, x7)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x3, 136, x7)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x3, 144, x7)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x3, 152, x7)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x3, 160, x7)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x3, 168, x7)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x3, 176, x7)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x3, 184, x7)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x3, 192, x7)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x3, 200, x7)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x3, 208, x7)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x3, 216, x7)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x3, 224, x7)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x3, 232, x7)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x3, 240, x7)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x3, 248, x7)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x3, 256, x7)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x3, 264, x7)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x3, 272, x7)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x3, 280, x7)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x3, 288, x7)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x3, 296, x7)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x3, 304, x7)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x3, 312, x7)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x3, 320, x7)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x3, 328, x7)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x3, 336, x7)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x3, 344, x7)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x3, 352, x7)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x3, 360, x7)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x3, 368, x7)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x3, 376, x7)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x3, 384, x7)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x3, 392, x7)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x3, 400, x7)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x3, 408, x7)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x3, 416, x7)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x3, 424, x7)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x3, 432, x7)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x3, 440, x7)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x3, 448, x7)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x3, 456, x7)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x3, 464, x7)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x3, 472, x7)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x3, 480, x7)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x3, 488, x7)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x3, 496, x7)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x3, 504, x7)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x3, 512, x7)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x3, 520, x7)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x3, 528, x7)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x3, 536, x7)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x3, 544, x7)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x3, 552, x7)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x3, 560, x7)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x3, 568, x7)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x3, 576, x7)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x3, 584, x7)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x3, 592, x7)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x3, 600, x7)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x3, 608, x7)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x3, 616, x7)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x3, 624, x7)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x3, 632, x7)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x3, 640, x7)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x3, 648, x7)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x3, 656, x7)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x3, 664, x7)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x3, 672, x7)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x3, 680, x7)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x3, 688, x7)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x3, 696, x7)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x3, 704, x7)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x3, 712, x7)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x3, 720, x7)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x3, 728, x7)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x3, 736, x7)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x3, 744, x7)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x3, 752, x7)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x3, 760, x7)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x3, 768, x7)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x3, 776, x7)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x3, 784, x7)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x3, 792, x7)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x3, 800, x7)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x3, 808, x7)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x3, 816, x7)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x3, 824, x7)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x3, 832, x7)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x3, 840, x7)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x3, 848, x7)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x3, 856, x7)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x3, 864, x7)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x3, 872, x7)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x3, 880, x7)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x3, 888, x7)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x3, 896, x7)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x3, 904, x7)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x3, 912, x7)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x3, 920, x7)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x3, 928, x7)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x3, 936, x7)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x3, 944, x7)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x3, 952, x7)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x3, 960, x7)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x3, 968, x7)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x3, 976, x7)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x3, 984, x7)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x3, 992, x7)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x3, 1000, x7)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x3, 1008, x7)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x3, 1016, x7)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x3, 1024, x7)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x3, 1032, x7)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x3, 1040, x7)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x3, 1048, x7)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x3, 1056, x7)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x3, 1064, x7)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x3, 1072, x7)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x3, 1080, x7)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x3, 1088, x7)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x3, 1096, x7)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x3, 1104, x7)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x3, 1112, x7)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x3, 1120, x7)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x3, 1128, x7)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x3, 1136, x7)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x3, 1144, x7)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x3, 1152, x7)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x3, 1160, x7)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x3, 1168, x7)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x3, 1176, x7)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x3, 1184, x7)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x3, 1192, x7)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x3, 1200, x7)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x3, 1208, x7)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x3, 1216, x7)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x3, 1224, x7)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x3, 1232, x7)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x3, 1240, x7)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x3, 1248, x7)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x3, 1256, x7)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x3, 1264, x7)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x3, 1272, x7)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x3, 1280, x7)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x3, 1288, x7)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x3, 1296, x7)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x3, 1304, x7)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x3, 1312, x7)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x3, 1320, x7)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x3, 1328, x7)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x3, 1336, x7)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x3, 1344, x7)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x3, 1352, x7)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x3, 1360, x7)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x3, 1368, x7)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x3, 1376, x7)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x3, 1384, x7)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x3, 1392, x7)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x3, 1400, x7)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x3, 1408, x7)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x3, 1416, x7)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x3, 1424, x7)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x3, 1432, x7)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x3, 1440, x7)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x3, 1448, x7)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x3, 1456, x7)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x3, 1464, x7)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x3, 1472, x7)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x3, 1480, x7)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x3, 1488, x7)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x3, 1496, x7)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x3, 1504, x7)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x3, 1512, x7)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x3, 1520, x7)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x3, 1528, x7)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x3, 1536, x7)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x3, 1544, x7)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x3, 1552, x7)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x3, 1560, x7)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x3, 1568, x7)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x3, 1576, x7)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x3, 1584, x7)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x3, 1592, x7)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x3, 1600, x7)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x3, 1608, x7)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x3, 1616, x7)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x3, 1624, x7)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x3, 1632, x7)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x3, 1640, x7)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x3, 1648, x7)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x3, 1656, x7)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x3, 1664, x7)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x3, 1672, x7)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x3, 1680, x7)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x3, 1688, x7)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x3, 1696, x7)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x3, 1704, x7)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x3, 1712, x7)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x3, 1720, x7)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x3, 1728, x7)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x3, 1736, x7)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x3, 1744, x7)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x3, 1752, x7)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x3, 1760, x7)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x3, 1768, x7)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x3, 1776, x7)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x3, 1784, x7)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x3, 1792, x7)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x3, 1800, x7)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x3, 1808, x7)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x3, 1816, x7)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x3, 1824, x7)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x3, 1832, x7)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x3, 1840, x7)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x3, 1848, x7)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x3, 1856, x7)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x3, 1864, x7)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x3, 1872, x7)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x3, 1880, x7)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x3, 1888, x7)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x3, 1896, x7)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x3, 1904, x7)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x3, 1912, x7)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x3, 1920, x7)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x3, 1928, x7)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x3, 1936, x7)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x3, 1944, x7)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x3, 1952, x7)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x3, 1960, x7)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x3, 1968, x7)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x3, 1976, x7)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x3, 1984, x7)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x3, 1992, x7)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x3, 2000, x7)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x3, 2008, x7)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x3, 2016, x7)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x3, 2024, x7)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x3, 2032, x7)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x3, 2040, x7)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x3, 0, x7)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x3, 8, x7)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x3, 16, x7)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x3, 24, x7)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x3, 32, x7)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x3, 40, x7)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x3, 48, x7)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x3, 56, x7)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x3, 64, x7)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x3, 72, x7)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x3, 80, x7)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x3, 88, x7)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x3, 96, x7)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x3, 104, x7)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x3, 112, x7)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x3, 120, x7)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x3, 128, x7)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x3, 136, x7)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x3, 144, x7)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x3, 152, x7)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x3, 160, x7)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x3, 168, x7)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x3, 176, x7)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x3, 184, x7)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x3, 192, x7)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x3, 200, x7)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x3, 208, x7)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x3, 216, x7)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x3, 224, x7)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x3, 232, x7)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x3, 240, x7)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x3, 248, x7)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x3, 256, x7)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x3, 264, x7)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x3, 272, x7)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x3, 280, x7)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x3, 288, x7)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x3, 296, x7)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x3, 304, x7)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x3, 312, x7)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x3, 320, x7)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x3, 328, x7)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x3, 336, x7)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x3, 344, x7)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x3, 352, x7)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x3, 360, x7)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x3, 368, x7)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x3, 376, x7)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x3, 384, x7)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x3, 392, x7)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x3, 400, x7)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x3, 408, x7)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x3, 416, x7)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x3, 424, x7)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x3, 432, x7)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x3, 440, x7)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x3, 448, x7)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x3, 456, x7)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x3, 464, x7)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x3, 472, x7)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x3, 480, x7)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x3, 488, x7)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x3, 496, x7)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x3, 504, x7)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x3, 512, x7)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x3, 520, x7)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x3, 528, x7)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x3, 536, x7)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x3, 544, x7)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x3, 552, x7)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x3, 560, x7)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x3, 568, x7)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x3, 576, x7)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x3, 584, x7)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x3, 592, x7)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x3, 600, x7)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x3, 608, x7)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x3, 616, x7)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x3, 624, x7)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x3, 632, x7)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x3, 640, x7)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x3, 648, x7)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x3, 656, x7)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x3, 664, x7)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x3, 672, x7)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x3, 680, x7)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x3, 688, x7)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x3, 696, x7)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x3, 704, x7)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x3, 712, x7)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x3, 720, x7)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x3, 728, x7)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x3, 736, x7)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x3, 744, x7)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x3, 752, x7)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x3, 760, x7)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x3, 768, x7)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x3, 776, x7)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x3, 784, x7)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x3, 792, x7)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x3, 800, x7)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x3, 808, x7)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x3, 816, x7)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x3, 824, x7)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x3, 832, x7)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x3, 840, x7)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x3, 848, x7)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x3, 856, x7)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x3, 864, x7)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x3, 872, x7)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x3, 880, x7)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x3, 888, x7)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x3, 896, x7)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x3, 904, x7)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x3, 912, x7)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x3, 920, x7)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x3, 928, x7)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x3, 936, x7)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x3, 944, x7)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x3, 952, x7)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x3, 960, x7)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x3, 968, x7)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x3, 976, x7)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x3, 984, x7)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x3, 992, x7)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x3, 1000, x7)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x3, 1008, x7)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x3, 1016, x7)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x3, 1024, x7)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x3, 1032, x7)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x3, 1040, x7)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x3, 1048, x7)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x3, 1056, x7)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x3, 1064, x7)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x3, 1072, x7)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x3, 1080, x7)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x3, 1088, x7)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x3, 1096, x7)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x3, 1104, x7)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x3, 1112, x7)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x3, 1120, x7)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x3, 1128, x7)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x3, 1136, x7)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x3, 1144, x7)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x3, 1152, x7)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x3, 1160, x7)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x3, 1168, x7)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x3, 1176, x7)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x3, 1184, x7)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x3, 1192, x7)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x3, 1200, x7)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x3, 1208, x7)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x3, 1216, x7)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x3, 1224, x7)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x3, 1232, x7)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x3, 1240, x7)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x3, 1248, x7)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x3, 1256, x7)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x3, 1264, x7)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x3, 1272, x7)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x3, 1280, x7)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x3, 1288, x7)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x3, 1296, x7)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x3, 1304, x7)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x3, 1312, x7)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x3, 1320, x7)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x3, 1328, x7)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x3, 1336, x7)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x3, 1344, x7)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x3, 1352, x7)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x3, 1360, x7)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x3, 1368, x7)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x3, 1376, x7)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x3, 1384, x7)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x3, 1392, x7)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x3, 1400, x7)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x3, 1408, x7)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x3, 1416, x7)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x3, 1424, x7)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x3, 1432, x7)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x3, 1440, x7)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x3, 1448, x7)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x3, 1456, x7)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x3, 1464, x7)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x3, 1472, x7)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x3, 1480, x7)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x3, 1488, x7)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x3, 1496, x7)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x3, 1504, x7)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x3, 1512, x7)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x3, 1520, x7)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x3, 1528, x7)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x3, 1536, x7)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x3, 1544, x7)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x3, 1552, x7)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x3, 1560, x7)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x3, 1568, x7)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x3, 1576, x7)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x3, 1584, x7)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x3, 1592, x7)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x3, 1600, x7)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x3, 1608, x7)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x3, 1616, x7)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x3, 1624, x7)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x3, 1632, x7)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x3, 1640, x7)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x3, 1648, x7)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x3, 1656, x7)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x3, 1664, x7)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x3, 1672, x7)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x3, 1680, x7)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x3, 1688, x7)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x3, 1696, x7)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x3, 1704, x7)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x3, 1712, x7)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x3, 1720, x7)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x3, 1728, x7)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x3, 1736, x7)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x3, 1744, x7)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x3, 1752, x7)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x3, 1760, x7)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x3, 1768, x7)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x3, 1776, x7)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x3, 1784, x7)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x3, 1792, x7)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x3, 1800, x7)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x3, 1808, x7)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x3, 1816, x7)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x3, 1824, x7)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x3, 1832, x7)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x3, 1840, x7)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x3, 1848, x7)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x3, 1856, x7)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x3, 1864, x7)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x3, 1872, x7)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x3, 1880, x7)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x3, 1888, x7)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x3, 1896, x7)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x3, 1904, x7)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x3, 1912, x7)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x3, 1920, x7)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x3, 1928, x7)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x3, 1936, x7)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x3, 1944, x7)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x3, 1952, x7)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x3, 1960, x7)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x3, 1968, x7)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x3, 1976, x7)
+
+inst_522:
+// rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x3, 1984, x7)
+
+inst_523:
+// rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x3, 1992, x7)
+
+inst_524:
+// rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: rolw ; op1:x10; op2:x11; dest:x12; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(rolw, x12, x10, x11, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x3, 2000, x7)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 251*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S
new file mode 100644
index 000000000..e54d69fae
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/ror-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the ror instruction of the RISC-V  extension for the ror covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",ror)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",ror)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",ror)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",ror)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x28, rs2==x28, rd==x19, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: ror ; op1:x28; op2:x28; dest:x19; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(ror, x19, x28, x28, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x5, 0, x10)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x6, rs2==x6, rd==x6, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: ror ; op1:x6; op2:x6; dest:x6; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(ror, x6, x6, x6, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x5, 8, x10)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x0, rs2==x15, rd==x22, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: ror ; op1:x0; op2:x15; dest:x22; op1val:0x0;  op2val:0x8000000000000000
+TEST_RR_OP(ror, x22, x0, x15, 0x0000000000000000, 0x0, 0x8000000000000000, x5, 16, x10)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x18, rs2==x29, rd==x18, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: ror ; op1:x18; op2:x29; dest:x18; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(ror, x18, x18, x29, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x5, 24, x10)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x16, rs2==x21, rd==x21, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: ror ; op1:x16; op2:x21; dest:x21; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(ror, x21, x16, x21, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x5, 32, x10)
+
+inst_5:
+// rs1==x13, rs2==x17, rd==x9, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: ror ; op1:x13; op2:x17; dest:x9; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(ror, x9, x13, x17, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x5, 40, x10)
+
+inst_6:
+// rs1==x29, rs2==x24, rd==x14, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: ror ; op1:x29; op2:x24; dest:x14; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(ror, x14, x29, x24, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x5, 48, x10)
+
+inst_7:
+// rs1==x30, rs2==x7, rd==x15, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: ror ; op1:x30; op2:x7; dest:x15; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(ror, x15, x30, x7, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x5, 56, x10)
+
+inst_8:
+// rs1==x27, rs2==x8, rd==x16, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: ror ; op1:x27; op2:x8; dest:x16; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(ror, x16, x27, x8, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x5, 64, x10)
+
+inst_9:
+// rs1==x22, rs2==x19, rd==x31, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: ror ; op1:x22; op2:x19; dest:x31; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(ror, x31, x22, x19, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x5, 72, x10)
+
+inst_10:
+// rs1==x11, rs2==x23, rd==x24, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: ror ; op1:x11; op2:x23; dest:x24; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(ror, x24, x11, x23, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x5, 80, x10)
+
+inst_11:
+// rs1==x9, rs2==x30, rd==x26, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: ror ; op1:x9; op2:x30; dest:x26; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(ror, x26, x9, x30, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x5, 88, x10)
+
+inst_12:
+// rs1==x31, rs2==x27, rd==x25, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: ror ; op1:x31; op2:x27; dest:x25; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(ror, x25, x31, x27, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x5, 96, x10)
+
+inst_13:
+// rs1==x15, rs2==x25, rd==x30, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: ror ; op1:x15; op2:x25; dest:x30; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(ror, x30, x15, x25, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x5, 104, x10)
+
+inst_14:
+// rs1==x21, rs2==x16, rd==x7, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: ror ; op1:x21; op2:x16; dest:x7; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(ror, x7, x21, x16, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x5, 112, x10)
+
+inst_15:
+// rs1==x2, rs2==x11, rd==x8, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: ror ; op1:x2; op2:x11; dest:x8; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(ror, x8, x2, x11, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x5, 120, x10)
+
+inst_16:
+// rs1==x12, rs2==x13, rd==x2, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: ror ; op1:x12; op2:x13; dest:x2; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(ror, x2, x12, x13, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x5, 128, x10)
+
+inst_17:
+// rs1==x3, rs2==x31, rd==x28, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: ror ; op1:x3; op2:x31; dest:x28; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(ror, x28, x3, x31, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x5, 136, x10)
+
+inst_18:
+// rs1==x20, rs2==x1, rd==x4, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: ror ; op1:x20; op2:x1; dest:x4; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(ror, x4, x20, x1, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x5, 144, x10)
+RVTEST_SIGBASE( x6,signature_x6_0)
+
+inst_19:
+// rs1==x23, rs2==x0, rd==x3, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: ror ; op1:x23; op2:x0; dest:x3; op1val:0x42bea7753d32d01e;  op2val:0x0
+TEST_RR_OP(ror, x3, x23, x0, 0x0000000000000000, 0x42bea7753d32d01e, 0x0, x6, 0, x15)
+
+inst_20:
+// rs1==x26, rs2==x2, rd==x12, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: ror ; op1:x26; op2:x2; dest:x12; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(ror, x12, x26, x2, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x6, 8, x15)
+
+inst_21:
+// rs1==x24, rs2==x4, rd==x0, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: ror ; op1:x24; op2:x4; dest:x0; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(ror, x0, x24, x4, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x6, 16, x15)
+
+inst_22:
+// rs1==x19, rs2==x20, rd==x5, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: ror ; op1:x19; op2:x20; dest:x5; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(ror, x5, x19, x20, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x6, 24, x15)
+
+inst_23:
+// rs1==x1, rs2==x3, rd==x23, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: ror ; op1:x1; op2:x3; dest:x23; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(ror, x23, x1, x3, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x6, 32, x15)
+
+inst_24:
+// rs1==x7, rs2==x5, rd==x20, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: ror ; op1:x7; op2:x5; dest:x20; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(ror, x20, x7, x5, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x6, 40, x15)
+
+inst_25:
+// rs1==x5, rs2==x26, rd==x11, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: ror ; op1:x5; op2:x26; dest:x11; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(ror, x11, x5, x26, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x6, 48, x15)
+
+inst_26:
+// rs1==x14, rs2==x18, rd==x1, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: ror ; op1:x14; op2:x18; dest:x1; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(ror, x1, x14, x18, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x6, 56, x15)
+
+inst_27:
+// rs1==x17, rs2==x14, rd==x29, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: ror ; op1:x17; op2:x14; dest:x29; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(ror, x29, x17, x14, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x6, 64, x15)
+
+inst_28:
+// rs1==x25, rs2==x22, rd==x27, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: ror ; op1:x25; op2:x22; dest:x27; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(ror, x27, x25, x22, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x6, 72, x15)
+
+inst_29:
+// rs1==x8, rs2==x10, rd==x17, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: ror ; op1:x8; op2:x10; dest:x17; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(ror, x17, x8, x10, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x6, 80, x15)
+
+inst_30:
+// rs1==x4, rs2==x12, rd==x13, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: ror ; op1:x4; op2:x12; dest:x13; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(ror, x13, x4, x12, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x6, 88, x15)
+
+inst_31:
+// rs1==x10, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: ror ; op1:x10; op2:x16; dest:x5; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(ror, x5, x10, x16, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x6, 96, x15)
+
+inst_32:
+// rs2==x9, rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: ror ; op1:x31; op2:x9; dest:x20; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(ror, x20, x31, x9, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x6, 104, x15)
+
+inst_33:
+// rd==x10, rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: ror ; op1:x20; op2:x19; dest:x10; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(ror, x10, x20, x19, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x6, 112, x15)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x6, 120, x15)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x6, 128, x15)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x6, 136, x15)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x6, 144, x15)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x6, 152, x15)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x6, 160, x15)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x6, 168, x15)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x6, 176, x15)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x6, 184, x15)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x6, 192, x15)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x6, 200, x15)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x6, 208, x15)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x6, 216, x15)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x6, 224, x15)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x6, 232, x15)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x6, 240, x15)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x6, 248, x15)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x6, 256, x15)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x6, 264, x15)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x6, 272, x15)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x6, 280, x15)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x6, 288, x15)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x6, 296, x15)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x6, 304, x15)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x6, 312, x15)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x6, 320, x15)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x6, 328, x15)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x6, 336, x15)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x6, 344, x15)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x6, 352, x15)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x6, 360, x15)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x6, 368, x15)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x6, 376, x15)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x6, 384, x15)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x6, 392, x15)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x6, 400, x15)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x6, 408, x15)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x6, 416, x15)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x6, 424, x15)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x6, 432, x15)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x6, 440, x15)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x6, 448, x15)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x6, 456, x15)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x6, 464, x15)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x6, 472, x15)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x6, 480, x15)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x6, 488, x15)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x6, 496, x15)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x6, 504, x15)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x6, 512, x15)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x6, 520, x15)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x6, 528, x15)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x6, 536, x15)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x6, 544, x15)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x6, 552, x15)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x6, 560, x15)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x6, 568, x15)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x6, 576, x15)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x6, 584, x15)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x6, 592, x15)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x6, 600, x15)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x6, 608, x15)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x6, 616, x15)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x6, 624, x15)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x6, 632, x15)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x6, 640, x15)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x6, 648, x15)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x6, 656, x15)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x6, 664, x15)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x6, 672, x15)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x6, 680, x15)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x6, 688, x15)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x6, 696, x15)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x6, 704, x15)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x6, 712, x15)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x6, 720, x15)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x6, 728, x15)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x6, 736, x15)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x6, 744, x15)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x6, 752, x15)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x6, 760, x15)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x6, 768, x15)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x6, 776, x15)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x6, 784, x15)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x6, 792, x15)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x6, 800, x15)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x6, 808, x15)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x6, 816, x15)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x6, 824, x15)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x6, 832, x15)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x6, 840, x15)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x6, 848, x15)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x6, 856, x15)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x6, 864, x15)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x6, 872, x15)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x6, 880, x15)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x6, 888, x15)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x6, 896, x15)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x6, 904, x15)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x6, 912, x15)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x6, 920, x15)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x6, 928, x15)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x6, 936, x15)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x6, 944, x15)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x6, 952, x15)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x6, 960, x15)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x6, 968, x15)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x6, 976, x15)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x6, 984, x15)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x6, 992, x15)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x6, 1000, x15)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x6, 1008, x15)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x6, 1016, x15)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x6, 1024, x15)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x6, 1032, x15)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x6, 1040, x15)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x6, 1048, x15)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x6, 1056, x15)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x6, 1064, x15)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x6, 1072, x15)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x6, 1080, x15)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x6, 1088, x15)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x6, 1096, x15)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x6, 1104, x15)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x6, 1112, x15)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x6, 1120, x15)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x6, 1128, x15)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x6, 1136, x15)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x6, 1144, x15)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x6, 1152, x15)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x6, 1160, x15)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x6, 1168, x15)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x6, 1176, x15)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x6, 1184, x15)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x6, 1192, x15)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x6, 1200, x15)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x6, 1208, x15)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x6, 1216, x15)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x6, 1224, x15)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x6, 1232, x15)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x6, 1240, x15)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x6, 1248, x15)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x6, 1256, x15)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x6, 1264, x15)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x6, 1272, x15)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x6, 1280, x15)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x6, 1288, x15)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x6, 1296, x15)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x6, 1304, x15)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x6, 1312, x15)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x6, 1320, x15)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x6, 1328, x15)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x6, 1336, x15)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x6, 1344, x15)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x6, 1352, x15)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x6, 1360, x15)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x6, 1368, x15)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x6, 1376, x15)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x6, 1384, x15)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x6, 1392, x15)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x6, 1400, x15)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x6, 1408, x15)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x6, 1416, x15)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x6, 1424, x15)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x6, 1432, x15)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x6, 1440, x15)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x6, 1448, x15)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x6, 1456, x15)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x6, 1464, x15)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x6, 1472, x15)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x6, 1480, x15)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x6, 1488, x15)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x6, 1496, x15)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x6, 1504, x15)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x6, 1512, x15)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x6, 1520, x15)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x6, 1528, x15)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x6, 1536, x15)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x6, 1544, x15)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x6, 1552, x15)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x6, 1560, x15)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x6, 1568, x15)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x6, 1576, x15)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x6, 1584, x15)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x6, 1592, x15)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x6, 1600, x15)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x6, 1608, x15)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x6, 1616, x15)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x6, 1624, x15)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x6, 1632, x15)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x6, 1640, x15)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x6, 1648, x15)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x6, 1656, x15)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x6, 1664, x15)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x6, 1672, x15)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x6, 1680, x15)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x6, 1688, x15)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x6, 1696, x15)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x6, 1704, x15)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x6, 1712, x15)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x6, 1720, x15)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x6, 1728, x15)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x6, 1736, x15)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x6, 1744, x15)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x6, 1752, x15)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x6, 1760, x15)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x6, 1768, x15)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x6, 1776, x15)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x6, 1784, x15)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x6, 1792, x15)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x6, 1800, x15)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x6, 1808, x15)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x6, 1816, x15)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x6, 1824, x15)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x6, 1832, x15)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x6, 1840, x15)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x6, 1848, x15)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x6, 1856, x15)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x6, 1864, x15)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x6, 1872, x15)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x6, 1880, x15)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x6, 1888, x15)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x6, 1896, x15)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x6, 1904, x15)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x6, 1912, x15)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x6, 1920, x15)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x6, 1928, x15)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x6, 1936, x15)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x6, 1944, x15)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x6, 1952, x15)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x6, 1960, x15)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x6, 1968, x15)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x6, 1976, x15)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x6, 1984, x15)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x6, 1992, x15)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x6, 2000, x15)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x6, 2008, x15)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x6, 2016, x15)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x6, 2024, x15)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x6, 2032, x15)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x6, 2040, x15)
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x6, 0, x15)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x6, 8, x15)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x6, 16, x15)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x6, 24, x15)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x6, 32, x15)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x6, 40, x15)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x6, 48, x15)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x6, 56, x15)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x6, 64, x15)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x6, 72, x15)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x6, 80, x15)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x6, 88, x15)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x6, 96, x15)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x6, 104, x15)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x6, 112, x15)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x6, 120, x15)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x6, 128, x15)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x6, 136, x15)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x6, 144, x15)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x6, 152, x15)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x6, 160, x15)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x6, 168, x15)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x6, 176, x15)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x6, 184, x15)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x6, 192, x15)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x6, 200, x15)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x6, 208, x15)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x6, 216, x15)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x6, 224, x15)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x6, 232, x15)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x6, 240, x15)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x6, 248, x15)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x6, 256, x15)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x6, 264, x15)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x6, 272, x15)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x6, 280, x15)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x6, 288, x15)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x6, 296, x15)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x6, 304, x15)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x6, 312, x15)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x6, 320, x15)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x6, 328, x15)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x6, 336, x15)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x6, 344, x15)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x6, 352, x15)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x6, 360, x15)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x6, 368, x15)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x6, 376, x15)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x6, 384, x15)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x6, 392, x15)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x6, 400, x15)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x6, 408, x15)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x6, 416, x15)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x6, 424, x15)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x6, 432, x15)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x6, 440, x15)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x6, 448, x15)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x6, 456, x15)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x6, 464, x15)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x6, 472, x15)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x6, 480, x15)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x6, 488, x15)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x6, 496, x15)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x6, 504, x15)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x6, 512, x15)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x6, 520, x15)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x6, 528, x15)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x6, 536, x15)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x6, 544, x15)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x6, 552, x15)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x6, 560, x15)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x6, 568, x15)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x6, 576, x15)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x6, 584, x15)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x6, 592, x15)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x6, 600, x15)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x6, 608, x15)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x6, 616, x15)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x6, 624, x15)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x6, 632, x15)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x6, 640, x15)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x6, 648, x15)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x6, 656, x15)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x6, 664, x15)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x6, 672, x15)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x6, 680, x15)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x6, 688, x15)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x6, 696, x15)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x6, 704, x15)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x6, 712, x15)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x6, 720, x15)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x6, 728, x15)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x6, 736, x15)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x6, 744, x15)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x6, 752, x15)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x6, 760, x15)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x6, 768, x15)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x6, 776, x15)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x6, 784, x15)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x6, 792, x15)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x6, 800, x15)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x6, 808, x15)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x6, 816, x15)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x6, 824, x15)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x6, 832, x15)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x6, 840, x15)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x6, 848, x15)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x6, 856, x15)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x6, 864, x15)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x6, 872, x15)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x6, 880, x15)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x6, 888, x15)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x6, 896, x15)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x6, 904, x15)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x6, 912, x15)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x6, 920, x15)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x6, 928, x15)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x6, 936, x15)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x6, 944, x15)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x6, 952, x15)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x6, 960, x15)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x6, 968, x15)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x6, 976, x15)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x6, 984, x15)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x6, 992, x15)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x6, 1000, x15)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x6, 1008, x15)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x6, 1016, x15)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x6, 1024, x15)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x6, 1032, x15)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x6, 1040, x15)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x6, 1048, x15)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x6, 1056, x15)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x6, 1064, x15)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x6, 1072, x15)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x6, 1080, x15)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x6, 1088, x15)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x6, 1096, x15)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x6, 1104, x15)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x6, 1112, x15)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x6, 1120, x15)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x6, 1128, x15)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x6, 1136, x15)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x6, 1144, x15)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x6, 1152, x15)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x6, 1160, x15)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x6, 1168, x15)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x6, 1176, x15)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x6, 1184, x15)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x6, 1192, x15)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x6, 1200, x15)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x6, 1208, x15)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x6, 1216, x15)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x6, 1224, x15)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x6, 1232, x15)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x6, 1240, x15)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x6, 1248, x15)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x6, 1256, x15)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x6, 1264, x15)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x6, 1272, x15)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x6, 1280, x15)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x6, 1288, x15)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x6, 1296, x15)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x6, 1304, x15)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x6, 1312, x15)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x6, 1320, x15)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x6, 1328, x15)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x6, 1336, x15)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x6, 1344, x15)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x6, 1352, x15)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x6, 1360, x15)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x6, 1368, x15)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x6, 1376, x15)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x6, 1384, x15)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x6, 1392, x15)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x6, 1400, x15)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x6, 1408, x15)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x6, 1416, x15)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x6, 1424, x15)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x6, 1432, x15)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x6, 1440, x15)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x6, 1448, x15)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x6, 1456, x15)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x6, 1464, x15)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x6, 1472, x15)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x6, 1480, x15)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x6, 1488, x15)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x6, 1496, x15)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x6, 1504, x15)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x6, 1512, x15)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x6, 1520, x15)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x6, 1528, x15)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x6, 1536, x15)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x6, 1544, x15)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x6, 1552, x15)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x6, 1560, x15)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x6, 1568, x15)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x6, 1576, x15)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x6, 1584, x15)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x6, 1592, x15)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x6, 1600, x15)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x6, 1608, x15)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x6, 1616, x15)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x6, 1624, x15)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x6, 1632, x15)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x6, 1640, x15)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x6, 1648, x15)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x6, 1656, x15)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x6, 1664, x15)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x6, 1672, x15)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x6, 1680, x15)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x6, 1688, x15)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x6, 1696, x15)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x6, 1704, x15)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x6, 1712, x15)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x6, 1720, x15)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x6, 1728, x15)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x6, 1736, x15)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x6, 1744, x15)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x6, 1752, x15)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x6, 1760, x15)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x6, 1768, x15)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x6, 1776, x15)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x6, 1784, x15)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x6, 1792, x15)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x6, 1800, x15)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x6, 1808, x15)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x6, 1816, x15)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x6, 1824, x15)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x6, 1832, x15)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x6, 1840, x15)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x6, 1848, x15)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x6, 1856, x15)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x6, 1864, x15)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x6, 1872, x15)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x6, 1880, x15)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x6, 1888, x15)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x6, 1896, x15)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x6, 1904, x15)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x6, 1912, x15)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x6, 1920, x15)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x6, 1928, x15)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x6, 1936, x15)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x6, 1944, x15)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x6, 1952, x15)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x6, 1960, x15)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x6, 1968, x15)
+
+inst_522:
+// rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x6, 1976, x15)
+
+inst_523:
+// rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x6, 1984, x15)
+
+inst_524:
+// rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: ror ; op1:x10; op2:x11; dest:x12; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(ror, x12, x10, x11, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x6, 1992, x15)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 250*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S
new file mode 100644
index 000000000..64b60a7f1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rori-01.S
@@ -0,0 +1,1531 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the rori instruction of the RISC-V  extension for the rori covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rori)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",rori)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",rori)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",rori)
+
+RVTEST_SIGBASE( x8,signature_x8_1)
+
+inst_0:
+// rs1 != rd, rs1==x22, rd==x16, rs1_val == 0xFFFFFFFFFFFFFFFF and imm_val == 0x36 
+// opcode: rori ; op1:x22; dest:x16; op1val:0xffffffffffffffff;  immval:0x36
+TEST_IMM_OP( rori, x16, x22, 0x0000000000000000, 0xffffffffffffffff, 0x36, x8, 0, x11)
+
+inst_1:
+// rs1 == rd, rs1==x0, rd==x0, imm_val == 0x00 and rs1_val == 0xCADB5BEC61250888 
+// opcode: rori ; op1:x0; dest:x0; op1val:0x0;  immval:0x0
+TEST_IMM_OP( rori, x0, x0, 0x0000000000000000, 0x0, 0x0, x8, 8, x11)
+
+inst_2:
+// rs1==x30, rd==x25, imm_val == 0x20 and rs1_val == 0xE917333212AF8F73 
+// opcode: rori ; op1:x30; dest:x25; op1val:0xe917333212af8f73;  immval:0x20
+TEST_IMM_OP( rori, x25, x30, 0x0000000000000000, 0xe917333212af8f73, 0x20, x8, 16, x11)
+
+inst_3:
+// rs1==x24, rd==x4, imm_val == 0x10 and rs1_val == 0xCC381E1007E8BF65 
+// opcode: rori ; op1:x24; dest:x4; op1val:0xcc381e1007e8bf65;  immval:0x10
+TEST_IMM_OP( rori, x4, x24, 0x0000000000000000, 0xcc381e1007e8bf65, 0x10, x8, 24, x11)
+
+inst_4:
+// rs1==x25, rd==x20, imm_val == 0x18 and rs1_val == 0xFAE216DC58F45328 
+// opcode: rori ; op1:x25; dest:x20; op1val:0xfae216dc58f45328;  immval:0x18
+TEST_IMM_OP( rori, x20, x25, 0x0000000000000000, 0xfae216dc58f45328, 0x18, x8, 32, x11)
+
+inst_5:
+// rs1==x2, rd==x7, imm_val == 0x1C and rs1_val == 0xE6A56AE617C67895 
+// opcode: rori ; op1:x2; dest:x7; op1val:0xe6a56ae617c67895;  immval:0x1c
+TEST_IMM_OP( rori, x7, x2, 0x0000000000000000, 0xe6a56ae617c67895, 0x1c, x8, 40, x11)
+
+inst_6:
+// rs1==x21, rd==x24, imm_val == 0x22 and rs1_val == 0x6AEB7DBD0A095049 
+// opcode: rori ; op1:x21; dest:x24; op1val:0x6aeb7dbd0a095049;  immval:0x22
+TEST_IMM_OP( rori, x24, x21, 0x0000000000000000, 0x6aeb7dbd0a095049, 0x22, x8, 48, x11)
+
+inst_7:
+// rs1==x12, rd==x1, imm_val == 0x0D and rs1_val == 0xF644D360EFB8C545 
+// opcode: rori ; op1:x12; dest:x1; op1val:0xf644d360efb8c545;  immval:0xd
+TEST_IMM_OP( rori, x1, x12, 0x0000000000000000, 0xf644d360efb8c545, 0xd, x8, 56, x11)
+
+inst_8:
+// rs1==x19, rd==x14, rs1_val == 0x0000000000000000 and imm_val == 0x1E 
+// opcode: rori ; op1:x19; dest:x14; op1val:0x0;  immval:0x1e
+TEST_IMM_OP( rori, x14, x19, 0x0000000000000000, 0x0, 0x1e, x8, 64, x11)
+
+inst_9:
+// rs1==x29, rd==x27, rs1_val == 0x8000000000000000 and imm_val == 0x22 
+// opcode: rori ; op1:x29; dest:x27; op1val:0x8000000000000000;  immval:0x22
+TEST_IMM_OP( rori, x27, x29, 0x0000000000000000, 0x8000000000000000, 0x22, x8, 72, x11)
+
+inst_10:
+// rs1==x4, rd==x22, rs1_val == 0xC000000000000000 and imm_val == 0x10 
+// opcode: rori ; op1:x4; dest:x22; op1val:0xc000000000000000;  immval:0x10
+TEST_IMM_OP( rori, x22, x4, 0x0000000000000000, 0xc000000000000000, 0x10, x8, 80, x11)
+
+inst_11:
+// rs1==x15, rd==x30, rs1_val == 0x6000000000000000 and imm_val == 0x00 
+// opcode: rori ; op1:x15; dest:x30; op1val:0x6000000000000000;  immval:0x0
+TEST_IMM_OP( rori, x30, x15, 0x0000000000000000, 0x6000000000000000, 0x0, x8, 88, x11)
+
+inst_12:
+// rs1==x10, rd==x21, rs1_val == 0xF000000000000000 and imm_val == 0x20 
+// opcode: rori ; op1:x10; dest:x21; op1val:0xf000000000000000;  immval:0x20
+TEST_IMM_OP( rori, x21, x10, 0x0000000000000000, 0xf000000000000000, 0x20, x8, 96, x11)
+
+inst_13:
+// rs1==x6, rd==x29, rs1_val == 0x1800000000000000 and imm_val == 0x1B 
+// opcode: rori ; op1:x6; dest:x29; op1val:0x1800000000000000;  immval:0x1b
+TEST_IMM_OP( rori, x29, x6, 0x0000000000000000, 0x1800000000000000, 0x1b, x8, 104, x11)
+
+inst_14:
+// rs1==x3, rd==x26, rs1_val == 0x4400000000000000 and imm_val == 0x38 
+// opcode: rori ; op1:x3; dest:x26; op1val:0x4400000000000000;  immval:0x38
+TEST_IMM_OP( rori, x26, x3, 0x0000000000000000, 0x4400000000000000, 0x38, x8, 112, x11)
+
+inst_15:
+// rs1==x23, rd==x15, rs1_val == 0x3E00000000000000 and imm_val == 0x05 
+// opcode: rori ; op1:x23; dest:x15; op1val:0x3e00000000000000;  immval:0x5
+TEST_IMM_OP( rori, x15, x23, 0x0000000000000000, 0x3e00000000000000, 0x5, x8, 120, x11)
+
+inst_16:
+// rs1==x16, rd==x12, rs1_val == 0x3500000000000000 and imm_val == 0x14 
+// opcode: rori ; op1:x16; dest:x12; op1val:0x3500000000000000;  immval:0x14
+TEST_IMM_OP( rori, x12, x16, 0x0000000000000000, 0x3500000000000000, 0x14, x8, 128, x11)
+
+inst_17:
+// rs1==x31, rd==x23, rs1_val == 0x6F80000000000000 and imm_val == 0x38 
+// opcode: rori ; op1:x31; dest:x23; op1val:0x6f80000000000000;  immval:0x38
+TEST_IMM_OP( rori, x23, x31, 0x0000000000000000, 0x6f80000000000000, 0x38, x8, 136, x11)
+
+inst_18:
+// rs1==x5, rd==x19, rs1_val == 0x4EC0000000000000 and imm_val == 0x2D 
+// opcode: rori ; op1:x5; dest:x19; op1val:0x4ec0000000000000;  immval:0x2d
+TEST_IMM_OP( rori, x19, x5, 0x0000000000000000, 0x4ec0000000000000, 0x2d, x8, 144, x11)
+
+inst_19:
+// rs1==x9, rd==x28, rs1_val == 0x1E20000000000000 and imm_val == 0x3D 
+// opcode: rori ; op1:x9; dest:x28; op1val:0x1e20000000000000;  immval:0x3d
+TEST_IMM_OP( rori, x28, x9, 0x0000000000000000, 0x1e20000000000000, 0x3d, x8, 152, x11)
+
+inst_20:
+// rs1==x26, rd==x18, rs1_val == 0x1910000000000000 and imm_val == 0x1D 
+// opcode: rori ; op1:x26; dest:x18; op1val:0x1910000000000000;  immval:0x1d
+TEST_IMM_OP( rori, x18, x26, 0x0000000000000000, 0x1910000000000000, 0x1d, x8, 160, x11)
+
+inst_21:
+// rs1==x13, rd==x3, rs1_val == 0x1248000000000000 and imm_val == 0x23 
+// opcode: rori ; op1:x13; dest:x3; op1val:0x1248000000000000;  immval:0x23
+TEST_IMM_OP( rori, x3, x13, 0x0000000000000000, 0x1248000000000000, 0x23, x8, 168, x4)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_22:
+// rs1==x27, rd==x10, rs1_val == 0xBF84000000000000 and imm_val == 0x29 
+// opcode: rori ; op1:x27; dest:x10; op1val:0xbf84000000000000;  immval:0x29
+TEST_IMM_OP( rori, x10, x27, 0x0000000000000000, 0xbf84000000000000, 0x29, x3, 0, x4)
+
+inst_23:
+// rs1==x11, rd==x17, rs1_val == 0xC116000000000000 and imm_val == 0x13 
+// opcode: rori ; op1:x11; dest:x17; op1val:0xc116000000000000;  immval:0x13
+TEST_IMM_OP( rori, x17, x11, 0x0000000000000000, 0xc116000000000000, 0x13, x3, 8, x4)
+
+inst_24:
+// rs1==x18, rd==x13, rs1_val == 0xD631000000000000 and imm_val == 0x2E 
+// opcode: rori ; op1:x18; dest:x13; op1val:0xd631000000000000;  immval:0x2e
+TEST_IMM_OP( rori, x13, x18, 0x0000000000000000, 0xd631000000000000, 0x2e, x3, 16, x4)
+
+inst_25:
+// rs1==x28, rd==x9, rs1_val == 0x17B2800000000000 and imm_val == 0x1F 
+// opcode: rori ; op1:x28; dest:x9; op1val:0x17b2800000000000;  immval:0x1f
+TEST_IMM_OP( rori, x9, x28, 0x0000000000000000, 0x17b2800000000000, 0x1f, x3, 24, x4)
+
+inst_26:
+// rs1==x17, rd==x5, rs1_val == 0x9568400000000000 and imm_val == 0x01 
+// opcode: rori ; op1:x17; dest:x5; op1val:0x9568400000000000;  immval:0x1
+TEST_IMM_OP( rori, x5, x17, 0x0000000000000000, 0x9568400000000000, 0x1, x3, 32, x4)
+
+inst_27:
+// rs1==x1, rd==x11, rs1_val == 0x8B06600000000000 and imm_val == 0x2B 
+// opcode: rori ; op1:x1; dest:x11; op1val:0x8b06600000000000;  immval:0x2b
+TEST_IMM_OP( rori, x11, x1, 0x0000000000000000, 0x8b06600000000000, 0x2b, x3, 40, x4)
+
+inst_28:
+// rs1==x20, rd==x6, rs1_val == 0xB93DF00000000000 and imm_val == 0x00 
+// opcode: rori ; op1:x20; dest:x6; op1val:0xb93df00000000000;  immval:0x0
+TEST_IMM_OP( rori, x6, x20, 0x0000000000000000, 0xb93df00000000000, 0x0, x3, 48, x4)
+
+inst_29:
+// rs1==x8, rd==x2, rs1_val == 0x88ADB80000000000 and imm_val == 0x1C 
+// opcode: rori ; op1:x8; dest:x2; op1val:0x88adb80000000000;  immval:0x1c
+TEST_IMM_OP( rori, x2, x8, 0x0000000000000000, 0x88adb80000000000, 0x1c, x3, 56, x4)
+
+inst_30:
+// rs1==x14, rd==x8, rs1_val == 0xE180E40000000000 and imm_val == 0x2E 
+// opcode: rori ; op1:x14; dest:x8; op1val:0xe180e40000000000;  immval:0x2e
+TEST_IMM_OP( rori, x8, x14, 0x0000000000000000, 0xe180e40000000000, 0x2e, x3, 64, x4)
+
+inst_31:
+// rs1==x7, rd==x31, rs1_val == 0xD5CB7E0000000000 and imm_val == 0x15 
+// opcode: rori ; op1:x7; dest:x31; op1val:0xd5cb7e0000000000;  immval:0x15
+TEST_IMM_OP( rori, x31, x7, 0x0000000000000000, 0xd5cb7e0000000000, 0x15, x3, 72, x4)
+
+inst_32:
+// rs1_val == 0xA438230000000000 and imm_val == 0x3D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa438230000000000;  immval:0x3d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa438230000000000, 0x3d, x3, 80, x4)
+
+inst_33:
+// rs1_val == 0xB9BE488000000000 and imm_val == 0x24 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb9be488000000000;  immval:0x24
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb9be488000000000, 0x24, x3, 88, x4)
+
+inst_34:
+// rs1_val == 0xE5ABA74000000000 and imm_val == 0x2F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe5aba74000000000;  immval:0x2f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe5aba74000000000, 0x2f, x3, 96, x4)
+
+inst_35:
+// rs1_val == 0xF2124BA000000000 and imm_val == 0x06 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf2124ba000000000;  immval:0x6
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf2124ba000000000, 0x6, x3, 104, x4)
+
+inst_36:
+// rs1_val == 0x96EBEC5000000000 and imm_val == 0x23 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x96ebec5000000000;  immval:0x23
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x96ebec5000000000, 0x23, x3, 112, x4)
+
+inst_37:
+// rs1_val == 0x6CA53BC800000000 and imm_val == 0x23 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6ca53bc800000000;  immval:0x23
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6ca53bc800000000, 0x23, x3, 120, x4)
+
+inst_38:
+// rs1_val == 0x035FF31C00000000 and imm_val == 0x1C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x35ff31c00000000;  immval:0x1c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x35ff31c00000000, 0x1c, x3, 128, x4)
+
+inst_39:
+// rs1_val == 0x8B38E95A00000000 and imm_val == 0x0D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x8b38e95a00000000;  immval:0xd
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x8b38e95a00000000, 0xd, x3, 136, x4)
+
+inst_40:
+// rs1_val == 0x0B21BBBB00000000 and imm_val == 0x1A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb21bbbb00000000;  immval:0x1a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb21bbbb00000000, 0x1a, x3, 144, x4)
+
+inst_41:
+// rs1_val == 0x9C6FFFDC80000000 and imm_val == 0x36 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9c6fffdc80000000;  immval:0x36
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9c6fffdc80000000, 0x36, x3, 152, x4)
+
+inst_42:
+// rs1_val == 0x8217FFBE40000000 and imm_val == 0x03 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x8217ffbe40000000;  immval:0x3
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x8217ffbe40000000, 0x3, x3, 160, x4)
+
+inst_43:
+// rs1_val == 0x60E68CB720000000 and imm_val == 0x37 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x60e68cb720000000;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x60e68cb720000000, 0x37, x3, 168, x4)
+
+inst_44:
+// rs1_val == 0xF5D02B2010000000 and imm_val == 0x16 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf5d02b2010000000;  immval:0x16
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf5d02b2010000000, 0x16, x3, 176, x4)
+
+inst_45:
+// rs1_val == 0x4204DE9838000000 and imm_val == 0x2A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4204de9838000000;  immval:0x2a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4204de9838000000, 0x2a, x3, 184, x4)
+
+inst_46:
+// rs1_val == 0xF6B1F180F4000000 and imm_val == 0x0E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf6b1f180f4000000;  immval:0xe
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf6b1f180f4000000, 0xe, x3, 192, x4)
+
+inst_47:
+// rs1_val == 0xF5BB75A166000000 and imm_val == 0x31 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf5bb75a166000000;  immval:0x31
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf5bb75a166000000, 0x31, x3, 200, x4)
+
+inst_48:
+// rs1_val == 0xAA5B397039000000 and imm_val == 0x2E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xaa5b397039000000;  immval:0x2e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xaa5b397039000000, 0x2e, x3, 208, x4)
+
+inst_49:
+// rs1_val == 0x0E7BD5B154800000 and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe7bd5b154800000;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe7bd5b154800000, 0x21, x3, 216, x4)
+
+inst_50:
+// rs1_val == 0xB7A2A2301A400000 and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb7a2a2301a400000;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb7a2a2301a400000, 0xa, x3, 224, x4)
+
+inst_51:
+// rs1_val == 0x29EF41AF7B600000 and imm_val == 0x31 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x29ef41af7b600000;  immval:0x31
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x29ef41af7b600000, 0x31, x3, 232, x4)
+
+inst_52:
+// rs1_val == 0xDD8AB0BCEFB00000 and imm_val == 0x3C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xdd8ab0bcefb00000;  immval:0x3c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xdd8ab0bcefb00000, 0x3c, x3, 240, x4)
+
+inst_53:
+// rs1_val == 0xFA3B344326080000 and imm_val == 0x35 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfa3b344326080000;  immval:0x35
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfa3b344326080000, 0x35, x3, 248, x4)
+
+inst_54:
+// rs1_val == 0xBF06387955040000 and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xbf06387955040000;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xbf06387955040000, 0xa, x3, 256, x4)
+
+inst_55:
+// rs1_val == 0x7D49F3CA79FA0000 and imm_val == 0x06 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7d49f3ca79fa0000;  immval:0x6
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7d49f3ca79fa0000, 0x6, x3, 264, x4)
+
+inst_56:
+// rs1_val == 0xAAB48A1C0F230000 and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xaab48a1c0f230000;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xaab48a1c0f230000, 0x14, x3, 272, x4)
+
+inst_57:
+// rs1_val == 0xA25E549735CB8000 and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa25e549735cb8000;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa25e549735cb8000, 0x11, x3, 280, x4)
+
+inst_58:
+// rs1_val == 0x49E43C96F2344000 and imm_val == 0x0E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x49e43c96f2344000;  immval:0xe
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x49e43c96f2344000, 0xe, x3, 288, x4)
+
+inst_59:
+// rs1_val == 0x971662E94AAA2000 and imm_val == 0x36 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x971662e94aaa2000;  immval:0x36
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x971662e94aaa2000, 0x36, x3, 296, x4)
+
+inst_60:
+// rs1_val == 0xFA51CD1D4D2B5000 and imm_val == 0x1C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfa51cd1d4d2b5000;  immval:0x1c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfa51cd1d4d2b5000, 0x1c, x3, 304, x4)
+
+inst_61:
+// rs1_val == 0xEBC398261A02E800 and imm_val == 0x07 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xebc398261a02e800;  immval:0x7
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xebc398261a02e800, 0x7, x3, 312, x4)
+
+inst_62:
+// rs1_val == 0x5334BAB9CA6C0400 and imm_val == 0x0B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5334bab9ca6c0400;  immval:0xb
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5334bab9ca6c0400, 0xb, x3, 320, x4)
+
+inst_63:
+// rs1_val == 0xEC133026333BC200 and imm_val == 0x2B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xec133026333bc200;  immval:0x2b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xec133026333bc200, 0x2b, x3, 328, x4)
+
+inst_64:
+// rs1_val == 0x82CC710F0F1C6B00 and imm_val == 0x19 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x82cc710f0f1c6b00;  immval:0x19
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x82cc710f0f1c6b00, 0x19, x3, 336, x4)
+
+inst_65:
+// rs1_val == 0x7AA3D594C52CFC80 and imm_val == 0x1A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7aa3d594c52cfc80;  immval:0x1a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7aa3d594c52cfc80, 0x1a, x3, 344, x4)
+
+inst_66:
+// rs1_val == 0x29DB927E9836F5C0 and imm_val == 0x2F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x29db927e9836f5c0;  immval:0x2f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x29db927e9836f5c0, 0x2f, x3, 352, x4)
+
+inst_67:
+// rs1_val == 0x0DA598F1DCB160E0 and imm_val == 0x12 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xda598f1dcb160e0;  immval:0x12
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xda598f1dcb160e0, 0x12, x3, 360, x4)
+
+inst_68:
+// rs1_val == 0xD45AF1CB0CAAE1D0 and imm_val == 0x1D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd45af1cb0caae1d0;  immval:0x1d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd45af1cb0caae1d0, 0x1d, x3, 368, x4)
+
+inst_69:
+// rs1_val == 0x25B37C62314026E8 and imm_val == 0x3A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x25b37c62314026e8;  immval:0x3a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x25b37c62314026e8, 0x3a, x3, 376, x4)
+
+inst_70:
+// rs1_val == 0x7FBFA447FC8A89F4 and imm_val == 0x3D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7fbfa447fc8a89f4;  immval:0x3d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7fbfa447fc8a89f4, 0x3d, x3, 384, x4)
+
+inst_71:
+// rs1_val == 0xC36673FE4902E9CE and imm_val == 0x01 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc36673fe4902e9ce;  immval:0x1
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc36673fe4902e9ce, 0x1, x3, 392, x4)
+
+inst_72:
+// rs1_val == 0x44DCDA6A797D76DF and imm_val == 0x2C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x44dcda6a797d76df;  immval:0x2c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x44dcda6a797d76df, 0x2c, x3, 400, x4)
+
+inst_73:
+// imm_val == 0x18 and rs1_val == 0x0B27C3726F2BF862 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb27c3726f2bf862;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb27c3726f2bf862, 0x18, x3, 408, x4)
+
+inst_74:
+// imm_val == 0x01 and rs1_val == 0x20D68CEC58FC0342 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x20d68cec58fc0342;  immval:0x1
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x20d68cec58fc0342, 0x1, x3, 416, x4)
+
+inst_75:
+// imm_val == 0x13 and rs1_val == 0x636A75E39A6DA5B1 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x636a75e39a6da5b1;  immval:0x13
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x636a75e39a6da5b1, 0x13, x3, 424, x4)
+
+inst_76:
+// imm_val == 0x37 and rs1_val == 0x37E0DE00280088DB 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x37e0de00280088db;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x37e0de00280088db, 0x37, x3, 432, x4)
+
+inst_77:
+// imm_val == 0x0F and rs1_val == 0x1CA7BD1F0D770F3C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1ca7bd1f0d770f3c;  immval:0xf
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1ca7bd1f0d770f3c, 0xf, x3, 440, x4)
+
+inst_78:
+// imm_val == 0x1F and rs1_val == 0x5536B8D863C2504C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5536b8d863c2504c;  immval:0x1f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5536b8d863c2504c, 0x1f, x3, 448, x4)
+
+inst_79:
+// imm_val == 0x3F and rs1_val == 0x4E6EE408C61B1FBF 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4e6ee408c61b1fbf;  immval:0x3f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4e6ee408c61b1fbf, 0x3f, x3, 456, x4)
+
+inst_80:
+// rs1_val == 0xC215E193118E5332 and imm_val == 0x05 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc215e193118e5332;  immval:0x5
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc215e193118e5332, 0x5, x3, 464, x4)
+
+inst_81:
+// rs1_val == 0x75EE935F65CB60C1 and imm_val == 0x0B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x75ee935f65cb60c1;  immval:0xb
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x75ee935f65cb60c1, 0xb, x3, 472, x4)
+
+inst_82:
+// rs1_val == 0x09C161626CE859BB and imm_val == 0x28 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9c161626ce859bb;  immval:0x28
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9c161626ce859bb, 0x28, x3, 480, x4)
+
+inst_83:
+// rs1_val == 0xA4053175342F57C7 and imm_val == 0x2C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa4053175342f57c7;  immval:0x2c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa4053175342f57c7, 0x2c, x3, 488, x4)
+
+inst_84:
+// rs1_val == 0x499006C897933E6F and imm_val == 0x36 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x499006c897933e6f;  immval:0x36
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x499006c897933e6f, 0x36, x3, 496, x4)
+
+inst_85:
+// rs1_val == 0xC5DD85CA5B064A1F and imm_val == 0x1F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc5dd85ca5b064a1f;  immval:0x1f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc5dd85ca5b064a1f, 0x1f, x3, 504, x4)
+
+inst_86:
+// rs1_val == 0x6CC30F7242302B3F and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6cc30f7242302b3f;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6cc30f7242302b3f, 0x1e, x3, 512, x4)
+
+inst_87:
+// rs1_val == 0xAF1DBF276CE4747F and imm_val == 0x1B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xaf1dbf276ce4747f;  immval:0x1b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xaf1dbf276ce4747f, 0x1b, x3, 520, x4)
+
+inst_88:
+// rs1_val == 0x25784F4FBD0608FF and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x25784f4fbd0608ff;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x25784f4fbd0608ff, 0x21, x3, 528, x4)
+
+inst_89:
+// rs1_val == 0x805A391B604C85FF and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x805a391b604c85ff;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x805a391b604c85ff, 0x14, x3, 536, x4)
+
+inst_90:
+// rs1_val == 0xCC7EB77D4BEB1BFF and imm_val == 0x04 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xcc7eb77d4beb1bff;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xcc7eb77d4beb1bff, 0x4, x3, 544, x4)
+
+inst_91:
+// rs1_val == 0xAB647BCA3919F7FF and imm_val == 0x1A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xab647bca3919f7ff;  immval:0x1a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xab647bca3919f7ff, 0x1a, x3, 552, x4)
+
+inst_92:
+// rs1_val == 0x7F1E7F8627B22FFF and imm_val == 0x3C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7f1e7f8627b22fff;  immval:0x3c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7f1e7f8627b22fff, 0x3c, x3, 560, x4)
+
+inst_93:
+// rs1_val == 0x51D6D6DA01769FFF and imm_val == 0x2A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x51d6d6da01769fff;  immval:0x2a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x51d6d6da01769fff, 0x2a, x3, 568, x4)
+
+inst_94:
+// rs1_val == 0xD5A2038FDA04BFFF and imm_val == 0x04 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd5a2038fda04bfff;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd5a2038fda04bfff, 0x4, x3, 576, x4)
+
+inst_95:
+// rs1_val == 0x784ABEBBF03B7FFF and imm_val == 0x2E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x784abebbf03b7fff;  immval:0x2e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x784abebbf03b7fff, 0x2e, x3, 584, x4)
+
+inst_96:
+// rs1_val == 0x44D988FBE81EFFFF and imm_val == 0x09 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x44d988fbe81effff;  immval:0x9
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x44d988fbe81effff, 0x9, x3, 592, x4)
+
+inst_97:
+// rs1_val == 0x6875944E1F19FFFF and imm_val == 0x26 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6875944e1f19ffff;  immval:0x26
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6875944e1f19ffff, 0x26, x3, 600, x4)
+
+inst_98:
+// rs1_val == 0xFF7746E52063FFFF and imm_val == 0x27 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xff7746e52063ffff;  immval:0x27
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xff7746e52063ffff, 0x27, x3, 608, x4)
+
+inst_99:
+// rs1_val == 0x17B8B123A527FFFF and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x17b8b123a527ffff;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x17b8b123a527ffff, 0x0, x3, 616, x4)
+
+inst_100:
+// rs1_val == 0x70890268F88FFFFF and imm_val == 0x2B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x70890268f88fffff;  immval:0x2b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x70890268f88fffff, 0x2b, x3, 624, x4)
+
+inst_101:
+// rs1_val == 0x6DDC74E6119FFFFF and imm_val == 0x04 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6ddc74e6119fffff;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6ddc74e6119fffff, 0x4, x3, 632, x4)
+
+inst_102:
+// rs1_val == 0x39BE2172E6BFFFFF and imm_val == 0x15 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x39be2172e6bfffff;  immval:0x15
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x39be2172e6bfffff, 0x15, x3, 640, x4)
+
+inst_103:
+// rs1_val == 0xC99324582A7FFFFF and imm_val == 0x0E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc99324582a7fffff;  immval:0xe
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc99324582a7fffff, 0xe, x3, 648, x4)
+
+inst_104:
+// rs1_val == 0x4B9A6C802EFFFFFF and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4b9a6c802effffff;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4b9a6c802effffff, 0x18, x3, 656, x4)
+
+inst_105:
+// rs1_val == 0x9541240E59FFFFFF and imm_val == 0x2B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9541240e59ffffff;  immval:0x2b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9541240e59ffffff, 0x2b, x3, 664, x4)
+
+inst_106:
+// rs1_val == 0xB3A8D61293FFFFFF and imm_val == 0x04 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb3a8d61293ffffff;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb3a8d61293ffffff, 0x4, x3, 672, x4)
+
+inst_107:
+// rs1_val == 0x9E03793FD7FFFFFF and imm_val == 0x05 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9e03793fd7ffffff;  immval:0x5
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9e03793fd7ffffff, 0x5, x3, 680, x4)
+
+inst_108:
+// rs1_val == 0x7F1071ECAFFFFFFF and imm_val == 0x1B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7f1071ecafffffff;  immval:0x1b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7f1071ecafffffff, 0x1b, x3, 688, x4)
+
+inst_109:
+// rs1_val == 0xF8A75516DFFFFFFF and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf8a75516dfffffff;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf8a75516dfffffff, 0x1e, x3, 696, x4)
+
+inst_110:
+// rs1_val == 0xB76D454DBFFFFFFF and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb76d454dbfffffff;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb76d454dbfffffff, 0x11, x3, 704, x4)
+
+inst_111:
+// rs1_val == 0xB494A73D7FFFFFFF and imm_val == 0x2F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb494a73d7fffffff;  immval:0x2f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb494a73d7fffffff, 0x2f, x3, 712, x4)
+
+inst_112:
+// rs1_val == 0xC28CB594FFFFFFFF and imm_val == 0x2C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc28cb594ffffffff;  immval:0x2c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc28cb594ffffffff, 0x2c, x3, 720, x4)
+
+inst_113:
+// rs1_val == 0x69DA8A2DFFFFFFFF and imm_val == 0x20 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x69da8a2dffffffff;  immval:0x20
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x69da8a2dffffffff, 0x20, x3, 728, x4)
+
+inst_114:
+// rs1_val == 0x40F27003FFFFFFFF and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x40f27003ffffffff;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x40f27003ffffffff, 0x14, x3, 736, x4)
+
+inst_115:
+// rs1_val == 0xB2B8AF97FFFFFFFF and imm_val == 0x38 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xb2b8af97ffffffff;  immval:0x38
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xb2b8af97ffffffff, 0x38, x3, 744, x4)
+
+inst_116:
+// rs1_val == 0x24496FEFFFFFFFFF and imm_val == 0x3F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x24496fefffffffff;  immval:0x3f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x24496fefffffffff, 0x3f, x3, 752, x4)
+
+inst_117:
+// rs1_val == 0xDE14BFDFFFFFFFFF and imm_val == 0x05 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xde14bfdfffffffff;  immval:0x5
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xde14bfdfffffffff, 0x5, x3, 760, x4)
+
+inst_118:
+// rs1_val == 0x008EEF3FFFFFFFFF and imm_val == 0x36 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x8eef3fffffffff;  immval:0x36
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x8eef3fffffffff, 0x36, x3, 768, x4)
+
+inst_119:
+// rs1_val == 0x6E2D707FFFFFFFFF and imm_val == 0x3B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6e2d707fffffffff;  immval:0x3b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6e2d707fffffffff, 0x3b, x3, 776, x4)
+
+inst_120:
+// rs1_val == 0x5DCF00FFFFFFFFFF and imm_val == 0x10 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5dcf00ffffffffff;  immval:0x10
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5dcf00ffffffffff, 0x10, x3, 784, x4)
+
+inst_121:
+// rs1_val == 0x3C5569FFFFFFFFFF and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3c5569ffffffffff;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3c5569ffffffffff, 0x18, x3, 792, x4)
+
+inst_122:
+// rs1_val == 0x7DA8D3FFFFFFFFFF and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7da8d3ffffffffff;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7da8d3ffffffffff, 0x1e, x3, 800, x4)
+
+inst_123:
+// rs1_val == 0xE3A707FFFFFFFFFF and imm_val == 0x10 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe3a707ffffffffff;  immval:0x10
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe3a707ffffffffff, 0x10, x3, 808, x4)
+
+inst_124:
+// rs1_val == 0x9B01EFFFFFFFFFFF and imm_val == 0x23 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9b01efffffffffff;  immval:0x23
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9b01efffffffffff, 0x23, x3, 816, x4)
+
+inst_125:
+// rs1_val == 0x5F011FFFFFFFFFFF and imm_val == 0x3A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5f011fffffffffff;  immval:0x3a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5f011fffffffffff, 0x3a, x3, 824, x4)
+
+inst_126:
+// rs1_val == 0x2DEDBFFFFFFFFFFF and imm_val == 0x2D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2dedbfffffffffff;  immval:0x2d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2dedbfffffffffff, 0x2d, x3, 832, x4)
+
+inst_127:
+// rs1_val == 0x2D377FFFFFFFFFFF and imm_val == 0x25 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2d377fffffffffff;  immval:0x25
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2d377fffffffffff, 0x25, x3, 840, x4)
+
+inst_128:
+// rs1_val == 0xAD44FFFFFFFFFFFF and imm_val == 0x38 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xad44ffffffffffff;  immval:0x38
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xad44ffffffffffff, 0x38, x3, 848, x4)
+
+inst_129:
+// rs1_val == 0x72C9FFFFFFFFFFFF and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x72c9ffffffffffff;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x72c9ffffffffffff, 0x11, x3, 856, x4)
+
+inst_130:
+// rs1_val == 0xD1D3FFFFFFFFFFFF and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd1d3ffffffffffff;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd1d3ffffffffffff, 0x21, x3, 864, x4)
+
+inst_131:
+// rs1_val == 0x5057FFFFFFFFFFFF and imm_val == 0x0F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5057ffffffffffff;  immval:0xf
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5057ffffffffffff, 0xf, x3, 872, x4)
+
+inst_132:
+// rs1_val == 0x5D2FFFFFFFFFFFFF and imm_val == 0x37 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5d2fffffffffffff;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5d2fffffffffffff, 0x37, x3, 880, x4)
+
+inst_133:
+// rs1_val == 0xE5DFFFFFFFFFFFFF and imm_val == 0x36 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe5dfffffffffffff;  immval:0x36
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe5dfffffffffffff, 0x36, x3, 888, x4)
+
+inst_134:
+// rs1_val == 0xD9BFFFFFFFFFFFFF and imm_val == 0x1D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd9bfffffffffffff;  immval:0x1d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd9bfffffffffffff, 0x1d, x3, 896, x4)
+
+inst_135:
+// rs1_val == 0x237FFFFFFFFFFFFF and imm_val == 0x20 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x237fffffffffffff;  immval:0x20
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x237fffffffffffff, 0x20, x3, 904, x4)
+
+inst_136:
+// rs1_val == 0x72FFFFFFFFFFFFFF and imm_val == 0x37 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x72ffffffffffffff;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x72ffffffffffffff, 0x37, x3, 912, x4)
+
+inst_137:
+// rs1_val == 0xDDFFFFFFFFFFFFFF and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xddffffffffffffff;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xddffffffffffffff, 0x21, x3, 920, x4)
+
+inst_138:
+// rs1_val == 0x43FFFFFFFFFFFFFF and imm_val == 0x12 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x43ffffffffffffff;  immval:0x12
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x43ffffffffffffff, 0x12, x3, 928, x4)
+
+inst_139:
+// rs1_val == 0x27FFFFFFFFFFFFFF and imm_val == 0x01 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x27ffffffffffffff;  immval:0x1
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x27ffffffffffffff, 0x1, x3, 936, x4)
+
+inst_140:
+// rs1_val == 0x4FFFFFFFFFFFFFFF and imm_val == 0x03 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4fffffffffffffff;  immval:0x3
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4fffffffffffffff, 0x3, x3, 944, x4)
+
+inst_141:
+// rs1_val == 0x1FFFFFFFFFFFFFFF and imm_val == 0x1B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1fffffffffffffff;  immval:0x1b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1fffffffffffffff, 0x1b, x3, 952, x4)
+
+inst_142:
+// rs1_val == 0x3FFFFFFFFFFFFFFF and imm_val == 0x17 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3fffffffffffffff;  immval:0x17
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3fffffffffffffff, 0x17, x3, 960, x4)
+
+inst_143:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and imm_val == 0x12 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7fffffffffffffff;  immval:0x12
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7fffffffffffffff, 0x12, x3, 968, x4)
+
+inst_144:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and imm_val == 0x17 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffffff;  immval:0x17
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffffff, 0x17, x3, 976, x4)
+
+inst_145:
+// imm_val == 0x22 and rs1_val == 0xF91ACB8D9279B1E9 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf91acb8d9279b1e9;  immval:0x22
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf91acb8d9279b1e9, 0x22, x3, 984, x4)
+
+inst_146:
+// imm_val == 0x13 and rs1_val == 0x482EA7602D1EF7BF 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x482ea7602d1ef7bf;  immval:0x13
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x482ea7602d1ef7bf, 0x13, x3, 992, x4)
+
+inst_147:
+// imm_val == 0x0B and rs1_val == 0x3FC2A9087219C1DA 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3fc2a9087219c1da;  immval:0xb
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3fc2a9087219c1da, 0xb, x3, 1000, x4)
+
+inst_148:
+// imm_val == 0x04 and rs1_val == 0x11B41900043E3EF5 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x11b41900043e3ef5;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x11b41900043e3ef5, 0x4, x3, 1008, x4)
+
+inst_149:
+// imm_val == 0x02 and rs1_val == 0xEA3A0683EAD81DCD 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xea3a0683ead81dcd;  immval:0x2
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xea3a0683ead81dcd, 0x2, x3, 1016, x4)
+
+inst_150:
+// imm_val == 0x01 and rs1_val == 0x12FAD8029D42F670 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x12fad8029d42f670;  immval:0x1
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x12fad8029d42f670, 0x1, x3, 1024, x4)
+
+inst_151:
+// imm_val == 0x00 and rs1_val == 0xFA285A0DB869135C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfa285a0db869135c;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfa285a0db869135c, 0x0, x3, 1032, x4)
+
+inst_152:
+// rs1_val == 0x852395744B1E943F and imm_val == 0x16 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x852395744b1e943f;  immval:0x16
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x852395744b1e943f, 0x16, x3, 1040, x4)
+
+inst_153:
+// rs1_val == 0x6BBA8D2141C9886F and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6bba8d2141c9886f;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6bba8d2141c9886f, 0x3e, x3, 1048, x4)
+
+inst_154:
+// rs1_val == 0x3D65693B3D0840FC and imm_val == 0x32 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3d65693b3d0840fc;  immval:0x32
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3d65693b3d0840fc, 0x32, x3, 1056, x4)
+
+inst_155:
+// rs1_val == 0x19E803191BEA8594 and imm_val == 0x20 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x19e803191bea8594;  immval:0x20
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x19e803191bea8594, 0x20, x3, 1064, x4)
+
+inst_156:
+// rs1_val == 0x0C2282666BE49EE8 and imm_val == 0x0D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc2282666be49ee8;  immval:0xd
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc2282666be49ee8, 0xd, x3, 1072, x4)
+
+inst_157:
+// rs1_val == 0x07862EACE1D73010 and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x7862eace1d73010;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x7862eace1d73010, 0xa, x3, 1080, x4)
+
+inst_158:
+// rs1_val == 0x033C1A7FAFDD8734 and imm_val == 0x31 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x33c1a7fafdd8734;  immval:0x31
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x33c1a7fafdd8734, 0x31, x3, 1088, x4)
+
+inst_159:
+// rs1_val == 0x0104A795BD4AEAB1 and imm_val == 0x19 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x104a795bd4aeab1;  immval:0x19
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x104a795bd4aeab1, 0x19, x3, 1096, x4)
+
+inst_160:
+// rs1_val == 0x0096C6C8B9B338EC and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x96c6c8b9b338ec;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x96c6c8b9b338ec, 0x14, x3, 1104, x4)
+
+inst_161:
+// rs1_val == 0x00775505E88E7530 and imm_val == 0x1F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x775505e88e7530;  immval:0x1f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x775505e88e7530, 0x1f, x3, 1112, x4)
+
+inst_162:
+// rs1_val == 0x00356991A0931ED5 and imm_val == 0x27 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x356991a0931ed5;  immval:0x27
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x356991a0931ed5, 0x27, x3, 1120, x4)
+
+inst_163:
+// rs1_val == 0x00174145DDD4A055 and imm_val == 0x17 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x174145ddd4a055;  immval:0x17
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x174145ddd4a055, 0x17, x3, 1128, x4)
+
+inst_164:
+// rs1_val == 0x000F19FDD5157E9E and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf19fdd5157e9e;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf19fdd5157e9e, 0x11, x3, 1136, x4)
+
+inst_165:
+// rs1_val == 0x0005D99A20918FA8 and imm_val == 0x3D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5d99a20918fa8;  immval:0x3d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5d99a20918fa8, 0x3d, x3, 1144, x4)
+
+inst_166:
+// rs1_val == 0x00032C075F27FF09 and imm_val == 0x3A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x32c075f27ff09;  immval:0x3a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x32c075f27ff09, 0x3a, x3, 1152, x4)
+
+inst_167:
+// rs1_val == 0x0001BCE703F8670E and imm_val == 0x2F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1bce703f8670e;  immval:0x2f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1bce703f8670e, 0x2f, x3, 1160, x4)
+
+inst_168:
+// rs1_val == 0x00009B8B356F8BD2 and imm_val == 0x1F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x9b8b356f8bd2;  immval:0x1f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x9b8b356f8bd2, 0x1f, x3, 1168, x4)
+
+inst_169:
+// rs1_val == 0x0000545212CA3F71 and imm_val == 0x0B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x545212ca3f71;  immval:0xb
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x545212ca3f71, 0xb, x3, 1176, x4)
+
+inst_170:
+// rs1_val == 0x00003090D48DD9F4 and imm_val == 0x31 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3090d48dd9f4;  immval:0x31
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3090d48dd9f4, 0x31, x3, 1184, x4)
+
+inst_171:
+// rs1_val == 0x00001DD8027385CA and imm_val == 0x2A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1dd8027385ca;  immval:0x2a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1dd8027385ca, 0x2a, x3, 1192, x4)
+
+inst_172:
+// rs1_val == 0x0000082236971E1C and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x82236971e1c;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x82236971e1c, 0x21, x3, 1200, x4)
+
+inst_173:
+// rs1_val == 0x000004440AC793F6 and imm_val == 0x12 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4440ac793f6;  immval:0x12
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4440ac793f6, 0x12, x3, 1208, x4)
+
+inst_174:
+// rs1_val == 0x000003D5FEEF16EA and imm_val == 0x0C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3d5feef16ea;  immval:0xc
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3d5feef16ea, 0xc, x3, 1216, x4)
+
+inst_175:
+// rs1_val == 0x0000010735F11AF3 and imm_val == 0x32 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x10735f11af3;  immval:0x32
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x10735f11af3, 0x32, x3, 1224, x4)
+
+inst_176:
+// rs1_val == 0x000000ACFF769E38 and imm_val == 0x02 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xacff769e38;  immval:0x2
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xacff769e38, 0x2, x3, 1232, x4)
+
+inst_177:
+// rs1_val == 0x000000764511488A and imm_val == 0x26 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x764511488a;  immval:0x26
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x764511488a, 0x26, x3, 1240, x4)
+
+inst_178:
+// rs1_val == 0x0000002DFD74106A and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2dfd74106a;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2dfd74106a, 0x0, x3, 1248, x4)
+
+inst_179:
+// rs1_val == 0x000000101DD377C0 and imm_val == 0x35 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x101dd377c0;  immval:0x35
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x101dd377c0, 0x35, x3, 1256, x4)
+
+inst_180:
+// rs1_val == 0x0000000A6B52B08E and imm_val == 0x31 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa6b52b08e;  immval:0x31
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa6b52b08e, 0x31, x3, 1264, x4)
+
+inst_181:
+// rs1_val == 0x00000004FC3B66FB and imm_val == 0x10 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4fc3b66fb;  immval:0x10
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4fc3b66fb, 0x10, x3, 1272, x4)
+
+inst_182:
+// rs1_val == 0x00000002728A6FD0 and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2728a6fd0;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2728a6fd0, 0x18, x3, 1280, x4)
+
+inst_183:
+// rs1_val == 0x00000001AE9CA08C and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1ae9ca08c;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1ae9ca08c, 0x18, x3, 1288, x4)
+
+inst_184:
+// rs1_val == 0x00000000CC099A1F and imm_val == 0x16 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xcc099a1f;  immval:0x16
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xcc099a1f, 0x16, x3, 1296, x4)
+
+inst_185:
+// rs1_val == 0x0000000042CDF2B0 and imm_val == 0x3B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x42cdf2b0;  immval:0x3b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x42cdf2b0, 0x3b, x3, 1304, x4)
+
+inst_186:
+// rs1_val == 0x000000002274EA19 and imm_val == 0x0C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2274ea19;  immval:0xc
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2274ea19, 0xc, x3, 1312, x4)
+
+inst_187:
+// rs1_val == 0x00000000120EF165 and imm_val == 0x0F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x120ef165;  immval:0xf
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x120ef165, 0xf, x3, 1320, x4)
+
+inst_188:
+// rs1_val == 0x000000000D2454F2 and imm_val == 0x34 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd2454f2;  immval:0x34
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd2454f2, 0x34, x3, 1328, x4)
+
+inst_189:
+// rs1_val == 0x00000000063E9BEE and imm_val == 0x27 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x63e9bee;  immval:0x27
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x63e9bee, 0x27, x3, 1336, x4)
+
+inst_190:
+// rs1_val == 0x00000000034C7CD0 and imm_val == 0x22 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x34c7cd0;  immval:0x22
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x34c7cd0, 0x22, x3, 1344, x4)
+
+inst_191:
+// rs1_val == 0x0000000001777310 and imm_val == 0x19 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1777310;  immval:0x19
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1777310, 0x19, x3, 1352, x4)
+
+inst_192:
+// rs1_val == 0x0000000000D11609 and imm_val == 0x32 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xd11609;  immval:0x32
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xd11609, 0x32, x3, 1360, x4)
+
+inst_193:
+// rs1_val == 0x0000000000680BE0 and imm_val == 0x06 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x680be0;  immval:0x6
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x680be0, 0x6, x3, 1368, x4)
+
+inst_194:
+// rs1_val == 0x0000000000294B16 and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x294b16;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x294b16, 0x0, x3, 1376, x4)
+
+inst_195:
+// rs1_val == 0x0000000000128D1B and imm_val == 0x02 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x128d1b;  immval:0x2
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x128d1b, 0x2, x3, 1384, x4)
+
+inst_196:
+// rs1_val == 0x0000000000089A12 and imm_val == 0x25 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x89a12;  immval:0x25
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x89a12, 0x25, x3, 1392, x4)
+
+inst_197:
+// rs1_val == 0x000000000005D25B and imm_val == 0x0D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5d25b;  immval:0xd
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5d25b, 0xd, x3, 1400, x4)
+
+inst_198:
+// rs1_val == 0x000000000003A2C3 and imm_val == 0x24 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3a2c3;  immval:0x24
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3a2c3, 0x24, x3, 1408, x4)
+
+inst_199:
+// rs1_val == 0x00000000000102FD and imm_val == 0x28 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x102fd;  immval:0x28
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x102fd, 0x28, x3, 1416, x4)
+
+inst_200:
+// rs1_val == 0x000000000000A6B3 and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa6b3;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa6b3, 0xa, x3, 1424, x4)
+
+inst_201:
+// rs1_val == 0x0000000000005238 and imm_val == 0x23 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x5238;  immval:0x23
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x5238, 0x23, x3, 1432, x4)
+
+inst_202:
+// rs1_val == 0x000000000000222A and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x222a;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x222a, 0xa, x3, 1440, x4)
+
+inst_203:
+// rs1_val == 0x0000000000001161 and imm_val == 0x25 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1161;  immval:0x25
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1161, 0x25, x3, 1448, x4)
+
+inst_204:
+// rs1_val == 0x0000000000000DB9 and imm_val == 0x19 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xdb9;  immval:0x19
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xdb9, 0x19, x3, 1456, x4)
+
+inst_205:
+// rs1_val == 0x00000000000004C1 and imm_val == 0x29 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x4c1;  immval:0x29
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x4c1, 0x29, x3, 1464, x4)
+
+inst_206:
+// rs1_val == 0x0000000000000390 and imm_val == 0x03 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x390;  immval:0x3
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x390, 0x3, x3, 1472, x4)
+
+inst_207:
+// rs1_val == 0x00000000000001D4 and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1d4;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1d4, 0x18, x3, 1480, x4)
+
+inst_208:
+// rs1_val == 0x00000000000000A7 and imm_val == 0x08 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa7;  immval:0x8
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa7, 0x8, x3, 1488, x4)
+
+inst_209:
+// rs1_val == 0x0000000000000079 and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x79;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x79, 0x14, x3, 1496, x4)
+
+inst_210:
+// rs1_val == 0x000000000000002C and imm_val == 0x32 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x2c;  immval:0x32
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x2c, 0x32, x3, 1504, x4)
+
+inst_211:
+// rs1_val == 0x000000000000001D and imm_val == 0x05 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1d;  immval:0x5
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1d, 0x5, x3, 1512, x4)
+
+inst_212:
+// rs1_val == 0x000000000000000C and imm_val == 0x26 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc;  immval:0x26
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc, 0x26, x3, 1520, x4)
+
+inst_213:
+// rs1_val == 0x0000000000000006 and imm_val == 0x17 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x6;  immval:0x17
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x6, 0x17, x3, 1528, x4)
+
+inst_214:
+// rs1_val == 0x0000000000000003 and imm_val == 0x3C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3;  immval:0x3c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3, 0x3c, x3, 1536, x4)
+
+inst_215:
+// rs1_val == 0x0000000000000001 and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x1;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x1, 0x18, x3, 1544, x4)
+
+inst_216:
+// rs1_val == 0x0000000000000000 and imm_val == 0x3B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x0;  immval:0x3b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x0, 0x3b, x3, 1552, x4)
+
+inst_217:
+// imm_val == 0x1C and rs1_val == 0xFC7C6D0A352C006F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfc7c6d0a352c006f;  immval:0x1c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfc7c6d0a352c006f, 0x1c, x3, 1560, x4)
+
+inst_218:
+// imm_val == 0x2C and rs1_val == 0x976AD220146A3673 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x976ad220146a3673;  immval:0x2c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x976ad220146a3673, 0x2c, x3, 1568, x4)
+
+inst_219:
+// imm_val == 0x37 and rs1_val == 0xFC6113A3312529DC 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfc6113a3312529dc;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfc6113a3312529dc, 0x37, x3, 1576, x4)
+
+inst_220:
+// imm_val == 0x3B and rs1_val == 0x242A809B7A3209FE 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x242a809b7a3209fe;  immval:0x3b
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x242a809b7a3209fe, 0x3b, x3, 1584, x4)
+
+inst_221:
+// imm_val == 0x3C and rs1_val == 0xE380A1764A104E66 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe380a1764a104e66;  immval:0x3c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe380a1764a104e66, 0x3c, x3, 1592, x4)
+
+inst_222:
+// imm_val == 0x3E and rs1_val == 0xA0E0BD86D4551408 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xa0e0bd86d4551408;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xa0e0bd86d4551408, 0x3e, x3, 1600, x4)
+
+inst_223:
+// imm_val == 0x3F and rs1_val == 0xAFE08A13086C1B78 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xafe08a13086c1b78;  immval:0x3f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xafe08a13086c1b78, 0x3f, x3, 1608, x4)
+
+inst_224:
+// rs1_val == 0x3CC279B3BD59213F and imm_val == 0x29 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x3cc279b3bd59213f;  immval:0x29
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x3cc279b3bd59213f, 0x29, x3, 1616, x4)
+
+inst_225:
+// rs1_val == 0x941060376C5E1579 and imm_val == 0x13 
+// opcode: rori ; op1:x10; dest:x11; op1val:0x941060376c5e1579;  immval:0x13
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0x941060376c5e1579, 0x13, x3, 1624, x4)
+
+inst_226:
+// rs1_val == 0xC9EA3210E5DF7F0B and imm_val == 0x3A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xc9ea3210e5df7f0b;  immval:0x3a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xc9ea3210e5df7f0b, 0x3a, x3, 1632, x4)
+
+inst_227:
+// rs1_val == 0xE9E93D5257DDE0F0 and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xe9e93d5257dde0f0;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xe9e93d5257dde0f0, 0x21, x3, 1640, x4)
+
+inst_228:
+// rs1_val == 0xF048E341C64C47E8 and imm_val == 0x39 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf048e341c64c47e8;  immval:0x39
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf048e341c64c47e8, 0x39, x3, 1648, x4)
+
+inst_229:
+// rs1_val == 0xF969730123A92480 and imm_val == 0x37 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xf969730123a92480;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xf969730123a92480, 0x37, x3, 1656, x4)
+
+inst_230:
+// rs1_val == 0xFC20CE1CD55D1CE8 and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfc20ce1cd55d1ce8;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfc20ce1cd55d1ce8, 0x3e, x3, 1664, x4)
+
+inst_231:
+// rs1_val == 0xFED775C526EA42ED and imm_val == 0x3A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfed775c526ea42ed;  immval:0x3a
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfed775c526ea42ed, 0x3a, x3, 1672, x4)
+
+inst_232:
+// rs1_val == 0xFF01DFA30CF25924 and imm_val == 0x0B 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xff01dfa30cf25924;  immval:0xb
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xff01dfa30cf25924, 0xb, x3, 1680, x4)
+
+inst_233:
+// rs1_val == 0xFF912F0A7046AB61 and imm_val == 0x08 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xff912f0a7046ab61;  immval:0x8
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xff912f0a7046ab61, 0x8, x3, 1688, x4)
+
+inst_234:
+// rs1_val == 0xFFCA96C9D43DB43F and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffca96c9d43db43f;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffca96c9d43db43f, 0x0, x3, 1696, x4)
+
+inst_235:
+// rs1_val == 0xFFEB4B49194135A5 and imm_val == 0x35 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffeb4b49194135a5;  immval:0x35
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffeb4b49194135a5, 0x35, x3, 1704, x4)
+
+inst_236:
+// rs1_val == 0xFFF1A2ADB3A63FA4 and imm_val == 0x38 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfff1a2adb3a63fa4;  immval:0x38
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfff1a2adb3a63fa4, 0x38, x3, 1712, x4)
+
+inst_237:
+// rs1_val == 0xFFF8306E89E6156C and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfff8306e89e6156c;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfff8306e89e6156c, 0x3e, x3, 1720, x4)
+
+inst_238:
+// rs1_val == 0xFFFDA6CA22C13476 and imm_val == 0x2C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffda6ca22c13476;  immval:0x2c
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffda6ca22c13476, 0x2c, x3, 1728, x4)
+
+inst_239:
+// rs1_val == 0xFFFE03B4AC9E9033 and imm_val == 0x33 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffe03b4ac9e9033;  immval:0x33
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffe03b4ac9e9033, 0x33, x3, 1736, x4)
+
+inst_240:
+// rs1_val == 0xFFFF3AD31011EEB5 and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffff3ad31011eeb5;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffff3ad31011eeb5, 0x3e, x3, 1744, x4)
+
+inst_241:
+// rs1_val == 0xFFFF90F48525E8A9 and imm_val == 0x3F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffff90f48525e8a9;  immval:0x3f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffff90f48525e8a9, 0x3f, x3, 1752, x4)
+
+inst_242:
+// rs1_val == 0xFFFFD6E6BC7F85E3 and imm_val == 0x22 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffd6e6bc7f85e3;  immval:0x22
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffd6e6bc7f85e3, 0x22, x3, 1760, x4)
+
+inst_243:
+// rs1_val == 0xFFFFE7F6AC60E057 and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffe7f6ac60e057;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffe7f6ac60e057, 0x1e, x3, 1768, x4)
+
+inst_244:
+// rs1_val == 0xFFFFF12863FD8180 and imm_val == 0x3F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffff12863fd8180;  immval:0x3f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffff12863fd8180, 0x3f, x3, 1776, x4)
+
+inst_245:
+// rs1_val == 0xFFFFFB5472B3CB0C and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffb5472b3cb0c;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffb5472b3cb0c, 0x14, x3, 1784, x4)
+
+inst_246:
+// rs1_val == 0xFFFFFD8D3E1C8522 and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffd8d3e1c8522;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffd8d3e1c8522, 0x21, x3, 1792, x4)
+
+inst_247:
+// rs1_val == 0xFFFFFE8F54E77CDC and imm_val == 0x28 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffe8f54e77cdc;  immval:0x28
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffe8f54e77cdc, 0x28, x3, 1800, x4)
+
+inst_248:
+// rs1_val == 0xFFFFFF048B7B5379 and imm_val == 0x05 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffff048b7b5379;  immval:0x5
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffff048b7b5379, 0x5, x3, 1808, x4)
+
+inst_249:
+// rs1_val == 0xFFFFFF856F4930C9 and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffff856f4930c9;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffff856f4930c9, 0x0, x3, 1816, x4)
+
+inst_250:
+// rs1_val == 0xFFFFFFDCC5D97467 and imm_val == 0x29 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffdcc5d97467;  immval:0x29
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffdcc5d97467, 0x29, x3, 1824, x4)
+
+inst_251:
+// rs1_val == 0xFFFFFFE5C70AFC93 and imm_val == 0x3D 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffe5c70afc93;  immval:0x3d
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffe5c70afc93, 0x3d, x3, 1832, x4)
+
+inst_252:
+// rs1_val == 0xFFFFFFF6A911655F and imm_val == 0x16 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffff6a911655f;  immval:0x16
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffff6a911655f, 0x16, x3, 1840, x4)
+
+inst_253:
+// rs1_val == 0xFFFFFFF974AB0A39 and imm_val == 0x15 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffff974ab0a39;  immval:0x15
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffff974ab0a39, 0x15, x3, 1848, x4)
+
+inst_254:
+// rs1_val == 0xFFFFFFFCDD68F202 and imm_val == 0x22 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffcdd68f202;  immval:0x22
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffcdd68f202, 0x22, x3, 1856, x4)
+
+inst_255:
+// rs1_val == 0xFFFFFFFE24BD4821 and imm_val == 0x16 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffe24bd4821;  immval:0x16
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffe24bd4821, 0x16, x3, 1864, x4)
+
+inst_256:
+// rs1_val == 0xFFFFFFFF3ED7E667 and imm_val == 0x23 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffff3ed7e667;  immval:0x23
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffff3ed7e667, 0x23, x3, 1872, x4)
+
+inst_257:
+// rs1_val == 0xFFFFFFFFB871CFDF and imm_val == 0x39 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffb871cfdf;  immval:0x39
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffb871cfdf, 0x39, x3, 1880, x4)
+
+inst_258:
+// rs1_val == 0xFFFFFFFFD29C11AE and imm_val == 0x37 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffd29c11ae;  immval:0x37
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffd29c11ae, 0x37, x3, 1888, x4)
+
+inst_259:
+// rs1_val == 0xFFFFFFFFE109799A and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffe109799a;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffe109799a, 0x18, x3, 1896, x4)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFF4E80B13 and imm_val == 0x0C 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffff4e80b13;  immval:0xc
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffff4e80b13, 0xc, x3, 1904, x4)
+
+inst_261:
+// rs1_val == 0xFFFFFFFFF9B7EA62 and imm_val == 0x13 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffff9b7ea62;  immval:0x13
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffff9b7ea62, 0x13, x3, 1912, x4)
+
+inst_262:
+// rs1_val == 0xFFFFFFFFFC51F638 and imm_val == 0x2F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffc51f638;  immval:0x2f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffc51f638, 0x2f, x3, 1920, x4)
+
+inst_263:
+// rs1_val == 0xFFFFFFFFFE9263CF and imm_val == 0x0A 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffe9263cf;  immval:0xa
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffe9263cf, 0xa, x3, 1928, x4)
+
+inst_264:
+// rs1_val == 0xFFFFFFFFFF216823 and imm_val == 0x09 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffff216823;  immval:0x9
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffff216823, 0x9, x3, 1936, x4)
+
+inst_265:
+// rs1_val == 0xFFFFFFFFFF861438 and imm_val == 0x04 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffff861438;  immval:0x4
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffff861438, 0x4, x3, 1944, x4)
+
+inst_266:
+// rs1_val == 0xFFFFFFFFFFD8C9D0 and imm_val == 0x34 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffd8c9d0;  immval:0x34
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffd8c9d0, 0x34, x3, 1952, x4)
+
+inst_267:
+// rs1_val == 0xFFFFFFFFFFE4D576 and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffe4d576;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffe4d576, 0x14, x3, 1960, x4)
+
+inst_268:
+// rs1_val == 0xFFFFFFFFFFF18C67 and imm_val == 0x29 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffff18c67;  immval:0x29
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffff18c67, 0x29, x3, 1968, x4)
+
+inst_269:
+// rs1_val == 0xFFFFFFFFFFFBB998 and imm_val == 0x08 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffbb998;  immval:0x8
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffbb998, 0x8, x3, 1976, x4)
+
+inst_270:
+// rs1_val == 0xFFFFFFFFFFFC2561 and imm_val == 0x39 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffc2561;  immval:0x39
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffc2561, 0x39, x3, 1984, x4)
+
+inst_271:
+// rs1_val == 0xFFFFFFFFFFFEEAB5 and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffeeab5;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffeeab5, 0x1e, x3, 1992, x4)
+
+inst_272:
+// rs1_val == 0xFFFFFFFFFFFF0651 and imm_val == 0x26 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffff0651;  immval:0x26
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffff0651, 0x26, x3, 2000, x4)
+
+inst_273:
+// rs1_val == 0xFFFFFFFFFFFF90E4 and imm_val == 0x18 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffff90e4;  immval:0x18
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffff90e4, 0x18, x3, 2008, x4)
+
+inst_274:
+// rs1_val == 0xFFFFFFFFFFFFCA23 and imm_val == 0x00 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffca23;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffca23, 0x0, x3, 2016, x4)
+
+inst_275:
+// rs1_val == 0xFFFFFFFFFFFFE2A0 and imm_val == 0x30 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffe2a0;  immval:0x30
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffe2a0, 0x30, x3, 2024, x4)
+
+inst_276:
+// rs1_val == 0xFFFFFFFFFFFFF2CC and imm_val == 0x1E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffff2cc;  immval:0x1e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffff2cc, 0x1e, x3, 2032, x4)
+
+inst_277:
+// rs1_val == 0xFFFFFFFFFFFFFAB4 and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffab4;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffab4, 0x11, x3, 2040, x4)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_278:
+// rs1_val == 0xFFFFFFFFFFFFFCEE and imm_val == 0x26 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffcee;  immval:0x26
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffcee, 0x26, x3, 0, x4)
+
+inst_279:
+// rs1_val == 0xFFFFFFFFFFFFFE04 and imm_val == 0x21 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffe04;  immval:0x21
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffe04, 0x21, x3, 8, x4)
+
+inst_280:
+// rs1_val == 0xFFFFFFFFFFFFFF2A and imm_val == 0x30 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffff2a;  immval:0x30
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffff2a, 0x30, x3, 16, x4)
+
+inst_281:
+// rs1_val == 0xFFFFFFFFFFFFFF9D and imm_val == 0x11 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffff9d;  immval:0x11
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffff9d, 0x11, x3, 24, x4)
+
+inst_282:
+// rs1_val == 0xFFFFFFFFFFFFFFC7 and imm_val == 0x2E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffffc7;  immval:0x2e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffffc7, 0x2e, x3, 32, x4)
+
+inst_283:
+// rs1_val == 0xFFFFFFFFFFFFFFE4 and imm_val == 0x1F 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xffffffffffffffe4;  immval:0x1f
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xffffffffffffffe4, 0x1f, x3, 40, x4)
+
+inst_284:
+// rs1_val == 0xFFFFFFFFFFFFFFF2 and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffff2;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffff2, 0x3e, x3, 48, x4)
+
+inst_285:
+// rs1_val == 0xFFFFFFFFFFFFFFF8 and imm_val == 0x14 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffff8;  immval:0x14
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffff8, 0x14, x3, 56, x4)
+
+inst_286:
+// rs1_val == 0xFFFFFFFFFFFFFFFD and imm_val == 0x3E 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;  immval:0x3e
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffffd, 0x3e, x3, 64, x4)
+
+inst_287:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and imm_val == 0x01 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;  immval:0x1
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xfffffffffffffffe, 0x1, x3, 72, x4)
+
+inst_288:
+// imm_val == 0x00 and rs1_val == 0xCADB5BEC61250888 
+// opcode: rori ; op1:x10; dest:x11; op1val:0xcadb5bec61250888;  immval:0x0
+TEST_IMM_OP( rori, x11, x10, 0x0000000000000000, 0xcadb5bec61250888, 0x0, x3, 80, x4)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x8_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 11*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S
new file mode 100644
index 000000000..f9d6a21ac
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/roriw-01.S
@@ -0,0 +1,1516 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the roriw instruction of the RISC-V  extension for the roriw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",roriw)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",roriw)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",roriw)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",roriw)
+
+RVTEST_SIGBASE( x18,signature_x18_1)
+
+inst_0:
+// rs1 != rd, rs1==x16, rd==x20, rs1_val == 0xFFFFFFFFFFFFFFFF and imm_val == 0x1B 
+// opcode: roriw ; op1:x16; dest:x20; op1val:0xffffffffffffffff;  immval:0x1b
+TEST_IMM_OP( roriw, x20, x16, 0x0000000000000000, 0xffffffffffffffff, 0x1b, x18, 0, x6)
+
+inst_1:
+// rs1 == rd, rs1==x17, rd==x17, imm_val == 0x00 and rs1_val == 0xE917333212AF8F73 
+// opcode: roriw ; op1:x17; dest:x17; op1val:0xe917333212af8f73;  immval:0x0
+TEST_IMM_OP( roriw, x17, x17, 0x0000000000000000, 0xe917333212af8f73, 0x0, x18, 8, x6)
+
+inst_2:
+// rs1==x3, rd==x1, imm_val == 0x10 and rs1_val == 0xCC381E1007E8BF65 
+// opcode: roriw ; op1:x3; dest:x1; op1val:0xcc381e1007e8bf65;  immval:0x10
+TEST_IMM_OP( roriw, x1, x3, 0x0000000000000000, 0xcc381e1007e8bf65, 0x10, x18, 16, x6)
+
+inst_3:
+// rs1==x30, rd==x19, imm_val == 0x18 and rs1_val == 0xFAE216DC58F45328 
+// opcode: roriw ; op1:x30; dest:x19; op1val:0xfae216dc58f45328;  immval:0x18
+TEST_IMM_OP( roriw, x19, x30, 0x0000000000000000, 0xfae216dc58f45328, 0x18, x18, 24, x6)
+
+inst_4:
+// rs1==x2, rd==x22, imm_val == 0x0C and rs1_val == 0xE6A56AE617C67895 
+// opcode: roriw ; op1:x2; dest:x22; op1val:0xe6a56ae617c67895;  immval:0xc
+TEST_IMM_OP( roriw, x22, x2, 0x0000000000000000, 0xe6a56ae617c67895, 0xc, x18, 32, x6)
+
+inst_5:
+// rs1==x25, rd==x3, imm_val == 0x12 and rs1_val == 0x6AEB7DBD0A095049 
+// opcode: roriw ; op1:x25; dest:x3; op1val:0x6aeb7dbd0a095049;  immval:0x12
+TEST_IMM_OP( roriw, x3, x25, 0x0000000000000000, 0x6aeb7dbd0a095049, 0x12, x18, 40, x6)
+
+inst_6:
+// rs1==x19, rd==x31, imm_val == 0x07 and rs1_val == 0xF644D360EFB8C545 
+// opcode: roriw ; op1:x19; dest:x31; op1val:0xf644d360efb8c545;  immval:0x7
+TEST_IMM_OP( roriw, x31, x19, 0x0000000000000000, 0xf644d360efb8c545, 0x7, x18, 48, x6)
+
+inst_7:
+// rs1==x8, rd==x25, rs1_val == 0x0000000000000000 and imm_val == 0x0F 
+// opcode: roriw ; op1:x8; dest:x25; op1val:0x0;  immval:0xf
+TEST_IMM_OP( roriw, x25, x8, 0x0000000000000000, 0x0, 0xf, x18, 56, x6)
+
+inst_8:
+// rs1==x22, rd==x14, rs1_val == 0x8000000000000000 and imm_val == 0x11 
+// opcode: roriw ; op1:x22; dest:x14; op1val:0x8000000000000000;  immval:0x11
+TEST_IMM_OP( roriw, x14, x22, 0x0000000000000000, 0x8000000000000000, 0x11, x18, 64, x6)
+
+inst_9:
+// rs1==x28, rd==x12, rs1_val == 0xC000000000000000 and imm_val == 0x08 
+// opcode: roriw ; op1:x28; dest:x12; op1val:0xc000000000000000;  immval:0x8
+TEST_IMM_OP( roriw, x12, x28, 0x0000000000000000, 0xc000000000000000, 0x8, x18, 72, x6)
+
+inst_10:
+// rs1==x23, rd==x5, rs1_val == 0x6000000000000000 and imm_val == 0x00 
+// opcode: roriw ; op1:x23; dest:x5; op1val:0x6000000000000000;  immval:0x0
+TEST_IMM_OP( roriw, x5, x23, 0x0000000000000000, 0x6000000000000000, 0x0, x18, 80, x6)
+
+inst_11:
+// rs1==x14, rd==x4, rs1_val == 0xF000000000000000 and imm_val == 0x10 
+// opcode: roriw ; op1:x14; dest:x4; op1val:0xf000000000000000;  immval:0x10
+TEST_IMM_OP( roriw, x4, x14, 0x0000000000000000, 0xf000000000000000, 0x10, x18, 88, x6)
+
+inst_12:
+// rs1==x4, rd==x26, rs1_val == 0x1800000000000000 and imm_val == 0x0D 
+// opcode: roriw ; op1:x4; dest:x26; op1val:0x1800000000000000;  immval:0xd
+TEST_IMM_OP( roriw, x26, x4, 0x0000000000000000, 0x1800000000000000, 0xd, x18, 96, x6)
+
+inst_13:
+// rs1==x13, rd==x16, rs1_val == 0x4400000000000000 and imm_val == 0x1C 
+// opcode: roriw ; op1:x13; dest:x16; op1val:0x4400000000000000;  immval:0x1c
+TEST_IMM_OP( roriw, x16, x13, 0x0000000000000000, 0x4400000000000000, 0x1c, x18, 104, x6)
+
+inst_14:
+// rs1==x27, rd==x11, rs1_val == 0x3E00000000000000 and imm_val == 0x02 
+// opcode: roriw ; op1:x27; dest:x11; op1val:0x3e00000000000000;  immval:0x2
+TEST_IMM_OP( roriw, x11, x27, 0x0000000000000000, 0x3e00000000000000, 0x2, x18, 112, x6)
+
+inst_15:
+// rs1==x20, rd==x7, rs1_val == 0x3500000000000000 and imm_val == 0x0A 
+// opcode: roriw ; op1:x20; dest:x7; op1val:0x3500000000000000;  immval:0xa
+TEST_IMM_OP( roriw, x7, x20, 0x0000000000000000, 0x3500000000000000, 0xa, x18, 120, x6)
+
+inst_16:
+// rs1==x11, rd==x30, rs1_val == 0x6F80000000000000 and imm_val == 0x1C 
+// opcode: roriw ; op1:x11; dest:x30; op1val:0x6f80000000000000;  immval:0x1c
+TEST_IMM_OP( roriw, x30, x11, 0x0000000000000000, 0x6f80000000000000, 0x1c, x18, 128, x6)
+
+inst_17:
+// rs1==x1, rd==x28, rs1_val == 0x4EC0000000000000 and imm_val == 0x16 
+// opcode: roriw ; op1:x1; dest:x28; op1val:0x4ec0000000000000;  immval:0x16
+TEST_IMM_OP( roriw, x28, x1, 0x0000000000000000, 0x4ec0000000000000, 0x16, x18, 136, x6)
+
+inst_18:
+// rs1==x0, rd==x23, rs1_val == 0x1E20000000000000 and imm_val == 0x1E 
+// opcode: roriw ; op1:x0; dest:x23; op1val:0x0;  immval:0x1e
+TEST_IMM_OP( roriw, x23, x0, 0x0000000000000000, 0x0, 0x1e, x18, 144, x6)
+
+inst_19:
+// rs1==x9, rd==x21, rs1_val == 0x1910000000000000 and imm_val == 0x0E 
+// opcode: roriw ; op1:x9; dest:x21; op1val:0x1910000000000000;  immval:0xe
+TEST_IMM_OP( roriw, x21, x9, 0x0000000000000000, 0x1910000000000000, 0xe, x18, 152, x6)
+
+inst_20:
+// rs1==x7, rd==x15, rs1_val == 0x1248000000000000 and imm_val == 0x11 
+// opcode: roriw ; op1:x7; dest:x15; op1val:0x1248000000000000;  immval:0x11
+TEST_IMM_OP( roriw, x15, x7, 0x0000000000000000, 0x1248000000000000, 0x11, x18, 160, x6)
+
+inst_21:
+// rs1==x24, rd==x27, rs1_val == 0xBF84000000000000 and imm_val == 0x14 
+// opcode: roriw ; op1:x24; dest:x27; op1val:0xbf84000000000000;  immval:0x14
+TEST_IMM_OP( roriw, x27, x24, 0x0000000000000000, 0xbf84000000000000, 0x14, x18, 168, x6)
+
+inst_22:
+// rs1==x10, rd==x6, rs1_val == 0xC116000000000000 and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x6; op1val:0xc116000000000000;  immval:0x9
+TEST_IMM_OP( roriw, x6, x10, 0x0000000000000000, 0xc116000000000000, 0x9, x18, 176, x3)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_23:
+// rs1==x29, rd==x8, rs1_val == 0xD631000000000000 and imm_val == 0x17 
+// opcode: roriw ; op1:x29; dest:x8; op1val:0xd631000000000000;  immval:0x17
+TEST_IMM_OP( roriw, x8, x29, 0x0000000000000000, 0xd631000000000000, 0x17, x1, 0, x3)
+
+inst_24:
+// rs1==x6, rd==x10, rs1_val == 0x17B2800000000000 and imm_val == 0x0F 
+// opcode: roriw ; op1:x6; dest:x10; op1val:0x17b2800000000000;  immval:0xf
+TEST_IMM_OP( roriw, x10, x6, 0x0000000000000000, 0x17b2800000000000, 0xf, x1, 8, x3)
+
+inst_25:
+// rs1==x12, rd==x0, rs1_val == 0x9568400000000000 and imm_val == 0x00 
+// opcode: roriw ; op1:x12; dest:x0; op1val:0x9568400000000000;  immval:0x0
+TEST_IMM_OP( roriw, x0, x12, 0x0000000000000000, 0x9568400000000000, 0x0, x1, 16, x3)
+
+inst_26:
+// rs1==x18, rd==x13, rs1_val == 0x8B06600000000000 and imm_val == 0x15 
+// opcode: roriw ; op1:x18; dest:x13; op1val:0x8b06600000000000;  immval:0x15
+TEST_IMM_OP( roriw, x13, x18, 0x0000000000000000, 0x8b06600000000000, 0x15, x1, 24, x3)
+
+inst_27:
+// rs1==x21, rd==x24, rs1_val == 0xB93DF00000000000 and imm_val == 0x00 
+// opcode: roriw ; op1:x21; dest:x24; op1val:0xb93df00000000000;  immval:0x0
+TEST_IMM_OP( roriw, x24, x21, 0x0000000000000000, 0xb93df00000000000, 0x0, x1, 32, x3)
+
+inst_28:
+// rs1==x15, rd==x9, rs1_val == 0x88ADB80000000000 and imm_val == 0x0E 
+// opcode: roriw ; op1:x15; dest:x9; op1val:0x88adb80000000000;  immval:0xe
+TEST_IMM_OP( roriw, x9, x15, 0x0000000000000000, 0x88adb80000000000, 0xe, x1, 40, x3)
+
+inst_29:
+// rs1==x5, rd==x18, rs1_val == 0xE180E40000000000 and imm_val == 0x17 
+// opcode: roriw ; op1:x5; dest:x18; op1val:0xe180e40000000000;  immval:0x17
+TEST_IMM_OP( roriw, x18, x5, 0x0000000000000000, 0xe180e40000000000, 0x17, x1, 48, x3)
+
+inst_30:
+// rs1==x26, rd==x29, rs1_val == 0xD5CB7E0000000000 and imm_val == 0x0A 
+// opcode: roriw ; op1:x26; dest:x29; op1val:0xd5cb7e0000000000;  immval:0xa
+TEST_IMM_OP( roriw, x29, x26, 0x0000000000000000, 0xd5cb7e0000000000, 0xa, x1, 56, x3)
+
+inst_31:
+// rs1==x31, rd==x2, rs1_val == 0xA438230000000000 and imm_val == 0x1E 
+// opcode: roriw ; op1:x31; dest:x2; op1val:0xa438230000000000;  immval:0x1e
+TEST_IMM_OP( roriw, x2, x31, 0x0000000000000000, 0xa438230000000000, 0x1e, x1, 64, x3)
+
+inst_32:
+// rs1_val == 0xB9BE488000000000 and imm_val == 0x12 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb9be488000000000;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb9be488000000000, 0x12, x1, 72, x3)
+
+inst_33:
+// rs1_val == 0xE5ABA74000000000 and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe5aba74000000000;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe5aba74000000000, 0x17, x1, 80, x3)
+
+inst_34:
+// rs1_val == 0xF2124BA000000000 and imm_val == 0x03 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf2124ba000000000;  immval:0x3
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf2124ba000000000, 0x3, x1, 88, x3)
+
+inst_35:
+// rs1_val == 0x96EBEC5000000000 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x96ebec5000000000;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x96ebec5000000000, 0x11, x1, 96, x3)
+
+inst_36:
+// rs1_val == 0x6CA53BC800000000 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6ca53bc800000000;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6ca53bc800000000, 0x11, x1, 104, x3)
+
+inst_37:
+// rs1_val == 0x035FF31C00000000 and imm_val == 0x0E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x35ff31c00000000;  immval:0xe
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x35ff31c00000000, 0xe, x1, 112, x3)
+
+inst_38:
+// rs1_val == 0x8B38E95A00000000 and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x8b38e95a00000000;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x8b38e95a00000000, 0x6, x1, 120, x3)
+
+inst_39:
+// rs1_val == 0x0B21BBBB00000000 and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb21bbbb00000000;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb21bbbb00000000, 0xd, x1, 128, x3)
+
+inst_40:
+// rs1_val == 0x9C6FFFDC80000000 and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9c6fffdc80000000;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9c6fffdc80000000, 0x1b, x1, 136, x3)
+
+inst_41:
+// rs1_val == 0x8217FFBE40000000 and imm_val == 0x01 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x8217ffbe40000000;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x8217ffbe40000000, 0x1, x1, 144, x3)
+
+inst_42:
+// rs1_val == 0x60E68CB720000000 and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x60e68cb720000000;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x60e68cb720000000, 0x1b, x1, 152, x3)
+
+inst_43:
+// rs1_val == 0xF5D02B2010000000 and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf5d02b2010000000;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf5d02b2010000000, 0xb, x1, 160, x3)
+
+inst_44:
+// rs1_val == 0x4204DE9838000000 and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4204de9838000000;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4204de9838000000, 0x15, x1, 168, x3)
+
+inst_45:
+// rs1_val == 0xF6B1F180F4000000 and imm_val == 0x07 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf6b1f180f4000000;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf6b1f180f4000000, 0x7, x1, 176, x3)
+
+inst_46:
+// rs1_val == 0xF5BB75A166000000 and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf5bb75a166000000;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf5bb75a166000000, 0x18, x1, 184, x3)
+
+inst_47:
+// rs1_val == 0xAA5B397039000000 and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xaa5b397039000000;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xaa5b397039000000, 0x17, x1, 192, x3)
+
+inst_48:
+// rs1_val == 0x0E7BD5B154800000 and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe7bd5b154800000;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe7bd5b154800000, 0x10, x1, 200, x3)
+
+inst_49:
+// rs1_val == 0xB7A2A2301A400000 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb7a2a2301a400000;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb7a2a2301a400000, 0x5, x1, 208, x3)
+
+inst_50:
+// rs1_val == 0x29EF41AF7B600000 and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x29ef41af7b600000;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x29ef41af7b600000, 0x18, x1, 216, x3)
+
+inst_51:
+// rs1_val == 0xDD8AB0BCEFB00000 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xdd8ab0bcefb00000;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xdd8ab0bcefb00000, 0x1e, x1, 224, x3)
+
+inst_52:
+// rs1_val == 0xFA3B344326080000 and imm_val == 0x1A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfa3b344326080000;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfa3b344326080000, 0x1a, x1, 232, x3)
+
+inst_53:
+// rs1_val == 0xBF06387955040000 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xbf06387955040000;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xbf06387955040000, 0x5, x1, 240, x3)
+
+inst_54:
+// rs1_val == 0x7D49F3CA79FA0000 and imm_val == 0x03 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7d49f3ca79fa0000;  immval:0x3
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7d49f3ca79fa0000, 0x3, x1, 248, x3)
+
+inst_55:
+// rs1_val == 0xAAB48A1C0F230000 and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xaab48a1c0f230000;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xaab48a1c0f230000, 0xa, x1, 256, x3)
+
+inst_56:
+// rs1_val == 0xA25E549735CB8000 and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa25e549735cb8000;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa25e549735cb8000, 0x8, x1, 264, x3)
+
+inst_57:
+// rs1_val == 0x49E43C96F2344000 and imm_val == 0x07 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x49e43c96f2344000;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x49e43c96f2344000, 0x7, x1, 272, x3)
+
+inst_58:
+// rs1_val == 0x971662E94AAA2000 and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x971662e94aaa2000;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x971662e94aaa2000, 0x1b, x1, 280, x3)
+
+inst_59:
+// rs1_val == 0xFA51CD1D4D2B5000 and imm_val == 0x0E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfa51cd1d4d2b5000;  immval:0xe
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfa51cd1d4d2b5000, 0xe, x1, 288, x3)
+
+inst_60:
+// rs1_val == 0xEBC398261A02E800 and imm_val == 0x03 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xebc398261a02e800;  immval:0x3
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xebc398261a02e800, 0x3, x1, 296, x3)
+
+inst_61:
+// rs1_val == 0x5334BAB9CA6C0400 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5334bab9ca6c0400;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5334bab9ca6c0400, 0x5, x1, 304, x3)
+
+inst_62:
+// rs1_val == 0xEC133026333BC200 and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xec133026333bc200;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xec133026333bc200, 0x15, x1, 312, x3)
+
+inst_63:
+// rs1_val == 0x82CC710F0F1C6B00 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x82cc710f0f1c6b00;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x82cc710f0f1c6b00, 0xc, x1, 320, x3)
+
+inst_64:
+// rs1_val == 0x7AA3D594C52CFC80 and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7aa3d594c52cfc80;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7aa3d594c52cfc80, 0xd, x1, 328, x3)
+
+inst_65:
+// rs1_val == 0x29DB927E9836F5C0 and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x29db927e9836f5c0;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x29db927e9836f5c0, 0x17, x1, 336, x3)
+
+inst_66:
+// rs1_val == 0x0DA598F1DCB160E0 and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xda598f1dcb160e0;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xda598f1dcb160e0, 0x9, x1, 344, x3)
+
+inst_67:
+// rs1_val == 0xD45AF1CB0CAAE1D0 and imm_val == 0x0E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd45af1cb0caae1d0;  immval:0xe
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd45af1cb0caae1d0, 0xe, x1, 352, x3)
+
+inst_68:
+// rs1_val == 0x25B37C62314026E8 and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x25b37c62314026e8;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x25b37c62314026e8, 0x1d, x1, 360, x3)
+
+inst_69:
+// rs1_val == 0x7FBFA447FC8A89F4 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7fbfa447fc8a89f4;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7fbfa447fc8a89f4, 0x1e, x1, 368, x3)
+
+inst_70:
+// rs1_val == 0xC36673FE4902E9CE and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc36673fe4902e9ce;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc36673fe4902e9ce, 0x0, x1, 376, x3)
+
+inst_71:
+// rs1_val == 0x44DCDA6A797D76DF and imm_val == 0x16 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x44dcda6a797d76df;  immval:0x16
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x44dcda6a797d76df, 0x16, x1, 384, x3)
+
+inst_72:
+// imm_val == 0x02 and rs1_val == 0x20D68CEC58FC0342 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x20d68cec58fc0342;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x20d68cec58fc0342, 0x2, x1, 392, x3)
+
+inst_73:
+// imm_val == 0x09 and rs1_val == 0x636A75E39A6DA5B1 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x636a75e39a6da5b1;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x636a75e39a6da5b1, 0x9, x1, 400, x3)
+
+inst_74:
+// imm_val == 0x1B and rs1_val == 0x37E0DE00280088DB 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x37e0de00280088db;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x37e0de00280088db, 0x1b, x1, 408, x3)
+
+inst_75:
+// imm_val == 0x07 and rs1_val == 0x1CA7BD1F0D770F3C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1ca7bd1f0d770f3c;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1ca7bd1f0d770f3c, 0x7, x1, 416, x3)
+
+inst_76:
+// imm_val == 0x0F and rs1_val == 0x5536B8D863C2504C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5536b8d863c2504c;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5536b8d863c2504c, 0xf, x1, 424, x3)
+
+inst_77:
+// imm_val == 0x1F and rs1_val == 0x4E6EE408C61B1FBF 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4e6ee408c61b1fbf;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4e6ee408c61b1fbf, 0x1f, x1, 432, x3)
+
+inst_78:
+// rs1_val == 0xC215E193118E5332 and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc215e193118e5332;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc215e193118e5332, 0x2, x1, 440, x3)
+
+inst_79:
+// rs1_val == 0x75EE935F65CB60C1 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x75ee935f65cb60c1;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x75ee935f65cb60c1, 0x5, x1, 448, x3)
+
+inst_80:
+// rs1_val == 0x09C161626CE859BB and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9c161626ce859bb;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9c161626ce859bb, 0x14, x1, 456, x3)
+
+inst_81:
+// rs1_val == 0xA4053175342F57C7 and imm_val == 0x16 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa4053175342f57c7;  immval:0x16
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa4053175342f57c7, 0x16, x1, 464, x3)
+
+inst_82:
+// rs1_val == 0x499006C897933E6F and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x499006c897933e6f;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x499006c897933e6f, 0x1b, x1, 472, x3)
+
+inst_83:
+// rs1_val == 0xC5DD85CA5B064A1F and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc5dd85ca5b064a1f;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc5dd85ca5b064a1f, 0xf, x1, 480, x3)
+
+inst_84:
+// rs1_val == 0x6CC30F7242302B3F and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6cc30f7242302b3f;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6cc30f7242302b3f, 0xf, x1, 488, x3)
+
+inst_85:
+// rs1_val == 0xAF1DBF276CE4747F and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xaf1dbf276ce4747f;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xaf1dbf276ce4747f, 0xd, x1, 496, x3)
+
+inst_86:
+// rs1_val == 0x25784F4FBD0608FF and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x25784f4fbd0608ff;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x25784f4fbd0608ff, 0x10, x1, 504, x3)
+
+inst_87:
+// rs1_val == 0x805A391B604C85FF and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x805a391b604c85ff;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x805a391b604c85ff, 0xa, x1, 512, x3)
+
+inst_88:
+// rs1_val == 0xCC7EB77D4BEB1BFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xcc7eb77d4beb1bff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xcc7eb77d4beb1bff, 0x2, x1, 520, x3)
+
+inst_89:
+// rs1_val == 0xAB647BCA3919F7FF and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xab647bca3919f7ff;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xab647bca3919f7ff, 0xd, x1, 528, x3)
+
+inst_90:
+// rs1_val == 0x7F1E7F8627B22FFF and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7f1e7f8627b22fff;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7f1e7f8627b22fff, 0x1e, x1, 536, x3)
+
+inst_91:
+// rs1_val == 0x51D6D6DA01769FFF and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x51d6d6da01769fff;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x51d6d6da01769fff, 0x15, x1, 544, x3)
+
+inst_92:
+// rs1_val == 0xD5A2038FDA04BFFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd5a2038fda04bfff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd5a2038fda04bfff, 0x2, x1, 552, x3)
+
+inst_93:
+// rs1_val == 0x784ABEBBF03B7FFF and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x784abebbf03b7fff;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x784abebbf03b7fff, 0x17, x1, 560, x3)
+
+inst_94:
+// rs1_val == 0x44D988FBE81EFFFF and imm_val == 0x04 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x44d988fbe81effff;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x44d988fbe81effff, 0x4, x1, 568, x3)
+
+inst_95:
+// rs1_val == 0x6875944E1F19FFFF and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6875944e1f19ffff;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6875944e1f19ffff, 0x13, x1, 576, x3)
+
+inst_96:
+// rs1_val == 0xFF7746E52063FFFF and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xff7746e52063ffff;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xff7746e52063ffff, 0x13, x1, 584, x3)
+
+inst_97:
+// rs1_val == 0x17B8B123A527FFFF and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x17b8b123a527ffff;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x17b8b123a527ffff, 0x0, x1, 592, x3)
+
+inst_98:
+// rs1_val == 0x70890268F88FFFFF and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x70890268f88fffff;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x70890268f88fffff, 0x15, x1, 600, x3)
+
+inst_99:
+// rs1_val == 0x6DDC74E6119FFFFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6ddc74e6119fffff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6ddc74e6119fffff, 0x2, x1, 608, x3)
+
+inst_100:
+// rs1_val == 0x39BE2172E6BFFFFF and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x39be2172e6bfffff;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x39be2172e6bfffff, 0xa, x1, 616, x3)
+
+inst_101:
+// rs1_val == 0xC99324582A7FFFFF and imm_val == 0x07 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc99324582a7fffff;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc99324582a7fffff, 0x7, x1, 624, x3)
+
+inst_102:
+// rs1_val == 0x4B9A6C802EFFFFFF and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4b9a6c802effffff;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4b9a6c802effffff, 0xc, x1, 632, x3)
+
+inst_103:
+// rs1_val == 0x9541240E59FFFFFF and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9541240e59ffffff;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9541240e59ffffff, 0x15, x1, 640, x3)
+
+inst_104:
+// rs1_val == 0xB3A8D61293FFFFFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb3a8d61293ffffff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb3a8d61293ffffff, 0x2, x1, 648, x3)
+
+inst_105:
+// rs1_val == 0x9E03793FD7FFFFFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9e03793fd7ffffff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9e03793fd7ffffff, 0x2, x1, 656, x3)
+
+inst_106:
+// rs1_val == 0x7F1071ECAFFFFFFF and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7f1071ecafffffff;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7f1071ecafffffff, 0xd, x1, 664, x3)
+
+inst_107:
+// rs1_val == 0xF8A75516DFFFFFFF and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf8a75516dfffffff;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf8a75516dfffffff, 0xf, x1, 672, x3)
+
+inst_108:
+// rs1_val == 0xB76D454DBFFFFFFF and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb76d454dbfffffff;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb76d454dbfffffff, 0x8, x1, 680, x3)
+
+inst_109:
+// rs1_val == 0xB494A73D7FFFFFFF and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb494a73d7fffffff;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb494a73d7fffffff, 0x17, x1, 688, x3)
+
+inst_110:
+// rs1_val == 0xC28CB594FFFFFFFF and imm_val == 0x16 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc28cb594ffffffff;  immval:0x16
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc28cb594ffffffff, 0x16, x1, 696, x3)
+
+inst_111:
+// rs1_val == 0x69DA8A2DFFFFFFFF and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x69da8a2dffffffff;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x69da8a2dffffffff, 0x10, x1, 704, x3)
+
+inst_112:
+// rs1_val == 0x40F27003FFFFFFFF and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x40f27003ffffffff;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x40f27003ffffffff, 0xa, x1, 712, x3)
+
+inst_113:
+// rs1_val == 0xB2B8AF97FFFFFFFF and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xb2b8af97ffffffff;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xb2b8af97ffffffff, 0x1c, x1, 720, x3)
+
+inst_114:
+// rs1_val == 0x24496FEFFFFFFFFF and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x24496fefffffffff;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x24496fefffffffff, 0x1f, x1, 728, x3)
+
+inst_115:
+// rs1_val == 0xDE14BFDFFFFFFFFF and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xde14bfdfffffffff;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xde14bfdfffffffff, 0x2, x1, 736, x3)
+
+inst_116:
+// rs1_val == 0x008EEF3FFFFFFFFF and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x8eef3fffffffff;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x8eef3fffffffff, 0x1b, x1, 744, x3)
+
+inst_117:
+// rs1_val == 0x6E2D707FFFFFFFFF and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6e2d707fffffffff;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6e2d707fffffffff, 0x1d, x1, 752, x3)
+
+inst_118:
+// rs1_val == 0x5DCF00FFFFFFFFFF and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5dcf00ffffffffff;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5dcf00ffffffffff, 0x8, x1, 760, x3)
+
+inst_119:
+// rs1_val == 0x3C5569FFFFFFFFFF and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3c5569ffffffffff;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3c5569ffffffffff, 0xc, x1, 768, x3)
+
+inst_120:
+// rs1_val == 0x7DA8D3FFFFFFFFFF and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7da8d3ffffffffff;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7da8d3ffffffffff, 0xf, x1, 776, x3)
+
+inst_121:
+// rs1_val == 0xE3A707FFFFFFFFFF and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe3a707ffffffffff;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe3a707ffffffffff, 0x8, x1, 784, x3)
+
+inst_122:
+// rs1_val == 0x9B01EFFFFFFFFFFF and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9b01efffffffffff;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9b01efffffffffff, 0x11, x1, 792, x3)
+
+inst_123:
+// rs1_val == 0x5F011FFFFFFFFFFF and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5f011fffffffffff;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5f011fffffffffff, 0x1d, x1, 800, x3)
+
+inst_124:
+// rs1_val == 0x2DEDBFFFFFFFFFFF and imm_val == 0x16 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2dedbfffffffffff;  immval:0x16
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2dedbfffffffffff, 0x16, x1, 808, x3)
+
+inst_125:
+// rs1_val == 0x2D377FFFFFFFFFFF and imm_val == 0x12 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2d377fffffffffff;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2d377fffffffffff, 0x12, x1, 816, x3)
+
+inst_126:
+// rs1_val == 0xAD44FFFFFFFFFFFF and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xad44ffffffffffff;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xad44ffffffffffff, 0x1c, x1, 824, x3)
+
+inst_127:
+// rs1_val == 0x72C9FFFFFFFFFFFF and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x72c9ffffffffffff;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x72c9ffffffffffff, 0x8, x1, 832, x3)
+
+inst_128:
+// rs1_val == 0xD1D3FFFFFFFFFFFF and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd1d3ffffffffffff;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd1d3ffffffffffff, 0x10, x1, 840, x3)
+
+inst_129:
+// rs1_val == 0x5057FFFFFFFFFFFF and imm_val == 0x07 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5057ffffffffffff;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5057ffffffffffff, 0x7, x1, 848, x3)
+
+inst_130:
+// rs1_val == 0x5D2FFFFFFFFFFFFF and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5d2fffffffffffff;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5d2fffffffffffff, 0x1b, x1, 856, x3)
+
+inst_131:
+// rs1_val == 0xE5DFFFFFFFFFFFFF and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe5dfffffffffffff;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe5dfffffffffffff, 0x1b, x1, 864, x3)
+
+inst_132:
+// rs1_val == 0xD9BFFFFFFFFFFFFF and imm_val == 0x0E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd9bfffffffffffff;  immval:0xe
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd9bfffffffffffff, 0xe, x1, 872, x3)
+
+inst_133:
+// rs1_val == 0x237FFFFFFFFFFFFF and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x237fffffffffffff;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x237fffffffffffff, 0x10, x1, 880, x3)
+
+inst_134:
+// rs1_val == 0x72FFFFFFFFFFFFFF and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x72ffffffffffffff;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x72ffffffffffffff, 0x1b, x1, 888, x3)
+
+inst_135:
+// rs1_val == 0xDDFFFFFFFFFFFFFF and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xddffffffffffffff;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xddffffffffffffff, 0x10, x1, 896, x3)
+
+inst_136:
+// rs1_val == 0x43FFFFFFFFFFFFFF and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x43ffffffffffffff;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x43ffffffffffffff, 0x9, x1, 904, x3)
+
+inst_137:
+// rs1_val == 0x27FFFFFFFFFFFFFF and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x27ffffffffffffff;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x27ffffffffffffff, 0x0, x1, 912, x3)
+
+inst_138:
+// rs1_val == 0x4FFFFFFFFFFFFFFF and imm_val == 0x01 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4fffffffffffffff;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4fffffffffffffff, 0x1, x1, 920, x3)
+
+inst_139:
+// rs1_val == 0x1FFFFFFFFFFFFFFF and imm_val == 0x0D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1fffffffffffffff;  immval:0xd
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1fffffffffffffff, 0xd, x1, 928, x3)
+
+inst_140:
+// rs1_val == 0x3FFFFFFFFFFFFFFF and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3fffffffffffffff;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3fffffffffffffff, 0xb, x1, 936, x3)
+
+inst_141:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7fffffffffffffff;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7fffffffffffffff, 0x9, x1, 944, x3)
+
+inst_142:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffffff;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffffff, 0xb, x1, 952, x3)
+
+inst_143:
+// imm_val == 0x12 and rs1_val == 0x482EA7602D1EF7BF 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x482ea7602d1ef7bf;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x482ea7602d1ef7bf, 0x12, x1, 960, x3)
+
+inst_144:
+// imm_val == 0x0E and rs1_val == 0x3FC2A9087219C1DA 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3fc2a9087219c1da;  immval:0xe
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3fc2a9087219c1da, 0xe, x1, 968, x3)
+
+inst_145:
+// imm_val == 0x04 and rs1_val == 0x11B41900043E3EF5 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x11b41900043e3ef5;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x11b41900043e3ef5, 0x4, x1, 976, x3)
+
+inst_146:
+// imm_val == 0x03 and rs1_val == 0xEA3A0683EAD81DCD 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xea3a0683ead81dcd;  immval:0x3
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xea3a0683ead81dcd, 0x3, x1, 984, x3)
+
+inst_147:
+// imm_val == 0x01 and rs1_val == 0x12FAD8029D42F670 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x12fad8029d42f670;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x12fad8029d42f670, 0x1, x1, 992, x3)
+
+inst_148:
+// imm_val == 0x00 and rs1_val == 0xFA285A0DB869135C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfa285a0db869135c;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfa285a0db869135c, 0x0, x1, 1000, x3)
+
+inst_149:
+// rs1_val == 0x852395744B1E943F and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x852395744b1e943f;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x852395744b1e943f, 0xb, x1, 1008, x3)
+
+inst_150:
+// rs1_val == 0x6BBA8D2141C9886F and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6bba8d2141c9886f;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6bba8d2141c9886f, 0x1f, x1, 1016, x3)
+
+inst_151:
+// rs1_val == 0x3D65693B3D0840FC and imm_val == 0x19 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3d65693b3d0840fc;  immval:0x19
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3d65693b3d0840fc, 0x19, x1, 1024, x3)
+
+inst_152:
+// rs1_val == 0x19E803191BEA8594 and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x19e803191bea8594;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x19e803191bea8594, 0x10, x1, 1032, x3)
+
+inst_153:
+// rs1_val == 0x0C2282666BE49EE8 and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc2282666be49ee8;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc2282666be49ee8, 0x6, x1, 1040, x3)
+
+inst_154:
+// rs1_val == 0x07862EACE1D73010 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x7862eace1d73010;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x7862eace1d73010, 0x5, x1, 1048, x3)
+
+inst_155:
+// rs1_val == 0x033C1A7FAFDD8734 and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x33c1a7fafdd8734;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x33c1a7fafdd8734, 0x18, x1, 1056, x3)
+
+inst_156:
+// rs1_val == 0x0104A795BD4AEAB1 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x104a795bd4aeab1;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x104a795bd4aeab1, 0xc, x1, 1064, x3)
+
+inst_157:
+// rs1_val == 0x0096C6C8B9B338EC and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x96c6c8b9b338ec;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x96c6c8b9b338ec, 0xa, x1, 1072, x3)
+
+inst_158:
+// rs1_val == 0x00775505E88E7530 and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x775505e88e7530;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x775505e88e7530, 0xf, x1, 1080, x3)
+
+inst_159:
+// rs1_val == 0x00356991A0931ED5 and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x356991a0931ed5;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x356991a0931ed5, 0x13, x1, 1088, x3)
+
+inst_160:
+// rs1_val == 0x00174145DDD4A055 and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x174145ddd4a055;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x174145ddd4a055, 0xb, x1, 1096, x3)
+
+inst_161:
+// rs1_val == 0x000F19FDD5157E9E and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf19fdd5157e9e;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf19fdd5157e9e, 0x8, x1, 1104, x3)
+
+inst_162:
+// rs1_val == 0x0005D99A20918FA8 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5d99a20918fa8;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5d99a20918fa8, 0x1e, x1, 1112, x3)
+
+inst_163:
+// rs1_val == 0x00032C075F27FF09 and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x32c075f27ff09;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x32c075f27ff09, 0x1d, x1, 1120, x3)
+
+inst_164:
+// rs1_val == 0x0001BCE703F8670E and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1bce703f8670e;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1bce703f8670e, 0x17, x1, 1128, x3)
+
+inst_165:
+// rs1_val == 0x00009B8B356F8BD2 and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9b8b356f8bd2;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9b8b356f8bd2, 0xf, x1, 1136, x3)
+
+inst_166:
+// rs1_val == 0x0000545212CA3F71 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x545212ca3f71;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x545212ca3f71, 0x5, x1, 1144, x3)
+
+inst_167:
+// rs1_val == 0x00003090D48DD9F4 and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3090d48dd9f4;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3090d48dd9f4, 0x18, x1, 1152, x3)
+
+inst_168:
+// rs1_val == 0x00001DD8027385CA and imm_val == 0x15 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1dd8027385ca;  immval:0x15
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1dd8027385ca, 0x15, x1, 1160, x3)
+
+inst_169:
+// rs1_val == 0x0000082236971E1C and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x82236971e1c;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x82236971e1c, 0x10, x1, 1168, x3)
+
+inst_170:
+// rs1_val == 0x000004440AC793F6 and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4440ac793f6;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4440ac793f6, 0x9, x1, 1176, x3)
+
+inst_171:
+// rs1_val == 0x000003D5FEEF16EA and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3d5feef16ea;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3d5feef16ea, 0x6, x1, 1184, x3)
+
+inst_172:
+// rs1_val == 0x0000010735F11AF3 and imm_val == 0x19 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x10735f11af3;  immval:0x19
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x10735f11af3, 0x19, x1, 1192, x3)
+
+inst_173:
+// rs1_val == 0x000000ACFF769E38 and imm_val == 0x01 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xacff769e38;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xacff769e38, 0x1, x1, 1200, x3)
+
+inst_174:
+// rs1_val == 0x000000764511488A and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x764511488a;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x764511488a, 0x13, x1, 1208, x3)
+
+inst_175:
+// rs1_val == 0x0000002DFD74106A and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2dfd74106a;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2dfd74106a, 0x0, x1, 1216, x3)
+
+inst_176:
+// rs1_val == 0x000000101DD377C0 and imm_val == 0x1A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x101dd377c0;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x101dd377c0, 0x1a, x1, 1224, x3)
+
+inst_177:
+// rs1_val == 0x0000000A6B52B08E and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa6b52b08e;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa6b52b08e, 0x18, x1, 1232, x3)
+
+inst_178:
+// rs1_val == 0x00000004FC3B66FB and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4fc3b66fb;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4fc3b66fb, 0x8, x1, 1240, x3)
+
+inst_179:
+// rs1_val == 0x00000002728A6FD0 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2728a6fd0;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2728a6fd0, 0xc, x1, 1248, x3)
+
+inst_180:
+// rs1_val == 0x00000001AE9CA08C and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1ae9ca08c;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1ae9ca08c, 0xc, x1, 1256, x3)
+
+inst_181:
+// rs1_val == 0x00000000CC099A1F and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xcc099a1f;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xcc099a1f, 0xb, x1, 1264, x3)
+
+inst_182:
+// rs1_val == 0x0000000042CDF2B0 and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x42cdf2b0;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x42cdf2b0, 0x1d, x1, 1272, x3)
+
+inst_183:
+// rs1_val == 0x000000002274EA19 and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2274ea19;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2274ea19, 0x6, x1, 1280, x3)
+
+inst_184:
+// rs1_val == 0x00000000120EF165 and imm_val == 0x07 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x120ef165;  immval:0x7
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x120ef165, 0x7, x1, 1288, x3)
+
+inst_185:
+// rs1_val == 0x000000000D2454F2 and imm_val == 0x1A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd2454f2;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd2454f2, 0x1a, x1, 1296, x3)
+
+inst_186:
+// rs1_val == 0x00000000063E9BEE and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x63e9bee;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x63e9bee, 0x13, x1, 1304, x3)
+
+inst_187:
+// rs1_val == 0x00000000034C7CD0 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x34c7cd0;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x34c7cd0, 0x11, x1, 1312, x3)
+
+inst_188:
+// rs1_val == 0x0000000001777310 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1777310;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1777310, 0xc, x1, 1320, x3)
+
+inst_189:
+// rs1_val == 0x0000000000D11609 and imm_val == 0x19 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xd11609;  immval:0x19
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xd11609, 0x19, x1, 1328, x3)
+
+inst_190:
+// rs1_val == 0x0000000000680BE0 and imm_val == 0x03 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x680be0;  immval:0x3
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x680be0, 0x3, x1, 1336, x3)
+
+inst_191:
+// rs1_val == 0x0000000000294B16 and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x294b16;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x294b16, 0x0, x1, 1344, x3)
+
+inst_192:
+// rs1_val == 0x0000000000128D1B and imm_val == 0x01 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x128d1b;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x128d1b, 0x1, x1, 1352, x3)
+
+inst_193:
+// rs1_val == 0x0000000000089A12 and imm_val == 0x12 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x89a12;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x89a12, 0x12, x1, 1360, x3)
+
+inst_194:
+// rs1_val == 0x000000000005D25B and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5d25b;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5d25b, 0x6, x1, 1368, x3)
+
+inst_195:
+// rs1_val == 0x000000000003A2C3 and imm_val == 0x12 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3a2c3;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3a2c3, 0x12, x1, 1376, x3)
+
+inst_196:
+// rs1_val == 0x00000000000102FD and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x102fd;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x102fd, 0x14, x1, 1384, x3)
+
+inst_197:
+// rs1_val == 0x000000000000A6B3 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa6b3;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa6b3, 0x5, x1, 1392, x3)
+
+inst_198:
+// rs1_val == 0x0000000000005238 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x5238;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x5238, 0x11, x1, 1400, x3)
+
+inst_199:
+// rs1_val == 0x000000000000222A and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x222a;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x222a, 0x5, x1, 1408, x3)
+
+inst_200:
+// rs1_val == 0x0000000000001161 and imm_val == 0x12 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1161;  immval:0x12
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1161, 0x12, x1, 1416, x3)
+
+inst_201:
+// rs1_val == 0x0000000000000DB9 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xdb9;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xdb9, 0xc, x1, 1424, x3)
+
+inst_202:
+// rs1_val == 0x00000000000004C1 and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x4c1;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x4c1, 0x14, x1, 1432, x3)
+
+inst_203:
+// rs1_val == 0x0000000000000390 and imm_val == 0x01 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x390;  immval:0x1
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x390, 0x1, x1, 1440, x3)
+
+inst_204:
+// rs1_val == 0x00000000000001D4 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1d4;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1d4, 0xc, x1, 1448, x3)
+
+inst_205:
+// rs1_val == 0x00000000000000A7 and imm_val == 0x04 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa7;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa7, 0x4, x1, 1456, x3)
+
+inst_206:
+// rs1_val == 0x0000000000000079 and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x79;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x79, 0xa, x1, 1464, x3)
+
+inst_207:
+// rs1_val == 0x000000000000002C and imm_val == 0x19 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x2c;  immval:0x19
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x2c, 0x19, x1, 1472, x3)
+
+inst_208:
+// rs1_val == 0x000000000000001D and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1d;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1d, 0x2, x1, 1480, x3)
+
+inst_209:
+// rs1_val == 0x000000000000000C and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc, 0x13, x1, 1488, x3)
+
+inst_210:
+// rs1_val == 0x0000000000000006 and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x6;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x6, 0xb, x1, 1496, x3)
+
+inst_211:
+// rs1_val == 0x0000000000000003 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3, 0x1e, x1, 1504, x3)
+
+inst_212:
+// rs1_val == 0x0000000000000001 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1, 0xc, x1, 1512, x3)
+
+inst_213:
+// rs1_val == 0x0000000000000000 and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x0;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x0, 0x1d, x1, 1520, x3)
+
+inst_214:
+// imm_val == 0x06 and rs1_val == 0x976AD220146A3673 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x976ad220146a3673;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x976ad220146a3673, 0x6, x1, 1528, x3)
+
+inst_215:
+// imm_val == 0x14 and rs1_val == 0xFC6113A3312529DC 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfc6113a3312529dc;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfc6113a3312529dc, 0x14, x1, 1536, x3)
+
+inst_216:
+// imm_val == 0x1A and rs1_val == 0x242A809B7A3209FE 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x242a809b7a3209fe;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x242a809b7a3209fe, 0x1a, x1, 1544, x3)
+
+inst_217:
+// imm_val == 0x1D and rs1_val == 0xE380A1764A104E66 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe380a1764a104e66;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe380a1764a104e66, 0x1d, x1, 1552, x3)
+
+inst_218:
+// imm_val == 0x1E and rs1_val == 0xA0E0BD86D4551408 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xa0e0bd86d4551408;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xa0e0bd86d4551408, 0x1e, x1, 1560, x3)
+
+inst_219:
+// imm_val == 0x1F and rs1_val == 0xAFE08A13086C1B78 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xafe08a13086c1b78;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xafe08a13086c1b78, 0x1f, x1, 1568, x3)
+
+inst_220:
+// rs1_val == 0x3CC279B3BD59213F and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x3cc279b3bd59213f;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x3cc279b3bd59213f, 0x14, x1, 1576, x3)
+
+inst_221:
+// rs1_val == 0x941060376C5E1579 and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x941060376c5e1579;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x941060376c5e1579, 0x9, x1, 1584, x3)
+
+inst_222:
+// rs1_val == 0xC9EA3210E5DF7F0B and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xc9ea3210e5df7f0b;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xc9ea3210e5df7f0b, 0x1d, x1, 1592, x3)
+
+inst_223:
+// rs1_val == 0xE9E93D5257DDE0F0 and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xe9e93d5257dde0f0;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xe9e93d5257dde0f0, 0x10, x1, 1600, x3)
+
+inst_224:
+// rs1_val == 0xF048E341C64C47E8 and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf048e341c64c47e8;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf048e341c64c47e8, 0x1c, x1, 1608, x3)
+
+inst_225:
+// rs1_val == 0xF969730123A92480 and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xf969730123a92480;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xf969730123a92480, 0x1b, x1, 1616, x3)
+
+inst_226:
+// rs1_val == 0xFC20CE1CD55D1CE8 and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfc20ce1cd55d1ce8;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfc20ce1cd55d1ce8, 0x1f, x1, 1624, x3)
+
+inst_227:
+// rs1_val == 0xFED775C526EA42ED and imm_val == 0x1D 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfed775c526ea42ed;  immval:0x1d
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfed775c526ea42ed, 0x1d, x1, 1632, x3)
+
+inst_228:
+// rs1_val == 0xFF01DFA30CF25924 and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xff01dfa30cf25924;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xff01dfa30cf25924, 0x5, x1, 1640, x3)
+
+inst_229:
+// rs1_val == 0xFF912F0A7046AB61 and imm_val == 0x04 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xff912f0a7046ab61;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xff912f0a7046ab61, 0x4, x1, 1648, x3)
+
+inst_230:
+// rs1_val == 0xFFCA96C9D43DB43F and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffca96c9d43db43f;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffca96c9d43db43f, 0x0, x1, 1656, x3)
+
+inst_231:
+// rs1_val == 0xFFEB4B49194135A5 and imm_val == 0x1A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffeb4b49194135a5;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffeb4b49194135a5, 0x1a, x1, 1664, x3)
+
+inst_232:
+// rs1_val == 0xFFF1A2ADB3A63FA4 and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfff1a2adb3a63fa4;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfff1a2adb3a63fa4, 0x1c, x1, 1672, x3)
+
+inst_233:
+// rs1_val == 0xFFF8306E89E6156C and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfff8306e89e6156c;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfff8306e89e6156c, 0x1f, x1, 1680, x3)
+
+inst_234:
+// rs1_val == 0xFFFDA6CA22C13476 and imm_val == 0x16 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffda6ca22c13476;  immval:0x16
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffda6ca22c13476, 0x16, x1, 1688, x3)
+
+inst_235:
+// rs1_val == 0xFFFE03B4AC9E9033 and imm_val == 0x19 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffe03b4ac9e9033;  immval:0x19
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffe03b4ac9e9033, 0x19, x1, 1696, x3)
+
+inst_236:
+// rs1_val == 0xFFFF3AD31011EEB5 and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffff3ad31011eeb5;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffff3ad31011eeb5, 0x1f, x1, 1704, x3)
+
+inst_237:
+// rs1_val == 0xFFFF90F48525E8A9 and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffff90f48525e8a9;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffff90f48525e8a9, 0x1f, x1, 1712, x3)
+
+inst_238:
+// rs1_val == 0xFFFFD6E6BC7F85E3 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffd6e6bc7f85e3;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffd6e6bc7f85e3, 0x11, x1, 1720, x3)
+
+inst_239:
+// rs1_val == 0xFFFFE7F6AC60E057 and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffe7f6ac60e057;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffe7f6ac60e057, 0xf, x1, 1728, x3)
+
+inst_240:
+// rs1_val == 0xFFFFF12863FD8180 and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffff12863fd8180;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffff12863fd8180, 0x1f, x1, 1736, x3)
+
+inst_241:
+// rs1_val == 0xFFFFFB5472B3CB0C and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffb5472b3cb0c;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffb5472b3cb0c, 0xa, x1, 1744, x3)
+
+inst_242:
+// rs1_val == 0xFFFFFD8D3E1C8522 and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffd8d3e1c8522;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffd8d3e1c8522, 0x10, x1, 1752, x3)
+
+inst_243:
+// rs1_val == 0xFFFFFE8F54E77CDC and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffe8f54e77cdc;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffe8f54e77cdc, 0x14, x1, 1760, x3)
+
+inst_244:
+// rs1_val == 0xFFFFFF048B7B5379 and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffff048b7b5379;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffff048b7b5379, 0x2, x1, 1768, x3)
+
+inst_245:
+// rs1_val == 0xFFFFFF856F4930C9 and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffff856f4930c9;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffff856f4930c9, 0x0, x1, 1776, x3)
+
+inst_246:
+// rs1_val == 0xFFFFFFDCC5D97467 and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffdcc5d97467;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffdcc5d97467, 0x14, x1, 1784, x3)
+
+inst_247:
+// rs1_val == 0xFFFFFFE5C70AFC93 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffe5c70afc93;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffe5c70afc93, 0x1e, x1, 1792, x3)
+
+inst_248:
+// rs1_val == 0xFFFFFFF6A911655F and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffff6a911655f;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffff6a911655f, 0xb, x1, 1800, x3)
+
+inst_249:
+// rs1_val == 0xFFFFFFF974AB0A39 and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffff974ab0a39;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffff974ab0a39, 0xa, x1, 1808, x3)
+
+inst_250:
+// rs1_val == 0xFFFFFFFCDD68F202 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffcdd68f202;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffcdd68f202, 0x11, x1, 1816, x3)
+
+inst_251:
+// rs1_val == 0xFFFFFFFE24BD4821 and imm_val == 0x0B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffe24bd4821;  immval:0xb
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffe24bd4821, 0xb, x1, 1824, x3)
+
+inst_252:
+// rs1_val == 0xFFFFFFFF3ED7E667 and imm_val == 0x11 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffff3ed7e667;  immval:0x11
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffff3ed7e667, 0x11, x1, 1832, x3)
+
+inst_253:
+// rs1_val == 0xFFFFFFFFB871CFDF and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffb871cfdf;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffb871cfdf, 0x1c, x1, 1840, x3)
+
+inst_254:
+// rs1_val == 0xFFFFFFFFD29C11AE and imm_val == 0x1B 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffd29c11ae;  immval:0x1b
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffd29c11ae, 0x1b, x1, 1848, x3)
+
+inst_255:
+// rs1_val == 0xFFFFFFFFE109799A and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffe109799a;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffe109799a, 0xc, x1, 1856, x3)
+
+inst_256:
+// rs1_val == 0xFFFFFFFFF4E80B13 and imm_val == 0x06 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffff4e80b13;  immval:0x6
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffff4e80b13, 0x6, x1, 1864, x3)
+
+inst_257:
+// rs1_val == 0xFFFFFFFFF9B7EA62 and imm_val == 0x09 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffff9b7ea62;  immval:0x9
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffff9b7ea62, 0x9, x1, 1872, x3)
+
+inst_258:
+// rs1_val == 0xFFFFFFFFFC51F638 and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffc51f638;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffc51f638, 0x17, x1, 1880, x3)
+
+inst_259:
+// rs1_val == 0xFFFFFFFFFE9263CF and imm_val == 0x05 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffe9263cf;  immval:0x5
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffe9263cf, 0x5, x1, 1888, x3)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFF216823 and imm_val == 0x04 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffff216823;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffff216823, 0x4, x1, 1896, x3)
+
+inst_261:
+// rs1_val == 0xFFFFFFFFFF861438 and imm_val == 0x02 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffff861438;  immval:0x2
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffff861438, 0x2, x1, 1904, x3)
+
+inst_262:
+// rs1_val == 0xFFFFFFFFFFD8C9D0 and imm_val == 0x1A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffd8c9d0;  immval:0x1a
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffd8c9d0, 0x1a, x1, 1912, x3)
+
+inst_263:
+// rs1_val == 0xFFFFFFFFFFE4D576 and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffe4d576;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffe4d576, 0xa, x1, 1920, x3)
+
+inst_264:
+// rs1_val == 0xFFFFFFFFFFF18C67 and imm_val == 0x14 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffff18c67;  immval:0x14
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffff18c67, 0x14, x1, 1928, x3)
+
+inst_265:
+// rs1_val == 0xFFFFFFFFFFFBB998 and imm_val == 0x04 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffbb998;  immval:0x4
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffbb998, 0x4, x1, 1936, x3)
+
+inst_266:
+// rs1_val == 0xFFFFFFFFFFFC2561 and imm_val == 0x1C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffc2561;  immval:0x1c
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffc2561, 0x1c, x1, 1944, x3)
+
+inst_267:
+// rs1_val == 0xFFFFFFFFFFFEEAB5 and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffeeab5;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffeeab5, 0xf, x1, 1952, x3)
+
+inst_268:
+// rs1_val == 0xFFFFFFFFFFFF0651 and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffff0651;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffff0651, 0x13, x1, 1960, x3)
+
+inst_269:
+// rs1_val == 0xFFFFFFFFFFFF90E4 and imm_val == 0x0C 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffff90e4;  immval:0xc
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffff90e4, 0xc, x1, 1968, x3)
+
+inst_270:
+// rs1_val == 0xFFFFFFFFFFFFCA23 and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffca23;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffca23, 0x0, x1, 1976, x3)
+
+inst_271:
+// rs1_val == 0xFFFFFFFFFFFFE2A0 and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffe2a0;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffe2a0, 0x18, x1, 1984, x3)
+
+inst_272:
+// rs1_val == 0xFFFFFFFFFFFFF2CC and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffff2cc;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffff2cc, 0xf, x1, 1992, x3)
+
+inst_273:
+// rs1_val == 0xFFFFFFFFFFFFFAB4 and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffab4;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffab4, 0x8, x1, 2000, x3)
+
+inst_274:
+// rs1_val == 0xFFFFFFFFFFFFFCEE and imm_val == 0x13 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffcee;  immval:0x13
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffcee, 0x13, x1, 2008, x3)
+
+inst_275:
+// rs1_val == 0xFFFFFFFFFFFFFE04 and imm_val == 0x10 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffe04;  immval:0x10
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffe04, 0x10, x1, 2016, x3)
+
+inst_276:
+// rs1_val == 0xFFFFFFFFFFFFFF2A and imm_val == 0x18 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffff2a;  immval:0x18
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffff2a, 0x18, x1, 2024, x3)
+
+inst_277:
+// rs1_val == 0xFFFFFFFFFFFFFF9D and imm_val == 0x08 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffff9d;  immval:0x8
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffff9d, 0x8, x1, 2032, x3)
+
+inst_278:
+// rs1_val == 0xFFFFFFFFFFFFFFC7 and imm_val == 0x17 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffffc7;  immval:0x17
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffffc7, 0x17, x1, 2040, x3)
+RVTEST_SIGBASE( x1,signature_x1_1)
+
+inst_279:
+// rs1_val == 0xFFFFFFFFFFFFFFE4 and imm_val == 0x0F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xffffffffffffffe4;  immval:0xf
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xffffffffffffffe4, 0xf, x1, 0, x3)
+
+inst_280:
+// rs1_val == 0xFFFFFFFFFFFFFFF2 and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffff2;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffff2, 0x1f, x1, 8, x3)
+
+inst_281:
+// rs1_val == 0xFFFFFFFFFFFFFFF8 and imm_val == 0x0A 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffff8;  immval:0xa
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffff8, 0xa, x1, 16, x3)
+
+inst_282:
+// rs1_val == 0xFFFFFFFFFFFFFFFD and imm_val == 0x1F 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;  immval:0x1f
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffffd, 0x1f, x1, 24, x3)
+
+inst_283:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0xfffffffffffffffe, 0x0, x1, 32, x3)
+
+inst_284:
+// rs1_val == 0x1E20000000000000 and imm_val == 0x1E 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x1e20000000000000;  immval:0x1e
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x1e20000000000000, 0x1e, x1, 40, x3)
+
+inst_285:
+// rs1_val == 0x9568400000000000 and imm_val == 0x00 
+// opcode: roriw ; op1:x10; dest:x11; op1val:0x9568400000000000;  immval:0x0
+TEST_IMM_OP( roriw, x11, x10, 0x0000000000000000, 0x9568400000000000, 0x0, x1, 48, x3)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x18_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x18_1:
+    .fill 23*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 7*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S
new file mode 100644
index 000000000..c38ced3ae
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/rorw-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the rorw instruction of the RISC-V  extension for the rorw covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",rorw)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",rorw)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",rorw)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKb.*);def TEST_CASE_1=True;",rorw)
+
+RVTEST_SIGBASE( x5,signature_x5_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x31, rs2==x31, rd==x24, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rorw ; op1:x31; op2:x31; dest:x24; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(rorw, x24, x31, x31, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x5, 0, x12)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x27, rs2==x27, rd==x27, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rorw ; op1:x27; op2:x27; dest:x27; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(rorw, x27, x27, x27, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x5, 8, x12)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x10, rs2==x22, rd==x15, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: rorw ; op1:x10; op2:x22; dest:x15; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(rorw, x15, x10, x22, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x5, 16, x12)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x7, rs2==x28, rd==x7, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: rorw ; op1:x7; op2:x28; dest:x7; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(rorw, x7, x7, x28, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x5, 24, x12)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x30, rs2==x4, rd==x4, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: rorw ; op1:x30; op2:x4; dest:x4; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(rorw, x4, x30, x4, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x5, 32, x12)
+
+inst_5:
+// rs1==x22, rs2==x21, rd==x29, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: rorw ; op1:x22; op2:x21; dest:x29; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(rorw, x29, x22, x21, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x5, 40, x12)
+
+inst_6:
+// rs1==x8, rs2==x19, rd==x13, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: rorw ; op1:x8; op2:x19; dest:x13; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(rorw, x13, x8, x19, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x5, 48, x12)
+
+inst_7:
+// rs1==x26, rs2==x0, rd==x28, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: rorw ; op1:x26; op2:x0; dest:x28; op1val:0x2405b307cec7313a;  op2val:0x0
+TEST_RR_OP(rorw, x28, x26, x0, 0x0000000000000000, 0x2405b307cec7313a, 0x0, x5, 56, x12)
+
+inst_8:
+// rs1==x21, rs2==x1, rd==x10, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: rorw ; op1:x21; op2:x1; dest:x10; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(rorw, x10, x21, x1, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x5, 64, x12)
+
+inst_9:
+// rs1==x15, rs2==x10, rd==x26, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: rorw ; op1:x15; op2:x10; dest:x26; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(rorw, x26, x15, x10, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x5, 72, x12)
+
+inst_10:
+// rs1==x9, rs2==x30, rd==x25, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: rorw ; op1:x9; op2:x30; dest:x25; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(rorw, x25, x9, x30, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x5, 80, x12)
+
+inst_11:
+// rs1==x4, rs2==x11, rd==x2, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: rorw ; op1:x4; op2:x11; dest:x2; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(rorw, x2, x4, x11, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x5, 88, x12)
+
+inst_12:
+// rs1==x3, rs2==x14, rd==x30, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: rorw ; op1:x3; op2:x14; dest:x30; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(rorw, x30, x3, x14, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x5, 96, x12)
+
+inst_13:
+// rs1==x6, rs2==x13, rd==x18, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: rorw ; op1:x6; op2:x13; dest:x18; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(rorw, x18, x6, x13, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x5, 104, x12)
+
+inst_14:
+// rs1==x19, rs2==x16, rd==x31, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: rorw ; op1:x19; op2:x16; dest:x31; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(rorw, x31, x19, x16, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x5, 112, x12)
+
+inst_15:
+// rs1==x25, rs2==x7, rd==x17, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: rorw ; op1:x25; op2:x7; dest:x17; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(rorw, x17, x25, x7, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x5, 120, x12)
+
+inst_16:
+// rs1==x14, rs2==x2, rd==x0, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: rorw ; op1:x14; op2:x2; dest:x0; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(rorw, x0, x14, x2, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x5, 128, x7)
+
+inst_17:
+// rs1==x28, rs2==x8, rd==x21, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: rorw ; op1:x28; op2:x8; dest:x21; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(rorw, x21, x28, x8, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x5, 136, x7)
+
+inst_18:
+// rs1==x24, rs2==x29, rd==x6, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: rorw ; op1:x24; op2:x29; dest:x6; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(rorw, x6, x24, x29, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x5, 144, x7)
+
+inst_19:
+// rs1==x13, rs2==x15, rd==x16, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: rorw ; op1:x13; op2:x15; dest:x16; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(rorw, x16, x13, x15, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x5, 152, x7)
+
+inst_20:
+// rs1==x20, rs2==x26, rd==x11, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: rorw ; op1:x20; op2:x26; dest:x11; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(rorw, x11, x20, x26, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x5, 160, x7)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_21:
+// rs1==x23, rs2==x5, rd==x1, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: rorw ; op1:x23; op2:x5; dest:x1; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(rorw, x1, x23, x5, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x4, 0, x7)
+
+inst_22:
+// rs1==x1, rs2==x6, rd==x22, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: rorw ; op1:x1; op2:x6; dest:x22; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(rorw, x22, x1, x6, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x4, 8, x7)
+
+inst_23:
+// rs1==x2, rs2==x12, rd==x3, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: rorw ; op1:x2; op2:x12; dest:x3; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(rorw, x3, x2, x12, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x4, 16, x7)
+
+inst_24:
+// rs1==x5, rs2==x9, rd==x12, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: rorw ; op1:x5; op2:x9; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(rorw, x12, x5, x9, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x4, 24, x7)
+
+inst_25:
+// rs1==x12, rs2==x18, rd==x5, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: rorw ; op1:x12; op2:x18; dest:x5; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(rorw, x5, x12, x18, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x4, 32, x7)
+
+inst_26:
+// rs1==x18, rs2==x23, rd==x19, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: rorw ; op1:x18; op2:x23; dest:x19; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(rorw, x19, x18, x23, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x4, 40, x7)
+
+inst_27:
+// rs1==x0, rs2==x20, rd==x9, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: rorw ; op1:x0; op2:x20; dest:x9; op1val:0x0;  op2val:0xfa56aa4000000000
+TEST_RR_OP(rorw, x9, x0, x20, 0x0000000000000000, 0x0, 0xfa56aa4000000000, x4, 48, x7)
+
+inst_28:
+// rs1==x16, rs2==x17, rd==x8, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: rorw ; op1:x16; op2:x17; dest:x8; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(rorw, x8, x16, x17, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x4, 56, x7)
+
+inst_29:
+// rs1==x11, rs2==x24, rd==x14, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: rorw ; op1:x11; op2:x24; dest:x14; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(rorw, x14, x11, x24, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x4, 64, x7)
+
+inst_30:
+// rs1==x17, rs2==x25, rd==x23, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: rorw ; op1:x17; op2:x25; dest:x23; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(rorw, x23, x17, x25, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x4, 72, x7)
+
+inst_31:
+// rs1==x29, rs2==x3, rd==x20, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: rorw ; op1:x29; op2:x3; dest:x20; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(rorw, x20, x29, x3, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x4, 80, x7)
+
+inst_32:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x4, 88, x7)
+
+inst_33:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x4, 96, x7)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x4, 104, x7)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x4, 112, x7)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x4, 120, x7)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x4, 128, x7)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x4, 136, x7)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x4, 144, x7)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x4, 152, x7)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x4, 160, x7)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x4, 168, x7)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x4, 176, x7)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x4, 184, x7)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x4, 192, x7)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x4, 200, x7)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x4, 208, x7)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x4, 216, x7)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x4, 224, x7)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x4, 232, x7)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x4, 240, x7)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x4, 248, x7)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x4, 256, x7)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x4, 264, x7)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x4, 272, x7)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x4, 280, x7)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x4, 288, x7)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x4, 296, x7)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x4, 304, x7)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x4, 312, x7)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x4, 320, x7)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x4, 328, x7)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x4, 336, x7)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x4, 344, x7)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x4, 352, x7)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x4, 360, x7)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x4, 368, x7)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x4, 376, x7)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x4, 384, x7)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x4, 392, x7)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x4, 400, x7)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x4, 408, x7)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x4, 416, x7)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x4, 424, x7)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x4, 432, x7)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x4, 440, x7)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x4, 448, x7)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x4, 456, x7)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x4, 464, x7)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x4, 472, x7)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x4, 480, x7)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x4, 488, x7)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x4, 496, x7)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x4, 504, x7)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x4, 512, x7)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x4, 520, x7)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x4, 528, x7)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x4, 536, x7)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x4, 544, x7)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x4, 552, x7)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x4, 560, x7)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x4, 568, x7)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x4, 576, x7)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x4, 584, x7)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x4, 592, x7)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x4, 600, x7)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x4, 608, x7)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x4, 616, x7)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x4, 624, x7)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x4, 632, x7)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x4, 640, x7)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x4, 648, x7)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x4, 656, x7)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x4, 664, x7)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x4, 672, x7)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x4, 680, x7)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x4, 688, x7)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x4, 696, x7)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x4, 704, x7)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x4, 712, x7)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x4, 720, x7)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x4, 728, x7)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x4, 736, x7)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x4, 744, x7)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x4, 752, x7)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x4, 760, x7)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x4, 768, x7)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x4, 776, x7)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x4, 784, x7)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x4, 792, x7)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x4, 800, x7)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x4, 808, x7)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x4, 816, x7)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x4, 824, x7)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x4, 832, x7)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x4, 840, x7)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x4, 848, x7)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x4, 856, x7)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x4, 864, x7)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x4, 872, x7)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x4, 880, x7)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x4, 888, x7)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x4, 896, x7)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x4, 904, x7)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x4, 912, x7)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x4, 920, x7)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x4, 928, x7)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x4, 936, x7)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x4, 944, x7)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x4, 952, x7)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x4, 960, x7)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x4, 968, x7)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x4, 976, x7)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x4, 984, x7)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x4, 992, x7)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x4, 1000, x7)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x4, 1008, x7)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x4, 1016, x7)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x4, 1024, x7)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x4, 1032, x7)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x4, 1040, x7)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x4, 1048, x7)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x4, 1056, x7)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x4, 1064, x7)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x4, 1072, x7)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x4, 1080, x7)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x4, 1088, x7)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x4, 1096, x7)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x4, 1104, x7)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x4, 1112, x7)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x4, 1120, x7)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x4, 1128, x7)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x4, 1136, x7)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x4, 1144, x7)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x4, 1152, x7)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x4, 1160, x7)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x4, 1168, x7)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x4, 1176, x7)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x4, 1184, x7)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x4, 1192, x7)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x4, 1200, x7)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x4, 1208, x7)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x4, 1216, x7)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x4, 1224, x7)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x4, 1232, x7)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x4, 1240, x7)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x4, 1248, x7)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x4, 1256, x7)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x4, 1264, x7)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x4, 1272, x7)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x4, 1280, x7)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x4, 1288, x7)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x4, 1296, x7)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x4, 1304, x7)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x4, 1312, x7)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x4, 1320, x7)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x4, 1328, x7)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x4, 1336, x7)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x4, 1344, x7)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x4, 1352, x7)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x4, 1360, x7)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x4, 1368, x7)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x4, 1376, x7)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x4, 1384, x7)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x4, 1392, x7)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x4, 1400, x7)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x4, 1408, x7)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x4, 1416, x7)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x4, 1424, x7)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x4, 1432, x7)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x4, 1440, x7)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x4, 1448, x7)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x4, 1456, x7)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x4, 1464, x7)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x4, 1472, x7)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x4, 1480, x7)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x4, 1488, x7)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x4, 1496, x7)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x4, 1504, x7)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x4, 1512, x7)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x4, 1520, x7)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x4, 1528, x7)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x4, 1536, x7)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x4, 1544, x7)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x4, 1552, x7)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x4, 1560, x7)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x4, 1568, x7)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x4, 1576, x7)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x4, 1584, x7)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x4, 1592, x7)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x4, 1600, x7)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x4, 1608, x7)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x4, 1616, x7)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x4, 1624, x7)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x4, 1632, x7)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x4, 1640, x7)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x4, 1648, x7)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x4, 1656, x7)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x4, 1664, x7)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x4, 1672, x7)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x4, 1680, x7)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x4, 1688, x7)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x4, 1696, x7)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x4, 1704, x7)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x4, 1712, x7)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x4, 1720, x7)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x4, 1728, x7)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x4, 1736, x7)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x4, 1744, x7)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x4, 1752, x7)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x4, 1760, x7)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x4, 1768, x7)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x4, 1776, x7)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x4, 1784, x7)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x4, 1792, x7)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x4, 1800, x7)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x4, 1808, x7)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x4, 1816, x7)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x4, 1824, x7)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x4, 1832, x7)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x4, 1840, x7)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x4, 1848, x7)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x4, 1856, x7)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x4, 1864, x7)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x4, 1872, x7)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x4, 1880, x7)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x4, 1888, x7)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x4, 1896, x7)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x4, 1904, x7)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x4, 1912, x7)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x4, 1920, x7)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x4, 1928, x7)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x4, 1936, x7)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x4, 1944, x7)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x4, 1952, x7)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x4, 1960, x7)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x4, 1968, x7)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x4, 1976, x7)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x4, 1984, x7)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x4, 1992, x7)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x4, 2000, x7)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x4, 2008, x7)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x4, 2016, x7)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x4, 2024, x7)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x4, 2032, x7)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x4, 2040, x7)
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x4, 0, x7)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x4, 8, x7)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x4, 16, x7)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x4, 24, x7)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x4, 32, x7)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x4, 40, x7)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x4, 48, x7)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x4, 56, x7)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x4, 64, x7)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x4, 72, x7)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x4, 80, x7)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x4, 88, x7)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x4, 96, x7)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x4, 104, x7)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x4, 112, x7)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x4, 120, x7)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x4, 128, x7)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x4, 136, x7)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x4, 144, x7)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x4, 152, x7)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x4, 160, x7)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x4, 168, x7)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x4, 176, x7)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x4, 184, x7)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x4, 192, x7)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x4, 200, x7)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x4, 208, x7)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x4, 216, x7)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x4, 224, x7)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x4, 232, x7)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x4, 240, x7)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x4, 248, x7)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x4, 256, x7)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x4, 264, x7)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x4, 272, x7)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x4, 280, x7)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x4, 288, x7)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x4, 296, x7)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x4, 304, x7)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x4, 312, x7)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x4, 320, x7)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x4, 328, x7)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x4, 336, x7)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x4, 344, x7)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x4, 352, x7)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x4, 360, x7)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x4, 368, x7)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x4, 376, x7)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x4, 384, x7)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x4, 392, x7)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x4, 400, x7)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x4, 408, x7)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x4, 416, x7)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x4, 424, x7)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x4, 432, x7)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x4, 440, x7)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x4, 448, x7)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x4, 456, x7)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x4, 464, x7)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x4, 472, x7)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x4, 480, x7)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x4, 488, x7)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x4, 496, x7)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x4, 504, x7)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x4, 512, x7)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x4, 520, x7)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x4, 528, x7)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x4, 536, x7)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x4, 544, x7)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x4, 552, x7)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x4, 560, x7)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x4, 568, x7)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x4, 576, x7)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x4, 584, x7)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x4, 592, x7)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x4, 600, x7)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x4, 608, x7)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x4, 616, x7)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x4, 624, x7)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x4, 632, x7)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x4, 640, x7)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x4, 648, x7)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x4, 656, x7)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x4, 664, x7)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x4, 672, x7)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x4, 680, x7)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x4, 688, x7)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x4, 696, x7)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x4, 704, x7)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x4, 712, x7)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x4, 720, x7)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x4, 728, x7)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x4, 736, x7)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x4, 744, x7)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x4, 752, x7)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x4, 760, x7)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x4, 768, x7)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x4, 776, x7)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x4, 784, x7)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x4, 792, x7)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x4, 800, x7)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x4, 808, x7)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x4, 816, x7)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x4, 824, x7)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x4, 832, x7)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x4, 840, x7)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x4, 848, x7)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x4, 856, x7)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x4, 864, x7)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x4, 872, x7)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x4, 880, x7)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x4, 888, x7)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x4, 896, x7)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x4, 904, x7)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x4, 912, x7)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x4, 920, x7)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x4, 928, x7)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x4, 936, x7)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x4, 944, x7)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x4, 952, x7)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x4, 960, x7)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x4, 968, x7)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x4, 976, x7)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x4, 984, x7)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x4, 992, x7)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x4, 1000, x7)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x4, 1008, x7)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x4, 1016, x7)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x4, 1024, x7)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x4, 1032, x7)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x4, 1040, x7)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x4, 1048, x7)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x4, 1056, x7)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x4, 1064, x7)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x4, 1072, x7)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x4, 1080, x7)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x4, 1088, x7)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x4, 1096, x7)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x4, 1104, x7)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x4, 1112, x7)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x4, 1120, x7)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x4, 1128, x7)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x4, 1136, x7)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x4, 1144, x7)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x4, 1152, x7)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x4, 1160, x7)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x4, 1168, x7)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x4, 1176, x7)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x4, 1184, x7)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x4, 1192, x7)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x4, 1200, x7)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x4, 1208, x7)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x4, 1216, x7)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x4, 1224, x7)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x4, 1232, x7)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x4, 1240, x7)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x4, 1248, x7)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x4, 1256, x7)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x4, 1264, x7)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x4, 1272, x7)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x4, 1280, x7)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x4, 1288, x7)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x4, 1296, x7)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x4, 1304, x7)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x4, 1312, x7)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x4, 1320, x7)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x4, 1328, x7)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x4, 1336, x7)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x4, 1344, x7)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x4, 1352, x7)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x4, 1360, x7)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x4, 1368, x7)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x4, 1376, x7)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x4, 1384, x7)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x4, 1392, x7)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x4, 1400, x7)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x4, 1408, x7)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x4, 1416, x7)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x4, 1424, x7)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x4, 1432, x7)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x4, 1440, x7)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x4, 1448, x7)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x4, 1456, x7)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x4, 1464, x7)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x4, 1472, x7)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x4, 1480, x7)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x4, 1488, x7)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x4, 1496, x7)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x4, 1504, x7)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x4, 1512, x7)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x4, 1520, x7)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x4, 1528, x7)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x4, 1536, x7)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x4, 1544, x7)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x4, 1552, x7)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x4, 1560, x7)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x4, 1568, x7)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x4, 1576, x7)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x4, 1584, x7)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x4, 1592, x7)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x4, 1600, x7)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x4, 1608, x7)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x4, 1616, x7)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x4, 1624, x7)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x4, 1632, x7)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x4, 1640, x7)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x4, 1648, x7)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x4, 1656, x7)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x4, 1664, x7)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x4, 1672, x7)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x4, 1680, x7)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x4, 1688, x7)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x4, 1696, x7)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x4, 1704, x7)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x4, 1712, x7)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x4, 1720, x7)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x4, 1728, x7)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x4, 1736, x7)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x4, 1744, x7)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x4, 1752, x7)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x4, 1760, x7)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x4, 1768, x7)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x4, 1776, x7)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x4, 1784, x7)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x4, 1792, x7)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x4, 1800, x7)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x4, 1808, x7)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x4, 1816, x7)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x4, 1824, x7)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x4, 1832, x7)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x4, 1840, x7)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x4, 1848, x7)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x4, 1856, x7)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x4, 1864, x7)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x4, 1872, x7)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x4, 1880, x7)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x4, 1888, x7)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x4, 1896, x7)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x4, 1904, x7)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x4, 1912, x7)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x4, 1920, x7)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x4, 1928, x7)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x4, 1936, x7)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x4, 1944, x7)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x4, 1952, x7)
+
+inst_522:
+// rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x4, 1960, x7)
+
+inst_523:
+// rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x4, 1968, x7)
+
+inst_524:
+// rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: rorw ; op1:x10; op2:x11; dest:x12; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(rorw, x12, x10, x11, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x4, 1976, x7)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x5_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x5_1:
+    .fill 21*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 248*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S
new file mode 100644
index 000000000..36a20d1fb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha256sig0 instruction of the RISC-V  extension for the sha256sig0 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKnh.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_SIGBASE( x7,signature_x7_1)
+
+inst_0:
+// rs1 != rd, rs1==x4, rd==x16, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha256sig0 ; op1:x4; dest:x16; op1val:0x75a3adb3254a9493;
+li x4, 0x75a3adb3254a9493
+sha256sig0 x16, x4
+sw x16, 0(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x16, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x28, rd==x28, rs1_val == 9223372036854775807, 
+// opcode: sha256sig0 ; op1:x28; dest:x28; op1val:0x7fffffffffffffff;
+li x28, 0x7fffffffffffffff
+sha256sig0 x28, x28
+sw x28, 8(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x28, 0x0000000000000000)
+
+inst_2:
+// rs1==x31, rd==x25, rs1_val == 13835058055282163711, 
+// opcode: sha256sig0 ; op1:x31; dest:x25; op1val:0xbfffffffffffffff;
+li x31, 0xbfffffffffffffff
+sha256sig0 x25, x31
+sw x25, 16(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x25, 0x0000000000000000)
+
+inst_3:
+// rs1==x14, rd==x21, rs1_val == 16140901064495857663, 
+// opcode: sha256sig0 ; op1:x14; dest:x21; op1val:0xdfffffffffffffff;
+li x14, 0xdfffffffffffffff
+sha256sig0 x21, x14
+sw x21, 24(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x21, 0x0000000000000000)
+
+inst_4:
+// rs1==x21, rd==x27, rs1_val == 17293822569102704639, 
+// opcode: sha256sig0 ; op1:x21; dest:x27; op1val:0xefffffffffffffff;
+li x21, 0xefffffffffffffff
+sha256sig0 x27, x21
+sw x27, 32(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x27, 0x0000000000000000)
+
+inst_5:
+// rs1==x16, rd==x23, rs1_val == 17870283321406128127, 
+// opcode: sha256sig0 ; op1:x16; dest:x23; op1val:0xf7ffffffffffffff;
+li x16, 0xf7ffffffffffffff
+sha256sig0 x23, x16
+sw x23, 40(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x23, 0x0000000000000000)
+
+inst_6:
+// rs1==x5, rd==x17, rs1_val == 18158513697557839871, 
+// opcode: sha256sig0 ; op1:x5; dest:x17; op1val:0xfbffffffffffffff;
+li x5, 0xfbffffffffffffff
+sha256sig0 x17, x5
+sw x17, 48(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x17, 0x0000000000000000)
+
+inst_7:
+// rs1==x18, rd==x12, rs1_val == 18302628885633695743, 
+// opcode: sha256sig0 ; op1:x18; dest:x12; op1val:0xfdffffffffffffff;
+li x18, 0xfdffffffffffffff
+sha256sig0 x12, x18
+sw x12, 56(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x12, 0x0000000000000000)
+
+inst_8:
+// rs1==x12, rd==x9, rs1_val == 18374686479671623679, 
+// opcode: sha256sig0 ; op1:x12; dest:x9; op1val:0xfeffffffffffffff;
+li x12, 0xfeffffffffffffff
+sha256sig0 x9, x12
+sw x9, 64(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x9, 0x0000000000000000)
+
+inst_9:
+// rs1==x2, rd==x1, rs1_val == 18410715276690587647, 
+// opcode: sha256sig0 ; op1:x2; dest:x1; op1val:0xff7fffffffffffff;
+li x2, 0xff7fffffffffffff
+sha256sig0 x1, x2
+sw x1, 72(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x1, 0x0000000000000000)
+
+inst_10:
+// rs1==x10, rd==x0, rs1_val == 18428729675200069631, 
+// opcode: sha256sig0 ; op1:x10; dest:x0; op1val:0xffbfffffffffffff;
+li x10, 0xffbfffffffffffff
+sha256sig0 x0, x10
+sw x0, 80(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x0, 0x0000000000000000)
+
+inst_11:
+// rs1==x9, rd==x31, rs1_val == 18437736874454810623, 
+// opcode: sha256sig0 ; op1:x9; dest:x31; op1val:0xffdfffffffffffff;
+li x9, 0xffdfffffffffffff
+sha256sig0 x31, x9
+sw x31, 88(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x31, 0x0000000000000000)
+
+inst_12:
+// rs1==x13, rd==x11, rs1_val == 18442240474082181119, 
+// opcode: sha256sig0 ; op1:x13; dest:x11; op1val:0xffefffffffffffff;
+li x13, 0xffefffffffffffff
+sha256sig0 x11, x13
+sw x11, 96(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_13:
+// rs1==x15, rd==x3, rs1_val == 18444492273895866367, 
+// opcode: sha256sig0 ; op1:x15; dest:x3; op1val:0xfff7ffffffffffff;
+li x15, 0xfff7ffffffffffff
+sha256sig0 x3, x15
+sw x3, 104(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x3, 0x0000000000000000)
+
+inst_14:
+// rs1==x23, rd==x19, rs1_val == 18445618173802708991, 
+// opcode: sha256sig0 ; op1:x23; dest:x19; op1val:0xfffbffffffffffff;
+li x23, 0xfffbffffffffffff
+sha256sig0 x19, x23
+sw x19, 112(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x19, 0x0000000000000000)
+
+inst_15:
+// rs1==x24, rd==x30, rs1_val == 18446181123756130303, 
+// opcode: sha256sig0 ; op1:x24; dest:x30; op1val:0xfffdffffffffffff;
+li x24, 0xfffdffffffffffff
+sha256sig0 x30, x24
+sw x30, 120(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x30, 0x0000000000000000)
+
+inst_16:
+// rs1==x3, rd==x20, rs1_val == 18446462598732840959, 
+// opcode: sha256sig0 ; op1:x3; dest:x20; op1val:0xfffeffffffffffff;
+li x3, 0xfffeffffffffffff
+sha256sig0 x20, x3
+sw x20, 128(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x20, 0x0000000000000000)
+
+inst_17:
+// rs1==x29, rd==x15, rs1_val == 18446603336221196287, 
+// opcode: sha256sig0 ; op1:x29; dest:x15; op1val:0xffff7fffffffffff;
+li x29, 0xffff7fffffffffff
+sha256sig0 x15, x29
+sw x15, 136(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x15, 0x0000000000000000)
+
+inst_18:
+// rs1==x1, rd==x24, rs1_val == 18446673704965373951, 
+// opcode: sha256sig0 ; op1:x1; dest:x24; op1val:0xffffbfffffffffff;
+li x1, 0xffffbfffffffffff
+sha256sig0 x24, x1
+sw x24, 144(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x24, 0x0000000000000000)
+
+inst_19:
+// rs1==x26, rd==x6, rs1_val == 18446708889337462783, 
+// opcode: sha256sig0 ; op1:x26; dest:x6; op1val:0xffffdfffffffffff;
+li x26, 0xffffdfffffffffff
+sha256sig0 x6, x26
+sw x6, 152(x7)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x6, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_20:
+// rs1==x19, rd==x10, rs1_val == 18446726481523507199, 
+// opcode: sha256sig0 ; op1:x19; dest:x10; op1val:0xffffefffffffffff;
+li x19, 0xffffefffffffffff
+sha256sig0 x10, x19
+sw x10, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x10, 0x0000000000000000)
+
+inst_21:
+// rs1==x22, rd==x8, rs1_val == 18446735277616529407, 
+// opcode: sha256sig0 ; op1:x22; dest:x8; op1val:0xfffff7ffffffffff;
+li x22, 0xfffff7ffffffffff
+sha256sig0 x8, x22
+sw x8, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x8, 0x0000000000000000)
+
+inst_22:
+// rs1==x7, rd==x5, rs1_val == 18446739675663040511, 
+// opcode: sha256sig0 ; op1:x7; dest:x5; op1val:0xfffffbffffffffff;
+li x7, 0xfffffbffffffffff
+sha256sig0 x5, x7
+sw x5, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x5, 0x0000000000000000)
+
+inst_23:
+// rs1==x30, rd==x13, rs1_val == 18446741874686296063, 
+// opcode: sha256sig0 ; op1:x30; dest:x13; op1val:0xfffffdffffffffff;
+li x30, 0xfffffdffffffffff
+sha256sig0 x13, x30
+sw x13, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x13, 0x0000000000000000)
+
+inst_24:
+// rs1==x20, rd==x4, rs1_val == 18446742974197923839, 
+// opcode: sha256sig0 ; op1:x20; dest:x4; op1val:0xfffffeffffffffff;
+li x20, 0xfffffeffffffffff
+sha256sig0 x4, x20
+sw x4, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x4, 0x0000000000000000)
+
+inst_25:
+// rs1==x27, rd==x29, rs1_val == 18446743523953737727, 
+// opcode: sha256sig0 ; op1:x27; dest:x29; op1val:0xffffff7fffffffff;
+li x27, 0xffffff7fffffffff
+sha256sig0 x29, x27
+sw x29, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x29, 0x0000000000000000)
+
+inst_26:
+// rs1==x25, rd==x22, rs1_val == 18446743798831644671, 
+// opcode: sha256sig0 ; op1:x25; dest:x22; op1val:0xffffffbfffffffff;
+li x25, 0xffffffbfffffffff
+sha256sig0 x22, x25
+sw x22, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x22, 0x0000000000000000)
+
+inst_27:
+// rs1==x17, rd==x14, rs1_val == 18446743936270598143, 
+// opcode: sha256sig0 ; op1:x17; dest:x14; op1val:0xffffffdfffffffff;
+li x17, 0xffffffdfffffffff
+sha256sig0 x14, x17
+sw x14, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x14, 0x0000000000000000)
+
+inst_28:
+// rs1==x11, rd==x7, rs1_val == 18446744004990074879, 
+// opcode: sha256sig0 ; op1:x11; dest:x7; op1val:0xffffffefffffffff;
+li x11, 0xffffffefffffffff
+sha256sig0 x7, x11
+sw x7, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x7, 0x0000000000000000)
+
+inst_29:
+// rs1==x6, rd==x2, rs1_val == 18446744039349813247, 
+// opcode: sha256sig0 ; op1:x6; dest:x2; op1val:0xfffffff7ffffffff;
+li x6, 0xfffffff7ffffffff
+sha256sig0 x2, x6
+sw x2, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x2, 0x0000000000000000)
+
+inst_30:
+// rs1==x8, rd==x26, rs1_val == 18446744056529682431, 
+// opcode: sha256sig0 ; op1:x8; dest:x26; op1val:0xfffffffbffffffff;
+li x8, 0xfffffffbffffffff
+sha256sig0 x26, x8
+sw x26, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x26, 0x0000000000000000)
+
+inst_31:
+// rs1==x0, rd==x18, rs1_val == 18446744065119617023, 
+// opcode: sha256sig0 ; op1:x0; dest:x18; op1val:0x0;
+li x0, 0x0
+sha256sig0 x18, x0
+sw x18, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x18, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha256sig0 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha256sig0 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha256sig0 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha256sig0 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha256sig0 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha256sig0 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha256sig0 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha256sig0 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha256sig0 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha256sig0 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha256sig0 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha256sig0 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha256sig0 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha256sig0 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha256sig0 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha256sig0 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha256sig0 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha256sig0 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha256sig0 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha256sig0 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha256sig0 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha256sig0 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha256sig0 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha256sig0 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha256sig0 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha256sig0 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha256sig0 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha256sig0 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha256sig0 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha256sig0 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha256sig0 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha256sig0 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha256sig0 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha256sig0 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha256sig0 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha256sig0 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha256sig0 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha256sig0 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha256sig0 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha256sig0 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha256sig0 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha256sig0 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha256sig0 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha256sig0 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha256sig0 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha256sig0 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha256sig0 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha256sig0 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha256sig0 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha256sig0 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha256sig0 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha256sig0 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha256sig0 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha256sig0 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha256sig0 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha256sig0 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha256sig0 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha256sig0 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha256sig0 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha256sig0 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha256sig0 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha256sig0 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha256sig0 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha256sig0 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha256sig0 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha256sig0 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha256sig0 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha256sig0 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha256sig0 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha256sig0 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha256sig0 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha256sig0 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha256sig0 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha256sig0 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha256sig0 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha256sig0 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha256sig0 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha256sig0 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha256sig0 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha256sig0 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha256sig0 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha256sig0 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha256sig0 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha256sig0 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha256sig0 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha256sig0 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha256sig0 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha256sig0 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha256sig0 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha256sig0 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha256sig0 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha256sig0 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha256sig0 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha256sig0 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha256sig0 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha256sig0 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha256sig0 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha256sig0 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha256sig0 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha256sig0 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha256sig0 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha256sig0 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha256sig0 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha256sig0 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha256sig0 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha256sig0 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha256sig0 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha256sig0 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha256sig0 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha256sig0 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha256sig0 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha256sig0 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha256sig0 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha256sig0 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha256sig0 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha256sig0 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18428729675200069631, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xffbfffffffffffff;
+li x10, 0xffbfffffffffffff
+sha256sig0 x11, x10
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446744065119617023, 
+// opcode: sha256sig0 ; op1:x10; dest:x11; op1val:0xfffffffdffffffff;
+li x10, 0xfffffffdffffffff
+sha256sig0 x11, x10
+sw x11, 1032(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x7_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_1:
+    .fill 20*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 130*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S
new file mode 100644
index 000000000..6e17b1d87
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha256sig0 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha256sig0 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha256sig0 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha256sig0 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha256sig0 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha256sig0 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha256sig0 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha256sig0 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha256sig0 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha256sig0 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha256sig0 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha256sig0 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha256sig0 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha256sig0 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha256sig0 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha256sig0 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha256sig0 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha256sig0 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha256sig0 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha256sig0 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha256sig0 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha256sig0 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha256sig0 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha256sig0 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha256sig0 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha256sig0 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha256sig0 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha256sig0 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha256sig0 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha256sig0 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha256sig0 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha256sig0 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha256sig0 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha256sig0 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha256sig0 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha256sig0 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha256sig0 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha256sig0 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha256sig0 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha256sig0 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha256sig0 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha256sig0 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha256sig0 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha256sig0 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha256sig0 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha256sig0 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha256sig0 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha256sig0 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha256sig0 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha256sig0 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha256sig0 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha256sig0 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha256sig0 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha256sig0 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha256sig0 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha256sig0 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha256sig0 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha256sig0 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha256sig0 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha256sig0 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha256sig0 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha256sig0 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha256sig0 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha256sig0 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha256sig0 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha256sig0 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha256sig0 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha256sig0 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha256sig0 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha256sig0 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha256sig0 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha256sig0 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha256sig0 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha256sig0 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha256sig0 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha256sig0 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha256sig0 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha256sig0 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha256sig0 & the result back into xor
+// opcode: sha256sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha256sig0 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha256sig0 & the result back into not
+// opcode: sha256sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha256sig0 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha256sig0 & the result back into add
+// opcode: sha256sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha256sig0 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S
new file mode 100644
index 000000000..df040e50b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig0-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha256sig0 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha256sig0 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha256sig0 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha256sig0 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha256sig0 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha256sig0 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha256sig0 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha256sig0 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha256sig0 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha256sig0 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha256sig0 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha256sig0 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha256sig0 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha256sig0 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha256sig0 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha256sig0 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha256sig0 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha256sig0 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha256sig0 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha256sig0 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha256sig0 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha256sig0 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha256sig0 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha256sig0 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha256sig0 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha256sig0 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha256sig0 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha256sig0; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha256sig0 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S
new file mode 100644
index 000000000..11c729bef
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha256sig1 instruction of the RISC-V  extension for the sha256sig1 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKnh.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_SIGBASE( x13,signature_x13_1)
+
+inst_0:
+// rs1 != rd, rs1==x5, rd==x29, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha256sig1 ; op1:x5; dest:x29; op1val:0x75a3adb3254a9493;
+li x5, 0x75a3adb3254a9493
+sha256sig1 x29, x5
+sw x29, 0(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x29, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x26, rd==x26, rs1_val == 9223372036854775807, 
+// opcode: sha256sig1 ; op1:x26; dest:x26; op1val:0x7fffffffffffffff;
+li x26, 0x7fffffffffffffff
+sha256sig1 x26, x26
+sw x26, 8(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x26, 0x0000000000000000)
+
+inst_2:
+// rs1==x1, rd==x18, rs1_val == 13835058055282163711, 
+// opcode: sha256sig1 ; op1:x1; dest:x18; op1val:0xbfffffffffffffff;
+li x1, 0xbfffffffffffffff
+sha256sig1 x18, x1
+sw x18, 16(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x18, 0x0000000000000000)
+
+inst_3:
+// rs1==x24, rd==x10, rs1_val == 16140901064495857663, 
+// opcode: sha256sig1 ; op1:x24; dest:x10; op1val:0xdfffffffffffffff;
+li x24, 0xdfffffffffffffff
+sha256sig1 x10, x24
+sw x10, 24(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x10, 0x0000000000000000)
+
+inst_4:
+// rs1==x6, rd==x14, rs1_val == 17293822569102704639, 
+// opcode: sha256sig1 ; op1:x6; dest:x14; op1val:0xefffffffffffffff;
+li x6, 0xefffffffffffffff
+sha256sig1 x14, x6
+sw x14, 32(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x14, 0x0000000000000000)
+
+inst_5:
+// rs1==x20, rd==x8, rs1_val == 17870283321406128127, 
+// opcode: sha256sig1 ; op1:x20; dest:x8; op1val:0xf7ffffffffffffff;
+li x20, 0xf7ffffffffffffff
+sha256sig1 x8, x20
+sw x8, 40(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x8, 0x0000000000000000)
+
+inst_6:
+// rs1==x7, rd==x11, rs1_val == 18158513697557839871, 
+// opcode: sha256sig1 ; op1:x7; dest:x11; op1val:0xfbffffffffffffff;
+li x7, 0xfbffffffffffffff
+sha256sig1 x11, x7
+sw x11, 48(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x11, 0x0000000000000000)
+
+inst_7:
+// rs1==x9, rd==x1, rs1_val == 18302628885633695743, 
+// opcode: sha256sig1 ; op1:x9; dest:x1; op1val:0xfdffffffffffffff;
+li x9, 0xfdffffffffffffff
+sha256sig1 x1, x9
+sw x1, 56(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x1, 0x0000000000000000)
+
+inst_8:
+// rs1==x29, rd==x24, rs1_val == 18374686479671623679, 
+// opcode: sha256sig1 ; op1:x29; dest:x24; op1val:0xfeffffffffffffff;
+li x29, 0xfeffffffffffffff
+sha256sig1 x24, x29
+sw x24, 64(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x24, 0x0000000000000000)
+
+inst_9:
+// rs1==x28, rd==x23, rs1_val == 18410715276690587647, 
+// opcode: sha256sig1 ; op1:x28; dest:x23; op1val:0xff7fffffffffffff;
+li x28, 0xff7fffffffffffff
+sha256sig1 x23, x28
+sw x23, 72(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x23, 0x0000000000000000)
+
+inst_10:
+// rs1==x30, rd==x25, rs1_val == 18428729675200069631, 
+// opcode: sha256sig1 ; op1:x30; dest:x25; op1val:0xffbfffffffffffff;
+li x30, 0xffbfffffffffffff
+sha256sig1 x25, x30
+sw x25, 80(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x25, 0x0000000000000000)
+
+inst_11:
+// rs1==x11, rd==x30, rs1_val == 18437736874454810623, 
+// opcode: sha256sig1 ; op1:x11; dest:x30; op1val:0xffdfffffffffffff;
+li x11, 0xffdfffffffffffff
+sha256sig1 x30, x11
+sw x30, 88(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x30, 0x0000000000000000)
+
+inst_12:
+// rs1==x2, rd==x19, rs1_val == 18442240474082181119, 
+// opcode: sha256sig1 ; op1:x2; dest:x19; op1val:0xffefffffffffffff;
+li x2, 0xffefffffffffffff
+sha256sig1 x19, x2
+sw x19, 96(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x19, 0x0000000000000000)
+
+inst_13:
+// rs1==x21, rd==x20, rs1_val == 18444492273895866367, 
+// opcode: sha256sig1 ; op1:x21; dest:x20; op1val:0xfff7ffffffffffff;
+li x21, 0xfff7ffffffffffff
+sha256sig1 x20, x21
+sw x20, 104(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x20, 0x0000000000000000)
+
+inst_14:
+// rs1==x12, rd==x16, rs1_val == 18445618173802708991, 
+// opcode: sha256sig1 ; op1:x12; dest:x16; op1val:0xfffbffffffffffff;
+li x12, 0xfffbffffffffffff
+sha256sig1 x16, x12
+sw x16, 112(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x16, 0x0000000000000000)
+
+inst_15:
+// rs1==x8, rd==x4, rs1_val == 18446181123756130303, 
+// opcode: sha256sig1 ; op1:x8; dest:x4; op1val:0xfffdffffffffffff;
+li x8, 0xfffdffffffffffff
+sha256sig1 x4, x8
+sw x4, 120(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x4, 0x0000000000000000)
+
+inst_16:
+// rs1==x0, rd==x7, rs1_val == 18446462598732840959, 
+// opcode: sha256sig1 ; op1:x0; dest:x7; op1val:0x0;
+li x0, 0x0
+sha256sig1 x7, x0
+sw x7, 128(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x7, 0x0000000000000000)
+
+inst_17:
+// rs1==x18, rd==x3, rs1_val == 18446603336221196287, 
+// opcode: sha256sig1 ; op1:x18; dest:x3; op1val:0xffff7fffffffffff;
+li x18, 0xffff7fffffffffff
+sha256sig1 x3, x18
+sw x3, 136(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x3, 0x0000000000000000)
+
+inst_18:
+// rs1==x4, rd==x28, rs1_val == 18446673704965373951, 
+// opcode: sha256sig1 ; op1:x4; dest:x28; op1val:0xffffbfffffffffff;
+li x4, 0xffffbfffffffffff
+sha256sig1 x28, x4
+sw x28, 144(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x28, 0x0000000000000000)
+
+inst_19:
+// rs1==x15, rd==x31, rs1_val == 18446708889337462783, 
+// opcode: sha256sig1 ; op1:x15; dest:x31; op1val:0xffffdfffffffffff;
+li x15, 0xffffdfffffffffff
+sha256sig1 x31, x15
+sw x31, 152(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x17, x31, 0x0000000000000000)
+
+inst_20:
+// rs1==x16, rd==x22, rs1_val == 18446726481523507199, 
+// opcode: sha256sig1 ; op1:x16; dest:x22; op1val:0xffffefffffffffff;
+li x16, 0xffffefffffffffff
+sha256sig1 x22, x16
+sw x22, 160(x13)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x22, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_21:
+// rs1==x27, rd==x6, rs1_val == 18446735277616529407, 
+// opcode: sha256sig1 ; op1:x27; dest:x6; op1val:0xfffff7ffffffffff;
+li x27, 0xfffff7ffffffffff
+sha256sig1 x6, x27
+sw x6, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x6, 0x0000000000000000)
+
+inst_22:
+// rs1==x14, rd==x2, rs1_val == 18446739675663040511, 
+// opcode: sha256sig1 ; op1:x14; dest:x2; op1val:0xfffffbffffffffff;
+li x14, 0xfffffbffffffffff
+sha256sig1 x2, x14
+sw x2, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x2, 0x0000000000000000)
+
+inst_23:
+// rs1==x3, rd==x13, rs1_val == 18446741874686296063, 
+// opcode: sha256sig1 ; op1:x3; dest:x13; op1val:0xfffffdffffffffff;
+li x3, 0xfffffdffffffffff
+sha256sig1 x13, x3
+sw x13, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x13, 0x0000000000000000)
+
+inst_24:
+// rs1==x13, rd==x17, rs1_val == 18446742974197923839, 
+// opcode: sha256sig1 ; op1:x13; dest:x17; op1val:0xfffffeffffffffff;
+li x13, 0xfffffeffffffffff
+sha256sig1 x17, x13
+sw x17, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x17, 0x0000000000000000)
+
+inst_25:
+// rs1==x19, rd==x15, rs1_val == 18446743523953737727, 
+// opcode: sha256sig1 ; op1:x19; dest:x15; op1val:0xffffff7fffffffff;
+li x19, 0xffffff7fffffffff
+sha256sig1 x15, x19
+sw x15, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x15, 0x0000000000000000)
+
+inst_26:
+// rs1==x23, rd==x9, rs1_val == 18446743798831644671, 
+// opcode: sha256sig1 ; op1:x23; dest:x9; op1val:0xffffffbfffffffff;
+li x23, 0xffffffbfffffffff
+sha256sig1 x9, x23
+sw x9, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x9, 0x0000000000000000)
+
+inst_27:
+// rs1==x10, rd==x27, rs1_val == 18446743936270598143, 
+// opcode: sha256sig1 ; op1:x10; dest:x27; op1val:0xffffffdfffffffff;
+li x10, 0xffffffdfffffffff
+sha256sig1 x27, x10
+sw x27, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x27, 0x0000000000000000)
+
+inst_28:
+// rs1==x31, rd==x5, rs1_val == 18446744004990074879, 
+// opcode: sha256sig1 ; op1:x31; dest:x5; op1val:0xffffffefffffffff;
+li x31, 0xffffffefffffffff
+sha256sig1 x5, x31
+sw x5, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x5, 0x0000000000000000)
+
+inst_29:
+// rs1==x25, rd==x21, rs1_val == 18446744039349813247, 
+// opcode: sha256sig1 ; op1:x25; dest:x21; op1val:0xfffffff7ffffffff;
+li x25, 0xfffffff7ffffffff
+sha256sig1 x21, x25
+sw x21, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x21, 0x0000000000000000)
+
+inst_30:
+// rs1==x22, rd==x0, rs1_val == 18446744056529682431, 
+// opcode: sha256sig1 ; op1:x22; dest:x0; op1val:0xfffffffbffffffff;
+li x22, 0xfffffffbffffffff
+sha256sig1 x0, x22
+sw x0, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x0, 0x0000000000000000)
+
+inst_31:
+// rs1==x17, rd==x12, rs1_val == 18446744065119617023, 
+// opcode: sha256sig1 ; op1:x17; dest:x12; op1val:0xfffffffdffffffff;
+li x17, 0xfffffffdffffffff
+sha256sig1 x12, x17
+sw x12, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x12, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha256sig1 x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha256sig1 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha256sig1 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha256sig1 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha256sig1 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha256sig1 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha256sig1 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha256sig1 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha256sig1 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha256sig1 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha256sig1 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha256sig1 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha256sig1 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha256sig1 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha256sig1 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha256sig1 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha256sig1 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha256sig1 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha256sig1 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha256sig1 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha256sig1 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha256sig1 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha256sig1 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha256sig1 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha256sig1 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha256sig1 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha256sig1 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha256sig1 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha256sig1 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha256sig1 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha256sig1 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha256sig1 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha256sig1 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha256sig1 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha256sig1 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha256sig1 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha256sig1 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha256sig1 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha256sig1 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha256sig1 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha256sig1 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha256sig1 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha256sig1 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha256sig1 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha256sig1 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha256sig1 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha256sig1 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha256sig1 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha256sig1 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha256sig1 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha256sig1 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha256sig1 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha256sig1 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha256sig1 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha256sig1 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha256sig1 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha256sig1 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha256sig1 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha256sig1 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha256sig1 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha256sig1 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha256sig1 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha256sig1 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha256sig1 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha256sig1 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha256sig1 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha256sig1 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha256sig1 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha256sig1 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha256sig1 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha256sig1 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha256sig1 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha256sig1 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha256sig1 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha256sig1 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha256sig1 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha256sig1 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha256sig1 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha256sig1 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha256sig1 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha256sig1 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha256sig1 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha256sig1 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha256sig1 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha256sig1 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha256sig1 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha256sig1 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha256sig1 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha256sig1 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha256sig1 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha256sig1 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha256sig1 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha256sig1 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha256sig1 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha256sig1 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha256sig1 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha256sig1 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha256sig1 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha256sig1 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha256sig1 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha256sig1 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha256sig1 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha256sig1 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha256sig1 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha256sig1 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha256sig1 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha256sig1 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha256sig1 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha256sig1 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha256sig1 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha256sig1 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha256sig1 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha256sig1 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha256sig1 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha256sig1 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha256sig1 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18446462598732840959, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffeffffffffffff;
+li x10, 0xfffeffffffffffff
+sha256sig1 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446744056529682431, 
+// opcode: sha256sig1 ; op1:x10; dest:x11; op1val:0xfffffffbffffffff;
+li x10, 0xfffffffbffffffff
+sha256sig1 x11, x10
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x13_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x13_1:
+    .fill 21*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 129*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S
new file mode 100644
index 000000000..23e180ee9
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha256sig1 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha256sig1 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha256sig1 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha256sig1 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha256sig1 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha256sig1 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha256sig1 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha256sig1 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha256sig1 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha256sig1 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha256sig1 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha256sig1 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha256sig1 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha256sig1 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha256sig1 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha256sig1 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha256sig1 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha256sig1 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha256sig1 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha256sig1 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha256sig1 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha256sig1 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha256sig1 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha256sig1 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha256sig1 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha256sig1 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha256sig1 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha256sig1 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha256sig1 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha256sig1 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha256sig1 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha256sig1 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha256sig1 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha256sig1 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha256sig1 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha256sig1 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha256sig1 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha256sig1 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha256sig1 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha256sig1 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha256sig1 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha256sig1 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha256sig1 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha256sig1 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha256sig1 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha256sig1 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha256sig1 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha256sig1 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha256sig1 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha256sig1 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha256sig1 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha256sig1 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha256sig1 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha256sig1 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha256sig1 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha256sig1 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha256sig1 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha256sig1 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha256sig1 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha256sig1 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha256sig1 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha256sig1 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha256sig1 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha256sig1 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha256sig1 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha256sig1 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha256sig1 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha256sig1 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha256sig1 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha256sig1 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha256sig1 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha256sig1 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha256sig1 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha256sig1 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha256sig1 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha256sig1 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha256sig1 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha256sig1 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha256sig1 & the result back into xor
+// opcode: sha256sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha256sig1 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha256sig1 & the result back into not
+// opcode: sha256sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha256sig1 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha256sig1 & the result back into add
+// opcode: sha256sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha256sig1 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S
new file mode 100644
index 000000000..b06950bd4
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sig1-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sig1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha256sig1 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha256sig1 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha256sig1 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha256sig1 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha256sig1 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha256sig1 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha256sig1 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha256sig1 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha256sig1 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha256sig1 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha256sig1 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha256sig1 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha256sig1 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha256sig1 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha256sig1 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha256sig1 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha256sig1 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha256sig1 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha256sig1 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha256sig1 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha256sig1 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha256sig1 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha256sig1 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha256sig1 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha256sig1 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha256sig1 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha256sig1 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha256sig1; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha256sig1 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S
new file mode 100644
index 000000000..bd40a36ac
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha256sum0 instruction of the RISC-V  extension for the sha256sum0 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKnh.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x26, rd==x20, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha256sum0 ; op1:x26; dest:x20; op1val:0x75a3adb3254a9493;
+li x26, 0x75a3adb3254a9493
+sha256sum0 x20, x26
+sw x20, 0(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x20, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x8, rd==x8, rs1_val == 9223372036854775807, 
+// opcode: sha256sum0 ; op1:x8; dest:x8; op1val:0x7fffffffffffffff;
+li x8, 0x7fffffffffffffff
+sha256sum0 x8, x8
+sw x8, 8(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x8, 0x0000000000000000)
+
+inst_2:
+// rs1==x5, rd==x15, rs1_val == 13835058055282163711, 
+// opcode: sha256sum0 ; op1:x5; dest:x15; op1val:0xbfffffffffffffff;
+li x5, 0xbfffffffffffffff
+sha256sum0 x15, x5
+sw x15, 16(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x15, 0x0000000000000000)
+
+inst_3:
+// rs1==x15, rd==x25, rs1_val == 16140901064495857663, 
+// opcode: sha256sum0 ; op1:x15; dest:x25; op1val:0xdfffffffffffffff;
+li x15, 0xdfffffffffffffff
+sha256sum0 x25, x15
+sw x25, 24(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x25, 0x0000000000000000)
+
+inst_4:
+// rs1==x27, rd==x10, rs1_val == 17293822569102704639, 
+// opcode: sha256sum0 ; op1:x27; dest:x10; op1val:0xefffffffffffffff;
+li x27, 0xefffffffffffffff
+sha256sum0 x10, x27
+sw x10, 32(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x10, 0x0000000000000000)
+
+inst_5:
+// rs1==x10, rd==x27, rs1_val == 17870283321406128127, 
+// opcode: sha256sum0 ; op1:x10; dest:x27; op1val:0xf7ffffffffffffff;
+li x10, 0xf7ffffffffffffff
+sha256sum0 x27, x10
+sw x27, 40(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x27, 0x0000000000000000)
+
+inst_6:
+// rs1==x30, rd==x2, rs1_val == 18158513697557839871, 
+// opcode: sha256sum0 ; op1:x30; dest:x2; op1val:0xfbffffffffffffff;
+li x30, 0xfbffffffffffffff
+sha256sum0 x2, x30
+sw x2, 48(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x2, 0x0000000000000000)
+
+inst_7:
+// rs1==x7, rd==x9, rs1_val == 18302628885633695743, 
+// opcode: sha256sum0 ; op1:x7; dest:x9; op1val:0xfdffffffffffffff;
+li x7, 0xfdffffffffffffff
+sha256sum0 x9, x7
+sw x9, 56(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x9, 0x0000000000000000)
+
+inst_8:
+// rs1==x21, rd==x24, rs1_val == 18374686479671623679, 
+// opcode: sha256sum0 ; op1:x21; dest:x24; op1val:0xfeffffffffffffff;
+li x21, 0xfeffffffffffffff
+sha256sum0 x24, x21
+sw x24, 64(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x24, 0x0000000000000000)
+
+inst_9:
+// rs1==x3, rd==x16, rs1_val == 18410715276690587647, 
+// opcode: sha256sum0 ; op1:x3; dest:x16; op1val:0xff7fffffffffffff;
+li x3, 0xff7fffffffffffff
+sha256sum0 x16, x3
+sw x16, 72(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x16, 0x0000000000000000)
+
+inst_10:
+// rs1==x31, rd==x12, rs1_val == 18428729675200069631, 
+// opcode: sha256sum0 ; op1:x31; dest:x12; op1val:0xffbfffffffffffff;
+li x31, 0xffbfffffffffffff
+sha256sum0 x12, x31
+sw x12, 80(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x12, 0x0000000000000000)
+
+inst_11:
+// rs1==x6, rd==x17, rs1_val == 18437736874454810623, 
+// opcode: sha256sum0 ; op1:x6; dest:x17; op1val:0xffdfffffffffffff;
+li x6, 0xffdfffffffffffff
+sha256sum0 x17, x6
+sw x17, 88(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x17, 0x0000000000000000)
+
+inst_12:
+// rs1==x1, rd==x22, rs1_val == 18442240474082181119, 
+// opcode: sha256sum0 ; op1:x1; dest:x22; op1val:0xffefffffffffffff;
+li x1, 0xffefffffffffffff
+sha256sum0 x22, x1
+sw x22, 96(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x22, 0x0000000000000000)
+
+inst_13:
+// rs1==x29, rd==x1, rs1_val == 18444492273895866367, 
+// opcode: sha256sum0 ; op1:x29; dest:x1; op1val:0xfff7ffffffffffff;
+li x29, 0xfff7ffffffffffff
+sha256sum0 x1, x29
+sw x1, 104(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x1, 0x0000000000000000)
+
+inst_14:
+// rs1==x2, rd==x19, rs1_val == 18445618173802708991, 
+// opcode: sha256sum0 ; op1:x2; dest:x19; op1val:0xfffbffffffffffff;
+li x2, 0xfffbffffffffffff
+sha256sum0 x19, x2
+sw x19, 112(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x19, 0x0000000000000000)
+
+inst_15:
+// rs1==x11, rd==x7, rs1_val == 18446181123756130303, 
+// opcode: sha256sum0 ; op1:x11; dest:x7; op1val:0xfffdffffffffffff;
+li x11, 0xfffdffffffffffff
+sha256sum0 x7, x11
+sw x7, 120(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x7, 0x0000000000000000)
+
+inst_16:
+// rs1==x25, rd==x23, rs1_val == 18446462598732840959, 
+// opcode: sha256sum0 ; op1:x25; dest:x23; op1val:0xfffeffffffffffff;
+li x25, 0xfffeffffffffffff
+sha256sum0 x23, x25
+sw x23, 128(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x23, 0x0000000000000000)
+
+inst_17:
+// rs1==x24, rd==x11, rs1_val == 18446603336221196287, 
+// opcode: sha256sum0 ; op1:x24; dest:x11; op1val:0xffff7fffffffffff;
+li x24, 0xffff7fffffffffff
+sha256sum0 x11, x24
+sw x11, 136(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x11, 0x0000000000000000)
+
+inst_18:
+// rs1==x20, rd==x3, rs1_val == 18446673704965373951, 
+// opcode: sha256sum0 ; op1:x20; dest:x3; op1val:0xffffbfffffffffff;
+li x20, 0xffffbfffffffffff
+sha256sum0 x3, x20
+sw x3, 144(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x3, 0x0000000000000000)
+
+inst_19:
+// rs1==x12, rd==x5, rs1_val == 18446708889337462783, 
+// opcode: sha256sum0 ; op1:x12; dest:x5; op1val:0xffffdfffffffffff;
+li x12, 0xffffdfffffffffff
+sha256sum0 x5, x12
+sw x5, 152(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x5, 0x0000000000000000)
+
+inst_20:
+// rs1==x14, rd==x0, rs1_val == 18446726481523507199, 
+// opcode: sha256sum0 ; op1:x14; dest:x0; op1val:0xffffefffffffffff;
+li x14, 0xffffefffffffffff
+sha256sum0 x0, x14
+sw x0, 160(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x0, 0x0000000000000000)
+
+inst_21:
+// rs1==x18, rd==x13, rs1_val == 18446735277616529407, 
+// opcode: sha256sum0 ; op1:x18; dest:x13; op1val:0xfffff7ffffffffff;
+li x18, 0xfffff7ffffffffff
+sha256sum0 x13, x18
+sw x13, 168(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x13, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_22:
+// rs1==x28, rd==x21, rs1_val == 18446739675663040511, 
+// opcode: sha256sum0 ; op1:x28; dest:x21; op1val:0xfffffbffffffffff;
+li x28, 0xfffffbffffffffff
+sha256sum0 x21, x28
+sw x21, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x0000000000000000)
+
+inst_23:
+// rs1==x17, rd==x26, rs1_val == 18446741874686296063, 
+// opcode: sha256sum0 ; op1:x17; dest:x26; op1val:0xfffffdffffffffff;
+li x17, 0xfffffdffffffffff
+sha256sum0 x26, x17
+sw x26, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x26, 0x0000000000000000)
+
+inst_24:
+// rs1==x16, rd==x30, rs1_val == 18446742974197923839, 
+// opcode: sha256sum0 ; op1:x16; dest:x30; op1val:0xfffffeffffffffff;
+li x16, 0xfffffeffffffffff
+sha256sum0 x30, x16
+sw x30, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x30, 0x0000000000000000)
+
+inst_25:
+// rs1==x19, rd==x31, rs1_val == 18446743523953737727, 
+// opcode: sha256sum0 ; op1:x19; dest:x31; op1val:0xffffff7fffffffff;
+li x19, 0xffffff7fffffffff
+sha256sum0 x31, x19
+sw x31, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000000000000)
+
+inst_26:
+// rs1==x4, rd==x14, rs1_val == 18446743798831644671, 
+// opcode: sha256sum0 ; op1:x4; dest:x14; op1val:0xffffffbfffffffff;
+li x4, 0xffffffbfffffffff
+sha256sum0 x14, x4
+sw x14, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x14, 0x0000000000000000)
+
+inst_27:
+// rs1==x0, rd==x28, rs1_val == 18446743936270598143, 
+// opcode: sha256sum0 ; op1:x0; dest:x28; op1val:0x0;
+li x0, 0x0
+sha256sum0 x28, x0
+sw x28, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x28, 0x0000000000000000)
+
+inst_28:
+// rs1==x13, rd==x6, rs1_val == 18446744004990074879, 
+// opcode: sha256sum0 ; op1:x13; dest:x6; op1val:0xffffffefffffffff;
+li x13, 0xffffffefffffffff
+sha256sum0 x6, x13
+sw x6, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x6, 0x0000000000000000)
+
+inst_29:
+// rs1==x23, rd==x29, rs1_val == 18446744039349813247, 
+// opcode: sha256sum0 ; op1:x23; dest:x29; op1val:0xfffffff7ffffffff;
+li x23, 0xfffffff7ffffffff
+sha256sum0 x29, x23
+sw x29, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x29, 0x0000000000000000)
+
+inst_30:
+// rs1==x9, rd==x4, rs1_val == 18446744056529682431, 
+// opcode: sha256sum0 ; op1:x9; dest:x4; op1val:0xfffffffbffffffff;
+li x9, 0xfffffffbffffffff
+sha256sum0 x4, x9
+sw x4, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x4, 0x0000000000000000)
+
+inst_31:
+// rs1==x22, rd==x18, rs1_val == 18446744065119617023, 
+// opcode: sha256sum0 ; op1:x22; dest:x18; op1val:0xfffffffdffffffff;
+li x22, 0xfffffffdffffffff
+sha256sum0 x18, x22
+sw x18, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x18, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha256sum0 x11, x10
+sw x11, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha256sum0 x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha256sum0 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha256sum0 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha256sum0 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha256sum0 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha256sum0 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha256sum0 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha256sum0 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha256sum0 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha256sum0 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha256sum0 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha256sum0 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha256sum0 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha256sum0 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha256sum0 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha256sum0 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha256sum0 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha256sum0 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha256sum0 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha256sum0 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha256sum0 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha256sum0 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha256sum0 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha256sum0 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha256sum0 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha256sum0 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha256sum0 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha256sum0 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha256sum0 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha256sum0 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha256sum0 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha256sum0 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha256sum0 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha256sum0 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha256sum0 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha256sum0 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha256sum0 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha256sum0 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha256sum0 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha256sum0 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha256sum0 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha256sum0 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha256sum0 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha256sum0 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha256sum0 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha256sum0 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha256sum0 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha256sum0 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha256sum0 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha256sum0 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha256sum0 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha256sum0 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha256sum0 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha256sum0 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha256sum0 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha256sum0 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha256sum0 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha256sum0 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha256sum0 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha256sum0 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha256sum0 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha256sum0 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha256sum0 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha256sum0 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha256sum0 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha256sum0 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha256sum0 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha256sum0 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha256sum0 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha256sum0 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha256sum0 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha256sum0 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha256sum0 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha256sum0 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha256sum0 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha256sum0 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha256sum0 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha256sum0 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha256sum0 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha256sum0 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha256sum0 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha256sum0 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha256sum0 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha256sum0 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha256sum0 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha256sum0 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha256sum0 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha256sum0 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha256sum0 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha256sum0 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha256sum0 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha256sum0 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha256sum0 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha256sum0 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha256sum0 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha256sum0 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha256sum0 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha256sum0 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha256sum0 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha256sum0 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha256sum0 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha256sum0 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha256sum0 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha256sum0 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha256sum0 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha256sum0 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha256sum0 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha256sum0 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha256sum0 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha256sum0 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha256sum0 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha256sum0 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha256sum0 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha256sum0 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha256sum0 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18446726481523507199, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffefffffffffff;
+li x10, 0xffffefffffffffff
+sha256sum0 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446743936270598143, 
+// opcode: sha256sum0 ; op1:x10; dest:x11; op1val:0xffffffdfffffffff;
+li x10, 0xffffffdfffffffff
+sha256sum0 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S
new file mode 100644
index 000000000..77c5577fe
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha256sum0 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha256sum0 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha256sum0 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha256sum0 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha256sum0 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha256sum0 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha256sum0 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha256sum0 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha256sum0 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha256sum0 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha256sum0 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha256sum0 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha256sum0 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha256sum0 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha256sum0 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha256sum0 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha256sum0 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha256sum0 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha256sum0 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha256sum0 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha256sum0 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha256sum0 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha256sum0 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha256sum0 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha256sum0 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha256sum0 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha256sum0 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha256sum0 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha256sum0 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha256sum0 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha256sum0 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha256sum0 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha256sum0 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha256sum0 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha256sum0 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha256sum0 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha256sum0 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha256sum0 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha256sum0 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha256sum0 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha256sum0 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha256sum0 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha256sum0 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha256sum0 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha256sum0 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha256sum0 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha256sum0 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha256sum0 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha256sum0 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha256sum0 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha256sum0 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha256sum0 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha256sum0 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha256sum0 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha256sum0 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha256sum0 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha256sum0 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha256sum0 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha256sum0 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha256sum0 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha256sum0 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha256sum0 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha256sum0 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha256sum0 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha256sum0 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha256sum0 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha256sum0 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha256sum0 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha256sum0 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha256sum0 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha256sum0 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha256sum0 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha256sum0 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha256sum0 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha256sum0 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha256sum0 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha256sum0 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha256sum0 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha256sum0 & the result back into xor
+// opcode: sha256sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha256sum0 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha256sum0 & the result back into not
+// opcode: sha256sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha256sum0 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha256sum0 & the result back into add
+// opcode: sha256sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha256sum0 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S
new file mode 100644
index 000000000..3e3c833f0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum0-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha256sum0 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha256sum0 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha256sum0 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha256sum0 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha256sum0 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha256sum0 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha256sum0 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha256sum0 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha256sum0 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha256sum0 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha256sum0 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha256sum0 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha256sum0 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha256sum0 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha256sum0 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha256sum0 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha256sum0 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha256sum0 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha256sum0 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha256sum0 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha256sum0 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha256sum0 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha256sum0 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha256sum0 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha256sum0 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha256sum0 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha256sum0 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha256sum0; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha256sum0 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S
new file mode 100644
index 000000000..7c84af1fc
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha256sum1 instruction of the RISC-V  extension for the sha256sum1 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKnh.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs1 != rd, rs1==x25, rd==x11, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha256sum1 ; op1:x25; dest:x11; op1val:0x75a3adb3254a9493;
+li x25, 0x75a3adb3254a9493
+sha256sum1 x11, x25
+sw x11, 0(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x8, rd==x8, rs1_val == 9223372036854775807, 
+// opcode: sha256sum1 ; op1:x8; dest:x8; op1val:0x7fffffffffffffff;
+li x8, 0x7fffffffffffffff
+sha256sum1 x8, x8
+sw x8, 8(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x8, 0x0000000000000000)
+
+inst_2:
+// rs1==x28, rd==x16, rs1_val == 13835058055282163711, 
+// opcode: sha256sum1 ; op1:x28; dest:x16; op1val:0xbfffffffffffffff;
+li x28, 0xbfffffffffffffff
+sha256sum1 x16, x28
+sw x16, 16(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x16, 0x0000000000000000)
+
+inst_3:
+// rs1==x22, rd==x7, rs1_val == 16140901064495857663, 
+// opcode: sha256sum1 ; op1:x22; dest:x7; op1val:0xdfffffffffffffff;
+li x22, 0xdfffffffffffffff
+sha256sum1 x7, x22
+sw x7, 24(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x7, 0x0000000000000000)
+
+inst_4:
+// rs1==x2, rd==x12, rs1_val == 17293822569102704639, 
+// opcode: sha256sum1 ; op1:x2; dest:x12; op1val:0xefffffffffffffff;
+li x2, 0xefffffffffffffff
+sha256sum1 x12, x2
+sw x12, 32(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x12, 0x0000000000000000)
+
+inst_5:
+// rs1==x26, rd==x17, rs1_val == 17870283321406128127, 
+// opcode: sha256sum1 ; op1:x26; dest:x17; op1val:0xf7ffffffffffffff;
+li x26, 0xf7ffffffffffffff
+sha256sum1 x17, x26
+sw x17, 40(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x17, 0x0000000000000000)
+
+inst_6:
+// rs1==x10, rd==x6, rs1_val == 18158513697557839871, 
+// opcode: sha256sum1 ; op1:x10; dest:x6; op1val:0xfbffffffffffffff;
+li x10, 0xfbffffffffffffff
+sha256sum1 x6, x10
+sw x6, 48(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x6, 0x0000000000000000)
+
+inst_7:
+// rs1==x21, rd==x4, rs1_val == 18302628885633695743, 
+// opcode: sha256sum1 ; op1:x21; dest:x4; op1val:0xfdffffffffffffff;
+li x21, 0xfdffffffffffffff
+sha256sum1 x4, x21
+sw x4, 56(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x4, 0x0000000000000000)
+
+inst_8:
+// rs1==x15, rd==x5, rs1_val == 18374686479671623679, 
+// opcode: sha256sum1 ; op1:x15; dest:x5; op1val:0xfeffffffffffffff;
+li x15, 0xfeffffffffffffff
+sha256sum1 x5, x15
+sw x5, 64(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x5, 0x0000000000000000)
+
+inst_9:
+// rs1==x1, rd==x9, rs1_val == 18410715276690587647, 
+// opcode: sha256sum1 ; op1:x1; dest:x9; op1val:0xff7fffffffffffff;
+li x1, 0xff7fffffffffffff
+sha256sum1 x9, x1
+sw x9, 72(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x9, 0x0000000000000000)
+
+inst_10:
+// rs1==x14, rd==x19, rs1_val == 18428729675200069631, 
+// opcode: sha256sum1 ; op1:x14; dest:x19; op1val:0xffbfffffffffffff;
+li x14, 0xffbfffffffffffff
+sha256sum1 x19, x14
+sw x19, 80(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x19, 0x0000000000000000)
+
+inst_11:
+// rs1==x16, rd==x21, rs1_val == 18437736874454810623, 
+// opcode: sha256sum1 ; op1:x16; dest:x21; op1val:0xffdfffffffffffff;
+li x16, 0xffdfffffffffffff
+sha256sum1 x21, x16
+sw x21, 88(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x21, 0x0000000000000000)
+
+inst_12:
+// rs1==x5, rd==x20, rs1_val == 18442240474082181119, 
+// opcode: sha256sum1 ; op1:x5; dest:x20; op1val:0xffefffffffffffff;
+li x5, 0xffefffffffffffff
+sha256sum1 x20, x5
+sw x20, 96(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x20, 0x0000000000000000)
+
+inst_13:
+// rs1==x29, rd==x31, rs1_val == 18444492273895866367, 
+// opcode: sha256sum1 ; op1:x29; dest:x31; op1val:0xfff7ffffffffffff;
+li x29, 0xfff7ffffffffffff
+sha256sum1 x31, x29
+sw x31, 104(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x31, 0x0000000000000000)
+
+inst_14:
+// rs1==x30, rd==x2, rs1_val == 18445618173802708991, 
+// opcode: sha256sum1 ; op1:x30; dest:x2; op1val:0xfffbffffffffffff;
+li x30, 0xfffbffffffffffff
+sha256sum1 x2, x30
+sw x2, 112(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x2, 0x0000000000000000)
+
+inst_15:
+// rs1==x9, rd==x23, rs1_val == 18446181123756130303, 
+// opcode: sha256sum1 ; op1:x9; dest:x23; op1val:0xfffdffffffffffff;
+li x9, 0xfffdffffffffffff
+sha256sum1 x23, x9
+sw x23, 120(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x23, 0x0000000000000000)
+
+inst_16:
+// rs1==x0, rd==x26, rs1_val == 18446462598732840959, 
+// opcode: sha256sum1 ; op1:x0; dest:x26; op1val:0x0;
+li x0, 0x0
+sha256sum1 x26, x0
+sw x26, 128(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x26, 0x0000000000000000)
+
+inst_17:
+// rs1==x19, rd==x15, rs1_val == 18446603336221196287, 
+// opcode: sha256sum1 ; op1:x19; dest:x15; op1val:0xffff7fffffffffff;
+li x19, 0xffff7fffffffffff
+sha256sum1 x15, x19
+sw x15, 136(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x15, 0x0000000000000000)
+
+inst_18:
+// rs1==x11, rd==x13, rs1_val == 18446673704965373951, 
+// opcode: sha256sum1 ; op1:x11; dest:x13; op1val:0xffffbfffffffffff;
+li x11, 0xffffbfffffffffff
+sha256sum1 x13, x11
+sw x13, 144(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x13, 0x0000000000000000)
+
+inst_19:
+// rs1==x7, rd==x14, rs1_val == 18446708889337462783, 
+// opcode: sha256sum1 ; op1:x7; dest:x14; op1val:0xffffdfffffffffff;
+li x7, 0xffffdfffffffffff
+sha256sum1 x14, x7
+sw x14, 152(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x14, 0x0000000000000000)
+
+inst_20:
+// rs1==x17, rd==x22, rs1_val == 18446726481523507199, 
+// opcode: sha256sum1 ; op1:x17; dest:x22; op1val:0xffffefffffffffff;
+li x17, 0xffffefffffffffff
+sha256sum1 x22, x17
+sw x22, 160(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x22, 0x0000000000000000)
+
+inst_21:
+// rs1==x27, rd==x10, rs1_val == 18446735277616529407, 
+// opcode: sha256sum1 ; op1:x27; dest:x10; op1val:0xfffff7ffffffffff;
+li x27, 0xfffff7ffffffffff
+sha256sum1 x10, x27
+sw x10, 168(x3)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x10, 0x0000000000000000)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_22:
+// rs1==x20, rd==x24, rs1_val == 18446739675663040511, 
+// opcode: sha256sum1 ; op1:x20; dest:x24; op1val:0xfffffbffffffffff;
+li x20, 0xfffffbffffffffff
+sha256sum1 x24, x20
+sw x24, 0(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x24, 0x0000000000000000)
+
+inst_23:
+// rs1==x6, rd==x25, rs1_val == 18446741874686296063, 
+// opcode: sha256sum1 ; op1:x6; dest:x25; op1val:0xfffffdffffffffff;
+li x6, 0xfffffdffffffffff
+sha256sum1 x25, x6
+sw x25, 8(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x25, 0x0000000000000000)
+
+inst_24:
+// rs1==x31, rd==x3, rs1_val == 18446742974197923839, 
+// opcode: sha256sum1 ; op1:x31; dest:x3; op1val:0xfffffeffffffffff;
+li x31, 0xfffffeffffffffff
+sha256sum1 x3, x31
+sw x3, 16(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x3, 0x0000000000000000)
+
+inst_25:
+// rs1==x4, rd==x1, rs1_val == 18446743523953737727, 
+// opcode: sha256sum1 ; op1:x4; dest:x1; op1val:0xffffff7fffffffff;
+li x4, 0xffffff7fffffffff
+sha256sum1 x1, x4
+sw x1, 24(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x1, 0x0000000000000000)
+
+inst_26:
+// rs1==x12, rd==x0, rs1_val == 18446743798831644671, 
+// opcode: sha256sum1 ; op1:x12; dest:x0; op1val:0xffffffbfffffffff;
+li x12, 0xffffffbfffffffff
+sha256sum1 x0, x12
+sw x0, 32(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x0, 0x0000000000000000)
+
+inst_27:
+// rs1==x18, rd==x30, rs1_val == 18446743936270598143, 
+// opcode: sha256sum1 ; op1:x18; dest:x30; op1val:0xffffffdfffffffff;
+li x18, 0xffffffdfffffffff
+sha256sum1 x30, x18
+sw x30, 40(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x30, 0x0000000000000000)
+
+inst_28:
+// rs1==x13, rd==x27, rs1_val == 18446744004990074879, 
+// opcode: sha256sum1 ; op1:x13; dest:x27; op1val:0xffffffefffffffff;
+li x13, 0xffffffefffffffff
+sha256sum1 x27, x13
+sw x27, 48(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x27, 0x0000000000000000)
+
+inst_29:
+// rs1==x3, rd==x29, rs1_val == 18446744039349813247, 
+// opcode: sha256sum1 ; op1:x3; dest:x29; op1val:0xfffffff7ffffffff;
+li x3, 0xfffffff7ffffffff
+sha256sum1 x29, x3
+sw x29, 56(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x29, 0x0000000000000000)
+
+inst_30:
+// rs1==x24, rd==x28, rs1_val == 18446744056529682431, 
+// opcode: sha256sum1 ; op1:x24; dest:x28; op1val:0xfffffffbffffffff;
+li x24, 0xfffffffbffffffff
+sha256sum1 x28, x24
+sw x28, 64(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x28, 0x0000000000000000)
+
+inst_31:
+// rs1==x23, rd==x18, rs1_val == 18446744065119617023, 
+// opcode: sha256sum1 ; op1:x23; dest:x18; op1val:0xfffffffdffffffff;
+li x23, 0xfffffffdffffffff
+sha256sum1 x18, x23
+sw x18, 72(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x18, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha256sum1 x11, x10
+sw x11, 80(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha256sum1 x11, x10
+sw x11, 88(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha256sum1 x11, x10
+sw x11, 96(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha256sum1 x11, x10
+sw x11, 104(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha256sum1 x11, x10
+sw x11, 112(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha256sum1 x11, x10
+sw x11, 120(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha256sum1 x11, x10
+sw x11, 128(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha256sum1 x11, x10
+sw x11, 136(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha256sum1 x11, x10
+sw x11, 144(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha256sum1 x11, x10
+sw x11, 152(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha256sum1 x11, x10
+sw x11, 160(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha256sum1 x11, x10
+sw x11, 168(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha256sum1 x11, x10
+sw x11, 176(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha256sum1 x11, x10
+sw x11, 184(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha256sum1 x11, x10
+sw x11, 192(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha256sum1 x11, x10
+sw x11, 200(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha256sum1 x11, x10
+sw x11, 208(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha256sum1 x11, x10
+sw x11, 216(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha256sum1 x11, x10
+sw x11, 224(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha256sum1 x11, x10
+sw x11, 232(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha256sum1 x11, x10
+sw x11, 240(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha256sum1 x11, x10
+sw x11, 248(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha256sum1 x11, x10
+sw x11, 256(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha256sum1 x11, x10
+sw x11, 264(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha256sum1 x11, x10
+sw x11, 272(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha256sum1 x11, x10
+sw x11, 280(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha256sum1 x11, x10
+sw x11, 288(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha256sum1 x11, x10
+sw x11, 296(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha256sum1 x11, x10
+sw x11, 304(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha256sum1 x11, x10
+sw x11, 312(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha256sum1 x11, x10
+sw x11, 320(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha256sum1 x11, x10
+sw x11, 328(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha256sum1 x11, x10
+sw x11, 336(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha256sum1 x11, x10
+sw x11, 344(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha256sum1 x11, x10
+sw x11, 352(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha256sum1 x11, x10
+sw x11, 360(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha256sum1 x11, x10
+sw x11, 368(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha256sum1 x11, x10
+sw x11, 376(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha256sum1 x11, x10
+sw x11, 384(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha256sum1 x11, x10
+sw x11, 392(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha256sum1 x11, x10
+sw x11, 400(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha256sum1 x11, x10
+sw x11, 408(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha256sum1 x11, x10
+sw x11, 416(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha256sum1 x11, x10
+sw x11, 424(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha256sum1 x11, x10
+sw x11, 432(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha256sum1 x11, x10
+sw x11, 440(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha256sum1 x11, x10
+sw x11, 448(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha256sum1 x11, x10
+sw x11, 456(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha256sum1 x11, x10
+sw x11, 464(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha256sum1 x11, x10
+sw x11, 472(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha256sum1 x11, x10
+sw x11, 480(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha256sum1 x11, x10
+sw x11, 488(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha256sum1 x11, x10
+sw x11, 496(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha256sum1 x11, x10
+sw x11, 504(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha256sum1 x11, x10
+sw x11, 512(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha256sum1 x11, x10
+sw x11, 520(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha256sum1 x11, x10
+sw x11, 528(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha256sum1 x11, x10
+sw x11, 536(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha256sum1 x11, x10
+sw x11, 544(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha256sum1 x11, x10
+sw x11, 552(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha256sum1 x11, x10
+sw x11, 560(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha256sum1 x11, x10
+sw x11, 568(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha256sum1 x11, x10
+sw x11, 576(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha256sum1 x11, x10
+sw x11, 584(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha256sum1 x11, x10
+sw x11, 592(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha256sum1 x11, x10
+sw x11, 600(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha256sum1 x11, x10
+sw x11, 608(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha256sum1 x11, x10
+sw x11, 616(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha256sum1 x11, x10
+sw x11, 624(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha256sum1 x11, x10
+sw x11, 632(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha256sum1 x11, x10
+sw x11, 640(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha256sum1 x11, x10
+sw x11, 648(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha256sum1 x11, x10
+sw x11, 656(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha256sum1 x11, x10
+sw x11, 664(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha256sum1 x11, x10
+sw x11, 672(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha256sum1 x11, x10
+sw x11, 680(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha256sum1 x11, x10
+sw x11, 688(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha256sum1 x11, x10
+sw x11, 696(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha256sum1 x11, x10
+sw x11, 704(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha256sum1 x11, x10
+sw x11, 712(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha256sum1 x11, x10
+sw x11, 720(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha256sum1 x11, x10
+sw x11, 728(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha256sum1 x11, x10
+sw x11, 736(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha256sum1 x11, x10
+sw x11, 744(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha256sum1 x11, x10
+sw x11, 752(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha256sum1 x11, x10
+sw x11, 760(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha256sum1 x11, x10
+sw x11, 768(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha256sum1 x11, x10
+sw x11, 776(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha256sum1 x11, x10
+sw x11, 784(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha256sum1 x11, x10
+sw x11, 792(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha256sum1 x11, x10
+sw x11, 800(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha256sum1 x11, x10
+sw x11, 808(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha256sum1 x11, x10
+sw x11, 816(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha256sum1 x11, x10
+sw x11, 824(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha256sum1 x11, x10
+sw x11, 832(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha256sum1 x11, x10
+sw x11, 840(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha256sum1 x11, x10
+sw x11, 848(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha256sum1 x11, x10
+sw x11, 856(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha256sum1 x11, x10
+sw x11, 864(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha256sum1 x11, x10
+sw x11, 872(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha256sum1 x11, x10
+sw x11, 880(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha256sum1 x11, x10
+sw x11, 888(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha256sum1 x11, x10
+sw x11, 896(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha256sum1 x11, x10
+sw x11, 904(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha256sum1 x11, x10
+sw x11, 912(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha256sum1 x11, x10
+sw x11, 920(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha256sum1 x11, x10
+sw x11, 928(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha256sum1 x11, x10
+sw x11, 936(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha256sum1 x11, x10
+sw x11, 944(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha256sum1 x11, x10
+sw x11, 952(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha256sum1 x11, x10
+sw x11, 960(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha256sum1 x11, x10
+sw x11, 968(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha256sum1 x11, x10
+sw x11, 976(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha256sum1 x11, x10
+sw x11, 984(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha256sum1 x11, x10
+sw x11, 992(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha256sum1 x11, x10
+sw x11, 1000(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18446462598732840959, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xfffeffffffffffff;
+li x10, 0xfffeffffffffffff
+sha256sum1 x11, x10
+sw x11, 1008(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446743798831644671, 
+// opcode: sha256sum1 ; op1:x10; dest:x11; op1val:0xffffffbfffffffff;
+li x10, 0xffffffbfffffffff
+sha256sum1 x11, x10
+sw x11, 1016(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x3_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S
new file mode 100644
index 000000000..834741471
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha256sum1 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha256sum1 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha256sum1 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha256sum1 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha256sum1 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha256sum1 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha256sum1 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha256sum1 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha256sum1 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha256sum1 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha256sum1 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha256sum1 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha256sum1 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha256sum1 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha256sum1 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha256sum1 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha256sum1 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha256sum1 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha256sum1 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha256sum1 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha256sum1 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha256sum1 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha256sum1 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha256sum1 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha256sum1 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha256sum1 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha256sum1 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha256sum1 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha256sum1 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha256sum1 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha256sum1 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha256sum1 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha256sum1 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha256sum1 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha256sum1 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha256sum1 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha256sum1 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha256sum1 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha256sum1 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha256sum1 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha256sum1 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha256sum1 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha256sum1 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha256sum1 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha256sum1 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha256sum1 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha256sum1 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha256sum1 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha256sum1 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha256sum1 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha256sum1 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha256sum1 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha256sum1 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha256sum1 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha256sum1 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha256sum1 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha256sum1 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha256sum1 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha256sum1 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha256sum1 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha256sum1 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha256sum1 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha256sum1 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha256sum1 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha256sum1 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha256sum1 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha256sum1 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha256sum1 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha256sum1 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha256sum1 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha256sum1 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha256sum1 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha256sum1 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha256sum1 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha256sum1 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha256sum1 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha256sum1 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha256sum1 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha256sum1 & the result back into xor
+// opcode: sha256sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha256sum1 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha256sum1 & the result back into not
+// opcode: sha256sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha256sum1 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha256sum1 & the result back into add
+// opcode: sha256sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha256sum1 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S
new file mode 100644
index 000000000..8e2c36a0d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha256sum1-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha256sum1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha256sum1 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha256sum1 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha256sum1 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha256sum1 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha256sum1 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha256sum1 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha256sum1 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha256sum1 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha256sum1 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha256sum1 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha256sum1 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha256sum1 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha256sum1 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha256sum1 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha256sum1 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha256sum1 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha256sum1 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha256sum1 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha256sum1 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha256sum1 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha256sum1 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha256sum1 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha256sum1 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha256sum1 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha256sum1 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha256sum1 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha256sum1 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha256sum1; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha256sum1 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S
new file mode 100644
index 000000000..654ce3e25
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha512sig0 instruction of the RISC-V  extension for the sha512sig0 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnh.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 != rd, rs1==x12, rd==x21, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha512sig0 ; op1:x12; dest:x21; op1val:0x75a3adb3254a9493;
+li x12, 0x75a3adb3254a9493
+sha512sig0 x21, x12
+sw x21, 0(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x21, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x11, rd==x11, rs1_val == 9223372036854775807, 
+// opcode: sha512sig0 ; op1:x11; dest:x11; op1val:0x7fffffffffffffff;
+li x11, 0x7fffffffffffffff
+sha512sig0 x11, x11
+sw x11, 8(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x11, 0x0000000000000000)
+
+inst_2:
+// rs1==x24, rd==x23, rs1_val == 13835058055282163711, 
+// opcode: sha512sig0 ; op1:x24; dest:x23; op1val:0xbfffffffffffffff;
+li x24, 0xbfffffffffffffff
+sha512sig0 x23, x24
+sw x23, 16(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x23, 0x0000000000000000)
+
+inst_3:
+// rs1==x10, rd==x26, rs1_val == 16140901064495857663, 
+// opcode: sha512sig0 ; op1:x10; dest:x26; op1val:0xdfffffffffffffff;
+li x10, 0xdfffffffffffffff
+sha512sig0 x26, x10
+sw x26, 24(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x26, 0x0000000000000000)
+
+inst_4:
+// rs1==x18, rd==x28, rs1_val == 17293822569102704639, 
+// opcode: sha512sig0 ; op1:x18; dest:x28; op1val:0xefffffffffffffff;
+li x18, 0xefffffffffffffff
+sha512sig0 x28, x18
+sw x28, 32(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x28, 0x0000000000000000)
+
+inst_5:
+// rs1==x7, rd==x9, rs1_val == 17870283321406128127, 
+// opcode: sha512sig0 ; op1:x7; dest:x9; op1val:0xf7ffffffffffffff;
+li x7, 0xf7ffffffffffffff
+sha512sig0 x9, x7
+sw x9, 40(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x9, 0x0000000000000000)
+
+inst_6:
+// rs1==x29, rd==x5, rs1_val == 18158513697557839871, 
+// opcode: sha512sig0 ; op1:x29; dest:x5; op1val:0xfbffffffffffffff;
+li x29, 0xfbffffffffffffff
+sha512sig0 x5, x29
+sw x5, 48(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x5, 0x0000000000000000)
+
+inst_7:
+// rs1==x1, rd==x0, rs1_val == 18302628885633695743, 
+// opcode: sha512sig0 ; op1:x1; dest:x0; op1val:0xfdffffffffffffff;
+li x1, 0xfdffffffffffffff
+sha512sig0 x0, x1
+sw x0, 56(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x0, 0x0000000000000000)
+
+inst_8:
+// rs1==x8, rd==x20, rs1_val == 18374686479671623679, 
+// opcode: sha512sig0 ; op1:x8; dest:x20; op1val:0xfeffffffffffffff;
+li x8, 0xfeffffffffffffff
+sha512sig0 x20, x8
+sw x20, 64(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x20, 0x0000000000000000)
+
+inst_9:
+// rs1==x31, rd==x27, rs1_val == 18410715276690587647, 
+// opcode: sha512sig0 ; op1:x31; dest:x27; op1val:0xff7fffffffffffff;
+li x31, 0xff7fffffffffffff
+sha512sig0 x27, x31
+sw x27, 72(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x27, 0x0000000000000000)
+
+inst_10:
+// rs1==x3, rd==x14, rs1_val == 18428729675200069631, 
+// opcode: sha512sig0 ; op1:x3; dest:x14; op1val:0xffbfffffffffffff;
+li x3, 0xffbfffffffffffff
+sha512sig0 x14, x3
+sw x14, 80(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x14, 0x0000000000000000)
+
+inst_11:
+// rs1==x14, rd==x10, rs1_val == 18437736874454810623, 
+// opcode: sha512sig0 ; op1:x14; dest:x10; op1val:0xffdfffffffffffff;
+li x14, 0xffdfffffffffffff
+sha512sig0 x10, x14
+sw x10, 88(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x10, 0x0000000000000000)
+
+inst_12:
+// rs1==x23, rd==x19, rs1_val == 18442240474082181119, 
+// opcode: sha512sig0 ; op1:x23; dest:x19; op1val:0xffefffffffffffff;
+li x23, 0xffefffffffffffff
+sha512sig0 x19, x23
+sw x19, 96(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x19, 0x0000000000000000)
+
+inst_13:
+// rs1==x15, rd==x3, rs1_val == 18444492273895866367, 
+// opcode: sha512sig0 ; op1:x15; dest:x3; op1val:0xfff7ffffffffffff;
+li x15, 0xfff7ffffffffffff
+sha512sig0 x3, x15
+sw x3, 104(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x3, 0x0000000000000000)
+
+inst_14:
+// rs1==x6, rd==x16, rs1_val == 18445618173802708991, 
+// opcode: sha512sig0 ; op1:x6; dest:x16; op1val:0xfffbffffffffffff;
+li x6, 0xfffbffffffffffff
+sha512sig0 x16, x6
+sw x16, 112(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x16, 0x0000000000000000)
+
+inst_15:
+// rs1==x20, rd==x1, rs1_val == 18446181123756130303, 
+// opcode: sha512sig0 ; op1:x20; dest:x1; op1val:0xfffdffffffffffff;
+li x20, 0xfffdffffffffffff
+sha512sig0 x1, x20
+sw x1, 120(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x1, 0x0000000000000000)
+
+inst_16:
+// rs1==x25, rd==x22, rs1_val == 18446462598732840959, 
+// opcode: sha512sig0 ; op1:x25; dest:x22; op1val:0xfffeffffffffffff;
+li x25, 0xfffeffffffffffff
+sha512sig0 x22, x25
+sw x22, 128(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x22, 0x0000000000000000)
+
+inst_17:
+// rs1==x27, rd==x8, rs1_val == 18446603336221196287, 
+// opcode: sha512sig0 ; op1:x27; dest:x8; op1val:0xffff7fffffffffff;
+li x27, 0xffff7fffffffffff
+sha512sig0 x8, x27
+sw x8, 136(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x8, 0x0000000000000000)
+
+inst_18:
+// rs1==x9, rd==x6, rs1_val == 18446673704965373951, 
+// opcode: sha512sig0 ; op1:x9; dest:x6; op1val:0xffffbfffffffffff;
+li x9, 0xffffbfffffffffff
+sha512sig0 x6, x9
+sw x6, 144(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x6, 0x0000000000000000)
+
+inst_19:
+// rs1==x19, rd==x4, rs1_val == 18446708889337462783, 
+// opcode: sha512sig0 ; op1:x19; dest:x4; op1val:0xffffdfffffffffff;
+li x19, 0xffffdfffffffffff
+sha512sig0 x4, x19
+sw x4, 152(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x13, x4, 0x0000000000000000)
+
+inst_20:
+// rs1==x28, rd==x30, rs1_val == 18446726481523507199, 
+// opcode: sha512sig0 ; op1:x28; dest:x30; op1val:0xffffefffffffffff;
+li x28, 0xffffefffffffffff
+sha512sig0 x30, x28
+sw x30, 160(x2)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x30, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_21:
+// rs1==x0, rd==x29, rs1_val == 18446735277616529407, 
+// opcode: sha512sig0 ; op1:x0; dest:x29; op1val:0x0;
+li x0, 0x0
+sha512sig0 x29, x0
+sw x29, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x29, 0x0000000000000000)
+
+inst_22:
+// rs1==x13, rd==x7, rs1_val == 18446739675663040511, 
+// opcode: sha512sig0 ; op1:x13; dest:x7; op1val:0xfffffbffffffffff;
+li x13, 0xfffffbffffffffff
+sha512sig0 x7, x13
+sw x7, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x7, 0x0000000000000000)
+
+inst_23:
+// rs1==x17, rd==x25, rs1_val == 18446741874686296063, 
+// opcode: sha512sig0 ; op1:x17; dest:x25; op1val:0xfffffdffffffffff;
+li x17, 0xfffffdffffffffff
+sha512sig0 x25, x17
+sw x25, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x25, 0x0000000000000000)
+
+inst_24:
+// rs1==x4, rd==x12, rs1_val == 18446742974197923839, 
+// opcode: sha512sig0 ; op1:x4; dest:x12; op1val:0xfffffeffffffffff;
+li x4, 0xfffffeffffffffff
+sha512sig0 x12, x4
+sw x12, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x12, 0x0000000000000000)
+
+inst_25:
+// rs1==x2, rd==x18, rs1_val == 18446743523953737727, 
+// opcode: sha512sig0 ; op1:x2; dest:x18; op1val:0xffffff7fffffffff;
+li x2, 0xffffff7fffffffff
+sha512sig0 x18, x2
+sw x18, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x18, 0x0000000000000000)
+
+inst_26:
+// rs1==x30, rd==x13, rs1_val == 18446743798831644671, 
+// opcode: sha512sig0 ; op1:x30; dest:x13; op1val:0xffffffbfffffffff;
+li x30, 0xffffffbfffffffff
+sha512sig0 x13, x30
+sw x13, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x13, 0x0000000000000000)
+
+inst_27:
+// rs1==x22, rd==x31, rs1_val == 18446743936270598143, 
+// opcode: sha512sig0 ; op1:x22; dest:x31; op1val:0xffffffdfffffffff;
+li x22, 0xffffffdfffffffff
+sha512sig0 x31, x22
+sw x31, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x31, 0x0000000000000000)
+
+inst_28:
+// rs1==x5, rd==x17, rs1_val == 18446744004990074879, 
+// opcode: sha512sig0 ; op1:x5; dest:x17; op1val:0xffffffefffffffff;
+li x5, 0xffffffefffffffff
+sha512sig0 x17, x5
+sw x17, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x17, 0x0000000000000000)
+
+inst_29:
+// rs1==x21, rd==x24, rs1_val == 18446744039349813247, 
+// opcode: sha512sig0 ; op1:x21; dest:x24; op1val:0xfffffff7ffffffff;
+li x21, 0xfffffff7ffffffff
+sha512sig0 x24, x21
+sw x24, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x24, 0x0000000000000000)
+
+inst_30:
+// rs1==x16, rd==x2, rs1_val == 18446744056529682431, 
+// opcode: sha512sig0 ; op1:x16; dest:x2; op1val:0xfffffffbffffffff;
+li x16, 0xfffffffbffffffff
+sha512sig0 x2, x16
+sw x2, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x2, 0x0000000000000000)
+
+inst_31:
+// rs1==x26, rd==x15, rs1_val == 18446744065119617023, 
+// opcode: sha512sig0 ; op1:x26; dest:x15; op1val:0xfffffffdffffffff;
+li x26, 0xfffffffdffffffff
+sha512sig0 x15, x26
+sw x15, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x15, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha512sig0 x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha512sig0 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha512sig0 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha512sig0 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha512sig0 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha512sig0 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha512sig0 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha512sig0 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha512sig0 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha512sig0 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha512sig0 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha512sig0 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha512sig0 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha512sig0 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha512sig0 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha512sig0 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha512sig0 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha512sig0 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha512sig0 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha512sig0 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha512sig0 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha512sig0 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha512sig0 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha512sig0 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha512sig0 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha512sig0 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha512sig0 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha512sig0 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha512sig0 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha512sig0 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha512sig0 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha512sig0 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha512sig0 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha512sig0 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha512sig0 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha512sig0 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha512sig0 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha512sig0 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha512sig0 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha512sig0 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha512sig0 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha512sig0 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha512sig0 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha512sig0 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha512sig0 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha512sig0 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha512sig0 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha512sig0 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha512sig0 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha512sig0 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha512sig0 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha512sig0 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha512sig0 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha512sig0 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha512sig0 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha512sig0 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha512sig0 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha512sig0 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha512sig0 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha512sig0 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha512sig0 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha512sig0 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha512sig0 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha512sig0 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha512sig0 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha512sig0 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha512sig0 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha512sig0 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha512sig0 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha512sig0 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha512sig0 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha512sig0 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha512sig0 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha512sig0 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha512sig0 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha512sig0 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha512sig0 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha512sig0 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha512sig0 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha512sig0 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha512sig0 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha512sig0 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha512sig0 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha512sig0 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha512sig0 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha512sig0 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha512sig0 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha512sig0 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha512sig0 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha512sig0 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha512sig0 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha512sig0 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha512sig0 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha512sig0 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha512sig0 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha512sig0 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha512sig0 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha512sig0 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha512sig0 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha512sig0 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha512sig0 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha512sig0 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha512sig0 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha512sig0 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha512sig0 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha512sig0 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha512sig0 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha512sig0 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha512sig0 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha512sig0 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha512sig0 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha512sig0 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha512sig0 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha512sig0 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha512sig0 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha512sig0 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18302628885633695743, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfdffffffffffffff;
+li x10, 0xfdffffffffffffff
+sha512sig0 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446735277616529407, 
+// opcode: sha512sig0 ; op1:x10; dest:x11; op1val:0xfffff7ffffffffff;
+li x10, 0xfffff7ffffffffff
+sha512sig0 x11, x10
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 21*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 129*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S
new file mode 100644
index 000000000..93a6a38a7
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha512sig0 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha512sig0 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha512sig0 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha512sig0 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha512sig0 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha512sig0 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha512sig0 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha512sig0 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha512sig0 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha512sig0 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha512sig0 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha512sig0 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha512sig0 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha512sig0 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha512sig0 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha512sig0 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha512sig0 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha512sig0 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha512sig0 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha512sig0 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha512sig0 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha512sig0 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha512sig0 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha512sig0 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha512sig0 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha512sig0 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha512sig0 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha512sig0 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha512sig0 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha512sig0 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha512sig0 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha512sig0 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha512sig0 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha512sig0 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha512sig0 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha512sig0 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha512sig0 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha512sig0 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha512sig0 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha512sig0 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha512sig0 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha512sig0 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha512sig0 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha512sig0 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha512sig0 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha512sig0 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha512sig0 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha512sig0 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha512sig0 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha512sig0 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha512sig0 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha512sig0 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha512sig0 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha512sig0 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha512sig0 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha512sig0 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha512sig0 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha512sig0 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha512sig0 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha512sig0 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha512sig0 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha512sig0 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha512sig0 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha512sig0 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha512sig0 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha512sig0 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha512sig0 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha512sig0 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha512sig0 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha512sig0 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha512sig0 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha512sig0 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha512sig0 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha512sig0 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha512sig0 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha512sig0 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha512sig0 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha512sig0 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha512sig0 & the result back into xor
+// opcode: sha512sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha512sig0 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha512sig0 & the result back into not
+// opcode: sha512sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha512sig0 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha512sig0 & the result back into add
+// opcode: sha512sig0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha512sig0 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S
new file mode 100644
index 000000000..2eea575e1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig0-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha512sig0 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha512sig0 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha512sig0 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha512sig0 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha512sig0 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha512sig0 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha512sig0 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha512sig0 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha512sig0 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha512sig0 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha512sig0 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha512sig0 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha512sig0 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha512sig0 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha512sig0 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha512sig0 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha512sig0 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha512sig0 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha512sig0 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha512sig0 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha512sig0 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha512sig0 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha512sig0 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha512sig0 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha512sig0 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha512sig0 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha512sig0 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha512sig0; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha512sig0 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S
new file mode 100644
index 000000000..200d8a8a1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha512sig1 instruction of the RISC-V  extension for the sha512sig1 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnh.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 != rd, rs1==x24, rd==x9, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha512sig1 ; op1:x24; dest:x9; op1val:0x75a3adb3254a9493;
+li x24, 0x75a3adb3254a9493
+sha512sig1 x9, x24
+sw x9, 0(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x9, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x16, rd==x16, rs1_val == 9223372036854775807, 
+// opcode: sha512sig1 ; op1:x16; dest:x16; op1val:0x7fffffffffffffff;
+li x16, 0x7fffffffffffffff
+sha512sig1 x16, x16
+sw x16, 8(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x16, 0x0000000000000000)
+
+inst_2:
+// rs1==x13, rd==x7, rs1_val == 13835058055282163711, 
+// opcode: sha512sig1 ; op1:x13; dest:x7; op1val:0xbfffffffffffffff;
+li x13, 0xbfffffffffffffff
+sha512sig1 x7, x13
+sw x7, 16(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x7, 0x0000000000000000)
+
+inst_3:
+// rs1==x31, rd==x15, rs1_val == 16140901064495857663, 
+// opcode: sha512sig1 ; op1:x31; dest:x15; op1val:0xdfffffffffffffff;
+li x31, 0xdfffffffffffffff
+sha512sig1 x15, x31
+sw x15, 24(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x15, 0x0000000000000000)
+
+inst_4:
+// rs1==x8, rd==x31, rs1_val == 17293822569102704639, 
+// opcode: sha512sig1 ; op1:x8; dest:x31; op1val:0xefffffffffffffff;
+li x8, 0xefffffffffffffff
+sha512sig1 x31, x8
+sw x31, 32(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x31, 0x0000000000000000)
+
+inst_5:
+// rs1==x17, rd==x27, rs1_val == 17870283321406128127, 
+// opcode: sha512sig1 ; op1:x17; dest:x27; op1val:0xf7ffffffffffffff;
+li x17, 0xf7ffffffffffffff
+sha512sig1 x27, x17
+sw x27, 40(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x27, 0x0000000000000000)
+
+inst_6:
+// rs1==x14, rd==x0, rs1_val == 18158513697557839871, 
+// opcode: sha512sig1 ; op1:x14; dest:x0; op1val:0xfbffffffffffffff;
+li x14, 0xfbffffffffffffff
+sha512sig1 x0, x14
+sw x0, 48(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x0, 0x0000000000000000)
+
+inst_7:
+// rs1==x18, rd==x13, rs1_val == 18302628885633695743, 
+// opcode: sha512sig1 ; op1:x18; dest:x13; op1val:0xfdffffffffffffff;
+li x18, 0xfdffffffffffffff
+sha512sig1 x13, x18
+sw x13, 56(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x13, 0x0000000000000000)
+
+inst_8:
+// rs1==x27, rd==x18, rs1_val == 18374686479671623679, 
+// opcode: sha512sig1 ; op1:x27; dest:x18; op1val:0xfeffffffffffffff;
+li x27, 0xfeffffffffffffff
+sha512sig1 x18, x27
+sw x18, 64(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x18, 0x0000000000000000)
+
+inst_9:
+// rs1==x4, rd==x26, rs1_val == 18410715276690587647, 
+// opcode: sha512sig1 ; op1:x4; dest:x26; op1val:0xff7fffffffffffff;
+li x4, 0xff7fffffffffffff
+sha512sig1 x26, x4
+sw x26, 72(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x26, 0x0000000000000000)
+
+inst_10:
+// rs1==x15, rd==x1, rs1_val == 18428729675200069631, 
+// opcode: sha512sig1 ; op1:x15; dest:x1; op1val:0xffbfffffffffffff;
+li x15, 0xffbfffffffffffff
+sha512sig1 x1, x15
+sw x1, 80(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x1, 0x0000000000000000)
+
+inst_11:
+// rs1==x20, rd==x25, rs1_val == 18437736874454810623, 
+// opcode: sha512sig1 ; op1:x20; dest:x25; op1val:0xffdfffffffffffff;
+li x20, 0xffdfffffffffffff
+sha512sig1 x25, x20
+sw x25, 88(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x25, 0x0000000000000000)
+
+inst_12:
+// rs1==x22, rd==x29, rs1_val == 18442240474082181119, 
+// opcode: sha512sig1 ; op1:x22; dest:x29; op1val:0xffefffffffffffff;
+li x22, 0xffefffffffffffff
+sha512sig1 x29, x22
+sw x29, 96(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x29, 0x0000000000000000)
+
+inst_13:
+// rs1==x5, rd==x20, rs1_val == 18444492273895866367, 
+// opcode: sha512sig1 ; op1:x5; dest:x20; op1val:0xfff7ffffffffffff;
+li x5, 0xfff7ffffffffffff
+sha512sig1 x20, x5
+sw x20, 104(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x20, 0x0000000000000000)
+
+inst_14:
+// rs1==x12, rd==x19, rs1_val == 18445618173802708991, 
+// opcode: sha512sig1 ; op1:x12; dest:x19; op1val:0xfffbffffffffffff;
+li x12, 0xfffbffffffffffff
+sha512sig1 x19, x12
+sw x19, 112(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x19, 0x0000000000000000)
+
+inst_15:
+// rs1==x30, rd==x12, rs1_val == 18446181123756130303, 
+// opcode: sha512sig1 ; op1:x30; dest:x12; op1val:0xfffdffffffffffff;
+li x30, 0xfffdffffffffffff
+sha512sig1 x12, x30
+sw x12, 120(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x12, 0x0000000000000000)
+
+inst_16:
+// rs1==x19, rd==x28, rs1_val == 18446462598732840959, 
+// opcode: sha512sig1 ; op1:x19; dest:x28; op1val:0xfffeffffffffffff;
+li x19, 0xfffeffffffffffff
+sha512sig1 x28, x19
+sw x28, 128(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x28, 0x0000000000000000)
+
+inst_17:
+// rs1==x21, rd==x22, rs1_val == 18446603336221196287, 
+// opcode: sha512sig1 ; op1:x21; dest:x22; op1val:0xffff7fffffffffff;
+li x21, 0xffff7fffffffffff
+sha512sig1 x22, x21
+sw x22, 136(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x22, 0x0000000000000000)
+
+inst_18:
+// rs1==x2, rd==x30, rs1_val == 18446673704965373951, 
+// opcode: sha512sig1 ; op1:x2; dest:x30; op1val:0xffffbfffffffffff;
+li x2, 0xffffbfffffffffff
+sha512sig1 x30, x2
+sw x30, 144(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x30, 0x0000000000000000)
+
+inst_19:
+// rs1==x28, rd==x8, rs1_val == 18446708889337462783, 
+// opcode: sha512sig1 ; op1:x28; dest:x8; op1val:0xffffdfffffffffff;
+li x28, 0xffffdfffffffffff
+sha512sig1 x8, x28
+sw x8, 152(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x8, 0x0000000000000000)
+
+inst_20:
+// rs1==x10, rd==x4, rs1_val == 18446726481523507199, 
+// opcode: sha512sig1 ; op1:x10; dest:x4; op1val:0xffffefffffffffff;
+li x10, 0xffffefffffffffff
+sha512sig1 x4, x10
+sw x4, 160(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x4, 0x0000000000000000)
+
+inst_21:
+// rs1==x3, rd==x14, rs1_val == 18446735277616529407, 
+// opcode: sha512sig1 ; op1:x3; dest:x14; op1val:0xfffff7ffffffffff;
+li x3, 0xfffff7ffffffffff
+sha512sig1 x14, x3
+sw x14, 168(x6)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x14, 0x0000000000000000)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_22:
+// rs1==x9, rd==x11, rs1_val == 18446739675663040511, 
+// opcode: sha512sig1 ; op1:x9; dest:x11; op1val:0xfffffbffffffffff;
+li x9, 0xfffffbffffffffff
+sha512sig1 x11, x9
+sw x11, 0(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_23:
+// rs1==x6, rd==x21, rs1_val == 18446741874686296063, 
+// opcode: sha512sig1 ; op1:x6; dest:x21; op1val:0xfffffdffffffffff;
+li x6, 0xfffffdffffffffff
+sha512sig1 x21, x6
+sw x21, 8(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x21, 0x0000000000000000)
+
+inst_24:
+// rs1==x26, rd==x5, rs1_val == 18446742974197923839, 
+// opcode: sha512sig1 ; op1:x26; dest:x5; op1val:0xfffffeffffffffff;
+li x26, 0xfffffeffffffffff
+sha512sig1 x5, x26
+sw x5, 16(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x5, 0x0000000000000000)
+
+inst_25:
+// rs1==x11, rd==x2, rs1_val == 18446743523953737727, 
+// opcode: sha512sig1 ; op1:x11; dest:x2; op1val:0xffffff7fffffffff;
+li x11, 0xffffff7fffffffff
+sha512sig1 x2, x11
+sw x2, 24(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x2, 0x0000000000000000)
+
+inst_26:
+// rs1==x1, rd==x24, rs1_val == 18446743798831644671, 
+// opcode: sha512sig1 ; op1:x1; dest:x24; op1val:0xffffffbfffffffff;
+li x1, 0xffffffbfffffffff
+sha512sig1 x24, x1
+sw x24, 32(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x24, 0x0000000000000000)
+
+inst_27:
+// rs1==x0, rd==x17, rs1_val == 18446743936270598143, 
+// opcode: sha512sig1 ; op1:x0; dest:x17; op1val:0x0;
+li x0, 0x0
+sha512sig1 x17, x0
+sw x17, 40(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x17, 0x0000000000000000)
+
+inst_28:
+// rs1==x7, rd==x10, rs1_val == 18446744004990074879, 
+// opcode: sha512sig1 ; op1:x7; dest:x10; op1val:0xffffffefffffffff;
+li x7, 0xffffffefffffffff
+sha512sig1 x10, x7
+sw x10, 48(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x10, 0x0000000000000000)
+
+inst_29:
+// rs1==x23, rd==x3, rs1_val == 18446744039349813247, 
+// opcode: sha512sig1 ; op1:x23; dest:x3; op1val:0xfffffff7ffffffff;
+li x23, 0xfffffff7ffffffff
+sha512sig1 x3, x23
+sw x3, 56(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x3, 0x0000000000000000)
+
+inst_30:
+// rs1==x25, rd==x23, rs1_val == 18446744056529682431, 
+// opcode: sha512sig1 ; op1:x25; dest:x23; op1val:0xfffffffbffffffff;
+li x25, 0xfffffffbffffffff
+sha512sig1 x23, x25
+sw x23, 64(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x23, 0x0000000000000000)
+
+inst_31:
+// rs1==x29, rd==x6, rs1_val == 18446744065119617023, 
+// opcode: sha512sig1 ; op1:x29; dest:x6; op1val:0xfffffffdffffffff;
+li x29, 0xfffffffdffffffff
+sha512sig1 x6, x29
+sw x6, 72(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x6, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha512sig1 x11, x10
+sw x11, 80(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha512sig1 x11, x10
+sw x11, 88(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha512sig1 x11, x10
+sw x11, 96(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha512sig1 x11, x10
+sw x11, 104(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha512sig1 x11, x10
+sw x11, 112(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha512sig1 x11, x10
+sw x11, 120(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha512sig1 x11, x10
+sw x11, 128(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha512sig1 x11, x10
+sw x11, 136(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha512sig1 x11, x10
+sw x11, 144(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha512sig1 x11, x10
+sw x11, 152(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha512sig1 x11, x10
+sw x11, 160(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha512sig1 x11, x10
+sw x11, 168(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha512sig1 x11, x10
+sw x11, 176(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha512sig1 x11, x10
+sw x11, 184(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha512sig1 x11, x10
+sw x11, 192(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha512sig1 x11, x10
+sw x11, 200(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha512sig1 x11, x10
+sw x11, 208(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha512sig1 x11, x10
+sw x11, 216(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha512sig1 x11, x10
+sw x11, 224(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha512sig1 x11, x10
+sw x11, 232(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha512sig1 x11, x10
+sw x11, 240(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha512sig1 x11, x10
+sw x11, 248(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha512sig1 x11, x10
+sw x11, 256(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha512sig1 x11, x10
+sw x11, 264(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha512sig1 x11, x10
+sw x11, 272(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha512sig1 x11, x10
+sw x11, 280(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha512sig1 x11, x10
+sw x11, 288(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha512sig1 x11, x10
+sw x11, 296(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha512sig1 x11, x10
+sw x11, 304(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha512sig1 x11, x10
+sw x11, 312(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha512sig1 x11, x10
+sw x11, 320(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha512sig1 x11, x10
+sw x11, 328(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha512sig1 x11, x10
+sw x11, 336(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha512sig1 x11, x10
+sw x11, 344(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha512sig1 x11, x10
+sw x11, 352(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha512sig1 x11, x10
+sw x11, 360(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha512sig1 x11, x10
+sw x11, 368(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha512sig1 x11, x10
+sw x11, 376(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha512sig1 x11, x10
+sw x11, 384(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha512sig1 x11, x10
+sw x11, 392(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha512sig1 x11, x10
+sw x11, 400(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha512sig1 x11, x10
+sw x11, 408(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha512sig1 x11, x10
+sw x11, 416(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha512sig1 x11, x10
+sw x11, 424(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha512sig1 x11, x10
+sw x11, 432(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha512sig1 x11, x10
+sw x11, 440(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha512sig1 x11, x10
+sw x11, 448(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha512sig1 x11, x10
+sw x11, 456(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha512sig1 x11, x10
+sw x11, 464(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha512sig1 x11, x10
+sw x11, 472(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha512sig1 x11, x10
+sw x11, 480(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha512sig1 x11, x10
+sw x11, 488(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha512sig1 x11, x10
+sw x11, 496(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha512sig1 x11, x10
+sw x11, 504(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha512sig1 x11, x10
+sw x11, 512(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha512sig1 x11, x10
+sw x11, 520(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha512sig1 x11, x10
+sw x11, 528(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha512sig1 x11, x10
+sw x11, 536(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha512sig1 x11, x10
+sw x11, 544(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha512sig1 x11, x10
+sw x11, 552(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha512sig1 x11, x10
+sw x11, 560(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha512sig1 x11, x10
+sw x11, 568(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha512sig1 x11, x10
+sw x11, 576(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha512sig1 x11, x10
+sw x11, 584(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha512sig1 x11, x10
+sw x11, 592(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha512sig1 x11, x10
+sw x11, 600(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha512sig1 x11, x10
+sw x11, 608(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha512sig1 x11, x10
+sw x11, 616(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha512sig1 x11, x10
+sw x11, 624(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha512sig1 x11, x10
+sw x11, 632(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha512sig1 x11, x10
+sw x11, 640(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha512sig1 x11, x10
+sw x11, 648(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha512sig1 x11, x10
+sw x11, 656(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha512sig1 x11, x10
+sw x11, 664(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha512sig1 x11, x10
+sw x11, 672(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha512sig1 x11, x10
+sw x11, 680(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha512sig1 x11, x10
+sw x11, 688(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha512sig1 x11, x10
+sw x11, 696(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha512sig1 x11, x10
+sw x11, 704(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha512sig1 x11, x10
+sw x11, 712(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha512sig1 x11, x10
+sw x11, 720(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha512sig1 x11, x10
+sw x11, 728(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha512sig1 x11, x10
+sw x11, 736(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha512sig1 x11, x10
+sw x11, 744(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha512sig1 x11, x10
+sw x11, 752(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha512sig1 x11, x10
+sw x11, 760(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha512sig1 x11, x10
+sw x11, 768(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha512sig1 x11, x10
+sw x11, 776(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha512sig1 x11, x10
+sw x11, 784(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha512sig1 x11, x10
+sw x11, 792(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha512sig1 x11, x10
+sw x11, 800(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha512sig1 x11, x10
+sw x11, 808(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha512sig1 x11, x10
+sw x11, 816(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha512sig1 x11, x10
+sw x11, 824(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha512sig1 x11, x10
+sw x11, 832(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha512sig1 x11, x10
+sw x11, 840(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha512sig1 x11, x10
+sw x11, 848(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha512sig1 x11, x10
+sw x11, 856(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha512sig1 x11, x10
+sw x11, 864(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha512sig1 x11, x10
+sw x11, 872(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha512sig1 x11, x10
+sw x11, 880(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha512sig1 x11, x10
+sw x11, 888(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha512sig1 x11, x10
+sw x11, 896(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha512sig1 x11, x10
+sw x11, 904(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha512sig1 x11, x10
+sw x11, 912(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha512sig1 x11, x10
+sw x11, 920(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha512sig1 x11, x10
+sw x11, 928(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha512sig1 x11, x10
+sw x11, 936(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha512sig1 x11, x10
+sw x11, 944(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha512sig1 x11, x10
+sw x11, 952(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha512sig1 x11, x10
+sw x11, 960(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha512sig1 x11, x10
+sw x11, 968(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha512sig1 x11, x10
+sw x11, 976(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha512sig1 x11, x10
+sw x11, 984(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha512sig1 x11, x10
+sw x11, 992(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha512sig1 x11, x10
+sw x11, 1000(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18158513697557839871, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xfbffffffffffffff;
+li x10, 0xfbffffffffffffff
+sha512sig1 x11, x10
+sw x11, 1008(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446743936270598143, 
+// opcode: sha512sig1 ; op1:x10; dest:x11; op1val:0xffffffdfffffffff;
+li x10, 0xffffffdfffffffff
+sha512sig1 x11, x10
+sw x11, 1016(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x8, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S
new file mode 100644
index 000000000..e5e7ee37a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha512sig1 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha512sig1 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha512sig1 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha512sig1 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha512sig1 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha512sig1 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha512sig1 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha512sig1 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha512sig1 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha512sig1 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha512sig1 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha512sig1 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha512sig1 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha512sig1 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha512sig1 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha512sig1 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha512sig1 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha512sig1 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha512sig1 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha512sig1 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha512sig1 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha512sig1 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha512sig1 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha512sig1 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha512sig1 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha512sig1 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha512sig1 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha512sig1 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha512sig1 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha512sig1 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha512sig1 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha512sig1 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha512sig1 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha512sig1 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha512sig1 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha512sig1 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha512sig1 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha512sig1 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha512sig1 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha512sig1 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha512sig1 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha512sig1 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha512sig1 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha512sig1 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha512sig1 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha512sig1 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha512sig1 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha512sig1 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha512sig1 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha512sig1 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha512sig1 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha512sig1 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha512sig1 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha512sig1 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha512sig1 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha512sig1 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha512sig1 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha512sig1 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha512sig1 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha512sig1 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha512sig1 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha512sig1 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha512sig1 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha512sig1 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha512sig1 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha512sig1 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha512sig1 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha512sig1 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha512sig1 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha512sig1 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha512sig1 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha512sig1 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha512sig1 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha512sig1 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha512sig1 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha512sig1 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha512sig1 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha512sig1 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha512sig1 & the result back into xor
+// opcode: sha512sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha512sig1 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha512sig1 & the result back into not
+// opcode: sha512sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha512sig1 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha512sig1 & the result back into add
+// opcode: sha512sig1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha512sig1 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S
new file mode 100644
index 000000000..b7bfa3a9e
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sig1-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sig1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha512sig1 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha512sig1 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha512sig1 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha512sig1 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha512sig1 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha512sig1 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha512sig1 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha512sig1 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha512sig1 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha512sig1 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha512sig1 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha512sig1 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha512sig1 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha512sig1 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha512sig1 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha512sig1 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha512sig1 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha512sig1 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha512sig1 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha512sig1 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha512sig1 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha512sig1 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha512sig1 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha512sig1 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha512sig1 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha512sig1 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha512sig1 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha512sig1; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha512sig1 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S
new file mode 100644
index 000000000..6c75a3a32
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha512sum0 instruction of the RISC-V  extension for the sha512sum0 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnh.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_SIGBASE( x9,signature_x9_1)
+
+inst_0:
+// rs1 != rd, rs1==x16, rd==x11, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha512sum0 ; op1:x16; dest:x11; op1val:0x75a3adb3254a9493;
+li x16, 0x75a3adb3254a9493
+sha512sum0 x11, x16
+sw x11, 0(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x11, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x10, rd==x10, rs1_val == 9223372036854775807, 
+// opcode: sha512sum0 ; op1:x10; dest:x10; op1val:0x7fffffffffffffff;
+li x10, 0x7fffffffffffffff
+sha512sum0 x10, x10
+sw x10, 8(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x10, 0x0000000000000000)
+
+inst_2:
+// rs1==x11, rd==x18, rs1_val == 13835058055282163711, 
+// opcode: sha512sum0 ; op1:x11; dest:x18; op1val:0xbfffffffffffffff;
+li x11, 0xbfffffffffffffff
+sha512sum0 x18, x11
+sw x18, 16(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x18, 0x0000000000000000)
+
+inst_3:
+// rs1==x13, rd==x19, rs1_val == 16140901064495857663, 
+// opcode: sha512sum0 ; op1:x13; dest:x19; op1val:0xdfffffffffffffff;
+li x13, 0xdfffffffffffffff
+sha512sum0 x19, x13
+sw x19, 24(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x19, 0x0000000000000000)
+
+inst_4:
+// rs1==x17, rd==x21, rs1_val == 17293822569102704639, 
+// opcode: sha512sum0 ; op1:x17; dest:x21; op1val:0xefffffffffffffff;
+li x17, 0xefffffffffffffff
+sha512sum0 x21, x17
+sw x21, 32(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x21, 0x0000000000000000)
+
+inst_5:
+// rs1==x14, rd==x31, rs1_val == 17870283321406128127, 
+// opcode: sha512sum0 ; op1:x14; dest:x31; op1val:0xf7ffffffffffffff;
+li x14, 0xf7ffffffffffffff
+sha512sum0 x31, x14
+sw x31, 40(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x31, 0x0000000000000000)
+
+inst_6:
+// rs1==x0, rd==x3, rs1_val == 18158513697557839871, 
+// opcode: sha512sum0 ; op1:x0; dest:x3; op1val:0x0;
+li x0, 0x0
+sha512sum0 x3, x0
+sw x3, 48(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x3, 0x0000000000000000)
+
+inst_7:
+// rs1==x28, rd==x20, rs1_val == 18302628885633695743, 
+// opcode: sha512sum0 ; op1:x28; dest:x20; op1val:0xfdffffffffffffff;
+li x28, 0xfdffffffffffffff
+sha512sum0 x20, x28
+sw x20, 56(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x20, 0x0000000000000000)
+
+inst_8:
+// rs1==x31, rd==x0, rs1_val == 18374686479671623679, 
+// opcode: sha512sum0 ; op1:x31; dest:x0; op1val:0xfeffffffffffffff;
+li x31, 0xfeffffffffffffff
+sha512sum0 x0, x31
+sw x0, 64(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x0, 0x0000000000000000)
+
+inst_9:
+// rs1==x4, rd==x26, rs1_val == 18410715276690587647, 
+// opcode: sha512sum0 ; op1:x4; dest:x26; op1val:0xff7fffffffffffff;
+li x4, 0xff7fffffffffffff
+sha512sum0 x26, x4
+sw x26, 72(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x26, 0x0000000000000000)
+
+inst_10:
+// rs1==x2, rd==x16, rs1_val == 18428729675200069631, 
+// opcode: sha512sum0 ; op1:x2; dest:x16; op1val:0xffbfffffffffffff;
+li x2, 0xffbfffffffffffff
+sha512sum0 x16, x2
+sw x16, 80(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x16, 0x0000000000000000)
+
+inst_11:
+// rs1==x1, rd==x8, rs1_val == 18437736874454810623, 
+// opcode: sha512sum0 ; op1:x1; dest:x8; op1val:0xffdfffffffffffff;
+li x1, 0xffdfffffffffffff
+sha512sum0 x8, x1
+sw x8, 88(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x8, 0x0000000000000000)
+
+inst_12:
+// rs1==x21, rd==x5, rs1_val == 18442240474082181119, 
+// opcode: sha512sum0 ; op1:x21; dest:x5; op1val:0xffefffffffffffff;
+li x21, 0xffefffffffffffff
+sha512sum0 x5, x21
+sw x5, 96(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x5, 0x0000000000000000)
+
+inst_13:
+// rs1==x25, rd==x23, rs1_val == 18444492273895866367, 
+// opcode: sha512sum0 ; op1:x25; dest:x23; op1val:0xfff7ffffffffffff;
+li x25, 0xfff7ffffffffffff
+sha512sum0 x23, x25
+sw x23, 104(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x23, 0x0000000000000000)
+
+inst_14:
+// rs1==x27, rd==x12, rs1_val == 18445618173802708991, 
+// opcode: sha512sum0 ; op1:x27; dest:x12; op1val:0xfffbffffffffffff;
+li x27, 0xfffbffffffffffff
+sha512sum0 x12, x27
+sw x12, 112(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x12, 0x0000000000000000)
+
+inst_15:
+// rs1==x20, rd==x7, rs1_val == 18446181123756130303, 
+// opcode: sha512sum0 ; op1:x20; dest:x7; op1val:0xfffdffffffffffff;
+li x20, 0xfffdffffffffffff
+sha512sum0 x7, x20
+sw x7, 120(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x7, 0x0000000000000000)
+
+inst_16:
+// rs1==x18, rd==x6, rs1_val == 18446462598732840959, 
+// opcode: sha512sum0 ; op1:x18; dest:x6; op1val:0xfffeffffffffffff;
+li x18, 0xfffeffffffffffff
+sha512sum0 x6, x18
+sw x6, 128(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x6, 0x0000000000000000)
+
+inst_17:
+// rs1==x24, rd==x29, rs1_val == 18446603336221196287, 
+// opcode: sha512sum0 ; op1:x24; dest:x29; op1val:0xffff7fffffffffff;
+li x24, 0xffff7fffffffffff
+sha512sum0 x29, x24
+sw x29, 136(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x15, x29, 0x0000000000000000)
+
+inst_18:
+// rs1==x22, rd==x25, rs1_val == 18446673704965373951, 
+// opcode: sha512sum0 ; op1:x22; dest:x25; op1val:0xffffbfffffffffff;
+li x22, 0xffffbfffffffffff
+sha512sum0 x25, x22
+sw x25, 144(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x25, 0x0000000000000000)
+RVTEST_SIGBASE( x16,signature_x16_0)
+
+inst_19:
+// rs1==x7, rd==x28, rs1_val == 18446708889337462783, 
+// opcode: sha512sum0 ; op1:x7; dest:x28; op1val:0xffffdfffffffffff;
+li x7, 0xffffdfffffffffff
+sha512sum0 x28, x7
+sw x28, 0(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x28, 0x0000000000000000)
+
+inst_20:
+// rs1==x8, rd==x9, rs1_val == 18446726481523507199, 
+// opcode: sha512sum0 ; op1:x8; dest:x9; op1val:0xffffefffffffffff;
+li x8, 0xffffefffffffffff
+sha512sum0 x9, x8
+sw x9, 8(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x9, 0x0000000000000000)
+
+inst_21:
+// rs1==x26, rd==x22, rs1_val == 18446735277616529407, 
+// opcode: sha512sum0 ; op1:x26; dest:x22; op1val:0xfffff7ffffffffff;
+li x26, 0xfffff7ffffffffff
+sha512sum0 x22, x26
+sw x22, 16(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x22, 0x0000000000000000)
+
+inst_22:
+// rs1==x12, rd==x14, rs1_val == 18446739675663040511, 
+// opcode: sha512sum0 ; op1:x12; dest:x14; op1val:0xfffffbffffffffff;
+li x12, 0xfffffbffffffffff
+sha512sum0 x14, x12
+sw x14, 24(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x14, 0x0000000000000000)
+
+inst_23:
+// rs1==x3, rd==x30, rs1_val == 18446741874686296063, 
+// opcode: sha512sum0 ; op1:x3; dest:x30; op1val:0xfffffdffffffffff;
+li x3, 0xfffffdffffffffff
+sha512sum0 x30, x3
+sw x30, 32(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x30, 0x0000000000000000)
+
+inst_24:
+// rs1==x9, rd==x4, rs1_val == 18446742974197923839, 
+// opcode: sha512sum0 ; op1:x9; dest:x4; op1val:0xfffffeffffffffff;
+li x9, 0xfffffeffffffffff
+sha512sum0 x4, x9
+sw x4, 40(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x4, 0x0000000000000000)
+
+inst_25:
+// rs1==x6, rd==x2, rs1_val == 18446743523953737727, 
+// opcode: sha512sum0 ; op1:x6; dest:x2; op1val:0xffffff7fffffffff;
+li x6, 0xffffff7fffffffff
+sha512sum0 x2, x6
+sw x2, 48(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x2, 0x0000000000000000)
+
+inst_26:
+// rs1==x29, rd==x1, rs1_val == 18446743798831644671, 
+// opcode: sha512sum0 ; op1:x29; dest:x1; op1val:0xffffffbfffffffff;
+li x29, 0xffffffbfffffffff
+sha512sum0 x1, x29
+sw x1, 56(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x1, 0x0000000000000000)
+
+inst_27:
+// rs1==x5, rd==x27, rs1_val == 18446743936270598143, 
+// opcode: sha512sum0 ; op1:x5; dest:x27; op1val:0xffffffdfffffffff;
+li x5, 0xffffffdfffffffff
+sha512sum0 x27, x5
+sw x27, 64(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x27, 0x0000000000000000)
+
+inst_28:
+// rs1==x19, rd==x17, rs1_val == 18446744004990074879, 
+// opcode: sha512sum0 ; op1:x19; dest:x17; op1val:0xffffffefffffffff;
+li x19, 0xffffffefffffffff
+sha512sum0 x17, x19
+sw x17, 72(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x17, 0x0000000000000000)
+
+inst_29:
+// rs1==x30, rd==x15, rs1_val == 18446744039349813247, 
+// opcode: sha512sum0 ; op1:x30; dest:x15; op1val:0xfffffff7ffffffff;
+li x30, 0xfffffff7ffffffff
+sha512sum0 x15, x30
+sw x15, 80(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x15, 0x0000000000000000)
+
+inst_30:
+// rs1==x15, rd==x24, rs1_val == 18446744056529682431, 
+// opcode: sha512sum0 ; op1:x15; dest:x24; op1val:0xfffffffbffffffff;
+li x15, 0xfffffffbffffffff
+sha512sum0 x24, x15
+sw x24, 88(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x24, 0x0000000000000000)
+
+inst_31:
+// rs1==x23, rd==x13, rs1_val == 18446744065119617023, 
+// opcode: sha512sum0 ; op1:x23; dest:x13; op1val:0xfffffffdffffffff;
+li x23, 0xfffffffdffffffff
+sha512sum0 x13, x23
+sw x13, 96(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x13, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha512sum0 x11, x10
+sw x11, 104(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha512sum0 x11, x10
+sw x11, 112(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha512sum0 x11, x10
+sw x11, 120(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha512sum0 x11, x10
+sw x11, 128(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha512sum0 x11, x10
+sw x11, 136(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha512sum0 x11, x10
+sw x11, 144(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha512sum0 x11, x10
+sw x11, 152(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha512sum0 x11, x10
+sw x11, 160(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha512sum0 x11, x10
+sw x11, 168(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha512sum0 x11, x10
+sw x11, 176(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha512sum0 x11, x10
+sw x11, 184(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha512sum0 x11, x10
+sw x11, 192(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha512sum0 x11, x10
+sw x11, 200(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha512sum0 x11, x10
+sw x11, 208(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha512sum0 x11, x10
+sw x11, 216(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha512sum0 x11, x10
+sw x11, 224(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha512sum0 x11, x10
+sw x11, 232(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha512sum0 x11, x10
+sw x11, 240(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha512sum0 x11, x10
+sw x11, 248(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha512sum0 x11, x10
+sw x11, 256(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha512sum0 x11, x10
+sw x11, 264(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha512sum0 x11, x10
+sw x11, 272(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha512sum0 x11, x10
+sw x11, 280(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha512sum0 x11, x10
+sw x11, 288(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha512sum0 x11, x10
+sw x11, 296(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha512sum0 x11, x10
+sw x11, 304(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha512sum0 x11, x10
+sw x11, 312(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha512sum0 x11, x10
+sw x11, 320(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha512sum0 x11, x10
+sw x11, 328(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha512sum0 x11, x10
+sw x11, 336(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha512sum0 x11, x10
+sw x11, 344(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha512sum0 x11, x10
+sw x11, 352(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha512sum0 x11, x10
+sw x11, 360(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha512sum0 x11, x10
+sw x11, 368(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha512sum0 x11, x10
+sw x11, 376(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha512sum0 x11, x10
+sw x11, 384(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha512sum0 x11, x10
+sw x11, 392(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha512sum0 x11, x10
+sw x11, 400(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha512sum0 x11, x10
+sw x11, 408(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha512sum0 x11, x10
+sw x11, 416(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha512sum0 x11, x10
+sw x11, 424(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha512sum0 x11, x10
+sw x11, 432(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha512sum0 x11, x10
+sw x11, 440(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha512sum0 x11, x10
+sw x11, 448(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha512sum0 x11, x10
+sw x11, 456(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha512sum0 x11, x10
+sw x11, 464(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha512sum0 x11, x10
+sw x11, 472(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha512sum0 x11, x10
+sw x11, 480(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha512sum0 x11, x10
+sw x11, 488(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha512sum0 x11, x10
+sw x11, 496(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha512sum0 x11, x10
+sw x11, 504(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha512sum0 x11, x10
+sw x11, 512(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha512sum0 x11, x10
+sw x11, 520(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha512sum0 x11, x10
+sw x11, 528(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha512sum0 x11, x10
+sw x11, 536(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha512sum0 x11, x10
+sw x11, 544(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha512sum0 x11, x10
+sw x11, 552(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha512sum0 x11, x10
+sw x11, 560(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha512sum0 x11, x10
+sw x11, 568(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha512sum0 x11, x10
+sw x11, 576(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha512sum0 x11, x10
+sw x11, 584(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha512sum0 x11, x10
+sw x11, 592(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha512sum0 x11, x10
+sw x11, 600(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha512sum0 x11, x10
+sw x11, 608(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha512sum0 x11, x10
+sw x11, 616(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha512sum0 x11, x10
+sw x11, 624(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha512sum0 x11, x10
+sw x11, 632(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha512sum0 x11, x10
+sw x11, 640(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha512sum0 x11, x10
+sw x11, 648(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha512sum0 x11, x10
+sw x11, 656(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha512sum0 x11, x10
+sw x11, 664(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha512sum0 x11, x10
+sw x11, 672(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha512sum0 x11, x10
+sw x11, 680(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha512sum0 x11, x10
+sw x11, 688(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha512sum0 x11, x10
+sw x11, 696(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha512sum0 x11, x10
+sw x11, 704(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha512sum0 x11, x10
+sw x11, 712(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha512sum0 x11, x10
+sw x11, 720(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha512sum0 x11, x10
+sw x11, 728(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha512sum0 x11, x10
+sw x11, 736(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha512sum0 x11, x10
+sw x11, 744(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha512sum0 x11, x10
+sw x11, 752(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha512sum0 x11, x10
+sw x11, 760(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha512sum0 x11, x10
+sw x11, 768(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha512sum0 x11, x10
+sw x11, 776(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha512sum0 x11, x10
+sw x11, 784(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha512sum0 x11, x10
+sw x11, 792(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha512sum0 x11, x10
+sw x11, 800(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha512sum0 x11, x10
+sw x11, 808(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha512sum0 x11, x10
+sw x11, 816(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha512sum0 x11, x10
+sw x11, 824(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha512sum0 x11, x10
+sw x11, 832(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha512sum0 x11, x10
+sw x11, 840(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha512sum0 x11, x10
+sw x11, 848(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha512sum0 x11, x10
+sw x11, 856(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha512sum0 x11, x10
+sw x11, 864(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha512sum0 x11, x10
+sw x11, 872(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha512sum0 x11, x10
+sw x11, 880(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha512sum0 x11, x10
+sw x11, 888(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha512sum0 x11, x10
+sw x11, 896(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha512sum0 x11, x10
+sw x11, 904(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha512sum0 x11, x10
+sw x11, 912(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha512sum0 x11, x10
+sw x11, 920(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha512sum0 x11, x10
+sw x11, 928(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha512sum0 x11, x10
+sw x11, 936(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha512sum0 x11, x10
+sw x11, 944(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha512sum0 x11, x10
+sw x11, 952(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha512sum0 x11, x10
+sw x11, 960(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha512sum0 x11, x10
+sw x11, 968(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha512sum0 x11, x10
+sw x11, 976(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha512sum0 x11, x10
+sw x11, 984(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha512sum0 x11, x10
+sw x11, 992(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha512sum0 x11, x10
+sw x11, 1000(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha512sum0 x11, x10
+sw x11, 1008(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha512sum0 x11, x10
+sw x11, 1016(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha512sum0 x11, x10
+sw x11, 1024(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18158513697557839871, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfbffffffffffffff;
+li x10, 0xfbffffffffffffff
+sha512sum0 x11, x10
+sw x11, 1032(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18374686479671623679, 
+// opcode: sha512sum0 ; op1:x10; dest:x11; op1val:0xfeffffffffffffff;
+li x10, 0xfeffffffffffffff
+sha512sum0 x11, x10
+sw x11, 1040(x16)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x9_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x9_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x16_0:
+    .fill 131*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S
new file mode 100644
index 000000000..4d71aa33d
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha512sum0 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha512sum0 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha512sum0 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha512sum0 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha512sum0 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha512sum0 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha512sum0 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha512sum0 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha512sum0 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha512sum0 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha512sum0 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha512sum0 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha512sum0 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha512sum0 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha512sum0 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha512sum0 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha512sum0 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha512sum0 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha512sum0 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha512sum0 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha512sum0 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha512sum0 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha512sum0 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha512sum0 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha512sum0 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha512sum0 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha512sum0 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha512sum0 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha512sum0 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha512sum0 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha512sum0 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha512sum0 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha512sum0 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha512sum0 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha512sum0 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha512sum0 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha512sum0 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha512sum0 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha512sum0 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha512sum0 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha512sum0 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha512sum0 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha512sum0 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha512sum0 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha512sum0 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha512sum0 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha512sum0 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha512sum0 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha512sum0 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha512sum0 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha512sum0 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha512sum0 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha512sum0 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha512sum0 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha512sum0 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha512sum0 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha512sum0 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha512sum0 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha512sum0 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha512sum0 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha512sum0 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha512sum0 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha512sum0 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha512sum0 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha512sum0 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha512sum0 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha512sum0 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha512sum0 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha512sum0 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha512sum0 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha512sum0 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha512sum0 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha512sum0 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha512sum0 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha512sum0 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha512sum0 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha512sum0 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha512sum0 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha512sum0 & the result back into xor
+// opcode: sha512sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha512sum0 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha512sum0 & the result back into not
+// opcode: sha512sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha512sum0 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha512sum0 & the result back into add
+// opcode: sha512sum0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha512sum0 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S
new file mode 100644
index 000000000..e1d7d2bc3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum0-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha512sum0 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha512sum0 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha512sum0 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha512sum0 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha512sum0 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha512sum0 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha512sum0 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha512sum0 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha512sum0 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha512sum0 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha512sum0 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha512sum0 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha512sum0 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha512sum0 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha512sum0 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha512sum0 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha512sum0 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha512sum0 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha512sum0 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha512sum0 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha512sum0 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha512sum0 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha512sum0 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha512sum0 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha512sum0 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha512sum0 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha512sum0 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha512sum0; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha512sum0 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S
new file mode 100644
index 000000000..d1bdc6f12
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sha512sum1 instruction of the RISC-V  extension for the sha512sum1 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKnh.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_0:
+// rs1 != rd, rs1==x13, rd==x6, rs1_val == 0x75a3adb3254a9493 
+// opcode: sha512sum1 ; op1:x13; dest:x6; op1val:0x75a3adb3254a9493;
+li x13, 0x75a3adb3254a9493
+sha512sum1 x6, x13
+sw x6, 0(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x6, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x24, rd==x24, rs1_val == 9223372036854775807, 
+// opcode: sha512sum1 ; op1:x24; dest:x24; op1val:0x7fffffffffffffff;
+li x24, 0x7fffffffffffffff
+sha512sum1 x24, x24
+sw x24, 8(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x24, 0x0000000000000000)
+
+inst_2:
+// rs1==x10, rd==x1, rs1_val == 13835058055282163711, 
+// opcode: sha512sum1 ; op1:x10; dest:x1; op1val:0xbfffffffffffffff;
+li x10, 0xbfffffffffffffff
+sha512sum1 x1, x10
+sw x1, 16(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x1, 0x0000000000000000)
+
+inst_3:
+// rs1==x5, rd==x27, rs1_val == 16140901064495857663, 
+// opcode: sha512sum1 ; op1:x5; dest:x27; op1val:0xdfffffffffffffff;
+li x5, 0xdfffffffffffffff
+sha512sum1 x27, x5
+sw x27, 24(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x27, 0x0000000000000000)
+
+inst_4:
+// rs1==x11, rd==x0, rs1_val == 17293822569102704639, 
+// opcode: sha512sum1 ; op1:x11; dest:x0; op1val:0xefffffffffffffff;
+li x11, 0xefffffffffffffff
+sha512sum1 x0, x11
+sw x0, 32(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x0, 0x0000000000000000)
+
+inst_5:
+// rs1==x26, rd==x30, rs1_val == 17870283321406128127, 
+// opcode: sha512sum1 ; op1:x26; dest:x30; op1val:0xf7ffffffffffffff;
+li x26, 0xf7ffffffffffffff
+sha512sum1 x30, x26
+sw x30, 40(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x30, 0x0000000000000000)
+
+inst_6:
+// rs1==x16, rd==x5, rs1_val == 18158513697557839871, 
+// opcode: sha512sum1 ; op1:x16; dest:x5; op1val:0xfbffffffffffffff;
+li x16, 0xfbffffffffffffff
+sha512sum1 x5, x16
+sw x5, 48(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x5, 0x0000000000000000)
+
+inst_7:
+// rs1==x19, rd==x23, rs1_val == 18302628885633695743, 
+// opcode: sha512sum1 ; op1:x19; dest:x23; op1val:0xfdffffffffffffff;
+li x19, 0xfdffffffffffffff
+sha512sum1 x23, x19
+sw x23, 56(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x23, 0x0000000000000000)
+
+inst_8:
+// rs1==x9, rd==x13, rs1_val == 18374686479671623679, 
+// opcode: sha512sum1 ; op1:x9; dest:x13; op1val:0xfeffffffffffffff;
+li x9, 0xfeffffffffffffff
+sha512sum1 x13, x9
+sw x13, 64(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x13, 0x0000000000000000)
+
+inst_9:
+// rs1==x17, rd==x8, rs1_val == 18410715276690587647, 
+// opcode: sha512sum1 ; op1:x17; dest:x8; op1val:0xff7fffffffffffff;
+li x17, 0xff7fffffffffffff
+sha512sum1 x8, x17
+sw x8, 72(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x8, 0x0000000000000000)
+
+inst_10:
+// rs1==x18, rd==x14, rs1_val == 18428729675200069631, 
+// opcode: sha512sum1 ; op1:x18; dest:x14; op1val:0xffbfffffffffffff;
+li x18, 0xffbfffffffffffff
+sha512sum1 x14, x18
+sw x14, 80(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x14, 0x0000000000000000)
+
+inst_11:
+// rs1==x29, rd==x7, rs1_val == 18437736874454810623, 
+// opcode: sha512sum1 ; op1:x29; dest:x7; op1val:0xffdfffffffffffff;
+li x29, 0xffdfffffffffffff
+sha512sum1 x7, x29
+sw x7, 88(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x7, 0x0000000000000000)
+
+inst_12:
+// rs1==x31, rd==x10, rs1_val == 18442240474082181119, 
+// opcode: sha512sum1 ; op1:x31; dest:x10; op1val:0xffefffffffffffff;
+li x31, 0xffefffffffffffff
+sha512sum1 x10, x31
+sw x10, 96(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x10, 0x0000000000000000)
+
+inst_13:
+// rs1==x15, rd==x3, rs1_val == 18444492273895866367, 
+// opcode: sha512sum1 ; op1:x15; dest:x3; op1val:0xfff7ffffffffffff;
+li x15, 0xfff7ffffffffffff
+sha512sum1 x3, x15
+sw x3, 104(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x3, 0x0000000000000000)
+
+inst_14:
+// rs1==x21, rd==x17, rs1_val == 18445618173802708991, 
+// opcode: sha512sum1 ; op1:x21; dest:x17; op1val:0xfffbffffffffffff;
+li x21, 0xfffbffffffffffff
+sha512sum1 x17, x21
+sw x17, 112(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x17, 0x0000000000000000)
+
+inst_15:
+// rs1==x14, rd==x26, rs1_val == 18446181123756130303, 
+// opcode: sha512sum1 ; op1:x14; dest:x26; op1val:0xfffdffffffffffff;
+li x14, 0xfffdffffffffffff
+sha512sum1 x26, x14
+sw x26, 120(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x26, 0x0000000000000000)
+
+inst_16:
+// rs1==x22, rd==x20, rs1_val == 18446462598732840959, 
+// opcode: sha512sum1 ; op1:x22; dest:x20; op1val:0xfffeffffffffffff;
+li x22, 0xfffeffffffffffff
+sha512sum1 x20, x22
+sw x20, 128(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x20, 0x0000000000000000)
+
+inst_17:
+// rs1==x30, rd==x15, rs1_val == 18446603336221196287, 
+// opcode: sha512sum1 ; op1:x30; dest:x15; op1val:0xffff7fffffffffff;
+li x30, 0xffff7fffffffffff
+sha512sum1 x15, x30
+sw x15, 136(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x15, 0x0000000000000000)
+
+inst_18:
+// rs1==x1, rd==x21, rs1_val == 18446673704965373951, 
+// opcode: sha512sum1 ; op1:x1; dest:x21; op1val:0xffffbfffffffffff;
+li x1, 0xffffbfffffffffff
+sha512sum1 x21, x1
+sw x21, 144(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x21, 0x0000000000000000)
+
+inst_19:
+// rs1==x0, rd==x12, rs1_val == 18446708889337462783, 
+// opcode: sha512sum1 ; op1:x0; dest:x12; op1val:0x0;
+li x0, 0x0
+sha512sum1 x12, x0
+sw x12, 152(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x2, x12, 0x0000000000000000)
+
+inst_20:
+// rs1==x8, rd==x2, rs1_val == 18446726481523507199, 
+// opcode: sha512sum1 ; op1:x8; dest:x2; op1val:0xffffefffffffffff;
+li x8, 0xffffefffffffffff
+sha512sum1 x2, x8
+sw x2, 160(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x2, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_21:
+// rs1==x2, rd==x29, rs1_val == 18446735277616529407, 
+// opcode: sha512sum1 ; op1:x2; dest:x29; op1val:0xfffff7ffffffffff;
+li x2, 0xfffff7ffffffffff
+sha512sum1 x29, x2
+sw x29, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x29, 0x0000000000000000)
+
+inst_22:
+// rs1==x3, rd==x31, rs1_val == 18446739675663040511, 
+// opcode: sha512sum1 ; op1:x3; dest:x31; op1val:0xfffffbffffffffff;
+li x3, 0xfffffbffffffffff
+sha512sum1 x31, x3
+sw x31, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x31, 0x0000000000000000)
+
+inst_23:
+// rs1==x25, rd==x28, rs1_val == 18446741874686296063, 
+// opcode: sha512sum1 ; op1:x25; dest:x28; op1val:0xfffffdffffffffff;
+li x25, 0xfffffdffffffffff
+sha512sum1 x28, x25
+sw x28, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x28, 0x0000000000000000)
+
+inst_24:
+// rs1==x7, rd==x4, rs1_val == 18446742974197923839, 
+// opcode: sha512sum1 ; op1:x7; dest:x4; op1val:0xfffffeffffffffff;
+li x7, 0xfffffeffffffffff
+sha512sum1 x4, x7
+sw x4, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x4, 0x0000000000000000)
+
+inst_25:
+// rs1==x20, rd==x25, rs1_val == 18446743523953737727, 
+// opcode: sha512sum1 ; op1:x20; dest:x25; op1val:0xffffff7fffffffff;
+li x20, 0xffffff7fffffffff
+sha512sum1 x25, x20
+sw x25, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x25, 0x0000000000000000)
+
+inst_26:
+// rs1==x6, rd==x11, rs1_val == 18446743798831644671, 
+// opcode: sha512sum1 ; op1:x6; dest:x11; op1val:0xffffffbfffffffff;
+li x6, 0xffffffbfffffffff
+sha512sum1 x11, x6
+sw x11, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_27:
+// rs1==x28, rd==x9, rs1_val == 18446743936270598143, 
+// opcode: sha512sum1 ; op1:x28; dest:x9; op1val:0xffffffdfffffffff;
+li x28, 0xffffffdfffffffff
+sha512sum1 x9, x28
+sw x9, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x9, 0x0000000000000000)
+
+inst_28:
+// rs1==x12, rd==x19, rs1_val == 18446744004990074879, 
+// opcode: sha512sum1 ; op1:x12; dest:x19; op1val:0xffffffefffffffff;
+li x12, 0xffffffefffffffff
+sha512sum1 x19, x12
+sw x19, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x19, 0x0000000000000000)
+
+inst_29:
+// rs1==x27, rd==x18, rs1_val == 18446744039349813247, 
+// opcode: sha512sum1 ; op1:x27; dest:x18; op1val:0xfffffff7ffffffff;
+li x27, 0xfffffff7ffffffff
+sha512sum1 x18, x27
+sw x18, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x18, 0x0000000000000000)
+
+inst_30:
+// rs1==x23, rd==x16, rs1_val == 18446744056529682431, 
+// opcode: sha512sum1 ; op1:x23; dest:x16; op1val:0xfffffffbffffffff;
+li x23, 0xfffffffbffffffff
+sha512sum1 x16, x23
+sw x16, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x16, 0x0000000000000000)
+
+inst_31:
+// rs1==x4, rd==x22, rs1_val == 18446744065119617023, 
+// opcode: sha512sum1 ; op1:x4; dest:x22; op1val:0xfffffffdffffffff;
+li x4, 0xfffffffdffffffff
+sha512sum1 x22, x4
+sw x22, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x22, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sha512sum1 x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sha512sum1 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sha512sum1 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sha512sum1 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sha512sum1 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sha512sum1 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sha512sum1 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sha512sum1 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sha512sum1 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sha512sum1 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sha512sum1 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sha512sum1 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sha512sum1 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sha512sum1 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sha512sum1 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sha512sum1 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sha512sum1 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sha512sum1 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sha512sum1 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sha512sum1 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sha512sum1 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sha512sum1 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sha512sum1 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sha512sum1 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sha512sum1 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sha512sum1 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sha512sum1 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sha512sum1 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sha512sum1 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sha512sum1 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sha512sum1 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sha512sum1 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sha512sum1 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sha512sum1 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sha512sum1 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sha512sum1 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sha512sum1 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sha512sum1 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sha512sum1 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sha512sum1 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sha512sum1 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sha512sum1 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sha512sum1 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sha512sum1 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sha512sum1 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sha512sum1 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sha512sum1 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sha512sum1 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sha512sum1 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sha512sum1 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sha512sum1 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sha512sum1 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sha512sum1 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sha512sum1 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sha512sum1 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sha512sum1 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sha512sum1 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sha512sum1 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sha512sum1 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sha512sum1 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sha512sum1 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sha512sum1 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sha512sum1 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sha512sum1 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sha512sum1 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sha512sum1 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sha512sum1 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sha512sum1 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sha512sum1 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sha512sum1 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sha512sum1 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sha512sum1 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sha512sum1 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sha512sum1 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sha512sum1 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sha512sum1 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sha512sum1 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sha512sum1 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sha512sum1 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sha512sum1 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sha512sum1 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sha512sum1 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sha512sum1 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sha512sum1 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sha512sum1 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sha512sum1 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sha512sum1 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sha512sum1 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sha512sum1 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sha512sum1 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sha512sum1 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sha512sum1 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sha512sum1 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sha512sum1 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sha512sum1 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sha512sum1 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sha512sum1 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sha512sum1 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sha512sum1 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sha512sum1 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sha512sum1 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sha512sum1 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sha512sum1 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sha512sum1 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sha512sum1 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sha512sum1 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sha512sum1 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sha512sum1 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sha512sum1 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sha512sum1 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sha512sum1 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sha512sum1 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sha512sum1 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sha512sum1 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sha512sum1 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sha512sum1 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 17293822569102704639, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xefffffffffffffff;
+li x10, 0xefffffffffffffff
+sha512sum1 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446708889337462783, 
+// opcode: sha512sum1 ; op1:x10; dest:x11; op1val:0xffffdfffffffffff;
+li x10, 0xffffdfffffffffff
+sha512sum1 x11, x10
+sw x11, 1024(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x5, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x4_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 21*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 129*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S
new file mode 100644
index 000000000..0ef60a2ef
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sha512sum1 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sha512sum1 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sha512sum1 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sha512sum1 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sha512sum1 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sha512sum1 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sha512sum1 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sha512sum1 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sha512sum1 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sha512sum1 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sha512sum1 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sha512sum1 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sha512sum1 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sha512sum1 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sha512sum1 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sha512sum1 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sha512sum1 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sha512sum1 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sha512sum1 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sha512sum1 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sha512sum1 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sha512sum1 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sha512sum1 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sha512sum1 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sha512sum1 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sha512sum1 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sha512sum1 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sha512sum1 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sha512sum1 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sha512sum1 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sha512sum1 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sha512sum1 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sha512sum1 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sha512sum1 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sha512sum1 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sha512sum1 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sha512sum1 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sha512sum1 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sha512sum1 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sha512sum1 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sha512sum1 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sha512sum1 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sha512sum1 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sha512sum1 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sha512sum1 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sha512sum1 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sha512sum1 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sha512sum1 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sha512sum1 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sha512sum1 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sha512sum1 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sha512sum1 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sha512sum1 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sha512sum1 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sha512sum1 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sha512sum1 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sha512sum1 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sha512sum1 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sha512sum1 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sha512sum1 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sha512sum1 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sha512sum1 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sha512sum1 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sha512sum1 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sha512sum1 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sha512sum1 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sha512sum1 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sha512sum1 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sha512sum1 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sha512sum1 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sha512sum1 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sha512sum1 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sha512sum1 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sha512sum1 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sha512sum1 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sha512sum1 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sha512sum1 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sha512sum1 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sha512sum1 & the result back into xor
+// opcode: sha512sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sha512sum1 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sha512sum1 & the result back into not
+// opcode: sha512sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sha512sum1 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sha512sum1 & the result back into add
+// opcode: sha512sum1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sha512sum1 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S
new file mode 100644
index 000000000..318e75df2
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sha512sum1-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKn.*);def TEST_CASE_1=True;",sha512sum1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sha512sum1 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sha512sum1 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sha512sum1 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sha512sum1 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sha512sum1 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sha512sum1 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sha512sum1 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sha512sum1 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sha512sum1 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sha512sum1 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sha512sum1 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sha512sum1 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sha512sum1 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sha512sum1 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sha512sum1 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sha512sum1 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sha512sum1 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sha512sum1 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sha512sum1 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sha512sum1 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sha512sum1 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sha512sum1 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sha512sum1 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sha512sum1 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sha512sum1 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sha512sum1 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sha512sum1 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sha512sum1; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sha512sum1 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S
new file mode 100644
index 000000000..73a31131f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sm3p0 instruction of the RISC-V  extension for the sm3p0 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I_Zks")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKsh.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_SIGBASE( x17,signature_x17_1)
+
+inst_0:
+// rs1 != rd, rs1==x4, rd==x25, rs1_val == 0x75a3adb3254a9493 
+// opcode: sm3p0 ; op1:x4; dest:x25; op1val:0x75a3adb3254a9493;
+li x4, 0x75a3adb3254a9493
+sm3p0 x25, x4
+sw x25, 0(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x25, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x16, rd==x16, rs1_val == 9223372036854775807, 
+// opcode: sm3p0 ; op1:x16; dest:x16; op1val:0x7fffffffffffffff;
+li x16, 0x7fffffffffffffff
+sm3p0 x16, x16
+sw x16, 8(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x16, 0x0000000000000000)
+
+inst_2:
+// rs1==x27, rd==x22, rs1_val == 13835058055282163711, 
+// opcode: sm3p0 ; op1:x27; dest:x22; op1val:0xbfffffffffffffff;
+li x27, 0xbfffffffffffffff
+sm3p0 x22, x27
+sw x22, 16(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x22, 0x0000000000000000)
+
+inst_3:
+// rs1==x13, rd==x29, rs1_val == 16140901064495857663, 
+// opcode: sm3p0 ; op1:x13; dest:x29; op1val:0xdfffffffffffffff;
+li x13, 0xdfffffffffffffff
+sm3p0 x29, x13
+sw x29, 24(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x29, 0x0000000000000000)
+
+inst_4:
+// rs1==x20, rd==x15, rs1_val == 17293822569102704639, 
+// opcode: sm3p0 ; op1:x20; dest:x15; op1val:0xefffffffffffffff;
+li x20, 0xefffffffffffffff
+sm3p0 x15, x20
+sw x15, 32(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x15, 0x0000000000000000)
+
+inst_5:
+// rs1==x19, rd==x21, rs1_val == 17870283321406128127, 
+// opcode: sm3p0 ; op1:x19; dest:x21; op1val:0xf7ffffffffffffff;
+li x19, 0xf7ffffffffffffff
+sm3p0 x21, x19
+sw x21, 40(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x21, 0x0000000000000000)
+
+inst_6:
+// rs1==x30, rd==x2, rs1_val == 18158513697557839871, 
+// opcode: sm3p0 ; op1:x30; dest:x2; op1val:0xfbffffffffffffff;
+li x30, 0xfbffffffffffffff
+sm3p0 x2, x30
+sw x2, 48(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x2, 0x0000000000000000)
+
+inst_7:
+// rs1==x21, rd==x14, rs1_val == 18302628885633695743, 
+// opcode: sm3p0 ; op1:x21; dest:x14; op1val:0xfdffffffffffffff;
+li x21, 0xfdffffffffffffff
+sm3p0 x14, x21
+sw x14, 56(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x14, 0x0000000000000000)
+
+inst_8:
+// rs1==x7, rd==x0, rs1_val == 18374686479671623679, 
+// opcode: sm3p0 ; op1:x7; dest:x0; op1val:0xfeffffffffffffff;
+li x7, 0xfeffffffffffffff
+sm3p0 x0, x7
+sw x0, 64(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x0, 0x0000000000000000)
+
+inst_9:
+// rs1==x3, rd==x12, rs1_val == 18410715276690587647, 
+// opcode: sm3p0 ; op1:x3; dest:x12; op1val:0xff7fffffffffffff;
+li x3, 0xff7fffffffffffff
+sm3p0 x12, x3
+sw x12, 72(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x12, 0x0000000000000000)
+
+inst_10:
+// rs1==x31, rd==x9, rs1_val == 18428729675200069631, 
+// opcode: sm3p0 ; op1:x31; dest:x9; op1val:0xffbfffffffffffff;
+li x31, 0xffbfffffffffffff
+sm3p0 x9, x31
+sw x9, 80(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x9, 0x0000000000000000)
+
+inst_11:
+// rs1==x29, rd==x11, rs1_val == 18437736874454810623, 
+// opcode: sm3p0 ; op1:x29; dest:x11; op1val:0xffdfffffffffffff;
+li x29, 0xffdfffffffffffff
+sm3p0 x11, x29
+sw x11, 88(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x11, 0x0000000000000000)
+
+inst_12:
+// rs1==x10, rd==x23, rs1_val == 18442240474082181119, 
+// opcode: sm3p0 ; op1:x10; dest:x23; op1val:0xffefffffffffffff;
+li x10, 0xffefffffffffffff
+sm3p0 x23, x10
+sw x23, 96(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x23, 0x0000000000000000)
+
+inst_13:
+// rs1==x0, rd==x1, rs1_val == 18444492273895866367, 
+// opcode: sm3p0 ; op1:x0; dest:x1; op1val:0x0;
+li x0, 0x0
+sm3p0 x1, x0
+sw x1, 104(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x1, 0x0000000000000000)
+
+inst_14:
+// rs1==x28, rd==x6, rs1_val == 18445618173802708991, 
+// opcode: sm3p0 ; op1:x28; dest:x6; op1val:0xfffbffffffffffff;
+li x28, 0xfffbffffffffffff
+sm3p0 x6, x28
+sw x6, 112(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x6, 0x0000000000000000)
+
+inst_15:
+// rs1==x22, rd==x28, rs1_val == 18446181123756130303, 
+// opcode: sm3p0 ; op1:x22; dest:x28; op1val:0xfffdffffffffffff;
+li x22, 0xfffdffffffffffff
+sm3p0 x28, x22
+sw x28, 120(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x28, 0x0000000000000000)
+
+inst_16:
+// rs1==x8, rd==x30, rs1_val == 18446462598732840959, 
+// opcode: sm3p0 ; op1:x8; dest:x30; op1val:0xfffeffffffffffff;
+li x8, 0xfffeffffffffffff
+sm3p0 x30, x8
+sw x30, 128(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x30, 0x0000000000000000)
+
+inst_17:
+// rs1==x5, rd==x4, rs1_val == 18446603336221196287, 
+// opcode: sm3p0 ; op1:x5; dest:x4; op1val:0xffff7fffffffffff;
+li x5, 0xffff7fffffffffff
+sm3p0 x4, x5
+sw x4, 136(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x18, x4, 0x0000000000000000)
+
+inst_18:
+// rs1==x11, rd==x5, rs1_val == 18446673704965373951, 
+// opcode: sm3p0 ; op1:x11; dest:x5; op1val:0xffffbfffffffffff;
+li x11, 0xffffbfffffffffff
+sm3p0 x5, x11
+sw x5, 144(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x5, 0x0000000000000000)
+
+inst_19:
+// rs1==x24, rd==x10, rs1_val == 18446708889337462783, 
+// opcode: sm3p0 ; op1:x24; dest:x10; op1val:0xffffdfffffffffff;
+li x24, 0xffffdfffffffffff
+sm3p0 x10, x24
+sw x10, 152(x17)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x10, 0x0000000000000000)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_20:
+// rs1==x17, rd==x20, rs1_val == 18446726481523507199, 
+// opcode: sm3p0 ; op1:x17; dest:x20; op1val:0xffffefffffffffff;
+li x17, 0xffffefffffffffff
+sm3p0 x20, x17
+sw x20, 0(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x20, 0x0000000000000000)
+
+inst_21:
+// rs1==x2, rd==x19, rs1_val == 18446735277616529407, 
+// opcode: sm3p0 ; op1:x2; dest:x19; op1val:0xfffff7ffffffffff;
+li x2, 0xfffff7ffffffffff
+sm3p0 x19, x2
+sw x19, 8(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x19, 0x0000000000000000)
+
+inst_22:
+// rs1==x1, rd==x24, rs1_val == 18446739675663040511, 
+// opcode: sm3p0 ; op1:x1; dest:x24; op1val:0xfffffbffffffffff;
+li x1, 0xfffffbffffffffff
+sm3p0 x24, x1
+sw x24, 16(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x24, 0x0000000000000000)
+
+inst_23:
+// rs1==x12, rd==x31, rs1_val == 18446741874686296063, 
+// opcode: sm3p0 ; op1:x12; dest:x31; op1val:0xfffffdffffffffff;
+li x12, 0xfffffdffffffffff
+sm3p0 x31, x12
+sw x31, 24(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x31, 0x0000000000000000)
+
+inst_24:
+// rs1==x26, rd==x7, rs1_val == 18446742974197923839, 
+// opcode: sm3p0 ; op1:x26; dest:x7; op1val:0xfffffeffffffffff;
+li x26, 0xfffffeffffffffff
+sm3p0 x7, x26
+sw x7, 32(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x7, 0x0000000000000000)
+
+inst_25:
+// rs1==x15, rd==x18, rs1_val == 18446743523953737727, 
+// opcode: sm3p0 ; op1:x15; dest:x18; op1val:0xffffff7fffffffff;
+li x15, 0xffffff7fffffffff
+sm3p0 x18, x15
+sw x18, 40(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x18, 0x0000000000000000)
+
+inst_26:
+// rs1==x6, rd==x26, rs1_val == 18446743798831644671, 
+// opcode: sm3p0 ; op1:x6; dest:x26; op1val:0xffffffbfffffffff;
+li x6, 0xffffffbfffffffff
+sm3p0 x26, x6
+sw x26, 48(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x26, 0x0000000000000000)
+
+inst_27:
+// rs1==x25, rd==x13, rs1_val == 18446743936270598143, 
+// opcode: sm3p0 ; op1:x25; dest:x13; op1val:0xffffffdfffffffff;
+li x25, 0xffffffdfffffffff
+sm3p0 x13, x25
+sw x13, 56(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x13, 0x0000000000000000)
+
+inst_28:
+// rs1==x9, rd==x27, rs1_val == 18446744004990074879, 
+// opcode: sm3p0 ; op1:x9; dest:x27; op1val:0xffffffefffffffff;
+li x9, 0xffffffefffffffff
+sm3p0 x27, x9
+sw x27, 64(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x27, 0x0000000000000000)
+
+inst_29:
+// rs1==x23, rd==x8, rs1_val == 18446744039349813247, 
+// opcode: sm3p0 ; op1:x23; dest:x8; op1val:0xfffffff7ffffffff;
+li x23, 0xfffffff7ffffffff
+sm3p0 x8, x23
+sw x8, 72(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x8, 0x0000000000000000)
+
+inst_30:
+// rs1==x18, rd==x17, rs1_val == 18446744056529682431, 
+// opcode: sm3p0 ; op1:x18; dest:x17; op1val:0xfffffffbffffffff;
+li x18, 0xfffffffbffffffff
+sm3p0 x17, x18
+sw x17, 80(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x17, 0x0000000000000000)
+
+inst_31:
+// rs1==x14, rd==x3, rs1_val == 18446744065119617023, 
+// opcode: sm3p0 ; op1:x14; dest:x3; op1val:0xfffffffdffffffff;
+li x14, 0xfffffffdffffffff
+sm3p0 x3, x14
+sw x3, 88(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x3, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sm3p0 x11, x10
+sw x11, 96(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sm3p0 x11, x10
+sw x11, 104(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sm3p0 x11, x10
+sw x11, 112(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sm3p0 x11, x10
+sw x11, 120(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sm3p0 x11, x10
+sw x11, 128(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sm3p0 x11, x10
+sw x11, 136(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sm3p0 x11, x10
+sw x11, 144(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sm3p0 x11, x10
+sw x11, 152(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sm3p0 x11, x10
+sw x11, 160(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sm3p0 x11, x10
+sw x11, 168(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sm3p0 x11, x10
+sw x11, 176(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sm3p0 x11, x10
+sw x11, 184(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sm3p0 x11, x10
+sw x11, 192(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sm3p0 x11, x10
+sw x11, 200(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sm3p0 x11, x10
+sw x11, 208(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sm3p0 x11, x10
+sw x11, 216(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sm3p0 x11, x10
+sw x11, 224(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sm3p0 x11, x10
+sw x11, 232(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sm3p0 x11, x10
+sw x11, 240(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sm3p0 x11, x10
+sw x11, 248(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sm3p0 x11, x10
+sw x11, 256(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sm3p0 x11, x10
+sw x11, 264(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sm3p0 x11, x10
+sw x11, 272(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sm3p0 x11, x10
+sw x11, 280(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sm3p0 x11, x10
+sw x11, 288(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sm3p0 x11, x10
+sw x11, 296(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sm3p0 x11, x10
+sw x11, 304(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sm3p0 x11, x10
+sw x11, 312(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sm3p0 x11, x10
+sw x11, 320(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sm3p0 x11, x10
+sw x11, 328(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sm3p0 x11, x10
+sw x11, 336(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sm3p0 x11, x10
+sw x11, 344(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sm3p0 x11, x10
+sw x11, 352(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sm3p0 x11, x10
+sw x11, 360(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sm3p0 x11, x10
+sw x11, 368(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sm3p0 x11, x10
+sw x11, 376(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sm3p0 x11, x10
+sw x11, 384(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sm3p0 x11, x10
+sw x11, 392(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sm3p0 x11, x10
+sw x11, 400(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sm3p0 x11, x10
+sw x11, 408(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sm3p0 x11, x10
+sw x11, 416(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sm3p0 x11, x10
+sw x11, 424(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sm3p0 x11, x10
+sw x11, 432(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sm3p0 x11, x10
+sw x11, 440(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sm3p0 x11, x10
+sw x11, 448(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sm3p0 x11, x10
+sw x11, 456(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sm3p0 x11, x10
+sw x11, 464(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sm3p0 x11, x10
+sw x11, 472(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sm3p0 x11, x10
+sw x11, 480(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sm3p0 x11, x10
+sw x11, 488(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sm3p0 x11, x10
+sw x11, 496(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sm3p0 x11, x10
+sw x11, 504(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sm3p0 x11, x10
+sw x11, 512(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sm3p0 x11, x10
+sw x11, 520(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sm3p0 x11, x10
+sw x11, 528(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sm3p0 x11, x10
+sw x11, 536(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sm3p0 x11, x10
+sw x11, 544(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sm3p0 x11, x10
+sw x11, 552(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sm3p0 x11, x10
+sw x11, 560(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sm3p0 x11, x10
+sw x11, 568(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sm3p0 x11, x10
+sw x11, 576(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sm3p0 x11, x10
+sw x11, 584(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sm3p0 x11, x10
+sw x11, 592(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sm3p0 x11, x10
+sw x11, 600(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sm3p0 x11, x10
+sw x11, 608(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sm3p0 x11, x10
+sw x11, 616(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sm3p0 x11, x10
+sw x11, 624(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sm3p0 x11, x10
+sw x11, 632(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sm3p0 x11, x10
+sw x11, 640(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sm3p0 x11, x10
+sw x11, 648(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sm3p0 x11, x10
+sw x11, 656(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sm3p0 x11, x10
+sw x11, 664(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sm3p0 x11, x10
+sw x11, 672(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sm3p0 x11, x10
+sw x11, 680(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sm3p0 x11, x10
+sw x11, 688(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sm3p0 x11, x10
+sw x11, 696(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sm3p0 x11, x10
+sw x11, 704(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sm3p0 x11, x10
+sw x11, 712(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sm3p0 x11, x10
+sw x11, 720(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sm3p0 x11, x10
+sw x11, 728(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sm3p0 x11, x10
+sw x11, 736(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sm3p0 x11, x10
+sw x11, 744(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sm3p0 x11, x10
+sw x11, 752(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sm3p0 x11, x10
+sw x11, 760(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sm3p0 x11, x10
+sw x11, 768(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sm3p0 x11, x10
+sw x11, 776(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sm3p0 x11, x10
+sw x11, 784(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sm3p0 x11, x10
+sw x11, 792(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sm3p0 x11, x10
+sw x11, 800(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sm3p0 x11, x10
+sw x11, 808(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sm3p0 x11, x10
+sw x11, 816(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sm3p0 x11, x10
+sw x11, 824(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sm3p0 x11, x10
+sw x11, 832(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sm3p0 x11, x10
+sw x11, 840(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sm3p0 x11, x10
+sw x11, 848(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sm3p0 x11, x10
+sw x11, 856(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sm3p0 x11, x10
+sw x11, 864(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sm3p0 x11, x10
+sw x11, 872(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sm3p0 x11, x10
+sw x11, 880(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sm3p0 x11, x10
+sw x11, 888(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sm3p0 x11, x10
+sw x11, 896(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sm3p0 x11, x10
+sw x11, 904(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sm3p0 x11, x10
+sw x11, 912(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sm3p0 x11, x10
+sw x11, 920(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sm3p0 x11, x10
+sw x11, 928(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sm3p0 x11, x10
+sw x11, 936(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sm3p0 x11, x10
+sw x11, 944(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sm3p0 x11, x10
+sw x11, 952(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sm3p0 x11, x10
+sw x11, 960(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sm3p0 x11, x10
+sw x11, 968(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sm3p0 x11, x10
+sw x11, 976(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sm3p0 x11, x10
+sw x11, 984(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sm3p0 x11, x10
+sw x11, 992(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sm3p0 x11, x10
+sw x11, 1000(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sm3p0 x11, x10
+sw x11, 1008(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sm3p0 x11, x10
+sw x11, 1016(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18374686479671623679, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfeffffffffffffff;
+li x10, 0xfeffffffffffffff
+sm3p0 x11, x10
+sw x11, 1024(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18444492273895866367, 
+// opcode: sm3p0 ; op1:x10; dest:x11; op1val:0xfff7ffffffffffff;
+li x10, 0xfff7ffffffffffff
+sm3p0 x11, x10
+sw x11, 1032(x4)
+RVMODEL_IO_ASSERT_GPR_EQ(x16, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x17_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x17_1:
+    .fill 20*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 130*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S
new file mode 100644
index 000000000..72c238d3f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sm3p0 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sm3p0 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sm3p0 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sm3p0 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sm3p0 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sm3p0 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sm3p0 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sm3p0 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sm3p0 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sm3p0 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sm3p0 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sm3p0 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sm3p0 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sm3p0 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sm3p0 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sm3p0 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sm3p0 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sm3p0 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sm3p0 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sm3p0 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sm3p0 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sm3p0 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sm3p0 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sm3p0 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sm3p0 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sm3p0 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sm3p0 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sm3p0 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sm3p0 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sm3p0 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sm3p0 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sm3p0 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sm3p0 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sm3p0 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sm3p0 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sm3p0 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sm3p0 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sm3p0 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sm3p0 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sm3p0 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sm3p0 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sm3p0 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sm3p0 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sm3p0 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sm3p0 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sm3p0 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sm3p0 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sm3p0 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sm3p0 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sm3p0 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sm3p0 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sm3p0 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sm3p0 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sm3p0 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sm3p0 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sm3p0 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sm3p0 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sm3p0 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sm3p0 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sm3p0 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sm3p0 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sm3p0 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sm3p0 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sm3p0 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sm3p0 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sm3p0 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sm3p0 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sm3p0 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sm3p0 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sm3p0 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sm3p0 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sm3p0 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sm3p0 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sm3p0 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sm3p0 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sm3p0 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sm3p0 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sm3p0 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sm3p0 & the result back into xor
+// opcode: sm3p0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sm3p0 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sm3p0 & the result back into not
+// opcode: sm3p0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sm3p0 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sm3p0 & the result back into add
+// opcode: sm3p0; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sm3p0 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S
new file mode 100644
index 000000000..c567bd969
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p0-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p0)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sm3p0 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sm3p0 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sm3p0 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sm3p0 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sm3p0 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sm3p0 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sm3p0 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sm3p0 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sm3p0 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sm3p0 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sm3p0 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sm3p0 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sm3p0 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sm3p0 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sm3p0 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sm3p0 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sm3p0 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sm3p0 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sm3p0 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sm3p0 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sm3p0 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sm3p0 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sm3p0 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sm3p0 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sm3p0 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sm3p0 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sm3p0 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sm3p0; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sm3p0 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S
new file mode 100644
index 000000000..77423add8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-01.S
@@ -0,0 +1,1279 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sm3p1 instruction of the RISC-V  extension for the sm3p1 covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I_Zks")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKsh.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_SIGBASE( x9,signature_x9_1)
+
+inst_0:
+// rs1 != rd, rs1==x16, rd==x20, rs1_val == 0x75a3adb3254a9493 
+// opcode: sm3p1 ; op1:x16; dest:x20; op1val:0x75a3adb3254a9493;
+li x16, 0x75a3adb3254a9493
+sm3p1 x20, x16
+sw x20, 0(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x20, 0x0000000000000000)
+
+inst_1:
+// rs1 == rd, rs1==x22, rd==x22, rs1_val == 9223372036854775807, 
+// opcode: sm3p1 ; op1:x22; dest:x22; op1val:0x7fffffffffffffff;
+li x22, 0x7fffffffffffffff
+sm3p1 x22, x22
+sw x22, 8(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x22, 0x0000000000000000)
+
+inst_2:
+// rs1==x10, rd==x6, rs1_val == 13835058055282163711, 
+// opcode: sm3p1 ; op1:x10; dest:x6; op1val:0xbfffffffffffffff;
+li x10, 0xbfffffffffffffff
+sm3p1 x6, x10
+sw x6, 16(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x6, 0x0000000000000000)
+
+inst_3:
+// rs1==x4, rd==x15, rs1_val == 16140901064495857663, 
+// opcode: sm3p1 ; op1:x4; dest:x15; op1val:0xdfffffffffffffff;
+li x4, 0xdfffffffffffffff
+sm3p1 x15, x4
+sw x15, 24(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x15, 0x0000000000000000)
+
+inst_4:
+// rs1==x11, rd==x16, rs1_val == 17293822569102704639, 
+// opcode: sm3p1 ; op1:x11; dest:x16; op1val:0xefffffffffffffff;
+li x11, 0xefffffffffffffff
+sm3p1 x16, x11
+sw x16, 32(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x16, 0x0000000000000000)
+
+inst_5:
+// rs1==x14, rd==x30, rs1_val == 17870283321406128127, 
+// opcode: sm3p1 ; op1:x14; dest:x30; op1val:0xf7ffffffffffffff;
+li x14, 0xf7ffffffffffffff
+sm3p1 x30, x14
+sw x30, 40(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x30, 0x0000000000000000)
+
+inst_6:
+// rs1==x13, rd==x3, rs1_val == 18158513697557839871, 
+// opcode: sm3p1 ; op1:x13; dest:x3; op1val:0xfbffffffffffffff;
+li x13, 0xfbffffffffffffff
+sm3p1 x3, x13
+sw x3, 48(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x3, 0x0000000000000000)
+
+inst_7:
+// rs1==x17, rd==x0, rs1_val == 18302628885633695743, 
+// opcode: sm3p1 ; op1:x17; dest:x0; op1val:0xfdffffffffffffff;
+li x17, 0xfdffffffffffffff
+sm3p1 x0, x17
+sw x0, 56(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x0, 0x0000000000000000)
+
+inst_8:
+// rs1==x1, rd==x18, rs1_val == 18374686479671623679, 
+// opcode: sm3p1 ; op1:x1; dest:x18; op1val:0xfeffffffffffffff;
+li x1, 0xfeffffffffffffff
+sm3p1 x18, x1
+sw x18, 64(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x18, 0x0000000000000000)
+
+inst_9:
+// rs1==x8, rd==x28, rs1_val == 18410715276690587647, 
+// opcode: sm3p1 ; op1:x8; dest:x28; op1val:0xff7fffffffffffff;
+li x8, 0xff7fffffffffffff
+sm3p1 x28, x8
+sw x28, 72(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x28, 0x0000000000000000)
+
+inst_10:
+// rs1==x30, rd==x7, rs1_val == 18428729675200069631, 
+// opcode: sm3p1 ; op1:x30; dest:x7; op1val:0xffbfffffffffffff;
+li x30, 0xffbfffffffffffff
+sm3p1 x7, x30
+sw x7, 80(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x7, 0x0000000000000000)
+
+inst_11:
+// rs1==x6, rd==x5, rs1_val == 18437736874454810623, 
+// opcode: sm3p1 ; op1:x6; dest:x5; op1val:0xffdfffffffffffff;
+li x6, 0xffdfffffffffffff
+sm3p1 x5, x6
+sw x5, 88(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x5, 0x0000000000000000)
+
+inst_12:
+// rs1==x23, rd==x26, rs1_val == 18442240474082181119, 
+// opcode: sm3p1 ; op1:x23; dest:x26; op1val:0xffefffffffffffff;
+li x23, 0xffefffffffffffff
+sm3p1 x26, x23
+sw x26, 96(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x26, 0x0000000000000000)
+
+inst_13:
+// rs1==x27, rd==x8, rs1_val == 18444492273895866367, 
+// opcode: sm3p1 ; op1:x27; dest:x8; op1val:0xfff7ffffffffffff;
+li x27, 0xfff7ffffffffffff
+sm3p1 x8, x27
+sw x8, 104(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x8, 0x0000000000000000)
+
+inst_14:
+// rs1==x24, rd==x12, rs1_val == 18445618173802708991, 
+// opcode: sm3p1 ; op1:x24; dest:x12; op1val:0xfffbffffffffffff;
+li x24, 0xfffbffffffffffff
+sm3p1 x12, x24
+sw x12, 112(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x12, 0x0000000000000000)
+
+inst_15:
+// rs1==x5, rd==x14, rs1_val == 18446181123756130303, 
+// opcode: sm3p1 ; op1:x5; dest:x14; op1val:0xfffdffffffffffff;
+li x5, 0xfffdffffffffffff
+sm3p1 x14, x5
+sw x14, 120(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x14, 0x0000000000000000)
+
+inst_16:
+// rs1==x29, rd==x10, rs1_val == 18446462598732840959, 
+// opcode: sm3p1 ; op1:x29; dest:x10; op1val:0xfffeffffffffffff;
+li x29, 0xfffeffffffffffff
+sm3p1 x10, x29
+sw x10, 128(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x10, 0x0000000000000000)
+
+inst_17:
+// rs1==x12, rd==x17, rs1_val == 18446603336221196287, 
+// opcode: sm3p1 ; op1:x12; dest:x17; op1val:0xffff7fffffffffff;
+li x12, 0xffff7fffffffffff
+sm3p1 x17, x12
+sw x17, 136(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x17, 0x0000000000000000)
+
+inst_18:
+// rs1==x2, rd==x1, rs1_val == 18446673704965373951, 
+// opcode: sm3p1 ; op1:x2; dest:x1; op1val:0xffffbfffffffffff;
+li x2, 0xffffbfffffffffff
+sm3p1 x1, x2
+sw x1, 144(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x1, 0x0000000000000000)
+
+inst_19:
+// rs1==x3, rd==x21, rs1_val == 18446708889337462783, 
+// opcode: sm3p1 ; op1:x3; dest:x21; op1val:0xffffdfffffffffff;
+li x3, 0xffffdfffffffffff
+sm3p1 x21, x3
+sw x21, 152(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x19, x21, 0x0000000000000000)
+
+inst_20:
+// rs1==x26, rd==x13, rs1_val == 18446726481523507199, 
+// opcode: sm3p1 ; op1:x26; dest:x13; op1val:0xffffefffffffffff;
+li x26, 0xffffefffffffffff
+sm3p1 x13, x26
+sw x13, 160(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x13, 0x0000000000000000)
+
+inst_21:
+// rs1==x7, rd==x25, rs1_val == 18446735277616529407, 
+// opcode: sm3p1 ; op1:x7; dest:x25; op1val:0xfffff7ffffffffff;
+li x7, 0xfffff7ffffffffff
+sm3p1 x25, x7
+sw x25, 168(x9)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x25, 0x0000000000000000)
+RVTEST_SIGBASE( x1,signature_x1_0)
+
+inst_22:
+// rs1==x19, rd==x29, rs1_val == 18446739675663040511, 
+// opcode: sm3p1 ; op1:x19; dest:x29; op1val:0xfffffbffffffffff;
+li x19, 0xfffffbffffffffff
+sm3p1 x29, x19
+sw x29, 0(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x29, 0x0000000000000000)
+
+inst_23:
+// rs1==x9, rd==x31, rs1_val == 18446741874686296063, 
+// opcode: sm3p1 ; op1:x9; dest:x31; op1val:0xfffffdffffffffff;
+li x9, 0xfffffdffffffffff
+sm3p1 x31, x9
+sw x31, 8(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x31, 0x0000000000000000)
+
+inst_24:
+// rs1==x28, rd==x11, rs1_val == 18446742974197923839, 
+// opcode: sm3p1 ; op1:x28; dest:x11; op1val:0xfffffeffffffffff;
+li x28, 0xfffffeffffffffff
+sm3p1 x11, x28
+sw x11, 16(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_25:
+// rs1==x31, rd==x24, rs1_val == 18446743523953737727, 
+// opcode: sm3p1 ; op1:x31; dest:x24; op1val:0xffffff7fffffffff;
+li x31, 0xffffff7fffffffff
+sm3p1 x24, x31
+sw x24, 24(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x24, 0x0000000000000000)
+
+inst_26:
+// rs1==x0, rd==x27, rs1_val == 18446743798831644671, 
+// opcode: sm3p1 ; op1:x0; dest:x27; op1val:0x0;
+li x0, 0x0
+sm3p1 x27, x0
+sw x27, 32(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x27, 0x0000000000000000)
+
+inst_27:
+// rs1==x15, rd==x19, rs1_val == 18446743936270598143, 
+// opcode: sm3p1 ; op1:x15; dest:x19; op1val:0xffffffdfffffffff;
+li x15, 0xffffffdfffffffff
+sm3p1 x19, x15
+sw x19, 40(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x19, 0x0000000000000000)
+
+inst_28:
+// rs1==x25, rd==x23, rs1_val == 18446744004990074879, 
+// opcode: sm3p1 ; op1:x25; dest:x23; op1val:0xffffffefffffffff;
+li x25, 0xffffffefffffffff
+sm3p1 x23, x25
+sw x23, 48(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x23, 0x0000000000000000)
+
+inst_29:
+// rs1==x18, rd==x4, rs1_val == 18446744039349813247, 
+// opcode: sm3p1 ; op1:x18; dest:x4; op1val:0xfffffff7ffffffff;
+li x18, 0xfffffff7ffffffff
+sm3p1 x4, x18
+sw x4, 56(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x4, 0x0000000000000000)
+
+inst_30:
+// rs1==x20, rd==x9, rs1_val == 18446744056529682431, 
+// opcode: sm3p1 ; op1:x20; dest:x9; op1val:0xfffffffbffffffff;
+li x20, 0xfffffffbffffffff
+sm3p1 x9, x20
+sw x9, 64(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x9, 0x0000000000000000)
+
+inst_31:
+// rs1==x21, rd==x2, rs1_val == 18446744065119617023, 
+// opcode: sm3p1 ; op1:x21; dest:x2; op1val:0xfffffffdffffffff;
+li x21, 0xfffffffdffffffff
+sm3p1 x2, x21
+sw x2, 72(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x2, 0x0000000000000000)
+
+inst_32:
+// rs1_val == 18446744069414584319, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffeffffffff;
+li x10, 0xfffffffeffffffff
+sm3p1 x11, x10
+sw x11, 80(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_33:
+// rs1_val == 18446744071562067967, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffff7fffffff;
+li x10, 0xffffffff7fffffff
+sm3p1 x11, x10
+sw x11, 88(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_34:
+// rs1_val == 18446744072635809791, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffbfffffff;
+li x10, 0xffffffffbfffffff
+sm3p1 x11, x10
+sw x11, 96(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_35:
+// rs1_val == 18446744073172680703, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffdfffffff;
+li x10, 0xffffffffdfffffff
+sm3p1 x11, x10
+sw x11, 104(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_36:
+// rs1_val == 18446744073441116159, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffefffffff;
+li x10, 0xffffffffefffffff
+sm3p1 x11, x10
+sw x11, 112(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_37:
+// rs1_val == 18446744073575333887, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffff7ffffff;
+li x10, 0xfffffffff7ffffff
+sm3p1 x11, x10
+sw x11, 120(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_38:
+// rs1_val == 18446744073642442751, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffbffffff;
+li x10, 0xfffffffffbffffff
+sm3p1 x11, x10
+sw x11, 128(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_39:
+// rs1_val == 18446744073675997183, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffdffffff;
+li x10, 0xfffffffffdffffff
+sm3p1 x11, x10
+sw x11, 136(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_40:
+// rs1_val == 18446744073692774399, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffeffffff;
+li x10, 0xfffffffffeffffff
+sm3p1 x11, x10
+sw x11, 144(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_41:
+// rs1_val == 18446744073701163007, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffff7fffff;
+li x10, 0xffffffffff7fffff
+sm3p1 x11, x10
+sw x11, 152(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_42:
+// rs1_val == 18446744073705357311, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffbfffff;
+li x10, 0xffffffffffbfffff
+sm3p1 x11, x10
+sw x11, 160(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_43:
+// rs1_val == 18446744073707454463, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffdfffff;
+li x10, 0xffffffffffdfffff
+sm3p1 x11, x10
+sw x11, 168(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_44:
+// rs1_val == 18446744073708503039, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffefffff;
+li x10, 0xffffffffffefffff
+sm3p1 x11, x10
+sw x11, 176(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_45:
+// rs1_val == 18446744073709027327, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffff7ffff;
+li x10, 0xfffffffffff7ffff
+sm3p1 x11, x10
+sw x11, 184(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_46:
+// rs1_val == 18446744073709289471, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffbffff;
+li x10, 0xfffffffffffbffff
+sm3p1 x11, x10
+sw x11, 192(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_47:
+// rs1_val == 18446744073709420543, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffdffff;
+li x10, 0xfffffffffffdffff
+sm3p1 x11, x10
+sw x11, 200(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_48:
+// rs1_val == 18446744073709486079, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffeffff;
+li x10, 0xfffffffffffeffff
+sm3p1 x11, x10
+sw x11, 208(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_49:
+// rs1_val == 18446744073709518847, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffff7fff;
+li x10, 0xffffffffffff7fff
+sm3p1 x11, x10
+sw x11, 216(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_50:
+// rs1_val == 18446744073709535231, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffbfff;
+li x10, 0xffffffffffffbfff
+sm3p1 x11, x10
+sw x11, 224(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_51:
+// rs1_val == 18446744073709543423, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffdfff;
+li x10, 0xffffffffffffdfff
+sm3p1 x11, x10
+sw x11, 232(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_52:
+// rs1_val == 18446744073709547519, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffefff;
+li x10, 0xffffffffffffefff
+sm3p1 x11, x10
+sw x11, 240(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_53:
+// rs1_val == 18446744073709549567, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffff7ff;
+li x10, 0xfffffffffffff7ff
+sm3p1 x11, x10
+sw x11, 248(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_54:
+// rs1_val == 18446744073709550591, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffbff;
+li x10, 0xfffffffffffffbff
+sm3p1 x11, x10
+sw x11, 256(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_55:
+// rs1_val == 18446744073709551103, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffdff;
+li x10, 0xfffffffffffffdff
+sm3p1 x11, x10
+sw x11, 264(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_56:
+// rs1_val == 18446744073709551359, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffeff;
+li x10, 0xfffffffffffffeff
+sm3p1 x11, x10
+sw x11, 272(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_57:
+// rs1_val == 18446744073709551487, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffff7f;
+li x10, 0xffffffffffffff7f
+sm3p1 x11, x10
+sw x11, 280(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_58:
+// rs1_val == 18446744073709551551, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffffbf;
+li x10, 0xffffffffffffffbf
+sm3p1 x11, x10
+sw x11, 288(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_59:
+// rs1_val == 18446744073709551583, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffffdf;
+li x10, 0xffffffffffffffdf
+sm3p1 x11, x10
+sw x11, 296(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_60:
+// rs1_val == 18446744073709551599, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffffffffffef;
+li x10, 0xffffffffffffffef
+sm3p1 x11, x10
+sw x11, 304(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_61:
+// rs1_val == 18446744073709551607, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffff7;
+li x10, 0xfffffffffffffff7
+sm3p1 x11, x10
+sw x11, 312(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_62:
+// rs1_val == 18446744073709551611, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffb;
+li x10, 0xfffffffffffffffb
+sm3p1 x11, x10
+sw x11, 320(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_63:
+// rs1_val == 18446744073709551613, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffd;
+li x10, 0xfffffffffffffffd
+sm3p1 x11, x10
+sw x11, 328(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_64:
+// rs1_val == 18446744073709551614, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffffffffffe;
+li x10, 0xfffffffffffffffe
+sm3p1 x11, x10
+sw x11, 336(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_65:
+// rs1_val == 9223372036854775808, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000000000000000;
+li x10, 0x8000000000000000
+sm3p1 x11, x10
+sw x11, 344(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_66:
+// rs1_val == 4611686018427387904, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000000000000000;
+li x10, 0x4000000000000000
+sm3p1 x11, x10
+sw x11, 352(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_67:
+// rs1_val == 2305843009213693952, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000000000000000;
+li x10, 0x2000000000000000
+sm3p1 x11, x10
+sw x11, 360(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_68:
+// rs1_val == 1152921504606846976, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000000000000000;
+li x10, 0x1000000000000000
+sm3p1 x11, x10
+sw x11, 368(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_69:
+// rs1_val == 576460752303423488, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800000000000000;
+li x10, 0x800000000000000
+sm3p1 x11, x10
+sw x11, 376(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_70:
+// rs1_val == 288230376151711744, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400000000000000;
+li x10, 0x400000000000000
+sm3p1 x11, x10
+sw x11, 384(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_71:
+// rs1_val == 144115188075855872, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200000000000000;
+li x10, 0x200000000000000
+sm3p1 x11, x10
+sw x11, 392(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_72:
+// rs1_val == 72057594037927936, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100000000000000;
+li x10, 0x100000000000000
+sm3p1 x11, x10
+sw x11, 400(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_73:
+// rs1_val == 36028797018963968, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000000000000;
+li x10, 0x80000000000000
+sm3p1 x11, x10
+sw x11, 408(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_74:
+// rs1_val == 18014398509481984, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000000000000;
+li x10, 0x40000000000000
+sm3p1 x11, x10
+sw x11, 416(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_75:
+// rs1_val == 9007199254740992, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000000000000;
+li x10, 0x20000000000000
+sm3p1 x11, x10
+sw x11, 424(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_76:
+// rs1_val == 4503599627370496, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000000000000;
+li x10, 0x10000000000000
+sm3p1 x11, x10
+sw x11, 432(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_77:
+// rs1_val == 2251799813685248, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000000000000;
+li x10, 0x8000000000000
+sm3p1 x11, x10
+sw x11, 440(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_78:
+// rs1_val == 1125899906842624, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000000000000;
+li x10, 0x4000000000000
+sm3p1 x11, x10
+sw x11, 448(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_79:
+// rs1_val == 562949953421312, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000000000000;
+li x10, 0x2000000000000
+sm3p1 x11, x10
+sw x11, 456(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_80:
+// rs1_val == 281474976710656, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000000000000;
+li x10, 0x1000000000000
+sm3p1 x11, x10
+sw x11, 464(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_81:
+// rs1_val == 140737488355328, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800000000000;
+li x10, 0x800000000000
+sm3p1 x11, x10
+sw x11, 472(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_82:
+// rs1_val == 70368744177664, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400000000000;
+li x10, 0x400000000000
+sm3p1 x11, x10
+sw x11, 480(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_83:
+// rs1_val == 35184372088832, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200000000000;
+li x10, 0x200000000000
+sm3p1 x11, x10
+sw x11, 488(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_84:
+// rs1_val == 17592186044416, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100000000000;
+li x10, 0x100000000000
+sm3p1 x11, x10
+sw x11, 496(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_85:
+// rs1_val == 1, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1;
+li x10, 0x1
+sm3p1 x11, x10
+sw x11, 504(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_86:
+// rs1_val == 0xb6f9706fb4f741aa 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xb6f9706fb4f741aa;
+li x10, 0xb6f9706fb4f741aa
+sm3p1 x11, x10
+sw x11, 512(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_87:
+// rs1_val == 0x40a5ff526f38a9c7 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40a5ff526f38a9c7;
+li x10, 0x40a5ff526f38a9c7
+sm3p1 x11, x10
+sw x11, 520(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_88:
+// rs1_val == 0xd05668ae0fdb82bc 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xd05668ae0fdb82bc;
+li x10, 0xd05668ae0fdb82bc
+sm3p1 x11, x10
+sw x11, 528(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_89:
+// rs1_val == 0x9bedfe390d6ddd9d 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x9bedfe390d6ddd9d;
+li x10, 0x9bedfe390d6ddd9d
+sm3p1 x11, x10
+sw x11, 536(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_90:
+// rs1_val == 0xaa6bb2bde9ed477d 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xaa6bb2bde9ed477d;
+li x10, 0xaa6bb2bde9ed477d
+sm3p1 x11, x10
+sw x11, 544(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_91:
+// rs1_val == 0xd75739f82ac177c6 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xd75739f82ac177c6;
+li x10, 0xd75739f82ac177c6
+sm3p1 x11, x10
+sw x11, 552(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_92:
+// rs1_val == 0x299c3bcf90efb625 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x299c3bcf90efb625;
+li x10, 0x299c3bcf90efb625
+sm3p1 x11, x10
+sw x11, 560(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_93:
+// rs1_val == 0x9a4e9ef10171f4df 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x9a4e9ef10171f4df;
+li x10, 0x9a4e9ef10171f4df
+sm3p1 x11, x10
+sw x11, 568(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_94:
+// rs1_val == 0x1fc493caa371db42 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1fc493caa371db42;
+li x10, 0x1fc493caa371db42
+sm3p1 x11, x10
+sw x11, 576(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_95:
+// rs1_val == 0xd169a3f8cad5e297 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xd169a3f8cad5e297;
+li x10, 0xd169a3f8cad5e297
+sm3p1 x11, x10
+sw x11, 584(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_96:
+// rs1_val == 0xf4c30307672f666d 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xf4c30307672f666d;
+li x10, 0xf4c30307672f666d
+sm3p1 x11, x10
+sw x11, 592(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_97:
+// rs1_val == 0xd5b9fe5cf69bdcf3 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xd5b9fe5cf69bdcf3;
+li x10, 0xd5b9fe5cf69bdcf3
+sm3p1 x11, x10
+sw x11, 600(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_98:
+// rs1_val == 0xa0569d765ebc64cb 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xa0569d765ebc64cb;
+li x10, 0xa0569d765ebc64cb
+sm3p1 x11, x10
+sw x11, 608(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_99:
+// rs1_val == 0xe4921bf73047c198 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xe4921bf73047c198;
+li x10, 0xe4921bf73047c198
+sm3p1 x11, x10
+sw x11, 616(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_100:
+// rs1_val == 0x2daf9ac7f5faf207 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2daf9ac7f5faf207;
+li x10, 0x2daf9ac7f5faf207
+sm3p1 x11, x10
+sw x11, 624(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_101:
+// rs1_val == 0xfcc1b543c49cd65b 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfcc1b543c49cd65b;
+li x10, 0xfcc1b543c49cd65b
+sm3p1 x11, x10
+sw x11, 632(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_102:
+// rs1_val == 0x3459294ef273b44c 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x3459294ef273b44c;
+li x10, 0x3459294ef273b44c
+sm3p1 x11, x10
+sw x11, 640(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_103:
+// rs1_val == 0x436f40f274b8de87 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x436f40f274b8de87;
+li x10, 0x436f40f274b8de87
+sm3p1 x11, x10
+sw x11, 648(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_104:
+// rs1_val == 0xc5521660f3a3c571 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xc5521660f3a3c571;
+li x10, 0xc5521660f3a3c571
+sm3p1 x11, x10
+sw x11, 656(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_105:
+// rs1_val == 8796093022208, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000000000;
+li x10, 0x80000000000
+sm3p1 x11, x10
+sw x11, 664(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_106:
+// rs1_val == 4398046511104, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000000000;
+li x10, 0x40000000000
+sm3p1 x11, x10
+sw x11, 672(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_107:
+// rs1_val == 2199023255552, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000000000;
+li x10, 0x20000000000
+sm3p1 x11, x10
+sw x11, 680(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_108:
+// rs1_val == 1099511627776, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000000000;
+li x10, 0x10000000000
+sm3p1 x11, x10
+sw x11, 688(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_109:
+// rs1_val == 549755813888, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000000000;
+li x10, 0x8000000000
+sm3p1 x11, x10
+sw x11, 696(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_110:
+// rs1_val == 274877906944, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000000000;
+li x10, 0x4000000000
+sm3p1 x11, x10
+sw x11, 704(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_111:
+// rs1_val == 137438953472, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000000000;
+li x10, 0x2000000000
+sm3p1 x11, x10
+sw x11, 712(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_112:
+// rs1_val == 68719476736, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000000000;
+li x10, 0x1000000000
+sm3p1 x11, x10
+sw x11, 720(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_113:
+// rs1_val == 34359738368, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800000000;
+li x10, 0x800000000
+sm3p1 x11, x10
+sw x11, 728(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_114:
+// rs1_val == 17179869184, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400000000;
+li x10, 0x400000000
+sm3p1 x11, x10
+sw x11, 736(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_115:
+// rs1_val == 8589934592, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200000000;
+li x10, 0x200000000
+sm3p1 x11, x10
+sw x11, 744(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_116:
+// rs1_val == 4294967296, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100000000;
+li x10, 0x100000000
+sm3p1 x11, x10
+sw x11, 752(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_117:
+// rs1_val == 2147483648, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000000;
+li x10, 0x80000000
+sm3p1 x11, x10
+sw x11, 760(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_118:
+// rs1_val == 1073741824, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000000;
+li x10, 0x40000000
+sm3p1 x11, x10
+sw x11, 768(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_119:
+// rs1_val == 536870912, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000000;
+li x10, 0x20000000
+sm3p1 x11, x10
+sw x11, 776(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_120:
+// rs1_val == 268435456, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000000;
+li x10, 0x10000000
+sm3p1 x11, x10
+sw x11, 784(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_121:
+// rs1_val == 134217728, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000000;
+li x10, 0x8000000
+sm3p1 x11, x10
+sw x11, 792(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_122:
+// rs1_val == 67108864, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000000;
+li x10, 0x4000000
+sm3p1 x11, x10
+sw x11, 800(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_123:
+// rs1_val == 33554432, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000000;
+li x10, 0x2000000
+sm3p1 x11, x10
+sw x11, 808(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_124:
+// rs1_val == 16777216, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000000;
+li x10, 0x1000000
+sm3p1 x11, x10
+sw x11, 816(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_125:
+// rs1_val == 8388608, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800000;
+li x10, 0x800000
+sm3p1 x11, x10
+sw x11, 824(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_126:
+// rs1_val == 4194304, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400000;
+li x10, 0x400000
+sm3p1 x11, x10
+sw x11, 832(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_127:
+// rs1_val == 2097152, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200000;
+li x10, 0x200000
+sm3p1 x11, x10
+sw x11, 840(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_128:
+// rs1_val == 1048576, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100000;
+li x10, 0x100000
+sm3p1 x11, x10
+sw x11, 848(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_129:
+// rs1_val == 524288, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000;
+li x10, 0x80000
+sm3p1 x11, x10
+sw x11, 856(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_130:
+// rs1_val == 262144, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000;
+li x10, 0x40000
+sm3p1 x11, x10
+sw x11, 864(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_131:
+// rs1_val == 131072, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000;
+li x10, 0x20000
+sm3p1 x11, x10
+sw x11, 872(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_132:
+// rs1_val == 65536, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000;
+li x10, 0x10000
+sm3p1 x11, x10
+sw x11, 880(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_133:
+// rs1_val == 32768, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000;
+li x10, 0x8000
+sm3p1 x11, x10
+sw x11, 888(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_134:
+// rs1_val == 16384, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000;
+li x10, 0x4000
+sm3p1 x11, x10
+sw x11, 896(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_135:
+// rs1_val == 8192, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000;
+li x10, 0x2000
+sm3p1 x11, x10
+sw x11, 904(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_136:
+// rs1_val == 4096, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000;
+li x10, 0x1000
+sm3p1 x11, x10
+sw x11, 912(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_137:
+// rs1_val == 2048, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800;
+li x10, 0x800
+sm3p1 x11, x10
+sw x11, 920(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_138:
+// rs1_val == 1024, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400;
+li x10, 0x400
+sm3p1 x11, x10
+sw x11, 928(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_139:
+// rs1_val == 512, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200;
+li x10, 0x200
+sm3p1 x11, x10
+sw x11, 936(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_140:
+// rs1_val == 256, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100;
+li x10, 0x100
+sm3p1 x11, x10
+sw x11, 944(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_141:
+// rs1_val == 128, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80;
+li x10, 0x80
+sm3p1 x11, x10
+sw x11, 952(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_142:
+// rs1_val == 64, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40;
+li x10, 0x40
+sm3p1 x11, x10
+sw x11, 960(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_143:
+// rs1_val == 32, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20;
+li x10, 0x20
+sm3p1 x11, x10
+sw x11, 968(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_144:
+// rs1_val == 16, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10;
+li x10, 0x10
+sm3p1 x11, x10
+sw x11, 976(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_145:
+// rs1_val == 8, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8;
+li x10, 0x8
+sm3p1 x11, x10
+sw x11, 984(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_146:
+// rs1_val == 4, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4;
+li x10, 0x4
+sm3p1 x11, x10
+sw x11, 992(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_147:
+// rs1_val == 2, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2;
+li x10, 0x2
+sm3p1 x11, x10
+sw x11, 1000(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_148:
+// rs1_val == 18302628885633695743, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfdffffffffffffff;
+li x10, 0xfdffffffffffffff
+sm3p1 x11, x10
+sw x11, 1008(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+
+inst_149:
+// rs1_val == 18446743798831644671, 
+// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffbfffffffff;
+li x10, 0xffffffbfffffffff
+sm3p1 x11, x10
+sw x11, 1016(x1)
+RVMODEL_IO_ASSERT_GPR_EQ(x3, x11, 0x0000000000000000)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x9_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x9_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 128*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S
new file mode 100644
index 000000000..80d605ce8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp1.S
@@ -0,0 +1,969 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+xor x3, x1, x2;
+sm3p1 x1, x3;
+xor x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,0);
+RVTEST_SIGUPD(x31,x1,8);
+RVTEST_SIGUPD(x31,x4,16);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+not x3, x2;
+sm3p1 x1, x3;
+not x4, x1;
+RVTEST_SIGUPD(x31,x3,24);
+RVTEST_SIGUPD(x31,x1,32);
+RVTEST_SIGUPD(x31,x4,40);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x3; dest1:x1; op1val:0x08577eb1924770d3; op2val:0x93fdcab87b89296c
+li x1, 0x08577eb1924770d3;
+li x2, 0x93fdcab87b89296c;
+add x3, x1, x2;
+sm3p1 x1, x3;
+add x4, x1, x2;
+RVTEST_SIGUPD(x31,x3,48);
+RVTEST_SIGUPD(x31,x1,56);
+RVTEST_SIGUPD(x31,x4,64);
+
+inst_1:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+xor x4, x2, x3;
+sm3p1 x2, x4;
+xor x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,72);
+RVTEST_SIGUPD(x31,x2,80);
+RVTEST_SIGUPD(x31,x5,88);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+not x4, x3;
+sm3p1 x2, x4;
+not x5, x2;
+RVTEST_SIGUPD(x31,x4,96);
+RVTEST_SIGUPD(x31,x2,104);
+RVTEST_SIGUPD(x31,x5,112);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x4; dest1:x2; op1val:0x137a977753e8eb43; op2val:0x5c74e45eff1e5bef
+li x2, 0x137a977753e8eb43;
+li x3, 0x5c74e45eff1e5bef;
+add x4, x2, x3;
+sm3p1 x2, x4;
+add x5, x2, x3;
+RVTEST_SIGUPD(x31,x4,120);
+RVTEST_SIGUPD(x31,x2,128);
+RVTEST_SIGUPD(x31,x5,136);
+
+inst_2:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+xor x5, x3, x4;
+sm3p1 x3, x5;
+xor x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,144);
+RVTEST_SIGUPD(x31,x3,152);
+RVTEST_SIGUPD(x31,x6,160);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+not x5, x4;
+sm3p1 x3, x5;
+not x6, x3;
+RVTEST_SIGUPD(x31,x5,168);
+RVTEST_SIGUPD(x31,x3,176);
+RVTEST_SIGUPD(x31,x6,184);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x5; dest1:x3; op1val:0xaf949e5e2cb7362c; op2val:0x5cd2875ea96ec2b3
+li x3, 0xaf949e5e2cb7362c;
+li x4, 0x5cd2875ea96ec2b3;
+add x5, x3, x4;
+sm3p1 x3, x5;
+add x6, x3, x4;
+RVTEST_SIGUPD(x31,x5,192);
+RVTEST_SIGUPD(x31,x3,200);
+RVTEST_SIGUPD(x31,x6,208);
+
+inst_3:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+xor x6, x4, x5;
+sm3p1 x4, x6;
+xor x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,216);
+RVTEST_SIGUPD(x31,x4,224);
+RVTEST_SIGUPD(x31,x7,232);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+not x6, x5;
+sm3p1 x4, x6;
+not x7, x4;
+RVTEST_SIGUPD(x31,x6,240);
+RVTEST_SIGUPD(x31,x4,248);
+RVTEST_SIGUPD(x31,x7,256);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x6; dest1:x4; op1val:0xe8dac663f0e58650; op2val:0x3d7c95f9e5f0307e
+li x4, 0xe8dac663f0e58650;
+li x5, 0x3d7c95f9e5f0307e;
+add x6, x4, x5;
+sm3p1 x4, x6;
+add x7, x4, x5;
+RVTEST_SIGUPD(x31,x6,264);
+RVTEST_SIGUPD(x31,x4,272);
+RVTEST_SIGUPD(x31,x7,280);
+
+inst_4:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+xor x7, x5, x6;
+sm3p1 x5, x7;
+xor x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,288);
+RVTEST_SIGUPD(x31,x5,296);
+RVTEST_SIGUPD(x31,x8,304);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+not x7, x6;
+sm3p1 x5, x7;
+not x8, x5;
+RVTEST_SIGUPD(x31,x7,312);
+RVTEST_SIGUPD(x31,x5,320);
+RVTEST_SIGUPD(x31,x8,328);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x7; dest1:x5; op1val:0x807da245d814d575; op2val:0x3d06143769b1dcbf
+li x5, 0x807da245d814d575;
+li x6, 0x3d06143769b1dcbf;
+add x7, x5, x6;
+sm3p1 x5, x7;
+add x8, x5, x6;
+RVTEST_SIGUPD(x31,x7,336);
+RVTEST_SIGUPD(x31,x5,344);
+RVTEST_SIGUPD(x31,x8,352);
+
+inst_5:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+xor x8, x6, x7;
+sm3p1 x6, x8;
+xor x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,360);
+RVTEST_SIGUPD(x31,x6,368);
+RVTEST_SIGUPD(x31,x9,376);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+not x8, x7;
+sm3p1 x6, x8;
+not x9, x6;
+RVTEST_SIGUPD(x31,x8,384);
+RVTEST_SIGUPD(x31,x6,392);
+RVTEST_SIGUPD(x31,x9,400);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x8; dest1:x6; op1val:0x7213516d6a013380; op2val:0x4652f62dae4839a1
+li x6, 0x7213516d6a013380;
+li x7, 0x4652f62dae4839a1;
+add x8, x6, x7;
+sm3p1 x6, x8;
+add x9, x6, x7;
+RVTEST_SIGUPD(x31,x8,408);
+RVTEST_SIGUPD(x31,x6,416);
+RVTEST_SIGUPD(x31,x9,424);
+
+inst_6:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+xor x9, x7, x8;
+sm3p1 x7, x9;
+xor x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,432);
+RVTEST_SIGUPD(x31,x7,440);
+RVTEST_SIGUPD(x31,x10,448);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+not x9, x8;
+sm3p1 x7, x9;
+not x10, x7;
+RVTEST_SIGUPD(x31,x9,456);
+RVTEST_SIGUPD(x31,x7,464);
+RVTEST_SIGUPD(x31,x10,472);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x9; dest1:x7; op1val:0x53fbff6c58fa6e1c; op2val:0x0b2e2669b66b3284
+li x7, 0x53fbff6c58fa6e1c;
+li x8, 0x0b2e2669b66b3284;
+add x9, x7, x8;
+sm3p1 x7, x9;
+add x10, x7, x8;
+RVTEST_SIGUPD(x31,x9,480);
+RVTEST_SIGUPD(x31,x7,488);
+RVTEST_SIGUPD(x31,x10,496);
+
+inst_7:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+xor x10, x8, x9;
+sm3p1 x8, x10;
+xor x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,504);
+RVTEST_SIGUPD(x31,x8,512);
+RVTEST_SIGUPD(x31,x11,520);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+not x10, x9;
+sm3p1 x8, x10;
+not x11, x8;
+RVTEST_SIGUPD(x31,x10,528);
+RVTEST_SIGUPD(x31,x8,536);
+RVTEST_SIGUPD(x31,x11,544);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x10; dest1:x8; op1val:0xe918be9ffe057dc5; op2val:0x1011eeb47ff822ed
+li x8, 0xe918be9ffe057dc5;
+li x9, 0x1011eeb47ff822ed;
+add x10, x8, x9;
+sm3p1 x8, x10;
+add x11, x8, x9;
+RVTEST_SIGUPD(x31,x10,552);
+RVTEST_SIGUPD(x31,x8,560);
+RVTEST_SIGUPD(x31,x11,568);
+
+inst_8:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+xor x11, x9, x10;
+sm3p1 x9, x11;
+xor x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,576);
+RVTEST_SIGUPD(x31,x9,584);
+RVTEST_SIGUPD(x31,x12,592);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+not x11, x10;
+sm3p1 x9, x11;
+not x12, x9;
+RVTEST_SIGUPD(x31,x11,600);
+RVTEST_SIGUPD(x31,x9,608);
+RVTEST_SIGUPD(x31,x12,616);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x11; dest1:x9; op1val:0xb3a63fa37d69ceef; op2val:0x70fc1afc8f0846a2
+li x9, 0xb3a63fa37d69ceef;
+li x10, 0x70fc1afc8f0846a2;
+add x11, x9, x10;
+sm3p1 x9, x11;
+add x12, x9, x10;
+RVTEST_SIGUPD(x31,x11,624);
+RVTEST_SIGUPD(x31,x9,632);
+RVTEST_SIGUPD(x31,x12,640);
+
+inst_9:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+xor x12, x10, x11;
+sm3p1 x10, x12;
+xor x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,648);
+RVTEST_SIGUPD(x31,x10,656);
+RVTEST_SIGUPD(x31,x13,664);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+not x12, x11;
+sm3p1 x10, x12;
+not x13, x10;
+RVTEST_SIGUPD(x31,x12,672);
+RVTEST_SIGUPD(x31,x10,680);
+RVTEST_SIGUPD(x31,x13,688);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x12; dest1:x10; op1val:0xccadb61ffe20ce1c; op2val:0x72745307ec325eec
+li x10, 0xccadb61ffe20ce1c;
+li x11, 0x72745307ec325eec;
+add x12, x10, x11;
+sm3p1 x10, x12;
+add x13, x10, x11;
+RVTEST_SIGUPD(x31,x12,696);
+RVTEST_SIGUPD(x31,x10,704);
+RVTEST_SIGUPD(x31,x13,712);
+
+inst_10:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+xor x13, x11, x12;
+sm3p1 x11, x13;
+xor x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,720);
+RVTEST_SIGUPD(x31,x11,728);
+RVTEST_SIGUPD(x31,x14,736);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+not x13, x12;
+sm3p1 x11, x13;
+not x14, x11;
+RVTEST_SIGUPD(x31,x13,744);
+RVTEST_SIGUPD(x31,x11,752);
+RVTEST_SIGUPD(x31,x14,760);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x13; dest1:x11; op1val:0xa0e0bd86d4551408; op2val:0xcebe24d906600792
+li x11, 0xa0e0bd86d4551408;
+li x12, 0xcebe24d906600792;
+add x13, x11, x12;
+sm3p1 x11, x13;
+add x14, x11, x12;
+RVTEST_SIGUPD(x31,x13,768);
+RVTEST_SIGUPD(x31,x11,776);
+RVTEST_SIGUPD(x31,x14,784);
+
+inst_11:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+xor x14, x12, x13;
+sm3p1 x12, x14;
+xor x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,792);
+RVTEST_SIGUPD(x31,x12,800);
+RVTEST_SIGUPD(x31,x15,808);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+not x14, x13;
+sm3p1 x12, x14;
+not x15, x12;
+RVTEST_SIGUPD(x31,x14,816);
+RVTEST_SIGUPD(x31,x12,824);
+RVTEST_SIGUPD(x31,x15,832);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x14; dest1:x12; op1val:0xd1142724fb37bec8; op2val:0xab8534c129a2575f
+li x12, 0xd1142724fb37bec8;
+li x13, 0xab8534c129a2575f;
+add x14, x12, x13;
+sm3p1 x12, x14;
+add x15, x12, x13;
+RVTEST_SIGUPD(x31,x14,840);
+RVTEST_SIGUPD(x31,x12,848);
+RVTEST_SIGUPD(x31,x15,856);
+
+inst_12:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+xor x15, x13, x14;
+sm3p1 x13, x15;
+xor x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,864);
+RVTEST_SIGUPD(x31,x13,872);
+RVTEST_SIGUPD(x31,x16,880);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+not x15, x14;
+sm3p1 x13, x15;
+not x16, x13;
+RVTEST_SIGUPD(x31,x15,888);
+RVTEST_SIGUPD(x31,x13,896);
+RVTEST_SIGUPD(x31,x16,904);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x15; dest1:x13; op1val:0x98f7c41c44115b04; op2val:0x01fbbe93a08b84f3
+li x13, 0x98f7c41c44115b04;
+li x14, 0x01fbbe93a08b84f3;
+add x15, x13, x14;
+sm3p1 x13, x15;
+add x16, x13, x14;
+RVTEST_SIGUPD(x31,x15,912);
+RVTEST_SIGUPD(x31,x13,920);
+RVTEST_SIGUPD(x31,x16,928);
+
+inst_13:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+xor x16, x14, x15;
+sm3p1 x14, x16;
+xor x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,936);
+RVTEST_SIGUPD(x31,x14,944);
+RVTEST_SIGUPD(x31,x17,952);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+not x16, x15;
+sm3p1 x14, x16;
+not x17, x14;
+RVTEST_SIGUPD(x31,x16,960);
+RVTEST_SIGUPD(x31,x14,968);
+RVTEST_SIGUPD(x31,x17,976);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x16; dest1:x14; op1val:0x5916d2810e24d9cc; op2val:0x74f5add55c37849a
+li x14, 0x5916d2810e24d9cc;
+li x15, 0x74f5add55c37849a;
+add x16, x14, x15;
+sm3p1 x14, x16;
+add x17, x14, x15;
+RVTEST_SIGUPD(x31,x16,984);
+RVTEST_SIGUPD(x31,x14,992);
+RVTEST_SIGUPD(x31,x17,1000);
+
+inst_14:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+xor x17, x15, x16;
+sm3p1 x15, x17;
+xor x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1008);
+RVTEST_SIGUPD(x31,x15,1016);
+RVTEST_SIGUPD(x31,x18,1024);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+not x17, x16;
+sm3p1 x15, x17;
+not x18, x15;
+RVTEST_SIGUPD(x31,x17,1032);
+RVTEST_SIGUPD(x31,x15,1040);
+RVTEST_SIGUPD(x31,x18,1048);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x17; dest1:x15; op1val:0x46ed745fb9fef1d6; op2val:0x9651ee657a1d33ca
+li x15, 0x46ed745fb9fef1d6;
+li x16, 0x9651ee657a1d33ca;
+add x17, x15, x16;
+sm3p1 x15, x17;
+add x18, x15, x16;
+RVTEST_SIGUPD(x31,x17,1056);
+RVTEST_SIGUPD(x31,x15,1064);
+RVTEST_SIGUPD(x31,x18,1072);
+
+inst_15:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+xor x18, x16, x17;
+sm3p1 x16, x18;
+xor x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1080);
+RVTEST_SIGUPD(x31,x16,1088);
+RVTEST_SIGUPD(x31,x19,1096);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+not x18, x17;
+sm3p1 x16, x18;
+not x19, x16;
+RVTEST_SIGUPD(x31,x18,1104);
+RVTEST_SIGUPD(x31,x16,1112);
+RVTEST_SIGUPD(x31,x19,1120);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x18; dest1:x16; op1val:0x9c3d087c65835bdf; op2val:0x9b11d383484641f5
+li x16, 0x9c3d087c65835bdf;
+li x17, 0x9b11d383484641f5;
+add x18, x16, x17;
+sm3p1 x16, x18;
+add x19, x16, x17;
+RVTEST_SIGUPD(x31,x18,1128);
+RVTEST_SIGUPD(x31,x16,1136);
+RVTEST_SIGUPD(x31,x19,1144);
+
+inst_16:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+xor x19, x17, x18;
+sm3p1 x17, x19;
+xor x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1152);
+RVTEST_SIGUPD(x31,x17,1160);
+RVTEST_SIGUPD(x31,x20,1168);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+not x19, x18;
+sm3p1 x17, x19;
+not x20, x17;
+RVTEST_SIGUPD(x31,x19,1176);
+RVTEST_SIGUPD(x31,x17,1184);
+RVTEST_SIGUPD(x31,x20,1192);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x19; dest1:x17; op1val:0x041bbaab97eb7c0f; op2val:0x93017690e356529c
+li x17, 0x041bbaab97eb7c0f;
+li x18, 0x93017690e356529c;
+add x19, x17, x18;
+sm3p1 x17, x19;
+add x20, x17, x18;
+RVTEST_SIGUPD(x31,x19,1200);
+RVTEST_SIGUPD(x31,x17,1208);
+RVTEST_SIGUPD(x31,x20,1216);
+
+inst_17:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+xor x20, x18, x19;
+sm3p1 x18, x20;
+xor x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1224);
+RVTEST_SIGUPD(x31,x18,1232);
+RVTEST_SIGUPD(x31,x21,1240);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+not x20, x19;
+sm3p1 x18, x20;
+not x21, x18;
+RVTEST_SIGUPD(x31,x20,1248);
+RVTEST_SIGUPD(x31,x18,1256);
+RVTEST_SIGUPD(x31,x21,1264);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x20; dest1:x18; op1val:0xef677106dc17ae6e; op2val:0xc5d09b942be2d8c9
+li x18, 0xef677106dc17ae6e;
+li x19, 0xc5d09b942be2d8c9;
+add x20, x18, x19;
+sm3p1 x18, x20;
+add x21, x18, x19;
+RVTEST_SIGUPD(x31,x20,1272);
+RVTEST_SIGUPD(x31,x18,1280);
+RVTEST_SIGUPD(x31,x21,1288);
+
+inst_18:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+xor x21, x19, x20;
+sm3p1 x19, x21;
+xor x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1296);
+RVTEST_SIGUPD(x31,x19,1304);
+RVTEST_SIGUPD(x31,x22,1312);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+not x21, x20;
+sm3p1 x19, x21;
+not x22, x19;
+RVTEST_SIGUPD(x31,x21,1320);
+RVTEST_SIGUPD(x31,x19,1328);
+RVTEST_SIGUPD(x31,x22,1336);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x21; dest1:x19; op1val:0x755961a98347ddf5; op2val:0x18d71be431c00570
+li x19, 0x755961a98347ddf5;
+li x20, 0x18d71be431c00570;
+add x21, x19, x20;
+sm3p1 x19, x21;
+add x22, x19, x20;
+RVTEST_SIGUPD(x31,x21,1344);
+RVTEST_SIGUPD(x31,x19,1352);
+RVTEST_SIGUPD(x31,x22,1360);
+
+inst_19:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+xor x22, x20, x21;
+sm3p1 x20, x22;
+xor x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1368);
+RVTEST_SIGUPD(x31,x20,1376);
+RVTEST_SIGUPD(x31,x23,1384);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+not x22, x21;
+sm3p1 x20, x22;
+not x23, x20;
+RVTEST_SIGUPD(x31,x22,1392);
+RVTEST_SIGUPD(x31,x20,1400);
+RVTEST_SIGUPD(x31,x23,1408);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x22; dest1:x20; op1val:0x8f2248c25c3577f5; op2val:0x2a5dc0a00d453cdf
+li x20, 0x8f2248c25c3577f5;
+li x21, 0x2a5dc0a00d453cdf;
+add x22, x20, x21;
+sm3p1 x20, x22;
+add x23, x20, x21;
+RVTEST_SIGUPD(x31,x22,1416);
+RVTEST_SIGUPD(x31,x20,1424);
+RVTEST_SIGUPD(x31,x23,1432);
+
+inst_20:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+xor x23, x21, x22;
+sm3p1 x21, x23;
+xor x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1440);
+RVTEST_SIGUPD(x31,x21,1448);
+RVTEST_SIGUPD(x31,x24,1456);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+not x23, x22;
+sm3p1 x21, x23;
+not x24, x21;
+RVTEST_SIGUPD(x31,x23,1464);
+RVTEST_SIGUPD(x31,x21,1472);
+RVTEST_SIGUPD(x31,x24,1480);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x23; dest1:x21; op1val:0x6dc3cceec36ffd4b; op2val:0xc2713ce25868105b
+li x21, 0x6dc3cceec36ffd4b;
+li x22, 0xc2713ce25868105b;
+add x23, x21, x22;
+sm3p1 x21, x23;
+add x24, x21, x22;
+RVTEST_SIGUPD(x31,x23,1488);
+RVTEST_SIGUPD(x31,x21,1496);
+RVTEST_SIGUPD(x31,x24,1504);
+
+inst_21:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+xor x24, x22, x23;
+sm3p1 x22, x24;
+xor x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1512);
+RVTEST_SIGUPD(x31,x22,1520);
+RVTEST_SIGUPD(x31,x25,1528);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+not x24, x23;
+sm3p1 x22, x24;
+not x25, x22;
+RVTEST_SIGUPD(x31,x24,1536);
+RVTEST_SIGUPD(x31,x22,1544);
+RVTEST_SIGUPD(x31,x25,1552);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x24; dest1:x22; op1val:0xe4367ccad9716f2c; op2val:0x9ea76f0885958881
+li x22, 0xe4367ccad9716f2c;
+li x23, 0x9ea76f0885958881;
+add x24, x22, x23;
+sm3p1 x22, x24;
+add x25, x22, x23;
+RVTEST_SIGUPD(x31,x24,1560);
+RVTEST_SIGUPD(x31,x22,1568);
+RVTEST_SIGUPD(x31,x25,1576);
+
+inst_22:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+xor x25, x23, x24;
+sm3p1 x23, x25;
+xor x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1584);
+RVTEST_SIGUPD(x31,x23,1592);
+RVTEST_SIGUPD(x31,x26,1600);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+not x25, x24;
+sm3p1 x23, x25;
+not x26, x23;
+RVTEST_SIGUPD(x31,x25,1608);
+RVTEST_SIGUPD(x31,x23,1616);
+RVTEST_SIGUPD(x31,x26,1624);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x25; dest1:x23; op1val:0x37c4c6b99530db93; op2val:0x132a717606aec150
+li x23, 0x37c4c6b99530db93;
+li x24, 0x132a717606aec150;
+add x25, x23, x24;
+sm3p1 x23, x25;
+add x26, x23, x24;
+RVTEST_SIGUPD(x31,x25,1632);
+RVTEST_SIGUPD(x31,x23,1640);
+RVTEST_SIGUPD(x31,x26,1648);
+
+inst_23:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+xor x26, x24, x25;
+sm3p1 x24, x26;
+xor x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1656);
+RVTEST_SIGUPD(x31,x24,1664);
+RVTEST_SIGUPD(x31,x27,1672);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+not x26, x25;
+sm3p1 x24, x26;
+not x27, x24;
+RVTEST_SIGUPD(x31,x26,1680);
+RVTEST_SIGUPD(x31,x24,1688);
+RVTEST_SIGUPD(x31,x27,1696);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x26; dest1:x24; op1val:0x04d3e5f42bccd6b6; op2val:0x339863c4d216eea8
+li x24, 0x04d3e5f42bccd6b6;
+li x25, 0x339863c4d216eea8;
+add x26, x24, x25;
+sm3p1 x24, x26;
+add x27, x24, x25;
+RVTEST_SIGUPD(x31,x26,1704);
+RVTEST_SIGUPD(x31,x24,1712);
+RVTEST_SIGUPD(x31,x27,1720);
+
+inst_24:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+xor x27, x25, x26;
+sm3p1 x25, x27;
+xor x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1728);
+RVTEST_SIGUPD(x31,x25,1736);
+RVTEST_SIGUPD(x31,x28,1744);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+not x27, x26;
+sm3p1 x25, x27;
+not x28, x25;
+RVTEST_SIGUPD(x31,x27,1752);
+RVTEST_SIGUPD(x31,x25,1760);
+RVTEST_SIGUPD(x31,x28,1768);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x27; dest1:x25; op1val:0xd6ac851f07155a89; op2val:0x2d885062faa97965
+li x25, 0xd6ac851f07155a89;
+li x26, 0x2d885062faa97965;
+add x27, x25, x26;
+sm3p1 x25, x27;
+add x28, x25, x26;
+RVTEST_SIGUPD(x31,x27,1776);
+RVTEST_SIGUPD(x31,x25,1784);
+RVTEST_SIGUPD(x31,x28,1792);
+
+inst_25:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+xor x28, x26, x27;
+sm3p1 x26, x28;
+xor x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1800);
+RVTEST_SIGUPD(x31,x26,1808);
+RVTEST_SIGUPD(x31,x29,1816);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+not x28, x27;
+sm3p1 x26, x28;
+not x29, x26;
+RVTEST_SIGUPD(x31,x28,1824);
+RVTEST_SIGUPD(x31,x26,1832);
+RVTEST_SIGUPD(x31,x29,1840);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x28; dest1:x26; op1val:0x8d3ba7550c3c31a8; op2val:0xb3e73cbb0d8258c4
+li x26, 0x8d3ba7550c3c31a8;
+li x27, 0xb3e73cbb0d8258c4;
+add x28, x26, x27;
+sm3p1 x26, x28;
+add x29, x26, x27;
+RVTEST_SIGUPD(x31,x28,1848);
+RVTEST_SIGUPD(x31,x26,1856);
+RVTEST_SIGUPD(x31,x29,1864);
+
+inst_26:
+// Forwarded xor into sm3p1 & the result back into xor
+// opcode: sm3p1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+xor x29, x27, x28;
+sm3p1 x27, x29;
+xor x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1872);
+RVTEST_SIGUPD(x31,x27,1880);
+RVTEST_SIGUPD(x31,x30,1888);
+
+// Forwarded not into sm3p1 & the result back into not
+// opcode: sm3p1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+not x29, x28;
+sm3p1 x27, x29;
+not x30, x27;
+RVTEST_SIGUPD(x31,x29,1896);
+RVTEST_SIGUPD(x31,x27,1904);
+RVTEST_SIGUPD(x31,x30,1912);
+
+// Forwarded add into sm3p1 & the result back into add
+// opcode: sm3p1; op1:x29; dest1:x27; op1val:0x239853f9120ff957; op2val:0x2d13320e40d0e5e7
+li x27, 0x239853f9120ff957;
+li x28, 0x2d13320e40d0e5e7;
+add x29, x27, x28;
+sm3p1 x27, x29;
+add x30, x27, x28;
+RVTEST_SIGUPD(x31,x29,1920);
+RVTEST_SIGUPD(x31,x27,1928);
+RVTEST_SIGUPD(x31,x30,1936);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 243*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S
new file mode 100644
index 000000000..5a4aa340b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm3p1-rwp2.S
@@ -0,0 +1,304 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm3p1)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+la x1, rvtest_data
+
+inst_0:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x2; dest1:x3;
+LREG x2, 0(x1);
+sm3p1 x3, x2;
+RVTEST_SIGUPD(x31,x2,0);
+RVTEST_SIGUPD(x31,x3,8);
+
+inst_1:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x3; dest1:x4;
+LREG x3, 8(x1);
+sm3p1 x4, x3;
+RVTEST_SIGUPD(x31,x3,16);
+RVTEST_SIGUPD(x31,x4,24);
+
+inst_2:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x4; dest1:x5;
+LREG x4, 16(x1);
+sm3p1 x5, x4;
+RVTEST_SIGUPD(x31,x4,32);
+RVTEST_SIGUPD(x31,x5,40);
+
+inst_3:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x5; dest1:x6;
+LREG x5, 24(x1);
+sm3p1 x6, x5;
+RVTEST_SIGUPD(x31,x5,48);
+RVTEST_SIGUPD(x31,x6,56);
+
+inst_4:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x6; dest1:x7;
+LREG x6, 32(x1);
+sm3p1 x7, x6;
+RVTEST_SIGUPD(x31,x6,64);
+RVTEST_SIGUPD(x31,x7,72);
+
+inst_5:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x7; dest1:x8;
+LREG x7, 40(x1);
+sm3p1 x8, x7;
+RVTEST_SIGUPD(x31,x7,80);
+RVTEST_SIGUPD(x31,x8,88);
+
+inst_6:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x8; dest1:x9;
+LREG x8, 48(x1);
+sm3p1 x9, x8;
+RVTEST_SIGUPD(x31,x8,96);
+RVTEST_SIGUPD(x31,x9,104);
+
+inst_7:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x9; dest1:x10;
+LREG x9, 56(x1);
+sm3p1 x10, x9;
+RVTEST_SIGUPD(x31,x9,112);
+RVTEST_SIGUPD(x31,x10,120);
+
+inst_8:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x10; dest1:x11;
+LREG x10, 64(x1);
+sm3p1 x11, x10;
+RVTEST_SIGUPD(x31,x10,128);
+RVTEST_SIGUPD(x31,x11,136);
+
+inst_9:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x11; dest1:x12;
+LREG x11, 72(x1);
+sm3p1 x12, x11;
+RVTEST_SIGUPD(x31,x11,144);
+RVTEST_SIGUPD(x31,x12,152);
+
+inst_10:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x12; dest1:x13;
+LREG x12, 80(x1);
+sm3p1 x13, x12;
+RVTEST_SIGUPD(x31,x12,160);
+RVTEST_SIGUPD(x31,x13,168);
+
+inst_11:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x13; dest1:x14;
+LREG x13, 88(x1);
+sm3p1 x14, x13;
+RVTEST_SIGUPD(x31,x13,176);
+RVTEST_SIGUPD(x31,x14,184);
+
+inst_12:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x14; dest1:x15;
+LREG x14, 96(x1);
+sm3p1 x15, x14;
+RVTEST_SIGUPD(x31,x14,192);
+RVTEST_SIGUPD(x31,x15,200);
+
+inst_13:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x15; dest1:x16;
+LREG x15, 104(x1);
+sm3p1 x16, x15;
+RVTEST_SIGUPD(x31,x15,208);
+RVTEST_SIGUPD(x31,x16,216);
+
+inst_14:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x16; dest1:x17;
+LREG x16, 112(x1);
+sm3p1 x17, x16;
+RVTEST_SIGUPD(x31,x16,224);
+RVTEST_SIGUPD(x31,x17,232);
+
+inst_15:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x17; dest1:x18;
+LREG x17, 120(x1);
+sm3p1 x18, x17;
+RVTEST_SIGUPD(x31,x17,240);
+RVTEST_SIGUPD(x31,x18,248);
+
+inst_16:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x18; dest1:x19;
+LREG x18, 128(x1);
+sm3p1 x19, x18;
+RVTEST_SIGUPD(x31,x18,256);
+RVTEST_SIGUPD(x31,x19,264);
+
+inst_17:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x19; dest1:x20;
+LREG x19, 136(x1);
+sm3p1 x20, x19;
+RVTEST_SIGUPD(x31,x19,272);
+RVTEST_SIGUPD(x31,x20,280);
+
+inst_18:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x20; dest1:x21;
+LREG x20, 144(x1);
+sm3p1 x21, x20;
+RVTEST_SIGUPD(x31,x20,288);
+RVTEST_SIGUPD(x31,x21,296);
+
+inst_19:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x21; dest1:x22;
+LREG x21, 152(x1);
+sm3p1 x22, x21;
+RVTEST_SIGUPD(x31,x21,304);
+RVTEST_SIGUPD(x31,x22,312);
+
+inst_20:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x22; dest1:x23;
+LREG x22, 160(x1);
+sm3p1 x23, x22;
+RVTEST_SIGUPD(x31,x22,320);
+RVTEST_SIGUPD(x31,x23,328);
+
+inst_21:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x23; dest1:x24;
+LREG x23, 168(x1);
+sm3p1 x24, x23;
+RVTEST_SIGUPD(x31,x23,336);
+RVTEST_SIGUPD(x31,x24,344);
+
+inst_22:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x24; dest1:x25;
+LREG x24, 176(x1);
+sm3p1 x25, x24;
+RVTEST_SIGUPD(x31,x24,352);
+RVTEST_SIGUPD(x31,x25,360);
+
+inst_23:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x25; dest1:x26;
+LREG x25, 184(x1);
+sm3p1 x26, x25;
+RVTEST_SIGUPD(x31,x25,368);
+RVTEST_SIGUPD(x31,x26,376);
+
+inst_24:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x26; dest1:x27;
+LREG x26, 192(x1);
+sm3p1 x27, x26;
+RVTEST_SIGUPD(x31,x26,384);
+RVTEST_SIGUPD(x31,x27,392);
+
+inst_25:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x27; dest1:x28;
+LREG x27, 200(x1);
+sm3p1 x28, x27;
+RVTEST_SIGUPD(x31,x27,400);
+RVTEST_SIGUPD(x31,x28,408);
+
+inst_26:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x28; dest1:x29;
+LREG x28, 208(x1);
+sm3p1 x29, x28;
+RVTEST_SIGUPD(x31,x28,416);
+RVTEST_SIGUPD(x31,x29,424);
+
+inst_27:
+// Checking load-to-use hazard!
+// opcode: sm3p1; op1:x29; dest1:x30;
+LREG x29, 216(x1);
+sm3p1 x30, x29;
+RVTEST_SIGUPD(x31,x29,432);
+RVTEST_SIGUPD(x31,x30,440);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.dword 0x08577eb1924770d3
+.dword 0x93fdcab87b89296c
+.dword 0xd2d6b8777dc59a3a
+.dword 0xcf84b683a749f9c5
+.dword 0x854a965708ceac39
+.dword 0x137a977753e8eb43
+.dword 0x5c74e45eff1e5bef
+.dword 0xdc3383836b9f15c4
+.dword 0x5ae6a2289a6ab329
+.dword 0x432779eeacca7f0d
+.dword 0xaf949e5e2cb7362c
+.dword 0x5cd2875ea96ec2b3
+.dword 0x9d02fc90708cc1b6
+.dword 0x953b00b00b54aa22
+.dword 0x224c06013c53d0e3
+.dword 0xe8dac663f0e58650
+.dword 0x3d7c95f9e5f0307e
+.dword 0x8c8a18b2aaac3142
+.dword 0x785036de6f9fb997
+.dword 0x95a4d257a7298c66
+.dword 0x807da245d814d575
+.dword 0x3d06143769b1dcbf
+.dword 0x7f21682208208d09
+.dword 0x14b91c79dae98554
+.dword 0xc5ec6148c6880007
+.dword 0x7213516d6a013380
+.dword 0x4652f62dae4839a1
+.dword 0x85986adb9e044706
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S
new file mode 100644
index 000000000..5b11998a0
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-01.S
@@ -0,0 +1,1489 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Thu Aug 12 11:00:04 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sm4ed instruction of the RISC-V _Zks extension for the sm4ed covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I_Zks")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sm4ed)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",sm4ed)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKsed.*);def TEST_CASE_1=True;",sm4ed)
+
+RVTEST_SIGBASE( x21,signature_x21_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x12, rs2==x16, rd==x2, rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 0 
+// opcode: sm4ed; rd: x2; op1:x12; op2:x16; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x0
+TEST_RI_OP(sm4ed, x2, x12, x16, 0x0, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x21, 0, x7)
+
+inst_1:
+// rs2 == rd != rs1, rs1==x6, rs2==x15, rd==x15, rs1_val == 0xbc36b151aeb006fc and rs2_val == 0x2cab43d86576923c and imm_val == 0x3 
+// opcode: sm4ed; rd: x15; op1:x6; op2:x15; op1val:0xbc36b151aeb006fc; op2val:0x2cab43d86576923c; immval:0x3
+TEST_RI_OP(sm4ed, x15, x6, x15, 0x3, 0x0000000000000000, 0xbc36b151aeb006fc, 0x2cab43d86576923c, x21, 8, x7)
+
+inst_2:
+// rs1 == rs2 != rd, rs1==x28, rs2==x28, rd==x12, rs1_val == 0x156fe482f9fcd292 and rs2_val == 0x24c6435c8dca0621 and imm_val == 0x0 
+// opcode: sm4ed; rd: x12; op1:x28; op2:x28; op1val:0x156fe482f9fcd292; op2val:0x156fe482f9fcd292; immval:0x0
+TEST_RI_OP(sm4ed, x12, x28, x28, 0x0, 0x0000000000000000, 0x156fe482f9fcd292, 0x156fe482f9fcd292, x21, 16, x7)
+
+inst_3:
+// rs1 == rs2 == rd, rs1==x3, rs2==x3, rd==x3, rs1_val == 0xa757e91e027e5943 and rs2_val == 0xda73ec2605e6750f and imm_val == 0x2 
+// opcode: sm4ed; rd: x3; op1:x3; op2:x3; op1val:0xa757e91e027e5943; op2val:0xa757e91e027e5943; immval:0x2
+TEST_RI_OP(sm4ed, x3, x3, x3, 0x2, 0x0000000000000000, 0xa757e91e027e5943, 0xa757e91e027e5943, x21, 24, x7)
+
+inst_4:
+// rs1 == rd != rs2, rs1==x20, rs2==x12, rd==x20, rs1_val == 0xf452cbd863fa921d and rs2_val == 0x4b6587d88ef464d1 and imm_val == 0x3 
+// opcode: sm4ed; rd: x20; op1:x20; op2:x12; op1val:0xf452cbd863fa921d; op2val:0x4b6587d88ef464d1; immval:0x3
+TEST_RI_OP(sm4ed, x20, x20, x12, 0x3, 0x0000000000000000, 0xf452cbd863fa921d, 0x4b6587d88ef464d1, x21, 32, x7)
+
+inst_5:
+// rs1==x23, rs2==x11, rd==x1, rs1_val == 0xd40f46a4356c1dcc and rs2_val == 0x30c33d97184e0f23 and imm_val == 0x0 
+// opcode: sm4ed; rd: x1; op1:x23; op2:x11; op1val:0xd40f46a4356c1dcc; op2val:0x30c33d97184e0f23; immval:0x0
+TEST_RI_OP(sm4ed, x1, x23, x11, 0x0, 0x0000000000000000, 0xd40f46a4356c1dcc, 0x30c33d97184e0f23, x21, 40, x7)
+
+inst_6:
+// rs1==x17, rs2==x9, rd==x14, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 and imm_val == 0x2 
+// opcode: sm4ed; rd: x14; op1:x17; op2:x9; op1val:0x6d23c0488a6019c1; op2val:0x860bdaad7447a088; immval:0x2
+TEST_RI_OP(sm4ed, x14, x17, x9, 0x2, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x21, 48, x7)
+
+inst_7:
+// rs1==x27, rs2==x2, rd==x9, rs1_val == 0x17168ab3a4351379 and rs2_val == 0xbbb4f560f222070c and imm_val == 0x0 
+// opcode: sm4ed; rd: x9; op1:x27; op2:x2; op1val:0x17168ab3a4351379; op2val:0xbbb4f560f222070c; immval:0x0
+TEST_RI_OP(sm4ed, x9, x27, x2, 0x0, 0x0000000000000000, 0x17168ab3a4351379, 0xbbb4f560f222070c, x21, 56, x7)
+
+inst_8:
+// rs1==x16, rs2==x19, rd==x5, rs1_val == 0x3fb0fe60ef1d54db and rs2_val == 0x09ff42451826a804 and imm_val == 0x1 
+// opcode: sm4ed; rd: x5; op1:x16; op2:x19; op1val:0x3fb0fe60ef1d54db; op2val:0x9ff42451826a804; immval:0x1
+TEST_RI_OP(sm4ed, x5, x16, x19, 0x1, 0x0000000000000000, 0x3fb0fe60ef1d54db, 0x9ff42451826a804, x21, 64, x7)
+
+inst_9:
+// rs1==x4, rs2==x1, rd==x18, rs1_val == 0xcc7b22010ca3ef52 and rs2_val == 0xc150f4d3df74d068 and imm_val == 0x1 
+// opcode: sm4ed; rd: x18; op1:x4; op2:x1; op1val:0xcc7b22010ca3ef52; op2val:0xc150f4d3df74d068; immval:0x1
+TEST_RI_OP(sm4ed, x18, x4, x1, 0x1, 0x0000000000000000, 0xcc7b22010ca3ef52, 0xc150f4d3df74d068, x21, 72, x7)
+
+inst_10:
+// rs1==x24, rs2==x29, rd==x28, rs1_val == 0x358a9235987daa20 and rs2_val == 0xb369e10209f393d7 and imm_val == 0x1 
+// opcode: sm4ed; rd: x28; op1:x24; op2:x29; op1val:0x358a9235987daa20; op2val:0xb369e10209f393d7; immval:0x1
+TEST_RI_OP(sm4ed, x28, x24, x29, 0x1, 0x0000000000000000, 0x358a9235987daa20, 0xb369e10209f393d7, x21, 80, x7)
+
+inst_11:
+// rs1==x0, rs2==x25, rd==x11, rs1_val == 0x91766f62ba2be4d3 and rs2_val == 0x74a813d25570084b and imm_val == 0x0 
+// opcode: sm4ed; rd: x11; op1:x0; op2:x25; op1val:0x0; op2val:0x74a813d25570084b; immval:0x0
+TEST_RI_OP(sm4ed, x11, x0, x25, 0x0, 0x0000000000000000, 0x0, 0x74a813d25570084b, x21, 88, x7)
+
+inst_12:
+// rs1==x10, rs2==x31, rd==x30, rs1_val == 0xb7c1fc5f1efa1095 and rs2_val == 0xe2cbb9ab3819fe4d and imm_val == 0x1 
+// opcode: sm4ed; rd: x30; op1:x10; op2:x31; op1val:0xb7c1fc5f1efa1095; op2val:0xe2cbb9ab3819fe4d; immval:0x1
+TEST_RI_OP(sm4ed, x30, x10, x31, 0x1, 0x0000000000000000, 0xb7c1fc5f1efa1095, 0xe2cbb9ab3819fe4d, x21, 96, x7)
+
+inst_13:
+// rs1==x15, rs2==x18, rd==x27, rs1_val == 0xa6c9253a4cc6382e and rs2_val == 0x25ae27ee4113ee60 and imm_val == 0x2 
+// opcode: sm4ed; rd: x27; op1:x15; op2:x18; op1val:0xa6c9253a4cc6382e; op2val:0x25ae27ee4113ee60; immval:0x2
+TEST_RI_OP(sm4ed, x27, x15, x18, 0x2, 0x0000000000000000, 0xa6c9253a4cc6382e, 0x25ae27ee4113ee60, x21, 104, x7)
+
+inst_14:
+// rs1==x11, rs2==x8, rd==x13, rs1_val == 0xf17f6920daaafe5c and rs2_val == 0x7bcad7c4ff9a1b80 and imm_val == 0x0 
+// opcode: sm4ed; rd: x13; op1:x11; op2:x8; op1val:0xf17f6920daaafe5c; op2val:0x7bcad7c4ff9a1b80; immval:0x0
+TEST_RI_OP(sm4ed, x13, x11, x8, 0x0, 0x0000000000000000, 0xf17f6920daaafe5c, 0x7bcad7c4ff9a1b80, x21, 112, x7)
+
+inst_15:
+// rs1==x14, rs2==x6, rd==x0, rs1_val == 0x3150e5fa299c3bcf and rs2_val == 0xe6fff3d9ec1ce9d2 and imm_val == 0x1 
+// opcode: sm4ed; rd: x0; op1:x14; op2:x6; op1val:0x3150e5fa299c3bcf; op2val:0xe6fff3d9ec1ce9d2; immval:0x1
+TEST_RI_OP(sm4ed, x0, x14, x6, 0x1, 0x0000000000000000, 0x3150e5fa299c3bcf, 0xe6fff3d9ec1ce9d2, x21, 120, x15)
+
+inst_16:
+// rs1==x29, rs2==x27, rd==x16, rs1_val == 0x1fc493caa371db42 and rs2_val == 0x9a4e9ef10171f4df and imm_val == 0x1 
+// opcode: sm4ed; rd: x16; op1:x29; op2:x27; op1val:0x1fc493caa371db42; op2val:0x9a4e9ef10171f4df; immval:0x1
+TEST_RI_OP(sm4ed, x16, x29, x27, 0x1, 0x0000000000000000, 0x1fc493caa371db42, 0x9a4e9ef10171f4df, x21, 128, x15)
+
+inst_17:
+// rs1==x5, rs2==x17, rd==x6, rs1_val == 0xf5faf2073430cb17 and rs2_val == 0x8e2eac2a760b3c5e and imm_val == 0x3 
+// opcode: sm4ed; rd: x6; op1:x5; op2:x17; op1val:0xf5faf2073430cb17; op2val:0x8e2eac2a760b3c5e; immval:0x3
+TEST_RI_OP(sm4ed, x6, x5, x17, 0x3, 0x0000000000000000, 0xf5faf2073430cb17, 0x8e2eac2a760b3c5e, x21, 136, x15)
+
+inst_18:
+// rs1==x19, rs2==x13, rd==x7, rs1_val == 0xbc991c531484f407 and rs2_val == 0x55d98c6e3459294e and imm_val == 0x2 
+// opcode: sm4ed; rd: x7; op1:x19; op2:x13; op1val:0xbc991c531484f407; op2val:0x55d98c6e3459294e; immval:0x2
+TEST_RI_OP(sm4ed, x7, x19, x13, 0x2, 0x0000000000000000, 0xbc991c531484f407, 0x55d98c6e3459294e, x21, 144, x15)
+RVTEST_SIGBASE( x3,signature_x3_0)
+
+inst_19:
+// rs1==x26, rs2==x22, rd==x23, rs1_val == 0x59885afcbb61a9cd and rs2_val == 0xccce240c81c1e7ff and imm_val == 0x0 
+// opcode: sm4ed; rd: x23; op1:x26; op2:x22; op1val:0x59885afcbb61a9cd; op2val:0xccce240c81c1e7ff; immval:0x0
+TEST_RI_OP(sm4ed, x23, x26, x22, 0x0, 0x0000000000000000, 0x59885afcbb61a9cd, 0xccce240c81c1e7ff, x3, 0, x15)
+
+inst_20:
+// rs1==x1, rs2==x21, rd==x4, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 and imm_val == 0x3 
+// opcode: sm4ed; rd: x4; op1:x1; op2:x21; op1val:0x75a3adb3254a9493; op2val:0xc5521660f3a3c571; immval:0x3
+TEST_RI_OP(sm4ed, x4, x1, x21, 0x3, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x3, 8, x15)
+
+inst_21:
+// rs1==x13, rs2==x30, rd==x31, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 3 
+// opcode: sm4ed; rd: x31; op1:x13; op2:x30; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x3
+TEST_RI_OP(sm4ed, x31, x13, x30, 0x3, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x3, 16, x15)
+
+inst_22:
+// rs1==x31, rs2==x20, rd==x22, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 2 
+// opcode: sm4ed; rd: x22; op1:x31; op2:x20; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x2
+TEST_RI_OP(sm4ed, x22, x31, x20, 0x2, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x3, 24, x15)
+
+inst_23:
+// rs1==x22, rs2==x23, rd==x29, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 1 
+// opcode: sm4ed; rd: x29; op1:x22; op2:x23; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x1
+TEST_RI_OP(sm4ed, x29, x22, x23, 0x1, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x3, 32, x15)
+
+inst_24:
+// rs1==x30, rs2==x26, rd==x10, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 0 
+// opcode: sm4ed; rd: x10; op1:x30; op2:x26; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x0
+TEST_RI_OP(sm4ed, x10, x30, x26, 0x0, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x3, 40, x15)
+
+inst_25:
+// rs1==x25, rs2==x7, rd==x19, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 3 
+// opcode: sm4ed; rd: x19; op1:x25; op2:x7; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x3
+TEST_RI_OP(sm4ed, x19, x25, x7, 0x3, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x3, 48, x15)
+
+inst_26:
+// rs1==x2, rs2==x4, rd==x26, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 2 
+// opcode: sm4ed; rd: x26; op1:x2; op2:x4; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x2
+TEST_RI_OP(sm4ed, x26, x2, x4, 0x2, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x3, 56, x15)
+
+inst_27:
+// rs1==x18, rs2==x14, rd==x24, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 1 
+// opcode: sm4ed; rd: x24; op1:x18; op2:x14; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x1
+TEST_RI_OP(sm4ed, x24, x18, x14, 0x1, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x3, 64, x15)
+
+inst_28:
+// rs1==x21, rs2==x10, rd==x17, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 0 
+// opcode: sm4ed; rd: x17; op1:x21; op2:x10; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x0
+TEST_RI_OP(sm4ed, x17, x21, x10, 0x0, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x3, 72, x15)
+
+inst_29:
+// rs1==x9, rs2==x24, rd==x25, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 3 
+// opcode: sm4ed; rd: x25; op1:x9; op2:x24; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x3
+TEST_RI_OP(sm4ed, x25, x9, x24, 0x3, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x3, 80, x15)
+
+inst_30:
+// rs1==x7, rs2==x5, rd==x8, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 2 
+// opcode: sm4ed; rd: x8; op1:x7; op2:x5; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x2
+TEST_RI_OP(sm4ed, x8, x7, x5, 0x2, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x3, 88, x15)
+
+inst_31:
+// rs1==x8, rs2==x0, rd==x21, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 1 
+// opcode: sm4ed; rd: x21; op1:x8; op2:x0; op1val:0xfbfaf9f8f7f6f5f4; op2val:0x0; immval:0x1
+TEST_RI_OP(sm4ed, x21, x8, x0, 0x1, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0x0, x3, 96, x15)
+
+inst_32:
+// rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x3, 104, x15)
+
+inst_33:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x3, 112, x1)
+
+inst_34:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x3, 120, x1)
+
+inst_35:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x3, 128, x1)
+
+inst_36:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x3, 136, x1)
+
+inst_37:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x3, 144, x1)
+
+inst_38:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x3, 152, x1)
+
+inst_39:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x3, 160, x1)
+
+inst_40:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x3, 168, x1)
+
+inst_41:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x3, 176, x1)
+
+inst_42:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x3, 184, x1)
+
+inst_43:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x3, 192, x1)
+
+inst_44:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x3, 200, x1)
+
+inst_45:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x3, 208, x1)
+
+inst_46:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x3, 216, x1)
+
+inst_47:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x3, 224, x1)
+
+inst_48:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x3, 232, x1)
+
+inst_49:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x3, 240, x1)
+
+inst_50:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x3, 248, x1)
+
+inst_51:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x3, 256, x1)
+
+inst_52:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x3, 264, x1)
+
+inst_53:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x3, 272, x1)
+
+inst_54:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x3, 280, x1)
+
+inst_55:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x3, 288, x1)
+
+inst_56:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x3, 296, x1)
+
+inst_57:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x3, 304, x1)
+
+inst_58:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x3, 312, x1)
+
+inst_59:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x3, 320, x1)
+
+inst_60:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x3, 328, x1)
+
+inst_61:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x3, 336, x1)
+
+inst_62:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x3, 344, x1)
+
+inst_63:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x3, 352, x1)
+
+inst_64:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x3, 360, x1)
+
+inst_65:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x3, 368, x1)
+
+inst_66:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x3, 376, x1)
+
+inst_67:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x3, 384, x1)
+
+inst_68:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x3, 392, x1)
+
+inst_69:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x3, 400, x1)
+
+inst_70:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x3, 408, x1)
+
+inst_71:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x3, 416, x1)
+
+inst_72:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x3, 424, x1)
+
+inst_73:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x3, 432, x1)
+
+inst_74:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x3, 440, x1)
+
+inst_75:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x3, 448, x1)
+
+inst_76:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x3, 456, x1)
+
+inst_77:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x3, 464, x1)
+
+inst_78:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x3, 472, x1)
+
+inst_79:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x3, 480, x1)
+
+inst_80:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x3, 488, x1)
+
+inst_81:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x3, 496, x1)
+
+inst_82:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x3, 504, x1)
+
+inst_83:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x3, 512, x1)
+
+inst_84:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x3, 520, x1)
+
+inst_85:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x3, 528, x1)
+
+inst_86:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x3, 536, x1)
+
+inst_87:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x3, 544, x1)
+
+inst_88:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x3, 552, x1)
+
+inst_89:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x3, 560, x1)
+
+inst_90:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x3, 568, x1)
+
+inst_91:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x3, 576, x1)
+
+inst_92:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x3, 584, x1)
+
+inst_93:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x3, 592, x1)
+
+inst_94:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x3, 600, x1)
+
+inst_95:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x3, 608, x1)
+
+inst_96:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x3, 616, x1)
+
+inst_97:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x3, 624, x1)
+
+inst_98:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x3, 632, x1)
+
+inst_99:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x3, 640, x1)
+
+inst_100:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x3, 648, x1)
+
+inst_101:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x3, 656, x1)
+
+inst_102:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x3, 664, x1)
+
+inst_103:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x3, 672, x1)
+
+inst_104:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x3, 680, x1)
+
+inst_105:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x3, 688, x1)
+
+inst_106:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x3, 696, x1)
+
+inst_107:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x3, 704, x1)
+
+inst_108:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x3, 712, x1)
+
+inst_109:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x3, 720, x1)
+
+inst_110:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x3, 728, x1)
+
+inst_111:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x3, 736, x1)
+
+inst_112:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x3, 744, x1)
+
+inst_113:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x3, 752, x1)
+
+inst_114:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x3, 760, x1)
+
+inst_115:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x3, 768, x1)
+
+inst_116:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x3, 776, x1)
+
+inst_117:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x3, 784, x1)
+
+inst_118:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x3, 792, x1)
+
+inst_119:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x3, 800, x1)
+
+inst_120:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x3, 808, x1)
+
+inst_121:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x3, 816, x1)
+
+inst_122:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x3, 824, x1)
+
+inst_123:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x3, 832, x1)
+
+inst_124:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x3, 840, x1)
+
+inst_125:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x3, 848, x1)
+
+inst_126:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x3, 856, x1)
+
+inst_127:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x3, 864, x1)
+
+inst_128:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x3, 872, x1)
+
+inst_129:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x3, 880, x1)
+
+inst_130:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x3, 888, x1)
+
+inst_131:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x3, 896, x1)
+
+inst_132:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x3, 904, x1)
+
+inst_133:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x3, 912, x1)
+
+inst_134:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x3, 920, x1)
+
+inst_135:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x3, 928, x1)
+
+inst_136:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x3, 936, x1)
+
+inst_137:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x3, 944, x1)
+
+inst_138:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x3, 952, x1)
+
+inst_139:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x3, 960, x1)
+
+inst_140:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x3, 968, x1)
+
+inst_141:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x3, 976, x1)
+
+inst_142:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x3, 984, x1)
+
+inst_143:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x3, 992, x1)
+
+inst_144:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x3, 1000, x1)
+
+inst_145:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x3, 1008, x1)
+
+inst_146:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x3, 1016, x1)
+
+inst_147:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x3, 1024, x1)
+
+inst_148:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x3, 1032, x1)
+
+inst_149:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x3, 1040, x1)
+
+inst_150:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x3, 1048, x1)
+
+inst_151:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x3, 1056, x1)
+
+inst_152:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x3, 1064, x1)
+
+inst_153:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x3, 1072, x1)
+
+inst_154:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x3, 1080, x1)
+
+inst_155:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x3, 1088, x1)
+
+inst_156:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x3, 1096, x1)
+
+inst_157:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x3, 1104, x1)
+
+inst_158:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x3, 1112, x1)
+
+inst_159:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x3, 1120, x1)
+
+inst_160:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x3, 1128, x1)
+
+inst_161:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x3, 1136, x1)
+
+inst_162:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x3, 1144, x1)
+
+inst_163:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x3, 1152, x1)
+
+inst_164:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x3, 1160, x1)
+
+inst_165:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x3, 1168, x1)
+
+inst_166:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x3, 1176, x1)
+
+inst_167:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x3, 1184, x1)
+
+inst_168:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x3, 1192, x1)
+
+inst_169:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x3, 1200, x1)
+
+inst_170:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x3, 1208, x1)
+
+inst_171:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x3, 1216, x1)
+
+inst_172:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x3, 1224, x1)
+
+inst_173:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x3, 1232, x1)
+
+inst_174:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x3, 1240, x1)
+
+inst_175:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x3, 1248, x1)
+
+inst_176:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x3, 1256, x1)
+
+inst_177:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x3, 1264, x1)
+
+inst_178:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x3, 1272, x1)
+
+inst_179:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x3, 1280, x1)
+
+inst_180:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x3, 1288, x1)
+
+inst_181:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x3, 1296, x1)
+
+inst_182:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x3, 1304, x1)
+
+inst_183:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x3, 1312, x1)
+
+inst_184:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x3, 1320, x1)
+
+inst_185:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x3, 1328, x1)
+
+inst_186:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x3, 1336, x1)
+
+inst_187:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x3, 1344, x1)
+
+inst_188:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x3, 1352, x1)
+
+inst_189:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x3, 1360, x1)
+
+inst_190:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x3, 1368, x1)
+
+inst_191:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x3, 1376, x1)
+
+inst_192:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x3, 1384, x1)
+
+inst_193:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x3, 1392, x1)
+
+inst_194:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x3, 1400, x1)
+
+inst_195:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x3, 1408, x1)
+
+inst_196:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x3, 1416, x1)
+
+inst_197:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x3, 1424, x1)
+
+inst_198:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x3, 1432, x1)
+
+inst_199:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x3, 1440, x1)
+
+inst_200:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x3, 1448, x1)
+
+inst_201:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x3, 1456, x1)
+
+inst_202:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x3, 1464, x1)
+
+inst_203:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x3, 1472, x1)
+
+inst_204:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x3, 1480, x1)
+
+inst_205:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x3, 1488, x1)
+
+inst_206:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x3, 1496, x1)
+
+inst_207:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x3, 1504, x1)
+
+inst_208:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x3, 1512, x1)
+
+inst_209:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x3, 1520, x1)
+
+inst_210:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x3, 1528, x1)
+
+inst_211:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x3, 1536, x1)
+
+inst_212:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x3, 1544, x1)
+
+inst_213:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x3, 1552, x1)
+
+inst_214:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x3, 1560, x1)
+
+inst_215:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x3, 1568, x1)
+
+inst_216:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x3, 1576, x1)
+
+inst_217:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x3, 1584, x1)
+
+inst_218:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x3, 1592, x1)
+
+inst_219:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x3, 1600, x1)
+
+inst_220:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x3, 1608, x1)
+
+inst_221:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x3, 1616, x1)
+
+inst_222:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x3, 1624, x1)
+
+inst_223:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x3, 1632, x1)
+
+inst_224:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x3, 1640, x1)
+
+inst_225:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x3, 1648, x1)
+
+inst_226:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x3, 1656, x1)
+
+inst_227:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x3, 1664, x1)
+
+inst_228:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x3, 1672, x1)
+
+inst_229:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x3, 1680, x1)
+
+inst_230:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x3, 1688, x1)
+
+inst_231:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x3, 1696, x1)
+
+inst_232:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x3, 1704, x1)
+
+inst_233:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x3, 1712, x1)
+
+inst_234:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x3, 1720, x1)
+
+inst_235:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x3, 1728, x1)
+
+inst_236:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x3, 1736, x1)
+
+inst_237:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x3, 1744, x1)
+
+inst_238:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x3, 1752, x1)
+
+inst_239:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x3, 1760, x1)
+
+inst_240:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x3, 1768, x1)
+
+inst_241:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x3, 1776, x1)
+
+inst_242:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x3, 1784, x1)
+
+inst_243:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x3, 1792, x1)
+
+inst_244:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x3, 1800, x1)
+
+inst_245:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x3, 1808, x1)
+
+inst_246:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x3, 1816, x1)
+
+inst_247:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x3, 1824, x1)
+
+inst_248:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x3, 1832, x1)
+
+inst_249:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x3, 1840, x1)
+
+inst_250:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x3, 1848, x1)
+
+inst_251:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x3, 1856, x1)
+
+inst_252:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x3, 1864, x1)
+
+inst_253:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x3, 1872, x1)
+
+inst_254:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x3, 1880, x1)
+
+inst_255:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x3, 1888, x1)
+
+inst_256:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x3, 1896, x1)
+
+inst_257:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x3, 1904, x1)
+
+inst_258:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x3, 1912, x1)
+
+inst_259:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x3, 1920, x1)
+
+inst_260:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x3, 1928, x1)
+
+inst_261:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x3, 1936, x1)
+
+inst_262:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x3, 1944, x1)
+
+inst_263:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x3, 1952, x1)
+
+inst_264:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x3, 1960, x1)
+
+inst_265:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x3, 1968, x1)
+
+inst_266:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x3, 1976, x1)
+
+inst_267:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x3, 1984, x1)
+
+inst_268:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x3, 1992, x1)
+
+inst_269:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x3, 2000, x1)
+
+inst_270:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x3, 2008, x1)
+
+inst_271:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x3, 2016, x1)
+
+inst_272:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x3, 2024, x1)
+
+inst_273:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 3 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x3
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x3, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x3, 2032, x1)
+
+inst_274:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x3, 2040, x1)
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_275:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x3, 0, x1)
+
+inst_276:
+// rs1_val == 0x156fe482f9fcd292 and rs2_val == 0x24c6435c8dca0621 and imm_val == 0x0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x156fe482f9fcd292; op2val:0x24c6435c8dca0621; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x156fe482f9fcd292, 0x24c6435c8dca0621, x3, 8, x1)
+
+inst_277:
+// rs1_val == 0xa757e91e027e5943 and rs2_val == 0xda73ec2605e6750f and imm_val == 0x2 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xa757e91e027e5943; op2val:0xda73ec2605e6750f; immval:0x2
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x2, 0x0000000000000000, 0xa757e91e027e5943, 0xda73ec2605e6750f, x3, 16, x1)
+
+inst_278:
+// rs1_val == 0x91766f62ba2be4d3 and rs2_val == 0x74a813d25570084b and imm_val == 0x0 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x91766f62ba2be4d3; op2val:0x74a813d25570084b; immval:0x0
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x0, 0x0000000000000000, 0x91766f62ba2be4d3, 0x74a813d25570084b, x3, 24, x1)
+
+inst_279:
+// rs1_val == 0x3150e5fa299c3bcf and rs2_val == 0xe6fff3d9ec1ce9d2 and imm_val == 0x1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0x3150e5fa299c3bcf; op2val:0xe6fff3d9ec1ce9d2; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0x3150e5fa299c3bcf, 0xe6fff3d9ec1ce9d2, x3, 32, x1)
+
+inst_280:
+// rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 1 
+// opcode: sm4ed; rd: x12; op1:x10; op2:x11; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x1
+TEST_RI_OP(sm4ed, x12, x10, x11, 0x1, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x3, 40, x1)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x21_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x21_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x3_1:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S
new file mode 100644
index 000000000..ccd7d481e
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ed-rwp1.S
@@ -0,0 +1,415 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm4ed)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm4ed)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x1; op1:x2; op1:x3; op1:x4; dest:x5;
+li  x1, 0x08577eb1924770d3;
+li  x2, 0x93fdcab87b89296c;
+li  x3, 0xd2d6b8777dc59a3a;
+li  x4, 0xcf84b683a749f9c5;
+li  x5, 0x854a965708ceac39;
+sm4ed x5, x5, x1, 0;
+sm4ed x5, x5, x2, 1;
+sm4ed x5, x5, x3, 2;
+sm4ed x5, x5, x4, 3;
+RVTEST_SIGUPD(x31,x5,0);
+
+inst_1:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x2; op1:x3; op1:x4; op1:x5; dest:x6;
+li  x2, 0x137a977753e8eb43;
+li  x3, 0x5c74e45eff1e5bef;
+li  x4, 0xdc3383836b9f15c4;
+li  x5, 0x5ae6a2289a6ab329;
+li  x6, 0x432779eeacca7f0d;
+sm4ed x6, x6, x2, 0;
+sm4ed x6, x6, x3, 1;
+sm4ed x6, x6, x4, 2;
+sm4ed x6, x6, x5, 3;
+RVTEST_SIGUPD(x31,x6,8);
+
+inst_2:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x3; op1:x4; op1:x5; op1:x6; dest:x7;
+li  x3, 0xaf949e5e2cb7362c;
+li  x4, 0x5cd2875ea96ec2b3;
+li  x5, 0x9d02fc90708cc1b6;
+li  x6, 0x953b00b00b54aa22;
+li  x7, 0x224c06013c53d0e3;
+sm4ed x7, x7, x3, 0;
+sm4ed x7, x7, x4, 1;
+sm4ed x7, x7, x5, 2;
+sm4ed x7, x7, x6, 3;
+RVTEST_SIGUPD(x31,x7,16);
+
+inst_3:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x4; op1:x5; op1:x6; op1:x7; dest:x8;
+li  x4, 0xe8dac663f0e58650;
+li  x5, 0x3d7c95f9e5f0307e;
+li  x6, 0x8c8a18b2aaac3142;
+li  x7, 0x785036de6f9fb997;
+li  x8, 0x95a4d257a7298c66;
+sm4ed x8, x8, x4, 0;
+sm4ed x8, x8, x5, 1;
+sm4ed x8, x8, x6, 2;
+sm4ed x8, x8, x7, 3;
+RVTEST_SIGUPD(x31,x8,24);
+
+inst_4:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x5; op1:x6; op1:x7; op1:x8; dest:x9;
+li  x5, 0x807da245d814d575;
+li  x6, 0x3d06143769b1dcbf;
+li  x7, 0x7f21682208208d09;
+li  x8, 0x14b91c79dae98554;
+li  x9, 0xc5ec6148c6880007;
+sm4ed x9, x9, x5, 0;
+sm4ed x9, x9, x6, 1;
+sm4ed x9, x9, x7, 2;
+sm4ed x9, x9, x8, 3;
+RVTEST_SIGUPD(x31,x9,32);
+
+inst_5:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x6; op1:x7; op1:x8; op1:x9; dest:x10;
+li  x6, 0x7213516d6a013380;
+li  x7, 0x4652f62dae4839a1;
+li  x8, 0x85986adb9e044706;
+li  x9, 0x1e9667c2dd68f201;
+li  x10, 0x4d753ac174ab0a38;
+sm4ed x10, x10, x6, 0;
+sm4ed x10, x10, x7, 1;
+sm4ed x10, x10, x8, 2;
+sm4ed x10, x10, x9, 3;
+RVTEST_SIGUPD(x31,x10,40);
+
+inst_6:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x7; op1:x8; op1:x9; op1:x10; dest:x11;
+li  x7, 0x53fbff6c58fa6e1c;
+li  x8, 0x0b2e2669b66b3284;
+li  x9, 0x51c5b8b2e59cf78f;
+li  x10, 0x43032e3e1475f78d;
+li  x11, 0x9535971c67a07b54;
+sm4ed x11, x11, x7, 0;
+sm4ed x11, x11, x8, 1;
+sm4ed x11, x11, x9, 2;
+sm4ed x11, x11, x10, 3;
+RVTEST_SIGUPD(x31,x11,48);
+
+inst_7:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x8; op1:x9; op1:x10; op1:x11; dest:x12;
+li  x8, 0xe918be9ffe057dc5;
+li  x9, 0x1011eeb47ff822ed;
+li  x10, 0xac9e90327d486895;
+li  x11, 0x66b072b9e5e290be;
+li  x12, 0x89e6156b59672bd6;
+sm4ed x12, x12, x8, 0;
+sm4ed x12, x12, x9, 1;
+sm4ed x12, x12, x10, 2;
+sm4ed x12, x12, x11, 3;
+RVTEST_SIGUPD(x31,x12,56);
+
+inst_8:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x9; op1:x10; op1:x11; op1:x12; dest:x13;
+li  x9, 0xb3a63fa37d69ceef;
+li  x10, 0x70fc1afc8f0846a2;
+li  x11, 0xf956ec0bf7fb4b49;
+li  x12, 0x0cf25923109ff475;
+li  x13, 0x26ea42ec17be082f;
+sm4ed x13, x13, x9, 0;
+sm4ed x13, x13, x10, 1;
+sm4ed x13, x13, x11, 2;
+sm4ed x13, x13, x12, 3;
+RVTEST_SIGUPD(x31,x13,64);
+
+inst_9:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x10; op1:x11; op1:x12; op1:x13; dest:x14;
+li  x10, 0xccadb61ffe20ce1c;
+li  x11, 0x72745307ec325eec;
+li  x12, 0xb2a7a18ac9ea3210;
+li  x13, 0xbd59213e27541f0b;
+li  x14, 0x9e7e1fc352b42eff;
+sm4ed x14, x14, x10, 0;
+sm4ed x14, x14, x11, 1;
+sm4ed x14, x14, x12, 2;
+sm4ed x14, x14, x13, 3;
+RVTEST_SIGUPD(x31,x14,72);
+
+inst_10:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x11; op1:x12; op1:x13; op1:x14; dest:x15;
+li  x11, 0xa0e0bd86d4551408;
+li  x12, 0xcebe24d906600792;
+li  x13, 0x4bd90a77f65cf3f3;
+li  x14, 0xdbdd4dd9d9e93409;
+li  x15, 0xf65e7737fbd2570d;
+sm4ed x15, x15, x11, 0;
+sm4ed x15, x15, x12, 1;
+sm4ed x15, x15, x13, 2;
+sm4ed x15, x15, x14, 3;
+RVTEST_SIGUPD(x31,x15,80);
+
+inst_11:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x12; op1:x13; op1:x14; op1:x15; dest:x16;
+li  x12, 0xd1142724fb37bec8;
+li  x13, 0xab8534c129a2575f;
+li  x14, 0xfc6113a3312529dc;
+li  x15, 0x6d3f408b31d4ff08;
+li  x16, 0x8e368ce0be5265f3;
+sm4ed x16, x16, x12, 0;
+sm4ed x16, x16, x13, 1;
+sm4ed x16, x16, x14, 2;
+sm4ed x16, x16, x15, 3;
+RVTEST_SIGUPD(x31,x16,88);
+
+inst_12:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x13; op1:x14; op1:x15; op1:x16; dest:x17;
+li  x13, 0x98f7c41c44115b04;
+li  x14, 0x01fbbe93a08b84f3;
+li  x15, 0x9c1a15286c834752;
+li  x16, 0xa6faba7bcfe6bc54;
+li  x17, 0xc5b3e01b11f6d600;
+sm4ed x17, x17, x13, 0;
+sm4ed x17, x17, x14, 1;
+sm4ed x17, x17, x15, 2;
+sm4ed x17, x17, x16, 3;
+RVTEST_SIGUPD(x31,x17,96);
+
+inst_13:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x14; op1:x15; op1:x16; op1:x17; dest:x18;
+li  x14, 0x5916d2810e24d9cc;
+li  x15, 0x74f5add55c37849a;
+li  x16, 0x4850e927bfdbb3be;
+li  x17, 0x67913217437cbc41;
+li  x18, 0x576e3d4fa3b633ab;
+sm4ed x18, x18, x14, 0;
+sm4ed x18, x18, x15, 1;
+sm4ed x18, x18, x16, 2;
+sm4ed x18, x18, x17, 3;
+RVTEST_SIGUPD(x31,x18,104);
+
+inst_14:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x15; op1:x16; op1:x17; op1:x18; dest:x19;
+li  x15, 0x46ed745fb9fef1d6;
+li  x16, 0x9651ee657a1d33ca;
+li  x17, 0xfe0a9c6c9a592829;
+li  x18, 0x9071f3aab87ce2a5;
+li  x19, 0x4e6168c8d6220b4f;
+sm4ed x19, x19, x15, 0;
+sm4ed x19, x19, x16, 1;
+sm4ed x19, x19, x17, 2;
+sm4ed x19, x19, x18, 3;
+RVTEST_SIGUPD(x31,x19,112);
+
+inst_15:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x16; op1:x17; op1:x18; op1:x19; dest:x20;
+li  x16, 0x9c3d087c65835bdf;
+li  x17, 0x9b11d383484641f5;
+li  x18, 0x2b24ced43da82c98;
+li  x19, 0xef8c60c0d12f8d4e;
+li  x20, 0xf37e27a312ea67e4;
+sm4ed x20, x20, x16, 0;
+sm4ed x20, x20, x17, 1;
+sm4ed x20, x20, x18, 2;
+sm4ed x20, x20, x19, 3;
+RVTEST_SIGUPD(x31,x20,120);
+
+inst_16:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x17; op1:x18; op1:x19; op1:x20; dest:x21;
+li  x17, 0x041bbaab97eb7c0f;
+li  x18, 0x93017690e356529c;
+li  x19, 0xd5e9d561f46a41bd;
+li  x20, 0x9408ad7db13971c0;
+li  x21, 0x90af95fe095b6425;
+sm4ed x21, x21, x17, 0;
+sm4ed x21, x21, x18, 1;
+sm4ed x21, x21, x19, 2;
+sm4ed x21, x21, x20, 3;
+RVTEST_SIGUPD(x31,x21,128);
+
+inst_17:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x18; op1:x19; op1:x20; op1:x21; dest:x22;
+li  x18, 0xef677106dc17ae6e;
+li  x19, 0xc5d09b942be2d8c9;
+li  x20, 0x596f5f89ce334459;
+li  x21, 0x5902a9dbe1832ab6;
+li  x22, 0xb4dc7dee71dabeac;
+sm4ed x22, x22, x18, 0;
+sm4ed x22, x22, x19, 1;
+sm4ed x22, x22, x20, 2;
+sm4ed x22, x22, x21, 3;
+RVTEST_SIGUPD(x31,x22,136);
+
+inst_18:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x19; op1:x20; op1:x21; op1:x22; dest:x23;
+li  x19, 0x755961a98347ddf5;
+li  x20, 0x18d71be431c00570;
+li  x21, 0x270e1922a422af66;
+li  x22, 0xdc336338eea4dd03;
+li  x23, 0xa2460e15a3da90b2;
+sm4ed x23, x23, x19, 0;
+sm4ed x23, x23, x20, 1;
+sm4ed x23, x23, x21, 2;
+sm4ed x23, x23, x22, 3;
+RVTEST_SIGUPD(x31,x23,144);
+
+inst_19:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x20; op1:x21; op1:x22; op1:x23; dest:x24;
+li  x20, 0x8f2248c25c3577f5;
+li  x21, 0x2a5dc0a00d453cdf;
+li  x22, 0xf3281b8ef4d325c3;
+li  x23, 0x947ac00e0caec993;
+li  x24, 0xd60235f35c4739b7;
+sm4ed x24, x24, x20, 0;
+sm4ed x24, x24, x21, 1;
+sm4ed x24, x24, x22, 2;
+sm4ed x24, x24, x23, 3;
+RVTEST_SIGUPD(x31,x24,152);
+
+inst_20:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x21; op1:x22; op1:x23; op1:x24; dest:x25;
+li  x21, 0x6dc3cceec36ffd4b;
+li  x22, 0xc2713ce25868105b;
+li  x23, 0x29ade05f7dddcc72;
+li  x24, 0x6baeea37b4c8839b;
+li  x25, 0x1e4e0fadd02bad0f;
+sm4ed x25, x25, x21, 0;
+sm4ed x25, x25, x22, 1;
+sm4ed x25, x25, x23, 2;
+sm4ed x25, x25, x24, 3;
+RVTEST_SIGUPD(x31,x25,160);
+
+inst_21:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x22; op1:x23; op1:x24; op1:x25; dest:x26;
+li  x22, 0xe4367ccad9716f2c;
+li  x23, 0x9ea76f0885958881;
+li  x24, 0xb183406662ebf954;
+li  x25, 0x796c1d88c313bc1f;
+li  x26, 0xe7e94a5193b3cb9a;
+sm4ed x26, x26, x22, 0;
+sm4ed x26, x26, x23, 1;
+sm4ed x26, x26, x24, 2;
+sm4ed x26, x26, x25, 3;
+RVTEST_SIGUPD(x31,x26,168);
+
+inst_22:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x23; op1:x24; op1:x25; op1:x26; dest:x27;
+li  x23, 0x37c4c6b99530db93;
+li  x24, 0x132a717606aec150;
+li  x25, 0x08011d17cfac3216;
+li  x26, 0xd65358aaa734906b;
+li  x27, 0xba1c4b6b2d9da6d7;
+sm4ed x27, x27, x23, 0;
+sm4ed x27, x27, x24, 1;
+sm4ed x27, x27, x25, 2;
+sm4ed x27, x27, x26, 3;
+RVTEST_SIGUPD(x31,x27,176);
+
+inst_23:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x24; op1:x25; op1:x26; op1:x27; dest:x28;
+li  x24, 0x04d3e5f42bccd6b6;
+li  x25, 0x339863c4d216eea8;
+li  x26, 0x3f13091de7fcc18b;
+li  x27, 0xc2cc1d388d15d800;
+li  x28, 0x0165f0f02016dc16;
+sm4ed x28, x28, x24, 0;
+sm4ed x28, x28, x25, 1;
+sm4ed x28, x28, x26, 2;
+sm4ed x28, x28, x27, 3;
+RVTEST_SIGUPD(x31,x28,184);
+
+inst_24:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x25; op1:x26; op1:x27; op1:x28; dest:x29;
+li  x25, 0xd6ac851f07155a89;
+li  x26, 0x2d885062faa97965;
+li  x27, 0x62a12347b17286fd;
+li  x28, 0xa97cbf8403beaecd;
+li  x29, 0xa9632e3dbd0070ae;
+sm4ed x29, x29, x25, 0;
+sm4ed x29, x29, x26, 1;
+sm4ed x29, x29, x27, 2;
+sm4ed x29, x29, x28, 3;
+RVTEST_SIGUPD(x31,x29,192);
+
+inst_25:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ed; op1:x26; op1:x27; op1:x28; op1:x29; dest:x30;
+li  x26, 0x8d3ba7550c3c31a8;
+li  x27, 0xb3e73cbb0d8258c4;
+li  x28, 0x7587e11994038f33;
+li  x29, 0x2f8d133555f7f60a;
+li  x30, 0xa0a1c6ef661a191b;
+sm4ed x30, x30, x26, 0;
+sm4ed x30, x30, x27, 1;
+sm4ed x30, x30, x28, 2;
+sm4ed x30, x30, x29, 3;
+RVTEST_SIGUPD(x31,x30,200);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 26*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S
new file mode 100644
index 000000000..b6a43b991
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-01.S
@@ -0,0 +1,1489 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.5.1
+// timestamp : Thu Aug 12 11:00:04 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sm4ks instruction of the RISC-V _Zks extension for the sm4ks covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I_Zks")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sm4ks)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",sm4ks)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKsed.*);def TEST_CASE_1=True;",sm4ks)
+
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x8, rs2==x30, rd==x29, rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 0 
+// opcode: sm4ks; rd: x29; op1:x8; op2:x30; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x0
+TEST_RI_OP(sm4ks, x29, x8, x30, 0x0, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x2, 0, x6)
+
+inst_1:
+// rs2 == rd != rs1, rs1==x28, rs2==x7, rd==x7, rs1_val == 0xbc36b151aeb006fc and rs2_val == 0x2cab43d86576923c and imm_val == 0x3 
+// opcode: sm4ks; rd: x7; op1:x28; op2:x7; op1val:0xbc36b151aeb006fc; op2val:0x2cab43d86576923c; immval:0x3
+TEST_RI_OP(sm4ks, x7, x28, x7, 0x3, 0x0000000000000000, 0xbc36b151aeb006fc, 0x2cab43d86576923c, x2, 8, x6)
+
+inst_2:
+// rs1 == rs2 != rd, rs1==x23, rs2==x23, rd==x24, rs1_val == 0x156fe482f9fcd292 and rs2_val == 0x24c6435c8dca0621 and imm_val == 0x0 
+// opcode: sm4ks; rd: x24; op1:x23; op2:x23; op1val:0x156fe482f9fcd292; op2val:0x156fe482f9fcd292; immval:0x0
+TEST_RI_OP(sm4ks, x24, x23, x23, 0x0, 0x0000000000000000, 0x156fe482f9fcd292, 0x156fe482f9fcd292, x2, 16, x6)
+
+inst_3:
+// rs1 == rs2 == rd, rs1==x26, rs2==x26, rd==x26, rs1_val == 0xa757e91e027e5943 and rs2_val == 0xda73ec2605e6750f and imm_val == 0x2 
+// opcode: sm4ks; rd: x26; op1:x26; op2:x26; op1val:0xa757e91e027e5943; op2val:0xa757e91e027e5943; immval:0x2
+TEST_RI_OP(sm4ks, x26, x26, x26, 0x2, 0x0000000000000000, 0xa757e91e027e5943, 0xa757e91e027e5943, x2, 24, x6)
+
+inst_4:
+// rs1 == rd != rs2, rs1==x10, rs2==x27, rd==x10, rs1_val == 0xf452cbd863fa921d and rs2_val == 0x4b6587d88ef464d1 and imm_val == 0x3 
+// opcode: sm4ks; rd: x10; op1:x10; op2:x27; op1val:0xf452cbd863fa921d; op2val:0x4b6587d88ef464d1; immval:0x3
+TEST_RI_OP(sm4ks, x10, x10, x27, 0x3, 0x0000000000000000, 0xf452cbd863fa921d, 0x4b6587d88ef464d1, x2, 32, x6)
+
+inst_5:
+// rs1==x22, rs2==x5, rd==x23, rs1_val == 0xd40f46a4356c1dcc and rs2_val == 0x30c33d97184e0f23 and imm_val == 0x0 
+// opcode: sm4ks; rd: x23; op1:x22; op2:x5; op1val:0xd40f46a4356c1dcc; op2val:0x30c33d97184e0f23; immval:0x0
+TEST_RI_OP(sm4ks, x23, x22, x5, 0x0, 0x0000000000000000, 0xd40f46a4356c1dcc, 0x30c33d97184e0f23, x2, 40, x6)
+
+inst_6:
+// rs1==x27, rs2==x14, rd==x16, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 and imm_val == 0x2 
+// opcode: sm4ks; rd: x16; op1:x27; op2:x14; op1val:0x6d23c0488a6019c1; op2val:0x860bdaad7447a088; immval:0x2
+TEST_RI_OP(sm4ks, x16, x27, x14, 0x2, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x2, 48, x6)
+
+inst_7:
+// rs1==x7, rs2==x21, rd==x13, rs1_val == 0x17168ab3a4351379 and rs2_val == 0xbbb4f560f222070c and imm_val == 0x0 
+// opcode: sm4ks; rd: x13; op1:x7; op2:x21; op1val:0x17168ab3a4351379; op2val:0xbbb4f560f222070c; immval:0x0
+TEST_RI_OP(sm4ks, x13, x7, x21, 0x0, 0x0000000000000000, 0x17168ab3a4351379, 0xbbb4f560f222070c, x2, 56, x6)
+
+inst_8:
+// rs1==x21, rs2==x24, rd==x25, rs1_val == 0x3fb0fe60ef1d54db and rs2_val == 0x09ff42451826a804 and imm_val == 0x1 
+// opcode: sm4ks; rd: x25; op1:x21; op2:x24; op1val:0x3fb0fe60ef1d54db; op2val:0x9ff42451826a804; immval:0x1
+TEST_RI_OP(sm4ks, x25, x21, x24, 0x1, 0x0000000000000000, 0x3fb0fe60ef1d54db, 0x9ff42451826a804, x2, 64, x6)
+
+inst_9:
+// rs1==x1, rs2==x11, rd==x21, rs1_val == 0xcc7b22010ca3ef52 and rs2_val == 0xc150f4d3df74d068 and imm_val == 0x1 
+// opcode: sm4ks; rd: x21; op1:x1; op2:x11; op1val:0xcc7b22010ca3ef52; op2val:0xc150f4d3df74d068; immval:0x1
+TEST_RI_OP(sm4ks, x21, x1, x11, 0x1, 0x0000000000000000, 0xcc7b22010ca3ef52, 0xc150f4d3df74d068, x2, 72, x6)
+
+inst_10:
+// rs1==x5, rs2==x4, rd==x27, rs1_val == 0x358a9235987daa20 and rs2_val == 0xb369e10209f393d7 and imm_val == 0x1 
+// opcode: sm4ks; rd: x27; op1:x5; op2:x4; op1val:0x358a9235987daa20; op2val:0xb369e10209f393d7; immval:0x1
+TEST_RI_OP(sm4ks, x27, x5, x4, 0x1, 0x0000000000000000, 0x358a9235987daa20, 0xb369e10209f393d7, x2, 80, x6)
+
+inst_11:
+// rs1==x9, rs2==x15, rd==x17, rs1_val == 0x91766f62ba2be4d3 and rs2_val == 0x74a813d25570084b and imm_val == 0x0 
+// opcode: sm4ks; rd: x17; op1:x9; op2:x15; op1val:0x91766f62ba2be4d3; op2val:0x74a813d25570084b; immval:0x0
+TEST_RI_OP(sm4ks, x17, x9, x15, 0x0, 0x0000000000000000, 0x91766f62ba2be4d3, 0x74a813d25570084b, x2, 88, x6)
+
+inst_12:
+// rs1==x31, rs2==x1, rd==x20, rs1_val == 0xb7c1fc5f1efa1095 and rs2_val == 0xe2cbb9ab3819fe4d and imm_val == 0x1 
+// opcode: sm4ks; rd: x20; op1:x31; op2:x1; op1val:0xb7c1fc5f1efa1095; op2val:0xe2cbb9ab3819fe4d; immval:0x1
+TEST_RI_OP(sm4ks, x20, x31, x1, 0x1, 0x0000000000000000, 0xb7c1fc5f1efa1095, 0xe2cbb9ab3819fe4d, x2, 96, x6)
+
+inst_13:
+// rs1==x0, rs2==x19, rd==x5, rs1_val == 0xa6c9253a4cc6382e and rs2_val == 0x25ae27ee4113ee60 and imm_val == 0x2 
+// opcode: sm4ks; rd: x5; op1:x0; op2:x19; op1val:0x0; op2val:0x25ae27ee4113ee60; immval:0x2
+TEST_RI_OP(sm4ks, x5, x0, x19, 0x2, 0x0000000000000000, 0x0, 0x25ae27ee4113ee60, x2, 104, x6)
+
+inst_14:
+// rs1==x4, rs2==x22, rd==x8, rs1_val == 0xf17f6920daaafe5c and rs2_val == 0x7bcad7c4ff9a1b80 and imm_val == 0x0 
+// opcode: sm4ks; rd: x8; op1:x4; op2:x22; op1val:0xf17f6920daaafe5c; op2val:0x7bcad7c4ff9a1b80; immval:0x0
+TEST_RI_OP(sm4ks, x8, x4, x22, 0x0, 0x0000000000000000, 0xf17f6920daaafe5c, 0x7bcad7c4ff9a1b80, x2, 112, x6)
+
+inst_15:
+// rs1==x3, rs2==x25, rd==x30, rs1_val == 0x3150e5fa299c3bcf and rs2_val == 0xe6fff3d9ec1ce9d2 and imm_val == 0x1 
+// opcode: sm4ks; rd: x30; op1:x3; op2:x25; op1val:0x3150e5fa299c3bcf; op2val:0xe6fff3d9ec1ce9d2; immval:0x1
+TEST_RI_OP(sm4ks, x30, x3, x25, 0x1, 0x0000000000000000, 0x3150e5fa299c3bcf, 0xe6fff3d9ec1ce9d2, x2, 120, x6)
+
+inst_16:
+// rs1==x17, rs2==x18, rd==x4, rs1_val == 0x1fc493caa371db42 and rs2_val == 0x9a4e9ef10171f4df and imm_val == 0x1 
+// opcode: sm4ks; rd: x4; op1:x17; op2:x18; op1val:0x1fc493caa371db42; op2val:0x9a4e9ef10171f4df; immval:0x1
+TEST_RI_OP(sm4ks, x4, x17, x18, 0x1, 0x0000000000000000, 0x1fc493caa371db42, 0x9a4e9ef10171f4df, x2, 128, x5)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_17:
+// rs1==x30, rs2==x2, rd==x6, rs1_val == 0xf5faf2073430cb17 and rs2_val == 0x8e2eac2a760b3c5e and imm_val == 0x3 
+// opcode: sm4ks; rd: x6; op1:x30; op2:x2; op1val:0xf5faf2073430cb17; op2val:0x8e2eac2a760b3c5e; immval:0x3
+TEST_RI_OP(sm4ks, x6, x30, x2, 0x3, 0x0000000000000000, 0xf5faf2073430cb17, 0x8e2eac2a760b3c5e, x4, 0, x5)
+
+inst_18:
+// rs1==x11, rs2==x9, rd==x15, rs1_val == 0xbc991c531484f407 and rs2_val == 0x55d98c6e3459294e and imm_val == 0x2 
+// opcode: sm4ks; rd: x15; op1:x11; op2:x9; op1val:0xbc991c531484f407; op2val:0x55d98c6e3459294e; immval:0x2
+TEST_RI_OP(sm4ks, x15, x11, x9, 0x2, 0x0000000000000000, 0xbc991c531484f407, 0x55d98c6e3459294e, x4, 8, x5)
+
+inst_19:
+// rs1==x25, rs2==x6, rd==x0, rs1_val == 0x59885afcbb61a9cd and rs2_val == 0xccce240c81c1e7ff and imm_val == 0x0 
+// opcode: sm4ks; rd: x0; op1:x25; op2:x6; op1val:0x59885afcbb61a9cd; op2val:0xccce240c81c1e7ff; immval:0x0
+TEST_RI_OP(sm4ks, x0, x25, x6, 0x0, 0x0000000000000000, 0x59885afcbb61a9cd, 0xccce240c81c1e7ff, x4, 16, x5)
+
+inst_20:
+// rs1==x15, rs2==x8, rd==x12, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 and imm_val == 0x3 
+// opcode: sm4ks; rd: x12; op1:x15; op2:x8; op1val:0x75a3adb3254a9493; op2val:0xc5521660f3a3c571; immval:0x3
+TEST_RI_OP(sm4ks, x12, x15, x8, 0x3, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x4, 24, x5)
+
+inst_21:
+// rs1==x13, rs2==x20, rd==x22, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 3 
+// opcode: sm4ks; rd: x22; op1:x13; op2:x20; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x3
+TEST_RI_OP(sm4ks, x22, x13, x20, 0x3, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x4, 32, x5)
+
+inst_22:
+// rs1==x14, rs2==x3, rd==x18, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 2 
+// opcode: sm4ks; rd: x18; op1:x14; op2:x3; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x2
+TEST_RI_OP(sm4ks, x18, x14, x3, 0x2, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x4, 40, x5)
+
+inst_23:
+// rs1==x6, rs2==x0, rd==x14, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 1 
+// opcode: sm4ks; rd: x14; op1:x6; op2:x0; op1val:0x3020100fffefdfc; op2val:0x0; immval:0x1
+TEST_RI_OP(sm4ks, x14, x6, x0, 0x1, 0x0000000000000000, 0x3020100fffefdfc, 0x0, x4, 48, x5)
+
+inst_24:
+// rs1==x29, rs2==x13, rd==x1, rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 0 
+// opcode: sm4ks; rd: x1; op1:x29; op2:x13; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x0
+TEST_RI_OP(sm4ks, x1, x29, x13, 0x0, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x4, 56, x5)
+
+inst_25:
+// rs1==x2, rs2==x17, rd==x3, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 3 
+// opcode: sm4ks; rd: x3; op1:x2; op2:x17; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x3
+TEST_RI_OP(sm4ks, x3, x2, x17, 0x3, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x4, 64, x5)
+
+inst_26:
+// rs1==x19, rs2==x16, rd==x2, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 2 
+// opcode: sm4ks; rd: x2; op1:x19; op2:x16; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x2
+TEST_RI_OP(sm4ks, x2, x19, x16, 0x2, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x4, 72, x5)
+
+inst_27:
+// rs1==x16, rs2==x28, rd==x31, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 1 
+// opcode: sm4ks; rd: x31; op1:x16; op2:x28; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x1
+TEST_RI_OP(sm4ks, x31, x16, x28, 0x1, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x4, 80, x5)
+
+inst_28:
+// rs1==x12, rs2==x29, rd==x9, rs1_val == 0xfffefdfcfbfaf9f8 and rs2_val == 0x03020100fffefdfc and imm_val == 0 
+// opcode: sm4ks; rd: x9; op1:x12; op2:x29; op1val:0xfffefdfcfbfaf9f8; op2val:0x3020100fffefdfc; immval:0x0
+TEST_RI_OP(sm4ks, x9, x12, x29, 0x0, 0x0000000000000000, 0xfffefdfcfbfaf9f8, 0x3020100fffefdfc, x4, 88, x5)
+
+inst_29:
+// rs1==x18, rs2==x12, rd==x28, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 3 
+// opcode: sm4ks; rd: x28; op1:x18; op2:x12; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x3
+TEST_RI_OP(sm4ks, x28, x18, x12, 0x3, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x4, 96, x5)
+
+inst_30:
+// rs1==x24, rs2==x10, rd==x19, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 2 
+// opcode: sm4ks; rd: x19; op1:x24; op2:x10; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x2
+TEST_RI_OP(sm4ks, x19, x24, x10, 0x2, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x4, 104, x5)
+
+inst_31:
+// rs1==x20, rs2==x31, rd==x11, rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 1 
+// opcode: sm4ks; rd: x11; op1:x20; op2:x31; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x1
+TEST_RI_OP(sm4ks, x11, x20, x31, 0x1, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x4, 112, x5)
+
+inst_32:
+// rs1_val == 0xfbfaf9f8f7f6f5f4 and rs2_val == 0xf7f6f5f4f3f2f1f0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xfbfaf9f8f7f6f5f4; op2val:0xf7f6f5f4f3f2f1f0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xfbfaf9f8f7f6f5f4, 0xf7f6f5f4f3f2f1f0, x4, 120, x5)
+
+inst_33:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x4, 128, x5)
+
+inst_34:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x4, 136, x5)
+
+inst_35:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x4, 144, x5)
+
+inst_36:
+// rs1_val == 0xf7f6f5f4f3f2f1f0 and rs2_val == 0xfbfaf9f8f7f6f5f4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf7f6f5f4f3f2f1f0; op2val:0xfbfaf9f8f7f6f5f4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xf7f6f5f4f3f2f1f0, 0xfbfaf9f8f7f6f5f4, x4, 152, x5)
+
+inst_37:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x4, 160, x5)
+
+inst_38:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x4, 168, x5)
+
+inst_39:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x4, 176, x5)
+
+inst_40:
+// rs1_val == 0xf3f2f1f0efeeedec and rs2_val == 0xefeeedecebeae9e8 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf3f2f1f0efeeedec; op2val:0xefeeedecebeae9e8; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xf3f2f1f0efeeedec, 0xefeeedecebeae9e8, x4, 184, x5)
+
+inst_41:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x4, 192, x5)
+
+inst_42:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x4, 200, x5)
+
+inst_43:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x4, 208, x5)
+
+inst_44:
+// rs1_val == 0xefeeedecebeae9e8 and rs2_val == 0xf3f2f1f0efeeedec and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xefeeedecebeae9e8; op2val:0xf3f2f1f0efeeedec; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xefeeedecebeae9e8, 0xf3f2f1f0efeeedec, x4, 216, x5)
+
+inst_45:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x4, 224, x5)
+
+inst_46:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x4, 232, x5)
+
+inst_47:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x4, 240, x5)
+
+inst_48:
+// rs1_val == 0xebeae9e8e7e6e5e4 and rs2_val == 0xe7e6e5e4e3e2e1e0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xebeae9e8e7e6e5e4; op2val:0xe7e6e5e4e3e2e1e0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xebeae9e8e7e6e5e4, 0xe7e6e5e4e3e2e1e0, x4, 248, x5)
+
+inst_49:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x4, 256, x5)
+
+inst_50:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x4, 264, x5)
+
+inst_51:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x4, 272, x5)
+
+inst_52:
+// rs1_val == 0xe7e6e5e4e3e2e1e0 and rs2_val == 0xebeae9e8e7e6e5e4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe7e6e5e4e3e2e1e0; op2val:0xebeae9e8e7e6e5e4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xe7e6e5e4e3e2e1e0, 0xebeae9e8e7e6e5e4, x4, 280, x5)
+
+inst_53:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x4, 288, x5)
+
+inst_54:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x4, 296, x5)
+
+inst_55:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x4, 304, x5)
+
+inst_56:
+// rs1_val == 0xe3e2e1e0dfdedddc and rs2_val == 0xdfdedddcdbdad9d8 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xe3e2e1e0dfdedddc; op2val:0xdfdedddcdbdad9d8; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xe3e2e1e0dfdedddc, 0xdfdedddcdbdad9d8, x4, 312, x5)
+
+inst_57:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x4, 320, x5)
+
+inst_58:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x4, 328, x5)
+
+inst_59:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x4, 336, x5)
+
+inst_60:
+// rs1_val == 0xdfdedddcdbdad9d8 and rs2_val == 0xe3e2e1e0dfdedddc and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdfdedddcdbdad9d8; op2val:0xe3e2e1e0dfdedddc; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xdfdedddcdbdad9d8, 0xe3e2e1e0dfdedddc, x4, 344, x5)
+
+inst_61:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x4, 352, x5)
+
+inst_62:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x4, 360, x5)
+
+inst_63:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x4, 368, x5)
+
+inst_64:
+// rs1_val == 0xdbdad9d8d7d6d5d4 and rs2_val == 0xd7d6d5d4d3d2d1d0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xdbdad9d8d7d6d5d4; op2val:0xd7d6d5d4d3d2d1d0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xdbdad9d8d7d6d5d4, 0xd7d6d5d4d3d2d1d0, x4, 376, x5)
+
+inst_65:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x4, 384, x5)
+
+inst_66:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x4, 392, x5)
+
+inst_67:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x4, 400, x5)
+
+inst_68:
+// rs1_val == 0xd7d6d5d4d3d2d1d0 and rs2_val == 0xdbdad9d8d7d6d5d4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd7d6d5d4d3d2d1d0; op2val:0xdbdad9d8d7d6d5d4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xd7d6d5d4d3d2d1d0, 0xdbdad9d8d7d6d5d4, x4, 408, x5)
+
+inst_69:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x4, 416, x5)
+
+inst_70:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x4, 424, x5)
+
+inst_71:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x4, 432, x5)
+
+inst_72:
+// rs1_val == 0xd3d2d1d0cfcecdcc and rs2_val == 0xcfcecdcccbcac9c8 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xd3d2d1d0cfcecdcc; op2val:0xcfcecdcccbcac9c8; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xd3d2d1d0cfcecdcc, 0xcfcecdcccbcac9c8, x4, 440, x5)
+
+inst_73:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x4, 448, x5)
+
+inst_74:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x4, 456, x5)
+
+inst_75:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x4, 464, x5)
+
+inst_76:
+// rs1_val == 0xcfcecdcccbcac9c8 and rs2_val == 0xd3d2d1d0cfcecdcc and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcfcecdcccbcac9c8; op2val:0xd3d2d1d0cfcecdcc; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xcfcecdcccbcac9c8, 0xd3d2d1d0cfcecdcc, x4, 472, x5)
+
+inst_77:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x4, 480, x5)
+
+inst_78:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x4, 488, x5)
+
+inst_79:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x4, 496, x5)
+
+inst_80:
+// rs1_val == 0xcbcac9c8c7c6c5c4 and rs2_val == 0xc7c6c5c4c3c2c1c0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xcbcac9c8c7c6c5c4; op2val:0xc7c6c5c4c3c2c1c0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xcbcac9c8c7c6c5c4, 0xc7c6c5c4c3c2c1c0, x4, 504, x5)
+
+inst_81:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x4, 512, x5)
+
+inst_82:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x4, 520, x5)
+
+inst_83:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x4, 528, x5)
+
+inst_84:
+// rs1_val == 0xc7c6c5c4c3c2c1c0 and rs2_val == 0xcbcac9c8c7c6c5c4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc7c6c5c4c3c2c1c0; op2val:0xcbcac9c8c7c6c5c4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xc7c6c5c4c3c2c1c0, 0xcbcac9c8c7c6c5c4, x4, 536, x5)
+
+inst_85:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x4, 544, x5)
+
+inst_86:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x4, 552, x5)
+
+inst_87:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x4, 560, x5)
+
+inst_88:
+// rs1_val == 0xc3c2c1c0bfbebdbc and rs2_val == 0xbfbebdbcbbbab9b8 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xc3c2c1c0bfbebdbc; op2val:0xbfbebdbcbbbab9b8; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xc3c2c1c0bfbebdbc, 0xbfbebdbcbbbab9b8, x4, 568, x5)
+
+inst_89:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x4, 576, x5)
+
+inst_90:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x4, 584, x5)
+
+inst_91:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x4, 592, x5)
+
+inst_92:
+// rs1_val == 0xbfbebdbcbbbab9b8 and rs2_val == 0xc3c2c1c0bfbebdbc and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbfbebdbcbbbab9b8; op2val:0xc3c2c1c0bfbebdbc; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xbfbebdbcbbbab9b8, 0xc3c2c1c0bfbebdbc, x4, 600, x5)
+
+inst_93:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x4, 608, x5)
+
+inst_94:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x4, 616, x5)
+
+inst_95:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x4, 624, x5)
+
+inst_96:
+// rs1_val == 0xbbbab9b8b7b6b5b4 and rs2_val == 0xb7b6b5b4b3b2b1b0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xbbbab9b8b7b6b5b4; op2val:0xb7b6b5b4b3b2b1b0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xbbbab9b8b7b6b5b4, 0xb7b6b5b4b3b2b1b0, x4, 632, x5)
+
+inst_97:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x4, 640, x5)
+
+inst_98:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x4, 648, x5)
+
+inst_99:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x4, 656, x5)
+
+inst_100:
+// rs1_val == 0xb7b6b5b4b3b2b1b0 and rs2_val == 0xbbbab9b8b7b6b5b4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb7b6b5b4b3b2b1b0; op2val:0xbbbab9b8b7b6b5b4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xb7b6b5b4b3b2b1b0, 0xbbbab9b8b7b6b5b4, x4, 664, x5)
+
+inst_101:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x4, 672, x5)
+
+inst_102:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x4, 680, x5)
+
+inst_103:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x4, 688, x5)
+
+inst_104:
+// rs1_val == 0xb3b2b1b0afaeadac and rs2_val == 0xafaeadacabaaa9a8 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb3b2b1b0afaeadac; op2val:0xafaeadacabaaa9a8; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xb3b2b1b0afaeadac, 0xafaeadacabaaa9a8, x4, 696, x5)
+
+inst_105:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x4, 704, x5)
+
+inst_106:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x4, 712, x5)
+
+inst_107:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x4, 720, x5)
+
+inst_108:
+// rs1_val == 0xafaeadacabaaa9a8 and rs2_val == 0xb3b2b1b0afaeadac and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xafaeadacabaaa9a8; op2val:0xb3b2b1b0afaeadac; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xafaeadacabaaa9a8, 0xb3b2b1b0afaeadac, x4, 728, x5)
+
+inst_109:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x4, 736, x5)
+
+inst_110:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x4, 744, x5)
+
+inst_111:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x4, 752, x5)
+
+inst_112:
+// rs1_val == 0xabaaa9a8a7a6a5a4 and rs2_val == 0xa7a6a5a4a3a2a1a0 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xabaaa9a8a7a6a5a4; op2val:0xa7a6a5a4a3a2a1a0; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xabaaa9a8a7a6a5a4, 0xa7a6a5a4a3a2a1a0, x4, 760, x5)
+
+inst_113:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x4, 768, x5)
+
+inst_114:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x4, 776, x5)
+
+inst_115:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x4, 784, x5)
+
+inst_116:
+// rs1_val == 0xa7a6a5a4a3a2a1a0 and rs2_val == 0xabaaa9a8a7a6a5a4 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa7a6a5a4a3a2a1a0; op2val:0xabaaa9a8a7a6a5a4; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xa7a6a5a4a3a2a1a0, 0xabaaa9a8a7a6a5a4, x4, 792, x5)
+
+inst_117:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x4, 800, x5)
+
+inst_118:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x4, 808, x5)
+
+inst_119:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x4, 816, x5)
+
+inst_120:
+// rs1_val == 0xa3a2a1a09f9e9d9c and rs2_val == 0x9f9e9d9c9b9a9998 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa3a2a1a09f9e9d9c; op2val:0x9f9e9d9c9b9a9998; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xa3a2a1a09f9e9d9c, 0x9f9e9d9c9b9a9998, x4, 824, x5)
+
+inst_121:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x4, 832, x5)
+
+inst_122:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x4, 840, x5)
+
+inst_123:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x4, 848, x5)
+
+inst_124:
+// rs1_val == 0x9f9e9d9c9b9a9998 and rs2_val == 0xa3a2a1a09f9e9d9c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9f9e9d9c9b9a9998; op2val:0xa3a2a1a09f9e9d9c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x9f9e9d9c9b9a9998, 0xa3a2a1a09f9e9d9c, x4, 856, x5)
+
+inst_125:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x4, 864, x5)
+
+inst_126:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x4, 872, x5)
+
+inst_127:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x4, 880, x5)
+
+inst_128:
+// rs1_val == 0x9b9a999897969594 and rs2_val == 0x9796959493929190 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9b9a999897969594; op2val:0x9796959493929190; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x9b9a999897969594, 0x9796959493929190, x4, 888, x5)
+
+inst_129:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x4, 896, x5)
+
+inst_130:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x4, 904, x5)
+
+inst_131:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x4, 912, x5)
+
+inst_132:
+// rs1_val == 0x9796959493929190 and rs2_val == 0x9b9a999897969594 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x9796959493929190; op2val:0x9b9a999897969594; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x9796959493929190, 0x9b9a999897969594, x4, 920, x5)
+
+inst_133:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x4, 928, x5)
+
+inst_134:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x4, 936, x5)
+
+inst_135:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x4, 944, x5)
+
+inst_136:
+// rs1_val == 0x939291908f8e8d8c and rs2_val == 0x8f8e8d8c8b8a8988 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x939291908f8e8d8c; op2val:0x8f8e8d8c8b8a8988; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x939291908f8e8d8c, 0x8f8e8d8c8b8a8988, x4, 952, x5)
+
+inst_137:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x4, 960, x5)
+
+inst_138:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x4, 968, x5)
+
+inst_139:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x4, 976, x5)
+
+inst_140:
+// rs1_val == 0x8f8e8d8c8b8a8988 and rs2_val == 0x939291908f8e8d8c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8f8e8d8c8b8a8988; op2val:0x939291908f8e8d8c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x8f8e8d8c8b8a8988, 0x939291908f8e8d8c, x4, 984, x5)
+
+inst_141:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x4, 992, x5)
+
+inst_142:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x4, 1000, x5)
+
+inst_143:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x4, 1008, x5)
+
+inst_144:
+// rs1_val == 0x8b8a898887868584 and rs2_val == 0x8786858483828180 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8b8a898887868584; op2val:0x8786858483828180; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x8b8a898887868584, 0x8786858483828180, x4, 1016, x5)
+
+inst_145:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x4, 1024, x5)
+
+inst_146:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x4, 1032, x5)
+
+inst_147:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x4, 1040, x5)
+
+inst_148:
+// rs1_val == 0x8786858483828180 and rs2_val == 0x8b8a898887868584 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x8786858483828180; op2val:0x8b8a898887868584; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x8786858483828180, 0x8b8a898887868584, x4, 1048, x5)
+
+inst_149:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x4, 1056, x5)
+
+inst_150:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x4, 1064, x5)
+
+inst_151:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x4, 1072, x5)
+
+inst_152:
+// rs1_val == 0x838281807f7e7d7c and rs2_val == 0x7f7e7d7c7b7a7978 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x838281807f7e7d7c; op2val:0x7f7e7d7c7b7a7978; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x838281807f7e7d7c, 0x7f7e7d7c7b7a7978, x4, 1080, x5)
+
+inst_153:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x4, 1088, x5)
+
+inst_154:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x4, 1096, x5)
+
+inst_155:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x4, 1104, x5)
+
+inst_156:
+// rs1_val == 0x7f7e7d7c7b7a7978 and rs2_val == 0x838281807f7e7d7c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7f7e7d7c7b7a7978; op2val:0x838281807f7e7d7c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x7f7e7d7c7b7a7978, 0x838281807f7e7d7c, x4, 1112, x5)
+
+inst_157:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x4, 1120, x5)
+
+inst_158:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x4, 1128, x5)
+
+inst_159:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x4, 1136, x5)
+
+inst_160:
+// rs1_val == 0x7b7a797877767574 and rs2_val == 0x7776757473727170 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7b7a797877767574; op2val:0x7776757473727170; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x7b7a797877767574, 0x7776757473727170, x4, 1144, x5)
+
+inst_161:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x4, 1152, x5)
+
+inst_162:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x4, 1160, x5)
+
+inst_163:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x4, 1168, x5)
+
+inst_164:
+// rs1_val == 0x7776757473727170 and rs2_val == 0x7b7a797877767574 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x7776757473727170; op2val:0x7b7a797877767574; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x7776757473727170, 0x7b7a797877767574, x4, 1176, x5)
+
+inst_165:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x4, 1184, x5)
+
+inst_166:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x4, 1192, x5)
+
+inst_167:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x4, 1200, x5)
+
+inst_168:
+// rs1_val == 0x737271706f6e6d6c and rs2_val == 0x6f6e6d6c6b6a6968 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x737271706f6e6d6c; op2val:0x6f6e6d6c6b6a6968; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x737271706f6e6d6c, 0x6f6e6d6c6b6a6968, x4, 1208, x5)
+
+inst_169:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x4, 1216, x5)
+
+inst_170:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x4, 1224, x5)
+
+inst_171:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x4, 1232, x5)
+
+inst_172:
+// rs1_val == 0x6f6e6d6c6b6a6968 and rs2_val == 0x737271706f6e6d6c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6f6e6d6c6b6a6968; op2val:0x737271706f6e6d6c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x6f6e6d6c6b6a6968, 0x737271706f6e6d6c, x4, 1240, x5)
+
+inst_173:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x4, 1248, x5)
+
+inst_174:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x4, 1256, x5)
+
+inst_175:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x4, 1264, x5)
+
+inst_176:
+// rs1_val == 0x6b6a696867666564 and rs2_val == 0x6766656463626160 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6b6a696867666564; op2val:0x6766656463626160; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x6b6a696867666564, 0x6766656463626160, x4, 1272, x5)
+
+inst_177:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x4, 1280, x5)
+
+inst_178:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x4, 1288, x5)
+
+inst_179:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x4, 1296, x5)
+
+inst_180:
+// rs1_val == 0x6766656463626160 and rs2_val == 0x6b6a696867666564 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x6766656463626160; op2val:0x6b6a696867666564; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x6766656463626160, 0x6b6a696867666564, x4, 1304, x5)
+
+inst_181:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x4, 1312, x5)
+
+inst_182:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x4, 1320, x5)
+
+inst_183:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x4, 1328, x5)
+
+inst_184:
+// rs1_val == 0x636261605f5e5d5c and rs2_val == 0x5f5e5d5c5b5a5958 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x636261605f5e5d5c; op2val:0x5f5e5d5c5b5a5958; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x636261605f5e5d5c, 0x5f5e5d5c5b5a5958, x4, 1336, x5)
+
+inst_185:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x4, 1344, x5)
+
+inst_186:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x4, 1352, x5)
+
+inst_187:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x4, 1360, x5)
+
+inst_188:
+// rs1_val == 0x5f5e5d5c5b5a5958 and rs2_val == 0x636261605f5e5d5c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5f5e5d5c5b5a5958; op2val:0x636261605f5e5d5c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x5f5e5d5c5b5a5958, 0x636261605f5e5d5c, x4, 1368, x5)
+
+inst_189:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x4, 1376, x5)
+
+inst_190:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x4, 1384, x5)
+
+inst_191:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x4, 1392, x5)
+
+inst_192:
+// rs1_val == 0x5b5a595857565554 and rs2_val == 0x5756555453525150 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5b5a595857565554; op2val:0x5756555453525150; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x5b5a595857565554, 0x5756555453525150, x4, 1400, x5)
+
+inst_193:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x4, 1408, x5)
+
+inst_194:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x4, 1416, x5)
+
+inst_195:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x4, 1424, x5)
+
+inst_196:
+// rs1_val == 0x5756555453525150 and rs2_val == 0x5b5a595857565554 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x5756555453525150; op2val:0x5b5a595857565554; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x5756555453525150, 0x5b5a595857565554, x4, 1432, x5)
+
+inst_197:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x4, 1440, x5)
+
+inst_198:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x4, 1448, x5)
+
+inst_199:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x4, 1456, x5)
+
+inst_200:
+// rs1_val == 0x535251504f4e4d4c and rs2_val == 0x4f4e4d4c4b4a4948 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x535251504f4e4d4c; op2val:0x4f4e4d4c4b4a4948; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x535251504f4e4d4c, 0x4f4e4d4c4b4a4948, x4, 1464, x5)
+
+inst_201:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x4, 1472, x5)
+
+inst_202:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x4, 1480, x5)
+
+inst_203:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x4, 1488, x5)
+
+inst_204:
+// rs1_val == 0x4f4e4d4c4b4a4948 and rs2_val == 0x535251504f4e4d4c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4f4e4d4c4b4a4948; op2val:0x535251504f4e4d4c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x4f4e4d4c4b4a4948, 0x535251504f4e4d4c, x4, 1496, x5)
+
+inst_205:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x4, 1504, x5)
+
+inst_206:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x4, 1512, x5)
+
+inst_207:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x4, 1520, x5)
+
+inst_208:
+// rs1_val == 0x4b4a494847464544 and rs2_val == 0x4746454443424140 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4b4a494847464544; op2val:0x4746454443424140; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x4b4a494847464544, 0x4746454443424140, x4, 1528, x5)
+
+inst_209:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x4, 1536, x5)
+
+inst_210:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x4, 1544, x5)
+
+inst_211:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x4, 1552, x5)
+
+inst_212:
+// rs1_val == 0x4746454443424140 and rs2_val == 0x4b4a494847464544 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x4746454443424140; op2val:0x4b4a494847464544; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x4746454443424140, 0x4b4a494847464544, x4, 1560, x5)
+
+inst_213:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x4, 1568, x5)
+
+inst_214:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x4, 1576, x5)
+
+inst_215:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x4, 1584, x5)
+
+inst_216:
+// rs1_val == 0x434241403f3e3d3c and rs2_val == 0x3f3e3d3c3b3a3938 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x434241403f3e3d3c; op2val:0x3f3e3d3c3b3a3938; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x434241403f3e3d3c, 0x3f3e3d3c3b3a3938, x4, 1592, x5)
+
+inst_217:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x4, 1600, x5)
+
+inst_218:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x4, 1608, x5)
+
+inst_219:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x4, 1616, x5)
+
+inst_220:
+// rs1_val == 0x3f3e3d3c3b3a3938 and rs2_val == 0x434241403f3e3d3c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3f3e3d3c3b3a3938; op2val:0x434241403f3e3d3c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x3f3e3d3c3b3a3938, 0x434241403f3e3d3c, x4, 1624, x5)
+
+inst_221:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x4, 1632, x5)
+
+inst_222:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x4, 1640, x5)
+
+inst_223:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x4, 1648, x5)
+
+inst_224:
+// rs1_val == 0x3b3a393837363534 and rs2_val == 0x3736353433323130 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3b3a393837363534; op2val:0x3736353433323130; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x3b3a393837363534, 0x3736353433323130, x4, 1656, x5)
+
+inst_225:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x4, 1664, x5)
+
+inst_226:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x4, 1672, x5)
+
+inst_227:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x4, 1680, x5)
+
+inst_228:
+// rs1_val == 0x3736353433323130 and rs2_val == 0x3b3a393837363534 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3736353433323130; op2val:0x3b3a393837363534; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x3736353433323130, 0x3b3a393837363534, x4, 1688, x5)
+
+inst_229:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x4, 1696, x5)
+
+inst_230:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x4, 1704, x5)
+
+inst_231:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x4, 1712, x5)
+
+inst_232:
+// rs1_val == 0x333231302f2e2d2c and rs2_val == 0x2f2e2d2c2b2a2928 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x333231302f2e2d2c; op2val:0x2f2e2d2c2b2a2928; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x333231302f2e2d2c, 0x2f2e2d2c2b2a2928, x4, 1720, x5)
+
+inst_233:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x4, 1728, x5)
+
+inst_234:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x4, 1736, x5)
+
+inst_235:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x4, 1744, x5)
+
+inst_236:
+// rs1_val == 0x2f2e2d2c2b2a2928 and rs2_val == 0x333231302f2e2d2c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2f2e2d2c2b2a2928; op2val:0x333231302f2e2d2c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x2f2e2d2c2b2a2928, 0x333231302f2e2d2c, x4, 1752, x5)
+
+inst_237:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x4, 1760, x5)
+
+inst_238:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x4, 1768, x5)
+
+inst_239:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x4, 1776, x5)
+
+inst_240:
+// rs1_val == 0x2b2a292827262524 and rs2_val == 0x2726252423222120 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2b2a292827262524; op2val:0x2726252423222120; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x2b2a292827262524, 0x2726252423222120, x4, 1784, x5)
+
+inst_241:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x4, 1792, x5)
+
+inst_242:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x4, 1800, x5)
+
+inst_243:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x4, 1808, x5)
+
+inst_244:
+// rs1_val == 0x2726252423222120 and rs2_val == 0x2b2a292827262524 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x2726252423222120; op2val:0x2b2a292827262524; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x2726252423222120, 0x2b2a292827262524, x4, 1816, x5)
+
+inst_245:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x4, 1824, x5)
+
+inst_246:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x4, 1832, x5)
+
+inst_247:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x4, 1840, x5)
+
+inst_248:
+// rs1_val == 0x232221201f1e1d1c and rs2_val == 0x1f1e1d1c1b1a1918 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x232221201f1e1d1c; op2val:0x1f1e1d1c1b1a1918; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x232221201f1e1d1c, 0x1f1e1d1c1b1a1918, x4, 1848, x5)
+
+inst_249:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x4, 1856, x5)
+
+inst_250:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x4, 1864, x5)
+
+inst_251:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x4, 1872, x5)
+
+inst_252:
+// rs1_val == 0x1f1e1d1c1b1a1918 and rs2_val == 0x232221201f1e1d1c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1f1e1d1c1b1a1918; op2val:0x232221201f1e1d1c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x1f1e1d1c1b1a1918, 0x232221201f1e1d1c, x4, 1880, x5)
+
+inst_253:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x4, 1888, x5)
+
+inst_254:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x4, 1896, x5)
+
+inst_255:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x4, 1904, x5)
+
+inst_256:
+// rs1_val == 0x1b1a191817161514 and rs2_val == 0x1716151413121110 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1b1a191817161514; op2val:0x1716151413121110; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x1b1a191817161514, 0x1716151413121110, x4, 1912, x5)
+
+inst_257:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x4, 1920, x5)
+
+inst_258:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x4, 1928, x5)
+
+inst_259:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x4, 1936, x5)
+
+inst_260:
+// rs1_val == 0x1716151413121110 and rs2_val == 0x1b1a191817161514 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x1716151413121110; op2val:0x1b1a191817161514; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x1716151413121110, 0x1b1a191817161514, x4, 1944, x5)
+
+inst_261:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x4, 1952, x5)
+
+inst_262:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x4, 1960, x5)
+
+inst_263:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x4, 1968, x5)
+
+inst_264:
+// rs1_val == 0x131211100f0e0d0c and rs2_val == 0x0f0e0d0c0b0a0908 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x131211100f0e0d0c; op2val:0xf0e0d0c0b0a0908; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x131211100f0e0d0c, 0xf0e0d0c0b0a0908, x4, 1976, x5)
+
+inst_265:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x4, 1984, x5)
+
+inst_266:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x4, 1992, x5)
+
+inst_267:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x4, 2000, x5)
+
+inst_268:
+// rs1_val == 0x0f0e0d0c0b0a0908 and rs2_val == 0x131211100f0e0d0c and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xf0e0d0c0b0a0908; op2val:0x131211100f0e0d0c; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xf0e0d0c0b0a0908, 0x131211100f0e0d0c, x4, 2008, x5)
+
+inst_269:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x4, 2016, x5)
+
+inst_270:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x4, 2024, x5)
+
+inst_271:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x4, 2032, x5)
+
+inst_272:
+// rs1_val == 0x0b0a090807060504 and rs2_val == 0x0706050403020100 and imm_val == 0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xb0a090807060504; op2val:0x706050403020100; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0xb0a090807060504, 0x706050403020100, x4, 2040, x5)
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_273:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 3 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x3
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x3, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x4, 0, x5)
+
+inst_274:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x4, 8, x5)
+
+inst_275:
+// rs1_val == 0x0706050403020100 and rs2_val == 0x0b0a090807060504 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x706050403020100; op2val:0xb0a090807060504; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x706050403020100, 0xb0a090807060504, x4, 16, x5)
+
+inst_276:
+// rs1_val == 0x156fe482f9fcd292 and rs2_val == 0x24c6435c8dca0621 and imm_val == 0x0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x156fe482f9fcd292; op2val:0x24c6435c8dca0621; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x156fe482f9fcd292, 0x24c6435c8dca0621, x4, 24, x5)
+
+inst_277:
+// rs1_val == 0xa757e91e027e5943 and rs2_val == 0xda73ec2605e6750f and imm_val == 0x2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa757e91e027e5943; op2val:0xda73ec2605e6750f; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xa757e91e027e5943, 0xda73ec2605e6750f, x4, 32, x5)
+
+inst_278:
+// rs1_val == 0xa6c9253a4cc6382e and rs2_val == 0x25ae27ee4113ee60 and imm_val == 0x2 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0xa6c9253a4cc6382e; op2val:0x25ae27ee4113ee60; immval:0x2
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x2, 0x0000000000000000, 0xa6c9253a4cc6382e, 0x25ae27ee4113ee60, x4, 40, x5)
+
+inst_279:
+// rs1_val == 0x59885afcbb61a9cd and rs2_val == 0xccce240c81c1e7ff and imm_val == 0x0 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x59885afcbb61a9cd; op2val:0xccce240c81c1e7ff; immval:0x0
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x0, 0x0000000000000000, 0x59885afcbb61a9cd, 0xccce240c81c1e7ff, x4, 48, x5)
+
+inst_280:
+// rs1_val == 0x03020100fffefdfc and rs2_val == 0xfffefdfcfbfaf9f8 and imm_val == 1 
+// opcode: sm4ks; rd: x12; op1:x10; op2:x11; op1val:0x3020100fffefdfc; op2val:0xfffefdfcfbfaf9f8; immval:0x1
+TEST_RI_OP(sm4ks, x12, x10, x11, 0x1, 0x0000000000000000, 0x3020100fffefdfc, 0xfffefdfcfbfaf9f8, x4, 56, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x2_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 17*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 8*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S
new file mode 100644
index 000000000..8cb95a8bb
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/sm4ks-rwp1.S
@@ -0,0 +1,415 @@
+
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64IK")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*K.*);def TEST_CASE_1=True;",sm4ks)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*RV64.*I.*ZKs.*);def TEST_CASE_1=True;",sm4ks)
+
+RVTEST_SIGBASE( x31,signature_x31_1)
+
+inst_0:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x1; op1:x2; op1:x3; op1:x4; dest:x5;
+li  x1, 0x08577eb1924770d3;
+li  x2, 0x93fdcab87b89296c;
+li  x3, 0xd2d6b8777dc59a3a;
+li  x4, 0xcf84b683a749f9c5;
+li  x5, 0x854a965708ceac39;
+sm4ks x5, x5, x1, 0;
+sm4ks x5, x5, x2, 1;
+sm4ks x5, x5, x3, 2;
+sm4ks x5, x5, x4, 3;
+RVTEST_SIGUPD(x31,x5,0);
+
+inst_1:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x2; op1:x3; op1:x4; op1:x5; dest:x6;
+li  x2, 0x137a977753e8eb43;
+li  x3, 0x5c74e45eff1e5bef;
+li  x4, 0xdc3383836b9f15c4;
+li  x5, 0x5ae6a2289a6ab329;
+li  x6, 0x432779eeacca7f0d;
+sm4ks x6, x6, x2, 0;
+sm4ks x6, x6, x3, 1;
+sm4ks x6, x6, x4, 2;
+sm4ks x6, x6, x5, 3;
+RVTEST_SIGUPD(x31,x6,8);
+
+inst_2:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x3; op1:x4; op1:x5; op1:x6; dest:x7;
+li  x3, 0xaf949e5e2cb7362c;
+li  x4, 0x5cd2875ea96ec2b3;
+li  x5, 0x9d02fc90708cc1b6;
+li  x6, 0x953b00b00b54aa22;
+li  x7, 0x224c06013c53d0e3;
+sm4ks x7, x7, x3, 0;
+sm4ks x7, x7, x4, 1;
+sm4ks x7, x7, x5, 2;
+sm4ks x7, x7, x6, 3;
+RVTEST_SIGUPD(x31,x7,16);
+
+inst_3:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x4; op1:x5; op1:x6; op1:x7; dest:x8;
+li  x4, 0xe8dac663f0e58650;
+li  x5, 0x3d7c95f9e5f0307e;
+li  x6, 0x8c8a18b2aaac3142;
+li  x7, 0x785036de6f9fb997;
+li  x8, 0x95a4d257a7298c66;
+sm4ks x8, x8, x4, 0;
+sm4ks x8, x8, x5, 1;
+sm4ks x8, x8, x6, 2;
+sm4ks x8, x8, x7, 3;
+RVTEST_SIGUPD(x31,x8,24);
+
+inst_4:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x5; op1:x6; op1:x7; op1:x8; dest:x9;
+li  x5, 0x807da245d814d575;
+li  x6, 0x3d06143769b1dcbf;
+li  x7, 0x7f21682208208d09;
+li  x8, 0x14b91c79dae98554;
+li  x9, 0xc5ec6148c6880007;
+sm4ks x9, x9, x5, 0;
+sm4ks x9, x9, x6, 1;
+sm4ks x9, x9, x7, 2;
+sm4ks x9, x9, x8, 3;
+RVTEST_SIGUPD(x31,x9,32);
+
+inst_5:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x6; op1:x7; op1:x8; op1:x9; dest:x10;
+li  x6, 0x7213516d6a013380;
+li  x7, 0x4652f62dae4839a1;
+li  x8, 0x85986adb9e044706;
+li  x9, 0x1e9667c2dd68f201;
+li  x10, 0x4d753ac174ab0a38;
+sm4ks x10, x10, x6, 0;
+sm4ks x10, x10, x7, 1;
+sm4ks x10, x10, x8, 2;
+sm4ks x10, x10, x9, 3;
+RVTEST_SIGUPD(x31,x10,40);
+
+inst_6:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x7; op1:x8; op1:x9; op1:x10; dest:x11;
+li  x7, 0x53fbff6c58fa6e1c;
+li  x8, 0x0b2e2669b66b3284;
+li  x9, 0x51c5b8b2e59cf78f;
+li  x10, 0x43032e3e1475f78d;
+li  x11, 0x9535971c67a07b54;
+sm4ks x11, x11, x7, 0;
+sm4ks x11, x11, x8, 1;
+sm4ks x11, x11, x9, 2;
+sm4ks x11, x11, x10, 3;
+RVTEST_SIGUPD(x31,x11,48);
+
+inst_7:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x8; op1:x9; op1:x10; op1:x11; dest:x12;
+li  x8, 0xe918be9ffe057dc5;
+li  x9, 0x1011eeb47ff822ed;
+li  x10, 0xac9e90327d486895;
+li  x11, 0x66b072b9e5e290be;
+li  x12, 0x89e6156b59672bd6;
+sm4ks x12, x12, x8, 0;
+sm4ks x12, x12, x9, 1;
+sm4ks x12, x12, x10, 2;
+sm4ks x12, x12, x11, 3;
+RVTEST_SIGUPD(x31,x12,56);
+
+inst_8:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x9; op1:x10; op1:x11; op1:x12; dest:x13;
+li  x9, 0xb3a63fa37d69ceef;
+li  x10, 0x70fc1afc8f0846a2;
+li  x11, 0xf956ec0bf7fb4b49;
+li  x12, 0x0cf25923109ff475;
+li  x13, 0x26ea42ec17be082f;
+sm4ks x13, x13, x9, 0;
+sm4ks x13, x13, x10, 1;
+sm4ks x13, x13, x11, 2;
+sm4ks x13, x13, x12, 3;
+RVTEST_SIGUPD(x31,x13,64);
+
+inst_9:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x10; op1:x11; op1:x12; op1:x13; dest:x14;
+li  x10, 0xccadb61ffe20ce1c;
+li  x11, 0x72745307ec325eec;
+li  x12, 0xb2a7a18ac9ea3210;
+li  x13, 0xbd59213e27541f0b;
+li  x14, 0x9e7e1fc352b42eff;
+sm4ks x14, x14, x10, 0;
+sm4ks x14, x14, x11, 1;
+sm4ks x14, x14, x12, 2;
+sm4ks x14, x14, x13, 3;
+RVTEST_SIGUPD(x31,x14,72);
+
+inst_10:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x11; op1:x12; op1:x13; op1:x14; dest:x15;
+li  x11, 0xa0e0bd86d4551408;
+li  x12, 0xcebe24d906600792;
+li  x13, 0x4bd90a77f65cf3f3;
+li  x14, 0xdbdd4dd9d9e93409;
+li  x15, 0xf65e7737fbd2570d;
+sm4ks x15, x15, x11, 0;
+sm4ks x15, x15, x12, 1;
+sm4ks x15, x15, x13, 2;
+sm4ks x15, x15, x14, 3;
+RVTEST_SIGUPD(x31,x15,80);
+
+inst_11:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x12; op1:x13; op1:x14; op1:x15; dest:x16;
+li  x12, 0xd1142724fb37bec8;
+li  x13, 0xab8534c129a2575f;
+li  x14, 0xfc6113a3312529dc;
+li  x15, 0x6d3f408b31d4ff08;
+li  x16, 0x8e368ce0be5265f3;
+sm4ks x16, x16, x12, 0;
+sm4ks x16, x16, x13, 1;
+sm4ks x16, x16, x14, 2;
+sm4ks x16, x16, x15, 3;
+RVTEST_SIGUPD(x31,x16,88);
+
+inst_12:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x13; op1:x14; op1:x15; op1:x16; dest:x17;
+li  x13, 0x98f7c41c44115b04;
+li  x14, 0x01fbbe93a08b84f3;
+li  x15, 0x9c1a15286c834752;
+li  x16, 0xa6faba7bcfe6bc54;
+li  x17, 0xc5b3e01b11f6d600;
+sm4ks x17, x17, x13, 0;
+sm4ks x17, x17, x14, 1;
+sm4ks x17, x17, x15, 2;
+sm4ks x17, x17, x16, 3;
+RVTEST_SIGUPD(x31,x17,96);
+
+inst_13:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x14; op1:x15; op1:x16; op1:x17; dest:x18;
+li  x14, 0x5916d2810e24d9cc;
+li  x15, 0x74f5add55c37849a;
+li  x16, 0x4850e927bfdbb3be;
+li  x17, 0x67913217437cbc41;
+li  x18, 0x576e3d4fa3b633ab;
+sm4ks x18, x18, x14, 0;
+sm4ks x18, x18, x15, 1;
+sm4ks x18, x18, x16, 2;
+sm4ks x18, x18, x17, 3;
+RVTEST_SIGUPD(x31,x18,104);
+
+inst_14:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x15; op1:x16; op1:x17; op1:x18; dest:x19;
+li  x15, 0x46ed745fb9fef1d6;
+li  x16, 0x9651ee657a1d33ca;
+li  x17, 0xfe0a9c6c9a592829;
+li  x18, 0x9071f3aab87ce2a5;
+li  x19, 0x4e6168c8d6220b4f;
+sm4ks x19, x19, x15, 0;
+sm4ks x19, x19, x16, 1;
+sm4ks x19, x19, x17, 2;
+sm4ks x19, x19, x18, 3;
+RVTEST_SIGUPD(x31,x19,112);
+
+inst_15:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x16; op1:x17; op1:x18; op1:x19; dest:x20;
+li  x16, 0x9c3d087c65835bdf;
+li  x17, 0x9b11d383484641f5;
+li  x18, 0x2b24ced43da82c98;
+li  x19, 0xef8c60c0d12f8d4e;
+li  x20, 0xf37e27a312ea67e4;
+sm4ks x20, x20, x16, 0;
+sm4ks x20, x20, x17, 1;
+sm4ks x20, x20, x18, 2;
+sm4ks x20, x20, x19, 3;
+RVTEST_SIGUPD(x31,x20,120);
+
+inst_16:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x17; op1:x18; op1:x19; op1:x20; dest:x21;
+li  x17, 0x041bbaab97eb7c0f;
+li  x18, 0x93017690e356529c;
+li  x19, 0xd5e9d561f46a41bd;
+li  x20, 0x9408ad7db13971c0;
+li  x21, 0x90af95fe095b6425;
+sm4ks x21, x21, x17, 0;
+sm4ks x21, x21, x18, 1;
+sm4ks x21, x21, x19, 2;
+sm4ks x21, x21, x20, 3;
+RVTEST_SIGUPD(x31,x21,128);
+
+inst_17:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x18; op1:x19; op1:x20; op1:x21; dest:x22;
+li  x18, 0xef677106dc17ae6e;
+li  x19, 0xc5d09b942be2d8c9;
+li  x20, 0x596f5f89ce334459;
+li  x21, 0x5902a9dbe1832ab6;
+li  x22, 0xb4dc7dee71dabeac;
+sm4ks x22, x22, x18, 0;
+sm4ks x22, x22, x19, 1;
+sm4ks x22, x22, x20, 2;
+sm4ks x22, x22, x21, 3;
+RVTEST_SIGUPD(x31,x22,136);
+
+inst_18:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x19; op1:x20; op1:x21; op1:x22; dest:x23;
+li  x19, 0x755961a98347ddf5;
+li  x20, 0x18d71be431c00570;
+li  x21, 0x270e1922a422af66;
+li  x22, 0xdc336338eea4dd03;
+li  x23, 0xa2460e15a3da90b2;
+sm4ks x23, x23, x19, 0;
+sm4ks x23, x23, x20, 1;
+sm4ks x23, x23, x21, 2;
+sm4ks x23, x23, x22, 3;
+RVTEST_SIGUPD(x31,x23,144);
+
+inst_19:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x20; op1:x21; op1:x22; op1:x23; dest:x24;
+li  x20, 0x8f2248c25c3577f5;
+li  x21, 0x2a5dc0a00d453cdf;
+li  x22, 0xf3281b8ef4d325c3;
+li  x23, 0x947ac00e0caec993;
+li  x24, 0xd60235f35c4739b7;
+sm4ks x24, x24, x20, 0;
+sm4ks x24, x24, x21, 1;
+sm4ks x24, x24, x22, 2;
+sm4ks x24, x24, x23, 3;
+RVTEST_SIGUPD(x31,x24,152);
+
+inst_20:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x21; op1:x22; op1:x23; op1:x24; dest:x25;
+li  x21, 0x6dc3cceec36ffd4b;
+li  x22, 0xc2713ce25868105b;
+li  x23, 0x29ade05f7dddcc72;
+li  x24, 0x6baeea37b4c8839b;
+li  x25, 0x1e4e0fadd02bad0f;
+sm4ks x25, x25, x21, 0;
+sm4ks x25, x25, x22, 1;
+sm4ks x25, x25, x23, 2;
+sm4ks x25, x25, x24, 3;
+RVTEST_SIGUPD(x31,x25,160);
+
+inst_21:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x22; op1:x23; op1:x24; op1:x25; dest:x26;
+li  x22, 0xe4367ccad9716f2c;
+li  x23, 0x9ea76f0885958881;
+li  x24, 0xb183406662ebf954;
+li  x25, 0x796c1d88c313bc1f;
+li  x26, 0xe7e94a5193b3cb9a;
+sm4ks x26, x26, x22, 0;
+sm4ks x26, x26, x23, 1;
+sm4ks x26, x26, x24, 2;
+sm4ks x26, x26, x25, 3;
+RVTEST_SIGUPD(x31,x26,168);
+
+inst_22:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x23; op1:x24; op1:x25; op1:x26; dest:x27;
+li  x23, 0x37c4c6b99530db93;
+li  x24, 0x132a717606aec150;
+li  x25, 0x08011d17cfac3216;
+li  x26, 0xd65358aaa734906b;
+li  x27, 0xba1c4b6b2d9da6d7;
+sm4ks x27, x27, x23, 0;
+sm4ks x27, x27, x24, 1;
+sm4ks x27, x27, x25, 2;
+sm4ks x27, x27, x26, 3;
+RVTEST_SIGUPD(x31,x27,176);
+
+inst_23:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x24; op1:x25; op1:x26; op1:x27; dest:x28;
+li  x24, 0x04d3e5f42bccd6b6;
+li  x25, 0x339863c4d216eea8;
+li  x26, 0x3f13091de7fcc18b;
+li  x27, 0xc2cc1d388d15d800;
+li  x28, 0x0165f0f02016dc16;
+sm4ks x28, x28, x24, 0;
+sm4ks x28, x28, x25, 1;
+sm4ks x28, x28, x26, 2;
+sm4ks x28, x28, x27, 3;
+RVTEST_SIGUPD(x31,x28,184);
+
+inst_24:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x25; op1:x26; op1:x27; op1:x28; dest:x29;
+li  x25, 0xd6ac851f07155a89;
+li  x26, 0x2d885062faa97965;
+li  x27, 0x62a12347b17286fd;
+li  x28, 0xa97cbf8403beaecd;
+li  x29, 0xa9632e3dbd0070ae;
+sm4ks x29, x29, x25, 0;
+sm4ks x29, x29, x26, 1;
+sm4ks x29, x29, x27, 2;
+sm4ks x29, x29, x28, 3;
+RVTEST_SIGUPD(x31,x29,192);
+
+inst_25:
+// Expected use-case sequence -> Aims to test things like pipeline forwarding
+// opcode: sm4ks; op1:x26; op1:x27; op1:x28; op1:x29; dest:x30;
+li  x26, 0x8d3ba7550c3c31a8;
+li  x27, 0xb3e73cbb0d8258c4;
+li  x28, 0x7587e11994038f33;
+li  x29, 0x2f8d133555f7f60a;
+li  x30, 0xa0a1c6ef661a191b;
+sm4ks x30, x30, x26, 0;
+sm4ks x30, x30, x27, 1;
+sm4ks x30, x30, x28, 2;
+sm4ks x30, x30, x29, 3;
+RVTEST_SIGUPD(x31,x30,200);
+
+#endif
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x31_1:
+    .fill 26*(XLEN/32),4,0xdeadbeef
+    
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S
new file mode 100644
index 000000000..e8675ad95
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xnor-01.S
@@ -0,0 +1,2711 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 20 05:32:05 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the xnor instruction of the RISC-V  extension for the xnor covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",xnor)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",xnor)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",xnor)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",xnor)
+
+RVTEST_SIGBASE( x12,signature_x12_1)
+
+inst_0:
+// rs1 == rs2 != rd, rs1==x24, rs2==x24, rd==x16, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: xnor ; op1:x24; op2:x24; dest:x16; op1val:0xffffffffffffffff;  op2val:0xffffffffffffffff
+TEST_RR_OP(xnor, x16, x24, x24, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, x12, 0, x19)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x14, rs2==x14, rd==x14, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: xnor ; op1:x14; op2:x14; dest:x14; op1val:0x5ba2c7dd5ae10604;  op2val:0x5ba2c7dd5ae10604
+TEST_RR_OP(xnor, x14, x14, x14, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x5ba2c7dd5ae10604, x12, 8, x19)
+
+inst_2:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x8, rs2==x7, rd==x31, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: xnor ; op1:x8; op2:x7; dest:x31; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(xnor, x31, x8, x7, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x12, 16, x19)
+
+inst_3:
+// rs1 == rd != rs2, rs1==x11, rs2==x31, rd==x11, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: xnor ; op1:x11; op2:x31; dest:x11; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(xnor, x11, x11, x31, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x12, 24, x19)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x7, rs2==x10, rd==x10, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: xnor ; op1:x7; op2:x10; dest:x10; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(xnor, x10, x7, x10, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x12, 32, x19)
+
+inst_5:
+// rs1==x13, rs2==x22, rd==x27, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: xnor ; op1:x13; op2:x22; dest:x27; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(xnor, x27, x13, x22, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x12, 40, x19)
+
+inst_6:
+// rs1==x1, rs2==x5, rd==x7, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: xnor ; op1:x1; op2:x5; dest:x7; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(xnor, x7, x1, x5, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x12, 48, x19)
+
+inst_7:
+// rs1==x0, rs2==x28, rd==x2, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: xnor ; op1:x0; op2:x28; dest:x2; op1val:0x0;  op2val:0x4c00000000000000
+TEST_RR_OP(xnor, x2, x0, x28, 0x0000000000000000, 0x0, 0x4c00000000000000, x12, 56, x19)
+
+inst_8:
+// rs1==x2, rs2==x21, rd==x4, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: xnor ; op1:x2; op2:x21; dest:x4; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(xnor, x4, x2, x21, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x12, 64, x19)
+
+inst_9:
+// rs1==x21, rs2==x18, rd==x1, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: xnor ; op1:x21; op2:x18; dest:x1; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(xnor, x1, x21, x18, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x12, 72, x19)
+
+inst_10:
+// rs1==x27, rs2==x0, rd==x5, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: xnor ; op1:x27; op2:x0; dest:x5; op1val:0xbf28804a83e2ba3a;  op2val:0x0
+TEST_RR_OP(xnor, x5, x27, x0, 0x0000000000000000, 0xbf28804a83e2ba3a, 0x0, x12, 80, x19)
+
+inst_11:
+// rs1==x3, rs2==x25, rd==x6, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: xnor ; op1:x3; op2:x25; dest:x6; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(xnor, x6, x3, x25, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x12, 88, x19)
+
+inst_12:
+// rs1==x20, rs2==x2, rd==x25, rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: xnor ; op1:x20; op2:x2; dest:x25; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(xnor, x25, x20, x2, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x12, 96, x19)
+
+inst_13:
+// rs1==x17, rs2==x27, rd==x0, rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: xnor ; op1:x17; op2:x27; dest:x0; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(xnor, x0, x17, x27, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x12, 104, x19)
+
+inst_14:
+// rs1==x30, rs2==x8, rd==x22, rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: xnor ; op1:x30; op2:x8; dest:x22; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(xnor, x22, x30, x8, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x12, 112, x19)
+
+inst_15:
+// rs1==x23, rs2==x9, rd==x15, rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: xnor ; op1:x23; op2:x9; dest:x15; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(xnor, x15, x23, x9, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x12, 120, x19)
+
+inst_16:
+// rs1==x4, rs2==x16, rd==x23, rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: xnor ; op1:x4; op2:x16; dest:x23; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(xnor, x23, x4, x16, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x12, 128, x1)
+
+inst_17:
+// rs1==x25, rs2==x26, rd==x13, rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: xnor ; op1:x25; op2:x26; dest:x13; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(xnor, x13, x25, x26, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x12, 136, x1)
+RVTEST_SIGBASE( x7,signature_x7_0)
+
+inst_18:
+// rs1==x10, rs2==x23, rd==x9, rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: xnor ; op1:x10; op2:x23; dest:x9; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(xnor, x9, x10, x23, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x7, 0, x1)
+
+inst_19:
+// rs1==x16, rs2==x15, rd==x3, rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: xnor ; op1:x16; op2:x15; dest:x3; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(xnor, x3, x16, x15, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x7, 8, x1)
+
+inst_20:
+// rs1==x15, rs2==x13, rd==x20, rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: xnor ; op1:x15; op2:x13; dest:x20; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(xnor, x20, x15, x13, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x7, 16, x1)
+
+inst_21:
+// rs1==x22, rs2==x30, rd==x19, rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: xnor ; op1:x22; op2:x30; dest:x19; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(xnor, x19, x22, x30, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x7, 24, x1)
+
+inst_22:
+// rs1==x5, rs2==x12, rd==x18, rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: xnor ; op1:x5; op2:x12; dest:x18; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(xnor, x18, x5, x12, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x7, 32, x1)
+
+inst_23:
+// rs1==x6, rs2==x20, rd==x8, rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: xnor ; op1:x6; op2:x20; dest:x8; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(xnor, x8, x6, x20, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x7, 40, x1)
+
+inst_24:
+// rs1==x9, rs2==x19, rd==x24, rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: xnor ; op1:x9; op2:x19; dest:x24; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(xnor, x24, x9, x19, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x7, 48, x1)
+
+inst_25:
+// rs1==x26, rs2==x17, rd==x21, rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: xnor ; op1:x26; op2:x17; dest:x21; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(xnor, x21, x26, x17, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x7, 56, x1)
+
+inst_26:
+// rs1==x12, rs2==x11, rd==x28, rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: xnor ; op1:x12; op2:x11; dest:x28; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(xnor, x28, x12, x11, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x7, 64, x1)
+
+inst_27:
+// rs1==x28, rs2==x6, rd==x26, rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: xnor ; op1:x28; op2:x6; dest:x26; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(xnor, x26, x28, x6, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x7, 72, x1)
+
+inst_28:
+// rs1==x19, rs2==x4, rd==x30, rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: xnor ; op1:x19; op2:x4; dest:x30; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(xnor, x30, x19, x4, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x7, 80, x1)
+
+inst_29:
+// rs1==x31, rs2==x3, rd==x17, rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: xnor ; op1:x31; op2:x3; dest:x17; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(xnor, x17, x31, x3, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x7, 88, x1)
+
+inst_30:
+// rs1==x18, rs2==x29, rd==x12, rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: xnor ; op1:x18; op2:x29; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(xnor, x12, x18, x29, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x7, 96, x1)
+
+inst_31:
+// rs1==x29, rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: xnor ; op1:x29; op2:x5; dest:x2; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(xnor, x2, x29, x5, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x7, 104, x1)
+
+inst_32:
+// rs2==x1, rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: xnor ; op1:x11; op2:x1; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(xnor, x12, x11, x1, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x7, 112, x2)
+
+inst_33:
+// rd==x29, rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: xnor ; op1:x30; op2:x10; dest:x29; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(xnor, x29, x30, x10, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x7, 120, x2)
+
+inst_34:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x7, 128, x2)
+
+inst_35:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x7, 136, x2)
+
+inst_36:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x7, 144, x2)
+
+inst_37:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x7, 152, x2)
+
+inst_38:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x7, 160, x2)
+
+inst_39:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x7, 168, x2)
+
+inst_40:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x7, 176, x2)
+
+inst_41:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x7, 184, x2)
+
+inst_42:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x7, 192, x2)
+
+inst_43:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x7, 200, x2)
+
+inst_44:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x7, 208, x2)
+
+inst_45:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x7, 216, x2)
+
+inst_46:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x7, 224, x2)
+
+inst_47:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x7, 232, x2)
+
+inst_48:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x7, 240, x2)
+
+inst_49:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x7, 248, x2)
+
+inst_50:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x7, 256, x2)
+
+inst_51:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x7, 264, x2)
+
+inst_52:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x7, 272, x2)
+
+inst_53:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x7, 280, x2)
+
+inst_54:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x7, 288, x2)
+
+inst_55:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x7, 296, x2)
+
+inst_56:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x7, 304, x2)
+
+inst_57:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x7, 312, x2)
+
+inst_58:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x7, 320, x2)
+
+inst_59:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x7, 328, x2)
+
+inst_60:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x7, 336, x2)
+
+inst_61:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x7, 344, x2)
+
+inst_62:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x7, 352, x2)
+
+inst_63:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x7, 360, x2)
+
+inst_64:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x7, 368, x2)
+
+inst_65:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x7, 376, x2)
+
+inst_66:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x7, 384, x2)
+
+inst_67:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x7, 392, x2)
+
+inst_68:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x7, 400, x2)
+
+inst_69:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x7, 408, x2)
+
+inst_70:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x7, 416, x2)
+
+inst_71:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x7, 424, x2)
+
+inst_72:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x7, 432, x2)
+
+inst_73:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x7, 440, x2)
+
+inst_74:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x7, 448, x2)
+
+inst_75:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x7, 456, x2)
+
+inst_76:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x7, 464, x2)
+
+inst_77:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x7, 472, x2)
+
+inst_78:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x7, 480, x2)
+
+inst_79:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x7, 488, x2)
+
+inst_80:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x7, 496, x2)
+
+inst_81:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x7, 504, x2)
+
+inst_82:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x7, 512, x2)
+
+inst_83:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x7, 520, x2)
+
+inst_84:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x7, 528, x2)
+
+inst_85:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x7, 536, x2)
+
+inst_86:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x7, 544, x2)
+
+inst_87:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x7, 552, x2)
+
+inst_88:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x7, 560, x2)
+
+inst_89:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x7, 568, x2)
+
+inst_90:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x7, 576, x2)
+
+inst_91:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x7, 584, x2)
+
+inst_92:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x7, 592, x2)
+
+inst_93:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x7, 600, x2)
+
+inst_94:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x7, 608, x2)
+
+inst_95:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x7, 616, x2)
+
+inst_96:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x7, 624, x2)
+
+inst_97:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x7, 632, x2)
+
+inst_98:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x7, 640, x2)
+
+inst_99:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x7, 648, x2)
+
+inst_100:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x7, 656, x2)
+
+inst_101:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x7, 664, x2)
+
+inst_102:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x7, 672, x2)
+
+inst_103:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x7, 680, x2)
+
+inst_104:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x7, 688, x2)
+
+inst_105:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x7, 696, x2)
+
+inst_106:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x7, 704, x2)
+
+inst_107:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x7, 712, x2)
+
+inst_108:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x7, 720, x2)
+
+inst_109:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x7, 728, x2)
+
+inst_110:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x7, 736, x2)
+
+inst_111:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x7, 744, x2)
+
+inst_112:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x7, 752, x2)
+
+inst_113:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x7, 760, x2)
+
+inst_114:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x7, 768, x2)
+
+inst_115:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x7, 776, x2)
+
+inst_116:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x7, 784, x2)
+
+inst_117:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x7, 792, x2)
+
+inst_118:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x7, 800, x2)
+
+inst_119:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x7, 808, x2)
+
+inst_120:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x7, 816, x2)
+
+inst_121:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x7, 824, x2)
+
+inst_122:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x7, 832, x2)
+
+inst_123:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x7, 840, x2)
+
+inst_124:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x7, 848, x2)
+
+inst_125:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x7, 856, x2)
+
+inst_126:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x7, 864, x2)
+
+inst_127:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x7, 872, x2)
+
+inst_128:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x7, 880, x2)
+
+inst_129:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x7, 888, x2)
+
+inst_130:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x7, 896, x2)
+
+inst_131:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x7, 904, x2)
+
+inst_132:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x7, 912, x2)
+
+inst_133:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x7, 920, x2)
+
+inst_134:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x7, 928, x2)
+
+inst_135:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x7, 936, x2)
+
+inst_136:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x7, 944, x2)
+
+inst_137:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x7, 952, x2)
+
+inst_138:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x7, 960, x2)
+
+inst_139:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x7, 968, x2)
+
+inst_140:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x7, 976, x2)
+
+inst_141:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x7, 984, x2)
+
+inst_142:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x7, 992, x2)
+
+inst_143:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x7, 1000, x2)
+
+inst_144:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x7, 1008, x2)
+
+inst_145:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x7, 1016, x2)
+
+inst_146:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x7, 1024, x2)
+
+inst_147:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x7, 1032, x2)
+
+inst_148:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x7, 1040, x2)
+
+inst_149:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x7, 1048, x2)
+
+inst_150:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x7, 1056, x2)
+
+inst_151:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x7, 1064, x2)
+
+inst_152:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x7, 1072, x2)
+
+inst_153:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x7, 1080, x2)
+
+inst_154:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x7, 1088, x2)
+
+inst_155:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x7, 1096, x2)
+
+inst_156:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x7, 1104, x2)
+
+inst_157:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x7, 1112, x2)
+
+inst_158:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x7, 1120, x2)
+
+inst_159:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x7, 1128, x2)
+
+inst_160:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x7, 1136, x2)
+
+inst_161:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x7, 1144, x2)
+
+inst_162:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x7, 1152, x2)
+
+inst_163:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x7, 1160, x2)
+
+inst_164:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x7, 1168, x2)
+
+inst_165:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x7, 1176, x2)
+
+inst_166:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x7, 1184, x2)
+
+inst_167:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x7, 1192, x2)
+
+inst_168:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x7, 1200, x2)
+
+inst_169:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x7, 1208, x2)
+
+inst_170:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x7, 1216, x2)
+
+inst_171:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x7, 1224, x2)
+
+inst_172:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x7, 1232, x2)
+
+inst_173:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x7, 1240, x2)
+
+inst_174:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x7, 1248, x2)
+
+inst_175:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x7, 1256, x2)
+
+inst_176:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x7, 1264, x2)
+
+inst_177:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x7, 1272, x2)
+
+inst_178:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x7, 1280, x2)
+
+inst_179:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x7, 1288, x2)
+
+inst_180:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x7, 1296, x2)
+
+inst_181:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x7, 1304, x2)
+
+inst_182:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x7, 1312, x2)
+
+inst_183:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x7, 1320, x2)
+
+inst_184:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x7, 1328, x2)
+
+inst_185:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x7, 1336, x2)
+
+inst_186:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x7, 1344, x2)
+
+inst_187:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x7, 1352, x2)
+
+inst_188:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x7, 1360, x2)
+
+inst_189:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x7, 1368, x2)
+
+inst_190:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x7, 1376, x2)
+
+inst_191:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x7, 1384, x2)
+
+inst_192:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x7, 1392, x2)
+
+inst_193:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x7, 1400, x2)
+
+inst_194:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x7, 1408, x2)
+
+inst_195:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x7, 1416, x2)
+
+inst_196:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x7, 1424, x2)
+
+inst_197:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x7, 1432, x2)
+
+inst_198:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x7, 1440, x2)
+
+inst_199:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x7, 1448, x2)
+
+inst_200:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x7, 1456, x2)
+
+inst_201:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x7, 1464, x2)
+
+inst_202:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x7, 1472, x2)
+
+inst_203:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x7, 1480, x2)
+
+inst_204:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x7, 1488, x2)
+
+inst_205:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x7, 1496, x2)
+
+inst_206:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x7, 1504, x2)
+
+inst_207:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x7, 1512, x2)
+
+inst_208:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x7, 1520, x2)
+
+inst_209:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x7, 1528, x2)
+
+inst_210:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x7, 1536, x2)
+
+inst_211:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x7, 1544, x2)
+
+inst_212:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x7, 1552, x2)
+
+inst_213:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x7, 1560, x2)
+
+inst_214:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x7, 1568, x2)
+
+inst_215:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x7, 1576, x2)
+
+inst_216:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x7, 1584, x2)
+
+inst_217:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x7, 1592, x2)
+
+inst_218:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x7, 1600, x2)
+
+inst_219:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x7, 1608, x2)
+
+inst_220:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x7, 1616, x2)
+
+inst_221:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x7, 1624, x2)
+
+inst_222:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x7, 1632, x2)
+
+inst_223:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x7, 1640, x2)
+
+inst_224:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x7, 1648, x2)
+
+inst_225:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x7, 1656, x2)
+
+inst_226:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x7, 1664, x2)
+
+inst_227:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x7, 1672, x2)
+
+inst_228:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x7, 1680, x2)
+
+inst_229:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x7, 1688, x2)
+
+inst_230:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x7, 1696, x2)
+
+inst_231:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x7, 1704, x2)
+
+inst_232:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x7, 1712, x2)
+
+inst_233:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x7, 1720, x2)
+
+inst_234:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x7, 1728, x2)
+
+inst_235:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x7, 1736, x2)
+
+inst_236:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x7, 1744, x2)
+
+inst_237:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x7, 1752, x2)
+
+inst_238:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x7, 1760, x2)
+
+inst_239:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x7, 1768, x2)
+
+inst_240:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x7, 1776, x2)
+
+inst_241:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x7, 1784, x2)
+
+inst_242:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x7, 1792, x2)
+
+inst_243:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x7, 1800, x2)
+
+inst_244:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x7, 1808, x2)
+
+inst_245:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x7, 1816, x2)
+
+inst_246:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x7, 1824, x2)
+
+inst_247:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x7, 1832, x2)
+
+inst_248:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x7, 1840, x2)
+
+inst_249:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x7, 1848, x2)
+
+inst_250:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x7, 1856, x2)
+
+inst_251:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x7, 1864, x2)
+
+inst_252:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x7, 1872, x2)
+
+inst_253:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x7, 1880, x2)
+
+inst_254:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x7, 1888, x2)
+
+inst_255:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x7, 1896, x2)
+
+inst_256:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x7, 1904, x2)
+
+inst_257:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x7, 1912, x2)
+
+inst_258:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x7, 1920, x2)
+
+inst_259:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x7, 1928, x2)
+
+inst_260:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x7, 1936, x2)
+
+inst_261:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x7, 1944, x2)
+
+inst_262:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x7, 1952, x2)
+
+inst_263:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x7, 1960, x2)
+
+inst_264:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x7, 1968, x2)
+
+inst_265:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x7, 1976, x2)
+
+inst_266:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x7, 1984, x2)
+
+inst_267:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x7, 1992, x2)
+
+inst_268:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x7, 2000, x2)
+
+inst_269:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x7, 2008, x2)
+
+inst_270:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x7, 2016, x2)
+
+inst_271:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x7, 2024, x2)
+
+inst_272:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x7, 2032, x2)
+
+inst_273:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x7, 2040, x2)
+RVTEST_SIGBASE( x7,signature_x7_1)
+
+inst_274:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x7, 0, x2)
+
+inst_275:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x7, 8, x2)
+
+inst_276:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x7, 16, x2)
+
+inst_277:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x7, 24, x2)
+
+inst_278:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x7, 32, x2)
+
+inst_279:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x7, 40, x2)
+
+inst_280:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x7, 48, x2)
+
+inst_281:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x7, 56, x2)
+
+inst_282:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x7, 64, x2)
+
+inst_283:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x7, 72, x2)
+
+inst_284:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x7, 80, x2)
+
+inst_285:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x7, 88, x2)
+
+inst_286:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x7, 96, x2)
+
+inst_287:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x7, 104, x2)
+
+inst_288:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x7, 112, x2)
+
+inst_289:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x7, 120, x2)
+
+inst_290:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x7, 128, x2)
+
+inst_291:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x7, 136, x2)
+
+inst_292:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x7, 144, x2)
+
+inst_293:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x7, 152, x2)
+
+inst_294:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x7, 160, x2)
+
+inst_295:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x7, 168, x2)
+
+inst_296:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x7, 176, x2)
+
+inst_297:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x7, 184, x2)
+
+inst_298:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x7, 192, x2)
+
+inst_299:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x7, 200, x2)
+
+inst_300:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x7, 208, x2)
+
+inst_301:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x7, 216, x2)
+
+inst_302:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x7, 224, x2)
+
+inst_303:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x7, 232, x2)
+
+inst_304:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x7, 240, x2)
+
+inst_305:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x7, 248, x2)
+
+inst_306:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x7, 256, x2)
+
+inst_307:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x7, 264, x2)
+
+inst_308:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x7, 272, x2)
+
+inst_309:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x7, 280, x2)
+
+inst_310:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x7, 288, x2)
+
+inst_311:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x7, 296, x2)
+
+inst_312:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x7, 304, x2)
+
+inst_313:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x7, 312, x2)
+
+inst_314:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x7, 320, x2)
+
+inst_315:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x7, 328, x2)
+
+inst_316:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x7, 336, x2)
+
+inst_317:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x7, 344, x2)
+
+inst_318:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x7, 352, x2)
+
+inst_319:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x7, 360, x2)
+
+inst_320:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x7, 368, x2)
+
+inst_321:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x7, 376, x2)
+
+inst_322:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x7, 384, x2)
+
+inst_323:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x7, 392, x2)
+
+inst_324:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x7, 400, x2)
+
+inst_325:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x7, 408, x2)
+
+inst_326:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x7, 416, x2)
+
+inst_327:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x7, 424, x2)
+
+inst_328:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x7, 432, x2)
+
+inst_329:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x7, 440, x2)
+
+inst_330:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x7, 448, x2)
+
+inst_331:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x7, 456, x2)
+
+inst_332:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x7, 464, x2)
+
+inst_333:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x7, 472, x2)
+
+inst_334:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x7, 480, x2)
+
+inst_335:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x7, 488, x2)
+
+inst_336:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x7, 496, x2)
+
+inst_337:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x7, 504, x2)
+
+inst_338:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x7, 512, x2)
+
+inst_339:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x7, 520, x2)
+
+inst_340:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x7, 528, x2)
+
+inst_341:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x7, 536, x2)
+
+inst_342:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x7, 544, x2)
+
+inst_343:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x7, 552, x2)
+
+inst_344:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x7, 560, x2)
+
+inst_345:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x7, 568, x2)
+
+inst_346:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x7, 576, x2)
+
+inst_347:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x7, 584, x2)
+
+inst_348:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x7, 592, x2)
+
+inst_349:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x7, 600, x2)
+
+inst_350:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x7, 608, x2)
+
+inst_351:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x7, 616, x2)
+
+inst_352:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x7, 624, x2)
+
+inst_353:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x7, 632, x2)
+
+inst_354:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x7, 640, x2)
+
+inst_355:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x7, 648, x2)
+
+inst_356:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x7, 656, x2)
+
+inst_357:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x7, 664, x2)
+
+inst_358:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x7, 672, x2)
+
+inst_359:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x7, 680, x2)
+
+inst_360:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x7, 688, x2)
+
+inst_361:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x7, 696, x2)
+
+inst_362:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x7, 704, x2)
+
+inst_363:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x7, 712, x2)
+
+inst_364:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x7, 720, x2)
+
+inst_365:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x7, 728, x2)
+
+inst_366:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x7, 736, x2)
+
+inst_367:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x7, 744, x2)
+
+inst_368:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x7, 752, x2)
+
+inst_369:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x7, 760, x2)
+
+inst_370:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x7, 768, x2)
+
+inst_371:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x7, 776, x2)
+
+inst_372:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x7, 784, x2)
+
+inst_373:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x7, 792, x2)
+
+inst_374:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x7, 800, x2)
+
+inst_375:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x7, 808, x2)
+
+inst_376:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x7, 816, x2)
+
+inst_377:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x7, 824, x2)
+
+inst_378:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x7, 832, x2)
+
+inst_379:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x7, 840, x2)
+
+inst_380:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x7, 848, x2)
+
+inst_381:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x7, 856, x2)
+
+inst_382:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x7, 864, x2)
+
+inst_383:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x7, 872, x2)
+
+inst_384:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x7, 880, x2)
+
+inst_385:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x7, 888, x2)
+
+inst_386:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x7, 896, x2)
+
+inst_387:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x7, 904, x2)
+
+inst_388:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x7, 912, x2)
+
+inst_389:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x7, 920, x2)
+
+inst_390:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x7, 928, x2)
+
+inst_391:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x7, 936, x2)
+
+inst_392:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x7, 944, x2)
+
+inst_393:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x7, 952, x2)
+
+inst_394:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x7, 960, x2)
+
+inst_395:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x7, 968, x2)
+
+inst_396:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x7, 976, x2)
+
+inst_397:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x7, 984, x2)
+
+inst_398:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x7, 992, x2)
+
+inst_399:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x7, 1000, x2)
+
+inst_400:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x7, 1008, x2)
+
+inst_401:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x7, 1016, x2)
+
+inst_402:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x7, 1024, x2)
+
+inst_403:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x7, 1032, x2)
+
+inst_404:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x7, 1040, x2)
+
+inst_405:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x7, 1048, x2)
+
+inst_406:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x7, 1056, x2)
+
+inst_407:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x7, 1064, x2)
+
+inst_408:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x7, 1072, x2)
+
+inst_409:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x7, 1080, x2)
+
+inst_410:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x7, 1088, x2)
+
+inst_411:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x7, 1096, x2)
+
+inst_412:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x7, 1104, x2)
+
+inst_413:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x7, 1112, x2)
+
+inst_414:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x7, 1120, x2)
+
+inst_415:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x7, 1128, x2)
+
+inst_416:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x7, 1136, x2)
+
+inst_417:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x7, 1144, x2)
+
+inst_418:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x7, 1152, x2)
+
+inst_419:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x7, 1160, x2)
+
+inst_420:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x7, 1168, x2)
+
+inst_421:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x7, 1176, x2)
+
+inst_422:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x7, 1184, x2)
+
+inst_423:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x7, 1192, x2)
+
+inst_424:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x7, 1200, x2)
+
+inst_425:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x7, 1208, x2)
+
+inst_426:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x7, 1216, x2)
+
+inst_427:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x7, 1224, x2)
+
+inst_428:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x7, 1232, x2)
+
+inst_429:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x7, 1240, x2)
+
+inst_430:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x7, 1248, x2)
+
+inst_431:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x7, 1256, x2)
+
+inst_432:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x7, 1264, x2)
+
+inst_433:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x7, 1272, x2)
+
+inst_434:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x7, 1280, x2)
+
+inst_435:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x7, 1288, x2)
+
+inst_436:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x7, 1296, x2)
+
+inst_437:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x7, 1304, x2)
+
+inst_438:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x7, 1312, x2)
+
+inst_439:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x7, 1320, x2)
+
+inst_440:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x7, 1328, x2)
+
+inst_441:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x7, 1336, x2)
+
+inst_442:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x7, 1344, x2)
+
+inst_443:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x7, 1352, x2)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x7, 1360, x2)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x7, 1368, x2)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x7, 1376, x2)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x7, 1384, x2)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x7, 1392, x2)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x7, 1400, x2)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x7, 1408, x2)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x7, 1416, x2)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x7, 1424, x2)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x7, 1432, x2)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x7, 1440, x2)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x7, 1448, x2)
+
+inst_456:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x7, 1456, x2)
+
+inst_457:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x7, 1464, x2)
+
+inst_458:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x7, 1472, x2)
+
+inst_459:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x7, 1480, x2)
+
+inst_460:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x7, 1488, x2)
+
+inst_461:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x7, 1496, x2)
+
+inst_462:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x7, 1504, x2)
+
+inst_463:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x7, 1512, x2)
+
+inst_464:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x7, 1520, x2)
+
+inst_465:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x7, 1528, x2)
+
+inst_466:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x7, 1536, x2)
+
+inst_467:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x7, 1544, x2)
+
+inst_468:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x7, 1552, x2)
+
+inst_469:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x7, 1560, x2)
+
+inst_470:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x7, 1568, x2)
+
+inst_471:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x7, 1576, x2)
+
+inst_472:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x7, 1584, x2)
+
+inst_473:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x7, 1592, x2)
+
+inst_474:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x7, 1600, x2)
+
+inst_475:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x7, 1608, x2)
+
+inst_476:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x7, 1616, x2)
+
+inst_477:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x7, 1624, x2)
+
+inst_478:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x7, 1632, x2)
+
+inst_479:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x7, 1640, x2)
+
+inst_480:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x7, 1648, x2)
+
+inst_481:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x7, 1656, x2)
+
+inst_482:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x7, 1664, x2)
+
+inst_483:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x7, 1672, x2)
+
+inst_484:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x7, 1680, x2)
+
+inst_485:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x7, 1688, x2)
+
+inst_486:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x7, 1696, x2)
+
+inst_487:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x7, 1704, x2)
+
+inst_488:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x7, 1712, x2)
+
+inst_489:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x7, 1720, x2)
+
+inst_490:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x7, 1728, x2)
+
+inst_491:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x7, 1736, x2)
+
+inst_492:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x7, 1744, x2)
+
+inst_493:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x7, 1752, x2)
+
+inst_494:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x7, 1760, x2)
+
+inst_495:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x7, 1768, x2)
+
+inst_496:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x7, 1776, x2)
+
+inst_497:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x7, 1784, x2)
+
+inst_498:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x7, 1792, x2)
+
+inst_499:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x7, 1800, x2)
+
+inst_500:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x7, 1808, x2)
+
+inst_501:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x7, 1816, x2)
+
+inst_502:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x7, 1824, x2)
+
+inst_503:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x7, 1832, x2)
+
+inst_504:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x7, 1840, x2)
+
+inst_505:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x7, 1848, x2)
+
+inst_506:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x7, 1856, x2)
+
+inst_507:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x7, 1864, x2)
+
+inst_508:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x7, 1872, x2)
+
+inst_509:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x7, 1880, x2)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x7, 1888, x2)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x7, 1896, x2)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x7, 1904, x2)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x7, 1912, x2)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x7, 1920, x2)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x7, 1928, x2)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x7, 1936, x2)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x7, 1944, x2)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x7, 1952, x2)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x7, 1960, x2)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x7, 1968, x2)
+
+inst_521:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x7, 1976, x2)
+
+inst_522:
+// rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x7, 1984, x2)
+
+inst_523:
+// rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x7, 1992, x2)
+
+inst_524:
+// rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: xnor ; op1:x10; op2:x11; dest:x12; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(xnor, x12, x10, x11, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x7, 2000, x2)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x12_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x12_1:
+    .fill 18*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x7_1:
+    .fill 251*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S
new file mode 100644
index 000000000..5f1f7e668
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.b-01.S
@@ -0,0 +1,2816 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 27 16:46:33 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the xperm.b instruction of the RISC-V  extension for the xperm.b covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",xperm.b)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",xperm.b)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",xperm.b)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",xperm.b)
+
+RVTEST_SIGBASE( x6,signature_x6_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x9, rs2==x4, rd==x25, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: xperm.b ; op1:x9; op2:x4; dest:x25; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(xperm.b, x25, x9, x4, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x6, 0, x10)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x22, rs2==x22, rd==x22, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: xperm.b ; op1:x22; op2:x22; dest:x22; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(xperm.b, x22, x22, x22, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x6, 8, x10)
+
+inst_2:
+// rs1 == rd != rs2, rs1==x24, rs2==x9, rd==x24, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: xperm.b ; op1:x24; op2:x9; dest:x24; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(xperm.b, x24, x24, x9, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x6, 16, x10)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x18, rs2==x18, rd==x17, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: xperm.b ; op1:x18; op2:x18; dest:x17; op1val:0x1f7d946f17168ab3;  op2val:0x1f7d946f17168ab3
+TEST_RR_OP(xperm.b, x17, x18, x18, 0x0000000000000000, 0x1f7d946f17168ab3, 0x1f7d946f17168ab3, x6, 24, x10)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x8, rs2==x28, rd==x28, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: xperm.b ; op1:x8; op2:x28; dest:x28; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(xperm.b, x28, x8, x28, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x6, 32, x10)
+
+inst_5:
+// rs1==x15, rs2==x3, rd==x29, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: xperm.b ; op1:x15; op2:x3; dest:x29; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(xperm.b, x29, x15, x3, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x6, 40, x10)
+
+inst_6:
+// rs1==x14, rs2==x19, rd==x2, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: xperm.b ; op1:x14; op2:x19; dest:x2; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(xperm.b, x2, x14, x19, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x6, 48, x10)
+
+inst_7:
+// rs1==x30, rs2==x27, rd==x26, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: xperm.b ; op1:x30; op2:x27; dest:x26; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(xperm.b, x26, x30, x27, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x6, 56, x10)
+
+inst_8:
+// rs1==x17, rs2==x24, rd==x30, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: xperm.b ; op1:x17; op2:x24; dest:x30; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(xperm.b, x30, x17, x24, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x6, 64, x10)
+
+inst_9:
+// rs1==x27, rs2==x14, rd==x5, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: xperm.b ; op1:x27; op2:x14; dest:x5; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(xperm.b, x5, x27, x14, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x6, 72, x10)
+
+inst_10:
+// rs1==x20, rs2==x0, rd==x9, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: xperm.b ; op1:x20; op2:x0; dest:x9; op1val:0x4113ee60952acffe;  op2val:0x0
+TEST_RR_OP(xperm.b, x9, x20, x0, 0x0000000000000000, 0x4113ee60952acffe, 0x0, x6, 80, x10)
+
+inst_11:
+// rs1==x5, rs2==x20, rd==x11, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: xperm.b ; op1:x5; op2:x20; dest:x11; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(xperm.b, x11, x5, x20, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x6, 88, x10)
+
+inst_12:
+// rs1==x0, rs2==x21, rd==x31, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: xperm.b ; op1:x0; op2:x21; dest:x31; op1val:0x0;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(xperm.b, x31, x0, x21, 0x0000000000000000, 0x0, 0xd05668ae0fdb82bc, x6, 96, x10)
+
+inst_13:
+// rs1==x7, rs2==x13, rd==x1, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: xperm.b ; op1:x7; op2:x13; dest:x1; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(xperm.b, x1, x7, x13, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x6, 104, x10)
+
+inst_14:
+// rs1==x29, rs2==x5, rd==x12, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: xperm.b ; op1:x29; op2:x5; dest:x12; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(xperm.b, x12, x29, x5, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x6, 112, x10)
+
+inst_15:
+// rs1==x25, rs2==x26, rd==x21, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: xperm.b ; op1:x25; op2:x26; dest:x21; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(xperm.b, x21, x25, x26, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x6, 120, x5)
+
+inst_16:
+// rs1==x13, rs2==x11, rd==x19, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: xperm.b ; op1:x13; op2:x11; dest:x19; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(xperm.b, x19, x13, x11, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x6, 128, x5)
+
+inst_17:
+// rs1==x19, rs2==x17, rd==x15, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: xperm.b ; op1:x19; op2:x17; dest:x15; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(xperm.b, x15, x19, x17, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x6, 136, x5)
+
+inst_18:
+// rs1==x31, rs2==x1, rd==x18, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: xperm.b ; op1:x31; op2:x1; dest:x18; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(xperm.b, x18, x31, x1, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x6, 144, x5)
+
+inst_19:
+// rs1==x12, rs2==x31, rd==x4, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: xperm.b ; op1:x12; op2:x31; dest:x4; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(xperm.b, x4, x12, x31, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x6, 152, x5)
+
+inst_20:
+// rs1==x2, rs2==x29, rd==x7, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: xperm.b ; op1:x2; op2:x29; dest:x7; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(xperm.b, x7, x2, x29, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x6, 160, x5)
+
+inst_21:
+// rs1==x4, rs2==x25, rd==x16, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: xperm.b ; op1:x4; op2:x25; dest:x16; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(xperm.b, x16, x4, x25, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x6, 168, x5)
+RVTEST_SIGBASE( x4,signature_x4_0)
+
+inst_22:
+// rs1==x11, rs2==x23, rd==x27, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: xperm.b ; op1:x11; op2:x23; dest:x27; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(xperm.b, x27, x11, x23, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x4, 0, x5)
+
+inst_23:
+// rs1==x10, rs2==x30, rd==x3, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: xperm.b ; op1:x10; op2:x30; dest:x3; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(xperm.b, x3, x10, x30, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x4, 8, x5)
+
+inst_24:
+// rs1==x3, rs2==x6, rd==x8, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: xperm.b ; op1:x3; op2:x6; dest:x8; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(xperm.b, x8, x3, x6, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x4, 16, x5)
+
+inst_25:
+// rs1==x26, rs2==x2, rd==x13, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: xperm.b ; op1:x26; op2:x2; dest:x13; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(xperm.b, x13, x26, x2, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x4, 24, x5)
+
+inst_26:
+// rs1==x1, rs2==x16, rd==x20, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: xperm.b ; op1:x1; op2:x16; dest:x20; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(xperm.b, x20, x1, x16, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x4, 32, x5)
+
+inst_27:
+// rs1==x23, rs2==x8, rd==x6, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: xperm.b ; op1:x23; op2:x8; dest:x6; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(xperm.b, x6, x23, x8, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x4, 40, x5)
+
+inst_28:
+// rs1==x6, rs2==x7, rd==x10, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: xperm.b ; op1:x6; op2:x7; dest:x10; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(xperm.b, x10, x6, x7, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x4, 48, x5)
+
+inst_29:
+// rs1==x16, rs2==x12, rd==x0, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: xperm.b ; op1:x16; op2:x12; dest:x0; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(xperm.b, x0, x16, x12, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x4, 56, x5)
+
+inst_30:
+// rs1==x28, rs2==x15, rd==x14, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: xperm.b ; op1:x28; op2:x15; dest:x14; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(xperm.b, x14, x28, x15, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x4, 64, x5)
+
+inst_31:
+// rs1==x21, rs2==x10, rd==x23, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: xperm.b ; op1:x21; op2:x10; dest:x23; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(xperm.b, x23, x21, x10, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x4, 72, x5)
+
+inst_32:
+// rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x4, 80, x5)
+
+inst_33:
+// rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x4, 88, x5)
+
+inst_34:
+// rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x4, 96, x5)
+
+inst_35:
+// rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x4, 104, x5)
+
+inst_36:
+// rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x4, 112, x5)
+
+inst_37:
+// rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x4, 120, x5)
+
+inst_38:
+// rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x4, 128, x5)
+
+inst_39:
+// rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x4, 136, x5)
+
+inst_40:
+// rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x4, 144, x5)
+
+inst_41:
+// rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x4, 152, x5)
+
+inst_42:
+// rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x4, 160, x5)
+
+inst_43:
+// rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x4, 168, x5)
+
+inst_44:
+// rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x4, 176, x5)
+
+inst_45:
+// rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x4, 184, x5)
+
+inst_46:
+// rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x4, 192, x5)
+
+inst_47:
+// rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x4, 200, x5)
+
+inst_48:
+// rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x4, 208, x5)
+
+inst_49:
+// rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x4, 216, x5)
+
+inst_50:
+// rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x4, 224, x5)
+
+inst_51:
+// rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x4, 232, x5)
+
+inst_52:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x4, 240, x5)
+
+inst_53:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x4, 248, x5)
+
+inst_54:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x4, 256, x5)
+
+inst_55:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x4, 264, x5)
+
+inst_56:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x4, 272, x5)
+
+inst_57:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x4, 280, x5)
+
+inst_58:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x4, 288, x5)
+
+inst_59:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x4, 296, x5)
+
+inst_60:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x4, 304, x5)
+
+inst_61:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x4, 312, x5)
+
+inst_62:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x4, 320, x5)
+
+inst_63:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x4, 328, x5)
+
+inst_64:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x4, 336, x5)
+
+inst_65:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x4, 344, x5)
+
+inst_66:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x4, 352, x5)
+
+inst_67:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x4, 360, x5)
+
+inst_68:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x4, 368, x5)
+
+inst_69:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x4, 376, x5)
+
+inst_70:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x4, 384, x5)
+
+inst_71:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x4, 392, x5)
+
+inst_72:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x4, 400, x5)
+
+inst_73:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x4, 408, x5)
+
+inst_74:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x4, 416, x5)
+
+inst_75:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x4, 424, x5)
+
+inst_76:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x4, 432, x5)
+
+inst_77:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x4, 440, x5)
+
+inst_78:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x4, 448, x5)
+
+inst_79:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x4, 456, x5)
+
+inst_80:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x4, 464, x5)
+
+inst_81:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x4, 472, x5)
+
+inst_82:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x4, 480, x5)
+
+inst_83:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x4, 488, x5)
+
+inst_84:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x4, 496, x5)
+
+inst_85:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x4, 504, x5)
+
+inst_86:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x4, 512, x5)
+
+inst_87:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x4, 520, x5)
+
+inst_88:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x4, 528, x5)
+
+inst_89:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x4, 536, x5)
+
+inst_90:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x4, 544, x5)
+
+inst_91:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x4, 552, x5)
+
+inst_92:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x4, 560, x5)
+
+inst_93:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x4, 568, x5)
+
+inst_94:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x4, 576, x5)
+
+inst_95:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x4, 584, x5)
+
+inst_96:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x4, 592, x5)
+
+inst_97:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x4, 600, x5)
+
+inst_98:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x4, 608, x5)
+
+inst_99:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x4, 616, x5)
+
+inst_100:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x4, 624, x5)
+
+inst_101:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x4, 632, x5)
+
+inst_102:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x4, 640, x5)
+
+inst_103:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x4, 648, x5)
+
+inst_104:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x4, 656, x5)
+
+inst_105:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x4, 664, x5)
+
+inst_106:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x4, 672, x5)
+
+inst_107:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x4, 680, x5)
+
+inst_108:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x4, 688, x5)
+
+inst_109:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x4, 696, x5)
+
+inst_110:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x4, 704, x5)
+
+inst_111:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x4, 712, x5)
+
+inst_112:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x4, 720, x5)
+
+inst_113:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x4, 728, x5)
+
+inst_114:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x4, 736, x5)
+
+inst_115:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x4, 744, x5)
+
+inst_116:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x4, 752, x5)
+
+inst_117:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x4, 760, x5)
+
+inst_118:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x4, 768, x5)
+
+inst_119:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x4, 776, x5)
+
+inst_120:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x4, 784, x5)
+
+inst_121:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x4, 792, x5)
+
+inst_122:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x4, 800, x5)
+
+inst_123:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x4, 808, x5)
+
+inst_124:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x4, 816, x5)
+
+inst_125:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x4, 824, x5)
+
+inst_126:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x4, 832, x5)
+
+inst_127:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x4, 840, x5)
+
+inst_128:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x4, 848, x5)
+
+inst_129:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x4, 856, x5)
+
+inst_130:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x4, 864, x5)
+
+inst_131:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x4, 872, x5)
+
+inst_132:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x4, 880, x5)
+
+inst_133:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x4, 888, x5)
+
+inst_134:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x4, 896, x5)
+
+inst_135:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x4, 904, x5)
+
+inst_136:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x4, 912, x5)
+
+inst_137:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x4, 920, x5)
+
+inst_138:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x4, 928, x5)
+
+inst_139:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x4, 936, x5)
+
+inst_140:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x4, 944, x5)
+
+inst_141:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x4, 952, x5)
+
+inst_142:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x4, 960, x5)
+
+inst_143:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x4, 968, x5)
+
+inst_144:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x4, 976, x5)
+
+inst_145:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x4, 984, x5)
+
+inst_146:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x4, 992, x5)
+
+inst_147:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x4, 1000, x5)
+
+inst_148:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x4, 1008, x5)
+
+inst_149:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x4, 1016, x5)
+
+inst_150:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x4, 1024, x5)
+
+inst_151:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x4, 1032, x5)
+
+inst_152:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x4, 1040, x5)
+
+inst_153:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x4, 1048, x5)
+
+inst_154:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x4, 1056, x5)
+
+inst_155:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x4, 1064, x5)
+
+inst_156:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x4, 1072, x5)
+
+inst_157:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x4, 1080, x5)
+
+inst_158:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x4, 1088, x5)
+
+inst_159:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x4, 1096, x5)
+
+inst_160:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x4, 1104, x5)
+
+inst_161:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x4, 1112, x5)
+
+inst_162:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x4, 1120, x5)
+
+inst_163:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x4, 1128, x5)
+
+inst_164:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x4, 1136, x5)
+
+inst_165:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x4, 1144, x5)
+
+inst_166:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x4, 1152, x5)
+
+inst_167:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x4, 1160, x5)
+
+inst_168:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x4, 1168, x5)
+
+inst_169:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x4, 1176, x5)
+
+inst_170:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x4, 1184, x5)
+
+inst_171:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x4, 1192, x5)
+
+inst_172:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x4, 1200, x5)
+
+inst_173:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x4, 1208, x5)
+
+inst_174:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x4, 1216, x5)
+
+inst_175:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x4, 1224, x5)
+
+inst_176:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x4, 1232, x5)
+
+inst_177:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x4, 1240, x5)
+
+inst_178:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x4, 1248, x5)
+
+inst_179:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x4, 1256, x5)
+
+inst_180:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x4, 1264, x5)
+
+inst_181:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x4, 1272, x5)
+
+inst_182:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x4, 1280, x5)
+
+inst_183:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x4, 1288, x5)
+
+inst_184:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x4, 1296, x5)
+
+inst_185:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x4, 1304, x5)
+
+inst_186:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x4, 1312, x5)
+
+inst_187:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x4, 1320, x5)
+
+inst_188:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x4, 1328, x5)
+
+inst_189:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x4, 1336, x5)
+
+inst_190:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x4, 1344, x5)
+
+inst_191:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x4, 1352, x5)
+
+inst_192:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x4, 1360, x5)
+
+inst_193:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x4, 1368, x5)
+
+inst_194:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x4, 1376, x5)
+
+inst_195:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x4, 1384, x5)
+
+inst_196:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x4, 1392, x5)
+
+inst_197:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x4, 1400, x5)
+
+inst_198:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x4, 1408, x5)
+
+inst_199:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x4, 1416, x5)
+
+inst_200:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x4, 1424, x5)
+
+inst_201:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x4, 1432, x5)
+
+inst_202:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x4, 1440, x5)
+
+inst_203:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x4, 1448, x5)
+
+inst_204:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x4, 1456, x5)
+
+inst_205:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x4, 1464, x5)
+
+inst_206:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x4, 1472, x5)
+
+inst_207:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x4, 1480, x5)
+
+inst_208:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x4, 1488, x5)
+
+inst_209:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x4, 1496, x5)
+
+inst_210:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x4, 1504, x5)
+
+inst_211:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x4, 1512, x5)
+
+inst_212:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x4, 1520, x5)
+
+inst_213:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x4, 1528, x5)
+
+inst_214:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x4, 1536, x5)
+
+inst_215:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x4, 1544, x5)
+
+inst_216:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x4, 1552, x5)
+
+inst_217:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x4, 1560, x5)
+
+inst_218:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x4, 1568, x5)
+
+inst_219:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x4, 1576, x5)
+
+inst_220:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x4, 1584, x5)
+
+inst_221:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x4, 1592, x5)
+
+inst_222:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x4, 1600, x5)
+
+inst_223:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x4, 1608, x5)
+
+inst_224:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x4, 1616, x5)
+
+inst_225:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x4, 1624, x5)
+
+inst_226:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x4, 1632, x5)
+
+inst_227:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x4, 1640, x5)
+
+inst_228:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x4, 1648, x5)
+
+inst_229:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x4, 1656, x5)
+
+inst_230:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x4, 1664, x5)
+
+inst_231:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x4, 1672, x5)
+
+inst_232:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x4, 1680, x5)
+
+inst_233:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x4, 1688, x5)
+
+inst_234:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x4, 1696, x5)
+
+inst_235:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x4, 1704, x5)
+
+inst_236:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x4, 1712, x5)
+
+inst_237:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x4, 1720, x5)
+
+inst_238:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x4, 1728, x5)
+
+inst_239:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x4, 1736, x5)
+
+inst_240:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x4, 1744, x5)
+
+inst_241:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x4, 1752, x5)
+
+inst_242:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x4, 1760, x5)
+
+inst_243:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x4, 1768, x5)
+
+inst_244:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x4, 1776, x5)
+
+inst_245:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x4, 1784, x5)
+
+inst_246:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x4, 1792, x5)
+
+inst_247:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x4, 1800, x5)
+
+inst_248:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x4, 1808, x5)
+
+inst_249:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x4, 1816, x5)
+
+inst_250:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x4, 1824, x5)
+
+inst_251:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x4, 1832, x5)
+
+inst_252:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x4, 1840, x5)
+
+inst_253:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x4, 1848, x5)
+
+inst_254:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x4, 1856, x5)
+
+inst_255:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x4, 1864, x5)
+
+inst_256:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x4, 1872, x5)
+
+inst_257:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x4, 1880, x5)
+
+inst_258:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x4, 1888, x5)
+
+inst_259:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x4, 1896, x5)
+
+inst_260:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x4, 1904, x5)
+
+inst_261:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x4, 1912, x5)
+
+inst_262:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x4, 1920, x5)
+
+inst_263:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x4, 1928, x5)
+
+inst_264:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x4, 1936, x5)
+
+inst_265:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x4, 1944, x5)
+
+inst_266:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x4, 1952, x5)
+
+inst_267:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x4, 1960, x5)
+
+inst_268:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x4, 1968, x5)
+
+inst_269:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x4, 1976, x5)
+
+inst_270:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x4, 1984, x5)
+
+inst_271:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x4, 1992, x5)
+
+inst_272:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x4, 2000, x5)
+
+inst_273:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x4, 2008, x5)
+
+inst_274:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x4, 2016, x5)
+
+inst_275:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x4, 2024, x5)
+
+inst_276:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x4, 2032, x5)
+
+inst_277:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x4, 2040, x5)
+RVTEST_SIGBASE( x4,signature_x4_1)
+
+inst_278:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x4, 0, x5)
+
+inst_279:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x4, 8, x5)
+
+inst_280:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x4, 16, x5)
+
+inst_281:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x4, 24, x5)
+
+inst_282:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x4, 32, x5)
+
+inst_283:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x4, 40, x5)
+
+inst_284:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x4, 48, x5)
+
+inst_285:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x4, 56, x5)
+
+inst_286:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x4, 64, x5)
+
+inst_287:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x4, 72, x5)
+
+inst_288:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x4, 80, x5)
+
+inst_289:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x4, 88, x5)
+
+inst_290:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x4, 96, x5)
+
+inst_291:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x4, 104, x5)
+
+inst_292:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x4, 112, x5)
+
+inst_293:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x4, 120, x5)
+
+inst_294:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x4, 128, x5)
+
+inst_295:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x4, 136, x5)
+
+inst_296:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x4, 144, x5)
+
+inst_297:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x4, 152, x5)
+
+inst_298:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x4, 160, x5)
+
+inst_299:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x4, 168, x5)
+
+inst_300:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x4, 176, x5)
+
+inst_301:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x4, 184, x5)
+
+inst_302:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x4, 192, x5)
+
+inst_303:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x4, 200, x5)
+
+inst_304:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x4, 208, x5)
+
+inst_305:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x4, 216, x5)
+
+inst_306:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x4, 224, x5)
+
+inst_307:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x4, 232, x5)
+
+inst_308:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x4, 240, x5)
+
+inst_309:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x4, 248, x5)
+
+inst_310:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x4, 256, x5)
+
+inst_311:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x4, 264, x5)
+
+inst_312:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x4, 272, x5)
+
+inst_313:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x4, 280, x5)
+
+inst_314:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x4, 288, x5)
+
+inst_315:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x4, 296, x5)
+
+inst_316:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x4, 304, x5)
+
+inst_317:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x4, 312, x5)
+
+inst_318:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x4, 320, x5)
+
+inst_319:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x4, 328, x5)
+
+inst_320:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x4, 336, x5)
+
+inst_321:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x4, 344, x5)
+
+inst_322:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x4, 352, x5)
+
+inst_323:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x4, 360, x5)
+
+inst_324:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x4, 368, x5)
+
+inst_325:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x4, 376, x5)
+
+inst_326:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x4, 384, x5)
+
+inst_327:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x4, 392, x5)
+
+inst_328:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x4, 400, x5)
+
+inst_329:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x4, 408, x5)
+
+inst_330:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x4, 416, x5)
+
+inst_331:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x4, 424, x5)
+
+inst_332:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x4, 432, x5)
+
+inst_333:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x4, 440, x5)
+
+inst_334:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x4, 448, x5)
+
+inst_335:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x4, 456, x5)
+
+inst_336:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x4, 464, x5)
+
+inst_337:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x4, 472, x5)
+
+inst_338:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x4, 480, x5)
+
+inst_339:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x4, 488, x5)
+
+inst_340:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x4, 496, x5)
+
+inst_341:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x4, 504, x5)
+
+inst_342:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x4, 512, x5)
+
+inst_343:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x4, 520, x5)
+
+inst_344:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x4, 528, x5)
+
+inst_345:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x4, 536, x5)
+
+inst_346:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x4, 544, x5)
+
+inst_347:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x4, 552, x5)
+
+inst_348:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x4, 560, x5)
+
+inst_349:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x4, 568, x5)
+
+inst_350:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x4, 576, x5)
+
+inst_351:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x4, 584, x5)
+
+inst_352:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x4, 592, x5)
+
+inst_353:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x4, 600, x5)
+
+inst_354:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x4, 608, x5)
+
+inst_355:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x4, 616, x5)
+
+inst_356:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x4, 624, x5)
+
+inst_357:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x4, 632, x5)
+
+inst_358:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x4, 640, x5)
+
+inst_359:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x4, 648, x5)
+
+inst_360:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x4, 656, x5)
+
+inst_361:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x4, 664, x5)
+
+inst_362:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x4, 672, x5)
+
+inst_363:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x4, 680, x5)
+
+inst_364:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x4, 688, x5)
+
+inst_365:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x4, 696, x5)
+
+inst_366:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x4, 704, x5)
+
+inst_367:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x4, 712, x5)
+
+inst_368:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x4, 720, x5)
+
+inst_369:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x4, 728, x5)
+
+inst_370:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x4, 736, x5)
+
+inst_371:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x4, 744, x5)
+
+inst_372:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x4, 752, x5)
+
+inst_373:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x4, 760, x5)
+
+inst_374:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x4, 768, x5)
+
+inst_375:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x4, 776, x5)
+
+inst_376:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x4, 784, x5)
+
+inst_377:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x4, 792, x5)
+
+inst_378:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x4, 800, x5)
+
+inst_379:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x4, 808, x5)
+
+inst_380:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x4, 816, x5)
+
+inst_381:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x4, 824, x5)
+
+inst_382:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x4, 832, x5)
+
+inst_383:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x4, 840, x5)
+
+inst_384:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x4, 848, x5)
+
+inst_385:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x4, 856, x5)
+
+inst_386:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x4, 864, x5)
+
+inst_387:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x4, 872, x5)
+
+inst_388:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x4, 880, x5)
+
+inst_389:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x4, 888, x5)
+
+inst_390:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x4, 896, x5)
+
+inst_391:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x4, 904, x5)
+
+inst_392:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x4, 912, x5)
+
+inst_393:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x4, 920, x5)
+
+inst_394:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x4, 928, x5)
+
+inst_395:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x4, 936, x5)
+
+inst_396:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x4, 944, x5)
+
+inst_397:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x4, 952, x5)
+
+inst_398:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x4, 960, x5)
+
+inst_399:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x4, 968, x5)
+
+inst_400:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x4, 976, x5)
+
+inst_401:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x4, 984, x5)
+
+inst_402:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x4, 992, x5)
+
+inst_403:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x4, 1000, x5)
+
+inst_404:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x4, 1008, x5)
+
+inst_405:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x4, 1016, x5)
+
+inst_406:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x4, 1024, x5)
+
+inst_407:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x4, 1032, x5)
+
+inst_408:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x4, 1040, x5)
+
+inst_409:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x4, 1048, x5)
+
+inst_410:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x4, 1056, x5)
+
+inst_411:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x4, 1064, x5)
+
+inst_412:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x4, 1072, x5)
+
+inst_413:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x4, 1080, x5)
+
+inst_414:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x4, 1088, x5)
+
+inst_415:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x4, 1096, x5)
+
+inst_416:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x4, 1104, x5)
+
+inst_417:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x4, 1112, x5)
+
+inst_418:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x4, 1120, x5)
+
+inst_419:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x4, 1128, x5)
+
+inst_420:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x4, 1136, x5)
+
+inst_421:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x4, 1144, x5)
+
+inst_422:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x4, 1152, x5)
+
+inst_423:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x4, 1160, x5)
+
+inst_424:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x4, 1168, x5)
+
+inst_425:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x4, 1176, x5)
+
+inst_426:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x4, 1184, x5)
+
+inst_427:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x4, 1192, x5)
+
+inst_428:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x4, 1200, x5)
+
+inst_429:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x4, 1208, x5)
+
+inst_430:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x4, 1216, x5)
+
+inst_431:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x4, 1224, x5)
+
+inst_432:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x4, 1232, x5)
+
+inst_433:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x4, 1240, x5)
+
+inst_434:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x4, 1248, x5)
+
+inst_435:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x4, 1256, x5)
+
+inst_436:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x4, 1264, x5)
+
+inst_437:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x4, 1272, x5)
+
+inst_438:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x4, 1280, x5)
+
+inst_439:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x4, 1288, x5)
+
+inst_440:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x4, 1296, x5)
+
+inst_441:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x4, 1304, x5)
+
+inst_442:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x4, 1312, x5)
+
+inst_443:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x4, 1320, x5)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x4, 1328, x5)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x4, 1336, x5)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x4, 1344, x5)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x4, 1352, x5)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x4, 1360, x5)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x4, 1368, x5)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x4, 1376, x5)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x4, 1384, x5)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x4, 1392, x5)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x4, 1400, x5)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x4, 1408, x5)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x4, 1416, x5)
+
+inst_456:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x4, 1424, x5)
+
+inst_457:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x4, 1432, x5)
+
+inst_458:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x4, 1440, x5)
+
+inst_459:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x4, 1448, x5)
+
+inst_460:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x4, 1456, x5)
+
+inst_461:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x4, 1464, x5)
+
+inst_462:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x4, 1472, x5)
+
+inst_463:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x4, 1480, x5)
+
+inst_464:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x4, 1488, x5)
+
+inst_465:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x4, 1496, x5)
+
+inst_466:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x4, 1504, x5)
+
+inst_467:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x4, 1512, x5)
+
+inst_468:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x4, 1520, x5)
+
+inst_469:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x4, 1528, x5)
+
+inst_470:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x4, 1536, x5)
+
+inst_471:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x4, 1544, x5)
+
+inst_472:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x4, 1552, x5)
+
+inst_473:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x4, 1560, x5)
+
+inst_474:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x4, 1568, x5)
+
+inst_475:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x4, 1576, x5)
+
+inst_476:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x4, 1584, x5)
+
+inst_477:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x4, 1592, x5)
+
+inst_478:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x4, 1600, x5)
+
+inst_479:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x4, 1608, x5)
+
+inst_480:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x4, 1616, x5)
+
+inst_481:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x4, 1624, x5)
+
+inst_482:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x4, 1632, x5)
+
+inst_483:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x4, 1640, x5)
+
+inst_484:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x4, 1648, x5)
+
+inst_485:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x4, 1656, x5)
+
+inst_486:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x4, 1664, x5)
+
+inst_487:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x4, 1672, x5)
+
+inst_488:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x4, 1680, x5)
+
+inst_489:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x4, 1688, x5)
+
+inst_490:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x4, 1696, x5)
+
+inst_491:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x4, 1704, x5)
+
+inst_492:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x4, 1712, x5)
+
+inst_493:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x4, 1720, x5)
+
+inst_494:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x4, 1728, x5)
+
+inst_495:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x4, 1736, x5)
+
+inst_496:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x4, 1744, x5)
+
+inst_497:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x4, 1752, x5)
+
+inst_498:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x4, 1760, x5)
+
+inst_499:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x4, 1768, x5)
+
+inst_500:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x4, 1776, x5)
+
+inst_501:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x4, 1784, x5)
+
+inst_502:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x4, 1792, x5)
+
+inst_503:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x4, 1800, x5)
+
+inst_504:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x4, 1808, x5)
+
+inst_505:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x4, 1816, x5)
+
+inst_506:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x4, 1824, x5)
+
+inst_507:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x4, 1832, x5)
+
+inst_508:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x4, 1840, x5)
+
+inst_509:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x4, 1848, x5)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x4, 1856, x5)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x4, 1864, x5)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x4, 1872, x5)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x4, 1880, x5)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x4, 1888, x5)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x4, 1896, x5)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x4, 1904, x5)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x4, 1912, x5)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x4, 1920, x5)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x4, 1928, x5)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x4, 1936, x5)
+
+inst_521:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x4, 1944, x5)
+
+inst_522:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x4, 1952, x5)
+
+inst_523:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x4, 1960, x5)
+
+inst_524:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x4, 1968, x5)
+
+inst_525:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x4, 1976, x5)
+
+inst_526:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x4, 1984, x5)
+
+inst_527:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x4, 1992, x5)
+
+inst_528:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x4, 2000, x5)
+
+inst_529:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x4, 2008, x5)
+
+inst_530:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x4, 2016, x5)
+
+inst_531:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x4, 2024, x5)
+
+inst_532:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x4, 2032, x5)
+
+inst_533:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x4, 2040, x5)
+RVTEST_SIGBASE( x4,signature_x4_2)
+
+inst_534:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x4, 0, x5)
+
+inst_535:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x4, 8, x5)
+
+inst_536:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x4, 16, x5)
+
+inst_537:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x4, 24, x5)
+
+inst_538:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x4, 32, x5)
+
+inst_539:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x4, 40, x5)
+
+inst_540:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x4, 48, x5)
+
+inst_541:
+// rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x4, 56, x5)
+
+inst_542:
+// rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x4, 64, x5)
+
+inst_543:
+// rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x4, 72, x5)
+
+inst_544:
+// rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: xperm.b ; op1:x10; op2:x11; dest:x12; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(xperm.b, x12, x10, x11, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x4, 80, x5)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_1:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x4_2:
+    .fill 11*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S
new file mode 100644
index 000000000..1f02df067
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/K_unratified/src/xperm.n-01.S
@@ -0,0 +1,2816 @@
+// -----------
+// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
+// version   : 0.4.5
+// timestamp : Thu May 27 16:46:33 2021 GMT
+// usage     : riscv_ctg \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv64i_k.cgf \
+//                  --base-isa rv64i \
+//                  --randomize
+// -----------
+//
+// -----------
+// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the xperm.n instruction of the RISC-V  extension for the xperm.n covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",xperm.n)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKs.*);def TEST_CASE_1=True;",xperm.n)
+
+RVTEST_CASE(2,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",xperm.n)
+
+RVTEST_CASE(3,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*ZKb.*);def TEST_CASE_1=True;",xperm.n)
+
+RVTEST_SIGBASE( x11,signature_x11_1)
+
+inst_0:
+// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==x15, rs2==x16, rd==x29, rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0x34C2DA8003CC0F27 
+// opcode: xperm.n ; op1:x15; op2:x16; dest:x29; op1val:0xffffffffffffffff;  op2val:0x34c2da8003cc0f27
+TEST_RR_OP(xperm.n, x29, x15, x16, 0x0000000000000000, 0xffffffffffffffff, 0x34c2da8003cc0f27, x11, 0, x18)
+
+inst_1:
+// rs1 == rs2 == rd, rs1==x22, rs2==x22, rd==x22, rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: xperm.n ; op1:x22; op2:x22; dest:x22; op1val:0x6af29145404fd8ed;  op2val:0x6af29145404fd8ed
+TEST_RR_OP(xperm.n, x22, x22, x22, 0x0000000000000000, 0x6af29145404fd8ed, 0x6af29145404fd8ed, x11, 8, x18)
+
+inst_2:
+// rs1 == rd != rs2, rs1==x8, rs2==x9, rd==x8, rs1_val == 0x6d23c0488a6019c1 and rs2_val == 0x860bdaad7447a088 
+// opcode: xperm.n ; op1:x8; op2:x9; dest:x8; op1val:0x6d23c0488a6019c1;  op2val:0x860bdaad7447a088
+TEST_RR_OP(xperm.n, x8, x8, x9, 0x0000000000000000, 0x6d23c0488a6019c1, 0x860bdaad7447a088, x11, 16, x18)
+
+inst_3:
+// rs1 == rs2 != rd, rs1==x29, rs2==x29, rd==x31, rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: xperm.n ; op1:x29; op2:x29; dest:x31; op1val:0x1f7d946f17168ab3;  op2val:0x1f7d946f17168ab3
+TEST_RR_OP(xperm.n, x31, x29, x29, 0x0000000000000000, 0x1f7d946f17168ab3, 0x1f7d946f17168ab3, x11, 24, x18)
+
+inst_4:
+// rs2 == rd != rs1, rs1==x6, rs2==x30, rd==x30, rs1_val == 0xef1d54db32b81f27 and rs2_val == 0x1826a804284fe16c 
+// opcode: xperm.n ; op1:x6; op2:x30; dest:x30; op1val:0xef1d54db32b81f27;  op2val:0x1826a804284fe16c
+TEST_RR_OP(xperm.n, x30, x6, x30, 0x0000000000000000, 0xef1d54db32b81f27, 0x1826a804284fe16c, x11, 32, x18)
+
+inst_5:
+// rs1==x12, rs2==x21, rd==x0, rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: xperm.n ; op1:x12; op2:x21; dest:x0; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(xperm.n, x0, x12, x21, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x11, 40, x18)
+
+inst_6:
+// rs1==x0, rs2==x25, rd==x16, rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: xperm.n ; op1:x0; op2:x25; dest:x16; op1val:0x0;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(xperm.n, x16, x0, x25, 0x0000000000000000, 0x0, 0x1aa1beebefb902cb, x11, 48, x18)
+
+inst_7:
+// rs1==x7, rs2==x31, rd==x10, rs1_val == 0x79bb7c341d3110bc and rs2_val == 0x8678f5e3d272e229 
+// opcode: xperm.n ; op1:x7; op2:x31; dest:x10; op1val:0x79bb7c341d3110bc;  op2val:0x8678f5e3d272e229
+TEST_RR_OP(xperm.n, x10, x7, x31, 0x0000000000000000, 0x79bb7c341d3110bc, 0x8678f5e3d272e229, x11, 56, x18)
+
+inst_8:
+// rs1==x17, rs2==x4, rd==x14, rs1_val == 0xe2eaf4a09869be8c and rs2_val == 0x5b730cad91766f62 
+// opcode: xperm.n ; op1:x17; op2:x4; dest:x14; op1val:0xe2eaf4a09869be8c;  op2val:0x5b730cad91766f62
+TEST_RR_OP(xperm.n, x14, x17, x4, 0x0000000000000000, 0xe2eaf4a09869be8c, 0x5b730cad91766f62, x11, 64, x18)
+
+inst_9:
+// rs1==x16, rs2==x27, rd==x17, rs1_val == 0xc0fe15dd0df9564b and rs2_val == 0xb22bbf7eb4c858fb 
+// opcode: xperm.n ; op1:x16; op2:x27; dest:x17; op1val:0xc0fe15dd0df9564b;  op2val:0xb22bbf7eb4c858fb
+TEST_RR_OP(xperm.n, x17, x16, x27, 0x0000000000000000, 0xc0fe15dd0df9564b, 0xb22bbf7eb4c858fb, x11, 72, x18)
+
+inst_10:
+// rs1==x30, rs2==x28, rd==x27, rs1_val == 0x4113ee60952acffe and rs2_val == 0x53a66ed1dc80d916 
+// opcode: xperm.n ; op1:x30; op2:x28; dest:x27; op1val:0x4113ee60952acffe;  op2val:0x53a66ed1dc80d916
+TEST_RR_OP(xperm.n, x27, x30, x28, 0x0000000000000000, 0x4113ee60952acffe, 0x53a66ed1dc80d916, x11, 80, x18)
+
+inst_11:
+// rs1==x24, rs2==x12, rd==x15, rs1_val == 0x40a5ff526f38a9c7 and rs2_val == 0xb6f9706fb4f741aa 
+// opcode: xperm.n ; op1:x24; op2:x12; dest:x15; op1val:0x40a5ff526f38a9c7;  op2val:0xb6f9706fb4f741aa
+TEST_RR_OP(xperm.n, x15, x24, x12, 0x0000000000000000, 0x40a5ff526f38a9c7, 0xb6f9706fb4f741aa, x11, 88, x18)
+
+inst_12:
+// rs1==x27, rs2==x7, rd==x6, rs1_val == 0x9bedfe390d6ddd9d and rs2_val == 0xd05668ae0fdb82bc 
+// opcode: xperm.n ; op1:x27; op2:x7; dest:x6; op1val:0x9bedfe390d6ddd9d;  op2val:0xd05668ae0fdb82bc
+TEST_RR_OP(xperm.n, x6, x27, x7, 0x0000000000000000, 0x9bedfe390d6ddd9d, 0xd05668ae0fdb82bc, x11, 96, x18)
+
+inst_13:
+// rs1==x21, rs2==x0, rd==x13, rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: xperm.n ; op1:x21; op2:x0; dest:x13; op1val:0xd75739f82ac177c6;  op2val:0x0
+TEST_RR_OP(xperm.n, x13, x21, x0, 0x0000000000000000, 0xd75739f82ac177c6, 0x0, x11, 104, x18)
+
+inst_14:
+// rs1==x19, rs2==x26, rd==x25, rs1_val == 0x9a4e9ef10171f4df and rs2_val == 0x299c3bcf90efb625 
+// opcode: xperm.n ; op1:x19; op2:x26; dest:x25; op1val:0x9a4e9ef10171f4df;  op2val:0x299c3bcf90efb625
+TEST_RR_OP(xperm.n, x25, x19, x26, 0x0000000000000000, 0x9a4e9ef10171f4df, 0x299c3bcf90efb625, x11, 112, x18)
+
+inst_15:
+// rs1==x2, rs2==x19, rd==x3, rs1_val == 0xd169a3f8cad5e297 and rs2_val == 0x1fc493caa371db42 
+// opcode: xperm.n ; op1:x2; op2:x19; dest:x3; op1val:0xd169a3f8cad5e297;  op2val:0x1fc493caa371db42
+TEST_RR_OP(xperm.n, x3, x2, x19, 0x0000000000000000, 0xd169a3f8cad5e297, 0x1fc493caa371db42, x11, 120, x18)
+
+inst_16:
+// rs1==x4, rs2==x14, rd==x12, rs1_val == 0xd5b9fe5cf69bdcf3 and rs2_val == 0xf4c30307672f666d 
+// opcode: xperm.n ; op1:x4; op2:x14; dest:x12; op1val:0xd5b9fe5cf69bdcf3;  op2val:0xf4c30307672f666d
+TEST_RR_OP(xperm.n, x12, x4, x14, 0x0000000000000000, 0xd5b9fe5cf69bdcf3, 0xf4c30307672f666d, x11, 128, x18)
+
+inst_17:
+// rs1==x5, rs2==x24, rd==x21, rs1_val == 0xe4921bf73047c198 and rs2_val == 0xa0569d765ebc64cb 
+// opcode: xperm.n ; op1:x5; op2:x24; dest:x21; op1val:0xe4921bf73047c198;  op2val:0xa0569d765ebc64cb
+TEST_RR_OP(xperm.n, x21, x5, x24, 0x0000000000000000, 0xe4921bf73047c198, 0xa0569d765ebc64cb, x11, 136, x18)
+
+inst_18:
+// rs1==x26, rs2==x2, rd==x5, rs1_val == 0xfcc1b543c49cd65b and rs2_val == 0x2daf9ac7f5faf207 
+// opcode: xperm.n ; op1:x26; op2:x2; dest:x5; op1val:0xfcc1b543c49cd65b;  op2val:0x2daf9ac7f5faf207
+TEST_RR_OP(xperm.n, x5, x26, x2, 0x0000000000000000, 0xfcc1b543c49cd65b, 0x2daf9ac7f5faf207, x11, 144, x18)
+
+inst_19:
+// rs1==x9, rs2==x3, rd==x2, rs1_val == 0x436f40f274b8de87 and rs2_val == 0x3459294ef273b44c 
+// opcode: xperm.n ; op1:x9; op2:x3; dest:x2; op1val:0x436f40f274b8de87;  op2val:0x3459294ef273b44c
+TEST_RR_OP(xperm.n, x2, x9, x3, 0x0000000000000000, 0x436f40f274b8de87, 0x3459294ef273b44c, x11, 152, x18)
+
+inst_20:
+// rs1==x13, rs2==x1, rd==x7, rs1_val == 0x75a3adb3254a9493 and rs2_val == 0xc5521660f3a3c571 
+// opcode: xperm.n ; op1:x13; op2:x1; dest:x7; op1val:0x75a3adb3254a9493;  op2val:0xc5521660f3a3c571
+TEST_RR_OP(xperm.n, x7, x13, x1, 0x0000000000000000, 0x75a3adb3254a9493, 0xc5521660f3a3c571, x11, 160, x18)
+
+inst_21:
+// rs1==x3, rs2==x10, rd==x20, rs2_val == 0x0000000000000000 and rs1_val == 0x5BA2C7DD5AE10604 
+// opcode: xperm.n ; op1:x3; op2:x10; dest:x20; op1val:0x5ba2c7dd5ae10604;  op2val:0x0
+TEST_RR_OP(xperm.n, x20, x3, x10, 0x0000000000000000, 0x5ba2c7dd5ae10604, 0x0, x11, 168, x7)
+RVTEST_SIGBASE( x2,signature_x2_0)
+
+inst_22:
+// rs1==x18, rs2==x8, rd==x28, rs2_val == 0x8000000000000000 and rs1_val == 0x6F061D6DC38671B6 
+// opcode: xperm.n ; op1:x18; op2:x8; dest:x28; op1val:0x6f061d6dc38671b6;  op2val:0x8000000000000000
+TEST_RR_OP(xperm.n, x28, x18, x8, 0x0000000000000000, 0x6f061d6dc38671b6, 0x8000000000000000, x2, 0, x7)
+
+inst_23:
+// rs1==x1, rs2==x5, rd==x18, rs2_val == 0x4000000000000000 and rs1_val == 0xD2EEEB1C2AF42D39 
+// opcode: xperm.n ; op1:x1; op2:x5; dest:x18; op1val:0xd2eeeb1c2af42d39;  op2val:0x4000000000000000
+TEST_RR_OP(xperm.n, x18, x1, x5, 0x0000000000000000, 0xd2eeeb1c2af42d39, 0x4000000000000000, x2, 8, x7)
+
+inst_24:
+// rs1==x25, rs2==x20, rd==x11, rs2_val == 0xA000000000000000 and rs1_val == 0x485246BF2502307F 
+// opcode: xperm.n ; op1:x25; op2:x20; dest:x11; op1val:0x485246bf2502307f;  op2val:0xa000000000000000
+TEST_RR_OP(xperm.n, x11, x25, x20, 0x0000000000000000, 0x485246bf2502307f, 0xa000000000000000, x2, 16, x7)
+
+inst_25:
+// rs1==x20, rs2==x13, rd==x19, rs2_val == 0x3000000000000000 and rs1_val == 0xD50BD94A392E6FA3 
+// opcode: xperm.n ; op1:x20; op2:x13; dest:x19; op1val:0xd50bd94a392e6fa3;  op2val:0x3000000000000000
+TEST_RR_OP(xperm.n, x19, x20, x13, 0x0000000000000000, 0xd50bd94a392e6fa3, 0x3000000000000000, x2, 24, x7)
+
+inst_26:
+// rs1==x10, rs2==x11, rd==x24, rs2_val == 0x3800000000000000 and rs1_val == 0x8862749480E4D23B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x24; op1val:0x8862749480e4d23b;  op2val:0x3800000000000000
+TEST_RR_OP(xperm.n, x24, x10, x11, 0x0000000000000000, 0x8862749480e4d23b, 0x3800000000000000, x2, 32, x7)
+
+inst_27:
+// rs1==x31, rs2==x23, rd==x26, rs2_val == 0x4C00000000000000 and rs1_val == 0x2405B307CEC7313A 
+// opcode: xperm.n ; op1:x31; op2:x23; dest:x26; op1val:0x2405b307cec7313a;  op2val:0x4c00000000000000
+TEST_RR_OP(xperm.n, x26, x31, x23, 0x0000000000000000, 0x2405b307cec7313a, 0x4c00000000000000, x2, 40, x7)
+
+inst_28:
+// rs1==x23, rs2==x18, rd==x1, rs2_val == 0x8200000000000000 and rs1_val == 0xB1410CBA5D003E38 
+// opcode: xperm.n ; op1:x23; op2:x18; dest:x1; op1val:0xb1410cba5d003e38;  op2val:0x8200000000000000
+TEST_RR_OP(xperm.n, x1, x23, x18, 0x0000000000000000, 0xb1410cba5d003e38, 0x8200000000000000, x2, 48, x7)
+
+inst_29:
+// rs1==x28, rs2==x17, rd==x4, rs2_val == 0x6900000000000000 and rs1_val == 0xDE81BCAD0B815EF0 
+// opcode: xperm.n ; op1:x28; op2:x17; dest:x4; op1val:0xde81bcad0b815ef0;  op2val:0x6900000000000000
+TEST_RR_OP(xperm.n, x4, x28, x17, 0x0000000000000000, 0xde81bcad0b815ef0, 0x6900000000000000, x2, 56, x7)
+
+inst_30:
+// rs1==x14, rs2==x15, rd==x23, rs2_val == 0xCC80000000000000 and rs1_val == 0xBF28804A83E2BA3A 
+// opcode: xperm.n ; op1:x14; op2:x15; dest:x23; op1val:0xbf28804a83e2ba3a;  op2val:0xcc80000000000000
+TEST_RR_OP(xperm.n, x23, x14, x15, 0x0000000000000000, 0xbf28804a83e2ba3a, 0xcc80000000000000, x2, 64, x7)
+
+inst_31:
+// rs1==x11, rs2==x6, rd==x9, rs2_val == 0x1940000000000000 and rs1_val == 0xFD8BF41246E4ABD8 
+// opcode: xperm.n ; op1:x11; op2:x6; dest:x9; op1val:0xfd8bf41246e4abd8;  op2val:0x1940000000000000
+TEST_RR_OP(xperm.n, x9, x11, x6, 0x0000000000000000, 0xfd8bf41246e4abd8, 0x1940000000000000, x2, 72, x7)
+
+inst_32:
+// rs2_val == 0x20A0000000000000 and rs1_val == 0x063BF2DA242D8CEF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x63bf2da242d8cef;  op2val:0x20a0000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x63bf2da242d8cef, 0x20a0000000000000, x2, 80, x7)
+
+inst_33:
+// rs2_val == 0x5C50000000000000 and rs1_val == 0x811D9484D8D8DD47 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x811d9484d8d8dd47;  op2val:0x5c50000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x811d9484d8d8dd47, 0x5c50000000000000, x2, 88, x7)
+
+inst_34:
+// rs2_val == 0xCD28000000000000 and rs1_val == 0x8CB7ED4FC1F36FAE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8cb7ed4fc1f36fae;  op2val:0xcd28000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8cb7ed4fc1f36fae, 0xcd28000000000000, x2, 96, x7)
+
+inst_35:
+// rs2_val == 0xEB24000000000000 and rs1_val == 0x666FAFE7D7704260 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x666fafe7d7704260;  op2val:0xeb24000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x666fafe7d7704260, 0xeb24000000000000, x2, 104, x7)
+
+inst_36:
+// rs2_val == 0xCFB6000000000000 and rs1_val == 0xFDB7038B058160E6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfdb7038b058160e6;  op2val:0xcfb6000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfdb7038b058160e6, 0xcfb6000000000000, x2, 112, x7)
+
+inst_37:
+// rs2_val == 0x118F000000000000 and rs1_val == 0xA4E23852D8BCA4DF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa4e23852d8bca4df;  op2val:0x118f000000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa4e23852d8bca4df, 0x118f000000000000, x2, 120, x7)
+
+inst_38:
+// rs2_val == 0x3B0B800000000000 and rs1_val == 0x718E177DE812DD49 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x718e177de812dd49;  op2val:0x3b0b800000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x718e177de812dd49, 0x3b0b800000000000, x2, 128, x7)
+
+inst_39:
+// rs2_val == 0x3DA8400000000000 and rs1_val == 0x42BEA7753D32D01E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x42bea7753d32d01e;  op2val:0x3da8400000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x42bea7753d32d01e, 0x3da8400000000000, x2, 136, x7)
+
+inst_40:
+// rs2_val == 0xA742A00000000000 and rs1_val == 0xE91EDE432037E34E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe91ede432037e34e;  op2val:0xa742a00000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe91ede432037e34e, 0xa742a00000000000, x2, 144, x7)
+
+inst_41:
+// rs2_val == 0xA3DEF00000000000 and rs1_val == 0xD2039372874434D3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd2039372874434d3;  op2val:0xa3def00000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd2039372874434d3, 0xa3def00000000000, x2, 152, x7)
+
+inst_42:
+// rs2_val == 0x3AF3780000000000 and rs1_val == 0xE8DEC4B7875E9BF5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe8dec4b7875e9bf5;  op2val:0x3af3780000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe8dec4b7875e9bf5, 0x3af3780000000000, x2, 160, x7)
+
+inst_43:
+// rs2_val == 0x4D64CC0000000000 and rs1_val == 0xEED7C61C17D8A217 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xeed7c61c17d8a217;  op2val:0x4d64cc0000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xeed7c61c17d8a217, 0x4d64cc0000000000, x2, 168, x7)
+
+inst_44:
+// rs2_val == 0xF37B4E0000000000 and rs1_val == 0x4EAB740B87F996D6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4eab740b87f996d6;  op2val:0xf37b4e0000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4eab740b87f996d6, 0xf37b4e0000000000, x2, 176, x7)
+
+inst_45:
+// rs2_val == 0xEFE7490000000000 and rs1_val == 0x2466B4600D42EA01 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2466b4600d42ea01;  op2val:0xefe7490000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2466b4600d42ea01, 0xefe7490000000000, x2, 184, x7)
+
+inst_46:
+// rs2_val == 0xE077678000000000 and rs1_val == 0x4256F18F2DE4EB20 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4256f18f2de4eb20;  op2val:0xe077678000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4256f18f2de4eb20, 0xe077678000000000, x2, 192, x7)
+
+inst_47:
+// rs2_val == 0xFA56AA4000000000 and rs1_val == 0x8533DC75D6308385 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8533dc75d6308385;  op2val:0xfa56aa4000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8533dc75d6308385, 0xfa56aa4000000000, x2, 200, x7)
+
+inst_48:
+// rs2_val == 0x60C9F22000000000 and rs1_val == 0xCA355A09AB72F99F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xca355a09ab72f99f;  op2val:0x60c9f22000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xca355a09ab72f99f, 0x60c9f22000000000, x2, 208, x7)
+
+inst_49:
+// rs2_val == 0xAF36F11000000000 and rs1_val == 0x22FED7DB4E7B7359 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x22fed7db4e7b7359;  op2val:0xaf36f11000000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x22fed7db4e7b7359, 0xaf36f11000000000, x2, 216, x7)
+
+inst_50:
+// rs2_val == 0x0333990800000000 and rs1_val == 0xB6DE8BCFD96429C9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb6de8bcfd96429c9;  op2val:0x333990800000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb6de8bcfd96429c9, 0x333990800000000, x2, 224, x7)
+
+inst_51:
+// rs2_val == 0x5C67C8FC00000000 and rs1_val == 0xB9FBD369C8CDF63E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb9fbd369c8cdf63e;  op2val:0x5c67c8fc00000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb9fbd369c8cdf63e, 0x5c67c8fc00000000, x2, 232, x7)
+
+inst_52:
+// rs2_val == 0xC706E0C200000000 and rs1_val == 0x324C464BC06209FB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x324c464bc06209fb;  op2val:0xc706e0c200000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x324c464bc06209fb, 0xc706e0c200000000, x2, 240, x7)
+
+inst_53:
+// rs2_val == 0xEFE091E300000000 and rs1_val == 0x70FD0C20644918A7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x70fd0c20644918a7;  op2val:0xefe091e300000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x70fd0c20644918a7, 0xefe091e300000000, x2, 248, x7)
+
+inst_54:
+// rs2_val == 0xCB7CDDA380000000 and rs1_val == 0x755CD0BF4F63879F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x755cd0bf4f63879f;  op2val:0xcb7cdda380000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x755cd0bf4f63879f, 0xcb7cdda380000000, x2, 256, x7)
+
+inst_55:
+// rs2_val == 0x51885E99C0000000 and rs1_val == 0xA31E74CF1F3C1AD7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa31e74cf1f3c1ad7;  op2val:0x51885e99c0000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa31e74cf1f3c1ad7, 0x51885e99c0000000, x2, 264, x7)
+
+inst_56:
+// rs2_val == 0x87503D9D20000000 and rs1_val == 0x300D9B713BB3E347 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x300d9b713bb3e347;  op2val:0x87503d9d20000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x300d9b713bb3e347, 0x87503d9d20000000, x2, 272, x7)
+
+inst_57:
+// rs2_val == 0x1AC7983C70000000 and rs1_val == 0xCB0ACB582BEDCFC5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcb0acb582bedcfc5;  op2val:0x1ac7983c70000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcb0acb582bedcfc5, 0x1ac7983c70000000, x2, 280, x7)
+
+inst_58:
+// rs2_val == 0x1857BC0AE8000000 and rs1_val == 0xFD5324A47C496066 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfd5324a47c496066;  op2val:0x1857bc0ae8000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfd5324a47c496066, 0x1857bc0ae8000000, x2, 288, x7)
+
+inst_59:
+// rs2_val == 0xB9545B9124000000 and rs1_val == 0xA46EE1F1A8552F4B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa46ee1f1a8552f4b;  op2val:0xb9545b9124000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa46ee1f1a8552f4b, 0xb9545b9124000000, x2, 296, x7)
+
+inst_60:
+// rs2_val == 0xFFE1759C3A000000 and rs1_val == 0x4BFF93C124507198 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4bff93c124507198;  op2val:0xffe1759c3a000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4bff93c124507198, 0xffe1759c3a000000, x2, 304, x7)
+
+inst_61:
+// rs2_val == 0xD12C4A6DFD000000 and rs1_val == 0xE3AC03436656B0E2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe3ac03436656b0e2;  op2val:0xd12c4a6dfd000000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe3ac03436656b0e2, 0xd12c4a6dfd000000, x2, 312, x7)
+
+inst_62:
+// rs2_val == 0x4978C51702800000 and rs1_val == 0x75BD36C79929DFEB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x75bd36c79929dfeb;  op2val:0x4978c51702800000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x75bd36c79929dfeb, 0x4978c51702800000, x2, 320, x7)
+
+inst_63:
+// rs2_val == 0xEC557C3C4D400000 and rs1_val == 0xEA894C29FF6036ED 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xea894c29ff6036ed;  op2val:0xec557c3c4d400000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xea894c29ff6036ed, 0xec557c3c4d400000, x2, 328, x7)
+
+inst_64:
+// rs2_val == 0x7FAB9B0810A00000 and rs1_val == 0x46B7549D93C22130 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x46b7549d93c22130;  op2val:0x7fab9b0810a00000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x46b7549d93c22130, 0x7fab9b0810a00000, x2, 336, x7)
+
+inst_65:
+// rs2_val == 0xAF8FDA6198900000 and rs1_val == 0x7E107814A1C1C528 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7e107814a1c1c528;  op2val:0xaf8fda6198900000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7e107814a1c1c528, 0xaf8fda6198900000, x2, 344, x7)
+
+inst_66:
+// rs2_val == 0x707DF5A4A8F80000 and rs1_val == 0x57E9F6C2408B97CD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x57e9f6c2408b97cd;  op2val:0x707df5a4a8f80000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x57e9f6c2408b97cd, 0x707df5a4a8f80000, x2, 352, x7)
+
+inst_67:
+// rs2_val == 0x924D5D8CDB8C0000 and rs1_val == 0xF3C9FBEDAA8DC392 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf3c9fbedaa8dc392;  op2val:0x924d5d8cdb8c0000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf3c9fbedaa8dc392, 0x924d5d8cdb8c0000, x2, 360, x7)
+
+inst_68:
+// rs2_val == 0x200DC7628C620000 and rs1_val == 0x1078E5395C962250 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1078e5395c962250;  op2val:0x200dc7628c620000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1078e5395c962250, 0x200dc7628c620000, x2, 368, x7)
+
+inst_69:
+// rs2_val == 0x415DC3E7526B0000 and rs1_val == 0x57B0D4C17C2890B1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x57b0d4c17c2890b1;  op2val:0x415dc3e7526b0000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x57b0d4c17c2890b1, 0x415dc3e7526b0000, x2, 376, x7)
+
+inst_70:
+// rs2_val == 0x448E60EF28288000 and rs1_val == 0x9812A13456F646E8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9812a13456f646e8;  op2val:0x448e60ef28288000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9812a13456f646e8, 0x448e60ef28288000, x2, 384, x7)
+
+inst_71:
+// rs2_val == 0xAD881BE63AAF4000 and rs1_val == 0xD367D9F15710B7AE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd367d9f15710b7ae;  op2val:0xad881be63aaf4000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd367d9f15710b7ae, 0xad881be63aaf4000, x2, 392, x7)
+
+inst_72:
+// rs2_val == 0xD3262066BA452000 and rs1_val == 0x1F8B62C23A810BD9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1f8b62c23a810bd9;  op2val:0xd3262066ba452000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1f8b62c23a810bd9, 0xd3262066ba452000, x2, 400, x7)
+
+inst_73:
+// rs2_val == 0x955964C554C37000 and rs1_val == 0xAB4A4D5C22FEB755 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xab4a4d5c22feb755;  op2val:0x955964c554c37000
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xab4a4d5c22feb755, 0x955964c554c37000, x2, 408, x7)
+
+inst_74:
+// rs2_val == 0x0B66A6669D416800 and rs1_val == 0x5CBAF664FCD220D7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5cbaf664fcd220d7;  op2val:0xb66a6669d416800
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5cbaf664fcd220d7, 0xb66a6669d416800, x2, 416, x7)
+
+inst_75:
+// rs2_val == 0x610EA25929454400 and rs1_val == 0xD497855D8B082833 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd497855d8b082833;  op2val:0x610ea25929454400
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd497855d8b082833, 0x610ea25929454400, x2, 424, x7)
+
+inst_76:
+// rs2_val == 0xC19961DDB6C00600 and rs1_val == 0x97DB1001072F6AC9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x97db1001072f6ac9;  op2val:0xc19961ddb6c00600
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x97db1001072f6ac9, 0xc19961ddb6c00600, x2, 432, x7)
+
+inst_77:
+// rs2_val == 0x4C41441591107F00 and rs1_val == 0xD63EF4DE0E724556 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd63ef4de0e724556;  op2val:0x4c41441591107f00
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd63ef4de0e724556, 0x4c41441591107f00, x2, 440, x7)
+
+inst_78:
+// rs2_val == 0xFC44172C98DFBD80 and rs1_val == 0x1BAF44CF3B50C99D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1baf44cf3b50c99d;  op2val:0xfc44172c98dfbd80
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1baf44cf3b50c99d, 0xfc44172c98dfbd80, x2, 448, x7)
+
+inst_79:
+// rs2_val == 0x985875B03F6A4D40 and rs1_val == 0xEAB762A9D6CBF3AE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xeab762a9d6cbf3ae;  op2val:0x985875b03f6a4d40
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xeab762a9d6cbf3ae, 0x985875b03f6a4d40, x2, 456, x7)
+
+inst_80:
+// rs2_val == 0xFCD876518F8264E0 and rs1_val == 0x9B90F7CAF66FA51D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9b90f7caf66fa51d;  op2val:0xfcd876518f8264e0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9b90f7caf66fa51d, 0xfcd876518f8264e0, x2, 464, x7)
+
+inst_81:
+// rs2_val == 0x443A809E48B4BE70 and rs1_val == 0xCBD297D6AEB522FC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcbd297d6aeb522fc;  op2val:0x443a809e48b4be70
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcbd297d6aeb522fc, 0x443a809e48b4be70, x2, 472, x7)
+
+inst_82:
+// rs2_val == 0xB914351D12915378 and rs1_val == 0xDA53E66763735E07 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xda53e66763735e07;  op2val:0xb914351d12915378
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xda53e66763735e07, 0xb914351d12915378, x2, 480, x7)
+
+inst_83:
+// rs2_val == 0x922EC2BF33ECD4FC and rs1_val == 0x77A061BA4B1D37E9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x77a061ba4b1d37e9;  op2val:0x922ec2bf33ecd4fc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x77a061ba4b1d37e9, 0x922ec2bf33ecd4fc, x2, 488, x7)
+
+inst_84:
+// rs2_val == 0x0E1DB424323E7F5E and rs1_val == 0xA6C873830196F0C0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa6c873830196f0c0;  op2val:0xe1db424323e7f5e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa6c873830196f0c0, 0xe1db424323e7f5e, x2, 496, x7)
+
+inst_85:
+// rs2_val == 0x7F8C74B1AF5BC16D and rs1_val == 0x33439FC489476E6E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x33439fc489476e6e;  op2val:0x7f8c74b1af5bc16d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x33439fc489476e6e, 0x7f8c74b1af5bc16d, x2, 504, x7)
+
+inst_86:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x1A323609E92A6130 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x1a323609e92a6130
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x0, 0x1a323609e92a6130, x2, 512, x7)
+
+inst_87:
+// rs1_val == 0x8000000000000000 and rs2_val == 0xED4ECED74BED2975 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8000000000000000;  op2val:0xed4eced74bed2975
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8000000000000000, 0xed4eced74bed2975, x2, 520, x7)
+
+inst_88:
+// rs1_val == 0x4000000000000000 and rs2_val == 0x29CB52AF3206B471 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4000000000000000;  op2val:0x29cb52af3206b471
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4000000000000000, 0x29cb52af3206b471, x2, 528, x7)
+
+inst_89:
+// rs1_val == 0x2000000000000000 and rs2_val == 0x0AE5DE174EF43B6F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2000000000000000;  op2val:0xae5de174ef43b6f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2000000000000000, 0xae5de174ef43b6f, x2, 536, x7)
+
+inst_90:
+// rs1_val == 0xD000000000000000 and rs2_val == 0xB725F591D236CDED 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd000000000000000;  op2val:0xb725f591d236cded
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd000000000000000, 0xb725f591d236cded, x2, 544, x7)
+
+inst_91:
+// rs1_val == 0x5800000000000000 and rs2_val == 0xD5F381D63480C0AD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5800000000000000;  op2val:0xd5f381d63480c0ad
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5800000000000000, 0xd5f381d63480c0ad, x2, 552, x7)
+
+inst_92:
+// rs1_val == 0xFC00000000000000 and rs2_val == 0x56FFE58D4360FEC9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfc00000000000000;  op2val:0x56ffe58d4360fec9
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfc00000000000000, 0x56ffe58d4360fec9, x2, 560, x7)
+
+inst_93:
+// rs1_val == 0x4200000000000000 and rs2_val == 0x699492C960E011EB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4200000000000000;  op2val:0x699492c960e011eb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4200000000000000, 0x699492c960e011eb, x2, 568, x7)
+
+inst_94:
+// rs1_val == 0x7700000000000000 and rs2_val == 0x25F013BA522AE822 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7700000000000000;  op2val:0x25f013ba522ae822
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7700000000000000, 0x25f013ba522ae822, x2, 576, x7)
+
+inst_95:
+// rs1_val == 0x6580000000000000 and rs2_val == 0x48659245994A555F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6580000000000000;  op2val:0x48659245994a555f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6580000000000000, 0x48659245994a555f, x2, 584, x7)
+
+inst_96:
+// rs1_val == 0x46C0000000000000 and rs2_val == 0x491F1B5A5D62953F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x46c0000000000000;  op2val:0x491f1b5a5d62953f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x46c0000000000000, 0x491f1b5a5d62953f, x2, 592, x7)
+
+inst_97:
+// rs1_val == 0x56E0000000000000 and rs2_val == 0x8B57454ACD07888B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x56e0000000000000;  op2val:0x8b57454acd07888b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x56e0000000000000, 0x8b57454acd07888b, x2, 600, x7)
+
+inst_98:
+// rs1_val == 0x56B0000000000000 and rs2_val == 0x2B9C75B64EA4788D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x56b0000000000000;  op2val:0x2b9c75b64ea4788d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x56b0000000000000, 0x2b9c75b64ea4788d, x2, 608, x7)
+
+inst_99:
+// rs1_val == 0x4738000000000000 and rs2_val == 0x045ABE77BB75156A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4738000000000000;  op2val:0x45abe77bb75156a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4738000000000000, 0x45abe77bb75156a, x2, 616, x7)
+
+inst_100:
+// rs1_val == 0x3544000000000000 and rs2_val == 0xA9CC49B7709E60F1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3544000000000000;  op2val:0xa9cc49b7709e60f1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3544000000000000, 0xa9cc49b7709e60f1, x2, 624, x7)
+
+inst_101:
+// rs1_val == 0x0932000000000000 and rs2_val == 0x75CDCD803FF7E48D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x932000000000000;  op2val:0x75cdcd803ff7e48d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x932000000000000, 0x75cdcd803ff7e48d, x2, 632, x7)
+
+inst_102:
+// rs1_val == 0xCD55000000000000 and rs2_val == 0xB2B64C4BE716713F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcd55000000000000;  op2val:0xb2b64c4be716713f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcd55000000000000, 0xb2b64c4be716713f, x2, 640, x7)
+
+inst_103:
+// rs1_val == 0xFD42800000000000 and rs2_val == 0x6EB5568BB03FF489 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfd42800000000000;  op2val:0x6eb5568bb03ff489
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfd42800000000000, 0x6eb5568bb03ff489, x2, 648, x7)
+
+inst_104:
+// rs1_val == 0x8E8A400000000000 and rs2_val == 0x5DD1EE295C3D56E7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8e8a400000000000;  op2val:0x5dd1ee295c3d56e7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8e8a400000000000, 0x5dd1ee295c3d56e7, x2, 656, x7)
+
+inst_105:
+// rs1_val == 0x1370A00000000000 and rs2_val == 0xF19C9FDA18CCD7F7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1370a00000000000;  op2val:0xf19c9fda18ccd7f7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1370a00000000000, 0xf19c9fda18ccd7f7, x2, 664, x7)
+
+inst_106:
+// rs1_val == 0x1408B00000000000 and rs2_val == 0x74FB05DC575D258E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1408b00000000000;  op2val:0x74fb05dc575d258e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1408b00000000000, 0x74fb05dc575d258e, x2, 672, x7)
+
+inst_107:
+// rs1_val == 0xE87AF80000000000 and rs2_val == 0x9F7C62BB7CE1F4B3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe87af80000000000;  op2val:0x9f7c62bb7ce1f4b3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe87af80000000000, 0x9f7c62bb7ce1f4b3, x2, 680, x7)
+
+inst_108:
+// rs1_val == 0xDBA9040000000000 and rs2_val == 0x5D98418D6F9F34B2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdba9040000000000;  op2val:0x5d98418d6f9f34b2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdba9040000000000, 0x5d98418d6f9f34b2, x2, 688, x7)
+
+inst_109:
+// rs1_val == 0x01D61E0000000000 and rs2_val == 0xB21E137C4F832EC8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1d61e0000000000;  op2val:0xb21e137c4f832ec8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1d61e0000000000, 0xb21e137c4f832ec8, x2, 696, x7)
+
+inst_110:
+// rs1_val == 0x6E90570000000000 and rs2_val == 0xAFC08ACE244D9206 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6e90570000000000;  op2val:0xafc08ace244d9206
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6e90570000000000, 0xafc08ace244d9206, x2, 704, x7)
+
+inst_111:
+// rs1_val == 0x2E84D28000000000 and rs2_val == 0x52D700AC5B130474 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2e84d28000000000;  op2val:0x52d700ac5b130474
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2e84d28000000000, 0x52d700ac5b130474, x2, 712, x7)
+
+inst_112:
+// rs1_val == 0xC70A28C000000000 and rs2_val == 0x94A7A5EA64E77961 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc70a28c000000000;  op2val:0x94a7a5ea64e77961
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc70a28c000000000, 0x94a7a5ea64e77961, x2, 720, x7)
+
+inst_113:
+// rs1_val == 0xBAA4F32000000000 and rs2_val == 0x4FE6A6F6305E3F80 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbaa4f32000000000;  op2val:0x4fe6a6f6305e3f80
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbaa4f32000000000, 0x4fe6a6f6305e3f80, x2, 728, x7)
+
+inst_114:
+// rs1_val == 0x5C106A3000000000 and rs2_val == 0xCADB5BEC61250888 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5c106a3000000000;  op2val:0xcadb5bec61250888
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5c106a3000000000, 0xcadb5bec61250888, x2, 736, x7)
+
+inst_115:
+// rs1_val == 0x230B9F8800000000 and rs2_val == 0xCC381E1007E8BF65 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x230b9f8800000000;  op2val:0xcc381e1007e8bf65
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x230b9f8800000000, 0xcc381e1007e8bf65, x2, 744, x7)
+
+inst_116:
+// rs1_val == 0x8D60807C00000000 and rs2_val == 0x903636CF6291F0E2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8d60807c00000000;  op2val:0x903636cf6291f0e2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8d60807c00000000, 0x903636cf6291f0e2, x2, 752, x7)
+
+inst_117:
+// rs1_val == 0x2D47691A00000000 and rs2_val == 0xFAE216DC58F45328 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2d47691a00000000;  op2val:0xfae216dc58f45328
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2d47691a00000000, 0xfae216dc58f45328, x2, 760, x7)
+
+inst_118:
+// rs1_val == 0xFABF0A7B00000000 and rs2_val == 0x6AEB7DBD0A095049 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfabf0a7b00000000;  op2val:0x6aeb7dbd0a095049
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfabf0a7b00000000, 0x6aeb7dbd0a095049, x2, 768, x7)
+
+inst_119:
+// rs1_val == 0x11B6621F80000000 and rs2_val == 0x6F6E71B73344CBB0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x11b6621f80000000;  op2val:0x6f6e71b73344cbb0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x11b6621f80000000, 0x6f6e71b73344cbb0, x2, 776, x7)
+
+inst_120:
+// rs1_val == 0x486E4B47C0000000 and rs2_val == 0x440D8382E2ED8971 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x486e4b47c0000000;  op2val:0x440d8382e2ed8971
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x486e4b47c0000000, 0x440d8382e2ed8971, x2, 784, x7)
+
+inst_121:
+// rs1_val == 0x60E99D0E60000000 and rs2_val == 0xB1B0D8FE00F1F68E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x60e99d0e60000000;  op2val:0xb1b0d8fe00f1f68e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x60e99d0e60000000, 0xb1b0d8fe00f1f68e, x2, 792, x7)
+
+inst_122:
+// rs1_val == 0xF547AF48F0000000 and rs2_val == 0x855EFA7448F71CB0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf547af48f0000000;  op2val:0x855efa7448f71cb0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf547af48f0000000, 0x855efa7448f71cb0, x2, 800, x7)
+
+inst_123:
+// rs1_val == 0x9254A04D98000000 and rs2_val == 0x0BC66A8ADF880B11 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9254a04d98000000;  op2val:0xbc66a8adf880b11
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9254a04d98000000, 0xbc66a8adf880b11, x2, 808, x7)
+
+inst_124:
+// rs1_val == 0xADF58064EC000000 and rs2_val == 0x29828207BD230058 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xadf58064ec000000;  op2val:0x29828207bd230058
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xadf58064ec000000, 0x29828207bd230058, x2, 816, x7)
+
+inst_125:
+// rs1_val == 0x01DAE23576000000 and rs2_val == 0x80904B4C86F90255 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1dae23576000000;  op2val:0x80904b4c86f90255
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1dae23576000000, 0x80904b4c86f90255, x2, 824, x7)
+
+inst_126:
+// rs1_val == 0xB1FF9D608B000000 and rs2_val == 0x27A1689480EBE557 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb1ff9d608b000000;  op2val:0x27a1689480ebe557
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb1ff9d608b000000, 0x27a1689480ebe557, x2, 832, x7)
+
+inst_127:
+// rs1_val == 0x179FAFE7FB800000 and rs2_val == 0xFBDB4DE81DB6027C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x179fafe7fb800000;  op2val:0xfbdb4de81db6027c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x179fafe7fb800000, 0xfbdb4de81db6027c, x2, 840, x7)
+
+inst_128:
+// rs1_val == 0xFBCF76282C400000 and rs2_val == 0x805C2F63023590F7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfbcf76282c400000;  op2val:0x805c2f63023590f7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfbcf76282c400000, 0x805c2f63023590f7, x2, 848, x7)
+
+inst_129:
+// rs1_val == 0xE9FD4B63C2200000 and rs2_val == 0x577F8847CD26CE1C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe9fd4b63c2200000;  op2val:0x577f8847cd26ce1c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe9fd4b63c2200000, 0x577f8847cd26ce1c, x2, 856, x7)
+
+inst_130:
+// rs1_val == 0x42DC43547B700000 and rs2_val == 0xF29C583101B56748 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x42dc43547b700000;  op2val:0xf29c583101b56748
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x42dc43547b700000, 0xf29c583101b56748, x2, 864, x7)
+
+inst_131:
+// rs1_val == 0xED4764DD0CC80000 and rs2_val == 0x2E9115B65D3BBCE0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xed4764dd0cc80000;  op2val:0x2e9115b65d3bbce0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xed4764dd0cc80000, 0x2e9115b65d3bbce0, x2, 872, x7)
+
+inst_132:
+// rs1_val == 0x51B0F5AB96FC0000 and rs2_val == 0x2AE568BAFD1032E8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x51b0f5ab96fc0000;  op2val:0x2ae568bafd1032e8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x51b0f5ab96fc0000, 0x2ae568bafd1032e8, x2, 880, x7)
+
+inst_133:
+// rs1_val == 0xA544ADE7DDE60000 and rs2_val == 0xDB04A838F57083EF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa544ade7dde60000;  op2val:0xdb04a838f57083ef
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa544ade7dde60000, 0xdb04a838f57083ef, x2, 888, x7)
+
+inst_134:
+// rs1_val == 0x925C46CBD3570000 and rs2_val == 0x5E4945ED75923260 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x925c46cbd3570000;  op2val:0x5e4945ed75923260
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x925c46cbd3570000, 0x5e4945ed75923260, x2, 896, x7)
+
+inst_135:
+// rs1_val == 0x1AE589FB47F98000 and rs2_val == 0x096EBEC44616E73D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1ae589fb47f98000;  op2val:0x96ebec44616e73d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1ae589fb47f98000, 0x96ebec44616e73d, x2, 904, x7)
+
+inst_136:
+// rs1_val == 0x1D2ACD14F9C74000 and rs2_val == 0x387BE8B88CCAEC71 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1d2acd14f9c74000;  op2val:0x387be8b88ccaec71
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1d2acd14f9c74000, 0x387be8b88ccaec71, x2, 912, x7)
+
+inst_137:
+// rs1_val == 0x9C9D5A527952A000 and rs2_val == 0x0B21BBBA6D5FCD18 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9c9d5a527952a000;  op2val:0xb21bbba6d5fcd18
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9c9d5a527952a000, 0xb21bbba6d5fcd18, x2, 920, x7)
+
+inst_138:
+// rs1_val == 0x2B20055D1CE93000 and rs2_val == 0x073465B82DEDB6A7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2b20055d1ce93000;  op2val:0x73465b82dedb6a7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2b20055d1ce93000, 0x73465b82dedb6a7, x2, 928, x7)
+
+inst_139:
+// rs1_val == 0xAE39ED63E301E800 and rs2_val == 0x409BD3051D241ED6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xae39ed63e301e800;  op2val:0x409bd3051d241ed6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xae39ed63e301e800, 0x409bd3051d241ed6, x2, 936, x7)
+
+inst_140:
+// rs1_val == 0xD7F893C3AC86AC00 and rs2_val == 0xB0AB577ADDBAD0B1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd7f893c3ac86ac00;  op2val:0xb0ab577addbad0b1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd7f893c3ac86ac00, 0xb0ab577addbad0b1, x2, 944, x7)
+
+inst_141:
+// rs1_val == 0x19B3BFF3DE167A00 and rs2_val == 0x42F5D75EA9E16E27 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x19b3bff3de167a00;  op2val:0x42f5d75ea9e16e27
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x19b3bff3de167a00, 0x42f5d75ea9e16e27, x2, 952, x7)
+
+inst_142:
+// rs1_val == 0xF09825A406BF0D00 and rs2_val == 0xF7AB62A81529755D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf09825a406bf0d00;  op2val:0xf7ab62a81529755d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf09825a406bf0d00, 0xf7ab62a81529755d, x2, 960, x7)
+
+inst_143:
+// rs1_val == 0x01555A450E079180 and rs2_val == 0x8A88C0676273ED06 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1555a450e079180;  op2val:0x8a88c0676273ed06
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1555a450e079180, 0x8a88c0676273ed06, x2, 968, x7)
+
+inst_144:
+// rs1_val == 0x532E2CC5D2955440 and rs2_val == 0xF8A885186C5744BC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x532e2cc5d2955440;  op2val:0xf8a885186c5744bc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x532e2cc5d2955440, 0xf8a885186c5744bc, x2, 976, x7)
+
+inst_145:
+// rs1_val == 0xFB7523B06EC13320 and rs2_val == 0x8248F803A97BCC25 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfb7523b06ec13320;  op2val:0x8248f803a97bcc25
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfb7523b06ec13320, 0x8248f803a97bcc25, x2, 984, x7)
+
+inst_146:
+// rs1_val == 0x382CC710F0F1C6B0 and rs2_val == 0x331B2FB3D19E3224 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x382cc710f0f1c6b0;  op2val:0x331b2fb3d19e3224
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x382cc710f0f1c6b0, 0x331b2fb3d19e3224, x2, 992, x7)
+
+inst_147:
+// rs1_val == 0x4C52CFC2F0F54BC8 and rs2_val == 0xE7EDD86756F547AB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4c52cfc2f0f54bc8;  op2val:0xe7edd86756f547ab
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4c52cfc2f0f54bc8, 0xe7edd86756f547ab, x2, 1000, x7)
+
+inst_148:
+// rs1_val == 0x3DCBE16292D9BE34 and rs2_val == 0xFA60DBD625329041 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3dcbe16292d9be34;  op2val:0xfa60dbd625329041
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3dcbe16292d9be34, 0xfa60dbd625329041, x2, 1008, x7)
+
+inst_149:
+// rs1_val == 0xFE4544F6058F7FE6 and rs2_val == 0x7B87A9E25FEFE911 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfe4544f6058f7fe6;  op2val:0x7b87a9e25fefe911
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfe4544f6058f7fe6, 0x7b87a9e25fefe911, x2, 1016, x7)
+
+inst_150:
+// rs1_val == 0x44DCDA6A797D76DF and rs2_val == 0x248174E5598B88DB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x44dcda6a797d76df;  op2val:0x248174e5598b88db
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x44dcda6a797d76df, 0x248174e5598b88db, x2, 1024, x7)
+
+inst_151:
+// rs2_val == 0x7AF0702B7727BD62 and rs1_val == 0x33BFB0E80AAB4E37 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x33bfb0e80aab4e37;  op2val:0x7af0702b7727bd62
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x33bfb0e80aab4e37, 0x7af0702b7727bd62, x2, 1032, x7)
+
+inst_152:
+// rs2_val == 0xEF6855EDB3AA58E5 and rs1_val == 0xDEDBF20A8F64B9BC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdedbf20a8f64b9bc;  op2val:0xef6855edb3aa58e5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdedbf20a8f64b9bc, 0xef6855edb3aa58e5, x2, 1040, x7)
+
+inst_153:
+// rs2_val == 0xB93AC7EE3D56AC8B and rs1_val == 0x070202441D19DF81 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x70202441d19df81;  op2val:0xb93ac7ee3d56ac8b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x70202441d19df81, 0xb93ac7ee3d56ac8b, x2, 1048, x7)
+
+inst_154:
+// rs2_val == 0xCC31D1DCB5FF09A7 and rs1_val == 0xA3A304857D3AED38 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa3a304857d3aed38;  op2val:0xcc31d1dcb5ff09a7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa3a304857d3aed38, 0xcc31d1dcb5ff09a7, x2, 1056, x7)
+
+inst_155:
+// rs2_val == 0xEF900FB814D5348F and rs1_val == 0x0368A58382283AEE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x368a58382283aee;  op2val:0xef900fb814d5348f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x368a58382283aee, 0xef900fb814d5348f, x2, 1064, x7)
+
+inst_156:
+// rs2_val == 0x7D572379F81A1E9F and rs1_val == 0xA0FA6A24963AB5D7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa0fa6a24963ab5d7;  op2val:0x7d572379f81a1e9f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa0fa6a24963ab5d7, 0x7d572379f81a1e9f, x2, 1072, x7)
+
+inst_157:
+// rs2_val == 0xF5858BCCDD9329BF and rs1_val == 0x1606F8CC740E023D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1606f8cc740e023d;  op2val:0xf5858bccdd9329bf
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1606f8cc740e023d, 0xf5858bccdd9329bf, x2, 1080, x7)
+
+inst_158:
+// rs2_val == 0xEA7BD40266EEF97F and rs1_val == 0x81294A71DFE4C7A5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x81294a71dfe4c7a5;  op2val:0xea7bd40266eef97f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x81294a71dfe4c7a5, 0xea7bd40266eef97f, x2, 1088, x7)
+
+inst_159:
+// rs2_val == 0xB95BF2E9865292FF and rs1_val == 0x9CA99ACFAF698A52 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9ca99acfaf698a52;  op2val:0xb95bf2e9865292ff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9ca99acfaf698a52, 0xb95bf2e9865292ff, x2, 1096, x7)
+
+inst_160:
+// rs2_val == 0x097CEAE809FC3DFF and rs1_val == 0x0440EA57B2FE4FC2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x440ea57b2fe4fc2;  op2val:0x97ceae809fc3dff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x440ea57b2fe4fc2, 0x97ceae809fc3dff, x2, 1104, x7)
+
+inst_161:
+// rs2_val == 0x67212B9D64092BFF and rs1_val == 0x6C456BFCE10E43D4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6c456bfce10e43d4;  op2val:0x67212b9d64092bff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6c456bfce10e43d4, 0x67212b9d64092bff, x2, 1112, x7)
+
+inst_162:
+// rs2_val == 0x9DA9065DD92F97FF and rs1_val == 0x64AD8CD4914AAD80 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x64ad8cd4914aad80;  op2val:0x9da9065dd92f97ff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x64ad8cd4914aad80, 0x9da9065dd92f97ff, x2, 1120, x7)
+
+inst_163:
+// rs2_val == 0xBD7A505430D04FFF and rs1_val == 0x757E5228E88130BA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x757e5228e88130ba;  op2val:0xbd7a505430d04fff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x757e5228e88130ba, 0xbd7a505430d04fff, x2, 1128, x7)
+
+inst_164:
+// rs2_val == 0x6CB1BE29E6371FFF and rs1_val == 0xC6592AAD0AE95557 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc6592aad0ae95557;  op2val:0x6cb1be29e6371fff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc6592aad0ae95557, 0x6cb1be29e6371fff, x2, 1136, x7)
+
+inst_165:
+// rs2_val == 0x6F3B6FA6F8DD3FFF and rs1_val == 0x7FB1AC680B72BB91 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7fb1ac680b72bb91;  op2val:0x6f3b6fa6f8dd3fff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7fb1ac680b72bb91, 0x6f3b6fa6f8dd3fff, x2, 1144, x7)
+
+inst_166:
+// rs2_val == 0x249808D0BE5F7FFF and rs1_val == 0x06E1DD67303CA1D0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6e1dd67303ca1d0;  op2val:0x249808d0be5f7fff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6e1dd67303ca1d0, 0x249808d0be5f7fff, x2, 1152, x7)
+
+inst_167:
+// rs2_val == 0x1A5B9CCD70C2FFFF and rs1_val == 0xB8F66A4F832CBAFF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb8f66a4f832cbaff;  op2val:0x1a5b9ccd70c2ffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb8f66a4f832cbaff, 0x1a5b9ccd70c2ffff, x2, 1160, x7)
+
+inst_168:
+// rs2_val == 0xF4EE2270D581FFFF and rs1_val == 0xC8738F370C99C902 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc8738f370c99c902;  op2val:0xf4ee2270d581ffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc8738f370c99c902, 0xf4ee2270d581ffff, x2, 1168, x7)
+
+inst_169:
+// rs2_val == 0x8E2B5C7E1493FFFF and rs1_val == 0x66A4E1F83E0AD875 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x66a4e1f83e0ad875;  op2val:0x8e2b5c7e1493ffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x66a4e1f83e0ad875, 0x8e2b5c7e1493ffff, x2, 1176, x7)
+
+inst_170:
+// rs2_val == 0x355695E68D37FFFF and rs1_val == 0x6673663C6DD54CB4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6673663c6dd54cb4;  op2val:0x355695e68d37ffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6673663c6dd54cb4, 0x355695e68d37ffff, x2, 1184, x7)
+
+inst_171:
+// rs2_val == 0xF4F31A2BCC6FFFFF and rs1_val == 0x7DE7F4261F893D02 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7de7f4261f893d02;  op2val:0xf4f31a2bcc6fffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7de7f4261f893d02, 0xf4f31a2bcc6fffff, x2, 1192, x7)
+
+inst_172:
+// rs2_val == 0x28F20E42BDDFFFFF and rs1_val == 0xF17DC31D6D64E7AD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf17dc31d6d64e7ad;  op2val:0x28f20e42bddfffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf17dc31d6d64e7ad, 0x28f20e42bddfffff, x2, 1200, x7)
+
+inst_173:
+// rs2_val == 0x5415A0435CBFFFFF and rs1_val == 0x1B607A8D3161B010 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1b607a8d3161b010;  op2val:0x5415a0435cbfffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1b607a8d3161b010, 0x5415a0435cbfffff, x2, 1208, x7)
+
+inst_174:
+// rs2_val == 0x590C01C43E7FFFFF and rs1_val == 0x04EF06236FB0F1C0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4ef06236fb0f1c0;  op2val:0x590c01c43e7fffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4ef06236fb0f1c0, 0x590c01c43e7fffff, x2, 1216, x7)
+
+inst_175:
+// rs2_val == 0x004FB0B2B4FFFFFF and rs1_val == 0x853ED27FA1D02D4D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x853ed27fa1d02d4d;  op2val:0x4fb0b2b4ffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x853ed27fa1d02d4d, 0x4fb0b2b4ffffff, x2, 1224, x7)
+
+inst_176:
+// rs2_val == 0x03EB3F6C71FFFFFF and rs1_val == 0xEB9A53986BE07552 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xeb9a53986be07552;  op2val:0x3eb3f6c71ffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xeb9a53986be07552, 0x3eb3f6c71ffffff, x2, 1232, x7)
+
+inst_177:
+// rs2_val == 0xE30AA425B3FFFFFF and rs1_val == 0xD183808ADB0BBA39 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd183808adb0bba39;  op2val:0xe30aa425b3ffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd183808adb0bba39, 0xe30aa425b3ffffff, x2, 1240, x7)
+
+inst_178:
+// rs2_val == 0xD756C0F057FFFFFF and rs1_val == 0x1FF934CB5D1139A4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1ff934cb5d1139a4;  op2val:0xd756c0f057ffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1ff934cb5d1139a4, 0xd756c0f057ffffff, x2, 1248, x7)
+
+inst_179:
+// rs2_val == 0xB5BB3B242FFFFFFF and rs1_val == 0x3BBC81CE7A44C8AD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3bbc81ce7a44c8ad;  op2val:0xb5bb3b242fffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3bbc81ce7a44c8ad, 0xb5bb3b242fffffff, x2, 1256, x7)
+
+inst_180:
+// rs2_val == 0xE52FB0819FFFFFFF and rs1_val == 0x8B89800093547E48 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8b89800093547e48;  op2val:0xe52fb0819fffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8b89800093547e48, 0xe52fb0819fffffff, x2, 1264, x7)
+
+inst_181:
+// rs2_val == 0x710733FE3FFFFFFF and rs1_val == 0x1AB5FFE4994902CA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1ab5ffe4994902ca;  op2val:0x710733fe3fffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1ab5ffe4994902ca, 0x710733fe3fffffff, x2, 1272, x7)
+
+inst_182:
+// rs2_val == 0xCEE6C9487FFFFFFF and rs1_val == 0x19A55FA94E2E7447 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x19a55fa94e2e7447;  op2val:0xcee6c9487fffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x19a55fa94e2e7447, 0xcee6c9487fffffff, x2, 1280, x7)
+
+inst_183:
+// rs2_val == 0x1E903AD2FFFFFFFF and rs1_val == 0xC0A83D81F7192179 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc0a83d81f7192179;  op2val:0x1e903ad2ffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc0a83d81f7192179, 0x1e903ad2ffffffff, x2, 1288, x7)
+
+inst_184:
+// rs2_val == 0xA6E915BDFFFFFFFF and rs1_val == 0x292268C615A03321 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x292268c615a03321;  op2val:0xa6e915bdffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x292268c615a03321, 0xa6e915bdffffffff, x2, 1296, x7)
+
+inst_185:
+// rs2_val == 0xBE4349E3FFFFFFFF and rs1_val == 0x36370FCCB733640C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x36370fccb733640c;  op2val:0xbe4349e3ffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x36370fccb733640c, 0xbe4349e3ffffffff, x2, 1304, x7)
+
+inst_186:
+// rs2_val == 0x3EA485F7FFFFFFFF and rs1_val == 0xE820BA0F6AEDE476 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe820ba0f6aede476;  op2val:0x3ea485f7ffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe820ba0f6aede476, 0x3ea485f7ffffffff, x2, 1312, x7)
+
+inst_187:
+// rs2_val == 0xC680322FFFFFFFFF and rs1_val == 0x4E0AA5616D2DB9E3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4e0aa5616d2db9e3;  op2val:0xc680322fffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4e0aa5616d2db9e3, 0xc680322fffffffff, x2, 1320, x7)
+
+inst_188:
+// rs2_val == 0x9EF4CE9FFFFFFFFF and rs1_val == 0x2C9AAA4CBFFB6C5C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2c9aaa4cbffb6c5c;  op2val:0x9ef4ce9fffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2c9aaa4cbffb6c5c, 0x9ef4ce9fffffffff, x2, 1328, x7)
+
+inst_189:
+// rs2_val == 0x83653EBFFFFFFFFF and rs1_val == 0x1C8073CF27B012A3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1c8073cf27b012a3;  op2val:0x83653ebfffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1c8073cf27b012a3, 0x83653ebfffffffff, x2, 1336, x7)
+
+inst_190:
+// rs2_val == 0x6FFD7D7FFFFFFFFF and rs1_val == 0xCC11F70E14A7DD83 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcc11f70e14a7dd83;  op2val:0x6ffd7d7fffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcc11f70e14a7dd83, 0x6ffd7d7fffffffff, x2, 1344, x7)
+
+inst_191:
+// rs2_val == 0x365EE0FFFFFFFFFF and rs1_val == 0x0C9DC3EC2F6AA770 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc9dc3ec2f6aa770;  op2val:0x365ee0ffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc9dc3ec2f6aa770, 0x365ee0ffffffffff, x2, 1352, x7)
+
+inst_192:
+// rs2_val == 0x1CE551FFFFFFFFFF and rs1_val == 0x8DF80A8D112154CC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8df80a8d112154cc;  op2val:0x1ce551ffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8df80a8d112154cc, 0x1ce551ffffffffff, x2, 1360, x7)
+
+inst_193:
+// rs2_val == 0xA10263FFFFFFFFFF and rs1_val == 0xE05474E1F96EAFFA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe05474e1f96eaffa;  op2val:0xa10263ffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe05474e1f96eaffa, 0xa10263ffffffffff, x2, 1368, x7)
+
+inst_194:
+// rs2_val == 0x4CC607FFFFFFFFFF and rs1_val == 0x4B6AE0AB8FBFF9BA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4b6ae0ab8fbff9ba;  op2val:0x4cc607ffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4b6ae0ab8fbff9ba, 0x4cc607ffffffffff, x2, 1376, x7)
+
+inst_195:
+// rs2_val == 0x00D36FFFFFFFFFFF and rs1_val == 0x884A2AF82552FBF9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x884a2af82552fbf9;  op2val:0xd36fffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x884a2af82552fbf9, 0xd36fffffffffff, x2, 1384, x7)
+
+inst_196:
+// rs2_val == 0x7B40DFFFFFFFFFFF and rs1_val == 0x1475D76C0F99D8BC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1475d76c0f99d8bc;  op2val:0x7b40dfffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1475d76c0f99d8bc, 0x7b40dfffffffffff, x2, 1392, x7)
+
+inst_197:
+// rs2_val == 0x6A0F3FFFFFFFFFFF and rs1_val == 0x729D8FD2B68C8FCE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x729d8fd2b68c8fce;  op2val:0x6a0f3fffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x729d8fd2b68c8fce, 0x6a0f3fffffffffff, x2, 1400, x7)
+
+inst_198:
+// rs2_val == 0x1FE47FFFFFFFFFFF and rs1_val == 0xC407E2A913E5CF6B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc407e2a913e5cf6b;  op2val:0x1fe47fffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc407e2a913e5cf6b, 0x1fe47fffffffffff, x2, 1408, x7)
+
+inst_199:
+// rs2_val == 0xDBEEFFFFFFFFFFFF and rs1_val == 0x5697EBD547CD73ED 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5697ebd547cd73ed;  op2val:0xdbeeffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5697ebd547cd73ed, 0xdbeeffffffffffff, x2, 1416, x7)
+
+inst_200:
+// rs2_val == 0x9269FFFFFFFFFFFF and rs1_val == 0x69F35DA38364A709 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x69f35da38364a709;  op2val:0x9269ffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x69f35da38364a709, 0x9269ffffffffffff, x2, 1424, x7)
+
+inst_201:
+// rs2_val == 0x93FBFFFFFFFFFFFF and rs1_val == 0x9230A15AD0917142 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9230a15ad0917142;  op2val:0x93fbffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9230a15ad0917142, 0x93fbffffffffffff, x2, 1432, x7)
+
+inst_202:
+// rs2_val == 0x1AB7FFFFFFFFFFFF and rs1_val == 0xE057776C76427709 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe057776c76427709;  op2val:0x1ab7ffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe057776c76427709, 0x1ab7ffffffffffff, x2, 1440, x7)
+
+inst_203:
+// rs2_val == 0x222FFFFFFFFFFFFF and rs1_val == 0xB9E861C820176DBE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb9e861c820176dbe;  op2val:0x222fffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb9e861c820176dbe, 0x222fffffffffffff, x2, 1448, x7)
+
+inst_204:
+// rs2_val == 0x489FFFFFFFFFFFFF and rs1_val == 0x17C5DA8E9738BFB9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x17c5da8e9738bfb9;  op2val:0x489fffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x17c5da8e9738bfb9, 0x489fffffffffffff, x2, 1456, x7)
+
+inst_205:
+// rs2_val == 0x5A3FFFFFFFFFFFFF and rs1_val == 0xB888D0205843990B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb888d0205843990b;  op2val:0x5a3fffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb888d0205843990b, 0x5a3fffffffffffff, x2, 1464, x7)
+
+inst_206:
+// rs2_val == 0xEA7FFFFFFFFFFFFF and rs1_val == 0xEE8EB1B125FB16B4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xee8eb1b125fb16b4;  op2val:0xea7fffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xee8eb1b125fb16b4, 0xea7fffffffffffff, x2, 1472, x7)
+
+inst_207:
+// rs2_val == 0x82FFFFFFFFFFFFFF and rs1_val == 0x0341EA23BD94509C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x341ea23bd94509c;  op2val:0x82ffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x341ea23bd94509c, 0x82ffffffffffffff, x2, 1480, x7)
+
+inst_208:
+// rs2_val == 0xB1FFFFFFFFFFFFFF and rs1_val == 0x6D5C2871FE183D04 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6d5c2871fe183d04;  op2val:0xb1ffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6d5c2871fe183d04, 0xb1ffffffffffffff, x2, 1488, x7)
+
+inst_209:
+// rs2_val == 0xC3FFFFFFFFFFFFFF and rs1_val == 0x9BAE401E386EF954 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9bae401e386ef954;  op2val:0xc3ffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9bae401e386ef954, 0xc3ffffffffffffff, x2, 1496, x7)
+
+inst_210:
+// rs2_val == 0x87FFFFFFFFFFFFFF and rs1_val == 0x9241B7ED0274846B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9241b7ed0274846b;  op2val:0x87ffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9241b7ed0274846b, 0x87ffffffffffffff, x2, 1504, x7)
+
+inst_211:
+// rs2_val == 0x8FFFFFFFFFFFFFFF and rs1_val == 0x3E610134180C5DB5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3e610134180c5db5;  op2val:0x8fffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3e610134180c5db5, 0x8fffffffffffffff, x2, 1512, x7)
+
+inst_212:
+// rs2_val == 0x9FFFFFFFFFFFFFFF and rs1_val == 0x39C88EC041E5A5DE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x39c88ec041e5a5de;  op2val:0x9fffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x39c88ec041e5a5de, 0x9fffffffffffffff, x2, 1520, x7)
+
+inst_213:
+// rs2_val == 0xBFFFFFFFFFFFFFFF and rs1_val == 0xA67CE511275BBF80 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa67ce511275bbf80;  op2val:0xbfffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa67ce511275bbf80, 0xbfffffffffffffff, x2, 1528, x7)
+
+inst_214:
+// rs2_val == 0x7FFFFFFFFFFFFFFF and rs1_val == 0x24B6B671AE5FDCBB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x24b6b671ae5fdcbb;  op2val:0x7fffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x24b6b671ae5fdcbb, 0x7fffffffffffffff, x2, 1536, x7)
+
+inst_215:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0x6DAE4547B0F94BB3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6dae4547b0f94bb3;  op2val:0xffffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6dae4547b0f94bb3, 0xffffffffffffffff, x2, 1544, x7)
+
+inst_216:
+// rs1_val == 0x0168EF241A5632E0 and rs2_val == 0x220746CC96C03042 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x168ef241a5632e0;  op2val:0x220746cc96c03042
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x168ef241a5632e0, 0x220746cc96c03042, x2, 1552, x7)
+
+inst_217:
+// rs1_val == 0x30D2EC9FD4D686CD and rs2_val == 0x2DC04D358033ADA7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x30d2ec9fd4d686cd;  op2val:0x2dc04d358033ada7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x30d2ec9fd4d686cd, 0x2dc04d358033ada7, x2, 1560, x7)
+
+inst_218:
+// rs1_val == 0xC42A14B631A3CF7B and rs2_val == 0xB6CF3DE46025666D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc42a14b631a3cf7b;  op2val:0xb6cf3de46025666d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc42a14b631a3cf7b, 0xb6cf3de46025666d, x2, 1568, x7)
+
+inst_219:
+// rs1_val == 0x27B2BDDA42EE9AA7 and rs2_val == 0x8964663CF541AB61 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x27b2bdda42ee9aa7;  op2val:0x8964663cf541ab61
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x27b2bdda42ee9aa7, 0x8964663cf541ab61, x2, 1576, x7)
+
+inst_220:
+// rs1_val == 0x2815A9156A8877CF and rs2_val == 0x7BEA8A85CD09E875 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2815a9156a8877cf;  op2val:0x7bea8a85cd09e875
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2815a9156a8877cf, 0x7bea8a85cd09e875, x2, 1584, x7)
+
+inst_221:
+// rs1_val == 0xFE0022C2EFEFFC5F and rs2_val == 0xDA80DDEFF3D107A2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfe0022c2efeffc5f;  op2val:0xda80ddeff3d107a2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfe0022c2efeffc5f, 0xda80ddeff3d107a2, x2, 1592, x7)
+
+inst_222:
+// rs1_val == 0x424F6311883EAD3F and rs2_val == 0x54FAD64046B88C5E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x424f6311883ead3f;  op2val:0x54fad64046b88c5e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x424f6311883ead3f, 0x54fad64046b88c5e, x2, 1600, x7)
+
+inst_223:
+// rs1_val == 0x4D0957FB733F597F and rs2_val == 0x86BDDB7C00F0A572 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4d0957fb733f597f;  op2val:0x86bddb7c00f0a572
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4d0957fb733f597f, 0x86bddb7c00f0a572, x2, 1608, x7)
+
+inst_224:
+// rs1_val == 0x448BFE1163DD2CFF and rs2_val == 0xC8EA69A8269E1925 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x448bfe1163dd2cff;  op2val:0xc8ea69a8269e1925
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x448bfe1163dd2cff, 0xc8ea69a8269e1925, x2, 1616, x7)
+
+inst_225:
+// rs1_val == 0x67DFCA774EF73DFF and rs2_val == 0x633F9E36FF03170E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x67dfca774ef73dff;  op2val:0x633f9e36ff03170e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x67dfca774ef73dff, 0x633f9e36ff03170e, x2, 1624, x7)
+
+inst_226:
+// rs1_val == 0xC312E040EB1873FF and rs2_val == 0x1C0290060A710087 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc312e040eb1873ff;  op2val:0x1c0290060a710087
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc312e040eb1873ff, 0x1c0290060a710087, x2, 1632, x7)
+
+inst_227:
+// rs1_val == 0x9F440F98291917FF and rs2_val == 0xB36964F8B74D1614 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9f440f98291917ff;  op2val:0xb36964f8b74d1614
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9f440f98291917ff, 0xb36964f8b74d1614, x2, 1640, x7)
+
+inst_228:
+// rs1_val == 0x5569DAB7FFE78FFF and rs2_val == 0xA09C74E3CF1EC7BA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5569dab7ffe78fff;  op2val:0xa09c74e3cf1ec7ba
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5569dab7ffe78fff, 0xa09c74e3cf1ec7ba, x2, 1648, x7)
+
+inst_229:
+// rs1_val == 0x03FD3B8CBA185FFF and rs2_val == 0xDDC89919457288A2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3fd3b8cba185fff;  op2val:0xddc89919457288a2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3fd3b8cba185fff, 0xddc89919457288a2, x2, 1656, x7)
+
+inst_230:
+// rs1_val == 0x0D5574B45F67BFFF and rs2_val == 0x07C8ADBBEE84A991 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd5574b45f67bfff;  op2val:0x7c8adbbee84a991
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd5574b45f67bfff, 0x7c8adbbee84a991, x2, 1664, x7)
+
+inst_231:
+// rs1_val == 0x8BA43677F63C7FFF and rs2_val == 0x42C1BE6C4C4006C3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8ba43677f63c7fff;  op2val:0x42c1be6c4c4006c3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8ba43677f63c7fff, 0x42c1be6c4c4006c3, x2, 1672, x7)
+
+inst_232:
+// rs1_val == 0x231D058C9D02FFFF and rs2_val == 0x4CACE19165844C17 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x231d058c9d02ffff;  op2val:0x4cace19165844c17
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x231d058c9d02ffff, 0x4cace19165844c17, x2, 1680, x7)
+
+inst_233:
+// rs1_val == 0x8C0F5CBFD6F1FFFF and rs2_val == 0x0D4C58ABE5C7946A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8c0f5cbfd6f1ffff;  op2val:0xd4c58abe5c7946a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8c0f5cbfd6f1ffff, 0xd4c58abe5c7946a, x2, 1688, x7)
+
+inst_234:
+// rs1_val == 0xB7E7669E0C03FFFF and rs2_val == 0x9EDFCC1B64A14081 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb7e7669e0c03ffff;  op2val:0x9edfcc1b64a14081
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb7e7669e0c03ffff, 0x9edfcc1b64a14081, x2, 1696, x7)
+
+inst_235:
+// rs1_val == 0x4399EC2A5857FFFF and rs2_val == 0xD24F0724CD41CAD2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4399ec2a5857ffff;  op2val:0xd24f0724cd41cad2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4399ec2a5857ffff, 0xd24f0724cd41cad2, x2, 1704, x7)
+
+inst_236:
+// rs1_val == 0x7A9AC0A716EFFFFF and rs2_val == 0x5F249E4DEE8F948A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7a9ac0a716efffff;  op2val:0x5f249e4dee8f948a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7a9ac0a716efffff, 0x5f249e4dee8f948a, x2, 1712, x7)
+
+inst_237:
+// rs1_val == 0x0143AC65E6DFFFFF and rs2_val == 0xAE7C7AE4DE38D7E2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x143ac65e6dfffff;  op2val:0xae7c7ae4de38d7e2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x143ac65e6dfffff, 0xae7c7ae4de38d7e2, x2, 1720, x7)
+
+inst_238:
+// rs1_val == 0xE31F9713E4BFFFFF and rs2_val == 0xBD5A3C088B9F8591 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe31f9713e4bfffff;  op2val:0xbd5a3c088b9f8591
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe31f9713e4bfffff, 0xbd5a3c088b9f8591, x2, 1728, x7)
+
+inst_239:
+// rs1_val == 0xCDBD527DF77FFFFF and rs2_val == 0x529D62B60C96A183 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcdbd527df77fffff;  op2val:0x529d62b60c96a183
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcdbd527df77fffff, 0x529d62b60c96a183, x2, 1736, x7)
+
+inst_240:
+// rs1_val == 0x59DDE3310AFFFFFF and rs2_val == 0x4BA4996688F931F4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x59dde3310affffff;  op2val:0x4ba4996688f931f4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x59dde3310affffff, 0x4ba4996688f931f4, x2, 1744, x7)
+
+inst_241:
+// rs1_val == 0xE05E8C5F95FFFFFF and rs2_val == 0xFD670591955235A4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe05e8c5f95ffffff;  op2val:0xfd670591955235a4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe05e8c5f95ffffff, 0xfd670591955235a4, x2, 1752, x7)
+
+inst_242:
+// rs1_val == 0x19835A0D23FFFFFF and rs2_val == 0x7DABB7005C6C32A5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x19835a0d23ffffff;  op2val:0x7dabb7005c6c32a5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x19835a0d23ffffff, 0x7dabb7005c6c32a5, x2, 1760, x7)
+
+inst_243:
+// rs1_val == 0x636A75E397FFFFFF and rs2_val == 0x088B3E9E4A7A5C05 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x636a75e397ffffff;  op2val:0x88b3e9e4a7a5c05
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x636a75e397ffffff, 0x88b3e9e4a7a5c05, x2, 1768, x7)
+
+inst_244:
+// rs1_val == 0x280088DBCFFFFFFF and rs2_val == 0x4ED6242837E0DE00 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x280088dbcfffffff;  op2val:0x4ed6242837e0de00
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x280088dbcfffffff, 0x4ed6242837e0de00, x2, 1776, x7)
+
+inst_245:
+// rs1_val == 0x4A18738A1FFFFFFF and rs2_val == 0x1CA7BD1F0D770F3C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4a18738a1fffffff;  op2val:0x1ca7bd1f0d770f3c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4a18738a1fffffff, 0x1ca7bd1f0d770f3c, x2, 1784, x7)
+
+inst_246:
+// rs1_val == 0xFDD2CB403FFFFFFF and rs2_val == 0x63C2504C8DFC2307 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfdd2cb403fffffff;  op2val:0x63c2504c8dfc2307
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfdd2cb403fffffff, 0x63c2504c8dfc2307, x2, 1792, x7)
+
+inst_247:
+// rs1_val == 0xC61B1FBF7FFFFFFF and rs2_val == 0x30BFF1924E6EE408 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc61b1fbf7fffffff;  op2val:0x30bff1924e6ee408
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc61b1fbf7fffffff, 0x30bff1924e6ee408, x2, 1800, x7)
+
+inst_248:
+// rs1_val == 0x0BACFC76FFFFFFFF and rs2_val == 0xEBDA5A4F998D1525 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbacfc76ffffffff;  op2val:0xebda5a4f998d1525
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbacfc76ffffffff, 0xebda5a4f998d1525, x2, 1808, x7)
+
+inst_249:
+// rs1_val == 0x65CB60BDFFFFFFFF and rs2_val == 0x1635B51A75EE935F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x65cb60bdffffffff;  op2val:0x1635b51a75ee935f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x65cb60bdffffffff, 0x1635b51a75ee935f, x2, 1816, x7)
+
+inst_250:
+// rs1_val == 0xA4053173FFFFFFFF and rs2_val == 0x6CE859BB59CF4BB2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa4053173ffffffff;  op2val:0x6ce859bb59cf4bb2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa4053173ffffffff, 0x6ce859bb59cf4bb2, x2, 1824, x7)
+
+inst_251:
+// rs1_val == 0x3E87B427FFFFFFFF and rs2_val == 0x499006C897933E6C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3e87b427ffffffff;  op2val:0x499006c897933e6c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3e87b427ffffffff, 0x499006c897933e6c, x2, 1832, x7)
+
+inst_252:
+// rs1_val == 0x6CC30F6FFFFFFFFF and rs2_val == 0x3C5B3EEE9687F28F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6cc30f6fffffffff;  op2val:0x3c5b3eee9687f28f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6cc30f6fffffffff, 0x3c5b3eee9687f28f, x2, 1840, x7)
+
+inst_253:
+// rs1_val == 0x25784F5FFFFFFFFF and rs2_val == 0xD95FD86AD2FE2E7E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x25784f5fffffffff;  op2val:0xd95fd86ad2fe2e7e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x25784f5fffffffff, 0xd95fd86ad2fe2e7e, x2, 1848, x7)
+
+inst_254:
+// rs1_val == 0x27B23DBFFFFFFFFF and rs2_val == 0xE91014A0B6D75E84 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x27b23dbfffffffff;  op2val:0xe91014a0b6d75e84
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x27b23dbfffffffff, 0xe91014a0b6d75e84, x2, 1856, x7)
+
+inst_255:
+// rs1_val == 0xD5A2037FFFFFFFFF and rs2_val == 0x01769A3C092936E8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd5a2037fffffffff;  op2val:0x1769a3c092936e8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd5a2037fffffffff, 0x1769a3c092936e8, x2, 1864, x7)
+
+inst_256:
+// rs1_val == 0xE81FDCFFFFFFFFFF and rs2_val == 0x85A300E0784ABEBB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe81fdcffffffffff;  op2val:0x85a300e0784abebb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe81fdcffffffffff, 0x85a300e0784abebb, x2, 1872, x7)
+
+inst_257:
+// rs1_val == 0xFF7745FFFFFFFFFF and rs2_val == 0x1F1BAF6A4F829B65 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xff7745ffffffffff;  op2val:0x1f1baf6a4f829b65
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xff7745ffffffffff, 0x1f1baf6a4f829b65, x2, 1880, x7)
+
+inst_258:
+// rs1_val == 0x708903FFFFFFFFFF and rs2_val == 0x86CE51BD17B8B123 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x708903ffffffffff;  op2val:0x86ce51bd17b8b123
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x708903ffffffffff, 0x86ce51bd17b8b123, x2, 1888, x7)
+
+inst_259:
+// rs1_val == 0xA4BE27FFFFFFFFFF and rs2_val == 0xB1F5D8538B16BB0D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa4be27ffffffffff;  op2val:0xb1f5d8538b16bb0d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa4be27ffffffffff, 0xb1f5d8538b16bb0d, x2, 1896, x7)
+
+inst_260:
+// rs1_val == 0x31602FFFFFFFFFFF and rs2_val == 0x2AD6072539BE2172 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x31602fffffffffff;  op2val:0x2ad6072539be2172
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x31602fffffffffff, 0x2ad6072539be2172, x2, 1904, x7)
+
+inst_261:
+// rs1_val == 0xBA4A1FFFFFFFFFFF and rs2_val == 0x5761A86691E42ACB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xba4a1fffffffffff;  op2val:0x5761a86691e42acb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xba4a1fffffffffff, 0x5761a86691e42acb, x2, 1912, x7)
+
+inst_262:
+// rs1_val == 0x7F103FFFFFFFFFFF and rs2_val == 0x09E4D1F4975A8550 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7f103fffffffffff;  op2val:0x9e4d1f4975a8550
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7f103fffffffffff, 0x9e4d1f4975a8550, x2, 1920, x7)
+
+inst_263:
+// rs1_val == 0xF8A77FFFFFFFFFFF and rs2_val == 0x9A7EF9E4B432D4F7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf8a77fffffffffff;  op2val:0x9a7ef9e4b432d4f7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf8a77fffffffffff, 0x9a7ef9e4b432d4f7, x2, 1928, x7)
+
+inst_264:
+// rs1_val == 0xDA88FFFFFFFFFFFF and rs2_val == 0xA827F5A3B76D454D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xda88ffffffffffff;  op2val:0xa827f5a3b76d454d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xda88ffffffffffff, 0xa827f5a3b76d454d, x2, 1936, x7)
+
+inst_265:
+// rs1_val == 0x2449FFFFFFFFFFFF and rs2_val == 0x59C05BB9CD9CB03A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2449ffffffffffff;  op2val:0x59c05bb9cd9cb03a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2449ffffffffffff, 0x59c05bb9cd9cb03a, x2, 1944, x7)
+
+inst_266:
+// rs1_val == 0x6C9BFFFFFFFFFFFF and rs2_val == 0xDE14BFF2EED7A24A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6c9bffffffffffff;  op2val:0xde14bff2eed7a24a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6c9bffffffffffff, 0xde14bff2eed7a24a, x2, 1952, x7)
+
+inst_267:
+// rs1_val == 0x6E27FFFFFFFFFFFF and rs2_val == 0x63C2A48F76B1FD3D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6e27ffffffffffff;  op2val:0x63c2a48f76b1fd3d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6e27ffffffffffff, 0x63c2a48f76b1fd3d, x2, 1960, x7)
+
+inst_268:
+// rs1_val == 0x31CFFFFFFFFFFFFF and rs2_val == 0x5DCF019DB3988B52 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x31cfffffffffffff;  op2val:0x5dcf019db3988b52
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x31cfffffffffffff, 0x5dcf019db3988b52, x2, 1968, x7)
+
+inst_269:
+// rs1_val == 0x215FFFFFFFFFFFFF and rs2_val == 0x90BB34803C464110 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x215fffffffffffff;  op2val:0x90bb34803c464110
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x215fffffffffffff, 0x90bb34803c464110, x2, 1976, x7)
+
+inst_270:
+// rs1_val == 0x433FFFFFFFFFFFFF and rs2_val == 0x47B7097B9B01F7CC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x433fffffffffffff;  op2val:0x47b7097b9b01f7cc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x433fffffffffffff, 0x47b7097b9b01f7cc, x2, 1984, x7)
+
+inst_271:
+// rs1_val == 0x857FFFFFFFFFFFFF and rs2_val == 0x40D90A1E5B331999 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x857fffffffffffff;  op2val:0x40d90a1e5b331999
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x857fffffffffffff, 0x40d90a1e5b331999, x2, 1992, x7)
+
+inst_272:
+// rs1_val == 0xACFFFFFFFFFFFFFF and rs2_val == 0x4B1634E12D37DE81 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xacffffffffffffff;  op2val:0x4b1634e12d37de81
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xacffffffffffffff, 0x4b1634e12d37de81, x2, 2000, x7)
+
+inst_273:
+// rs1_val == 0x6DFFFFFFFFFFFFFF and rs2_val == 0xFCB627AFBF97E520 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6dffffffffffffff;  op2val:0xfcb627afbf97e520
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6dffffffffffffff, 0xfcb627afbf97e520, x2, 2008, x7)
+
+inst_274:
+// rs1_val == 0x3BFFFFFFFFFFFFFF and rs2_val == 0xABB4DA1C6DF8CCF6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3bffffffffffffff;  op2val:0xabb4da1c6df8ccf6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3bffffffffffffff, 0xabb4da1c6df8ccf6, x2, 2016, x7)
+
+inst_275:
+// rs1_val == 0x67FFFFFFFFFFFFFF and rs2_val == 0x41B79D35E08409F0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x67ffffffffffffff;  op2val:0x41b79d35e08409f0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x67ffffffffffffff, 0x41b79d35e08409f0, x2, 2024, x7)
+
+inst_276:
+// rs1_val == 0x2FFFFFFFFFFFFFFF and rs2_val == 0xD38CADCD432FF218 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2fffffffffffffff;  op2val:0xd38cadcd432ff218
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2fffffffffffffff, 0xd38cadcd432ff218, x2, 2032, x7)
+
+inst_277:
+// rs1_val == 0xDFFFFFFFFFFFFFFF and rs2_val == 0xFE339ECA03B1D74B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdfffffffffffffff;  op2val:0xfe339eca03b1d74b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdfffffffffffffff, 0xfe339eca03b1d74b, x2, 2040, x7)
+RVTEST_SIGBASE( x2,signature_x2_1)
+
+inst_278:
+// rs1_val == 0xBFFFFFFFFFFFFFFF and rs2_val == 0x07AC5FED4B6EA010 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbfffffffffffffff;  op2val:0x7ac5fed4b6ea010
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbfffffffffffffff, 0x7ac5fed4b6ea010, x2, 0, x7)
+
+inst_279:
+// rs1_val == 0x7FFFFFFFFFFFFFFF and rs2_val == 0x2FF7C0FCBBE8F88D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7fffffffffffffff;  op2val:0x2ff7c0fcbbe8f88d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7fffffffffffffff, 0x2ff7c0fcbbe8f88d, x2, 8, x7)
+
+inst_280:
+// rs1_val == 0xFFFFFFFFFFFFFFFF and rs2_val == 0xA6EA1C0D2F8B9E9D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffff;  op2val:0xa6ea1c0d2f8b9e9d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffff, 0xa6ea1c0d2f8b9e9d, x2, 16, x7)
+
+inst_281:
+// rs2_val == 0xF192D0D741B2BB9A and rs1_val == 0x8138093C66CC59EE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8138093c66cc59ee;  op2val:0xf192d0d741b2bb9a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8138093c66cc59ee, 0xf192d0d741b2bb9a, x2, 24, x7)
+
+inst_282:
+// rs2_val == 0x5D8A9EA91D617A4D and rs1_val == 0xBD21A9561BA9A6B5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbd21a9561ba9a6b5;  op2val:0x5d8a9ea91d617a4d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbd21a9561ba9a6b5, 0x5d8a9ea91d617a4d, x2, 32, x7)
+
+inst_283:
+// rs2_val == 0x2537437FC3015FA0 and rs1_val == 0x932D823FFAE6F67D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x932d823ffae6f67d;  op2val:0x2537437fc3015fa0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x932d823ffae6f67d, 0x2537437fc3015fa0, x2, 40, x7)
+
+inst_284:
+// rs2_val == 0x17F8388BA8E61CB6 and rs1_val == 0xB3852A64369580FF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb3852a64369580ff;  op2val:0x17f8388ba8e61cb6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb3852a64369580ff, 0x17f8388ba8e61cb6, x2, 48, x7)
+
+inst_285:
+// rs2_val == 0x0DE1B9523B6B6093 and rs1_val == 0x567B159A4C8281A2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x567b159a4c8281a2;  op2val:0xde1b9523b6b6093
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x567b159a4c8281a2, 0xde1b9523b6b6093, x2, 56, x7)
+
+inst_286:
+// rs2_val == 0x07571FE602B653E5 and rs1_val == 0x9FBFCB0AE717A666 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9fbfcb0ae717a666;  op2val:0x7571fe602b653e5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9fbfcb0ae717a666, 0x7571fe602b653e5, x2, 64, x7)
+
+inst_287:
+// rs2_val == 0x037ADFD3CC1E0438 and rs1_val == 0x7805EC944D3B8462 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7805ec944d3b8462;  op2val:0x37adfd3cc1e0438
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7805ec944d3b8462, 0x37adfd3cc1e0438, x2, 72, x7)
+
+inst_288:
+// rs2_val == 0x01F2BAE567DEF006 and rs1_val == 0x2F5031F8B8FE90A6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2f5031f8b8fe90a6;  op2val:0x1f2bae567def006
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2f5031f8b8fe90a6, 0x1f2bae567def006, x2, 80, x7)
+
+inst_289:
+// rs2_val == 0x00C42276E94AE4A8 and rs1_val == 0xC3E60E906E803472 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc3e60e906e803472;  op2val:0xc42276e94ae4a8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc3e60e906e803472, 0xc42276e94ae4a8, x2, 88, x7)
+
+inst_290:
+// rs2_val == 0x007FB91691D6CEDD and rs1_val == 0x421D9B0AC32C4DA8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x421d9b0ac32c4da8;  op2val:0x7fb91691d6cedd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x421d9b0ac32c4da8, 0x7fb91691d6cedd, x2, 96, x7)
+
+inst_291:
+// rs2_val == 0x0037193EE4A7C5BA and rs1_val == 0xF088BED0A11F7657 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf088bed0a11f7657;  op2val:0x37193ee4a7c5ba
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf088bed0a11f7657, 0x37193ee4a7c5ba, x2, 104, x7)
+
+inst_292:
+// rs2_val == 0x00172F2A1844EBD2 and rs1_val == 0x03F26964CAD764C4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3f26964cad764c4;  op2val:0x172f2a1844ebd2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3f26964cad764c4, 0x172f2a1844ebd2, x2, 112, x7)
+
+inst_293:
+// rs2_val == 0x000FCB682E67A854 and rs1_val == 0x9AD8E8B131F3C57C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9ad8e8b131f3c57c;  op2val:0xfcb682e67a854
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9ad8e8b131f3c57c, 0xfcb682e67a854, x2, 120, x7)
+
+inst_294:
+// rs2_val == 0x0007044699D68912 and rs1_val == 0xD8219C9D0A76F50A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd8219c9d0a76f50a;  op2val:0x7044699d68912
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd8219c9d0a76f50a, 0x7044699d68912, x2, 128, x7)
+
+inst_295:
+// rs2_val == 0x0003DB776D2B6540 and rs1_val == 0x6E19CE135AC51CC8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6e19ce135ac51cc8;  op2val:0x3db776d2b6540
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6e19ce135ac51cc8, 0x3db776d2b6540, x2, 136, x7)
+
+inst_296:
+// rs2_val == 0x00013EF0C3C4B8A1 and rs1_val == 0x6410FF8753AAF3B7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6410ff8753aaf3b7;  op2val:0x13ef0c3c4b8a1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6410ff8753aaf3b7, 0x13ef0c3c4b8a1, x2, 144, x7)
+
+inst_297:
+// rs2_val == 0x0000AC0B226B5502 and rs1_val == 0x764A44B4AE53C374 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x764a44b4ae53c374;  op2val:0xac0b226b5502
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x764a44b4ae53c374, 0xac0b226b5502, x2, 152, x7)
+
+inst_298:
+// rs2_val == 0x000067A5ED48D09E and rs1_val == 0x946C61BC186211CB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x946c61bc186211cb;  op2val:0x67a5ed48d09e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x946c61bc186211cb, 0x67a5ed48d09e, x2, 160, x7)
+
+inst_299:
+// rs2_val == 0x000028A12C2869B7 and rs1_val == 0xFD8464202874799A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfd8464202874799a;  op2val:0x28a12c2869b7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfd8464202874799a, 0x28a12c2869b7, x2, 168, x7)
+
+inst_300:
+// rs2_val == 0x00001BF925849DE3 and rs1_val == 0x1D6D2A932F3DC554 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1d6d2a932f3dc554;  op2val:0x1bf925849de3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1d6d2a932f3dc554, 0x1bf925849de3, x2, 176, x7)
+
+inst_301:
+// rs2_val == 0x00000F99099565A3 and rs1_val == 0x9199165CE7B4B57E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9199165ce7b4b57e;  op2val:0xf99099565a3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9199165ce7b4b57e, 0xf99099565a3, x2, 184, x7)
+
+inst_302:
+// rs2_val == 0x0000044ECD872AB5 and rs1_val == 0x1B2E2CD77B692CDA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1b2e2cd77b692cda;  op2val:0x44ecd872ab5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1b2e2cd77b692cda, 0x44ecd872ab5, x2, 192, x7)
+
+inst_303:
+// rs2_val == 0x0000021380B68BE6 and rs1_val == 0xD53C269BAF88E590 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd53c269baf88e590;  op2val:0x21380b68be6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd53c269baf88e590, 0x21380b68be6, x2, 200, x7)
+
+inst_304:
+// rs2_val == 0x00000112B467FB8B and rs1_val == 0xC21668AAA2792E75 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc21668aaa2792e75;  op2val:0x112b467fb8b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc21668aaa2792e75, 0x112b467fb8b, x2, 208, x7)
+
+inst_305:
+// rs2_val == 0x000000A4E94FBD21 and rs1_val == 0x5C7FB02DF7E7A342 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5c7fb02df7e7a342;  op2val:0xa4e94fbd21
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5c7fb02df7e7a342, 0xa4e94fbd21, x2, 216, x7)
+
+inst_306:
+// rs2_val == 0x0000007518972E45 and rs1_val == 0xAEB0A94C91E4F834 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaeb0a94c91e4f834;  op2val:0x7518972e45
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaeb0a94c91e4f834, 0x7518972e45, x2, 224, x7)
+
+inst_307:
+// rs2_val == 0x0000002D671C82FC and rs1_val == 0xCC81F272AF6A3E68 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xcc81f272af6a3e68;  op2val:0x2d671c82fc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xcc81f272af6a3e68, 0x2d671c82fc, x2, 232, x7)
+
+inst_308:
+// rs2_val == 0x000000118B142F97 and rs1_val == 0x2041C033B47053DE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2041c033b47053de;  op2val:0x118b142f97
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2041c033b47053de, 0x118b142f97, x2, 240, x7)
+
+inst_309:
+// rs2_val == 0x0000000818D6084E and rs1_val == 0xF0F1D8DBD508FF34 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf0f1d8dbd508ff34;  op2val:0x818d6084e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf0f1d8dbd508ff34, 0x818d6084e, x2, 248, x7)
+
+inst_310:
+// rs2_val == 0x0000000650DD1AF1 and rs1_val == 0x426E6DDF1690A1F7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x426e6ddf1690a1f7;  op2val:0x650dd1af1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x426e6ddf1690a1f7, 0x650dd1af1, x2, 256, x7)
+
+inst_311:
+// rs2_val == 0x000000023B8F801D and rs1_val == 0xE715DFE558FC0A18 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe715dfe558fc0a18;  op2val:0x23b8f801d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe715dfe558fc0a18, 0x23b8f801d, x2, 264, x7)
+
+inst_312:
+// rs2_val == 0x0000000187951CB6 and rs1_val == 0xDB54E659962E5835 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdb54e659962e5835;  op2val:0x187951cb6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdb54e659962e5835, 0x187951cb6, x2, 272, x7)
+
+inst_313:
+// rs2_val == 0x00000000E0303F46 and rs1_val == 0xA372959988B48922 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa372959988b48922;  op2val:0xe0303f46
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa372959988b48922, 0xe0303f46, x2, 280, x7)
+
+inst_314:
+// rs2_val == 0x000000007B1BDA5E and rs1_val == 0x6FD08D91E0F48D2F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6fd08d91e0f48d2f;  op2val:0x7b1bda5e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6fd08d91e0f48d2f, 0x7b1bda5e, x2, 288, x7)
+
+inst_315:
+// rs2_val == 0x0000000031B0F86A and rs1_val == 0x1AD9C6D87FB2D83B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1ad9c6d87fb2d83b;  op2val:0x31b0f86a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1ad9c6d87fb2d83b, 0x31b0f86a, x2, 296, x7)
+
+inst_316:
+// rs2_val == 0x000000001CDE8A08 and rs1_val == 0x05D54CB2FA2F0AFD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5d54cb2fa2f0afd;  op2val:0x1cde8a08
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5d54cb2fa2f0afd, 0x1cde8a08, x2, 304, x7)
+
+inst_317:
+// rs2_val == 0x000000000BCE1A9C and rs1_val == 0x9E2E5BE56B66EC95 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9e2e5be56b66ec95;  op2val:0xbce1a9c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9e2e5be56b66ec95, 0xbce1a9c, x2, 312, x7)
+
+inst_318:
+// rs2_val == 0x0000000006A1096C and rs1_val == 0x866534CD79FE0C5F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x866534cd79fe0c5f;  op2val:0x6a1096c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x866534cd79fe0c5f, 0x6a1096c, x2, 320, x7)
+
+inst_319:
+// rs2_val == 0x0000000003211CB3 and rs1_val == 0x56F552452080F2AC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x56f552452080f2ac;  op2val:0x3211cb3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x56f552452080f2ac, 0x3211cb3, x2, 328, x7)
+
+inst_320:
+// rs2_val == 0x0000000001E48237 and rs1_val == 0x44EB31E46776FD34 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x44eb31e46776fd34;  op2val:0x1e48237
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x44eb31e46776fd34, 0x1e48237, x2, 336, x7)
+
+inst_321:
+// rs2_val == 0x0000000000B0FBCE and rs1_val == 0x7DB4D3B51F36DDF8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7db4d3b51f36ddf8;  op2val:0xb0fbce
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7db4d3b51f36ddf8, 0xb0fbce, x2, 344, x7)
+
+inst_322:
+// rs2_val == 0x00000000005516A9 and rs1_val == 0x3372969F7F65D54D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3372969f7f65d54d;  op2val:0x5516a9
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3372969f7f65d54d, 0x5516a9, x2, 352, x7)
+
+inst_323:
+// rs2_val == 0x000000000021BF99 and rs1_val == 0xA38D0F398FC0819E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa38d0f398fc0819e;  op2val:0x21bf99
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa38d0f398fc0819e, 0x21bf99, x2, 360, x7)
+
+inst_324:
+// rs2_val == 0x00000000001F99DE and rs1_val == 0xB06670AAF2FBC7F9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb06670aaf2fbc7f9;  op2val:0x1f99de
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb06670aaf2fbc7f9, 0x1f99de, x2, 368, x7)
+
+inst_325:
+// rs2_val == 0x00000000000BEEC1 and rs1_val == 0x23F7D227EA7F7301 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x23f7d227ea7f7301;  op2val:0xbeec1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x23f7d227ea7f7301, 0xbeec1, x2, 376, x7)
+
+inst_326:
+// rs2_val == 0x0000000000079DD3 and rs1_val == 0x887AAE6A2C42EEAC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x887aae6a2c42eeac;  op2val:0x79dd3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x887aae6a2c42eeac, 0x79dd3, x2, 384, x7)
+
+inst_327:
+// rs2_val == 0x0000000000035BC3 and rs1_val == 0x106607DCDE17B009 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x106607dcde17b009;  op2val:0x35bc3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x106607dcde17b009, 0x35bc3, x2, 392, x7)
+
+inst_328:
+// rs2_val == 0x000000000001DB50 and rs1_val == 0xC4AAF35A6BE1FCDE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc4aaf35a6be1fcde;  op2val:0x1db50
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc4aaf35a6be1fcde, 0x1db50, x2, 400, x7)
+
+inst_329:
+// rs2_val == 0x000000000000C1F1 and rs1_val == 0x0981ABB61530959B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x981abb61530959b;  op2val:0xc1f1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x981abb61530959b, 0xc1f1, x2, 408, x7)
+
+inst_330:
+// rs2_val == 0x0000000000004632 and rs1_val == 0xDB14A009B7E06D03 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdb14a009b7e06d03;  op2val:0x4632
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdb14a009b7e06d03, 0x4632, x2, 416, x7)
+
+inst_331:
+// rs2_val == 0x0000000000003CDC and rs1_val == 0xEEA93B6FCA71067B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xeea93b6fca71067b;  op2val:0x3cdc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xeea93b6fca71067b, 0x3cdc, x2, 424, x7)
+
+inst_332:
+// rs2_val == 0x0000000000001AD8 and rs1_val == 0xFA342B15167CD62E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfa342b15167cd62e;  op2val:0x1ad8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfa342b15167cd62e, 0x1ad8, x2, 432, x7)
+
+inst_333:
+// rs2_val == 0x0000000000000E5E and rs1_val == 0xB7B8B1A0EC9A5DC8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb7b8b1a0ec9a5dc8;  op2val:0xe5e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb7b8b1a0ec9a5dc8, 0xe5e, x2, 440, x7)
+
+inst_334:
+// rs2_val == 0x0000000000000456 and rs1_val == 0x3473F51FFB7A3B3B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3473f51ffb7a3b3b;  op2val:0x456
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3473f51ffb7a3b3b, 0x456, x2, 448, x7)
+
+inst_335:
+// rs2_val == 0x0000000000000216 and rs1_val == 0x57D53E43F1BAE498 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x57d53e43f1bae498;  op2val:0x216
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x57d53e43f1bae498, 0x216, x2, 456, x7)
+
+inst_336:
+// rs2_val == 0x000000000000014D and rs1_val == 0x2141C6D163522556 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2141c6d163522556;  op2val:0x14d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2141c6d163522556, 0x14d, x2, 464, x7)
+
+inst_337:
+// rs2_val == 0x00000000000000AD and rs1_val == 0xE7FF25B9B3257DDA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe7ff25b9b3257dda;  op2val:0xad
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe7ff25b9b3257dda, 0xad, x2, 472, x7)
+
+inst_338:
+// rs2_val == 0x0000000000000042 and rs1_val == 0x28C0D4AEC196C5C2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x28c0d4aec196c5c2;  op2val:0x42
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x28c0d4aec196c5c2, 0x42, x2, 480, x7)
+
+inst_339:
+// rs2_val == 0x0000000000000032 and rs1_val == 0x0942C3FBB6D3E879 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x942c3fbb6d3e879;  op2val:0x32
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x942c3fbb6d3e879, 0x32, x2, 488, x7)
+
+inst_340:
+// rs2_val == 0x000000000000001E and rs1_val == 0x418BFBB079A2ED17 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x418bfbb079a2ed17;  op2val:0x1e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x418bfbb079a2ed17, 0x1e, x2, 496, x7)
+
+inst_341:
+// rs2_val == 0x000000000000000D and rs1_val == 0xAF3AEAA313F5BC90 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaf3aeaa313f5bc90;  op2val:0xd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaf3aeaa313f5bc90, 0xd, x2, 504, x7)
+
+inst_342:
+// rs2_val == 0x0000000000000004 and rs1_val == 0x1D849E2BA111F5FB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1d849e2ba111f5fb;  op2val:0x4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1d849e2ba111f5fb, 0x4, x2, 512, x7)
+
+inst_343:
+// rs2_val == 0x0000000000000003 and rs1_val == 0x44339C10D4652689 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x44339c10d4652689;  op2val:0x3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x44339c10d4652689, 0x3, x2, 520, x7)
+
+inst_344:
+// rs2_val == 0x0000000000000001 and rs1_val == 0x746FE5B967BA7848 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x746fe5b967ba7848;  op2val:0x1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x746fe5b967ba7848, 0x1, x2, 528, x7)
+
+inst_345:
+// rs2_val == 0x0000000000000000 and rs1_val == 0x9064DBD9CAA0A141 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9064dbd9caa0a141;  op2val:0x0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9064dbd9caa0a141, 0x0, x2, 536, x7)
+
+inst_346:
+// rs1_val == 0x880F73BBD42779F6 and rs2_val == 0x9211A8D847F439F3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x880f73bbd42779f6;  op2val:0x9211a8d847f439f3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x880f73bbd42779f6, 0x9211a8d847f439f3, x2, 544, x7)
+
+inst_347:
+// rs1_val == 0x6030130961EEAC38 and rs2_val == 0x520235BC73D58E1C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6030130961eeac38;  op2val:0x520235bc73d58e1c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6030130961eeac38, 0x520235bc73d58e1c, x2, 552, x7)
+
+inst_348:
+// rs1_val == 0x2CFCC3964671120E and rs2_val == 0xD4B59C0536CDF8A1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2cfcc3964671120e;  op2val:0xd4b59c0536cdf8a1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2cfcc3964671120e, 0xd4b59c0536cdf8a1, x2, 560, x7)
+
+inst_349:
+// rs1_val == 0x1B4C0859D26542EF and rs2_val == 0x735DC3271CE262D6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1b4c0859d26542ef;  op2val:0x735dc3271ce262d6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1b4c0859d26542ef, 0x735dc3271ce262d6, x2, 568, x7)
+
+inst_350:
+// rs1_val == 0x086B6A04B6125E0D and rs2_val == 0xFAF8DFCDF33335B6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x86b6a04b6125e0d;  op2val:0xfaf8dfcdf33335b6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x86b6a04b6125e0d, 0xfaf8dfcdf33335b6, x2, 576, x7)
+
+inst_351:
+// rs1_val == 0x06720C5422DC73AC and rs2_val == 0xD945BBF3E5498256 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6720c5422dc73ac;  op2val:0xd945bbf3e5498256
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6720c5422dc73ac, 0xd945bbf3e5498256, x2, 584, x7)
+
+inst_352:
+// rs1_val == 0x02D51BFFE1594DC5 and rs2_val == 0x51054839EBB9C596 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2d51bffe1594dc5;  op2val:0x51054839ebb9c596
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2d51bffe1594dc5, 0x51054839ebb9c596, x2, 592, x7)
+
+inst_353:
+// rs1_val == 0x01554174CDC02ECE and rs2_val == 0xEA0A668AC12F694D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1554174cdc02ece;  op2val:0xea0a668ac12f694d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1554174cdc02ece, 0xea0a668ac12f694d, x2, 600, x7)
+
+inst_354:
+// rs1_val == 0x00A746A4AA785C62 and rs2_val == 0xA2592B9D32D1464E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa746a4aa785c62;  op2val:0xa2592b9d32d1464e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa746a4aa785c62, 0xa2592b9d32d1464e, x2, 608, x7)
+
+inst_355:
+// rs1_val == 0x005A629624AA1735 and rs2_val == 0x53B3B0FF3DD1E044 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5a629624aa1735;  op2val:0x53b3b0ff3dd1e044
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5a629624aa1735, 0x53b3b0ff3dd1e044, x2, 616, x7)
+
+inst_356:
+// rs1_val == 0x00260FDDF517E383 and rs2_val == 0x5E320F4A02E50777 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x260fddf517e383;  op2val:0x5e320f4a02e50777
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x260fddf517e383, 0x5e320f4a02e50777, x2, 624, x7)
+
+inst_357:
+// rs1_val == 0x00159ECB99EDD4D2 and rs2_val == 0x05B4D7567B1FFC6A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x159ecb99edd4d2;  op2val:0x5b4d7567b1ffc6a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x159ecb99edd4d2, 0x5b4d7567b1ffc6a, x2, 632, x7)
+
+inst_358:
+// rs1_val == 0x000DC63D84C955F2 and rs2_val == 0x07A04E6483B852D7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdc63d84c955f2;  op2val:0x7a04e6483b852d7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdc63d84c955f2, 0x7a04e6483b852d7, x2, 640, x7)
+
+inst_359:
+// rs1_val == 0x0006690070C61509 and rs2_val == 0x8A8F7AEFD69F6B16 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6690070c61509;  op2val:0x8a8f7aefd69f6b16
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6690070c61509, 0x8a8f7aefd69f6b16, x2, 648, x7)
+
+inst_360:
+// rs1_val == 0x0002B3DBBA6BC77D and rs2_val == 0x94B953EDB1B43D07 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2b3dbba6bc77d;  op2val:0x94b953edb1b43d07
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2b3dbba6bc77d, 0x94b953edb1b43d07, x2, 656, x7)
+
+inst_361:
+// rs1_val == 0x0001BC4414881EDD and rs2_val == 0xE13A099641D812CD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1bc4414881edd;  op2val:0xe13a099641d812cd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1bc4414881edd, 0xe13a099641d812cd, x2, 664, x7)
+
+inst_362:
+// rs1_val == 0x0000F1B26111B4B6 and rs2_val == 0x9BDEB398032FBCE3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf1b26111b4b6;  op2val:0x9bdeb398032fbce3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf1b26111b4b6, 0x9bdeb398032fbce3, x2, 672, x7)
+
+inst_363:
+// rs1_val == 0x0000676692A38329 and rs2_val == 0xA98A372E9FFD6A18 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x676692a38329;  op2val:0xa98a372e9ffd6a18
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x676692a38329, 0xa98a372e9ffd6a18, x2, 680, x7)
+
+inst_364:
+// rs1_val == 0x0000239D5A11CCA6 and rs2_val == 0xDD0C8B9407BFC096 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x239d5a11cca6;  op2val:0xdd0c8b9407bfc096
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x239d5a11cca6, 0xdd0c8b9407bfc096, x2, 688, x7)
+
+inst_365:
+// rs1_val == 0x00001FA08BCCE7CE and rs2_val == 0xEA3D9BE7F6A00758 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1fa08bcce7ce;  op2val:0xea3d9be7f6a00758
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1fa08bcce7ce, 0xea3d9be7f6a00758, x2, 696, x7)
+
+inst_366:
+// rs1_val == 0x00000C1FBB01EA76 and rs2_val == 0x13446DF8128AE84A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc1fbb01ea76;  op2val:0x13446df8128ae84a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc1fbb01ea76, 0x13446df8128ae84a, x2, 704, x7)
+
+inst_367:
+// rs1_val == 0x000006E3F6782942 and rs2_val == 0x7B73CCF813284C79 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6e3f6782942;  op2val:0x7b73ccf813284c79
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6e3f6782942, 0x7b73ccf813284c79, x2, 712, x7)
+
+inst_368:
+// rs1_val == 0x000002FA798C06FF and rs2_val == 0xB372C56B5B8349CE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2fa798c06ff;  op2val:0xb372c56b5b8349ce
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2fa798c06ff, 0xb372c56b5b8349ce, x2, 720, x7)
+
+inst_369:
+// rs1_val == 0x0000012BA82CB2CE and rs2_val == 0xEC7038C908FB09A0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x12ba82cb2ce;  op2val:0xec7038c908fb09a0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x12ba82cb2ce, 0xec7038c908fb09a0, x2, 728, x7)
+
+inst_370:
+// rs1_val == 0x000000AA236EBA20 and rs2_val == 0xFB019DF47349DBC4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaa236eba20;  op2val:0xfb019df47349dbc4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaa236eba20, 0xfb019df47349dbc4, x2, 736, x7)
+
+inst_371:
+// rs1_val == 0x0000004A482EA761 and rs2_val == 0x1799E72821AF214A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4a482ea761;  op2val:0x1799e72821af214a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4a482ea761, 0x1799e72821af214a, x2, 744, x7)
+
+inst_372:
+// rs1_val == 0x000000287219C1DB and rs2_val == 0x0BEDDB070F7A0443 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x287219c1db;  op2val:0xbeddb070f7a0443
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x287219c1db, 0xbeddb070f7a0443, x2, 752, x7)
+
+inst_373:
+// rs1_val == 0x00000015BFBD7D15 and rs2_val == 0x44E9E4A511B41900 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x15bfbd7d15;  op2val:0x44e9e4a511b41900
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x15bfbd7d15, 0x44e9e4a511b41900, x2, 760, x7)
+
+inst_374:
+// rs1_val == 0x0000000E47BC7549 and rs2_val == 0xEA3A0683EAD81DCD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe47bc7549;  op2val:0xea3a0683ead81dcd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe47bc7549, 0xea3a0683ead81dcd, x2, 768, x7)
+
+inst_375:
+// rs1_val == 0x000000063A782EBC and rs2_val == 0x9D42F6709DA9B14D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x63a782ebc;  op2val:0x9d42f6709da9b14d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x63a782ebc, 0x9d42f6709da9b14d, x2, 776, x7)
+
+inst_376:
+// rs1_val == 0x000000024B1E943F and rs2_val == 0x119B4FE5FA285A0D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x24b1e943f;  op2val:0x119b4fe5fa285a0d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x24b1e943f, 0x119b4fe5fa285a0d, x2, 784, x7)
+
+inst_377:
+// rs1_val == 0x000000016BBA8D22 and rs2_val == 0x98B20411E7A28CBD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x16bba8d22;  op2val:0x98b20411e7a28cbd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x16bba8d22, 0x98b20411e7a28cbd, x2, 792, x7)
+
+inst_378:
+// rs1_val == 0x00000000BD0840FC and rs2_val == 0x64409DDBB45F51C3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbd0840fc;  op2val:0x64409ddbb45f51c3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbd0840fc, 0x64409ddbb45f51c3, x2, 800, x7)
+
+inst_379:
+// rs1_val == 0x000000005BEA8594 and rs2_val == 0xF6724BA08329C05B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5bea8594;  op2val:0xf6724ba08329c05b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5bea8594, 0xf6724ba08329c05b, x2, 808, x7)
+
+inst_380:
+// rs1_val == 0x000000003A8137EA and rs2_val == 0x0C2282666BE49EE7 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3a8137ea;  op2val:0xc2282666be49ee7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3a8137ea, 0xc2282666be49ee7, x2, 816, x7)
+
+inst_381:
+// rs1_val == 0x000000001891DD3D and rs2_val == 0xE1D7300F6361B9F8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1891dd3d;  op2val:0xe1d7300f6361b9f8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1891dd3d, 0xe1d7300f6361b9f8, x2, 824, x7)
+
+inst_382:
+// rs1_val == 0x000000000BF8670E and rs2_val == 0xB9B338EB3FDF2348 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbf8670e;  op2val:0xb9b338eb3fdf2348
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbf8670e, 0xb9b338eb3fdf2348, x2, 832, x7)
+
+inst_383:
+// rs1_val == 0x000000000711EB58 and rs2_val == 0xA2F7647A952E1B8B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x711eb58;  op2val:0xa2f7647a952e1b8b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x711eb58, 0xa2f7647a952e1b8b, x2, 840, x7)
+
+inst_384:
+// rs1_val == 0x00000000028DD9F4 and rs2_val == 0x12CA3F7062DC08D6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x28dd9f4;  op2val:0x12ca3f7062dc08d6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x28dd9f4, 0x12ca3f7062dc08d6, x2, 848, x7)
+
+inst_385:
+// rs1_val == 0x00000000011E7A61 and rs2_val == 0x9C3ECB54C5CEFDD8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x11e7a61;  op2val:0x9c3ecb54c5cefdd8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x11e7a61, 0x9c3ecb54c5cefdd8, x2, 856, x7)
+
+inst_386:
+// rs1_val == 0x0000000000C793F6 and rs2_val == 0x36971E1B2577C1EC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc793f6;  op2val:0x36971e1b2577c1ec
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc793f6, 0x36971e1b2577c1ec, x2, 864, x7)
+
+inst_387:
+// rs1_val == 0x0000000000736008 and rs2_val == 0x93B3A3D9A44F576A 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x736008;  op2val:0x93b3a3d9a44f576a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x736008, 0x93b3a3d9a44f576a, x2, 872, x7)
+
+inst_388:
+// rs1_val == 0x000000000034106A and rs2_val == 0x050684BFE286852C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x34106a;  op2val:0x50684bfe286852c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x34106a, 0x50684bfe286852c, x2, 880, x7)
+
+inst_389:
+// rs1_val == 0x00000000001A83B3 and rs2_val == 0x65151C401DD377BF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1a83b3;  op2val:0x65151c401dd377bf
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1a83b3, 0x65151c401dd377bf, x2, 888, x7)
+
+inst_390:
+// rs1_val == 0x0000000000099A1F and rs2_val == 0x21870F0BC4FF64DE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x99a1f;  op2val:0x21870f0bc4ff64de
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x99a1f, 0x21870f0bc4ff64de, x2, 896, x7)
+
+inst_391:
+// rs1_val == 0x00000000000700AF and rs2_val == 0x0F552C9402CDF2AF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x700af;  op2val:0xf552c9402cdf2af
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x700af, 0xf552c9402cdf2af, x2, 904, x7)
+
+inst_392:
+// rs1_val == 0x000000000002F165 and rs2_val == 0x2274EA181E34B3F1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2f165;  op2val:0x2274ea181e34b3f1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2f165, 0x2274ea181e34b3f1, x2, 912, x7)
+
+inst_393:
+// rs1_val == 0x0000000000016F3F and rs2_val == 0xF6CDB2F803E0D681 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x16f3f;  op2val:0xf6cdb2f803e0d681
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x16f3f, 0xf6cdb2f803e0d681, x2, 920, x7)
+
+inst_394:
+// rs1_val == 0x000000000000B80F and rs2_val == 0x563E9BED45100358 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb80f;  op2val:0x563e9bed45100358
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb80f, 0x563e9bed45100358, x2, 928, x7)
+
+inst_395:
+// rs1_val == 0x0000000000004DAA and rs2_val == 0x6B77730F65BD9ACB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x4daa;  op2val:0x6b77730f65bd9acb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x4daa, 0x6b77730f65bd9acb, x2, 936, x7)
+
+inst_396:
+// rs1_val == 0x0000000000002242 and rs2_val == 0x785116080D650372 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2242;  op2val:0x785116080d650372
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2242, 0x785116080d650372, x2, 944, x7)
+
+inst_397:
+// rs1_val == 0x0000000000001AAB and rs2_val == 0x36A80BDF0023B682 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1aab;  op2val:0x36a80bdf0023b682
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1aab, 0x36a80bdf0023b682, x2, 952, x7)
+
+inst_398:
+// rs1_val == 0x0000000000000A12 and rs2_val == 0x4A789CB3D8B9B45C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa12;  op2val:0x4a789cb3d8b9b45c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa12, 0x4a789cb3d8b9b45c, x2, 960, x7)
+
+inst_399:
+// rs1_val == 0x000000000000065B and rs2_val == 0xC42B7170902A174F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x65b;  op2val:0xc42b7170902a174f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x65b, 0xc42b7170902a174f, x2, 968, x7)
+
+inst_400:
+// rs1_val == 0x00000000000003FD and rs2_val == 0x834C687A3ACB6266 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3fd;  op2val:0x834c687a3acb6266
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3fd, 0x834c687a3acb6266, x2, 976, x7)
+
+inst_401:
+// rs1_val == 0x0000000000000191 and rs2_val == 0xB53302FC154CD2AA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x191;  op2val:0xb53302fc154cd2aa
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x191, 0xb53302fc154cd2aa, x2, 984, x7)
+
+inst_402:
+// rs1_val == 0x00000000000000AA and rs2_val == 0x15C1D2DFA9964AEF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaa;  op2val:0x15c1d2dfa9964aef
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaa, 0x15c1d2dfa9964aef, x2, 992, x7)
+
+inst_403:
+// rs1_val == 0x0000000000000079 and rs2_val == 0xA3EA284D3BD03346 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x79;  op2val:0xa3ea284d3bd03346
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x79, 0xa3ea284d3bd03346, x2, 1000, x7)
+
+inst_404:
+// rs1_val == 0x0000000000000026 and rs2_val == 0x76C468AEC7321CC0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x26;  op2val:0x76c468aec7321cc0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x26, 0x76c468aec7321cc0, x2, 1008, x7)
+
+inst_405:
+// rs1_val == 0x0000000000000014 and rs2_val == 0xE12B2B8F30B17D0B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x14;  op2val:0xe12b2b8f30b17d0b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x14, 0xe12b2b8f30b17d0b, x2, 1016, x7)
+
+inst_406:
+// rs1_val == 0x000000000000000F and rs2_val == 0x8743FEB6D4EA65D0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf;  op2val:0x8743feb6d4ea65d0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf, 0x8743feb6d4ea65d0, x2, 1024, x7)
+
+inst_407:
+// rs1_val == 0x0000000000000007 and rs2_val == 0xA66B0D389D95847E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7;  op2val:0xa66b0d389d95847e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7, 0xa66b0d389d95847e, x2, 1032, x7)
+
+inst_408:
+// rs1_val == 0x0000000000000002 and rs2_val == 0x2FA91425CB008853 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2;  op2val:0x2fa91425cb008853
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2, 0x2fa91425cb008853, x2, 1040, x7)
+
+inst_409:
+// rs1_val == 0x0000000000000001 and rs2_val == 0x309D6B79965EDA32 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1;  op2val:0x309d6b79965eda32
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1, 0x309d6b79965eda32, x2, 1048, x7)
+
+inst_410:
+// rs1_val == 0x0000000000000000 and rs2_val == 0x7734D7C1C7FDE805 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x0;  op2val:0x7734d7c1c7fde805
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x0, 0x7734d7c1c7fde805, x2, 1056, x7)
+
+inst_411:
+// rs2_val == 0x2DC86F6D7443F200 and rs1_val == 0x2BB9DAA6AA01E126 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2bb9daa6aa01e126;  op2val:0x2dc86f6d7443f200
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2bb9daa6aa01e126, 0x2dc86f6d7443f200, x2, 1064, x7)
+
+inst_412:
+// rs2_val == 0xB2DE7072DAB0001E and rs1_val == 0xF01528EC3591DB10 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf01528ec3591db10;  op2val:0xb2de7072dab0001e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf01528ec3591db10, 0xb2de7072dab0001e, x2, 1072, x7)
+
+inst_413:
+// rs2_val == 0xDABFC6D78901096D and rs1_val == 0x74A8EAEC656224E9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x74a8eaec656224e9;  op2val:0xdabfc6d78901096d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x74a8eaec656224e9, 0xdabfc6d78901096d, x2, 1080, x7)
+
+inst_414:
+// rs2_val == 0xE3FF5EC4DCF0C656 and rs1_val == 0xFCC1650F30D268BD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfcc1650f30d268bd;  op2val:0xe3ff5ec4dcf0c656
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfcc1650f30d268bd, 0xe3ff5ec4dcf0c656, x2, 1088, x7)
+
+inst_415:
+// rs2_val == 0xF7FE676EB828FD34 and rs1_val == 0x61D4C262D69F32E6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x61d4c262d69f32e6;  op2val:0xf7fe676eb828fd34
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x61d4c262d69f32e6, 0xf7fe676eb828fd34, x2, 1096, x7)
+
+inst_416:
+// rs2_val == 0xFBDE6F8E2D79E311 and rs1_val == 0xBEE2EE6EF38E735F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xbee2ee6ef38e735f;  op2val:0xfbde6f8e2d79e311
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xbee2ee6ef38e735f, 0xfbde6f8e2d79e311, x2, 1104, x7)
+
+inst_417:
+// rs2_val == 0xFD5D359F1A5928F7 and rs1_val == 0x6D80FEEE74BC1570 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6d80feee74bc1570;  op2val:0xfd5d359f1a5928f7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6d80feee74bc1570, 0xfd5d359f1a5928f7, x2, 1112, x7)
+
+inst_418:
+// rs2_val == 0xFEB171E36F6DA856 and rs1_val == 0xEFB5B593B918B7FA 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xefb5b593b918b7fa;  op2val:0xfeb171e36f6da856
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xefb5b593b918b7fa, 0xfeb171e36f6da856, x2, 1120, x7)
+
+inst_419:
+// rs2_val == 0xFF4F4D100880B668 and rs1_val == 0xEE412DA70282F24D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xee412da70282f24d;  op2val:0xff4f4d100880b668
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xee412da70282f24d, 0xff4f4d100880b668, x2, 1128, x7)
+
+inst_420:
+// rs2_val == 0xFFA80C91E9E678BB and rs1_val == 0x09322235B8B00CB6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9322235b8b00cb6;  op2val:0xffa80c91e9e678bb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9322235b8b00cb6, 0xffa80c91e9e678bb, x2, 1136, x7)
+
+inst_421:
+// rs2_val == 0xFFDB13919C23BDB8 and rs1_val == 0xC9763989EB74F8BB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc9763989eb74f8bb;  op2val:0xffdb13919c23bdb8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc9763989eb74f8bb, 0xffdb13919c23bdb8, x2, 1144, x7)
+
+inst_422:
+// rs2_val == 0xFFE25182F83106C9 and rs1_val == 0x0C64D280859B4C3F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc64d280859b4c3f;  op2val:0xffe25182f83106c9
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc64d280859b4c3f, 0xffe25182f83106c9, x2, 1152, x7)
+
+inst_423:
+// rs2_val == 0xFFF0FFC40E22C1E0 and rs1_val == 0xAC79FC270DA5F55F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xac79fc270da5f55f;  op2val:0xfff0ffc40e22c1e0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xac79fc270da5f55f, 0xfff0ffc40e22c1e0, x2, 1160, x7)
+
+inst_424:
+// rs2_val == 0xFFF8E49CE41BA01B and rs1_val == 0x513EE651F044106F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x513ee651f044106f;  op2val:0xfff8e49ce41ba01b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x513ee651f044106f, 0xfff8e49ce41ba01b, x2, 1168, x7)
+
+inst_425:
+// rs2_val == 0xFFFCD94D8514F49D and rs1_val == 0x612FAF5E8E73758E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x612faf5e8e73758e;  op2val:0xfffcd94d8514f49d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x612faf5e8e73758e, 0xfffcd94d8514f49d, x2, 1176, x7)
+
+inst_426:
+// rs2_val == 0xFFFEE5CEB3B2FA55 and rs1_val == 0x36334245FB566E3E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x36334245fb566e3e;  op2val:0xfffee5ceb3b2fa55
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x36334245fb566e3e, 0xfffee5ceb3b2fa55, x2, 1184, x7)
+
+inst_427:
+// rs2_val == 0xFFFF34A37D61CE76 and rs1_val == 0x2A9CC14F63ADCDBB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2a9cc14f63adcdbb;  op2val:0xffff34a37d61ce76
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2a9cc14f63adcdbb, 0xffff34a37d61ce76, x2, 1192, x7)
+
+inst_428:
+// rs2_val == 0xFFFFB7E981B4D2D8 and rs1_val == 0x279EE9737825D0F4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x279ee9737825d0f4;  op2val:0xffffb7e981b4d2d8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x279ee9737825d0f4, 0xffffb7e981b4d2d8, x2, 1200, x7)
+
+inst_429:
+// rs2_val == 0xFFFFC1B69BFA3293 and rs1_val == 0x2DD60261C5F0A710 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2dd60261c5f0a710;  op2val:0xffffc1b69bfa3293
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2dd60261c5f0a710, 0xffffc1b69bfa3293, x2, 1208, x7)
+
+inst_430:
+// rs2_val == 0xFFFFEB07E778555D and rs1_val == 0x071C80A02407E26D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x71c80a02407e26d;  op2val:0xffffeb07e778555d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x71c80a02407e26d, 0xffffeb07e778555d, x2, 1216, x7)
+
+inst_431:
+// rs2_val == 0xFFFFF54D4CAE8B6C and rs1_val == 0x76B4A3DDD9E0E7FE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x76b4a3ddd9e0e7fe;  op2val:0xfffff54d4cae8b6c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x76b4a3ddd9e0e7fe, 0xfffff54d4cae8b6c, x2, 1224, x7)
+
+inst_432:
+// rs2_val == 0xFFFFF905DBC1F2B1 and rs1_val == 0x1D95CDB0B5C06C9D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1d95cdb0b5c06c9d;  op2val:0xfffff905dbc1f2b1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1d95cdb0b5c06c9d, 0xfffff905dbc1f2b1, x2, 1232, x7)
+
+inst_433:
+// rs2_val == 0xFFFFFCC036C35DC6 and rs1_val == 0x6B3D9C59D788D65B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6b3d9c59d788d65b;  op2val:0xfffffcc036c35dc6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6b3d9c59d788d65b, 0xfffffcc036c35dc6, x2, 1240, x7)
+
+inst_434:
+// rs2_val == 0xFFFFFE5BA2465D2A and rs1_val == 0x891B827336015D9B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x891b827336015d9b;  op2val:0xfffffe5ba2465d2a
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x891b827336015d9b, 0xfffffe5ba2465d2a, x2, 1248, x7)
+
+inst_435:
+// rs2_val == 0xFFFFFF0FCF4C7D09 and rs1_val == 0xB68A272A255C09E0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb68a272a255c09e0;  op2val:0xffffff0fcf4c7d09
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb68a272a255c09e0, 0xffffff0fcf4c7d09, x2, 1256, x7)
+
+inst_436:
+// rs2_val == 0xFFFFFF8D49AAE370 and rs1_val == 0xCE80F7B19E49C4A1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xce80f7b19e49c4a1;  op2val:0xffffff8d49aae370
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xce80f7b19e49c4a1, 0xffffff8d49aae370, x2, 1264, x7)
+
+inst_437:
+// rs2_val == 0xFFFFFFDF2752AA64 and rs1_val == 0x897D9FC51AC24829 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x897d9fc51ac24829;  op2val:0xffffffdf2752aa64
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x897d9fc51ac24829, 0xffffffdf2752aa64, x2, 1272, x7)
+
+inst_438:
+// rs2_val == 0xFFFFFFEE40D0E5E8 and rs1_val == 0x75F32B5017550D1C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x75f32b5017550d1c;  op2val:0xffffffee40d0e5e8
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x75f32b5017550d1c, 0xffffffee40d0e5e8, x2, 1280, x7)
+
+inst_439:
+// rs2_val == 0xFFFFFFF3A0A1C6F0 and rs1_val == 0x239853F9120FF957 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x239853f9120ff957;  op2val:0xfffffff3a0a1c6f0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x239853f9120ff957, 0xfffffff3a0a1c6f0, x2, 1288, x7)
+
+inst_440:
+// rs2_val == 0xFFFFFFFA748CA591 and rs1_val == 0x08D6920B2F8D1335 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x8d6920b2f8d1335;  op2val:0xfffffffa748ca591
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x8d6920b2f8d1335, 0xfffffffa748ca591, x2, 1296, x7)
+
+inst_441:
+// rs2_val == 0xFFFFFFFC9FC745D1 and rs1_val == 0x94038F336056F5E8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x94038f336056f5e8;  op2val:0xfffffffc9fc745d1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x94038f336056f5e8, 0xfffffffc9fc745d1, x2, 1304, x7)
+
+inst_442:
+// rs2_val == 0xFFFFFFFEA97CBF85 and rs1_val == 0xA9632E3DBD0070AE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa9632e3dbd0070ae;  op2val:0xfffffffea97cbf85
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa9632e3dbd0070ae, 0xfffffffea97cbf85, x2, 1312, x7)
+
+inst_443:
+// rs2_val == 0xFFFFFFFF1FE84EBD and rs1_val == 0x1141B67F62A12347 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1141b67f62a12347;  op2val:0xffffffff1fe84ebd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1141b67f62a12347, 0xffffffff1fe84ebd, x2, 1320, x7)
+
+inst_444:
+// rs2_val == 0xFFFFFFFFAF8957F9 and rs1_val == 0xFAA97965C478EF2D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfaa97965c478ef2d;  op2val:0xffffffffaf8957f9
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfaa97965c478ef2d, 0xffffffffaf8957f9, x2, 1328, x7)
+
+inst_445:
+// rs2_val == 0xFFFFFFFFC165F0F1 and rs1_val == 0xD6AC851F07155A89 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd6ac851f07155a89;  op2val:0xffffffffc165f0f1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd6ac851f07155a89, 0xffffffffc165f0f1, x2, 1336, x7)
+
+inst_446:
+// rs2_val == 0xFFFFFFFFEFADEA82 and rs1_val == 0x07F5E51DC2CC1D38 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x7f5e51dc2cc1d38;  op2val:0xffffffffefadea82
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x7f5e51dc2cc1d38, 0xffffffffefadea82, x2, 1344, x7)
+
+inst_447:
+// rs2_val == 0xFFFFFFFFF7FCC18C and rs1_val == 0x9875BAD195A6BEA9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9875bad195a6bea9;  op2val:0xfffffffff7fcc18c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9875bad195a6bea9, 0xfffffffff7fcc18c, x2, 1352, x7)
+
+inst_448:
+// rs2_val == 0xFFFFFFFFF8D3E5F5 and rs1_val == 0x339863C4D216EEA8 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x339863c4d216eea8;  op2val:0xfffffffff8d3e5f5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x339863c4d216eea8, 0xfffffffff8d3e5f5, x2, 1360, x7)
+
+inst_449:
+// rs2_val == 0xFFFFFFFFFC15B0F7 and rs1_val == 0xC988A7CCFC9A02B1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc988a7ccfc9a02b1;  op2val:0xfffffffffc15b0f7
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc988a7ccfc9a02b1, 0xfffffffffc15b0f7, x2, 1368, x7)
+
+inst_450:
+// rs2_val == 0xFFFFFFFFFEAC3217 and rs1_val == 0x5BC1C3660C20B9EE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5bc1c3660c20b9ee;  op2val:0xfffffffffeac3217
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5bc1c3660c20b9ee, 0xfffffffffeac3217, x2, 1376, x7)
+
+inst_451:
+// rs2_val == 0xFFFFFFFFFF5BA80C and rs1_val == 0x132A717606AEC150 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x132a717606aec150;  op2val:0xffffffffff5ba80c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x132a717606aec150, 0xffffffffff5ba80c, x2, 1384, x7)
+
+inst_452:
+// rs2_val == 0xFFFFFFFFFF87984F and rs1_val == 0x498DB88F37C4C6B9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x498db88f37c4c6b9;  op2val:0xffffffffff87984f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x498db88f37c4c6b9, 0xffffffffff87984f, x2, 1392, x7)
+
+inst_453:
+// rs2_val == 0xFFFFFFFFFFCE1BBC and rs1_val == 0xC313BC1FA311D81E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xc313bc1fa311d81e;  op2val:0xffffffffffce1bbc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xc313bc1fa311d81e, 0xffffffffffce1bbc, x2, 1400, x7)
+
+inst_454:
+// rs2_val == 0xFFFFFFFFFFEF1D76 and rs1_val == 0xB183406662EBF954 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb183406662ebf954;  op2val:0xffffffffffef1d76
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb183406662ebf954, 0xffffffffffef1d76, x2, 1408, x7)
+
+inst_455:
+// rs2_val == 0xFFFFFFFFFFF3AE62 and rs1_val == 0xAA467BBE0320DF72 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaa467bbe0320df72;  op2val:0xfffffffffff3ae62
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaa467bbe0320df72, 0xfffffffffff3ae62, x2, 1416, x7)
+
+inst_456:
+// rs2_val == 0xFFFFFFFFFFF81475 and rs1_val == 0x9B9AAAD179A6551F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9b9aaad179a6551f;  op2val:0xfffffffffff81475
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9b9aaad179a6551f, 0xfffffffffff81475, x2, 1424, x7)
+
+inst_457:
+// rs2_val == 0xFFFFFFFFFFFCE9A5 and rs1_val == 0xE4367CCAD9716F2C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe4367ccad9716f2c;  op2val:0xfffffffffffce9a5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe4367ccad9716f2c, 0xfffffffffffce9a5, x2, 1432, x7)
+
+inst_458:
+// rs2_val == 0xFFFFFFFFFFFE5770 and rs1_val == 0x3C2C0E921E4E0FAD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x3c2c0e921e4e0fad;  op2val:0xfffffffffffe5770
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x3c2c0e921e4e0fad, 0xfffffffffffe5770, x2, 1440, x7)
+
+inst_459:
+// rs2_val == 0xFFFFFFFFFFFF4877 and rs1_val == 0xB264D045E3D4DD27 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb264d045e3d4dd27;  op2val:0xffffffffffff4877
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb264d045e3d4dd27, 0xffffffffffff4877, x2, 1448, x7)
+
+inst_460:
+// rs2_val == 0xFFFFFFFFFFFFB0B3 and rs1_val == 0x6BAEEA37B4C8839B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6baeea37b4c8839b;  op2val:0xffffffffffffb0b3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6baeea37b4c8839b, 0xffffffffffffb0b3, x2, 1456, x7)
+
+inst_461:
+// rs2_val == 0xFFFFFFFFFFFFDD0F and rs1_val == 0xE0F003E954084572 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe0f003e954084572;  op2val:0xffffffffffffdd0f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe0f003e954084572, 0xffffffffffffdd0f, x2, 1464, x7)
+
+inst_462:
+// rs2_val == 0xFFFFFFFFFFFFE1E2 and rs1_val == 0xF69B0AE6C099BC4C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf69b0ae6c099bc4c;  op2val:0xffffffffffffe1e2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf69b0ae6c099bc4c, 0xffffffffffffe1e2, x2, 1472, x7)
+
+inst_463:
+// rs2_val == 0xFFFFFFFFFFFFF4E3 and rs1_val == 0x29ADE05F7DDDCC72 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x29ade05f7dddcc72;  op2val:0xfffffffffffff4e3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x29ade05f7dddcc72, 0xfffffffffffff4e3, x2, 1480, x7)
+
+inst_464:
+// rs2_val == 0xFFFFFFFFFFFFFB86 and rs1_val == 0x13E6D9036DC3CCEE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x13e6d9036dc3ccee;  op2val:0xfffffffffffffb86
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x13e6d9036dc3ccee, 0xfffffffffffffb86, x2, 1488, x7)
+
+inst_465:
+// rs2_val == 0xFFFFFFFFFFFFFDC4 and rs1_val == 0x0AF2EE97D9ADF5D6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaf2ee97d9adf5d6;  op2val:0xfffffffffffffdc4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaf2ee97d9adf5d6, 0xfffffffffffffdc4, x2, 1496, x7)
+
+inst_466:
+// rs2_val == 0xFFFFFFFFFFFFFEC3 and rs1_val == 0x2A5DC0A00D453CDF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x2a5dc0a00d453cdf;  op2val:0xfffffffffffffec3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x2a5dc0a00d453cdf, 0xfffffffffffffec3, x2, 1504, x7)
+
+inst_467:
+// rs2_val == 0xFFFFFFFFFFFFFF3F and rs1_val == 0xE6A4D5CACB293EBD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe6a4d5cacb293ebd;  op2val:0xffffffffffffff3f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe6a4d5cacb293ebd, 0xffffffffffffff3f, x2, 1512, x7)
+
+inst_468:
+// rs2_val == 0xFFFFFFFFFFFFFFB1 and rs1_val == 0xA422AF666ED26006 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xa422af666ed26006;  op2val:0xffffffffffffffb1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xa422af666ed26006, 0xffffffffffffffb1, x2, 1520, x7)
+
+inst_469:
+// rs2_val == 0xFFFFFFFFFFFFFFD6 and rs1_val == 0x755961A98347DDF5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x755961a98347ddf5;  op2val:0xffffffffffffffd6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x755961a98347ddf5, 0xffffffffffffffd6, x2, 1528, x7)
+
+inst_470:
+// rs2_val == 0xFFFFFFFFFFFFFFEF and rs1_val == 0x9AAACD63FC6C3192 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9aaacd63fc6c3192;  op2val:0xffffffffffffffef
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9aaacd63fc6c3192, 0xffffffffffffffef, x2, 1536, x7)
+
+inst_471:
+// rs2_val == 0xFFFFFFFFFFFFFFF4 and rs1_val == 0x9C1F741F7886E3EB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x9c1f741f7886e3eb;  op2val:0xfffffffffffffff4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x9c1f741f7886e3eb, 0xfffffffffffffff4, x2, 1544, x7)
+
+inst_472:
+// rs2_val == 0xFFFFFFFFFFFFFFFB and rs1_val == 0x5902A9DBE1832AB6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x5902a9dbe1832ab6;  op2val:0xfffffffffffffffb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x5902a9dbe1832ab6, 0xfffffffffffffffb, x2, 1552, x7)
+
+inst_473:
+// rs2_val == 0xFFFFFFFFFFFFFFFC and rs1_val == 0x1694BD33596F5F89 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1694bd33596f5f89;  op2val:0xfffffffffffffffc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1694bd33596f5f89, 0xfffffffffffffffc, x2, 1560, x7)
+
+inst_474:
+// rs2_val == 0xFFFFFFFFFFFFFFFE and rs1_val == 0xDD4EC4D8CA11073D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xdd4ec4d8ca11073d;  op2val:0xfffffffffffffffe
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xdd4ec4d8ca11073d, 0xfffffffffffffffe, x2, 1568, x7)
+
+inst_475:
+// rs2_val == 0xFFFFFFFFFFFFFFFF and rs1_val == 0xEF677106DC17AE6E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xef677106dc17ae6e;  op2val:0xffffffffffffffff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xef677106dc17ae6e, 0xffffffffffffffff, x2, 1576, x7)
+
+inst_476:
+// rs1_val == 0x313971C0A85AB567 and rs2_val == 0x0CD5D8E29408AD7D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x313971c0a85ab567;  op2val:0xcd5d8e29408ad7d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x313971c0a85ab567, 0xcd5d8e29408ad7d, x2, 1584, x7)
+
+inst_477:
+// rs1_val == 0xAEC1527485D77C9B and rs2_val == 0xDEC85B0D53A27EE1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xaec1527485d77c9b;  op2val:0xdec85b0d53a27ee1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xaec1527485d77c9b, 0xdec85b0d53a27ee1, x2, 1592, x7)
+
+inst_478:
+// rs1_val == 0xD9157BEE56DF45DE and rs2_val == 0x93017690E356529C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd9157bee56df45de;  op2val:0x93017690e356529c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd9157bee56df45de, 0x93017690e356529c, x2, 1600, x7)
+
+inst_479:
+// rs1_val == 0xE9907C4BEA37DC21 and rs2_val == 0x647981B7041BBAAB 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xe9907c4bea37dc21;  op2val:0x647981b7041bbaab
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xe9907c4bea37dc21, 0x647981b7041bbaab, x2, 1608, x7)
+
+inst_480:
+// rs1_val == 0xF1CCAECF31150919 and rs2_val == 0xFBDF8F979267ACB5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xf1ccaecf31150919;  op2val:0xfbdf8f979267acb5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xf1ccaecf31150919, 0xfbdf8f979267acb5, x2, 1616, x7)
+
+inst_481:
+// rs1_val == 0xFAB2993A91ED6C94 and rs2_val == 0xF37E27A312EA67E4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfab2993a91ed6c94;  op2val:0xf37e27a312ea67e4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfab2993a91ed6c94, 0xf37e27a312ea67e4, x2, 1624, x7)
+
+inst_482:
+// rs1_val == 0xFC6F9F6B4EC6F18C and rs2_val == 0x0DA64FCFEF8C60C0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfc6f9f6b4ec6f18c;  op2val:0xda64fcfef8c60c0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfc6f9f6b4ec6f18c, 0xda64fcfef8c60c0, x2, 1632, x7)
+
+inst_483:
+// rs1_val == 0xFE11D383484641F6 and rs2_val == 0x3DA82C982FB5A758 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfe11d383484641f6;  op2val:0x3da82c982fb5a758
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfe11d383484641f6, 0x3da82c982fb5a758, x2, 1640, x7)
+
+inst_484:
+// rs1_val == 0xFF0D9D6012E91176 and rs2_val == 0x9C3D087C65835BDF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xff0d9d6012e91176;  op2val:0x9c3d087c65835bdf
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xff0d9d6012e91176, 0x9c3d087c65835bdf, x2, 1648, x7)
+
+inst_485:
+// rs1_val == 0xFFBE66B1042D678A and rs2_val == 0xA6C5E21453E1E6BC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffbe66b1042d678a;  op2val:0xa6c5e21453e1e6bc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffbe66b1042d678a, 0xa6c5e21453e1e6bc, x2, 1656, x7)
+
+inst_486:
+// rs1_val == 0xFFD1F3AAB87CE2A6 and rs2_val == 0xD6220B4FBBC9DF37 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffd1f3aab87ce2a6;  op2val:0xd6220b4fbbc9df37
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffd1f3aab87ce2a6, 0xd6220b4fbbc9df37, x2, 1664, x7)
+
+inst_487:
+// rs1_val == 0xFFEB78CC9651EE66 and rs2_val == 0xFE0A9C6C9A592829 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffeb78cc9651ee66;  op2val:0xfe0a9c6c9a592829
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffeb78cc9651ee66, 0xfe0a9c6c9a592829, x2, 1672, x7)
+
+inst_488:
+// rs1_val == 0xFFF6F2FC7B8B7233 and rs2_val == 0xDA70525A725F3A8F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfff6f2fc7b8b7233;  op2val:0xda70525a725f3a8f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfff6f2fc7b8b7233, 0xda70525a725f3a8f, x2, 1680, x7)
+
+inst_489:
+// rs1_val == 0xFFFA3D4FA3B633AC and rs2_val == 0xB9FEF1D65956B39D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffa3d4fa3b633ac;  op2val:0xb9fef1d65956b39d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffa3d4fa3b633ac, 0xb9fef1d65956b39d, x2, 1688, x7)
+
+inst_490:
+// rs1_val == 0xFFFD116081ED75E8 and rs2_val == 0x67913217437CBC41 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffd116081ed75e8;  op2val:0x67913217437cbc41
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffd116081ed75e8, 0x67913217437cbc41, x2, 1696, x7)
+
+inst_491:
+// rs1_val == 0xFFFEB3BEA0FBC248 and rs2_val == 0x81AA70AC4B43AD85 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffeb3bea0fbc248;  op2val:0x81aa70ac4b43ad85
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffeb3bea0fbc248, 0x81aa70ac4b43ad85, x2, 1704, x7)
+
+inst_492:
+// rs1_val == 0xFFFF2DD55C37849B and rs2_val == 0xC26801926C967B0E 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffff2dd55c37849b;  op2val:0xc26801926c967b0e
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffff2dd55c37849b, 0xc26801926c967b0e, x2, 1712, x7)
+
+inst_493:
+// rs1_val == 0xFFFFAE62C5B3E01C and rs2_val == 0x5916D2810E24D9CC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffae62c5b3e01c;  op2val:0x5916d2810e24d9cc
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffae62c5b3e01c, 0x5916d2810e24d9cc, x2, 1720, x7)
+
+inst_494:
+// rs1_val == 0xFFFFC75235A7EFC1 and rs2_val == 0x3322358CA6FABA7B 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffc75235a7efc1;  op2val:0x3322358ca6faba7b
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffc75235a7efc1, 0x3322358ca6faba7b, x2, 1728, x7)
+
+inst_495:
+// rs1_val == 0xFFFFE41C44115B05 and rs2_val == 0xA08B84F3C86342C2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffe41c44115b05;  op2val:0xa08b84f3c86342c2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffe41c44115b05, 0xa08b84f3c86342c2, x2, 1736, x7)
+
+inst_496:
+// rs1_val == 0xFFFFF59572976012 and rs2_val == 0x8E368CE0BE5265F3 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffff59572976012;  op2val:0x8e368ce0be5265f3
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffff59572976012, 0x8e368ce0be5265f3, x2, 1744, x7)
+
+inst_497:
+// rs1_val == 0xFFFFF9E2E3356CC4 and rs2_val == 0xB8F4169F85BF95C0 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffff9e2e3356cc4;  op2val:0xb8f4169f85bf95c0
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffff9e2e3356cc4, 0xb8f4169f85bf95c0, x2, 1752, x7)
+
+inst_498:
+// rs1_val == 0xFFFFFC47FC7C6D0B and rs2_val == 0xFFEC35FEAF334E15 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffc47fc7c6d0b;  op2val:0xffec35feaf334e15
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffc47fc7c6d0b, 0xffec35feaf334e15, x2, 1760, x7)
+
+inst_499:
+// rs1_val == 0xFFFFFE96FC6113A4 and rs2_val == 0x6D3F408B31D4FF08 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffe96fc6113a4;  op2val:0x6d3f408b31d4ff08
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffe96fc6113a4, 0x6d3f408b31d4ff08, x2, 1768, x7)
+
+inst_500:
+// rs1_val == 0xFFFFFF3F985A9EF1 and rs2_val == 0xC96EFDC4EB6992D5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffff3f985a9ef1;  op2val:0xc96efdc4eb6992d5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffff3f985a9ef1, 0xc96efdc4eb6992d5, x2, 1776, x7)
+
+inst_501:
+// rs1_val == 0xFFFFFFA4FB37BEC9 and rs2_val == 0x242A809B7A3209FE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffa4fb37bec9;  op2val:0x242a809b7a3209fe
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffa4fb37bec9, 0x242a809b7a3209fe, x2, 1784, x7)
+
+inst_502:
+// rs1_val == 0xFFFFFFC50BD61D6D and rs2_val == 0xF65E7737FBD2570D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffc50bd61d6d;  op2val:0xf65e7737fbd2570d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffc50bd61d6d, 0xf65e7737fbd2570d, x2, 1792, x7)
+
+inst_503:
+// rs1_val == 0xFFFFFFE96F738905 and rs2_val == 0xE380A1764A104E66 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffe96f738905;  op2val:0xe380a1764a104e66
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffe96f738905, 0xe380a1764a104e66, x2, 1800, x7)
+
+inst_504:
+// rs1_val == 0xFFFFFFF1AFE08A14 and rs2_val == 0xF65CF3F31DCACF74 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffff1afe08a14;  op2val:0xf65cf3f31dcacf74
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffff1afe08a14, 0xf65cf3f31dcacf74, x2, 1808, x7)
+
+inst_505:
+// rs1_val == 0xFFFFFFFBBD59213F and rs2_val == 0x9E7E1FC352B42EFF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffbbd59213f;  op2val:0x9e7e1fc352b42eff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffbbd59213f, 0x9e7e1fc352b42eff, x2, 1816, x7)
+
+inst_506:
+// rs1_val == 0xFFFFFFFDA6478A56 and rs2_val == 0x85FCD601E8D7A714 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffda6478a56;  op2val:0x85fcd601e8d7a714
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffda6478a56, 0x85fcd601e8d7a714, x2, 1824, x7)
+
+inst_507:
+// rs1_val == 0xFFFFFFFEB9E93D53 and rs2_val == 0x6C5E1578754F9B96 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffeb9e93d53;  op2val:0x6c5e1578754f9b96
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffeb9e93d53, 0x6c5e1578754f9b96, x2, 1832, x7)
+
+inst_508:
+// rs1_val == 0xFFFFFFFF75697302 and rs2_val == 0x72745307EC325EEC 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff75697302;  op2val:0x72745307ec325eec
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffff75697302, 0x72745307ec325eec, x2, 1840, x7)
+
+inst_509:
+// rs1_val == 0xFFFFFFFF955D1CE8 and rs2_val == 0x7C2C966DCCADB61F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffff955d1ce8;  op2val:0x7c2c966dccadb61f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffff955d1ce8, 0x7c2c966dccadb61f, x2, 1848, x7)
+
+inst_510:
+// rs1_val == 0xFFFFFFFFD7BE0830 and rs2_val == 0x9BB4752D1BD775C5 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffd7be0830;  op2val:0x9bb4752d1bd775c5
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffd7be0830, 0x9bb4752d1bd775c5, x2, 1856, x7)
+
+inst_511:
+// rs1_val == 0xFFFFFFFFE046AB61 and rs2_val == 0x0CF25923109FF475 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffe046ab61;  op2val:0xcf25923109ff475
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffe046ab61, 0xcf25923109ff475, x2, 1864, x7)
+
+inst_512:
+// rs1_val == 0xFFFFFFFFF14135A5 and rs2_val == 0xDF3C45B4090A96C9 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffff14135a5;  op2val:0xdf3c45b4090a96c9
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffff14135a5, 0xdf3c45b4090a96c9, x2, 1872, x7)
+
+inst_513:
+// rs1_val == 0xFFFFFFFFFBA1A6CB and rs2_val == 0x8F0846A22A71A2AD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffba1a6cb;  op2val:0x8f0846a22a71a2ad
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffba1a6cb, 0x8f0846a22a71a2ad, x2, 1880, x7)
+
+inst_514:
+// rs1_val == 0xFFFFFFFFFC9E9033 and rs2_val == 0x66B072B9E5E290BE 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffc9e9033;  op2val:0x66b072b9e5e290be
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffc9e9033, 0x66b072b9e5e290be, x2, 1888, x7)
+
+inst_515:
+// rs1_val == 0xFFFFFFFFFE238B6B and rs2_val == 0x2A933AD31011EEB4 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffe238b6b;  op2val:0x2a933ad31011eeb4
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffe238b6b, 0x2a933ad31011eeb4, x2, 1896, x7)
+
+inst_516:
+// rs1_val == 0xFFFFFFFFFF7D8180 and rs2_val == 0x8525E8A8458DA5EF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff7d8180;  op2val:0x8525e8a8458da5ef
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffff7d8180, 0x8525e8a8458da5ef, x2, 1904, x7)
+
+inst_517:
+// rs1_val == 0xFFFFFFFFFF832E3F and rs2_val == 0x9535971C67A07B54 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffff832e3f;  op2val:0x9535971c67a07b54
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffff832e3f, 0x9535971c67a07b54, x2, 1912, x7)
+
+inst_518:
+// rs1_val == 0xFFFFFFFFFFC77CDC and rs2_val == 0x3E1C852151C5B8B2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffc77cdc;  op2val:0x3e1c852151c5b8b2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffc77cdc, 0x3e1c852151c5b8b2, x2, 1920, x7)
+
+inst_519:
+// rs1_val == 0xFFFFFFFFFFE22746 and rs2_val == 0xB66B32848B7B5378 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffe22746;  op2val:0xb66b32848b7b5378
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffe22746, 0xb66b32848b7b5378, x2, 1928, x7)
+
+inst_520:
+// rs1_val == 0xFFFFFFFFFFF20599 and rs2_val == 0x53FBFF6C58FA6E1C 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffff20599;  op2val:0x53fbff6c58fa6e1c
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffff20599, 0x53fbff6c58fa6e1c, x2, 1936, x7)
+
+inst_521:
+// rs1_val == 0xFFFFFFFFFFFBE2C6 and rs2_val == 0xC70AFC922C9F7296 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffbe2c6;  op2val:0xc70afc922c9f7296
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffbe2c6, 0xc70afc922c9f7296, x2, 1944, x7)
+
+inst_522:
+// rs1_val == 0xFFFFFFFFFFFC39A2 and rs2_val == 0xDD68F2012DAF94C1 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffc39a2;  op2val:0xdd68f2012daf94c1
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffc39a2, 0xdd68f2012daf94c1, x2, 1952, x7)
+
+inst_523:
+// rs1_val == 0xFFFFFFFFFFFED06B and rs2_val == 0x7213516D6A013380 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffed06b;  op2val:0x7213516d6a013380
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffed06b, 0x7213516d6a013380, x2, 1960, x7)
+
+inst_524:
+// rs1_val == 0xFFFFFFFFFFFF5EA2 and rs2_val == 0x18BB28E9C5EC6148 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff5ea2;  op2val:0x18bb28e9c5ec6148
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffff5ea2, 0x18bb28e9c5ec6148, x2, 1968, x7)
+
+inst_525:
+// rs1_val == 0xFFFFFFFFFFFF8647 and rs2_val == 0x265039F699EF1857 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffff8647;  op2val:0x265039f699ef1857
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffff8647, 0x265039f699ef1857, x2, 1976, x7)
+
+inst_526:
+// rs1_val == 0xFFFFFFFFFFFFC823 and rs2_val == 0x14B91C79DAE98554 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffc823;  op2val:0x14b91c79dae98554
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffc823, 0x14b91c79dae98554, x2, 1984, x7)
+
+inst_527:
+// rs1_val == 0xFFFFFFFFFFFFEDB9 and rs2_val == 0x0973E89C3D061437 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffedb9;  op2val:0x973e89c3d061437
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffedb9, 0x973e89c3d061437, x2, 1992, x7)
+
+inst_528:
+// rs1_val == 0xFFFFFFFFFFFFF576 and rs2_val == 0xD798C9CF280B11FD 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffff576;  op2val:0xd798c9cf280b11fd
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffff576, 0xd798c9cf280b11fd, x2, 2000, x7)
+
+inst_529:
+// rs1_val == 0xFFFFFFFFFFFFFADF and rs2_val == 0x95A4D257A7298C66 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffadf;  op2val:0x95a4d257a7298c66
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffadf, 0x95a4d257a7298c66, x2, 2008, x7)
+
+inst_530:
+// rs1_val == 0xFFFFFFFFFFFFFD7F and rs2_val == 0x735C076B8C8A18B2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffd7f;  op2val:0x735c076b8c8a18b2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffd7f, 0x735c076b8c8a18b2, x2, 2016, x7)
+
+inst_531:
+// rs1_val == 0xFFFFFFFFFFFFFEE4 and rs2_val == 0x894DEAB44D88450F 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffee4;  op2val:0x894deab44d88450f
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffee4, 0x894deab44d88450f, x2, 2024, x7)
+
+inst_532:
+// rs1_val == 0xFFFFFFFFFFFFFF11 and rs2_val == 0x953B00B00B54AA22 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff11;  op2val:0x953b00b00b54aa22
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff11, 0x953b00b00b54aa22, x2, 2032, x7)
+
+inst_533:
+// rs1_val == 0xFFFFFFFFFFFFFF8B and rs2_val == 0xF829D29F3D4806C2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffff8b;  op2val:0xf829d29f3d4806c2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffff8b, 0xf829d29f3d4806c2, x2, 2040, x7)
+RVTEST_SIGBASE( x2,signature_x2_2)
+
+inst_534:
+// rs1_val == 0xFFFFFFFFFFFFFFCD and rs2_val == 0xA96EC2B34D984BFF 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffcd;  op2val:0xa96ec2b34d984bff
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffcd, 0xa96ec2b34d984bff, x2, 0, x7)
+
+inst_535:
+// rs1_val == 0xFFFFFFFFFFFFFFE0 and rs2_val == 0x432779EEACCA7F0D 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xffffffffffffffe0;  op2val:0x432779eeacca7f0d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xffffffffffffffe0, 0x432779eeacca7f0d, x2, 8, x7)
+
+inst_536:
+// rs1_val == 0xFFFFFFFFFFFFFFF5 and rs2_val == 0x61B0EE095AE6A228 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffff5;  op2val:0x61b0ee095ae6a228
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffff5, 0x61b0ee095ae6a228, x2, 16, x7)
+
+inst_537:
+// rs1_val == 0xFFFFFFFFFFFFFFFB and rs2_val == 0xFF1E5BEFBEDC25E6 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffb;  op2val:0xff1e5befbedc25e6
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffb, 0xff1e5befbedc25e6, x2, 24, x7)
+
+inst_538:
+// rs1_val == 0xFFFFFFFFFFFFFFFC and rs2_val == 0x137A977753E8EB43 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffc;  op2val:0x137a977753e8eb43
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffc, 0x137a977753e8eb43, x2, 32, x7)
+
+inst_539:
+// rs1_val == 0xFFFFFFFFFFFFFFFE and rs2_val == 0x2904CDEFCF84B683 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xfffffffffffffffe;  op2val:0x2904cdefcf84b683
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xfffffffffffffffe, 0x2904cdefcf84b683, x2, 40, x7)
+
+inst_540:
+// rs1_val == 0x6af29145404fd8ed and rs2_val == 0x990e75eafff569c2 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x6af29145404fd8ed;  op2val:0x990e75eafff569c2
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x6af29145404fd8ed, 0x990e75eafff569c2, x2, 48, x7)
+
+inst_541:
+// rs1_val == 0x1f7d946f17168ab3 and rs2_val == 0x66eae3d9bbb4f560 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x1f7d946f17168ab3;  op2val:0x66eae3d9bbb4f560
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x1f7d946f17168ab3, 0x66eae3d9bbb4f560, x2, 56, x7)
+
+inst_542:
+// rs1_val == 0xb694de26ad9e5431 and rs2_val == 0x293f9f6071fad878 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xb694de26ad9e5431;  op2val:0x293f9f6071fad878
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xb694de26ad9e5431, 0x293f9f6071fad878, x2, 64, x7)
+
+inst_543:
+// rs1_val == 0x987daa20b858e304 and rs2_val == 0x1aa1beebefb902cb 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0x987daa20b858e304;  op2val:0x1aa1beebefb902cb
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0x987daa20b858e304, 0x1aa1beebefb902cb, x2, 72, x7)
+
+inst_544:
+// rs1_val == 0xd75739f82ac177c6 and rs2_val == 0xaa6bb2bde9ed477d 
+// opcode: xperm.n ; op1:x10; op2:x11; dest:x12; op1val:0xd75739f82ac177c6;  op2val:0xaa6bb2bde9ed477d
+TEST_RR_OP(xperm.n, x12, x10, x11, 0x0000000000000000, 0xd75739f82ac177c6, 0xaa6bb2bde9ed477d, x2, 80, x7)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x11_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x11_1:
+    .fill 22*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_1:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x2_2:
+    .fill 11*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile
new file mode 100644
index 000000000..f767da3a4
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64im -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag
new file mode 100644
index 000000000..261a9a852
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/M/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV64IM Makefrag
+#
+# Copyright (c) 2018, Imperas Software Ltd.
+# Copyright (c) 2020, InCore Semiconductors. Pvt. Ltd.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Imperas Software Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64IM architectural tests
+
+rv64im_sc_tests = \
+ 
+rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests))
+
+target_tests += $(rv64im_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output
deleted file mode 100644
index 6f8523bbf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output
+++ /dev/null
@@ -1,36 +0,0 @@
-00000000  # fsq of 1
-00000000
-00000000
-3fff0000
-dead4000  # fsh of 1
-deadbeef
-deadbeef
-deadbeef
-00000000  # fsq of 3
-00000000
-00000000
-40008000
-00000000  # fsq of -1
-00000000
-00000000
-bfff0000
-00000000  # fsq of 6
-00000000
-00000000
-40018000
-00000000  # fsq of -4
-00000000
-00000000
-C0010000
-00000000  # fsq of -2
-00000000
-00000000
-C0000000
-00000000   # fsq of 4
-00000000
-00000000
-40010000
-00000000   # fsq of 2
-00000000
-00000000
-40000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S
deleted file mode 100644
index ea8bd15d5..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S
+++ /dev/null
@@ -1,154 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
-// David_Harris@hmc.edu & Rose Thompson
-// Created 07 March 2024 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFDQZfh_Zicsr")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*Q.*);def TEST_CASE_1=True;def NO_SAIL=True",flq-align)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-#endif
-
-# turn on the floating point unit
-li x7, 1
-slli x7, x7, 13
-csrw mstatus, x7
-
-li x4, 1        # 3fff 0000 0000 0000 0000 0000 0000 0000
-li x2, 2        # 4000 0000 0000 0000 0000 0000 0000 0000
-fcvt.q.w f2, x2
-fcvt.q.w f4, x4
-
-fcvt.h.w f5, x2  # 4000
-
-# test quad load/store
-fsq f4, 0(x3)
-flq f7, 0(x3)
-fsq f7, 0(x1)
-
-# test half load/store
-fsh f5, 16(x3)
-flh f6, 16(x3)
-fsh f6, 16(x1)
-	
-# 1 + 2 = 3           # 4000 8000 0000 0000 0000 0000 0000 0000
-fadd.q f8, f2, f4
-fsq f8, 32(x1)
-	
-# 1 - 2 = -1
-fsub.q f9, f4, f2     # bfff 0000000000000000000000000000
-fsq f9, 48(x1)
-	
-# 2 * 3 = 6
-fmul.q f10, f2, f8     # 4001 8000000000000000000000000000
-fsq f10, 64(x1)
-
-# 6 * (-1) + 2 = -4
-fmadd.q f11, f10, f9, f2     # C001 0000000000000000000000000000
-fsq f11, 80(x1)
-
-# -4 / 2 = -2
-fdiv.q f12, f11, f2     # C000 0000000000000000000000000000
-fsq f12, 96(x1)
-
-# sign injection (-4, 1)  = 4
-fsgnj.q f13, f11, f4    # 4001 0000000000000000000000000000
-fsq f13, 112(x1)
-
-# sqrt(4)  = 2
-fsqrt.q f14, f13    # 4000 0000000000000000000000000000
-fsq f14, 128(x1)
-        
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-test_dataset_0:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_1:
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-
-
-
-
-signature_x1_1:
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-    .int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefile
new file mode 100644
index 000000000..18dc245c8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefrag
new file mode 100644
index 000000000..e6b9e250a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/Makefrag
@@ -0,0 +1,34 @@
+# RISC-V Architecture Test RV64I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64I architectural tests
+
+rv64i_sc_tests = \
+ 
+rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
+
+target_tests += $(rv64i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
new file mode 100644
index 000000000..701b28235
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
@@ -0,0 +1,96 @@
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the fence.i instruction of the RISC-V Zifencei  extension.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+
+# Test Virtual Machine (TVM) used by program.
+RVTEST_ISA("RV64I")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
+
+#ifdef TEST_CASE_1
+  RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*); check ISA:=regex(.*Zifencei.*); def TEST_CASE_1=True", fencei)
+
+    # ---------------------------------------------------------------------------------------------
+    RVMODEL_IO_WRITE_STR(x31, "# Test part A - test fence\n");
+
+    # Addresses for test data and results
+    la      x16, test_A_data
+    la      x17, test_A_res
+
+    # Register initialization
+    li      x3, 0
+
+    # Load testdata
+    lw      x1, 0(x16)
+    lw      x2, 4(x16)
+
+    # Test
+    la      x20, instr_A_src
+    la      x21, instr_A_dst
+    lw      x15, 0(x20)
+    sw      x15, 0(x21)
+    fence.i
+instr_A_dst:
+    lui     x2, 0
+
+    # Store results
+    sw      x1, 0(x17)
+    sw      x2, 4(x17)
+    sw      x3, 8(x17)
+    sw      x15, 12(x17)
+
+    //
+    // Assert
+    //
+    RVMODEL_IO_ASSERT_GPR_EQ(x17, x2,  0x00000012)
+    RVMODEL_IO_ASSERT_GPR_EQ(x17, x3,  0x00000042)
+    RVMODEL_IO_ASSERT_GPR_EQ(x17, x15, 0x001101B3)
+
+    RVMODEL_IO_WRITE_STR(x31, "# Test part A1  - Complete\n");
+
+    RVMODEL_IO_WRITE_STR(x31, "# Test End\n")
+
+#endif
+
+ # ---------------------------------------------------------------------------------------------
+    # HALT
+    RVMODEL_HALT
+
+RVTEST_CODE_END
+
+RVTEST_DATA_BEGIN
+# Input data section.
+    .data
+    .align 4
+
+instr_A_src:
+    add     x3, x2, x1
+
+test_A_data:
+    .word 0x30
+    .word 0x12
+RVTEST_DATA_END
+
+# Output data section.
+RVMODEL_DATA_BEGIN
+test_A_res:
+    .fill 4, 4, 0xdeadbeef
+
+#ifdef rvtest_gpr_save
+gpr_save:
+    .fill 32*(XLEN/32), 4, 0xdeadbeef
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile
new file mode 100644
index 000000000..7404f07c1
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile
@@ -0,0 +1,5 @@
+include ../../Makefile.include
+
+RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
+
+$(eval $(call compile_template,-march=rv64iaf -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
new file mode 100644
index 000000000..319c5d930
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
@@ -0,0 +1,64 @@
+# RISC-V Architecture Test RV64I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64I architectural tests
+
+rv64i_sc_tests = \
+    WALLY-mmu-sv39 \
+    WALLY-mmu-sv48 \
+    WALLY-pmp \
+    WALLY-minfo-01 \
+    WALLY-csr-permission-s-01 \
+    WALLY-csr-permission-u-01 \
+    WALLY-misa-01 \
+    WALLY-amo \
+    WALLY-lrsc \
+    WALLY-trap-sret-01 \
+    WALLY-status-mie-01 \
+    WALLY-status-sie-01 \
+    WALLY-status-tw-01 \
+
+
+# Don't simulate these because they rely on SoC features that Spike does not offer.
+target_tests_nosim = \
+    WALLY-pma \
+    WALLY-periph \
+    WALLY-mtvec-01 \
+    WALLY-stvec-01 \
+    WALLY-mie-01 \
+    WALLY-sie-01 \
+    WALLY-trap-01 \
+    WALLY-trap-s-01 \
+    WALLY-trap-u-01 \
+    WALLY-status-fp-enabled-01 \
+    WALLY-wfi-01 \
+
+# unclear why status-fp-enabled and wfi aren't simulating ok
+
+rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
+
+target_tests += $(rv64i_tests)
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output
new file mode 100644
index 000000000..edce96fe8
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-amo-01.reference_output
@@ -0,0 +1,72 @@
+fffffffe
+ffffffff
+00000001
+00000000
+fffffffb
+ffffffff
+fffffffd
+ffffffff
+ffffffef
+ffffffff
+000007ef
+00000000
+ffffffbf
+ffffffff
+ffffffff
+ffffffff
+fffffeff
+ffffffff
+fffffd7e
+ffffffff
+fffffeff
+ffffffff
+000007ff
+00000000
+ffffefff
+ffffffff
+ffffefff
+ffffffff
+ffffefff
+ffffffff
+ffffefff
+ffffffff
+fffeffff
+ffffffff
+000007fa
+00000000
+fffbffff
+fff7ffff
+00000001
+00000000
+ffefffff
+ffdfffff
+fff00001
+ffdfffff
+ffbfffff
+ff7fffff
+000007cf
+00000000
+feffffff
+fdffffff
+ffffffff
+fdffffff
+feffffff
+f7ffffff
+fefffc7e
+f7ffffff
+efffffff
+dfffffff
+000007ff
+00000000
+efffffff
+7fffffff
+000007fd
+00000000
+ffffffff
+00000001
+ffffffff
+00000001
+00000002
+00000004
+000007fa
+00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
deleted file mode 100644
index 2059466b7..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
+++ /dev/null
@@ -1,456 +0,0 @@
-deadbeef # begin_signature
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef  # destination 1
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-00000000  # destination 2
-00000001
-00000002
-00000003
-00000004
-00000005
-00000006
-00000007
-00000008
-00000009
-0000000a
-0000000b
-0000000c
-0000000d
-0000000e
-0000000f
-00000010
-00000011
-00000012
-00000013
-00000014
-00000015
-00000016
-00000017
-00000018
-00000019
-0000001a
-0000001b
-0000001c
-0000001d
-0000001e
-0000001f
-00000020
-00000021
-00000022
-00000023
-00000024
-00000025
-00000026
-00000027
-00000028
-00000029
-0000002a
-0000002b
-0000002c
-0000002d
-0000002e
-0000002f
-00000030
-00000031
-00000032
-00000033
-00000034
-00000035
-00000036
-00000037
-00000038
-00000039
-0000003a
-0000003b
-0000003c
-0000003d
-0000003e
-0000003f
-00000040
-00000041
-00000042
-00000043
-00000044
-00000045
-00000046
-00000047
-00000048
-00000049
-0000004a
-0000004b
-0000004c
-0000004d
-0000004e
-0000004f
-00000050
-00000051
-00000052
-00000053
-00000054
-00000055
-00000056
-00000057
-00000058
-00000059
-0000005a
-0000005b
-0000005c
-0000005d
-0000005e
-0000005f
-00000060
-00000061
-00000062
-00000063
-00000064
-00000065
-00000066
-00000067
-00000068
-00000069
-0000006a
-0000006b
-0000006c
-0000006d
-0000006e
-0000006f
-00000070
-00000071
-00000072
-00000073
-00000074
-00000075
-00000076
-00000077
-00000078
-00000079
-0000007a
-0000007b
-0000007c
-0000007d
-0000007e
-0000007f
-00000000  # destination 3
-00000001
-00000002
-00000003
-00000004
-00000005
-00000006
-00000007
-00000008
-00000009
-0000000a
-0000000b
-0000000c
-0000000d
-0000000e
-0000000f
-00000010
-00000011
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-00000013
-00000014
-00000015
-00000016
-00000017
-00000018
-00000019
-0000001a
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-0000001c
-0000001d
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-00000020
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-00000024
-00000025
-00000026
-00000027
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-00000029
-0000002a
-0000002b
-0000002c
-0000002d
-0000002e
-0000002f
-00000030
-00000031
-00000032
-00000033
-00000034
-00000035
-00000036
-00000037
-00000038
-00000039
-0000003a
-0000003b
-0000003c
-0000003d
-0000003e
-0000003f
-00000040
-00000041
-00000042
-00000043
-00000044
-00000045
-00000046
-00000047
-00000048
-00000049
-0000004a
-0000004b
-0000004c
-0000004d
-0000004e
-0000004f
-00000050
-00000051
-00000052
-00000053
-00000054
-00000055
-00000056
-00000057
-00000058
-00000059
-0000005a
-0000005b
-0000005c
-0000005d
-0000005e
-0000005f
-00000060
-00000061
-00000062
-00000063
-00000064
-00000065
-00000066
-00000067
-00000068
-00000069
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-00000070
-00000071
-00000072
-00000073
-00000074
-00000075
-00000076
-00000077
-00000078
-00000079
-0000007a
-0000007b
-0000007c
-0000007d
-0000007e
-0000007f
-ffffffff  # signature  The test writes -1 for correct answers and the a positive integer for incorrect copies.
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
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-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-0bad0bad # controls
-0bad0bad
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cboz-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cboz-01.reference_output
deleted file mode 100644
index 644fa6f0b..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cboz-01.reference_output
+++ /dev/null
@@ -1,204 +0,0 @@
-deadbeef # begin_signature
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-00000000  # destination 1
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
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-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
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-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
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-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000  # destination 2
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-ffffffff  # signature  The test writes -1 for correct answers and the a positive integer for incorrect copies.
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff
-ffffffff  
-0bad0bad
-0bad0bad
-0bad0bad
-0bad0bad
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
index 96e7da3dc..811bfe7ca 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
@@ -24,12 +24,6 @@
 00000000
 00000bad
 00000000
-00000002 # S mode write to mconfigptr with illegal instruction
-00000000
-00000002 # S mode read from mconfigptr with illegal instruction
-00000000
-00000bad
-00000000
 00000002 # S mode write to mstatus with illegal instruction
 00000000
 00000002 # S mode read from mstatus with illegal instruction
@@ -102,18 +96,6 @@
 00000000
 00000bad
 00000000
-00000002 # S mode write to menvcfg with illegal instruction
-00000000
-00000002 # S mode read from menvcfg with illegal instruction
-00000000
-00000bad
-00000000
-00000002 # S mode write to mseccfg with illegal instruction
-00000000
-00000002 # S mode read from mseccfg with illegal instruction
-00000000
-00000bad
-00000000
 00000002 # S mode write to pmpcfg0 with illegal instruction
 00000000
 00000002 # S mode read from pmpcfg0 with illegal instruction
@@ -590,3 +572,453 @@
 00000000
 00000009 # ecall from terminating tess from S mode
 00000000
+deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
index 439997356..c8cd62ab1 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
@@ -84,12 +84,6 @@
 00000000
 00000bad
 00000000
-00000002 # S mode write to mconfigptr with illegal instruction
-00000000
-00000002 # S mode read from mconfigptr with illegal instruction
-00000000
-00000bad
-00000000
 00000002 # U mode write to mstatus with illegal instruction
 00000000
 00000002 # U mode read from mstatus with illegal instruction
@@ -162,18 +156,6 @@
 00000000
 00000bad
 00000000
-00000002 # S mode write to menvcfg with illegal instruction
-00000000
-00000002 # S mode read from menvcfg with illegal instruction
-00000000
-00000bad
-00000000
-00000002 # S mode write to mseccfg with illegal instruction
-00000000
-00000002 # S mode read from mseccfg with illegal instruction
-00000000
-00000bad
-00000000
 00000002 # U mode write to pmpcfg0 with illegal instruction
 00000000
 00000002 # U mode read from pmpcfg0 with illegal instruction
@@ -650,3 +632,393 @@
 00000000
 00000008 # ecall from terminating tests in U mode
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output
new file mode 100644
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+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-lrsc-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mie-01.reference_output
index 14c63efbc..a50302e59 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mie-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output
index d38ddb879..e37c37626 100644
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 00000011 # confirm read-only permissions of mhartid
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-00000002 # write to read-only CSR failed with illegal instruction
-00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output
index fcbb2b921..f5a34cb06 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output
@@ -2,3 +2,1023 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misaligned-access-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misaligned-access-01.reference_output
deleted file mode 100644
index 209eb4cf4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misaligned-access-01.reference_output
+++ /dev/null
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output
index 360afba6b..23b88c0df 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-01.reference_output
@@ -1,4 +1,4 @@
-0000000b # Test 11.3.1.1.3: ecall from going to S mode from M mode
+0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode
 00000000
 beef0000 # Read test success from confirming writes of known values
 0000dead
@@ -14,13 +14,13 @@ beef0440 # Read test success from confirming writes of known values
 0330dead
 beef0bb0 # Read test success from confirming writes of known values
 0440dead
-beef0000 # Test 11.3.1.1.4: Read test success from checking translation works
+beef0000 # Test 12.3.1.1.4: Read test success from checking translation works
 0000dead
 beef0055 # Read test success from checking translation works
 0880dead
 beef0099 # Read test success from checking translation works
 0220dead
-0000000d # Test 11.3.1.2.1: Read test with page fault from upper vaddr bits not the same
+0000000d # Test 12.3.1.2.1: Read test with page fault from upper vaddr bits not the same
 00000000
 00000bad
 00000000
@@ -28,17 +28,17 @@ beef0099 # Read test success from checking translation works
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.2.2: read test with page fault
+0000000d # Test 12.3.1.2.2: read test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.2.3: write test with page fault
+0000000f # Test 12.3.1.2.3: write test with page fault
 00000000
-0000000d # Test 11.3.1.2.4: read test with page fault
+0000000d # Test 12.3.1.2.4: read test with page fault
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.2.5: 2 read tests with page faults
+0000000d # Test 12.3.1.2.5: 2 read tests with page faults
 00000000
 00000bad
 00000000
@@ -46,7 +46,7 @@ beef0099 # Read test success from checking translation works
 00000000
 00000bad
 00000000
-00000111 # Test 11.3.1.3.1: execute test success
+00000111 # Test 12.3.1.3.1: execute test success
 00000000
 00000009 # ecall from going to U mode from S mode
 00000000
@@ -58,7 +58,7 @@ beef0099 # Read test success from checking translation works
 00000000
 00000bad
 00000000
-beef0033 # Test 11.3.1.3.2: read test success
+beef0033 # Test 12.3.1.3.2: read test success
 0990dead
 00000008 # ecall from going to S mode from U mode
 00000000
@@ -72,43 +72,39 @@ beef0077 # read test success
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.3.3: read test with page fault 
+0000000d # Test 12.3.1.3.3: read test with page fault 
 00000000
 00000bad
 00000000
 beef0440 # read test success
 0330dead
-beef0110 # Test 11.3.1.3.4: read test success
+beef0110 # Test 12.3.1.3.4: read test success
 0440dead
 0000000f # write test with page fault
 00000000
-0000000c # Test 11.3.1.3.5: execute test with page fault
+0000000c # Test 12.3.1.3.5: execute test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.3.6: write test with page fault
+0000000f # Test 12.3.1.3.6: write test with page fault
 00000000
 0000000d # read test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.3.7: write test with page fault
+0000000f # Test 12.3.1.3.7: write test with page fault
 00000000
 beef0bb0 # read test success
 0440dead
-0000000c # Test 11.3.1.3.8: read test with page fault for nonzero reserved bit
-00000000
-00000bad
-00000000
-beef0000 # Test 11.3.1.4.1: read test success from new page table mapping
+beef0000 # Test 12.3.1.4.1: read test success from new page table mapping
 0000dead
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
+00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode
 00000000
 00000000 # previous mprv value before writing 1 to it.
 00000000
 beef0099 # Read test success when mprv=1 So translation should occur
 0220dead # even though we're in M mode with translation off
-0000000b # Test 11.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
+0000000b # Test 12.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
 00000000
 00000009 # ecall from going to m mode from s mode (so we can access mstatus)
 00000000
@@ -116,3 +112,913 @@ beef0099 # Read test success when mprv=1 So translation should occur
 00000000
 0000000b # ecall from test termination from M mode
 00000000
+deadbeef # rest of the output space
+deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
deleted file mode 100644
index ce5c4cc3a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
+++ /dev/null
@@ -1,142 +0,0 @@
-0000000b # Test 11.3.1.1.3: ecall from going to S mode from M mode
-00000000
-beef0000 # Read test success from confirming writes of known values
-0000dead
-beef0055 # Read test success from confirming writes of known values
-0880dead
-beef0033 # Read test success from confirming writes of known values
-0990dead
-beef0077 # Read test success from confirming writes of known values
-0110dead
-beef0099 # Read test success from confirming writes of known values
-0220dead
-beef0440 # Read test success from confirming writes of known values
-0330dead
-beef0000 # Test 11.3.1.1.4: Read test success from checking translation works
-0000dead
-beef0055 # Read test success from checking translation works
-0880dead
-beef0099 # Read test success from checking translation works
-0220dead
-0000000d # Test 11.3.1.2.1: Read test with page fault from upper vaddr bits not the same
-00000000
-00000bad
-00000000
-0000000d # Read test with page fault from upper vaddr bits not the same
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.2.2: read test with page fault
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.2.3: write test with page fault
-00000000
-0000000d # Test 11.3.1.2.4: read test with page fault
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.2.5: 2 read tests with page faults
-00000000
-00000bad
-00000000
-0000000d # read 2
-00000000
-00000bad
-00000000
-00000111 # Test 11.3.1.3.1: execute test success
-00000000
-00000009 # ecall from going to U mode from S mode
-00000000
-0000000d # read test with page fault
-00000000
-00000bad
-00000000
-0000000c # execute test with page fault
-00000000
-00000bad
-00000000
-beef0033 # Test 11.3.1.3.2: read test success
-0990dead
-00000008 # ecall from going to S mode from U mode
-00000000
-beef0077 # read test success
-0110dead
-0000000c # execute test with page fault 
-00000000
-00000bad
-00000000
-0000000d # read test with page fault
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.3.3: read test with page fault 
-00000000
-00000bad
-00000000
-beef0440 # read test success
-0330dead
-beef0110 # Test 11.3.1.3.4: read test success
-0440dead
-0000000f # write test with page fault
-00000000
-0000000c # Test 11.3.1.3.5: execute test with page fault
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.3.6(a): write test with page fault
-00000000
-0000000d # read test with page fault
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.3.7(a): write test with page fault
-00000000
-beef0991 # read test success but nothing was written so read back default
-0880dead
-00000009 # ecall from going to M mode from S mode
-00000000
-0000000B # ecall from going to S mode from M mode
-00000000
-beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1 
-0990dead
-beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
-0440dead
-0000000d # Test 11.3.1.3.8: read test with page fault for nonzero reserved bit
-00000000
-00000bad
-00000000
-BEEF0660 # Test 11.3.1.3.9: NAPOT read
-0550DEAD
-0000000d # Test 11.3.1.3.9: page fault on malformed NAPOT PTE
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0
-00000000
-00000009 # ecall from going to M mode from S mode
-00000000
-0000000B # ecall from going to S mode from M mode
-00000000
-56567878 # write with PBMT = 1
-12123434
-56567878 # write with PBMT = 2
-23123434
-0000000f # write page fault because PBMT = 3
-00000000
-beef0000 # Test 11.3.1.4.1: read test success from new page table mapping
-0000dead
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
-00000000
-00000000 # previous mprv value before writing 1 to it.
-00000000
-beef0099 # Read test success when mprv=1 So translation should occur
-0220dead # even though we're in M mode with translation off
-0000000b # Test 11.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
-00000000
-00000009 # ecall from going to m mode from s mode (so we can access mstatus)
-00000000
-00000000 # previous mprv value zeroed out from mret after going to s mode.
-00000000
-0000000b # ecall from test termination from M mode
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output
index 450713c52..ee8ae119e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-01.reference_output
@@ -1,4 +1,4 @@
-0000000b # Test 11.3.1.1.3: ecall from going to S mode from M mode
+0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode
 00000000
 beef0cc0 # 8 read test successes
 0ee0dead
@@ -16,7 +16,7 @@ beef0440 # read 7
 0330dead
 beef0bb0 # read 8
 0440dead
-beef0cc0 # Test 11.3.1.1.4: 4 read test successes
+beef0cc0 # Test 12.3.1.1.4: 4 read test successes
 0ee0dead
 beef0000 # read 2
 0000dead
@@ -24,7 +24,7 @@ beef0055 # read 3
 0880dead
 beef0099 # read 4
 0220dead
-0000000d # Test 11.3.1.2.1: 2 read tests with page fault
+0000000d # Test 12.3.1.2.1: 2 read tests with page fault
 00000000
 00000bad
 00000000
@@ -32,17 +32,17 @@ beef0099 # read 4
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.2.2: read test with page fault
+0000000d # Test 12.3.1.2.2: read test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.2.3: write test with page fault
+0000000f # Test 12.3.1.2.3: write test with page fault
 00000000
-0000000d # Test 11.3.1.2.4: read test with page fault
+0000000d # Test 12.3.1.2.4: read test with page fault
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.2.5: 3 read tests with page fault
+0000000d # Test 12.3.1.2.5: 3 read tests with page fault
 00000000
 00000bad
 00000000
@@ -54,7 +54,7 @@ beef0099 # read 4
 00000000
 00000bad
 00000000
-00000111 # Test 11.3.1.3.1: Execute test success
+00000111 # Test 12.3.1.3.1: Execute test success
 00000000
 00000009 # ecall from going to U mode from S mode
 00000000
@@ -66,7 +66,7 @@ beef0099 # read 4
 00000000
 00000bad
 00000000
-beef0033 # Test 11.3.1.3.2: read test success
+beef0033 # Test 12.3.1.3.2: read test success
 0990dead
 00000008 # ecall from going to S mode from U mode
 00000000
@@ -80,39 +80,39 @@ beef0077 # read test success
 00000000
 00000bad
 00000000
-0000000d # Test 11.3.1.3.3: read test with page fault
+0000000d # Test 12.3.1.3.3: read test with page fault
 00000000
 00000bad
 00000000
 beef0440 # read test success
 0330dead
-beef0110 # Test 11.3.1.3.4: read test success
+beef0110 # Test 12.3.1.3.4: read test success
 0440dead
 0000000f # write test with page fault
 00000000
-0000000c # Test 11.3.1.3.5: executable test with page fault
+0000000c # Test 12.3.1.3.5: executable test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.3.6: write test with page fault
+0000000f # Test 12.3.1.3.6: write test with page fault
 00000000
 0000000d # read test with page fault
 00000000
 00000bad
 00000000
-0000000f # Test 11.3.1.3.7: write test with page fault
+0000000f # Test 12.3.1.3.7: write test with page fault
 00000000
 beef0bb0 # read test success
 0440dead
-beef0000 # Test 11.3.1.4.1: read test success on new page table mapping
+beef0000 # Test 12.3.1.4.1: read test success on new page table mapping
 0000dead 
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
+00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode
 00000000
 00000000 # previous value of mprv before write
 00000000
 beef0099 # Read test success when mprv=1 So translation should occur
 0220dead # even though we're in M mode with translation off
-0000000b # Test 11.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
+0000000b # Test 12.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
 00000000
 00000009 # ecall from going to m mode from s mode (so we can access mstatus)
 00000000
@@ -120,3 +120,905 @@ beef0099 # Read test success when mprv=1 So translation should occur
 00000000
 0000000b # ecall from test termination in S mode.
 00000000
+deadbeef # rest of the output space
+deadbeef
+deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output
deleted file mode 100644
index dd3801705..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv48-svadu-01.reference_output
+++ /dev/null
@@ -1,128 +0,0 @@
-0000000b # Test 11.3.1.1.3: ecall from going to S mode from M mode
-00000000
-beef0cc0 # 8 read test successes
-0ee0dead
-beef0000 # read 2
-0000dead
-beef0055 # read 3
-0880dead
-beef0033 # read 4
-0990dead
-beef0077 # read 5
-0110dead
-beef0099 # read 6
-0220dead
-beef0440 # read 7
-0330dead
-beef0cc0 # Test 11.3.1.1.4: 4 read test successes
-0ee0dead
-beef0000 # read 2
-0000dead
-beef0055 # read 3
-0880dead
-beef0099 # read 4
-0220dead
-0000000d # Test 11.3.1.2.1: 2 read tests with page fault
-00000000
-00000bad
-00000000
-0000000d # read 2
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.2.2: read test with page fault
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.2.3: write test with page fault
-00000000
-0000000d # Test 11.3.1.2.4: read test with page fault
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.2.5: 3 read tests with page fault
-00000000
-00000bad
-00000000
-0000000d # read 2
-00000000
-00000bad
-00000000
-0000000d # read 3
-00000000
-00000bad
-00000000
-00000111 # Test 11.3.1.3.1: Execute test success
-00000000
-00000009 # ecall from going to U mode from S mode
-00000000
-0000000d # read test with page fault
-00000000
-00000bad
-00000000
-0000000c # execute test with page fault
-00000000
-00000bad
-00000000
-beef0033 # Test 11.3.1.3.2: read test success
-0990dead
-00000008 # ecall from going to S mode from U mode
-00000000
-beef0077 # read test success
-0110dead
-0000000c # execute test with page fault
-00000000
-00000bad
-00000000
-0000000d # read test with page fault`
-00000000
-00000bad
-00000000
-0000000d # Test 11.3.1.3.3: read test with page fault
-00000000
-00000bad
-00000000
-beef0440 # read test success
-0330dead
-beef0110 # Test 11.3.1.3.4: read test success
-0440dead
-0000000f # write test with page fault
-00000000
-0000000c # Test 11.3.1.3.5: executable test with page fault
-00000000
-00000bad
-00000000 
-0000000f # Test 11.3.1.3.6(a): write test with page fault
-00000000
-0000000d # read test with page fault
-00000000
-00000bad
-00000000
-0000000f # Test 11.3.1.3.7(a): write test with page fault
-00000000
-deadbeef # read test success but get deadbeef because nothing was written
-deadbeef
-00000009 # ecall from going to M mode from S mode
-00000000
-0000000B # ecall from going to S mode from M mode
-00000000
-beef0770 # Test 11.3.1.3.6(b): check successful read/write when A=0 and SVADU=1
-0990dead
-beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
-0440dead
-beef0000 # Test 11.3.1.4.1: read test success on new page table mapping
-0000dead 
-00000009 # Test 11.3.1.5.1: ecall from going to m mode from s mode
-00000000
-00000000 # previous value of mprv before write
-00000000
-beef0099 # Read test success when mprv=1 So translation should occur
-0220dead # even though we're in M mode with translation off
-0000000b # Test 11.3.1.5.2 ecall from going to s mode from m mode (zeroing mprv)
-00000000
-00000009 # ecall from going to m mode from s mode (so we can access mstatus)
-00000000
-00000000 # previous mprv value zeroed out from mret after going to s mode.
-00000000
-0000000b # ecall from test termination in S mode.
-00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
index 64d1d7806..93e18c06d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
@@ -12,3 +12,1013 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output
index 6c2080fff..fd88590e3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph-01.reference_output
@@ -440,7 +440,7 @@ FFFFFFCC # serviced low ip
 00000065
 00000060
 00000001
-000000FF
+00000000
 00000000
 00000000
 00000000
@@ -488,7 +488,7 @@ FFFFFFFE
 0000006e
 00000060
 00000001
-000000FF
+00000000
 00000000
 00000000
 00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output
index b4f0eb957..f6434b676 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma-01.reference_output
@@ -144,3 +144,881 @@ ffffffff
 00000000
 0000000b # ecall from terminating tests in M mode
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output
index dd9c15aaa..ea5a0cb18 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output
@@ -54,3 +54,971 @@
 00000000
 00000009 # ecall from terminating tests in S mode
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output
index 8ad794f1d..e6728f2e0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output
@@ -1,6 +1,6 @@
 0000000b # Test *** Number: Ecall from going from M mode to S mode
 00000000
-00000001 # Instruction access fault from turning on virtual memory with invalid satp address
+00000002 # illegal instruction from truining on virtual memory with invalid satp address
 00000000
 00000009 # ecall from ending tests in S mode.
 00000000
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sie-01.reference_output
index a4592d3dd..9cefa2aa0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-sie-01.reference_output
@@ -12,3 +12,1013 @@
 00000000
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output
deleted file mode 100644
index bc17f4beb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output
+++ /dev/null
@@ -1,306 +0,0 @@
-00000003    # reset tests sck_div
-00000000
-00000000    # sck_mode
-00000000
-00000000    # cs_id
-00000000
-0000000F    # cs_def
-00000000
-00000000    # cs_mode
-00000000
-00010001    # delay 0
-00000000
-00000001    # delay 1
-00000000
-00080000    # fmt
-00000000    
-00000000    # tx_data
-00000000
-00000000    # tx_mark
-00000000
-00000000    # rx_mark
-00000000
-00000000    # ie reset
-00000000
-00000000    # ip reset
-00000000 
-00000000    # fifo watermark and edge case tests
-00000000
-00000001
-00000000
-00000003
-00000000
-00000003
-00000000
-00000074
-00000000
-00000063
-00000000
-00000052
-00000000
-00000041
-00000000
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-00000000
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-00000000
-00000001
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-00000000
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-00000000
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-00000000
-00000001
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-00000000
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-000000A7
-00000000
-000000B7
-00000000
-000000C7
-00000000
-00000002
-00000000
-000000D7
-00000000
-00000000
-00000000
-00000011 #basic read write
-00000000
-000000FF
-00000000
-000000AE
-00000000
-000000AD
-00000000
-000000AC
-00000000
-000000AB
-00000000
-000000AE
-00000000
-000000AD
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-00000000
-0000000B
-00000000
-000000F3
-00000000
-00000079
-00000000
-00000000
-00000000
-000000C0
-00000000
-00000011
-00000000
-00000020 #delay registers
-00000000
-00000032
-00000000
-00000048
-00000000
-000000AF
-00000000
-00000050
-00000000
-0000006B
-00000000
-00000011
-00000000
-00000015
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-00000000
-00000010
-00000000
-00000010
-00000000
-00000010
-00000000
-00000011
-00000000
-00000011
-00000000
-00000011
-00000000
-00000011
-00000000
-00000011
-00000000
-00000011
-00000000
-00000011 #delay1
-00000000
-00000022
-00000000
-00000033
-00000000
-00000044
-00000000
-0000007B
-00000000
-00000021
-00000000
-00000032
-00000000
-00000043
-00000000
-00000054
-00000000
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-00000000
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-00000000
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-00000000
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-00000000
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-00000000
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-00000000
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-00000000
-00000065
-00000000
-00000076
-00000000
-00000087
-00000000
-00000098
-00000000
-00000048
-00000000
-000000DD
-00000000
-000000CC
-00000000
-000000BB
-00000000
-000000AA
-00000000
-000000DE
-00000000
-000000CD
-00000000
-000000BC
-00000000
-000000AB
-00000000
-000000CE hold mode deassert
-00000000
-000000F0 #fmt register
-00000000
-00000000
-00000000
-00000080
-00000000
-00000000
-00000000
-00000080
-00000000
-000000A8
-00000000
-000000F8
-00000000
-00000048
-00000000
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-00000000
-00000000 
-00000000
-00000008
-00000000
-00000003
-00000000
-00000017
-00000000
-0000000F
-00000000
-0000001F
-00000000
-00000001 #watermark interrupts
-00000000
-00000000 #read mip
-00000000
-00000000 #read tx ip
-00000000 
-00000022 #clear 1 frame from rx fifo
-00000000
-00000000 # read recieve ip
-00000000
-00000002 #read recieve ip
-00000000
-00000000 #read mip
-00000000
-00000033 #clear frame
-00000000
-00000000 # read receive ip
-00000000
-00000044 #clear frame
-00000000
-00000055 #clear frame
-00000000
-00000001 #read tx ip
-00000000
-00000800 #read mip
-00000000
-00000022 #clear frame
-00000000
-00000000 #read rx ip
-00000000
-00000000 #read mip 94
-00000000
-00000002 #read rx ip
-00000000
-00000800 #read mip
-00000000
-00000033 #clear frame
-00000000
-00000000 #read rx wm
-00000000
-00000000 #read mip 99
-00000000
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
index 400ba8a9c..88c3a32f7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
@@ -10,3 +10,1015 @@
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 0000000b # mcause from M mode ecall from test termination
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output
index 6137356a4..9a4330543 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-mie-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output
index fe70c5c8a..273f04e8c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-sie-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tvm-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tvm-01.reference_output
index 17e6cf404..81c4993ea 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tvm-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tvm-01.reference_output
@@ -8,3 +8,1017 @@
 00000000
 00000009 # mcause from S mode ecall from test termination
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output
index f62af5979..5e277ede9 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output
@@ -16,3 +16,1009 @@
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 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
index 4f9ece298..769df3823 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
@@ -38,3 +38,987 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
index 0d4d58764..d77998a66 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,8 +1,3 @@
-
-FFFFFFFF # stimecmp low bits
-00000000 # stimecmp high bits
-00000000 # menvcfg low bits
-80000000 # menvcfg high bits
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
@@ -13,19 +8,19 @@ FFFFFFFF # stimecmp low bits
 00000000
 00000002 # mcause from an Illegal instruction
 00000000
-FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
+00000000 # mtval of faulting instruction (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000003 # mcause from Breakpoint
 00000000
-80000458 # mtval of breakpoint instruction adress (0x80000458)
+800003f4 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -37,7 +32,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # mcause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -113,8 +108,8 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
-00000000
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
+ffffffff
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
@@ -125,19 +120,19 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
 00000000
 00000002 # mcause from an Illegal instruction
 00000000
-FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
+00000000 # mtval of faulting instruction (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000003 # mcause from Breakpoint
 00000000
-80000458 # mtval of breakpoint instruction adress (0x80000458)
+800003f4 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -149,7 +144,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # mcause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -195,3 +190,835 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
index 6ee0e975f..fe559dfb7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
@@ -8,25 +8,25 @@
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # scause from an instruction access fault
 00000000
-00000000 # stval of faulting instruction address (0x00000000)
+00000000 # stval of faulting instruction address (0x0)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000002 # scause from an Illegal instruction
 00000000
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000458 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # scause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -60,6 +60,14 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
+0007ec01 # value to indicate successful vectoring on s soft interrupt 
+00000000
+00000001 # scause value from s soft interrupt
+80000000
+00000000 # stval for ssoft interrupt (0x0)
+00000000
+00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
 0007ec03 # value to indicate successful vectoring on m soft interrupt 
 00000000
 00000003 # scause value from m soft interrupt
@@ -98,8 +106,8 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
-00000000
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
+ffffffff
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000
 0000000b # scause from M mode ecall 
@@ -116,19 +124,19 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000002 # scause from an Illegal instruction
 00000000
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000458 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -140,7 +148,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # scause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -184,3 +192,833 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output
index 8c0e49170..240da5850 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output
@@ -16,3 +16,1009 @@
 00000000
 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
index 240fe10f0..39f874ef7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
@@ -8,25 +8,25 @@
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # scause from an instruction access fault
 00000000
-00000000 # stval of faulting instruction address (0x00000000)
+00000000 # stval of faulting instruction address (0x0)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000002 # scause from an Illegal instruction
 00000000
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000458 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # scause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -92,8 +92,8 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
-0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
-00000000
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
+ffffffff
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000
 0000000b # scause from M mode ecall 
@@ -110,19 +110,19 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000002 # scause from an Illegal instruction
 00000000
-FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
+00000000 # stval of faulting instruction (0x0)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000458 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-02000001 # mtval of misaligned address 
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -134,7 +134,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000006 # scause from store misaligned
 00000000
-02000001 # mtval of misaligned address 
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -164,3 +164,861 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-wfi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-wfi-01.reference_output
index 8bb320321..9bdbce963 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-wfi-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-wfi-01.reference_output
@@ -16,3 +16,1009 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 555244798..86568c12b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -57,11 +57,6 @@ RVTEST_CODE_BEGIN
     csrw sscratch, sp
     la sp, stack_top
 
-    // set up PMP so user and supervisor mode can access full address space
-    csrw pmpcfg0, 0xF   # configure PMP0 to TOR RWX
-    li t0, 0xFFFFFFFF   
-    csrw pmpaddr0, t0   # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
-
 .endm
 
 // Code to trigger traps goes here so we have consistent mtvals for instruction adresses
@@ -90,7 +85,7 @@ cause_instr_access:
     ret
 
 cause_illegal_instr:
-    .word 0xFFFFFFFF // 32 bit 1s is an illegal instruction
+    .word 0x00000000 // 32 bit zero is an illegal instruction
     ret
 
 cause_breakpnt:
@@ -98,8 +93,7 @@ cause_breakpnt:
     ret
 
 cause_load_addr_misaligned:
-    li t3, 0x02000000 // base address of clint, because with zicclsm misaligned cached access won't trap
-    //auipc t3, 0      // get current PC, which is aligned
+    auipc t3, 0      // get current PC, which is aligned
     addi t3, t3, 1
     lw t4, 0(t3)    // load from a misaligned address
     ret
@@ -109,8 +103,7 @@ cause_load_acc:
     ret
 
 cause_store_addr_misaligned:
-    li t3, 0x02000000 // base address of clint, because with zicclsm misaligned cached access won't trap
-    //auipc t3, 0      // get current PC, which is aligned
+    auipc t3, 0      // get current PC, which is aligned
     addi t3, t3, 1
     sw t4, 0(t3)     // store to a misaligned address
     ret
@@ -134,30 +127,22 @@ cause_m_time_interrupt:
     lw t2, 0(t5)         // low word of MTIME
     lw t6, 4(t5)         // high word of MTIME
     add t3, t2, t3       // add desired offset to the current time
-    bgtu t3, t2, nowrap_m  // check new time exceeds current time (no wraparound)
+    bgtu t3, t2, nowrap  // check new time exceeds current time (no wraparound)
     addi t6, t6, 1       // if wrap, increment most significant word
-nowrap_m:
     sw t6,4(t4)          // store into most significant word of MTIMECMP
+nowrap:
     sw t3, 0(t4)         // store into least significant word of MTIMECMP
-time_loop_m:
+time_loop:
     addi a3, a3, -1
-    bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt
+    bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
     ret
 
 cause_s_time_interrupt:
-    li t3, 0x30          // Desired offset from the present time
-    mv a3, t3            // copy value in to know to stop waiting for interrupt after this many cycles
-    // la t4, 0x02004000    // MTIMECMP register in CLINT 
-    la t5, 0x0200BFF8    // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it
-    lw t2, 0(t5)         // low word of MTIME
-    lw t6, 4(t5)         // high word of MTIME
-    add t3, t2, t3       // add desired offset to the current time
-    csrw stimecmp, t3     // store into most significant word of STIMECMP
-time_loop_s:
-    addi a3, a3, -1
-    bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
+    li t3, 0x20
+    csrs mip, t3 // set supervisor time interrupt pending.
+    nop // added extra nops in so the csrs can get through the pipeline before returning.
     ret
-    
+
 cause_m_soft_interrupt:
     la t3, 0x02000000      // MSIP register in CLINT
     li t4, 1               // 1 in the lsb
@@ -169,11 +154,6 @@ cause_s_soft_interrupt:
     csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
     ret
 
-cause_s_soft_from_m_interrupt:
-    li t3, 0x2
-    csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
-    ret
-
 cause_m_ext_interrupt:
     // ========== Configure PLIC ==========
     li a3, 0x40
@@ -276,7 +256,7 @@ end_trap_triggers:
     la t4, 0x02004000    // MTIMECMP register in CLINT
     li t5, 0xFFFFFFFF
     sd t5, 0(t4) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
- 
+
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
@@ -559,8 +539,7 @@ soft_interrupt_\MODE\():
 time_interrupt_\MODE\():
     la t0, 0x02004000    // MTIMECMP register in CLINT
     li t2, 0xFFFFFFFF
-    sd t2, 0(t0) // reset interrupt by setting mtimecmp to max
-    csrw stimecmp, t2 // reset stime interrupts by doing the same.
+    sd t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
     
     li t0, 0x20
     csrc \MODE\()ip, t0
@@ -886,7 +865,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 
     .equ PLIC_INTPRI_GPIO, 0x0C00000C       # GPIO is interrupt 3
     .equ PLIC_INTPRI_UART, 0x0C000028       # UART is interrupt 10
-    .equ PLIC_INTPRI_SPI,  0x0C000018       # SPI in interrupt 6
     .equ PLIC_INTPENDING0, 0x0C001000       # intPending0 register
     .equ PLIC_INTEN00,     0x0C002000       # interrupt enables for context 0 (machine mode) sources 31:1
     .equ PLIC_INTEN10,     0x0C002080       # interrupt enables for context 1 (supervisor mode) sources 31:1
@@ -899,7 +877,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     .8byte PLIC_THRESH1, 7, write32_test    # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts
     .8byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority
     .8byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority
-    .8byte PLIC_INTPRI_SPI,  7, write32_test # Set SPI to high priority
     .8byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode
     .8byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode
 .endm
@@ -1069,12 +1046,6 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
     sw t3, 0(t2)
     sw t4, -4(sp)
     addi sp, sp, -4
-    li t2, 0x0C000018 // SPI priority
-    li t3, 7
-    lw t4, 0(t2)
-    sw t3, 0(t2)
-    sw t4, -4(sp)
-    addi sp, sp, -4
     li t2, 0x0C002000
     li t3, 0x0C200004
     li t4, 0xFFF
@@ -1085,14 +1056,11 @@ claim_m_plic_interrupts: // clears one non-pending PLIC interrupt
     sw t6, 0(t2) // restore saved enable status
     li t2, 0x0C00000C // GPIO priority
     li t3, 0x0C000028 // UART priority
-    li t6, 0x0C000018 // SPI priority
-    lw a4, 8(sp) // load stored GPIO prioroty
-    lw t4, 4(sp) // load stored UART priority
-    lw t5, 0(sp) // load stored SPI priority
-    addi sp, sp, 12 // restore stack pointer
-    sw a4, 0(t2)
-    sw t4, 0(t3)
-    sw t5, 0(t6)
+    lw t4, 4(sp) // load stored GPIO and UART priority
+    lw t5, 0(sp)
+    addi sp, sp, 8 // restore stack pointer
+    sw t4, 0(t2)
+    sw t5, 0(t3)
     j test_loop
 
 claim_s_plic_interrupts: // clears one non-pending PLIC interrupt
@@ -1139,36 +1107,33 @@ uart_save_iir_status:
     j test_loop
 
 uart_data_wait:
-    li t2, 0x10000002
-    lbu t3, 0(t2) // save IIR before reading LSR might clear it
-    // Check IIR to see if theres an rxfifio or txempty interrupt and handle it before continuing.
-    li t2, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
-    beq t3, t2, uart_rxfifo_timout
-    li t2, 0xC2 // Value in IIR for Fifo Enabled, with txempty interrupt pending.
-    beq t3, t2, uart_txempty_intr
-    li t2, 0x10000005 // There needs to be an instruction here between the beq and the lb or the tests will hang
-    lb t4, 0(t2) // read LSR
-    li t2, 0x61
-    bne t4, t2, uart_data_wait // wait until all transmissions are done and data is ready
+    li t2, 0x10000005 // LSR
+    li t3, 0x10000002 // IIR
+    li a4, 0x61
+uart_read_LSR_IIR:
+    lbu t4, 0(t3) // save IIR before reading LSR might clear it
+    //  check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this.
+    li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending
+    beq t4, t5, uart_rxfifo_timout
+    lb t5, 0(t2) // read LSR
+    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
+    bne a4, t6, uart_read_LSR_IIR
     j uart_data_ready
 uart_rxfifo_timout:
-    li t2, 0x10000000 // read from the fifo to clear the rx timeout error
-    lb t5, 0(t2)
-    sb t5, 0(t2) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
-    j uart_data_wait
-uart_txempty_intr:
-    li t2, 0x10000002
-    lb t5, 0(t2) // Read IIR to clear this bit in LSR
-    j uart_data_wait
+    li t4, 0x10000000 // read from the fifo to clear the rx timeout error
+    lb t5, 0(t4)
+    sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur.
+    //read the fifo until empty
+    j uart_read_LSR_IIR
+
 
 uart_data_ready:
-    li t2, 0x10000002
-    lbu t3, 0(t2) // re read IIR
-    andi t4, t4, 0x9F // mask THRE and TEMT from IIR signature
     li t2, 0
     sd t2, 0(t1) // clear entry deadbeef from memory
-    sb t3, 1(t1) // IIR
-    sb t4, 0(t1) // LSR
+    lbu t4, 0(t3) // re read IIR
+    andi t5, t5, 0x9F // mask THRE and TEMT from signature
+    sb t4, 1(t1) // IIR
+    sb t5, 0(t1) // LSR
     addi t1, t1, 8
     addi a6, a6, 8
     j test_loop
@@ -1178,34 +1143,6 @@ uart_clearmodemintr:
     lb t2, 0(t2)
     j test_loop
 
-spi_data_wait:
-    li t2, 0x10040054
-    sw t4, 0(t2) // set rx watermark level 
-    li t2, 0x10040074
-    lw t3, 0(t2) //read ip (interrupt pending register)
-    slli t3, t3, 56
-    srli t3, t3, 56
-    li t2, 0x00000002
-    bge t3, t2, spi_data_ready //branch to done if transmission complete
-    j spi_data_wait //else check again 
-
-spi_data_ready:
-    li t2, 0x10040070
-    li t3, 0x00000000
-    sw t3, 0(t2) //disable rx watermark interrupt
-    j test_loop
-
-spi_burst_send: //function for loading multiple frames at once to test delays without returning to test loop
-    mv t2, t4
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    srli t2, t2, 8
-    sw t2, 0(t3)
-    j test_loop
-
 goto_s_mode:
     // return to address in t3, 
     li a0, 3 // Trap handler behavior (go to supervisor mode)
@@ -1403,12 +1340,6 @@ write_mideleg:
     csrw mideleg, t4
     j test_loop
 
-write_menvcfg:
-    // writes the value in t4 to the menvcfg register
-    // Doesn't log anything
-    csrw menvcfg, t4
-    j test_loop
-
 executable_test:
     // Execute the code at the address in t3, returning the value in t2.
     // Assumes the code modifies t2, to become the value stored in t4 for this test.  
@@ -1463,9 +1394,6 @@ RVMODEL_DATA_BEGIN
 test_1_res:
     .fill 1024, 4, 0xdeadbeef
 
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
 
 #ifdef rvtest_mtrap_routine
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S
new file mode 100644
index 000000000..1d246a54b
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo-01.S
@@ -0,0 +1,258 @@
+///////////////////////////////////////////
+// WALLY-AMO.S
+//
+// Tests Atomic AMO instructions
+//
+// David_Harris@hmc.edu 10 March 2021
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Adapted from Imperas RISCV-TEST_SUITE
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV64IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo)
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+
+    # ---------------------------------------------------------------------------------------------
+    # Addresses for test data and results
+    la x6, wally_signature
+    la x31, test_data
+
+    # Testcase 0:  amoswap.w
+    li x7, 1
+    amoswap.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be fffffffffffffffe (sign extended from test data)
+    sd x9, 8(x6)        # should be 0000000000000001 (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 1:  amoadd.w
+    li x7, 2
+    amoadd.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be fffffffffffffffb (sign extended from test data)
+    sd x9, 8(x6)        # should be fffffffffffffffd (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 2:  amoand.w
+    li x7, 0x7ff
+    amoand.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be ffffffffffffffef (sign extended from test data)
+    sd x9, 8(x6)        # should be 00000000000007ef (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 3:  amoor.w
+    li x7, 0x44
+    amoor.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be ffffffffffffffbf (sign extended from test data)
+    sd x9, 8(x6)        # should be ffffffffffffffff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 4:  amoxor.w
+    li x7, 0x381
+    amoxor.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be fffffffffffffeff (sign extended from test data)
+    sd x9, 8(x6)        # should be fffffffffffffd7e (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 5:  amomax.w
+    li x7, 0x7ff
+    amomax.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be fffffffffffffeff (sign extended from test data)
+    sd x9, 8(x6)        # should be 00000000000007ff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 6:  amomin.w
+    li x7, 0x7fd
+    amomin.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be ffffffffffffefff (sign extended from test data)
+    sd x9, 8(x6)        # should be ffffffffffffefff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 7:  amomaxu.w
+    li x7, 0x7fb
+    amomaxu.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be ffffffffffffefff (sign extended from test data)
+    sd x9, 8(x6)        # should be ffffffffffffefff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 8:  amominu.w
+    li x7, 0x7fa
+    amominu.w x8, x7, (x31)
+    lw x9, 0(x31)
+    sd x8, 0(x6)        # should be fffffffffffeffff (sign extended from test data)
+    sd x9, 8(x6)        # should be 00000000000007fa (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+
+    # Testcase 9:  amoswap.d
+    li x7, 1
+    amoswap.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xfff7fffffffbffff (directly read from test data)
+    sd x9, 8(x6)        # should be 0000000000000001 (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 10:  amoadd.d
+    li x7, 2
+    amoadd.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xffdfffffffefffff (directly read from test data)
+    sd x9, 8(x6)        # should be 0xffdffffffff00001 (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 11:  amoand.d
+    li x7, 0x7cf
+    amoand.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xff7fffffffbfffff (directly read from test data)
+    sd x9, 8(x6)        # should be 00000000000007cf (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 12:  amoor.d
+    li x7, 0x0d000011
+    amoor.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xfdfffffffeffffff (directly read from test data)
+    sd x9, 8(x6)        # should be 0xfdffffffffffffff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 13:  amoxor.d
+    li x7, 0x381
+    amoxor.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xf7fffffffeffffff (directly read from test data)
+    sd x9, 8(x6)        # should be 0xf7fffffffefffc7e (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 14:  amomax.d
+    li x7, 0x7ff
+    amomax.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0xdfffffffefffffff (directly read from test data)
+    sd x9, 8(x6)        # should be 00000000000007ff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 15:  amomin.d
+    li x7, 0x7fd
+    amomin.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0x7fffffffefffffff (directly read from test data)
+    sd x9, 8(x6)        # should be 00000000000007fd (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 16:  amomaxu.d
+    li x7, 0x7fb
+    amomaxu.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0x00000001ffffffff (directly read from test data)
+    sd x9, 8(x6)        # should be 0x00000001ffffffff (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # Testcase 17:  amominu.d
+    li x7, 0x7fa
+    amominu.d x8, x7, (x31)
+    ld x9, 0(x31)
+    sd x8, 0(x6)        # should be 0x0000000400000002 (directly read from test data)
+    sd x9, 8(x6)        # should be 00000000000007fa (stored by amo)
+    addi x31, x31, 8
+    addi x6, x6, 16
+
+    # ---------------------------------------------------------------------------------------------
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+    .align 8
+test_data:
+    .dword 0xfffffffdfffffffe
+    .dword 0xfffffff7fffffffb
+    .dword 0xffffffdfffffffef
+    .dword 0xffffff7fffffffbf
+    .dword 0xfffffdfffffffeff
+    .dword 0xfffff7fffffffeff
+    .dword 0x0fffdfffffffefff
+    .dword 0xffff7fffffffefff
+    .dword 0x3ffdfffffffeffff
+    .dword 0xfff7fffffffbffff
+    .dword 0xffdfffffffefffff
+    .dword 0xff7fffffffbfffff
+    .dword 0xfdfffffffeffffff
+    .dword 0xf7fffffffeffffff
+    .dword 0xdfffffffefffffff
+    .dword 0x7fffffffefffffff
+    .dword 0x00000001ffffffff
+    .dword 0x0000000400000002
+    .dword 0x0000001000000008
+    .dword 0x0000004000000020
+    .dword 0x0000010000000080
+    .dword 0x0000040000000200
+    .dword 0x0000100000000800
+    .dword 0x0000400000002000
+    .dword 0x0000000100008000
+    .dword 0x0004000000000002
+    .dword 0x0000001000080000
+    .dword 0x0040000000000020
+    .dword 0x0000010000800000
+    .dword 0x0400000000000200
+    .dword 0x0000100008000000
+    .dword 0x4000000000002000
+    .dword 0x0000000080000000
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+# signature output
+wally_signature:
+.fill 36, 8, -1
+
+#ifdef rvtest_mtrap_routine
+#mtrap_sigptr:
+#    .fill 64*(XLEN/32),4,0xdeadbeef
+#endif
+
+#ifdef rvtest_gpr_save
+#gpr_save:
+#    .fill 32*(XLEN/32),4,0xdeadbeef
+#endif
+RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
deleted file mode 100644
index e0c724aec..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
+++ /dev/null
@@ -1,633 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-cache-management-tests 
-// invalidate, clean, and flush
-//
-// Author: Rose Thompson <rose@rosethompson.net>
-//
-// Created 18 August 2023
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-# Purpose: Tests the 3 Zicbom cache instructions which all operate on cacheline
-#          granularity blocks of memory.  Invalidate: Clears valid and dirty bits
-#          and does not write back.  Clean: Writes back dirty cacheline if needed
-#          and clears dirty bit.  Does NOT clear valid bit.  Flush:  Cleans and then
-#          Invalidates.  These operations apply to all caches in the memory system.
-#          The tests are divided into three parts one for the data cache
-#          and checks to verify the uncached regions of memory cause exceptions.
-# -----------
-# Copyright (c) 2020. RISC-V International. All rights reserved.
-# SPDX-License-Identifier: BSD-3-Clause
-# -----------
-#
-# This assembly file tests the cbo.inval, cbo.clean, and cbo.flush instructions of the RISC-V Zicbom extension.
-# 
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I_Zicbom")
-# Test code region
-.section .text.init
-.globl rvtest_entry_point
-	
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.inval)
-
-RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
-	
-CBOMTest:
-        # *** TODO
-        # first need to discover the length of the cacheline.
-        # for now assume it is 64 bytes
-
-        #addi sp, sp, -16
-        #sd s0, 0(sp)
-        #sd ra, 8(sp)
-
-	la s0, signature
-
-        ################################################################################
-        # INVALIDATE  D$
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Invalidate the second region
-        # 4. Verify the second region has the original invalid data
-        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
-        # but the next should have the copied data.
-
-        # step 1
-CBOMTest_inval_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcpy8
-
-        # step 2
-CBOMTest_inval_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 3
-CBOMTest_inval_step3: 
-        la a1, Destination1
-        cbo.inval (a1)
-        # step 4  (should be Invalid)
-        la a0, DeadBeafData1
-        la a1, Destination1
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-        # step 4 next line (should still be valid)
-CBOMTest_inval_step4: 
-        la a0, SourceData+64
-        la a1, Destination1+64
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-        # step 3 (Invalidate all remaining lines)
-CBOMTest_inval_step3_all: 
-        la a1, Destination1+64
-        cbo.inval (a1)
-        cbo.inval (a1)          # verify invalidating an already non present line does not cause an issue.
-        la a1, Destination1+128
-        cbo.inval (a1)
-        la a1, Destination1+192
-        cbo.inval (a1)
-        la a1, Destination1+256
-        cbo.inval (a1)
-        la a1, Destination1+320
-        cbo.inval (a1)
-        la a1, Destination1+384
-        cbo.inval (a1)
-        la a1, Destination1+448
-        cbo.inval (a1)
-	
-        # step 4 All should be invalid
-CBOMTest_inval_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-        ################################################################################
-        # INVALIDATE  all ways D$
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Invalidate the second region
-        # 4. Verify the second region has the original invalid data
-        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
-        # but the next should have the copied data.
-	
-        # step 0 copy deadbeef to remote regions spaced 4KiB apart
-CBOMTest_way_inval_4096_step0: 
-        la a0, DeadBeafData1
-        la a1, Destination1+4096
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_8192_step0: 
-        la a0, DeadBeafData1
-        la a1, Destination1+8192
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_12288_step0: 
-        la a0, DeadBeafData1
-        la a1, Destination1+12288
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_16384_step0:       
-        la a0, DeadBeafData1
-        la a1, Destination1+16384
-        li a2, 8
-        jal ra, memcpy8
-        # one of the following will force an eviction of each of the previous
-CBOMTest_way_inval_20480_step0:       # this one should force eviction of _4096
-        la a0, DeadBeafData1
-        la a1, Destination1+20480
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_24576_step0:       # this one should force eviction of _4096
-        la a0, DeadBeafData1
-        la a1, Destination1+24576
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_28672_step0:       # this one should force eviction of _4096
-        la a0, DeadBeafData1
-        la a1, Destination1+28672
-        li a2, 8
-        jal ra, memcpy8
-CBOMTest_way_inval_32768_step0:       # this one should force eviction of _4096
-        la a0, DeadBeafData1
-        la a1, Destination1+32768
-        li a2, 8
-        jal ra, memcpy8
-        
-        # step 1
-CBOMTest_way_inval_4096_step1: 
-        la a0, SourceData
-        la a1, Destination1+4096
-        li a2, 8
-        jal ra, memcpy8
-
-CBOMTest_way_inval_8192_step1: 
-        la a0, SourceData
-        la a1, Destination1+8192
-        li a2, 8
-        jal ra, memcpy8
-
-CBOMTest_way_inval_12288_step1: 
-        la a0, SourceData
-        la a1, Destination1+12288
-        li a2, 8
-        jal ra, memcpy8
-        
-CBOMTest_way_inval_16384_step1: 
-        la a0, SourceData
-        la a1, Destination1+16384
-        li a2, 8
-        jal ra, memcpy8
-
-        # don't want to ca      use a write back for the previous writes since we want to invalidate them
-	
-        # step 2
-CBOMTest_way_inval_4096_step2: 
-        la a0, SourceData
-        la a1, Destination1+4096
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-	
-CBOMTest_way_inval_8192_step2: 
-        la a0, SourceData
-        la a1, Destination1+8192
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-CBOMTest_way_inval_12288_step2: 
-        la a0, SourceData
-        la a1, Destination1+12288
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-CBOMTest_way_inval_16384_step2: 
-        la a0, SourceData
-        la a1, Destination1+16384
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-CBOMTest_way_inval_step3_all_again: 
-        la a1, Destination1+4096
-        la a2, Destination1+8192
-        la a3, Destination1+12288
-        la a4, Destination1+16384
-        cbo.inval (a1)
-        cbo.inval (a2)          
-        cbo.inval (a3)
-        cbo.inval (a4)          
-        
-        # step 4 All should be invalid
-CBOMTest_way_inval_4096_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1+4096
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-CBOMTest_way_inval_8192_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1+8192
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-CBOMTest_way_inval_12288_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1+12288
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-	
-CBOMTest_way_inval_16384_step4_all: 
-        la a0, DeadBeafData1
-        la a1, Destination1+16384
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-	
-        ################################################################################
-        # Clean D$
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Invalidate the second region
-        # 4. Verify the second region has the original invalid data
-        # 5. Repeat step 1
-        # 6. Clean cachelines
-        # 7. Verify the second region has the same data
-        # 8. Invalidate the second region
-        # 9. Verify again but this time it should contain the same data
-        # DON'T batch each step.  We want to see the transition between cachelines. The current should be invalidated
-        # but the next should have the copied data.
-        
-        # step 1
-CBOMTest_clean_step1: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 64
-        jal ra, memcpy8
-
-        # step 2
-CBOMTest_clean_step2:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 3
-CBOMTest_clean_step3:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-        la a1, Destination2+128
-        cbo.inval (a1)
-        la a1, Destination2+192
-        cbo.inval (a1)
-        la a1, Destination2+256
-        cbo.inval (a1)
-        la a1, Destination2+320
-        cbo.inval (a1)
-        la a1, Destination2+384
-        cbo.inval (a1)
-        la a1, Destination2+448
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-        cbo.inval (a1)
-
-        # step 4 All should be invalid
-CBOMTest_clean_step4:
-        la a0, DeadBeafData1
-        la a1, Destination2
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-        
-        # step 5
-CBOMTest_clean_step5:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 64
-        jal ra, memcpy8
-
-        # step 6  only clean 1 line
-CBOMTest_clean_step6:
-        la a1, Destination2
-        cbo.clean (a1)
-	
-        # step 7  only check that 1 line
-CBOMTest_clean_step7:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 8  invalidate that 1 line and the next
-CBOMTest_clean_step8:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-	
-        # step 9  that 1 line should contain the valid data
-CBOMTest_clean_step9_line1:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 9 the next should contain the invalid data
-CBOMTest_clean_step9_line2:
-        la a0, DeadBeafData1
-        la a1, Destination2+64
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 5 # now recopy the one we just corrupted
-CBOMTest_clean_step5_recopy_line2:
-        la a0, SourceData+64
-        la a1, Destination2+64
-        li a2, 8
-        jal ra, memcpy8
-
-        # step 6 # clean the remaining
-CBOMTest_clean_step6_clean_all:
-        la a1, Destination2+64
-        cbo.clean (a1)
-        la a1, Destination2+128
-        cbo.clean (a1)
-        la a1, Destination2+192
-        cbo.clean (a1)
-        la a1, Destination2+256
-        cbo.clean (a1)
-        la a1, Destination2+320
-        cbo.clean (a1)
-        la a1, Destination2+384
-        cbo.clean (a1)
-        la a1, Destination2+448
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-        cbo.clean (a1)
-	
-        # step 8 # invalidate all remaining
-CBOMTest_clean_step7_invalidate_all:
-        la a1, Destination2
-        cbo.inval (a1)
-        la a1, Destination2+64
-        cbo.inval (a1)
-        la a1, Destination2+128
-        cbo.inval (a1)
-        la a1, Destination2+192
-        cbo.inval (a1)
-        la a1, Destination2+256
-        cbo.inval (a1)
-        la a1, Destination2+320
-        cbo.inval (a1)
-        la a1, Destination2+384
-        cbo.inval (a1)
-        la a1, Destination2+448
-        cbo.inval (a1)
-	
-        # step 9 # check all
-CBOMTest_clean_step9_check_all:
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        ################################################################################
-        # Flush D$ line
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. For flush there is no way to create a negative control. We will flush 1 cache line
-        # 4. Verify whole region
-        # 5. Flush the remaining lines
-        # 6. Verify whole region
-
-        # step 1
-CBOMTest_flush_step1: 
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 64
-        jal ra, memcpy8
-
-        # step 2 All should be valid
-CBOMTest_flush_step2_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 3 # flush 1 line
-CBOMTest_flush_step3:
-        la a1, Destination3
-        cbo.flush (a1)
-
-        # step 4 
-CBOMTest_flush_step4_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 5
-CBOMTest_flush_step5_flush_all:
-        la a1, Destination3
-        cbo.flush (a1)
-        la a1, Destination3+64
-        cbo.flush (a1)
-        la a1, Destination3+128
-        cbo.flush (a1)
-        la a1, Destination3+192
-        cbo.flush (a1)
-        la a1, Destination3+256
-        cbo.flush (a1)
-        la a1, Destination3+320
-        cbo.flush (a1)
-        la a1, Destination3+384
-        cbo.flush (a1)
-        la a1, Destination3+448
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-        cbo.flush (a1)
-	
-        # step 6
-CBOMTest_flush_step6_verify:
-        la a0, SourceData
-        la a1, Destination3
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-        
-
-        #ld s0, 0(sp)
-        #ld ra, 8(sp)
-        #addi sp, sp, 16
-        #ret
-RVMODEL_HALT
-
-	
-.type memcpy8, @function
-memcpy8:        
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcpy8_loop:   
-        ld t3, 0(t0)
-        sd t3, 0(t1)
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_loop
-        ret
-
-.type memcmp8, @function
-# returns which index mismatch, -1 if none
-memcmp8:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp8_loop:
-        ld t3, 0(t0)
-        ld t4, 0(t1)
-        bne t3, t4, memcmp8_ne
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcmp8_loop
-        li a0, -1
-        ret
-memcmp8_ne:
-        mv a0, t2
-        ret
-
-RVTEST_CODE_END
-        
-
-RVTEST_DATA_BEGIN
-# Input data section.
-#.data
-.align 7
-
-DeadBeafData1:
-        .fill 128, 4, 0xdeadbeef
-SourceData:
-        .int 0, 1, 2, 3, 4, 5, 6, 7
-        .int 8, 9, 10, 11, 12, 13, 14, 15
-        .int 16, 17, 18, 19, 20, 21, 22, 23
-        .int 24, 25, 26, 27, 28, 29, 30, 31
-        .int 32, 33, 34, 35, 36, 37, 38, 39
-        .int 40, 41, 42, 43, 44, 45, 46, 47
-        .int 48, 49, 50, 51, 52, 53, 54, 55
-        .int 56, 57, 58, 59, 60, 61, 62, 63
-        .int 64, 65, 66, 67, 68, 69, 70, 71
-        .int 72, 73, 74, 75, 76, 77, 78, 79
-        .int 80, 81, 82, 83, 84, 85, 86, 87
-        .int 88, 89, 90, 91, 92, 93, 94, 95
-        .int 96, 97, 98, 99, 100, 101, 102, 103
-        .int 104, 105, 106, 107, 108, 109, 110, 111
-        .int 112, 113, 114, 115, 116, 117, 118, 119
-        .int 120, 121, 122, 123, 124, 125, 126, 127
-
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-        .fill 28, 4, 0xdeadbeef   # this is annoying, but RVMODEL_DATA_END and BEGIN insert
-        # 4 bytes.  This needs to be aligned to a cacheline
-
-        .align 6
-Destination1:
-        .fill 128, 4, 0xdeadbeef
-Destination2:   
-        .fill 128, 4, 0xdeadbeef
-Destination3:
-        .fill 128, 4, 0xdeadbeef
-signature:
-        .fill 44, 4, 0x0bad0bad
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-	
-RVMODEL_DATA_END
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S
deleted file mode 100644
index 0e615a943..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S
+++ /dev/null
@@ -1,380 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-cache-management-tests 
-// invalidate, clean, and flush
-//
-// Author: Rose Thompson <rose@rosethompson.net>
-//
-// Created 22 August 2023
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-# Purpose: Tests the Zicboz cache instruction which all operate on cacheline
-#          granularity blocks of memory.  The instruction cbo.zero allocates a cacheline
-#          and writes 0 to each byte.  A dirty cacheline is overwritten, any data in main
-#          memory is over written.        
-# -----------
-# Copyright (c) 2020. RISC-V International. All rights reserved.
-# SPDX-License-Identifier: BSD-3-Clause
-# -----------
-#
-# This assembly file tests the cbo.zero instruction of the RISC-V Zicboz extension.
-# 
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I_Zicboz_Zicbom")
-# Test code region
-.section .text.init
-.globl rvtest_entry_point
-	
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero)
-
-RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")
-	
-CBOZTest:
-        # *** TODO
-        # first need to discover the length of the cacheline.
-        # for now assume it is 64 bytes
-
-        #addi sp, sp, -16
-        #sd s0, 0(sp)
-        #sd ra, 8(sp)
-
-	la s0, signature
-
-        ################################################################################
-        # Zero cache line hit overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Zero that region of memory
-        # 4. Verify the second region is all zero.
-
-        # step 1
-CBOZTest_zero_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcpy8
-
-        # step 2
-CBOZTest_zero_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 3
-CBOZTest_zero_step3: 
-        la a1, Destination1
-        cbo.zero (a1)
-        la a1, Destination1+64
-        cbo.zero (a1)
-        la a1, Destination1+128
-        cbo.zero (a1)
-        la a1, Destination1+192
-        cbo.zero (a1)
-        la a1, Destination1+256
-        cbo.zero (a1)
-        la a1, Destination1+320
-        cbo.zero (a1)
-        la a1, Destination1+384
-        cbo.zero (a1)
-        la a1, Destination1+448
-        cbo.zero (a1)
-
-CBOZTest_zero_step4:    
-        # step 4  (should be zero)
-        la a0, ZeroData
-        la a1, Destination1
-        li a2, 64
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-        ################################################################################
-        # Verify cbo.zero miss overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
-        # 2. Then verify the second region has the same data
-        # 3. Flush that one line
-        # 4. Zero that one line
-        # 5. Verify the second region is zero
-
-        # step 1
-CBOZTest_miss_zero_step1: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 8
-        jal ra, memcpy8
-
-        # step 2
-CBOZTest_miss_zero_step2: 
-        la a0, SourceData
-        la a1, Destination1
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 3
-CBOZTest_miss_zero_step3: 
-        la a1, Destination1
-        cbo.flush (a1)
-        cbo.zero (a1)
-
-CBOZTest_miss_zero_step4:    
-        # step 4  (should be Invalid)
-        la a0, ZeroData
-        la a1, Destination1
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-	
-        ################################################################################
-        # Verify cbo.zero miss with eviction overwrites
-        ################################################################################
-
-        # theory of operation
-        # 1. Read 1 cacheline of data from memory into the d cache and copy to a second region of memory
-        # 2. Repeate 1 four times at 4KiB intervals
-        # 2. Then verify the second region has the same data
-        # 4. Zero each line
-        # 5. Verify the second region is zero
-
-        # step 1
-CBOZTest_eviction_zero_step1_0: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 8
-        jal ra, memcpy8
-
-CBOZTest_eviction_zero_step2_4096: 
-        la a0, SourceData+8
-        la a1, Destination2+4096
-        li a2, 8
-        jal ra, memcpy8
-
-CBOZTest_eviction_zero_step2_8192: 
-        la a0, SourceData+16
-        la a1, Destination2+8192
-        li a2, 8
-        jal ra, memcpy8
-
-CBOZTest_eviction_zero_step2_12288: 
-        la a0, SourceData+24
-        la a1, Destination2+12288
-        li a2, 8
-        jal ra, memcpy8
-
-CBOZTest_eviction_zero_step2_16384: 
-        la a0, SourceData+32
-        la a1, Destination2+16384
-        li a2, 8
-        jal ra, memcpy8
-
-        # step 3
-CBOZTest_eviction_zero_step3_0: 
-        la a0, SourceData
-        la a1, Destination2
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-CBOZTest_eviction_zero_step3_4096: 
-        la a0, SourceData+8
-        la a1, Destination2+4096
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-CBOZTest_eviction_zero_step3_8192: 
-        la a0, SourceData+16
-        la a1, Destination2+8192
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-        
-CBOZTest_eviction_zero_step3_12288: 
-        la a0, SourceData+24
-        la a1, Destination2+12288
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-        
-CBOZTest_eviction_zero_step3_16384: 
-        la a0, SourceData+32
-        la a1, Destination2+16384
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)     # should be -1
-        addi s0, s0, 8
-
-        # step 4
-CBOZTest_eviction_zero_step4: 
-        la a1, Destination2
-        cbo.zero (a1)
-        la a1, Destination2+4096
-        cbo.zero (a1)
-        la a1, Destination2+8192
-        cbo.zero (a1)
-        la a1, Destination2+12288
-        cbo.zero (a1)
-        la a1, Destination2+16384
-        cbo.zero (a1)
-
-CBOZTest_eviction_zero_step5_0:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-CBOZTest_eviction_zero_step5_4096:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+4096
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-        
-CBOZTest_eviction_zero_step5_8192:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+8192
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-
-CBOZTest_eviction_zero_step5_12288:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+12288
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-        
-CBOZTest_eviction_zero_step5_16384:
-        # step 5  (should be zero)
-        la a0, ZeroData
-        la a1, Destination2+16384
-        li a2, 8
-        jal ra, memcmp8
-        sd a0, 0(s0)    # should be -1
-        addi s0, s0, 8
-	
-
-        #ld s0, 0(sp)
-        #ld ra, 8(sp)
-        #addi sp, sp, 16
-        #ret
-RVMODEL_HALT
-
-	
-.type memcpy8, @function
-memcpy8:        
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcpy8_loop:   
-        ld t3, 0(t0)
-        sd t3, 0(t1)
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_loop
-        ret
-
-.type memcmp8, @function
-# returns which index mismatch, -1 if none
-memcmp8:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp8_loop:
-        ld t3, 0(t0)
-        ld t4, 0(t1)
-        bne t3, t4, memcmp8_ne
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcmp8_loop
-        li a0, -1
-        ret
-memcmp8_ne:
-        mv a0, t2
-        ret
-
-RVTEST_CODE_END
-        
-
-RVTEST_DATA_BEGIN
-# Input data section.
-#.data
-.align 7
-
-ZeroData:
-        .fill 128, 4, 0x0
-SourceData:
-        .int 0, 1, 2, 3, 4, 5, 6, 7
-        .int 8, 9, 10, 11, 12, 13, 14, 15
-        .int 16, 17, 18, 19, 20, 21, 22, 23
-        .int 24, 25, 26, 27, 28, 29, 30, 31
-        .int 32, 33, 34, 35, 36, 37, 38, 39
-        .int 40, 41, 42, 43, 44, 45, 46, 47
-        .int 48, 49, 50, 51, 52, 53, 54, 55
-        .int 56, 57, 58, 59, 60, 61, 62, 63
-        .int 64, 65, 66, 67, 68, 69, 70, 71
-        .int 72, 73, 74, 75, 76, 77, 78, 79
-        .int 80, 81, 82, 83, 84, 85, 86, 87
-        .int 88, 89, 90, 91, 92, 93, 94, 95
-        .int 96, 97, 98, 99, 100, 101, 102, 103
-        .int 104, 105, 106, 107, 108, 109, 110, 111
-        .int 112, 113, 114, 115, 116, 117, 118, 119
-        .int 120, 121, 122, 123, 124, 125, 126, 127
-
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-        .fill 28, 4, 0xdeadbeef   # this is annoying, but RVMODEL_DATA_END and BEGIN insert
-        # 4 bytes.  This needs to be aligned to a cacheline
-
-        .align 6
-Destination1:
-        .fill 128, 4, 0xdeadbeef
-Destination2:   
-        .fill 16, 4, 0xdeadbeef
-signature:
-        .fill 32, 4, 0x0bad0bad
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-	
-RVMODEL_DATA_END
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
index 3aaa58706..838e4654d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
index 410dd78ea..2ff2e99f2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s)
 
 INIT_TESTS
 
@@ -45,7 +45,7 @@ WRITE_READ_CSR mvendorid, 0x111
 WRITE_READ_CSR marchid, 0x111
 WRITE_READ_CSR mimpid, 0x111
 WRITE_READ_CSR mhartid, 0x111
-WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
 WRITE_READ_CSR mstatus, 0x111
@@ -62,10 +62,12 @@ WRITE_READ_CSR mepc, 0x111
 WRITE_READ_CSR mcause, 0x111
 WRITE_READ_CSR mtval, 0x111
 WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-WRITE_READ_CSR menvcfg, 0x111
-WRITE_READ_CSR mseccfg, 0x111
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
 WRITE_READ_CSR pmpcfg0, 0x111
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
index b03d44a92..848186a98 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u)
 
 INIT_TESTS
 
@@ -61,7 +61,7 @@ WRITE_READ_CSR mvendorid, 0x111
 WRITE_READ_CSR marchid, 0x111
 WRITE_READ_CSR mimpid, 0x111
 WRITE_READ_CSR mhartid, 0x111
-WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
+# WRITE_READ_CSR mconfigptr, 0x111 # mconfigptr unimplemented in spike as of 31 Jan 22
 
 # Machine Trap Setup
 WRITE_READ_CSR mstatus, 0x111
@@ -78,10 +78,12 @@ WRITE_READ_CSR mepc, 0x111
 WRITE_READ_CSR mcause, 0x111
 WRITE_READ_CSR mtval, 0x111
 WRITE_READ_CSR mip, 0x111
+# WRITE_READ_CSR mtinst, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mtval2, 0x111
 
 # Machine Configuration
-WRITE_READ_CSR menvcfg, 0x111
-WRITE_READ_CSR mseccfg, 0x111
+# WRITE_READ_CSR menvcfg, 0x111 # *** these appear not to be implemented in GCC
+# WRITE_READ_CSR mseccgf, 0x111
 
 # Machine Memory Protection
 WRITE_READ_CSR pmpcfg0, 0x111
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
index b5505e1b1..38bc6fd18 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
index c991721ea..6e3ebcbcb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
index 6258b0807..3cf332f6b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
@@ -48,7 +48,7 @@ RVMODEL_BOOT
 
  # Testcase 1:  Do an unsuccessful load-reserved / store conditional word operation
 	addi x6, x6, 24
-    addi x30, x31, 8    # 8 bytes later (reservation set size is 8 bytes)
+    addi x30, x31, 4
     li x11, 43
     lr.w x10, (x30)
     sc.w x12, x11, (x31)  # should fail because not reserved
@@ -59,7 +59,7 @@ RVMODEL_BOOT
 
     # Testcase 2:  Do a successful load-reserved / store conditional doubleword operation
  	addi x6, x6, 24
-    addi x31, x30, 8
+    addi x31, x30, 4
     li x11, 44
     lr.d x10, (x31)
     sc.d x12, x11, (x31)
@@ -135,7 +135,4 @@ RVMODEL_DATA_BEGIN
 wally_signature:
 .fill 12, 8, -1
 
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
index df688afbd..664e8ce08 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mie)
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
index 195f290a8..5f4ae446a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
 
 INIT_TESTS
 
@@ -34,7 +34,7 @@ CSR_R_ACCESS mvendorid
 CSR_R_ACCESS marchid 
 CSR_R_ACCESS mimpid 
 CSR_R_ACCESS mhartid 
-CSR_R_ACCESS mconfigptr 
+# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
index fbbc4d18e..9dc0b5c43 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",misa)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S
deleted file mode 100644
index a831df75a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S
+++ /dev/null
@@ -1,755 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.916813//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",ld)
-
-        # This test checks the misaligned load and stores work correctly and across D$ line spills.
-        # The general approach is to
-        # 1. load a region of memory using load doubles equal to two cache lines.  And copy to a new
-        #    region but using stores of bytes, half, word, or doubles.  Each are repeated for all possible
-        #    misaligned access. Bytes are always aligned, halves are 0, and 1, words are 0, 1, 2, and 3, and
-        #    doubles are 0 through 7.  Then the new region is compared against the reference region.  Because
-        #    of the misalignment the last few bytes will not be written so they will be some portion of deadbeef.
-        #    The comparison is done using using same abyte, half, word, and double misaligned approach.
-
-        la a3, signature  # does not get overwritten by any functions
-
-TEST_BYTE:      
-        # byte copy region. always naturally aligned
-        la a0, SourceData
-        la a1, ByteDstData
-        li a2, 16
-        jal ra, memcpy8_1
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, ByteDstData
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-        
-TEST_HALF0:
-        la a0, SourceData
-        la a1, Half0DstData
-        li a2, 16
-        jal ra, memcpy8_2
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Half0DstData
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-
-TEST_HALF1:
-        la a0, SourceData
-        la a1, Half1DstData+1
-        li a2, 16
-        jal ra, memcpy8_2
-        
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Half1DstData+1
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_WORD0:
-        la a0, SourceData
-        la a1, Word0DstData
-        li a2, 16
-        jal ra, memcpy8_4
-
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Word0DstData
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_WORD1:
-        la a0, SourceData
-        la a1, Word1DstData+1
-        li a2, 16
-        jal ra, memcpy8_4
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Word1DstData+1
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_WORD2:
-        la a0, SourceData
-        la a1, Word2DstData+2
-        li a2, 16
-        jal ra, memcpy8_4
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Word2DstData+2
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_WORD3:
-        la a0, SourceData
-        la a1, Word3DstData+3
-        li a2, 16
-        jal ra, memcpy8_4
-
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Word3DstData+3
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE0:
-        la a0, SourceData
-        la a1, Double0DstData
-        li a2, 16
-        jal ra, memcpy8_8
-        
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double0DstData
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE1:
-        la a0, SourceData
-        la a1, Double1DstData+1
-        li a2, 16
-        jal ra, memcpy8_8
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double1DstData+1
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE2:
-        la a0, SourceData
-        la a1, Double2DstData+2
-        li a2, 16
-        jal ra, memcpy8_8
-
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double2DstData+2
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE3:
-        la a0, SourceData
-        la a1, Double3DstData+3
-        li a2, 16
-        jal ra, memcpy8_8
-
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double3DstData+3
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE4:
-        la a0, SourceData
-        la a1, Double4DstData+4
-        li a2, 16
-        jal ra, memcpy8_8
-        
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double4DstData+4
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE5:
-        la a0, SourceData
-        la a1, Double5DstData+5
-        li a2, 16
-        jal ra, memcpy8_8
-        
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double5DstData+5
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE6:
-        la a0, SourceData
-        la a1, Double6DstData+6
-        li a2, 16
-        jal ra, memcpy8_8
-	
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double6DstData+6
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-TEST_DOUBLE7:
-        la a0, SourceData
-        la a1, Double7DstData+7
-        li a2, 16
-        jal ra, memcpy8_8
-
-        # check if the values are write for all sizes and offsets of misaligned loads.
-        la a0, SourceData
-        la a1, Double7DstData+7
-        li a2, 16
-        jal ra, CheckAllWriteSignature
-	
-RVMODEL_HALT
-	
-.type CheckAll, @function
-# a0 is the SourceData, (golden), a1 is the data to be checked.
-# a2 is the number of doubles
-# a3 is the signature pointer
-# returns a0 as 0 for no mismatch, 1 for mismatch,
-# returns a3 as incremented signature pointer
-CheckAllWriteSignature:       
-        mv s0, a0
-        mv s1, a1
-        mv s2, a2
-        mv s3, a3
-        # there is no stack so I'm saving ra into s5
-        mv s5, ra
-
-        # check values byte by byte
-        mv a0, s0  # SourceData
-        mv a1, s1  # ie: ByteDstData
-        slli a2, s2, 3  # * 8
-        jal ra, memcmp1
-        sb a0, 0(s3)
-        mv s4, a0
-
-        # check values half by half
-        mv a0, s0  # SourceData
-        mv a1, s1  # ie: ByteDstData
-        slli a2, s2, 2  # * 4
-        jal ra, memcmp2
-        sb a0, 1(s3)
-        or s4, s4, a0
-
-        # check values half by half
-        addi a0, s0, 1  # SourceData+1
-        addi a1, s1, 1  # ie: ByteDstData+1
-        slli a2, s2, 2  # * 4 -1
-        addi a2, a2, -1
-        jal ra, memcmp2
-        sb a0, 2(s3)
-        or s4, s4, a0
-        
-        # check values word by word
-        addi a0, s0, 0  # SourceData
-        mv a1, s1  # ie: ByteDstData
-        slli a2, s2, 1  # * 2
-        jal ra, memcmp4
-        sb a0, 3(s3)
-        or s4, s4, a0
-
-        # check values word by word
-        addi a0, s0, 1  # SourceData+1
-        addi a1, s1, 1  # ie: ByteDstData+1
-        slli a2, s2, 1  # * 2 -1
-        addi a2, a2, -1
-        jal ra, memcmp4
-        sb a0, 4(s3)
-        or s4, s4, a0
-
-        # check values word by word
-        addi a0, s0, 2  # SourceData+2
-        addi a1, s1, 2  # ie: ByteDstData+2
-        slli a2, s2, 1  # * 2 -1
-        addi a2, a2, -1
-        jal ra, memcmp4
-        sb a0, 5(s3)
-        or s4, s4, a0
-        
-        # check values word by word
-        addi a0, s0, 3  # SourceData+3
-        addi a1, s1, 3  # ie: ByteDstData+3
-        slli a2, s2, 1  # * 2 -1
-        addi a2, a2, -1
-        jal ra, memcmp4
-        sb a0, 6(s3)
-        or s4, s4, a0
-	
-        # check values double by double
-        mv a0, s0  # SourceData
-        mv a1, s1  # ie: ByteDstData
-        slli a2, s2, 0  # * 1
-        jal ra, memcmp8
-        sb a0, 7(s3)
-
-        # check values double by double
-        addi a0, s0, 1  # SourceData+1
-        addi a1, s1, 1  # ie: ByteDstData+1
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 8(s3)
-
-        # check values double by double
-        addi a0, s0, 2  # SourceData+2
-        addi a1, s1, 2  # ie: ByteDstData+2
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 9(s3)
-        
-        # check values double by double
-        addi a0, s0, 3  # SourceData+3
-        addi a1, s1, 3  # ie: ByteDstData+3
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 10(s3)
-	
-        # check values double by double
-        addi a0, s0, 4  # SourceData+4
-        addi a1, s1, 4  # ie: ByteDstData+4
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 11(s3)
-
-        # check values double by double
-        addi a0, s0, 5  # SourceData+5
-        addi a1, s1, 5  # ie: ByteDstData+5
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 12(s3)
-	
-        # check values double by double
-        addi a0, s0, 6  # SourceData+6
-        addi a1, s1, 6  # ie: ByteDstData+6
-        slli a2, s2, 0  # * 1 -1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 13(s3)
-	
-        # check values double by double
-        addi a0, s0, 7  # SourceData+7
-        addi a1, s1, 7  # ie: ByteDstData+7
-        slli a2, s2, 0  # * 1
-        addi a2, a2, -1
-        jal ra, memcmp8
-        sb a0, 14(s3)
-	
-        addi s3, s3, 15
-        mv a3, s3
-        or a0, s4, a0
-        mv ra, s5
-        ret
-
-
-.type memcmp1, @function
-# returns which index mismatch, -1 if none
-memcmp1:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 1 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp1_loop:
-        lbu t3, 0(t0)
-        lbu t4, 0(t1)
-        bne t3, t4, memcmp1_ne
-        addi t0, t0, 1
-        addi t1, t1, 1
-        addi t2, t2, 1
-        blt t2, a2, memcmp1_loop
-        li a0, -1
-        ret
-memcmp1_ne:
-        mv a0, t2
-        ret
-	
-.type memcmp2, @function
-# returns which index mismatch, -1 if none
-memcmp2:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 2 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp2_loop:
-        lhu t3, 0(t0)
-        lhu t4, 0(t1)
-        bne t3, t4, memcmp2_ne
-        addi t0, t0, 2
-        addi t1, t1, 2
-        addi t2, t2, 1
-        blt t2, a2, memcmp2_loop
-        li a0, -1
-        ret
-memcmp2_ne:
-        mv a0, t2
-        ret
-	
-.type memcmp4, @function
-# returns which index mismatch, -1 if none
-memcmp4:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 4 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp4_loop:
-        lwu t3, 0(t0)
-        lwu t4, 0(t1)
-        bne t3, t4, memcmp4_ne
-        addi t0, t0, 4
-        addi t1, t1, 4
-        addi t2, t2, 1
-        blt t2, a2, memcmp4_loop
-        li a0, -1
-        ret
-memcmp4_ne:
-        mv a0, t2
-        ret
-	
-.type memcmp8, @function
-# returns which index mismatch, -1 if none
-memcmp8:        
-        # a0 is the source1
-        # a1 is the source2
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcmp8_loop:
-        ld t3, 0(t0)
-        ld t4, 0(t1)
-        bne t3, t4, memcmp8_ne
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcmp8_loop
-        li a0, -1
-        ret
-memcmp8_ne:
-        mv a0, t2
-        ret
-        
-	
-RVTEST_CODE_END
-
-.type memcpy8_1, @function
-# load 8 bytes using load double then store using 8 sb
-memcpy8_1:        
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-memcpy8_1_loop:   
-        ld t3, 0(t0)
-        andi t4, t3, 0xff
-        sb t4, 0(t1)
-        srli t4, t3, 8
-        andi t4, t4, 0xff
-        sb t4, 1(t1)
-	
-        srli t4, t3, 16
-        andi t4, t4, 0xff
-        sb t4, 2(t1)
-
-        srli t4, t3, 24
-        andi t4, t4, 0xff
-        sb t4, 3(t1)
-        
-        srli t4, t3, 32
-        andi t4, t4, 0xff
-        sb t4, 4(t1)
-	
-        srli t4, t3, 40
-        andi t4, t4, 0xff
-        sb t4, 5(t1)
-	
-        srli t4, t3, 48
-        andi t4, t4, 0xff
-        sb t4, 6(t1)
-	
-        srli t4, t3, 56
-        andi t4, t4, 0xff
-        sb t4, 7(t1)
-	
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_1_loop
-        ret
-	
-.type memcpy8_2, @function
-# load 8 bytes using load double then store using 4 sh
-memcpy8_2:
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-
-        # 16 bit mask
-        lui t4, 0xf
-        li t3, 0xfff
-        or t5, t4, t3
-
-memcpy8_2_loop:   
-        ld t3, 0(t0)
-        and t4, t3, t5
-        sh t4, 0(t1)
-
-        srli t4, t3, 16
-        and t4, t4, t5
-        sh t4, 2(t1)
-	
-        srli t4, t3, 32
-        and t4, t4, t5
-        sh t4, 4(t1)
-
-        srli t4, t3, 48
-        and t4, t4, t5
-        sh t4, 6(t1)
-        
-	
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_2_loop
-        ret
-
-.type memcpy8_4, @function
-# load 8 bytes using load double then store using 2 sw
-memcpy8_4:
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-
-        # 32 bit mask
-        addi t4, x0, -1
-        srli t5, t4, 32
-
-memcpy8_4_loop:   
-        ld t3, 0(t0)
-        and t4, t3, t5
-        sw t4, 0(t1)
-
-        srli t4, t3, 32
-        and t4, t4, t5
-        sw t4, 4(t1)
-	
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_4_loop
-        ret
-
-.type memcpy8_8, @function
-# load 8 bytes using load double then store using 1 sd
-memcpy8_8:
-        # a0 is the source
-        # a1 is the dst
-        # a2 is the number of 8 byte words
-        mv t0, a0
-        mv t1, a1
-        li t2, 0
-
-memcpy8_8_loop:   
-        ld t3, 0(t0)
-        sd t3, 0(t1)
-	
-        addi t0, t0, 8
-        addi t1, t1, 8
-        addi t2, t2, 1
-        blt t2, a2, memcpy8_8_loop
-        ret
-        
-
-RVTEST_DATA_BEGIN
-.align 3
-rvtest_data:
-SourceData:     
-.8byte 0x0706050403020100, 0x0f0e0d0c0b0a0908, 0x1716151413021110, 0x1f1e1d1c1b1a1918
-.8byte 0x2726252423222120, 0x2f2e2d2c2b2a2928, 0x3736353433023130, 0x3f3e3d3c3b3a3938
-.8byte 0x4746454443424140, 0x4f4e4d4c4b4a4948, 0x5756555453025150, 0x5f5e5d5c5b5a5958
-.8byte 0x6766656463626160, 0x6f6e6d6c6b6a6968, 0x7776757473027170, 0x7f7e7d7c7b7a7978
-.8byte 0xdeadbeefdeadbeef
-
-Response1ByteOffsetData:     
-.8byte 0x0807060504030201, 0x100f0e0d0c0b0a09, 0x1817161514130211, 0x201f1e1d1c1b1a19
-.8byte 0x2827262524232221, 0x302f2e2d2c2b2a29, 0x3837363534330231, 0x403f3e3d3c3b3a39
-.8byte 0x4847464544434241, 0x504f4e4d4c4b4a49, 0x5857565554530251, 0x605f5e5d5c5b5a59
-.8byte 0x6867666564636261, 0x706f6e6d6c6b6a69, 0x7877767574730271, 0xde7f7e7d7c7b7a79
-
-Response2ByteOffsetData:     
-.8byte 0x0908070605040302, 0x11100f0e0d0c0b0a, 0x1918171615141302, 0x21201f1e1d1c1b1a
-.8byte 0x2928272625242322, 0x31302f2e2d2c2b2a, 0x3938373635343302, 0x41403f3e3d3c3b3a
-.8byte 0x4948474645444342, 0x51504f4e4d4c4b4a, 0x5958575655545302, 0x61605f5e5d5c5b5a
-.8byte 0x6968676665646362, 0x71706f6e6d6c6b6a, 0x7978777675747302, 0xdead7f7e7d7c7b7a
-
-Response3ByteOffsetData:     
-.8byte 0x0a09080706050403, 0x0211100f0e0d0c0b, 0x1a19181716151413, 0x2221201f1e1d1c1b
-.8byte 0x2a29282726252423, 0x0231302f2e2d2c2b, 0x3a39383736353433, 0x4241403f3e3d3c3b
-.8byte 0x4a49484746454443, 0x0251504f4e4d4c4b, 0x5a59585756555453, 0x6261605f5e5d5c5b
-.8byte 0x6a69686766656463, 0x0271706f6e6d6c6b, 0x7a79787776757473, 0xdeadbe7f7e7d7c7b
-
-Response4ByteOffsetData:     
-.8byte 0x0b0a090807060504, 0x130211100f0e0d0c, 0x1b1a191817161514, 0x232221201f1e1d1c
-.8byte 0x2b2a292827262524, 0x330231302f2e2d2c, 0x3b3a393837363534, 0x434241403f3e3d3c
-.8byte 0x4b4a494847464544, 0x530251504f4e4d4c, 0x5b5a595857565554, 0x636261605f5e5d5c
-.8byte 0x6b6a696867666564, 0x730271706f6e6d6c, 0x7b7a797877767574, 0xdeadbeef7f7e7d7c
-        
-Response5ByteOffsetData:     
-.8byte 0x0c0b0a0908070605, 0x14130211100f0e0d, 0x1c1b1a1918171615, 0x24232221201f1e1d
-.8byte 0x2c2b2a2928272625, 0x34330231302f2e2d, 0x3c3b3a3938373635, 0x44434241403f3e3d
-.8byte 0x4c4b4a4948474645, 0x54530251504f4e4d, 0x5c5b5a5958575655, 0x64636261605f5e5d
-.8byte 0x6c6b6a6968676665, 0x74730271706f6e6d, 0x7c7b7a7978777675, 0xdeadbeefde7f7e7d
-
-Response6ByteOffsetData:     
-.8byte 0x0d0c0b0a09080706, 0x1514130211100f0e, 0x1d1c1b1a19181716, 0x2524232221201f1e
-.8byte 0x2d2c2b2a29282726, 0x3534330231302f2e, 0x3d3c3b3a39383736, 0x4544434241403f3e
-.8byte 0x4d4c4b4a49484746, 0x5554530251504f4e, 0x5d5c5b5a59585756, 0x6564636261605f5e
-.8byte 0x6d6c6b6a69686766, 0x7574730271706f6e, 0x7d7c7b7a79787776, 0xdeadbeefdead7f7e
-
-Response7ByteOffsetData:     
-.8byte 0x0e0d0c0b0a090807, 0x161514130211100f, 0x1e1d1c1b1a191817, 0x262524232221201f
-.8byte 0x2e2d2c2b2a292827, 0x363534330231302f, 0x3e3d3c3b3a393837, 0x464544434241403f
-.8byte 0x4e4d4c4b4a494847, 0x565554530251504f, 0x5e5d5c5b5a595857, 0x666564636261605f
-.8byte 0x6e6d6c6b6a696867, 0x767574730271706f, 0x7e7d7c7b7a797877, 0xdeadbeefdeadbe7f
-        
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-ByteDstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-
-Half0DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-	
-Half1DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef
-Word0DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-
-Word1DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef
-Word2DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Word3DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double0DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-
-Double1DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double2DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double3DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double4DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double5DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double6DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef	
-Double7DstData:    
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef
-.8byte 0xdeadbeefdeadbeef
-signature:
-        .fill 225, 1, 0x00
-	
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
index 0690b1282..2a54d4868 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 //
-// WALLY-MMU-SV39
+// WALLY-MMU
 //
 // Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
 //
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mmu-sv39)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",mmu-sv39)
 
 INIT_TESTS
 
@@ -52,9 +52,9 @@ test_cases:
 # 
 # ---------------------------------------------------------------------------------------------
 
-# =========== test 11.3.1.1 Page Table Translation ===========
+# =========== test 12.3.1.1 Page Table Translation ===========
 
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
+# test 12.3.1.1.1 write page tables / entries to phyiscal memory
 # sv39 page table (See Figure 12.12***):
 # Level 2 page table, situated at 0x8000D000
 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A
@@ -82,28 +82,27 @@ test_cases:
 .8byte 0x0000000080018020, 0x0000000020080C57, write64_test# Vaddr 0x4000 Paddr 0x80203000: D=0, should cause write fault
 .8byte 0x0000000080018028, 0x00000000200814C7, write64_test# Vaddr 0x5000 Paddr 0x80205000: X=0, fetches should fault
 .8byte 0x0000000080018030, 0x00000000200814C0, write64_test# Vaddr 0x6000: invalid page
-.8byte 0x0000000080018038, 0x01000000200800DF, write64_test# Vaddr 0x7000, Paddr = 0x80200000, bad reserved bit
 # Level 0 page table B
 .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
 
 # second page table to check context switches with satp
-.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
-.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
+.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
+.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
 
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
+# test 12.3.1.1.2 write values to Paddrs in each page
+# each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments.
 # when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there.
-.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 11.3.1.1.4 and 11.3.1.4.1
-.8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test# 11.3.1.1.4
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test# 11.3.1.3.2
-.8byte 0x80203130, 0x0110DEADBEEF0077, write64_test# 11.3.1.3.2
-.8byte 0x80099000, 0x0000806711100393, write64_test# 11.3.1.3.1 and 11.3.1.3.2 write executable code for "li x7, 0x111; ret"
-.8byte 0x80205AA0, 0x0000806711100393, write64_test# 11.3.1.3.5 write same executable code
-.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test# 11.3.1.1.4
-.8byte 0x84212348, 0x0330DEADBEEF0440, write64_test# 11.3.1.3.3
-.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test# 11.3.1.3.7
+.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 12.3.1.1.4 and 12.3.1.4.1
+.8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test# 12.3.1.1.4
+.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test# 12.3.1.3.2
+.8byte 0x80203130, 0x0110DEADBEEF0077, write64_test# 12.3.1.3.2
+.8byte 0x80099000, 0x0000806711100393, write64_test# 12.3.1.3.1 and 12.3.1.3.2 write executable code for "li x7, 0x111; ret"
+.8byte 0x80205AA0, 0x0000806711100393, write64_test# 12.3.1.3.5 write same executable code
+.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test# 12.3.1.1.4
+.8byte 0x84212348, 0x0330DEADBEEF0440, write64_test# 12.3.1.3.3
+.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test# 12.3.1.3.7
 
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
+# test 12.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
 .8byte 0x0, 0x0, goto_baremetal# satp.MODE = baremetal / no translation.
 .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
 .8byte 0x80200AB0, 0x0000DEADBEEF0000, read64_test
@@ -114,42 +113,42 @@ test_cases:
 .8byte 0x84212348, 0x0330DEADBEEF0440, read64_test
 .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, read64_test
 
-# test 11.3.1.1.4 check translation works in sv39, read the same values from previous tests, this time with Vaddrs
+# test 12.3.1.1.4 check translation works in sv39, read the same values from previous tests, this time with Vaddrs
 .8byte 0x8000D, 0x0, goto_sv39 # satp.MODE = sv39, with base page table PPN = 0x8000D and ASID = 0. current VPN: gigapage at 0x80000000.
 .8byte 0x80200AB0, 0x0000DEADBEEF0000, read64_test         # gigapage at Vaddr 0x80000000, Paddr 0x80000000
 .8byte 0x400FFAB8, 0x0880DEADBEEF0055, read64_test         # megapage at Vaddr 0x40400000, Paddr 0x80000000
 .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test # kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000
 
-# =========== test 11.3.1.2 page fault tests ===========
+# =========== test 12.3.1.2 page fault tests ===========
 
-# test 11.3.1.2.1 load page fault if upper bits of Vaddr are not the same
+# test 12.3.1.2.1 load page fault if upper bits of Vaddr are not the same
 .8byte 0x0010000080000AB0, 0x0, read64_test# gigapage at Vaddr 0x80000000, Paddr 0x80000000, bad 1 in upper bits
 .8byte 0xFF0FFFFFFFFFF888, 0x0, read64_test# kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000, bad 0000 in upper bits
 
-# test 11.3.1.2.2 load page fault when reading an address where the valid flag is zero
+# test 12.3.1.2.2 load page fault when reading an address where the valid flag is zero
 .8byte 0x6000, 0x0, read64_test
 
-# test 11.3.1.2.3 store page fault if PTE has W and ~R flags set
+# test 12.3.1.2.3 store page fault if PTE has W and ~R flags set
 .8byte 0x2000, 0x0, write64_test
 
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
+# test 12.3.1.2.4 Fault if last level PTE is a pointer
 .8byte 0x0020, 0x0, read64_test
 
-# test 11.3.1.2.5 load page fault on misaligned pages
+# test 12.3.1.2.5 load page fault on misaligned pages
 .8byte 0xC0000000, 0x0, read64_test# misaligned gigapage
 .8byte 0x40200000, 0x0, read64_test# misaligned megapage
 
-# =========== test 11.3.1.3 PTE Protection flags ===========
+# =========== test 12.3.1.3 PTE Protection flags ===========
 
 
-# test 11.3.1.3.1 User flag == 0
-# *** reads on pages with U=0 already tested in 11.3.1.1.4
+# test 12.3.1.3.1 User flag == 0
+# *** reads on pages with U=0 already tested in 12.3.1.1.4
 .8byte 0x40099000, 0x111, executable_test                       # execute success when U=0, priv=S
 .8byte 0x40400000, 0x2, goto_u_mode                         # go to U mode, return to megapage at 0x40400000 where U = 1. 0x9 written to output
 .8byte 0xFFFFFFFFFFFFFC80, 0x0880DEADBEEF0550, read64_test # load page fault when U=0, priv=U
 .8byte 0x40099000, 0xbad, executable_test                       # execute fault when U=0, priv=U
 
-# test 11.3.1.3.2 User flag == 1
+# test 12.3.1.3.2 User flag == 1
 .8byte 0x1AC0, 0x0990DEADBEEF0033, read64_test # read success when U=1, priv=U
 .8byte 0x80000000, 0x1, goto_s_mode                   # go back to S mode, return to gigapage at 0x80000000 where U = 0. 0x8 written to output
 .8byte 0x0, 0x3, write_mxr_sum                    # set sstatus.[MXR, SUM] = 11
@@ -158,64 +157,58 @@ test_cases:
 .8byte 0x0, 0x2, write_mxr_sum                    # set sstatus.[MXR, SUM] = 10.
 .8byte 0x1AC0, 0x0990DEADBEEF0033, read64_test # load page fault when U-1, priv=S, sstatus.SUM=0
 
-# test 11.3.1.3.3 Read flag
-# *** reads on pages with R=1 already tested in 11.3.1.1.4
+# test 12.3.1.3.3 Read flag
+# *** reads on pages with R=1 already tested in 12.3.1.1.4
 .8byte 0x0, 0x1, write_mxr_sum                        # set sstatus.[MXR, SUM] = 01.
 .8byte 0x40612348, 0x0330DEADBEEF0440, read64_test # load page fault when R=0, sstatus.MXR=0
 .8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11.
 .8byte 0x40612348, 0x0330DEADBEEF0440, read64_test # read success when MXR=1, X=1
 
-# test 11.3.1.3.4 Write flag
+# test 12.3.1.3.4 Write flag
 .8byte 0x80AAAAA0, 0x0440DEADBEEF0110, write64_test# write success when W=1
 .8byte 0x80AAAAA0, 0x0440DEADBEEF0110, read64_test# check write success by reading the same address
 .8byte 0x40000000, 0x0220DEADBEEF0BB0, write64_test# store page fault when W=0
 
-# test 11.3.1.3.5 eXecute flag
-# *** fetches on pages with X = 1 already tested in 11.3.1.3.1
+# test 12.3.1.3.5 eXecute flag
+# *** fetches on pages with X = 1 already tested in 12.3.1.3.1
 .8byte 0x5AA0, 0x1, executable_test                 # instr page fault when X=0
 
-# In the following two tests, SVADU is not supported, so the software handles the A/D bits
-# Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits
-
-# test 11.3.1.3.6 Accessed flag == 0
+# test 12.3.1.3.6 Accessed flag == 0
 .8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0
 .8byte 0x3AB8, 0x0990DEADBEEF0990, read64_test# load page fault when A=0
 
-# test 11.3.1.3.7 Dirty flag == 0
+# test 12.3.1.3.7 Dirty flag == 0
 .8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0
 .8byte 0x4AA0, 0x0440DEADBEEF0BB0, read64_test# read success when D=0
 
-# test 11.3.1.3.8 Reserved bits nonzero
-.8byte 0x7AA0, 0x123456789ABCDEF, read64_test # load page fault because reserved is nonzero
+# =========== test 12.3.1.4 SATP Register ===========
 
-# =========== test 11.3.1.4 SATP Register ===========
-
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
+# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
 // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
-.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
+.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
 .8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping 
 
-# test 11.3.1.4.2 Test Global mapping
+# test 12.3.1.4.2 Test Global mapping
 // ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping.
 
 
-# =========== test 11.3.1.5 STATUS Registers ===========
+# =========== test 12.3.1.5 STATUS Registers ===========
 
-# test 11.3.1.5.1 mstatus.mprv translation
+# test 12.3.1.5.1 mstatus.mprv translation
 # *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
 .8byte 0x8000D, 0x0, goto_sv39 // go back to old, extensive page table
 .8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
 .8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
 .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
 
-# test 11.3.1.5.2 mstatus.mprv clearing
+# test 12.3.1.5.2 mstatus.mprv clearing
 # mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
 .8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
 .8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
 .8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
 
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
+# test 12.3.1.5.3 sstatus.mxr read
+# this bitfield already tested in 12.3.1.3.3
 
 # terminate tests
 .8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
deleted file mode 100644
index c086c934f..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
+++ /dev/null
@@ -1,279 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-MMU-SV39-SVADU
-//
-// Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
-//
-// Created 2021-06-15
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mmu-sv39)
-
-INIT_TESTS
-
-TRAP_HANDLER m
-
-j run_test_loop // begin test loop/table tests instead of executing inline code.
-
-INIT_TEST_TABLE
-
-TEST_STACK_AND_DATA
-
-.align 3
-test_cases:
-
-# ---------------------------------------------------------------------------------------------
-# Test Contents
-#
-#   Here is where the actual tests are held, or rather, what the actual tests do.
-#   each entry consists of 3 values that will be read in as follows:
-#   
-#   '.8byte [x28 Value], [x29 Value], [x30 value]'
-#                     or
-#   '.8byte [address], [value], [test type]'
-#
-#   The encoding for x30 test type values can be found in the test handler
-# 
-# ---------------------------------------------------------------------------------------------
-
-# =========== test 11.3.1.1 Page Table Translation ===========
-
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
-# sv39 page table (See Figure 12.12***):
-# Level 2 page table, situated at 0x8000D000
-.8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A
-.8byte 0x000000008000D008, 0x0000000020005001, write64_test# points to level 1 page table B #*** replacing all the pointers DAU bits with 0.
-.8byte 0x000000008000D010, 0x00000000200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory)
-.8byte 0x000000008000D018, 0x00004000004000C7, write64_test# Vaddr 0xC000_0000: misaligned gigapage
-.8byte 0x000000008000DFF8, 0x0000000020005401, write64_test # points to level 1 page table C
-
-# Level 1 page table A
-.8byte 0x0000000080013000, 0x0000000020006001, write64_test# points to level 0 page table A
-
-# Level 1 page table B
-.8byte 0x0000000080014000, 0x00000000200000CB, write64_test# Vaddr 0x4000_0000, Paddr 0x80000000: aligned megapage, W=0, used for execution tests
-.8byte 0x0000000080014008, 0x00000400000080C3, write64_test# Vaddr 0x4020_0000: misaligned megapage
-.8byte 0x0000000080014010, 0x00000000200000DF, write64_test# Vaddr 0x4040_0000, Paddr 0x80000000: aligned megapage, aliased with program, U=1
-.8byte 0x0000000080014018, 0x00000000210800C9, write64_test# Vaddr 0x4060_0000, Paddr 0x84200000: R=0, reads should fault
-# Level 1 page table C
-.8byte 0x0000000080015FF8, 0x0000000020005801, write64_test# points to level 0 page table B
-
-# Level 0 page table A
-.8byte 0x0000000080018000, 0x00000000200070D1, write64_test# Vaddr 0x0000: bad PTE points to level -1 table
-.8byte 0x0000000080018008, 0x00000000200800DF, write64_test# Vaddr 0x1000, Paddr = 0x80200000: aligned kilopage
-.8byte 0x0000000080018010, 0x00000000200810D5, write64_test# Vaddr 0x2000: bad PTE has W but not R
-.8byte 0x0000000080018018, 0x0000000020080817, write64_test# Vaddr 0x3000 Paddr 0x80202000: A=0, should cause read fault
-.8byte 0x0000000080018020, 0x0000000020080C57, write64_test# Vaddr 0x4000 Paddr 0x80203000: D=0, should cause write fault
-.8byte 0x0000000080018028, 0x00000000200814C7, write64_test# Vaddr 0x5000 Paddr 0x80205000: X=0, fetches should fault
-.8byte 0x0000000080018030, 0x00000000200814C0, write64_test# Vaddr 0x6000: invalid page
-.8byte 0x0000000080018038, 0x01000000200800DF, write64_test# Vaddr 0x7000, Paddr = 0x80200000, bad reserved bit
-.8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1
-.8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2
-.8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3
-.8byte 0x0000000080018080, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x0000000080018088, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x0000000080018090, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x0000000080018098, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180A0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180A8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180B0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180B8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180C0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180C8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180D0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180D8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180E0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180E8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180F0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x00000000800180F8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
-.8byte 0x0000000080018150, 0x80000000200800DF, write64_test# Vaddr 0x20000, Paddr = 0x80200000, NAPOT malformed with ppn[3] =0
-
-# Level 0 page table B
-.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
-
-# second page table to check context switches with satp
-.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
-.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
-
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
-# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there.
-.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test # 11.3.1.1.4 and 11.3.1.4.1
-.8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test # 11.3.1.1.4
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
-.8byte 0x80203130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
-.8byte 0x80099000, 0x0000806711100393, write64_test # 11.3.1.3.1 and 11.3.1.3.2 write executable code for "li x7, 0x111; ret"
-.8byte 0x80205AA0, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
-.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test # 11.3.1.1.4
-.8byte 0x84212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
-.8byte 0x8020A400, 0x0550DEADBEEF0660, write64_test # 11.3.1.3.9 
-.8byte 0x80205000, 0x0770DEADBEEF0880, write64_test # 11.3.1.2.2 junk in memory location corresponding to invalid page
-	
-#.8byte 0x800ffab8, 0x0880deadbeef0990, write64_test # 11.3.1.1.4 
-.8byte 0x80203aa0, 0x0880deadbeef0991, write64_test # 11.3.1.3.7(a)
-#.8byte 0x80205000, 0x0770DEADBEEF0880, write64_test # 11.3.1.2.2 junk in memory location corresponding to invalid page
-
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
-.8byte 0x0, 0x0, goto_baremetal# satp.MODE = baremetal / no translation.
-.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-.8byte 0x80200AB0, 0x0000DEADBEEF0000, read64_test
-.8byte 0x800FFAB8, 0x0880DEADBEEF0055, read64_test
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, read64_test
-.8byte 0x80203130, 0x0110DEADBEEF0077, read64_test
-.8byte 0x80201888, 0x0220DEADBEEF0099, read64_test
-.8byte 0x84212348, 0x0330DEADBEEF0440, read64_test
-
-# test 11.3.1.1.4 check translation works in sv39, read the same values from previous tests, this time with Vaddrs
-.8byte 0x8000D, 0x0, goto_sv39 # satp.MODE = sv39, with base page table PPN = 0x8000D and ASID = 0. current VPN: gigapage at 0x80000000.
-.8byte 0x80200AB0, 0x0000DEADBEEF0000, read64_test         # gigapage at Vaddr 0x80000000, Paddr 0x80000000
-.8byte 0x400FFAB8, 0x0880DEADBEEF0055, read64_test         # megapage at Vaddr 0x40400000, Paddr 0x80000000
-.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test # kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000
-
-# =========== test 11.3.1.2 page fault tests ===========
-
-# test 11.3.1.2.1 load page fault if upper bits of Vaddr are not the same
-.8byte 0x0010000080000AB0, 0x0, read64_test# gigapage at Vaddr 0x80000000, Paddr 0x80000000, bad 1 in upper bits
-.8byte 0xFF0FFFFFFFFFF888, 0x0, read64_test# kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000, bad 0000 in upper bits
-
-# test 11.3.1.2.2 load page fault when reading an address where the valid flag is zero
-.8byte 0x6000, 0x0, read64_test
-
-# test 11.3.1.2.3 store page fault if PTE has W and ~R flags set
-.8byte 0x2000, 0x0, write64_test
-
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
-.8byte 0x0020, 0x0, read64_test
-
-# test 11.3.1.2.5 load page fault on misaligned pages
-.8byte 0xC0000000, 0x0, read64_test# misaligned gigapage
-.8byte 0x40200000, 0x0, read64_test# misaligned megapage
-
-# =========== test 11.3.1.3 PTE Protection flags ===========
-
-
-# test 11.3.1.3.1 User flag == 0
-# *** reads on pages with U=0 already tested in 11.3.1.1.4
-.8byte 0x40099000, 0x111, executable_test                       # execute success when U=0, priv=S
-.8byte 0x40400000, 0x2, goto_u_mode                         # go to U mode, return to megapage at 0x40400000 where U = 1. 0x9 written to output
-.8byte 0xFFFFFFFFFFFFFC80, 0x0880DEADBEEF0550, read64_test # load page fault when U=0, priv=U
-.8byte 0x40099000, 0xbad, executable_test                       # execute fault when U=0, priv=U
-
-# test 11.3.1.3.2 User flag == 1
-.8byte 0x1AC0, 0x0990DEADBEEF0033, read64_test # read success when U=1, priv=U
-.8byte 0x80000000, 0x1, goto_s_mode                   # go back to S mode, return to gigapage at 0x80000000 where U = 0. 0x8 written to output
-.8byte 0x0, 0x3, write_mxr_sum                    # set sstatus.[MXR, SUM] = 11
-.8byte 0x4130, 0x0110DEADBEEF0077, read64_test # read success when U=1, priv=S, sstatus.SUM=1
-.8byte 0x40499000, 0xbad, executable_test           # instr page fault when U=1, priv=S (with any sstatus.SUM)
-.8byte 0x0, 0x2, write_mxr_sum                    # set sstatus.[MXR, SUM] = 10.
-.8byte 0x1AC0, 0x0990DEADBEEF0033, read64_test # load page fault when U-1, priv=S, sstatus.SUM=0
-
-# test 11.3.1.3.3 Read flag
-# *** reads on pages with R=1 already tested in 11.3.1.1.4
-.8byte 0x0, 0x1, write_mxr_sum                        # set sstatus.[MXR, SUM] = 01.
-.8byte 0x40612348, 0x0330DEADBEEF0440, read64_test # load page fault when R=0, sstatus.MXR=0
-.8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11.
-.8byte 0x40612348, 0x0330DEADBEEF0440, read64_test # read success when MXR=1, X=1
-
-# test 11.3.1.3.4 Write flag
-.8byte 0x80AAAAA0, 0x0440DEADBEEF0110, write64_test# write success when W=1
-.8byte 0x80AAAAA0, 0x0440DEADBEEF0110, read64_test# check write success by reading the same address
-.8byte 0x40000000, 0x0220DEADBEEF0BB0, write64_test# store page fault when W=0
-
-# test 11.3.1.3.5 eXecute flag
-# *** fetches on pages with X = 1 already tested in 11.3.1.3.1
-.8byte 0x5AA0, 0x1, executable_test                 # instr page fault when X=0
-
-
-# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
-# Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
-
-# test 11.3.1.3.6(a) Accessed flag == 0
-.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test# store page fault when A=0
-.8byte 0x3AB8, 0x0990DEADBEEF0990, read64_test# load page fault when A=0
-
-# test 11.3.1.3.7(a) Dirty flag == 0
-.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test# store page fault when D=0
-.8byte 0x4AA0, 0xDEADBEEFDEADBEEF, read64_test# read success when D=0
-
-# Now set ADUE bit
-.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
-.8byte 0x0, 0x2000000000000000, write_menvcfg  # set menvcfg.HADE = 1
-.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-
-# Since SVADU is 1, there are no faults when A/D=0
-# test 11.3.1.3.6(b) Accessed flag == 0
-.8byte 0x36D0, 0x0990DEADBEEF0770, write64_test # Write success when A=0 and SVADU is enabled
-.8byte 0x36D0, 0x0990DEADBEEF0770, read64_test # Read success when A=0 and SVADU is enabled
-
-# test 11.3.1.3.7(b) Dirty flag == 0
-.8byte 0x4658, 0x0440DEADBEEF0AA0, write64_test # Write success when D=0 and SVADU is enabled
-.8byte 0x4658, 0x0440DEADBEEF0AA0, read64_test # read success when D=0
-
-# test 11.3.1.3.8 Reserved bits nonzero
-.8byte 0x7AA0, 0x123456789ABCDEF, read64_test # load page fault because reserved is nonzero
-
-# test 11.3.1.3.9 NAPOT read
-.8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page
-
-# test 11.3.1.3.9 NAPOT read
-.8byte 0x2A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page with malformed PTE should page fault
-
-# test 11.3.1.3.10 PBMT checks
-.8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0
-.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
-.8byte 0x0, 0x4000000000000000, write_menvcfg  # set menvcfg.PBMTE = 1
-.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-.8byte 0x8040, 0x1212343456567878, write64_test # Write success with PBMT = 1
-.8byte 0x8040, 0x1212343456567878, read64_test # Read back success with PBMT = 1
-.8byte 0x9050, 0x2312343456567878, write64_test # Write success with PBMT = 2
-.8byte 0x9050, 0x2312343456567878, read64_test # Read back success with PBMT = 2
-.8byte 0xA060, 0x3412343456567878, write64_test # Write faults with PBMT = 3
-
-# =========== test 11.3.1.4 SATP Register ===========
-
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
-// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
-.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
-.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping 
-
-# test 11.3.1.4.2 Test Global mapping
-// ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping.
-
-
-# =========== test 11.3.1.5 STATUS Registers ===========
-
-# test 11.3.1.5.1 mstatus.mprv translation
-# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
-.8byte 0x8000D, 0x0, goto_sv39 // go back to old, extensive page table
-.8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
-.8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
-.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
-
-# test 11.3.1.5.2 mstatus.mprv clearing
-# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
-.8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
-.8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
-.8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
-
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
-
-# terminate tests
-.8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
index f84e68109..fafaa242a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
@@ -1,6 +1,6 @@
 ///////////////////////////////////////////
 //
-// WALLY-MMU-SV48
+// WALLY-MMU
 //
 // Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
 //
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sv48)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sv48)
 
 INIT_TESTS
 
@@ -54,9 +54,9 @@ test_cases:
 # ---------------------------------------------------------------------------------------------
 
 
-# =========== test 11.3.1.1 Page Table Translation ===========
+# =========== test 12.3.1.1 Page Table Translation ===========
 
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
+# test 12.3.1.1.1 write page tables / entries to phyiscal memory
 # sv48 page table (See Figure 12.12***):
 # Level 3 page table, situated at 0x8000D000
 .8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A
@@ -101,22 +101,22 @@ test_cases:
 .8byte 0x8002F010, 0x200000CF, write64_test # Vaddr 0x80000000, Paddr 0x80000000: aligned gigapage (data and instr memory)
 
 
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
+# test 12.3.1.1.2 write values to Paddrs in each page
+# each of these values is used for 12.3.1.1.3 and some other tests, specified in the comments.
 # when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
-.8byte 0x82777778, 0x0EE0DEADBEEF0CC0, write64_test # 11.3.1.1.4 terapage
-.8byte 0x85BC0AB0, 0x0000DEADBEEF0000, write64_test # 11.3.1.1.4 gigapage
-.8byte 0x800F0AB8, 0x0880DEADBEEF0055, write64_test # 11.3.1.1.4 megapage
-.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test # 11.3.1.1.4 kilopage
-.8byte 0x80099000, 0x0000806711100393, write64_test # 11.3.1.3.1 write executable code for "li x7, 0x111; ret"
-.8byte 0x80200400, 0x0000806711100393, write64_test # 11.3.1.3.2 write same executable code 
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 
-.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
-.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
-.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
-.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7
+.8byte 0x82777778, 0x0EE0DEADBEEF0CC0, write64_test # 12.3.1.1.4 terapage
+.8byte 0x85BC0AB0, 0x0000DEADBEEF0000, write64_test # 12.3.1.1.4 gigapage
+.8byte 0x800F0AB8, 0x0880DEADBEEF0055, write64_test # 12.3.1.1.4 megapage
+.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test # 12.3.1.1.4 kilopage
+.8byte 0x80099000, 0x0000806711100393, write64_test # 12.3.1.3.1 write executable code for "li x7, 0x111; ret"
+.8byte 0x80200400, 0x0000806711100393, write64_test # 12.3.1.3.2 write same executable code 
+.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 12.3.1.3.2 
+.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 12.3.1.3.2
+.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 12.3.1.3.3
+.8byte 0x88888000, 0x0000806711100393, write64_test # 12.3.1.3.5 write same executable code
+.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 12.3.1.3.7
 
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
+# test 12.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
 .8byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation.
 .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
 .8byte 0x82777778, 0x0EE0DEADBEEF0CC0, read64_test
@@ -128,43 +128,43 @@ test_cases:
 .8byte 0x85212348, 0x0330DEADBEEF0440, read64_test
 .8byte 0x80203AA0, 0x0440DEADBEEF0BB0, read64_test
 
-# test 11.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
+# test 12.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
 .8byte 0x8000D, 0x0, goto_sv48 # satp.MODE = sv48, with base page table PPN = 0x8000D and ASID = 0. current VPN: megapage at 0x80000000. Nothing written to output
 .8byte 0x10082777778, 0x0EE0DEADBEEF0CC0, read64_test      # terapage at Vaddr 0x010000000000, Paddr 0x0
 .8byte 0x8005BC0AB0, 0x0000DEADBEEF0000, read64_test       # gigapage at Vaddr 0x008000000000, Paddr 0x80000000
 .8byte 0x800F0AB8, 0x0880DEADBEEF0055, read64_test         # megapage at Vaddr 0x80000000, Paddr 0x80000000
 .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test # kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000
 
-# =========== test 11.3.1.2 page fault tests ===========
+# =========== test 12.3.1.2 page fault tests ===========
 
-# test 11.3.1.2.1 page fault if upper bits of Vaddr are not the same
+# test 12.3.1.2.1 page fault if upper bits of Vaddr are not the same
 .8byte 0x001000800ABC0AB0, 0x0, read64_test# gigapage at Vaddr 0x008000000000, Paddr 0x80000000, bad 1 in upper bits
 .8byte 0xFF0FFFFFFFFFF888, 0x0, read64_test# kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000, bad 0000 in upper bits
 
-# test 11.3.1.2.2 read fault when reading an address where the valid flag is zero
+# test 12.3.1.2.2 read fault when reading an address where the valid flag is zero
 .8byte 0x80205000, 0x0, read64_test
 
-# test 11.3.1.2.3 write fault if PTE has W and ~R flags set
+# test 12.3.1.2.3 write fault if PTE has W and ~R flags set
 .8byte 0x80202000, 0x0, write64_test 
 
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
+# test 12.3.1.2.4 Fault if last level PTE is a pointer
 .8byte 0x80200000, 0x0, read64_test
 
-# test 11.3.1.2.5 read fault on misaligned pages
+# test 12.3.1.2.5 read fault on misaligned pages
 .8byte 0x18000000000, 0x0, read64_test # misaligned terapage
 .8byte 0x8080000000, 0x0, read64_test  # misaligned gigapage
 .8byte 0x80400000, 0x0, read64_test    # misaligned megapage
 
-# =========== test 11.3.1.3 PTE Protection flags ===========
+# =========== test 12.3.1.3 PTE Protection flags ===========
 
-# test 11.3.1.3.1 User flag == 0
-# reads on pages with U=0 already tested in 11.3.1.1.4
+# test 12.3.1.3.1 User flag == 0
+# reads on pages with U=0 already tested in 12.3.1.1.4
 .8byte 0x008000099000, 0x111, executable_test                   # execute success when U=0, priv=S
 .8byte 0x008040000000, 0x1, goto_u_mode                     # go to U mode, return to gigapage at 0x008040000000 where PTE.U = 1. 0x9 written to output
 .8byte 0xFFFFFFFFFFFFFC80, 0x0880DEADBEEF0550, read64_test # read fault when U=0, priv=U
 .8byte 0x008000099000, 0xbad, executable_test                   # execute fault when U=0, priv=U
 
-# test 11.3.1.3.2 User flag == 1
+# test 12.3.1.3.2 User flag == 1
 .8byte 0x80201AC0, 0x0990DEADBEEF0033, read64_test # read success when U=1, priv=U
 .8byte 0x80000000, 0x2, goto_s_mode 
 .8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11
@@ -173,61 +173,58 @@ test_cases:
 .8byte 0x0, 0x2, write_mxr_sum                        # set sstatus.[MXR, SUM] = 10.
 .8byte 0x80201AC0, 0x0990DEADBEEF0033, read64_test # read fault when U=1, priv=S, sstatus.SUM=0
 
-# test 11.3.1.3.3 Read flag
-# reads on pages with R=1 already tested in 11.3.1.1.4
+# test 12.3.1.3.3 Read flag
+# reads on pages with R=1 already tested in 12.3.1.1.4
 .8byte 0x0, 0x1, write_mxr_sum                        # set sstatus.[MXR, SUM] = 01.
 .8byte 0x80612348, 0x0330DEADBEEF0440, read64_test # read fault when R=0, sstatus.MXR=0
 .8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11.
 .8byte 0x80612348, 0x0330DEADBEEF0440, read64_test # read success when MXR=1, X=1
 
-# test 11.3.1.3.4 Write flag
+# test 12.3.1.3.4 Write flag
 .8byte 0x10080BCDED8, 0x0440DEADBEEF0110, write64_test    # write success when W=1 (corresponding Paddr = 0x80BCDED8)
 .8byte 0x10080BCDED8, 0x0440DEADBEEF0110, read64_test   # check write success by reading value back
 .8byte 0x8000009E88, 0x0220DEADBEEF0BB0, write64_test     # write fault when W=0
 
-# test 11.3.1.3.5 eXecute flag
-# executes on pages with X = 1 already tested in 11.3.1.3.1
-.8byte 0x010087888000, 0x2, executable_test               # execute fault when X=0 
+# test 12.3.1.3.5 eXecute flag
+# executes on pages with X = 1 already tested in 12.3.1.3.1
+.8byte 0x010088888000, 0x2, executable_test               # execute fault when X=0 
 
-# In the following two tests, SVADU is not supported, so the software handles the A/D bits
-# Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits
-
-# test 11.3.1.3.6 Accessed flag == 0
+# test 12.3.1.3.6 Accessed flag == 0
 .8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # write fault when A=0
 .8byte 0x80203AB8, 0x0990DEADBEEF0990, read64_test# read fault when A=0
 
-# test 11.3.1.3.7 Dirty flag == 0
+# test 12.3.1.3.7 Dirty flag == 0
 .8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # write fault when D=0
 .8byte 0x80204AA0, 0x0440DEADBEEF0BB0, read64_test# read success when D=0
 
-# =========== test 11.3.1.4 SATP Register ===========
+# =========== test 12.3.1.4 SATP Register ===========
 
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
+# test 12.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
 // *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
 .8byte 0x8000F, 0x11, goto_sv48 # go to SV39 on a second, very minimal page table
 .8byte 0x5BC0AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping 
 
-# test 11.3.1.4.2 Test Global mapping
+# test 12.3.1.4.2 Test Global mapping
 // ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping.
 
 
-# =========== test 11.3.1.5 STATUS Registers ===========
+# =========== test 12.3.1.5 STATUS Registers ===========
 
-# test 11.3.1.5.1 mstatus.mprv translation
+# test 12.3.1.5.1 mstatus.mprv translation
 # *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
 .8byte 0x8000D, 0x0, goto_sv48 // go back to old, extensive page table
 .8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
 .8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
 .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
 
-# test 11.3.1.5.2 mstatus.mprv clearing
+# test 12.3.1.5.2 mstatus.mprv clearing
 # mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
 .8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
 .8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
 .8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
 
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
+# test 12.3.1.5.3 sstatus.mxr read
+# this bitfield already tested in 12.3.1.3.3
 
 # terminate tests
 .8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
deleted file mode 100644
index dcea1ff33..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
+++ /dev/null
@@ -1,251 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-MMU-SV48-SVADU
-//
-// Author: David_Harris@hmc.edu and Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
-//
-// Created 2021-06-15
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48)
-
-INIT_TESTS
-
-TRAP_HANDLER m
-
-j run_test_loop // begin test loop/table tests instead of executing inline code.
-
-INIT_TEST_TABLE
-
-TEST_STACK_AND_DATA
-
-# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook
-.align 3
-test_cases:
-
-# ---------------------------------------------------------------------------------------------
-# Test Contents
-#
-#   Here is where the actual tests are held, or rather, what the actual tests do.
-#   each entry consists of 3 values that will be read in as follows:
-#   
-#   '.8byte [x28 Value], [x29 Value], [x30 value]'
-#                     or
-#   '.8byte [address], [value], [test type]'
-#
-#   The encoding for x30 test type values can be found in the test handler in the framework file
-# 
-# ---------------------------------------------------------------------------------------------
-
-
-# =========== test 11.3.1.1 Page Table Translation ===========
-
-# test 11.3.1.1.1 write page tables / entries to phyiscal memory
-# sv48 page table (See Figure 12.12***):
-# Level 3 page table, situated at 0x8000D000
-.8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A
-.8byte 0x000000008000D008, 0x0000000020005001, write64_test # points to level 2 page table B # Changing DAU bits of each pointer to zero
-.8byte 0x000000008000D010, 0x00000000000000C7, write64_test # Vaddr 0x010000000000, Paddr 0x00000000: aligned terapage
-.8byte 0x000000008000D018, 0x00004000004000C7, write64_test # Vaddr 0x018000000000, misaligned terapage
-.8byte 0x000000008000DFF8, 0x0000000020005401, write64_test # points to level 2 page table C
-
-# Level 2 page table A
-.8byte 0x0000000080013010, 0x0000000020006001, write64_test # points to level 1 page table A
-
-# Level 2 page table B
-.8byte 0x0000000080014000, 0x00000000200000CB, write64_test # Vaddr 0x008000000000, Paddr 0x80000000: aligned gigapage used for execution tests
-.8byte 0x0000000080014008, 0x00000000200000DF, write64_test # Vaddr 0x008040000000, Paddr 0x80000000: aligned gigapage (aliased with data and instr memory) U bit set.
-.8byte 0x0000000080014010, 0x00000400080000C3, write64_test # Vaddr 0x008080000000, misaligned gigapage
-# Level 2 page table C
-.8byte 0x0000000080015FF8, 0x0000000020005801, write64_test # points to level 1 page table B
-
-# Level 1 page table A
-.8byte 0x0000000080018000, 0x00000000200000CF, write64_test # Vaddr 0x80000000, Paddr 0x80000000: aligned megapage (data and instr memory)
-.8byte 0x0000000080018008, 0x0000000020006401, write64_test # points to level 0 page table A
-.8byte 0x0000000080018010, 0x000000C0000400CF, write64_test # Vaddr 0x80400000, misaligned megapage
-.8byte 0x0000000080018018, 0x00000000214800C9, write64_test # Vaddr 0x80600000, Paddr 0x85200000: aligned megapage, R=0
-# Level 1 page table B
-.8byte 0x0000000080016FF8, 0x0000000020006801, write64_test # points to level 0 page table B
-
-# Level 0 page table A
-.8byte 0x0000000080019000, 0x00000000200070D1, write64_test # Vaddr 0x80200000, Paddr 0x8001C000: bad PTE points to level -1 table
-.8byte 0x0000000080019008, 0x00000000200800DF, write64_test # Vaddr 0x80201000, Paddr 0x80200000: aligned kilopage
-.8byte 0x0000000080019010, 0x00000000200810DF, write64_test # Vaddr 0x80202000, Paddr 0x80204000: bad PTE has W but not R
-.8byte 0x0000000080019018, 0x0000000020080817, write64_test # Vaddr 0x80203000, Paddr 0x80202000: A=0, should cause read fault
-.8byte 0x0000000080019020, 0x0000000020080C57, write64_test # Vaddr 0x80204000, Paddr 0x80203000: D=0, should cause write fault
-.8byte 0x0000000080019028, 0x0000000020333000, write64_test # Vaddr 0x80205000, Paddr 0x80CCC000, invalid page.
-# Level 0 page table B
-.8byte 0x000000008001AFF8, 0x00000000200804CF, write64_test # Vaddr 0xFFFFFFFFF000, Paddr 0x80201000: aligned kilopage
-
-# second page table to check context switches with satp
-# Level 3 page table A
-.8byte 0x8000F000, 0x2000BC01, write64_test # points to level 2 page table A
-# Level 2 page table A
-.8byte 0x8002F000, 0x200000CF, write64_test # Vaddr 0x0, Paddr 0x80000000: aligned gigapage
-.8byte 0x8002F010, 0x200000CF, write64_test # Vaddr 0x80000000, Paddr 0x80000000: aligned gigapage (data and instr memory)
-
-
-# test 11.3.1.1.2 write values to Paddrs in each page
-# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
-# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
-.8byte 0x82777778, 0x0EE0DEADBEEF0CC0, write64_test # 11.3.1.1.4 terapage
-.8byte 0x85BC0AB0, 0x0000DEADBEEF0000, write64_test # 11.3.1.1.4 gigapage
-.8byte 0x800F0AB8, 0x0880DEADBEEF0055, write64_test # 11.3.1.1.4 megapage
-.8byte 0x80201888, 0x0220DEADBEEF0099, write64_test # 11.3.1.1.4 kilopage
-.8byte 0x80099000, 0x0000806711100393, write64_test # 11.3.1.3.1 write executable code for "li x7, 0x111; ret"
-.8byte 0x80200400, 0x0000806711100393, write64_test # 11.3.1.3.2 write same executable code 
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2 
-.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
-.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
-.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
-.8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a) 
-	
-#.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4
-        
-# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
-.8byte 0x0, 0x0, goto_baremetal # satp.MODE = baremetal / no translation.
-.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-.8byte 0x82777778, 0x0EE0DEADBEEF0CC0, read64_test
-.8byte 0x85BC0AB0, 0x0000DEADBEEF0000, read64_test
-.8byte 0x800F0AB8, 0x0880DEADBEEF0055, read64_test
-.8byte 0x80200AC0, 0x0990DEADBEEF0033, read64_test
-.8byte 0x80200130, 0x0110DEADBEEF0077, read64_test
-.8byte 0x80201888, 0x0220DEADBEEF0099, read64_test
-.8byte 0x85212348, 0x0330DEADBEEF0440, read64_test
-
-# test 11.3.1.1.4 check translation works in sv48, read the same values from previous tests, this time with Vaddrs
-.8byte 0x8000D, 0x0, goto_sv48 # satp.MODE = sv48, with base page table PPN = 0x8000D and ASID = 0. current VPN: megapage at 0x80000000. Nothing written to output
-.8byte 0x10082777778, 0x0EE0DEADBEEF0CC0, read64_test      # terapage at Vaddr 0x010000000000, Paddr 0x0
-.8byte 0x8005BC0AB0, 0x0000DEADBEEF0000, read64_test       # gigapage at Vaddr 0x008000000000, Paddr 0x80000000
-.8byte 0x800F0AB8, 0x0880DEADBEEF0055, read64_test         # megapage at Vaddr 0x80000000, Paddr 0x80000000
-.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test # kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000
-
-# =========== test 11.3.1.2 page fault tests ===========
-
-# test 11.3.1.2.1 page fault if upper bits of Vaddr are not the same
-.8byte 0x001000800ABC0AB0, 0x0, read64_test# gigapage at Vaddr 0x008000000000, Paddr 0x80000000, bad 1 in upper bits
-.8byte 0xFF0FFFFFFFFFF888, 0x0, read64_test# kilopage at Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000, bad 0000 in upper bits
-
-# test 11.3.1.2.2 read fault when reading an address where the valid flag is zero
-.8byte 0x80205000, 0x0, read64_test
-
-# test 11.3.1.2.3 write fault if PTE has W and ~R flags set
-.8byte 0x80202000, 0x0, write64_test 
-
-# test 11.3.1.2.4 Fault if last level PTE is a pointer
-.8byte 0x80200000, 0x0, read64_test
-
-# test 11.3.1.2.5 read fault on misaligned pages
-.8byte 0x18000000000, 0x0, read64_test # misaligned terapage
-.8byte 0x8080000000, 0x0, read64_test  # misaligned gigapage
-.8byte 0x80400000, 0x0, read64_test    # misaligned megapage
-
-# =========== test 11.3.1.3 PTE Protection flags ===========
-
-# test 11.3.1.3.1 User flag == 0
-# reads on pages with U=0 already tested in 11.3.1.1.4
-.8byte 0x008000099000, 0x111, executable_test                   # execute success when U=0, priv=S
-.8byte 0x008040000000, 0x1, goto_u_mode                     # go to U mode, return to gigapage at 0x008040000000 where PTE.U = 1. 0x9 written to output
-.8byte 0xFFFFFFFFFFFFFC80, 0x0880DEADBEEF0550, read64_test # read fault when U=0, priv=U
-.8byte 0x008000099000, 0xbad, executable_test                   # execute fault when U=0, priv=U
-
-# test 11.3.1.3.2 User flag == 1
-.8byte 0x80201AC0, 0x0990DEADBEEF0033, read64_test # read success when U=1, priv=U
-.8byte 0x80000000, 0x2, goto_s_mode 
-.8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11
-.8byte 0x80201130, 0x0110DEADBEEF0077, read64_test # read success when U=1, priv=S, sstatus.SUM=1
-.8byte 0x80201400, 0xbad, executable_test               # execute fault when U=1, priv=S (with any sstatus.SUM) 
-.8byte 0x0, 0x2, write_mxr_sum                        # set sstatus.[MXR, SUM] = 10.
-.8byte 0x80201AC0, 0x0990DEADBEEF0033, read64_test # read fault when U=1, priv=S, sstatus.SUM=0
-
-# test 11.3.1.3.3 Read flag
-# reads on pages with R=1 already tested in 11.3.1.1.4
-.8byte 0x0, 0x1, write_mxr_sum                        # set sstatus.[MXR, SUM] = 01.
-.8byte 0x80612348, 0x0330DEADBEEF0440, read64_test # read fault when R=0, sstatus.MXR=0
-.8byte 0x0, 0x3, write_mxr_sum                        # set sstatus.[MXR, SUM] = 11.
-.8byte 0x80612348, 0x0330DEADBEEF0440, read64_test # read success when MXR=1, X=1
-
-# test 11.3.1.3.4 Write flag
-.8byte 0x10080BCDED8, 0x0440DEADBEEF0110, write64_test    # write success when W=1 (corresponding Paddr = 0x80BCDED8)
-.8byte 0x10080BCDED8, 0x0440DEADBEEF0110, read64_test   # check write success by reading value back
-.8byte 0x8000009E88, 0x0220DEADBEEF0BB0, write64_test     # write fault when W=0
-
-# test 11.3.1.3.5 eXecute flag
-# executes on pages with X = 1 already tested in 11.3.1.3.1
-.8byte 0x010087888000, 0x2, executable_test               # execute fault when X=0 
-
-
-# In the following two tests, SVADU is supported, so the hardware handles the A/D bits
-# Initially test with ADUE = 0, so needing to set A/D bits triggers page fault
-
-# test 11.3.1.3.6(a) Accessed flag == 0
-.8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # store page fault when A=0
-.8byte 0x802036D0, 0x0990DEADBEEF0990, read64_test  # load page fault when A=0
-
-# test 11.3.1.3.7(a) Dirty flag == 0
-.8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # store page fault when D=0
-.8byte 0x80204658, 0xDEADBEEFDEADBEEF, read64_test  # read success when D=0
-
-# Now set ADUE bit
-.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
-.8byte 0x0, 0x2000000000000000, write_menvcfg  # set menvcfg.ADUE = 1
-.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
-
-# Since SVADU is 1, there are no faults when A/D=0
-
-# test 11.3.1.3.6 Accessed flag == 0
-.8byte 0x802036D0, 0x0990DEADBEEF0770, write64_test # Write success when A=0 and SVADU is enabled
-.8byte 0x802036D0, 0x0990DEADBEEF0770, read64_test # Read success when A=0 and SVADU is enabled
-
-# test 11.3.1.3.7 Dirty flag == 0
-.8byte 0x80204658, 0x0440DEADBEEF0AA0, write64_test # Write success when D=0 and SVADU is enabled
-.8byte 0x80204658, 0x0440DEADBEEF0AA0, read64_test # read success when D=0
-
-# =========== test 11.3.1.4 SATP Register ===========
-
-# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
-// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
-.8byte 0x8000F, 0x11, goto_sv48 # go to SV39 on a second, very minimal page table
-.8byte 0x5BC0AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping 
-
-# test 11.3.1.4.2 Test Global mapping
-// ***.8byte 0x7FFFFFF888, 0x0220DEADBEEF0099, read64_test # read success of global PTE undefined in current mapping.
-
-
-# =========== test 11.3.1.5 STATUS Registers ===========
-
-# test 11.3.1.5.1 mstatus.mprv translation
-# *** mstatus.mprv = 0 tested on every one of the translated reads and writes before this.
-.8byte 0x8000D, 0x0, goto_sv48 // go back to old, extensive page table
-.8byte 0x80000000, 0x1, goto_m_mode // go to m mode to be able to write mstatus
-.8byte 0x1, 0x1, read_write_mprv // write 1 to mstatus.mprv and set mstatus.mpp to be 01=S
-.8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, read64_test // read test succeeds with translation even though we're in M mode since MPP=S and MPRV=1
-
-# test 11.3.1.5.2 mstatus.mprv clearing
-# mstatus.mprv is already 1 from the last test so going to S mode should clear it with the mret
-.8byte 0x80000000, 0x1, goto_s_mode // This should zero out the mprv bit but now to read and write mstatus, we have to 
-.8byte 0x80000000, 0x1, goto_m_mode // go back to m mode to allow us to reread mstatus.
-.8byte 0x0, 0x0, read_write_mprv // read what should be a zeroed out mprv value and then force it back to zero.
-
-# test 11.3.1.5.3 sstatus.mxr read
-# this bitfield already tested in 11.3.1.3.3
-
-# terminate tests
-.8byte 0x0, 0x0, terminate_test # brings us back into machine mode with a final ecall, writing 0x9 to the output.
-
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
index 3cb9b2421..b192d229c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",mtvec)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
index 93c9d1b92..69562c59d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph-01.S
@@ -23,7 +23,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
+// this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); 
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
 
 .section .text.init
@@ -224,6 +225,9 @@ main_code: #####
     # load address of trap handler
     la t0, trap_handler
     csrrw x0, mtvec, t0
+    # delegate all external interrupts to machine mode
+    li t0, 0xD00
+    csrrc x0, mideleg, t0
     # set MIE
     li t0, 0x8
     csrrs x0, mstatus, t0
@@ -913,7 +917,4 @@ RVMODEL_DATA_BEGIN
 # signature output
 wally_signature:
 .fill 0x200, 8, 0x00000000
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
 RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
index ce15c0525..b50b20f96 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
index 3f312c9b3..5a6dc34e2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
index a5385e001..3048c1ebc 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
@@ -35,7 +35,7 @@
 #define PLIC_RANGE     0x03FFFFFF
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
index 140c0d97d..fc3864d38 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
index 01b3736bc..7a565c71d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
index fa2bd599c..28df4374c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S
deleted file mode 100644
index a31069470..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S
+++ /dev/null
@@ -1,698 +0,0 @@
-///////////////////////////////////////////
-//
-// WALLY-spi
-//
-// Author: David_Harris@hmc.edu and Naiche Whyte-Aguayo 
-//
-// Created 2023-02-01
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "WALLY-TEST-LIB-64.h" 
-
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",spi)
-
-INIT_TESTS
-
-TRAP_HANDLER m
-
-j run_test_loop // begin test loop/table tests instead of executing inline code.
-
-INIT_TEST_TABLE
-
-END_TESTS
-
-TEST_STACK_AND_DATA
-
-.align 3
-test_cases:
-# ---------------------------------------------------------------------------------------------
-# Test Contents
-#
-#   Here is where the actual tests are held, or rather, what the actual tests do.
-#   each entry consists of 3 values that will be read in as follows:
-#   
-#   '.8byte [x28 Value], [x29 Value], [x30 value]'
-#                     or
-#   '.8byte [address], [value], [test type]'
-#
-#   The encoding for x30 test type values can be found in the test handler in the framework file
-# ---------------------------------------------------------------------------------------------
-
-.equ SPI, 0x10040000
-.equ sck_div, (SPI+0x00)
-.equ sck_mode, (SPI+0x04)
-.equ cs_id, (SPI+0x10)
-.equ cs_def, (SPI+0x14)
-.equ cs_mode, (SPI+0x18)
-.equ delay0, (SPI+0x28)
-.equ delay1, (SPI+0x2C)
-.equ fmt, (SPI+0x40)
-.equ tx_data, (SPI+0x48)
-.equ rx_data, (SPI+0x4C)
-.equ tx_mark, (SPI+0x50)
-.equ rx_mark, (SPI+0x54)
-.equ ie, (SPI+0x70)
-.equ ip, (SPI+0x74)
-
-# =========== Verify all registers reset to correct values ===========
-
-.8byte sck_div, 0x00000003, read32_test     # sck_div reset to 0x3
-.8byte sck_mode, 0x00000000, read32_test    # sck_mode reset to 0x0
-.8byte cs_id, 0x00000000, read32_test       # cs_id reset to 0x0
-.8byte cs_def, 0x0000000F, read32_test      # cs_def reset to 0x1
-.8byte cs_mode, 0x00000000, read32_test     # cs_mode reset to 0x0
-.8byte delay0, 0x00010001, read32_test      # delay0 reset to [31:24] 0x0, [23:16] 0x1, [15:8] 0x0, [7:0] 0x1
-.8byte delay1, 0x00000001, read32_test      # delay1 reset to 0x1
-.8byte fmt, 0x00080000, read32_test         # fmt reset to [31:20] 0x0, [19:16] 0x8, [15:0] 0x0 for non-flash enabled SPI controllers
-.8byte tx_data, 0x00000000, read32_test     # tx_data [30:0] reset to 0x0, [31] read only
-.8byte tx_mark, 0x00000000, read32_test     # tx_mark reset to 0x0 for non-flash enabled controllers
-.8byte rx_mark, 0x00000000, read32_test     # rx_mark reset to 0x0
-.8byte ie, 0x00000000, read32_test          # ie reset to 0x0
-.8byte ip, 0x00000000, read32_test          # ip reset to 0x0
-
-# =========== watermark interrupts ===============
-
-#test watermark interrupts at beginning where fifo read/write pointers are known b/c reset
-# txwmp raised when # of entries in txfifo < txmark, rxwm raised when # of entries in rxfifo > rxmark
-
-.8byte ip, 0x00000000, read32_test          # txfifo entries not < 0, rxfifo entries not > 0;
-.8byte tx_mark, 0x00000004, write32_test    # set tx_mark to 4
-.8byte rx_mark, 0x00000003, write32_test    # set rx_mark to 3
-.8byte ip, 0x00000001, read32_test          # tx entries < 4, rx entries ! > 3
-.8byte tx_data, 0x41526374, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte ip, 0x00000003, read32_test          # tx entries < 4, rx entries > 3, visual inspection should see tx TransmitFIFOReadIncrement
-
-# txfifo wptr now at 0011, rxfifo wptr at 0000
-
-.8byte rx_mark, 0x00000007, write32_test    # set rx_mark to 7
-.8byte tx_data, 0xD4C3B2A1, spi_burst_send
-.8byte 0x0, 0x00000007, spi_data_wait       # rxfifo full, txfifo wptr at 1000, rxfifo wptr at 0000
-.8byte ip, 0x00000003, read32_test        
-.8byte rx_data, 0x00000074, read32_test
-.8byte rx_data, 0x00000063, read32_test     # clear 2 entries, txfifo wptr at 1000, rxfifo wptr at 0010
-
-
-.8byte tx_data, 0x000000A4, write32_test
-.8byte tx_data, 0x000000B4, write32_test    # tx 1010, rx 0010
-.8byte 0x0, 0x00000007, spi_data_wait       # 8 tx 1010, rx 0010
-.8byte rx_mark, 0x00000004, write32_test
-.8byte rx_data, 0x00000052, read32_test     # 7 rx 0011
-.8byte rx_data, 0x00000041, read32_test     # 6 rx 0100
-.8byte rx_data, 0x000000A1, read32_test     # 5 rx 0101
-.8byte ip, 0x00000003, read32_test          # 5 things in rx fifo
-.8byte rx_data, 0x000000B2, read32_test     # 4 tx 1010, rx 0110
-.8byte ip, 0x00000001, read32_test          # 4 entries in rxfifo, not strictly greater than 4
-
-.8byte rx_mark, 0x00000007, write32_test
-.8byte tx_data, 0xD5C5B5A5, spi_burst_send  # 8 tx1110, rx 0110
-.8byte 0x0, 0x00000007, spi_data_wait       
-
-.8byte rx_mark, 0x00000005, write32_test
-.8byte rx_data, 0x000000C3, read32_test     # tx 1110, rx 0111
-.8byte rx_data, 0x000000D4, read32_test     # tx 1110, rx 1000
-.8byte ip, 0x00000003, read32_test          # 6 entries
-.8byte rx_data, 0x000000A4, read32_test     # tx 1110, rx 1001
-.8byte ip, 0x00000001, read32_test          # 5 entries
-.8byte rx_data, 0x000000B4, read32_test     # tx 1110, rx 1010
-.8byte rx_data, 0x000000A5, read32_test     # tx 1110, rx 1011
-
-.8byte rx_mark, 0x00000006, write32_test
-.8byte tx_data, 0xD7C7B7A7, spi_burst_send
-.8byte 0x0, 0x00000006, spi_data_wait       # tx 0010, rx 1011
-.8byte tx_mark, 0x00000000, write32_test
-.8byte rx_mark, 0x00000000, write32_test
-.8byte rx_data, 0x000000B5, read32_test     # tx 0010, rx 1100
-.8byte rx_data, 0x000000C5, read32_test     # tx 0010, rx 1101
-.8byte rx_data, 0x000000D5, read32_test     # tx 0010, rx 1110
-.8byte rx_data, 0x000000A7, read32_test     # tx 0010, rx 1111
-.8byte rx_data, 0x000000B7, read32_test     # tx 0010, rx 0000
-.8byte rx_data, 0x000000C7, read32_test     # tx 0010, rx 0001
-.8byte ip, 0x00000002, read32_test
-.8byte rx_data, 0x000000D7, read32_test     # tx 0010, rx 1010
-.8byte ip, 0x00000000, read32_test
-.8byte tx_mark, 0x00000000, write32_test
-.8byte rx_mark, 0x00000000, write32_test    # reset watermark registers
-
-# =========== Basic read-write ===========
-
-.8byte tx_data, 0x000000011, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# =========== Different cs_mode, sck_mode, cs_def, sck_div ===========
-
-# Test sck_div
-
-.8byte sck_div, 0x00000101, write32_test    # set sck_div to 0x101
-.8byte tx_data, 0x000000FF, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000FF, read32_test     # read rx_data
-
-# Test min sck_div
-
-.8byte sck_div, 0x000000000, write32_test   #set sck_div to 0
-.8byte tx_data, 0xABACADAE, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x000000AE, read32_test
-.8byte rx_data, 0x000000AD, read32_test
-.8byte rx_data, 0x000000AC, read32_test
-.8byte rx_data, 0x000000AB, read32_test
-
-# min sck_div, sckmode 01
-
-.8byte sck_mode, 0x00000001, write32_test
-.8byte tx_data, 0xABACADAE, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x000000AE, read32_test
-.8byte rx_data, 0x000000AD, read32_test
-.8byte rx_data, 0x000000AC, read32_test
-.8byte rx_data, 0x000000AB, read32_test
-
-#min sck_div, sckmode 10
-.8byte sck_mode, 0x00000002, write32_test
-.8byte tx_data, 0xABACADAE, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x000000AE, read32_test
-.8byte rx_data, 0x000000AD, read32_test
-.8byte rx_data, 0x000000AC, read32_test
-.8byte rx_data, 0x000000AB, read32_test
-
-#min sck_div, sckmode 11
-.8byte sck_mode, 0x00000003, write32_test
-.8byte tx_data, 0xABACADAE, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x000000AE, read32_test
-.8byte rx_data, 0x000000AD, read32_test
-.8byte rx_data, 0x000000AC, read32_test
-.8byte rx_data, 0x000000AB, read32_test
-
-
-
-
-# Test phase
-
-.8byte sck_div, 0x00000003, write32_test    # reset sck_div to 0x03 so only sck_mode is different
-.8byte sck_mode, 0x00000001, write32_test   # change phase to falling edge
-.8byte tx_data, 0x000000A0, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000A0, read32_test     # read rx_data
-
-# Test polarity 
-
-.8byte sck_mode, 0x00000000, write32_test   # reset sck phase to rising edge
-.8byte sck_mode, 0x00000002, write32_test   # set sck polarity active low
-.8byte tx_data, 0x0000000B, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x0000000B, read32_test     # read rx_data
-
-# Test phase polarity
-.8byte sck_mode, 0x00000003, write32_test   # set sck mode to 11
-.8byte tx_data, 0x000000F3, write32_test    # place f3 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       # wait for transmission to end
-.8byte rx_data, 0x000000F3, read32_test     # read rx_data
-    
-# Test chip select polarity
-
-.8byte sck_mode, 0x00000000, write32_test   # reset sck polarity to active high
-.8byte cs_def, 0x0000000E, write32_test     # set cs[0] to inactive low
-.8byte tx_data, 0x00000079, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000079, read32_test     # read rx_data
-
-# Test chip id 
-
-.8byte cs_def, 0x0000000F, write32_test     # reset all cs to active low
-.8byte cs_id, 0x00000001, write32_test      # select cs[1] 
-.8byte tx_data, 0x00000000, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test cs hold mode
-
-.8byte cs_id, 0x00000000, write32_test      # select cs[0] 
-.8byte cs_mode, 0x00000002, write32_test    # set cs_mode to HOLD
-.8byte tx_data, 0x000000C0, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000C0, read32_test     # read rx_data
-
-# Test cs OFF mode
-
-.8byte cs_mode, 0x00000003, write32_test    # set cs_mode to OFF
-.8byte tx_data, 0x00000011, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# =========== Test delay0 register (mode auto)===========
-
-# Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay)
-
-.8byte cs_mode, 0x00000000, write32_test    # reset cs_mode to auto, all cs and sck mode settings should be defualt
-.8byte delay0, 0x00010000, write32_test     # set cs-sck delay to 0
-.8byte tx_data, 0x00000020, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000020, read32_test     # read rx_data
-
-# Test cs-sck delay of 0 with sck phase 1 (no delay)
-
-.8byte sck_mode, 0x00000001, write32_test   # set sck_mode[0] to 1 (sck phase = 1)
-.8byte tx_data, 0x00000032, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000032, read32_test     # read rx_data
-
-# Test arbitrary cs-sck delay (sck phase 1)
-
-.8byte delay0, 0x00010005, write32_test     # set cs-sck delay to 5 cycles
-.8byte tx_data, 0x00000048, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000048, read32_test     # read rx_data
-
-# Test arbitrary cs-sck delay (sck phase 0)
-
-.8byte sck_mode, 0x00000000, write32_test   # set sck phase to 0
-.8byte delay0, 0x00010005, write32_test     # set cs-sck delay to AF cycles
-.8byte tx_data, 0x000000AF, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000AF, read32_test     # read rx_data
-
-
-# Test sck-cs delay of 0 with sck phase = 0 (no delay)
-
-.8byte delay0, 0x00000001, write32_test     # set cs-sck delay to 0
-.8byte tx_data, 0x00000050, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000050, read32_test     # read rx_data
-
-# Test sck-cs delay of 0 with sck phase 1 (implicit half cycle delay)
-
-.8byte sck_mode, 0x00000001, write32_test   # set sck_mode[0] to 1 (sck phase = 1)
-.8byte tx_data, 0x0000006B, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x0000006B, read32_test     # read rx_data
-
-# Test arbitrary sck-cs delay (sck phase 1)
-
-.8byte delay0, 0x00050001, write32_test     # set cs-sck delay to A5 cycles
-.8byte tx_data, 0x00000011, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000011, read32_test     # read rx_data
-
-# Test arbitrary sck-cs delay (sck phase 0)
-
-.8byte sck_mode, 0x00000000, write32_test   # set sck phase to 0
-.8byte delay0, 0x00050001, write32_test     # set cs-sck delay to 5 cycles
-.8byte tx_data, 0x00000015, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000015, read32_test     # read rx_data
-
-# SCKCS Delay of 0, SCKMODE 10
-.8byte sck_mode, 0x00000002, write32_test    #set sckmode to 10
-.8byte delay0, 0x00000001, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Arbitrary SCKCS delay, SCKMODE 10
-.8byte delay0, 0x00050001, write32_test    # set sckcs delay to 5
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Long SCKCS delay, SCKMODE 10
-.8byte delay0, 0x00A50001, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# CSSCK Delay 0, SCKMODE 10
-.8byte delay0, 0x00010000, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Arbitrary CSSCK delay, SCKMODE 10
-.8byte delay0, 0x00010005, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-# Long CSSCK delay, SCKMODE 10
-.8byte delay0, 0x000100A5, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000010, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000010, read32_test     # reade rx_data
-
-
-
-# SCKCS Delay of 0, SCKMODE 11
-.8byte sck_mode, 0x00000003, write32_test
-.8byte delay0, 0x00000001, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Arbitrary SCKCS delay, SCKMODE 11
-.8byte delay0, 0x00050001, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Long SCKCS delay, SCKMODE 11
-.8byte delay0, 0x00A50001, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# CSSCK Delay 0, SCKMODE 11
-.8byte delay0, 0x00010000, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Arbitrary CSSCK delay, SCKMODE 11
-.8byte delay0, 0x00010005, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# Long CSSCK delay, SCKMODE 11
-.8byte delay0, 0x000100A5, write32_test    # set sckcs delay to 0
-.8byte tx_data, 0x00000011, write32_test    # place 10 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait       #wait for transmission
-.8byte rx_data, 0x00000011, read32_test     # reade rx_data
-
-# =========== Test delay1 register ===========
-
-# Test inter cs delay 
-
-.8byte sck_mode, 0x00000000, write32_test   #reset sck_mode
-.8byte delay0, 0x00010001, write32_test     # reset delay0 register
-.8byte delay1, 0x00000005, write32_test     # set inter_cs delay to 5
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x44332211, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000011, read32_test
-.8byte rx_data, 0x00000022, read32_test
-.8byte rx_data, 0x00000033, read32_test
-.8byte rx_data, 0x00000044, read32_test     
-
-#test long inter_cs delay
-
-.8byte delay1, 0x000000A5, write32_test
-.8byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x0000007B, write32_test
-.8byte 0x0, 0x00000000, spi_data_wait
-.8byte rx_data, 0x0000007B, read32_test
-
-
-# Test inter_cs delay set to 0
-
-.8byte delay1, 0x00000000, write32_test     # set inter_cs delay to 5
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x54433221, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000021, read32_test
-.8byte rx_data, 0x00000032, read32_test
-.8byte rx_data, 0x00000043, read32_test
-.8byte rx_data, 0x00000054, read32_test
-
-
-# Test inter_xfr delay of 0 (maybe change behavior to half-period instead of period)
-
-.8byte delay1, 0x00000001, write32_test     # reset inter_cs delay to 1
-.8byte cs_mode, 0x00000002, write32_test    # set cs_mode to HOLD 
-.8byte tx_data, 0x99887766, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000066, read32_test
-.8byte rx_data, 0x00000077, read32_test
-.8byte rx_data, 0x00000088, read32_test
-.8byte rx_data, 0x00000099, read32_test
-
-# Test inter_xfr delay 0 with phase = 1
-.8byte sck_mode, 0x00000001, write32_test
-.8byte tx_data, 0x99887766, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x00000066, read32_test
-.8byte rx_data, 0x00000077, read32_test
-.8byte rx_data, 0x00000088, read32_test
-.8byte rx_data, 0x00000099, read32_test
-
-
-# Test arbitrary inter_xfr delay
-
-.8byte delay1, 0x00050001, write32_test     # set inter_xfr delay to 5
-.8byte sck_mode, 0x00000001, write32_test
-.8byte tx_data, 0x98877665, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000065, read32_test
-.8byte rx_data, 0x00000076, read32_test
-.8byte rx_data, 0x00000087, read32_test
-.8byte rx_data, 0x00000098, read32_test
-
-# test long inter_xfr delay
-.8byte delay1, 0x00A50001, write32_test
-.8byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x00000048, write32_test
-.8byte 0x0, 0x00000000, spi_data_wait
-.8byte rx_data, 0x00000048, read32_test
-
-# Test cs-sck delay with cs_mode = HOLD
-
-.8byte delay1, 0x00000001, write32_test     # set inter_xfr delay to 0
-.8byte delay0, 0x00010005, write32_test     # set cs-sck delay to 5 (should have no effect because cs is never inactive)
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0xAABBCCDD, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000DD, read32_test     # read rx_data
-.8byte rx_data, 0x000000CC, read32_test
-.8byte rx_data, 0x000000BB, read32_test
-.8byte rx_data, 0x000000AA, read32_test
-
-# Test sck-cs delay cs_mode = HOLD
-
-.8byte delay0, 0x00000501, write32_test     # set sck-cs delay to 5 (should have no effect because cs is never inactive)
-.8byte tx_data, 0xABBCCDDE, spi_burst_send   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000DE, read32_test     # read rx_data
-.8byte rx_data, 0x000000CD, read32_test
-.8byte rx_data, 0x000000BC, read32_test
-.8byte rx_data, 0x000000AB, read32_test
-
-# Test hold mode deassert conditions
-
-.8byte delay1, 0x00000001, write32_test     # reset delay1 register
-.8byte delay0, 0x00010001, write32_test     # reset delay0 register
-.8byte cs_mode, 0x00000002, write32_test    # set cs_mode to hold
-.8byte tx_data, 0x000000CE, write32_test    # place data into tx_data
-.8byte cs_id, 0x00000001, write32_test      #change selected cs pin. should deassert cs[0] in hold mode
-.8byte cs_def, 0x0000000D, write32_test     # change selected cs pins def value. should deassert cs[1]
-.8byte cs_mode, 0x00000000, write32_test    # change cs_mode to auto, should deassert cs[1], have now gone through all deassertion conditions
-.8byte cs_def, 0x0000000F, write32_test     # reset cs_def
-.8byte cs_id, 0x00000000, write32_test      # reset cs_id
-.8byte rx_data, 0x000000CE, read32_test     # clear rx_fifo
-
-# =========== Test frame format (fmt) register ===========
-
-# Test frame length of 4
-
-.8byte delay1, 0x00000001, write32_test     # reset delay1 register
-.8byte delay0, 0x00010001, write32_test     # reset delay0 register
-.8byte sck_mode, 0x00000000, write32_test   #reset sckmode register
-.8byte cs_mode, 0x00000000, write32_test    # set cs_mode to AUTO 
-.8byte fmt, 0x00040000, write32_test        # set frame length to 4
-.8byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x000000F0, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000F0, read32_test     # read rx_data
-
-# Test frame length of 0
-
-#.8byte fmt, 0x00000000, write32_test        # set frame length to 4
-#.8byte tx_data, 0x00000077, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x0101, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x00000077, read32_test     # read rx_data
-
-# test frame length 1 burst
-.8byte fmt, 0x00010000, write32_test
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x80008000, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x00000000, read32_test
-.8byte rx_data, 0x00000080, read32_test
-.8byte rx_data, 0x00000000, read32_test
-.8byte rx_data, 0x00000080, read32_test
-
-
-# Test big endian with frame length = 5
-
-.8byte fmt, 0x00050000, write32_test        # set frame length to 5, big endian
-.8byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x000000A8, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x000000A8, read32_test     # read rx_data
-
-# Test big endian burst with frame length = 5
-
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x03774FFF, spi_burst_send 
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x000000F8, read32_test 
-.8byte rx_data, 0x00000048, read32_test
-.8byte rx_data, 0x00000070, read32_test
-.8byte rx_data, 0x00000000, read32_test
-
-
-
-
-# Test little endian with frame length = 5
-
-.8byte fmt, 0x00050004, write32_test        # set frame length to 5, little-endian
-.8byte rx_mark, 0x0000000, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0x000000A8, write32_test   # place 8'h11 into tx_data
-.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-.8byte rx_data, 0x00000008, read32_test     # read rx_data -> 08
-
-#test little endian burst with frame length = 5
-
-.8byte rx_mark, 0x0000003, write32_test     # preset rx watermark b/c of hardware interlock
-.8byte tx_data, 0xFF4F7703, spi_burst_send
-.8byte 0x0, 0x00000003, spi_data_wait
-.8byte rx_data, 0x00000003, read32_test     #03
-.8byte rx_data, 0x00000017, read32_test     #17
-.8byte rx_data, 0x0000000F, read32_test     #0F
-.8byte rx_data, 0x0000001F, read32_test     #1F
-
-# Test dual SPI protocol, frame length = 8, big endian
-
-#.8byte fmt, 0x00080001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x000000C8, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test dual SPI protocol, frame length = 4
-
-#.8byte fmt, 0x00040001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x000000A2, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x000000A0, read32_test     # read rx_data
-
-# Test dual SPI protocol, frame length = 5
-
-#.8byte fmt, 0x00050001, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x00000075, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x00000074, read32_test     # read rx_data
-
-# Test dual SPI protocol burst, frame length = 5
-#.8byte tx_data, 0x30733FFF, spi_burst_send
-#.8byte 0x0, 0x00000003, spi_data_wait
-#.8byte rx_data, 0x000000FC, read32_test
-#.8byte rx_data, 0x0000003C, read32_test
-#.8byte rx_data, 0x00000070, read32_test
-#.8byte rx_data, 0x00000030, read32_test 
-
-# Test quad SPI protocol, frame length = 5
-
-#.8byte fmt, 0x00050002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x0000003F, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x0000003F, read32_test     # read rx_data
-
-# Test quad SPI protocol, frame length = 4
-
-#.8byte fmt, 0x00040002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x0000000F, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x00000000, read32_test     # read rx_data
-
-# Test quad SPI protocol, frame length = 8
-
-#.8byte fmt, 0x00080002, write32_test        # set frame length to 8, big-endian, dual SPI
-#.8byte tx_data, 0x000000F0, write32_test   # place 8'h11 into tx_data
-#.8byte 0x0, 0x00000000, spi_data_wait           # wait for transmission to end
-#.8byte rx_data, 0x000000F0, read32_test     # read rx_data
-
-
-
-
-
-
-
-
-
-# =========== Test watermark interrupts ===========
-
-# Test transmit watermark interrupt (triggers when entries in tx FIFO < tx watermark) without external enables
-
-SETUP_PLIC
-.8byte fmt, 0x00080000, write32_test        # reset format register
-.8byte delay1, 0x0000001, write32_test      # reset delay1 register
-.8byte cs_mode, 0x00000000, write32_test    # reset cs_mode
-.8byte sck_div, 0x00000100, write32_test    # lower SPI clock rate so reads are done at correct time when ICACHE not supported
-.8byte tx_mark, 0x00000001, write32_test    # set transmit watermark to 1 (any entry turns mark off)
-#.8byte ie, 0x00000000, write32_test         # enable transmit interrupt
-.8byte ip, 0x00000001, read32_test          # tx watermark interupt should be pending
-.8byte 0x0, 0x00000000, readmip_test
-.8byte tx_data, 0x55443322, spi_burst_send    # place 4 entries in transmit fifo
-.8byte ip, 0x00000000, read32_test          # tx watermark interupt should be off 125
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-
-# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
-
-.8byte tx_mark, 0x00000000, write32_test      # set tx_mark to 0
-.8byte rx_data, 0x00000022, read32_test       # clear one entry from rx FIFO
-.8byte rx_mark, 0x00000003, write32_test      # set recieve watermark to 3
-#.8byte ie, 0x0000002, write32_test          # enable receive interrupts
-.8byte ip, 0x00000000, read32_test          # rx interrupts should be low (rx FIFO has 3 entries)
-.8byte rx_mark, 0x00000002, write32_test    # set recieve watermark to 2
-.8byte ip, 0x00000002, read32_test          # recieve interrupt should be high
-.8byte 0x0, 0x00000000, readmip_test
-.8byte rx_data, 0x00000033, read32_test     # clear one more entry from recieve FIFO (2 entries)
-.8byte ip, 0x00000000, read32_test          # receive interrupt should be low
-.8byte rx_data, 0x00000044, read32_test
-.8byte rx_data, 0x00000055, read32_test     # clear rx fifo
-
-
-.8byte tx_mark, 0x00000001, write32_test    # set transmit watermark to 0
-.8byte ie, 0x00000001, write32_test         # enable transmit interrupt
-.8byte ip, 0x00000001, read32_test          # tx watermark interupt should be pending
-.8byte 0x0, 0x00000800, readmip_test
-.8byte ie, 0x00000000, write32_test      # disable tx intr
-.8byte tx_data, 0x55443322, spi_burst_send    # place 4 entries in transmit fifo
-.8byte 0x0, 0x00000003, spi_data_wait           # wait for transmission to end
-
-# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
-
-.8byte tx_mark, 0x00000000, write32_test
-.8byte 0x0, 0x00000000, claim_m_plic_interrupts
-.8byte rx_data, 0x00000022, read32_test       # clear one entry from rx FIFO
-.8byte rx_mark, 0x00000003, write32_test      # set recieve watermark to 3
-.8byte ie, 0x0000002, write32_test          # enable receive interrupts
-.8byte ip, 0x00000000, read32_test          # rx interrupts should be low (rx FIFO has 3 entries)
-.8byte 0x0, 0x00000000, readmip_test
-.8byte rx_mark, 0x00000002, write32_test    # set recieve watermark to 2
-.8byte ip, 0x00000002, read32_test          # recieve interrupt should be high
-.8byte 0x0, 0x00000800, readmip_test
-.8byte rx_data, 0x00000033, read32_test     # clear one more entry from recieve FIFO (2 entries)
-.8byte 0x0, 0x00000000, claim_m_plic_interrupts
-.8byte ip, 0x00000000, read32_test          # receive interrupt should be low
-.8byte 0x0, 0x00000000, readmip_test
-
-
-
-.8byte 0x0, 0x0, terminate_test
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
index c2ad3ef11..fc71eeede 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64IAF_Zicsr")
+RVTEST_ISA("RV64IAF")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
index 0b90a59ae..6fc868984 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S
@@ -22,8 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-mie)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-mie)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
index c52f23c3d..e9a9e443b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
index 0eca80ebb..eba9208fd 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tvm-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-64.h"
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tvm)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
index 43ddf8cc9..184b022ed 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S
@@ -23,7 +23,7 @@
 
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-tw)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
index 96bf81f8b..ad3a3e6f7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
@@ -23,8 +23,8 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",xlen)
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
 
 INIT_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
index 92e3709c5..4a4bdb768 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",stvec)
 
 INIT_TESTS
@@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes
 
 GOTO_M_MODE 
 
-jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
+jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
 
 GOTO_U_MODE // Should cause software interrupt to fire off. 
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
index 24caa603a..41d9cd072 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Sstc_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
@@ -33,9 +33,7 @@ TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on tr
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR stimecmp, 0xFFFFFFFF // set timer to high value so it doesn't go off immediately
-WRITE_READ_CSR menvcfg, 0x8000000000000000 // Enable menvcfg.STCE
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources 
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
 
 // test 5.3.1.4 Basic trap tests 
 
@@ -52,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall
 GOTO_M_MODE // Causes S mode ecall
 
 
-jal cause_s_soft_from_m_interrupt
+jal cause_s_soft_interrupt 
 jal cause_m_soft_interrupt
 jal cause_s_time_interrupt
 jal cause_m_time_interrupt
@@ -74,7 +72,7 @@ jal cause_store_addr_misaligned
 jal cause_store_acc
 jal cause_ecall // M mode ecall
 
-jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1
+jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
 jal cause_m_soft_interrupt
 jal cause_s_time_interrupt 
 jal cause_m_time_interrupt
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
index 4ed0941ae..cfe02f3a6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-s)
 
 INIT_TESTS
@@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall
 GOTO_S_MODE // Causes U mode ecall
 
 
-// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9)
-//jal cause_s_soft_interrupt 
+// some interrupts excluded becaus writing MIP is illegal from S mode
+jal cause_s_soft_interrupt 
 jal cause_m_soft_interrupt
 jal cause_m_time_interrupt
 li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
-// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
+// since interrupts are not always enabled,
 jal cause_s_ext_interrupt_GPIO
 li a3, 0x40
 jal cause_m_ext_interrupt
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
index 041d548ad..78692fd1c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
index af0d9f32d..e10e5d988 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
index 2c2b2ab07..3cbf3591b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr_Zifencei")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
index 3611f99ef..c67d3c24a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
 
 INIT_TESTS
@@ -35,24 +35,30 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
 
 // Code copied from test library to cause m time interrupt, with time loop replaced with wfi.
 
-    li x28, 0x60          // Desired offset from the present time
-    mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
-    la x29, 0x02004000    // MTIMECMP register in CLINT
-    la x30, 0x0200BFF8    // MTIME register in CLINT
-    ld x7, 0(x30)         // read MTIME
-    add x28, x7, x28      // add offset
-    sw x28, 0(x29)        // MTIMECMP = MTIME + offset
+li x28, 0x60          // Desired offset from the present time
+mv a3, x28            // copy value in to know to stop waiting for interrupt after this many cycles
+la x29, 0x02004000    // MTIMECMP register in CLINT
+la x30, 0x0200BFF8    // MTIME register in CLINT
+lw x7, 0(x30)         // low word of MTIME
+lw x31, 4(x30)         // high word of MTIME
+add x28, x7, x28       // add desired offset to the current time
+bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+addi x31, x31, 1       // if wrap, increment most significant word
+sw x31,4(x29)          // store into most significant word of MTIMECMP
 
-    auipc ra, 0x0
-    addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt
+nowrap:
+    sw x28, 0(x29)         // store into least significant word of MTIMECMP
 
-    wfi // test wfi until trap goes off
+auipc ra, 0x0
+addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt
 
-    li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off.
-    // this tests whether wfi is a nop or not since we should get the output for the interrupt before this one
-    sd x28, 0(x6)
-    addi x6, x6, 8
-    addi x16, x16, 8
+wfi // test wfi until trap goes off
+
+li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off.
+// this tests whether wfi is a nop or not since we should get the output for the interrupt before this one
+sd x28, 0(x6)
+addi x6, x6, 8
+addi x16, x16, 8
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py
index 1569482da..5eb7b45b4 100755
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/periph-test-signature-address-calculator.py
@@ -17,7 +17,7 @@ if __name__ == "__main__":
         line_num = int(sig_adr / 4) + 1
         offset = sig_adr & 0x3F
         test_num = int((sig_adr-offset)/int("40",16))
-        print(f"IntrNum 0x{test_num:02X}")
-        print(f"Offset 0x{offset:02X}")
+        print("IntrNum 0x{:02X}".format(test_num))
+        print("Offset 0x{:02X}".format(offset))
         print("LineNum "+str(line_num))
    
diff --git a/wallyriscvTopAll.png b/wallyriscvTopAll.png
deleted file mode 100644
index a0d0e7cce..000000000
Binary files a/wallyriscvTopAll.png and /dev/null differ